Repository: riscv-software-src/riscv-ctg (language: python)

Issue:
Fixing Address Offset for F&D Instructions
Hi,
This merge request had the below changes on CTG towards Floating point fixes. And the code changes are verified against below, on all of the given instructions across cover groups.

    RV64F
    RV32D
    RV32F
    RV64D

High level descriptions of changes made
_generator.py_
1. Added a condition to manipulate the offset with respect to FLEN
2. Addition of new instructions to the required conditions

_template.yaml_
1. Removal of additional FLEN value from the respective instructions block

Thanks
Prasanna T
ptprasanna@gmail.com


Discussion / hints:

Fix patch:
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 21eaee5c..183bd568 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,6 +2,12 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [0.8.0] - 2022-08-08
+- Added support for a distributed template database.
+- Added generic mechanisms to generate data sections based on test instances.
+- Update templates for floating point tests.
+- Fix test generation and macros for floating point tests.
+
 ## [0.7.2]
 - Fix errors related to global variables across processes.
 
diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py
index c8217c19..c8e86302 100644
--- a/riscv_ctg/__init__.py
+++ b/riscv_ctg/__init__.py
@@ -4,5 +4,5 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = 'incorebot@gmail.com'
-__version__ = '0.7.2'
+__version__ = '0.8.0'
 
diff --git a/riscv_ctg/constants.py b/riscv_ctg/constants.py
index 7dbad50e..8458637b 100644
--- a/riscv_ctg/constants.py
+++ b/riscv_ctg/constants.py
@@ -180,18 +180,20 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 # dataset for 0x5, 0xa, 0x3, 0xc, 0x6, 0x9 patterns
 
     dataset = ["0x"+"".join(["5"]*int(bit_width/4)), "0x"+"".join(["a"]*int(bit_width/4)), "0x"+"".join(["3"]*int(bit_width/4)), "0x"+"".join(["6"]*int(bit_width/4)),"0x"+"".join(["9"]*int(bit_width/4)),"0x"+"".join(["c"]*int(bit_width/4))]
-    dataset = list(map(conv_func,dataset)) 
+    dataset = list(map(conv_func,dataset))
 
 # dataset0 is  for 0,1 and 0xf pattern. 0xf pattern is added instead of -1 so that code for checking coverpoints in coverage.py
 # is kept simple.
 
     dataset0 = [0,1,"0x"+"".join(["f"]*int(bit_width/4))]
-    dataset0 = list(map(conv_func,dataset0)) 
+    dataset0 = list(map(conv_func,dataset0))
 
 # increment each value in dataset, increment each value in dataset, add them to the dataset
     return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0
 
-template_file = os.path.join(root,"data/template.yaml")
+template_fnames = ["template.yaml","imc.yaml","fd.yaml"]
+
+template_files = [os.path.join(root,"data/"+f) for f in template_fnames]
 
 usage = Template('''
 // -----------
@@ -239,7 +241,7 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 RVMODEL_DATA_END
 ''')
 case_template = Template('''
-RVTEST_CASE($num,"//check ISA:=regex(.*$xlen.*);$cond;def TEST_CASE_1=True;",$cov_label)
+RVTEST_CASE($num,"//$cond;def TEST_CASE_1=True;",$cov_label)
 ''')
 
 part_template = Template('''
@@ -251,6 +253,6 @@ def gen_bitmanip_dataset(bit_width,sign=True):
 
 signode_template = Template('''
 $label:
-    .fill $n*(XLEN/32),4,0xdeadbeef
+    .fill $n*$sz,4,0xdeadbeef
 ''')
 
diff --git a/riscv_ctg/ctg.py b/riscv_ctg/ctg.py
index 05f15458..b0c86480 100644
--- a/riscv_ctg/ctg.py
+++ b/riscv_ctg/ctg.py
@@ -14,8 +14,8 @@
 from math import *
 from riscv_ctg.__init__ import __version__
 
-def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen):
-    flen = 0
+def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen, flen):
+    iflen = 0
     if 'mnemonics' not in node:
         logger.warning("mnemonics node not found in covergroup: " + str(label))
         return
@@ -23,29 +23,30 @@ def create_test(usage_str, node,label,base_isa,max_inst, op_template, randomize,
         logger.info("Ignoring :" + str(label))
         if node['ignore']:
             return
-    
+
     # Function to encompass checks and test generation
     def gen_test(op_node, opcode):
+        iflen = 0
         if xlen not in op_node['xlen']:
             logger.warning("Skipping {0} since its not supported in current XLEN:".format(opcode))
             return
-        flen = 0
         if 'flen' in op_node:
-            if '.d' in opcode:
-                flen = 64
-            elif '.s' in opcode:
-                flen = 32
-            else:
-                flen = op_node['flen'][0]
-            #if flen not in op_node['flen']:
-            #    return
+            if flen not in op_node['flen']:
+                logger.warning("Skipping {0} since its not supported in current FLEN({1}):".format(\
+                        opcode, flen))
+                return
+            iflen = min(op_node['flen'])
         fprefix = os.path.join(out_dir,str(label))
         logger.info('Generating Test for :' + str(label) +"-" + opcode)
         formattype  = op_node['formattype']
-        gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,base_isa)
+        gen = Generator(formattype,op_node,opcode,randomize,xlen,flen,iflen,base_isa)
         op_comb = gen.opcomb(node)
         val_comb = gen.valcomb(node)
-        instr_dict = gen.correct_val(gen.testreg(gen.swreg(gen.gen_inst(op_comb, val_comb, node))))
+        instr_dict = gen.correct_val(
+            gen.valreg(
+                gen.testreg(
+                    gen.swreg(
+                        gen.gen_inst(op_comb, val_comb, node)))))
         logger.info("Writing tests for :"+str(label))
         my_dict = gen.reformat_instr(instr_dict)
         gen.write_test(fprefix,node,label,my_dict, op_node, usage_str, max_inst)
@@ -60,7 +61,6 @@ def gen_test(op_node, opcode):
         if base_op in op_template and pseudop in op_template:
             op_node = copy.deepcopy(op_template[base_op])
             pseudo_template = op_template[pseudop]
-            
             # Ovewrite/add nodes from pseudoinstruction template in base instruction template
             for key, val in pseudo_template.items():
                 op_node[key] = val
@@ -76,13 +76,13 @@ def gen_test(op_node, opcode):
             else:
                 logger.warning(str(opcode) + " not found in template file. Skipping")
                 return
-    
-    # Return if there is no corresponding template 
+
+    # Return if there is no corresponding template
     if op_node is None:
         logger.warning("Skipping :" + str(opcode))
         return
 
-def ctg(verbose, out, random ,xlen_arg, cgf_file,num_procs,base_isa, max_inst):
+def ctg(verbose, out, random ,xlen_arg,flen_arg, cgf_file,num_procs,base_isa, max_inst):
     logger.level(verbose)
     logger.info('****** RISC-V Compliance Test Generator {0} *******'.format(__version__ ))
     logger.info('Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.')
@@ -92,6 +92,7 @@ def ctg(verbose, out, random ,xlen_arg, cgf_file,num_procs,base_isa, max_inst):
     if not os.path.exists(env_dir):
         shutil.copytree(const.env,env_dir)
     xlen = int(xlen_arg)
+    flen = int(flen_arg)
     out_dir = out
     randomize = random
     mytime = time.asctime(time.gmtime(time.time()) ) + ' GMT'
@@ -104,8 +105,14 @@ def ctg(verbose, out, random ,xlen_arg, cgf_file,num_procs,base_isa, max_inst):
     usage_str = const.usage.safe_substitute(base_isa=base_isa, \
             cgf=cgf_argument, version = __version__, time=mytime, \
             randomize=randomize_argument,xlen=str(xlen_arg))
-    op_template = utils.load_yaml(const.template_file)
-    cgf = expand_cgf(cgf_file,xlen)
+    op_template = utils.load_yamls(const.template_files)
+    cgf = expand_cgf(cgf_file,xlen,flen)
     pool = mp.Pool(num_procs)
-    results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template, randomize, out_dir, xlen) for label,node in cgf.items()])
-    pool.close()
\ No newline at end of file
+# <<<<<<< HEAD
+    # results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst) for label,node in cgf.items()])
+    # pool.close()
+# =======
+    results = pool.starmap(create_test, [(usage_str, node,label,base_isa,max_inst, op_template,
+        randomize, out_dir, xlen, flen) for label,node in cgf.items()])
+    pool.close()
+# >>>>>>> master
diff --git a/riscv_ctg/data/fd.yaml b/riscv_ctg/data/fd.yaml
new file mode 100644
index 00000000..3c5e0bf4
--- /dev/null
+++ b/riscv_ctg/data/fd.yaml
@@ -0,0 +1,1711 @@
+# See LICENSE.incore for details
+fadd.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  std_op:
+  formattype: 'rformat'
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; 
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg 
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fadd.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; 
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg 
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+
+fsub.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsub.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmul.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmul.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fdiv.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fdiv.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsqrt.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr */
+    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsqrt.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr */
+    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmadd.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmadd.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmsub.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmsub.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fnmadd.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fnmadd.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fnmsub.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fnmsub.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 3
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'r4format'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rs3_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val;
+    testreg:$testreg; fcsr_val:$fcsr */
+    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+
+fsgnj.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsgnj.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2,  $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsgnjn.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset;  fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsgnjn.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsgnjx.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fsgnjx.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmin.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmin.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmax.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset; fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmax.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+       valaddr_reg:$valaddr_reg; val_offset:$val_offset;  fcsr: $fcsr;
+       correctval:$correctval; testreg:$testreg
+    */
+    TEST_FPRR_OP_NRM($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+feq.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+feq.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+flt.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+flt.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fle.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fle.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 2
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'rformat'
+  rs1_op_data: *all_fregs
+  rs2_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val;
+    valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fmv.w.x:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '4'
+    val_template: "'.word $val;'"
+    load_instr: "lw"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fmv.x.w:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fcvt.w.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fcvt.w.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fcvt.wu.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+
+fcvt.wu.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fcvt.l.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+
+fcvt.lu.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fmv.x.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP_NRM($inst, $rd, $rs1,  $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fcvt.s.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr */
+    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+    
+fcvt.d.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_fregs
+  template: |-
+
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr */
+    TEST_FPSR_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)  
+    
+fcvt.s.w:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '4'
+    val_template: "'.word $val;'"
+    load_instr: "lw"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+
+fcvt.s.wu:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '4'
+    val_template: "'.word $val;'"
+    load_instr: "LREGWU"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+ 
+fcvt.d.w:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '4'
+    val_template: "'.word $val;'"
+    load_instr: "lw"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+
+fcvt.d.wu:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '4'
+    val_template: "'.word $val;'"
+    load_instr: "LREGWU"
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fcvt.d.l:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "'.dword $val;'"
+    load_instr: "ld"
+  xlen: [64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+
+fcvt.d.lu:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "'.dword $val;'"
+    load_instr: "ld"
+  xlen: [64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+
+fmv.d.x:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "'.dword $val;'"
+    load_instr: "ld"
+  xlen: [64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fclass.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+   
+fclass.d:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [32, 64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP_NRM($inst, $rd, $rs1, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg)
+
+# The val nodes are present in the fmem ops right now as a hack to force allocation of flagreg. Once
+# anxilliary registers are moved to their own functions, this can be removed.
+fsw:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_fregs
+  xlen: [32,64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'sformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: '[0xABCDEF12]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+    // valreg: $valaddr_reg; valoffset: $val_offset
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+    
+flw:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '4'
+    val_template: "''"
+    load_instr: "flw"
+  rs1_op_data: *all_regs_mx0 
+  rd_op_data: *all_fregs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+    
+fsd:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_fregs
+  std_op:
+  xlen: [32,64]
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'sformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: '[0x0123456789ABCDEF]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+    // valreg: $valaddr_reg; valoffset: $val_offset
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+    
+fld:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "''"
+    load_instr: "fld"
+  rs1_op_data: *all_regs_mx0 
+  rd_op_data: *all_fregs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IFD_Zicsr
+  flen: [64]
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+    
+fcvt.l.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [64]
+  std_op:
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[0,1,2,3,4,7]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fcvt.lu.s:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "'NAN_BOXED($val,$width,FLEN)'"
+    load_instr: "FLREG"
+  xlen: [64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[0,1,2,3,4,7]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_fregs
+  rd_op_data: *all_regs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val:$fcsr*/
+    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+    
+fcvt.s.l:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "'.dword $val;'"
+    load_instr: "ld"
+  xlen: [64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  std_op:
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+ 
+fcvt.s.lu:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "'.dword $val;'"
+    load_instr: "ld"
+  xlen: [64]
+  isa: 
+    - IF_Zicsr
+    - IFD_Zicsr
+  flen: [32,64]
+  rm_val_data: '[7,0,1,2,3,4]'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  std_op:
+  formattype: 'fsrformat'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_fregs
+  template: |-
+    // $comment
+    /* opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg;
+    val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg;
+    fcsr_val: $fcsr*/
+    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $fcsr, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $testreg,$load_instr)
+ 
diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml
new file mode 100644
index 00000000..dcd04ffd
--- /dev/null
+++ b/riscv_ctg/data/imc.yaml
@@ -0,0 +1,1877 @@
+# See LICENSE.incore for details
+add:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+sub:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  isa: 
+    - I
+  operation: 'hex((rs1_val - rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+
+addw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) + (rs2_val & 0xFFFFFFFF) ,32))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+subw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) - (rs2_val & 0xFFFFFFFF) ,32))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+and:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+or:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val | rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+slt:
+  rs1_op_data: *all_regs
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(int(rs1_val < rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+sltu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(int(rs1_val < rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+xor:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val ^ rs2_val) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+sllw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend((rs1_val << (rs2_val%32)) ,32))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(5)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+srlw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend((rs1_val & 0xffffffff) >> (rs2_val%32), 32))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(5)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+sraw:
+  rs1_op_data: *all_regs
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend((sign_extend(rs1_val,32) >> ((rs2_val & 0xffffffff) %32))& 0xffffffff ,32))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(5)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+sll:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val << (rs2_val%xlen)) & (2**(xlen)-1))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+srl:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val & (2**(xlen)-1)) >> (rs2_val%xlen))'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+sra:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(rs1_val >> (rs2_val%xlen) )'
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+addi:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+addiw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) + (imm_val & 0xffffffff) , 32))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12,True)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+slti:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(int(rs1_val < imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12,True)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+sltiu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(int(rs1_val < int(imm_val if imm_val&0x800 == 0 else imm_val + int("0x"+"".join("f"*int((xlen-12)/4)+"000"),16))) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
+  imm_val_data: 'gen_usign_dataset(12)+ gen_sp_dataset(12,False)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+andi:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val & imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+ori:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val | imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+xori:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val ^ imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+slli:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val << imm_val) & (2**(xlen)-1))'
+  formattype: 'iformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+srli:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex((rs1_val & (2**(xlen)-1)) >> imm_val)'
+  formattype: 'iformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+srai:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(rs1_val >> (imm_val))'
+  formattype: 'iformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+slliw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend((rs1_val << imm_val) , 32))'
+  formattype: 'iformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_usign_dataset(5)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+srliw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) >> imm_val , 32))'
+  formattype: 'iformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_usign_dataset(5)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+sraiw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend((sign_extend(rs1_val,32) >> ((imm_val & 0xfff) %32)) & 0xffffffff, 32))'
+  formattype: 'iformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_usign_dataset(5)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+lui:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend(imm_val << (12), 32))'
+  formattype: 'uformat'
+  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest:$rd; immval:$imm_val
+    TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd,$imm_val)
+
+auipc:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  operation: 'hex(sign_extend(imm_val << (12) ,32))'
+  formattype: 'uformat'
+  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20, False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest:$rd; immval:$imm_val
+    TEST_AUIPC($inst, $rd, $correctval, $imm_val, $swreg, $offset, $testreg)
+
+beq:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'bformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
+
+bge:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'bformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
+
+bgeu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'bformat'
+  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
+
+blt:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'bformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
+
+bltu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'bformat'
+  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
+
+bne:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'bformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen) '
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen) '
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
+  template: |-
+
+    // $comment
+    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
+
+sd:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'sformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
+
+sw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'sformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
+
+sh:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'sformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
+
+sb:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'sformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
+
+ld:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  isa: 
+    - I
+  xlen: [64]
+  std_op:
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3,4,5,6,7]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+lwu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  isa: 
+    - I
+  xlen: [64]
+  std_op:
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+lw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0 
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+lhu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+lh:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+lbu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+lb:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
+
+jal:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'jformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(20)))'
+  template: |-
+
+    // $comment
+    // opcode: jal; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_JAL_OP($testreg, $rd, $imm_val, $label, $swreg, $offset,$ea_align)
+
+jalr:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I
+  formattype: 'iformat'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: 'gen_sign_dataset(12)'
+  template: |-
+
+    // $comment
+    // opcode: jalr; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
+    TEST_JALR_OP($testreg, $rd, $rs1, $imm_val, $swreg, $offset,$ea_align)
+
+mul:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mulh:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(((rs1_val * rs2_val)>>xlen) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mulhu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(((rs1_val * rs2_val)>>xlen) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mulhsu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(((rs1_val * (rs2_val if rs2_val>=0 else int(hex((1<<xlen) + rs2_val),base=16)))>>xlen) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+div:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation:  'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+divu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(int(rs1_val // rs2_val) & (2**(xlen)-1)) if rs2_val!=0 else "0x"+("F"*int(xlen/4))'
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+rem:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  #  operation: 'hex(rs1_val if rs2_val==0 or (rs1_val<rs2_val and rs2_val<0) else (rs1_val % rs2_val) & (2**(xlen)-1))'
+  operation: 'hex(rs1_val) if rs2_val == 0 else hex(int(abs(rs1_val) % abs(rs2_val))) if rs1_val > 0 else hex(-int(abs(rs1_val) % abs(rs2_val)))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+remu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(rs1_val) if rs2_val == 0 else hex(int(abs(rs1_val) % abs(rs2_val))) '
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mulw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) * (rs2_val & 0xFFFFFFFF) ,32))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+divw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  #  operation: 'hex(sign_extend(int((rs1_val & 0xFFFFFFFF) // (rs2_val & 0xFFFFFFFF)) ,32)) if (rs2_val&0xFFFFFFFF)!=0 else "0x"+("F"*int(xlen/4))'
+  operation: 'hex(sign_extend(int(abs(sign_extend(rs1_val,32))//abs(sign_extend(rs2_val,32))),32)) if (sign_extend(rs1_val,32) * sign_extend(rs2_val,32) > 0) else hex(-int(abs(sign_extend(rs1_val,32))//abs(sign_extend(rs2_val, 32)))) if sign_extend(rs2_val,32) != 0 else "0x"+("F"*int(xlen/4))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+divuw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(sign_extend(int((rs1_val & 0xFFFFFFFF) // (rs2_val & 0xFFFFFFFF)) ,32)) if (rs2_val&0xFFFFFFFF)!=0 else "0x"+("F"*int(xlen/4))'
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+remw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  #  operation: 'hex(sign_extend(((rs1_val & 0xFFFFFFFF) % (rs2_val & 0xFFFFFFFF)) , 32)) if (rs2_val&0xFFFFFFFF)!=0 else hex(rs1_val)'
+  operation: 'hex(sign_extend(rs1_val,32)) if (rs2_val&0xffffffff) == 0 else hex(sign_extend(int(abs(sign_extend(rs1_val,32)) % abs(sign_extend(rs2_val,32))),32)) if sign_extend(rs1_val,32) > 0 else hex(-int(abs(sign_extend(rs1_val,32)) % abs(sign_extend(rs2_val,32))))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+remuw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IM
+  formattype: 'rformat'
+  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) % (rs2_val & 0xFFFFFFFF) , 32)) if (rs2_val&0xFFFFFFFF)!=0 else hex(sign_extend(rs1_val,32))'
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.mv:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *all_regs_mx0
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cmvformat'
+  operation: 'hex(rs2_val)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op2:$rs2; dest:$rd; op2val:$rs2_val
+    TEST_CMV_OP( $inst, $rd, $rs2, $correctval, $rs2_val, $swreg, $offset, $testreg)
+
+c.add:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.addw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex(sign_extend((rs1_val + rs2_val) ,32))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.and:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.or:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex((rs1_val | rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.xor:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex((rs1_val ^ rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.sub:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex((rs1_val - rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.subw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) - (rs2_val & 0xFFFFFFFF) ,32))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+c.andi:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cbformat'
+  operation: 'hex((rs1_val & imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(6)+gen_sp_dataset(6)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; immval:$imm_val
+    TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.nop:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+  
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CNOP_OP($inst, $testreg, $imm_val, $swreg, $offset)
+
+c.addi:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(6) + gen_sp_dataset(6)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.addiw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs_mx0
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  operation: 'hex(sign_extend(((rs1_val & 0xFFFFFFFF) + (imm_val & 0xffffffff)) , 32))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  imm_val_data: 'gen_sign_dataset(6) + gen_sp_dataset(6)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.addi16sp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: "['x2']"
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'list(filter( lambda x: x!=0 , [ 16*x for x in gen_sign_dataset(6)])) + [496]'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:x2; dest:x2 op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, x2, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.addi4spn:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciwformat'
+  operation: 'hex(imm_val)'
+  imm_val_data: 'list(filter( lambda x: x!=0 , [ 4*x for x in gen_usign_dataset(8)]))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; dest:$rd; immval:$imm_val
+    TEST_CADDI4SPN_OP( $inst, $rd, $correctval, $imm_val, $swreg, $offset, $testreg)
+
+c.slli:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  operation: 'hex((rs1_val << imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.srli:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cbformat'
+  operation: 'hex(((rs1_val & (2**(xlen)-1)) >> imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; dest:$rs1 op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.srai:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cbformat'
+  operation: 'hex(rs1_val >> (imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; dest:$rs1 op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.li:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  operation : 'hex(sign_extend(imm_val,6))'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+
+    // $comment
+    // opcode:$inst; dest:$rd; immval:$imm_val
+    TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd, $imm_val;)
+
+c.lui:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  operation: 'hex(sign_extend(imm_val << 12,32))'
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'list(filter(lambda x: x!=0 ,gen_usign_dataset(6)))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
+    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
+
+c.sw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'csformat'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
+
+c.sd:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'csformat'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
+
+c.ld:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_regs 
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$rs1_val)
+
+c.lw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
+
+c.lwsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
+
+c.ldsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs_mx0
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'ciformat'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,x2,$rd,$imm_val,$offset,$inst,0)
+
+c.swsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cssformat'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val
+    TEST_STORE($swreg,$testreg,$index,x2,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
+
+c.sdsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *all_regs
+  xlen: [64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cssformat'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val
+    TEST_STORE($swreg,$testreg,$index,x2,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
+
+c.beqz:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cbformat'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
+  imm_val_data: 'list(filter(lambda x: (x >=4 and x<250) or (x<=-4 and x>=-250),[x*2 for x in gen_sign_dataset(8)]))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; op1:$rs1; op1val:$rs1_val; immval:$imm_val
+    TEST_CBRANCH_OP($inst, $testreg, $rs1, $rs1_val, $imm_val, $label, $swreg, $offset)
+
+c.bnez:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cbformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
+  imm_val_data: 'list(filter(lambda x: (x >=4 and x<250) if x>0 else (x<=-4 and x>=-250),[x*2 for x in gen_sign_dataset(8)]))'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op1val:$rs1_val; immval:$imm_val
+    TEST_CBRANCH_OP($inst, $testreg, $rs1, $rs1_val, $imm_val, $label, $swreg, $offset)
+
+c.j:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cjformat'
+  imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CJ_OP($inst, $testreg, $imm_val, $label, $swreg, $offset)
+
+c.jal:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'cbformat'
+  imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))'
+  template: |-
+
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CJAL_OP($inst, $testreg, $imm_val, $label, $swreg, $offset)
+
+c.jr:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  template: |-
+
+    // $comment
+    // opcode: c.jr; op1:$rs1
+    TEST_CJR_OP($testreg, $rs1, $swreg, $offset)
+
+c.jalr:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IC
+  formattype: 'crformat'
+  template: |-
+
+    // $comment
+    // opcode:c.jalr; op1:$rs1
+    TEST_CJALR_OP($testreg, $rs1, $swreg, $offset)
+
diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml
index 5009c8c1..9dcc8b13 100644
--- a/riscv_ctg/data/template.yaml
+++ b/riscv_ctg/data/template.yaml
@@ -6,2704 +6,11 @@ metadata:
   c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
 
-add:
-  stride: 1
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-sub:
-  stride: 1
-  xlen: [32,64]
-  std_op:
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  isa: 
-    - I
-  operation: 'hex((rs1_val - rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-
-addw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) + (rs2_val & 0xFFFFFFFF) ,32))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-subw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) - (rs2_val & 0xFFFFFFFF) ,32))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-and:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-or:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val | rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-slt:
-  rs1_op_data: *all_regs
-  stride: 1
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(int(rs1_val < rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-sltu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(int(rs1_val < rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-xor:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val ^ rs2_val) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-sllw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend((rs1_val << (rs2_val%32)) ,32))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(5)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-srlw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend((rs1_val & 0xffffffff) >> (rs2_val%32), 32))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(5)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-sraw:
-  rs1_op_data: *all_regs
-  stride: 1
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend((sign_extend(rs1_val,32) >> ((rs2_val & 0xffffffff) %32))& 0xffffffff ,32))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(5)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-sll:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val << (rs2_val%xlen)) & (2**(xlen)-1))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-srl:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val & (2**(xlen)-1)) >> (rs2_val%xlen))'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-sra:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(rs1_val >> (rs2_val%xlen) )'
-  formattype: 'rformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-addi:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-addiw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend( (rs1_val & 0xFFFFFFFF) + (imm_val & 0xffffffff) , 32))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12,True)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-slti:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(int(rs1_val < imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12,True)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-sltiu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(int(rs1_val < int(imm_val if imm_val&0x800 == 0 else imm_val + int("0x"+"".join("f"*int((xlen-12)/4)+"000"),16))) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
-  imm_val_data: 'gen_usign_dataset(12)+ gen_sp_dataset(12,False)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-andi:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val & imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-ori:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val | imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-xori:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val ^ imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
-  formattype: 'iformat'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-slli:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val << imm_val) & (2**(xlen)-1))'
-  formattype: 'iformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-srli:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex((rs1_val & (2**(xlen)-1)) >> imm_val)'
-  formattype: 'iformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-srai:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(rs1_val >> (imm_val))'
-  formattype: 'iformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-slliw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend((rs1_val << imm_val) , 32))'
-  formattype: 'iformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_usign_dataset(5)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-srliw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) >> imm_val , 32))'
-  formattype: 'iformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_usign_dataset(5)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-sraiw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend((sign_extend(rs1_val,32) >> ((imm_val & 0xfff) %32)) & 0xffffffff, 32))'
-  formattype: 'iformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  imm_val_data: 'gen_usign_dataset(5)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
-    TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-lui:
-  stride: 1
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend(imm_val << (12), 32))'
-  formattype: 'uformat'
-  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; dest:$rd; immval:$imm_val
-    TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd,$imm_val)
-
-auipc:
-  stride: 1
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  operation: 'hex(sign_extend(imm_val << (12) ,32))'
-  formattype: 'uformat'
-  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20, False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; dest:$rd; immval:$imm_val
-    TEST_AUIPC($inst, $rd, $correctval, $imm_val, $swreg, $offset, $testreg)
-
-beq:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'bformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
-
-bge:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'bformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
-
-bgeu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'bformat'
-  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
-
-blt:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'bformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
-
-bltu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'bformat'
-  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,False)'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
-
-bne:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'bformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen) '
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen) '
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(12)))'
-  template: |-
-
-    // $comment
-    // opcode: $inst, op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_BRANCH_OP($inst, $testreg, $rs1, $rs2, $rs1_val, $rs2_val, $imm_val, $label, $swreg, $offset,$ea_align)
-
-sd:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'sformat'
-  ea_align_data: '[0,1,2,3,4,5,6,7]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
-
-sw:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'sformat'
-  ea_align_data: '[0,1,2,3]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
-
-sh:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'sformat'
-  ea_align_data: '[0,1,2,3]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
-
-sb:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'sformat'
-  ea_align_data: '[0,1,2,3]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align
-    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align)
-
-ld:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  isa: 
-    - I
-  xlen: [64]
-  std_op:
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3,4,5,6,7]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-lwu:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  isa: 
-    - I
-  xlen: [64]
-  std_op:
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-lw:
-  stride: 1
-  rs1_op_data: *all_regs_mx0 
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-lhu:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-lh:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-lbu:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-lb:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align)
-
-jal:
-  stride: 1
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'jformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'list(filter(lambda x: x%2==0,gen_sign_dataset(20)))'
-  template: |-
-
-    // $comment
-    // opcode: jal; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_JAL_OP($testreg, $rd, $imm_val, $label, $swreg, $offset,$ea_align)
-
-jalr:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - I
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-
-    // $comment
-    // opcode: jalr; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align
-    TEST_JALR_OP($testreg, $rd, $rs1, $imm_val, $swreg, $offset,$ea_align)
-
-mul:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-mulh:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(((rs1_val * rs2_val)>>xlen) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-mulhu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(((rs1_val * rs2_val)>>xlen) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-mulhsu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(((rs1_val * (rs2_val if rs2_val>=0 else int(hex((1<<xlen) + rs2_val),base=16)))>>xlen) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-div:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation:  'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-divu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(int(rs1_val // rs2_val) & (2**(xlen)-1)) if rs2_val!=0 else "0x"+("F"*int(xlen/4))'
-  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-rem:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  #  operation: 'hex(rs1_val if rs2_val==0 or (rs1_val<rs2_val and rs2_val<0) else (rs1_val % rs2_val) & (2**(xlen)-1))'
-  operation: 'hex(rs1_val) if rs2_val == 0 else hex(int(abs(rs1_val) % abs(rs2_val))) if rs1_val > 0 else hex(-int(abs(rs1_val) % abs(rs2_val)))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-remu:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(rs1_val) if rs2_val == 0 else hex(int(abs(rs1_val) % abs(rs2_val))) '
-  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-mulw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) * (rs2_val & 0xFFFFFFFF) ,32))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-divw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  #  operation: 'hex(sign_extend(int((rs1_val & 0xFFFFFFFF) // (rs2_val & 0xFFFFFFFF)) ,32)) if (rs2_val&0xFFFFFFFF)!=0 else "0x"+("F"*int(xlen/4))'
-  operation: 'hex(sign_extend(int(abs(sign_extend(rs1_val,32))//abs(sign_extend(rs2_val,32))),32)) if (sign_extend(rs1_val,32) * sign_extend(rs2_val,32) > 0) else hex(-int(abs(sign_extend(rs1_val,32))//abs(sign_extend(rs2_val, 32)))) if sign_extend(rs2_val,32) != 0 else "0x"+("F"*int(xlen/4))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-divuw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(sign_extend(int((rs1_val & 0xFFFFFFFF) // (rs2_val & 0xFFFFFFFF)) ,32)) if (rs2_val&0xFFFFFFFF)!=0 else "0x"+("F"*int(xlen/4))'
-  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-remw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  #  operation: 'hex(sign_extend(((rs1_val & 0xFFFFFFFF) % (rs2_val & 0xFFFFFFFF)) , 32)) if (rs2_val&0xFFFFFFFF)!=0 else hex(rs1_val)'
-  operation: 'hex(sign_extend(rs1_val,32)) if (rs2_val&0xffffffff) == 0 else hex(sign_extend(int(abs(sign_extend(rs1_val,32)) % abs(sign_extend(rs2_val,32))),32)) if sign_extend(rs1_val,32) > 0 else hex(-int(abs(sign_extend(rs1_val,32)) % abs(sign_extend(rs2_val,32))))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-remuw:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs
-  rd_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IM
-  formattype: 'rformat'
-  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) % (rs2_val & 0xFFFFFFFF) , 32)) if (rs2_val&0xFFFFFFFF)!=0 else hex(sign_extend(rs1_val,32))'
-  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  rs2_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.mv:
-  stride: 1
-  rs2_op_data: *all_regs_mx0
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cmvformat'
-  operation: 'hex(rs2_val)'
-  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op2:$rs2; dest:$rd; op2val:$rs2_val
-    TEST_CMV_OP( $inst, $rd, $rs2, $correctval, $rs2_val, $swreg, $offset, $testreg)
-
-c.add:
-  stride: 1
-  rs1_op_data: *all_regs
-  rs2_op_data: *all_regs_mx0
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex((rs1_val + rs2_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen,True)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen,True)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.addw:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex(sign_extend((rs1_val + rs2_val) ,32))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.and:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex((rs1_val & rs2_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.or:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex((rs1_val | rs2_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.xor:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex((rs1_val ^ rs2_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.sub:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex((rs1_val - rs2_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.subw:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  operation: 'hex(sign_extend((rs1_val & 0xFFFFFFFF) - (rs2_val & 0xFFFFFFFF) ,32))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  rs2_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
-    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
-
-c.andi:
-  stride: 1
-  rs1_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cbformat'
-  operation: 'hex((rs1_val & imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)+gen_sp_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(6)+gen_sp_dataset(6)'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; immval:$imm_val
-    TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.nop:
-  stride: 1
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cjformat'
-  imm_val_data: 'gen_sign_dataset(6)'
-  template: |-
-  
-    // $comment
-    // opcode:$inst; immval:$imm_val
-    TEST_CNOP_OP($inst, $testreg, $imm_val, $swreg, $offset)
-
-c.addi:
-  stride: 1
-  rd_op_data: *all_regs_mx0
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(6) + gen_sp_dataset(6)'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.addiw:
-  stride: 1
-  rd_op_data: *all_regs_mx0
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  operation: 'hex(sign_extend(((rs1_val & 0xFFFFFFFF) + (imm_val & 0xffffffff)) , 32))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(6) + gen_sp_dataset(6)'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.addi16sp:
-  stride: 1
-  rd_op_data: "['x2']"
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'list(filter( lambda x: x!=0 , [ 16*x for x in gen_sign_dataset(6)])) + [496]'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:x2; dest:x2 op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, x2, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.addi4spn:
-  stride: 1
-  rd_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciwformat'
-  operation: 'hex(imm_val)'
-  imm_val_data: 'list(filter( lambda x: x!=0 , [ 4*x for x in gen_usign_dataset(8)]))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; dest:$rd; immval:$imm_val
-    TEST_CADDI4SPN_OP( $inst, $rd, $correctval, $imm_val, $swreg, $offset, $testreg)
-
-c.slli:
-  stride: 1
-  rd_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  operation: 'hex((rs1_val << imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.srli:
-  stride: 1
-  rs1_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cbformat'
-  operation: 'hex(((rs1_val & (2**(xlen)-1)) >> imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rs1; dest:$rs1 op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.srai:
-  stride: 1
-  rs1_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cbformat'
-  operation: 'hex(rs1_val >> (imm_val) & (2**(xlen)-1))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  imm_val_data: 'list(filter(lambda x: x!=0, gen_usign_dataset(ceil(log(xlen,2)))))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rs1; dest:$rs1 op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.li:
-  stride: 1
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  operation : 'hex(sign_extend(imm_val,6))'
-  imm_val_data: 'gen_sign_dataset(6)'
-  template: |-
-
-    // $comment
-    // opcode:$inst; dest:$rd; immval:$imm_val
-    TEST_CASE($testreg, $rd, $correctval, $swreg, $offset, $inst $rd, $imm_val;)
-
-c.lui:
-  stride: 1
-  rd_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  operation: 'hex(sign_extend(imm_val << 12,32))'
-  rs1_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'list(filter(lambda x: x!=0 ,gen_usign_dataset(6)))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rd; dest:$rd op1val:$rs1_val; immval:$imm_val
-    TEST_CI_OP( $inst, $rd, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
-
-c.sw:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'csformat'
-  rs1_val_data: '[0]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
-    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
-
-c.sd:
-  stride: 1
-  rs1_op_data: *c_regs
-  rs2_op_data: *c_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'csformat'
-  rs1_val_data: '[0]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
-    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
-
-c.ld:
-  stride: 1
-  rs1_op_data: *c_regs
-  rd_op_data: *c_regs 
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'clformat'
-  rs1_val_data: '[0]'
-  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$rs1_val)
-
-c.lw:
-  stride: 1
-  rs1_op_data: *c_regs
-  rd_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'clformat'
-  rs1_val_data: '[0]'
-  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
-
-c.lwsp:
-  stride: 1
-  rd_op_data: *all_regs_mx0
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
-    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
-
-c.ldsp:
-  stride: 1
-  rd_op_data: *all_regs_mx0
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'ciformat'
-  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val
-    TEST_LOAD($swreg,$testreg,$index,x2,$rd,$imm_val,$offset,$inst,0)
-
-c.swsp:
-  stride: 1
-  rs2_op_data: *all_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cssformat'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val
-    TEST_STORE($swreg,$testreg,$index,x2,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
-
-c.sdsp:
-  stride: 1
-  rs2_op_data: *all_regs
-  xlen: [64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cssformat'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; immval:$imm_val
-    TEST_STORE($swreg,$testreg,$index,x2,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
-
-c.beqz:
-  stride: 1
-  rs1_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cbformat'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen)'
-  imm_val_data: 'list(filter(lambda x: (x >=4 and x<250) or (x<=-4 and x>=-250),[x*2 for x in gen_sign_dataset(8)]))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; op1:$rs1; op1val:$rs1_val; immval:$imm_val
-    TEST_CBRANCH_OP($inst, $testreg, $rs1, $rs1_val, $imm_val, $label, $swreg, $offset)
-
-c.bnez:
-  stride: 1
-  rs1_op_data: *c_regs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cbformat'
-  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
-  imm_val_data: 'list(filter(lambda x: (x >=4 and x<250) if x>0 else (x<=-4 and x>=-250),[x*2 for x in gen_sign_dataset(8)]))'
-  template: |-
-
-    // $comment
-    // opcode: $inst; op1:$rs1; op1val:$rs1_val; immval:$imm_val
-    TEST_CBRANCH_OP($inst, $testreg, $rs1, $rs1_val, $imm_val, $label, $swreg, $offset)
-
-c.j:
-  stride: 1
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cjformat'
-  imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; immval:$imm_val
-    TEST_CJ_OP($inst, $testreg, $imm_val, $label, $swreg, $offset)
-
-c.jal:
-  stride: 1
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'cbformat'
-  imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))'
-  template: |-
-
-    // $comment
-    // opcode:$inst; immval:$imm_val
-    TEST_CJAL_OP($inst, $testreg, $imm_val, $label, $swreg, $offset)
-
-c.jr:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  template: |-
-
-    // $comment
-    // opcode: c.jr; op1:$rs1
-    TEST_CJR_OP($testreg, $rs1, $swreg, $offset)
-
-c.jalr:
-  stride: 1
-  rs1_op_data: *all_regs_mx0
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IC
-  formattype: 'crformat'
-  template: |-
-
-    // $comment
-    // opcode:c.jalr; op1:$rs1
-    TEST_CJALR_OP($testreg, $rs1, $swreg, $offset)
-
-fadd.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fadd.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fsub.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsub.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmul.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmul.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fdiv.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fdiv.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsqrt.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsqrt.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmadd.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmadd.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmsub.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmsub.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fnmadd.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fnmadd.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fnmsub.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fnmsub.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fr4format'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rs3_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; op3:$rs3; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; op3val:$rs3_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; testreg:$testreg
-    TEST_FPR4_OP($inst, $rd, $rs1, $rs2, $rs3, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fsgnj.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsgnj.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsgnjn.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsgnjn.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsgnjx.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fsgnjx.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmin.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmin.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmax.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmax.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPRR_OP($inst, $rd, $rs1, $rs2, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-feq.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg
-    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-feq.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg
-    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-flt.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg
-    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-flt.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg
-    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fle.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg
-    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fle.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'frformat'
-  rs1_op_data: *all_fregs
-  rs2_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; correctval:$correctval; testreg:$testreg
-    TEST_FCMP_OP($inst, $rd, $rs1, $rs2, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmv.w.x:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmv.x.w:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.w.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.w.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.wu.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fcvt.wu.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.l.d:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fcvt.lu.d:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fmv.x.d:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.s.d:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.d.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_fregs
-  template: |-
-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPSR_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)  
-    
-fcvt.s.w:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fcvt.s.wu:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
- 
-fcvt.d.w:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fcvt.d.wu:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.d.l:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fcvt.d.lu:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fmv.d.x:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fclass.s:
-  stride: 2
-  xlen: [32,64]
-  isa: 
-    - IF
-  std_op:
-  flen: [32]
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-   
-fclass.d:
-  stride: 2
-  xlen: [32, 64]
-  isa: 
-    - IFD
-  flen: [64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-
-fsw:
-  stride: 2
-  rs1_op_data: *all_regs_mx0
-  rs2_op_data: *all_fregs
-  xlen: [32,64]
-  isa: 
-    - IF
-  std_op:
-  flen: [32]
-  formattype: 'sformat'
-  ea_align_data: '[0,1,2,3]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
-    TEST_STORE_F($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align,$flagreg)
-    
-flw:
-  stride: 2
-  rs1_op_data: *all_regs_mx0 
-  rd_op_data: *all_fregs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IF
-  flen: [32]
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg
-    TEST_LOAD_F($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align,$flagreg)
-    
-fsd:
-  stride: 2
-  rs1_op_data: *all_regs_mx0
-  rs2_op_data: *all_fregs
-  std_op:
-  xlen: [32,64]
-  isa: 
-    - IFD
-  flen: [64]
-  formattype: 'sformat'
-  ea_align_data: '[0,1,2,3]'
-  rs2_val_data: 'gen_sign_dataset(xlen)'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-    // $comment
-    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
-    TEST_STORE_F($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,$ea_align,$flagreg)
-    
-fld:
-  stride: 2
-  rs1_op_data: *all_regs_mx0 
-  rd_op_data: *all_fregs
-  xlen: [32,64]
-  std_op:
-  isa: 
-    - IFD
-  flen: [64]
-  formattype: 'iformat'
-  ea_align_data: '[0,1,2,3]'
-  imm_val_data: 'gen_sign_dataset(12)'
-  template: |-
-    // $comment
-    // opcode:$inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flag_reg
-    TEST_LOAD_F($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,$ea_align,$flagreg)
-    
-fcvt.l.s:
-  stride: 2
-  xlen: [64]
-  std_op:
-  isa: 
-    - IF
-  flen: [32,64]
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.lu.s:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_fregs
-  rd_op_data: *all_regs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPID_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-    
-fcvt.s.l:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IF
-  std_op:
-  flen: [32,64]
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
- 
-fcvt.s.lu:
-  stride: 2
-  xlen: [64]
-  isa: 
-    - IF
-  flen: [32,64]
-  std_op:
-  formattype: 'fsrformat'
-  rs1_op_data: *all_regs
-  rd_op_data: *all_fregs
-  template: |-
-    // $comment
-    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; valaddr_reg:$valaddr_reg; val_offset:$val_offset; rmval:$rm_val; correctval:$correctval; testreg:$testreg
-    TEST_FPIO_OP($inst, $rd, $rs1, $rm_val, $correctval, $valaddr_reg, $val_offset, $flagreg, $swreg, $offset, $testreg)
-        
 aes32dsi:
-  stride: 1
+  sig:
+    sig:
+    stride: 1
+    sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2719,7 +26,9 @@ aes32dsi:
     TEST_RI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes32dsmi:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2735,7 +44,9 @@ aes32dsmi:
     TEST_RI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes32esi:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2751,7 +62,9 @@ aes32esi:
     TEST_RI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes32esmi:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2767,7 +80,9 @@ aes32esmi:
     TEST_RI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sm4ed:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2783,7 +98,9 @@ sm4ed:
     TEST_RI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sm4ks:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2799,7 +116,9 @@ sm4ks:
     TEST_RI_OP($inst, $rd, $rs1, $rs2, $imm_val, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 sha256sig0:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2818,7 +137,9 @@ sha256sig0:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 sha256sig1:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2837,7 +158,9 @@ sha256sig1:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 sha256sum0:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2856,7 +179,9 @@ sha256sum0:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 sha256sum1:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2875,7 +200,9 @@ sha256sum1:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 sm3p0:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2894,7 +221,9 @@ sm3p0:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 sm3p1:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2913,7 +242,9 @@ sm3p1:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 sha512sig0h:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2931,7 +262,9 @@ sha512sig0h:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 sha512sig0l:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2949,7 +282,9 @@ sha512sig0l:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    
     
 sha512sig1h:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2967,7 +302,9 @@ sha512sig1h:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    
 
 sha512sig1l:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -2985,7 +322,9 @@ sha512sig1l:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sha512sum0r:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3003,7 +342,9 @@ sha512sum0r:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sha512sum1r:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3021,7 +362,9 @@ sha512sum1r:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rol:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   operation: 'hex((rs1_val << (rs2_val%xlen)) & (2**(xlen)-1))'
@@ -3046,7 +389,9 @@ rol:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 rev.b:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op: grevi
   isa: 
@@ -3064,7 +409,9 @@ rev.b:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 zip:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32, 64]
   std_op: shfli
   isa: 
@@ -3082,7 +429,9 @@ zip:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 unzip:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32, 64]
   std_op: unshfli
   isa: 
@@ -3100,7 +449,9 @@ unzip:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 pack:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3121,7 +472,9 @@ pack:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 packu:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3137,7 +490,9 @@ packu:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 packh:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3158,7 +513,9 @@ packh:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 xperm.n:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3174,7 +531,9 @@ xperm.n:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 xperm.b:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3190,7 +549,9 @@ xperm.b:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 aes64ds:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3206,7 +567,9 @@ aes64ds:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes64dsm:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3222,7 +585,9 @@ aes64dsm:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes64es:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3238,7 +603,9 @@ aes64es:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes64esm:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3254,7 +621,9 @@ aes64esm:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 aes64ks1i:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3269,7 +638,9 @@ aes64ks1i:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
     
 aes64ks2:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3287,7 +658,9 @@ aes64ks2:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sha512sig0:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3306,7 +679,9 @@ sha512sig0:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 sha512sig1:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3325,7 +700,9 @@ sha512sig1:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 sha512sum0:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3344,7 +721,9 @@ sha512sum0:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 sha512sum1:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3363,7 +742,9 @@ sha512sum1:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 aes64im:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3382,7 +763,9 @@ aes64im:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
     
 rolw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3403,7 +786,9 @@ rolw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 rev8.w:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op: grevi
   isa: 
@@ -3421,7 +806,9 @@ rev8.w:
     RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
 
 packw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3442,7 +829,9 @@ packw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 packuw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3458,7 +847,9 @@ packuw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 add.uw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3477,7 +868,9 @@ add.uw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sh1add:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3496,7 +889,9 @@ sh1add:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sh1add.uw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3515,7 +910,9 @@ sh1add.uw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sh2add:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3534,7 +931,9 @@ sh2add:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sh2add.uw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3553,7 +952,9 @@ sh2add.uw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sh3add:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3572,7 +973,9 @@ sh3add:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 sh3add.uw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3591,7 +994,9 @@ sh3add.uw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 slli.uw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -3610,7 +1015,9 @@ slli.uw:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 andn:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3636,7 +1043,9 @@ andn:
 # 3.1.1. 16-bit Addition & Subtraction Instructions
 
 add16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3661,7 +1070,9 @@ add16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 radd16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3686,7 +1097,9 @@ radd16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 uradd16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3711,7 +1124,9 @@ uradd16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kadd16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3736,7 +1151,9 @@ kadd16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukadd16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3761,7 +1178,9 @@ ukadd16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 sub16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3787,7 +1206,9 @@ sub16:
 
 
 rsub16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3813,7 +1234,9 @@ rsub16:
 
 
 ursub16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3838,7 +1261,9 @@ ursub16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ksub16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3863,7 +1288,9 @@ ksub16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 uksub16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3888,7 +1315,9 @@ uksub16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 cras16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3913,7 +1342,9 @@ cras16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rcras16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3939,7 +1370,9 @@ rcras16:
 
 
 urcras16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3964,7 +1397,9 @@ urcras16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kcras16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -3988,7 +1423,9 @@ kcras16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 clz:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4005,7 +1442,9 @@ clz:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
     
 clzw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -4022,7 +1461,9 @@ clzw:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 cpop:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4039,7 +1480,9 @@ cpop:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) 
     
 cpopw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -4056,7 +1499,9 @@ cpopw:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
     
 ctz:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4073,7 +1518,9 @@ ctz:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
     
 ctzw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -4090,7 +1537,9 @@ ctzw:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
     
 max:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4109,7 +1558,9 @@ max:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukcras16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4133,7 +1584,9 @@ ukcras16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg) 
     
 maxu:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4152,7 +1605,9 @@ maxu:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 crsa16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4176,7 +1631,9 @@ crsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 min:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4195,7 +1652,9 @@ min:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rcrsa16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4219,7 +1678,9 @@ rcrsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 minu:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4238,7 +1699,9 @@ minu:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urcrsa16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4263,7 +1726,9 @@ urcrsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kcrsa16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4287,7 +1752,9 @@ kcrsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 orc.b:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4304,7 +1771,9 @@ orc.b:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) 
 
 orn:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa:
@@ -4327,7 +1796,9 @@ orn:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukcrsa16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4352,7 +1823,9 @@ ukcrsa16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 stas16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4377,7 +1850,9 @@ stas16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rstas16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4401,7 +1876,9 @@ rstas16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 rev8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op: grevi
   isa: 
@@ -4427,7 +1904,9 @@ rev8:
 
 
 ror:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4450,7 +1929,9 @@ ror:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urstas16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4475,7 +1956,9 @@ urstas16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kstas16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4500,7 +1983,9 @@ kstas16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukstas16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4524,7 +2009,9 @@ ukstas16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rori:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4546,7 +2033,9 @@ rori:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
  
 roriw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -4568,7 +2057,9 @@ roriw:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 rorw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -4591,7 +2082,9 @@ rorw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 stsa16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4616,7 +2109,9 @@ stsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rstsa16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4641,7 +2136,9 @@ rstsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urstsa16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4665,7 +2162,9 @@ urstsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 sext.b:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4682,7 +2181,9 @@ sext.b:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)  
     
 sext.h:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4699,7 +2200,9 @@ sext.h:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg) 
 
 xnor:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa:
@@ -4722,7 +2225,9 @@ xnor:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kstsa16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4747,7 +2252,9 @@ kstsa16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukstsa16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4771,7 +2278,9 @@ ukstsa16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
   
 zext.h:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4788,7 +2297,9 @@ zext.h:
     TEST_RD_OP($inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 clmul:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa:
@@ -4814,7 +2325,9 @@ clmul:
 # 3.1.2. 8-bit Addition & Subtraction Instructions
 
 add8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4846,7 +2359,9 @@ add8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 clmulh:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa:
@@ -4870,7 +2385,9 @@ clmulh:
 
 
 radd8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4903,7 +2420,9 @@ radd8:
 
 
 clmulr:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4922,7 +2441,9 @@ clmulr:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 uradd8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4954,7 +2475,9 @@ uradd8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 bclr:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -4974,7 +2497,9 @@ bclr:
 
 
 kadd8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5007,7 +2532,9 @@ kadd8:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukadd8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5039,7 +2566,9 @@ ukadd8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 bclri:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5056,7 +2585,9 @@ bclri:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
     
 bext:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5075,7 +2606,9 @@ bext:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 sub8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5108,7 +2641,9 @@ sub8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rsub8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5141,7 +2676,9 @@ rsub8:
 
     
 bexti:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5158,7 +2695,9 @@ bexti:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
     
 binv:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5178,7 +2717,9 @@ binv:
 
 
 ursub8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5212,7 +2753,9 @@ ursub8:
 
 
 ksub8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5245,7 +2788,9 @@ ksub8:
 
     
 binvi:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5262,7 +2807,9 @@ binvi:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
     
 bset:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5281,7 +2828,9 @@ bset:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 uksub8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5316,7 +2865,9 @@ uksub8:
 # 3.1.3. 16-bit Shift Instructions
 
 sra16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5338,7 +2889,9 @@ sra16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5359,7 +2912,9 @@ srai16:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 sra16.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5381,7 +2936,9 @@ sra16.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai16.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5402,7 +2959,9 @@ srai16.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 srl16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5424,7 +2983,9 @@ srl16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srli16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5445,7 +3006,9 @@ srli16:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 srl16.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5467,7 +3030,9 @@ srl16.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srli16.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5488,7 +3053,9 @@ srli16.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 sll16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5510,7 +3077,9 @@ sll16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 slli16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5531,7 +3100,9 @@ slli16:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 ksll16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5553,7 +3124,9 @@ ksll16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslli16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5574,7 +3147,9 @@ kslli16:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 kslra16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5596,7 +3171,9 @@ kslra16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslra16.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5620,7 +3197,9 @@ kslra16.u:
 # 3.1.4. 8-bit Shift Instructions
 
 sra8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5646,7 +3225,9 @@ sra8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5671,7 +3252,9 @@ srai8:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 sra8.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5697,7 +3280,9 @@ sra8.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai8.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5722,7 +3307,9 @@ srai8.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 srl8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5748,7 +3335,9 @@ srl8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srli8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5773,7 +3362,9 @@ srli8:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 srl8.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5799,7 +3390,9 @@ srl8.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srli8.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5824,7 +3417,9 @@ srli8.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 sll8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5850,7 +3445,9 @@ sll8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 slli8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5875,7 +3472,9 @@ slli8:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 ksll8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5901,7 +3500,9 @@ ksll8:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslli8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5926,7 +3527,9 @@ kslli8:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 kslra8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5952,7 +3555,9 @@ kslra8:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslra8.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -5980,7 +3585,9 @@ kslra8.u:
 # 3.1.5. 16-bit Compare Instructions
 
 cmpeq16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6005,7 +3612,9 @@ cmpeq16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 scmplt16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6030,7 +3639,9 @@ scmplt16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 scmple16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6055,7 +3666,9 @@ scmple16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ucmplt16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6080,7 +3693,9 @@ ucmplt16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ucmple16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6107,7 +3722,9 @@ ucmple16:
 # 3.1.6. 8-bit Compare Instructions
 
 cmpeq8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6140,7 +3757,9 @@ cmpeq8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 scmplt8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6173,7 +3792,9 @@ scmplt8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 scmple8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6206,7 +3827,9 @@ scmple8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ucmplt8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6239,7 +3862,9 @@ ucmplt8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ucmple8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6274,7 +3899,9 @@ ucmple8:
 # 3.1.7. 16-bit Multiply Instructions
 
 smul16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6300,7 +3927,9 @@ smul16:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smulx16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6326,7 +3955,9 @@ smulx16:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umul16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6352,7 +3983,9 @@ umul16:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umulx16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6378,7 +4011,9 @@ umulx16:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 khm16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6403,7 +4038,9 @@ khm16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmx16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6430,7 +4067,9 @@ khmx16:
 # 3.1.8. 8-bit Multiply Instructions
 
 smul8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6464,7 +4103,9 @@ smul8:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smulx8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6498,7 +4139,9 @@ smulx8:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umul8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6532,7 +4175,9 @@ umul8:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umulx8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6566,7 +4211,9 @@ umulx8:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 khm8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6599,7 +4246,9 @@ khm8:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmx8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6634,7 +4283,9 @@ khmx8:
 # 3.1.9. 16-bit Misc Instructions
 
 smin16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6659,7 +4310,9 @@ smin16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umin16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6684,7 +4337,9 @@ umin16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smax16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6709,7 +4364,9 @@ smax16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umax16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6734,7 +4391,9 @@ umax16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 sclip16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6755,7 +4414,9 @@ sclip16:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 uclip16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6776,7 +4437,9 @@ uclip16:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 kabs16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6796,7 +4459,9 @@ kabs16:
     TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg)
 
 clrs16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6816,7 +4481,9 @@ clrs16:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 clz16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6836,7 +4503,9 @@ clz16:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 swap16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6858,7 +4527,9 @@ swap16:
 # 3.1.10. 8-bit Misc Instructions
 
 smin8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6891,7 +4562,9 @@ smin8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umin8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6924,7 +4597,9 @@ umin8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smax8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6957,7 +4632,9 @@ smax8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umax8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6990,7 +4667,9 @@ umax8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kabs8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7014,7 +4693,9 @@ kabs8:
     TEST_PKR_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $rs1, $swreg, $offset, $testreg)
 
 sclip8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7039,7 +4720,9 @@ sclip8:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 uclip8:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7064,7 +4747,9 @@ uclip8:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 clrs8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7088,7 +4773,9 @@ clrs8:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 clz8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7112,7 +4799,9 @@ clz8:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 swap8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7138,7 +4827,9 @@ swap8:
 # 3.1.11. 8-bit Unpacking Instructions
 
 sunpkd810:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7162,7 +4853,9 @@ sunpkd810:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 sunpkd820:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7186,7 +4879,9 @@ sunpkd820:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 sunpkd830:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7210,7 +4905,9 @@ sunpkd830:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 sunpkd831:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7234,7 +4931,9 @@ sunpkd831:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 sunpkd832:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7258,7 +4957,9 @@ sunpkd832:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 zunpkd810:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7282,7 +4983,9 @@ zunpkd810:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 zunpkd820:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7306,7 +5009,9 @@ zunpkd820:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 zunpkd830:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7330,7 +5035,9 @@ zunpkd830:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 zunpkd831:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7354,7 +5061,9 @@ zunpkd831:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 zunpkd832:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7380,7 +5089,9 @@ zunpkd832:
 # 3.2 Partial-SIMD Data Processing Instructions
 
 pkbb16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7405,7 +5116,9 @@ pkbb16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pkbt16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7430,7 +5143,9 @@ pkbt16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pktb16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7455,7 +5170,9 @@ pktb16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pktt16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7480,7 +5197,9 @@ pktt16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 # 3.2.2 Most Significant Word 32x32 Multiply & Add Instructions
 smmul:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7501,7 +5220,9 @@ smmul:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smmul.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7522,7 +5243,9 @@ smmul.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kmmac:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7543,7 +5266,9 @@ kmmac:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmac.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7564,7 +5289,9 @@ kmmac.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmsb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7585,7 +5312,9 @@ kmmsb:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmsb.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7606,7 +5335,9 @@ kmmsb.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kwmmul:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7627,7 +5358,9 @@ kwmmul:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kwmmul.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7650,7 +5383,9 @@ kwmmul.u:
 
 # 3.2.3 Most Significant Word 32x16 Multiply & Add Instructions
 smmwb:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7673,7 +5408,9 @@ smmwb:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smmwb.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7696,7 +5433,9 @@ smmwb.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smmwt:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7719,7 +5458,9 @@ smmwt:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smmwt.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7742,7 +5483,9 @@ smmwt.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kmmawb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7765,7 +5508,9 @@ kmmawb:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmawb.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7788,7 +5533,9 @@ kmmawb.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmawt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7811,7 +5558,9 @@ kmmawt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmawt.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7834,7 +5583,9 @@ kmmawt.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmwb2:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7858,7 +5609,9 @@ kmmwb2:
 
 
 kmmwb2.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7881,7 +5634,9 @@ kmmwb2.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmwt2:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7904,7 +5659,9 @@ kmmwt2:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmwt2.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7928,7 +5685,9 @@ kmmwt2.u:
 
 
 kmmawb2:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7951,7 +5710,9 @@ kmmawb2:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmawb2.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7974,7 +5735,9 @@ kmmawb2.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmawt2:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -7997,7 +5760,9 @@ kmmawt2:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmmawt2.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8023,7 +5788,9 @@ kmmawt2.u:
 # 3.2.4 Signed 16-bit Multiply with 32-bit Add/Subtract Instructions
 
 smbb16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8048,7 +5815,9 @@ smbb16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smbt16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8073,7 +5842,9 @@ smbt16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smtt16:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8098,7 +5869,9 @@ smtt16:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kmda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8123,7 +5896,9 @@ kmda:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmxda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8148,7 +5923,9 @@ kmxda:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 smds:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8173,7 +5950,9 @@ smds:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smdrs:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8198,7 +5977,9 @@ smdrs:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smxds:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8223,7 +6004,9 @@ smxds:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kmabb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8248,7 +6031,9 @@ kmabb:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmabt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8273,7 +6058,9 @@ kmabt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmatt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8298,7 +6085,9 @@ kmatt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmada:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8323,7 +6112,9 @@ kmada:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmaxda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8348,7 +6139,9 @@ kmaxda:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmads:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8373,7 +6166,9 @@ kmads:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmadrs:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8398,7 +6193,9 @@ kmadrs:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmaxds:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8423,7 +6220,9 @@ kmaxds:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmsda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8448,7 +6247,9 @@ kmsda:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmsxda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8475,7 +6276,9 @@ kmsxda:
 # 3.2.5 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
 
 smal:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8503,7 +6306,9 @@ smal:
 # 3.2.6 Miscellaneous Instructions
 
 sclip32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8522,7 +6327,9 @@ sclip32:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 uclip32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8541,7 +6348,9 @@ uclip32:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 clrs32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8559,7 +6368,9 @@ clrs32:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 clz32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8577,7 +6388,9 @@ clz32:
     TEST_RD_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
 
 pbsad:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8610,7 +6423,9 @@ pbsad:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pbsada:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8645,7 +6460,9 @@ pbsada:
 # 3.2.7. 8-bit Multiply with 32-bit Add Instructions
 
 smaqa:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8678,7 +6495,9 @@ smaqa:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umaqa:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8711,7 +6530,9 @@ umaqa:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smaqa.su:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8746,7 +6567,9 @@ smaqa.su:
 # 3.3.1 64-bit Addition & Subtraction Instructions
 
 add64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32]
   std_op:
   isa: 
@@ -8767,7 +6590,9 @@ add64:
     TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)
 
 radd64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8788,7 +6613,9 @@ radd64:
     TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)
 
 uradd64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8851,7 +6678,9 @@ ukadd64:
     TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)
 
 sub64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32]
   std_op:
   isa: 
@@ -8872,7 +6701,9 @@ sub64:
     TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)
 
 rsub64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8893,7 +6724,9 @@ rsub64:
     TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)
 
 ursub64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8958,7 +6791,9 @@ uksub64:
 # 3.2.2 32-bit Multiply with 64-bit Add/Subtract Instructions
 
 smar64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -8981,7 +6816,9 @@ smar64:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smsr64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9004,7 +6841,9 @@ smsr64:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umar64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9027,7 +6866,9 @@ umar64:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umsr64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9145,7 +6986,9 @@ ukmsr64:
 # 3.3.3 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
 
 smalbb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9172,7 +7015,9 @@ smalbb:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smalbt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9199,7 +7044,9 @@ smalbt:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smaltt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9226,7 +7073,9 @@ smaltt:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smalda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9253,7 +7102,9 @@ smalda:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smalxda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9280,7 +7131,9 @@ smalxda:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smalds:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9307,7 +7160,9 @@ smalds:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smaldrs:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9334,7 +7189,9 @@ smaldrs:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smalxds:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9361,7 +7218,9 @@ smalxds:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smslda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9388,7 +7247,9 @@ smslda:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smslxda:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9417,7 +7278,9 @@ smslxda:
 # 3.4.1 Q15 Saturation Instructions
 
 kaddh:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9443,7 +7306,9 @@ kaddh:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ksubh:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9469,7 +7334,9 @@ ksubh:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmbb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9495,7 +7362,9 @@ khmbb:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmbt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9520,7 +7389,9 @@ khmbt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmtt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9545,7 +7416,9 @@ khmtt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukaddh:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9570,7 +7443,9 @@ ukaddh:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 uksubh:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9597,7 +7472,9 @@ uksubh:
 # 3.4.2 Q31 Saturation Instructions
 
 kaddw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9618,7 +7495,9 @@ kaddw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukaddw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9639,7 +7518,9 @@ ukaddw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ksubw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9660,7 +7541,9 @@ ksubw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 uksubw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9681,7 +7564,9 @@ uksubw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmbb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9706,7 +7591,9 @@ kdmbb:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmbt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9731,7 +7618,9 @@ kdmbt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmtt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9756,7 +7645,9 @@ kdmtt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslraw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9777,7 +7668,9 @@ kslraw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslraw.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9798,7 +7691,9 @@ kslraw.u:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ksllw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9818,7 +7713,9 @@ ksllw:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslliw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9838,7 +7735,9 @@ kslliw:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 kdmabb:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9863,7 +7762,9 @@ kdmabb:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmabt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9888,7 +7789,9 @@ kdmabt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmatt:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9913,7 +7816,9 @@ kdmatt:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kabsw:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9933,7 +7838,9 @@ kabsw:
 # 3.4.3. 32-bit Computation Instructions
 
 raddw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9954,7 +7861,9 @@ raddw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 uraddw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9975,7 +7884,9 @@ uraddw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rsubw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -9996,7 +7907,9 @@ rsubw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ursubw:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10017,7 +7930,9 @@ ursubw:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 mulr64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10040,7 +7955,9 @@ mulr64:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 mulsr64:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10063,7 +7980,9 @@ mulsr64:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 maddr32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10084,7 +8003,9 @@ maddr32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 msubr32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10107,7 +8028,9 @@ msubr32:
 # 3.4.4 Overflow/Saturation Status Manipulation Instructions
 # alias for CSRR Rd, vxsat 
 # rdov:
-#   stride: 1
+#   sig:
+#    stride: 1
+#    sz: 'XLEN/8'
 #   rd_op_data: *all_regs
 #   xlen: [32,64]
 #   std_op:
@@ -10123,7 +8046,9 @@ msubr32:
 
 # alias for CSRRCI x0, vxsat, 1
 # clrov:
-#   stride: 1
+#   sig:
+#    stride: 1
+#    sz: 'XLEN/8'
 #   rd_op_data: *all_regs
 #   xlen: [32,64]
 #   std_op:
@@ -10140,7 +8065,9 @@ msubr32:
 # 3.4.5. Miscellaneous Instructions
 
 ave:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10158,7 +8085,9 @@ ave:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 sra.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10176,7 +8105,9 @@ sra.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10194,7 +8125,9 @@ srai.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 bitrev:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10212,7 +8145,9 @@ bitrev:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 bitrevi:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10229,7 +8164,9 @@ bitrevi:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 wext:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10257,7 +8194,9 @@ wext:
     TEST_P64_NPN_OP($inst, $rd, $rs1, $rs1_hi, $rs2, $correctval, $rs1_val, $rs1_val_hi, $rs2_val, $swreg, $offset, $testreg)
 
 wexti:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10278,7 +8217,9 @@ wexti:
 
 
 insb:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10298,7 +8239,9 @@ insb:
 # Table 27. (RV64 Only) SIMD 32-bit Add/Subtract Instructions
 
 add32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10319,7 +8262,9 @@ add32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 radd32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10340,7 +8285,9 @@ radd32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 uradd32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10361,7 +8308,9 @@ uradd32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kadd32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10382,7 +8331,9 @@ kadd32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukadd32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10403,7 +8354,9 @@ ukadd32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 sub32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10424,7 +8377,9 @@ sub32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rsub32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10445,7 +8400,9 @@ rsub32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ursub32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10466,7 +8423,9 @@ ursub32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 ksub32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10487,7 +8446,9 @@ ksub32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 uksub32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10508,7 +8469,9 @@ uksub32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 cras32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10529,7 +8492,9 @@ cras32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rcras32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10550,7 +8515,9 @@ rcras32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urcras32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10571,7 +8538,9 @@ urcras32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kcras32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10592,7 +8561,9 @@ kcras32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukcras32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10613,7 +8584,9 @@ ukcras32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 crsa32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10634,7 +8607,9 @@ crsa32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rcrsa32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10655,7 +8630,9 @@ rcrsa32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urcrsa32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10676,7 +8653,9 @@ urcrsa32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kcrsa32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10697,7 +8676,9 @@ kcrsa32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukcrsa32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10718,7 +8699,9 @@ ukcrsa32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 stas32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10739,7 +8722,9 @@ stas32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rstas32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10760,7 +8745,9 @@ rstas32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urstas32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10781,7 +8768,9 @@ urstas32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kstas32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10802,7 +8791,9 @@ kstas32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukstas32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10823,7 +8814,9 @@ ukstas32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 stsa32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10844,7 +8837,9 @@ stsa32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 rstsa32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10865,7 +8860,9 @@ rstsa32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 urstsa32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10886,7 +8883,9 @@ urstsa32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kstsa32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10907,7 +8906,9 @@ kstsa32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukstsa32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10930,7 +8931,9 @@ ukstsa32:
 # Table 28. (RV64 Only) SIMD 32-bit Shift Instructions
 
 sra32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10950,7 +8953,9 @@ sra32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10969,7 +8974,9 @@ srai32:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 sra32.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -10989,7 +8996,9 @@ sra32.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srai32.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11008,7 +9017,9 @@ srai32.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 srl32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11028,7 +9039,9 @@ srl32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srli32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11047,7 +9060,9 @@ srli32:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 srl32.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11067,7 +9082,9 @@ srl32.u:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 srli32.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11086,7 +9103,9 @@ srli32.u:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 sll32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11106,7 +9125,9 @@ sll32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 slli32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11125,7 +9146,9 @@ slli32:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 ksll32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11145,7 +9168,9 @@ ksll32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslli32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11164,7 +9189,9 @@ kslli32:
     TEST_PKIMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $rs1, $swreg, $offset, $testreg)
 
 kslra32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11184,7 +9211,9 @@ kslra32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kslra32.u:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11206,7 +9235,9 @@ kslra32.u:
 # Table 29. (RV64 Only) SIMD 32-bit Miscellaneous Instructions
 
 smin32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11227,7 +9258,9 @@ smin32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umin32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11248,7 +9281,9 @@ umin32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smax32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11269,7 +9304,9 @@ smax32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 umax32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11290,7 +9327,9 @@ umax32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kabs32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11310,7 +9349,9 @@ kabs32:
 # Table 30. (RV64 Only) SIMD Q15 saturating Multiply Instructions
 
 khmbb16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11335,7 +9376,9 @@ khmbb16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmbt16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11360,7 +9403,9 @@ khmbt16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 khmtt16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11385,7 +9430,9 @@ khmtt16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmbb16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11410,7 +9457,9 @@ kdmbb16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmbt16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11435,7 +9484,9 @@ kdmbt16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmtt16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11460,7 +9511,9 @@ kdmtt16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmabb16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11485,7 +9538,9 @@ kdmabb16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmabt16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11510,7 +9565,9 @@ kdmabt16:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kdmatt16:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11537,7 +9594,9 @@ kdmatt16:
 # Table 31. (RV64 Only) 32-bit Multiply Instructions
 
 smbb32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11558,7 +9617,9 @@ smbb32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smbt32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11579,7 +9640,9 @@ smbt32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smtt32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11602,7 +9665,9 @@ smtt32:
 # Table 32. (RV64 Only) 32-bit Multiply & Add Instructions
 
 kmabb32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11623,7 +9688,9 @@ kmabb32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmabt32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11644,7 +9711,9 @@ kmabt32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmatt32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11667,7 +9736,9 @@ kmatt32:
 # Table 33. (RV64 Only) 32-bit Parallel Multiply & Add Instructions
 
 kmda32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11688,7 +9759,9 @@ kmda32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmxda32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11709,7 +9782,9 @@ kmxda32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmada32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11730,7 +9805,9 @@ kmada32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmaxda32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11751,7 +9828,9 @@ kmaxda32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmads32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11772,7 +9851,9 @@ kmads32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmadrs32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11793,7 +9874,9 @@ kmadrs32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmaxds32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11814,7 +9897,9 @@ kmaxds32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmsda32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11835,7 +9920,9 @@ kmsda32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmsxda32:
-  stride: 2
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11856,7 +9943,9 @@ kmsxda32:
     TEST_PKRR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 smds32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11877,7 +9966,9 @@ smds32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smdrs32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11898,7 +9989,9 @@ smdrs32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 smxds32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11921,7 +10014,9 @@ smxds32:
 # Table 34. (RV64 Only) Non-SIMD 32-bit Shift Instructions
 
 sraiw.u:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11942,7 +10037,9 @@ sraiw.u:
 # Table 35. (RV64 Only) 32-bit Packing Instructions
 
 pkbb32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11963,7 +10060,9 @@ pkbb32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pkbt32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -11984,7 +10083,9 @@ pkbt32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pktb32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -12005,7 +10106,9 @@ pktb32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 pktt32:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [64]
   std_op:
   isa: 
@@ -12026,7 +10129,9 @@ pktt32:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
     
 bseti:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -12043,7 +10148,9 @@ bseti:
     TEST_IMM_OP( $inst, $rd, $rs1, $correctval, $rs1_val, $imm_val, $swreg, $offset, $testreg)
 
 xperm4:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -12063,7 +10170,9 @@ xperm4:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 xperm8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa:
@@ -12083,7 +10192,9 @@ xperm8:
     TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 brev8:
-  stride: 1
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op: brev8
   isa:
diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py
index 229e63fc..e1deff40 100644
--- a/riscv_ctg/generator.py
+++ b/riscv_ctg/generator.py
@@ -5,6 +5,7 @@
 import re
 from riscv_ctg.constants import *
 from riscv_ctg.log import logger
+from riscv_ctg.helpers import *
 import time
 from math import *
 import struct
@@ -15,15 +16,24 @@
 two_operand_finstructions = ["fadd.s","fsub.s","fmul.s","fdiv.s","fmax.s","fmin.s","feq.s","flt.s","fle.s","fsgnj.s","fsgnjn.s","fsgnjx.s"]
 three_operand_finstructions = ["fmadd.s","fmsub.s","fnmadd.s","fnmsub.s"]
 
-one_operand_dinstructions = ["fsqrt.d","fclass.d","fcvt.w.d","fcvt.wu.d","fcvt.d.w","fcvt.d.wu"]
+one_operand_dinstructions = ["fsqrt.d","fclass.d","fcvt.w.d","fcvt.wu.d","fcvt.d.w","fcvt.d.wu","fcvt.d.s","fcvt.s.d"]
 two_operand_dinstructions = ["fadd.d","fsub.d","fmul.d","fdiv.d","fmax.d","fmin.d","feq.d","flt.d","fle.d","fsgnj.d","fsgnjn.d","fsgnjx.d"]
 three_operand_dinstructions = ["fmadd.d","fmsub.d","fnmadd.d","fnmsub.d"]
 from riscv_ctg.dsp_function import *
 
 twos_xlen = lambda x: twos(x,xlen)
 
+def get_rm(opcode):
+    if any([x in opcode for x in
+        ['fsgnj','fle','flt','feq','fclass','fmv','flw','fsw','fld','fsd','fmin','fmax',
+            'fcvt.d.s', 'fcvt.d.w','fcvt.d.wu']]):
+        return []
+    else:
+        return ['rm_val']
+
 OPS = {
     'rformat': ['rs1', 'rs2', 'rd'],
+    'r4format': ['rs1', 'rs2', 'rs3', 'rd'],
     'iformat': ['rs1', 'rd'],
     'sformat': ['rs1', 'rs2'],
     'bsformat': ['rs1', 'rs2', 'rd'],
@@ -41,9 +51,9 @@
     'cbformat': ['rs1'],
     'cjformat': [],
     'kformat': ['rs1','rd'],
-    'frformat': ['rs1', 'rs2', 'rd'],
+    # 'frformat': ['rs1', 'rs2', 'rd'],
     'fsrformat': ['rs1', 'rd'],
-    'fr4format': ['rs1', 'rs2', 'rs3', 'rd'],
+    # 'fr4format': ['rs1', 'rs2', 'rs3', 'rd'],
     'pbrrformat': ['rs1', 'rs2', 'rd'],
     'phrrformat': ['rs1', 'rs2', 'rd'],
     'pbrformat': ['rs1', 'rd'],
@@ -65,9 +75,12 @@
 ''' Dictionary mapping instruction formats to operands used by those formats '''
 
 VALS = {
-    'rformat': "['rs1_val', 'rs2_val']",
-    'iformat': "['rs1_val', 'imm_val']",
-    'sformat': "['rs1_val', 'rs2_val', 'imm_val']",
+    'rformat': "['rs1_val', 'rs2_val'] + ((get_rm(opcode)+['fcsr']) if is_fext else []) + \
+        ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,3)])",
+    'r4format': "['rs1_val', 'rs2_val', 'rs3_val'] + (['rm_val','fcsr'] if is_fext else []) + \
+        ([] if not is_nan_box else ['rs{0}_nan_prefix'.format(x) for x in range(1,4)])",
+    'iformat': "['rs1_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])",
+    'sformat': "['rs1_val', 'rs2_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])",
     'bsformat': "['rs1_val', 'rs2_val', 'imm_val']",
     'bformat': "['rs1_val', 'rs2_val', 'imm_val']",
     'uformat': "['imm_val']",
@@ -83,9 +96,10 @@
     'cbformat': "['rs1_val', 'imm_val']",
     'cjformat': "['imm_val']",
     'kformat': "['rs1_val']",
-    'frformat': "['rs1_val', 'rs2_val', 'rm_val']",
-    'fsrformat': "['rs1_val', 'rm_val']",
-    'fr4format': "['rs1_val', 'rs2_val', 'rs3_val', 'rm_val']",
+    # 'frformat': "['rs1_val', 'rs2_val', 'rm_val', 'fcsr']",
+    'fsrformat': "['rs1_val', 'fcsr'] + get_rm(opcode) + \
+        ([] if not is_nan_box else ['rs1_nan_prefix'])",
+    # 'fr4format': "['rs1_val', 'rs2_val', 'rs3_val', 'rm_val', 'fcsr']",
     'pbrrformat': 'simd_val_vars("rs1", xlen, 8) + simd_val_vars("rs2", xlen, 8)',
     'phrrformat': 'simd_val_vars("rs1", xlen, 16) + simd_val_vars("rs2", xlen, 16)',
     'pbrformat': 'simd_val_vars("rs1", xlen, 8)',
@@ -167,7 +181,7 @@ class Generator():
     :type xl: int
     :type base_isa_str: str
     '''
-    def __init__(self,fmt,opnode,opcode,randomization, xl, fl,base_isa_str):
+    def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str):
         '''
         This is a Constructor function which initializes various class variables
         depending on the arguments.
@@ -183,22 +197,37 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl,base_isa_str):
         '''
         global xlen
         global flen
+        global iflen
         global base_isa
         xlen = xl
         flen = fl
+        iflen = ifl
         base_isa = base_isa_str
+
+
+        is_nan_box = False
+        is_fext = any(['F' in x or 'D' in x for x in opnode['isa']])
+
+        self.xlen = xl
+        self.flen = fl
+        self.iflen = ifl
+        self.base_isa = base_isa_str
         self.fmt = fmt
         self.opcode = opcode
-
         self.op_vars = OPS[fmt]
-
         self.val_vars = eval(VALS[fmt])
+        self.is_fext = is_fext
+        self.is_nan_box = is_nan_box
+        if is_fext:
+            if fl>ifl:
+                is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']])
+                is_nan_box = not is_int_src
 
         if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd"]:
             self.val_vars = self.val_vars + ['ea_align']
         self.template = opnode['template']
         self.opnode = opnode
-        self.stride = opnode['stride']
+        # self.stride = opnode['stride']
         if 'operation' in opnode:
             self.operation = opnode['operation']
         else:
@@ -217,7 +246,9 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl,base_isa_str):
             if key in opnode:
                 datasets[entry] = eval(opnode[key])
             else:
+                logger.warning("{0} not defined for {1}. Defaulting to [0].".format(key,self.opcode))
                 datasets[entry] = [0]
+
         self.datasets = datasets
         self.random=randomization
         self.default_regs = get_default_registers(self.op_vars, self.datasets)
@@ -341,6 +372,10 @@ def valcomb(self, cgf):
 
         conds = list(cgf['val_comb'].keys())
         inds = set(range(len(conds)))
+        merge = True
+        if 'fcvt' in self.opcode or 'fmv' in self.opcode:
+            if self.opcode.split(".")[-1] in ['x','w','wu','l','lu']:
+                merge = "fmv.x.w" in self.opcode
         while inds:
             req_val_comb = conds[inds.pop()]
             if("#nosat" in req_val_comb):
@@ -349,81 +384,32 @@ def valcomb(self, cgf):
                 req_val_comb_minus_comm = req_val_comb.split("#")[0]
                 x = req_val_comb_minus_comm.split(" and ")
 
-                if self.opcode[0] == 'f' and 'fence' not in self.opcode:
+                if self.is_fext:
 	                # fs + fe + fm -> Combiner Script
-                    if (flen == 32):
-                        e_sz = 8
-                        m_sz = 23
-                    else:
-                        e_sz = 11
-                        m_sz = 52
-                    e_sz_string = '{:0'+str(e_sz)+'b}'
-                    m_sz_string = '{:0'+str(m_sz)+'b}'
-                    size_string = '{:0'+str(int(flen/4))+'x}'
-
-                    if len(x) == (1*3 + 1):																# 1 Operand Instructions
-                        fs1 = x[0].split(" == ")[1]
-                        fe1 = x[1].split(" == ")[1]
-                        fm1 = x[2].split(" == ")[1]
-                        rm = x[-1].split(" == ")[1]
-                        bin_val1 = fs1 + e_sz_string.format(int(fe1,16)) + m_sz_string.format(int(fm1,16))
-                        hex_val1 = '0x' + size_string.format(int(bin_val1, 2))
-                        x = ["rs1_val == " + hex_val1, "rm_val == " + rm]
-
-                    elif len(x) == (2*3 + 1):															# 2 Operand Instructions
-                        fs1 = x[0].split(" == ")[1]
-                        fe1 = x[1].split(" == ")[1]
-                        fm1 = x[2].split(" == ")[1]
-                        fs2 = x[3].split(" == ")[1]
-                        fe2 = x[4].split(" == ")[1]
-                        fm2 = x[5].split(" == ")[1]
-                        rm = x[-1].split(" == ")[1]
-                        bin_val1 = fs1 + e_sz_string.format(int(fe1,16)) + m_sz_string.format(int(fm1,16))
-                        bin_val2 = fs2 + e_sz_string.format(int(fe2,16)) + m_sz_string.format(int(fm2,16))
-                        hex_val1 = '0x' + size_string.format(int(bin_val1, 2))
-                        hex_val2 = '0x' + size_string.format(int(bin_val2, 2))
-                        x = ["rs1_val == " + hex_val1, "rs2_val == " + hex_val2, "rm_val == " + rm]
-
-                    elif len(x) == (3*3 + 1):															# 3 Operand Instructions
-                        fs1 = x[0].split(" == ")[1]
-                        fe1 = x[1].split(" == ")[1]
-                        fm1 = x[2].split(" == ")[1]
-                        fs2 = x[3].split(" == ")[1]
-                        fe2 = x[4].split(" == ")[1]
-                        fm2 = x[5].split(" == ")[1]
-                        fs3 = x[6].split(" == ")[1]
-                        fe3 = x[7].split(" == ")[1]
-                        fm3 = x[8].split(" == ")[1]
-                        rm = x[-1].split(" == ")[1]
-                        bin_val1 = fs1 + e_sz_string.format(int(fe1,16)) + m_sz_string.format(int(fm1,16))
-                        bin_val2 = fs2 + e_sz_string.format(int(fe2,16)) + m_sz_string.format(int(fm2,16))
-                        bin_val3 = fs3 + e_sz_string.format(int(fe3,16)) + m_sz_string.format(int(fm3,16))
-                        hex_val1 = '0x' + size_string.format(int(bin_val1, 2))
-                        hex_val2 = '0x' + size_string.format(int(bin_val2, 2))
-                        hex_val3 = '0x' + size_string.format(int(bin_val3, 2))
-                        x = ["rs1_val == " + hex_val1, "rs2_val == " + hex_val2, "rs3_val == " + hex_val3, "rm_val == " + rm]
-
-                for i in self.val_vars:
-                    for j in x:
-                        if i in j:
-                            if(d.get(i,"None") == "None"):
-                                d[i] = j.split("==")[1]
-                            else:
-                                logger.error("Invalid Coverpoint: More than one value of "+ i +" found!")
-                                sys.exit(1)
-                if(list(d.keys()) != self.val_vars):
-                    logger.error("Invalid Coverpoint: Cannot bypass SAT Solver for partially defined coverpoints!")
-                    sys.exit(1)
-                for y in d:
-                    if("0x" in d[y]):
-                        soln.append(int(d[y],16))
-                    elif("0b" in d[y]):
-                        soln.append(int(d[y],2))
-                    else:
-                        soln.append(int(d[y]))
+                    try:
+                        d = merge_fields_f(self.val_vars,req_val_comb,self.flen,self.iflen,merge)
+                    except ExtractException as e:
+                        logger.warning("Valcomb skip: "+str(e))
+                        continue
+                else:
+                    for i in self.val_vars:
+                        for j in x:
+                            if i in j:
+                                if(d.get(i,"None") == "None"):
+                                    d[i] = j.split("==")[1]
+                                else:
+                                    logger.error("Invalid Coverpoint: More than one value of "+ i +" found!")
+                                    sys.exit(1)
+                if(set(d.keys()) != set(self.val_vars)):
+                    logger.warning(
+                        "Valcomb skip: Cannot bypass SAT Solver for partially defined coverpoints!"\
+                                + str(req_val_comb))
+                    continue
+                for y in self.val_vars:
+                    soln.append(d[y])
+
                 soln.append(req_val_comb_minus_comm)
                 val_tuple = soln
-
             else:
                 if self.random:
                     problem = Problem(MinConflictsSolver())
@@ -666,6 +652,40 @@ def __instr__(self, op=None, val=None):
                 instr[var] = str(self.datasets[var][0])
         return instr
 
+    def __fext_instr__(self,op=None,val=None):
+        rm_dict = {
+                0: 'rne',
+                1: 'rtz',
+                2: 'rdn',
+                3: 'rup',
+                4: 'rmm',
+                7: 'dyn'}
+        cond_str = ''
+        if op:
+            cond_str += op[-1]+','
+        if val:
+            cond_str += val[-1]
+        instr = {'inst':self.opcode,'comment':cond_str,'index':'0'}
+        if op:
+            for var,reg in zip(self.op_vars,op):
+                instr[var] = str(reg)
+        else:
+            for i,var in enumerate(self.op_vars):
+                instr[var]=self.default_regs[var]
+        if val:
+            for i,var in enumerate(self.val_vars):
+                if var == 'rm_val':
+                    instr[var] = str(rm_dict[val[i]])
+                else:
+                    instr[var] = str(val[i])
+        else:
+            for var in self.val_vars:
+                if var == 'rm_val':
+                    instr[var] = 'dyn'
+                else:
+                    instr[var] = str(self.datasets[var][0])
+        return instr
+
     def gen_inst(self,op_comb, val_comb, cgf):
         '''
         This function combines the op_comb and val_comb solution dictionaries
@@ -713,7 +733,9 @@ def gen_inst(self,op_comb, val_comb, cgf):
                     for y in op_inds[i:]:
                         if op[y] == op[x]:
                             val[ind_dict[y]] = val[ind_dict[x]]
-            if self.opcode == 'c.lui':
+            if self.is_fext:
+                instr_dict.append(self.__fext_instr__(op,val))
+            elif self.opcode == 'c.lui':
                 instr_dict.append(self.__clui_instr__(op,val))
             elif self.opcode in ['c.beqz', 'c.bnez']:
                 instr_dict.append(self.__cb_instr__(op,val))
@@ -731,7 +753,9 @@ def gen_inst(self,op_comb, val_comb, cgf):
                 instr_dict.append(self.__instr__(op,val))
         op = None
         for val in cont:
-            if self.opcode == 'c.lui':
+            if self.is_fext:
+                instr_dict.append(self.__fext_instr__(op,val))
+            elif self.opcode == 'c.lui':
                 instr_dict.append(self.__clui_instr__(op,val))
             elif self.opcode in ['c.beqz', 'c.bnez']:
                 instr_dict.append(self.__cb_instr__(op,val))
@@ -750,187 +774,207 @@ def gen_inst(self,op_comb, val_comb, cgf):
         final_instr = []
         def eval_inst_coverage(coverpoints,instr):
             cover_hits = {}
-            if 'ea_align' in instr:
-                ea_align = int(instr['ea_align'])
-            if 'rs1_val' in instr:
-                rs1_val = int(instr['rs1_val'])
-            if 'rs2_val' in instr:
-                rs2_val = int(instr['rs2_val'])
-            if 'rs3_val' in instr:
-                rs3_val = int(instr['rs3_val'])
-            if 'rm_val' in instr:
-                rm_val = int(instr['rm_val'])
-            if 'rs1_b0_val' in instr:
-                rs1_b0_val = int(instr['rs1_b0_val'])
-            if 'rs1_b1_val' in instr:
-                rs1_b1_val = int(instr['rs1_b1_val'])
-            if 'rs1_b2_val' in instr:
-                rs1_b2_val = int(instr['rs1_b2_val'])
-            if 'rs1_b3_val' in instr:
-                rs1_b3_val = int(instr['rs1_b3_val'])
-            if 'rs1_b4_val' in instr:
-                rs1_b4_val = int(instr['rs1_b4_val'])
-            if 'rs1_b5_val' in instr:
-                rs1_b5_val = int(instr['rs1_b5_val'])
-            if 'rs1_b6_val' in instr:
-                rs1_b6_val = int(instr['rs1_b6_val'])
-            if 'rs1_b7_val' in instr:
-                rs1_b7_val = int(instr['rs1_b7_val'])
-            if 'rs2_b0_val' in instr:
-                rs2_b0_val = int(instr['rs2_b0_val'])
-            if 'rs2_b1_val' in instr:
-                rs2_b1_val = int(instr['rs2_b1_val'])
-            if 'rs2_b2_val' in instr:
-                rs2_b2_val = int(instr['rs2_b2_val'])
-            if 'rs2_b3_val' in instr:
-                rs2_b3_val = int(instr['rs2_b3_val'])
-            if 'rs2_b4_val' in instr:
-                rs2_b4_val = int(instr['rs2_b4_val'])
-            if 'rs2_b5_val' in instr:
-                rs2_b5_val = int(instr['rs2_b5_val'])
-            if 'rs2_b6_val' in instr:
-                rs2_b6_val = int(instr['rs2_b6_val'])
-            if 'rs2_b7_val' in instr:
-                rs2_b7_val = int(instr['rs2_b7_val'])
-            if 'rs1_h0_val' in instr:
-                rs1_h0_val = int(instr['rs1_h0_val'])
-            if 'rs1_h1_val' in instr:
-                rs1_h1_val = int(instr['rs1_h1_val'])
-            if 'rs1_h2_val' in instr:
-                rs1_h2_val = int(instr['rs1_h2_val'])
-            if 'rs1_h3_val' in instr:
-                rs1_h3_val = int(instr['rs1_h3_val'])
-            if 'rs2_h0_val' in instr:
-                rs2_h0_val = int(instr['rs2_h0_val'])
-            if 'rs2_h1_val' in instr:
-                rs2_h1_val = int(instr['rs2_h1_val'])
-            if 'rs2_h2_val' in instr:
-                rs2_h2_val = int(instr['rs2_h2_val'])
-            if 'rs2_h3_val' in instr:
-                rs2_h3_val = int(instr['rs2_h3_val'])
-            if 'rs1_w0_val' in instr:
-                rs1_w0_val = int(instr['rs1_w0_val'])
-            if 'rs1_w1_val' in instr:
-                rs1_w1_val = int(instr['rs1_w1_val'])
-            if 'rs2_w0_val' in instr:
-                rs2_w0_val = int(instr['rs2_w0_val'])
-            if 'rs2_w1_val' in instr:
-                rs2_w1_val = int(instr['rs2_w1_val'])
-            if 'imm_val' in instr:
-                if self.fmt in ['jformat','bformat'] or instr['inst'] in \
+            var_dict = {}
+            for key in self.val_vars:
+                if key == 'imm_val':
+                    if self.fmt in ['jformat','bformat'] or instr['inst'] in \
                         ['c.beqz','c.bnez','c.jal','c.j','c.jalr']:
-                    imm_val = (-1 if instr['label'] == '1b' else 1) * int(instr['imm_val'])
+                        var_dict['imm_val'] = \
+                            (-1 if instr['label'] == '1b' else 1) * int(instr['imm_val'])
+                    else:
+                        var_dict['imm_val'] = int(instr['imm_val'])
+                elif key == 'rm_val':
+                    var_dict['rm_val'] = int(rm_dict[instr['rm_val']])
                 else:
-                    imm_val = int(instr['imm_val'])
-            if 'rs2' in instr:
-                rs2 = instr['rs2']
-            if 'rd' in instr:
-                rd = instr['rd']
-            if 'rs1' in instr:
-                rs1 = instr['rs1']
-            if 'rs3' in instr:
-                rs3 = instr['rs3']
+                    var_dict[key] = int(instr[key])
+            for key in self.op_vars:
+                var_dict[key] = instr[key]
             if 'val_comb' in coverpoints:
                 valcomb_hits = set([])
                 for coverpoint in coverpoints['val_comb']:
-	                fs1=fe1=fm1=fs2=fe2=fm2=fs3=fe3=fm3=None
-	                bin_val = ''
-	                e_sz = 0
-	                m_sz = 0
-	                if self.opcode[0] == 'f' and 'fence' not in self.opcode and 'fcvt.s.w' not in self.opcode and 'fcvt.s.wu' not in self.opcode and 'fmv.w.x' not in self.opcode and "fsw" not in self.opcode and "fcvt.s.l" not in self.opcode and 'fcvt.s.lu' not in self.opcode and 'fcvt.d.w' not in self.opcode and 'fcvt.d.wu' not in self.opcode and 'fcvt.d.l' not in self.opcode and 'fcvt.d.lu' not in self.opcode and 'fmv.d.x' not in self.opcode and "fld" not in self.opcode and "fsd" not in self.opcode:
-	                    if (flen == 32):
-	                        e_sz = 8
-	                    else:
-	                        e_sz = 11
-	                    if (flen == 32):
-	                        m_sz = 23
-	                    else:
-	                        m_sz = 52
-	                    if 'rs1_val' in instr:
-	                        if (flen == 32):
-	                            bin_val = '{:032b}'.format(rs1_val)
-	                        else:
-	                            bin_val = '{:064b}'.format(rs1_val)
-	                        fs1 = int(bin_val[0],2)
-	                        fe1 = int(bin_val[1:e_sz+1],2)
-	                        fm1 = int(bin_val[e_sz+1:],2)
-	                    if 'rs2_val' in instr:
-	                        if (flen == 32):
-	                            bin_val = '{:032b}'.format(rs2_val)
-	                        else:
-	                            bin_val = '{:064b}'.format(rs2_val)
-	                        fs2 = int(bin_val[0],2)
-	                        fe2 = int(bin_val[1:e_sz+1],2)
-	                        fm2 = int(bin_val[e_sz+1:],2)
-	                    if 'rs3_val' in instr:
-	                        if (flen == 32):
-	                            bin_val = '{:032b}'.format(rs3_val)
-	                        else:
-	                            bin_val = '{:064b}'.format(rs3_val)
-	                        fs3 = int(bin_val[0],2)
-	                        fe3 = int(bin_val[1:e_sz+1],2)
-	                        fm3 = int(bin_val[e_sz+1:],2)
-	                if eval(coverpoint):
-	                	valcomb_hits.add(coverpoint)
+                    if eval(coverpoint,globals(),var_dict):
+                        valcomb_hits.add(coverpoint)
                 cover_hits['val_comb']=valcomb_hits
             if 'op_comb' in coverpoints:
                 opcomb_hits = set([])
                 for coverpoint in coverpoints['op_comb']:
-                    if eval(coverpoint):
+                    if eval(coverpoint,globals(),var_dict):
                         opcomb_hits.add(coverpoint)
                 cover_hits['op_comb']=opcomb_hits
             if 'rs1' in coverpoints:
-                if rs1 in coverpoints['rs1']:
-                    cover_hits['rs1'] = set([rs1])
+                if var_dict['rs1'] in coverpoints['rs1']:
+                    cover_hits['rs1'] = set([var_dict['rs1']])
             if 'rs2' in coverpoints:
-                if rs2 in coverpoints['rs2']:
-                    cover_hits['rs2'] = set([rs2])
+                if var_dict['rs2'] in coverpoints['rs2']:
+                    cover_hits['rs2'] = set([var_dict['rs2']])
             if 'rs3' in coverpoints:
-                if rs3 in coverpoints['rs3']:
-                    cover_hits['rs3'] = set([rs3])
-
+                if var_dict['rs3'] in coverpoints['rs3']:
+                    cover_hits['rs3'] = set([var_dict['rs3']])
             if 'rd' in coverpoints:
-                if rd in coverpoints['rd']:
-                    cover_hits['rd'] = set([rd])
+                if var_dict['rd'] in coverpoints['rd']:
+                    cover_hits['rd'] = set([var_dict['rd']])
             return cover_hits
         i = 0
-        for instr in instr_dict:
-            unique = False
-            skip_val = False
-            if instr['inst'] in cgf['mnemonics']:
-                if 'rs1' in instr and 'rs2' in instr:
-                    if instr['rs1'] == instr['rs2']:
-                        skip_val = True
-                if 'rs1' in instr:
-                    if instr['rs1'] == 'x0' or instr['rs1'] == 'f0':
-                        skip_val = True
-                if 'rs2' in instr:
-                    if instr['rs2'] == 'x0' or instr['rs2'] == 'f0':
-                        skip_val = True
-                if 'rd' in instr:
-                    if instr['rd'] == 'x0' or instr['rd'] == 'f0':
-                        skip_val = True
-                cover_hits = eval_inst_coverage(cgf,instr)
-                for entry in cover_hits:
-                    if entry=='val_comb' and skip_val:
-                        continue
-                    over = hits[entry] & cover_hits[entry]
-                    if over != cover_hits[entry]:
-                        unique = unique or True
-                    hits[entry] |= cover_hits[entry]
-                if unique:
-                    final_instr.append(instr)
-                else:
-                    i+=1
+        if not self.is_fext:
+            for instr in instr_dict:
+                unique = False
+                skip_val = False
+                if instr['inst'] in cgf['mnemonics']:
+                    if 'rs1' in instr and 'rs2' in instr:
+                        if instr['rs1'] == instr['rs2']:
+                            skip_val = True
+                    if 'rs1' in instr:
+                        if instr['rs1'] == 'x0' or instr['rs1'] == 'f0':
+                            skip_val = True
+                    if 'rs2' in instr:
+                        if instr['rs2'] == 'x0' or instr['rs2'] == 'f0':
+                            skip_val = True
+                    if 'rd' in instr:
+                        if instr['rd'] == 'x0' or instr['rd'] == 'f0':
+                            skip_val = True
+                    cover_hits = eval_inst_coverage(cgf,instr)
+                    for entry in cover_hits:
+                        if entry=='val_comb' and skip_val:
+                            continue
+                        over = hits[entry] & cover_hits[entry]
+                        if over != cover_hits[entry]:
+                            unique = unique or True
+                        hits[entry] |= cover_hits[entry]
+                    if unique:
+                        final_instr.append(instr)
+                    else:
+                        i+=1
+        else:
+            final_instr = instr_dict
 
         if any('IP' in isa for isa in self.opnode['isa']):
             if 'p64_profile' in self.opnode:
-                gen_pair_reg_data(final_instr, xlen, self.opnode['bit_width'], self.opnode['p64_profile'])
+                gen_pair_reg_data(final_instr, self.xlen, self.opnode['bit_width'], self.opnode['p64_profile'])
             elif 'bit_width' in self.opnode:
-                concat_simd_data(final_instr, xlen, self.opnode['bit_width'])
+                concat_simd_data(final_instr, self.xlen, self.opnode['bit_width'])
 
         return final_instr
 
+    def valreg(self,instr_dict):
+        '''
+        This function is responsible for identifying which register can be used to store addresses
+        to load values from memory.
+
+        This register is calculated by traversing the dictionary of solutions
+        created so far and removing all the registers which are used as either
+        operands or destination. When 3 or less registers are pending, one of
+        those registers is used as signature pointer for all the solutions
+        traversed so far.
+
+        Along with the register the offset is also assigned in this function.
+        The offset is incremented by the amount specified in the template node bytes always.
+
+        Care is taken to never use 'x0' as signature pointer.
+        :param instr_dict: list of dictionaries containing the various values necessary for the macro
+        :type instr_dict: list
+        :return: list of dictionaries containing the various values necessary for the macro
+        '''
+        # TODO: Move flagreg allocation to separate function. Preferable to club all anxilliary
+        # register allocations to a generalised function and club both swreg and valreg to it too.
+        if 'val' in self.opnode:
+            paired_regs=0
+            if self.xlen == 32 and 'p64_profile' in self.opnode:
+                p64_profile = self.opnode['p64_profile']
+                paired_regs = self.opnode['p64_profile'].count('p')
+
+            regset = e_regset if 'e' in self.base_isa else default_regset
+            total_instr = len(instr_dict)
+            available_reg = regset.copy()
+            available_reg.remove('x0')
+            count = 0
+            assigned = 0
+            offset = 0
+            stride = self.opnode['val']['stride']
+            num_vars = len(self.op_vars)-1 if 'rd' in self.op_vars else len(self.op_vars)
+            suffix = self.opnode['val']['sz']
+            if flen in self.opnode:
+                FLEN = max(self.opnode['flen'])
+            else:
+                FLEN = 0
+            XLEN = max(self.opnode['xlen'])
+            SIGALIGN = max(XLEN,FLEN)/8
+            stride_sz = eval(suffix)
+            template = Template(eval(self.opnode['val']['val_template']))
+            width = self.iflen if self.is_fext else self.xlen
+            for instr in instr_dict:
+                if 'rs1' in instr and instr['rs1'] in available_reg:
+                    available_reg.remove(instr['rs1'])
+                if 'rs2' in instr and instr['rs2'] in available_reg:
+                    available_reg.remove(instr['rs2'])
+                if 'rd' in instr and instr['rd'] in available_reg:
+                    available_reg.remove(instr['rd'])
+                if 'rs1_hi' in instr and instr['rs1_hi'] in available_reg:
+                    available_reg.remove(instr['rs1_hi'])
+                if 'rs2_hi' in instr and instr['rs2_hi'] in available_reg:
+                    available_reg.remove(instr['rs2_hi'])
+                if 'rd_hi' in instr and instr['rd_hi'] in available_reg:
+                    available_reg.remove(instr['rd_hi'])
+                if 'swreg' in instr and instr['swreg'] in available_reg:
+                    available_reg.remove(instr['swreg'])
+                if 'testreg' in instr and instr['testreg'] in available_reg:
+                    available_reg.remove(instr['testreg'])
+                if len(available_reg) <= 3+len(self.op_vars)+paired_regs:
+                    curr_reg = available_reg[0]
+                    offset = 0
+                    for i in range(assigned, count+1):
+                        if 'valaddr_reg' not in instr_dict[i]:
+                            instr_dict[i]['valaddr_reg'] = curr_reg
+                            instr_dict[i]['val_offset'] = str(offset) + '*' + suffix
+                            offset += stride
+                            if offset*stride_sz > 2047:
+                                offset = 0
+                            assigned += 1
+                            instr_dict[i]['val_section'] = []
+                            for j in range(1,num_vars+1):
+                                dval = ()
+                                if self.is_nan_box:
+                                    dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)],
+                                            instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen)
+                                else:
+                                    dval = (instr_dict[i]['rs{0}_val'.format(j)],width)
+                                if self.is_fext:
+                                    instr_dict[i]['flagreg'] = available_reg[1]
+                                instr_dict[i]['val_section'].append(
+                                        template.substitute(val=dval[0],width=dval[1]))
+                                instr_dict[i]['load_instr'] = self.opnode['val']['load_instr']
+                    available_reg = regset.copy()
+                    available_reg.remove('x0')
+                count += 1
+            if assigned != total_instr and len(available_reg) != 0:
+                curr_reg = available_reg[0]
+                offset = 0
+                for i in range(len(instr_dict)):
+                    if 'valaddr_reg' not in instr_dict[i]:
+                        instr_dict[i]['valaddr_reg'] = curr_reg
+                        instr_dict[i]['val_offset'] = str(offset) + '*' + suffix
+                        offset += stride
+                        if offset*stride_sz > 2047:
+                            offset = 0
+                        assigned += 1
+                        instr_dict[i]['val_section'] = []
+                        for j in range(1,num_vars+1):
+                            dval = ()
+                            if self.is_nan_box:
+                                dval = nan_box(instr_dict[i]['rs{0}_nan_prefix'.format(j)],
+                                        instr_dict[i]['rs{0}_val'.format(j)],self.flen,self.iflen)
+                            else:
+                                dval = (instr_dict[i]['rs{0}_val'.format(j)],width)
+                            if self.is_fext:
+                                instr_dict[i]['flagreg'] = available_reg[1]
+                            instr_dict[i]['val_section'].append(
+                                    template.substitute(val=dval[0],width=dval[1]))
+                            instr_dict[i]['load_instr'] = self.opnode['val']['load_instr']
+            return instr_dict
+        else:
+            return instr_dict
+
+
+
     def swreg(self, instr_dict):
         '''
         This function is responsible for identifying which register can be used
@@ -943,71 +987,37 @@ def swreg(self, instr_dict):
         traversed so far.
 
         Along with the register the offset is also assigned in this function.
-        The offset is incremented by xlen/8 bytes always.
+        The offset is incremented by the amount specified in the template node bytes always.
 
         Care is taken to never use 'x0' as signature pointer.
         :param instr_dict: list of dictionaries containing the various values necessary for the macro
         :type instr_dict: list
         :return: list of dictionaries containing the various values necessary for the macro
         '''
-        if self.opcode[0] == 'f' and 'fence' not in self.opcode:
-           offset = 0
-           val_offset = 0
-           hardcoded_regs = ['x15','x16','x17']
-           flag = True
-           for i in range(len(instr_dict)):
-                if 'swreg' not in instr_dict[i]:
-                    instr_dict[i]['swreg'] = 'x15'
-                    instr_dict[i]['valaddr_reg'] = 'x16'
-                    instr_dict[i]['flagreg'] = 'x17'
-                    if self.opcode in ['fsw','fsd']:
-                        if instr_dict[i]['rs1'] in hardcoded_regs:
-                            instr_dict[i]['swreg'] = 'x19'
-                            instr_dict[i]['valaddr_reg'] = 'x20'
-                            instr_dict[i]['flagreg'] = 'x21'
-                            if not flag:
-                                offset = 0
-                                flag = True
-                        elif flag:
-                            offset = 0
-                            flag = False
-                    elif instr_dict[i]['rs1'] in hardcoded_regs or instr_dict[i]['rd'] in hardcoded_regs:
-                        instr_dict[i]['swreg'] = 'x19'
-                        instr_dict[i]['valaddr_reg'] = 'x20'
-                        instr_dict[i]['flagreg'] = 'x21'
-                        if not flag:
-                            flag = True
-                            offset = 0
-                    elif flag:
-                        offset = 0
-                        flag = False
-                    instr_dict[i]['offset'] = str(offset)
-                    instr_dict[i]['val_offset'] = str(val_offset)
-                    offset += int((flen/8)+(xlen/8))
-                    if self.fmt == 'frformat' or self.fmt == 'rformat':
-                        val_offset += 2*(int(flen/8))
-                    elif self.fmt == 'fsrformat':
-                        val_offset += (int(flen/8))
-                    elif self.fmt == 'fr4format':
-                        val_offset += 3*(int(flen/8))
-                    if offset >= 2030:
-                        offset = 0
-                    if val_offset >= 2030:
-                        val_offset = 0
-           return instr_dict
+        # TODO: Clean this up and merge it with the code below to generalise adding val bases to
+        # generic macro templates.
 
         paired_regs=0
-        if xlen == 32 and 'p64_profile' in self.opnode:
+        if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
             paired_regs = self.opnode['p64_profile'].count('p')
 
-        regset = e_regset if 'e' in base_isa else default_regset
+        regset = e_regset if 'e' in self.base_isa else default_regset
         total_instr = len(instr_dict)
         available_reg = regset.copy()
         available_reg.remove('x0')
         count = 0
         assigned = 0
         offset = 0
+        stride = self.opnode['sig']['stride']
+        suffix = self.opnode['sig']['sz']
+        if flen in self.opnode:
+            FLEN = max(self.opnode['flen'])
+        else:
+            FLEN = 0
+        XLEN = max(self.opnode['xlen'])
+        SIGALIGN = max(XLEN,FLEN)/8
+        stride_sz = eval(suffix)
         for instr in instr_dict:
             if 'rs1' in instr and instr['rs1'] in available_reg:
                 available_reg.remove(instr['rs1'])
@@ -1021,19 +1031,19 @@ def swreg(self, instr_dict):
                 available_reg.remove(instr['rs2_hi'])
             if 'rd_hi' in instr and instr['rd_hi'] in available_reg:
                 available_reg.remove(instr['rd_hi'])
+            if 'testreg' in instr and instr['testreg'] in available_reg:
+                available_reg.remove(instr['testreg'])
 
-            if len(available_reg) <= 1+len(self.op_vars)+paired_regs:
+            if len(available_reg) <= 2+len(self.op_vars)+paired_regs:
                 curr_swreg = available_reg[0]
                 offset = 0
                 for i in range(assigned, count+1):
                     if 'swreg' not in instr_dict[i]:
-                        next_offset = offset + int(xlen/8)*self.stride
-                        if next_offset > 2048:
+                        instr_dict[i]['offset'] = str(offset) + '*' + suffix
+                        offset += stride
+                        if offset*stride_sz > 2047:
                             offset = 0
-                            next_offset = 0
                         instr_dict[i]['swreg'] = curr_swreg
-                        instr_dict[i]['offset'] = str(offset)
-                        offset = next_offset
                         assigned += 1
                 available_reg = regset.copy()
                 available_reg.remove('x0')
@@ -1043,13 +1053,11 @@ def swreg(self, instr_dict):
             offset = 0
             for i in range(len(instr_dict)):
                 if 'swreg' not in instr_dict[i]:
-                    next_offset = offset + int(xlen/8)*self.stride
-                    if next_offset > 2048:
+                    instr_dict[i]['offset'] = str(offset) + '*' + suffix
+                    offset += stride
+                    if offset*stride_sz > 2047:
                         offset = 0
-                        next_offset = 0
                     instr_dict[i]['swreg'] = curr_swreg
-                    instr_dict[i]['offset'] = str(offset)
-                    offset = next_offset
         return instr_dict
 
     def testreg(self, instr_dict):
@@ -1068,17 +1076,7 @@ def testreg(self, instr_dict):
         :type instr_dict: list
         :return: list of dictionaries containing the various values necessary for the macro
         '''
-        if self.opcode[0] == 'f' and 'fence' not in self.opcode:
-            for i in range(len(instr_dict)):
-                instr_dict[i]['testreg'] = 'x18'
-                if self.opcode in ['fsw','fsd']:
-                    if instr_dict[i]['rs1'] == 'x18':
-                        instr_dict[i]['testreg'] = 'x22'
-                elif instr_dict[i]['rs1'] == 'x18' or instr_dict[i]['rd'] == 'x18':
-                    instr_dict[i]['testreg'] = 'x22'
-            return instr_dict
-
-        regset = e_regset if 'e' in base_isa else default_regset
+        regset = e_regset if 'e' in self.base_isa else default_regset
         total_instr = len(instr_dict)
         available_reg = regset.copy()
         available_reg.remove('x0')
@@ -1086,7 +1084,7 @@ def testreg(self, instr_dict):
         assigned = 0
 
         paired_regs=0
-        if xlen == 32 and 'p64_profile' in self.opnode:
+        if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
             paired_regs = p64_profile.count('p')
 
@@ -1106,7 +1104,7 @@ def testreg(self, instr_dict):
             if 'swreg' in instr and instr['swreg'] in available_reg:
                 available_reg.remove(instr['swreg'])
 
-            if len(available_reg) <= 1+len(self.op_vars)+paired_regs:
+            if len(available_reg) <= 2+len(self.op_vars)+paired_regs:
                 curr_testreg = available_reg[0]
                 for i in range(assigned, count+1):
                     if 'testreg' not in instr_dict[i]:
@@ -1136,7 +1134,7 @@ def correct_val(self,instr_dict):
             for i in range(len(instr_dict)):
                 instr_dict[i]['correctval'] = '0'
             return instr_dict
-        if xlen == 32 and 'p64_profile' in self.opnode:
+        if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
             if len(p64_profile) >= 3 and p64_profile[0]=='p':
                 for i in range(len(instr_dict)):
@@ -1153,7 +1151,7 @@ def correct_val(self,instr_dict):
                 instr_dict[i]['correctval'] = str(normalise(correctval,instr_dict[i]))
         else:
             for i in range(len(instr_dict)):
-                instr_dict[i]['correctval'] = '0x' + '0'.zfill(int(xlen/4))
+                instr_dict[i]['correctval'] = '0x' + '0'.zfill(int(self.xlen/4))
         return instr_dict
 
     def reformat_instr(self, instr_dict):
@@ -1166,7 +1164,7 @@ def reformat_instr(self, instr_dict):
         '''
         if any('IP' in isa for isa in self.opnode['isa']):
             # instr_dict is already in the desired format for instructions that perform SIMD operations, or Zpsfoperand instructions in RV32.
-            if 'bit_width' in self.opnode or (xlen == 32 and 'p64_profile' in self.opnode):
+            if 'bit_width' in self.opnode or (self.xlen == 32 and 'p64_profile' in self.opnode):
                 return instr_dict
 
         for i in range(len(instr_dict)):
@@ -1181,10 +1179,11 @@ def reformat_instr(self, instr_dict):
                 #         size = '>Q'
                 #     else:
                 #         size = '>q'
-                if 'val' in field and field != 'correctval' and field != 'valaddr_reg' and field != 'val_offset':
+                if 'val' in field and field != 'correctval' and field != 'valaddr_reg' and \
+                    field != 'val_section' and field != 'val_offset' and field != 'rm_val':
                     value = instr_dict[i][field]
                     if '0x' in value:
-                        value = '0x' + value[2:].zfill(int(xlen/4))
+                        value = '0x' + value[2:].zfill(int(self.xlen/4))
                         value = struct.unpack(size, bytes.fromhex(value[2:]))[0]
                     else:
                         value = int(value)
@@ -1234,76 +1233,67 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str):
         '''
         regs = defaultdict(lambda: 0)
         sreg = instr_dict[0]['swreg']
-        vreg = 0
+        vreg = None
         code = []
         sign = [""]
         data = [".align 4","rvtest_data:",".word 0xbabecafe", \
                 ".word 0xabecafeb", ".word 0xbecafeba", ".word 0xecafebab"]
-        stride = self.stride
-        if self.opcode[0] == 'f' and 'fence' not in self.opcode:
-            vreg = instr_dict[0]['valaddr_reg']
-            k = 0
-            if self.opcode not in ['fsw','flw']:
-                data.append("test_fp:")
+        stride = self.opnode['sig']['stride']
+        if self.is_fext:
             code.append("RVTEST_FP_ENABLE()")
 
         if any('IP' in isa for isa in self.opnode['isa']):
             code.append("RVTEST_VXSAT_ENABLE()")
 
-        if xlen == 32 and 'p64_profile' in self.opnode:
+        if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
 
         n = 0
+        is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']])
+        src_len = xlen if self.opcode.endswith('.x') else (32 if 'w' in self.opcode else 64)
+        sz = 'word' if src_len == 32 else 'dword'
         opcode = instr_dict[0]['inst']
         op_node_isa = ""
         extension = ""
-        rvxlen = "RV"+str(xlen)
-        op_node_isa = ",".join([rvxlen + isa for isa in op_node['isa']])
-        op_node_isa = op_node_isa.replace("I","E") if 'e' in base_isa else op_node_isa
+        xlens = [self.xlen] + \
+            (list(filter(lambda x: x>self.xlen,self.opnode['xlen'])) if self.is_fext else [])
+        for val in xlens:
+            rvxlen = "RV"+str(val)
+            op_node_isa += ((","  if op_node_isa else "") \
+                    + ",".join([rvxlen + isa for isa in op_node['isa']]))
+        op_node_isa = op_node_isa.replace("I","E") if 'e' in self.base_isa else op_node_isa
         extension = op_node_isa.replace('I',"").replace('E',"")
         count = 0
         neg_offset = 0
+        width = self.iflen if not self.is_nan_box else self.flen
+        dset_n = 0
+        sig_sz = '(({0})/4)'.format(self.opnode['sig']['sz'])
+        cond_prefix = '' if self.is_fext else 'check ISA:=regex(.*{0}.*);'.format(self.xlen)
         for instr in instr_dict:
+            switch = False
             res = '\ninst_{0}:'.format(str(count))
             res += Template(op_node['template']).safe_substitute(instr)
-            if self.opcode[0] == 'f' and 'fence' not in self.opcode:
-                if self.fmt == 'frformat' or self.fmt == 'rformat':
-                    if flen == 32:
-                        data.append(".word "+instr["rs1_val"])
-                        data.append(".word "+instr["rs2_val"])
-                    elif flen == 64:
-                        data.append(".dword "+instr["rs1_val"])
-                        data.append(".dword "+instr["rs2_val"])
-                elif self.fmt == 'fsrformat':
-                    if flen == 32:
-                        data.append(".word "+instr["rs1_val"])
-                    elif flen == 64:
-                        data.append(".dword "+instr["rs1_val"])
-                elif self.fmt == 'fr4format':
-                    if flen == 32:
-                        data.append(".word "+instr["rs1_val"])
-                        data.append(".word "+instr["rs2_val"])
-                        data.append(".word "+instr["rs3_val"])
-                    elif flen == 64:
-                        data.append(".dword "+instr["rs1_val"])
-                        data.append(".dword "+instr["rs2_val"])
-                        data.append(".dword "+instr["rs3_val"])
-                if self.opcode not in ['fsw','flw']:
-                    if instr['val_offset'] == '0' and k == 0:
-                        code.append("RVTEST_VALBASEUPD("+vreg+",test_fp)")
-                        k = 1;
-                    elif instr['val_offset'] == '0' and k!= 0:
-                        if instr['inst'] in three_operand_dinstructions + three_operand_finstructions:
-                            code.append("addi "+vreg+","+vreg+","+str(2040))
-                        elif instr['inst'] in one_operand_dinstructions + two_operand_dinstructions + one_operand_finstructions + two_operand_finstructions:
-                            code.append("addi "+vreg+","+vreg+","+str(2032))
-                        else:
-                            code.append("RVTEST_VALBASEUPD("+vreg+")")
-                    if instr['valaddr_reg'] != vreg:
-                        code.append("RVTEST_VALBASEMOV("+instr['valaddr_reg']+", "+vreg+")")
-                        vreg = instr['valaddr_reg']
-            if instr['swreg'] != sreg or instr['offset'] == '0':
-                sign.append(signode_template.substitute({'n':n,'label':"signature_"+sreg+"_"+str(regs[sreg])}))
+            if 'val' in self.opnode:
+                if eval(instr['val_offset'],{},
+                        {'FLEN':width,'XLEN':self.xlen,'SIGALIGN':max(self.xlen,self.flen)/8}
+                        ) == 0 or instr['valaddr_reg'] != vreg:
+                    dlabel = 'test_dataset_'+str(dset_n)
+                    dset_n += 1
+                    data.append(dlabel+":")
+                    vreg = instr['valaddr_reg']
+                    code.append("RVTEST_VALBASEUPD("+vreg+","+dlabel+")")
+                # for i in range(1,num_vars+1):
+                #     dval = ()
+                #     if self.is_nan_box:
+                #         dval = nan_box(instr['rs{0}_nan_prefix'.format(i)],
+                #                 instr['rs{0}_val'.format(i)],self.flen,self.iflen)
+                #     else:
+                #         dval = (instr['rs{0}_val'.format(i)],self.iflen)
+                data.extend(instr['val_section'])
+            if instr['swreg'] != sreg or eval(instr['offset'],{},
+                        {'FLEN':width,'XLEN':self.xlen,'SIGALIGN':max(self.xlen,self.flen)/8}) == 0:
+                sign.append(signode_template.substitute(
+                    {'n':n,'label':"signature_"+sreg+"_"+str(regs[sreg]),'sz':sig_sz}))
                 n = stride
                 regs[sreg]+=1
                 sreg = instr['swreg']
@@ -1312,10 +1302,13 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str):
                 n+=stride
             code.append(res)
             count = count + 1
-        case_str = ''.join([case_template.safe_substitute(xlen=xlen,num=i,cond=cond,cov_label=label) for i,cond in enumerate(node['config'])])
-        sign.append(signode_template.substitute({'n':n,'label':"signature_"+sreg+"_"+str(regs[sreg])}))
+        case_str = ''.join([case_template.safe_substitute(xlen=self.xlen,num=i,cond=cond,cov_label=label) for i,cond in enumerate(node['config'])])
+        sign.append(signode_template.substitute({'n':n,
+                'label':"signature_"+sreg+"_"+str(regs[sreg]),'sz':sig_sz}))
         test = part_template.safe_substitute(case_str=case_str,code='\n'.join(code))
-        sign.append("#ifdef rvtest_mtrap_routine\n"+signode_template.substitute({'n':64,'label':"mtrap_sigptr"})+"\n#endif\n")
-        sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute({'n':32,'label':"gpr_save"})+"\n#endif\n")
+        sign.append("#ifdef rvtest_mtrap_routine\n"+signode_template.substitute(
+            {'n':64,'label':"mtrap_sigptr",'sz':'XLEN/32'})+"\n#endif\n")
+        sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute(
+            {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n")
         with open(file_name,"w") as fd:
             fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label))
diff --git a/riscv_ctg/helpers.py b/riscv_ctg/helpers.py
new file mode 100644
index 00000000..b080b0b6
--- /dev/null
+++ b/riscv_ctg/helpers.py
@@ -0,0 +1,76 @@
+import re
+
+class ExtractException(Exception):
+    pass
+
+num_dict = {
+        'rs1_val': '1',
+        'rs2_val': '2',
+        'rs3_val': '3',
+}
+fsub_vars = ['fe','fm','fs']
+
+val_regex = "{0}\s*==\s*(?P<{1}>[0-9abcdefx+\-\*/\|\&]*)\s*"
+
+def to_int(x):
+    if '0x' in x:
+        return int(x,16)
+    else:
+        return int(x)
+
+def nan_box(prefix,rs,flen,iflen):
+    if prefix == 2**(flen-iflen)-1:
+        return (rs,iflen)
+    else:
+        return (str(to_int(rs)|(to_int(prefix)<<iflen)),flen)
+
+def extract_frs_fields(reg,cvp,iflen):
+    if (iflen == 32):
+        e_sz = 8
+        m_sz = 23
+    else:
+        e_sz = 11
+        m_sz = 52
+    s_sz_string = '{:01b}'
+    e_sz_string = '{:0'+str(e_sz)+'b}'
+    m_sz_string = '{:0'+str(m_sz)+'b}'
+    size_string = '{:0'+str(int(iflen/4))+'x}'
+    fvals = {}
+    for var in fsub_vars:
+        regex = val_regex.format(var+reg,var+reg)
+        match_obj = re.search(regex,cvp)
+        if match_obj is not None:
+            fvals[var+reg] = eval(match_obj.group(var+reg))
+        else:
+            raise ExtractException("{0} not defined in coverpoint:{1}".format(var+reg,cvp))
+    bin_val1 = s_sz_string.format(fvals['fs'+reg]) + e_sz_string.format(fvals['fe'+reg]) \
+            + m_sz_string.format(fvals['fm'+reg])
+    hex_val1 = '0x' + size_string.format(int(bin_val1, 2))
+    return int(hex_val1,16)
+
+def merge_fields_f(val_vars,cvp,flen,iflen,merge):
+    nan_box = False
+    if flen > iflen:
+        nan_box = True
+    fdict = {}
+    for var in val_vars:
+        if var in num_dict and merge:
+            fdict[var] = extract_frs_fields(num_dict[var],cvp,iflen)
+            if nan_box:
+                nan_var = 'rs{0}_nan_prefix'.format(num_dict[var])
+                regex = val_regex.format(nan_var.replace("_","\\_"),nan_var)
+                match_obj = re.search(regex,cvp)
+                if match_obj is not None:
+                    fdict[nan_var] = eval(match_obj.group(nan_var))
+                else:
+                    fdict[nan_var] = (2**(flen-iflen))-1
+        else:
+            regex = val_regex.format(var.replace("_","\\_"),var)
+            match_obj = re.search(regex,cvp)
+            if match_obj is not None:
+                fdict[var] = eval(match_obj.group(var))
+            elif 'nan_prefix' not in var:
+                raise ExtractException("{0} not defined in coverpoint:{1}".format(var,cvp))
+    return fdict
+
+
diff --git a/riscv_ctg/main.py b/riscv_ctg/main.py
index 71dd1efe..b127689b 100644
--- a/riscv_ctg/main.py
+++ b/riscv_ctg/main.py
@@ -16,12 +16,14 @@
 @click.option('--cgf','-cf',multiple=True,type=click.Path(exists=True,resolve_path=True,readable=True),help="Path to the cgf file(s). Multiple allowed.")
 @click.option('--procs','-p',type=int,default=1,help='Max number of processes to spawn')
 @click.option('--base-isa','-bi',type=click.Choice(['rv32e','rv32i','rv64i']),help="Base ISA string for the tests.")
+@click.option('--flen','-fl',type=click.Choice(['32','64','0']),help="Value of FLEN in\
+        hardware.",default='0')
 @click.option("--inst",type=int,help="Maximum number of Macro Instances per test.")
-def cli(verbose, out_dir, randomize , cgf,procs,base_isa,inst):
+def cli(verbose, out_dir, randomize , cgf,procs,base_isa, flen,inst):
     if not os.path.exists(out_dir):
         os.mkdir(out_dir)
     if '32' in base_isa:
         xlen = 32
     elif '64' in base_isa:
         xlen = 64
-    ctg(verbose, out_dir, randomize ,xlen, cgf,procs,base_isa,inst)
+    ctg(verbose, out_dir, randomize ,xlen, int(flen), cgf,procs,base_isa,inst)
diff --git a/riscv_ctg/requirements.txt b/riscv_ctg/requirements.txt
index c838459c..af94a163 100644
--- a/riscv_ctg/requirements.txt
+++ b/riscv_ctg/requirements.txt
@@ -2,4 +2,4 @@ click
 ruamel.yaml>=0.16.0
 colorlog
 python-constraint
-riscv_isac
+riscv_isac>=0.14.0
diff --git a/riscv_ctg/utils.py b/riscv_ctg/utils.py
index 10949799..94abc2db 100644
--- a/riscv_ctg/utils.py
+++ b/riscv_ctg/utils.py
@@ -8,6 +8,7 @@
 from riscv_ctg.log import logger
 import ruamel
 from ruamel.yaml import YAML
+from riscv_isac.utils import combineReader
 
 yaml = YAML(typ="rt")
 yaml.default_flow_style = False
@@ -23,6 +24,10 @@ def load_yaml(foo):
         logger.error(error)
         raise SystemExit
 
+def load_yamls(foo):
+    with combineReader(foo) as fp:
+        return dict(yaml.load(fp))
+
 class makeUtil():
     """
     Utility for ease of use of make commands like `make` and `pmake`.
@@ -309,7 +314,7 @@ def sys_command(command):
 def sys_command_file(command, filename):
     cmd = command.split(' ')
     cmd = [x.strip(' ') for x in cmd]
-    cmd = [i for i in cmd if i] 
+    cmd = [i for i in cmd if i]
     logger.debug('{0} > {1}'.format(' '.join(cmd), filename))
     fp = open(filename, 'w')
     out = subprocess.Popen(cmd, stdout=fp, stderr=fp)
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf
similarity index 66%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fadd.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf
index 988309d1..fd1092a3 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fadd.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fadd.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fadd_b1:
+fadd.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fadd_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fadd.d", 2)': 0
+        'ibm_b1(flen,64, "fadd.d", 2)': 0
         
-fadd_b2:
+fadd.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fadd_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fadd.d", 2)': 0
+        'ibm_b2(flen,64, "fadd.d", 2)': 0
         
-fadd_b3:
+fadd.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fadd_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fadd.d", 2)': 0
+        'ibm_b3(flen,64, "fadd.d", 2)': 0
         
-fadd_b4:
+fadd.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fadd_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fadd.d", 2)': 0
+        'ibm_b4(flen,64, "fadd.d", 2)': 0
         
-fadd_b5:
+fadd.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fadd_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fadd.d", 2)': 0
+        'ibm_b5(flen,64, "fadd.d", 2)': 0
         
-fadd_b7:
+fadd.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fadd_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fadd.d", 2)': 0
+        'ibm_b7(flen,64, "fadd.d", 2)': 0
         
-fadd_b8:
+fadd.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fadd_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fadd.d", 2)': 0
+        'ibm_b8(flen,64, "fadd.d", 2)': 0
         
-fadd_b10:
+fadd.d_b10:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fadd_b10:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b10(64, "fadd.d", 2)': 0
+        'ibm_b10(flen,64, "fadd.d", 2)': 0
         
-fadd_b11:
+fadd.d_b11:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -151,12 +151,12 @@ fadd_b11:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b11(64, "fadd.d", 2)': 0
+        'ibm_b11(flen,64, "fadd.d", 2)': 0
         
-fadd_b12:
+fadd.d_b12:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -168,12 +168,12 @@ fadd_b12:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b12(64, "fadd.d", 2)': 0
+        'ibm_b12(flen,64, "fadd.d", 2)': 0
         
-fadd_b13:
+fadd.d_b13:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -185,4 +185,4 @@ fadd_b13:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b13(64, "fadd.d", 2)': 0
+        'ibm_b13(flen,64, "fadd.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fclass.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fclass.d.cgf
similarity index 70%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fclass.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fclass.d.cgf
index 9649b394..a400d6d8 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fclass.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fclass.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fclass_b1:
+fclass.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fclass.d: 0
     rs1: 
       <<: *all_fregs
@@ -11,5 +11,5 @@ fclass_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fclass.d", 1)': 0
+        'ibm_b1(flen,64, "fclass.d", 1)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.s.cgf
similarity index 67%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.s.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.s.cgf
index 2856444a..def774ab 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.s.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.s.cgf
@@ -2,8 +2,8 @@
 
 fcvt.d.s_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -13,12 +13,12 @@ fcvt.d.s_b1:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fcvt.d.s", 1)': 0
+        'ibm_b1(flen,32, "fcvt.d.s", 1)': 0
         
 fcvt.d.s_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -28,12 +28,12 @@ fcvt.d.s_b22:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fcvt.d.s", 1)': 0
+        'ibm_b22(flen,32, "fcvt.d.s", 1)': 0
         
 fcvt.d.s_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -43,12 +43,12 @@ fcvt.d.s_b23:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fcvt.d.s", 1)': 0
+        'ibm_b23(flen,32, "fcvt.d.s", 1)': 0
         
 fcvt.d.s_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -58,12 +58,12 @@ fcvt.d.s_b24:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fcvt.d.s", 1)': 0
+        'ibm_b24(flen,32, "fcvt.d.s", 1)': 0
         
 fcvt.d.s_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -73,12 +73,12 @@ fcvt.d.s_b27:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fcvt.d.s", 1)': 0
+        'ibm_b27(flen,32, "fcvt.d.s", 1)': 0
         
 fcvt.d.s_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -88,12 +88,12 @@ fcvt.d.s_b28:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fcvt.d.s", 1)': 0
+        'ibm_b28(flen,32, "fcvt.d.s", 1)': 0
         
 fcvt.d.s_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.s: 0
     rs1: 
       <<: *all_fregs
@@ -103,4 +103,4 @@ fcvt.d.s_b29:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fcvt.d.s", 1)': 0
+        'ibm_b29(flen,32, "fcvt.d.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.w.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.w.cgf
similarity index 75%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.w.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.w.cgf
index b8013591..2dcf295f 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.w.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.w.cgf
@@ -2,8 +2,8 @@
       
 fcvt.d.w_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.w: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.d.w_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fcvt.d.w", 1)': 0
+        'ibm_b25(flen,32, "fcvt.d.w", 1)': 0
         
 fcvt.d.w_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.w: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.wu.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.wu.cgf
similarity index 75%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.wu.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.wu.cgf
index a6f2a893..0f9ed15c 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.wu.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.d.wu.cgf
@@ -2,8 +2,8 @@
       
 fcvt.d.wu_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.wu: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.d.wu_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fcvt.d.wu", 1)': 0
+        'ibm_b25(flen,32, "fcvt.d.wu", 1)': 0
         
 fcvt.d.wu_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.d.wu: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.s.d.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.s.d.cgf
similarity index 67%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.s.d.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fcvt.s.d.cgf
index 1452bee2..9d87ab7b 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.s.d.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.s.d.cgf
@@ -2,8 +2,8 @@
 
 fcvt.s.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -13,12 +13,12 @@ fcvt.s.d_b1:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fcvt.s.d", 1)': 0
+        'ibm_b1(flen,64, "fcvt.s.d", 1)': 0
         
 fcvt.s.d_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -28,12 +28,12 @@ fcvt.s.d_b22:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fcvt.s.d", 1)': 0
+        'ibm_b22(flen,64, "fcvt.s.d", 1)': 0
         
 fcvt.s.d_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -43,12 +43,12 @@ fcvt.s.d_b23:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fcvt.s.d", 1)': 0
+        'ibm_b23(flen,64, "fcvt.s.d", 1)': 0
         
 fcvt.s.d_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -58,12 +58,12 @@ fcvt.s.d_b24:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fcvt.s.d", 1)': 0
+        'ibm_b24(flen,64, "fcvt.s.d", 1)': 0
         
 fcvt.s.d_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -73,12 +73,12 @@ fcvt.s.d_b27:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fcvt.s.d", 1)': 0
+        'ibm_b27(flen,64, "fcvt.s.d", 1)': 0
         
 fcvt.s.d_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -88,12 +88,12 @@ fcvt.s.d_b28:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fcvt.s.d", 1)': 0
+        'ibm_b28(flen,64, "fcvt.s.d", 1)': 0
         
 fcvt.s.d_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.s.d: 0
     rs1: 
       <<: *all_fregs
@@ -103,4 +103,4 @@ fcvt.s.d_b29:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fcvt.s.d", 1)': 0
+        'ibm_b29(flen,64, "fcvt.s.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.w.d.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.w.d.cgf
similarity index 63%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.w.d.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fcvt.w.d.cgf
index 617e053c..dc81adfa 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.w.d.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.w.d.cgf
@@ -2,8 +2,8 @@
 
 fcvt.w.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.w.d_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fcvt.w.d", 1)': 0
+        'ibm_b1(flen,64, "fcvt.w.d", 1)': 0
         
 fcvt.w.d_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.w.d_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fcvt.w.d", 1)': 0
+        'ibm_b22(flen,64, "fcvt.w.d", 1)': 0
         
 fcvt.w.d_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.w.d_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fcvt.w.d", 1)': 0
+        'ibm_b23(flen,64, "fcvt.w.d", 1)': 0
         
 fcvt.w.d_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.w.d_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fcvt.w.d", 1)': 0
+        'ibm_b24(flen,64, "fcvt.w.d", 1)': 0
         
 fcvt.w.d_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.w.d_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fcvt.w.d", 1)': 0
+        'ibm_b27(flen,64, "fcvt.w.d", 1)': 0
         
 fcvt.w.d_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.w.d_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fcvt.w.d", 1)': 0
+        'ibm_b28(flen,64, "fcvt.w.d", 1)': 0
         
 fcvt.w.d_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.w.d: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.w.d_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fcvt.w.d", 1)': 0
+        'ibm_b29(flen,64, "fcvt.w.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.wu.d.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.wu.d.cgf
similarity index 63%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.wu.d.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fcvt.wu.d.cgf
index f9687954..dacb2e39 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.wu.d.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fcvt.wu.d.cgf
@@ -2,8 +2,8 @@
 
 fcvt.wu.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.wu.d_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fcvt.wu.d", 1)': 0
+        'ibm_b1(flen,64, "fcvt.wu.d", 1)': 0
         
 fcvt.wu.d_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.wu.d_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fcvt.wu.d", 1)': 0
+        'ibm_b22(flen,64, "fcvt.wu.d", 1)': 0
         
 fcvt.wu.d_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.wu.d_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fcvt.wu.d", 1)': 0
+        'ibm_b23(flen,64, "fcvt.wu.d", 1)': 0
         
 fcvt.wu.d_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.wu.d_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fcvt.wu.d", 1)': 0
+        'ibm_b24(flen,64, "fcvt.wu.d", 1)': 0
         
 fcvt.wu.d_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.wu.d_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fcvt.wu.d", 1)': 0
+        'ibm_b27(flen,64, "fcvt.wu.d", 1)': 0
         
 fcvt.wu.d_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.wu.d_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fcvt.wu.d", 1)': 0
+        'ibm_b28(flen,64, "fcvt.wu.d", 1)': 0
         
 fcvt.wu.d_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fcvt.wu.d: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.wu.d_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fcvt.wu.d", 1)': 0
+        'ibm_b29(flen,64, "fcvt.wu.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fdiv.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fdiv.d.cgf
similarity index 66%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fdiv.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fdiv.d.cgf
index 6c586b00..d1e37d83 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fdiv.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fdiv.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fdiv_b1:
+fdiv.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fdiv_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fdiv.d", 2)': 0
+        'ibm_b1(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b2:
+fdiv.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fdiv_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fdiv.d", 2)': 0
+        'ibm_b2(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b3:
+fdiv.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fdiv_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fdiv.d", 2)': 0
+        'ibm_b3(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b4:
+fdiv.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fdiv_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fdiv.d", 2)': 0
+        'ibm_b4(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b5:
+fdiv.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fdiv_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fdiv.d", 2)': 0
+        'ibm_b5(flen,64, "fdiv.d", 2)': 0
 
-fdiv_b6:
+fdiv.d_b6:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fdiv_b6:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(64, "fdiv.d", 2)': 0
+        'ibm_b6(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b7:
+fdiv.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fdiv_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fdiv.d", 2)': 0
+        'ibm_b7(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b8:
+fdiv.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fdiv_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fdiv.d", 2)': 0
+        'ibm_b8(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b9:
+fdiv.d_b9:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -151,12 +151,12 @@ fdiv_b9:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b9(64, "fdiv.d", 2)': 0
+        'ibm_b9(flen,64, "fdiv.d", 2)': 0
 
-fdiv_b20:
+fdiv.d_b20:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -168,12 +168,12 @@ fdiv_b20:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b20(64, "fdiv.d", 2)': 0
+        'ibm_b20(flen,64, "fdiv.d", 2)': 0
         
-fdiv_b21:
+fdiv.d_b21:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fdiv.d: 0
     rs1: 
       <<: *all_fregs
@@ -185,4 +185,4 @@ fdiv_b21:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b21(64, "fdiv.d", 2)': 0
+        'ibm_b21(flen,64, "fdiv.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_feq.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/feq.d.cgf
similarity index 71%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_feq.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/feq.d.cgf
index f26e1083..9d86e46f 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_feq.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/feq.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-feq_b1:
+feq.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       feq.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ feq_b1:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "feq.d", 2)': 0
+        'ibm_b1(flen,64, "feq.d", 2)': 0
         
-feq_b19:
+feq.d_b19:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       feq.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ feq_b19:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(64, "feq.d", 2)': 0
+        'ibm_b19(flen,64, "feq.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf
new file mode 100644
index 00000000..8ddbe633
--- /dev/null
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf
@@ -0,0 +1,23 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fld-align:
+    config: 
+      - check ISA:=regex(.*D.*)
+    mnemonics: 
+      fld: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_fregs
+    val_comb:
+        'ea_align == 0 and (imm_val % 8) == 0 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 1 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 2 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 3 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 4 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 5 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 6 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 7 and fcsr == 0': 0
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val < 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fle.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fle.d.cgf
similarity index 71%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fle.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fle.d.cgf
index 9ee4a45f..d5a6e764 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fle.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fle.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fle_b1:
+fle.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fle.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fle_b1:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fle.d", 2)': 0
+        'ibm_b1(flen,64, "fle.d", 2)': 0
         
-fle_b19:
+fle.d_b19:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fle.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ fle_b19:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(64, "fle.d", 2)': 0
+        'ibm_b19(flen,64, "fle.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_flt.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/flt.d.cgf
similarity index 71%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_flt.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/flt.d.cgf
index 2124b404..f350b32e 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_flt.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/flt.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-flt_b1:
+flt.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       flt.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ flt_b1:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "flt.d", 2)': 0
+        'ibm_b1(flen,64, "flt.d", 2)': 0
         
-flt_b19:
+flt.d_b19:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       flt.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ flt_b19:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(64, "flt.d", 2)': 0
+        'ibm_b19(flen,64, "flt.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fmadd.d.cgf
similarity index 69%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmadd.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fmadd.d.cgf
index 84ab80e8..a9a49cfb 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmadd.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fmadd.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fmadd_b1:
+fmadd.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fmadd_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fmadd.d", 3)': 0
+        'ibm_b1(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b2:
+fmadd.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fmadd_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fmadd.d", 3)': 0
+        'ibm_b2(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b3:
+fmadd.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fmadd_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fmadd.d", 3)': 0
+        'ibm_b3(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b4:
+fmadd.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fmadd_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fmadd.d", 3)': 0
+        'ibm_b4(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b5:
+fmadd.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fmadd_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fmadd.d", 3)': 0
+        'ibm_b5(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b6:
+fmadd.d_b6:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fmadd_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(64, "fmadd.d", 3)': 0
+        'ibm_b6(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b7:
+fmadd.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fmadd_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fmadd.d", 3)': 0
+        'ibm_b7(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b8:
+fmadd.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fmadd_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fmadd.d", 3)': 0
+        'ibm_b8(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b14:
+fmadd.d_b14:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fmadd_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(64, "fmadd.d", 3)': 0
+        'ibm_b14(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b15:
+fmadd.d_b15:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fmadd_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(64, "fmadd.d", 3)': 0
+        'ibm_b15(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b16:
+fmadd.d_b16:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fmadd_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(64, "fmadd.d", 3)': 0
+        'ibm_b16(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b17:
+fmadd.d_b17:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fmadd_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(64, "fmadd.d", 3)': 0
+        'ibm_b17(flen,64, "fmadd.d", 3)': 0
         
-fmadd_b18:
+fmadd.d_b18:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fmadd_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(64, "fmadd.d", 3)': 0
+        'ibm_b18(flen,64, "fmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmax.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fmax.d.cgf
similarity index 70%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmax.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fmax.d.cgf
index 0e87171b..73633a2f 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmax.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fmax.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fmax_b1:
+fmax.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmax.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fmax_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fmax.d", 2)': 0
+        'ibm_b1(flen,64, "fmax.d", 2)': 0
         
-fmax_b19:
+fmax.d_b19:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmax.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ fmax_b19:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(64, "fmax.d", 2)': 0
+        'ibm_b19(flen,64, "fmax.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmin.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fmin.d.cgf
similarity index 70%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmin.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fmin.d.cgf
index e63f9f09..df0a710e 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmin.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fmin.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fmin_b1:
+fmin.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmin.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fmin_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fmin.d", 2)': 0
+        'ibm_b1(flen,64, "fmin.d", 2)': 0
         
-fmin_b19:
+fmin.d_b19:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmin.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ fmin_b19:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(64, "fmin.d", 2)': 0
+        'ibm_b19(flen,64, "fmin.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fmsub.d.cgf
similarity index 69%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmsub.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fmsub.d.cgf
index 65dbbbab..7f734f8f 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmsub.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fmsub.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fmsub_b1:
+fmsub.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fmsub_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fmsub.d", 3)': 0
+        'ibm_b1(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b2:
+fmsub.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fmsub_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fmsub.d", 3)': 0
+        'ibm_b2(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b3:
+fmsub.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fmsub_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fmsub.d", 3)': 0
+        'ibm_b3(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b4:
+fmsub.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fmsub_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fmsub.d", 3)': 0
+        'ibm_b4(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b5:
+fmsub.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fmsub_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fmsub.d", 3)': 0
+        'ibm_b5(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b6:
+fmsub.d_b6:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fmsub_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(64, "fmsub.d", 3)': 0
+        'ibm_b6(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b7:
+fmsub.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fmsub_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fmsub.d", 3)': 0
+        'ibm_b7(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b8:
+fmsub.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fmsub_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fmsub.d", 3)': 0
+        'ibm_b8(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b14:
+fmsub.d_b14:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fmsub_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(64, "fmsub.d", 3)': 0
+        'ibm_b14(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b15:
+fmsub.d_b15:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fmsub_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(64, "fmsub.d", 3)': 0
+        'ibm_b15(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b16:
+fmsub.d_b16:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fmsub_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(64, "fmsub.d", 3)': 0
+        'ibm_b16(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b17:
+fmsub.d_b17:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fmsub_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(64, "fmsub.d", 3)': 0
+        'ibm_b17(flen,64, "fmsub.d", 3)': 0
         
-fmsub_b18:
+fmsub.d_b18:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fmsub_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(64, "fmsub.d", 3)': 0
+        'ibm_b18(flen,64, "fmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmul.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fmul.d.cgf
similarity index 67%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmul.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fmul.d.cgf
index 9842326c..48db171f 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmul.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fmul.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fmul_b1:
+fmul.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fmul_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fmul.d", 2)': 0
+        'ibm_b1(flen,64, "fmul.d", 2)': 0
         
-fmul_b2:
+fmul.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fmul_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fmul.d", 2)': 0
+        'ibm_b2(flen,64, "fmul.d", 2)': 0
         
-fmul_b3:
+fmul.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fmul_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fmul.d", 2)': 0
+        'ibm_b3(flen,64, "fmul.d", 2)': 0
         
-fmul_b4:
+fmul.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fmul_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fmul.d", 2)': 0
+        'ibm_b4(flen,64, "fmul.d", 2)': 0
         
-fmul_b5:
+fmul.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fmul_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fmul.d", 2)': 0
+        'ibm_b5(flen,64, "fmul.d", 2)': 0
 
-fmul_b6:
+fmul.d_b6:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fmul_b6:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(64, "fmul.d", 2)': 0
+        'ibm_b6(flen,64, "fmul.d", 2)': 0
         
-fmul_b7:
+fmul.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fmul_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fmul.d", 2)': 0
+        'ibm_b7(flen,64, "fmul.d", 2)': 0
         
-fmul_b8:
+fmul.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fmul_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fmul.d", 2)': 0
+        'ibm_b8(flen,64, "fmul.d", 2)': 0
         
-fmul_b9:
+fmul.d_b9:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fmul.d: 0
     rs1: 
       <<: *all_fregs
@@ -151,5 +151,5 @@ fmul_b9:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b9(64, "fmul.d", 2)': 0
+        'ibm_b9(flen,64, "fmul.d", 2)': 0
 
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fnmadd.d.cgf
similarity index 69%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmadd.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fnmadd.d.cgf
index 73777070..192d998c 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmadd.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fnmadd.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fnmadd_b1:
+fnmadd.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fnmadd_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fnmadd.d", 3)': 0
+        'ibm_b1(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b2:
+fnmadd.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fnmadd_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fnmadd.d", 3)': 0
+        'ibm_b2(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b3:
+fnmadd.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fnmadd_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fnmadd.d", 3)': 0
+        'ibm_b3(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b4:
+fnmadd.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fnmadd_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fnmadd.d", 3)': 0
+        'ibm_b4(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b5:
+fnmadd.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fnmadd_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fnmadd.d", 3)': 0
+        'ibm_b5(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b6:
+fnmadd.d_b6:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fnmadd_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(64, "fnmadd.d", 3)': 0
+        'ibm_b6(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b7:
+fnmadd.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fnmadd_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fnmadd.d", 3)': 0
+        'ibm_b7(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b8:
+fnmadd.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fnmadd_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fnmadd.d", 3)': 0
+        'ibm_b8(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b14:
+fnmadd.d_b14:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fnmadd_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(64, "fnmadd.d", 3)': 0
+        'ibm_b14(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b15:
+fnmadd.d_b15:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fnmadd_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(64, "fnmadd.d", 3)': 0
+        'ibm_b15(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b16:
+fnmadd.d_b16:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fnmadd_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(64, "fnmadd.d", 3)': 0
+        'ibm_b16(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b17:
+fnmadd.d_b17:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fnmadd_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(64, "fnmadd.d", 3)': 0
+        'ibm_b17(flen,64, "fnmadd.d", 3)': 0
         
-fnmadd_b18:
+fnmadd.d_b18:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmadd.d: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fnmadd_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(64, "fnmadd.d", 3)': 0
+        'ibm_b18(flen,64, "fnmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fnmsub.d.cgf
similarity index 69%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmsub.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fnmsub.d.cgf
index 3cd16329..5c8c2b6d 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmsub.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fnmsub.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fnmsub_b1:
+fnmsub.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fnmsub_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fnmsub.d", 3)': 0
+        'ibm_b1(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b2:
+fnmsub.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fnmsub_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fnmsub.d", 3)': 0
+        'ibm_b2(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b3:
+fnmsub.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fnmsub_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fnmsub.d", 3)': 0
+        'ibm_b3(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b4:
+fnmsub.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fnmsub_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fnmsub.d", 3)': 0
+        'ibm_b4(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b5:
+fnmsub.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fnmsub_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fnmsub.d", 3)': 0
+        'ibm_b5(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b6:
+fnmsub.d_b6:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fnmsub_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(64, "fnmsub.d", 3)': 0
+        'ibm_b6(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b7:
+fnmsub.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fnmsub_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fnmsub.d", 3)': 0
+        'ibm_b7(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b8:
+fnmsub.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fnmsub_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fnmsub.d", 3)': 0
+        'ibm_b8(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b14:
+fnmsub.d_b14:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fnmsub_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(64, "fnmsub.d", 3)': 0
+        'ibm_b14(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b15:
+fnmsub.d_b15:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fnmsub_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(64, "fnmsub.d", 3)': 0
+        'ibm_b15(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b16:
+fnmsub.d_b16:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fnmsub_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(64, "fnmsub.d", 3)': 0
+        'ibm_b16(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b17:
+fnmsub.d_b17:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fnmsub_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(64, "fnmsub.d", 3)': 0
+        'ibm_b17(flen,64, "fnmsub.d", 3)': 0
         
-fnmsub_b18:
+fnmsub.d_b18:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fnmsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fnmsub_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(64, "fnmsub.d", 3)': 0
+        'ibm_b18(flen,64, "fnmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf
new file mode 100644
index 00000000..4897723b
--- /dev/null
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf
@@ -0,0 +1,23 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fsd-align:
+    config: 
+      - check ISA:=regex(.*D.*)
+    mnemonics: 
+      fsd: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_fregs
+    val_comb:
+        'ea_align == 0 and (imm_val % 8) == 0 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 1 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 2 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 3 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 4 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 5 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 6 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 8) == 7 and fcsr == 0': 0
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val < 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnj.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf
similarity index 75%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnj.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf
index 1b45513c..c92ce150 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnj.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fsgnj.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fsgnj_b1:
+fsgnj.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsgnj.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,5 +15,5 @@ fsgnj_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fsgnj.d", 2)': 0
+        'ibm_b1(flen,64, "fsgnj.d", 2)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnjn.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjn.d.cgf
similarity index 74%
rename from sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnjn.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fsgnjn.d.cgf
index 134a8fc5..7eab86ec 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnjn.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjn.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fsgnjn_b1:
+fsgnjn.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsgnjn.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,5 +15,5 @@ fsgnjn_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fsgnjn.d", 2)': 0
+        'ibm_b1(flen,64, "fsgnjn.d", 2)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnjx.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjx.d.cgf
similarity index 74%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnjx.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fsgnjx.d.cgf
index 25cefb40..ba00bff1 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnjx.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fsgnjx.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fsgnjx_b1:
+fsgnjx.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsgnjx.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,5 +15,5 @@ fsgnjx_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fsgnjx.d", 2)': 0
+        'ibm_b1(flen,64, "fsgnjx.d", 2)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsqrt.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fsqrt.d.cgf
similarity index 62%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsqrt.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fsqrt.d.cgf
index 3a19dfb4..4c12d7bb 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsqrt.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fsqrt.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fsqrt_b1:
+fsqrt.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -13,12 +13,12 @@ fsqrt_b1:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fsqrt.d", 1)': 0
+        'ibm_b1(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b2:
+fsqrt.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -28,12 +28,12 @@ fsqrt_b2:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fsqrt.d", 1)': 0
+        'ibm_b2(flen,64, "fsqrt.d", 1)': 0
         
-fsqrt_b3:
+fsqrt.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -43,12 +43,12 @@ fsqrt_b3:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fsqrt.d", 1)': 0
+        'ibm_b3(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b4:
+fsqrt.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -58,12 +58,12 @@ fsqrt_b4:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fsqrt.d", 1)': 0
+        'ibm_b4(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b5:
+fsqrt.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -73,12 +73,12 @@ fsqrt_b5:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fsqrt.d", 1)': 0
+        'ibm_b5(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b7:
+fsqrt.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -88,12 +88,12 @@ fsqrt_b7:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fsqrt.d", 1)': 0
+        'ibm_b7(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b8:
+fsqrt.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -103,12 +103,12 @@ fsqrt_b8:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fsqrt.d", 1)': 0
+        'ibm_b8(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b9:
+fsqrt.d_b9:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -118,12 +118,12 @@ fsqrt_b9:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b9(64, "fsqrt.d", 1)': 0
+        'ibm_b9(flen,64, "fsqrt.d", 1)': 0
 
-fsqrt_b20:
+fsqrt.d_b20:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsqrt.d: 0
     rs1: 
       <<: *all_fregs
@@ -133,5 +133,5 @@ fsqrt_b20:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b20(64, "fsqrt.d", 1)': 0
+        'ibm_b20(flen,64, "fsqrt.d", 1)': 0
 
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/fsub.d.cgf
similarity index 66%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsub.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32D/fsub.d.cgf
index 76b4dfd6..df8a6f94 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsub.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32D/fsub.d.cgf
@@ -1,9 +1,9 @@
 # For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
 
-fsub_b1:
+fssub.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fsub_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fsub.d", 2)': 0
+        'ibm_b1(flen,64, "fsub.d", 2)': 0
         
-fsub_b2:
+fssub.d_b2:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fsub_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(64, "fsub.d", 2)': 0
+        'ibm_b2(flen,64, "fsub.d", 2)': 0
         
-fsub_b3:
+fssub.d_b3:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fsub_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(64, "fsub.d", 2)': 0
+        'ibm_b3(flen,64, "fsub.d", 2)': 0
         
-fsub_b4:
+fssub.d_b4:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fsub_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(64, "fsub.d", 2)': 0
+        'ibm_b4(flen,64, "fsub.d", 2)': 0
         
-fsub_b5:
+fssub.d_b5:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fsub_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(64, "fsub.d", 2)': 0
+        'ibm_b5(flen,64, "fsub.d", 2)': 0
         
-fsub_b7:
+fssub.d_b7:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fsub_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(64, "fsub.d", 2)': 0
+        'ibm_b7(flen,64, "fsub.d", 2)': 0
         
-fsub_b8:
+fssub.d_b8:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fsub_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(64, "fsub.d", 2)': 0
+        'ibm_b8(flen,64, "fsub.d", 2)': 0
         
-fsub_b10:
+fssub.d_b10:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fsub_b10:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b10(64, "fsub.d", 2)': 0
+        'ibm_b10(flen,64, "fsub.d", 2)': 0
         
-fsub_b11:
+fssub.d_b11:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -151,12 +151,12 @@ fsub_b11:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b11(64, "fsub.d", 2)': 0
+        'ibm_b11(flen,64, "fsub.d", 2)': 0
         
-fsub_b12:
+fssub.d_b12:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -168,12 +168,12 @@ fsub_b12:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b12(64, "fsub.d", 2)': 0
+        'ibm_b12(flen,64, "fsub.d", 2)': 0
         
-fsub_b13:
+fssub.d_b13:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*I.*D.*)
+    mnemonics: 
       fsub.d: 0
     rs1: 
       <<: *all_fregs
@@ -185,4 +185,4 @@ fsub_b13:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b13(64, "fsub.d", 2)': 0
+        'ibm_b13(flen,64, "fsub.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fclass.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fclass.cgf
deleted file mode 100644
index ddaf4fff..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fclass.cgf
+++ /dev/null
@@ -1,17 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fclass_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fclass.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fclass.d", 1)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.s.cgf
deleted file mode 100644
index e6244934..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.d.s.cgf
+++ /dev/null
@@ -1,106 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fcvt.d.s_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fcvt.d.s", 1)': 0
-        
-fcvt.d.s_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b22(32, "fcvt.d.s", 1)': 0
-        
-fcvt.d.s_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b23(32, "fcvt.d.s", 1)': 0
-        
-fcvt.d.s_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b24(32, "fcvt.d.s", 1)': 0
-        
-fcvt.d.s_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b27(32, "fcvt.d.s", 1)': 0
-        
-fcvt.d.s_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b28(32, "fcvt.d.s", 1)': 0
-        
-fcvt.d.s_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b29(32, "fcvt.d.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.w.d.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.w.d.cgf
deleted file mode 100644
index 617e053c..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fcvt.w.d.cgf
+++ /dev/null
@@ -1,92 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fcvt.w.d_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fcvt.w.d", 1)': 0
-        
-fcvt.w.d_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b22(64, "fcvt.w.d", 1)': 0
-        
-fcvt.w.d_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b23(64, "fcvt.w.d", 1)': 0
-        
-fcvt.w.d_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b24(64, "fcvt.w.d", 1)': 0
-        
-fcvt.w.d_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b27(64, "fcvt.w.d", 1)': 0
-        
-fcvt.w.d_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b28(64, "fcvt.w.d", 1)': 0
-        
-fcvt.w.d_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b29(64, "fcvt.w.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fdiv.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fdiv.cgf
deleted file mode 100644
index 6c586b00..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fdiv.cgf
+++ /dev/null
@@ -1,188 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fdiv_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fdiv.d", 2)': 0
-        
-fdiv_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fdiv.d", 2)': 0
-        
-fdiv_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fdiv.d", 2)': 0
-        
-fdiv_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fdiv.d", 2)': 0
-        
-fdiv_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fdiv.d", 2)': 0
-
-fdiv_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fdiv.d", 2)': 0
-        
-fdiv_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fdiv.d", 2)': 0
-        
-fdiv_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fdiv.d", 2)': 0
-        
-fdiv_b9:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b9(64, "fdiv.d", 2)': 0
-
-fdiv_b20:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b20(64, "fdiv.d", 2)': 0
-        
-fdiv_b21:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b21(64, "fdiv.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_feq.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_feq.cgf
deleted file mode 100644
index f26e1083..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_feq.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-feq_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      feq.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "feq.d", 2)': 0
-        
-feq_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      feq.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(64, "feq.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fld.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fld.cgf
deleted file mode 100644
index 7d3dd2d2..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fld.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fld-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      fld: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rd: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fle.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fle.cgf
deleted file mode 100644
index 9ee4a45f..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fle.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fle_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fle.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fle.d", 2)': 0
-        
-fle_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fle.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(64, "fle.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmadd.cgf
deleted file mode 100644
index 84ab80e8..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmadd.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmadd_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fmadd.d", 3)': 0
-        
-fmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmadd.d", 3)': 0
-        
-fmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmadd.d", 3)': 0
-        
-fmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmadd.d", 3)': 0
-        
-fmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmadd.d", 3)': 0
-        
-fmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmadd.d", 3)': 0
-        
-fmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmadd.d", 3)': 0
-        
-fmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmadd.d", 3)': 0
-        
-fmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fmadd.d", 3)': 0
-        
-fmadd_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(64, "fmadd.d", 3)': 0
-        
-fmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fmadd.d", 3)': 0
-        
-fmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fmadd.d", 3)': 0
-        
-fmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmadd1.cgf
deleted file mode 100644
index 82b7f269..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmadd.d", 3)': 0
-        
-fmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmadd.d", 3)': 0
-        
-fmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmadd.d", 3)': 0
-        
-fmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmadd.d", 3)': 0
-        
-fmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmadd.d", 3)': 0
-        
-fmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmadd.d", 3)': 0
-        
-fmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmadd.d", 3)': 0
-        
-fmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fmadd.d", 3)': 0
-        
-fmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fmadd.d", 3)': 0
-        
-fmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fmadd.d", 3)': 0
-        
-fmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmax.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmax.cgf
deleted file mode 100644
index 0e87171b..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmax.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmax_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmax.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fmax.d", 2)': 0
-        
-fmax_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmax.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(64, "fmax.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmsub.cgf
deleted file mode 100644
index 65dbbbab..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmsub.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmsub_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fmsub.d", 3)': 0
-        
-fmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmsub.d", 3)': 0
-        
-fmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmsub.d", 3)': 0
-        
-fmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmsub.d", 3)': 0
-        
-fmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmsub.d", 3)': 0
-        
-fmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmsub.d", 3)': 0
-        
-fmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmsub.d", 3)': 0
-        
-fmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmsub.d", 3)': 0
-        
-fmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fmsub.d", 3)': 0
-        
-fmsub_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(64, "fmsub.d", 3)': 0
-        
-fmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fmsub.d", 3)': 0
-        
-fmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fmsub.d", 3)': 0
-        
-fmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmsub1.cgf
deleted file mode 100644
index ff286f83..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmsub.d", 3)': 0
-        
-fmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmsub.d", 3)': 0
-        
-fmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmsub.d", 3)': 0
-        
-fmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmsub.d", 3)': 0
-        
-fmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmsub.d", 3)': 0
-        
-fmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmsub.d", 3)': 0
-        
-fmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmsub.d", 3)': 0
-        
-fmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fmsub.d", 3)': 0
-                
-fmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fmsub.d", 3)': 0
-        
-fmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fmsub.d", 3)': 0
-        
-fmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmul.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmul.cgf
deleted file mode 100644
index 9842326c..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fmul.cgf
+++ /dev/null
@@ -1,155 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmul_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fmul.d", 2)': 0
-        
-fmul_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmul.d", 2)': 0
-        
-fmul_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmul.d", 2)': 0
-        
-fmul_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmul.d", 2)': 0
-        
-fmul_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmul.d", 2)': 0
-
-fmul_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmul.d", 2)': 0
-        
-fmul_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmul.d", 2)': 0
-        
-fmul_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmul.d", 2)': 0
-        
-fmul_b9:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b9(64, "fmul.d", 2)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmadd1.cgf
deleted file mode 100644
index c40b2239..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fnmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fnmadd.d", 3)': 0
-                
-fnmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fnmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmsub.cgf
deleted file mode 100644
index 3cd16329..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmsub.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmsub_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fnmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmsub1.cgf
deleted file mode 100644
index 85e902cc..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fnmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fnmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fnmsub.d", 3)': 0
-                
-fnmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fnmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsd.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsd.cgf
deleted file mode 100644
index 3c4675f5..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsd.cgf
+++ /dev/null
@@ -1,22 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsd-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      fsd: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rs2: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
-        <<: [  *base_rs2val_sgn]
-        abstract_comb:
-          <<: [*rs2val_walking]
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnj.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnj.cgf
deleted file mode 100644
index 1b45513c..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnj.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsgnj_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsgnj.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fsgnj.d", 2)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnjx.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnjx.cgf
deleted file mode 100644
index 25cefb40..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsgnjx.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsgnjx_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsgnjx.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fsgnjx.d", 2)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsqrt.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsqrt.cgf
deleted file mode 100644
index 3a19dfb4..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsqrt.cgf
+++ /dev/null
@@ -1,137 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsqrt_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fsqrt.d", 1)': 0
-
-fsqrt_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fsqrt.d", 1)': 0
-        
-fsqrt_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fsqrt.d", 1)': 0
-
-fsqrt_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fsqrt.d", 1)': 0
-
-fsqrt_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fsqrt.d", 1)': 0
-
-fsqrt_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fsqrt.d", 1)': 0
-
-fsqrt_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fsqrt.d", 1)': 0
-
-fsqrt_b9:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b9(64, "fsqrt.d", 1)': 0
-
-fsqrt_b20:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b20(64, "fsqrt.d", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsub.cgf
deleted file mode 100644
index 76b4dfd6..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32D/rv32d_fsub.cgf
+++ /dev/null
@@ -1,188 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsub_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fsub.d", 2)': 0
-        
-fsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fsub.d", 2)': 0
-        
-fsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fsub.d", 2)': 0
-        
-fsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fsub.d", 2)': 0
-        
-fsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fsub.d", 2)': 0
-        
-fsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fsub.d", 2)': 0
-        
-fsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fsub.d", 2)': 0
-        
-fsub_b10:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b10(64, "fsub.d", 2)': 0
-        
-fsub_b11:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b11(64, "fsub.d", 2)': 0
-        
-fsub_b12:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b12(64, "fsub.d", 2)': 0
-        
-fsub_b13:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b13(64, "fsub.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf
similarity index 81%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fadd.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf
index 7c8c6093..01fc5104 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fadd.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fadd.s.cgf
@@ -3,7 +3,7 @@
 fadd_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fadd_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fadd.s", 2)': 0
+        'ibm_b1(flen,32, "fadd.s", 2)': 0
         
 fadd_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fadd_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fadd.s", 2)': 0
+        'ibm_b2(flen,32, "fadd.s", 2)': 0
         
 fadd_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fadd_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fadd.s", 2)': 0
+        'ibm_b3(flen,32, "fadd.s", 2)': 0
         
 fadd_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fadd_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fadd.s", 2)': 0
+        'ibm_b4(flen,32, "fadd.s", 2)': 0
         
 fadd_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fadd_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fadd.s", 2)': 0
+        'ibm_b5(flen,32, "fadd.s", 2)': 0
         
 fadd_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fadd_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fadd.s", 2)': 0
+        'ibm_b7(flen,32, "fadd.s", 2)': 0
         
 fadd_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fadd_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fadd.s", 2)': 0
+        'ibm_b8(flen,32, "fadd.s", 2)': 0
         
 fadd_b10:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fadd_b10:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b10(32, "fadd.s", 2)': 0
+        'ibm_b10(flen,32, "fadd.s", 2)': 0
         
 fadd_b11:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -151,12 +151,12 @@ fadd_b11:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b11(32, "fadd.s", 2)': 0
+        'ibm_b11(flen,32, "fadd.s", 2)': 0
         
 fadd_b12:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -168,12 +168,12 @@ fadd_b12:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b12(32, "fadd.s", 2)': 0
+        'ibm_b12(flen,32, "fadd.s", 2)': 0
         
 fadd_b13:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -185,4 +185,4 @@ fadd_b13:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b13(32, "fadd.s", 2)': 0
+        'ibm_b13(flen,32, "fadd.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fclass.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fclass.s.cgf
similarity index 83%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fclass.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fclass.s.cgf
index 1c1d58af..cf7cd1db 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fclass.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fclass.s.cgf
@@ -3,7 +3,7 @@
 fclass_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fclass.s: 0
     rs1: 
       <<: *all_fregs
@@ -11,5 +11,5 @@ fclass_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fclass.s", 1)': 0
+        'ibm_b1(flen,32, "fclass.s", 1)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.w.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.w.cgf
similarity index 87%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.w.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.w.cgf
index 35f7a951..49dc0f9c 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.w.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.w.cgf
@@ -3,7 +3,7 @@
 fcvt.s.w_b25:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.s.w: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.s.w_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fcvt.s.w", 1)': 0
+        'ibm_b25(flen,32, "fcvt.s.w", 1)': 0
         
 fcvt.s.w_b26:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.s.w: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.wu.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.wu.cgf
similarity index 87%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.wu.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.wu.cgf
index ec34d6f8..eff47266 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.wu.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.s.wu.cgf
@@ -3,7 +3,7 @@
 fcvt.s.wu_b25:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.s.wu: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.s.wu_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fcvt.s.wu", 1)': 0
+        'ibm_b25(flen,32, "fcvt.s.wu", 1)': 0
         
 fcvt.s.wu_b26:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.s.wu: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.w.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.w.s.cgf
similarity index 76%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.w.s.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fcvt.w.s.cgf
index 17a04a7b..1950bc32 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.w.s.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.w.s.cgf
@@ -3,7 +3,7 @@
 fcvt.w.s_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.w.s_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fcvt.w.s", 1)': 0
+        'ibm_b1(flen,32, "fcvt.w.s", 1)': 0
         
 fcvt.w.s_b22:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.w.s_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(32, "fcvt.w.s", 1)': 0
+        'ibm_b22(flen,32, "fcvt.w.s", 1)': 0
         
 fcvt.w.s_b23:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.w.s_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(32, "fcvt.w.s", 1)': 0
+        'ibm_b23(flen,32, "fcvt.w.s", 1)': 0
         
 fcvt.w.s_b24:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.w.s_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(32, "fcvt.w.s", 1)': 0
+        'ibm_b24(flen,32, "fcvt.w.s", 1)': 0
         
 fcvt.w.s_b27:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.w.s_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(32, "fcvt.w.s", 1)': 0
+        'ibm_b27(flen,32, "fcvt.w.s", 1)': 0
         
 fcvt.w.s_b28:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.w.s_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(32, "fcvt.w.s", 1)': 0
+        'ibm_b28(flen,32, "fcvt.w.s", 1)': 0
         
 fcvt.w.s_b29:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.w.s: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.w.s_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(32, "fcvt.w.s", 1)': 0
+        'ibm_b29(flen,32, "fcvt.w.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.wu.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.wu.s.cgf
similarity index 76%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.wu.s.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fcvt.wu.s.cgf
index 9921007f..4ab625dd 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.wu.s.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fcvt.wu.s.cgf
@@ -3,7 +3,7 @@
 fcvt.wu.s_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.wu.s_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fcvt.wu.s", 1)': 0
+        'ibm_b1(flen,32, "fcvt.wu.s", 1)': 0
         
 fcvt.wu.s_b22:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.wu.s_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(32, "fcvt.wu.s", 1)': 0
+        'ibm_b22(flen,32, "fcvt.wu.s", 1)': 0
         
 fcvt.wu.s_b23:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.wu.s_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(32, "fcvt.wu.s", 1)': 0
+        'ibm_b23(flen,32, "fcvt.wu.s", 1)': 0
         
 fcvt.wu.s_b24:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.wu.s_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(32, "fcvt.wu.s", 1)': 0
+        'ibm_b24(flen,32, "fcvt.wu.s", 1)': 0
         
 fcvt.wu.s_b27:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.wu.s_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(32, "fcvt.wu.s", 1)': 0
+        'ibm_b27(flen,32, "fcvt.wu.s", 1)': 0
         
 fcvt.wu.s_b28:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.wu.s_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(32, "fcvt.wu.s", 1)': 0
+        'ibm_b28(flen,32, "fcvt.wu.s", 1)': 0
         
 fcvt.wu.s_b29:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fcvt.wu.s: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.wu.s_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(32, "fcvt.wu.s", 1)': 0
+        'ibm_b29(flen,32, "fcvt.wu.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fdiv.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fdiv.s.cgf
similarity index 81%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fdiv.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fdiv.s.cgf
index 0f16fbad..f4b3e143 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fdiv.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fdiv.s.cgf
@@ -3,7 +3,7 @@
 fdiv_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fdiv_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fdiv.s", 2)': 0
+        'ibm_b1(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fdiv_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fdiv.s", 2)': 0
+        'ibm_b2(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fdiv_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fdiv.s", 2)': 0
+        'ibm_b3(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fdiv_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fdiv.s", 2)': 0
+        'ibm_b4(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fdiv_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fdiv.s", 2)': 0
+        'ibm_b5(flen,32, "fdiv.s", 2)': 0
 
 fdiv_b6:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fdiv_b6:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(32, "fdiv.s", 2)': 0
+        'ibm_b6(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fdiv_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fdiv.s", 2)': 0
+        'ibm_b7(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fdiv_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fdiv.s", 2)': 0
+        'ibm_b8(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b9:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -151,12 +151,12 @@ fdiv_b9:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b9(32, "fdiv.s", 2)': 0
+        'ibm_b9(flen,32, "fdiv.s", 2)': 0
 
 fdiv_b20:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -168,12 +168,12 @@ fdiv_b20:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b20(32, "fdiv.s", 2)': 0
+        'ibm_b20(flen,32, "fdiv.s", 2)': 0
         
 fdiv_b21:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fdiv.s: 0
     rs1: 
       <<: *all_fregs
@@ -185,4 +185,4 @@ fdiv_b21:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b21(32, "fdiv.s", 2)': 0
+        'ibm_b21(flen,32, "fdiv.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_feq.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/feq.s.cgf
similarity index 83%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_feq.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/feq.s.cgf
index 29ebfff4..7cf20e82 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_feq.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/feq.s.cgf
@@ -3,7 +3,7 @@
 feq_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       feq.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ feq_b1:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "feq.s", 2)': 0
+        'ibm_b1(flen,32, "feq.s", 2)': 0
         
 feq_b19:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       feq.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ feq_b19:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(32, "feq.s", 2)': 0
+        'ibm_b19(flen,32, "feq.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fle.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fle.s.cgf
similarity index 83%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fle.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fle.s.cgf
index f01954a4..0e743cfb 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fle.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fle.s.cgf
@@ -3,7 +3,7 @@
 fle_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fle.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fle_b1:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fle.s", 2)': 0
+        'ibm_b1(flen,32, "fle.s", 2)': 0
         
 fle_b19:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fle.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ fle_b19:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(32, "fle.s", 2)': 0
+        'ibm_b19(flen,32, "fle.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_flt.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/flt.s.cgf
similarity index 83%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_flt.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/flt.s.cgf
index ba1a0dc4..0cbfc496 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_flt.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/flt.s.cgf
@@ -3,7 +3,7 @@
 flt_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       flt.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ flt_b1:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "flt.s", 2)': 0
+        'ibm_b1(flen,32, "flt.s", 2)': 0
         
 flt_b19:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       flt.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ flt_b19:
       <<: *sfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(32, "flt.s", 2)': 0
+        'ibm_b19(flen,32, "flt.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf
new file mode 100644
index 00000000..62ed7d1b
--- /dev/null
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf
@@ -0,0 +1,19 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+flw-align:
+    config: 
+      - check ISA:=regex(.*F.*)
+    mnemonics: 
+      flw: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rd: 
+      <<: *all_fregs
+    val_comb:
+        'ea_align == 0 and (imm_val % 4) == 0 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 4) == 1 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 4) == 2 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 4) == 3 and fcsr == 0': 0
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val < 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmadd.s.cgf
similarity index 82%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmadd.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmadd.s.cgf
index 4ad35dc3..b5f3c9a8 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmadd.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmadd.s.cgf
@@ -3,7 +3,7 @@
 fmadd_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fmadd_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fmadd.s", 3)': 0
+        'ibm_b1(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fmadd_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fmadd.s", 3)': 0
+        'ibm_b2(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fmadd_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fmadd.s", 3)': 0
+        'ibm_b3(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fmadd_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fmadd.s", 3)': 0
+        'ibm_b4(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fmadd_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fmadd.s", 3)': 0
+        'ibm_b5(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b6:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fmadd_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(32, "fmadd.s", 3)': 0
+        'ibm_b6(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fmadd_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fmadd.s", 3)': 0
+        'ibm_b7(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fmadd_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fmadd.s", 3)': 0
+        'ibm_b8(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b14:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fmadd_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(32, "fmadd.s", 3)': 0
+        'ibm_b14(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b15:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fmadd_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(32, "fmadd.s", 3)': 0
+        'ibm_b15(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b16:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fmadd_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(32, "fmadd.s", 3)': 0
+        'ibm_b16(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b17:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fmadd_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(32, "fmadd.s", 3)': 0
+        'ibm_b17(flen,32, "fmadd.s", 3)': 0
         
 fmadd_b18:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fmadd_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(32, "fmadd.s", 3)': 0
+        'ibm_b18(flen,32, "fmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmax.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmax.s.cgf
similarity index 83%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmax.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmax.s.cgf
index 4e5a4375..6652fcbf 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmax.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmax.s.cgf
@@ -3,7 +3,7 @@
 fmax_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmax.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fmax_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fmax.s", 2)': 0
+        'ibm_b1(flen,32, "fmax.s", 2)': 0
         
 fmax_b19:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmax.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ fmax_b19:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(32, "fmax.s", 2)': 0
+        'ibm_b19(flen,32, "fmax.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmin.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmin.s.cgf
similarity index 83%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmin.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmin.s.cgf
index 12198dad..81d4ba06 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmin.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmin.s.cgf
@@ -3,7 +3,7 @@
 fmin_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmin.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fmin_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fmin.s", 2)': 0
+        'ibm_b1(flen,32, "fmin.s", 2)': 0
         
 fmin_b19:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmin.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,4 +32,4 @@ fmin_b19:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b19(32, "fmin.s", 2)': 0
+        'ibm_b19(flen,32, "fmin.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmsub.s.cgf
similarity index 82%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmsub.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmsub.s.cgf
index e3248890..ff6b7464 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmsub.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmsub.s.cgf
@@ -3,7 +3,7 @@
 fmsub_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fmsub_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fmsub.s", 3)': 0
+        'ibm_b1(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fmsub_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fmsub.s", 3)': 0
+        'ibm_b2(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fmsub_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fmsub.s", 3)': 0
+        'ibm_b3(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fmsub_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fmsub.s", 3)': 0
+        'ibm_b4(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fmsub_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fmsub.s", 3)': 0
+        'ibm_b5(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b6:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fmsub_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(32, "fmsub.s", 3)': 0
+        'ibm_b6(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fmsub_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fmsub.s", 3)': 0
+        'ibm_b7(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fmsub_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fmsub.s", 3)': 0
+        'ibm_b8(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b14:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fmsub_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(32, "fmsub.s", 3)': 0
+        'ibm_b14(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b15:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fmsub_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(32, "fmsub.s", 3)': 0
+        'ibm_b15(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b16:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fmsub_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(32, "fmsub.s", 3)': 0
+        'ibm_b16(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b17:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fmsub_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(32, "fmsub.s", 3)': 0
+        'ibm_b17(flen,32, "fmsub.s", 3)': 0
         
 fmsub_b18:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fmsub_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(32, "fmsub.s", 3)': 0
+        'ibm_b18(flen,32, "fmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmul.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmul.s.cgf
similarity index 81%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmul.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmul.s.cgf
index 02471fe0..5d09eba2 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmul.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmul.s.cgf
@@ -3,7 +3,7 @@
 fmul_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fmul_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fmul.s", 2)': 0
+        'ibm_b1(flen,32, "fmul.s", 2)': 0
         
 fmul_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fmul_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fmul.s", 2)': 0
+        'ibm_b2(flen,32, "fmul.s", 2)': 0
         
 fmul_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fmul_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fmul.s", 2)': 0
+        'ibm_b3(flen,32, "fmul.s", 2)': 0
         
 fmul_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fmul_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fmul.s", 2)': 0
+        'ibm_b4(flen,32, "fmul.s", 2)': 0
         
 fmul_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fmul_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fmul.s", 2)': 0
+        'ibm_b5(flen,32, "fmul.s", 2)': 0
 
 fmul_b6:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fmul_b6:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(32, "fmul.s", 2)': 0
+        'ibm_b6(flen,32, "fmul.s", 2)': 0
         
 fmul_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fmul_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fmul.s", 2)': 0
+        'ibm_b7(flen,32, "fmul.s", 2)': 0
         
 fmul_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fmul_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fmul.s", 2)': 0
+        'ibm_b8(flen,32, "fmul.s", 2)': 0
         
 fmul_b9:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmul.s: 0
     rs1: 
       <<: *all_fregs
@@ -151,5 +151,5 @@ fmul_b9:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b9(32, "fmul.s", 2)': 0
+        'ibm_b9(flen,32, "fmul.s", 2)': 0
 
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmv.w.x.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmv.w.x.cgf
similarity index 87%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmv.w.x.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmv.w.x.cgf
index 85916229..fae501ea 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmv.w.x.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmv.w.x.cgf
@@ -3,7 +3,7 @@
 fmv.w.x_b25:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.w.x: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fmv.w.x_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fmv.w.x", 1)': 0
+        'ibm_b25(flen,32, "fmv.w.x", 1)': 0
         
 fmv.w.x_b26:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.w.x: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmv.x.w.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fmv.x.w.cgf
similarity index 76%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmv.x.w.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fmv.x.w.cgf
index d961e892..e58bacec 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmv.x.w.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fmv.x.w.cgf
@@ -3,7 +3,7 @@
 fmv.x.w_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fmv.x.w_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fmv.x.w", 1)': 0
+        'ibm_b1(flen,32, "fmv.x.w", 1)': 0
         
 fmv.x.w_b22:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fmv.x.w_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(32, "fmv.x.w", 1)': 0
+        'ibm_b22(flen,32, "fmv.x.w", 1)': 0
         
 fmv.x.w_b23:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fmv.x.w_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(32, "fmv.x.w", 1)': 0
+        'ibm_b23(flen,32, "fmv.x.w", 1)': 0
         
 fmv.x.w_b24:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fmv.x.w_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(32, "fmv.x.w", 1)': 0
+        'ibm_b24(flen,32, "fmv.x.w", 1)': 0
         
 fmv.x.w_b27:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fmv.x.w_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(32, "fmv.x.w", 1)': 0
+        'ibm_b27(flen,32, "fmv.x.w", 1)': 0
         
 fmv.x.w_b28:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fmv.x.w_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(32, "fmv.x.w", 1)': 0
+        'ibm_b28(flen,32, "fmv.x.w", 1)': 0
         
 fmv.x.w_b29:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fmv.x.w: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fmv.x.w_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(32, "fmv.x.w", 1)': 0
+        'ibm_b29(flen,32, "fmv.x.w", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fnmadd.s.cgf
similarity index 82%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmadd.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fnmadd.s.cgf
index cb330469..f8834ff4 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmadd.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fnmadd.s.cgf
@@ -3,7 +3,7 @@
 fnmadd_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fnmadd_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fnmadd.s", 3)': 0
+        'ibm_b1(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fnmadd_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fnmadd.s", 3)': 0
+        'ibm_b2(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fnmadd_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fnmadd.s", 3)': 0
+        'ibm_b3(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fnmadd_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fnmadd.s", 3)': 0
+        'ibm_b4(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fnmadd_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fnmadd.s", 3)': 0
+        'ibm_b5(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b6:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fnmadd_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(32, "fnmadd.s", 3)': 0
+        'ibm_b6(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fnmadd_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fnmadd.s", 3)': 0
+        'ibm_b7(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fnmadd_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fnmadd.s", 3)': 0
+        'ibm_b8(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b14:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fnmadd_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(32, "fnmadd.s", 3)': 0
+        'ibm_b14(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b15:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fnmadd_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(32, "fnmadd.s", 3)': 0
+        'ibm_b15(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b16:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fnmadd_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(32, "fnmadd.s", 3)': 0
+        'ibm_b16(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b17:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fnmadd_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(32, "fnmadd.s", 3)': 0
+        'ibm_b17(flen,32, "fnmadd.s", 3)': 0
         
 fnmadd_b18:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmadd.s: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fnmadd_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(32, "fnmadd.s", 3)': 0
+        'ibm_b18(flen,32, "fnmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fnmsub.s.cgf
similarity index 82%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmsub.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fnmsub.s.cgf
index 9ed9caed..f163e3ce 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmsub.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fnmsub.s.cgf
@@ -3,7 +3,7 @@
 fnmsub_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -17,12 +17,12 @@ fnmsub_b1:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fnmsub.s", 3)': 0
+        'ibm_b1(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -36,12 +36,12 @@ fnmsub_b2:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fnmsub.s", 3)': 0
+        'ibm_b2(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -55,12 +55,12 @@ fnmsub_b3:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fnmsub.s", 3)': 0
+        'ibm_b3(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -74,12 +74,12 @@ fnmsub_b4:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fnmsub.s", 3)': 0
+        'ibm_b4(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -93,12 +93,12 @@ fnmsub_b5:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fnmsub.s", 3)': 0
+        'ibm_b5(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b6:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -112,12 +112,12 @@ fnmsub_b6:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b6(32, "fnmsub.s", 3)': 0
+        'ibm_b6(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -131,12 +131,12 @@ fnmsub_b7:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fnmsub.s", 3)': 0
+        'ibm_b7(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -150,12 +150,12 @@ fnmsub_b8:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fnmsub.s", 3)': 0
+        'ibm_b8(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b14:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -169,12 +169,12 @@ fnmsub_b14:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b14(32, "fnmsub.s", 3)': 0
+        'ibm_b14(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b15:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -188,12 +188,12 @@ fnmsub_b15:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b15(32, "fnmsub.s", 3)': 0
+        'ibm_b15(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b16:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -207,12 +207,12 @@ fnmsub_b16:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b16(32, "fnmsub.s", 3)': 0
+        'ibm_b16(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b17:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -226,12 +226,12 @@ fnmsub_b17:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b17(32, "fnmsub.s", 3)': 0
+        'ibm_b17(flen,32, "fnmsub.s", 3)': 0
         
 fnmsub_b18:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fnmsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -245,4 +245,4 @@ fnmsub_b18:
       <<: *r4fmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b18(32, "fnmsub.s", 3)': 0
+        'ibm_b18(flen,32, "fnmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnj.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fsgnj.s.cgf
similarity index 86%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnj.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fsgnj.s.cgf
index 7f9a6296..cd04be5f 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnj.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fsgnj.s.cgf
@@ -3,7 +3,7 @@
 fsgnj_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsgnj.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,5 +15,5 @@ fsgnj_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fsgnj.s", 2)': 0
+        'ibm_b1(flen,32, "fsgnj.s", 2)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnjn.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjn.s.cgf
similarity index 85%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnjn.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fsgnjn.s.cgf
index 940e46ff..9b115f28 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnjn.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjn.s.cgf
@@ -3,7 +3,7 @@
 fsgnjn_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsgnjn.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,5 +15,5 @@ fsgnjn_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fsgnjn.s", 2)': 0
+        'ibm_b1(flen,32, "fsgnjn.s", 2)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnjx.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjx.s.cgf
similarity index 85%
rename from sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnjx.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fsgnjx.s.cgf
index bac9d36c..f157bf00 100644
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsgnjx.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fsgnjx.s.cgf
@@ -3,7 +3,7 @@
 fsgnjx_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsgnjx.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,5 +15,5 @@ fsgnjx_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fsgnjx.s", 2)': 0
+        'ibm_b1(flen,32, "fsgnjx.s", 2)': 0
         
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsqrt.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fsqrt.s.cgf
similarity index 79%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsqrt.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fsqrt.s.cgf
index 796c6cfc..0595ee6a 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsqrt.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fsqrt.s.cgf
@@ -3,7 +3,7 @@
 fsqrt_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -13,12 +13,12 @@ fsqrt_b1:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fsqrt.s", 1)': 0
+        'ibm_b1(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -28,12 +28,12 @@ fsqrt_b2:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fsqrt.s", 1)': 0
+        'ibm_b2(flen,32, "fsqrt.s", 1)': 0
         
 fsqrt_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -43,12 +43,12 @@ fsqrt_b3:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fsqrt.s", 1)': 0
+        'ibm_b3(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -58,12 +58,12 @@ fsqrt_b4:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fsqrt.s", 1)': 0
+        'ibm_b4(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -73,12 +73,12 @@ fsqrt_b5:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fsqrt.s", 1)': 0
+        'ibm_b5(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -88,12 +88,12 @@ fsqrt_b7:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fsqrt.s", 1)': 0
+        'ibm_b7(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -103,12 +103,12 @@ fsqrt_b8:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fsqrt.s", 1)': 0
+        'ibm_b8(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b9:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -118,12 +118,12 @@ fsqrt_b9:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b9(32, "fsqrt.s", 1)': 0
+        'ibm_b9(flen,32, "fsqrt.s", 1)': 0
 
 fsqrt_b20:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsqrt.s: 0
     rs1: 
       <<: *all_fregs
@@ -133,5 +133,5 @@ fsqrt_b20:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b20(32, "fsqrt.s", 1)': 0
+        'ibm_b20(flen,32, "fsqrt.s", 1)': 0
 
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fsub.s.cgf
similarity index 81%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsub.cgf
rename to sample_cgfs/sample_cgfs_fext/RV32F/fsub.s.cgf
index dd03928e..30eba036 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsub.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fsub.s.cgf
@@ -3,7 +3,7 @@
 fsub_b1:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -15,12 +15,12 @@ fsub_b1:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fsub.s", 2)': 0
+        'ibm_b1(flen,32, "fsub.s", 2)': 0
         
 fsub_b2:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -32,12 +32,12 @@ fsub_b2:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b2(32, "fsub.s", 2)': 0
+        'ibm_b2(flen,32, "fsub.s", 2)': 0
         
 fsub_b3:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -49,12 +49,12 @@ fsub_b3:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b3(32, "fsub.s", 2)': 0
+        'ibm_b3(flen,32, "fsub.s", 2)': 0
         
 fsub_b4:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -66,12 +66,12 @@ fsub_b4:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b4(32, "fsub.s", 2)': 0
+        'ibm_b4(flen,32, "fsub.s", 2)': 0
         
 fsub_b5:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -83,12 +83,12 @@ fsub_b5:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b5(32, "fsub.s", 2)': 0
+        'ibm_b5(flen,32, "fsub.s", 2)': 0
         
 fsub_b7:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -100,12 +100,12 @@ fsub_b7:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b7(32, "fsub.s", 2)': 0
+        'ibm_b7(flen,32, "fsub.s", 2)': 0
         
 fsub_b8:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -117,12 +117,12 @@ fsub_b8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b8(32, "fsub.s", 2)': 0
+        'ibm_b8(flen,32, "fsub.s", 2)': 0
         
 fsub_b10:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -134,12 +134,12 @@ fsub_b10:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b10(32, "fsub.s", 2)': 0
+        'ibm_b10(flen,32, "fsub.s", 2)': 0
         
 fsub_b11:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -151,12 +151,12 @@ fsub_b11:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b11(32, "fsub.s", 2)': 0
+        'ibm_b11(flen,32, "fsub.s", 2)': 0
         
 fsub_b12:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -168,12 +168,12 @@ fsub_b12:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b12(32, "fsub.s", 2)': 0
+        'ibm_b12(flen,32, "fsub.s", 2)': 0
         
 fsub_b13:
     config: 
       - check ISA:=regex(.*I.*F.*)
-    opcode: 
+    mnemonics: 
       fsub.s: 0
     rs1: 
       <<: *all_fregs
@@ -185,4 +185,4 @@ fsub_b13:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'ibm_b13(32, "fsub.s", 2)': 0
+        'ibm_b13(flen,32, "fsub.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf
new file mode 100644
index 00000000..3188c369
--- /dev/null
+++ b/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf
@@ -0,0 +1,19 @@
+# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
+
+fsw-align:
+    config: 
+      - check ISA:=regex(.*F.*)
+    mnemonics: 
+      fsw: 0
+    rs2: 
+      <<: *all_fregs
+    rs1: 
+      <<: *all_regs_mx0
+    val_comb:
+        'ea_align == 0 and (imm_val % 4) == 0 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 4) == 1 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 4) == 2 and fcsr == 0': 0
+        'ea_align == 0 and (imm_val % 4) == 3 and fcsr == 0': 0
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val < 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.s.w.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.s.w.cgf
deleted file mode 100644
index 35f7a951..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.s.w.cgf
+++ /dev/null
@@ -1,28 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-      
-fcvt.s.w_b25:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.w: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b25(32, "fcvt.s.w", 1)': 0
-        
-fcvt.s.w_b26:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.w: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b26(32, "fcvt.s.w", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.s.wu.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.s.wu.cgf
deleted file mode 100644
index ec34d6f8..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.s.wu.cgf
+++ /dev/null
@@ -1,28 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-      
-fcvt.s.wu_b25:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.wu: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b25(32, "fcvt.s.wu", 1)': 0
-        
-fcvt.s.wu_b26:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.wu: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b26(32, "fcvt.s.wu", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.w.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.w.s.cgf
deleted file mode 100644
index 17a04a7b..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.w.s.cgf
+++ /dev/null
@@ -1,92 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fcvt.w.s_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fcvt.w.s", 1)': 0
-        
-fcvt.w.s_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b22(32, "fcvt.w.s", 1)': 0
-        
-fcvt.w.s_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b23(32, "fcvt.w.s", 1)': 0
-        
-fcvt.w.s_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b24(32, "fcvt.w.s", 1)': 0
-        
-fcvt.w.s_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b27(32, "fcvt.w.s", 1)': 0
-        
-fcvt.w.s_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b28(32, "fcvt.w.s", 1)': 0
-        
-fcvt.w.s_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.w.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b29(32, "fcvt.w.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.wu.s.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.wu.s.cgf
deleted file mode 100644
index 9921007f..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fcvt.wu.s.cgf
+++ /dev/null
@@ -1,92 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fcvt.wu.s_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fcvt.wu.s", 1)': 0
-        
-fcvt.wu.s_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b22(32, "fcvt.wu.s", 1)': 0
-        
-fcvt.wu.s_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b23(32, "fcvt.wu.s", 1)': 0
-        
-fcvt.wu.s_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b24(32, "fcvt.wu.s", 1)': 0
-        
-fcvt.wu.s_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b27(32, "fcvt.wu.s", 1)': 0
-        
-fcvt.wu.s_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b28(32, "fcvt.wu.s", 1)': 0
-        
-fcvt.wu.s_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b29(32, "fcvt.wu.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_feq.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_feq.cgf
deleted file mode 100644
index 29ebfff4..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_feq.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-feq_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      feq.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "feq.s", 2)': 0
-        
-feq_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      feq.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(32, "feq.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_flw.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_flw.cgf
deleted file mode 100644
index e4822fd6..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_flw.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-flw-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      flw: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rd: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmadd1.cgf
deleted file mode 100644
index 6aca1d2a..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmadd.s", 3)': 0
-        
-fmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmadd.s", 3)': 0
-        
-fmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmadd.s", 3)': 0
-        
-fmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmadd.s", 3)': 0
-        
-fmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmadd.s", 3)': 0
-        
-fmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmadd.s", 3)': 0
-        
-fmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmadd.s", 3)': 0
-        
-fmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fmadd.s", 3)': 0
-        
-fmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fmadd.s", 3)': 0
-        
-fmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fmadd.s", 3)': 0
-        
-fmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmsub1.cgf
deleted file mode 100644
index d1ab2dce..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmsub.s", 3)': 0
-        
-fmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmsub.s", 3)': 0
-        
-fmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmsub.s", 3)': 0
-        
-fmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmsub.s", 3)': 0
-        
-fmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmsub.s", 3)': 0
-        
-fmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmsub.s", 3)': 0
-        
-fmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmsub.s", 3)': 0
-        
-fmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fmsub.s", 3)': 0
-        
-fmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fmsub.s", 3)': 0
-        
-fmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fmsub.s", 3)': 0
-        
-fmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmadd1.cgf
deleted file mode 100644
index 93154e37..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fnmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmsub1.cgf
deleted file mode 100644
index 51d9bc68..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fnmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fnmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fnmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsqrt.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsqrt.cgf
deleted file mode 100644
index 796c6cfc..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsqrt.cgf
+++ /dev/null
@@ -1,137 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsqrt_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fsqrt.s", 1)': 0
-
-fsqrt_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fsqrt.s", 1)': 0
-        
-fsqrt_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fsqrt.s", 1)': 0
-
-fsqrt_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fsqrt.s", 1)': 0
-
-fsqrt_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fsqrt.s", 1)': 0
-
-fsqrt_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fsqrt.s", 1)': 0
-
-fsqrt_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fsqrt.s", 1)': 0
-
-fsqrt_b9:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b9(32, "fsqrt.s", 1)': 0
-
-fsqrt_b20:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsqrt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b20(32, "fsqrt.s", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsub.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsub.cgf
deleted file mode 100644
index dd03928e..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsub.cgf
+++ /dev/null
@@ -1,188 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsub_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fsub.s", 2)': 0
-        
-fsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fsub.s", 2)': 0
-        
-fsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fsub.s", 2)': 0
-        
-fsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fsub.s", 2)': 0
-        
-fsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fsub.s", 2)': 0
-        
-fsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fsub.s", 2)': 0
-        
-fsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fsub.s", 2)': 0
-        
-fsub_b10:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b10(32, "fsub.s", 2)': 0
-        
-fsub_b11:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b11(32, "fsub.s", 2)': 0
-        
-fsub_b12:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b12(32, "fsub.s", 2)': 0
-        
-fsub_b13:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b13(32, "fsub.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsw.cgf b/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsw.cgf
deleted file mode 100644
index bfaf7b4a..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV32F/rv32f_fsw.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsw-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      fsw: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rs2: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.l.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.l.cgf
similarity index 74%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.l.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.l.cgf
index 30ae8c49..7db8eeb9 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.l.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.l.cgf
@@ -2,8 +2,8 @@
       
 fcvt.d.l_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.d.l: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.d.l_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(64, "fcvt.d.l", 1)': 0
+        'ibm_b25(flen,64, "fcvt.d.l", 1)': 0
         
 fcvt.d.l_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.d.l: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.lu.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.lu.cgf
similarity index 74%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.lu.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.lu.cgf
index a405fd70..a2dac71c 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.lu.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.d.lu.cgf
@@ -2,8 +2,8 @@
       
 fcvt.d.lu_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.d.lu: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.d.lu_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(64, "fcvt.d.lu", 1)': 0
+        'ibm_b25(flen,64, "fcvt.d.lu", 1)': 0
         
 fcvt.d.lu_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.d.lu: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.l.d.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.l.d.cgf
similarity index 61%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.l.d.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64D/fcvt.l.d.cgf
index 6f533814..a5079b4d 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.l.d.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.l.d.cgf
@@ -2,8 +2,8 @@
 
 fcvt.l.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.l.d_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fcvt.l.d", 1)': 0
+        'ibm_b1(flen,64, "fcvt.l.d", 1)': 0
         
 fcvt.l.d_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.l.d_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fcvt.l.d", 1)': 0
+        'ibm_b22(flen,64, "fcvt.l.d", 1)': 0
         
 fcvt.l.d_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.l.d_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fcvt.l.d", 1)': 0
+        'ibm_b23(flen,64, "fcvt.l.d", 1)': 0
         
 fcvt.l.d_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.l.d_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fcvt.l.d", 1)': 0
+        'ibm_b24(flen,64, "fcvt.l.d", 1)': 0
         
 fcvt.l.d_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.l.d_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fcvt.l.d", 1)': 0
+        'ibm_b27(flen,64, "fcvt.l.d", 1)': 0
         
 fcvt.l.d_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.l.d_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fcvt.l.d", 1)': 0
+        'ibm_b28(flen,64, "fcvt.l.d", 1)': 0
         
 fcvt.l.d_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.l.d: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.l.d_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fcvt.l.d", 1)': 0
+        'ibm_b29(flen,64, "fcvt.l.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.lu.d.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.lu.d.cgf
similarity index 61%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.lu.d.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64D/fcvt.lu.d.cgf
index 5e5a2e23..7402e452 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.lu.d.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64D/fcvt.lu.d.cgf
@@ -2,8 +2,8 @@
 
 fcvt.lu.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.lu.d_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fcvt.lu.d", 1)': 0
+        'ibm_b1(flen,64, "fcvt.lu.d", 1)': 0
         
 fcvt.lu.d_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.lu.d_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fcvt.lu.d", 1)': 0
+        'ibm_b22(flen,64, "fcvt.lu.d", 1)': 0
         
 fcvt.lu.d_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.lu.d_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fcvt.lu.d", 1)': 0
+        'ibm_b23(flen,64, "fcvt.lu.d", 1)': 0
         
 fcvt.lu.d_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.lu.d_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fcvt.lu.d", 1)': 0
+        'ibm_b24(flen,64, "fcvt.lu.d", 1)': 0
         
 fcvt.lu.d_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.lu.d_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fcvt.lu.d", 1)': 0
+        'ibm_b27(flen,64, "fcvt.lu.d", 1)': 0
         
 fcvt.lu.d_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.lu.d_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fcvt.lu.d", 1)': 0
+        'ibm_b28(flen,64, "fcvt.lu.d", 1)': 0
         
 fcvt.lu.d_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fcvt.lu.d: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.lu.d_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fcvt.lu.d", 1)': 0
+        'ibm_b29(flen,64, "fcvt.lu.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmv.d.x.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/fmv.d.x.cgf
similarity index 73%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmv.d.x.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64D/fmv.d.x.cgf
index 2d9f35b0..05d67690 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmv.d.x.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64D/fmv.d.x.cgf
@@ -2,8 +2,8 @@
       
 fmv.d.x_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.d.x: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fmv.d.x_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(64, "fmv.d.x", 1)': 0
+        'ibm_b25(flen,64, "fmv.d.x", 1)': 0
         
 fmv.d.x_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.d.x: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmv.x.d.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/fmv.x.d.cgf
similarity index 61%
rename from sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmv.x.d.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64D/fmv.x.d.cgf
index 44ff6f39..2cc96bdc 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmv.x.d.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64D/fmv.x.d.cgf
@@ -2,8 +2,8 @@
 
 fmv.x.d_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fmv.x.d_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(64, "fmv.x.d", 1)': 0
+        'ibm_b1(flen,64, "fmv.x.d", 1)': 0
         
 fmv.x.d_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fmv.x.d_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(64, "fmv.x.d", 1)': 0
+        'ibm_b22(flen,64, "fmv.x.d", 1)': 0
         
 fmv.x.d_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fmv.x.d_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(64, "fmv.x.d", 1)': 0
+        'ibm_b23(flen,64, "fmv.x.d", 1)': 0
         
 fmv.x.d_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fmv.x.d_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(64, "fmv.x.d", 1)': 0
+        'ibm_b24(flen,64, "fmv.x.d", 1)': 0
         
 fmv.x.d_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fmv.x.d_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(64, "fmv.x.d", 1)': 0
+        'ibm_b27(flen,64, "fmv.x.d", 1)': 0
         
 fmv.x.d_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fmv.x.d_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(64, "fmv.x.d", 1)': 0
+        'ibm_b28(flen,64, "fmv.x.d", 1)': 0
         
 fmv.x.d_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*D.*)
+    mnemonics: 
       fmv.x.d: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fmv.x.d_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(64, "fmv.x.d", 1)': 0
+        'ibm_b29(flen,64, "fmv.x.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fadd.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fadd.cgf
deleted file mode 100644
index 988309d1..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fadd.cgf
+++ /dev/null
@@ -1,188 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fadd_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fadd.d", 2)': 0
-        
-fadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fadd.d", 2)': 0
-        
-fadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fadd.d", 2)': 0
-        
-fadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fadd.d", 2)': 0
-        
-fadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fadd.d", 2)': 0
-        
-fadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fadd.d", 2)': 0
-        
-fadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fadd.d", 2)': 0
-        
-fadd_b10:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b10(64, "fadd.d", 2)': 0
-        
-fadd_b11:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b11(64, "fadd.d", 2)': 0
-        
-fadd_b12:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b12(64, "fadd.d", 2)': 0
-        
-fadd_b13:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b13(64, "fadd.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.w.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.w.cgf
deleted file mode 100644
index 823e7af7..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.w.cgf
+++ /dev/null
@@ -1,28 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-      
-fcvt.d.w_b25:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.w: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b25(64, "fcvt.d.w", 1)': 0
-        
-fcvt.d.w_b26:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.w: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b26(64, "fcvt.d.w", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.wu.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.wu.cgf
deleted file mode 100644
index c94cfaad..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.d.wu.cgf
+++ /dev/null
@@ -1,28 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-      
-fcvt.d.wu_b25:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.wu: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b25(64, "fcvt.d.wu", 1)': 0
-        
-fcvt.d.wu_b26:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.d.wu: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b26(64, "fcvt.d.wu", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.s.d.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.s.d.cgf
deleted file mode 100644
index 1452bee2..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.s.d.cgf
+++ /dev/null
@@ -1,106 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fcvt.s.d_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fcvt.s.d", 1)': 0
-        
-fcvt.s.d_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b22(64, "fcvt.s.d", 1)': 0
-        
-fcvt.s.d_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b23(64, "fcvt.s.d", 1)': 0
-        
-fcvt.s.d_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b24(64, "fcvt.s.d", 1)': 0
-        
-fcvt.s.d_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b27(64, "fcvt.s.d", 1)': 0
-        
-fcvt.s.d_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b28(64, "fcvt.s.d", 1)': 0
-        
-fcvt.s.d_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.s.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *ifmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b29(64, "fcvt.s.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.wu.d.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.wu.d.cgf
deleted file mode 100644
index f9687954..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fcvt.wu.d.cgf
+++ /dev/null
@@ -1,92 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fcvt.wu.d_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fcvt.wu.d", 1)': 0
-        
-fcvt.wu.d_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b22(64, "fcvt.wu.d", 1)': 0
-        
-fcvt.wu.d_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b23(64, "fcvt.wu.d", 1)': 0
-        
-fcvt.wu.d_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b24(64, "fcvt.wu.d", 1)': 0
-        
-fcvt.wu.d_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b27(64, "fcvt.wu.d", 1)': 0
-        
-fcvt.wu.d_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b28(64, "fcvt.wu.d", 1)': 0
-        
-fcvt.wu.d_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fcvt.wu.d: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b29(64, "fcvt.wu.d", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fld.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fld.cgf
deleted file mode 100644
index 7d3dd2d2..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fld.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fld-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      fld: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rd: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_flt.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_flt.cgf
deleted file mode 100644
index 2124b404..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_flt.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-flt_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      flt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "flt.d", 2)': 0
-        
-flt_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      flt.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(64, "flt.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmadd1.cgf
deleted file mode 100644
index 332990d6..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmadd.d", 3)': 0
-        
-fmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmadd.d", 3)': 0
-        
-fmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmadd.d", 3)': 0
-        
-fmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmadd.d", 3)': 0
-        
-fmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmadd.d", 3)': 0
-        
-fmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmadd.d", 3)': 0
-        
-fmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmadd.d", 3)': 0
-        
-fmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fmadd.d", 3)': 0
-        
-fmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fmadd.d", 3)': 0
-        
-fmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fmadd.d", 3)': 0
-        
-fmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmin.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmin.cgf
deleted file mode 100644
index e63f9f09..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmin.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmin_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmin.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fmin.d", 2)': 0
-        
-fmin_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmin.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(64, "fmin.d", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmsub1.cgf
deleted file mode 100644
index 90ee7040..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fmsub.d", 3)': 0
-        
-fmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fmsub.d", 3)': 0
-        
-fmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fmsub.d", 3)': 0
-        
-fmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fmsub.d", 3)': 0
-        
-fmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fmsub.d", 3)': 0
-        
-fmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fmsub.d", 3)': 0
-        
-fmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fmsub.d", 3)': 0
-        
-fmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fmsub.d", 3)': 0
-                
-fmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fmsub.d", 3)': 0
-        
-fmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fmsub.d", 3)': 0
-        
-fmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmadd.cgf
deleted file mode 100644
index 73777070..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmadd.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmadd_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fnmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmadd1.cgf
deleted file mode 100644
index d783e07e..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fnmadd.d", 3)': 0
-                
-fnmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fnmadd.d", 3)': 0
-        
-fnmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fnmadd.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmsub1.cgf
deleted file mode 100644
index 25415c69..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fnmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(64, "fnmsub.d", 3)': 0
-        
-fnmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(64, "fnmsub.d", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsd.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsd.cgf
deleted file mode 100644
index 0fb93150..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsd.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsd-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      fsd: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rs2: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnjn.cgf b/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnjn.cgf
deleted file mode 100644
index 134a8fc5..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64D/rv64d_fsgnjn.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsgnjn_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsgnjn.d: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(64, "fsgnjn.d", 2)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.l.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.l.s.cgf
similarity index 61%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.l.s.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64F/fcvt.l.s.cgf
index 32fdd121..152ad753 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.l.s.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.l.s.cgf
@@ -2,8 +2,8 @@
 
 fcvt.l.s_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.l.s_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fcvt.l.s", 1)': 0
+        'ibm_b1(flen,32, "fcvt.l.s", 1)': 0
         
 fcvt.l.s_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.l.s_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(32, "fcvt.l.s", 1)': 0
+        'ibm_b22(flen,32, "fcvt.l.s", 1)': 0
         
 fcvt.l.s_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.l.s_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(32, "fcvt.l.s", 1)': 0
+        'ibm_b23(flen,32, "fcvt.l.s", 1)': 0
         
 fcvt.l.s_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.l.s_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(32, "fcvt.l.s", 1)': 0
+        'ibm_b24(flen,32, "fcvt.l.s", 1)': 0
         
 fcvt.l.s_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.l.s_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(32, "fcvt.l.s", 1)': 0
+        'ibm_b27(flen,32, "fcvt.l.s", 1)': 0
         
 fcvt.l.s_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.l.s_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(32, "fcvt.l.s", 1)': 0
+        'ibm_b28(flen,32, "fcvt.l.s", 1)': 0
         
 fcvt.l.s_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.l.s: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.l.s_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(32, "fcvt.l.s", 1)': 0
+        'ibm_b29(flen,32, "fcvt.l.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.lu.s.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.lu.s.cgf
similarity index 61%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.lu.s.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64F/fcvt.lu.s.cgf
index 555a8ac3..544a7966 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.lu.s.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.lu.s.cgf
@@ -2,8 +2,8 @@
 
 fcvt.lu.s_b1:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -11,12 +11,12 @@ fcvt.lu.s_b1:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b1(32, "fcvt.lu.s", 1)': 0
+        'ibm_b1(flen,32, "fcvt.lu.s", 1)': 0
         
 fcvt.lu.s_b22:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -24,12 +24,12 @@ fcvt.lu.s_b22:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b22(32, "fcvt.lu.s", 1)': 0
+        'ibm_b22(flen,32, "fcvt.lu.s", 1)': 0
         
 fcvt.lu.s_b23:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -37,12 +37,12 @@ fcvt.lu.s_b23:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b23(32, "fcvt.lu.s", 1)': 0
+        'ibm_b23(flen,32, "fcvt.lu.s", 1)': 0
         
 fcvt.lu.s_b24:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -50,12 +50,12 @@ fcvt.lu.s_b24:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b24(32, "fcvt.lu.s", 1)': 0
+        'ibm_b24(flen,32, "fcvt.lu.s", 1)': 0
         
 fcvt.lu.s_b27:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -63,12 +63,12 @@ fcvt.lu.s_b27:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b27(32, "fcvt.lu.s", 1)': 0
+        'ibm_b27(flen,32, "fcvt.lu.s", 1)': 0
         
 fcvt.lu.s_b28:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -76,12 +76,12 @@ fcvt.lu.s_b28:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b28(32, "fcvt.lu.s", 1)': 0
+        'ibm_b28(flen,32, "fcvt.lu.s", 1)': 0
         
 fcvt.lu.s_b29:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.lu.s: 0
     rs1: 
       <<: *all_fregs
@@ -89,4 +89,4 @@ fcvt.lu.s_b29:
       <<: *all_regs
     val_comb:
       abstract_comb:
-        'ibm_b29(32, "fcvt.lu.s", 1)': 0
+        'ibm_b29(flen,32, "fcvt.lu.s", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.l.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.l.cgf
similarity index 67%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.l.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.l.cgf
index c309ef1c..e6eeebce 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.l.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.l.cgf
@@ -2,8 +2,8 @@
       
 fcvt.s.l_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.s.l: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.s.l_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fcvt.s.l", 1)': 0
+        'ibm_b25(flen,64, "fcvt.s.l", 1)': 0
         
 fcvt.s.l_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.s.l: 0
     rs1: 
       <<: *all_regs
@@ -24,5 +24,5 @@ fcvt.s.l_b26:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b26(32, "fcvt.s.l", 1)': 0
+        'ibm_b26(64, "fcvt.s.l", 1)': 0
 
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.lu.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.lu.cgf
similarity index 67%
rename from sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.lu.cgf
rename to sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.lu.cgf
index 134188be..4a23073d 100644
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fcvt.s.lu.cgf
+++ b/sample_cgfs/sample_cgfs_fext/RV64F/fcvt.s.lu.cgf
@@ -2,8 +2,8 @@
       
 fcvt.s.lu_b25:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.s.lu: 0
     rs1: 
       <<: *all_regs
@@ -11,12 +11,12 @@ fcvt.s.lu_b25:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b25(32, "fcvt.s.lu", 1)': 0
+        'ibm_b25(flen,64, "fcvt.s.lu", 1)': 0
         
 fcvt.s.lu_b26:
     config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
+      - check ISA:=regex(.*RV64.*I.*F.*)
+    mnemonics: 
       fcvt.s.lu: 0
     rs1: 
       <<: *all_regs
@@ -24,5 +24,5 @@ fcvt.s.lu_b26:
       <<: *all_fregs
     val_comb:
       abstract_comb:
-        'ibm_b26(32, "fcvt.s.lu", 1)': 0
+        'ibm_b26(64, "fcvt.s.lu", 1)': 0
 
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fadd.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fadd.cgf
deleted file mode 100644
index 7c8c6093..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fadd.cgf
+++ /dev/null
@@ -1,188 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fadd_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fadd.s", 2)': 0
-        
-fadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fadd.s", 2)': 0
-        
-fadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fadd.s", 2)': 0
-        
-fadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fadd.s", 2)': 0
-        
-fadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fadd.s", 2)': 0
-        
-fadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fadd.s", 2)': 0
-        
-fadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fadd.s", 2)': 0
-        
-fadd_b10:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b10(32, "fadd.s", 2)': 0
-        
-fadd_b11:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b11(32, "fadd.s", 2)': 0
-        
-fadd_b12:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b12(32, "fadd.s", 2)': 0
-        
-fadd_b13:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b13(32, "fadd.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fclass.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fclass.cgf
deleted file mode 100644
index 1c1d58af..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fclass.cgf
+++ /dev/null
@@ -1,15 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fclass_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fclass.s: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fclass.s", 1)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fdiv.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fdiv.cgf
deleted file mode 100644
index 0f16fbad..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fdiv.cgf
+++ /dev/null
@@ -1,188 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fdiv_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fdiv.s", 2)': 0
-        
-fdiv_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fdiv.s", 2)': 0
-        
-fdiv_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fdiv.s", 2)': 0
-        
-fdiv_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fdiv.s", 2)': 0
-        
-fdiv_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fdiv.s", 2)': 0
-
-fdiv_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fdiv.s", 2)': 0
-        
-fdiv_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fdiv.s", 2)': 0
-        
-fdiv_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fdiv.s", 2)': 0
-        
-fdiv_b9:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b9(32, "fdiv.s", 2)': 0
-
-fdiv_b20:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b20(32, "fdiv.s", 2)': 0
-        
-fdiv_b21:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fdiv.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b21(32, "fdiv.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fle.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fle.cgf
deleted file mode 100644
index f01954a4..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fle.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fle_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fle.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fle.s", 2)': 0
-        
-fle_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fle.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(32, "fle.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_flt.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_flt.cgf
deleted file mode 100644
index ba1a0dc4..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_flt.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-flt_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      flt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "flt.s", 2)': 0
-        
-flt_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      flt.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    op_comb: 
-      <<: *sfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(32, "flt.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_flw.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_flw.cgf
deleted file mode 100644
index e4822fd6..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_flw.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-flw-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      flw: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rd: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmadd.cgf
deleted file mode 100644
index 4ad35dc3..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmadd.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmadd_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fmadd.s", 3)': 0
-        
-fmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmadd.s", 3)': 0
-        
-fmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmadd.s", 3)': 0
-        
-fmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmadd.s", 3)': 0
-        
-fmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmadd.s", 3)': 0
-        
-fmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmadd.s", 3)': 0
-        
-fmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmadd.s", 3)': 0
-        
-fmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmadd.s", 3)': 0
-        
-fmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fmadd.s", 3)': 0
-        
-fmadd_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(32, "fmadd.s", 3)': 0
-        
-fmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fmadd.s", 3)': 0
-        
-fmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fmadd.s", 3)': 0
-        
-fmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmadd1.cgf
deleted file mode 100644
index 6aca1d2a..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmadd.s", 3)': 0
-        
-fmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmadd.s", 3)': 0
-        
-fmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmadd.s", 3)': 0
-        
-fmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmadd.s", 3)': 0
-        
-fmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmadd.s", 3)': 0
-        
-fmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmadd.s", 3)': 0
-        
-fmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmadd.s", 3)': 0
-        
-fmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fmadd.s", 3)': 0
-        
-fmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fmadd.s", 3)': 0
-        
-fmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fmadd.s", 3)': 0
-        
-fmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmax.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmax.cgf
deleted file mode 100644
index 4e5a4375..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmax.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmax_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmax.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fmax.s", 2)': 0
-        
-fmax_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmax.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(32, "fmax.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmin.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmin.cgf
deleted file mode 100644
index 12198dad..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmin.cgf
+++ /dev/null
@@ -1,35 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmin_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmin.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fmin.s", 2)': 0
-        
-fmin_b19:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmin.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b19(32, "fmin.s", 2)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmsub.cgf
deleted file mode 100644
index e3248890..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmsub.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmsub_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fmsub.s", 3)': 0
-        
-fmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmsub.s", 3)': 0
-        
-fmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmsub.s", 3)': 0
-        
-fmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmsub.s", 3)': 0
-        
-fmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmsub.s", 3)': 0
-        
-fmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmsub.s", 3)': 0
-        
-fmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmsub.s", 3)': 0
-        
-fmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmsub.s", 3)': 0
-        
-fmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fmsub.s", 3)': 0
-        
-fmsub_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(32, "fmsub.s", 3)': 0
-        
-fmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fmsub.s", 3)': 0
-        
-fmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fmsub.s", 3)': 0
-        
-fmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmsub1.cgf
deleted file mode 100644
index 3a23560b..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmsub.s", 3)': 0
-        
-fmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmsub.s", 3)': 0
-        
-fmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmsub.s", 3)': 0
-        
-fmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmsub.s", 3)': 0
-        
-fmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmsub.s", 3)': 0
-        
-fmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmsub.s", 3)': 0
-        
-fmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmsub.s", 3)': 0
-        
-fmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fmsub.s", 3)': 0
-        
-fmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fmsub.s", 3)': 0
-        
-fmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fmsub.s", 3)': 0
-        
-fmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmul.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmul.cgf
deleted file mode 100644
index 02471fe0..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmul.cgf
+++ /dev/null
@@ -1,155 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmul_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fmul.s", 2)': 0
-        
-fmul_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fmul.s", 2)': 0
-        
-fmul_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fmul.s", 2)': 0
-        
-fmul_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fmul.s", 2)': 0
-        
-fmul_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fmul.s", 2)': 0
-
-fmul_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fmul.s", 2)': 0
-        
-fmul_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fmul.s", 2)': 0
-        
-fmul_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fmul.s", 2)': 0
-        
-fmul_b9:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmul.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b9(32, "fmul.s", 2)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmv.w.x.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmv.w.x.cgf
deleted file mode 100644
index 85916229..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmv.w.x.cgf
+++ /dev/null
@@ -1,28 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-      
-fmv.w.x_b25:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.w.x: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b25(32, "fmv.w.x", 1)': 0
-        
-fmv.w.x_b26:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.w.x: 0
-    rs1: 
-      <<: *all_regs
-    rd: 
-      <<: *all_fregs
-    val_comb:
-      abstract_comb:
-        'ibm_b26(32, "fmv.w.x", 1)': 0
-
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmv.x.w.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmv.x.w.cgf
deleted file mode 100644
index d961e892..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fmv.x.w.cgf
+++ /dev/null
@@ -1,92 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fmv.x.w_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fmv.x.w", 1)': 0
-        
-fmv.x.w_b22:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b22(32, "fmv.x.w", 1)': 0
-        
-fmv.x.w_b23:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b23(32, "fmv.x.w", 1)': 0
-        
-fmv.x.w_b24:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b24(32, "fmv.x.w", 1)': 0
-        
-fmv.x.w_b27:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b27(32, "fmv.x.w", 1)': 0
-        
-fmv.x.w_b28:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b28(32, "fmv.x.w", 1)': 0
-        
-fmv.x.w_b29:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fmv.x.w: 0
-    rs1: 
-      <<: *all_fregs
-    rd: 
-      <<: *all_regs
-    val_comb:
-      abstract_comb:
-        'ibm_b29(32, "fmv.x.w", 1)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmadd.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmadd.cgf
deleted file mode 100644
index cb330469..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmadd.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmadd_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fnmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmadd1.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmadd1.cgf
deleted file mode 100644
index 817a6e21..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmadd1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fnmadd_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fnmadd.s", 3)': 0
-        
-fnmadd_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmadd.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fnmadd.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmsub.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmsub.cgf
deleted file mode 100644
index 9ed9caed..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmsub.cgf
+++ /dev/null
@@ -1,248 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fnmsub_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b15:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b15(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fnmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmsub1.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmsub1.cgf
deleted file mode 100644
index 51d9bc68..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fnmsub1.cgf
+++ /dev/null
@@ -1,210 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-        
-fnmsub_b2:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b2(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b3:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b3(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b4:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b4(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b5:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b5(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b6:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b6(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b7:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b7(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b8:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b8(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b14:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b14(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b16:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b16(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b17:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b17(32, "fnmsub.s", 3)': 0
-        
-fnmsub_b18:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fnmsub.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rs3:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *r4fmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b18(32, "fnmsub.s", 3)': 0
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnj.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnj.cgf
deleted file mode 100644
index 7f9a6296..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnj.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsgnj_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsgnj.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fsgnj.s", 2)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnjn.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnjn.cgf
deleted file mode 100644
index 940e46ff..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnjn.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsgnjn_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsgnjn.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fsgnjn.s", 2)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnjx.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnjx.cgf
deleted file mode 100644
index bac9d36c..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsgnjx.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsgnjx_b1:
-    config: 
-      - check ISA:=regex(.*I.*F.*)
-    opcode: 
-      fsgnjx.s: 0
-    rs1: 
-      <<: *all_fregs
-    rs2:
-      <<: *all_fregs
-    rd: 
-      <<: *all_fregs
-    op_comb: 
-      <<: *rfmt_op_comb
-    val_comb:
-      abstract_comb:
-        'ibm_b1(32, "fsgnjx.s", 2)': 0
-        
diff --git a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsw.cgf b/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsw.cgf
deleted file mode 100644
index bfaf7b4a..00000000
--- a/sample_cgfs/sample_cgfs_fext/RV64F/rv64f_fsw.cgf
+++ /dev/null
@@ -1,19 +0,0 @@
-# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore
-
-fsw-align:
-    config: 
-      - check ISA:=regex(.*I.*)
-    opcode: 
-      fsw: 0
-    rs1: 
-      <<: *all_regs_mx0
-    rs2: 
-      <<: *all_fregs
-    val_comb:
-        'ea_align == 0 and (imm_val % 4) == 0': 0
-        'ea_align == 0 and (imm_val % 4) == 1': 0
-        'ea_align == 0 and (imm_val % 4) == 2': 0
-        'ea_align == 0 and (imm_val % 4) == 3': 0
-        'imm_val > 0': 0
-        'imm_val < 0': 0
-        'imm_val == 0': 0
diff --git a/setup.cfg b/setup.cfg
index 0ed322e3..4e51c62d 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -1,5 +1,5 @@
 [bumpversion]
-current_version = 0.7.2
+current_version = 0.8.0
 commit = True
 tag = True
 
diff --git a/setup.py b/setup.py
index 389a79b7..e9161e37 100644
--- a/setup.py
+++ b/setup.py
@@ -26,7 +26,7 @@ def read_requires():
 
 setup(
     name='riscv_ctg',
-    version='0.7.2',
+    version='0.8.0',
     description="RISC-V CTG",
     long_description=readme + '\n\n',
     classifiers=[


Test patch:
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
index c3cbcb18..99338d25 100644
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@@ -40,23 +40,19 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2
+      
+      - uses: actions-ecosystem/action-get-latest-tag@v1
+        id: get-latest-tag
+      
       - name: version check
         run: |
           export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); 
           echo "CHANGELOG VERSION: $CHNGVER"
-          export INITVER=$(grep -P "__version__ = '.*?'" riscv_ctg/__init__.py | awk '{print $3}'|sed "s/'//g"); 
-          echo "INIT VERSION: $INITVER"
-          export TAGVER=$(git describe --tags --abbrev=0);
-          echo "TAGVER: $TAGVER"
-          if [ "$CHNGVER" = "$INITVER" ]; then
-              echo "Versions are equal in Changelog and init.py."
-          else
-              echo "Versions are not equal in Changelog and init.py."
-              exit 1
-          fi
+          export TAGVER=${{ steps.get-latest-tag.outputs.tag }}; 
+          echo "TAG VERSION: $TAGVER"
           if [ "$CHNGVER" = "$TAGVER" ]; then
-              echo "Versions are equal in Changelog and current tag."
+              echo "No changelog update."
               exit 1
           else
-              echo "Versions are not equal in Changelog and current tag. Good."
+              echo "Changelog updated."
           fi
diff --git a/riscv_ctg/env/arch_test.h b/riscv_ctg/env/arch_test.h
index 647fce85..f588bb0c 100644
--- a/riscv_ctg/env/arch_test.h
+++ b/riscv_ctg/env/arch_test.h
@@ -11,7 +11,6 @@
 //   #define rvtest_gpr_save
 // #endif
 
-
 //-----------------------------------------------------------------------
 // RV Arch Test Macros
 //-----------------------------------------------------------------------
@@ -68,6 +67,7 @@
 #if XLEN==64
   #define SREG sd
   #define LREG ld
+  #define LREGWU lwu
   #define REGWIDTH 8
   #define MASK 0xFFFFFFFFFFFFFFFF
 
@@ -75,6 +75,7 @@
   #if XLEN==32
     #define SREG sw
     #define LREG lw
+    #define LREGWU lw
     #define REGWIDTH 4
   #define MASK 0xFFFFFFFF
 
@@ -85,12 +86,17 @@
   #define FLREG fld
   #define FSREG fsd
   #define FREGWIDTH 8
-
+  #define SIGALIGN 8
 #else 
   #if FLEN==32
     #define FLREG flw
     #define FSREG fsw
     #define FREGWIDTH 4
+    #if XLEN==64
+        #define SIGALIGN 8
+    #else
+        #define SIGALIGN 4
+    #endif
   #endif
 #endif
 
@@ -107,6 +113,36 @@
   #define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16)
 #endif
 
+#define NAN_BOXED(__val__,__width__,__max__)    \
+    .if __width__ == 32                        ;\
+        .word __val__                          ;\
+    .else                                      ;\
+        .dword __val__                         ;\
+    .endif                                     ;\
+    .if __max__ > __width__                    ;\
+        .set pref_bytes,(__max__-__width__)/32 ;\
+    .else                                      ;\
+        .set pref_bytes, 0                     ;\
+    .endif                                     ;\
+    .rept pref_bytes                           ;\
+        .word 0xffffffff                       ;\
+    .endr                                      ;
+
+
+#define ZERO_EXTEND(__val__,__width__,__max__)  \
+    .if __max__ > __width__                    ;\
+        .set pref_bytes,(__max__-__width__)/32 ;\
+    .else                                      ;\
+        .set pref_bytes, 0                     ;\
+    .endif                                     ;\
+    .rept pref_bytes                           ;\
+        .word 0                                ;\
+    .endr                                      ;\
+    .if __width__ == 32                        ;\
+        .word __val__                          ;\
+    .else                                      ;\
+        .dword __val__                         ;\
+    .endif;
 
 // ----------------------------------- CODE BEGIN w/ TRAP HANDLER START ------------------------ //
 
@@ -252,10 +288,10 @@
   /**** to a return for anything above that (which causes a mismatch)****/
   /**********************************************************************/
   mtrampoline:		// 64 or 32 entry table
-  value = 0
+  .set value, 0
   .rept NUM_SPECD_INTCAUSES     	  // located at each possible int vectors
      j	mtrap_handler + 12*(value)  //offset < +/- 1MB
-     value = value + 1
+     .set value, value + 1
   .endr
   .rept RLENG-NUM_SPECD_INTCAUSES   // fill at each impossible entry
   	mret
@@ -552,10 +588,14 @@
  csrs mstatus, a0;                      \
  csrwi fcsr, 0
 
+#ifdef pext_check_vxsat_ov
 #define RVTEST_VXSAT_ENABLE()\
  li a0, MSTATUS_VS & (MSTATUS_VS >> 1); \
  csrs mstatus, a0;                      \
  clrov
+#else
+#define RVTEST_VXSAT_ENABLE()
+#endif
 
 #define RVTEST_SIGBASE(_R,_TAG) \
   LA(_R,_TAG);\
@@ -569,6 +609,33 @@
 #define _ARG1(_1ST,...) _1ST
 #define NARG(...) _ARG5(__VA_OPT__(__VA_ARGS__,)4,3,2,1,0)
 
+#define LOAD_MEM_VAL(_LINST, _AREG, _RD, _OFF, _TREG)  \
+    .if _OFF >= 2048                                  ;\
+        .set _off, _OFF%2048                          ;\
+        LI(_TREG, _OFF-_off)                          ;\
+        add _AREG,_AREG,_TREG                         ;\
+    .else                                             ;\
+        .set _off, _OFF                               ;\
+    .endif                                            ;\
+    _LINST _RD, _off(_AREG)                           ;\
+    .if _OFF >= 2048                                  ;\
+        sub _AREG,_AREG,_TREG                         ;\
+    .endif
+
+ /* use this function to ensure individual signature stores don't exceed offset limits */
+  /* if they would, then update the base by offset & reduce offset by -2048             */
+  /* there is an option to pre-increment offset if there was a previous signture store  */
+
+#define CHK_OFFSET(_BREG, _SZ, _PRE_INC) \
+  .if (_PRE_INC!=0)                      ;\
+    .set offset, offset+_SZ             ;\
+  .endif                                ;\
+  .if offset>=2048                      ;\
+     addi  _BREG, _BREG, (2048 - _SZ)   ;\
+     .set  offset, offset -(2048 - _SZ)  ;\
+  .endif
+
+
  /* automatically adjust base and offset if offset gets too big */
  /* RVTEST_SIGUPD(basereg, sigreg)        stores sigreg at offset(basereg) and updates offset by regwidth */
  /* RVTEST_SIGUPD(basereg, sigreg,newoff) stores sigreg at newoff(basereg) and updates offset to regwidth+newoff */
@@ -576,10 +643,7 @@
   .if NARG(__VA_ARGS__) == 1                            ;\
 	.set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
   .endif                                                ;\
-  .if offset+REGWIDTH>=2048                             ;\
-     addi   _BR, _BR, offset                            ;\
-     .set   offset,   0					;\
-  .endif						;\
+  CHK_OFFSET(_BR,REGWIDTH,0);\
    SREG _R,offset(_BR)                                  ;\
   .set offset,offset+REGWIDTH
 
@@ -587,26 +651,30 @@
   .if NARG(__VA_ARGS__) == 1                            ;\
      .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
   .endif                                                ;\
-  .if offset+2*REGWIDTH>=2048                           ;\
-     addi   _BR, _BR,offset                             ;\
-     .set   offset, 0					;\
-  .endif						;\
-   FSREG _R,offset(_BR)					;\
-   SREG  _F,offset+REGWIDTH(_BR)			;\
-   .set offset,offset+(2*REGWIDTH)
+  .if (offset & (SIGALIGN-1)) != 0                      ;\
+      .warning "Incorrect Offset Alignment for Signature.";\
+      .err                                              ;\
+  .endif                                                ;\
+  CHK_OFFSET(_BR,SIGALIGN,0);\
+  FSREG _R,offset(_BR)					;\
+  CHK_OFFSET(_BR,SIGALIGN,1);\
+   SREG  _F,offset(_BR)			;\
+   .set offset,offset+(SIGALIGN)
 
   
 #define RVTEST_SIGUPD_FID(_BR,_R,_F,...)		 \
   .if NARG(__VA_ARGS__) == 1                            ;\
      .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
   .endif                                                ;\
-  .if offset+2*REGWIDTH>=2048                           ;\
-     addi   _BR, _BR,offset                             ;\
-     .set   offset, 0					;\
-  .endif						;\
+  .if (offset & (SIGALIGN-1)) != 0                      ;\
+      .warning "Incorrect Offset Alignment for Signature.";\
+      .err                                              ;\
+  .endif                                                ;\
+  CHK_OFFSET(_BR,SIGALIGN,0);\
     SREG _R,offset(_BR)					;\
-    SREG _F,offset+REGWIDTH(_BR)			;\
-    .set offset,offset+(2*REGWIDTH)
+  CHK_OFFSET(_BR,SIGALIGN,1);\
+    SREG _F,offset(_BR)			;\
+    .set offset,offset+(SIGALIGN)
   
 // for updating signatures when 'rd' is a paired register (64-bit) in Zpsfoperand extension in RV32.
 #define RVTEST_SIGUPD_P64(_BR,_R,_R_HI,...)		 \
@@ -616,18 +684,26 @@
 	RVTEST_SIGUPD_FID(_BR,_R,_R_HI,_ARG1(__VA_OPT__(__VA_ARGS__,0)));\
  .endif
 
+// for reading vxsat.OV flag in P-ext; and only reads the flag when Zicsr extension is present
+#ifdef pext_check_vxsat_ov
+#define RDOV(_F)\
+   rdov _F
+#else
+#define RDOV(_F)\
+   nop
+#endif
+
 // for updating signatures that include flagreg when 'rd' is a paired register (64-bit) in Zpsfoperand extension in RV32.
 #define RVTEST_SIGUPD_PK64(_BR,_R,_R_HI,_F,...)\
   .if NARG(__VA_ARGS__) == 1                            ;\
      .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))	;\
   .endif                                                ;\
-  .if offset+3*REGWIDTH>=2048                           ;\
-     addi   _BR, _BR,offset                             ;\
-     .set   offset, 0					;\
-  .endif						;\
+  CHK_OFFSET(_BR,REGWIDTH,0);\
     SREG _R,offset(_BR)					;\
+  CHK_OFFSET(_BR,REGWIDTH,1);\
     SREG _R_HI,offset+REGWIDTH(_BR)			;\
-    rdov _F                                             ;\
+    RDOV(_F)                                            ;\
+  CHK_OFFSET(_BR,REGWIDTH,1);\
     SREG _F,offset+2*REGWIDTH(_BR)			;\
     .set offset,offset+(3*REGWIDTH)
 
@@ -703,12 +779,12 @@
     jalr x0,0(tempreg)                       ;\
 6:  LA(tempreg, 4f                          ) ;\
     jalr x0,0(tempreg)                        ;\
-1:  .if adj & 2 == 2                         ;\
+1:  .if (adj & 2 == 2) && (label == 1b)      ;\
     .fill 2,1,0x00                          ;\
     .endif                                    ;\
     xori rd,rd, 0x1                           ;\
     beq x0,x0,6b                               ;\
-    .if adj & 2 == 2                              ;\
+    .if (adj & 2 == 2) && (label == 1b)     ;\
     .fill 2,1,0x00                          ;\
     .endif                                    ;\
     .if (imm/2) - 2 >= 0                      ;\
@@ -716,7 +792,7 @@
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-     .if label == 3f                          ;\
+     .ifc label, 3f                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -735,19 +811,19 @@
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-    .if label == 1b                          ;\
+    .ifc label, 1b                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
     nop                                       ;\
     .endr                                     ;\
-3:  .if adj & 2 == 2                              ;\
+3:  .if (adj & 2 == 2) && (label == 3f)      ;\
     .fill 2,1,0x00                          ;\
     .endif                                    ;\
     xori rd,rd, 0x3                           ;\
     LA(tempreg, 4f                          ) ;\
     jalr x0,0(tempreg)                        ;\
-    .if adj&2 == 2                              ;\
+    .if (adj&2 == 2) && (label == 3f)       ;\
     .fill 2,1,0x00                     ;\
     .endif                                    ;\
 4: LA(tempreg, 5b                            ) ;\
@@ -775,7 +851,7 @@
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-     .if label == 3f                          ;\
+     .ifc label, 3f                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -790,7 +866,7 @@
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-     .if label == 1b                          ;\
+     .ifc label, 1b                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -826,25 +902,25 @@ nop                                                                         ;\
 RVTEST_SIGUPD(swreg,destreg,offset) 
 //SREG destreg, offset(swreg);
 
-#define TEST_STORE_F(swreg,testreg,index,rs1,rs2,rs2_val,imm_val,offset,inst,adj,flagreg)   ;\
-LI(flagreg,rs2_val)                                                           ;\
-fmv.w.x rs2, flagreg                                                          ;\
+#define TEST_STORE_F(swreg,testreg,fcsr_val,rs1,rs2,imm_val,offset,inst,adj,flagreg,valaddr_reg, val_offset);\
+LOAD_MEM_VAL(FLREG, valaddr_reg, rs2, val_offset, testreg); \
 addi rs1,swreg,offset+adj                                                     ;\
 LI(testreg,imm_val)                                                         ;\
 sub rs1,rs1,testreg                                                          ;\
 inst rs2, imm_val(rs1)                                                      ;\
 nop                                                                         ;\
 nop                                                                         ;\
-csrrs flagreg, fflags, x0                                                   ;\
-RVTEST_SIGUPD(swreg,flagreg,offset)
-
-#define TEST_LOAD_F(swreg,testreg,index,rs1,destreg,imm_val,offset,inst,adj,flagreg)   ;\
-LA(rs1,rvtest_data+(index*4)+adj-imm_val)                                      ;\
-inst destreg, imm_val(rs1)                                                   ;\
-nop                                                                         ;\
-nop                                                                         ;\
-csrrs flagreg, fflags, x0                                                   ;\
-RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset) 
+csrr flagreg, fcsr                                                         ;\
+RVTEST_SIGUPD(swreg,flagreg,offset+SIGALIGN)
+
+#define TEST_LOAD_F(swreg,testreg,fcsr_val,rs1,destreg,imm_val,inst,adj,flagreg)    ;\
+LA(rs1,rvtest_data+adj-imm_val)                                               ;\
+LI(testreg, fcsr_val); csrw fcsr, testreg                                                ;\
+inst destreg, imm_val(rs1)                                                              ;\
+nop                                                                                     ;\
+nop                                                                                     ;\
+csrr flagreg, fcsr                                                                      ;\
+RVTEST_SIGUPD_F(swreg,destreg,flagreg) 
 
 #define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) \
     LI(TEMP_REG,VAL);\
@@ -862,14 +938,14 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     RVTEST_SIGUPD(swreg,destreg,offset); \
     RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
 
-#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, code... ) \
+#define TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, code... ) \
     code; \
-    RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset); \
+    RVTEST_SIGUPD_F(swreg,destreg,flagreg); \
     RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
     
-#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, code... ) \
+#define TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, code... ) \
     code; \
-    RVTEST_SIGUPD_FID(swreg,destreg,flagreg,offset); \
+    RVTEST_SIGUPD_FID(swreg,destreg,flagreg); \
     RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)
 
 #define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \
@@ -888,30 +964,60 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     )
 
 //Tests for floating-point instructions with a single register operand
-#define TEST_FPSR_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
-      FLREG freg, val_offset(valaddr_reg); \
-      csrrwi x0, frm, rm; \
+#define TEST_FPSR_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
+      inst destreg, freg, rm; \
+      csrr flagreg, fcsr      ; \
+    )
+
+//Tests for floating-point instructions with a single register operand
+//This variant does not take the rm field and set it while writing the instruction
+#define TEST_FPSR_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
       inst destreg, freg; \
-      csrrs flagreg, fflags, x0; \
+      csrr flagreg, fcsr      ; \
     )
     
 //Tests for floating-point instructions with a single register operand and integer destination register
-#define TEST_FPID_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
-    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \
-      FLREG freg, val_offset(valaddr_reg); \
-      csrrwi x0, frm, rm; \
-      inst destreg, freg; \
-      csrrs flagreg, fflags, x0; \
+#define TEST_FPID_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg,load_instr) \
+    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
+      inst destreg, freg, rm; \
+      csrr flagreg, fcsr      ; \
+      )
+    
+//Tests for floating-point instructions with a single register operand and integer operand register
+#define TEST_FPIO_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
+      inst destreg, freg, rm; \
+      csrr flagreg, fcsr; \
     )
+
+//Tests for floating-point instructions with a single register operand and integer destination register
+//This variant does not take the rm field and set it while writing the instruction
+#define TEST_FPID_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg, val_offset, testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
+      inst destreg, freg; \
+      csrr flagreg, fcsr      ; \
+      )
     
 //Tests for floating-point instructions with a single register operand and integer operand register
-#define TEST_FPIO_OP( inst, destreg, freg, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
-      LREG freg, val_offset(valaddr_reg); \
-      csrrwi x0, frm, rm; \
+//This variant does not take the rm field and set it while writing the instruction
+#define TEST_FPIO_OP_NRM( inst, destreg, freg, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
       inst destreg, freg; \
-      csrrs flagreg, fflags, x0; \
+      csrr flagreg, fcsr; \
     )
 
 //Tests for instructions with register-register-immediate operands
@@ -938,33 +1044,45 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
       inst destreg, reg1, reg2; \
     )
 //Tests for floating-point instructions with register-register operand
-#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
-      FLREG freg1, val_offset(valaddr_reg); \
-      FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
-      csrrwi x0, frm, rm; \
+//This variant does not take the rm field and set it while writing the instruction
+#define TEST_FPRR_OP_NRM(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
       inst destreg, freg1, freg2; \
-      csrrs flagreg, fflags, x0; \
+      csrr flagreg, fcsr; \
+    )
+
+//Tests for floating-point instructions with register-register operand
+#define TEST_FPRR_OP(inst, destreg, freg1, freg2, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
+      inst destreg, freg1, freg2, rm; \
+      csrr flagreg, fcsr; \
     )
     
 //Tests for floating-point CMP instructions with register-register operand
-#define TEST_FCMP_OP(inst, destreg, freg1, freg2, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
-    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, offset, \
-      FLREG freg1, val_offset(valaddr_reg); \
-      FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
+#define TEST_FCMP_OP(inst, destreg, freg1, freg2, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_FID(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
       inst destreg, freg1, freg2; \
-      csrrs flagreg, fflags, x0; \
+      csrr flagreg, fcsr      ; \
     )
 
 //Tests for floating-point R4 type instructions
-#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm, correctval, valaddr_reg, val_offset, flagreg, swreg, offset, testreg) \
-    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, offset, \
-      FLREG freg1, val_offset(valaddr_reg); \
-      FLREG freg2, val_offset+FREGWIDTH(valaddr_reg); \
-      FLREG freg3, val_offset+2*FREGWIDTH(valaddr_reg); \
-      csrrwi x0, frm, rm; \
-      inst destreg, freg1, freg2, freg3; \
-      csrrs flagreg, fflags, x0; \
+#define TEST_FPR4_OP(inst, destreg, freg1, freg2, freg3, rm , fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg) \
+    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg, \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg1, val_offset, testreg); \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg2, (val_offset+FREGWIDTH), testreg); \
+      LOAD_MEM_VAL(FLREG, valaddr_reg, freg3, (val_offset+2*FREGWIDTH), testreg); \
+      LI(testreg, fcsr_val); csrw fcsr, testreg; \
+      inst destreg, freg1, freg2, freg3, rm; \
+      csrr flagreg, fcsr      ; \
     )
 
 #define TEST_CNOP_OP( inst, testreg, imm_val, swreg, offset) \
@@ -1146,7 +1264,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-    .if label == 3f                           ;\
+    .ifc label, 3f                           ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -1163,7 +1281,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-     .if label == 1b                          ;\
+     .ifc label, 1b                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -1189,7 +1307,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-    .if label == 3f                           ;\
+    .ifc label, 3f                           ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -1206,7 +1324,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-     .if label == 1b                          ;\
+     .ifc label, 1b                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -1232,7 +1350,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-    .if label == 3f                           ;\
+    .ifc label, 3f                           ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\
@@ -1249,7 +1367,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg,offset)
     .else                                     ;\
         .set num,0                            ;\
     .endif                                    ;\
-     .if label == 1b                          ;\
+     .ifc label, 1b                          ;\
         .set num,0                            ;\
     .endif                                    ;\
     .rept num                                 ;\