Repository: riscv-software-src/riscv-ctg (language: python)

Issue:
Add yaml file for CI, other fixes
-Add test-1.yml for CI
-Add hardcoded register testcases to dataset.cgf and rv32im.cgf (missing coverage in the division testcases https://github.com/riscv-non-isa/riscv-arch-test/issues/306)
-Update in generator.py- The missing coverage of hard coded register testcases will be taken care of only if a hard coded register is assigned in the op_comb node of a coverpoint of an instruction.
-Add 'warning' as a verbose level in main.py
-Update 'opcode' to 'mnemonics' in the cgf files
-Define rs1_val_data for c.ldsp in imc.yaml
-Define rs1_val_data and rs2_val_data for instructions from zicfiss.cgf in template.yaml


Discussion / hints:

Fix patch:
diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md
new file mode 100644
index 00000000..6b0e8c95
--- /dev/null
+++ b/.github/pull_request_template.md
@@ -0,0 +1,25 @@
+<FOR DOC UPDATES FILL ONLY DESCRIPTION AND RELATED ISSUES SECTION AND REMOVE THE OTHERS>
+
+#DEVELOPMENT PRs SHOULD BE TO DEV BRANCH ONLY
+
+## Description
+
+> Provide a detailed description of the changes performed by the PR.
+
+### Related Issues
+
+> Please list all the issues related to this PR. Use NA if no issues exist.
+
+### Update to/for Ratified/Unratified Extensions or to framework
+
+- [ ] Ratified
+- [ ] Unratified
+- [ ] Framework
+
+### List Extensions
+
+> List the extensions that your PR affects. In case of unratified extensions, please provide a link to the spec draft that was referred to make this PR.
+
+### Mandatory Checklist:
+
+  - [ ] Make sure to have created a suitable entry in the CHANGELOG.md under `[WIP-DEV]` section.
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
index 28b8f6f7..b8308b32 100644
--- a/.github/workflows/main.yml
+++ b/.github/workflows/main.yml
@@ -95,4 +95,3 @@ jobs:
           #          asset_content_type: application/pdf
           
       
-
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 14d689c5..7e13d0f7 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -2,6 +2,49 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
+Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
+versioned header while the `WIP-DEV` is left empty
+
+## [0.12.0] - 2024-02-22
+- Update generator.py to take care of hard coded register testcases only if a hard coded register is assigned in the op_comb node of a coverpoint of an instruction.
+- Add hardcoded register testcases to dataset.cgf and rv32im.cgf
+- Define rs1_val_data for c.ldsp in imc.yaml
+- Update "opcode" to "mnemonics" in the cgf files
+- Delete main.yml 
+- Update test.yml for CI
+- Define rs1_val_data for instructions from zicfiss.cgf in template.yaml
+- Add "warning" in the verbose definition
+- Add unratified Zicfiss extension
+- Add unratified Zicfilp extension
+- Add corner case of division for division operations for RV64
+- Fix csr_comb to write test information
+- Add unratified Zaamo subcomponent of A extension
+- Add unratified B extension
+- Fix issues with csr_comb
+- Minor fix in kslraw.u in rv32ip 
+- Fix incorrect 'sig:' entry in aes32dsi in template.yaml
+- Add sig and sz for instructions in template.yaml
+- Minor change of rd definition in c.lui in rv32ec
+- Minor fix in rv32i_k
+- Add rs1_val_data, rs2_val_data, imm_val_data for instructions in template.yaml
+- Comment xlenlim out of val_comb in rv32i_b, rv64i_b
+- Fix the formats of leading_ones, leading_zeros, trailing_ones, trailing_zeros for instructions in rv32i_b, rv32e_b
+- Add op_comb for instructions in rv32i_zcb
+- Add rs1_val_data for instructions in imc.yaml
+- Add op_comb and val_comb for instructions in rv32ic, rv64ic, rv32ec
+- Add corner case of division for division operations for RV32
+- Comment print statements out from generator.py
+- Fix whitespaces on empty lines in yaml template files.
+- Add unratified Zabha extension
+- Add support for unratified Zcmop extension
+- Add support for unratified Zimop extension
+- Add missing coverage for hard coded register testcases
+- Updated CONTRIBUTING.rst to capture the new git strategy adopted to follow a monthly release cadence.
+- Add Zifencei, Bit Manipulation and Privilege tests cgf files for RV32E
+- Add unratified Zacas extension
+- Add support for standard Atomic(A) extension
+
 ## [0.11.1] - 2023-08-15
 - Fixed hex values handling for K extensions
 - Fixed set indexing error during opcomb gen
diff --git a/CONTRIBUTING.rst b/CONTRIBUTING.rst
index 5e0df16b..391e2711 100644
--- a/CONTRIBUTING.rst
+++ b/CONTRIBUTING.rst
@@ -2,9 +2,9 @@
 
 .. highlight:: shell
 
-============
-Contributing
-============
+======================
+Developer Contribution
+======================
 
 Contributions are welcome, and they are greatly appreciated and credit will always be given.
 
@@ -30,15 +30,31 @@ If you are proposing a feature:
 * Remember that this is a volunteer-driven project, and that contributions
   are welcome :)
 
+Git Strategy
+------------
+
+The repo adopts a simple git strategy where all contributions to the repo are made to the ``dev``
+branch (i.e. all Pull-Requests must use ``dev`` as the target branch). On a monthly cadence (decided
+and controlled by the SIG-ARCH-TEST members) the ``dev`` branch will be merged to the ``main`` to by
+the official maintainers of the repo. This will create an official release capturing all the 
+development over the month into a single release.
+
+To implement the above strategy successfully the following needs be followed:
+
+* Developers: All pull-requests from developers must target the ``dev`` branch and the PR must
+contain an entry in the CHANGELOG.md file under `[WIP-DEV]` section.
+* Maintainers: When a making a release the maintainers shall assign semantic version number by
+updating the CHANGELOG and the respective python files before raising a PR from the `dev` to `main`.
+
 Get Started!
 ------------
 
 Ready to contribute? Here's how to set up `riscv_ctg` for local development.
 
 1. Fork the `riscv_ctg` repo on GitHub.
-2. Clone your fork locally::
+2. Clone your fork locally and checkout the ``dev`` branch::
 
-    $ git clone  https://github.com/riscv-software-src/riscv-ctg.git
+    $ git clone  https://github.com/riscv-software-src/riscv-ctg.git -b dev
 
 3. Create an issue and WIP merge request that creates a working branch for you::
 
@@ -58,33 +74,46 @@ Ready to contribute? Here's how to set up `riscv_ctg` for local development.
     $ git commit -m "Your detailed description of your changes."
     $ git push origin name-of-your-bugfix-or-feature
 
-6. Submit a merge request through the GitHub website.
+6. Submit a pull-request through the GitHub website. Make sure the pull-request is on the `dev`
+branch of the origin repo.
+
+7. Do not forget to make an entry in the CHANGELOG.md file under the `[WIP-DEV]` section
+highlighting the changes you have done.
 
 Merge Request Guidelines
-----------------------------
+------------------------
 
 Before you submit a merge request, check that it meets these guidelines:
 
-1. The merge request should include tests.
+1. The merge request should include tests (if any).
 2. If the merge request adds functionality, the docs should be updated. 
-3. The merge request should work for Python 3.6, 3.7 and 3.8, and for PyPy. 
-   and make sure that the tests pass for all supported Python versions.
+3. The target branch must always be the `dev` branch.
+
+
+Versioning (only for maintainers)
+---------------------------------
+
+When issuing pull requests to the main branch (from dev), a version entry in the CHANGELOG.md is mandatory. The tool adheres to
+the [`Semantic Versioning`](https://semver.org/spec/v2.0.0.html) scheme. Following guidelines must
+be followed while assigning a new version number :
+
+- Patch-updates: all doc updates (like typos, more clarification,etc).
+- Minor-updates: Fixing bugs in current features, adding new features which do not break current
+  features or working. Adding new extensions.
+- Major-updates: Backward incompatible changes.
 
-Tips
-----
+Note: You can have either a patch or minor or major update.
+Note: In case of a conflict, the maintainers will decide the final version to be assigned.
 
-To run a subset of tests::
+To update the version of the python package for deployment you can use `bumpversion` (installed
+using ``pip install bumpversion``)::
 
-    $ pytest tests.test_riscv_ctg
+$ bumpversion --no-tag --config-file setup.cfg patch # last arg can be: major or minor or patch
 
+If you don't have bumpversion installed you can manually update the version in the following files:
 
-Deploying
----------
+- change the value of variable ``current_version`` in `./setup.cfg`
+- change the value of variable ``__version__`` in `./riscv_ctg/__init__.py`
 
-A reminder for the maintainers on how to deploy.
-Make sure all your changes are committed.
-Then run::
 
-$ bumpversion --no-tag --config-file setup.cfg patch  # possible: major / minor / patch
-$ git push origin name-of-your-branch
 
diff --git a/riscv_ctg/__init__.py b/riscv_ctg/__init__.py
index e0d030a3..1d96eb63 100644
--- a/riscv_ctg/__init__.py
+++ b/riscv_ctg/__init__.py
@@ -4,4 +4,4 @@
 
 __author__ = """InCore Semiconductors Pvt Ltd"""
 __email__ = 'incorebot@gmail.com'
-__version__ = '0.11.1'
+__version__ = '0.12.0'
diff --git a/riscv_ctg/cross_comb.py b/riscv_ctg/cross_comb.py
index 2b8172f9..25112a26 100644
--- a/riscv_ctg/cross_comb.py
+++ b/riscv_ctg/cross_comb.py
@@ -51,7 +51,8 @@
     'pphrrformat' : '$instr $rd, $rs1, $rs2',
     'ppbrrformat' : '$instr $rd, $rs1, $rs2',
     'prrformat'   : '$instr ',
-    'prrrformat'  : '$instr'
+    'prrrformat'  : '$instr',
+    'dcasrformat'   : '$instr '
 }
 '''Dictionary to store instruction formats'''
 
@@ -497,4 +498,4 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, full_solution):
                                                         label = cov_label,
                                                         extension = extension
                                                         )
-                    )
\ No newline at end of file
+                    )
diff --git a/riscv_ctg/csr_comb.py b/riscv_ctg/csr_comb.py
index 2e83b3b6..ef75d388 100644
--- a/riscv_ctg/csr_comb.py
+++ b/riscv_ctg/csr_comb.py
@@ -15,7 +15,7 @@
     'or' : -3,
 }
 
-CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr']
+CSR_REGS = ['mvendorid', 'marchid', 'mimpid', 'mhartid', 'mstatus', 'misa', 'medeleg', 'mideleg', 'mie', 'mtvec', 'mcounteren', 'mscratch', 'mepc', 'mcause', 'mtval', 'mip', 'pmpcfg0', 'pmpcfg1', 'pmpcfg2', 'pmpcfg3', 'mcycle', 'minstret', 'mcycleh', 'minstreth', 'mcountinhibit', 'tselect', 'tdata1', 'tdata2', 'tdata3', 'dcsr', 'dpc', 'dscratch0', 'dscratch1', 'sstatus', 'sedeleg', 'sideleg', 'sie', 'stvec', 'scounteren', 'sscratch', 'sepc', 'scause', 'stval', 'sip', 'satp', 'vxsat', 'fflags', 'frm', 'fcsr', 'CSR_SRMCFG']
 csr_regs_capture_group = f'({"|".join(CSR_REGS)})'
 csr_regs_with_modifiers_capture_group = r'(write|old) *\( *"' + csr_regs_capture_group + r'" *\)'
 
@@ -260,7 +260,7 @@ class GeneratorCSRComb():
     '''
 
     def __init__(self, base_isa, xlen, randomize):
-        self.base_isa = base_isa
+        self.base_isa = base_isa + "_Zicsr"
         self.xlen = xlen
         self.randomize = randomize
 
@@ -366,7 +366,7 @@ def csr_comb(self, cgf_node):
                     instr_dict_csr_read_and_sig_upds.append({
                         'csr_reg': csr_reg, 'dest_reg': dest_reg, 'offset': offset
                     })
-                    offset += 4
+                    offset += (self.xlen >> 3)
 
                 instr_dict.append((instr_dict_csr_writes, instr_dict_csr_read_and_sig_upds, instr_dict_csr_restores))
 
@@ -413,8 +413,9 @@ def write_test(self, fprefix, cgf_node, usage_str, cov_label, instr_dict):
 
         case_str = ''.join([case_template.safe_substitute(xlen = self.xlen, num = i, cov_label = cov_label) for i, cond in enumerate(cgf_node.get('config', []))])
         test_str = part_template.safe_substitute(case_str = case_str, code = '\n'.join(code))
-
-        with open(fprefix + '_csr-comb.S', 'w') as fp:
+        fname = fprefix + '_csr-comb.S'
+        logger.debug("Writing Test to %s", str(fname))
+        with open(fname, 'w') as fp:
             fp.write(usage_str + csr_comb_test_template.safe_substitute(
                 isa = self.base_isa.upper(), # how to get the extensions?
                 test = test_str,
diff --git a/riscv_ctg/data/imc.yaml b/riscv_ctg/data/imc.yaml
index 571b6273..be5b1995 100644
--- a/riscv_ctg/data/imc.yaml
+++ b/riscv_ctg/data/imc.yaml
@@ -744,6 +744,7 @@ sd:
   ea_align_data: '[0,1,2,3,4,5,6,7]'
   rs2_val_data: 'gen_sign_dataset(xlen)'
   imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   template: |-
 
     // $comment
@@ -763,6 +764,7 @@ sw:
   formattype: 'sformat'
   ea_align_data: '[0,1,2,3]'
   rs2_val_data: 'gen_sign_dataset(xlen)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -783,6 +785,7 @@ sh:
   formattype: 'sformat'
   ea_align_data: '[0,1,2,3]'
   rs2_val_data: 'gen_sign_dataset(xlen)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -803,6 +806,7 @@ sb:
   formattype: 'sformat'
   ea_align_data: '[0,1,2,3]'
   rs2_val_data: 'gen_sign_dataset(xlen)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -823,6 +827,7 @@ ld:
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3,4,5,6,7]'
   imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   template: |-
 
     // $comment
@@ -842,6 +847,7 @@ lwu:
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
   imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   template: |-
 
     // $comment
@@ -860,6 +866,7 @@ lw:
     - I
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -879,6 +886,7 @@ lhu:
     - I
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
+  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -898,6 +906,7 @@ lh:
     - I
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -918,6 +927,7 @@ lbu:
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
   imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_usign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   template: |-
 
     // $comment
@@ -937,6 +947,7 @@ lb:
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
   imm_val_data: 'gen_sign_dataset(12)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   template: |-
 
     // $comment
@@ -973,6 +984,7 @@ jalr:
     - I
   formattype: 'iformat'
   ea_align_data: '[0,1,2,3]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
   imm_val_data: 'gen_sign_dataset(12)'
   template: |-
 
@@ -1077,7 +1089,7 @@ div:
     - IM
   formattype: 'rformat'
   operation:  'hex(int(abs(rs1_val)//abs(rs2_val))) if (rs1_val * rs2_val > 0) else hex(-int(abs(rs1_val)//abs(rs2_val))) if rs2_val != 0 else "0x"+("F"*int(xlen/4))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + [-(2**(xlen-1))]'
   rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
   template: |-
 
@@ -1120,7 +1132,7 @@ rem:
   formattype: 'rformat'
   #  operation: 'hex(rs1_val if rs2_val==0 or (rs1_val<rs2_val and rs2_val<0) else (rs1_val % rs2_val) & (2**(xlen)-1))'
   operation: 'hex(rs1_val) if rs2_val == 0 else hex(int(abs(rs1_val) % abs(rs2_val))) if rs1_val > 0 else hex(-int(abs(rs1_val) % abs(rs2_val)))'
-  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True) + [-(2**(xlen-1))]'
   rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
   template: |-
 
@@ -1595,6 +1607,7 @@ c.li:
   formattype: 'ciformat'
   operation : 'hex(sign_extend(imm_val,6))'
   imm_val_data: 'gen_sign_dataset(6)'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
 
     // $comment
@@ -1709,6 +1722,7 @@ c.lwsp:
     - IC
   formattype: 'ciformat'
   imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
 
     // $comment
@@ -1726,6 +1740,7 @@ c.ldsp:
     - IC
   formattype: 'ciformat'
   imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
 
     // $comment
@@ -1830,6 +1845,7 @@ c.jal:
     - IC
   formattype: 'cbformat'
   imm_val_data: 'list(filter(lambda x: (x >=4 and x<2030) if x>0 else (x<=-4 and x> -2030 ),[x*2 for x in gen_sign_dataset(11)]))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
 
     // $comment
@@ -1846,6 +1862,8 @@ c.jr:
   isa: 
     - IC
   formattype: 'crformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
 
     // $comment
@@ -1862,9 +1880,11 @@ c.jalr:
   isa: 
     - IC
   formattype: 'crformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
 
     // $comment
-    // opcode:c.jalr; op1:$rs1
+    // opcode: c.jalr; op1:$rs1
     TEST_CJALR_OP($testreg, $rs1, $swreg, $offset)
 
diff --git a/riscv_ctg/data/template.yaml b/riscv_ctg/data/template.yaml
index eb5a4218..d1f87c8d 100644
--- a/riscv_ctg/data/template.yaml
+++ b/riscv_ctg/data/template.yaml
@@ -5,15 +5,18 @@ metadata:
   all_regs_mx0: &all_regs_mx0 "['x'+str(x) for x in range(1,32 if 'e' not in base_isa else 16)]"
   c_regs: &c_regs "['x'+str(x) for x in range(8,16)]"
   pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]"
+  rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]"
 
 aes32dsi:
   sig:
-    sig:
     stride: 1
     sz: 'XLEN/8'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   xlen: [32]
   std_op:
   isa: 
@@ -34,6 +37,9 @@ aes32dsmi:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   xlen: [32]
   std_op:
   isa: 
@@ -54,6 +60,9 @@ aes32esi:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   xlen: [32]
   std_op:
   isa: 
@@ -74,6 +83,9 @@ aes32esmi:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   xlen: [32]
   std_op:
   isa: 
@@ -94,6 +106,9 @@ sm4ed:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   xlen: [32,64]
   std_op:
   isa: 
@@ -113,6 +128,9 @@ sm4ks:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   xlen: [32,64]
   std_op:
   isa: 
@@ -406,6 +424,7 @@ rol:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -453,6 +472,7 @@ zip:
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -476,6 +496,7 @@ unzip:
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -500,6 +521,8 @@ pack:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -539,6 +562,8 @@ packh:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -595,6 +620,8 @@ aes64ds:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -615,6 +642,8 @@ aes64dsm:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -635,6 +664,8 @@ aes64es:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -655,6 +686,8 @@ aes64esm:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -675,6 +708,8 @@ aes64ks1i:
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_usign_dataset(ceil(log(xlen,2)))'
   template: |-
 
     // $comment
@@ -831,10 +866,13 @@ rolw:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
   template: |-
 
     // $comment
@@ -876,6 +914,8 @@ packw:
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
   rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
   template: |-
 
     // $comment
@@ -908,6 +948,7 @@ add.uw:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -928,6 +969,7 @@ sh1add:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -948,6 +990,7 @@ sh1add.uw:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -968,6 +1011,7 @@ sh2add:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -988,6 +1032,7 @@ sh2add.uw:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1008,6 +1053,7 @@ sh3add:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1028,6 +1074,7 @@ sh3add.uw:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1048,6 +1095,7 @@ slli.uw:
   std_op:
   isa: 
     - IZba
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1072,6 +1120,7 @@ andn:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1475,6 +1524,7 @@ clz:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1492,6 +1542,7 @@ clzw:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1509,6 +1560,7 @@ cpop:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1526,6 +1578,7 @@ cpopw:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1543,6 +1596,7 @@ ctz:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1560,6 +1614,7 @@ ctzw:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1577,6 +1632,7 @@ max:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1622,6 +1678,7 @@ maxu:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1667,6 +1724,7 @@ min:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1712,6 +1770,7 @@ minu:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1783,6 +1842,7 @@ orc.b:
   std_op: orc.b
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1804,6 +1864,7 @@ orn:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -1905,6 +1966,7 @@ rev8:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -1930,6 +1992,7 @@ ror:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -2031,6 +2094,7 @@ rori:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2054,6 +2118,7 @@ roriw:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2077,6 +2142,7 @@ rorw:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -2177,6 +2243,7 @@ sext.b:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2194,6 +2261,7 @@ sext.h:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2215,6 +2283,7 @@ xnor:
     - IZk
     - IZkn
     - IZks
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -2288,6 +2357,7 @@ zext.h:
   std_op:
   isa: 
     - IZbb
+    - IB
   formattype: 'kformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
@@ -2479,6 +2549,7 @@ bclr:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -2569,10 +2640,12 @@ bclri:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
   rs1_val_data: 'zerotoxlen(xlen)+[-1]'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   template: |-
 
     // $comment
@@ -2677,10 +2750,12 @@ bexti:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
   rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   template: |-
 
     // $comment
@@ -2695,6 +2770,7 @@ binv:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -2787,10 +2863,12 @@ binvi:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
   rs1_val_data: 'zerotoxlen(xlen)+gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   template: |-
 
     // $comment
@@ -2805,6 +2883,7 @@ bset:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'rformat'
   rs1_op_data: *all_regs
   rs2_op_data: *all_regs
@@ -6626,7 +6705,9 @@ uradd64:
     TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)
 
 kadd64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6647,7 +6728,9 @@ kadd64:
     TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)
 
 ukadd64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6737,7 +6820,9 @@ ursub64:
     TEST_P64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $swreg, $offset, $testreg)
 
 ksub64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6758,7 +6843,9 @@ ksub64:
     TEST_PK64_PPP_OP($inst, $rd, $rd_hi, $rs1, $rs1_hi, $rs2, $rs2_hi, $correctval, $correctval_hi, $rs1_val, $rs1_val_hi, $rs2_val, $rs2_val_hi, $rs1, $swreg, $offset, $testreg)
 
 uksub64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6881,7 +6968,9 @@ umsr64:
     TEST_P64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
 
 kmar64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6904,7 +6993,9 @@ kmar64:
     TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 kmsr64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6927,7 +7018,9 @@ kmsr64:
     TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukmar64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -6950,7 +7043,9 @@ ukmar64:
     TEST_PK64_PNN_OP($inst, $rd, $rd_hi, $rs1, $rs2, $correctval, $correctval_hi, $rs1_val, $rs2_val, $rs1, $swreg, $offset, $testreg)
 
 ukmsr64:
-  stride: 3
+  sig:
+    stride: 3
+    sz: 'XLEN/8'
   xlen: [32,64]
   std_op:
   isa: 
@@ -10126,10 +10221,12 @@ bseti:
   std_op:
   isa: 
     - IZbs
+    - IB
   formattype: 'iformat'
   rs1_op_data: *all_regs
   rd_op_data: *all_regs
   rs1_val_data: 'zerotoxlen(xlen)'
+  imm_val_data: 'gen_imm_dataset(ceil(log(xlen,2)))'
   template: |-
 
     // $comment
@@ -10317,4 +10414,2250 @@ czero.nez:
 
     // $comment
     // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
-    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)    
+
+amoadd.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoand.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoswap.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoxor.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoor.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomin.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amominu.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomax.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+ 
+amomaxu.w:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoadd.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoand.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoswap.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoxor.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoor.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomin.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amominu.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomax.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+ 
+amomaxu.d:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - IA
+    - IZaamo
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amocas.w:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZacas
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *pair_regs
+  rd_op_data: *pair_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
+    TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);
+
+amocas.d_32:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32]
+  std_op:
+  isa:
+   - IZacas
+  bit_width: 64
+  dcas_profile: 'pnp'
+  formattype: 'dcasrformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *pair_regs
+  rd_op_data: *pair_regs
+  rs1_val_data: 'gen_sign_dataset(64)'
+  rs2_val_data: 'gen_sign_dataset(64)'
+
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi); swreg:$swreg; $offset
+    TEST_DCAS_OP(amocas.d, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset);
+
+amocas.d_64:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa:
+    - IZacas
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *pair_regs
+  rd_op_data: *pair_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
+    TEST_CAS_OP(amocas.d, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);
+
+amocas.q:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa:
+   - IZacas
+  bit_width: 128
+  dcas_profile: 'pnp'
+  formattype: 'dcasrformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(128)'
+  rs2_val_data: 'gen_sign_dataset(128)'
+
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest($rd, $rd_hi) addr:$rs1; src:($rs2, $rs2_hi); swap_val:($rs2_val, $rs2_val_hi), swreg:$swreg, $offset
+    TEST_DCAS_OP($inst, $rd, $rd_hi, $rs1, $rs2, $rs2_hi, $rs2_val, $rs2_val_hi, $swreg, $offset);
+
+c.lbu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: 'gen_usign_dataset(2)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
+    
+c.lhu:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: 'gen_usign_dataset(2)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
+  
+c.lh:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rd_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'clformat'
+  rs1_val_data: '[0]'
+  imm_val_data: 'gen_usign_dataset(2)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val
+    TEST_LOAD($swreg,$testreg,$index,$rs1,$rd,$imm_val,$offset,$inst,0)
+
+c.sb:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'csformat'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_usign_dataset(2)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
+
+c.sh:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'csformat'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: 'gen_usign_dataset(2)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val
+    TEST_STORE($swreg,$testreg,$index,$rs1,$rs2,$rs2_val,$imm_val,$offset,$inst,0)
+
+c.sext.b:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb_Zbb
+  formattype: 'ckformat'
+  rs1_op_data: *c_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
+    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
+
+c.sext.h:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb_Zbb
+  formattype: 'ckformat'
+  rs1_op_data: *c_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)+[65408]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
+    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
+
+c.zext.b:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'ckformat'
+  rs1_op_data: *c_regs
+  rs1_val_data: 'gen_usign_dataset(xlen)+[128]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
+    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
+
+c.zext.h:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb_Zbb
+  formattype: 'ckformat'
+  rs1_op_data: *c_regs
+  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
+    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
+
+c.zext.w:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb_Zba
+  formattype: 'ckformat'
+  rs1_op_data: *c_regs
+  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
+    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
+
+c.not:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - I_Zca_Zcb
+  formattype: 'kformat'
+  rs1_op_data: *c_regs
+  rs1_val_data: 'gen_usign_dataset(xlen)+[65408]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1=dest:$rs1 ; op1val:$rs1_val;
+    TEST_CRD_OP($inst, $rs1, $correctval, $rs1_val, $swreg, $offset, $testreg)
+
+c.mul:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_regs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IM_Zca_Zcb
+  formattype: 'crformat'
+  operation: 'hex((rs1_val * rs2_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst; op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val
+    TEST_CR_OP( $inst, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+amoadd.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoand.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoswap.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoxor.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoor.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomin.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amominu.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomax.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+ 
+amomaxu.b:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amocas.b:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZacas
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
+    TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);
+
+amoadd.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoand.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoswap.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoxor.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amoor.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomin.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amominu.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amomax.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+ 
+amomaxu.h:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IA
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_AMO_OP($inst, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $offset)
+
+amocas.h:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZacas
+  formattype: 'rformat'
+  rs1_op_data: *all_regs_mx0
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+
+  template: |-
+
+    // $comment
+    // opcode: $inst ; dest:$rd; addr:$rs1; src:$rs2; swap_val:$rs2_val; swreg:$swreg; $offset
+    TEST_CAS_OP($inst, $rd, $rs1, $rs2, $rs2_val, $swreg, $offset);
+
+mop.rr.0:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.1:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.2:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.3:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.4:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.5:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.6:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.rr.7:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val;  op2val:$rs2_val
+    TEST_RR_OP($inst, $rd, $rs1, $rs2, 0, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
+
+mop.r.0:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.1:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.2:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.3:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.4:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.5:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.6:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.7:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.8:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.9:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.10:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.11:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.12:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.13:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.14:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.15:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.16:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.17:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.18:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.19:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.20:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.21:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.22:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.23:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.24:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.25:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.26:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.27:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.28:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.29:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.30:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+mop.r.31:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *all_regs
+  rd_op_data: *all_regs
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZimop
+  operation: 'hex((rs1_val + imm_val) & (2**(xlen)-1))'
+  rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)'
+  imm_val_data: 'gen_sign_dataset(12)+ gen_sp_dataset(12)'
+  formattype: 'iformat'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val;  immval:$imm_val
+    TEST_R_OP( $inst, $rd, $rs1, 0, $rs1_val, $swreg, $offset, $testreg)
+
+c.mop.1:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x1, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.3:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x3, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.5:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x5, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.7:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x7, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.9:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x9, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.11:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x11, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.13:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x13, $imm_val, $swreg, $testreg, $offset)
+
+c.mop.15:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - ICZcmop
+  formattype: 'cjformat'
+  imm_val_data: 'gen_sign_dataset(6)'
+  template: |-
+    // $comment
+    // opcode:$inst; immval:$imm_val
+    TEST_CMOP_OP($inst, x15, $imm_val, $swreg, $testreg, $offset)
+
+lpad-m:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicfilp
+  formattype: 'uformat'
+  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
+  template: |-
+    // $comment
+    // opcode: lpad ; dest:x0; immval:$imm_val
+    TEST_LPAD_MMODE($testreg, $swreg, $offset, $imm_val)
+
+lpad-s:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicfilp
+  formattype: 'uformat'
+  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
+  template: |-
+    // $comment
+    // opcode: lpad ; dest:x0; immval:$imm_val
+    TEST_LPAD_SMODE($testreg, $swreg, $offset, $imm_val)
+
+lpad-u:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicfilp
+  formattype: 'uformat'
+  imm_val_data: 'gen_usign_dataset(20)+ gen_sp_dataset(20,False)'
+  template: |-
+    // $comment
+    // opcode: lpad ; dest:x0; immval:$imm_val
+    TEST_LPAD_UMODE($testreg, $swreg, $offset, $imm_val)
+
+sspushpopchk_u:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32, 64]
+  std_op:
+  isa:
+    - I_Zicfiss_Zicsr
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+    // $comment
+    TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode)
+
+sspushpopchk_s:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32, 64]
+  std_op:
+  isa:
+    - I_Zicfiss_Zicsr
+  formattype: 'rformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+    // $comment
+    TEST_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode)
+
+c.sspushpopchk_u:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32, 64]
+  std_op:
+  isa:
+    - IC_Zicfiss_Zicsr
+  formattype: 'crformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+    // $comment
+    TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Umode)
+
+c.sspushpopchk_s:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32, 64]
+  std_op:
+  isa:
+    - IC_Zicfiss_Zicsr
+  formattype: 'crformat'
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  template: |-
+    // $comment
+    TEST_C_SSPUSH_SSPOP_OP($swreg, $offset, $rs2_val, Smode)
+
+ssamoswap.w_s:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IA_Zicfiss_Zicsr
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+    // $comment
+    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
+    #ifndef ZICFISS_SETUP_DONE
+    .set zicfiss_setup_done, 0
+    #define ZICFISS_SETUP_DONE 1
+    #endif
+    TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode)
+
+ssamoswap.d_s:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa:
+    - IA_Zicfiss_Zicsr
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+    // $comment
+    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
+    #ifndef ZICFISS_SETUP_DONE
+    .set zicfiss_setup_done, 0
+    #define ZICFISS_SETUP_DONE 1
+    #endif
+    TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Smode)
+
+ssamoswap.w_u:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IA_Zicfiss_Zicsr
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+    // $comment
+    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
+    #ifndef ZICFISS_SETUP_DONE
+    .set zicfiss_setup_done, 0
+    #define ZICFISS_SETUP_DONE 1
+    #endif
+    TEST_SSAMOSWAP_OP(ssamoswap.w, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode)
+
+ssamoswap.d_u:
+  sig:
+    stride: 2
+    sz: 'XLEN/8'
+  xlen: [64]
+  std_op:
+  isa:
+    - IA_Zicfiss_Zicsr
+  formattype: 'rformat'
+  rs1_op_data: *all_regs
+  rs2_op_data: *all_regs
+  rd_op_data: *all_regs
+  rs1_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)+gen_usign_dataset(xlen)'
+  template: |-
+    // $comment
+    // opcode: $inst ; dest: $rd op1:$rs1; op2:$rs2; op1val:$rs1_val; op2val:$rs2_val; $swreg; $testreg; Priv
+    #ifndef ZICFISS_SETUP_DONE
+    .set zicfiss_setup_done, 0
+    #define ZICFISS_SETUP_DONE 1
+    #endif
+    TEST_SSAMOSWAP_OP(ssamoswap.d, $rd, $rs1, $rs2, $rs1_val, $rs2_val, $swreg, $testreg, Umode)
+
+ssrdp_s:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa:
+    - I_Zicfiss_Zicsr
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  formattype: 'rformat'
+  template: |-
+    // $comment
+    // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv
+    #ifndef ZICFISS_SETUP_DONE
+    .set zicfiss_setup_done, 0
+    #define ZICFISS_SETUP_DONE 1
+    #endif
+    TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Smode)
+
+ssrdp_u:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *all_regs_mx0
+  xlen: [32,64]
+  std_op:
+  isa:
+    - I_Zicfiss_Zicsr
+  rs1_val_data: 'gen_sign_dataset(xlen)'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  formattype: 'rformat'
+  template: |-
+    // $comment
+    // opcode:ssrdp; dest: $rd; $swreg; $testreg; Priv
+    #ifndef ZICFISS_SETUP_DONE
+    .set zicfiss_setup_done, 0
+    #define ZICFISS_SETUP_DONE 1
+    #endif
+    TEST_SSRDP_OP(ssrdp, $rd, $swreg, $testreg, Umode)
diff --git a/riscv_ctg/dsp_function.py b/riscv_ctg/dsp_function.py
index 7f892243..4b0f12bd 100644
--- a/riscv_ctg/dsp_function.py
+++ b/riscv_ctg/dsp_function.py
@@ -175,9 +175,14 @@ def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile):
     else:
         bit_width1, bit_width2 = _bit_width, _bit_width
 
-    rs1_width = 64 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen
-    rs2_width = 64 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen
-    rd_width  = 64 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen
+    if xlen == 32:
+        rs1_width = 64 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen
+        rs2_width = 64 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen
+        rd_width  = 64 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen
+    else:
+        rs1_width = 128 if len(p64_profile) >= 3 and p64_profile[1]=='p' else xlen
+        rs2_width = 128 if len(p64_profile) >= 3 and p64_profile[2]=='p' else xlen
+        rd_width  = 128 if len(p64_profile) >= 3 and p64_profile[0]=='p' else xlen
 
     for instr in instr_dict:
         if 'rs1' in instr:
diff --git a/riscv_ctg/generator.py b/riscv_ctg/generator.py
index 035b97d5..d666b408 100644
--- a/riscv_ctg/generator.py
+++ b/riscv_ctg/generator.py
@@ -12,6 +12,7 @@
 import struct
 import sys
 import itertools
+import re
 
 one_operand_finstructions = ["fsqrt.s","fmv.x.w","fcvt.wu.s","fcvt.w.s","fclass.s","fcvt.l.s","fcvt.lu.s","fcvt.s.l","fcvt.s.lu"]
 two_operand_finstructions = ["fadd.s","fsub.s","fmul.s","fdiv.s","fmax.s","fmin.s","feq.s","flt.s","fle.s","fsgnj.s","fsgnjn.s","fsgnjx.s"]
@@ -58,6 +59,7 @@ def get_rm(opcode):
     'cbformat': ['rs1'],
     'cjformat': [],
     'kformat': ['rs1','rd'],
+    'ckformat': ['rs1'],
     # 'frformat': ['rs1', 'rs2', 'rd'],
     'fsrformat': ['rs1', 'rd'],
     # 'fr4format': ['rs1', 'rs2', 'rs3', 'rd'],
@@ -77,7 +79,8 @@ def get_rm(opcode):
     'pphrrformat': ['rs1', 'rs2', 'rd'],
     'ppbrrformat': ['rs1', 'rs2', 'rd'],
     'prrformat': ['rs1', 'rs2', 'rd'],
-    'prrrformat': ['rs1', 'rs2', 'rs3', 'rd']
+    'prrrformat': ['rs1', 'rs2', 'rs3', 'rd'],
+    'dcasrformat': ['rs1', 'rs2', 'rd']
 }
 ''' Dictionary mapping instruction formats to operands used by those formats '''
 
@@ -103,6 +106,7 @@ def get_rm(opcode):
     'cbformat': "['rs1_val', 'imm_val']",
     'cjformat': "['imm_val']",
     'kformat': "['rs1_val']",
+    'ckformat': "['rs1_val']",
     # 'frformat': "['rs1_val', 'rs2_val', 'rm_val', 'fcsr']",
     'fsrformat': "['rs1_val', 'fcsr'] + get_rm(opcode) + \
         ([] if not is_nan_box else ['rs1_nan_prefix'])",
@@ -123,7 +127,8 @@ def get_rm(opcode):
     'pphrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 16)',
     'ppbrrformat': '["rs1_val"] + simd_val_vars("rs2", xlen, 8)',
     'prrformat': '["rs1_val", "rs2_val"]',
-    'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']"
+    'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']",
+    'dcasrformat': '["rs1_val", "rs2_val"]'
 }
 ''' Dictionary mapping instruction formats to operand value variables used by those formats '''
 
@@ -271,10 +276,15 @@ def opcomb(self, cgf):
         to ensure that all those registers occur atleast once in the respective
         operand/destination location in the instruction. These contraints are
         then supplied to the solver for solutions
-
+        
         If randomization is enabled we use the ``MinConflictsSolver`` solver to
         find solutions.
 
+        If harcoded registers are given in the cgf file, then for the conditions other
+        than the first one, there will be No Solution. To solve that problem, some code
+        is written which will find the required register in the condition and generate the
+        solution normally.
+        
         :param cgf: a covergroup in cgf format containing the set of coverpoints to be satisfied.
 
         :type cgf: dict
@@ -284,6 +294,7 @@ def opcomb(self, cgf):
         logger.debug(self.opcode + ' : Generating OpComb')
         solutions = []
         op_conds = {}
+        opcomb_value = cgf.get("op_comb")
         if "op_comb" in cgf:
             op_comb = set(cgf["op_comb"])
         else:
@@ -323,9 +334,26 @@ def comb_constraint(*args):
                 problem.addConstraint(AllDifferentConstraint())
             count = 0
             solution = problem.getSolution()
-            while (solution is None and count < 5):
+            while solution is None and count < 5:
+                if opcomb_value:
+                    for i in opcomb_value:
+                        opcomb_match = re.search(r'x\d{1,2}', i)
+                        if opcomb_match is not None:
+                            pattern = r'(?:rs1|rs2|rd) == "(x\d+)"'
+                            matches = re.findall(pattern, cond)
+                            if not matches or any(int(match[1:]) > 31 for match in matches):
+                                result = None
+                            else:
+                                result = matches
+                                for match in result:
+                                    op_conds['rs1'].add(match)
+                                    op_conds['rs2'].add(match)
+                                    op_conds['rd'].add(match)
+                                op_comb.add(cond)
+                                break
                 solution = problem.getSolution()
                 count = count + 1
+
             if solution is None:
                 if individual:
                     if nodiff:
@@ -336,7 +364,6 @@ def comb_constraint(*args):
                 else:
                     individual = True
                 continue
-
             op_tuple = []
             for key in self.op_vars:
                 op_tuple.append(solution[key])
@@ -873,6 +900,14 @@ def eval_inst_coverage(coverpoints,instr):
             elif 'bit_width' in self.opnode:
                 concat_simd_data(final_instr, self.xlen, self.opnode['bit_width'])
 
+        '''
+        Zacas introduces double xlen cas operations that need paired source and destination registers
+        '''
+        if any('Zacas' in isa for isa in self.opnode['isa']):
+            if 'dcas_profile' in self.opnode:
+                gen_pair_reg_data(final_instr, self.xlen, self.opnode['bit_width'], self.opnode['dcas_profile'])
+
+
         return final_instr
 
     def valreg(self,instr_dict):
@@ -901,6 +936,9 @@ def valreg(self,instr_dict):
             if self.xlen == 32 and 'p64_profile' in self.opnode:
                 p64_profile = self.opnode['p64_profile']
                 paired_regs = self.opnode['p64_profile'].count('p')
+            if 'dcas_profile' in self.opnode:
+                dcas_profile = self.opnode['dcas_profile']
+                paired_regs = self.opnode['dcas_profile'].count('p')
 
             regset = e_regset if 'e' in self.base_isa else default_regset
             total_instr = len(instr_dict)
@@ -1021,6 +1059,9 @@ def swreg(self, instr_dict):
         if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
             paired_regs = self.opnode['p64_profile'].count('p')
+        if 'dcas_profile' in self.opnode:
+            dcas_profile = self.opnode['dcas_profile']
+            paired_regs = self.opnode['dcas_profile'].count('p')
 
         regset = e_regset if 'e' in self.base_isa else default_regset
         total_instr = len(instr_dict)
@@ -1107,6 +1148,9 @@ def testreg(self, instr_dict):
         if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
             paired_regs = p64_profile.count('p')
+        if 'dcas_profile' in self.opnode:
+            dcas_profile = self.opnode['dcas_profile']
+            paired_regs = dcas_profile.count('p')
 
         for instr in instr_dict:
             if 'rs1' in instr and instr['rs1'] in available_reg:
@@ -1159,6 +1203,11 @@ def correct_val(self,instr_dict):
             if len(p64_profile) >= 3 and p64_profile[0]=='p':
                 for i in range(len(instr_dict)):
                     instr_dict[i]['correctval_hi'] = '0'
+        if 'dcas_profile' in self.opnode:
+            dcas_profile = self.opnode['dcas_profile']
+            if len(dcas_profile) >= 3 and dcas_profile[0]=='p':
+                for i in range(len(instr_dict)):
+                    instr_dict[i]['correctval_hi'] = '0'
         if self.fmt in ['caformat','crformat']:
             normalise = lambda x,y: 0 if y['rs1']=='x0' else x
         else:
@@ -1186,6 +1235,11 @@ def reformat_instr(self, instr_dict):
             # instr_dict is already in the desired format for instructions that perform SIMD operations, or Zpsfoperand instructions in RV32.
             if 'bit_width' in self.opnode or (self.xlen == 32 and 'p64_profile' in self.opnode):
                 return instr_dict
+        if any('Zacas' in isa for isa in self.opnode['isa']):
+            # instr_dict is already in the desired format for Zacas dcas instructions
+            if 'bit_width' in self.opnode or 'dcas_profile' in self.opnode:
+                return instr_dict
+        
         # Fix all K instructions to be unsigned to output unsigned hex values into the test. Its
         # only a cosmetic difference and has no impact on coverage
         is_unsigned = any('IZk' in isa for isa in self.opnode['isa'])
@@ -1205,14 +1259,14 @@ def reformat_instr(self, instr_dict):
                 if 'val' in field and field != 'correctval' and field != 'valaddr_reg' and \
                     field != 'val_section' and field != 'val_offset' and field != 'rm_val':
                     value = (instr_dict[i][field]).strip()
-                    print(value)
+                    #print(value)
                     if '0x' in value:
                         value = '0x' + value[2:].zfill(int(self.xlen/4))
                         value = struct.unpack(size, bytes.fromhex(value[2:]))[0]
                     else:
                         value = int(value)
 #                    value = '0x' + struct.pack(size,value).hex()
-                    print("test",hex(value))
+                    #print("test",hex(value))
                     instr_dict[i][field] = hex(value)
         return instr_dict
 
@@ -1269,9 +1323,10 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str):
 
         if any('IP' in isa for isa in self.opnode['isa']):
             code.append("RVTEST_VXSAT_ENABLE()")
-
         if self.xlen == 32 and 'p64_profile' in self.opnode:
             p64_profile = self.opnode['p64_profile']
+        if 'dcas_profile' in self.opnode:
+            dcas_profile = self.opnode['dcas_profile']
 
         n = 0
         is_int_src = any([self.opcode.endswith(x) for x in ['.x','.w','.l','.wu','.lu']])
@@ -1336,4 +1391,4 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str):
         sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute(
             {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n")
         with open(file_name,"w") as fd:
-            fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label))
+            fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label))
\ No newline at end of file
diff --git a/riscv_ctg/main.py b/riscv_ctg/main.py
index b127689b..0e0bc30d 100644
--- a/riscv_ctg/main.py
+++ b/riscv_ctg/main.py
@@ -10,7 +10,7 @@
 from riscv_isac.cgf_normalize import expand_cgf
 @click.command()
 @click.version_option(prog_name="RISC-V Compliance Test Generator",version=__version__)
-@click.option('--verbose', '-v', default='error', help='Set verbose level', type=click.Choice(['info','error','debug'],case_sensitive=False))
+@click.option('--verbose', '-v', default='error', help='Set verbose level', type=click.Choice(['info','error','debug','warning'],case_sensitive=False))
 @click.option('--out-dir', '-d', default='./', type=click.Path(resolve_path=True,writable=True), help='Output directory path')
 @click.option('--randomize','-r', default=False , is_flag='True', help='Randomize Outputs.')
 @click.option('--cgf','-cf',multiple=True,type=click.Path(exists=True,resolve_path=True,readable=True),help="Path to the cgf file(s). Multiple allowed.")
diff --git a/sample_cgfs/dataset.cgf b/sample_cgfs/dataset.cgf
index bf0f52e4..2d3565ea 100644
--- a/sample_cgfs/dataset.cgf
+++ b/sample_cgfs/dataset.cgf
@@ -224,7 +224,18 @@ datasets:
     'rs2 == rd != rs1': 0
     'rs1 == rs2 == rd': 0
     'rs1 != rs2  and rs1 != rd and rs2 != rd': 0
-    
+
+  div_hardcoded_opcomb: &div_hardcoded_opcomb
+    'rs1 == rd != rs2 and rd != "x0"': 0
+    'rs1 == rd != rs2 and rd == "x0"': 0
+    'rs1 == "x0" != rd': 0
+    'rd == "x0" != rs1': 0
+
+  ramofmt_op_comb: &ramofmt_op_comb
+    'rs1 == rd != rs2': 0
+    'rs2 == rd != rs1': 0
+    'rs1 != rs2  and rs1 != rd and rs2 != rd': 0
+
   r4fmt_op_comb: &r4fmt_op_comb
     'rs1 == rs2 == rs3 == rd': 0
     'rs1 == rs2 == rs3 != rd': 0
@@ -246,12 +257,22 @@ datasets:
   sfmt_op_comb: &sfmt_op_comb
     'rs1 == rs2': 0
     'rs1 != rs2': 0
+
+  r0fmt_op_comb: &r0fmt_op_comb
+    'rs1 == 0': 0
+    'rs1 != 0': 0
   
   base_rs1val_sgn: &base_rs1val_sgn
     'rs1_val == (-2**(xlen-1))': 0
     'rs1_val == 0': 0
     'rs1_val == (2**(xlen-1)-1)': 0
     'rs1_val == 1': 0
+
+  base_rs1val_sgn_rs2val_zero: &base_rs1val_sgn_rs2val_zero
+    'rs1_val == (-2**(xlen-1)) and rs2_val == 0': 0
+    'rs1_val == 0 and rs2_val == 0': 0
+    'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0
+    'rs1_val == 1 and rs2_val == 0': 0
   
   base_rs2val_sgn: &base_rs2val_sgn
     'rs2_val == (-2**(xlen-1))': 0
@@ -288,6 +309,9 @@ datasets:
     'rs1_val < 0 and rs2_val > 0': 0
     'rs1_val == rs2_val': 0
     'rs1_val != rs2_val': 0
+
+  div_corner_case: &div_corner_case
+    'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0
   
   rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn
     'rs1_val > 0 and rs2_val > 0': 0
@@ -488,3 +512,52 @@ datasets:
     'walking_ones("rs2_val", 64, signed=False)': 0
     'walking_zeros("rs2_val", 64, signed=False)': 0
     'alternate("rs2_val",64, signed=False)': 0
+
+  rvp128_rs1val_sgn: &rvp128_rs1val_sgn
+    'rs1_val == 0': 0
+    'rs1_val == 1': 0
+
+  rvp128_rs2val_sgn: &rvp128_rs2val_sgn
+    'rs2_val == 0': 0
+    'rs2_val == 1': 0
+
+  rvp128_rs1val_walking_sgn: &rvp128_rs1val_walking_sgn
+    'walking_ones("rs1_val", 128)': 0
+    'walking_zeros("rs1_val", 128)': 0
+    'alternate("rs1_val",128)': 0
+
+  rvp128_rs2val_walking_sgn: &rvp128_rs2val_walking_sgn
+    'walking_ones("rs2_val", 128)': 0
+    'walking_zeros("rs2_val", 128)': 0
+    'alternate("rs2_val",128)': 0
+
+  zacas_op_comb: &zacas_op_comb
+    'rs1 != rs2  and rs1 != rd and rs2 != rd': 0
+
+  zacas_dcas_rs1val_sgn: &zacas_dcas_rs1val_sgn
+    'rs1_val == 0': 0
+    'rs1_val == 1': 0
+
+  zacas_dcas_rs2val_sgn: &zacas_dcas_rs2val_sgn
+    'rs2_val == 0': 0
+    'rs2_val == 1': 0
+
+  zacas128_rs1val_walking_sgn: &zacas128_rs1val_walking_sgn
+    'walking_ones("rs1_val", 128)': 0
+    'walking_zeros("rs1_val", 128)': 0
+    'alternate("rs1_val",128)': 0
+
+  zacas128_rs2val_walking_sgn: &zacas128_rs2val_walking_sgn
+    'walking_ones("rs2_val", 128)': 0
+    'walking_zeros("rs2_val", 128)': 0
+    'alternate("rs2_val",128)': 0
+
+  zacas64_rs1val_walking_sgn: &zacas64_rs1val_walking_sgn
+    'walking_ones("rs1_val", 64)': 0
+    'walking_zeros("rs1_val", 64)': 0
+    'alternate("rs1_val",64)': 0
+
+  zacas64_rs2val_walking_sgn: &zacas64_rs2val_walking_sgn
+    'walking_ones("rs2_val", 64)': 0
+    'walking_zeros("rs2_val", 64)': 0
+    'alternate("rs2_val",64)': 0
diff --git a/sample_cgfs/rv32e.cgf b/sample_cgfs/rv32e.cgf
index 033d4b3b..31b4c8af 100644
--- a/sample_cgfs/rv32e.cgf
+++ b/sample_cgfs/rv32e.cgf
@@ -3,13 +3,13 @@
 fence:
   config: 
     - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     fence: 0
 
 addi:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       addi: 0
     rs1: 
       <<: *rv32e_regs
@@ -26,7 +26,7 @@ addi:
 slti:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       slti: 0
     rs1: 
       <<: *rv32e_regs
@@ -43,7 +43,7 @@ slti:
 sltiu:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sltiu: 0
     rs1: 
       <<: *rv32e_regs
@@ -60,7 +60,7 @@ sltiu:
 andi:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       andi: 0
     rs1: 
       <<: *rv32e_regs
@@ -77,7 +77,7 @@ andi:
 ori:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       ori: 0
     rs1: 
       <<: *rv32e_regs
@@ -94,7 +94,7 @@ ori:
 xori:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       xori: 0
     rs1: 
       <<: *rv32e_regs
@@ -111,7 +111,7 @@ xori:
 slli:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       slli: 0
     rs1: 
       <<: *rv32e_regs
@@ -131,7 +131,7 @@ slli:
 srai:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       srai: 0
     rs1: 
       <<: *rv32e_regs
@@ -151,7 +151,7 @@ srai:
 srli:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       srli: 0
     rs1: 
       <<: *rv32e_regs
@@ -171,7 +171,7 @@ srli:
 add:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       add: 0
     rs1: 
       <<: *rv32e_regs
@@ -190,7 +190,7 @@ add:
 sub:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sub: 0
     rs1: 
       <<: *rv32e_regs
@@ -209,7 +209,7 @@ sub:
 slt:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       slt: 0
     rs1: 
       <<: *rv32e_regs
@@ -228,7 +228,7 @@ slt:
 sltu:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sltu: 0
     rs1: 
       <<: *rv32e_regs
@@ -247,7 +247,7 @@ sltu:
 and:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       and: 0
     rs1: 
       <<: *rv32e_regs
@@ -266,7 +266,7 @@ and:
 or:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       or: 0
     rs1: 
       <<: *rv32e_regs
@@ -285,7 +285,7 @@ or:
 xor:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       xor: 0
     rs1: 
       <<: *rv32e_regs
@@ -304,7 +304,7 @@ xor:
 sll:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sll: 0
     rs1: 
       <<: *rv32e_regs
@@ -326,7 +326,7 @@ sll:
 srl:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       srl: 0
     rs1: 
       <<: *rv32e_regs
@@ -348,7 +348,7 @@ srl:
 sra:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sra: 0
     rs1: 
       <<: *rv32e_regs
@@ -370,7 +370,7 @@ sra:
 beq:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       beq: 0
     rs1: 
       <<: *rv32e_regs
@@ -387,7 +387,7 @@ beq:
 bge:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       bge: 0
     rs1: 
       <<: *rv32e_regs
@@ -404,7 +404,7 @@ bge:
 bgeu:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       bgeu: 0
     rs1: 
       <<: *rv32e_regs
@@ -421,7 +421,7 @@ bgeu:
 blt:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       blt: 0
     rs1: 
       <<: *rv32e_regs
@@ -438,7 +438,7 @@ blt:
 bltu:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       bltu: 0
     rs1: 
       <<: *rv32e_regs
@@ -455,7 +455,7 @@ bltu:
 bne:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       bne: 0
     rs1: 
       <<: *rv32e_regs
@@ -472,7 +472,7 @@ bne:
 lhu-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       lhu: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -496,7 +496,7 @@ lhu-align:
 lh-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       lh: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -520,7 +520,7 @@ lh-align:
 lbu-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       lbu: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -552,7 +552,7 @@ lbu-align:
 lb-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       lb: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -584,7 +584,7 @@ lb-align:
 lw-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       lw: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -605,7 +605,7 @@ lw-align:
 sh-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sh: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -632,7 +632,7 @@ sh-align:
 sb-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sb: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -667,7 +667,7 @@ sb-align:
 sw-align:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       sw: 0
     rs1: 
       <<: *rv32e_regs_mx0
@@ -690,7 +690,7 @@ sw-align:
 auipc:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       auipc: 0
     rd: 
       <<: *rv32e_regs
@@ -707,7 +707,7 @@ auipc:
 lui:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       lui: 0
     rd: 
       <<: *rv32e_regs
@@ -724,7 +724,7 @@ lui:
 jal:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       jal: 0
     rd: 
       <<: *rv32e_regs
@@ -737,7 +737,7 @@ jal:
 jalr:
     config: 
       - check ISA:=regex(.*E.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       jalr: 0
     rs1:
       <<: *rv32e_regs_mx0
diff --git a/sample_cgfs/rv32e_b.cgf b/sample_cgfs/rv32e_b.cgf
new file mode 100644
index 00000000..6ab80eb1
--- /dev/null
+++ b/sample_cgfs/rv32e_b.cgf
@@ -0,0 +1,705 @@
+sh1add:
+    config: 
+      - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True
+    mnemonics: 
+      sh1add: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+sh2add:
+    config: 
+      - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True
+    mnemonics: 
+      sh2add: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+        
+sh3add:
+    config: 
+      - check ISA:=regex(.*E.*Zba.*) ;def RVTEST_E = True
+    mnemonics: 
+      sh3add: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+        
+xnor:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      xnor: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen,signed=False)': 0
+        <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn]
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0
+        
+zext.h_32:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      zext.h: 0
+    base_op: pack
+    p_op_cond: rs2 == x0
+    rs1: 
+      <<: *rv32e_regs
+    rd: 
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x80': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+        'uniform_random(20, 100, ["rs1_val"], [xlen])': 0
+andn:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      andn: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *rs2val_walking_unsgn]
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0
+        'bitmanip_dataset(xlen,["rs1_val","rs2_val"],False)': 0
+
+clz:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      clz: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd: 
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
+
+ctz:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      ctz: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd: 
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
+        
+cpop:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      cpop: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd: 
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
+        
+max:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      max: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+maxu:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      maxu: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen,signed=False)': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+        
+min:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      min: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+        
+minu:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      minu: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen,signed=False)': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+        
+orcb_32:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      orc.b: 0
+    base_op: gorci
+    p_op_cond: imm_val == 7
+    rs1: 
+      <<: *rv32e_regs
+    rd: 
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'rs1_val == 0x1020408': 0
+      'rs1_val == 0x2040801': 0
+      'rs1_val == 0x4080102': 0
+      'rs1_val == 0x8010204': 0
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+
+        
+orn:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      orn: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
+      abstract_comb:
+        'bitmanip_dataset(xlen,signed=False)': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0
+
+rev8_32:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      rev8: 0
+    base_op: grevi
+    p_op_cond: imm_val == 24
+    rs1: 
+      <<: *rv32e_regs
+    rd: 
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'rs1_val == 0x1020408': 0
+      'rs1_val == 0x2040801': 0
+      'rs1_val == 0x4080102': 0
+      'rs1_val == 0x8010204': 0
+      abstract_comb:
+        'leading_ones(32, ["rs1_val"], [32])': 0
+        'trailing_ones(32, ["rs1_val"], [32])': 0
+        'leading_zeros(32, ["rs1_val"], [32])': 0
+        'trailing_zeros(32, ["rs1_val"], [32])': 0
+        'bitmanip_dataset(xlen,["rs1_val"],signed=False)': 0
+        
+rol:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      rol: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:      
+        'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+
+ror:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*I.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*I.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      ror: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:      
+        'leading_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        'trailing_ones(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        'leading_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        'trailing_zeros(32, ["rs1_val","rs2_val"],[xlen,xlen])': 0
+        
+rori:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkb.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*I.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*I.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      rori: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:      
+        'leading_ones(32, ["rs1_val","imm_val"],[32,5])': 0
+        'trailing_ones(32, ["rs1_val","imm_val"],[32,5])': 0
+        'leading_zeros(32, ["rs1_val","imm_val"],[32,5])': 0
+        'trailing_zeros(32, ["rs1_val","imm_val"],[32,5])': 0
+
+sext.b:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      sext.b: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x8000': 0
+      abstract_comb:      
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+        'uniform_random(20, 100, ["rs1_val"], [xlen])': 0
+
+sext.h:
+    config: 
+      - check ISA:=regex(.*E.*Zbb.*) ;def RVTEST_E = True
+    mnemonics: 
+      sext.h: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x80': 0
+      'rs1_val == 0xff80': 0
+      abstract_comb:      
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+        'uniform_random(20, 100, ["rs1_val"], [xlen])': 0
+
+clmul:
+    config: 
+      - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkc.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+    mnemonics: 
+      clmul: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      'rs1_val==1 and rs2_val==1': 0
+      'rs1_val==1 and rs2_val==0': 0 
+      'rs1_val==1 and rs2_val==0x1000': 0
+      'rs1_val==0 and rs2_val==1': 0
+      'rs1_val==0 and rs2_val==0': 0 
+      'rs1_val==0 and rs2_val==0x1000': 0
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0
+        
+clmulh:
+    config: 
+      - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zbkc.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zk.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zkn.*) ;def RVTEST_E = True
+      - check ISA:=regex(.*E.*Zks.*) ;def RVTEST_E = True
+    mnemonics: 
+      clmulh: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      'rs1_val==1 and rs2_val==1': 0
+      'rs1_val==1 and rs2_val==0': 0 
+      'rs1_val==1 and rs2_val==0x1000': 0
+      'rs1_val==0 and rs2_val==1': 0
+      'rs1_val==0 and rs2_val==0': 0 
+      'rs1_val==0 and rs2_val==0x1000': 0
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0
+
+        
+clmulr:
+    config: 
+      - check ISA:=regex(.*E.*Zbc.*) ;def RVTEST_E = True
+    mnemonics: 
+      clmulr: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      'rs1_val==1 and rs2_val==1': 0
+      'rs1_val==1 and rs2_val==0': 0 
+      'rs1_val==1 and rs2_val==0x1000': 0
+      'rs1_val==0 and rs2_val==1': 0
+      'rs1_val==0 and rs2_val==0': 0 
+      'rs1_val==0 and rs2_val==0x1000': 0
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [xlen, xlen])': 0
+
+bclr:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      bclr: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
+        'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
+        'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
+        'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+
+        
+bclri:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      bclri: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:      
+#        'xlenlim("rs1_val", xlen)': 0
+        'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+
+        
+bext:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      bext: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
+        'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
+        'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
+        'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+
+        
+bexti:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      bexti: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:      
+#        'xlenlim("rs1_val", xlen)': 0
+        'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+
+        
+binv:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      binv: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
+        'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
+        'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
+        'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+
+        
+binvi:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      binvi: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:      
+#        'xlenlim("rs1_val", xlen)': 0
+        'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+        
+bset:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      bset: 0
+    rs1: 
+      <<: *rv32e_regs
+    rs2: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      abstract_comb:
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
+        'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
+        'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
+        'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "rs2_val"], [32,5])': 0
+        <<: [*rs1val_walking_unsgn,*rs2val_walking_unsgn]
+
+        
+bseti:
+    config: 
+      - check ISA:=regex(.*E.*Zbs.*) ;def RVTEST_E = True
+    mnemonics: 
+      bseti: 0
+    rs1: 
+      <<: *rv32e_regs
+    rd:
+      <<: *rv32e_regs
+    op_comb: 
+      <<: *ifmt_op_comb
+    val_comb:
+      abstract_comb:      
+#        'xlenlim("rs1_val", xlen)': 0
+        'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
+        'trailing_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
diff --git a/sample_cgfs/rv32e_fencei.cgf b/sample_cgfs/rv32e_fencei.cgf
new file mode 100644
index 00000000..0339821e
--- /dev/null
+++ b/sample_cgfs/rv32e_fencei.cgf
@@ -0,0 +1,6 @@
+fencei:
+  config: 
+    - check ISA:=regex(.*E.*Zifencei.*) ;def RVTEST_E = True
+  mnemonics: 
+    fence.i: 0
+
diff --git a/sample_cgfs/rv32e_priv.cgf b/sample_cgfs/rv32e_priv.cgf
new file mode 100644
index 00000000..129677f1
--- /dev/null
+++ b/sample_cgfs/rv32e_priv.cgf
@@ -0,0 +1,146 @@
+misalign-lh:
+  cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True
+  config:
+    - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  mnemonics:
+    lh: 0
+  val_comb:
+    'ea_align == 1': 0
+
+misalign-lhu:
+  config:
+    - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True
+  mnemonics:
+    lhu: 0
+  val_comb:
+    'ea_align == 1': 0
+
+
+misalign-lw:
+  config:
+    - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True
+  mnemonics:
+    lw: 0
+  val_comb:
+    'ea_align == 1': 0
+    'ea_align == 2': 0
+    'ea_align == 3': 0
+
+misalign-sh:
+  config:
+    - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True
+  mnemonics:
+    sh: 0
+  val_comb:
+    'ea_align == 1': 0
+
+misalign-sw:
+  config:
+    - check ISA:=regex(.*E.*); check hw_data_misaligned_support:=True ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*Zicsr.*) ;def RVTEST_E = True
+  mnemonics:
+    sw: 0
+  val_comb:
+    'ea_align == 1': 0
+    'ea_align == 2': 0
+    'ea_align == 3': 0
+
+misalign2-jalr:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    jalr: 0
+  val_comb:
+    'imm_val%2 == 1 and ea_align == 2': 0
+    'imm_val%2 == 0 and ea_align == 2': 0
+
+misalign1-jalr:
+  config: 
+    - check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    jalr: 0
+  val_comb:
+    'imm_val%2 == 1 and ea_align == 1': 0
+    'imm_val%2 == 0 and ea_align == 1': 0
+
+misalign-jal:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    jal: 0
+  val_comb:
+    'ea_align == 2': 0
+
+misalign-bge:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    bge: 0
+  val_comb:
+    ' rs1_val>rs2_val and ea_align == 2': 0
+
+misalign-bgeu:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True 
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    bgeu: 0
+  val_comb:
+    ' rs1_val>rs2_val and ea_align == 2': 0
+
+misalign-blt:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    blt: 0
+  val_comb:
+    ' rs1_val<rs2_val and ea_align == 2': 0
+
+misalign-bltu:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    bltu: 0
+  val_comb:
+    ' rs1_val<rs2_val and ea_align == 2': 0
+
+misalign-bne:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    bne: 0
+  val_comb:
+    ' rs1_val!=rs2_val and ea_align == 2': 0
+
+misalign-beq:
+  config:
+    - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
+    - check ISA:=regex(.*E.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True ;def RVTEST_E = True
+  cond: check ISA:=regex(.*E.*) ;def RVTEST_E = True
+  mnemonics:
+    beq: 0
+  val_comb:
+    ' rs1_val==rs2_val and ea_align == 2': 0
+
+
diff --git a/sample_cgfs/rv32ec.cgf b/sample_cgfs/rv32ec.cgf
index cd8fb7c0..c995686e 100644
--- a/sample_cgfs/rv32ec.cgf
+++ b/sample_cgfs/rv32ec.cgf
@@ -3,13 +3,13 @@
 cebreak:
   config: 
     - check ISA:=regex(.*E.*Zicsr.*.C*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.ebreak: 0
 
 caddi4spn:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.addi4spn: 0
     rd:
       <<: *c_regs
@@ -24,7 +24,7 @@ caddi4spn:
 clw:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.lw: 0
     rs1: 
       <<: *c_regs
@@ -45,7 +45,7 @@ clw:
 csw:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.sw: 0
     rs1: 
       <<: *c_regs
@@ -67,7 +67,7 @@ csw:
 cnop:
     config: 
       - check ISA:=regex(.*E.*C.*)  ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.nop: 0
     val_comb:
       abstract_comb:
@@ -76,7 +76,7 @@ cnop:
 caddi:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.addi: 0
     rd:
       <<: *rv32e_regs_mx0
@@ -89,7 +89,7 @@ caddi:
 cjal:
   config: 
       - check ISA:=regex(.*RV32.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.jal: 0
   val_comb:
     'imm_val > 0': 0
@@ -102,7 +102,7 @@ cjal:
 cli:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.li: 0
   rd:
     <<: *rv32e_regs
@@ -116,7 +116,7 @@ cli:
 caddi16sp:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.addi16sp: 0
     rd:
       x2: 0
@@ -133,41 +133,10 @@ caddi16sp:
 clui:
   config: 
     - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.lui: 0
   rd:
-    x0: 0
-    x1: 0
-    x3: 0
-    x4: 0
-    x5: 0
-    x6: 0
-    x7: 0
-    x8: 0
-    x9: 0
-    x10: 0
-    x11: 0
-    x12: 0
-    x13: 0
-    x14: 0
-    x15: 0
-    x16: 0
-    x17: 0
-    x18: 0
-    x19: 0
-    x20: 0
-    x21: 0
-    x22: 0
-    x23: 0
-    x24: 0
-    x25: 0
-    x26: 0
-    x27: 0
-    x28: 0
-    x29: 0
-    x30: 0
-    x31: 0
-
+    <<: *rv32e_regs_mx2
   val_comb:
     'rs1_val > 0 and imm_val > 32': 0
     'rs1_val > 0 and imm_val < 32 and imm_val !=0 ': 0
@@ -181,7 +150,7 @@ clui:
 csrli:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.srli: 0
   rs1:
     <<: *c_regs
@@ -203,7 +172,7 @@ csrli:
 csrai:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.srai: 0
   rs1:
     <<: *c_regs
@@ -225,7 +194,7 @@ csrai:
 candi:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.andi: 0
     rs1:
       <<: *c_regs
@@ -238,7 +207,7 @@ candi:
 csub:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.sub: 0
     rs1:
       <<: *c_regs
@@ -255,7 +224,7 @@ csub:
 cxor:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.xor: 0
     rs1:
       <<: *c_regs
@@ -272,7 +241,7 @@ cxor:
 cor:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.or: 0
     rs1:
       <<: *c_regs
@@ -289,7 +258,7 @@ cor:
 cand:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.and: 0
     rs1:
       <<: *c_regs
@@ -308,7 +277,7 @@ cand:
 cj:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.j: 0
   val_comb:
     'imm_val > 0': 0
@@ -321,7 +290,7 @@ cj:
 cbeqz:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.beqz: 0
   rs1:
     <<: *c_regs
@@ -340,7 +309,7 @@ cbeqz:
 cbnez:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.bnez: 0
   rs1:
     <<: *c_regs
@@ -359,7 +328,7 @@ cbnez:
 cslli:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.slli: 0
   rd:
     <<: *c_regs
@@ -381,7 +350,7 @@ cslli:
 clwsp:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.lwsp: 0
     rd: 
       <<: *rv32e_regs_mx0
@@ -397,15 +366,22 @@ clwsp:
 cjr:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.jr: 0
   rs1:
     <<: *rv32e_regs_mx0
+  op_comb:
+    <<: *sfmt_op_comb
+  val_comb:
+    <<: *base_rs1val_sgn_rs2val_zero
+    abstract_comb:
+      'sp_dataset(xlen)': 0
+      <<: *rs1val_walking
 
 cmv:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.mv: 0
     rs2:
       <<: *rv32e_regs_mx0
@@ -423,7 +399,7 @@ cmv:
 cadd:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.add: 0
     rs1:
       <<: *rv32e_regs
@@ -440,15 +416,22 @@ cadd:
 cjalr:
   config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-  opcode: 
+  mnemonics: 
     c.jalr: 0
   rs1:
     <<: *rv32e_regs_mx0
+  op_comb:
+    <<: *sfmt_op_comb
+  val_comb:
+    <<: *base_rs1val_sgn_rs2val_zero
+    abstract_comb:
+      'sp_dataset(xlen)': 0
+      <<: *rs1val_walking
 
 cswsp:
     config: 
       - check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       c.swsp: 0
     rs2: 
       <<: *rv32e_regs_mx2
@@ -461,4 +444,3 @@ cswsp:
           'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
           'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
           'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0
-
diff --git a/sample_cgfs/rv32em.cgf b/sample_cgfs/rv32em.cgf
index ca7cc093..0bee9655 100644
--- a/sample_cgfs/rv32em.cgf
+++ b/sample_cgfs/rv32em.cgf
@@ -3,7 +3,7 @@
 mul:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       mul: 0
     rs1: 
       <<: *rv32e_regs
@@ -22,7 +22,7 @@ mul:
 mulh:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       mulh: 0
     rs1: 
       <<: *rv32e_regs
@@ -41,7 +41,7 @@ mulh:
 mulhu:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       mulhu: 0
     rs1: 
       <<: *rv32e_regs
@@ -60,7 +60,7 @@ mulhu:
 mulhsu:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       mulhsu: 0
     rs1: 
       <<: *rv32e_regs
@@ -80,7 +80,7 @@ mulhsu:
 div:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       div: 0
     rs1: 
       <<: *rv32e_regs
@@ -99,7 +99,7 @@ div:
 divu:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       divu: 0
     rs1: 
       <<: *rv32e_regs
@@ -118,7 +118,7 @@ divu:
 rem:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       rem: 0
     rs1: 
       <<: *rv32e_regs
@@ -137,7 +137,7 @@ rem:
 remu:
     config: 
       - check ISA:=regex(.*E.*M.*) ;def RVTEST_E = True
-    opcode: 
+    mnemonics: 
       remu: 0
     rs1: 
       <<: *rv32e_regs
diff --git a/sample_cgfs/rv32i.cgf b/sample_cgfs/rv32i.cgf
index c548d63f..54ce07fb 100644
--- a/sample_cgfs/rv32i.cgf
+++ b/sample_cgfs/rv32i.cgf
@@ -3,13 +3,13 @@
 fence:
   config: 
     - check ISA:=regex(.*I.*)
-  opcode: 
+  mnemonics: 
     fence: 0
 
 addi:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       addi: 0
     rs1: 
       <<: *all_regs
@@ -26,7 +26,7 @@ addi:
 slti:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       slti: 0
     rs1: 
       <<: *all_regs
@@ -43,7 +43,7 @@ slti:
 sltiu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sltiu: 0
     rs1: 
       <<: *all_regs
@@ -60,7 +60,7 @@ sltiu:
 andi:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       andi: 0
     rs1: 
       <<: *all_regs
@@ -77,7 +77,7 @@ andi:
 ori:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       ori: 0
     rs1: 
       <<: *all_regs
@@ -94,7 +94,7 @@ ori:
 xori:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       xori: 0
     rs1: 
       <<: *all_regs
@@ -111,7 +111,7 @@ xori:
 slli:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       slli: 0
     rs1: 
       <<: *all_regs
@@ -131,7 +131,7 @@ slli:
 srai:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       srai: 0
     rs1: 
       <<: *all_regs
@@ -151,7 +151,7 @@ srai:
 srli:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       srli: 0
     rs1: 
       <<: *all_regs
@@ -171,7 +171,7 @@ srli:
 add:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       add: 0
     rs1: 
       <<: *all_regs
@@ -190,7 +190,7 @@ add:
 sub:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sub: 0
     rs1: 
       <<: *all_regs
@@ -209,7 +209,7 @@ sub:
 slt:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       slt: 0
     rs1: 
       <<: *all_regs
@@ -228,7 +228,7 @@ slt:
 sltu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sltu: 0
     rs1: 
       <<: *all_regs
@@ -247,7 +247,7 @@ sltu:
 and:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       and: 0
     rs1: 
       <<: *all_regs
@@ -266,7 +266,7 @@ and:
 or:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       or: 0
     rs1: 
       <<: *all_regs
@@ -285,7 +285,7 @@ or:
 xor:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       xor: 0
     rs1: 
       <<: *all_regs
@@ -304,7 +304,7 @@ xor:
 sll:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sll: 0
     rs1: 
       <<: *all_regs
@@ -326,7 +326,7 @@ sll:
 srl:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       srl: 0
     rs1: 
       <<: *all_regs
@@ -348,7 +348,7 @@ srl:
 sra:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sra: 0
     rs1: 
       <<: *all_regs
@@ -370,7 +370,7 @@ sra:
 beq:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       beq: 0
     rs1: 
       <<: *all_regs
@@ -387,7 +387,7 @@ beq:
 bge:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bge: 0
     rs1: 
       <<: *all_regs
@@ -404,7 +404,7 @@ bge:
 bgeu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bgeu: 0
     rs1: 
       <<: *all_regs
@@ -421,7 +421,7 @@ bgeu:
 blt:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       blt: 0
     rs1: 
       <<: *all_regs
@@ -438,7 +438,7 @@ blt:
 bltu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bltu: 0
     rs1: 
       <<: *all_regs
@@ -455,7 +455,7 @@ bltu:
 bne:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bne: 0
     rs1: 
       <<: *all_regs
@@ -472,7 +472,7 @@ bne:
 lhu-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lhu: 0
     rs1: 
       <<: *all_regs_mx0
@@ -496,7 +496,7 @@ lhu-align:
 lh-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lh: 0
     rs1: 
       <<: *all_regs_mx0
@@ -520,7 +520,7 @@ lh-align:
 lbu-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lbu: 0
     rs1: 
       <<: *all_regs_mx0
@@ -552,7 +552,7 @@ lbu-align:
 lb-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lb: 0
     rs1: 
       <<: *all_regs_mx0
@@ -584,7 +584,7 @@ lb-align:
 lw-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lw: 0
     rs1: 
       <<: *all_regs_mx0
@@ -605,7 +605,7 @@ lw-align:
 sh-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sh: 0
     rs1: 
       <<: *all_regs_mx0
@@ -632,7 +632,7 @@ sh-align:
 sb-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sb: 0
     rs1: 
       <<: *all_regs_mx0
@@ -667,7 +667,7 @@ sb-align:
 sw-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sw: 0
     rs1: 
       <<: *all_regs_mx0
@@ -690,7 +690,7 @@ sw-align:
 auipc:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       auipc: 0
     rd: 
       <<: *all_regs
@@ -707,7 +707,7 @@ auipc:
 lui:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lui: 0
     rd: 
       <<: *all_regs
@@ -724,7 +724,7 @@ lui:
 jal:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       jal: 0
     rd: 
       <<: *all_regs
@@ -737,7 +737,7 @@ jal:
 jalr:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       jalr: 0
     rs1:
       <<: *all_regs_mx0
diff --git a/sample_cgfs/rv32i_b.cgf b/sample_cgfs/rv32i_b.cgf
index 5893bc0e..14fe4a01 100644
--- a/sample_cgfs/rv32i_b.cgf
+++ b/sample_cgfs/rv32i_b.cgf
@@ -1,5 +1,6 @@
 sh1add:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zba.*)
     mnemonics: 
       sh1add: 0
@@ -19,6 +20,7 @@ sh1add:
         
 sh2add:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zba.*)
     mnemonics: 
       sh2add: 0
@@ -38,6 +40,7 @@ sh2add:
         
 sh3add:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zba.*)
     mnemonics: 
       sh3add: 0
@@ -57,6 +60,7 @@ sh3add:
         
 xnor:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -81,6 +85,7 @@ xnor:
         
 zext.h_32:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       zext.h: 0
@@ -102,6 +107,7 @@ zext.h_32:
         'uniform_random(20, 100, ["rs1_val"], [xlen])': 0
 andn:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -126,6 +132,7 @@ andn:
 
 clz:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       clz: 0
@@ -138,13 +145,14 @@ clz:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
 
 ctz:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       ctz: 0
@@ -157,13 +165,14 @@ ctz:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
         
 cpop:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       cpop: 0
@@ -176,13 +185,14 @@ cpop:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
         
 max:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       max: 0
@@ -202,6 +212,7 @@ max:
 
 maxu:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       maxu: 0
@@ -221,6 +232,7 @@ maxu:
         
 min:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       min: 0
@@ -240,6 +252,7 @@ min:
         
 minu:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       minu: 0
@@ -259,6 +272,7 @@ minu:
         
 orcb_32:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       orc.b: 0
@@ -281,6 +295,7 @@ orcb_32:
         
 orn:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -305,6 +320,7 @@ orn:
 
 rev8_32:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -334,6 +350,7 @@ rev8_32:
         
 rol:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -358,6 +375,7 @@ rol:
 
 ror:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -382,6 +400,7 @@ ror:
         
 rori:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -404,6 +423,7 @@ rori:
 
 sext.b:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       sext.b: 0
@@ -423,6 +443,7 @@ sext.b:
 
 sext.h:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       sext.h: 0
@@ -524,6 +545,7 @@ clmulr:
 
 bclr:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bclr: 0
@@ -537,8 +559,8 @@ bclr:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -550,6 +572,7 @@ bclr:
         
 bclri:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bclri: 0
@@ -561,7 +584,7 @@ bclri:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
@@ -570,6 +593,7 @@ bclri:
         
 bext:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bext: 0
@@ -583,8 +607,8 @@ bext:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -596,6 +620,7 @@ bext:
         
 bexti:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bexti: 0
@@ -607,7 +632,7 @@ bexti:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
@@ -616,6 +641,7 @@ bexti:
         
 binv:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       binv: 0
@@ -629,8 +655,8 @@ binv:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -642,6 +668,7 @@ binv:
         
 binvi:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       binvi: 0
@@ -653,7 +680,7 @@ binvi:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
@@ -661,6 +688,7 @@ binvi:
         
 bset:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bset: 0
@@ -674,8 +702,8 @@ bset:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(32, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -687,6 +715,7 @@ bset:
         
 bseti:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bseti: 0
@@ -698,7 +727,7 @@ bseti:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(32, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(32, ["rs1_val", "imm_val"], [32,5])': 0
diff --git a/sample_cgfs/rv32i_fencei.cgf b/sample_cgfs/rv32i_fencei.cgf
index 6f1a71bc..7699d7c4 100644
--- a/sample_cgfs/rv32i_fencei.cgf
+++ b/sample_cgfs/rv32i_fencei.cgf
@@ -1,6 +1,6 @@
 fencei:
   config: 
     - check ISA:=regex(.*I.*Zifencei.*)
-  opcode: 
+  mnemonics: 
     fence.i: 0
 
diff --git a/sample_cgfs/rv32i_priv.cgf b/sample_cgfs/rv32i_priv.cgf
index 320dbda2..94131f0a 100644
--- a/sample_cgfs/rv32i_priv.cgf
+++ b/sample_cgfs/rv32i_priv.cgf
@@ -1,13 +1,13 @@
 ecall:
   config: 
     - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True 
-  opcode: 
+  mnemonics: 
     ecall: 0
 
 ebreak:
   config: 
     - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True 
-  opcode: 
+  mnemonics: 
     ebreak: 0
 
 misalign-lh:
@@ -15,7 +15,7 @@ misalign-lh:
   config:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
-  opcode:
+  mnemonics:
     lh: 0
   val_comb:
     'ea_align == 1': 0
@@ -25,7 +25,7 @@ misalign-lhu:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     lhu: 0
   val_comb:
     'ea_align == 1': 0
@@ -36,7 +36,7 @@ misalign-lw:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     lw: 0
   val_comb:
     'ea_align == 1': 0
@@ -48,7 +48,7 @@ misalign-sh:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     sh: 0
   val_comb:
     'ea_align == 1': 0
@@ -58,7 +58,7 @@ misalign-sw:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     sw: 0
   val_comb:
     'ea_align == 1': 0
@@ -70,7 +70,7 @@ misalign2-jalr:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     jalr: 0
   val_comb:
     'imm_val%2 == 1 and ea_align == 2': 0
@@ -79,7 +79,7 @@ misalign2-jalr:
 misalign1-jalr:
   config: 
     - check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     jalr: 0
   val_comb:
     'imm_val%2 == 1 and ea_align == 1': 0
@@ -90,7 +90,7 @@ misalign-jal:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     jal: 0
   val_comb:
     'ea_align == 2': 0
@@ -100,7 +100,7 @@ misalign-bge:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bge: 0
   val_comb:
     ' rs1_val>rs2_val and ea_align == 2': 0
@@ -110,7 +110,7 @@ misalign-bgeu:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bgeu: 0
   val_comb:
     ' rs1_val>rs2_val and ea_align == 2': 0
@@ -120,7 +120,7 @@ misalign-blt:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     blt: 0
   val_comb:
     ' rs1_val<rs2_val and ea_align == 2': 0
@@ -130,7 +130,7 @@ misalign-bltu:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bltu: 0
   val_comb:
     ' rs1_val<rs2_val and ea_align == 2': 0
@@ -140,7 +140,7 @@ misalign-bne:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bne: 0
   val_comb:
     ' rs1_val!=rs2_val and ea_align == 2': 0
@@ -150,7 +150,7 @@ misalign-beq:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     beq: 0
   val_comb:
     ' rs1_val==rs2_val and ea_align == 2': 0
diff --git a/sample_cgfs/rv32i_zcb.cgf b/sample_cgfs/rv32i_zcb.cgf
new file mode 100644
index 00000000..2fc96375
--- /dev/null
+++ b/sample_cgfs/rv32i_zcb.cgf
@@ -0,0 +1,176 @@
+
+clbu:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.lbu: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 1': 0
+        'imm_val == 2': 0
+        'imm_val == 3': 0
+
+clhu:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.lhu: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 2': 0
+
+clh:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.lh: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 2': 0
+
+csb:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.sb: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 1': 0
+        'imm_val == 2': 0
+        'imm_val == 3': 0
+
+csh:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.sh: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 2': 0
+
+csext.b:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*)
+    mnemonics: 
+      c.sext.b: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x80': 0
+      'rs1_val == 0x8000': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+csext.h:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*)
+    mnemonics: 
+      c.sext.h: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+czext.b:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.zext.b: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x80': 0
+      'rs1_val == 0x8000': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+czext.h:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*)
+    mnemonics: 
+      c.zext.h: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+cnot:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.not: 0
+    rs1: 
+      <<: *c_regs
+    op_comb:
+      <<: *r0fmt_op_comb
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+cmul:
+    config: 
+      - check ISA:=regex(.*I.*M.*Zca.*Zcb.*)
+    mnemonics: 
+      c.mul: 0
+    rs1:
+      <<: *c_regs
+    rs2:
+      <<: *c_regs
+    op_comb:
+      <<: *sfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+  
\ No newline at end of file
diff --git a/sample_cgfs/rv32ia.cgf b/sample_cgfs/rv32ia.cgf
new file mode 100644
index 00000000..cf5f345c
--- /dev/null
+++ b/sample_cgfs/rv32ia.cgf
@@ -0,0 +1,170 @@
+amoadd.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amoadd.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoand.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amoand.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoswap.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amoswap.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoxor.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amoxor.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoor.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amoor.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomin.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amomin.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amominu.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amominu.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomax.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amomax.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomaxu.w:
+    config: 
+      - check ISA:=regex(.*32.*I.*A.*)
+      - check ISA:=regex(.*32.*I.*Zaamo.*)
+    mnemonics: 
+      amomaxu.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
diff --git a/sample_cgfs/rv32ic.cgf b/sample_cgfs/rv32ic.cgf
index a3991032..0c8eb4f4 100644
--- a/sample_cgfs/rv32ic.cgf
+++ b/sample_cgfs/rv32ic.cgf
@@ -3,13 +3,13 @@
 cebreak:
   config: 
     - check ISA:=regex(.*I.*Zicsr.*.C*)
-  opcode: 
+  mnemonics: 
     c.ebreak: 0
 
 caddi4spn:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addi4spn: 0
     rd:
       <<: *c_regs
@@ -24,7 +24,7 @@ caddi4spn:
 clw:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.lw: 0
     rs1: 
       <<: *c_regs
@@ -45,7 +45,7 @@ clw:
 csw:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.sw: 0
     rs1: 
       <<: *c_regs
@@ -67,7 +67,7 @@ csw:
 cnop:
     config: 
       - check ISA:=regex(.*I.*C.*) 
-    opcode: 
+    mnemonics: 
       c.nop: 0
     val_comb:
       abstract_comb:
@@ -76,7 +76,7 @@ cnop:
 caddi:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addi: 0
     rd:
       <<: *all_regs_mx0
@@ -89,7 +89,7 @@ caddi:
 cjal:
   config: 
       - check ISA:=regex(.*RV32.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.jal: 0
   val_comb:
     'imm_val > 0': 0
@@ -102,7 +102,7 @@ cjal:
 cli:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.li: 0
   rd:
     <<: *all_regs
@@ -116,7 +116,7 @@ cli:
 caddi16sp:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addi16sp: 0
     rd:
       x2: 0
@@ -133,7 +133,7 @@ caddi16sp:
 clui:
   config: 
     - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.lui: 0
   rd:
     x0: 0
@@ -181,7 +181,7 @@ clui:
 csrli:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.srli: 0
   rs1:
     <<: *c_regs
@@ -203,7 +203,7 @@ csrli:
 csrai:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.srai: 0
   rs1:
     <<: *c_regs
@@ -225,7 +225,7 @@ csrai:
 candi:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.andi: 0
     rs1:
       <<: *c_regs
@@ -238,7 +238,7 @@ candi:
 csub:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.sub: 0
     rs1:
       <<: *c_regs
@@ -255,7 +255,7 @@ csub:
 cxor:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.xor: 0
     rs1:
       <<: *c_regs
@@ -272,7 +272,7 @@ cxor:
 cor:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.or: 0
     rs1:
       <<: *c_regs
@@ -289,7 +289,7 @@ cor:
 cand:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.and: 0
     rs1:
       <<: *c_regs
@@ -308,7 +308,7 @@ cand:
 cj:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.j: 0
   val_comb:
     'imm_val > 0': 0
@@ -321,7 +321,7 @@ cj:
 cbeqz:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.beqz: 0
   rs1:
     <<: *c_regs
@@ -340,7 +340,7 @@ cbeqz:
 cbnez:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.bnez: 0
   rs1:
     <<: *c_regs
@@ -359,7 +359,7 @@ cbnez:
 cslli:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.slli: 0
   rd:
     <<: *c_regs
@@ -381,7 +381,7 @@ cslli:
 clwsp:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.lwsp: 0
     rd: 
       <<: *all_regs_mx0
@@ -397,15 +397,22 @@ clwsp:
 cjr:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.jr: 0
   rs1:
     <<: *all_regs_mx0
+  op_comb:
+    <<: *sfmt_op_comb
+  val_comb:
+    <<: *base_rs1val_sgn_rs2val_zero
+    abstract_comb:
+      'sp_dataset(xlen)': 0
+      <<: *rs1val_walking
 
 cmv:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.mv: 0
     rs2:
       <<: *all_regs_mx0
@@ -423,7 +430,7 @@ cmv:
 cadd:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.add: 0
     rs1:
       <<: *all_regs
@@ -440,15 +447,22 @@ cadd:
 cjalr:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.jalr: 0
   rs1:
     <<: *all_regs_mx0
+  op_comb:
+    <<: *sfmt_op_comb
+  val_comb:
+    <<: *base_rs1val_sgn_rs2val_zero
+    abstract_comb:
+      'sp_dataset(xlen)': 0
+      <<: *rs1val_walking
 
 cswsp:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.swsp: 0
     rs2: 
       <<: *all_regs_mx2
diff --git a/sample_cgfs/rv32im.cgf b/sample_cgfs/rv32im.cgf
index 0af3d178..d69131e4 100644
--- a/sample_cgfs/rv32im.cgf
+++ b/sample_cgfs/rv32im.cgf
@@ -3,7 +3,7 @@
 mul:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mul: 0
     rs1: 
       <<: *all_regs
@@ -22,7 +22,7 @@ mul:
 mulh:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulh: 0
     rs1: 
       <<: *all_regs
@@ -41,7 +41,7 @@ mulh:
 mulhu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulhu: 0
     rs1: 
       <<: *all_regs
@@ -60,7 +60,7 @@ mulhu:
 mulhsu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulhsu: 0
     rs1: 
       <<: *all_regs
@@ -80,7 +80,7 @@ mulhsu:
 div:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       div: 0
     rs1: 
       <<: *all_regs
@@ -89,9 +89,9 @@ div:
     rd: 
       <<: *all_regs
     op_comb: 
-      <<: *rfmt_op_comb
+      <<: [*rfmt_op_comb , *div_hardcoded_opcomb]
     val_comb:
-      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case]
       abstract_comb:
         'sp_dataset(xlen)': 0
         <<: [*rs1val_walking, *rs2val_walking]
@@ -99,7 +99,7 @@ div:
 divu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       divu: 0
     rs1: 
       <<: *all_regs
@@ -108,7 +108,7 @@ divu:
     rd: 
       <<: *all_regs
     op_comb: 
-      <<: *rfmt_op_comb
+      <<: [*rfmt_op_comb , *div_hardcoded_opcomb]
     val_comb:
       <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
       abstract_comb:
@@ -118,7 +118,7 @@ divu:
 rem:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       rem: 0
     rs1: 
       <<: *all_regs
@@ -127,9 +127,9 @@ rem:
     rd: 
       <<: *all_regs
     op_comb: 
-      <<: *rfmt_op_comb
+      <<: [*rfmt_op_comb , *div_hardcoded_opcomb]
     val_comb:
-      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case]
       abstract_comb:
         'sp_dataset(xlen)': 0
         <<: [*rs1val_walking, *rs2val_walking]
@@ -137,7 +137,7 @@ rem:
 remu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       remu: 0
     rs1: 
       <<: *all_regs
@@ -146,7 +146,7 @@ remu:
     rd: 
       <<: *all_regs
     op_comb: 
-      <<: *rfmt_op_comb
+      <<: [*rfmt_op_comb , *div_hardcoded_opcomb]
     val_comb:
       <<: [*base_rs1val_unsgn , *base_rs2val_unsgn , *rfmt_val_comb_unsgn]
       abstract_comb:
diff --git a/sample_cgfs/rv32ip.cgf b/sample_cgfs/rv32ip.cgf
index 1f95d79c..3fa586ed 100644
--- a/sample_cgfs/rv32ip.cgf
+++ b/sample_cgfs/rv32ip.cgf
@@ -3,7 +3,7 @@
 add16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       add16: 0
     rs1:
       <<: *all_regs
@@ -22,7 +22,7 @@ add16:
 radd16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       radd16: 0
     rs1:
       <<: *all_regs
@@ -41,7 +41,7 @@ radd16:
 uradd16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uradd16: 0
     rs1:
       <<: *all_regs
@@ -60,7 +60,7 @@ uradd16:
 kadd16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kadd16: 0
     rs1:
       <<: *all_regs
@@ -79,7 +79,7 @@ kadd16:
 ukadd16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukadd16: 0
     rs1:
       <<: *all_regs
@@ -98,7 +98,7 @@ ukadd16:
 sub16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sub16: 0
     rs1:
       <<: *all_regs
@@ -117,7 +117,7 @@ sub16:
 rsub16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rsub16: 0
     rs1:
       <<: *all_regs
@@ -137,7 +137,7 @@ rsub16:
 ursub16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ursub16: 0
     rs1:
       <<: *all_regs
@@ -156,7 +156,7 @@ ursub16:
 ksub16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksub16: 0
     rs1:
       <<: *all_regs
@@ -175,7 +175,7 @@ ksub16:
 uksub16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uksub16: 0
     rs1:
       <<: *all_regs
@@ -194,7 +194,7 @@ uksub16:
 cras16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       cras16: 0
     rs1:
       <<: *all_regs
@@ -213,7 +213,7 @@ cras16:
 rcras16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rcras16: 0
     rs1:
       <<: *all_regs
@@ -232,7 +232,7 @@ rcras16:
 urcras16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urcras16: 0
     rs1:
       <<: *all_regs
@@ -251,7 +251,7 @@ urcras16:
 kcras16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kcras16: 0
     rs1:
       <<: *all_regs
@@ -270,7 +270,7 @@ kcras16:
 ukcras16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukcras16: 0
     rs1:
       <<: *all_regs
@@ -289,7 +289,7 @@ ukcras16:
 crsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       crsa16: 0
     rs1:
       <<: *all_regs
@@ -308,7 +308,7 @@ crsa16:
 rcrsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rcrsa16: 0
     rs1:
       <<: *all_regs
@@ -327,7 +327,7 @@ rcrsa16:
 urcrsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urcrsa16: 0
     rs1:
       <<: *all_regs
@@ -346,7 +346,7 @@ urcrsa16:
 kcrsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kcrsa16: 0
     rs1:
       <<: *all_regs
@@ -365,7 +365,7 @@ kcrsa16:
 ukcrsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukcrsa16: 0
     rs1:
       <<: *all_regs
@@ -384,7 +384,7 @@ ukcrsa16:
 stas16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       stas16: 0
     rs1:
       <<: *all_regs
@@ -403,7 +403,7 @@ stas16:
 rstas16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rstas16: 0
     rs1:
       <<: *all_regs
@@ -422,7 +422,7 @@ rstas16:
 urstas16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urstas16: 0
     rs1:
       <<: *all_regs
@@ -441,7 +441,7 @@ urstas16:
 kstas16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kstas16: 0
     rs1:
       <<: *all_regs
@@ -460,7 +460,7 @@ kstas16:
 ukstas16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukstas16: 0
     rs1:
       <<: *all_regs
@@ -479,7 +479,7 @@ ukstas16:
 stsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       stsa16: 0
     rs1:
       <<: *all_regs
@@ -498,7 +498,7 @@ stsa16:
 rstsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rstsa16: 0
     rs1:
       <<: *all_regs
@@ -517,7 +517,7 @@ rstsa16:
 urstsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urstsa16: 0
     rs1:
       <<: *all_regs
@@ -536,7 +536,7 @@ urstsa16:
 kstsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kstsa16: 0
     rs1:
       <<: *all_regs
@@ -555,7 +555,7 @@ kstsa16:
 ukstsa16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukstsa16: 0
     rs1:
       <<: *all_regs
@@ -574,7 +574,7 @@ ukstsa16:
 add8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       add8: 0
     rs1:
       <<: *all_regs
@@ -593,7 +593,7 @@ add8:
 radd8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       radd8: 0
     rs1:
       <<: *all_regs
@@ -612,7 +612,7 @@ radd8:
 uradd8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uradd8: 0
     rs1:
       <<: *all_regs
@@ -631,7 +631,7 @@ uradd8:
 kadd8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kadd8: 0
     rs1:
       <<: *all_regs
@@ -650,7 +650,7 @@ kadd8:
 ukadd8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       ukadd8: 0
     rs1: 
       <<: *all_regs
@@ -669,7 +669,7 @@ ukadd8:
 sub8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sub8: 0
     rs1:
       <<: *all_regs
@@ -688,7 +688,7 @@ sub8:
 rsub8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rsub8: 0
     rs1:
       <<: *all_regs
@@ -707,7 +707,7 @@ rsub8:
 ursub8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ursub8: 0
     rs1:
       <<: *all_regs
@@ -726,7 +726,7 @@ ursub8:
 ksub8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksub8: 0
     rs1:
       <<: *all_regs
@@ -745,7 +745,7 @@ ksub8:
 uksub8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uksub8: 0
     rs1:
       <<: *all_regs
@@ -764,7 +764,7 @@ uksub8:
 sra16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sra16: 0
     rs1:
       <<: *all_regs
@@ -784,7 +784,7 @@ sra16:
 srai16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srai16: 0
     rs1:
       <<: *all_regs
@@ -800,7 +800,7 @@ srai16:
 sra16.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sra16.u: 0
     rs1:
       <<: *all_regs
@@ -820,7 +820,7 @@ sra16.u:
 srai16.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srai16.u: 0
     rs1:
       <<: *all_regs
@@ -836,7 +836,7 @@ srai16.u:
 srl16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srl16: 0
     rs1:
       <<: *all_regs
@@ -856,7 +856,7 @@ srl16:
 srli16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srli16: 0
     rs1:
       <<: *all_regs
@@ -872,7 +872,7 @@ srli16:
 srl16.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srl16.u: 0
     rs1:
       <<: *all_regs
@@ -892,7 +892,7 @@ srl16.u:
 srli16.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srli16.u: 0
     rs1:
       <<: *all_regs
@@ -908,7 +908,7 @@ srli16.u:
 sll16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sll16: 0
     rs1:
       <<: *all_regs
@@ -928,7 +928,7 @@ sll16:
 slli16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       slli16: 0
     rs1:
       <<: *all_regs
@@ -944,7 +944,7 @@ slli16:
 ksll16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksll16: 0
     rs1:
       <<: *all_regs
@@ -964,7 +964,7 @@ ksll16:
 kslli16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslli16: 0
     rs1:
       <<: *all_regs
@@ -980,7 +980,7 @@ kslli16:
 kslra16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslra16: 0
     rs1:
       <<: *all_regs
@@ -1000,7 +1000,7 @@ kslra16:
 kslra16.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslra16.u: 0
     rs1:
       <<: *all_regs
@@ -1020,7 +1020,7 @@ kslra16.u:
 sra8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sra8: 0
     rs1:
       <<: *all_regs
@@ -1040,7 +1040,7 @@ sra8:
 srai8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srai8: 0
     rs1:
       <<: *all_regs
@@ -1056,7 +1056,7 @@ srai8:
 sra8.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sra8.u: 0
     rs1:
       <<: *all_regs
@@ -1076,7 +1076,7 @@ sra8.u:
 srai8.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srai8.u: 0
     rs1:
       <<: *all_regs
@@ -1092,7 +1092,7 @@ srai8.u:
 srl8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srl8: 0
     rs1:
       <<: *all_regs
@@ -1112,7 +1112,7 @@ srl8:
 srli8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srli8: 0
     rs1:
       <<: *all_regs
@@ -1128,7 +1128,7 @@ srli8:
 srl8.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srl8.u: 0
     rs1:
       <<: *all_regs
@@ -1148,7 +1148,7 @@ srl8.u:
 srli8.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srli8.u: 0
     rs1:
       <<: *all_regs
@@ -1164,7 +1164,7 @@ srli8.u:
 sll8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sll8: 0
     rs1:
       <<: *all_regs
@@ -1184,7 +1184,7 @@ sll8:
 slli8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       slli8: 0
     rs1:
       <<: *all_regs
@@ -1200,7 +1200,7 @@ slli8:
 ksll8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksll8: 0
     rs1:
       <<: *all_regs
@@ -1220,7 +1220,7 @@ ksll8:
 kslli8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslli8: 0
     rs1:
       <<: *all_regs
@@ -1236,7 +1236,7 @@ kslli8:
 kslra8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslra8: 0
     rs1:
       <<: *all_regs
@@ -1256,7 +1256,7 @@ kslra8:
 kslra8.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslra8.u: 0
     rs1:
       <<: *all_regs
@@ -1276,7 +1276,7 @@ kslra8.u:
 cmpeq16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       cmpeq16: 0
     rs1:
       <<: *all_regs
@@ -1295,7 +1295,7 @@ cmpeq16:
 scmplt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       scmplt16: 0
     rs1:
       <<: *all_regs
@@ -1314,7 +1314,7 @@ scmplt16:
 scmple16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       scmple16: 0
     rs1:
       <<: *all_regs
@@ -1333,7 +1333,7 @@ scmple16:
 ucmplt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ucmplt16: 0
     rs1:
       <<: *all_regs
@@ -1352,7 +1352,7 @@ ucmplt16:
 ucmple16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ucmple16: 0
     rs1:
       <<: *all_regs
@@ -1371,7 +1371,7 @@ ucmple16:
 cmpeq8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       cmpeq8: 0
     rs1:
       <<: *all_regs
@@ -1390,7 +1390,7 @@ cmpeq8:
 scmplt8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       scmplt8: 0
     rs1:
       <<: *all_regs
@@ -1409,7 +1409,7 @@ scmplt8:
 scmple8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       scmple8: 0
     rs1:
       <<: *all_regs
@@ -1428,7 +1428,7 @@ scmple8:
 ucmplt8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ucmplt8: 0
     rs1:
       <<: *all_regs
@@ -1447,7 +1447,7 @@ ucmplt8:
 ucmple8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ucmple8: 0
     rs1:
       <<: *all_regs
@@ -1466,7 +1466,7 @@ ucmple8:
 smul16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smul16: 0
     rs1:
       <<: *all_regs
@@ -1485,7 +1485,7 @@ smul16:
 smulx16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smulx16: 0
     rs1:
       <<: *all_regs
@@ -1504,7 +1504,7 @@ smulx16:
 umul16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umul16: 0
     rs1:
       <<: *all_regs
@@ -1523,7 +1523,7 @@ umul16:
 umulx16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umulx16: 0
     rs1:
       <<: *all_regs
@@ -1542,7 +1542,7 @@ umulx16:
 khm16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khm16: 0
     rs1:
       <<: *all_regs
@@ -1561,7 +1561,7 @@ khm16:
 khmx16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khmx16: 0
     rs1:
       <<: *all_regs
@@ -1580,7 +1580,7 @@ khmx16:
 smul8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smul8: 0
     rs1:
       <<: *all_regs
@@ -1599,7 +1599,7 @@ smul8:
 smulx8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smulx8: 0
     rs1:
       <<: *all_regs
@@ -1618,7 +1618,7 @@ smulx8:
 umul8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umul8: 0
     rs1:
       <<: *all_regs
@@ -1637,7 +1637,7 @@ umul8:
 umulx8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umulx8: 0
     rs1:
       <<: *all_regs
@@ -1656,7 +1656,7 @@ umulx8:
 khm8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khm8: 0
     rs1:
       <<: *all_regs
@@ -1675,7 +1675,7 @@ khm8:
 khmx8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khmx8: 0
     rs1:
       <<: *all_regs
@@ -1694,7 +1694,7 @@ khmx8:
 smin16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smin16: 0
     rs1:
       <<: *all_regs
@@ -1713,7 +1713,7 @@ smin16:
 umin16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umin16: 0
     rs1:
       <<: *all_regs
@@ -1732,7 +1732,7 @@ umin16:
 smax16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smax16: 0
     rs1:
       <<: *all_regs
@@ -1751,7 +1751,7 @@ smax16:
 umax16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umax16: 0
     rs1:
       <<: *all_regs
@@ -1770,7 +1770,7 @@ umax16:
 sclip16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sclip16: 0
     rs1:
       <<: *all_regs
@@ -1786,7 +1786,7 @@ sclip16:
 uclip16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uclip16: 0
     rs1:
       <<: *all_regs
@@ -1802,7 +1802,7 @@ uclip16:
 kabs16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kabs16: 0
     rs1:
       <<: *all_regs
@@ -1815,7 +1815,7 @@ kabs16:
 clrs16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       clrs16: 0
     rs1:
       <<: *all_regs
@@ -1828,7 +1828,7 @@ clrs16:
 clz16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       clz16: 0
     rs1:
       <<: *all_regs
@@ -1842,7 +1842,7 @@ clz16:
 # swap16:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       swap16: 0
 #     rs1:
 #       <<: *all_regs
@@ -1855,7 +1855,7 @@ clz16:
 smin8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smin8: 0
     rs1:
       <<: *all_regs
@@ -1874,7 +1874,7 @@ smin8:
 umin8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umin8: 0
     rs1:
       <<: *all_regs
@@ -1893,7 +1893,7 @@ umin8:
 smax8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smax8: 0
     rs1:
       <<: *all_regs
@@ -1912,7 +1912,7 @@ smax8:
 umax8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umax8: 0
     rs1:
       <<: *all_regs
@@ -1931,7 +1931,7 @@ umax8:
 kabs8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kabs8: 0
     rs1:
       <<: *all_regs
@@ -1944,7 +1944,7 @@ kabs8:
 sclip8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sclip8: 0
     rs1:
       <<: *all_regs
@@ -1960,7 +1960,7 @@ sclip8:
 uclip8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uclip8: 0
     rs1:
       <<: *all_regs
@@ -1976,7 +1976,7 @@ uclip8:
 clrs8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       clrs8: 0
     rs1:
       <<: *all_regs
@@ -1989,7 +1989,7 @@ clrs8:
 clz8:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       clz8: 0
     rs1:
       <<: *all_regs
@@ -2003,7 +2003,7 @@ clz8:
 # swap8:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       swap8: 0
 #     rs1:
 #       <<: *all_regs
@@ -2016,7 +2016,7 @@ clz8:
 sunpkd810:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sunpkd810: 0
     rs1:
       <<: *all_regs
@@ -2029,7 +2029,7 @@ sunpkd810:
 sunpkd820:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sunpkd820: 0
     rs1:
       <<: *all_regs
@@ -2042,7 +2042,7 @@ sunpkd820:
 sunpkd830:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sunpkd830: 0
     rs1:
       <<: *all_regs
@@ -2055,7 +2055,7 @@ sunpkd830:
 sunpkd831:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sunpkd831: 0
     rs1:
       <<: *all_regs
@@ -2068,7 +2068,7 @@ sunpkd831:
 sunpkd832:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sunpkd832: 0
     rs1:
       <<: *all_regs
@@ -2081,7 +2081,7 @@ sunpkd832:
 zunpkd810:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       zunpkd810: 0
     rs1:
       <<: *all_regs
@@ -2094,7 +2094,7 @@ zunpkd810:
 zunpkd820:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       zunpkd820: 0
     rs1:
       <<: *all_regs
@@ -2107,7 +2107,7 @@ zunpkd820:
 zunpkd830:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       zunpkd830: 0
     rs1:
       <<: *all_regs
@@ -2120,7 +2120,7 @@ zunpkd830:
 zunpkd831:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       zunpkd831: 0
     rs1:
       <<: *all_regs
@@ -2133,7 +2133,7 @@ zunpkd831:
 zunpkd832:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       zunpkd832: 0
     rs1:
       <<: *all_regs
@@ -2147,7 +2147,7 @@ zunpkd832:
 # pkbb16:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       pkbb16: 0
 #     rs1:
 #       <<: *all_regs
@@ -2166,7 +2166,7 @@ zunpkd832:
 pkbt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       pkbt16: 0
     rs1:
       <<: *all_regs
@@ -2185,7 +2185,7 @@ pkbt16:
 pktb16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       pktb16: 0
     rs1:
       <<: *all_regs
@@ -2205,7 +2205,7 @@ pktb16:
 # pktt16:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       pktt16: 0
 #     rs1:
 #       <<: *all_regs
@@ -2225,7 +2225,7 @@ pktb16:
 smmul:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smmul: 0
     rs1:
       <<: *all_regs
@@ -2243,7 +2243,7 @@ smmul:
 smmul.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smmul.u: 0
     rs1:
       <<: *all_regs
@@ -2261,7 +2261,7 @@ smmul.u:
 kmmac:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmac: 0
     rs1:
       <<: *all_regs
@@ -2279,7 +2279,7 @@ kmmac:
 kmmac.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmac.u: 0
     rs1:
       <<: *all_regs
@@ -2297,7 +2297,7 @@ kmmac.u:
 kmmsb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmsb: 0
     rs1:
       <<: *all_regs
@@ -2315,7 +2315,7 @@ kmmsb:
 kmmsb.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmsb.u: 0
     rs1:
       <<: *all_regs
@@ -2333,7 +2333,7 @@ kmmsb.u:
 kwmmul:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kwmmul: 0
     rs1:
       <<: *all_regs
@@ -2351,7 +2351,7 @@ kwmmul:
 kwmmul.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kwmmul.u: 0
     rs1:
       <<: *all_regs
@@ -2372,7 +2372,7 @@ kwmmul.u:
 smmwb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smmwb: 0
     rs1:
       <<: *all_regs
@@ -2390,7 +2390,7 @@ smmwb:
 smmwb.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smmwb.u: 0
     rs1:
       <<: *all_regs
@@ -2408,7 +2408,7 @@ smmwb.u:
 smmwt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smmwt: 0
     rs1:
       <<: *all_regs
@@ -2426,7 +2426,7 @@ smmwt:
 smmwt.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smmwt.u: 0
     rs1:
       <<: *all_regs
@@ -2445,7 +2445,7 @@ smmwt.u:
 kmmawb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawb: 0
     rs1:
       <<: *all_regs
@@ -2463,7 +2463,7 @@ kmmawb:
 kmmawb.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawb.u: 0
     rs1:
       <<: *all_regs
@@ -2481,7 +2481,7 @@ kmmawb.u:
 kmmawt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawt: 0
     rs1:
       <<: *all_regs
@@ -2499,7 +2499,7 @@ kmmawt:
 kmmawt.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawt.u: 0
     rs1:
       <<: *all_regs
@@ -2518,7 +2518,7 @@ kmmawt.u:
 kmmwb2:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmwb2: 0
     rs1:
       <<: *all_regs
@@ -2536,7 +2536,7 @@ kmmwb2:
 kmmwb2.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmwb2.u: 0
     rs1:
       <<: *all_regs
@@ -2554,7 +2554,7 @@ kmmwb2.u:
 kmmwt2:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmwt2: 0
     rs1:
       <<: *all_regs
@@ -2572,7 +2572,7 @@ kmmwt2:
 kmmwt2.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmwt2.u: 0
     rs1:
       <<: *all_regs
@@ -2591,7 +2591,7 @@ kmmwt2.u:
 kmmawb2:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawb2: 0
     rs1:
       <<: *all_regs
@@ -2609,7 +2609,7 @@ kmmawb2:
 kmmawb2.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawb2.u: 0
     rs1:
       <<: *all_regs
@@ -2627,7 +2627,7 @@ kmmawb2.u:
 kmmawt2:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawt2: 0
     rs1:
       <<: *all_regs
@@ -2645,7 +2645,7 @@ kmmawt2:
 kmmawt2.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmmawt2.u: 0
     rs1:
       <<: *all_regs
@@ -2665,7 +2665,7 @@ kmmawt2.u:
 smbb16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smbb16: 0
     rs1:
       <<: *all_regs
@@ -2684,7 +2684,7 @@ smbb16:
 smbt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smbt16: 0
     rs1:
       <<: *all_regs
@@ -2703,7 +2703,7 @@ smbt16:
 smtt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smtt16: 0
     rs1:
       <<: *all_regs
@@ -2722,7 +2722,7 @@ smtt16:
 kmda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmda: 0
     rs1:
       <<: *all_regs
@@ -2741,7 +2741,7 @@ kmda:
 kmxda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmxda: 0
     rs1:
       <<: *all_regs
@@ -2759,7 +2759,7 @@ kmxda:
 smds:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smds: 0
     rs1:
       <<: *all_regs
@@ -2778,7 +2778,7 @@ smds:
 smdrs:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smdrs: 0
     rs1:
       <<: *all_regs
@@ -2797,7 +2797,7 @@ smdrs:
 smxds:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smxds: 0
     rs1:
       <<: *all_regs
@@ -2816,7 +2816,7 @@ smxds:
 kmabb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmabb: 0
     rs1:
       <<: *all_regs
@@ -2835,7 +2835,7 @@ kmabb:
 kmabt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmabt: 0
     rs1:
       <<: *all_regs
@@ -2854,7 +2854,7 @@ kmabt:
 kmatt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmatt: 0
     rs1:
       <<: *all_regs
@@ -2873,7 +2873,7 @@ kmatt:
 kmada:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmada: 0
     rs1:
       <<: *all_regs
@@ -2892,7 +2892,7 @@ kmada:
 kmaxda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmaxda: 0
     rs1:
       <<: *all_regs
@@ -2911,7 +2911,7 @@ kmaxda:
 kmads:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmads: 0
     rs1:
       <<: *all_regs
@@ -2930,7 +2930,7 @@ kmads:
 kmadrs:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmadrs: 0
     rs1:
       <<: *all_regs
@@ -2949,7 +2949,7 @@ kmadrs:
 kmaxds:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmaxds: 0
     rs1:
       <<: *all_regs
@@ -2968,7 +2968,7 @@ kmaxds:
 kmsda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmsda: 0
     rs1:
       <<: *all_regs
@@ -2987,7 +2987,7 @@ kmsda:
 kmsxda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmsxda: 0
     rs1:
       <<: *all_regs
@@ -3007,7 +3007,7 @@ kmsxda:
 smal:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smal: 0
     rs1:
       <<: *pair_regs
@@ -3027,7 +3027,7 @@ smal:
 sclip32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sclip32: 0
     rs1:
       <<: *all_regs
@@ -3043,7 +3043,7 @@ sclip32:
 uclip32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uclip32: 0
     rs1:
       <<: *all_regs
@@ -3059,7 +3059,7 @@ uclip32:
 clrs32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       clrs32: 0
     rs1:
       <<: *all_regs
@@ -3073,7 +3073,7 @@ clrs32:
 # clz32:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       clz32: 0
 #     rs1:
 #       <<: *all_regs
@@ -3086,7 +3086,7 @@ clrs32:
 pbsad:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       pbsad: 0
     rs1:
       <<: *all_regs
@@ -3105,7 +3105,7 @@ pbsad:
 pbsada:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       pbsada: 0
     rs1:
       <<: *all_regs
@@ -3124,7 +3124,7 @@ pbsada:
 smaqa:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smaqa: 0
     rs1:
       <<: *all_regs
@@ -3143,7 +3143,7 @@ smaqa:
 umaqa:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umaqa: 0
     rs1:
       <<: *all_regs
@@ -3162,7 +3162,7 @@ umaqa:
 smaqa.su:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smaqa.su: 0
     rs1:
       <<: *all_regs
@@ -3182,7 +3182,7 @@ smaqa.su:
 add64:
     config:
       - check ISA:=regex(.*32.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       add64: 0
     rs1:
       <<: *pair_regs
@@ -3200,7 +3200,7 @@ add64:
 radd64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       radd64: 0
     rs1:
       <<: *pair_regs
@@ -3218,7 +3218,7 @@ radd64:
 uradd64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uradd64: 0
     rs1:
       <<: *pair_regs
@@ -3236,7 +3236,7 @@ uradd64:
 kadd64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kadd64: 0
     rs1:
       <<: *pair_regs
@@ -3254,7 +3254,7 @@ kadd64:
 ukadd64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukadd64: 0
     rs1:
       <<: *pair_regs
@@ -3272,7 +3272,7 @@ ukadd64:
 sub64:
     config:
       - check ISA:=regex(.*32.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sub64: 0
     rs1:
       <<: *pair_regs
@@ -3290,7 +3290,7 @@ sub64:
 rsub64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rsub64: 0
     rs1:
       <<: *pair_regs
@@ -3308,7 +3308,7 @@ rsub64:
 ursub64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ursub64: 0
     rs1:
       <<: *pair_regs
@@ -3326,7 +3326,7 @@ ursub64:
 ksub64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksub64: 0
     rs1:
       <<: *pair_regs
@@ -3344,7 +3344,7 @@ ksub64:
 uksub64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uksub64: 0
     rs1:
       <<: *pair_regs
@@ -3363,7 +3363,7 @@ uksub64:
 smar64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smar64: 0
     rs1:
       <<: *all_regs
@@ -3382,7 +3382,7 @@ smar64:
 smsr64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smsr64: 0
     rs1:
       <<: *all_regs
@@ -3401,7 +3401,7 @@ smsr64:
 umar64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umar64: 0
     rs1:
       <<: *all_regs
@@ -3420,7 +3420,7 @@ umar64:
 umsr64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       umsr64: 0
     rs1:
       <<: *all_regs
@@ -3439,7 +3439,7 @@ umsr64:
 kmar64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmar64: 0
     rs1:
       <<: *all_regs
@@ -3458,7 +3458,7 @@ kmar64:
 kmsr64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmsr64: 0
     rs1:
       <<: *all_regs
@@ -3477,7 +3477,7 @@ kmsr64:
 ukmar64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukmar64: 0
     rs1:
       <<: *all_regs
@@ -3496,7 +3496,7 @@ ukmar64:
 ukmsr64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukmsr64: 0
     rs1:
       <<: *all_regs
@@ -3516,7 +3516,7 @@ ukmsr64:
 smalbb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smalbb: 0
     rs1:
       <<: *all_regs
@@ -3535,7 +3535,7 @@ smalbb:
 smalbt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smalbt: 0
     rs1:
       <<: *all_regs
@@ -3554,7 +3554,7 @@ smalbt:
 smaltt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smaltt: 0
     rs1:
       <<: *all_regs
@@ -3573,7 +3573,7 @@ smaltt:
 smalda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smalda: 0
     rs1:
       <<: *all_regs
@@ -3592,7 +3592,7 @@ smalda:
 smalxda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smalxda: 0
     rs1:
       <<: *all_regs
@@ -3611,7 +3611,7 @@ smalxda:
 smalds:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smalds: 0
     rs1:
       <<: *all_regs
@@ -3630,7 +3630,7 @@ smalds:
 smaldrs:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smaldrs: 0
     rs1:
       <<: *all_regs
@@ -3649,7 +3649,7 @@ smaldrs:
 smalxds:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smalxds: 0
     rs1:
       <<: *all_regs
@@ -3668,7 +3668,7 @@ smalxds:
 smslda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smslda: 0
     rs1:
       <<: *all_regs
@@ -3687,7 +3687,7 @@ smslda:
 smslxda:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smslxda: 0
     rs1:
       <<: *all_regs
@@ -3708,7 +3708,7 @@ smslxda:
 kaddh:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kaddh: 0
     rs1:
       <<: *all_regs
@@ -3727,7 +3727,7 @@ kaddh:
 ksubh:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksubh: 0
     rs1:
       <<: *all_regs
@@ -3746,7 +3746,7 @@ ksubh:
 khmbb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khmbb: 0
     rs1:
       <<: *all_regs
@@ -3765,7 +3765,7 @@ khmbb:
 khmbt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khmbt: 0
     rs1:
       <<: *all_regs
@@ -3784,7 +3784,7 @@ khmbt:
 khmtt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       khmtt: 0
     rs1:
       <<: *all_regs
@@ -3803,7 +3803,7 @@ khmtt:
 ukaddh:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukaddh: 0
     rs1:
       <<: *all_regs
@@ -3822,7 +3822,7 @@ ukaddh:
 uksubh:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uksubh: 0
     rs1:
       <<: *all_regs
@@ -3841,7 +3841,7 @@ uksubh:
 kaddw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kaddw: 0
     rs1:
       <<: *all_regs
@@ -3860,7 +3860,7 @@ kaddw:
 ukaddw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukaddw: 0
     rs1:
       <<: *all_regs
@@ -3879,7 +3879,7 @@ ukaddw:
 ksubw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksubw: 0
     rs1:
       <<: *all_regs
@@ -3898,7 +3898,7 @@ ksubw:
 uksubw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uksubw: 0
     rs1:
       <<: *all_regs
@@ -3917,7 +3917,7 @@ uksubw:
 kdmbb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmbb: 0
     rs1:
       <<: *all_regs
@@ -3936,7 +3936,7 @@ kdmbb:
 kdmbt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmbt: 0
     rs1:
       <<: *all_regs
@@ -3955,7 +3955,7 @@ kdmbt:
 kdmtt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmtt: 0
     rs1:
       <<: *all_regs
@@ -3974,7 +3974,7 @@ kdmtt:
 kslraw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslraw: 0
     rs1:
       <<: *all_regs
@@ -3993,7 +3993,7 @@ kslraw:
 kslraw.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslraw.u: 0
     rs1:
       <<: *all_regs
@@ -4004,16 +4004,16 @@ kslraw.u:
     op_comb:
       <<: *rfmt_op_comb
     val_comb:
+      'rs1_w0_val == rs2_w0_val': 0
+      'rs1_w0_val != rs2_w0_val': 0
       abstract_comb:
         'simd_base_val("rs1", xlen, 32, signed=False)': 0
         'simd_base_val("rs2", xlen, 32, signed=True)': 0
-        'rs1_val == rs2_val': 0
-        'rs1_val != rs2_val': 0
 
 ksllw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksllw: 0
     rs1:
       <<: *all_regs
@@ -4033,7 +4033,7 @@ ksllw:
 kslliw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kslliw: 0
     rs1:
       <<: *all_regs
@@ -4049,7 +4049,7 @@ kslliw:
 kdmabb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmabb: 0
     rs1:
       <<: *all_regs
@@ -4068,7 +4068,7 @@ kdmabb:
 kdmabt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmabt: 0
     rs1:
       <<: *all_regs
@@ -4087,7 +4087,7 @@ kdmabt:
 kdmatt:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmatt: 0
     rs1:
       <<: *all_regs
@@ -4106,7 +4106,7 @@ kdmatt:
 kabsw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kabsw: 0
     rs1:
       <<: *all_regs
@@ -4120,7 +4120,7 @@ kabsw:
 raddw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       raddw: 0
     rs1:
       <<: *all_regs
@@ -4138,7 +4138,7 @@ raddw:
 uraddw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uraddw: 0
     rs1:
       <<: *all_regs
@@ -4156,7 +4156,7 @@ uraddw:
 rsubw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rsubw: 0
     rs1:
       <<: *all_regs
@@ -4174,7 +4174,7 @@ rsubw:
 ursubw:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ursubw: 0
     rs1:
       <<: *all_regs
@@ -4192,7 +4192,7 @@ ursubw:
 mulr64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       mulr64: 0
     rs1:
       <<: *all_regs
@@ -4209,7 +4209,7 @@ mulr64:
 mulsr64:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       mulsr64: 0
     rs1:
       <<: *all_regs
@@ -4227,7 +4227,7 @@ mulsr64:
 maddr32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       maddr32: 0
     rs1:
       <<: *all_regs
@@ -4245,7 +4245,7 @@ maddr32:
 msubr32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       msubr32: 0
     rs1:
       <<: *all_regs
@@ -4265,7 +4265,7 @@ msubr32:
 # rdov:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       rdov: 0
 #     rd:
 #       <<: *all_regs
@@ -4274,7 +4274,7 @@ msubr32:
 # clrov:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       clrov: 0
 #     rd:
 #       <<: *all_regs
@@ -4283,7 +4283,7 @@ msubr32:
 ave:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ave: 0
     rs1:
       <<: *all_regs
@@ -4301,7 +4301,7 @@ ave:
 sra.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sra.u: 0
     rs1:
       <<: *all_regs
@@ -4319,7 +4319,7 @@ sra.u:
 srai.u:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       srai.u: 0
     rs1:
       <<: *all_regs
@@ -4336,7 +4336,7 @@ srai.u:
 # bitrev:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       bitrev: 0
 #     rs1:
 #       <<: *all_regs
@@ -4355,7 +4355,7 @@ srai.u:
 # bitrevi:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       bitrevi: 0
 #     rs1:
 #       <<: *all_regs
@@ -4371,7 +4371,7 @@ srai.u:
 # wext:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       wext: 0
 #     rs1:
 #       <<: *pair_regs
@@ -4389,7 +4389,7 @@ srai.u:
 # wexti:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       wexti: 0
 #     rs1:
 #       <<: *pair_regs
@@ -4405,7 +4405,7 @@ srai.u:
 insb:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       insb: 0
     rs1:
       <<: *all_regs
diff --git a/sample_cgfs/rv32zabha.cgf b/sample_cgfs/rv32zabha.cgf
new file mode 100644
index 00000000..754130df
--- /dev/null
+++ b/sample_cgfs/rv32zabha.cgf
@@ -0,0 +1,362 @@
+amoadd.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoadd.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoand.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoand.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoswap.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoswap.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoxor.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoxor.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoor.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoor.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomin.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amomin.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amominu.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amominu.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomax.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amomax.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomaxu.b:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amomaxu.b: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amocas.b:
+    config:
+      - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*)
+    mnemonics:
+      amocas.b: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+
+amoadd.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoadd.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoand.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoand.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoswap.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoswap.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoxor.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoxor.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoor.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amoor.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomin.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amomin.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amominu.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amominu.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomax.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amomax.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomaxu.h:
+    config: 
+      - check ISA:=regex(.*I.*A.*Zabha.*)
+    mnemonics: 
+      amomaxu.h: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amocas.h:
+    config:
+      - check ISA:=regex(.*I.*A.*Zabha.*Zacas.*)
+    mnemonics:
+      amocas.h: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+
diff --git a/sample_cgfs/rv32zacas.cgf b/sample_cgfs/rv32zacas.cgf
new file mode 100644
index 00000000..70935c46
--- /dev/null
+++ b/sample_cgfs/rv32zacas.cgf
@@ -0,0 +1,36 @@
+# cover group format file for Zacas extension
+amocas.w:
+    config: 
+      - check ISA:=regex(.*Zacas.*)
+    mnemonics: 
+      amocas.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+amocas.d_32:
+    config:
+      - check ISA:=regex(.*Zacas.*)
+    mnemonics:
+      amocas.d_32: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *pair_regs
+    rd:
+      <<: *pair_regs
+    op_comb:
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn]
+      abstract_comb:
+        <<: [*zacas64_rs1val_walking_sgn, *zacas64_rs2val_walking_sgn]
diff --git a/sample_cgfs/rv64i.cgf b/sample_cgfs/rv64i.cgf
index c499bb47..0a4a816d 100644
--- a/sample_cgfs/rv64i.cgf
+++ b/sample_cgfs/rv64i.cgf
@@ -3,13 +3,13 @@
 fence:
   config: 
     - check ISA:=regex(.*I.*)
-  opcode: 
+  mnemonics: 
     fence: 0
 
 addi:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       addi: 0
     rs1: 
       <<: *all_regs
@@ -26,7 +26,7 @@ addi:
 slti:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       slti: 0
     rs1: 
       <<: *all_regs
@@ -43,7 +43,7 @@ slti:
 sltiu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sltiu: 0
     rs1: 
       <<: *all_regs
@@ -60,7 +60,7 @@ sltiu:
 andi:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       andi: 0
     rs1: 
       <<: *all_regs
@@ -77,7 +77,7 @@ andi:
 ori:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       ori: 0
     rs1: 
       <<: *all_regs
@@ -94,7 +94,7 @@ ori:
 xori:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       xori: 0
     rs1: 
       <<: *all_regs
@@ -111,7 +111,7 @@ xori:
 slli:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       slli: 0
     rs1: 
       <<: *all_regs
@@ -131,7 +131,7 @@ slli:
 srai:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       srai: 0
     rs1: 
       <<: *all_regs
@@ -151,7 +151,7 @@ srai:
 srli:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       srli: 0
     rs1: 
       <<: *all_regs
@@ -171,7 +171,7 @@ srli:
 add:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       add: 0
     rs1: 
       <<: *all_regs
@@ -190,7 +190,7 @@ add:
 sub:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sub: 0
     rs1: 
       <<: *all_regs
@@ -209,7 +209,7 @@ sub:
 slt:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       slt: 0
     rs1: 
       <<: *all_regs
@@ -228,7 +228,7 @@ slt:
 sltu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sltu: 0
     rs1: 
       <<: *all_regs
@@ -247,7 +247,7 @@ sltu:
 and:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       and: 0
     rs1: 
       <<: *all_regs
@@ -266,7 +266,7 @@ and:
 or:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       or: 0
     rs1: 
       <<: *all_regs
@@ -285,7 +285,7 @@ or:
 xor:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       xor: 0
     rs1: 
       <<: *all_regs
@@ -304,7 +304,7 @@ xor:
 sll:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sll: 0
     rs1: 
       <<: *all_regs
@@ -326,7 +326,7 @@ sll:
 srl:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       srl: 0
     rs1: 
       <<: *all_regs
@@ -348,7 +348,7 @@ srl:
 sra:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sra: 0
     rs1: 
       <<: *all_regs
@@ -370,7 +370,7 @@ sra:
 beq:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       beq: 0
     rs1: 
       <<: *all_regs
@@ -387,7 +387,7 @@ beq:
 bge:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bge: 0
     rs1: 
       <<: *all_regs
@@ -404,7 +404,7 @@ bge:
 bgeu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bgeu: 0
     rs1: 
       <<: *all_regs
@@ -421,7 +421,7 @@ bgeu:
 blt:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       blt: 0
     rs1: 
       <<: *all_regs
@@ -438,7 +438,7 @@ blt:
 bltu:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bltu: 0
     rs1: 
       <<: *all_regs
@@ -455,7 +455,7 @@ bltu:
 bne:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       bne: 0
     rs1: 
       <<: *all_regs
@@ -472,7 +472,7 @@ bne:
 lhu-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lhu: 0
     rs1: 
       <<: *all_regs_mx0
@@ -496,7 +496,7 @@ lhu-align:
 lh-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lh: 0
     rs1: 
       <<: *all_regs_mx0
@@ -520,7 +520,7 @@ lh-align:
 lbu-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lbu: 0
     rs1: 
       <<: *all_regs_mx0
@@ -552,7 +552,7 @@ lbu-align:
 lb-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lb: 0
     rs1: 
       <<: *all_regs_mx0
@@ -584,7 +584,7 @@ lb-align:
 lw-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lw: 0
     rs1: 
       <<: *all_regs_mx0
@@ -605,7 +605,7 @@ lw-align:
 sh-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sh: 0
     rs1: 
       <<: *all_regs_mx0
@@ -632,7 +632,7 @@ sh-align:
 sb-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sb: 0
     rs1: 
       <<: *all_regs_mx0
@@ -667,7 +667,7 @@ sb-align:
 sw-align:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       sw: 0
     rs1: 
       <<: *all_regs_mx0
@@ -690,7 +690,7 @@ sw-align:
 auipc:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       auipc: 0
     rd: 
       <<: *all_regs
@@ -707,7 +707,7 @@ auipc:
 lui:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       lui: 0
     rd: 
       <<: *all_regs
@@ -724,7 +724,7 @@ lui:
 jal:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       jal: 0
     rd: 
       <<: *all_regs
@@ -737,7 +737,7 @@ jal:
 jalr:
     config: 
       - check ISA:=regex(.*I.*)
-    opcode: 
+    mnemonics: 
       jalr: 0
     rs1:
       <<: *all_regs_mx0
@@ -754,7 +754,7 @@ jalr:
 lwu-align:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       lwu: 0
     rs1: 
       <<: *all_regs_mx0
@@ -774,7 +774,7 @@ lwu-align:
 ld-align:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       ld: 0
     rs1: 
       <<: *all_regs_mx0
@@ -798,7 +798,7 @@ ld-align:
 sd-align:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       sd: 0
     rs1: 
       <<: *all_regs_mx0
@@ -825,7 +825,7 @@ sd-align:
 addiw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       addiw: 0
     rs1: 
       <<: *all_regs
@@ -842,7 +842,7 @@ addiw:
 slliw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       slliw: 0
     rs1: 
       <<: *all_regs
@@ -862,7 +862,7 @@ slliw:
 srliw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       srliw: 0
     rs1: 
       <<: *all_regs
@@ -882,7 +882,7 @@ srliw:
 sraiw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       sraiw: 0
     rs1: 
       <<: *all_regs
@@ -902,7 +902,7 @@ sraiw:
 addw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       addw: 0
     rs1: 
       <<: *all_regs
@@ -921,7 +921,7 @@ addw:
 subw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       subw: 0
     rs1: 
       <<: *all_regs
@@ -940,7 +940,7 @@ subw:
 sllw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       sllw: 0
     rs1: 
       <<: *all_regs
@@ -962,7 +962,7 @@ sllw:
 srlw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       srlw: 0
     rs1: 
       <<: *all_regs
@@ -983,7 +983,7 @@ srlw:
 sraw:
     config: 
       - check ISA:=regex(.*RV64.*I.*)
-    opcode: 
+    mnemonics: 
       sraw: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/rv64i_b.cgf b/sample_cgfs/rv64i_b.cgf
index 7fc20838..5cd7cca4 100644
--- a/sample_cgfs/rv64i_b.cgf
+++ b/sample_cgfs/rv64i_b.cgf
@@ -1,5 +1,6 @@
 add.uw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zba.*)
     mnemonics: 	
       add.uw: 0
@@ -19,6 +20,7 @@ add.uw:
         
 sh1add:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zba.*)
     mnemonics: 
       sh1add: 0
@@ -39,6 +41,7 @@ sh1add:
         
 sh1add.uw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zba.*)
     mnemonics: 
       sh1add.uw: 0
@@ -58,6 +61,7 @@ sh1add.uw:
         
 sh2add:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zba.*)
     mnemonics: 
       sh2add: 0
@@ -77,6 +81,7 @@ sh2add:
         
 sh2add.uw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zba.*)
     mnemonics: 
       sh2add.uw: 0
@@ -96,6 +101,7 @@ sh2add.uw:
         
 sh3add:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zba.*)
     mnemonics: 
       sh3add: 0
@@ -115,6 +121,7 @@ sh3add:
         
 sh3add.uw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zba.*)
     mnemonics: 
       sh3add.uw: 0
@@ -134,6 +141,7 @@ sh3add.uw:
         
 slli.uw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zba.*)
     mnemonics: 
       slli.uw: 0
@@ -153,6 +161,7 @@ slli.uw:
 
 xnor:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -177,6 +186,7 @@ xnor:
         
 zext.h_64:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       zext.h: 0
@@ -198,6 +208,7 @@ zext.h_64:
         'uniform_random(20, 100, ["rs1_val"], [xlen])': 0
 andn:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -222,6 +233,7 @@ andn:
 
 clz:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       clz: 0
@@ -234,14 +246,15 @@ clz:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
 
         
 clzw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zbb.*)
     mnemonics: 
       clzw: 0
@@ -254,13 +267,14 @@ clzw:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
         
 ctz:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       ctz: 0
@@ -273,13 +287,14 @@ ctz:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
         
 ctzw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zbb.*)
     mnemonics: 
       ctzw: 0
@@ -292,14 +307,15 @@ ctzw:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
 
         
 cpop:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       cpop: 0
@@ -312,13 +328,14 @@ cpop:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
         
 cpopw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zbb.*)
     mnemonics: 
       cpopw: 0
@@ -331,13 +348,14 @@ cpopw:
     val_comb:
       abstract_comb:
         <<: [*rs1val_walking_unsgn]
-        'leading_zeros("rs1_val", xlen, False)': 0
-        'leading_ones("rs1_val", xlen, False)': 0
-        'trailing_zeros("rs1_val", xlen, False)': 0
-        'trailing_ones("rs1_val", xlen, False)': 0
+        'leading_zeros(xlen, ["rs1_val"], [xlen], 11)': 0
+        'leading_ones(xlen, ["rs1_val"], [xlen], 10)': 0
+        'trailing_zeros(xlen, ["rs1_val"], [xlen], 12)': 0
+        'trailing_ones(xlen, ["rs1_val"], [xlen], 13)': 0
         
 max:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       max: 0
@@ -357,6 +375,7 @@ max:
 
 maxu:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       maxu: 0
@@ -376,6 +395,7 @@ maxu:
         
 min:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       min: 0
@@ -395,6 +415,7 @@ min:
         
 minu:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       minu: 0
@@ -414,6 +435,7 @@ minu:
         
 orcb_64:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       orc.b: 0
@@ -436,6 +458,7 @@ orcb_64:
         
 orn:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -460,6 +483,7 @@ orn:
 
 rev8:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -489,6 +513,7 @@ rev8:
         
 rol:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -513,6 +538,7 @@ rol:
 
 rolw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zbb.*)
       - check ISA:=regex(.*RV64.*I.*Zbkb.*)
       - check ISA:=regex(.*RV64.*I.*Zk.*)
@@ -537,6 +563,7 @@ rolw:
         
 ror:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -561,6 +588,7 @@ ror:
         
 rori:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
       - check ISA:=regex(.*I.*Zbkb.*)
       - check ISA:=regex(.*I.*Zk.*)
@@ -584,6 +612,7 @@ rori:
         
 roriw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zbb.*)
       - check ISA:=regex(.*RV64.*I.*Zbkb.*)
       - check ISA:=regex(.*RV64.*I.*Zk.*)
@@ -606,6 +635,7 @@ roriw:
 
 rorw:
     config: 
+      - check ISA:=regex(.*RV64.*I.*B.*)
       - check ISA:=regex(.*RV64.*I.*Zbb.*)
       - check ISA:=regex(.*RV64.*I.*Zbkb.*)
       - check ISA:=regex(.*RV64.*I.*Zk.*)
@@ -631,6 +661,7 @@ rorw:
         
 sext.b:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       sext.b: 0
@@ -650,6 +681,7 @@ sext.b:
 
 sext.h:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbb.*)
     mnemonics: 
       sext.h: 0
@@ -751,6 +783,7 @@ clmulr:
 
 bclr:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bclr: 0
@@ -764,8 +797,8 @@ bclr:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -777,6 +810,7 @@ bclr:
         
 bclri:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bclri: 0
@@ -788,7 +822,7 @@ bclri:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0
@@ -797,6 +831,7 @@ bclri:
         
 bext:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bext: 0
@@ -810,8 +845,8 @@ bext:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -823,6 +858,7 @@ bext:
         
 bexti:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bexti: 0
@@ -834,7 +870,7 @@ bexti:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0
@@ -843,6 +879,7 @@ bexti:
         
 binv:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       binv: 0
@@ -856,8 +893,8 @@ binv:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -869,6 +906,7 @@ binv:
         
 binvi:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       binvi: 0
@@ -880,7 +918,7 @@ binvi:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0
@@ -888,6 +926,7 @@ binvi:
         
 bset:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bset: 0
@@ -901,8 +940,8 @@ bset:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:
-        'xlenlim("rs1_val", xlen)': 0
-        'xlenlim("rs2_val", xlen )': 0
+#        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs2_val", xlen )': 0
         'walking_ones("rs1_val", ceil(log(xlen, 2)), False)': 0
         'walking_ones("rs2_val", ceil(log(xlen, 2)), False)': 0
         'leading_ones(64, ["rs1_val", "rs2_val"], [32,5])': 0
@@ -915,6 +954,7 @@ bset:
         
 bseti:
     config: 
+      - check ISA:=regex(.*I.*B.*)
       - check ISA:=regex(.*I.*Zbs.*)
     mnemonics: 
       bseti: 0
@@ -926,7 +966,7 @@ bseti:
       <<: *ifmt_op_comb
     val_comb:
       abstract_comb:      
-        'xlenlim("rs1_val", xlen)': 0
+#        'xlenlim("rs1_val", xlen)': 0
         'leading_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'trailing_ones(64, ["rs1_val", "imm_val"], [32,5])': 0
         'leading_zeros(64, ["rs1_val", "imm_val"], [32,5])': 0
diff --git a/sample_cgfs/rv64i_fencei.cgf b/sample_cgfs/rv64i_fencei.cgf
index 9a32e494..3397e5a0 100644
--- a/sample_cgfs/rv64i_fencei.cgf
+++ b/sample_cgfs/rv64i_fencei.cgf
@@ -2,7 +2,7 @@
 fencei:
   config: 
     - check ISA:=regex(.*I.*Zifencei.*)
-  opcode: 
+  mnemonics: 
     fence.i: 0
 
 
diff --git a/sample_cgfs/rv64i_k.cgf b/sample_cgfs/rv64i_k.cgf
index a4310aea..87d34b96 100644
--- a/sample_cgfs/rv64i_k.cgf
+++ b/sample_cgfs/rv64i_k.cgf
@@ -140,8 +140,9 @@ xperm8:
       <<: *rfmt_op_comb
     val_comb:
       abstract_comb:      
-        'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64],False)': 0
-        'walikng_ones(64, ["rs1_val","rs2_val"], [64,64])': 0
+        'uniform_random(20, 100, ["rs1_val","rs2_val"], [64, 64])': 0
+        'walking_ones("rs1_val", 64, False)': 0
+        'walking_ones("rs2_val", 64, False)': 0
         'trailing_ones(64, ["rs1_val","rs2_val"], [64,64],False)': 0
         'leading_zeros(64, ["rs1_val","rs2_val"], [64,64],False)': 0
         'trailing_zeros(64, ["rs1_val","rs2_val"], [64,64],False)': 0
diff --git a/sample_cgfs/rv64i_priv.cgf b/sample_cgfs/rv64i_priv.cgf
index 184d45e0..8babd644 100644
--- a/sample_cgfs/rv64i_priv.cgf
+++ b/sample_cgfs/rv64i_priv.cgf
@@ -1,13 +1,13 @@
 ecall:
   config: 
     - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True 
-  opcode: 
+  mnemonics: 
     ecall: 0
 
 ebreak:
   config: 
     - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True 
-  opcode: 
+  mnemonics: 
     ebreak: 0
 
 misalign-lh:
@@ -15,7 +15,7 @@ misalign-lh:
   config:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
-  opcode:
+  mnemonics:
     lh: 0
   val_comb:
     'ea_align == 1': 0
@@ -25,7 +25,7 @@ misalign-lhu:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     lhu: 0
   val_comb:
     'ea_align == 1': 0
@@ -35,7 +35,7 @@ misalign-lwu:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*64.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     lwu: 0
   val_comb:
     'ea_align == 1': 0
@@ -47,7 +47,7 @@ misalign-sd:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*64.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     sd: 0
   val_comb:
     'ea_align == 1': 0
@@ -63,7 +63,7 @@ misalign-ld:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*64.*I.*)
-  opcode:
+  mnemonics:
     ld: 0
   val_comb:
     'ea_align == 1': 0
@@ -79,7 +79,7 @@ misalign-lw:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     lw: 0
   val_comb:
     'ea_align == 1': 0
@@ -91,7 +91,7 @@ misalign-sh:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     sh: 0
   val_comb:
     'ea_align == 1': 0
@@ -101,7 +101,7 @@ misalign-sw:
     - check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True
     - check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True
   cond: check ISA:=regex(.*I.*Zicsr.*)
-  opcode:
+  mnemonics:
     sw: 0
   val_comb:
     'ea_align == 1': 0
@@ -113,7 +113,7 @@ misalign2-jalr:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     jalr: 0
   val_comb:
     'ea_align == 2': 0
@@ -121,7 +121,7 @@ misalign2-jalr:
 misalign1-jalr:
   config: 
     - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True
-  opcode:
+  mnemonics:
     jalr: 0
   val_comb:
     'ea_align == 1': 0
@@ -131,7 +131,7 @@ misalign-jal:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     jal: 0
   val_comb:
     'ea_align == 2': 0
@@ -141,7 +141,7 @@ misalign-bge:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bge: 0
   val_comb:
     ' rs1_val>rs2_val and ea_align == 2': 0
@@ -151,7 +151,7 @@ misalign-bgeu:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bgeu: 0
   val_comb:
     ' rs1_val>rs2_val and ea_align == 2': 0
@@ -161,7 +161,7 @@ misalign-blt:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     blt: 0
   val_comb:
     ' rs1_val<rs2_val and ea_align == 2': 0
@@ -171,7 +171,7 @@ misalign-bltu:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bltu: 0
   val_comb:
     ' rs1_val<rs2_val and ea_align == 2': 0
@@ -181,7 +181,7 @@ misalign-bne:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     bne: 0
   val_comb:
     ' rs1_val!=rs2_val and ea_align == 2': 0
@@ -191,7 +191,7 @@ misalign-beq:
     - check ISA:=regex(.*I.*C.*)
     - check ISA:=regex(.*I.*Zicsr.*); check ISA:=regex(^[^C]+$); def rvtest_mtrap_routine=True 
   cond: check ISA:=regex(.*I.*)
-  opcode:
+  mnemonics:
     beq: 0
   val_comb:
     ' rs1_val==rs2_val and ea_align == 2': 0
diff --git a/sample_cgfs/rv64i_zcb.cgf b/sample_cgfs/rv64i_zcb.cgf
new file mode 100644
index 00000000..3bad58b7
--- /dev/null
+++ b/sample_cgfs/rv64i_zcb.cgf
@@ -0,0 +1,190 @@
+
+clbu:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.lbu: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 1': 0
+        'imm_val == 2': 0
+        'imm_val == 3': 0
+
+clhu:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.lhu: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 2': 0
+
+clh:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.lh: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_regs
+    op_comb:
+        'rs1 == rd': 0
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 2': 0
+
+csb:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.sb: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 1': 0
+        'imm_val == 2': 0
+        'imm_val == 3': 0
+
+csh:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.sh: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_regs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val == 0': 0
+        'imm_val == 2': 0
+
+csext.b:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*)
+    mnemonics: 
+      c.sext.b: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x80': 0
+      'rs1_val == 0x8000': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+csext.h:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*)
+    mnemonics: 
+      c.sext.h: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+czext.b:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.zext.b: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x80': 0
+      'rs1_val == 0x8000': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+czext.h:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zbb.*)
+    mnemonics: 
+      c.zext.h: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+czext.w:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*.Zba.*)
+    mnemonics: 
+      c.zext.w: 0
+    rs1: 
+      <<: *c_regs
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+cnot:
+    config: 
+      - check ISA:=regex(.*I.*Zca.*Zcb.*)
+    mnemonics: 
+      c.not: 0
+    rs1: 
+      <<: *c_regs
+    op_comb:
+      <<: *r0fmt_op_comb
+    val_comb:
+      'rs1_val == 0': 0
+      'rs1_val == 0x800': 0
+      'rs1_val == 0xFF80': 0
+      abstract_comb:
+        'walking_ones("rs1_val", xlen, False)': 0
+        'walking_zeros("rs1_val", xlen, False)': 0
+
+cmul:
+    config: 
+      - check ISA:=regex(.*I.*M.*Zca.*Zcb.*)
+    mnemonics: 
+      c.mul: 0
+    rs1:
+      <<: *c_regs
+    rs2:
+      <<: *c_regs
+    op_comb:
+      <<: *sfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
diff --git a/sample_cgfs/rv64ia.cgf b/sample_cgfs/rv64ia.cgf
new file mode 100644
index 00000000..2cd7895d
--- /dev/null
+++ b/sample_cgfs/rv64ia.cgf
@@ -0,0 +1,341 @@
+amoadd.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoadd.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoand.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoand.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoswap.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoswap.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoxor.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoxor.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoor.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoor.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomin.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amomin.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amominu.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amominu.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomax.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amomax.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomaxu.w:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amomaxu.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoadd.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoadd.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoand.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoand.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoswap.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoswap.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoxor.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoxor.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amoor.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amoor.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomin.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amomin.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amominu.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amominu.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomax.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amomax.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+amomaxu.d:
+    config: 
+      - check ISA:=regex(.*64.*I.*A.*)
+      - check ISA:=regex(.*64.*I.*Zaamo.*)
+    mnemonics: 
+      amomaxu.d: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
diff --git a/sample_cgfs/rv64ic.cgf b/sample_cgfs/rv64ic.cgf
index f6acf8f4..9492e1d7 100644
--- a/sample_cgfs/rv64ic.cgf
+++ b/sample_cgfs/rv64ic.cgf
@@ -3,13 +3,13 @@
 cebreak:
   config: 
     - check ISA:=regex(.*I.*C.*)
-  opcode: 
+  mnemonics: 
     c.ebreak: 0
 
 caddi4spn:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addi4spn: 0
     rd:
       <<: *c_regs
@@ -24,7 +24,7 @@ caddi4spn:
 clw:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.lw: 0
     rs1: 
       <<: *c_regs
@@ -44,7 +44,7 @@ clw:
 cld:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.ld: 0
     rs1: 
       <<: *c_regs
@@ -64,7 +64,7 @@ cld:
 csw:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.sw: 0
     rs1: 
       <<: *c_regs
@@ -85,7 +85,7 @@ csw:
 csd:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.sd: 0
     rs1: 
       <<: *c_regs
@@ -106,7 +106,7 @@ csd:
 cnop:
     config: 
       - check ISA:=regex(.*I.*C.*) 
-    opcode: 
+    mnemonics: 
       c.nop: 0
     val_comb:
       abstract_comb:
@@ -115,7 +115,7 @@ cnop:
 caddi:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addi: 0
     rd:
       <<: *all_regs_mx0
@@ -128,7 +128,7 @@ caddi:
 caddiw:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*) 
-    opcode: 
+    mnemonics: 
       c.addiw: 0
     rd: 
       <<: *all_regs_mx0
@@ -148,7 +148,7 @@ caddiw:
 cli:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.li: 0
   rd:
     <<: *all_regs
@@ -162,7 +162,7 @@ cli:
 caddi16sp:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addi16sp: 0
     rd:
       x2: 0
@@ -179,7 +179,7 @@ caddi16sp:
 clui:
   config: 
     - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.lui: 0
   rd:
     x0: 0
@@ -227,7 +227,7 @@ clui:
 csrli:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.srli: 0
   rs1:
     <<: *c_regs
@@ -249,7 +249,7 @@ csrli:
 csrai:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.srai: 0
   rs1:
     <<: *c_regs
@@ -271,7 +271,7 @@ csrai:
 candi:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.andi: 0
     rs1:
       <<: *c_regs
@@ -284,7 +284,7 @@ candi:
 csub:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.sub: 0
     rs1:
       <<: *c_regs
@@ -301,7 +301,7 @@ csub:
 cxor:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.xor: 0
     rs1:
       <<: *c_regs
@@ -318,7 +318,7 @@ cxor:
 cor:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.or: 0
     rs1:
       <<: *c_regs
@@ -335,7 +335,7 @@ cor:
 cand:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.and: 0
     rs1:
       <<: *c_regs
@@ -352,7 +352,7 @@ cand:
 csubw:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.subw: 0
     rs1:
       <<: *c_regs
@@ -369,7 +369,7 @@ csubw:
 caddw:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.addw: 0
     rs1:
       <<: *c_regs
@@ -386,7 +386,7 @@ caddw:
 cj:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.j: 0
   val_comb:
     'imm_val > 0': 0
@@ -399,7 +399,7 @@ cj:
 cbeqz:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.beqz: 0
   rs1:
     <<: *c_regs
@@ -418,7 +418,7 @@ cbeqz:
 cbnez:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.bnez: 0
   rs1:
     <<: *c_regs
@@ -437,7 +437,7 @@ cbnez:
 cslli:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.slli: 0
   rd:
     <<: *c_regs
@@ -459,7 +459,7 @@ cslli:
 clwsp:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.lwsp: 0
     rd: 
       <<: *all_regs_mx0
@@ -474,7 +474,7 @@ clwsp:
 cldsp:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.ldsp: 0
     rd: 
       <<: *all_regs_mx0
@@ -489,15 +489,22 @@ cldsp:
 cjr:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.jr: 0
   rs1:
     <<: *all_regs_mx0
+  op_comb:
+    <<: *sfmt_op_comb
+  val_comb:
+    <<: *base_rs1val_sgn_rs2val_zero
+    abstract_comb:
+      'sp_dataset(xlen)': 0
+      <<: *rs1val_walking
 
 cmv:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.mv: 0
     rs2:
       <<: *all_regs_mx0
@@ -515,7 +522,7 @@ cmv:
 cadd:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.add: 0
     rs1:
       <<: *all_regs
@@ -532,15 +539,22 @@ cadd:
 cjalr:
   config: 
       - check ISA:=regex(.*I.*C.*) 
-  opcode: 
+  mnemonics: 
     c.jalr: 0
   rs1:
     <<: *all_regs_mx0
-
+  op_comb:
+    <<: *sfmt_op_comb
+  val_comb:
+    <<: *base_rs1val_sgn_rs2val_zero
+    abstract_comb:
+      'sp_dataset(xlen)': 0
+      <<: *rs1val_walking
+      
 cswsp:
     config: 
       - check ISA:=regex(.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.swsp: 0
     rs2: 
       <<: *all_regs_mx2
@@ -557,7 +571,7 @@ cswsp:
 csdsp:
     config: 
       - check ISA:=regex(.*RV64.*I.*C.*)
-    opcode: 
+    mnemonics: 
       c.sdsp: 0
     rs2: 
       <<: *all_regs_mx2
diff --git a/sample_cgfs/rv64im.cgf b/sample_cgfs/rv64im.cgf
index 87129aaf..92ac8c09 100644
--- a/sample_cgfs/rv64im.cgf
+++ b/sample_cgfs/rv64im.cgf
@@ -3,7 +3,7 @@
 mul:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mul: 0
     rs1: 
       <<: *all_regs
@@ -22,7 +22,7 @@ mul:
 mulh:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulh: 0
     rs1: 
       <<: *all_regs
@@ -41,7 +41,7 @@ mulh:
 mulhu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulhu: 0
     rs1: 
       <<: *all_regs
@@ -60,7 +60,7 @@ mulhu:
 mulhsu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulhsu: 0
     rs1: 
       <<: *all_regs
@@ -80,7 +80,7 @@ mulhsu:
 div:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       div: 0
     rs1: 
       <<: *all_regs
@@ -91,7 +91,7 @@ div:
     op_comb: 
       <<: *rfmt_op_comb
     val_comb:
-      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case]
       abstract_comb:
         'sp_dataset(xlen)': 0
         <<: [*rs1val_walking, *rs2val_walking]
@@ -99,7 +99,7 @@ div:
 divu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       divu: 0
     rs1: 
       <<: *all_regs
@@ -118,7 +118,7 @@ divu:
 rem:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       rem: 0
     rs1: 
       <<: *all_regs
@@ -129,7 +129,7 @@ rem:
     op_comb: 
       <<: *rfmt_op_comb
     val_comb:
-      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case]
       abstract_comb:
         'sp_dataset(xlen)': 0
         <<: [*rs1val_walking, *rs2val_walking]
@@ -137,7 +137,7 @@ rem:
 remu:
     config: 
       - check ISA:=regex(.*I.*M.*)
-    opcode: 
+    mnemonics: 
       remu: 0
     rs1: 
       <<: *all_regs
@@ -156,7 +156,7 @@ remu:
 mulw:
     config: 
       - check ISA:=regex(.*RV64.*I.*M.*)
-    opcode: 
+    mnemonics: 
       mulw: 0
     rs1: 
       <<: *all_regs
@@ -175,7 +175,7 @@ mulw:
 divw:
     config: 
       - check ISA:=regex(.*RV64.*I.*M.*)
-    opcode: 
+    mnemonics: 
       divw: 0
     rs1: 
       <<: *all_regs
@@ -186,7 +186,7 @@ divw:
     op_comb: 
       <<: *rfmt_op_comb
     val_comb:
-      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case]
       abstract_comb:
         'sp_dataset(xlen)': 0
         <<: [*rs1val_walking, *rs2val_walking]
@@ -194,7 +194,7 @@ divw:
 divuw:
     config: 
       - check ISA:=regex(.*RV64.*I.*M.*)
-    opcode: 
+    mnemonics: 
       divuw: 0
     rs1: 
       <<: *all_regs
@@ -213,7 +213,7 @@ divuw:
 remw:
     config: 
       - check ISA:=regex(.*RV64.*I.*M.*)
-    opcode: 
+    mnemonics: 
       remw: 0
     rs1: 
       <<: *all_regs
@@ -224,7 +224,7 @@ remw:
     op_comb: 
       <<: *rfmt_op_comb
     val_comb:
-      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn, *div_corner_case]
       abstract_comb:
         'sp_dataset(xlen)': 0
         <<: [*rs1val_walking, *rs2val_walking]
@@ -232,7 +232,7 @@ remw:
 remuw:
     config: 
       - check ISA:=regex(.*RV64.*I.*M.*)
-    opcode: 
+    mnemonics: 
       remuw: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/rv64ip.cgf b/sample_cgfs/rv64ip.cgf
index 6b2ed4ac..cf0ca4ba 100644
--- a/sample_cgfs/rv64ip.cgf
+++ b/sample_cgfs/rv64ip.cgf
@@ -3,7 +3,7 @@
 add32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       add32: 0
     rs1: 
       <<: *all_regs
@@ -22,7 +22,7 @@ add32:
 radd32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       radd32: 0
     rs1:
       <<: *all_regs
@@ -41,7 +41,7 @@ radd32:
 uradd32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uradd32: 0
     rs1:
       <<: *all_regs
@@ -60,7 +60,7 @@ uradd32:
 kadd32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kadd32: 0
     rs1:
       <<: *all_regs
@@ -79,7 +79,7 @@ kadd32:
 ukadd32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukadd32: 0
     rs1:
       <<: *all_regs
@@ -98,7 +98,7 @@ ukadd32:
 sub32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       sub32: 0
     rs1:
       <<: *all_regs
@@ -117,7 +117,7 @@ sub32:
 rsub32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rsub32: 0
     rs1:
       <<: *all_regs
@@ -137,7 +137,7 @@ rsub32:
 ursub32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ursub32: 0
     rs1:
       <<: *all_regs
@@ -156,7 +156,7 @@ ursub32:
 ksub32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ksub32: 0
     rs1:
       <<: *all_regs
@@ -175,7 +175,7 @@ ksub32:
 uksub32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       uksub32: 0
     rs1:
       <<: *all_regs
@@ -194,7 +194,7 @@ uksub32:
 cras32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       cras32: 0
     rs1:
       <<: *all_regs
@@ -213,7 +213,7 @@ cras32:
 rcras32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rcras32: 0
     rs1:
       <<: *all_regs
@@ -232,7 +232,7 @@ rcras32:
 urcras32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urcras32: 0
     rs1:
       <<: *all_regs
@@ -251,7 +251,7 @@ urcras32:
 kcras32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kcras32: 0
     rs1:
       <<: *all_regs
@@ -270,7 +270,7 @@ kcras32:
 ukcras32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukcras32: 0
     rs1:
       <<: *all_regs
@@ -289,7 +289,7 @@ ukcras32:
 crsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       crsa32: 0
     rs1:
       <<: *all_regs
@@ -308,7 +308,7 @@ crsa32:
 rcrsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rcrsa32: 0
     rs1:
       <<: *all_regs
@@ -327,7 +327,7 @@ rcrsa32:
 urcrsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urcrsa32: 0
     rs1:
       <<: *all_regs
@@ -346,7 +346,7 @@ urcrsa32:
 kcrsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kcrsa32: 0
     rs1:
       <<: *all_regs
@@ -365,7 +365,7 @@ kcrsa32:
 ukcrsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukcrsa32: 0
     rs1:
       <<: *all_regs
@@ -384,7 +384,7 @@ ukcrsa32:
 stas32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       stas32: 0
     rs1:
       <<: *all_regs
@@ -403,7 +403,7 @@ stas32:
 rstas32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rstas32: 0
     rs1:
       <<: *all_regs
@@ -422,7 +422,7 @@ rstas32:
 urstas32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urstas32: 0
     rs1:
       <<: *all_regs
@@ -441,7 +441,7 @@ urstas32:
 kstas32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kstas32: 0
     rs1:
       <<: *all_regs
@@ -460,7 +460,7 @@ kstas32:
 ukstas32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukstas32: 0
     rs1:
       <<: *all_regs
@@ -479,7 +479,7 @@ ukstas32:
 stsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       stsa32: 0
     rs1:
       <<: *all_regs
@@ -498,7 +498,7 @@ stsa32:
 rstsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       rstsa32: 0
     rs1:
       <<: *all_regs
@@ -517,7 +517,7 @@ rstsa32:
 urstsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       urstsa32: 0
     rs1:
       <<: *all_regs
@@ -536,7 +536,7 @@ urstsa32:
 kstsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kstsa32: 0
     rs1:
       <<: *all_regs
@@ -555,7 +555,7 @@ kstsa32:
 ukstsa32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       ukstsa32: 0
     rs1:
       <<: *all_regs
@@ -574,7 +574,7 @@ ukstsa32:
 sra32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       sra32: 0
     rs1: 
       <<: *all_regs
@@ -594,7 +594,7 @@ sra32:
 srai32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       srai32: 0
     rs1: 
       <<: *all_regs
@@ -610,7 +610,7 @@ srai32:
 sra32.u:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       sra32.u: 0
     rs1: 
       <<: *all_regs
@@ -630,7 +630,7 @@ sra32.u:
 srai32.u:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       srai32.u: 0
     rs1: 
       <<: *all_regs
@@ -646,7 +646,7 @@ srai32.u:
 srl32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       srl32: 0
     rs1: 
       <<: *all_regs
@@ -666,7 +666,7 @@ srl32:
 srli32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       srli32: 0
     rs1: 
       <<: *all_regs
@@ -682,7 +682,7 @@ srli32:
 srl32.u:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       srl32.u: 0
     rs1: 
       <<: *all_regs
@@ -702,7 +702,7 @@ srl32.u:
 srli32.u:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       srli32.u: 0
     rs1: 
       <<: *all_regs
@@ -718,7 +718,7 @@ srli32.u:
 sll32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       sll32: 0
     rs1: 
       <<: *all_regs
@@ -738,7 +738,7 @@ sll32:
 slli32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       slli32: 0
     rs1: 
       <<: *all_regs
@@ -754,7 +754,7 @@ slli32:
 ksll32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       ksll32: 0
     rs1: 
       <<: *all_regs
@@ -774,7 +774,7 @@ ksll32:
 kslli32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       kslli32: 0
     rs1: 
       <<: *all_regs
@@ -790,7 +790,7 @@ kslli32:
 kslra32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       kslra32: 0
     rs1: 
       <<: *all_regs
@@ -810,7 +810,7 @@ kslra32:
 kslra32.u:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       kslra32.u: 0
     rs1: 
       <<: *all_regs
@@ -830,7 +830,7 @@ kslra32.u:
 smin32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       smin32: 0
     rs1: 
       <<: *all_regs
@@ -849,7 +849,7 @@ smin32:
 umin32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       umin32: 0
     rs1: 
       <<: *all_regs
@@ -868,7 +868,7 @@ umin32:
 smax32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       smax32: 0
     rs1: 
       <<: *all_regs
@@ -887,7 +887,7 @@ smax32:
 umax32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       umax32: 0
     rs1: 
       <<: *all_regs
@@ -906,7 +906,7 @@ umax32:
 kabs32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       kabs32: 0
     rs1: 
       <<: *all_regs
@@ -919,7 +919,7 @@ kabs32:
 khmbb16:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       khmbb16: 0
     rs1: 
       <<: *all_regs
@@ -938,7 +938,7 @@ khmbb16:
 khmbt16:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       khmbt16: 0
     rs1: 
       <<: *all_regs
@@ -957,7 +957,7 @@ khmbt16:
 khmtt16:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       khmtt16: 0
     rs1: 
       <<: *all_regs
@@ -976,7 +976,7 @@ khmtt16:
 kdmbb16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmbb16: 0
     rs1:
       <<: *all_regs
@@ -995,7 +995,7 @@ kdmbb16:
 kdmbt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmbt16: 0
     rs1:
       <<: *all_regs
@@ -1014,7 +1014,7 @@ kdmbt16:
 kdmtt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmtt16: 0
     rs1:
       <<: *all_regs
@@ -1033,7 +1033,7 @@ kdmtt16:
 kdmabb16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmabb16: 0
     rs1:
       <<: *all_regs
@@ -1052,7 +1052,7 @@ kdmabb16:
 kdmabt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmabt16: 0
     rs1:
       <<: *all_regs
@@ -1071,7 +1071,7 @@ kdmabt16:
 kdmatt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kdmatt16: 0
     rs1:
       <<: *all_regs
@@ -1091,7 +1091,7 @@ kdmatt16:
 # smbb32:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       smbb32: 0
 #     rs1:
 #       <<: *all_regs
@@ -1110,7 +1110,7 @@ kdmatt16:
 smbt32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smbt32: 0
     rs1:
       <<: *all_regs
@@ -1129,7 +1129,7 @@ smbt32:
 smtt32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smtt32: 0
     rs1:
       <<: *all_regs
@@ -1148,7 +1148,7 @@ smtt32:
 kmabb32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmabb32: 0
     rs1:
       <<: *all_regs
@@ -1167,7 +1167,7 @@ kmabb32:
 kmabt32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmabt32: 0
     rs1:
       <<: *all_regs
@@ -1186,7 +1186,7 @@ kmabt32:
 kmatt32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmatt32: 0
     rs1:
       <<: *all_regs
@@ -1205,7 +1205,7 @@ kmatt32:
 kmda32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmda32: 0
     rs1:
       <<: *all_regs
@@ -1224,7 +1224,7 @@ kmda32:
 kmxda32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmxda32: 0
     rs1:
       <<: *all_regs
@@ -1244,7 +1244,7 @@ kmxda32:
 # kmada32:
 #     config:
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode:
+#     mnemonics:
 #       kmada32: 0
 #     rs1:
 #       <<: *all_regs
@@ -1263,7 +1263,7 @@ kmxda32:
 kmaxda32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmaxda32: 0
     rs1:
       <<: *all_regs
@@ -1282,7 +1282,7 @@ kmaxda32:
 kmads32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmads32: 0
     rs1:
       <<: *all_regs
@@ -1301,7 +1301,7 @@ kmads32:
 kmadrs32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmadrs32: 0
     rs1:
       <<: *all_regs
@@ -1320,7 +1320,7 @@ kmadrs32:
 kmaxds32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmaxds32: 0
     rs1:
       <<: *all_regs
@@ -1339,7 +1339,7 @@ kmaxds32:
 kmsda32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmsda32: 0
     rs1:
       <<: *all_regs
@@ -1358,7 +1358,7 @@ kmsda32:
 kmsxda32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       kmsxda32: 0
     rs1:
       <<: *all_regs
@@ -1377,7 +1377,7 @@ kmsxda32:
 smds32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smds32: 0
     rs1:
       <<: *all_regs
@@ -1396,7 +1396,7 @@ smds32:
 smdrs32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smdrs32: 0
     rs1:
       <<: *all_regs
@@ -1415,7 +1415,7 @@ smdrs32:
 smxds32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       smxds32: 0
     rs1:
       <<: *all_regs
@@ -1434,7 +1434,7 @@ smxds32:
 sraiw.u:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       sraiw.u: 0
     rs1: 
       <<: *all_regs
@@ -1451,7 +1451,7 @@ sraiw.u:
 # pkbb32:
 #     config: 
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode: 
+#     mnemonics: 
 #       pkbb32: 0
 #     rs1: 
 #       <<: *all_regs
@@ -1470,7 +1470,7 @@ sraiw.u:
 pkbt32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       pkbt32: 0
     rs1: 
       <<: *all_regs
@@ -1489,7 +1489,7 @@ pkbt32:
 pktb32:
     config: 
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode: 
+    mnemonics: 
       pktb32: 0
     rs1: 
       <<: *all_regs
@@ -1509,7 +1509,7 @@ pktb32:
 # pktt32:
 #     config: 
 #       - check ISA:=regex(.*I.*P.*Zicsr.*)
-#     opcode: 
+#     mnemonics: 
 #       pktt32: 0
 #     rs1: 
 #       <<: *all_regs
@@ -1529,7 +1529,7 @@ pktb32:
 clz32:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       clz32: 0
     rs1:
       <<: *all_regs
@@ -1542,7 +1542,7 @@ clz32:
 pkbb16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       pkbb16: 0
     rs1:
       <<: *all_regs
@@ -1561,7 +1561,7 @@ pkbb16:
 pktt16:
     config:
       - check ISA:=regex(.*I.*P.*Zicsr.*)
-    opcode:
+    mnemonics:
       pktt16: 0
     rs1:
       <<: *all_regs
diff --git a/sample_cgfs/rv64zacas.cgf b/sample_cgfs/rv64zacas.cgf
new file mode 100644
index 00000000..6d4db482
--- /dev/null
+++ b/sample_cgfs/rv64zacas.cgf
@@ -0,0 +1,54 @@
+# cover group format file for Zacas extension
+amocas.w:
+    config: 
+      - check ISA:=regex(.*Zacas.*)
+    mnemonics: 
+      amocas.w: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+amocas.d_64:
+    config: 
+      - check ISA:=regex(.*Zacas.*)
+    mnemonics: 
+      amocas.d_64: 0
+    rs1: 
+      <<: *all_regs_mx0
+    rs2: 
+      <<: *pair_regs
+    rd: 
+      <<: *pair_regs
+    op_comb: 
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn, *base_rs2val_sgn, *rfmt_val_comb_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking, *rs2val_walking]
+
+amocas.q:
+    config:
+      - check ISA:=regex(.*Zacas.*)
+    mnemonics:
+      amocas.q: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *pair_regs
+    rd:
+      <<: *pair_regs
+    op_comb:
+      <<: *zacas_op_comb
+    val_comb:
+      <<: [*zacas_dcas_rs1val_sgn, *zacas_dcas_rs2val_sgn, *rfmt_val_comb_sgn]
+      abstract_comb:
+        <<: [*zacas128_rs1val_walking_sgn, *zacas128_rs2val_walking_sgn]
diff --git a/sample_cgfs/srmcfg.cgf b/sample_cgfs/srmcfg.cgf
new file mode 100644
index 00000000..411d0543
--- /dev/null
+++ b/sample_cgfs/srmcfg.cgf
@@ -0,0 +1,77 @@
+srmcfg:
+  config:
+    - check ISA:=regex(.*I.*Zicsr.*Ssqosid.*); def rvtest_mtrap_routine=True
+  isa:
+    - I_Zicsr_Ssqosid
+  csr_comb:
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00000001': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00000003': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00000007': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0000000F': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0000001F': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0000003F': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0000007F': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x000000FF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x000001FF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x000003FF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x000007FF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00000FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00010FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00030FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00070FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x000F0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x001F0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x003F0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x007F0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00FF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x01FF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x03FF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFE': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFC': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF8': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF0': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FE0': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FC0': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F80': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F00': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0E00': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0C00': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0800': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFE0000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFC0000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF80000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF00000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FE00000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FC00000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0F800000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0F000000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0E000000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0C000000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x08000000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x00000000': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFD': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFB': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FF7': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FEF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FDF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FBF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0F7F': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0EFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0DFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0BFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF07FF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFE0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFD0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFB0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FF70FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FEF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FDF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FBF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0F7F0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0EFF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0DFF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0BFF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x07FF0FFF': 0
+    'CSR_SRMCFG & 0x0FFF0FFF == 0x0FFF0FFF': 0
+
diff --git a/sample_cgfs/zcmop.cgf b/sample_cgfs/zcmop.cgf
new file mode 100644
index 00000000..8af2caa0
--- /dev/null
+++ b/sample_cgfs/zcmop.cgf
@@ -0,0 +1,71 @@
+c.mop.1:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.1:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.3:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.3:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.5:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.5:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.7:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.7:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.9:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.9:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.11:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.11:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.13:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.13:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
+
+c.mop.15:
+  config: 
+      - check ISA:=regex(.*C.*Zcmop.*) 
+  mnemonics: 
+    c.mop.15:
+  val_comb:
+    abstract_comb:
+      <<: *cbimm_val_walking
diff --git a/sample_cgfs/zicfilp.cgf b/sample_cgfs/zicfilp.cgf
new file mode 100644
index 00000000..6ead1de8
--- /dev/null
+++ b/sample_cgfs/zicfilp.cgf
@@ -0,0 +1,44 @@
+lpad-m:
+  config:
+    - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+  mnemonics:
+    lpad-m: 0
+  val_comb:
+    'imm_val == 0': 0
+    'imm_val > 0': 0
+    'imm_val == ((2**20)-1)': 0
+    abstract_comb:
+        'sp_dataset(20,["imm_val"],signed=False)': 0
+        'walking_ones("imm_val", 20, False)': 0
+        'walking_zeros("imm_val", 20, False)': 0
+        'alternate("imm_val", 20, False)': 0
+
+lpad-s:
+  config:
+    - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+  mnemonics:
+    lpad-s: 0
+  val_comb:
+    'imm_val == 0': 0
+    'imm_val > 0': 0
+    'imm_val == ((2**20)-1)': 0
+    abstract_comb:
+        'sp_dataset(20,["imm_val"],signed=False)': 0
+        'walking_ones("imm_val", 20, False)': 0
+        'walking_zeros("imm_val", 20, False)': 0
+        'alternate("imm_val", 20, False)': 0
+
+lpad-u:
+  config:
+    - check ISA:=regex(.*I.*Zicsr.*Zicfilp.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+  mnemonics:
+    lpad-u: 0
+  val_comb:
+    'imm_val == 0': 0
+    'imm_val > 0': 0
+    'imm_val == ((2**20)-1)': 0
+    abstract_comb:
+        'sp_dataset(20,["imm_val"],signed=False)': 0
+        'walking_ones("imm_val", 20, False)': 0
+        'walking_zeros("imm_val", 20, False)': 0
+        'alternate("imm_val", 20, False)': 0
diff --git a/sample_cgfs/zicfiss.cgf b/sample_cgfs/zicfiss.cgf
new file mode 100644
index 00000000..b1c1140c
--- /dev/null
+++ b/sample_cgfs/zicfiss.cgf
@@ -0,0 +1,133 @@
+sspush_popchk_u:
+    config: 
+      - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics: 
+      sspushpopchk_u: 0
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+sspush_popchk_s:
+    config:
+      - check ISA:=regex(.*I.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      sspushpopchk_s: 0
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+csspush_popchk_u:
+    config: 
+      - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics: 
+      c.sspushpopchk_u: 0
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+csspush_popchk_s:
+    config:
+      - check ISA:=regex(.*I.*C.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      c.sspushpopchk_s: 0
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+ssamoswap.w_s:
+    config:
+      - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      ssamoswap.w_s: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+ssamoswap.d_s:
+    config:
+      - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      ssamoswap.d_s: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+
+ssamoswap.w_u:
+    config:
+      - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      ssamoswap.w_u: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+ssamoswap.d_u:
+    config:
+      - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      ssamoswap.d_u: 0
+    rs1:
+      <<: *all_regs_mx0
+    rs2:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: [*ramofmt_op_comb]
+    val_comb:
+      <<: [*base_rs2val_sgn]
+      abstract_comb:
+        <<: [*rs2val_walking]
+
+ssrdp_u:
+    config:
+      - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      ssrdp_u: 0
+    rd:
+      <<: *all_regs_mx0
+    op_comb:
+      <<: *rfmt_op_comb
+
+ssrdp_s:
+    config:
+      - check ISA:=regex(.*I.*A.*Zicsr.*Zicfiss.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+    mnemonics:
+      ssrdp_s: 0
+    rd:
+      <<: *all_regs_mx0
+    op_comb:
+      <<: *rfmt_op_comb
+
diff --git a/sample_cgfs/zicond.cgf b/sample_cgfs/zicond.cgf
index f7f2a499..af6c1b82 100644
--- a/sample_cgfs/zicond.cgf
+++ b/sample_cgfs/zicond.cgf
@@ -1,7 +1,7 @@
 czero.eqz:
     config: 
       - check ISA:=regex(.*Zicond.*)
-    opcode: 
+    mnemonics: 
       czero.eqz: 0
     rs1: 
       <<: *all_regs
@@ -20,7 +20,7 @@ czero.eqz:
 czero.nez:
     config: 
       - check ISA:=regex(.*Zicond.*)
-    opcode: 
+    mnemonics: 
       czero.nez: 0
     rs1: 
       <<: *all_regs
diff --git a/sample_cgfs/zimop.cgf b/sample_cgfs/zimop.cgf
new file mode 100644
index 00000000..25fb014c
--- /dev/null
+++ b/sample_cgfs/zimop.cgf
@@ -0,0 +1,697 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+mop.rr.0:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.0: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.1:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.1: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.2:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.2: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.3:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.3: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.4:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.4: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.5:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.5: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.6:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.6: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.rr.7:
+    config: 
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics: 
+      mop.rr.7: 0
+    rs1: 
+      <<: *all_regs
+    rs2: 
+      <<: *all_regs
+    rd: 
+      <<: *all_regs
+    op_comb: 
+      <<: *rfmt_op_comb
+    val_comb:
+      <<: [*base_rs1val_sgn , *base_rs2val_sgn , *rfmt_val_comb_sgn]
+      abstract_comb:
+        'sp_dataset(xlen)': 0
+        <<: [*rs1val_walking, *rs2val_walking]
+
+mop.r.0:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.0: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.1:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.1: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.2:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.2: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.3:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.3: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.4:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.4: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.5:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.5: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.6:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.6: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.7:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.7: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.8:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.8: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.9:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.9: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.10:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.10: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.11:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.11: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.12:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.12: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.13:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.13: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.14:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.14: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.15:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.15: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.16:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.16: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.17:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.17: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.18:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.18: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.19:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.19: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.20:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.20: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.21:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.21: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.22:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.22: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.23:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.23: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.24:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.24: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.25:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.25: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.26:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.26: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.27:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.27: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.28:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.28: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.29:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.29: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.30:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.30: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
+
+mop.r.31:
+    config:
+      - check ISA:=regex(.*Zimop.*)
+    mnemonics:
+      mop.r.31: 0
+    rs1:
+      <<: *all_regs
+    rd:
+      <<: *all_regs
+    op_comb:
+      <<: *ifmt_op_comb
+    val_comb:
+      <<: [ *ifmt_val_comb_sgn, *base_rs1val_sgn, *ifmt_base_immval_sgn]
+    abstract_comb:
+      'sp_dataset(xlen,["rs1_val",("imm_val",12)])': 0
+      <<: [*rs1val_walking, *ifmt_immval_walking]
diff --git a/setup.cfg b/setup.cfg
index 878241cf..0c3d811e 100644
--- a/setup.cfg
+++ b/setup.cfg
@@ -1,12 +1,8 @@
 [bumpversion]
-current_version = 0.11.1
+current_version = 0.12.0
 commit = True
 tag = True
 
-[bumpversion:file:setup.py]
-search = version='{current_version}'
-replace = version='{new_version}'
-
 [bumpversion:file:riscv_ctg/__init__.py]
 search = __version__ = '{current_version}'
 replace = __version__ = '{new_version}'
diff --git a/setup.py b/setup.py
index edf39544..cfba8937 100644
--- a/setup.py
+++ b/setup.py
@@ -4,6 +4,7 @@
 
 from setuptools import setup, find_packages
 import os
+import riscv_ctg
 
 # Base directory of package
 here = os.path.abspath(os.path.dirname(__file__))
@@ -26,7 +27,7 @@ def read_requires():
 
 setup(
     name='riscv_ctg',
-    version='0.11.1',
+    version=riscv_ctg.__version__,
     description="RISC-V CTG",
     long_description=readme + '\n\n',
     classifiers=[


Test patch:
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
index 174651c2..f77b8a39 100644
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@@ -1,26 +1,19 @@
-# This is a basic workflow to help you get started with Actions
-
 name: test
-
-# Controls when the action will run. 
 on:
-  # Triggers the workflow on push or pull request events but only for the master branch
   pull_request:
-    branches: [ master ]
-
-  # Allows you to run this workflow manually from the Actions tab
+    branches:
+        -master
+        -dev
   workflow_dispatch:
 
-# A workflow run is made up of one or more jobs that can run sequentially or in parallel
 jobs:
-  # This workflow contains a single job called "build"
   build:
-    # The type of runner that the job will run on
     runs-on: ubuntu-latest
-
-    # Steps represent a sequence of tasks that will be executed as part of the job
+    strategy:
+        matrix:
+            cgf_files: ["./sample_cgfs/*.cgf"]
+            architecture: ["rv32e", "rv32i", "rv64i", "rv32i_64i"]
     steps:
-      # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
       - uses: actions/checkout@v2
       - name: Set up Python
         uses: actions/setup-python@v2
@@ -33,10 +26,63 @@ jobs:
           pip install -r riscv_ctg/requirements.txt
           pip install --editable .
           
-      - name: Run rv32i
-        run: riscv_ctg -r -d rv32i -bi rv32i -cf sample_cgfs/dataset.cgf -cf sample_cgfs/rv32i.cgf -v debug -p $(nproc)
+
+      - name: Run RISC-V CTG for RV32E
+        run: |
+          set -e
+          for cgf_file in ./sample_cgfs/*.cgf; do
+          if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
+              if [[ "$cgf_file" == *rv32e* ]] && [ "${{matrix.architecture}}" == "rv32e" ] ; then
+                cmd="riscv_ctg -r -d ./tests -bi rv32e -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
+                echo $cmd
+                eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
+              fi
+          fi
+          done
+
+      - name: Run RISC-V CTG for RV32I
+        run: |
+          set -e
+          for cgf_file in ./sample_cgfs/*.cgf; do
+          if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
+              if [[ "$cgf_file" != *rv32e* ]] && [[ "cgf_file" == *rv32* ]] && [ "${{matrix.architecture}}" == "rv32i" ] ; then
+                cmd="riscv_ctg -r -d ./tests -bi rv32i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
+                echo $cmd
+                eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
+              fi
+          fi
+          done
+
+      - name: Run RISC-V CTG for RV64I
+        run: |
+          set -e
+          for cgf_file in ./sample_cgfs/*.cgf; do
+          if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
+              if [[ "$cgf_file" == *rv64* ]] && [ "${{matrix.architecture}}" == "rv64i" ] ; then
+                cmd="riscv_ctg -r -d ./tests -bi rv64i -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
+                echo $cmd
+                eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
+              fi
+          fi
+          done
+
+      - name: Run RISC-V CTG for RV64I and RV32I
+        run: |
+          set -e
+          for cgf_file in ./sample_cgfs/*.cgf; do
+          if [ "$cgf_file" != "./sample_cgfs/dataset.cgf" ]; then
+              if [[ "$cgf_file" != *rv32e* ]] && [[ "$cgf_file" != *rv32* ]] && [[ "$cgf_file" != *rv64* ]] && [ "${{matrix.architecture}}" == "rv32i_64i" ] ; then
+                for arch in rv32i rv64i; do
+                  cmd="riscv_ctg -r -d ./tests -bi $arch -cf sample_cgfs/dataset.cgf -cf \"$cgf_file\" -v warning -p \$(nproc)"
+                  echo $cmd
+                  eval $cmd || { echo "Error executing command: $cmd"; exit 1; }
+                done
+              fi
+          fi
+          done
 
   check-version:
+    if: github.ref == 'refs/heads/master'
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v2
@@ -51,21 +97,8 @@ jobs:
               echo "Versions are equal in Changelog and init.py."
           else
               echo "Versions are not equal in Changelog and init.py."
-              exit 1
+          exit 1
           fi
-
-  check-version-changelog:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v2
-      
-      - uses: actions-ecosystem/action-get-latest-tag@v1
-        id: get-latest-tag
-      
-      - name: version check
-        run: |
-          export CHNGVER=$(grep -P -o '(?<=## \[).*(?=\])' -m1 CHANGELOG.md); 
-          echo "CHANGELOG VERSION: $CHNGVER"
           export TAGVER=${{ steps.get-latest-tag.outputs.tag }}; 
           echo "TAG VERSION: $TAGVER"
           if [ "$CHNGVER" = "$TAGVER" ]; then
@@ -74,3 +107,5 @@ jobs:
           else
               echo "Changelog updated."
           fi
+
+       
\ No newline at end of file