Repository: oddball/ipxact2systemverilog (language: python)

Issue:
trigger circleci
trying to trigger circleci


Discussion / hints:

Fix patch:
diff --git a/.circleci/config.yml b/.circleci/config.yml
index bc4977d..5b01490 100644
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -18,7 +18,6 @@ jobs:
             sudo apt-get update
             sudo apt-get install -y pandoc
             sudo apt-get install ghdl gtkwave
-            sudo pip install rst2pdf
             sudo pip install -e .
 
       - run: python --version
diff --git a/.gitignore b/.gitignore
index 5c1770c..ccd86cc 100644
--- a/.gitignore
+++ b/.gitignore
@@ -12,6 +12,7 @@ schema1.5/
 
 # Compiled python modules.
 *.pyc
+build/
 
 # Setuptools distribution folder.
 /dist/
@@ -19,3 +20,10 @@ schema1.5/
 # Python egg metadata, regenerated from source files by setuptools.
 /*.egg-info
 /*.egg
+
+# ghdl compiler
+work*.cf
+
+# created by the test, but not under git
+example.pdf
+example.docx
diff --git a/.prospector.yaml b/.prospector.yaml
new file mode 100644
index 0000000..2b173b4
--- /dev/null
+++ b/.prospector.yaml
@@ -0,0 +1,8 @@
+pep8:
+  disable:
+      - N801
+      - N802
+      - N803
+      - N806
+  options:
+      max-line-length: 159
diff --git a/Makefile b/Makefile
index 659f2ba..5398d17 100644
--- a/Makefile
+++ b/Makefile
@@ -16,15 +16,29 @@ endif
 
 all: gen
 
-gen: 
+gen:
+        # no config
 	bin/ipxact2systemverilog --srcFile example/input/test.xml --destDir example/output
 	bin/ipxact2rst --srcFile example/input/test.xml --destDir example/output
+	bin/ipxact2md --srcFile example/input/test.xml --destDir example/output
 	bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output
+	bin/ipxact2md --srcFile example/input/test.xml --destDir example/output
 	rst2html5.py example/output/example.rst example/output/example.html
-	rst2pdf example/output/example.rst -o example/output/example.pdf
 	pandoc -s example/output/example.rst -o example/output/example.rtf
 	pandoc -s example/output/example.rst -o example/output/example.docx
 
+        # default config
+	bin/ipxact2systemverilog --srcFile example/input/test.xml --destDir example/output_default  --config example/input/default.ini
+	bin/ipxact2rst --srcFile example/input/test.xml --destDir example/output_default  --config example/input/default.ini
+	bin/ipxact2md --srcFile example/input/test.xml --destDir example/output_default  --config example/input/default.ini
+	bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output_default  --config example/input/default.ini
+
+       # no default config
+	bin/ipxact2systemverilog --srcFile example/input/test.xml --destDir example/output_no_default  --config example/input/no_default.ini
+	bin/ipxact2rst --srcFile example/input/test.xml --destDir example/output_no_default  --config example/input/no_default.ini
+	bin/ipxact2md --srcFile example/input/test.xml --destDir example/output_no_default  --config example/input/no_default.ini
+	bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output_no_default  --config example/input/no_default.ini
+
 compile: 
 	test -d work || vlib work
 	vlog  +incdir+example/output  example/output/example_sv_pkg.sv example/tb/sv_dut.sv example/tb/tb.sv
diff --git a/README.rst b/README.rst
index 14bf272..ef394c0 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,5 @@
-ipxact2systemverilog ipxact2rst ipxact2vhdl
--------------------------------------------
+xact2systemverilog ipxact2rst ipxact2md ipxact2vhdl
+---------------------------------------------------
 
 .. image:: https://circleci.com/gh/oddball/ipxact2systemverilog.svg?style=shield&circle-token=071d263d097ebb33943a749ecb66549c9f0512ed
    :target: https://circleci.com/gh/oddball/ipxact2systemverilog
@@ -19,6 +19,7 @@ Usage
    
    ipxact2systemverilog --srcFile FILE --destDir DIR
    ipxact2rst --srcFile FILE --destDir DIR
+   ipxact2md --srcFile FILE --destDir DIR
    ipxact2vhdl --srcFile FILE --destDir DIR
 
 
@@ -41,7 +42,6 @@ If Modelsim is installed:
 
 Note
 ====
-You can use http://rst2pdf.ralsina.me to make a pdf from the generated reStructuredText.
 You can use http://pandoc.org/demos.html to convert to almost any fileformat.
 
 
@@ -59,7 +59,7 @@ Dependencies
 
 ::
    
-    pip install docutils lxml tabulate future
+    pip install docutils lxml tabulate future mdutils
 
 
 Dependencies used by makefile
@@ -68,7 +68,6 @@ These are not needed for ipxact2systemverilog, but used for generating some of t
 
 ::
    
-   pip2 install rst2pdf
    brew install pandoc
 
 
diff --git a/bin/ipxact2md b/bin/ipxact2md
new file mode 100755
index 0000000..c68b00f
--- /dev/null
+++ b/bin/ipxact2md
@@ -0,0 +1,36 @@
+#!/usr/bin/env python
+from __future__ import print_function
+import configparser
+import sys
+import os
+import argparse
+from pprint import pprint
+
+from ipxact2systemverilog.ipxact2hdlCommon import ipxactParser
+from ipxact2systemverilog.ipxact2hdlCommon import ipxact2otherGenerator
+from ipxact2systemverilog.ipxact2hdlCommon import mdAddressBlock
+from ipxact2systemverilog.ipxact2hdlCommon import DEFAULT_INI
+from ipxact2systemverilog.validate import validate
+
+if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description='ipxact2md')
+    parser.add_argument('-s', '--srcFile', help='ipxact xml input file', required=True)
+    parser.add_argument('-d', '--destDir', help="write generated file to dir", required=True)
+    parser.add_argument('-c', '--config', help="configuration ini file")
+
+    args, unknown_args = parser.parse_known_args()
+
+    if not validate(args.srcFile):
+        print("%s doesn't validate" % args.srcFile)
+        sys.exit(1)
+
+    config = configparser.ConfigParser()
+    if args.config:
+        config.read(args.config)
+    else:
+        config.read_dict(DEFAULT_INI)
+        
+    e = ipxactParser(args.srcFile, config)
+    document = e.returnDocument()
+    generator = ipxact2otherGenerator(args.destDir)
+    generator.generate(mdAddressBlock, document)
diff --git a/bin/ipxact2rst b/bin/ipxact2rst
index 405c5fa..42fe92b 100755
--- a/bin/ipxact2rst
+++ b/bin/ipxact2rst
@@ -1,5 +1,6 @@
 #!/usr/bin/env python
 from __future__ import print_function
+import configparser
 import sys
 import os
 import argparse
@@ -8,20 +9,28 @@ from pprint import pprint
 from ipxact2systemverilog.ipxact2hdlCommon import ipxactParser
 from ipxact2systemverilog.ipxact2hdlCommon import ipxact2otherGenerator
 from ipxact2systemverilog.ipxact2hdlCommon import rstAddressBlock
+from ipxact2systemverilog.ipxact2hdlCommon import DEFAULT_INI
 from ipxact2systemverilog.validate import validate
 
 if __name__ == '__main__':
     parser = argparse.ArgumentParser(description='ipxact2rst')
     parser.add_argument('-s', '--srcFile', help='ipxact xml input file', required=True)
     parser.add_argument('-d', '--destDir', help="write generated file to dir", required=True)
+    parser.add_argument('-c', '--config', help="configuration ini file")
 
     args, unknown_args = parser.parse_known_args()
 
     if not validate(args.srcFile):
         print("%s doesn't validate" % args.srcFile)
         sys.exit(1)
+
+    config = configparser.ConfigParser()
+    if args.config:
+        config.read(args.config)
+    else:
+        config.read_dict(DEFAULT_INI)
         
-    e = ipxactParser(args.srcFile)
+    e = ipxactParser(args.srcFile, config)
     document = e.returnDocument()
     generator = ipxact2otherGenerator(args.destDir)
     generator.generate(rstAddressBlock, document)
diff --git a/bin/ipxact2systemverilog b/bin/ipxact2systemverilog
index ec6837c..3b543c4 100755
--- a/bin/ipxact2systemverilog
+++ b/bin/ipxact2systemverilog
@@ -1,14 +1,16 @@
-#!/usr/bin/env python
+#!/usr/bin/env python3
 
-from __future__ import print_function
+import configparser
 import sys
 import os
 import argparse
 
+print(sys.path)
 
 from ipxact2systemverilog.ipxact2hdlCommon import ipxactParser
 from ipxact2systemverilog.ipxact2hdlCommon import ipxact2otherGenerator
 from ipxact2systemverilog.ipxact2hdlCommon import systemVerilogAddressBlock
+from ipxact2systemverilog.ipxact2hdlCommon import DEFAULT_INI
 from ipxact2systemverilog.validate import validate
 
 
@@ -16,6 +18,7 @@ if __name__ == '__main__':
     parser = argparse.ArgumentParser(description='ipxact2systemverilog')
     parser.add_argument('-s', '--srcFile', help='ipxact xml input file', required=True)
     parser.add_argument('-d', '--destDir', help="write generated file to dir", required=True)
+    parser.add_argument('-c', '--config', help="configuration ini file")
 
     args, unknown_args = parser.parse_known_args()
 
@@ -23,7 +26,13 @@ if __name__ == '__main__':
         print("%s doesn't validate" % args.srcFile)
         sys.exit(1)
 
-    e = ipxactParser(args.srcFile)
+    config = configparser.ConfigParser()
+    if args.config:
+        config.read(args.config)
+    else: 
+        config.read_dict(DEFAULT_INI)
+        
+    e = ipxactParser(args.srcFile, config)
     document = e.returnDocument()
     generator = ipxact2otherGenerator(args.destDir)
     generator.generate(systemVerilogAddressBlock, document)
diff --git a/bin/ipxact2vhdl b/bin/ipxact2vhdl
index c5ee2f9..369c898 100755
--- a/bin/ipxact2vhdl
+++ b/bin/ipxact2vhdl
@@ -1,5 +1,6 @@
 #!/usr/bin/env python
 from __future__ import print_function
+import configparser
 import sys
 import os
 import argparse
@@ -7,6 +8,7 @@ import argparse
 from ipxact2systemverilog.ipxact2hdlCommon import ipxactParser
 from ipxact2systemverilog.ipxact2hdlCommon import ipxact2otherGenerator
 from ipxact2systemverilog.ipxact2hdlCommon import vhdlAddressBlock
+from ipxact2systemverilog.ipxact2hdlCommon import DEFAULT_INI
 from ipxact2systemverilog.validate import validate
 
 
@@ -14,14 +16,21 @@ if __name__ == '__main__':
     parser = argparse.ArgumentParser(description='ipxact2vhdl')
     parser.add_argument('-s', '--srcFile', help='ipxact xml input file', required=True)
     parser.add_argument('-d', '--destDir', help="write generated file to dir", required=True)
+    parser.add_argument('-c', '--config', help="configuration ini file")
 
     args, unknown_args = parser.parse_known_args()
 
     if not validate(args.srcFile):
         print("%s doesn't validate" % args.srcFile)
         sys.exit(1)
+
+    config = configparser.ConfigParser()
+    if args.config:
+        config.read(args.config)
+    else:
+        config.read_dict(DEFAULT_INI)
         
-    e = ipxactParser(args.srcFile)
+    e = ipxactParser(args.srcFile, config)
     document = e.returnDocument()
     generator = ipxact2otherGenerator(args.destDir)
     generator.generate(vhdlAddressBlock, document)
diff --git a/example/input/default.ini b/example/input/default.ini
new file mode 100644
index 0000000..2297a73
--- /dev/null
+++ b/example/input/default.ini
@@ -0,0 +1,29 @@
+[global]
+# Do add unused bits in a register between two used fields.
+# E.g.
+#   Input:
+#      <spirit:field>
+#        <spirit:name>nibble0</spirit:name>
+#        <spirit:description>write something useful for nibble0</spirit:description>
+#        <spirit:bitOffset>0</spirit:bitOffset>
+#        <spirit:bitWidth>4</spirit:bitWidth>
+#      </spirit:field>
+#      <spirit:field>
+#        <spirit:name>nibble1</spirit:name>
+#        <spirit:description>write something useful for nibble1</spirit:description>
+#        <spirit:bitOffset>8</spirit:bitOffset>
+#        <spirit:bitWidth>4</spirit:bitWidth>
+#      </spirit:field>
+#   Output (VHDL):
+#      type reg7_record_type is record
+#        nibble1 : std_ulogic_vector(3 downto 0); -- [11:8]
+#        unused0 : std_ulogic_vector(3 downto 0); -- [7:4]
+#        nibble0 : std_ulogic_vector(3 downto 0); -- [3:0]
+#      end record;
+UnusedHoles = yes
+
+
+# If no: no enums will be generated for register fields of 1 bit.
+# If yes: enums will be generated even if the register field is 1 bit width.
+OneBitEnum = no
+
diff --git a/example/input/no_default.ini b/example/input/no_default.ini
new file mode 100644
index 0000000..75e09d5
--- /dev/null
+++ b/example/input/no_default.ini
@@ -0,0 +1,5 @@
+[global]
+UnusedHoles = no
+OneBitEnum = yes
+
+
diff --git a/example/output/example.docx b/example/output/example.docx
index 263eff4..cea9ae4 100644
Binary files a/example/output/example.docx and b/example/output/example.docx differ
diff --git a/example/output/example.html b/example/output/example.html
index 4dc0ad3..209c310 100644
--- a/example/output/example.html
+++ b/example/output/example.html
@@ -2,14 +2,14 @@
 <html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en" lang="en">
 <head>
 <meta charset="utf-8"/>
-<meta name="generator" content="Docutils 0.14: http://docutils.sourceforge.net/" />
+<meta name="generator" content="Docutils 0.16: http://docutils.sourceforge.net/" />
 <title>Register description</title>
 <style type="text/css">
 
 /* Minimal style sheet for the HTML output of Docutils.                    */
 /*                                                                         */
 /* :Author: Günter Milde, based on html4css1.css by David Goodger          */
-/* :Id: $Id: minimal.css 8036 2017-02-14 13:05:46Z milde $               */
+/* :Id: $Id: minimal.css 8397 2019-09-20 11:09:34Z milde $               */
 /* :Copyright: © 2015 Günter Milde.                                        */
 /* :License: Released under the terms of the `2-Clause BSD license`_,      */
 /*    in short:                                                            */
@@ -40,10 +40,10 @@
 h1.title, p.subtitle {
   text-align: center;
 }
-p.admonition-title,
 p.topic-title,
 p.sidebar-title,
 p.rubric,
+p.admonition-title,
 p.system-message-title {
   font-weight: bold;
 }
@@ -101,10 +101,11 @@
 }
 
 /* Table of Contents */
-div.topic.contents { margin: 0; }
-ul.auto-toc {
+div.topic.contents { margin: 0.5em 0; }
+div.topic.contents ul {
   list-style-type: none;
-  padding-left: 1.5em; }
+  padding-left: 1.5em;
+}
 
 /* Enumerated Lists */
 ol.arabic     { list-style: decimal }
@@ -159,7 +160,7 @@
 dd.authors > p { margin: 0; }
 
 /* Option Lists */
-dl.option-list { margin-left: 40px; }
+dl.option-list { margin-left: 1.5em; }
 dl.option-list > dt { font-weight: normal; }
 span.option { white-space: nowrap; }
 
@@ -189,45 +190,56 @@
 
 /* Figures, Images, and Tables */
 .figure.align-left,
+figure.align-left,
 img.align-left,
 object.align-left,
 table.align-left {
   margin-right: auto;
 }
 .figure.align-center,
+figure.align-center,
 img.align-center,
-object.align-center {
-  margin-left: auto;
-  margin-right: auto;
-  display: block;
-}
+object.align-center,
 table.align-center {
   margin-left: auto;
   margin-right: auto;
 }
 .figure.align-right,
+figure.align-right,
 img.align-right,
 object.align-right,
 table.align-right {
   margin-left: auto;
 }
+.figure.align-center, .figure.align-right,
+figure.align-center, figure.align-right,
+img.align-center, img.align-right,
+object.align-center, object.align-right {
+  display: block;
+}
 /* reset inner alignment in figures and tables */
-/* div.align-left, div.align-center, div.align-right, */
-table.align-left, table.align-center, table.align-right
-{ text-align: inherit }
+.figure.align-left, .figure.align-right,
+figure.align-left, figure.align-right,
+table.align-left, table.align-center, table.align-right {
+  text-align: inherit;
+}
 
 /* Admonitions and System Messages */
 div.admonition,
 div.system-message,
-div.sidebar{
-  margin: 40px;
+div.sidebar,
+aside.sidebar {
+  margin: 1em 1.5em;
   border: medium outset;
+  padding-top: 0.5em;
+  padding-bottom: 0.5em;
   padding-right: 1em;
   padding-left: 1em;
 }
 
 /* Sidebar */
-div.sidebar {
+div.sidebar,
+aside.sidebar {
   width: 30%;
   max-width: 26em;
   float: right;
@@ -235,13 +247,14 @@
 }
 
 /* Text Blocks */
+blockquote,
 div.topic,
 pre.literal-block,
 pre.doctest-block,
 pre.math,
 pre.code {
-  margin-right: 40px;
-  margin-left: 40px;
+  margin-left: 1.5em;
+  margin-right: 1.5em;
 }
 pre.code .ln { color: gray; } /* line numbers */
 
@@ -267,6 +280,17 @@
   padding-right: 0.5em /* separate table cells */
 }
 
+/* Document Header and Footer */
+/* div.header,				      */
+/* header { border-bottom: 1px solid black; } */
+/* div.footer,				      */
+/* footer { border-top: 1px solid black; }    */
+
+/* new HTML5 block elements: set display for older browsers */
+header, section, footer, aside, nav, main, article, figure {
+  display: block;
+}
+
 </style>
 <style type="text/css">
 
@@ -274,7 +298,7 @@
 /* Rules for easy reading and pre-defined style variants.		   */
 /*                                                                         */
 /* :Author: Günter Milde, based on html4css1.css by David Goodger          */
-/* :Id: $Id: plain.css 8120 2017-06-22 21:02:40Z milde $               */
+/* :Id: $Id: plain.css 8397 2019-09-20 11:09:34Z milde $               */
 /* :Copyright: © 2015 Günter Milde.                                        */
 /* :License: Released under the terms of the `2-Clause BSD license`_,      */
 /*    in short:                                                            */
@@ -294,17 +318,20 @@
 
 /* "page layout" */
 body {
-  padding: 0 5%;
-  margin: 8px 0;
+  margin: 0;
+  background-color: #dbdbdb;
 }
-div.document {
+div.document,
+main {
   line-height:1.3;
   counter-reset: table;
   /* counter-reset: figure; */
   /* avoid long lines --> better reading */
   /* OTOH: lines should not be too short because of missing hyphenation, */
   max-width: 50em;
+  padding: 1px 2%; /* 1px on top avoids grey bar above title (mozilla) */
   margin: auto;
+  background-color: white;
 }
 
 /* Sections */
@@ -318,32 +345,33 @@
   clear: both;
 }
 
-/* Paragraphs               */
-/* ==========               */
+/* Paragraphs */
+/* ========== */
 
 /* vertical space (parskip) */
 p, ol, ul, dl,
 div.line-block,
-table{
+div.topic,
+table {
   margin-top: 0.5em;
   margin-bottom: 0.5em;
 }
+p:first-child { margin-top: 0; }
+/* (:last-child is new in CSS 3) */
+p:last-child  { margin-bottom: 0; }
+
 h1, h2, h3, h4, h5, h6,
 dl > dd {
   margin-bottom: 0.5em;
 }
 
-/* Lists                    */
-/* ==========               */
-
-/* Definition Lists         */
+/* Lists */
+/* ===== */
 
-dl > dd > p:first-child { margin-top: 0; }
-/* :last-child is not part of CSS 2.1 (introduced in CSS 3) */
-dl > dd > p:last-child  { margin-bottom: 0; }
+/* Definition Lists */
 
 /* lists nested in definition lists */
-/* :only-child is not part of CSS 2.1 (introduced in CSS 3) */
+/* (:only-child is new in CSS 3) */
 dd > ul:only-child, dd > ol:only-child { padding-left: 1em; }
 
 /* Description Lists */
@@ -392,23 +420,20 @@
   font-weight: normal;
 }
 
-/* Text Blocks           */
-/* ============          */
+/* Text Blocks */
+/* =========== */
 
-/* Literal Blocks           */
-pre.literal-block, pre.doctest-block,
-pre.math, pre.code {
-  margin-left: 1.5em;
-  margin-right: 1.5em
+/* Literal Blocks */
+
+pre.literal-block,
+pre.doctest-block,
+pre.math,
+pre.code {
+  font-family: monospace;
 }
 
-/* Block Quotes             */
+/* Block Quotes */
 
-blockquote,
-div.topic {
-  margin-left: 1.5em;
-  margin-right: 1.5em
-}
 blockquote > table,
 div.topic > table {
   margin-top: 0;
@@ -420,8 +445,8 @@
   margin-left: 20%;
 }
 
-/* Tables                   */
-/* ======                   */
+/* Tables */
+/* ====== */
 
 /* th { vertical-align: bottom; } */
 
@@ -448,11 +473,11 @@
   font-weight: bold;
 }
 
-/* Explicit Markup Blocks   */
-/* ======================   */
+/* Explicit Markup Blocks */
+/* ====================== */
 
-/* Footnotes and Citations  */
-/* -----------------------  */
+/* Footnotes and Citations */
+/* ----------------------- */
 
 /* line on the left */
 dl.footnote {
@@ -461,48 +486,52 @@
   border-left-width: thin;
 }
 
-/* Directives               */
-/* ----------               */
+/* Directives */
+/* ---------- */
 
-/* Body Elements            */
-/* ~~~~~~~~~~~~~            */
+/* Body Elements */
+/* ~~~~~~~~~~~~~ */
 
 /* Images and Figures */
 
 /* let content flow to the side of aligned images and figures */
 .figure.align-left,
+figure.align-left,
 img.align-left,
 object.align-left {
   display: block;
   clear: left;
   float: left;
-  margin-right: 1em
+  margin-right: 1em;
 }
 .figure.align-right,
+figure.align-right,
 img.align-right,
 object.align-right {
   display: block;
   clear: right;
   float: right;
-  margin-left: 1em
+  margin-left: 1em;
 }
 /* Stop floating sidebars, images and figures at section level 1,2,3 */
 h1, h2, h3 { clear: both; }
 
 /* Sidebar */
 
-/* Move into the margin. In a layout with fixed margins, */
-/* it can be moved into the margin completely.		 */
-div.sidebar {
+/* Move right. In a layout with fixed margins, */
+/* it can be moved into the margin.   	       */
+div.sidebar,
+aside.sidebar {
   width: 30%;
   max-width: 26em;
   margin-left: 1em;
-  margin-right: -5.5%;
-  background-color: #ffffee ;
+  margin-right: -2%;
+  background-color: #ffffee;
 }
 
-/* Code                     */
+/* Code */
 
+pre.code { padding: 0.7ex }
 pre.code, code { background-color: #eeeeee }
 pre.code .ln { color: gray; } /* line numbers */
 /* basic highlighting: for a complete scheme, see */
@@ -514,50 +543,55 @@
 pre.code .deleted, code .deleted { background-color: #DEB0A1}
 pre.code .inserted, code .inserted { background-color: #A3D289}
 
-/* Math                     */
+/* Math */
 /* styled separately (see math.css for math-output=HTML) */
 
-/* Epigraph                 */
-/* Highlights               */
-/* Pull-Quote               */
-/* Compound Paragraph       */
-/* Container                */
+/* Epigraph           */
+/* Highlights         */
+/* Pull-Quote         */
+/* Compound Paragraph */
+/* Container          */
 
 /* can be styled in a custom stylesheet */
 
 /* Document Header and Footer */
 
+footer, header,
 div.footer, div.header {
-  clear: both;
   font-size: smaller;
+  clear: both;
+  padding: 0.5em 2%;
+  background-color: #ebebee;
+  border: none;
 }
 
-/* Inline Markup            */
-/* =============            */
+/* Inline Markup */
+/* ============= */
+
+/* Emphasis           */
+/*   em               */
+/* Strong Emphasis    */
+/*   strong	      */
+/* Interpreted Text   */
+/*   span.interpreted */
+/* Title Reference    */
+/*   cite	      */
 
-/* Emphasis                 */
-/*   em                     */
-/* Strong Emphasis          */
-/*   strong		    */
-/* Interpreted Text         */
-/*   span.interpreted  	    */
-/* Title Reference 	    */
-/*   cite		    */
-/* Inline Literals          */
+/* Inline Literals                                          */
 /* possible values: normal, nowrap, pre, pre-wrap, pre-line */
-/*   span.docutils.literal { white-space: pre-wrap; } */
+/*   span.docutils.literal { white-space: pre-wrap; }       */
 
-/* Hyperlink References     */
+/* Hyperlink References */
 a { text-decoration: none; }
 
-/* External Targets         */
-/*   span.target.external   */
-/* Internal Targets  	    */
-/*   span.target.internal   */
-/* Footnote References      */
-/*   a.footnote-reference   */
-/* Citation References      */
-/*   a.citation-reference   */
+/* External Targets       */
+/*   span.target.external */
+/* Internal Targets  	  */
+/*   span.target.internal */
+/* Footnote References    */
+/*   a.footnote-reference */
+/* Citation References    */
+/*   a.citation-reference */
 
 </style>
 </head>
diff --git a/example/output/example.md b/example/output/example.md
new file mode 100644
index 0000000..0543638
--- /dev/null
+++ b/example/output/example.md
@@ -0,0 +1,111 @@
+
+# Register description
+
+## Registers
+
+|Address|Register Name|Description|
+| :--- | :--- | :--- |
+|0x00|[reg0](#reg0)|write something useful for reg0|
+|0x01|[reg1](#reg1)|write something useful for reg1|
+|0x02|[reg2](#reg2)|write something useful for reg2|
+|0x03|[reg3](#reg3)|write something useful for reg3|
+|0x04|[reg4](#reg4)|reg4 is a very useful register. It can take down the moon when configured correctly.|
+|0x05|[reg5](#reg5)|reg5 is as useful as reg4 but without a reset value defined.|
+|0x06|[reg6](#reg6)|reg6 is a read only register.|
+|0x07|[reg7](#reg7)|write something useful for reg7|
+
+### reg0
+  
+**Name** reg0  
+**Address** 0x0  
+**Reset Value** 0x00000000  
+**Access** read-write  
+**Description** write something useful for reg0
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:24]|byte3||write something useful for field3|
+|[23:16]|byte2||write something useful for field2|
+|[15:8]|byte1||write something useful for field1|
+|[7:0]|byte0||write something useful for field0|
+
+### reg1
+  
+**Name** reg1  
+**Address** 0x1  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg1
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|field0||write something useful for field0|
+
+### reg2
+  
+**Name** reg2  
+**Address** 0x2  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg2
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[5:4]|monkey2|chimp=0, gorilla=1, phb=2|which monkey|
+|[3:2]|monkey|chimp=0, gorilla=1, phb=2|which monkey|
+|[1:1]|power2||write something useful for field power2|
+|[0:0]|power||write something useful for field power|
+
+### reg3
+  
+**Name** reg3  
+**Address** 0x3  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg3
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|field0||write something useful for field0|
+
+### reg4
+  
+**Name** reg4  
+**Address** 0x4  
+**Reset Value** 0x0000000c  
+**Access** read-write  
+**Description** reg4 is a very useful register. It can take down the moon when configured correctly.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg4|||
+
+### reg5
+  
+**Name** reg5  
+**Address** 0x5  
+**Access** read-write  
+**Description** reg5 is as useful as reg4 but without a reset value defined.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg5|||
+
+### reg6
+  
+**Name** reg6  
+**Address** 0x6  
+**Access** read-only  
+**Description** reg6 is a read only register.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg6|||
+
+### reg7
+  
+**Name** reg7  
+**Address** 0x7  
+**Reset Value** 0x00000000  
+**Access** read-write  
+**Description** write something useful for reg7
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[19:16]|nibble2||write something useful for nibble2|
+|[15:12]|unused1||unused|
+|[11:8]|nibble1||write something useful for nibble1|
+|[7:4]|unused0||unused|
+|[3:0]|nibble0||write something useful for nibble0|
diff --git a/example/output/example.pdf b/example/output/example.pdf
index cfe644d..32ad620 100644
Binary files a/example/output/example.pdf and b/example/output/example.pdf differ
diff --git a/example/output/example.rtf b/example/output/example.rtf
index d21bcb2..29d5dda 100644
--- a/example/output/example.rtf
+++ b/example/output/example.rtf
@@ -25,7 +25,7 @@
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x00\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg0"}}{\fldrslt{\ul
 reg0
 }}}
 \par}
@@ -41,7 +41,7 @@ reg0
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x01\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg1"}}{\fldrslt{\ul
 reg1
 }}}
 \par}
@@ -57,7 +57,7 @@ reg1
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x02\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg2"}}{\fldrslt{\ul
 reg2
 }}}
 \par}
@@ -73,7 +73,7 @@ reg2
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x03\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg3"}}{\fldrslt{\ul
 reg3
 }}}
 \par}
@@ -89,7 +89,7 @@ reg3
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x04\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg4"}}{\fldrslt{\ul
 reg4
 }}}
 \par}
@@ -105,7 +105,7 @@ reg4
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x05\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg5"}}{\fldrslt{\ul
 reg5
 }}}
 \par}
@@ -121,7 +121,7 @@ reg5
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x06\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg6"}}{\fldrslt{\ul
 reg6
 }}}
 \par}
@@ -137,7 +137,7 @@ reg6
 {
 {{\pard\intbl \ql \f0 \sa0 \li0 \fi0 0x07\par}
 \cell}
-{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK ""}}{\fldrslt{\ul
+{{\pard\intbl \ql \f0 \sa0 \li0 \fi0 {\field{\*\fldinst{HYPERLINK "#reg7"}}{\fldrslt{\ul
 reg7
 }}}
 \par}
diff --git a/example/output/example_sv_pkg.sv b/example/output/example_sv_pkg.sv
index b795a6e..9ba71bb 100644
--- a/example/output/example_sv_pkg.sv
+++ b/example/output/example_sv_pkg.sv
@@ -136,7 +136,7 @@ function bit [31:0] read_example(example_struct_type registers,int address);
 endfunction
 
 function example_struct_type write_example(bit [31:0] data, int address, 
-                                        example_struct_type registers);
+                                           example_struct_type registers);
    example_struct_type r;
    r = registers;
    case(address)
diff --git a/example/output/example_vhd_pkg.vhd b/example/output/example_vhd_pkg.vhd
index 46d88b6..6b8e315 100644
--- a/example/output/example_vhd_pkg.vhd
+++ b/example/output/example_vhd_pkg.vhd
@@ -23,21 +23,21 @@ package example_vhd_pkg is
 
   function sulv_to_monkey_enum(v: std_ulogic_vector (2-1 downto 0)) return monkey_enum;
 
-  constant reg0_addr : natural := 0;
-  constant reg1_addr : natural := 1;
-  constant reg2_addr : natural := 2;
-  constant reg3_addr : natural := 3;
-  constant reg4_addr : natural := 4;
-  constant reg5_addr : natural := 5;
-  constant reg6_addr : natural := 6;
-  constant reg7_addr : natural := 7;
-
-  constant reg0_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector( to_unsigned(0, data_width ));
-  constant reg1_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector( to_unsigned(1, data_width ));
-  constant reg2_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector( to_unsigned(1, data_width ));
-  constant reg3_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector( to_unsigned(1, data_width ));
-  constant reg4_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector( to_unsigned(12, data_width ));
-  constant reg7_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector( to_unsigned(0, data_width ));
+  constant reg0_addr : natural := 0 ;  -- 0x0
+  constant reg1_addr : natural := 1 ;  -- 0x1
+  constant reg2_addr : natural := 2 ;  -- 0x2
+  constant reg3_addr : natural := 3 ;  -- 0x3
+  constant reg4_addr : natural := 4 ;  -- 0x4
+  constant reg5_addr : natural := 5 ;  -- 0x5
+  constant reg6_addr : natural := 6 ;  -- 0x6
+  constant reg7_addr : natural := 7 ;  -- 0x7
+
+  constant reg0_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width));  -- 0x00000000
+  constant reg1_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg2_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg3_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg4_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(12, data_width));  -- 0x0000000c
+  constant reg7_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width));  -- 0x00000000
 
 
   type reg0_record_type is record
@@ -83,26 +83,26 @@ package example_vhd_pkg is
   end record;
 
   type example_in_record_type is record
-    reg6 : reg6_record_type; -- addr 6
+    reg6 : reg6_record_type; -- addr 0x6
   end record;
 
   type example_out_record_type is record
-    reg0 : reg0_record_type; -- addr 0
-    reg1 : reg1_record_type; -- addr 1
-    reg2 : reg2_record_type; -- addr 2
-    reg3 : reg3_record_type; -- addr 3
-    reg4 : reg4_record_type; -- addr 4
-    reg5 : reg5_record_type; -- addr 5
-    reg7 : reg7_record_type; -- addr 7
+    reg0 : reg0_record_type; -- addr 0x0
+    reg1 : reg1_record_type; -- addr 0x1
+    reg2 : reg2_record_type; -- addr 0x2
+    reg3 : reg3_record_type; -- addr 0x3
+    reg4 : reg4_record_type; -- addr 0x4
+    reg5 : reg5_record_type; -- addr 0x5
+    reg7 : reg7_record_type; -- addr 0x7
   end record;
 
   function read_example(registers_i : example_in_record_type;
                         registers_o : example_out_record_type;
-                        address   : std_ulogic_vector (addr_width-1 downto 0)
+                        address : std_ulogic_vector (addr_width-1 downto 0)
                         ) return std_ulogic_vector;
 
-  function write_example(value     : std_ulogic_vector (data_width-1 downto 0);
-                         address   : std_ulogic_vector (addr_width-1 downto 0);
+  function write_example(value : std_ulogic_vector (data_width-1 downto 0);
+                         address : std_ulogic_vector (addr_width-1 downto 0);
                          registers_o : example_out_record_type
                          ) return example_out_record_type;
 
@@ -277,9 +277,9 @@ package body example_vhd_pkg is
   end function;
 
   function read_example(registers_i : example_in_record_type;
-                                 registers_o : example_out_record_type;
-                                 address   : std_ulogic_vector (addr_width-1 downto 0)
-                                 ) return std_ulogic_vector is
+                        registers_o : example_out_record_type;
+                        address : std_ulogic_vector (addr_width-1 downto 0)
+                        ) return std_ulogic_vector is
     variable r : std_ulogic_vector (data_width-1 downto 0);
   begin
     case to_integer(unsigned(address)) is
@@ -291,15 +291,15 @@ package body example_vhd_pkg is
       when reg5_addr => r:= reg5_record_type_to_sulv(registers_o.reg5);
       when reg6_addr => r:= reg6_record_type_to_sulv(registers_i.reg6);
       when reg7_addr => r:= reg7_record_type_to_sulv(registers_o.reg7);
-      when others    => r := (others => '0');
+      when others => r := (others => '0');
     end case;
     return r;
   end function;
 
-  function write_example(value     : std_ulogic_vector (data_width-1 downto 0);
-                               address   : std_ulogic_vector (addr_width-1 downto 0);
-                               registers_o : example_out_record_type
-                               ) return example_out_record_type is
+  function write_example(value : std_ulogic_vector (data_width-1 downto 0);
+                         address : std_ulogic_vector (addr_width-1 downto 0);
+                         registers_o : example_out_record_type
+                         ) return example_out_record_type is
     variable r : example_out_record_type;
   begin
     r := registers_o;
@@ -311,7 +311,7 @@ package body example_vhd_pkg is
          when reg4_addr => r.reg4 := sulv_to_reg4_record_type(value);
          when reg5_addr => r.reg5 := sulv_to_reg5_record_type(value);
          when reg7_addr => r.reg7 := sulv_to_reg7_record_type(value);
-      when others    => null;
+      when others => null;
     end case;
     return r;
   end function;
diff --git a/example/output_default/example.md b/example/output_default/example.md
new file mode 100644
index 0000000..0543638
--- /dev/null
+++ b/example/output_default/example.md
@@ -0,0 +1,111 @@
+
+# Register description
+
+## Registers
+
+|Address|Register Name|Description|
+| :--- | :--- | :--- |
+|0x00|[reg0](#reg0)|write something useful for reg0|
+|0x01|[reg1](#reg1)|write something useful for reg1|
+|0x02|[reg2](#reg2)|write something useful for reg2|
+|0x03|[reg3](#reg3)|write something useful for reg3|
+|0x04|[reg4](#reg4)|reg4 is a very useful register. It can take down the moon when configured correctly.|
+|0x05|[reg5](#reg5)|reg5 is as useful as reg4 but without a reset value defined.|
+|0x06|[reg6](#reg6)|reg6 is a read only register.|
+|0x07|[reg7](#reg7)|write something useful for reg7|
+
+### reg0
+  
+**Name** reg0  
+**Address** 0x0  
+**Reset Value** 0x00000000  
+**Access** read-write  
+**Description** write something useful for reg0
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:24]|byte3||write something useful for field3|
+|[23:16]|byte2||write something useful for field2|
+|[15:8]|byte1||write something useful for field1|
+|[7:0]|byte0||write something useful for field0|
+
+### reg1
+  
+**Name** reg1  
+**Address** 0x1  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg1
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|field0||write something useful for field0|
+
+### reg2
+  
+**Name** reg2  
+**Address** 0x2  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg2
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[5:4]|monkey2|chimp=0, gorilla=1, phb=2|which monkey|
+|[3:2]|monkey|chimp=0, gorilla=1, phb=2|which monkey|
+|[1:1]|power2||write something useful for field power2|
+|[0:0]|power||write something useful for field power|
+
+### reg3
+  
+**Name** reg3  
+**Address** 0x3  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg3
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|field0||write something useful for field0|
+
+### reg4
+  
+**Name** reg4  
+**Address** 0x4  
+**Reset Value** 0x0000000c  
+**Access** read-write  
+**Description** reg4 is a very useful register. It can take down the moon when configured correctly.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg4|||
+
+### reg5
+  
+**Name** reg5  
+**Address** 0x5  
+**Access** read-write  
+**Description** reg5 is as useful as reg4 but without a reset value defined.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg5|||
+
+### reg6
+  
+**Name** reg6  
+**Address** 0x6  
+**Access** read-only  
+**Description** reg6 is a read only register.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg6|||
+
+### reg7
+  
+**Name** reg7  
+**Address** 0x7  
+**Reset Value** 0x00000000  
+**Access** read-write  
+**Description** write something useful for reg7
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[19:16]|nibble2||write something useful for nibble2|
+|[15:12]|unused1||unused|
+|[11:8]|nibble1||write something useful for nibble1|
+|[7:4]|unused0||unused|
+|[3:0]|nibble0||write something useful for nibble0|
diff --git a/example/output_default/example.rst b/example/output_default/example.rst
new file mode 100644
index 0000000..5ac4900
--- /dev/null
+++ b/example/output_default/example.rst
@@ -0,0 +1,165 @@
+====================
+Register description
+====================
+
+Registers
+---------
+
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| Address   | Register Name   | Description                                                                          |
++===========+=================+======================================================================================+
+| 0x00      | reg0_           | write something useful for reg0                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x01      | reg1_           | write something useful for reg1                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x02      | reg2_           | write something useful for reg2                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x03      | reg3_           | write something useful for reg3                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x04      | reg4_           | reg4 is a very useful register. It can take down the moon when configured correctly. |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x05      | reg5_           | reg5 is as useful as reg4 but without a reset value defined.                         |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x06      | reg6_           | reg6 is a read only register.                                                        |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x07      | reg7_           | write something useful for reg7                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+
+reg0
+----
+
+:Name:        reg0
+:Address:     0x0
+:Reset Value: 0x00000000
+:Access:      read-write
+:Description: write something useful for reg0
+
++---------+--------------+--------+-----------------------------------+
+| Bits    | Field name   | Type   | Description                       |
++=========+==============+========+===================================+
+| [31:24] | byte3        |        | write something useful for field3 |
++---------+--------------+--------+-----------------------------------+
+| [23:16] | byte2        |        | write something useful for field2 |
++---------+--------------+--------+-----------------------------------+
+| [15:8]  | byte1        |        | write something useful for field1 |
++---------+--------------+--------+-----------------------------------+
+| [7:0]   | byte0        |        | write something useful for field0 |
++---------+--------------+--------+-----------------------------------+
+
+reg1
+----
+
+:Name:        reg1
+:Address:     0x1
+:Reset Value: 0x00000001
+:Access:      read-write
+:Description: write something useful for reg1
+
++--------+--------------+--------+-----------------------------------+
+| Bits   | Field name   | Type   | Description                       |
++========+==============+========+===================================+
+| [31:0] | field0       |        | write something useful for field0 |
++--------+--------------+--------+-----------------------------------+
+
+reg2
+----
+
+:Name:        reg2
+:Address:     0x2
+:Reset Value: 0x00000001
+:Access:      read-write
+:Description: write something useful for reg2
+
++--------+--------------+---------------------------+-----------------------------------------+
+| Bits   | Field name   | Type                      | Description                             |
++========+==============+===========================+=========================================+
+| [5:4]  | monkey2      | chimp=0, gorilla=1, phb=2 | which monkey                            |
++--------+--------------+---------------------------+-----------------------------------------+
+| [3:2]  | monkey       | chimp=0, gorilla=1, phb=2 | which monkey                            |
++--------+--------------+---------------------------+-----------------------------------------+
+| [1:1]  | power2       |                           | write something useful for field power2 |
++--------+--------------+---------------------------+-----------------------------------------+
+| [0:0]  | power        |                           | write something useful for field power  |
++--------+--------------+---------------------------+-----------------------------------------+
+
+reg3
+----
+
+:Name:        reg3
+:Address:     0x3
+:Reset Value: 0x00000001
+:Access:      read-write
+:Description: write something useful for reg3
+
++--------+--------------+--------+-----------------------------------+
+| Bits   | Field name   | Type   | Description                       |
++========+==============+========+===================================+
+| [31:0] | field0       |        | write something useful for field0 |
++--------+--------------+--------+-----------------------------------+
+
+reg4
+----
+
+:Name:        reg4
+:Address:     0x4
+:Reset Value: 0x0000000c
+:Access:      read-write
+:Description: reg4 is a very useful register. It can take down the moon when configured correctly.
+
++--------+--------------+--------+---------------+
+| Bits   | Field name   | Type   | Description   |
++========+==============+========+===============+
+| [31:0] | reg4         |        |               |
++--------+--------------+--------+---------------+
+
+reg5
+----
+
+:Name:        reg5
+:Address:     0x5
+:Access:      read-write
+:Description: reg5 is as useful as reg4 but without a reset value defined.
+
++--------+--------------+--------+---------------+
+| Bits   | Field name   | Type   | Description   |
++========+==============+========+===============+
+| [31:0] | reg5         |        |               |
++--------+--------------+--------+---------------+
+
+reg6
+----
+
+:Name:        reg6
+:Address:     0x6
+:Access:      read-only
+:Description: reg6 is a read only register.
+
++--------+--------------+--------+---------------+
+| Bits   | Field name   | Type   | Description   |
++========+==============+========+===============+
+| [31:0] | reg6         |        |               |
++--------+--------------+--------+---------------+
+
+reg7
+----
+
+:Name:        reg7
+:Address:     0x7
+:Reset Value: 0x00000000
+:Access:      read-write
+:Description: write something useful for reg7
+
++---------+--------------+--------+------------------------------------+
+| Bits    | Field name   | Type   | Description                        |
++=========+==============+========+====================================+
+| [19:16] | nibble2      |        | write something useful for nibble2 |
++---------+--------------+--------+------------------------------------+
+| [15:12] | unused1      |        | unused                             |
++---------+--------------+--------+------------------------------------+
+| [11:8]  | nibble1      |        | write something useful for nibble1 |
++---------+--------------+--------+------------------------------------+
+| [7:4]   | unused0      |        | unused                             |
++---------+--------------+--------+------------------------------------+
+| [3:0]   | nibble0      |        | write something useful for nibble0 |
++---------+--------------+--------+------------------------------------+
+
diff --git a/example/output_default/example_sv_pkg.sv b/example/output_default/example_sv_pkg.sv
new file mode 100644
index 0000000..b84a889
--- /dev/null
+++ b/example/output_default/example_sv_pkg.sv
@@ -0,0 +1,166 @@
+// Automatically generated
+// with the command 'bin/ipxact2systemverilog --srcFile example/input/test.xml --destDir example/output_default --config example/input/default.ini'
+// 
+// Do not manually edit!
+// 
+package example_sv_pkg;
+
+
+const int addr_width = 3;
+const int data_width = 32;
+
+const int reg0_addr = 0;
+const int reg1_addr = 1;
+const int reg2_addr = 2;
+const int reg3_addr = 3;
+const int reg4_addr = 4;
+const int reg5_addr = 5;
+const int reg6_addr = 6;
+const int reg7_addr = 7;
+
+//synopsys translate_off
+const int example_regAddresses [8] = {
+     reg0_addr,
+     reg1_addr,
+     reg2_addr,
+     reg3_addr,
+     reg4_addr,
+     reg5_addr,
+     reg6_addr,
+     reg7_addr};
+
+const string example_regNames [8] = {
+      "reg0",
+      "reg1",
+      "reg2",
+      "reg3",
+      "reg4",
+      "reg5",
+      "reg6",
+      "reg7"};
+const reg example_regUnResetedAddresses [8] = {
+   0,
+   0,
+   0,
+   0,
+   0,
+   1,
+   1,
+   0};
+
+//synopsys translate_on
+
+
+
+typedef struct packed {
+   bit [7:0] byte3;//bits [31:24]
+   bit [7:0] byte2;//bits [23:16]
+   bit [7:0] byte1;//bits [15:8]
+   bit [7:0] byte0;//bits [7:0]
+} reg0_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] field0;//bits [31:0]
+} reg1_struct_type;
+
+
+typedef struct packed {
+   bit [1:0] monkey2;//bits [5:4]
+   bit [1:0] monkey;//bits [3:2]
+   bit [0:0] power2;//bits [1:1]
+   bit [0:0] power;//bits [0:0]
+} reg2_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] field0;//bits [31:0]
+} reg3_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] reg4;//bits [31:0]
+} reg4_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] reg5;//bits [31:0]
+} reg5_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] reg6;//bits [31:0]
+} reg6_struct_type;
+
+
+typedef struct packed {
+   bit [3:0] nibble2;//bits [19:16]
+   bit [3:0] unused1;//bits [15:12]
+   bit [3:0] nibble1;//bits [11:8]
+   bit [3:0] unused0;//bits [7:4]
+   bit [3:0] nibble0;//bits [3:0]
+} reg7_struct_type;
+
+const reg0_struct_type reg0_reset_value = 0;
+const reg1_struct_type reg1_reset_value = 1;
+const reg2_struct_type reg2_reset_value = 1;
+const reg3_struct_type reg3_reset_value = 1;
+const reg4_struct_type reg4_reset_value = 12;
+const reg7_struct_type reg7_reset_value = 0;
+
+typedef struct packed {
+   reg0_struct_type reg0;
+   reg1_struct_type reg1;
+   reg2_struct_type reg2;
+   reg3_struct_type reg3;
+   reg4_struct_type reg4;
+   reg5_struct_type reg5;
+   reg6_struct_type reg6;
+   reg7_struct_type reg7;
+} example_struct_type;
+
+function bit [31:0] read_example(example_struct_type registers,int address);
+      bit [31:0]  r;
+      case(address)
+         reg0_addr: r = registers.reg0;
+         reg1_addr: r = registers.reg1;
+         reg2_addr: r = registers.reg2;
+         reg3_addr: r = registers.reg3;
+         reg4_addr: r = registers.reg4;
+         reg5_addr: r = registers.reg5;
+         reg6_addr: r = registers.reg6;
+         reg7_addr: r = registers.reg7;
+        default: r =0;
+      endcase
+      return r;
+endfunction
+
+function example_struct_type write_example(bit [31:0] data, int address, 
+                                           example_struct_type registers);
+   example_struct_type r;
+   r = registers;
+   case(address)
+         reg0_addr: r.reg0=data;
+         reg1_addr: r.reg1=data;
+         reg2_addr: r.reg2=data;
+         reg3_addr: r.reg3=data;
+         reg4_addr: r.reg4=data;
+         reg5_addr: r.reg5=data;
+         reg6_addr: r.reg6=data;
+         reg7_addr: r.reg7=data;
+   endcase // case address
+   return r;
+endfunction
+
+function example_struct_type reset_example();
+   example_struct_type r;
+   r.reg0=reg0_reset_value;
+   r.reg1=reg1_reset_value;
+   r.reg2=reg2_reset_value;
+   r.reg3=reg3_reset_value;
+   r.reg4=reg4_reset_value;
+   r.reg7=reg7_reset_value;
+   return r;
+endfunction
+
+endpackage //example_sv_pkg
diff --git a/example/output_default/example_sv_pkg.svh b/example/output_default/example_sv_pkg.svh
new file mode 100644
index 0000000..872837a
--- /dev/null
+++ b/example/output_default/example_sv_pkg.svh
@@ -0,0 +1,3 @@
+
+`define example_addr_width 3
+`define example_data_width 32
diff --git a/example/output_default/example_vhd_pkg.vhd b/example/output_default/example_vhd_pkg.vhd
new file mode 100644
index 0000000..33e8815
--- /dev/null
+++ b/example/output_default/example_vhd_pkg.vhd
@@ -0,0 +1,331 @@
+-- 
+-- Automatically generated
+-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output_default --config example/input/default.ini'
+-- 
+-- Do not manually edit!
+-- 
+-- VHDL 93
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package example_vhd_pkg is
+
+  constant addr_width : natural := 3;
+  constant data_width : natural := 32;
+
+
+  type monkey_enum is (chimp,gorilla,phb);
+
+  function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector;
+
+  function sulv_to_monkey_enum(v: std_ulogic_vector (2-1 downto 0)) return monkey_enum;
+
+  constant reg0_addr : natural := 0 ;  -- 0x0
+  constant reg1_addr : natural := 1 ;  -- 0x1
+  constant reg2_addr : natural := 2 ;  -- 0x2
+  constant reg3_addr : natural := 3 ;  -- 0x3
+  constant reg4_addr : natural := 4 ;  -- 0x4
+  constant reg5_addr : natural := 5 ;  -- 0x5
+  constant reg6_addr : natural := 6 ;  -- 0x6
+  constant reg7_addr : natural := 7 ;  -- 0x7
+
+  constant reg0_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width));  -- 0x00000000
+  constant reg1_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg2_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg3_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg4_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(12, data_width));  -- 0x0000000c
+  constant reg7_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width));  -- 0x00000000
+
+
+  type reg0_record_type is record
+    byte3 : std_ulogic_vector(7 downto 0); -- [31:24]
+    byte2 : std_ulogic_vector(7 downto 0); -- [23:16]
+    byte1 : std_ulogic_vector(7 downto 0); -- [15:8]
+    byte0 : std_ulogic_vector(7 downto 0); -- [7:0]
+  end record;
+
+  type reg1_record_type is record
+    field0 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg2_record_type is record
+    monkey2 : monkey_enum; -- [5:4]
+    monkey : monkey_enum; -- [3:2]
+    power2 : std_ulogic; -- [1]
+    power : std_ulogic; -- [0]
+  end record;
+
+  type reg3_record_type is record
+    field0 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg4_record_type is record
+    reg4 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg5_record_type is record
+    reg5 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg6_record_type is record
+    reg6 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg7_record_type is record
+    nibble2 : std_ulogic_vector(3 downto 0); -- [19:16]
+    unused1 : std_ulogic_vector(3 downto 0); -- [15:12]
+    nibble1 : std_ulogic_vector(3 downto 0); -- [11:8]
+    unused0 : std_ulogic_vector(3 downto 0); -- [7:4]
+    nibble0 : std_ulogic_vector(3 downto 0); -- [3:0]
+  end record;
+
+  type example_in_record_type is record
+    reg6 : reg6_record_type; -- addr 0x6
+  end record;
+
+  type example_out_record_type is record
+    reg0 : reg0_record_type; -- addr 0x0
+    reg1 : reg1_record_type; -- addr 0x1
+    reg2 : reg2_record_type; -- addr 0x2
+    reg3 : reg3_record_type; -- addr 0x3
+    reg4 : reg4_record_type; -- addr 0x4
+    reg5 : reg5_record_type; -- addr 0x5
+    reg7 : reg7_record_type; -- addr 0x7
+  end record;
+
+  function read_example(registers_i : example_in_record_type;
+                        registers_o : example_out_record_type;
+                        address : std_ulogic_vector (addr_width-1 downto 0)
+                        ) return std_ulogic_vector;
+
+  function write_example(value : std_ulogic_vector (data_width-1 downto 0);
+                         address : std_ulogic_vector (addr_width-1 downto 0);
+                         registers_o : example_out_record_type
+                         ) return example_out_record_type;
+
+  function reset_example return example_out_record_type;
+
+end;
+
+
+package body example_vhd_pkg is 
+
+  function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector is
+    variable r : std_ulogic_vector (2-1 downto 0);
+  begin
+       case v is
+         when chimp => r:="00"; -- 0
+         when gorilla => r:="01"; -- 1
+         when phb => r:="10"; -- 2
+       end case;
+    return r;
+  end function;
+
+  function sulv_to_monkey_enum(v: std_ulogic_vector (2-1 downto 0)) return monkey_enum is
+    variable r : monkey_enum;
+  begin
+       case v is
+         when "00" => r:=chimp;
+         when "01" => r:=gorilla;
+         when "10" => r:=phb;
+         when others => r:=chimp; -- error 
+       end case;
+    return r;
+  end function;
+
+  function reg0_record_type_to_sulv (v : reg0_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 24) := v.byte3;
+    r(23 downto 16) := v.byte2;
+    r(15 downto 8) := v.byte1;
+    r(7 downto 0) := v.byte0;
+    return r;
+  end function;
+
+  function sulv_to_reg0_record_type (v : std_ulogic_vector) return reg0_record_type is
+    variable r : reg0_record_type;
+  begin
+    r.byte3 := v(31 downto 24);
+    r.byte2 := v(23 downto 16);
+    r.byte1 := v(15 downto 8);
+    r.byte0 := v(7 downto 0);
+    return r;
+  end function;
+
+  function reg1_record_type_to_sulv (v : reg1_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.field0;
+    return r;
+  end function;
+
+  function sulv_to_reg1_record_type (v : std_ulogic_vector) return reg1_record_type is
+    variable r : reg1_record_type;
+  begin
+    r.field0 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg2_record_type_to_sulv (v : reg2_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(5 downto 4) := monkey_enum_to_sulv(v.monkey2);
+    r(3 downto 2) := monkey_enum_to_sulv(v.monkey);
+    r(1) := v.power2;
+    r(0) := v.power;
+    return r;
+  end function;
+
+  function sulv_to_reg2_record_type (v : std_ulogic_vector) return reg2_record_type is
+    variable r : reg2_record_type;
+  begin
+    r.monkey2 := sulv_to_monkey_enum(v(5 downto 4));
+    r.monkey := sulv_to_monkey_enum(v(3 downto 2));
+    r.power2 := v(1);
+    r.power := v(0);
+    return r;
+  end function;
+
+  function reg3_record_type_to_sulv (v : reg3_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.field0;
+    return r;
+  end function;
+
+  function sulv_to_reg3_record_type (v : std_ulogic_vector) return reg3_record_type is
+    variable r : reg3_record_type;
+  begin
+    r.field0 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg4_record_type_to_sulv (v : reg4_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.reg4;
+    return r;
+  end function;
+
+  function sulv_to_reg4_record_type (v : std_ulogic_vector) return reg4_record_type is
+    variable r : reg4_record_type;
+  begin
+    r.reg4 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg5_record_type_to_sulv (v : reg5_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.reg5;
+    return r;
+  end function;
+
+  function sulv_to_reg5_record_type (v : std_ulogic_vector) return reg5_record_type is
+    variable r : reg5_record_type;
+  begin
+    r.reg5 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg6_record_type_to_sulv (v : reg6_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.reg6;
+    return r;
+  end function;
+
+  function sulv_to_reg6_record_type (v : std_ulogic_vector) return reg6_record_type is
+    variable r : reg6_record_type;
+  begin
+    r.reg6 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg7_record_type_to_sulv (v : reg7_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(19 downto 16) := v.nibble2;
+    r(15 downto 12) := v.unused1;
+    r(11 downto 8) := v.nibble1;
+    r(7 downto 4) := v.unused0;
+    r(3 downto 0) := v.nibble0;
+    return r;
+  end function;
+
+  function sulv_to_reg7_record_type (v : std_ulogic_vector) return reg7_record_type is
+    variable r : reg7_record_type;
+  begin
+    r.nibble2 := v(19 downto 16);
+    r.unused1 := v(15 downto 12);
+    r.nibble1 := v(11 downto 8);
+    r.unused0 := v(7 downto 4);
+    r.nibble0 := v(3 downto 0);
+    return r;
+  end function;
+
+  function read_example(registers_i : example_in_record_type;
+                        registers_o : example_out_record_type;
+                        address : std_ulogic_vector (addr_width-1 downto 0)
+                        ) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    case to_integer(unsigned(address)) is
+      when reg0_addr => r:= reg0_record_type_to_sulv(registers_o.reg0);
+      when reg1_addr => r:= reg1_record_type_to_sulv(registers_o.reg1);
+      when reg2_addr => r:= reg2_record_type_to_sulv(registers_o.reg2);
+      when reg3_addr => r:= reg3_record_type_to_sulv(registers_o.reg3);
+      when reg4_addr => r:= reg4_record_type_to_sulv(registers_o.reg4);
+      when reg5_addr => r:= reg5_record_type_to_sulv(registers_o.reg5);
+      when reg6_addr => r:= reg6_record_type_to_sulv(registers_i.reg6);
+      when reg7_addr => r:= reg7_record_type_to_sulv(registers_o.reg7);
+      when others => r := (others => '0');
+    end case;
+    return r;
+  end function;
+
+  function write_example(value : std_ulogic_vector (data_width-1 downto 0);
+                         address : std_ulogic_vector (addr_width-1 downto 0);
+                         registers_o : example_out_record_type
+                         ) return example_out_record_type is
+    variable r : example_out_record_type;
+  begin
+    r := registers_o;
+    case to_integer(unsigned(address)) is
+         when reg0_addr => r.reg0 := sulv_to_reg0_record_type(value);
+         when reg1_addr => r.reg1 := sulv_to_reg1_record_type(value);
+         when reg2_addr => r.reg2 := sulv_to_reg2_record_type(value);
+         when reg3_addr => r.reg3 := sulv_to_reg3_record_type(value);
+         when reg4_addr => r.reg4 := sulv_to_reg4_record_type(value);
+         when reg5_addr => r.reg5 := sulv_to_reg5_record_type(value);
+         when reg7_addr => r.reg7 := sulv_to_reg7_record_type(value);
+      when others => null;
+    end case;
+    return r;
+  end function;
+
+  function reset_example return example_out_record_type is
+    variable r : example_out_record_type;
+  begin
+         r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
+         r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
+         r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
+         r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
+         r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
+         r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
+    return r;
+  end function;
+
+end package body; 
diff --git a/example/output_no_default/example.md b/example/output_no_default/example.md
new file mode 100644
index 0000000..ccfe5b8
--- /dev/null
+++ b/example/output_no_default/example.md
@@ -0,0 +1,109 @@
+
+# Register description
+
+## Registers
+
+|Address|Register Name|Description|
+| :--- | :--- | :--- |
+|0x00|[reg0](#reg0)|write something useful for reg0|
+|0x01|[reg1](#reg1)|write something useful for reg1|
+|0x02|[reg2](#reg2)|write something useful for reg2|
+|0x03|[reg3](#reg3)|write something useful for reg3|
+|0x04|[reg4](#reg4)|reg4 is a very useful register. It can take down the moon when configured correctly.|
+|0x05|[reg5](#reg5)|reg5 is as useful as reg4 but without a reset value defined.|
+|0x06|[reg6](#reg6)|reg6 is a read only register.|
+|0x07|[reg7](#reg7)|write something useful for reg7|
+
+### reg0
+  
+**Name** reg0  
+**Address** 0x0  
+**Reset Value** 0x00000000  
+**Access** read-write  
+**Description** write something useful for reg0
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:24]|byte3||write something useful for field3|
+|[23:16]|byte2||write something useful for field2|
+|[15:8]|byte1||write something useful for field1|
+|[7:0]|byte0||write something useful for field0|
+
+### reg1
+  
+**Name** reg1  
+**Address** 0x1  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg1
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|field0||write something useful for field0|
+
+### reg2
+  
+**Name** reg2  
+**Address** 0x2  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg2
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[5:4]|monkey2|chimp=0, gorilla=1, phb=2|which monkey|
+|[3:2]|monkey|chimp=0, gorilla=1, phb=2|which monkey|
+|[1:1]|power2|false=0, true=1|write something useful for field power2|
+|[0:0]|power|false=0, true=1|write something useful for field power|
+
+### reg3
+  
+**Name** reg3  
+**Address** 0x3  
+**Reset Value** 0x00000001  
+**Access** read-write  
+**Description** write something useful for reg3
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|field0||write something useful for field0|
+
+### reg4
+  
+**Name** reg4  
+**Address** 0x4  
+**Reset Value** 0x0000000c  
+**Access** read-write  
+**Description** reg4 is a very useful register. It can take down the moon when configured correctly.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg4|||
+
+### reg5
+  
+**Name** reg5  
+**Address** 0x5  
+**Access** read-write  
+**Description** reg5 is as useful as reg4 but without a reset value defined.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg5|||
+
+### reg6
+  
+**Name** reg6  
+**Address** 0x6  
+**Access** read-only  
+**Description** reg6 is a read only register.
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[31:0]|reg6|||
+
+### reg7
+  
+**Name** reg7  
+**Address** 0x7  
+**Reset Value** 0x00000000  
+**Access** read-write  
+**Description** write something useful for reg7
+|Bits|Field name|Type|Description|
+| :--- | :--- | :--- | :--- |
+|[19:16]|nibble2||write something useful for nibble2|
+|[11:8]|nibble1||write something useful for nibble1|
+|[3:0]|nibble0||write something useful for nibble0|
diff --git a/example/output_no_default/example.rst b/example/output_no_default/example.rst
new file mode 100644
index 0000000..a9e66da
--- /dev/null
+++ b/example/output_no_default/example.rst
@@ -0,0 +1,161 @@
+====================
+Register description
+====================
+
+Registers
+---------
+
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| Address   | Register Name   | Description                                                                          |
++===========+=================+======================================================================================+
+| 0x00      | reg0_           | write something useful for reg0                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x01      | reg1_           | write something useful for reg1                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x02      | reg2_           | write something useful for reg2                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x03      | reg3_           | write something useful for reg3                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x04      | reg4_           | reg4 is a very useful register. It can take down the moon when configured correctly. |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x05      | reg5_           | reg5 is as useful as reg4 but without a reset value defined.                         |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x06      | reg6_           | reg6 is a read only register.                                                        |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+| 0x07      | reg7_           | write something useful for reg7                                                      |
++-----------+-----------------+--------------------------------------------------------------------------------------+
+
+reg0
+----
+
+:Name:        reg0
+:Address:     0x0
+:Reset Value: 0x00000000
+:Access:      read-write
+:Description: write something useful for reg0
+
++---------+--------------+--------+-----------------------------------+
+| Bits    | Field name   | Type   | Description                       |
++=========+==============+========+===================================+
+| [31:24] | byte3        |        | write something useful for field3 |
++---------+--------------+--------+-----------------------------------+
+| [23:16] | byte2        |        | write something useful for field2 |
++---------+--------------+--------+-----------------------------------+
+| [15:8]  | byte1        |        | write something useful for field1 |
++---------+--------------+--------+-----------------------------------+
+| [7:0]   | byte0        |        | write something useful for field0 |
++---------+--------------+--------+-----------------------------------+
+
+reg1
+----
+
+:Name:        reg1
+:Address:     0x1
+:Reset Value: 0x00000001
+:Access:      read-write
+:Description: write something useful for reg1
+
++--------+--------------+--------+-----------------------------------+
+| Bits   | Field name   | Type   | Description                       |
++========+==============+========+===================================+
+| [31:0] | field0       |        | write something useful for field0 |
++--------+--------------+--------+-----------------------------------+
+
+reg2
+----
+
+:Name:        reg2
+:Address:     0x2
+:Reset Value: 0x00000001
+:Access:      read-write
+:Description: write something useful for reg2
+
++--------+--------------+---------------------------+-----------------------------------------+
+| Bits   | Field name   | Type                      | Description                             |
++========+==============+===========================+=========================================+
+| [5:4]  | monkey2      | chimp=0, gorilla=1, phb=2 | which monkey                            |
++--------+--------------+---------------------------+-----------------------------------------+
+| [3:2]  | monkey       | chimp=0, gorilla=1, phb=2 | which monkey                            |
++--------+--------------+---------------------------+-----------------------------------------+
+| [1:1]  | power2       | false=0, true=1           | write something useful for field power2 |
++--------+--------------+---------------------------+-----------------------------------------+
+| [0:0]  | power        | false=0, true=1           | write something useful for field power  |
++--------+--------------+---------------------------+-----------------------------------------+
+
+reg3
+----
+
+:Name:        reg3
+:Address:     0x3
+:Reset Value: 0x00000001
+:Access:      read-write
+:Description: write something useful for reg3
+
++--------+--------------+--------+-----------------------------------+
+| Bits   | Field name   | Type   | Description                       |
++========+==============+========+===================================+
+| [31:0] | field0       |        | write something useful for field0 |
++--------+--------------+--------+-----------------------------------+
+
+reg4
+----
+
+:Name:        reg4
+:Address:     0x4
+:Reset Value: 0x0000000c
+:Access:      read-write
+:Description: reg4 is a very useful register. It can take down the moon when configured correctly.
+
++--------+--------------+--------+---------------+
+| Bits   | Field name   | Type   | Description   |
++========+==============+========+===============+
+| [31:0] | reg4         |        |               |
++--------+--------------+--------+---------------+
+
+reg5
+----
+
+:Name:        reg5
+:Address:     0x5
+:Access:      read-write
+:Description: reg5 is as useful as reg4 but without a reset value defined.
+
++--------+--------------+--------+---------------+
+| Bits   | Field name   | Type   | Description   |
++========+==============+========+===============+
+| [31:0] | reg5         |        |               |
++--------+--------------+--------+---------------+
+
+reg6
+----
+
+:Name:        reg6
+:Address:     0x6
+:Access:      read-only
+:Description: reg6 is a read only register.
+
++--------+--------------+--------+---------------+
+| Bits   | Field name   | Type   | Description   |
++========+==============+========+===============+
+| [31:0] | reg6         |        |               |
++--------+--------------+--------+---------------+
+
+reg7
+----
+
+:Name:        reg7
+:Address:     0x7
+:Reset Value: 0x00000000
+:Access:      read-write
+:Description: write something useful for reg7
+
++---------+--------------+--------+------------------------------------+
+| Bits    | Field name   | Type   | Description                        |
++=========+==============+========+====================================+
+| [19:16] | nibble2      |        | write something useful for nibble2 |
++---------+--------------+--------+------------------------------------+
+| [11:8]  | nibble1      |        | write something useful for nibble1 |
++---------+--------------+--------+------------------------------------+
+| [3:0]   | nibble0      |        | write something useful for nibble0 |
++---------+--------------+--------+------------------------------------+
+
diff --git a/example/output_no_default/example_sv_pkg.sv b/example/output_no_default/example_sv_pkg.sv
new file mode 100644
index 0000000..c4f01d2
--- /dev/null
+++ b/example/output_no_default/example_sv_pkg.sv
@@ -0,0 +1,164 @@
+// Automatically generated
+// with the command 'bin/ipxact2systemverilog --srcFile example/input/test.xml --destDir example/output_no_default --config example/input/no_default.ini'
+// 
+// Do not manually edit!
+// 
+package example_sv_pkg;
+
+
+const int addr_width = 3;
+const int data_width = 32;
+
+const int reg0_addr = 0;
+const int reg1_addr = 1;
+const int reg2_addr = 2;
+const int reg3_addr = 3;
+const int reg4_addr = 4;
+const int reg5_addr = 5;
+const int reg6_addr = 6;
+const int reg7_addr = 7;
+
+//synopsys translate_off
+const int example_regAddresses [8] = {
+     reg0_addr,
+     reg1_addr,
+     reg2_addr,
+     reg3_addr,
+     reg4_addr,
+     reg5_addr,
+     reg6_addr,
+     reg7_addr};
+
+const string example_regNames [8] = {
+      "reg0",
+      "reg1",
+      "reg2",
+      "reg3",
+      "reg4",
+      "reg5",
+      "reg6",
+      "reg7"};
+const reg example_regUnResetedAddresses [8] = {
+   0,
+   0,
+   0,
+   0,
+   0,
+   1,
+   1,
+   0};
+
+//synopsys translate_on
+
+
+
+typedef struct packed {
+   bit [7:0] byte3;//bits [31:24]
+   bit [7:0] byte2;//bits [23:16]
+   bit [7:0] byte1;//bits [15:8]
+   bit [7:0] byte0;//bits [7:0]
+} reg0_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] field0;//bits [31:0]
+} reg1_struct_type;
+
+
+typedef struct packed {
+   bit [1:0] monkey2;//bits [5:4]
+   bit [1:0] monkey;//bits [3:2]
+   bit [0:0] power2;//bits [1:1]
+   bit [0:0] power;//bits [0:0]
+} reg2_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] field0;//bits [31:0]
+} reg3_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] reg4;//bits [31:0]
+} reg4_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] reg5;//bits [31:0]
+} reg5_struct_type;
+
+
+typedef struct packed {
+   bit [31:0] reg6;//bits [31:0]
+} reg6_struct_type;
+
+
+typedef struct packed {
+   bit [3:0] nibble2;//bits [19:16]
+   bit [3:0] nibble1;//bits [11:8]
+   bit [3:0] nibble0;//bits [3:0]
+} reg7_struct_type;
+
+const reg0_struct_type reg0_reset_value = 0;
+const reg1_struct_type reg1_reset_value = 1;
+const reg2_struct_type reg2_reset_value = 1;
+const reg3_struct_type reg3_reset_value = 1;
+const reg4_struct_type reg4_reset_value = 12;
+const reg7_struct_type reg7_reset_value = 0;
+
+typedef struct packed {
+   reg0_struct_type reg0;
+   reg1_struct_type reg1;
+   reg2_struct_type reg2;
+   reg3_struct_type reg3;
+   reg4_struct_type reg4;
+   reg5_struct_type reg5;
+   reg6_struct_type reg6;
+   reg7_struct_type reg7;
+} example_struct_type;
+
+function bit [31:0] read_example(example_struct_type registers,int address);
+      bit [31:0]  r;
+      case(address)
+         reg0_addr: r = registers.reg0;
+         reg1_addr: r = registers.reg1;
+         reg2_addr: r = registers.reg2;
+         reg3_addr: r = registers.reg3;
+         reg4_addr: r = registers.reg4;
+         reg5_addr: r = registers.reg5;
+         reg6_addr: r = registers.reg6;
+         reg7_addr: r = registers.reg7;
+        default: r =0;
+      endcase
+      return r;
+endfunction
+
+function example_struct_type write_example(bit [31:0] data, int address, 
+                                           example_struct_type registers);
+   example_struct_type r;
+   r = registers;
+   case(address)
+         reg0_addr: r.reg0=data;
+         reg1_addr: r.reg1=data;
+         reg2_addr: r.reg2=data;
+         reg3_addr: r.reg3=data;
+         reg4_addr: r.reg4=data;
+         reg5_addr: r.reg5=data;
+         reg6_addr: r.reg6=data;
+         reg7_addr: r.reg7=data;
+   endcase // case address
+   return r;
+endfunction
+
+function example_struct_type reset_example();
+   example_struct_type r;
+   r.reg0=reg0_reset_value;
+   r.reg1=reg1_reset_value;
+   r.reg2=reg2_reset_value;
+   r.reg3=reg3_reset_value;
+   r.reg4=reg4_reset_value;
+   r.reg7=reg7_reset_value;
+   return r;
+endfunction
+
+endpackage //example_sv_pkg
diff --git a/example/output_no_default/example_sv_pkg.svh b/example/output_no_default/example_sv_pkg.svh
new file mode 100644
index 0000000..872837a
--- /dev/null
+++ b/example/output_no_default/example_sv_pkg.svh
@@ -0,0 +1,3 @@
+
+`define example_addr_width 3
+`define example_data_width 32
diff --git a/example/output_no_default/example_vhd_pkg.vhd b/example/output_no_default/example_vhd_pkg.vhd
new file mode 100644
index 0000000..8bdc845
--- /dev/null
+++ b/example/output_no_default/example_vhd_pkg.vhd
@@ -0,0 +1,352 @@
+-- 
+-- Automatically generated
+-- with the command 'bin/ipxact2vhdl --srcFile example/input/test.xml --destDir example/output_no_default --config example/input/no_default.ini'
+-- 
+-- Do not manually edit!
+-- 
+-- VHDL 93
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package example_vhd_pkg is
+
+  constant addr_width : natural := 3;
+  constant data_width : natural := 32;
+
+
+  type power_enum is (false,true);
+
+  function power_enum_to_sulv(v: power_enum ) return std_ulogic_vector;
+
+  function sulv_to_power_enum(v: std_ulogic_vector (1-1 downto 0)) return power_enum;
+
+  type monkey_enum is (chimp,gorilla,phb);
+
+  function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector;
+
+  function sulv_to_monkey_enum(v: std_ulogic_vector (2-1 downto 0)) return monkey_enum;
+
+  constant reg0_addr : natural := 0 ;  -- 0x0
+  constant reg1_addr : natural := 1 ;  -- 0x1
+  constant reg2_addr : natural := 2 ;  -- 0x2
+  constant reg3_addr : natural := 3 ;  -- 0x3
+  constant reg4_addr : natural := 4 ;  -- 0x4
+  constant reg5_addr : natural := 5 ;  -- 0x5
+  constant reg6_addr : natural := 6 ;  -- 0x6
+  constant reg7_addr : natural := 7 ;  -- 0x7
+
+  constant reg0_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width));  -- 0x00000000
+  constant reg1_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg2_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg3_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(1, data_width));  -- 0x00000001
+  constant reg4_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(12, data_width));  -- 0x0000000c
+  constant reg7_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned(0, data_width));  -- 0x00000000
+
+
+  type reg0_record_type is record
+    byte3 : std_ulogic_vector(7 downto 0); -- [31:24]
+    byte2 : std_ulogic_vector(7 downto 0); -- [23:16]
+    byte1 : std_ulogic_vector(7 downto 0); -- [15:8]
+    byte0 : std_ulogic_vector(7 downto 0); -- [7:0]
+  end record;
+
+  type reg1_record_type is record
+    field0 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg2_record_type is record
+    monkey2 : monkey_enum; -- [5:4]
+    monkey : monkey_enum; -- [3:2]
+    power2 : power_enum; -- [1:1]
+    power : power_enum; -- [0:0]
+  end record;
+
+  type reg3_record_type is record
+    field0 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg4_record_type is record
+    reg4 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg5_record_type is record
+    reg5 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg6_record_type is record
+    reg6 : std_ulogic_vector(31 downto 0); -- [31:0]
+  end record;
+
+  type reg7_record_type is record
+    nibble2 : std_ulogic_vector(3 downto 0); -- [19:16]
+    nibble1 : std_ulogic_vector(3 downto 0); -- [11:8]
+    nibble0 : std_ulogic_vector(3 downto 0); -- [3:0]
+  end record;
+
+  type example_in_record_type is record
+    reg6 : reg6_record_type; -- addr 0x6
+  end record;
+
+  type example_out_record_type is record
+    reg0 : reg0_record_type; -- addr 0x0
+    reg1 : reg1_record_type; -- addr 0x1
+    reg2 : reg2_record_type; -- addr 0x2
+    reg3 : reg3_record_type; -- addr 0x3
+    reg4 : reg4_record_type; -- addr 0x4
+    reg5 : reg5_record_type; -- addr 0x5
+    reg7 : reg7_record_type; -- addr 0x7
+  end record;
+
+  function read_example(registers_i : example_in_record_type;
+                        registers_o : example_out_record_type;
+                        address : std_ulogic_vector (addr_width-1 downto 0)
+                        ) return std_ulogic_vector;
+
+  function write_example(value : std_ulogic_vector (data_width-1 downto 0);
+                         address : std_ulogic_vector (addr_width-1 downto 0);
+                         registers_o : example_out_record_type
+                         ) return example_out_record_type;
+
+  function reset_example return example_out_record_type;
+
+end;
+
+
+package body example_vhd_pkg is 
+
+  function power_enum_to_sulv(v: power_enum ) return std_ulogic_vector is
+    variable r : std_ulogic_vector (1-1 downto 0);
+  begin
+       case v is
+         when false => r:="0"; -- 0
+         when true => r:="1"; -- 1
+       end case;
+    return r;
+  end function;
+
+  function sulv_to_power_enum(v: std_ulogic_vector (1-1 downto 0)) return power_enum is
+    variable r : power_enum;
+  begin
+       case v is
+         when "0" => r:=false;
+         when "1" => r:=true;
+         when others => r:=false; -- error 
+       end case;
+    return r;
+  end function;
+
+  function monkey_enum_to_sulv(v: monkey_enum ) return std_ulogic_vector is
+    variable r : std_ulogic_vector (2-1 downto 0);
+  begin
+       case v is
+         when chimp => r:="00"; -- 0
+         when gorilla => r:="01"; -- 1
+         when phb => r:="10"; -- 2
+       end case;
+    return r;
+  end function;
+
+  function sulv_to_monkey_enum(v: std_ulogic_vector (2-1 downto 0)) return monkey_enum is
+    variable r : monkey_enum;
+  begin
+       case v is
+         when "00" => r:=chimp;
+         when "01" => r:=gorilla;
+         when "10" => r:=phb;
+         when others => r:=chimp; -- error 
+       end case;
+    return r;
+  end function;
+
+  function reg0_record_type_to_sulv (v : reg0_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 24) := v.byte3;
+    r(23 downto 16) := v.byte2;
+    r(15 downto 8) := v.byte1;
+    r(7 downto 0) := v.byte0;
+    return r;
+  end function;
+
+  function sulv_to_reg0_record_type (v : std_ulogic_vector) return reg0_record_type is
+    variable r : reg0_record_type;
+  begin
+    r.byte3 := v(31 downto 24);
+    r.byte2 := v(23 downto 16);
+    r.byte1 := v(15 downto 8);
+    r.byte0 := v(7 downto 0);
+    return r;
+  end function;
+
+  function reg1_record_type_to_sulv (v : reg1_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.field0;
+    return r;
+  end function;
+
+  function sulv_to_reg1_record_type (v : std_ulogic_vector) return reg1_record_type is
+    variable r : reg1_record_type;
+  begin
+    r.field0 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg2_record_type_to_sulv (v : reg2_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(5 downto 4) := monkey_enum_to_sulv(v.monkey2);
+    r(3 downto 2) := monkey_enum_to_sulv(v.monkey);
+    r(1 downto 1) := power_enum_to_sulv(v.power2);
+    r(0 downto 0) := power_enum_to_sulv(v.power);
+    return r;
+  end function;
+
+  function sulv_to_reg2_record_type (v : std_ulogic_vector) return reg2_record_type is
+    variable r : reg2_record_type;
+  begin
+    r.monkey2 := sulv_to_monkey_enum(v(5 downto 4));
+    r.monkey := sulv_to_monkey_enum(v(3 downto 2));
+    r.power2 := sulv_to_power_enum(v(1 downto 1));
+    r.power := sulv_to_power_enum(v(0 downto 0));
+    return r;
+  end function;
+
+  function reg3_record_type_to_sulv (v : reg3_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.field0;
+    return r;
+  end function;
+
+  function sulv_to_reg3_record_type (v : std_ulogic_vector) return reg3_record_type is
+    variable r : reg3_record_type;
+  begin
+    r.field0 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg4_record_type_to_sulv (v : reg4_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.reg4;
+    return r;
+  end function;
+
+  function sulv_to_reg4_record_type (v : std_ulogic_vector) return reg4_record_type is
+    variable r : reg4_record_type;
+  begin
+    r.reg4 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg5_record_type_to_sulv (v : reg5_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.reg5;
+    return r;
+  end function;
+
+  function sulv_to_reg5_record_type (v : std_ulogic_vector) return reg5_record_type is
+    variable r : reg5_record_type;
+  begin
+    r.reg5 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg6_record_type_to_sulv (v : reg6_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(31 downto 0) := v.reg6;
+    return r;
+  end function;
+
+  function sulv_to_reg6_record_type (v : std_ulogic_vector) return reg6_record_type is
+    variable r : reg6_record_type;
+  begin
+    r.reg6 := v(31 downto 0);
+    return r;
+  end function;
+
+  function reg7_record_type_to_sulv (v : reg7_record_type) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    r :=  (others => '0');
+    r(19 downto 16) := v.nibble2;
+    r(11 downto 8) := v.nibble1;
+    r(3 downto 0) := v.nibble0;
+    return r;
+  end function;
+
+  function sulv_to_reg7_record_type (v : std_ulogic_vector) return reg7_record_type is
+    variable r : reg7_record_type;
+  begin
+    r.nibble2 := v(19 downto 16);
+    r.nibble1 := v(11 downto 8);
+    r.nibble0 := v(3 downto 0);
+    return r;
+  end function;
+
+  function read_example(registers_i : example_in_record_type;
+                        registers_o : example_out_record_type;
+                        address : std_ulogic_vector (addr_width-1 downto 0)
+                        ) return std_ulogic_vector is
+    variable r : std_ulogic_vector (data_width-1 downto 0);
+  begin
+    case to_integer(unsigned(address)) is
+      when reg0_addr => r:= reg0_record_type_to_sulv(registers_o.reg0);
+      when reg1_addr => r:= reg1_record_type_to_sulv(registers_o.reg1);
+      when reg2_addr => r:= reg2_record_type_to_sulv(registers_o.reg2);
+      when reg3_addr => r:= reg3_record_type_to_sulv(registers_o.reg3);
+      when reg4_addr => r:= reg4_record_type_to_sulv(registers_o.reg4);
+      when reg5_addr => r:= reg5_record_type_to_sulv(registers_o.reg5);
+      when reg6_addr => r:= reg6_record_type_to_sulv(registers_i.reg6);
+      when reg7_addr => r:= reg7_record_type_to_sulv(registers_o.reg7);
+      when others => r := (others => '0');
+    end case;
+    return r;
+  end function;
+
+  function write_example(value : std_ulogic_vector (data_width-1 downto 0);
+                         address : std_ulogic_vector (addr_width-1 downto 0);
+                         registers_o : example_out_record_type
+                         ) return example_out_record_type is
+    variable r : example_out_record_type;
+  begin
+    r := registers_o;
+    case to_integer(unsigned(address)) is
+         when reg0_addr => r.reg0 := sulv_to_reg0_record_type(value);
+         when reg1_addr => r.reg1 := sulv_to_reg1_record_type(value);
+         when reg2_addr => r.reg2 := sulv_to_reg2_record_type(value);
+         when reg3_addr => r.reg3 := sulv_to_reg3_record_type(value);
+         when reg4_addr => r.reg4 := sulv_to_reg4_record_type(value);
+         when reg5_addr => r.reg5 := sulv_to_reg5_record_type(value);
+         when reg7_addr => r.reg7 := sulv_to_reg7_record_type(value);
+      when others => null;
+    end case;
+    return r;
+  end function;
+
+  function reset_example return example_out_record_type is
+    variable r : example_out_record_type;
+  begin
+         r.reg0 := sulv_to_reg0_record_type(reg0_reset_value);
+         r.reg1 := sulv_to_reg1_record_type(reg1_reset_value);
+         r.reg2 := sulv_to_reg2_record_type(reg2_reset_value);
+         r.reg3 := sulv_to_reg3_record_type(reg3_reset_value);
+         r.reg4 := sulv_to_reg4_record_type(reg4_reset_value);
+         r.reg7 := sulv_to_reg7_record_type(reg7_reset_value);
+    return r;
+  end function;
+
+end package body; 
diff --git a/ipxact2systemverilog/ipxact2hdlCommon.py b/ipxact2systemverilog/ipxact2hdlCommon.py
index d4460cd..a57a5aa 100644
--- a/ipxact2systemverilog/ipxact2hdlCommon.py
+++ b/ipxact2systemverilog/ipxact2hdlCommon.py
@@ -19,16 +19,24 @@
 #
 # andreas.lindh (a) hiced.com
 from __future__ import print_function
-import datetime
 import math
 import os
 import sys
 import xml.etree.ElementTree as ETree
 import tabulate
+from mdutils.mdutils import MdUtils
 
+DEFAULT_INI = {'global': {'unusedholes': 'yes',
+                          'onebitenum': 'no'}}
 
-def sortRegisterAndFillHoles(regName, fieldNameList, bitOffsetList,
-                             bitWidthList, fieldDescList, enumTypeList):
+
+def sortRegisterAndFillHoles(regName,
+                             fieldNameList,
+                             bitOffsetList,
+                             bitWidthList,
+                             fieldDescList,
+                             enumTypeList,
+                             unusedHoles=True):
     # sort the lists, highest offset first
     fieldNameList = fieldNameList
     bitOffsetList = [int(x) for x in bitOffsetList]
@@ -44,27 +52,28 @@ def sortRegisterAndFillHoles(regName, fieldNameList, bitOffsetList,
     bitWidthList = list([int(x) for x in bitWidthList])
     fieldDescList = list(fieldDescList)
     enumTypeList = list(enumTypeList)
-    unUsedCnt = 0
-    nextFieldStartingPos = 0
-    # fill up the holes
-    index = 0
-    register_width = bitOffsetList[-1] + bitWidthList[-1]
-    while register_width > nextFieldStartingPos:
-        if nextFieldStartingPos != bitOffsetList[index]:
-            newBitWidth = bitOffsetList[index] - nextFieldStartingPos
-            bitOffsetList.insert(index, nextFieldStartingPos)
-            fieldNameList.insert(index, 'unused' + str(unUsedCnt))
-            bitWidthList.insert(index, newBitWidth)
-            fieldDescList.insert(index, 'unused')
-            enumTypeList.insert(index, '')
-            unUsedCnt += 1
-        nextFieldStartingPos = int(bitOffsetList[index]) + int(bitWidthList[index])
-        index += 1
+    if unusedHoles:
+        unUsedCnt = 0
+        nextFieldStartingPos = 0
+        # fill up the holes
+        index = 0
+        register_width = bitOffsetList[-1] + bitWidthList[-1]
+        while register_width > nextFieldStartingPos:
+            if nextFieldStartingPos != bitOffsetList[index]:
+                newBitWidth = bitOffsetList[index] - nextFieldStartingPos
+                bitOffsetList.insert(index, nextFieldStartingPos)
+                fieldNameList.insert(index, 'unused' + str(unUsedCnt))
+                bitWidthList.insert(index, newBitWidth)
+                fieldDescList.insert(index, 'unused')
+                enumTypeList.insert(index, '')
+                unUsedCnt += 1
+            nextFieldStartingPos = int(bitOffsetList[index]) + int(bitWidthList[index])
+            index += 1
 
     return regName, fieldNameList, bitOffsetList, bitWidthList, fieldDescList, enumTypeList
 
 
-class documentClass(object):
+class documentClass():
     def __init__(self, name):
         self.name = name
         self.memoryMapList = []
@@ -73,7 +82,7 @@ def addMemoryMap(self, memoryMap):
         self.memoryMapList.append(memoryMap)
 
 
-class memoryMapClass(object):
+class memoryMapClass():
     def __init__(self, name):
         self.name = name
         self.addressBlockList = []
@@ -82,7 +91,7 @@ def addAddressBlock(self, addressBlock):
         self.addressBlockList.append(addressBlock)
 
 
-class addressBlockClass(object):
+class addressBlockClass():
     def __init__(self, name, addrWidth, dataWidth):
         self.name = name
         self.addrWidth = addrWidth
@@ -101,7 +110,7 @@ def returnAsString(self):
         raise NotImplementedError("method returnAsString() is virutal and must be overridden.")
 
 
-class registerClass(object):
+class registerClass():
     def __init__(self, name, address, resetValue, size, access, desc, fieldNameList,
                  bitOffsetList, bitWidthList, fieldDescList, enumTypeList):
         assert isinstance(enumTypeList, list), 'enumTypeList is not a list'
@@ -118,7 +127,7 @@ def __init__(self, name, address, resetValue, size, access, desc, fieldNameList,
         self.enumTypeList = enumTypeList
 
 
-class enumTypeClassRegistry(object):
+class enumTypeClassRegistry():
     """ should perhaps be a singleton instead """
 
     def __init__(self):
@@ -134,7 +143,7 @@ def enumAllReadyExist(self, enum):
         return enum
 
 
-class enumTypeClass(object):
+class enumTypeClass():
     def __init__(self, name, bitWidth, keyList, valueList):
         self.name = name
         self.bitWidth = bitWidth
@@ -231,20 +240,95 @@ def returnRstSubTitle(self):
 
     def returnRstRegDesc(self, name, address, size, resetValue, desc, access):
         r = ""
-        r = r + name + "\n"
-        r = r + len(name) * '-' + "\n"
+        r += name + "\n"
+        r += len(name) * '-' + "\n"
         r += "\n"
-        r = r + ":Name:        " + str(name) + "\n"
-        r = r + ":Address:     " + hex(address) + "\n"
+        r += ":Name:        " + str(name) + "\n"
+        r += ":Address:     " + hex(address) + "\n"
         if resetValue:
             # display the resetvalue in hex notation in the full length of the register
-            r = r + ":Reset Value: {value:#0{size:d}x}\n".format(value=int(resetValue, 0), size=size // 4 + 2)
-        r = r + ":Access:      " + access + "\n"
-        r = r + ":Description: " + desc + "\n"
+            r += ":Reset Value: {value:#0{size:d}x}\n".format(value=int(resetValue, 0), size=size // 4 + 2)
+        r += ":Access:      " + access + "\n"
+        r += ":Description: " + desc + "\n"
         r += "\n"
         return r
 
 
+class mdAddressBlock(addressBlockClass):
+    """Generates a Markdown file from a IP-XACT register description"""
+
+    def __init__(self, name, addrWidth, dataWidth):
+        self.name = name
+        self.addrWidth = addrWidth
+        self.dataWidth = dataWidth
+        self.registerList = []
+        self.suffix = ".md"
+        self.mdFile = MdUtils(file_name="none",
+                              title="")
+
+    def returnEnumValueString(self, enumTypeObj):
+        if isinstance(enumTypeObj, enumTypeClass):
+            l = []
+            for i in range(len(enumTypeObj.keyList)):
+                l.append(enumTypeObj.keyList[i] + '=' + enumTypeObj.valueList[i])
+            s = ", ".join(l)
+        else:
+            s = ''
+        return s
+
+    def returnAsString(self):
+        r = ""
+        regNameList = [reg.name for reg in self.registerList]
+        regAddressList = [reg.address for reg in self.registerList]
+        regDescrList = [reg.desc for reg in self.registerList]
+
+        self.mdFile.new_header(level=1, title="Register description")
+        self.mdFile.new_header(level=2, title="Registers")
+
+
+        # summary
+        header=['Address', 'Register Name', 'Description']
+        rows = []
+        for i in range(len(regNameList)):
+            rows.extend(["{:#04x}".format(regAddressList[i]),
+                         f"[{regNameList[i]}](#{regNameList[i]})",
+                         str(regDescrList[i])])
+        self.mdFile.new_table(columns=len(header),
+                              rows=len(regNameList) + 1,  # header + data
+                              text=header + rows,
+                              text_align='left')
+
+        # all registers
+        headers=['Bits', 'Field name', 'Type', 'Description']
+        for reg in self.registerList:
+            self.returnMdRegDesc(reg.name, reg.address, reg.size, reg.resetValue, reg.desc, reg.access)
+            reg_table = []
+            for fieldIndex in reversed(list(range(len(reg.fieldNameList)))):
+                bits = "[" + str(reg.bitOffsetList[fieldIndex] + reg.bitWidthList[fieldIndex] - 1) + \
+                       ":" + str(reg.bitOffsetList[fieldIndex]) + "]"
+                reg_table.append(bits)
+                reg_table.append(reg.fieldNameList[fieldIndex])
+                reg_table.append(self.returnEnumValueString(reg.enumTypeList[fieldIndex]))
+                reg_table.append(reg.fieldDescList[fieldIndex])
+
+            self.mdFile.new_table(columns=len(headers),
+                                  rows=len(reg.fieldNameList) + 1,
+                                  text=headers + reg_table,
+                                  text_align='left')
+
+        return self.mdFile.file_data_text
+
+    def returnMdRegDesc(self, name, address, size, resetValue, desc, access):
+        self.mdFile.new_header(level=3, title=name)
+        self.mdFile.new_line("**Name** " + str(name))
+        self.mdFile.new_line("**Address** " + hex(address))
+        if resetValue:
+            # display the resetvalue in hex notation in the full length of the register
+            self.mdFile.new_line("**Reset Value** {value:#0{size:d}x}".format(value=int(resetValue, 0), size=size // 4 + 2))
+        self.mdFile.new_line("**Access** " + access)
+        self.mdFile.new_line("**Description** " + desc)
+
+
 class vhdlAddressBlock(addressBlockClass):
     """Generates a vhdl file from a IP-XACT register description"""
 
@@ -277,23 +361,26 @@ def returnPkgHeaderString(self):
         r += "use ieee.std_logic_1164.all;\n"
         r += "use ieee.numeric_std.all;\n"
         r += "\n"
-        r = r + "package " + self.name + "_vhd_pkg is\n"
+        r += "package " + self.name + "_vhd_pkg is\n"
         r += "\n"
-        r = r + "  constant addr_width : natural := " + str(self.addrWidth) + ";\n"
-        r = r + "  constant data_width : natural := " + str(self.dataWidth) + ";\n"
+        r += "  constant addr_width : natural := " + str(self.addrWidth) + ";\n"
+        r += "  constant data_width : natural := " + str(self.dataWidth) + ";\n"
 
         r += "\n\n"
 
-        r = r + self.returnRegFieldEnumTypeStrings(True)
+        r += self.returnRegFieldEnumTypeStrings(True)
 
         for reg in self.registerList:
-            r = r + "  constant " + reg.name + "_addr : natural := " + str(reg.address) + ";\n"
+            r += "  constant {name}_addr : natural := {address} ;  -- {address:#0{width}x}\n".format(name=reg.name,
+                                                                                                     address=reg.address,
+                                                                                                     width=math.ceil(self.addrWidth / 4) + 2)  # +2 for the '0x'
         r += "\n"
 
         for reg in self.registerList:
             if reg.resetValue:
-                r = r + "  constant " + reg.name + "_reset_value : std_ulogic_vector (data_width-1 downto 0)"
-                r = r + " := std_ulogic_vector( to_unsigned(" + str(int(reg.resetValue, 0)) + ", data_width ));\n"
+                r += "  constant {name}_reset_value : std_ulogic_vector (data_width-1 downto 0) := std_ulogic_vector(to_unsigned({value:d}, data_width));  -- {value:#0{width}x}\n".format(name=reg.name,
+                                                                                                                                                                                           value=int(reg.resetValue, 0),
+                                                                                                                                                                                           width=math.ceil((self.dataWidth / 4)) + 2)
 
         r += "\n\n"
 
@@ -303,17 +390,21 @@ def returnPkgHeaderString(self):
         r += self.returnRegistersInRecordTypeString()
         r += self.returnRegistersOutRecordTypeString()
 
-        r = r + "  function read_" + self.name + "(registers_i : " + self.name + "_in_record_type;\n"
-        r = r + "                        registers_o : " + self.name + "_out_record_type;\n"
-        r += "                        address   : std_ulogic_vector (addr_width-1 downto 0)\n"
-        r += "                        ) return std_ulogic_vector;\n\n"
+        t = "  function read_" + self.name + "(registers_i : " + self.name + "_in_record_type;\n"
+        r += t
+        indent = t.find('(') + 1
+        r += " " * indent + "registers_o : " + self.name + "_out_record_type;\n"
+        r += " " * indent + "address : std_ulogic_vector (addr_width-1 downto 0)\n"
+        r += " " * indent + ") return std_ulogic_vector;\n\n"
 
-        r = r + "  function write_" + self.name + "(value     : std_ulogic_vector (data_width-1 downto 0);\n"
-        r += "                         address   : std_ulogic_vector (addr_width-1 downto 0);\n"
-        r = r + "                         registers_o : " + self.name + "_out_record_type\n"
-        r = r + "                         ) return " + self.name + "_out_record_type;\n\n"
+        t = "  function write_" + self.name + "(value : std_ulogic_vector (data_width-1 downto 0);\n"
+        r += t
+        indent = t.find('(') + 1
+        r += " " * indent + "address : std_ulogic_vector (addr_width-1 downto 0);\n"
+        r += " " * indent + "registers_o : " + self.name + "_out_record_type\n"
+        r += " " * indent + ") return " + self.name + "_out_record_type;\n\n"
 
-        r = r + "  function reset_" + self.name + " return " + self.name + "_out_record_type;\n\n"
+        r += "  function reset_" + self.name + " return " + self.name + "_out_record_type;\n\n"
 
         r += "end;\n"
 
@@ -326,15 +417,15 @@ def returnRegFieldEnumTypeStrings(self, prototype):
                 if isinstance(enum, enumTypeClass) and not enum.allReadyExist:
                     if prototype:
                         s = ",".join(enum.keyList)
-                        r = r + "  type " + enum.name + "_enum is (" + s + ");\n\n"
+                        r += "  type " + enum.name + "_enum is (" + s + ");\n\n"
 
-                    r = r + "  function " + enum.name + \
+                    r += "  function " + enum.name + \
                         "_enum_to_sulv(v: " + enum.name + "_enum ) return std_ulogic_vector"
                     if prototype:
                         r += ";\n\n"
                     else:
                         r += " is\n"
-                        r = r + "    variable r : std_ulogic_vector (" + str(enum.bitWidth) + "-1 downto 0);\n"
+                        r += "    variable r : std_ulogic_vector (" + str(enum.bitWidth) + "-1 downto 0);\n"
                         r += "  begin\n"
                         r += "       case v is\n"
                         for i in range(len(enum.keyList)):
@@ -347,7 +438,7 @@ def returnRegFieldEnumTypeStrings(self, prototype):
                         r += "    return r;\n"
                         r += "  end function;\n\n"
 
-                    r = r + "  function sulv_to_" + enum.name + \
+                    r += "  function sulv_to_" + enum.name + \
                         "_enum(v: std_ulogic_vector (" + str(enum.bitWidth) + "-1 downto 0)) return " + \
                         enum.name + "_enum"
                     if prototype:
@@ -361,7 +452,7 @@ def returnRegFieldEnumTypeStrings(self, prototype):
                             r += '         when "{value_int:0{bitwidth}b}" => r:={key};\n'.format(key=enum.keyList[i],
                                                                                                   value_int=int(enum.valueList[i]),
                                                                                                   bitwidth=int(enum.bitWidth))
-                        r = r + '         when others => r:=' + enum.keyList[0] + '; -- error \n'
+                        r += '         when others => r:=' + enum.keyList[0] + '; -- error \n'
                         r += "       end case;\n"
                         r += "    return r;\n"
                         r += "  end function;\n\n"
@@ -370,47 +461,51 @@ def returnRegFieldEnumTypeStrings(self, prototype):
 
     def returnRegRecordTypeString(self, reg):
         r = ''
-        r = r + "  type " + reg.name + "_record_type is record\n"
+        r += "  type " + reg.name + "_record_type is record\n"
         for i in reversed(list(range(len(reg.fieldNameList)))):
             bits = "[" + str(reg.bitOffsetList[i] + reg.bitWidthList[i] - 1) + ":" + str(reg.bitOffsetList[i]) + "]"
             bit = "[" + str(reg.bitOffsetList[i]) + "]"
             if isinstance(reg.enumTypeList[i], enumTypeClass):
                 if not reg.enumTypeList[i].allReadyExist:
-                    r = r + "    " + reg.fieldNameList[i] + " : " + \
+                    r += "    " + reg.fieldNameList[i] + " : " + \
                         reg.enumTypeList[i].name + "_enum; -- " + bits + "\n"
                 else:
-                    r = r + "    " + reg.fieldNameList[i] + " : " + \
+                    r += "    " + reg.fieldNameList[i] + " : " + \
                         reg.enumTypeList[i].enumName + "_enum; -- " + bits + "\n"
             else:
                 if reg.bitWidthList[i] == 1:  # single bit
-                    r = r + "    " + reg.fieldNameList[i] + " : std_ulogic; -- " + bit + "\n"
+                    r += "    " + reg.fieldNameList[i] + " : std_ulogic; -- " + bit + "\n"
                 else:  # vector
-                    r = r + "    " + reg.fieldNameList[i] + " : std_ulogic_vector(" + str(reg.bitWidthList[i] - 1) + \
+                    r += "    " + reg.fieldNameList[i] + " : std_ulogic_vector(" + str(reg.bitWidthList[i] - 1) + \
                         " downto 0); -- " + bits + "\n"
         r += "  end record;\n\n"
         return r
 
     def returnRegistersInRecordTypeString(self):
         r = ""
-        r = r + "  type " + self.name + "_in_record_type is record\n"
+        r += "  type " + self.name + "_in_record_type is record\n"
         for reg in self.registerList:
             if reg.access == "read-only":
-                r = r + '    ' + reg.name + ' : ' + reg.name + "_record_type; -- addr " + str(int(reg.address)) + "\n"
+                r += "    {name} : {name}_record_type; -- addr {addr:#0{width}x}\n".format(name=reg.name,
+                                                                                           addr=reg.address,
+                                                                                           width=math.ceil(self.addrWidth / 4) + 2)  # +2 for the '0x'
         r += "  end record;\n\n"
         return r
 
     def returnRegistersOutRecordTypeString(self):
         r = ""
-        r = r + "  type " + self.name + "_out_record_type is record\n"
+        r += "  type " + self.name + "_out_record_type is record\n"
         for reg in self.registerList:
             if reg.access != "read-only":
-                r = r + '    ' + reg.name + ' : ' + reg.name + "_record_type; -- addr " + str(int(reg.address)) + "\n"
+                r += "    {name} : {name}_record_type; -- addr {addr:#0{width}x}\n".format(name=reg.name,
+                                                                                           addr=reg.address,
+                                                                                           width=math.ceil(self.addrWidth / 4) + 2)  # +2 for the '0x'
         r += "  end record;\n\n"
         return r
 
     def returnRecToSulvFunctionString(self, reg):
         r = ""
-        r = r + "  function " + reg.name + \
+        r += "  function " + reg.name + \
             "_record_type_to_sulv (v : " + reg.name + "_record_type) return std_ulogic_vector is\n"
         r += "    variable r : std_ulogic_vector (data_width-1 downto 0);\n"
         r += "  begin\n"
@@ -420,41 +515,41 @@ def returnRecToSulvFunctionString(self, reg):
             bit = str(reg.bitOffsetList[i])
             if isinstance(reg.enumTypeList[i], enumTypeClass):
                 if not reg.enumTypeList[i].allReadyExist:
-                    r = r + "    r(" + bits + ") := " + \
+                    r += "    r(" + bits + ") := " + \
                         reg.enumTypeList[i].name + "_enum_to_sulv(v." + reg.fieldNameList[i] + ");\n"
                 else:
-                    r = r + "    r(" + bits + ") := " + \
+                    r += "    r(" + bits + ") := " + \
                         reg.enumTypeList[i].enumName + "_enum_to_sulv(v." + reg.fieldNameList[i] + ");\n"
             else:
                 if reg.bitWidthList[i] == 1:  # single bit
-                    r = r + "    r(" + bit + ") := v." + reg.fieldNameList[i] + ";\n"
+                    r += "    r(" + bit + ") := v." + reg.fieldNameList[i] + ";\n"
                 else:  # vector
-                    r = r + "    r(" + bits + ") := v." + reg.fieldNameList[i] + ";\n"
+                    r += "    r(" + bits + ") := v." + reg.fieldNameList[i] + ";\n"
         r += "    return r;\n"
         r += "  end function;\n\n"
         return r
 
     def returnSulvToRecFunctionString(self, reg):
         r = ""
-        r = r + "  function sulv_to_" + reg.name + \
+        r += "  function sulv_to_" + reg.name + \
             "_record_type (v : std_ulogic_vector) return " + reg.name + "_record_type is\n"
-        r = r + "    variable r : " + reg.name + "_record_type;\n"
+        r += "    variable r : " + reg.name + "_record_type;\n"
         r += "  begin\n"
         for i in reversed(list(range(len(reg.fieldNameList)))):
             bits = str(reg.bitOffsetList[i] + reg.bitWidthList[i] - 1) + " downto " + str(reg.bitOffsetList[i])
             bit = str(reg.bitOffsetList[i])
             if isinstance(reg.enumTypeList[i], enumTypeClass):
                 if not reg.enumTypeList[i].allReadyExist:
-                    r = r + "    r." + reg.fieldNameList[i] + " := sulv_to_" + \
+                    r += "    r." + reg.fieldNameList[i] + " := sulv_to_" + \
                         reg.enumTypeList[i].name + "_enum(v(" + bits + "));\n"
                 else:
-                    r = r + "    r." + reg.fieldNameList[i] + " := sulv_to_" + \
+                    r += "    r." + reg.fieldNameList[i] + " := sulv_to_" + \
                         reg.enumTypeList[i].enumName + "_enum(v(" + bits + "));\n"
             else:
                 if reg.bitWidthList[i] == 1:  # single bit
-                    r = r + "    r." + reg.fieldNameList[i] + " := v(" + bit + ");\n"
+                    r += "    r." + reg.fieldNameList[i] + " := v(" + bit + ");\n"
                 else:
-                    r = r + "    r." + reg.fieldNameList[i] + " := v(" + bits + ");\n"
+                    r += "    r." + reg.fieldNameList[i] + " := v(" + bits + ");\n"
         r += "    return r;\n"
         r += "  end function;\n\n"
 
@@ -462,21 +557,23 @@ def returnSulvToRecFunctionString(self, reg):
 
     def returnReadFunctionString(self):
         r = ""
-        r = r + "  function read_" + self.name + "(registers_i : " + self.name + "_in_record_type;\n"
-        r = r + "                                 registers_o : " + self.name + "_out_record_type;\n"
-        r += "                                 address   : std_ulogic_vector (addr_width-1 downto 0)\n"
-        r += "                                 ) return std_ulogic_vector is\n"
+        t = "  function read_" + self.name + "(registers_i : " + self.name + "_in_record_type;\n"
+        indent = t.find('(') + 1
+        r += t
+        r += " " * indent + "registers_o : " + self.name + "_out_record_type;\n"
+        r += " " * indent + "address : std_ulogic_vector (addr_width-1 downto 0)\n"
+        r += " " * indent + ") return std_ulogic_vector is\n"
         r += "    variable r : std_ulogic_vector (data_width-1 downto 0);\n"
         r += "  begin\n"
         r += "    case to_integer(unsigned(address)) is\n"
         for reg in self.registerList:
             if reg.access == "read-only":
-                r = r + "      when " + reg.name + "_addr => r:= " + reg.name + \
-                    "_record_type_to_sulv(registers_i." + reg.name + ");\n"
+                r += "      when " + reg.name + "_addr => r:= " + reg.name + \
+                     "_record_type_to_sulv(registers_i." + reg.name + ");\n"
             else:
-                r = r + "      when " + reg.name + "_addr => r:= " + reg.name + \
-                    "_record_type_to_sulv(registers_o." + reg.name + ");\n"
-        r += "      when others    => r := (others => '0');\n"
+                r += "      when " + reg.name + "_addr => r:= " + reg.name + \
+                     "_record_type_to_sulv(registers_o." + reg.name + ");\n"
+        r += "      when others => r := (others => '0');\n"
         r += "    end case;\n"
         r += "    return r;\n"
         r += "  end function;\n\n"
@@ -484,19 +581,21 @@ def returnReadFunctionString(self):
 
     def returnWriteFunctionString(self):
         r = ""
-        r = r + "  function write_" + self.name + "(value     : std_ulogic_vector (data_width-1 downto 0);\n"
-        r += "                               address   : std_ulogic_vector (addr_width-1 downto 0);\n"
-        r = r + "                               registers_o : " + self.name + "_out_record_type\n"
-        r = r + "                               ) return " + self.name + "_out_record_type is\n"
-        r = r + "    variable r : " + self.name + "_out_record_type;\n"
+        t = "  function write_" + self.name + "(value : std_ulogic_vector (data_width-1 downto 0);\n"
+        r += t
+        indent = t.find('(') + 1
+        r += " " * indent + "address : std_ulogic_vector (addr_width-1 downto 0);\n"
+        r += " " * indent + "registers_o : " + self.name + "_out_record_type\n"
+        r += " " * indent + ") return " + self.name + "_out_record_type is\n"
+        r += "    variable r : " + self.name + "_out_record_type;\n"
         r += "  begin\n"
         r += "    r := registers_o;\n"
         r += "    case to_integer(unsigned(address)) is\n"
         for reg in self.registerList:
             if reg.access != "read-only":
-                r = r + "         when " + reg.name + "_addr => r." + reg.name + \
-                    " := sulv_to_" + reg.name + "_record_type(value);\n"
-        r += "      when others    => null;\n"
+                r += "         when " + reg.name + "_addr => r." + reg.name + \
+                     " := sulv_to_" + reg.name + "_record_type(value);\n"
+        r += "      when others => null;\n"
         r += "    end case;\n"
         r += "    return r;\n"
         r += "  end function;\n\n"
@@ -504,13 +603,13 @@ def returnWriteFunctionString(self):
 
     def returnResetFunctionString(self):
         r = ""
-        r = r + "  function reset_" + self.name + " return " + self.name + "_out_record_type is\n"
-        r = r + "    variable r : " + self.name + "_out_record_type;\n"
+        r += "  function reset_" + self.name + " return " + self.name + "_out_record_type is\n"
+        r += "    variable r : " + self.name + "_out_record_type;\n"
         r += "  begin\n"
         for reg in self.registerList:
             if reg.resetValue:
                 if reg.access != "read-only":
-                    r = r + "         r." + reg.name + " := sulv_to_" + \
+                    r += "         r." + reg.name + " := sulv_to_" + \
                         reg.name + "_record_type(" + reg.name + "_reset_value);\n"
         r += "    return r;\n"
         r += "  end function;\n\n"
@@ -518,9 +617,9 @@ def returnResetFunctionString(self):
 
     def returnPkgBodyString(self):
         r = ""
-        r = r + "package body " + self.name + "_vhd_pkg is \n\n"
+        r += "package body " + self.name + "_vhd_pkg is \n\n"
 
-        r = r + self.returnRegFieldEnumTypeStrings(False)
+        r += self.returnRegFieldEnumTypeStrings(False)
 
         for reg in self.registerList:
             r += self.returnRecToSulvFunctionString(reg)
@@ -543,27 +642,27 @@ def __init__(self, name, addrWidth, dataWidth):
 
     def returnIncludeString(self):
         r = "\n"
-        r = r + "`define " + self.name + "_addr_width " + str(self.addrWidth) + "\n"
-        r = r + "`define " + self.name + "_data_width " + str(self.dataWidth) + "\n"
+        r += "`define " + self.name + "_addr_width " + str(self.addrWidth) + "\n"
+        r += "`define " + self.name + "_data_width " + str(self.dataWidth) + "\n"
         return r
 
     def returnSizeString(self):
         r = "\n"
-        r = r + "const int addr_width = " + str(self.addrWidth) + ";\n"
-        r = r + "const int data_width = " + str(self.dataWidth) + ";\n"
+        r += "const int addr_width = " + str(self.addrWidth) + ";\n"
+        r += "const int data_width = " + str(self.dataWidth) + ";\n"
         return r
 
     def returnAddressesString(self):
         r = "\n"
         for reg in self.registerList:
-            r = r + "const int " + reg.name + "_addr = " + str(reg.address) + ";\n"
+            r += "const int " + reg.name + "_addr = " + str(reg.address) + ";\n"
         r += "\n"
         return r
 
     def returnAddressListString(self):
         r = "\n"
         r = "//synopsys translate_off\n"
-        r = r + "const int " + self.name + "_regAddresses [" + str(len(self.registerList)) + "] = {"
+        r += "const int " + self.name + "_regAddresses [" + str(len(self.registerList)) + "] = {"
         l = []
         for reg in self.registerList:
             l.append("\n     " + reg.name + "_addr")
@@ -571,14 +670,14 @@ def returnAddressListString(self):
         r += ",".join(l)
         r += "};\n"
         r += "\n"
-        r = r + "const string " + self.name + "_regNames [" + str(len(self.registerList)) + "] = {"
+        r += "const string " + self.name + "_regNames [" + str(len(self.registerList)) + "] = {"
         l = []
         for reg in self.registerList:
             l.append('\n      "' + reg.name + '"')
         r += ",".join(l)
         r += "};\n"
 
-        r = r + "const reg " + self.name + "_regUnResetedAddresses [" + str(len(self.registerList)) + "] = {"
+        r += "const reg " + self.name + "_regUnResetedAddresses [" + str(len(self.registerList)) + "] = {"
         l = []
         for reg in self.registerList:
             if reg.resetValue:
@@ -600,14 +699,14 @@ def enumeratedType(self, prepend, fieldName, valueNames, values):
             name = valueNames[index]
             value = values[index]
             members.append(name + "=" + value)
-        r = "typedef enum { " + ",".join(members) + "} enum_" + fieldName + ";\n"
+        r += "typedef enum { " + ",".join(members) + "} enum_" + fieldName + ";\n"
         return r
 
     def returnResetValuesString(self):
         r = ""
         for reg in self.registerList:
             if reg.resetValue:
-                r = r + "const " + reg.name + "_struct_type " + reg.name + \
+                r += "const " + reg.name + "_struct_type " + reg.name + \
                     "_reset_value = " + str(int(reg.resetValue, 0)) + ";\n"
         r += "\n"
         return r
@@ -619,16 +718,16 @@ def returnStructString(self):
             for i in reversed(list(range(len(reg.fieldNameList)))):
                 bits = "bits [" + str(reg.bitOffsetList[i] + reg.bitWidthList[i] - 1) + \
                        ":" + str(reg.bitOffsetList[i]) + "]"
-                r = r + "   bit [" + str(reg.bitWidthList[i] - 1) + ":0] " + \
+                r += "   bit [" + str(reg.bitWidthList[i] - 1) + ":0] " + \
                     str(reg.fieldNameList[i]) + ";//" + bits + "\n"
-            r = r + "} " + reg.name + "_struct_type;\n\n"
+            r += "} " + reg.name + "_struct_type;\n\n"
         return r
 
     def returnRegistersStructString(self):
         r = "typedef struct packed {\n"
         for reg in self.registerList:
-            r = r + "   " + reg.name + "_struct_type " + reg.name + ";\n"
-        r = r + "} " + self.name + "_struct_type;\n\n"
+            r += "   " + reg.name + "_struct_type " + reg.name + ";\n"
+        r += "} " + self.name + "_struct_type;\n\n"
         return r
 
     def returnReadFunctionString(self):
@@ -636,7 +735,7 @@ def returnReadFunctionString(self):
         r += "      bit [31:0]  r;\n"
         r += "      case(address)\n"
         for reg in self.registerList:
-            r = r + "         " + reg.name + "_addr: r = registers." + reg.name + ";\n"
+            r += "         " + reg.name + "_addr: r = registers." + reg.name + ";\n"
         r += "        default: r =0;\n"
         r += "      endcase\n"
         r += "      return r;\n"
@@ -644,13 +743,15 @@ def returnReadFunctionString(self):
         return r
 
     def returnWriteFunctionString(self):
-        r = "function " + self.name + "_struct_type write_" + self.name + "(bit [31:0] data, int address, \n"
-        r = r + "                                        " + self.name + "_struct_type registers);\n"
-        r = r + "   " + self.name + "_struct_type r;\n"
-        r = r + "   r = registers;\n"
-        r = r + "   case(address)\n"
+        t = "function " + self.name + "_struct_type write_" + self.name + "(bit [31:0] data, int address, \n"
+        r = t
+        indent = r.find('(') + 1
+        r += " " * indent + self.name + "_struct_type registers);\n"
+        r += "   " + self.name + "_struct_type r;\n"
+        r += "   r = registers;\n"
+        r += "   case(address)\n"
         for reg in self.registerList:
-            r = r + "         " + reg.name + "_addr: r." + reg.name + "=data;\n"
+            r += "         " + reg.name + "_addr: r." + reg.name + "=data;\n"
         r += "   endcase // case address\n"
         r += "   return r;\n"
         r += "endfunction\n\n"
@@ -658,10 +759,10 @@ def returnWriteFunctionString(self):
 
     def returnResetFunctionString(self):
         r = "function " + self.name + "_struct_type reset_" + self.name + "();\n"
-        r = r + "   " + self.name + "_struct_type r;\n"
+        r += "   " + self.name + "_struct_type r;\n"
         for reg in self.registerList:
             if reg.resetValue:
-                r = r + "   r." + reg.name + "=" + reg.name + "_reset_value;\n"
+                r += "   r." + reg.name + "=" + reg.name + "_reset_value;\n"
         r += "   return r;\n"
         r += "endfunction\n"
         r += "\n"
@@ -674,7 +775,7 @@ def returnAsString(self):
         r += "// \n"
         r += "// Do not manually edit!\n"
         r += "// \n"        
-        r = r + "package " + self.name + "_sv_pkg;\n\n"
+        r += "package " + self.name + "_sv_pkg;\n\n"
         r += self.returnSizeString()
         r += self.returnAddressesString()
         r += self.returnAddressListString()
@@ -684,13 +785,14 @@ def returnAsString(self):
         r += self.returnReadFunctionString()
         r += self.returnWriteFunctionString()
         r += self.returnResetFunctionString()
-        r = r + "endpackage //" + self.name + "_sv_pkg\n"
+        r += "endpackage //" + self.name + "_sv_pkg\n"
         return r
 
 
-class ipxactParser(object):
-    def __init__(self, srcFile):
+class ipxactParser():
+    def __init__(self, srcFile, config):
         self.srcFile = srcFile
+        self.config = config
         self.enumTypeClassRegistry = enumTypeClassRegistry()
 
     def returnDocument(self):
@@ -710,10 +812,10 @@ def returnDocument(self):
             for addressBlock in addressBlockList:
                 addressBlockName = addressBlock.find(spiritString + "name").text
                 registerList = addressBlock.findall(spiritString + "register")
-                baseAddress = int(addressBlock.find(spiritString + "baseAddress").text)
-                nbrOfAddresses = int(addressBlock.find(spiritString + "range").text)  # TODO, this is wrong
+                baseAddress = int(addressBlock.find(spiritString + "baseAddress").text, 0)
+                nbrOfAddresses = int(addressBlock.find(spiritString + "range").text, 0)  # TODO, this is wrong
                 addrWidth = int(math.ceil((math.log(baseAddress + nbrOfAddresses, 2))))
-                dataWidth = int(addressBlock.find(spiritString + "width").text)
+                dataWidth = int(addressBlock.find(spiritString + "width").text, 0)
                 a = addressBlockClass(addressBlockName, addrWidth, dataWidth)
                 for registerElem in registerList:
                     regName = registerElem.find(spiritString + "name").text
@@ -722,10 +824,10 @@ def returnDocument(self):
                         resetValue = reset.find(spiritString + "value").text
                     else:
                         resetValue = None
-                    size = int(registerElem.find(spiritString + "size").text)
+                    size = int(registerElem.find(spiritString + "size").text, 0)
                     access = registerElem.find(spiritString + "access").text
                     desc = registerElem.find(spiritString + "description").text
-                    regAddress = baseAddress + int(registerElem.find(spiritString + "addressOffset").text)
+                    regAddress = baseAddress + int(registerElem.find(spiritString + "addressOffset").text, 0)
                     r = self.returnRegister(spiritString, registerElem, regAddress,
                                             resetValue, size, access, desc, dataWidth)
                     a.addRegister(r)
@@ -751,12 +853,18 @@ def returnRegister(self, spiritString, registerElem, regAddress, resetValue, siz
                 enumeratedValueList = enumeratedValuesElem.findall(spiritString + "enumeratedValue")
                 valuesNameList = [item.find(spiritString + "name").text for item in enumeratedValueList]
                 valuesList = [item.find(spiritString + "value").text for item in enumeratedValueList]
-                if len(valuesNameList) > 0 and int(bitWidth) > 1:
-                    # dont create enums of booleans
-                    # only decreases readability
-                    enum = enumTypeClass(fieldName, bitWidth, valuesNameList, valuesList)
-                    enum = self.enumTypeClassRegistry.enumAllReadyExist(enum)
-                    enumTypeList.append(enum)
+                if len(valuesNameList) > 0:
+                    if int(bitWidth) > 1:  # if the field of a enum is longer than 1 bit, always use enums
+                        enum = enumTypeClass(fieldName, bitWidth, valuesNameList, valuesList)
+                        enum = self.enumTypeClassRegistry.enumAllReadyExist(enum)
+                        enumTypeList.append(enum)
+                    else:  # bit field of 1 bit
+                        if self.config['global'].getboolean('onebitenum'):  # do create one bit enums
+                            enum = enumTypeClass(fieldName, bitWidth, valuesNameList, valuesList)
+                            enum = self.enumTypeClassRegistry.enumAllReadyExist(enum)
+                            enumTypeList.append(enum)
+                        else:  # dont create enums of booleans because this only decreases readability
+                            enumTypeList.append(None)
                 else:
                     enumTypeList.append(None)
             else:
@@ -770,14 +878,14 @@ def returnRegister(self, spiritString, registerElem, regAddress, resetValue, siz
             enumTypeList.append(None)
 
         (regName, fieldNameList, bitOffsetList, bitWidthList, fieldDescList, enumTypeList) = sortRegisterAndFillHoles(
-                regName, fieldNameList, bitOffsetList, bitWidthList, fieldDescList, enumTypeList)
+                regName, fieldNameList, bitOffsetList, bitWidthList, fieldDescList, enumTypeList, self.config['global'].getboolean('unusedholes'))
 
         reg = registerClass(regName, regAddress, resetValue, size, access, regDesc, fieldNameList,
                             bitOffsetList, bitWidthList, fieldDescList, enumTypeList)
         return reg
 
 
-class ipxact2otherGenerator(object):
+class ipxact2otherGenerator():
     def __init__(self, destDir, namingScheme="addressBlockName"):
         self.destDir = destDir
         self.namingScheme = namingScheme
@@ -788,7 +896,7 @@ def write(self, fileName, string):
 
         if not os.path.exists(os.path.dirname(_dest)):
             os.makedirs(os.path.dirname(_dest))
-            
+
         with open(_dest, "w") as f:
             f.write(string)
 
@@ -804,7 +912,7 @@ def generate(self, generatorClass, document):
                                        addressBlock.dataWidth)
                 block.setRegisterList(addressBlock.registerList)
                 s = block.returnAsString()
-                if (self.namingScheme == "addressBlockName"):
+                if self.namingScheme == "addressBlockName":
                     fileName = blockName + block.suffix
                 else:
                     fileName = docName + '_' + mapName + '_' + blockName + block.suffix
diff --git a/ipxact2systemverilog/validate.py b/ipxact2systemverilog/validate.py
index 12280d3..8cf7688 100644
--- a/ipxact2systemverilog/validate.py
+++ b/ipxact2systemverilog/validate.py
@@ -6,6 +6,7 @@
 schema_file = os.path.join(os.path.dirname(__file__), 'xml', 'component.xsd')
 schema = etree.XMLSchema(file=schema_file)
 
+
 def validate(xmlfilename):
     f = open(xmlfilename, 'r')
     doc = etree.parse(f)
@@ -13,5 +14,3 @@ def validate(xmlfilename):
     if not result:
         print(schema.error_log)
     return result
-
-
diff --git a/setup.py b/setup.py
index 18189fc..ff5d3dc 100644
--- a/setup.py
+++ b/setup.py
@@ -8,7 +8,7 @@ def readme():
 
 setup(name='ipxact2systemverilog',
       version='1.0.5',
-      description='Generate VHDL, SystemVerilog, html, rst, pdf from an IPXACT description',
+      description='Generate VHDL, SystemVerilog, html, rst, md, pdf from an IPXACT description',
       long_description=readme(),
       classifiers=[
         'Development Status :: 4 - Beta',
@@ -17,14 +17,14 @@ def readme():
         'Programming Language :: Python :: 3.6',
         'Topic :: Text Processing :: Linguistic',
       ],
-      keywords='ipxact2systemverilog ipxact2vhdl VHDL SystemVerilog html rst pdf IPXACT',
+      keywords='ipxact2systemverilog ipxact2vhdl VHDL SystemVerilog html rst md pdf IPXACT',
       url='https://github.com/oddball/ipxact2systemverilog',
       author='oddball',
       license='GPL',
       packages=['ipxact2systemverilog'],
       install_requires=[
-          'docutils', 'lxml', 'tabulate', 'future'
+          'docutils', 'lxml', 'tabulate', 'future', 'mdutils'
       ],
-      scripts=['bin/ipxact2rst', 'bin/ipxact2systemverilog', 'bin/ipxact2vhdl'],
+      scripts=['bin/ipxact2rst', 'bin/ipxact2md', 'bin/ipxact2systemverilog', 'bin/ipxact2vhdl'],
       include_package_data=True,
       zip_safe=False)


Test patch:
diff --git a/example/input/test.xml b/example/input/test.xml
index 8d4a1ed..5933ebd 100644
--- a/example/input/test.xml
+++ b/example/input/test.xml
@@ -199,11 +199,11 @@
         <spirit:register>
           <spirit:name>reg7</spirit:name>
           <spirit:description>write something useful for reg7</spirit:description>
-          <spirit:addressOffset>7</spirit:addressOffset>
+          <spirit:addressOffset>0x07</spirit:addressOffset>
           <spirit:size>32</spirit:size>
           <spirit:access>read-write</spirit:access>
           <spirit:reset>
-            <spirit:value>0</spirit:value>
+            <spirit:value>0x00000000</spirit:value>
           </spirit:reset>
           <spirit:field>
             <spirit:name>nibble0</spirit:name>