Repository: linien-org/linien (language: python)

Issue:
Deprecation warnings and failing tests
Some of the tests are currently failing, `test_approacher.py` and `test_root.py`, see the report below.

There are also a number of deprecation warnings.


```xml
<?xml version="1.0" encoding="utf-8"?><testsuites><testsuite errors="0" failures="2" hostname="DESKTOP-DBEB5CF" name="pytest" skipped="0" tests="22" time="507.206" timestamp="2021-12-09T13:57:01.991647"><testcase classname="tests.test_algorithm_selection" name="test_forced_algorithm_selection" time="0.008" /><testcase classname="tests.test_algorithm_selection" name="test_automatic_algorithm_selection" time="0.316" /><testcase classname="tests.test_approacher" name="test_approacher" time="0.454"><failure message="assert False">def test_approacher():
        def _get_signal(shift):
            return get_signal(
                parameters.ramp_amplitude.value, parameters.center.value, shift
            )
    
        for ref_shift in (-0.4, -0.2, 0.3):
            for target_shift in (-0.3, 0.6):
                print(f"----- ref_shift={ref_shift}, target_shift={target_shift} -----")
                parameters = Parameters()
                control = FakeControl(parameters)
    
                # approaching a line at the center is too easy
                # we generate a reference signal that is shifted in some direction
                # and then simulate that the user wants to approach a line that is not at
                # the center (this is done using get_lock_point)
                reference_signal = _get_signal(ref_shift)
    
                (
                    central_y,
                    target_slope_rising,
                    _,
                    rolled_reference_signal,
                    line_width,
                    peak_idxs,
                ) = get_lock_point(reference_signal, 0, len(reference_signal))
    
                """plt.plot(reference_signal)
                plt.plot(rolled_reference_signal)
                plt.show()"""
    
                assert abs(central_y - Y_SHIFT) &lt; 1
    
                approacher = Approacher(
                    control,
                    parameters,
                    rolled_reference_signal,
                    100,
                    central_y,
                    wait_time_between_current_corrections=0,
                )
    
                found = False
    
                for i in range(100):
                    shift = target_shift * (1 + (0.025 * np.random.randn()))
                    error_signal = _get_signal(shift)[:]
                    approacher.approach_line(error_signal)
    
                    if parameters.ramp_amplitude.value &lt;= 0.2:
                        found = True
                        break
    
&gt;               assert found
E               assert False

tests\test_approacher.py:98: AssertionError</failure></testcase><testcase classname="tests.test_common" name="test_determine_shift_by_correlation" time="0.014" /><testcase classname="tests.test_fast_autolock" name="test_autolock" time="0.130" /><testcase classname="tests.test_limit" name="test_limit" time="0.048" /><testcase classname="tests.test_modulate" name="test_modulate" time="84.959" /><testcase classname="tests.test_optimizer_engines" name="test_multi" time="0.293" /><testcase classname="tests.test_optimizer_engines" name="test_optimization" time="5.765" /><testcase classname="tests.test_optimizer_utils" name="test_get_max_slope" time="0.004" /><testcase classname="tests.test_optimizer_utils" name="test_iq" time="0.614" /><testcase classname="tests.test_pid" name="test_pid" time="1.986" /><testcase classname="tests.test_pid_transfer" name="test_pid_transfer" time="54.363" /><testcase classname="tests.test_robust_autolock" name="test_get_description" time="307.126" /><testcase classname="tests.test_robust_autolock" name="test_dynamic_delay" time="3.432" /><testcase classname="tests.test_robust_autolock" name="test_sum_diff_calculator" time="7.829" /><testcase classname="tests.test_robust_autolock" name="test_sum_diff_calculator2" time="6.719" /><testcase classname="tests.test_robust_autolock" name="test_compare_sum_diff_calculator_implementations" time="17.971" /><testcase classname="tests.test_robust_autolock" name="test_fpga_lock_position_finder" time="7.396" /><testcase classname="tests.test_robust_autolock" name="test_crop_spectra_to_same_view" time="0.016" /><testcase classname="tests.test_root" name="test_root" time="4.809"><failure message="assert 0 == 1">def test_root():
        def tb(root: LinienLogic, lock_target_position):
            print("lock target position", lock_target_position)
            sweep: SweepCSR = root.sweep
            pid: PID = root.pid
            autolock = root.autolock
            fast = autolock.fast
    
            yield fast.target_position.storage.eq(lock_target_position)
    
            yield sweep.step.storage.eq(1 &lt;&lt; sweep.step_shift)
            yield sweep.run.storage.eq(1)
    
            yield pid.input.eq(4096)
            yield pid.kp.storage.eq(4096)
            yield pid.ki.storage.eq(0)
            yield pid.reset.storage.eq(1)
    
            yield
    
            for iteration in range(2):
                print("iteration", iteration)
                ramp_sign = (-1, 1, -1)[iteration]
    
                sweep_out_at_beginning = yield sweep.y
    
                # start the ramp and check that PID doesn't operate
                for i in range(100 - sweep_out_at_beginning):
                    yield
                    sweep_out = yield sweep.y
                    pid_out = yield pid.pid_out
                    pid_running = yield pid.running
    
                    assert sweep_out == sweep_out_at_beginning + ramp_sign * i
                    assert pid_out == 0
                    assert pid_running == 0
    
                # now turn around the ramp and request lock
                yield sweep.sweep.turn.eq(1)
                yield autolock.request_lock.storage.eq(1)
                yield
                yield
    
                # check that lock isn't turned on yet
                for i in range(102 + lock_target_position):
                    yield
                    sweep_out = yield sweep.y
                    assert ramp_sign * sweep_out == 100 - i
                    pid_running = yield pid.running
                    assert pid_running == 0
                    pid_out = yield pid.pid_out
                    assert pid_out == 0
    
                if iteration == 0:
                    # check that after zero crossing, PID is turned on and ramp off
                    yield
                    pid_running = yield pid.running
                    assert pid_running == 1
    
                    yield
                    yield
    
                    sweep_out_at_begin_of_lock = yield sweep.y
                    assert sweep_out_at_begin_of_lock == 3 + lock_target_position
    
                    for i in range(100):
                        sweep_out = yield sweep.y
                        assert sweep_out == sweep_out_at_begin_of_lock
                        pid_out = yield pid.pid_out
                        assert pid_out &gt; 0
    
                    yield autolock.request_lock.storage.eq(0)
                    print("turn on ramp again")
                    yield
                    yield
                else:
                    # in the second iteration, we approached the zero crossing from
                    # the other side. In this case, we don't want to turn on the PID
                    for i in range(10):
                        yield
                        sweep_out = yield sweep.y
                        pid_running = yield pid.running
                        assert pid_running == 0
    
        dut = LinienLogic()
&gt;       run_simulation(dut, tb(dut, 0), vcd_name="root.vcd")

tests\test_root.py:93: 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 
..\..\..\miniconda3\envs\linien\lib\site-packages\migen\sim\core.py:414: in run_simulation
    s.run()
..\..\..\miniconda3\envs\linien\lib\site-packages\migen\sim\core.py:403: in run
    self._process_generators(cd)
..\..\..\miniconda3\envs\linien\lib\site-packages\migen\sim\core.py:357: in _process_generators
    request = generator.send(reply)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 

root = &lt;gateware.linien.LinienLogic object at 0x000001FB197C9C48&gt;
lock_target_position = 0

    def tb(root: LinienLogic, lock_target_position):
        print("lock target position", lock_target_position)
        sweep: SweepCSR = root.sweep
        pid: PID = root.pid
        autolock = root.autolock
        fast = autolock.fast
    
        yield fast.target_position.storage.eq(lock_target_position)
    
        yield sweep.step.storage.eq(1 &lt;&lt; sweep.step_shift)
        yield sweep.run.storage.eq(1)
    
        yield pid.input.eq(4096)
        yield pid.kp.storage.eq(4096)
        yield pid.ki.storage.eq(0)
        yield pid.reset.storage.eq(1)
    
        yield
    
        for iteration in range(2):
            print("iteration", iteration)
            ramp_sign = (-1, 1, -1)[iteration]
    
            sweep_out_at_beginning = yield sweep.y
    
            # start the ramp and check that PID doesn't operate
            for i in range(100 - sweep_out_at_beginning):
                yield
                sweep_out = yield sweep.y
                pid_out = yield pid.pid_out
                pid_running = yield pid.running
    
                assert sweep_out == sweep_out_at_beginning + ramp_sign * i
                assert pid_out == 0
                assert pid_running == 0
    
            # now turn around the ramp and request lock
            yield sweep.sweep.turn.eq(1)
            yield autolock.request_lock.storage.eq(1)
            yield
            yield
    
            # check that lock isn't turned on yet
            for i in range(102 + lock_target_position):
                yield
                sweep_out = yield sweep.y
                assert ramp_sign * sweep_out == 100 - i
                pid_running = yield pid.running
                assert pid_running == 0
                pid_out = yield pid.pid_out
                assert pid_out == 0
    
            if iteration == 0:
                # check that after zero crossing, PID is turned on and ramp off
                yield
                pid_running = yield pid.running
&gt;               assert pid_running == 1
E               assert 0 == 1

tests\test_root.py:65: AssertionError</failure></testcase><testcase classname="tests.test_sweep" name="test_sweep" time="0.359" /></testsuite></testsuites>
```


Discussion / hints:

Fix patch:
diff --git a/gateware/logic/delta_sigma.py b/gateware/logic/delta_sigma.py
index 61e9d20f..9a4bf226 100644
--- a/gateware/logic/delta_sigma.py
+++ b/gateware/logic/delta_sigma.py
@@ -81,4 +81,3 @@ def tb(dut, x, y):
         # plt.plot(y.ravel())
         plt.psd(np.array(y), detrend=plt.mlab.detrend_mean, NFFT=4096 * 2)
         plt.xscale("log")
-    plt.show()
diff --git a/requirements_dev.txt b/requirements_dev.txt
index 0e9aefc6..c2010e3c 100644
--- a/requirements_dev.txt
+++ b/requirements_dev.txt
@@ -8,4 +8,5 @@ pre-commit
 matplotlib
 migen
 pytest
-git+https://github.com/m-labs/misoc
\ No newline at end of file
+git+https://github.com/m-labs/misoc
+pytest-plt
\ No newline at end of file


Test patch:
diff --git a/pytest.ini b/pytest.ini
new file mode 100644
index 00000000..7db3b0d6
--- /dev/null
+++ b/pytest.ini
@@ -0,0 +1,7 @@
+[pytest]
+plt_dirname = tests/plots
+
+# don't complain about plt_dirname
+filterwarnings = ignore::pytest.PytestConfigWarning 
+
+markers = slow : marks tests as slow (deselect with '-m "not slow"')
diff --git a/tests/test_algorithm_selection.py b/tests/test_algorithm_selection.py
index efe3df0e..4379d4c0 100644
--- a/tests/test_algorithm_selection.py
+++ b/tests/test_algorithm_selection.py
@@ -41,7 +41,10 @@ def continue_acquisition(self):
 
     def exposed_write_data(self):
         print(
-            f"write: center={self.parameters.center.value} amp={self.parameters.ramp_amplitude.value}"
+            f"""
+            write: center={self.parameters.center.value}\n
+            amp={self.parameters.ramp_amplitude.value}
+            """
         )
 
     def exposed_start_lock(self):
diff --git a/tests/test_approacher.py b/tests/test_approacher.py
index 6d6489e4..efe53c9f 100644
--- a/tests/test_approacher.py
+++ b/tests/test_approacher.py
@@ -42,7 +42,7 @@ def exposed_write_data(self):
         )
 
 
-def test_approacher():
+def test_approacher(plt):
     def _get_signal(shift):
         return get_signal(
             parameters.ramp_amplitude.value, parameters.center.value, shift
@@ -69,9 +69,8 @@ def _get_signal(shift):
                 peak_idxs,
             ) = get_lock_point(reference_signal, 0, len(reference_signal))
 
-            """plt.plot(reference_signal)
+            plt.plot(reference_signal)
             plt.plot(rolled_reference_signal)
-            plt.show()"""
 
             assert abs(central_y - Y_SHIFT) < 1
 
diff --git a/tests/test_limit.py b/tests/test_limit.py
index 6dee5bea..c0a02ae7 100644
--- a/tests/test_limit.py
+++ b/tests/test_limit.py
@@ -1,7 +1,11 @@
+from pathlib import Path
+
 from migen import run_simulation
 
 from gateware.logic.limit import Limit
 
+VCD_DIR = Path(__file__).parent / "vcd"
+
 
 def test_limit():
     def tb(limit, n):
@@ -36,4 +40,4 @@ def tb(limit, n):
 
     dut = Limit(16)
     n = 1 << 6
-    run_simulation(dut, tb(dut, n), vcd_name="limit.vcd")
+    run_simulation(dut, tb(dut, n), vcd_name=VCD_DIR / "limit.vcd")
diff --git a/tests/test_modulate.py b/tests/test_modulate.py
index 93f53928..7ec46f4e 100644
--- a/tests/test_modulate.py
+++ b/tests/test_modulate.py
@@ -1,9 +1,13 @@
-import matplotlib.pyplot as plt
+from pathlib import Path
+
 import numpy as np
+import pytest
 from migen import Module, Signal, run_simulation
 
 from gateware.logic.modulate import Demodulate, Modulate
 
+VCD_DIR = Path(__file__).parent / "vcd"
+
 
 def moving_average(a, n):
     ret = np.cumsum(a, dtype=float)
@@ -25,7 +29,8 @@ def block_average(a, n):
 factor = 5
 
 
-def test_modulate():
+@pytest.mark.slow
+def test_modulate(plt):
     width = 16
     data = []
     phase = []
@@ -70,7 +75,7 @@ def __init__(self):
             ]
 
     dut = Combined()
-    run_simulation(dut, tb(dut), vcd_name="modulate.vcd")
+    run_simulation(dut, tb(dut), vcd_name=VCD_DIR / "modulate.vcd")
 
     """        """
     plt.plot(data, label="y")
@@ -84,7 +89,6 @@ def __init__(self):
     plt.plot(np.sqrt(averaged1 ** 2 + averaged2 ** 2), label="averaged+averaged")
 
     plt.legend()
-    plt.show()
 
 
 if __name__ == "__main__":
diff --git a/tests/test_pid.py b/tests/test_pid.py
index 2f1c9c11..604e4b55 100644
--- a/tests/test_pid.py
+++ b/tests/test_pid.py
@@ -1,11 +1,14 @@
+from pathlib import Path
+
 import numpy as np
-from matplotlib import pyplot as plt
 from migen import run_simulation
 
 from gateware.logic.pid import PID
 
+VCD_DIR = Path(__file__).parent / "vcd"
+
 
-def test_pid():
+def test_pid(plt):
     def pid_testbench(pid):
         def test_not_running():
             input_ = 1000
@@ -29,7 +32,7 @@ def test_p():
             yield pid.ki.storage.eq(0)
             yield pid.kd.storage.eq(0)
 
-            for i in range(10):
+            for _ in range(10):
                 yield
 
             out = yield pid.pid_out
@@ -109,11 +112,10 @@ def test_d():
                     out = yield pid.pid_out
                     y.append(out)
 
-                # plt.plot(x)
-                # plt.plot(y)
+                plt.plot(x)
+                plt.plot(y)
 
                 ys.append(y)
-            # plt.show()
 
             assert np.all(np.abs(np.array(ys[0][10:]) - np.array(ys[1][10:])) <= 1)
 
@@ -124,7 +126,7 @@ def test_d():
         yield from test_d()
 
     pid = PID(width=25)
-    run_simulation(pid, pid_testbench(pid), vcd_name="pid.vcd")
+    run_simulation(pid, pid_testbench(pid), vcd_name=VCD_DIR / "pid.vcd")
 
 
 if __name__ == "__main__":
diff --git a/tests/test_pid_transfer.py b/tests/test_pid_transfer.py
index 94404bfb..b11faa46 100644
--- a/tests/test_pid_transfer.py
+++ b/tests/test_pid_transfer.py
@@ -1,11 +1,16 @@
+from pathlib import Path
+
 import numpy as np
-from matplotlib import pyplot as plt
+import pytest
 from migen import run_simulation
 
 from gateware.logic.pid import PID
 
+VCD_DIR = Path(__file__).parent / "vcd"
+
 
-def test_pid_transfer():
+@pytest.mark.slow
+def test_pid_transfer(plt):
     def pid_testbench(pid):
         np.random.seed(299792458)
         amplitude = 0.01
@@ -91,10 +96,9 @@ def do_test(p=0, i=0, d=0):
         plt.legend(loc=(1.04, 0))
         plt.grid()
         plt.tight_layout()
-        plt.show()
 
     pid = PID(width=25)
-    run_simulation(pid, pid_testbench(pid), vcd_name="pid.vcd")
+    run_simulation(pid, pid_testbench(pid), vcd_name=VCD_DIR / "pid.vcd")
 
 
 if __name__ == "__main__":
diff --git a/tests/test_robust_autolock.py b/tests/test_robust_autolock.py
index 2beb3ecb..3b976671 100644
--- a/tests/test_robust_autolock.py
+++ b/tests/test_robust_autolock.py
@@ -1,5 +1,7 @@
+from pathlib import Path
+
 import numpy as np
-from matplotlib import pyplot as plt
+import pytest
 from migen import run_simulation
 
 from gateware.logic.autolock import (
@@ -19,6 +21,7 @@
     sum_up_spectrum,
 )
 
+VCD_DIR = Path(__file__).parent / "vcd"
 FPGA_DELAY_SUMDIFF_CALCULATOR = 2
 
 
@@ -64,7 +67,8 @@ def add_jitter(spectrum, level=None, exact_value=None):
     return np.roll(spectrum, shift)
 
 
-def test_get_description(debug=False):
+@pytest.mark.slow
+def test_get_description(plt, debug=True):
     for sign_spectrum_multiplicator in (1, -1):
         for spectrum_generator in (pfd_spectrum, atomic_spectrum):
             spectrum, target_idxs = spectrum_generator(0)
@@ -72,7 +76,6 @@ def test_get_description(debug=False):
 
             if debug:
                 plt.plot(spectrum)
-                plt.show()
 
             jitters = [
                 0 if i == 0 else int(round(np.random.randn() * 50)) for i in range(10)
@@ -148,7 +151,6 @@ def test_get_description(debug=False):
                 )
 
                 plt.legend()
-                plt.show()
 
 
 def test_dynamic_delay():
@@ -168,7 +170,9 @@ def tb(dut):
         assert out == 1
 
     dut = DynamicDelay(14 + 14, max_delay=8191)
-    run_simulation(dut, tb(dut), vcd_name="experimental_autolock_dynamic_delay.vcd")
+    run_simulation(
+        dut, tb(dut), vcd_name=VCD_DIR / "experimental_autolock_dynamic_delay.vcd"
+    )
 
 
 def test_sum_diff_calculator():
@@ -211,7 +215,7 @@ def tb(dut):
 
     dut = SumDiffCalculator(14, 8192)
     run_simulation(
-        dut, tb(dut), vcd_name="experimental_autolock_sum_diff_calculator.vcd"
+        dut, tb(dut), vcd_name=VCD_DIR / "experimental_autolock_sum_diff_calculator.vcd"
     )
 
 
@@ -234,7 +238,7 @@ def tb(dut):
 
     dut = SumDiffCalculator(14, 8192)
     run_simulation(
-        dut, tb(dut), vcd_name="experimental_autolock_sum_diff_calculator.vcd"
+        dut, tb(dut), vcd_name=VCD_DIR / "experimental_autolock_sum_diff_calculator.vcd"
     )
 
     summed = sum_up_spectrum(spectrum)
@@ -246,7 +250,8 @@ def tb(dut):
     assert out_fpga[1:] == summed_xscaled[:-1]
 
 
-def test_compare_sum_diff_calculator_implementations(debug=False):
+@pytest.mark.slow
+def test_compare_sum_diff_calculator_implementations(plt, debug=True):
     for iteration in (0, 1):
         if iteration == 1:
             spectrum, target_idxs = atomic_spectrum(0)
@@ -280,7 +285,9 @@ def tb(dut):
 
         dut = RobustAutolock()
         run_simulation(
-            dut, tb(dut), vcd_name="experimental_autolock_fpga_lock_position_finder.vcd"
+            dut,
+            tb(dut),
+            vcd_name=VCD_DIR / "experimental_autolock_fpga_lock_position_finder.vcd",
         )
 
         if debug:
@@ -292,7 +299,6 @@ def tb(dut):
                 label="FPGA calculation",
             )
             plt.legend()
-            plt.show()
 
             plt.plot(
                 summed_xscaled[:-FPGA_DELAY_SUMDIFF_CALCULATOR],
@@ -303,7 +309,6 @@ def tb(dut):
                 label="FPGA calculation",
             )
             plt.legend()
-            plt.show()
 
         assert (
             summed[:-FPGA_DELAY_SUMDIFF_CALCULATOR]
@@ -400,11 +405,13 @@ def tb(dut: RobustAutolock):
 
     dut = RobustAutolock()
     run_simulation(
-        dut, tb(dut), vcd_name="experimental_autolock_fpga_lock_position_finder.vcd"
+        dut,
+        tb(dut),
+        vcd_name=VCD_DIR / "experimental_autolock_fpga_lock_position_finder.vcd",
     )
 
 
-def test_crop_spectra_to_same_view():
+def test_crop_spectra_to_same_view(plt):
     spectra_to_test = (
         [np.roll(atomic_spectrum(0)[0], -i * 10) for i in range(10)],
         [np.roll(atomic_spectrum(0)[0], i * 10) for i in range(10)],
@@ -423,8 +430,7 @@ def test_crop_spectra_to_same_view():
         for cropped_spectrum in cropped_spectra:
             assert np.all(cropped_spectrum == cropped_spectra[0])
 
-            # plt.plot(cropped_spectrum)
-        # plt.show()
+            plt.plot(cropped_spectrum)
 
 
 if __name__ == "__main__":
@@ -434,4 +440,4 @@ def test_crop_spectra_to_same_view():
     test_sum_diff_calculator()
     test_sum_diff_calculator2()
     test_fpga_lock_position_finder()
-    test_get_description(debug=False)
+    test_get_description(debug=True)
diff --git a/tests/test_root.py b/tests/test_root.py
index b6e69e61..b939a288 100644
--- a/tests/test_root.py
+++ b/tests/test_root.py
@@ -1,9 +1,13 @@
+from pathlib import Path
+
 from migen import run_simulation
 
 from gateware.linien import LinienLogic
 from gateware.logic.pid import PID
 from gateware.logic.sweep import SweepCSR
 
+VCD_DIR = Path(__file__).parent / "vcd"
+
 
 def test_root():
     def tb(root: LinienLogic, lock_target_position):
@@ -90,11 +94,11 @@ def tb(root: LinienLogic, lock_target_position):
                     assert pid_running == 0
 
     dut = LinienLogic()
-    run_simulation(dut, tb(dut, 0), vcd_name="root.vcd")
+    run_simulation(dut, tb(dut, 0), vcd_name=VCD_DIR / "root_target0.vcd")
     dut = LinienLogic()
-    run_simulation(dut, tb(dut, -40), vcd_name="root.vcd")
+    run_simulation(dut, tb(dut, -40), vcd_name=VCD_DIR / "root_target-40.vcd")
     dut = LinienLogic()
-    run_simulation(dut, tb(dut, 51), vcd_name="root.vcd")
+    run_simulation(dut, tb(dut, 51), vcd_name=VCD_DIR / "root_target_51.vcd")
 
 
 if __name__ == "__main__":
diff --git a/tests/test_sweep.py b/tests/test_sweep.py
index 6c247728..150ca548 100644
--- a/tests/test_sweep.py
+++ b/tests/test_sweep.py
@@ -1,10 +1,13 @@
-import matplotlib.pyplot as plt
+from pathlib import Path
+
 from migen import run_simulation
 
 from gateware.logic.sweep import SweepCSR
 
+VCD_DIR = Path(__file__).parent / "vcd"
+
 
-def test_sweep():
+def test_sweep(plt):
     # s = Sweep(16)
     # from migen.fhdl import verilog
     # print(verilog.convert(s, ios=set()))
@@ -29,13 +32,11 @@ def tb(sweep, out, n):
     out = []
     trig = []
     dut = SweepCSR(width=16)
-    run_simulation(dut, tb(dut, out, n), vcd_name="sweep.vcd")
+    run_simulation(dut, tb(dut, out, n), vcd_name=VCD_DIR / "sweep.vcd")
 
-    if False:
-        plt.plot(out, label="ramp output")
-        plt.plot([v * max(out) for v in trig], label="trigger_signal")
-        plt.legend()
-        plt.show()
+    plt.plot(out, label="ramp output")
+    plt.plot([v * max(out) for v in trig], label=VCD_DIR / "trigger_signal")
+    plt.legend()
 
     assert out[66] == -1024
     assert trig[66] == 1
diff --git a/tests/vcd/.gitignore b/tests/vcd/.gitignore
new file mode 100644
index 00000000..86b5730b
--- /dev/null
+++ b/tests/vcd/.gitignore
@@ -0,0 +1,4 @@
+# Ignore all other files in this folder since they are only used for storing files for
+# testing.
+*
+!.gitignore
\ No newline at end of file