SlowGuess/NeurIPS_2023_OCR huggingface dataset:
All columns, except for #Partitions, are predetermined and unalterable in the benchmark. The #Partitions, however, constitutes a crucial hyperparameter, which is determined heuristically based on the heights and widths of the macros and the canvas. To elaborate, in the case where multiple macros of identical size, e.g.,  $30 \times 20$ , are present on a given chip, with the canvas size  $9000 \times 9000$ , the value of #Partitions would be set to 300, thereby resulting in a grid size of  $30 \times 30$  for each grid. The influence of #Partitions is discussed in Table 7 of Appendix B.2.
B.1 Post local search
As the genotype-phenotype mapping in the objective evaluation of WireMask-BBO is performed greedily, guided by wire mask, we propose a post local search procedure to modify the final generated macro placement, which will probably bring further improvement. For a final generated macro placement, the positions of all macros are sequentially adjusted; the position of each macro is adjusted to the best grid (ties are broken randomly) which reduces the current HPWL value most. Note that when adjusting the position of one macro, all the other macros are fixed, which is different from that in the objective evaluation of WireMask-BBO, which is only based on the positions of those macros that have been adjusted. We have applied this post local search procedure to the final placements generated by SP-SA [33], MaskPlace [26] and WireMask-BBO. The macros are adjusted sequentially according to the order employed by WireMask-BBO (i.e., lines 1–2 in Algorithm 1); this process is performed twice. Note that the adjustment order of macros can be arbitrary when applying this post local search process. The results in Table 6 show that the final placements can be further improved, which is expected because both MaskPlace and WireMask involve (probabilistically) greedy incremental placement guided by wire mask.
<sup>3</sup>Note that for the bigblue2 chip, which has over 20,000 macros and 30,000 macro-related hyper-edges, a single objective evaluation by step-by-step placement costs more than an hour. Thus, we do not include this chip in our experiments as [26], and its #Partitions is denoted as /.
Table 6: HPWL values  $(\times 10^{5})$  obtained by post local search on existing placements. The last column, Avg. Imp., denotes the average improvement ratio across seven chips, obtained by comparing the HPWL values before and after post local search.
benchmark	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4	Avg. Imp.
SP-SA [33]	18.84 ± 4.62	117.36 ± 8.73	115.48 ± 7.56	120.03 ± 4.25	5.12 ± 1.43	164.70 ± 19.55	25.49 ± 2.73	25.62%
after_local_search	12.52 ± 1.59	97.22 ± 8.34	104.46 ± 7.73	102.17 ± 5.50	2.70 ± 0.17	138.85 ± 14.53	14.94 ± 0.84
MaskPlace [26]	6.56	79.98	79.33	75.75	2.42	82.61	/	9.69%
after_local_search	6.15 ± 0.05	72.46 ± 3.69	74.18 ± 0.68	67.99 ± 1.13	2.22 ± 0.02	77.87 ± 1.54	/
WireMask-RS	6.13 ± 0.05	59.28 ± 1.48	60.60 ± 0.45	62.06 ± 0.22	2.19 ± 0.01	62.58 ± 2.07	8.20 ± 0.17	3.57%
after_local_search	5.99 ± 0.06	57.23 ± 1.75	59.22 ± 0.40	60.99 ± 0.82	2.17 ± 0.01	58.32 ± 3.57	7.64 ± 0.24
WireMask-BO	6.07 ± 0.14	59.17 ± 3.94	61.00 ± 2.08	63.86 ± 1.01	2.14 ± 0.03	67.48 ± 6.49	8.62 ± 0.18	3.77%
after_local_search	6.04 ± 0.12	54.24 ± 2.92	60.29 ± 2.29	62.96 ± 1.16	2.13 ± 0.01	63.87 ± 8.26	7.86 ± 0.21
WireMask-EA	5.91 ± 0.07	52.63 ± 2.23	57.75 ± 1.16	58.79 ± 1.02	2.12 ± 0.01	59.87 ± 3.40	8.28 ± 0.25	3.32%
after_local_search	5.89 ± 0.07	49.04 ± 2.35	57.41 ± 1.04	57.72 ± 0.76	2.11 ± 0.01	56.29 ± 5.23	7.66 ± 0.26
B.2 Hyper-parameter analysis
We empirically investigate the influence of the hyper-parameters of WireMask-EA, i.e., the number of partitions when discretizing the chip canvas into grids, the order of adjusting the positions of macros in objective evaluation, and the mutation operator.
Number of partitions. In our main experiments, the number of partitions is heuristically determined based on detailed macro statistics and varies across different chips, ranging from 108 for adaptec4 to 273 for bigblue4, as shown in Table 5. The first two rows of Table 7 show the results of WireMask-EA after increasing and decreasing the number of partitions by 100, respectively. The last row gives the results of the default WireMask-EA, achieving the highest average rank.
Table 7: HPWL values  $(\times 10^{5})$  obtained by WireMask-EA under different grid partition numbers. The symbol  $\times$  denotes that the method fails to generate non-overlapping placements. The best (smallest) mean value on each chip is bolded. The symbols  $+$ ,  $-$ , and  $\approx$  indicate that the number of chips where the result is significantly superior to, inferior to, and almost equivalent to the default setting, respectively, according to the Wilcoxon rank-sum test with significance level 0.05.
Method	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4	+/-/≈	Avg. Rank
+100_grid_num	5.88 ± 0.09	56.97 ± 2.16	57.74 ± 0.98	59.36 ± 1.10	2.30 ± 0.02	62.93 ± 3.36	8.32 ± 0.24	0/3/4	1.71
-100_grid_num	7.07 ± 0.18	×	×	×	3.06 ± 0.07	84.37 ± 4.14	10.14 ± 0.30	0/4/0	3.00
default setting	5.91 ± 0.07	52.63 ± 2.23	57.75 ± 1.16	58.79 ± 1.02	2.12 ± 0.01	59.87 ± 3.40	8.28 ± 0.25	1.28
By increasing the grid partition number, more fine-grained genotype-phenotype mapping guided by wire mask can be achieved, but the computational overhead is also increased. If the grid partition number is too small, the mapping may even not lead to non-overlapping placements, as observed on the chips adaptec2, adaptec3 and adaptec4 after decreasing the grid partition number by 100. Thus, a good balance needs to be considered, when determining the grid partition number in practice.
Order of adjusting the positions of macros. In the objective evaluation of WireMask-BBO, the positions of macros are adjusted sequentially, in the decreasing order of the sum of area of each macro's connected cells, as shown in lines 1-2 of Algorithm 1. Here, we also test the random adjustment order and the order only considering the area of each macro itself, the results of which are shown in the first two rows, respectively, of Table 8.
Table 8: HPWL values  $(\times 10^{5})$  obtained by WireMask-EA using different orders to adjust the positions of macros in objective evaluation. The symbol  $\times$  denotes that the method fails to generate non-overlapping placements. The best (smallest) mean value on each chip is bolded. The symbols  $+'$ ,  $-'$  and  $\approx$  indicate that the number of chips where the result is significantly superior to, inferior to, and almost equivalent to default setting, respectively, according to the Wilcoxon rank-sum test with significance level 0.05.
Benchmark	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4	+/-/≈	Avg. Rank
random_order	12.65 ± 0.68	×	×	93.25 ± 4.66	3.40 ± 0.09	×	×	0/3/0	3.00
size_only_order	6.32 ± 0.13	47.39 ± 1.02	61.18 ± 1.03	54.57 ± 1.69	2.16 ± 0.01	102.99 ± 7.69	10.80 ± 0.24	2/5/0	1.71
default setting	5.91 ± 0.07	52.63 ± 2.23	57.75 ± 1.16	58.79 ± 1.02	2.12 ± 0.01	59.87 ± 3.40	8.28 ± 0.25	1.28
The random order always leads to the worst result, and may even fail to generate non-overlapping placements. Compared with using the order only considering each macro's area, the original WireMask-EA performs significantly better on five chips, and worse on the other two chips. Its best overall performance is expected, because the order considering the sum of area of each macro's connected cells is more closely related to the performance metric HPWL.
Mutation operator. For WireMask-EA, which performs the best among the three variants of WireMask-BBO, we also examine the influence of its mutation operator. We employed the swap mutation operator in our experiments, which randomly selects two macros and interchanges their coordinates. To further investigate, we implement the uniform mutation operator as well, which selects a macro at random and uniformly reallocates it on the chip canvas. Moreover, we combine these two mutation operators, with each being executed with a probability of  $1/2$ . As shown in Figure 5, the utilization of the swap mutation operator alone (i.e., Swap_only) performs better than using the uniform mutation operator alone (i.e., Uniform_only) or their combination (i.e., Mix).
Figure 5: HPWL  $(\times 10^{5})$  vs. wall clock time of WireMask-EA using different mutation operators, where the shaded region represents the standard error derived from 5 independent runs.
B.3 Number of evaluations
Table 9 lists the number of evaluations used by WireMask-RS, WireMask-BO and WireMask-EA in Table 1, each of which runs for 1000 minutes. The number of evaluations of RS and EA is rather close, indicating that our EA operator is quite efficient. Besides, BO uses fewer evaluations than RS and EA, owing to the time-consuming cost of updating the Gaussian process model and optimizing the acquisition function.
Table 9: Number of evaluations of WireMask-RS, WireMask-BO and WireMask-EA in Table 1.
1000 min	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4
WireMask-RS	3610	3689	5257	2791	7367	976	106
WireMask-BO	820	655	810	600	1580	540	59
WireMask-EA	3526	3540	5179	2685	7217	877	97
B.4 Results on the ariane benchmark
We evaluate the performance of our WireMask-BBO framework on another benchmark, the ariane RISC-V CPU design [48], which has been previously studied in works such as [32, 26]. Our evaluation involves a comparison with three analytical methods and three RL methods, and the results are summarized in Table 10. The results of analytical and RL methods are directly from [26]. The analytical methods all fail to generate non-overlapping placement results on ariane, likely due to its high macro area utilization ratio of 0.78, which is the largest among all the benchmarks in Table 5. The overlapping issue is consistent with our discussion presented in Section 2.3. The RL-based methods show significantly worse performance compared to our proposed WireMask-BBO methods. The three different variants of WireMask-BBO are comparable based on the statistical test, with WireMask-EA demonstrating the lowest mean HPWL value.
Table 10: Comparison of HPWL values  $(\times 10^{5})$  on the ariane benchmark [48]. A ‘×’ symbol means that the method fails the legalization and thus cannot generate non-overlapping placement results. The best (smallest) mean value is bolded. The symbols ‘+’, ‘-’ and ‘≈’ indicate that the result is significantly superior to, inferior to, and almost equivalent to WireMask-EA, respectively, according to the Wilcoxon rank-sum test with significance level 0.05.
Method	Type	ariane	+/- / ≈
NTUPlace3 [12]	Analytical	×
RePlace [13]	Analytical	×
DREAMPlace [28]	Analytical	×
Graph [32]	RL	16.89 ± 0.60	-
DeepPR [15]	RL	52.20 ± 0.89	-
MaskPlace [26]	RL	14.63 ± 0.20	-
WireMask-RS	Ours	9.90 ± 0.18	≈
WireMask-BO	Ours	9.71 ± 0.46	≈
WireMask-EA	Ours	9.68 ± 0.61
B.5 Comparison with concurrent works
Recently, ChiPFormer [25] and AutoDMP [4] are proposed as new state-of-the-art methods in macro placement. For a comprehensive comparison, we also conduct experiments with these two concurrent works here.
ChiPFformer. ChiPFformer [25] incorporates an offline learning decision transformer to improve the generalizability. The pre-trained model provides placement results with acceptable quality within minutes, and converges to better results than MaskPlace [26] using fewer evaluations. We have compared our proposed WireMask-EA with ChiPFformer on ten chips, as outlined in Table 11. The experimental results show that our WireMask-EA clearly outperforms ChiPFformer on 9 circuits out of 10, no matter the number of evaluations is 1, 300 or  $2\mathrm{k}$ .
AutoDMP. AutoDMP [4] improves the efficient DREAMPlace [28], using Bayesian optimization to explore the configuration space and showing potential in real EDA application. We have included running time comparison between the state-of-the-art method AutoDMP [4] and our proposed WireMask-EA as shown in Figure 6. The results of MaskPlace (3k evaluations) and ChiPFformer (2k evaluations) are plotted by dotted lines in the figure. We can observe that on the two chip benchmarks, adaptec1 and bigblue1, AutoDMP and WireMask-EA can surpass MaskPlace and ChiPFformer quickly, and WireMask-EA performs the best.
Table 11: HPWL values  $(\times 10^{5})$  obtained by the recent proposed state-of-the-art method ChiP-Former [25] and our proposed WireMask-EA on ten chips, including adaptec and bigblue from ISPD2005 benchmark [35] and ibm from ICCAD2004 benchmark [3]. The number in () denotes the number of evaluations used. Each result consists of the mean and standard deviation of five runs. The best (smallest) mean value on each chip is bolded.
Benchmark	ChiPFormer (1)	WireMask-EA (1)	ChiPFormer (0.3k)	WireMask-EA (0.3k)	ChiPFormer (2k)	WireMask-EA (2k)
adaptec1	8.87 ± 0.98	7.20 ± 0.34	7.02 ± 0.11	6.29 ± 0.07	6.62 ± 0.05	5.96 ± 0.08
adaptec2	122.37 ± 22.61	111.04 ± 20.09	70.42 ± 2.67	61.25 ± 4.10	67.10 ± 5.46	53.88 ± 2.53
adaptec3	107.11 ± 8.84	75.37 ± 2.93	78.32 ± 2.03	64.49 ± 1.69	76.70 ± 1.15	59.26 ± 1.30
adaptec4	85.63 ± 7.52	75.63 ± 1.30	69.42 ± 0.54	64.52 ± 1.81	68.80 ± 1.59	59.52 ± 1.71
bigblue1	3.11 ± 0.03	2.31 ± 0.06	2.96 ± 0.04	2.18 ± 0.01	2.95 ± 0.04	2.14 ± 0.01
bigblue3	131.78 ± 17.36	99.20 ± 24.69	81.48 ± 4.83	64.51 ± 4.15	72.92 ± 2.56	56.65 ± 2.81
ibm01	4.57 ± 0.27	3.76 ± 0.36	3.61 ± 0.08	2.92 ± 0.07	3.05 ± 0.11	2.39 ± 0.07
ibm02	6.01 ± 0.41	5.13 ± 0.16	4.84 ± 0.17	3.86 ± 0.03	4.24 ± 0.25	3.56 ± 0.05
ibm03	2.15 ± 0.17	3.10 ± 0.12	1.75 ± 0.07	2.20 ± 0.11	1.64 ± 0.06	1.69 ± 0.11
ibm04	5.00 ± 0.14	3.60 ± 0.17	4.19 ± 0.11	2.93 ± 0.11	4.06 ± 0.13	2.62 ± 0.04
Figure 6: HPWL  $(\times 10^{5})$  vs. wall clock time of WireMask-EA and AutoDMP [4], where the shaded region represents the standard error derived from 5 independent runs.