SlowGuess/NeurIPS_2023_OCR huggingface dataset:
The positions of macros B and C are adjusted similarly. Figure 3(c) shows the adjusted placement of macro A, and also the wire mask when trying to place macro B. Figure 3(d) shows the adjusted placement of macros A and B, and also the wire mask when trying to place macro C. Figure 3(e) gives the final improved placement after adjusting the positions of all macros. As HPWL is the sum of all hyper-edges' bounding rectangles' half perimeters, these rectangles can be updated each time a macro is placed, as shown by the red and black dotted squares in Figure 3. That is, for any individual macro, it is only necessary to update the bounding rectangles of its associated hyper-edges and compute the increase in their half perimeters. Thus, the calculation of HPWL can be performed incrementally, as in line 9 of Algorithm 1. In Figure 3, the increment of HPWL after placing macros A, B and C is 6, 3 and 2, respectively, leading to the HPWL value 11 of the final improved placement. Note that the red and black dotted bounding rectangles in Figure 3 are shown for illustrative purposes, while the actual HPWL calculation in our experiments is based on pin information.
Therefore, we have formulated macro placement as a black-box optimization problem, where the genotype-phenotype mapping is greedily guided by wire mask. Figures 3(a) and (e) give an example of genotype and phenotype representation. An algorithm for solving this problem will search in the genotype space, where the goodness of a genotype solution is estimated by the objective value of its corresponding phenotype. When an algorithm terminates, the corresponding phenotype of the generated genotype solution will be output as the final macro placement. Note that by the wire-mask-guided mapping process, the phenotype solution is guaranteed to have no overlap, and thus an algorithm can search in the genotype space without considering constraints.
3.2 Black-Box Optimization
The above formulated problem can be solved by any BBO algorithm. In our experiments, we employ three simple ones, random search (RS), Bayesian optimization (BO) [17] and evolutionary algorithm (EA) [7]. RS randomly allocates all macros in a solution and evaluates it, recording the historical best. For BO, we adopt the efficient TuRBO approach [16] to directly optimize the continuous coordinates  $(x_{1},y_{1},\ldots ,x_{k},y_{k})$  of all macros, resulting in a dimension of  $2k$ , where  $k$  is the number of macros. For EA, we choose the simple  $(1 + 1)$ -EA [6, 49], which maintains only one solution and iteratively improves it by mutation. We design the mutation operator by randomly selecting two macros and exchanging their coordinates in a solution. Our experiments will show that using these three simple BBO algorithms has been sufficient for the superior performance over previous methods. It is expected to design better BBO algorithms for the proposed formulation of macro placement.
By adopting the grid-based discretization and designing the wire-mask-guided greedy genotype-phenotype mapping, the proposed framework WireMask-BBO can efficiently generate a non-overlapping high-quality placement, addressing the poor scalability issue of packing-based methods as well as the overlapping issue of analytical methods. The use of black-box optimization enhances the exploration ability, making WireMask-BBO able to surpass the state-of-the-art RL-based method MaskPlace [26]. Figure 2(d) visualizes a placement generated by WireMask-BBO equipped with EA, which is better than that by SP-SA (a representative packing-based method) [33], DREAMPlace (a representative analytical method) [28] and MaskPlace [26], as shown in Figures 2(a), 2(b) and 2(c).
We mainly empirically test our method on the ISPD2005 benchmark [35], which was originally proposed as a standard cell placement benchmark with fixed macros. Following conventional practice [15, 14, 26], we modify all macros to be movable for the macro placement problem. The ISPD2005 benchmark contains eight chips, i.e., adaptec1-4 and bigblue1-4. Note that for the bigblue2 chip, which has over 20,000 macros and 30,000 macro-related hyper-edges, a single objective evaluation by step-by-step placement costs more than an hour. Thus, we do not include this chip in our experiments as [26]. For each chip, the canvas is partitioned into approximately  $150 \times 150$  grids heuristically. The detailed statistics (e.g., the number of macros, partitions, etc.) of the chips are provided in Appendix A.
We compare WireMask-BBO with several representative macro placement methods, including the packing-based SP-SA [33], three analytical methods NTUPlace3 [12], RePlace [13], DREAM-Place [28], and three RL-based methods Graph placement [32], DeepPR [15], MaskPlace [26]. As introduced in Section 3.2, we equip the proposed WireMask-BBO framework with RS, BO and EA,
Table 1: HPWL values  $(\times 10^{5})$  obtained by ten compared methods on seven chips. Each result consists of the mean and standard deviation of five runs. The best (smallest) mean value on each chip is bolded. The symbols  $^+$ ,  $^-$  and  $^{\approx}$  indicate the number of chips where the result is significantly superior to, inferior to, and almost equivalent to WireMask-EA, respectively, according to the Wilcoxon rank-sum test with significance level 0.05.
Method	Type	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4 (×107)	+/-/~	Avg. Rank
SP-SA [33]	Packing	18.84 ± 4.62	117.36 ± 8.73	115.48 ± 7.56	120.03 ± 4.25	5.12 ± 1.43	164.70 ± 19.55	25.49 ± 2.73	0/7/0	6.86
NTUPlace3 [12]	Analytical	26.62	321.17	328.44	462.93	22.85	455.53	48.38	0/7/0	9.00
RePlace [13]	Analytical	16.19 ± 2.10	153.26 ± 29.01	111.21 ± 11.69	37.64 ± 1.05	2.45 ± 0.06	119.84 ± 34.43	11.80 ± 0.73	1/6/0	5.28
DREAMPlace [28]	Analytical	15.81 ± 1.64	140.79 ± 26.73	121.94 ± 25.05	37.41 ± 0.87	2.44 ± 0.06	107.19 ± 29.91	12.29 ± 1.64	1/6/0	4.86
Graph [32]	RL	30.10 ± 2.98	351.71 ± 38.20	358.18 ± 13.95	151.42 ± 9.72	10.58 ± 1.29	357.48 ± 47.83	53.35 ± 4.06	0/7/0	9.00
DeepPR [15]	RL	19.91 ± 2.13	203.51 ± 6.27	347.16 ± 4.32	311.86 ± 56.74	23.33 ± 3.65	430.48 ± 12.18	68.30 ± 4.44	0/7/0	8.86
MaskPlace [26]	RL	6.38 ± 0.35	73.75 ± 6.35	84.44 ± 3.60	79.21 ± 0.65	2.39 ± 0.05	91.11 ± 7.83	11.07 ± 0.90	0/7/0	4.28
WireMask-RS	Ours	6.13 ± 0.05	59.28 ± 1.48	60.60 ± 0.45	62.06 ± 0.22	2.19 ± 0.01	62.58 ± 2.07	8.20 ± 0.17	0/5/2	2.57
WireMask-BO	Ours	6.07 ± 0.14	59.17 ± 3.94	61.00 ± 2.08	63.86 ± 1.01	2.14 ± 0.03	67.48 ± 6.49	8.62 ± 0.18	0/3/4	2.86
WireMask-EA	Ours	5.91 ± 0.07	52.63 ± 2.23	57.75 ± 1.16	58.79 ± 1.02	2.12 ± 0.01	59.87 ± 3.40	8.28 ± 0.25	1.43
denoted as WireMask-RS, WireMask-BO and WireMask-EA, respectively. For the employed method TuRBO [16] for BO, we use the common hyper-parameters. For the EA, its initial solution is set as the best among 100 random solutions. All experiments are run on two Intel Xeon Platinum 8171M CPUs, each with 26 cores and 52 threads.
Main results. Table 1 gives the detailed results of running each method using five random seeds. The runtime for each run of WireMask-BBO is set as 1,000 minutes. The results of analytical and RL-based methods are directly from [26]. Note that the analytical method NTUPlace3 is deterministic, and thus has no standard deviation. We compute the rank of each method on each chip as in [21], which are averaged in the last column of Table 1. WireMask-RS, WireMask-BO and WireMask-EA achieve the three highest ranks, disclosing the effectiveness of the proposed general framework WireMask-BBO. Among these three variants, WireMask-EA performs the best, which has the highest rank 1.43 and achieves the smallest HPWL value on 5 out of the 7 chips. RS relies solely on random sampling without leveraging any search history. BO performs well in many low-dimensional tasks (typically when the dimension  $d \leq 20$  [17]), but suffers from the curse of dimensionality due to the time-consuming cost of updating the Gaussian process surrogate model and optimizing the acquisition function [8]. For example, in our experiments where  $d$  (i.e., 2 times the number of macros) is always larger than 1000, EA can sample much more solutions (about 2–7 times as shown in Table 9 of Appendix B) than BO during the 1000-minutes running. Compared with any previous method, WireMask-EA is significantly better on at least 6 out of the 7 chips, by the Wilcoxon rank-sum test with significance level 0.05. It is outperformed by RePlace and DREAMPlace on the chip adaptec4, implying the suitability of analytical methods for this particular problem.
Running time analysis. As shown in Table 1, any variant of WireMask-BBO always performs better than the state-of-the-art MaskPlace [26], which ranks the highest among the compared previous methods. While [26] did not offer explicit training time details, the authors state a 200-minute convergence time in response to our inquiry. Next, we examine the efficiency of WireMask-BBO when compared with MaskPlace. Taking MaskPlace as the baseline, we plot the curve of HPWL over the wall clock time for WireMask-BBO in Figure 4. Each variant of WireMask-BBO surpasses MaskPlace very quickly. Particularly, WireMask-EA requires only 39, 8, 0.37, 0.62, 0.15, and 3 minutes, respectively, with an average of 8 minutes to surpass MaskPlace across six benchmark chips. This is notably faster than the 200-minute convergence time reported for MaskPlace. We have excluded the bigblue4 chip in Figure 4, because the 1,000-minute search for WireMask-EA only completes its initialization on this large-scale chip. On the chips adaptec3 and adaptec4, WireMask-EA actually outperforms MaskPlace after only a single greedy placement guided by wire mask, implying that MaskPlace fails to balance exploration and exploitation.
Performance on congestion metric. Aside from HPWL, congestion and density are also vital metrics as introduced in Section 2.1. As our framework WireMask-BBO maintains the non-overlapping property, density constraint does not need to be considered. Here, we evaluate placement congestion and compare it to the results of MaskPlace [26] and SP-SA [33] in Table 2. We normalize the congestion values by setting WireMask-EA's congestion to 1.00. The MaskPlace placements are provided by its authors<sup>2</sup>, while the SP-SA and WireMask-BBO placement results are obtained from a
2All the MaskPlace evaluations are based upon the placement file provided by its authors. Note that the authors provided only one placement on each benchmark chip, and did not provide the results on bigblue4, which are marked by a '/' symbol in the following tables.
Figure 4: HPWL  $(\times 10^{5})$  vs. wall clock time of WireMask-BBO, where the shaded region represents the standard error derived from 5 independent runs.
Table 2: Comparison on HPWL  $\left( {\times {10}^{5}}\right)$  and Congestion (Cong.).
Benchmark Metrics	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4	Avg. Rank
HPWL	Cong.	HPWL	Cong.	HPWL	Cong.	HPWL	Cong.	HPWL	Cong.	HPWL	Cong.	HPWL	Cong.	HPWL	Cong.
SP-SA [33]	18.77	4.21	117.63	1.34	122.30	2.03	102.54	1.54	5.30	2.09	136.16	1.50	19.00	2.72	4.86	4.71
MaskPlace [26]	6.56	1.22	79.98	1.63	79.32	1.25	75.75	1.17	2.42	1.63	82.61	0.86	/	/	4.00	3.67
WireMask-RS	6.09	1.01	57.31	1.04	60.91	1.04	60.02	0.98	2.18	1.09	63.86	1.01	8.21	1.10	2.29	2.43
WireMask-BO	6.14	1.02	55.31	0.99	58.67	1.06	61.67	1.06	2.10	0.94	68.88	1.19	8.39	1.07	2.29	2.43
WireMask-EA	5.81	1.00	49.32	1.00	56.56	1.00	58.79	1.00	2.12	1.00	60.88	1.00	8.45	1.00	1.43	1.57
1,000-minute search using the same random seed. The results show that though optimizing HPWL, WireMask-BBO can also achieve smaller congestion. The reason is that the RUDY approximation of congestion is sometimes positively related to the HPWL metric. Given a macro placement solution, the HPWL in Eq. (1) is computed as the sum of the rectangle's half-perimeter of hyper-edge, i.e.,  $\sum_{e_j\in E}(w_j + h_j)$ , where  $e_j$  denotes a hyper-edge,  $E$  denotes the hyper-graph comprised of all hyper-edges,  $w_j$  and  $h_j$  denote the width and height of the rectangle corresponding to  $e_j$ , respectively. The RUDY measures the overall congestion on the canvas, and the congestion of each grid  $g_i$  on the canvas is calculated by the cumulative impact of all hyper-edges encompassing the grid. Note that a hyper-edge  $e_j$  will add an impact to each of its covered grids by  $\frac{1}{w_j} +\frac{1}{h_j}$ . Then, the overall congestion of all grids is  $\sum_{g_i}\sum_{e_j\in E(g_i)}\frac{1}{w_j} +\frac{1}{h_j} = \sum_{e_j\in E}w_j\cdot h_j\cdot (\frac{1}{w_j} +\frac{1}{h_j}) = \sum_{e_j\in E}(w_j + h_j) = \mathrm{HPWL}$ , where  $E(g_i)$  denotes the set of hyper-edges whose corresponding rectangle covers the grid  $g_i$ . The first equality holds because the number of times of a hyper-edge  $e_j\in E$  enumerated in LHS is equal to the number of grids covered by it, which is  $w_j\cdot h_j$ . Thus, we can observe a positive relation between RUDY and HPWL. Besides our results, Table 4 in MaskPlace [26] and Table 4 in ChiPFormer [25] have also shown that the best HPWL can lead to the best congestion. However, a lower HPWL does not necessarily lead to a lower RUDY, because RUDY only considers the top-10% congested grids as introduced in Section 2.1.
Full placement results. Table 3 shows the results of different methods on the full placement task involving both macros and standard cells. We utilize PRNet [14] and DREAMPlace [28] as baselines, because both of them are designed to handle mixed-size placement tasks. The other five macro placement methods first optimize the macro placement, fix the macro positions, and then employ DREAMPlace to optimize the standard cell placement exclusively. The mean±std values are derived from DREAMPlace standard cell placement using five different random seeds. The results of PRNet are directly from [14]. Although WireMask-EA achieves the best performance on only one chip, i.e., adaptec4, it attains the highest average rank. Compared with the mixed-size placement optimization methods PRNet and DREAMPlace, WireMask-EA does not explicitly optimize the full
Table 3: Comparison of HPWL values  $(\times 10^{7})$  on the full placement task involving both macros and standard cells. The best (smallest) mean value on each chip is bolded. The symbols  $+$ ,  $-$  and  $\approx$  indicate the number of chips where the result is significantly superior to, inferior to, and almost equivalent to WireMask-EA+DREAMPlace, respectively, according to the Wilcoxon rank-sum test with significance level 0.05.
benchmark	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	bigblue4	+/-/~	Avg. Rank
PRNet [14]	8.28	12.33	23.24	23.40	14.10	46.86	100.13	2/5/0	3.29
DREAMPlace [28]	11.10±1.31	13.84±1.74	17.03±0.99	24.37±1.13	10.06±0.28	36.51±0.56	175.86±2.23	2/4/1	3.57
SP-SA [33]+DREAMPlace	10.18±0.18	14.80±0.01	30.63±0.82	28.89±0.02	10.70±0.01	63.60±0.12	203.79±0.36	0/7/0	6.29
MaskPlace [26]+DREAMPlace	10.86±0.01	12.98±0.58	26.14±0.07	23.52±0.01	10.64±0.01	54.98±1.06	/	0/6/0	5.00
WireMask-RS+DREAMPlace	9.40±0.02	9.07±0.02	22.76±0.01	22.09±0.01	10.11±0.03	42.58±0.20	262.16±0.08	2/4/1	3.00
WireMask-BO+DREAMPlace	9.19±0.26	12.87±0.01	26.61±0.04	26.70±0.01	10.56±0.01	56.00±3.32	122.28±0.06	1/6/0	4.43
WireMask-EA+DREAMPlace	8.93±0.01	9.20±0.05	21.72±0.01	20.51±0.01	10.35±0.02	42.52±0.11	171.23±0.48	2.14
placement wirelength; thus, its best overall performance confirms the contribution of high-quality macro placement to an overall superior final placement.
Fine-tuning results. In fact, WireMask-BBO can be combined with any existing macro placement method for post-processing. The placement generated by any existing method can be treated as the initial solution of WireMask-BBO and then further improved. Table 4 shows the HPWL results of SP-SA and MaskPlace before and after 1,000 minutes of fine-tuning by WireMask-EA, with the average improvement ratio of  $53.93\%$  and  $17.06\%$ , respectively. Compared to Table 1, fine-tuning the placement of MaskPlace leads to the best HPWL value on the two chips adaptc1 and bigblue1.
Table 4: HPWL  $(\times 10^{5})$  values obtained after fine-tuning existing placements by running WireMaskEA for 1,000 minutes. The last column, Avg. Imp., denotes the average improvement ratio across six chips, obtained by comparing the HPWL values before and after fine-tuning.
Method	adaptec1	adaptec2	adaptec3	adaptec4	bigblue1	bigblue3	Avg. Imp.
SP-SA [33]	18.84	117.36	115.48	120.03	5.12	164.70	53.93%
+WireMask-EA (1000min)	6.02 ± 0.11	60.35 ± 4.41	57.88 ± 0.62	59.50 ± 0.92	2.21 ± 0.02	82.68 ± 18.17
MaskPlace [26]	6.56	79.98	79.32	75.75	2.42	82.61	17.06%
+WireMask-EA (1000min)	5.84 ± 0.10	61.43 ± 1.23	59.24 ± 2.71	60.35 ± 1.38	2.10 ± 0.01	74.93 ± 7.79
Additional results. We propose a post local search procedure to further improve final placement results. We investigate the influence of the two hyper-parameters of WireMask-BBO, i.e., number of partitions in chip canvas discretization, and adjustment order of macros in objective evaluation. For WireMask-EA, the best-performed variant of WireMask-BBO, the influence of different mutation operators is also examined. We compare the number of evaluations of WireMask-BBO methods in 1000 minutes. Furthermore, we test on the ariane RISC-V CPU design benchmark [48], still showing the clear superiority of WireMask-BBO over previous methods. We finally include comparisons with two concurrent advanced methods, i.e., ChiPFormer [25] and AutoDMP [4], and our WireMask-EA still maintains the superior performance. These results are provided in Appendix B.
This paper proposes the general framework WireMask-BBO for macro placement, which adopts a wire-mask-guided greedy genotype-phenotype mapping and can be equipped with any BBO algorithm. Extensive experimental results show that WireMask-BBO is clearly superior to previous packing-based, analytical, and RL-based methods. Furthermore, it can be combined with any existing macro placement method to further improve the final placement. Though showing significant potential, WireMask-BBO also has some limitations. First, it can only deal with macro placement, leaving standard cells for analytical placers. Second, its performance is limited for chips with a large number of macros due to the expensive objective evaluation. This, however, can be alleviated by equipping with high-dimensional BBO algorithms [8] or designing specific efficient BBO algorithms for macro placement, which is a very interesting future work. Our method does not have negative social impacts.
We would like to thank Yao Lai from The University of Hong Kong for his generous help and valuable discussions, and the anonymous reviewers for their helpful comments. This work was supported by the National Key R&D Program of China (2022ZD0116600) and National Science Foundation of China (62022039). Chao Qian is the corresponding author.
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The detailed statistics of benchmarks are in Table 5. Each column in the table represents the following:
- #Macros: the number of macros.
- #Standard cells: the number of standard cells.
- #Hyper-edges: the number of hyper-edges.
- #Macro-related Hyper-edges: the number of hyper-edges that are related to Marco, which is used in the objective evaluation process of WireMask-BBO.
- Area Utilization Ratio: the proportion of the total area of the chip canvas that is occupied by the macros, calculated by dividing the area of the macros by the total area of the chip canvas. A higher Area Utilization Ratio to some extent indicates a harder placement problem because we have to maintain the non-overlapping property.
- #Partitions: the number of partitions when discretizing the chip canvas into grids.
Table 5: Detailed statistics of different benchmarks.
Benchmark	#Macros	#Standard cells	#Hyper-edges	#Macro-related Hyper-edges	Area Utilization Ratio	#Partitions
adaptec1	543	210,904	3,709	693	0.48	160
adaptec2	566	254,457	266,009	4,201	0.63	158
adaptec3	723	450,927	466,758	3,259	0.55	113
adaptec4	1,329	494,716	515,951	2,949	0.48	108
bigblue1	560	277,604	284,479	409	0.27	160
bigblue2	23,084	534,782	577,235	33,223	0.38	/
bigblue3	1,298	1,095,514	1,123,170	3,937	0.66	234
bigblue4	8,170	2,196,183	2,229,886	22,223	0.37	273
ariane	932	0	12,404	12,404	0.78	357