[14] Ruoyu Cheng, Xianglong Lyu, Yang Li, Junjie Ye, Jianye Hao, and Junchi Yan. The policy-gradient placement and generative routing neural networks for chip design. In Advances in Neural Information Processing Systems 35, New Orleans, LA, 2022.
[15] Ruoyu Cheng and Junchi Yan. On joint learning for solving placement and routing in chip design. In Advances in Neural Information Processing Systems 34, pages 16508-16519, Virtual, 2021.
[16] David Eriksson, Michael Pearce, Jacob Gardner, Ryan D Turner, and Matthias Poloczek. Scalable global optimization via local Bayesian optimization. In Advances in neural information processing systems 32, Vancouver, Canada, 2019.
[17] Peter I Frazier. A tutorial on Bayesian optimization. arXiv preprint arXiv:1807.02811, 2018.
[18] Shinn-Ying Ho, Shinn-Jang Ho, Yi-Kuang Lin, and WC-C Chu. An orthogonal simulated annealing algorithm for large floorplanning problems. IEEE Transactions on Very Large Scale Integration Systems, 12(8):874-877, 2004.
[19] Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, and Jun Gu. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In Proceedings of the 13th IEEE/ACM International Conference on Computer Aided Design, pages 8-12, San Jose, CA, 2000.
[20] Meng-Kai Hsu, Yao-Wen Chang, and Valeriy Balabanov. TSV-aware analytical placement for 3D IC designs. In Proceedings of the 48th Design Automation Conference, pages 664-669, San Diego, CA, 2011.
[21] Demšar Janez. Statistical comparisons of classifiers over multiple data sets. Journal of Machine Learning Research, 7:1-30, 2006.
[22] Andrew B Kahng and Sherief Reda. A tale of two nets: Studies of wirelength progression in physical design. In Proceedings of the 7th International Workshop on System-level Interconnect Prediction, pages 17-24, Munich, Germany, 2006.
[23] George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. Multilevel hypergraph partitioning: Application in VLSI domain. In Proceedings of the 34th annual Design Automation Conference, pages 526-529, Anaheim, CA, 1997.
[24] Scott Kirkpatrick, C Daniel Gelatt Jr, and Mario P Vecchi. Optimization by simulated annealing. Science, 220(4598):671-680, 1983.
[25] Yao Lai, Jinxin Liu, Zhentao Tang, Bin Wang, Jianye Hao, and Ping Luo. Chipformer: Transferable chip placement via offline decision transformer. In Proceedings of the 40th International Conference on Machine Learning, pages 18346-18364, Honolulu, HA, 2023.
[26] Yao Lai, Yao Mu, and Ping Luo. Maskplace: Fast chip placement via reinforced visual representation learning. In Advances in Neural Information Processing Systems 35, New Orleans, LA, 2022.
[27] Jai-Ming Lin and Yao-Wen Chang. TCG-S: Orthogonal coupling of  $\mathbf{P}^*$ -admissible representations for general floorplans. In Proceedings of the 39th Annual Design Automation Conference, page 842-847, New Orleans, LA, 2002.
[28] Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, and David Z Pan. DREAMPlace: Deep learning toolkit-enabledgpu acceleration for modern VLSI placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(4):748-761, 2020.
[29] Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, and Chung-Kuan Cheng. ePlace: Electrostatics-based placement using fast Fourier transform and Nesterov's method. ACM Transactions on Design Automation of Electronic Systems, 20(2):1-34, 2015.