SlowGuess/NeurIPS_2023_OCR huggingface dataset:
Yunqi Shi, Ke Xue, Lei Song, Chao Qian*  
National Key Laboratory for Novel Software Technology, Nanjing University, China  
School of Artificial Intelligence, Nanjing University, China  
{shiyq, xuek, songl, qianc}@lamda.nju.edu.cn
The development of very large-scale integration (VLSI) technology has posed new challenges for electronic design automation (EDA) techniques in chip floorplanning. During this process, macro placement is an important subproblem, which tries to determine the positions of all macros with the aim of minimizing half-perimeter wirelength (HPWL) and avoiding overlapping. Previous methods include packing-based, analytical and reinforcement learning methods. In this paper, we propose a new black-box optimization (BBO) framework (called WireMask-BBO) for macro placement, by using a wire-mask-guided greedy procedure for objective evaluation. Equipped with different BBO algorithms, WireMask-BBO empirically achieves significant improvements over previous methods, i.e., achieves significantly shorter HPWL by using much less time. Furthermore, it can fine-tune existing placements by treating them as initial solutions, which can bring up to  $50\%$  improvement in HPWL. WireMask-BBO has the potential to significantly improve the quality and efficiency of chip floorplanning, which makes it appealing to researchers and practitioners in EDA and will also promote the application of BBO. Our code is available at https://github.com/lamda-bbo/WireMask-BBO.
EDA techniques have been widely employed to assist engineers in designing chips [30, 31], while the rapid advancement of VLSI technology has led to an exponential growth in chip scale, posing significant challenges. Particularly, for the important chip floorplanning stage in EDA, which strives to optimize power, performance, and area metrics while adhering to constraints such as congestion and density [45], the number of cells to be placed on the chip canvas increases rapidly and their routing relationships also become more complex, requiring innovative and efficient methods.
During the floorplanning placement stage, the position of each cell on the chip canvas is established. A modern chip typically comprises thousands of macros (i.e., individual building blocks such as memories) and millions of standard cells (i.e., smaller basic components like logic gates). The designer provides a netlist, which outlines the design requirements and serves as a large-scale hypergraph containing numerous hyper-edges (also called nets) that represent the routing relationships among macros and standard cells. Traditionally, the placement problem is divided into two successive stages [4]: macro placement, which is usually addressed by heuristic or learning methods [42, 44], and standard cell placement, which is usually addressed by analytical solvers [13, 28]. After placing all the cells (including macros and standard cells), a routing stage is performed. The general flow of chip floorplanning and routing is illustrated in Figure 1. In this work, we concentrate on macro placement due to its greater impact on placement quality: Macros are often larger and more crucial for achieving optimal placement [4, 47].
Figure 1: General flow of chip floorplanning and routing, where the routing stage basically relies on the placement result. We focus on the macro placement task in this paper.
Earlier methods often formulate macro placement as a rectangular packing problem, where solutions are represented by sequence pair (SP) [33],  $\mathbf{B}^*$ -tree [11], corner block list (CBL) [19] or other data structures [34, 27], and solve it by simulated annealing (SA) [1, 18, 24, 40]. This kind of method suffers from the poor scalability due to the quadratic complexity of decoding a genotype solution to a phenotype placement. Analytical methods [12, 13, 28, 29] place macros and standard cells simultaneously, and relax the task to a mathematical programming problem, which can be solved efficiently. However, they cannot guarantee the non-overlapping between cells, which is a hard constraint of cell placement. More recently, by dividing the chip canvas into discrete grids and formulating the task of placing macros onto grids step by step as a Markov decision process (MDP), reinforcement learning (RL) methods have been applied, showing promising performance [14, 15, 26, 32]. But their fast convergence (after only a few hundred evaluations) observed in experiments may imply that the huge search space of placement is still underexplored, and further improvement is expected. A detailed review of these existing methods is provided in Section 2.
In this paper, we propose a new BBO framework for macro placement. To allow better exploration, a solution is directly represented by the coordinates of all macros on the chip canvas. HPWL is used as the minimization objective function. The key of our framework is that in order to improve efficiency, we use an elaborate evaluation procedure, which greedily improves a solution (with the goal of minimizing HPWL while avoiding overlapping) before evaluation. Concretely, using the wire mask [26] to record the increment of HPWL by moving a macro to each candidate grid on the chip canvas, the macros in the solution are sequentially adjusted to the nearest best grid. This framework is briefly called WireMask-BBO, which can use any BBO algorithm to solve the resulting problem.
Experimental results on multiple popular benchmarks demonstrate that WireMask-BBO, when equipped with different BBO algorithms such as random search (RS), Bayesian optimization (BO), and evolutionary algorithms (EA), significantly outperforms the compared representative methods, including traditional BBO methods based on packing formulation, analytical methods, and RL methods. Especially, WireMask-EA (i.e., WireMask-BBO equipped with EA) generates the highest-quality placement in 6 out of 7 different chip benchmarks, and surpasses the state-of-the-art MaskPlace [26] in 8 minutes on average. Besides, as an optimization-based method, WireMask-BBO can fine-tune any existing placement, regardless of how it was generated. That is, WireMask-BBO can be combined with any existing macro placement method as post-processing. Our experiments show that such fine-tuning can lead to an improvement of up to  $50\%$  in the objective HPWL.
Our main contribution is introducing the general framework WireMask-BBO, while not developing new BBO algorithms. In fact, our experiments show that even employing simple BBO techniques has led to superior performance over previous methods. We will open-source WireMask-BBO and use it as an optimization benchmark to encourage the invention of more efficient BBO algorithms for solving macro placement problems, as well as broaden the application scenario of BBO.
In this section, we introduce the macro placement problem, and the existing methods which can be generally categorized into packing-based, analytical, and grid-based RL methods.
2.1 Macro Placement
The input for a macro placement problem constitutes a netlist  $H = (V, E)$ , where  $V$  denotes the information (i.e., height and width) about all cells designated for placement on the chip, and  $E$  is a hyper-graph comprised of hyper-edges  $e_i \in E$ , which encompasses multiple cells (including both macros and standard cells) and signifies their interconnectivity during the routing phase. A macro placement solution consists of the positions of all macros  $\{v_i\}_{i=1}^k$  with the coordinates of each macro  $v_i \in V$  on the chip canvas expressed as  $(x_i, y_i)$ , where  $k$  denotes the total number of maccros. To facilitate a comprehensive understanding of the macro placement problem, we present several key metrics for evaluating placement outcomes.
HPWL is the predominant metric for gauging placement quality, as it offers a precise estimation of the wirelength necessary for routing [9, 22, 38]. A shorter wirelength decreases delay and power consumption, enhancing overall performance [36]. To calculate HPWL of a macro placement solution  $s$ , each hyper-edge  $e_j \in E$  corresponds to a rectangle area characterized by its lower-left endpoint, with coordinates  $(\min_{v_i \in e_j} x_i, \min_{v_i \in e_j} y_i)$ , and its upper-right endpoint, with coordinates  $(\max_{v_i \in e_j} x_i, \max_{v_i \in e_j} y_i)$ . That is, the rectangle is the smallest one bounding all cells within  $e_j$ . Let  $w_j = \max_{v_i \in e_j} x_i - \min_{v_i \in e_j} x_i$  and  $h_j = \max_{v_i \in e_j} y_i - \min_{v_i \in e_j} y_i$  denote the width and height of the rectangle, respectively. Then,
$$
\operatorname {H P W L} (s, H) = \sum_ {e _ {j} \in E} \left(w _ {j} + h _ {j}\right). \tag {1}
$$
Congestion serves as a vital metric in determining the routability of a given placement, exerting a direct influence on the manufacturing process. A widely-adopted approach for approximating congestion is rectangular uniform wire density (RUDY) [41]. The congestion of a grid on the canvas can be represented as the cumulative impact of all hyper-edge rectangle areas encompassing the grid. By selecting the top  $10\%$  congested grids (denoted as  $G^{*}$ ) and computing the mean of their congestion, the RUDY value of a macro placement solution is calculated as  $\frac{1}{|G^{*}|}\sum_{g_i\in G^*}\sum_{e_j\in E(g_i)}\frac{w_j + h_j}{w_j\cdot h_j}$ , where  $|G^{*}|$  is the size of  $G^{*}$ ,  $E(g_{i})$  denotes the set of hyper-edges whose rectangle areas cover  $g_{i}$ , and  $(w_{j} + h_{j}) / (w_{j}\cdot h_{j})$  measures the impact of the rectangle area of hyper-edge  $e_j$ .
Density measures the overlap degree between cells by employing an electrostatic analogy [29]. It is often treated as a penalty to diminish overlap, yielding a more uniform distribution of cells across the chip area [4, 13, 28, 29]. Further discussion will not be provided here, as our formulation ensures non-overlapping, which is a hard constraint of macro placement.
Area denotes the area of the minimum bounding rectangle that encloses all the macros. It was prevalent when the focus was on tightly packing macros and minimizing the area they occupied [10, 42]. However, when considering fixed-area chips as in [15, 26, 28, 32] and our work, the placement of cells optimized is to reduce wirelength and congestion rather than minimize the area.
2.2 Packing-based Methods
As the focus was once on minimizing the bounding area of given macros, which can lead to a higher chip area utilization ratio [31], the packing formulation emerged as a natural and straightforward approach for the macro placement problem. Each macro, represented as a rectangle, has to be packed within a specified chip canvas, with the objective being to optimize the weighted sum of the area metric and HPWL metric. Several solution representation methods have been proposed, such as SP [33],  $\mathbf{B}^*$ -tree [11], CBL [19], etc. These genotype solutions will be mapped to concrete macro placement (phenotype) solutions for evaluation. SA is often employed [1, 18, 24, 40] to solve such BBO problems by perturbing the genotype to generate new offspring solutions and evaluating the corresponding phenotype to determine whether to accept the perturbation.
To handle both macros and standard cells, a divide-and-conquer idea is introduced [39, 43]. The standard cells are first clustered into blocks using either the logical hierarchy or min-cut-based partitioning algorithms [23, 37]. Placement is then performed on the mix of macro blocks and clustered standard cell blocks, often by SA using packing formulation [1, 2]. Finally, the standard cells are re-allocated by detailed placement. While reducing the problem size, clustering standard cells into rectangular blocks may cut some connections and hinder finding an optimal solution.
Recently, RL has been introduced to decide which perturbation operator should be selected and which macro should be perturbed by SA [46]. Moreover, [5] formulates the CBL establishment as a
(a) SP-SA [33]:
HPWL = 1.22 × 10<sup>7</sup>
Congestion  $= 1.07$
(b) DREAMPlace [28]:
HPWL = 9.88 × 10^6
Congestion  $= 0.83$
(c) MaskPlace [26]:
HPWL = 7.93 × 10^6
Congestion  $= 0.66$
(d) WireMask-EA (ours):
$\mathbf{HPWL} = 5.66 \times 10^{6}$
Congestion  $= 0.53$
Figure 2: Visualization of macro placement on the circuit benchmark adaptec3 using the proposed WireMask-EA and three representative methods. The macros are represented by yellow rectangles. The performance is evaluated in terms of HPWL and congestion; the lower the value, the better.
MDP and constructs a CBL genotype step by step. These advancements continue to grapple with the drawbacks of packing, such as poor scalability, which cannot be solved fundamentally because the drawbacks come from the quadratic complexity of mapping from genotype to phenotype [33]. Besides, at least one edge of each macro under the packing setting must be attached to another macro or the canvas's edge, making the placement quite congested, as visualized in Figure 2(a). Note that the congested macro placement will limit the space for subsequent standard cell placement, and lead to the bad performance of full placement, which will be shown in Table 3.
2.3 Analytical Methods
Analytical methods [12, 13, 28, 29] place macros and standard cells simultaneously, and relax the full placement task to a mathematical programming problem, which can be solved efficiently. For example, DREAMPlace [28], a state-of-the-art and highly efficient analytical placement method, recasts the full placement task as min  $\mathrm{WA}(s,H) + \lambda \cdot \mathrm{Density}(s,H)$ , where WA represents the smooth weighted-average wirelength (originally proposed by [20]) for approximating HPWL. Density denotes a differentiable density metric for penalizing overlapping, and  $\lambda$  is a trade-off factor. This problem is then solved numerically using classical mathematical optimization techniques (e.g., gradient descent), to rapidly generate high-quality full placement. Figure 2(b) shows a macro placement generated by DREAMPlace, which is better than that generated by packing in Figure 2(a). However, analytical methods cannot guarantee the non-overlapping between cells. Even employing macro placement legalization techniques, numerous overlaps may persist [4].
2.4 Grid-based RL Methods
As the number of macros increases, packing-based methods encounter scalability challenges, while analytical methods may produce overlapping placements that are impractical for manufacturing [4]. To meet the demands of modern chip design and fully leverage RL, the Graph placement published in Nature [32] divides the chip canvas into discrete grids, with each macro assigned discrete coordinates of grids, and formulates the placement problem as a MDP, wherein the agent decides the placement of the next macro at each step. Notably, no reward is given until the final step, when all macros are placed. The ultimate reward is the weighted sum of HPWL and congestion. Compared with packing-based methods, the grid-based design eliminates edge attachment and provides room for standard cell placement while offering improved scalability. The length of the MDP grows linearly with the number of macros, as opposed to the quadratic complexity of packing formulation [33]. DeepPR [15] integrates convolutional and graph neural networks during the embedding stage, and introduces an intrinsic reward to promote exploration. However, DeepPR brings overlaps. Though PRNet [14] incorporates the overlap area into the reward function as a penalty, the non-overlapping issue still exists as observed in their experiments.
A key limitation of the above-mentioned methods is the absence of extrinsic rewards until the final step, leading to sub-optimal performance for a long MDP with over one thousand steps. To
address this issue, MaskPlace [26] introduces a dense reward RL pipeline, incorporating a view mask for gathering global information, a position mask to ensure non-overlapping, and a wire mask to evaluate the placement of the current macro. Notably, the wire mask offers an immediate reward, calculated as the increase in HPWL after placing the current macro. These three masks are processed by a convolutional neural network and serve as input features for both the value and policy networks. MaskPlace can generate high-quality non-overlapping placement results in an affordable time. Figure 2(c) gives a placement example, which is better than that generated by packing and analytical methods as shown in Figures 2(a) and 2(b). From the experiments in [26], we can also observe that MaskPlace converges after only a few hundred evaluations, implying that the huge search space of placement may be still underexplored. The experimental results in Section 4 will confirm this conjecture, showing that our proposed framework will bring significant improvement.
3 Proposed Framework WireMask-BBO
This section is devoted to our proposed WireMask-BBO, where Section 3.1 introduces the problem formulation and Section 3.2 is concerned with optimization methods to solve the resulting problem.
3.1 Wire-Mask-Guided Problem Formulation
Solution representation. To allow better exploration, a macro placement solution  $s$  is directly represented by the coordinates of all macros  $\{v_i\}_{i=1}^k$ , i.e.,  $s = (x_1, y_1, \ldots, x_k, y_k)$ , where  $(x_i, y_i)$  denotes the coordinates of the macro  $v_i$  on the chip canvas. For example, there are three macros A, B and C for the placement task in Figure 3, and thus a solution  $s$  is represented by  $(x_1, y_1, x_2, y_2, x_3, y_3)$ .
Objective evaluation. The metric HPWL in Eq. (1) is used as the objective function to be minimized. But if optimizing in the solution space directly, it is difficult to efficiently find a solution that has a small HPWL value and satisfies the non-overlapping constraint. To improve the efficiency, a greedy improvement strategy is applied to a solution before evaluating it.
As in [32], the chip canvas is first divided into discrete grids. In the process of improving a solution greedily, each macro is moved to a grid by letting the macro's bottom-left corner situate at the bottom-left corner of the grid. The order of adjusting the position of a macro  $v_{i}$  is determined by the area of all the cells connected with  $v_{i}$ , i.e., all the cells in the hyper-edges containing  $v_{i}$ . Note that each hyper-edge contains a set of connected cells. The positions of all macros will be adjusted sequentially in the decreasing order of their corresponding computed areas, because a macro with a larger computed area implies connecting with more large cells and thus is intuitively more important.
Let  $v_{1}^{*}, \ldots, v_{k}^{*}$  denote the ordered macros. Assume that the positions of  $v_{1}^{*}, \ldots, v_{i-1}^{*}$  have been adjusted. When considering  $v_{i}^{*}$ , a wire mask  $W_{i}$  introduced in [26] is first computed, which records the increase of HPWL by placing  $v_{i}^{*}$  to each candidate grid, given  $v_{1}^{*}, \ldots, v_{i-1}^{*}$  already adjusted. Note that those grids that will lead to overlap or exceeding the canvas boundary after placing  $v_{i}^{*}$  are excluded. Then,  $v_{i}^{*}$  is moved to the grid with the least increment of HPWL. If such a grid is not unique,  $v_{i}^{*}$  is moved to the nearest one among them. This is actually a greedy step that moves  $v_{i}^{*}$  to the grid with the least increment on HPWL given the placement of  $v_{1}^{*}, \ldots, v_{i-1}^{*}$ . This process is repeated until the positions of all the macros have been adjusted. The HPWL of the resulting solution with all the adjusted macros is treated as the objective value of the original solution. Thus, a solution and its improved version in objective evaluation can be viewed as the genotype and phenotype representation of a macro placement. The detailed process of objective evaluation is presented in Algorithm 1.
Figure 3 gives an example illustration of objective evaluation. For the input netlist  $H = (V, E)$ ,  $V$  contains three macros A, B and C, and the hyper-graph  $E$  contains two hyper-edges: one encompasses macros A and B, and the other encompasses A and C. Each hyper-edge signifies the interconnectivity of the macros contained by it. The chip canvas is partitioned into  $5 \times 5$  grids. Assume that the width and height of each grid is both 1. The solution to be evaluated (as shown in Figure 3(a)) consists of the positions of macros A, B and C. According to the hyper-graph  $E$ , we know that during the routing phase, macro A is connected with B and C, while macro B and C are both connected with only A. Thus, the corresponding areas computed in line 1 of Algorithm 1 are decreasingly ordered as A, B and C, which is just the order in line 2 to adjust the positions of macros sequentially.
When trying to adjust the position of macro A, a wire mask is first computed as in line 5 of Algorithm 1, which is shown in Figure 3(b), where the number in each grid is the increment of HPWL
Algorithm 1 Objective evaluation of WireMask-BBO
Input: solution  $s$ , netlist  $H = (V,E)$ , and number  $m$  of partitions  
Output: improved solution  $s'$ , and the corresponding objective (i.e., HPWL) value  
Process:  
1: For each macro  $v_{i} \in V$ , compute the area of all the cells connected with it, i.e.,  $\cup_{v_{i} \in e_{j} \in E} e_{j}$ ;  
2: Order all macros decreasingly, denoted as  $v_{1}^{*}, \ldots, v_{k}^{*}$ , according to their corresponding areas;  
3: Initialize the canvas as  $m \times m$  grids, and let  $f = 0$ ;  
4: for each macro  $v_{i}^{*}$  do  
5: Generate wire mask  $W_{i}$  according to the updated positions of  $v_{1}^{*}, \ldots, v_{i-1}^{*}$  (see Algorithm 1 in [26]), which records the increment of HPWL by moving  $v_{i}^{*}$  to each candidate grid;  
6:  $Q \gets$  the set of grids that has the minimum increment of HPWL (denoted as  $f_{i}$ ) in  $W_{i}$ ;  
7: Select the grid  $g$  from  $Q$ , which has the smallest Euclidean distance to the macro  $v_{i}^{*}$ ;  
8: Update the position of  $v_{i}^{*}$  to be that of the grid  $g$ ;  
9:  $f \gets f + f_{i}$   
10: end for  
11:  $s' \gets$  the updated positions of all the macros  
12: return  $s', f$
Figure 3: An example illustration of objective evaluation of WireMask-BBO.
led by placing macro A in that grid. For example, if placing macro A in the center grid as shown in Figure 3(c), both the two hyper-edges correspond to the smallest rectangle bounding macro A (i.e., the red and black dotted square in Figure 3(c)) for computing HPWL in Eq. (1), and thus the corresponding HPWL is 6, which is the sum of half perimeters of these two rectangles. As the initial HPWL before placing macro A is 0, the increment of HPWL is 6. Note that when adjusting the position of a macro, its bottom-left corner must be situated at the bottom-left corner of a grid, and grids without numbers in the wire mask indicate that the current macro should not be placed there due to overlap or exceeding the canvas boundary. The underlined italic number in the wire mask denotes the least HPWL increment, representing the locally optimal choice, i.e., the set  $Q$  in line 6 of Algorithm 1. Then, as shown in lines 7-8 of Algorithm 1, macro A is placed at the local optimal grid, which has the smallest Euclidean distance to it. The coordinate of macro A in the original placement is denoted by the red star in Figure 3(b), and thus it is adjusted to be situated at the grid closest to it, as shown in Figure 3(c).