[8] Mohsen Hassanpourghadi, Shiyu Su, Rezwan A Rasul, Juzheng Liu, Qiaochu Zhang, and Mike Shuo-Wei Chen. Circuit connectivity inspired neural network for analog mixed-signal functional modeling. In 2021 58th ACM/IEEE Design Automation Conference (DAC), pages 505–510, 2021.
[9] Praveen Jaraut, Abubaker Abdelhafiz, et al. Augmented convolutional neural network for behavioral modeling and digital predistortion of concurrent multiband power amplifiers. IEEE Transactions on Microwave Theory and Techniques, 69(9):4142-4156, 2021.
[10] Vassilis Kalofolias. How to learn a graph from smooth signals, 2016.
[11] Thomas N. Kipf and Max Welling. Semi-supervised classification with graph convolutional networks, 2016.
[12] Sandeep Kumar, Jiaxi Ying, José Vinícius De M. Cardoso, and Daniel P Palomar. A unified framework for structured graph learning via spectral constraints. The Journal of Machine Learning Research, 21(1):785-844, 2020.
[13] Yaguang Li et al. A customized graph neural network model for guiding analog ic placement. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pages 1-9, 2020.
[14] Bo Liu, Georges Gielen, and Francisco V. Fernández. Automated Design of Analog and High-Frequency Circuits: A Computational Intelligence Approach. Springer Publishing Company, Incorporated, 2013.
[15] Bo Liu, Qingfu Zhang, and Georges G. E. Gielen. A gaussian process surrogate model assisted evolutionary algorithm for medium scale expensive optimization problems. IEEE Transactions on Evolutionary Computation, 18(2):180-192, 2014.
[16] Bo Liu, Dixian Zhao, Patrick Reynaert, and Georges G. E. Gielen. Synthesis of integrated passive components for high-frequency rfics based on evolutionary computation and machine learning techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(10):1458-1468, 2011.
[17] Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, and Haoxing Ren. Parasitic-aware analog circuit sizing with graph neural networks and bayesian optimization. In 2021 Design, Automation Test in Europe Conference Exhibition (DATE), pages 1372-1377, 2021.
[18] Yi-Chen Lu et al. Gan-cts: A generative adversarial framework for clock tree prediction and optimization. In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–8, 2019.
[19] Teruki Matsuba, Nobukazu Takai, Masafumi Fukuda, and Yusuke Kubo. Inference of suitable for required specification analog circuit topology using deep learning. In 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 131-134, 2018.
[20] Azalia Mirhoseini et al. A graph placement methodology for fast chip design. Nature, 594, 7862:207-212, 2021.
[21] J. M. Parr, A. J. Keane, A. I.J. Forrester, and C. M.E. Holden. Infill sampling criteria for surrogate-based optimization with constraint handling. Engineering Optimization, 44(10):1147-1166, 2012.
[22] Haoxing Ren, George F. Kokai, Walker J. Turner, and Ting-Sheng Ku. Paragraph: Layout parasitics and device parameter prediction using graph neural networks. In Proceedings of the 57th ACM/EDAC/IEEE Design Automation Conference, DAC '20. IEEE Press, 2020.
[23] Prakash Kumar Rout, Debiprasad Priyabrata Acharya, and Ganapati Panda. A multiobjective optimization based fast and robust design methodology for low power and low phase noise current starved vco. IEEE Transactions on Semiconductor Manufacturing, 27:43-50, 2014.