SlowGuess/NeurIPS_2023_OCR huggingface dataset:
Theorem 2 is the tightest known upper bound for log-precision transformers and shows that it is still possible to characterize transformers in a simple variant of first-order logic even with log-precision and uniform attention. As alluded to earlier, Theorem 2 immediately implies that any problem complete for  $\mathsf{FO}(\mathsf{M})$  (or a larger class) is also transformer-hard. Since integer division and Dyck language membership are known to be  $\mathsf{FO}(\mathsf{M})$ -complete (Hesse, 2001; Aaronson et al., 2022), it follows, perhaps surprisingly, that the entire computation of any transformer on input  $x$  can be reduced to a single integer division or a finite number of Dyck-language queries:
Corollary 2.1. Let  $\mathcal{T}$  be a transformer satisfying Theorem 2. For any input  $x$ , there exist first-order definable integers  $a, b$ , and  $i$  (dependent on  $\mathcal{T}$  and  $x$ ) such that  $\mathcal{T}(x)$  equals the  $i$ -th bit of  $\lfloor a / b \rfloor$ . For any  $x$ , there also exist first-order definable strings  $w_1, \ldots, w_m$  such that  $\mathcal{T}(x)$  is first-order definable in terms of the membership of the  $w_i$ 's in  $k$ -Dyck.
5 Preliminaries for Proving Theorem 2
5.1 Computation Graphs
A computation graph  $G$  over a datatype  $\mathbb{D} \subseteq \{0,1\}^*$  and a countable set of primitive functions  $\mathfrak{F} \subseteq \mathbb{D}^* \times \mathbb{D}$  is a directed acyclic graph where:
1. Each node is labelled by a node type: a function  $f \in \mathfrak{F}$  computed by this node.
2. Each edge represents a value  $\mathbb{D}$  flowing as output from one node into another node. We consider the edges flowing into node  $j$  to have an order, i.e., be numbered.
3.  $\mathfrak{F}$  contains the special symbol input, which designates  $k$  nodes as input nodes. We refer to  $k$  as the arity and assume w.l.o.g. that nodes  $0,\ldots ,k - 1$  are inputs. $^{14}$
4. A single node is taken as the output node (w.l.o.g., the node with the largest index).
A computation graph  $G$  of arity  $k$  parameterizes a function  $\mathbb{D}^k \to \mathbb{D}$  in the standard way: the input nodes are assigned the input values, and the value of each node is computed (traversing the graph in a bottom-up topological order) as a function of the values of its children until the output node receives a value. The value of the output node is considered the output of the function. It is worth noting that computation graphs can only process inputs of bounded length. To process arbitrary-length inputs, we will need to generalize them to computation graph families (Section 5.2).
For a computation graph  $G$ ,  $\mathrm{size}(G)$  is the number of nodes,  $\mathrm{depth}(G)$  is the length of the longest path from an input node to the output, and  $\mathrm{arity}(G, i)$  is the number of inputs to node  $i$ .
Threshold circuits. A threshold circuit is a special case of a computation graph where  $\mathbb{D} = \{0,1\}$  and  $\mathcal{F}$  is the set of threshold functions of the form  $\theta_{\leq \Delta}$  and  $\theta_{\geq \Delta}$  over  $\mathbb{D}^*$ , defined as follows:  $\theta_{\leq \Delta}(x) = 1$  if  $\sum_{\sigma \in x}\sigma \leq \Delta$  and 0 otherwise;  $\theta_{\geq \Delta}(x)$  is defined analogously. Typical AND, OR, and NOT gates are a special case of threshold gates, as is an IDENTITY gate. $^{15}$
We allow nodes with the  $k' \geq 1$  largest indices to all be designated as (ordered) output nodes. A threshold circuit with arity  $k$  and  $k'$  output nodes will thus be a function from  $\{0,1\}^k$  to  $\{0,1\}^{k'}$ . This will be convenient when simulating neural network components that output multiple bits.
We will find it useful to consider threshold circuits as a kind of compilation target for computation graphs: in other words, we will be concerned with simulating computation graphs defined over more complex functions and data types into threshold circuits.
5.2 Computation Graph Families
A computation graph family over  $\mathbb{D}$  and  $\mathfrak{F}$  is a mapping from  $n\in \mathbb{N}$  to a computation graph  $G_{n}$  for processing inputs of size  $n$ . Thus,  $\mathcal{G}$  defines a function from  $\mathbb{D}^*\to \mathbb{D}$ , where  $\mathcal{G}(x) = G_{|x|}(x)$ .
Theorem 2 can also be extended to apply to log-precision transformers with log-uniform weights, i.e., where  $\theta_{\mathcal{T}}$  can grow in size and precision with  $n$  (see Appendix B).
<sup>14</sup>By convention in computer science, we let computation graph nodes be zero-indexed.
For more background on threshold circuits, see Merrill & Sabharwal (2023) and Merrill et al. (2022).
Intuitively, computation graph families are useful because they generalize computation graphs to define functions over unbounded-length strings as inputs.
Size, depth, and arity. For computation graph families, the size, depth, and arity become functions of the input length  $n$ :  $\text{size}_{\mathcal{G}}(n) = \text{size}(G_n)$ ,  $\text{depth}_{\mathcal{G}}(n) = \text{depth}(G_n)$ ,  $\text{arity}_{\mathcal{G}}(n,i) = \text{arity}(G_n,i)$ .
Uniformity. The infinite set  $\mathcal{G}$  can be alternatively represented by two functions:
1.  $\mathrm{node}_{\mathcal{G}}(n,i)$ , which returns the type of node  $i$  in  $G_{n}$  if  $i \leq \mathrm{size}(G_{n})$ , and  $\emptyset$  otherwise. For example, if node  $i$  computes the logical AND of its inputs, then  $\mathrm{node}_{\mathcal{G}}(n,i) = \wedge$ .
2. edge $_{\mathcal{G}}(n, i, j)$ , which returns the argument index of  $i$  into node  $j$  if  $G_{n}$  contains an edge  $i \to j$  and  $-1$  otherwise. edge $_{\mathcal{G}}(n, i, j)$  only needs to be defined over  $i, j < \text{size}(G_{n})$ . For example, if  $G_{n}$  contains a node  $j$  with three incoming edges, the second of which comes from node  $i$ , then edge $_{\mathcal{G}}(n, i, j) = 1$ .
A pair of algorithms implementing these two functions uniquely specifies a computation graph family, as it enables building the computation graph  $G_{n}$  for any  $n$ . Uniform computation graph families (generalizing uniform circuits; cf. Arora & Barak, 2009) are families where node  $\mathcal{G}$  and edge  $\mathcal{G}$  can be computed efficiently, i.e., under some constraints on space or time:
Definition 5 (Uniformity). A computation graph family  $\mathcal{G}$  is  $T(n)$ -uniform iff  $\mathrm{node}_{\mathcal{G}}(n,i)$  and  $\mathrm{edge}_{\mathcal{G}}(n,i,j)$  can be computed by a deterministic Turing machine in time  $T(n)$ . We focus on log-uniform computation graph families: i.e., where  $T(n) = \mathrm{O}(\log n)$ .<sup>16</sup>
Threshold circuit families. These are simply families of threshold circuits. We will be simulating computation graph families with threshold circuit families. Log-uniform  $\mathsf{TC}^0$  is the class of languages recognized by log-uniform constant-depth, poly-size threshold circuit families. See Merrill & Sabharwal (2023); Liu et al. (2023); Arora & Barak (2009) for more background on  $\mathsf{TC}^0$  and circuits.
6 Proof of Theorem 2
The idea is to simulate a transformer with a log-uniform  $\mathsf{TC}^0$  circuit family. Since log-uniform  $\mathsf{TC}^0 = \mathsf{FO}(\mathsf{M})$ , this would imply any transformer can be expressed in  $\mathsf{FO}(\mathsf{M})$ . First, we note that transformers are log-uniform computation graphs:
Lemma 1 (Proof in Appendix B.1). A transformer  $\mathcal{T}$  is a log-uniform computation graph family where  $\mathfrak{F}$  contains embedding, self-attention, feedforward, and output components.
Further, each core module of the transformer can be simulated by a log-uniform  $\mathsf{TC}^0$  circuit family:
Lemma 2 (Proof in Appendix B.2). Let  $\mathcal{T}$  be a log-precision transformer with fixed parameters  $\theta_{\mathcal{T}}$ . Then each component in  $\mathfrak{F}$  is computable in log-uniform  $\mathsf{TC}^0$ .
Intuitively, we can now simulate a transformer in log-uniform  $\mathsf{TC}^0$  by just simulating each of its components with a threshold circuit and routing their inputs and outputs appropriately. However, we will need two more technical conditions to verify that this construction is indeed log-uniform:
Lemma 3 (Proof in Appendix B.3). Let  $\mathcal{T}$  be a log-precision transformer with fixed parameters  $\theta_{\mathcal{T}}$ . There exists a function  $\mathrm{bsize}(n)$  that is a power of 2 and computable in  $\mathrm{O}(\log n)$  time s.t.  $\mathrm{size}_{\mathcal{F}}(n) \leq \mathrm{bsize}(n)$  for all  $\mathcal{F} \in \mathfrak{F}$ .
Lemma 4 (Proof in Appendix B.4). If  $\mathcal{F}$  is a log-uniform  $\mathsf{TC}^0$  family and  $\mathrm{size}_{\mathcal{F}}(n)\leq \mathrm{bsize}(n)$ , there exists a log-uniform  $\mathsf{TC}^0$  family  $\mathcal{F}'$  s.t.  $\mathcal{F}(x) = \mathcal{F}'(x)$  for all  $x$  and  $\mathrm{size}_{\mathcal{F}'}(n) = \mathrm{bsize}(n)$ .
Combined, Lemmas 3 and 4 show that each  $\mathcal{F} \in \mathfrak{F}$  is computable by a log-uniform  $\mathsf{TC}^0$  family with size  $\mathrm{bsize}(n)$  that is a power of 2 and computable in time  $\mathrm{O}(\log n)$ . We will show these conditions imply a transformer  $\mathcal{T}$  can be simulated by a  $\mathsf{TC}^0$  family  $\mathcal{C}$  (Theorem 3) and moreover that  $\mathcal{C}$  is log-uniform (Corollary 3.2). By the equivalence of log-uniform  $\mathsf{TC}^0$  and  $\mathrm{FO}(\mathsf{M})$  (Barrington et al., 1990), we then conclude that any log-precision transformer can be expressed in  $\mathrm{FO}(\mathsf{M})$ .
<sup>16</sup> Past work (Merrill & Sabharwal, 2023) analyzes transformers with a similarly named but weaker notion of uniformity, namely log-space (rather than log-time) uniformity.
Algorithm 1 nodeC(n,i)Return the type of gate i in circuit Cn.	Algorithm 2 edgeC(n,i,j)If Cn contains an edge i → j, return the argument number of that edge. Otherwise, return -1.
1: F← nodeG(n,bnode(n,i))2: if F ≠ ∅ then3: return nodeF(n,i-bstart(n,i'))4: else return ∅	1: i' ← bnode(n,i)2: j' ← bnode(n,j)3: si ← bstart(n,i')4: sj ← bstart(n,j')5: if i' = j' then6: F ← nodeG(n,i')7: return edgeF(n,i-si,j-sj)8: else if edgeG(n,i',j') ≥ 0 then9: bi ← i-(si + bsize(n,i') - p(n))10: bj ← j-(sj + p(n)·edgeG(n,i',j'))11: if bi = bj < p(n) then return j - sj)12: else return -113: else return -1
6.1 Simulating Computation Graph Families with Circuit Families
We give algorithms that take a computation graph family and define a circuit family simulating it. Intuitively, the algorithms create contiguous blocks of circuit gates simulating each node in the computation graph and route inputs and outputs between blocks appropriately.
Block mapping. This algorithm depends on a block mapping, which is an implementation of the following three functions:
1. The block node  $\text{bnode}(n, i)$ : the index of the node that gate  $i$ 's block is simulating.
2. The block start bstart  $(n,i^{\prime})$  : the smallest gate index in the block simulating node  $i^{\prime}$
3. The block size  $\mathrm{bsize}(n,i')$ : the number of gates in the block simulating node  $i'$ .
Further, we enforce that a valid block mapping must satisfy that, for all  $i$ , with  $i' = \mathrm{bnode}(n,i)$
$$
\operatorname {b s t a r t} \left(n, i ^ {\prime}\right) \leq i <   \operatorname {b s t a r t} \left(n, i ^ {\prime}\right) + \operatorname {b s i z e} \left(n, i ^ {\prime}\right).
$$
Let  $\mathcal{G}$  be a computation graph whose primitive functions are computable by log-uniform threshold circuits. We can identify each primitive function with a log-uniform threshold circuit family  $\mathcal{F}$  that computes it, where the first arity  $\mathcal{F}(n)$  gates are IDENTITY gates reserved for taking input. For such a graph, node $_{\mathcal{G}}$  can be taken to return a symbol identifying a circuit family  $\mathcal{F}$ . In this case, our algorithm requires that, for all  $i'$ , the block size of  $i'$  must match the size of the circuit for the type of block  $i'$ , i.e.,  $\mathrm{bsize}(n,i') = \mathrm{size}_{\mathrm{node}_{\mathcal{G}}(n,i')} (n)$ . These properties let us meaningfully identify a graph node  $i'$  with a block of nodes that will simulate it. This intuition enables us to develop Algorithms 1 and 2 for constructing a uniform threshold circuit family from a uniform computation graph family.
Theorem 3. Let  $\mathcal{G}$  be a computation graph over a finite set of node types  $\mathfrak{F}$ , where each  $\mathcal{F} \in \mathfrak{F}$  is specified by a log-uniform circuit family. Let bnode, bstart, and bsize be a valid block mapping in the sense above. Then Algorithms 1 and 2 define a circuit family  $\mathcal{C}$  such that
1.  $\mathcal{C}$  and  $\mathcal{G}$  compute the same  $\mathbb{D}_p^* \to \mathbb{D}_p$  function (let the final  $p$  gates of each  $C_i$  be its output).
2.  $\mathrm{depth}_{\mathcal{C}}(n)\leq \mathrm{depth}_{\mathcal{G}}(n)\cdot \max_{\mathcal{F}}\mathrm{depth}_{\mathcal{F}}(n).$
3.  $\mathsf{size}_{\mathcal{C}}(n)\leq \mathsf{size}_{\mathcal{G}}(n)\cdot \max_{\mathcal{F}}\mathsf{size}_{\mathcal{F}}(n).$
Proof. Assume w.l.o.g. that the gates of  $\mathcal{C}$  are topologically ordered. We show by induction over circuit gates  $j$  (with  $j' = \mathrm{bnode}(n, j)$ ) that:
1. For all  $i' < j'$ , the last  $p$  nodes of block  $i'$  store the value of node  $i'$ .
2. For all  $i$  such that  $\mathrm{bstart}(n,j')\leq i\leq j$ , gate  $i$  of  $\mathcal{C}$  (as a function of the input nodes of  $j'$ ) computes gate  $i - \mathrm{bstart}(n,j')$  of  $\mathrm{node}_{\mathcal{G}}(n,j')$ .
Base case. We have two circuits with no gates, so the premises are trivially satisfied.
Inductive case. Assume the premises hold up to  $j$ . We will show they hold for  $j + 1$ . Let  $\mathcal{T} = \mathrm{node}_{\mathcal{G}}(n, j')$ . By Premise 1, we know that the last  $p$  nodes of block  $i'$  store the output of node  $i'$ , for
$i' < j'$ . By Algorithm 2, for each  $i'$  such that  $\mathrm{edge}_{\mathcal{G}}(n,i',j') = a$  with  $0 \leq k < \mathrm{arity}_{\mathcal{F}}(n)$ , gates  $kp$  through  $k(p + 1) - 1$  of block  $j'$  will copy the final  $p$  gates of block  $i'$ . Thus, the first  $k \cdot \mathrm{arity}_{\mathcal{F}}(n)$  gates of block  $j'$  store the inputs to node  $j'$ .
At this point, we use Premise 2 to conclude that the first  $j - \mathrm{bstart}(n,j')$  gates of block  $j'$  compute the same function as the first  $j - \mathrm{bstart}(n,j')$  gates of  $\mathcal{F}$  with respect to this input. Thus, we just need to show that gate  $j + 1$  is also correct. Within Algorithm 2, we fall in case  $i' = j'$ , meaning that gate  $j + 1$  of block  $j'$  gates the same inputs as gate  $j + 1$  of  $\mathcal{F}$ . By Algorithm 1, the type of gate  $j + 1$  in block  $j'$  is the type of gate  $j + 1$  of  $\mathcal{F}$ . Thus, gate  $j + 1$  in block  $j'$  computes the same function of the input gates as gate  $j + 1$  in  $\mathcal{F}$ . If  $j + 1 = \mathrm{bsize}(n,j')$ , we conclude that the final  $p$  gates of block  $j'$  store the output of node  $j'$ .
Let  $\mathsf{XC}^0$  denote any family of constant-depth, poly-size circuits, including  $\mathsf{AC}^0$  and  $\mathsf{TC}^0$ .<sup>17</sup>
Corollary 3.1. Let  $\mathcal{G}$  be a constant-depth, poly-size computation graph family over a finite  $\mathfrak{F}$ . If every node type in  $\mathfrak{F}$  can be computed by  $\times C^0$  circuits, the function computed by  $\mathcal{G}$  is in  $\times C^0$ .
Since a transformer has constant depth and polynomial size, Corollary 3.1 lets us easily recover prior results about hard-attention transformers (Hao et al., 2022; Hahn, 2020) and saturated attention transformers (Merrill et al., 2022) using a common framework. All one has to do is show that all individual node types in such transformers can be computed by  $\mathsf{AC}^0$  and  $\mathsf{TC}^0$  circuits, respectively.
Corollary 3.1 established that Algorithms 1 and 2 construct a circuit family that simulates  $\mathcal{G}$ . With the right block mapping,  $\mathcal{C}$  will be log-uniform as long as  $\mathcal{G}$  and its node types are log-uniform.
Corollary 3.2. Let  $\mathcal{G}$  be a log-uniform, constant-depth computation graph family over a finite  $\mathfrak{F}$ , where each  $\mathcal{F} \in \mathfrak{F}$  is specified by a log-uniform  $\mathsf{TC}^0$  family with  $\text{size}_{\mathcal{F}}(n) = \text{bsize}(n)$  that is a power of 2 computable in  $\mathrm{O}(\log n)$  time. Then  $\mathcal{G}$  can be simulated by a log-uniform  $\mathsf{TC}^0$  family  $\mathcal{C}$  that obeys the size and depth properties of Theorem 3.
Proof. Let  $\mathcal{C}$  be the circuit family defined by Algorithms 1 and 2 given  $\mathcal{G}$  and the following block mapping:  $\mathtt{bnode}(n,i) = \lfloor i / \mathtt{bsize}(n)\rfloor$ ,  $\mathtt{bstart}(n,i') = i'\cdot \mathtt{bsize}(n)$ ,  $\mathtt{bsize}(n,i') = \mathtt{bsize}(n)$ . Since  $\mathtt{bsize}(n)$  is a power of 2,  $\mathtt{bnode}$  and  $\mathtt{bstart}$  are reducible to left and right shifting over  $\mathrm{O}(\log n)$ -bit integers, which can be implemented in  $\mathrm{O}(\log n)$  time. Thus, each block mapping function is computable in time  $\mathrm{O}(\log n)$ . Since  $\mathtt{node}_{\mathcal{G}}$  and  $\mathtt{edge}_{\mathcal{G}}$  are just calling functions computable in time  $\mathrm{O}(\log n)$  with constant overhead, we conclude that  $\mathcal{C}$ , the circuit family they define, is log-uniform, and it is already known to simulate  $\mathcal{G}$  with constant depth and polynomial size by Theorem 3.
We proved that any log-precision transformer classifier can be translated to an  $\mathsf{FO}(\mathsf{M})$  sentence that computes the same function (on all inputs of any length). This result comes by first simulating a transformer with a highly uniform threshold circuit family, and then leveraging the established equivalence of log-uniform circuits and  $\mathsf{FO}(\mathsf{M})$ . Transformers and other neural nets are often discussed in contrast with symbolic models based on logical formalisms (Garnelo & Shanahan, 2019)—an immediate implication of our result is that it is possible to express the inner workings of transformers also in a simple logic, challenging the premise of a rigid division between symbolic and neural models. Our results also provide the tightest known upper bound on log-precision transformers.
While it is striking that a full transformer can be translated to a sentence in a logic as simple as  $\mathsf{FO}(\mathsf{M})$ , we believe the bound is not tight. In particular, we conjecture that it is possible to simulate any transformer with an  $\mathsf{FO}(\mathsf{M})$  sentence of quantifier depth of at most 2, which could be proven by establishing a hierarchy theorem describing the  $\mathsf{FO}(\mathsf{M})$  quantifier depth needed to simulate a  $\mathsf{TC}^0$  family of a certain size. It would also be an interesting extension to translate real transformers to  $\mathsf{FO}(\mathsf{M})$  sentences. In this sense, we believe our results provide a theoretical foundation to guide mechanistic interpretability work (cf. Weiss et al., 2021; Lindner et al., 2023).
Our findings provide a novel view into transformer classifiers and their limits. It would be exciting for future research to extend our results to account for other common practical uses of transformers, such as for long-form generation, chain-of-thought reasoning, and in-context learning.
Formally,  $\mathfrak{F}$  just needs to contain  $\wedge$  and  $\vee$ .
We thank Paul Beame, David Chiang, anonymous reviewers, and researchers at the Allen Institute for AI for feedback. WM was supported by an NSF graduate research fellowship and in part by NSF award 1922658.
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