* Z:\home\khalils\Downloads\files\data\raw_asc\LT7184S.asc
* Generated by LTspice 26.0.1 for Windows.
* NOTES FOR SIMULATION\n \nPlease read the following notes carefully since the model behaves differently from the user \ninterface for the LT7184S_verify_2025JUN11v1.\n \n(1) PMBus communication and memory address related functions and pins are not modeled, \nincluding SDA, SCL, WP. \n(2) Changes to parameter values while the simulation is running will not take effect unless the\nsimulation is stopped and restarted. This is different from the way the part operates which will\nrespond to the changes while running. \n(3) Resistor Configuration pins are not modelled. \n(4) Initialization time is not modelled. After power is applied to PVIN0 or EXTVCC, the real LT7184S_verify_2025JUN11v1\nrequires 13ms (typical) before power conversion or communication can begin.\n(5) Default Fault Response is only modelled (VIN_OV_Fault, Vout_OV_Fault: Immediate off, Infinite retry (10ms retry time), Other Faults: Ignore)\n The LT7184S_verify_2025JUN11v1 offers different fault response possibility for different faults and programmable retry time\n(6) SHARE_CLK: Default behaviour is modelled ( SHARE_CLK Pulls low when VIN falls below VIN_OFF, Output will be disabled if SHARE_CLK held low)\n \n \nDESCRIPTION OF PARAMETERS\n \nThe following parameters can be defined by right-clicking on the LT7184S_verify_2025JUN11v1 symbol.\nThe nomenclature used here differs from the one in the data sheet. If any value of these parameters is\nset beyond the scope described in the data sheet, the resulting simulation will not be meaningful.:\n \nFREQUENCY_SWITCH -- in Hz, sets switching frequency for both channels\n \nThe parameters below are set independantly for each channel (0 and 1): \nVOUT_COMMAND_n -- in volt, sets output voltage\n \nTON_DELAY_n & TON_RISE_n -- in sec, set turn-on delay and soft-start time\nTOFF_DELAY_n & TOFF_FALL_n -- in sec, set turn-off delay and soft-off time \n \nIlim_range_n -- selects inductor valley current limit option:\n 0 positive valley current limit of 4A, negative valley current limit of -3.5A\n 1 positive valley current limit of 7A, negative valley current limit of -6A\n 2 positive valley current limit of 9A, negative valley current limit of -7.5A\n 3 positive valley current limit of 9A, negative valley current limit of -9A \n \nPulseSkipMode_n --sets operation mode: 1 for pulse skip mode, 0 for forced continuous conduction mode\n \n \n \nGMEA_control_n --Sets Error Amp parameters, x=0 to 7\n GmEA = 0.15mS*(x+1)*(1+3*HPLV_n) (relative to VSENSE)\n \nHPLV_n -- if set to 1, selects High-Performance Low-Vout mode (max 1.375Vout, GMEA is 4X higher)\n \nRITH_n --in ohm, programmable internal compensation\n \nCITH_n --in Farad, programmable internal compensation\n \nMFR_PWM_PHASE_n -- in degree, sets the channel phase delay in 15-degree increments \n (this is relative to the SYNC input clock if present).\nMFR_DISCHARGE_THRESHOLD--Output voltage threshold to determine that the output has decayed sufficiently to reenable the channel\n \n \nVout_UV_Fault_Limit and Vout_OV_Fault_Limit --- in volt, set the fault limits for the PGOOD and /FAULT outputs\n Note channel shuts down if VOUT OV FAULT occurs, or VIN>17.6V, or /FAULT pin is pulled low externally\nVout_UV_Warn_Limit and Vout_OV_Warn_Limit-- in volt, set the warning limit for the /ALERT output\n \nEN_SYNC_OUT ---1 Output SYNC Pulses, 0 SYNC works as input.\n \n \n \nTo simulate parallel operation \n \nTie RUN, VIN, SHARE_CLK, _FAULT, _ALERT, PGOOD, ITH pins of all the channels together\nset EN_SYNC_OUT = 1 for only one channel and set EN_SYNC_OUT = 0 for all other channel\nThe parameters set in all the channels should be identical other than EN_SYNC_OUT
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT7184S.asy)
V5 EXTVCC 0 5
V1 VIN 0 12
C4 0 DRVCC 10
C7 0 N001 470p
I2 OUT1 0 PULSE(0 4 1.9m 1u 1u 100u) load
XU1 VIN SW0 0 SW1 BOOST0 BOOST1 DRVCC INTVCC EXTVCC VDD18 _ALERT 0 OUT0 0 RUN0 PGOOD0 ITH1 SYNC VIN OUT1 0 PGOOD0 INTVCC PGOOD1 _FAULT _FAULT SHARE_CLK LT7184S FREQUENCY_SWITCH=1Meg MFR_PWM_PHASE_0=0 VOUT_COMMAND_0=3.3 HPLV_0=0 ILIM_RANGE_0=2 GMEA_CONTROL_0=3 RITH_0=40k CITH_0=80p MFR_DISCHARGE_THRESHOLD_0=0.2 VOUT_UV_FAULT_LIMIT_0=3.069 VOUT_OV_FAULT_LIMIT_0=3.63 VOUT_UV_WARN_LIMIT_0=3.086 VOUT_OV_WARN_LIMIT_0=3.5475 VIN_ON_0=1.5 VIN_OFF_0=1.45 TON_DELAY_0=0.01m TON_RISE_0=0.5m TOFF_DELAY_0=0.1m TOFF_FALL_0=0.3m MFR_PWM_PHASE_1=180 VOUT_COMMAND_1=0.8 HPLV_1=1 ILIM_RANGE_1=2 GMEA_CONTROL_1=7 RITH_1=40k CITH_1=80p MFR_DISCHARGE_THRESHOLD_1=0.2 VOUT_UV_FAULT_LIMIT_1=0.744 VOUT_OV_FAULT_LIMIT_1=0.88 VOUT_UV_WARN_LIMIT_1=0.748 VOUT_OV_WARN_LIMIT_1=0.86 VIN_ON_1= 1.4 VIN_OFF_1=1.35 TON_DELAY_1=0.1m TON_RISE_1=0.5m TOFF_DELAY_1=0 TOFF_FALL_1=0.3m EN_SYNC_OUT=0 ;pnba PVIN0)SW0)SGND)SW1)BOOST0)BOOST1)DRVCC)INTVCC)EXTVCC)VDD18)_ALERT)PGND)VSENS0P)VSENS0N)RUN0)PGOOD0)ITH1)SYNC)PVIN1)VSENS1P)VSENS1N)RUN1)ITH0)PGOOD1)_FAULT0)_FAULT1)SHARE_CLK
R2 OUT0 0 3.3
C2 OUT0 0 100 x3 Rser=2m
V7 CLK_EXT 0 PULSE(0 5 2.5m 1n 1n 500n 1u 500)
R3 EXTVCC PGOOD1 10k
R8 _ALERT EXTVCC 4700
I3 OUT0 0 PULSE(0 6 1.4m 1u 1u 100u) load
C1 OUT1 0 100 x2 Rser=2m
C5 0 INTVCC 10
C3 0 VDD18 4.7
V6 RUN0 0 PWL(500u 0 500.001u 5 3000u 5 3000.001u 0)
R1 OUT1 0 0.3
C8 BOOST1 SW1 0.1
L2 SW1 OUT1 470n Rser=2.5m
C10 BOOST0 SW0 0.1
R10 _FAULT EXTVCC 10k
R9 PGOOD0 EXTVCC 10k
R6 ITH1 N001 15k
R7 SYNC 0 162k
L3 SW0 OUT0 1 Rser=2.5m
R11 SHARE_CLK EXTVCC 10k
C12 CLK_EXT SYNC 1.5n
.tran 3.6m startup
.lib LT7184S.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1724 1384
WIRE -2448 -544 -2464 -544
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WIRE -1904 640 -1904 608
WIRE -1712 640 -1712 608
SYMBOL res -1504 512 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 15k
SYMBOL ind -2288 -288 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 1
SYMATTR SpiceLine Rser=2.5m
SYMBOL cap -2432 -208 R0
WINDOW 123 57 48 Left 2
WINDOW 3 50 26 Left 2
SYMATTR Value2 x3
SYMATTR Value 100
SYMATTR InstName C2
SYMATTR SpiceLine Rser=2m
SYMBOL cap -2304 -384 R0
WINDOW 0 -40 12 Left 2
SYMATTR InstName C10
SYMATTR Value 0.1
SYMBOL current -2912 -256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 31 95 Left 2
WINDOW 3 31 67 Left 2
SYMATTR SpiceLine load
SYMATTR Value PULSE(0 6 1.4m 1u 1u 100u)
SYMATTR InstName I3
SYMBOL cap -2640 320 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C12
SYMATTR Value 1.5n
SYMBOL voltage -2448 256 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL cap -1408 352 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C5
SYMATTR Value 10
SYMBOL res -2208 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 10k
SYMBOL res -2240 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 4700
SYMBOL res -1088 -256 R0
SYMATTR InstName R1
SYMATTR Value 0.3
SYMBOL cap -1216 -208 R0
WINDOW 123 65 49 Left 2
WINDOW 3 59 27 Left 2
SYMATTR Value2 x2
SYMATTR Value 100
SYMATTR InstName C1
SYMATTR SpiceLine Rser=2m
SYMBOL res -2240 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 10k
SYMBOL res -2240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 10k
SYMBOL cap -1408 272 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL res -2528 -256 R0
SYMATTR InstName R2
SYMATTR Value 3.3
SYMBOL res -1312 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL voltage -2752 384 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value PULSE(0 5 2.5m 1n 1n 500n 1u 500)
SYMATTR InstName V7
SYMBOL cap -1408 192 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL res -2544 336 R0
SYMATTR InstName R7
SYMATTR Value 162k
SYMBOL current -976 -240 R0
WINDOW 123 24 122 Left 2
WINDOW 39 24 101 Left 2
SYMATTR SpiceLine load
SYMATTR Value PULSE(0 4 1.9m 1u 1u 100u)
SYMATTR InstName I2
SYMBOL cap -1328 512 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C7
SYMATTR Value 470p
SYMBOL voltage -2464 -544 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap -1408 -368 R0
WINDOW 3 -55 29 Left 2
SYMATTR Value 0.1
SYMATTR InstName C8
SYMBOL voltage -2912 -64 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
WINDOW 3 39 48 Left 2
WINDOW 0 39 20 Left 2
SYMATTR Value PWL(500u 0 500.001u 5 3000u 5 3000.001u 0)
SYMATTR InstName V6
SYMBOL LT7184S -1856 -128 R0
SYMATTR InstName U1
SYMBOL ind -1360 -288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 470n
SYMATTR SpiceLine Rser=2.5m
FLAG -2464 -432 0
FLAG -1392 256 0
FLAG -1392 176 0
FLAG -1504 256 VDD18
FLAG -1504 176 DRVCC
FLAG -1392 336 0
FLAG -1504 336 INTVCC
FLAG -1264 16 EXTVCC
FLAG -1488 16 PGOOD1
FLAG -1488 96 _FAULT
FLAG -1312 496 0
FLAG -1520 496 ITH1
FLAG -1488 -384 BOOST1
FLAG -1504 -304 SW1
FLAG -1200 -96 0
FLAG -976 -96 0
FLAG -1184 -304 OUT1
FLAG -2448 -544 VIN
FLAG -2112 -384 BOOST0
FLAG -2096 -304 SW0
FLAG -2416 -96 0
FLAG -2912 -144 0
FLAG -2448 -304 OUT0
FLAG -2560 256 0
FLAG -2912 32 0
FLAG -2096 -64 RUN0
FLAG -2192 496 INTVCC
FLAG -2752 480 0
FLAG -2720 336 CLK_EXT
FLAG -2112 336 SYNC
FLAG -2528 432 0
FLAG -2112 176 _ALERT
FLAG -2112 16 PGOOD0
FLAG -2112 96 _FAULT
FLAG -2112 256 EXTVCC
FLAG -2320 416 EXTVCC
FLAG -1904 640 0
FLAG -1712 640 0
FLAG -1440 -64 PGOOD0
FLAG -1072 -96 0
FLAG -2512 -96 0
FLAG -2144 416 SHARE_CLK
TEXT -1104 600 Left 2 !.tran 3.6m startup
TEXT -528 -600 Left 2 ;NOTES FOR SIMULATION\n \nPlease read the following notes carefully since the model behaves differently from the user \ninterface for the LT7184S_verify_2025JUN11v1.\n \n(1) PMBus communication and memory address related functions and pins are not modeled, \nincluding SDA, SCL, WP.  \n(2) Changes to parameter values while the simulation is running will not take effect unless the\nsimulation is stopped and restarted. This is different from the way the part operates which will\nrespond to the changes while running.  \n(3) Resistor Configuration pins are not modelled. \n(4) Initialization time is not modelled.  After power is applied to PVIN0 or EXTVCC, the real LT7184S_verify_2025JUN11v1\nrequires 13ms (typical) before power conversion or communication can begin.\n(5) Default Fault Response is only modelled (VIN_OV_Fault, Vout_OV_Fault: Immediate off, Infinite retry (10ms retry time), Other Faults: Ignore)\n    The LT7184S_verify_2025JUN11v1 offers different fault response possibility for different faults and programmable retry time\n(6) SHARE_CLK: Default behaviour is modelled ( SHARE_CLK Pulls low when VIN falls below VIN_OFF, Output will be disabled if SHARE_CLK held low)\n \n \nDESCRIPTION OF PARAMETERS\n \nThe following parameters can be defined by right-clicking on the LT7184S_verify_2025JUN11v1 symbol.\nThe nomenclature used here differs from the one in the data sheet. If any value of these parameters is\nset beyond the scope described in the data sheet, the resulting simulation will not be meaningful.:\n \nFREQUENCY_SWITCH -- in Hz, sets switching frequency for both channels\n \nThe parameters below are set independantly for each channel (0 and 1): \nVOUT_COMMAND_n -- in volt, sets output voltage\n \nTON_DELAY_n & TON_RISE_n -- in sec, set turn-on delay and soft-start time\nTOFF_DELAY_n & TOFF_FALL_n -- in sec, set turn-off delay and soft-off time \n \nIlim_range_n -- selects inductor valley current limit option:\n   0 positive valley current limit of 4A, negative valley current limit of -3.5A\n   1 positive valley current limit of 7A, negative valley current limit of -6A\n   2 positive valley current limit of 9A, negative valley current limit of -7.5A\n   3 positive valley current limit of 9A, negative valley current limit of -9A         \n \nPulseSkipMode_n --sets operation mode: 1 for pulse skip mode, 0 for forced continuous conduction mode\n \n \n \nGMEA_control_n --Sets Error Amp parameters, x=0 to 7\n     GmEA = 0.15mS*(x+1)*(1+3*HPLV_n)  (relative to VSENSE)\n \nHPLV_n -- if set to 1, selects High-Performance Low-Vout mode (max 1.375Vout, GMEA is 4X higher)\n \nRITH_n --in ohm, programmable internal compensation\n \nCITH_n --in Farad, programmable internal compensation\n \nMFR_PWM_PHASE_n -- in degree, sets the channel phase delay in 15-degree increments \n                                        (this is relative to the SYNC  input clock if present).\nMFR_DISCHARGE_THRESHOLD--Output voltage threshold to determine that the output has decayed sufficiently to reenable the channel\n \n \nVout_UV_Fault_Limit and Vout_OV_Fault_Limit --- in volt, set the fault limits for the PGOOD and /FAULT outputs\n      Note channel shuts down if VOUT OV FAULT occurs, or VIN>17.6V, or /FAULT pin is pulled low externally\nVout_UV_Warn_Limit and Vout_OV_Warn_Limit-- in volt, set the warning limit for the /ALERT output\n \nEN_SYNC_OUT ---1 Output SYNC Pulses, 0 SYNC works as input.\n \n \n \nTo simulate parallel operation \n \nTie RUN, VIN, SHARE_CLK, _FAULT, _ALERT, PGOOD, ITH pins of all the channels together\nset EN_SYNC_OUT = 1 for only one channel and set EN_SYNC_OUT = 0 for all other channel\nThe parameters set in all the channels should be identical other than EN_SYNC_OUT