Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\65d5f253c403_zener_diode.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N001 470
V1 N001 0 12
D1 0 N002 D1N4733A
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model D1N4733A D(Bv=5.1 Ibv=5u Rs=1 N=1.2 Cjo=50p M=0.333)
.dc V1 0 12 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1152 680
WIRE 128 112 32 112
WIRE 336 112 208 112
WIRE 32 144 32 112
WIRE 336 176 336 112
WIRE 32 272 32 224
WIRE 336 272 336 240
WIRE 336 272 32 272
WIRE 336 320 336 272
SYMBOL res 224 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 470
SYMBOL voltage 32 128 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL zener 352 240 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value D1N4733A
FLAG 336 320 0
TEXT 352 280 Left 2 !.model D1N4733A D(Bv=5.1 Ibv=5u Rs=1 N=1.2 Cjo=50p M=0.333)
TEXT 40 296 Left 2 !.dc V1 0 12 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\10c4e24592a4_questo2v1.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N002 0 3300
R1 N001 N002 5600
V1 N001 0 10
R3 N002 0 2200
.tran 0 10 0 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 32 48 32
WIRE 304 32 208 32
WIRE 464 32 304 32
WIRE 672 32 544 32
WIRE 48 160 48 32
WIRE 304 176 304 32
WIRE 48 400 48 240
WIRE 304 400 304 256
WIRE 304 400 48 400
WIRE 672 400 672 32
WIRE 672 400 304 400
WIRE 48 448 48 400
SYMBOL voltage 48 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 448 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 3300
SYMBOL res 112 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 5600
SYMBOL res 288 160 R0
SYMATTR InstName R3
SYMATTR Value 2200
FLAG 48 448 0
TEXT 8 472 Left 2 !.tran 0 10 0 10
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1375.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1375.asy)
C1 N001 N003 .1
L1 N003 OUT 10 Rser=0.02 Rpar=5000
R1 N006 0 4.99K
XU1 N001 IN N003 N002 MP_01 0 N006 N005 LT1375 top=1K bot=1T ;pnba Boost)Vin)SW)_SHDN))GND)FB)Vc
R3 N005 N004 1K
C2 OUT 0 100 Rser=0.05
D1 0 N003 MBRS340
C4 N004 0 10n
R2 OUT N006 5.36K
V1 IN 0 6.2
D2 OUT N001 1N4148
Rload OUT 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT1375.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2372 1144
WIRE 1328 672 1120 672
WIRE 1584 672 1456 672
WIRE 1664 672 1584 672
WIRE 1776 672 1728 672
WIRE 1120 688 1120 672
WIRE 1328 704 1328 672
WIRE 1456 704 1456 672
WIRE 1584 704 1584 672
WIRE 1120 784 1120 768
WIRE 1248 784 1232 784
WIRE 1584 784 1584 768
WIRE 1584 784 1536 784
WIRE 1664 784 1584 784
WIRE 1776 784 1776 672
WIRE 1776 784 1744 784
WIRE 1888 784 1776 784
WIRE 2000 784 1888 784
WIRE 1584 800 1584 784
WIRE 1776 800 1776 784
WIRE 1888 800 1888 784
WIRE 2000 800 2000 784
WIRE 1584 880 1584 864
WIRE 1888 896 1888 864
WIRE 2000 896 2000 880
WIRE 1072 912 1056 912
WIRE 1152 912 1136 912
WIRE 1248 912 1232 912
WIRE 1776 912 1776 880
WIRE 1776 912 1536 912
WIRE 1776 928 1776 912
WIRE 1392 1008 1392 992
WIRE 1776 1024 1776 1008
SYMBOL DIODE 1728 656 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL res 1248 896 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL POLCAP 1872 800 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.05
SYMBOL RES 1760 912 R0
SYMATTR InstName R1
SYMATTR Value 4.99K
SYMBOL schottky 1568 864 M180
WINDOW 0 36 54 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL cap 1136 896 R90
WINDOW 3 32 32 VTop 2
WINDOW 0 0 32 VBottom 2
SYMATTR Value 10n
SYMATTR InstName C4
SYMBOL IND 1648 800 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL res 1760 784 R0
SYMATTR InstName R2
SYMATTR Value 5.36K
SYMBOL POWERPRODUCTS\\LT1375 1392 848 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1120 672 R0
SYMATTR InstName V1
SYMATTR Value 6.2
SYMBOL POLCAP 1568 704 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 1984 784 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 1776 1024 0
FLAG 1584 880 0
FLAG 2000 896 0
FLAG 1888 896 0
FLAG 1392 1008 0
FLAG 1120 784 0
FLAG 1056 912 0
FLAG 2000 784 OUT
FLAG 1120 672 IN
TEXT 1520 1032 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2fbe4595deef_FFinputBlock2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 D 0 PWL(0 0 2.25m 0 2.250001m 5 5.1m 5 5.10001m 0 5.4m 0 5.40001m 5 5.7m 5 5.70001m 0 6.3m 0 6.30001m 5 6.6m 5 6.60001m 0)
V2 CLK 0 PULSE(0 5 0 1n 1n 0.5m 1m)
.tran 8.1m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1.1
SHEET 1 1864 680
WIRE 272 -64 192 -64
WIRE 192 -16 192 -64
WIRE 272 128 192 128
WIRE 192 160 192 128
FLAG 192 240 0
FLAG 192 64 0
FLAG 272 128 CLK
IOPIN 272 128 Out
FLAG 272 -64 D
IOPIN 272 -64 Out
SYMBOL voltage 192 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 2.25m 0 2.250001m 5 5.1m 5 5.10001m 0 5.4m 0 5.40001m 5 5.7m 5 5.70001m 0 6.3m 0 6.30001m 5 6.6m 5 6.60001m 0)
SYMBOL voltage 192 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1n 1n 0.5m 1m)
TEXT 152 264 Left 2 !.tran 8.1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-5.0.asy)
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
V1 IN 0 3.3
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-5.0 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
Rload OUT 0 50
.tran 400u startup
.lib ADP2504-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2504-5.0 176 176 R0
SYMATTR InstName U1
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 392 384 Left 2 !.tran 400u startup
TEXT 176 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\33b0a869ae3d_R2.asc
* Generated by LTspice 26.0.1 for Windows.
M_P dp N001 sp sp P_1u l={Lp2} w={Wp2}
vdp dp 0
VinP N001 0 0 AC 1
vdd sp 0 1.1367383
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.inc cmosedu_models.txt
.dc vdp -2.5 2.5 0.0001
.meas id_p_1 FIND Id(M_P) AT -1.3427744+0.05
.meas id_p_2 FIND Id(M_P) AT -1.3427744-0.05
.param Wp=49.992332u Lp=49.986531u Wp2=49.998294u Lp2=9.069192u Wn=41.548244u Ln=47.775368u Wn2=49.906981u Ln2=28.964298u C=0.100001p Iref=10892.687537n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1932 680
WIRE 512 -48 512 -128
WIRE 592 -48 512 -48
WIRE 464 -32 336 -32
WIRE -16 -16 -16 -48
WIRE 160 -16 160 -48
WIRE 336 -16 336 -32
WIRE 592 0 592 -48
WIRE 592 0 512 0
WIRE 512 80 512 48
WIRE -16 128 -16 64
WIRE 160 128 160 64
WIRE 336 128 336 64
SYMBOL voltage 160 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 24 44 Left 2
SYMATTR Value ""
SYMATTR InstName vdp
SYMBOL voltage 336 -32 R0
WINDOW 3 25 87 Left 2
WINDOW 123 25 115 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMATTR InstName inP
SYMBOL voltage -16 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 25 97 Left 2
SYMATTR Value 1.1367383
SYMATTR InstName vdd
SYMBOL pmos4 464 48 M180
SYMATTR InstName M_P
SYMATTR Value P_1u
SYMATTR Value2 l={Lp2} w={Wp2}
FLAG 512 -128 sp
FLAG 336 128 0
FLAG 160 128 0
FLAG 160 -48 dp
FLAG 512 80 dp
FLAG -16 128 0
FLAG -16 -48 sp
TEXT -48 224 Left 2 !.inc cmosedu_models.txt
TEXT -48 272 Left 2 !.dc vdp -2.5 2.5 0.0001
TEXT -48 176 Left 2 !.meas id_p_1 FIND Id(M_P) AT -1.3427744+0.05
TEXT -48 200 Left 2 !.meas id_p_2 FIND Id(M_P) AT -1.3427744-0.05
TEXT -264 248 Left 2 !.param Wp=49.992332u Lp=49.986531u Wp2=49.998294u Lp2=9.069192u Wn=41.548244u Ln=47.775368u Wn2=49.906981u Ln2=28.964298u C=0.100001p Iref=10892.687537n
* Z:\home\khalils\Downloads\files\data\raw_asc\24e3cf5706e8_Comparator_with_hysteresis.asc
* Generated by LTspice 26.0.1 for Windows.
* Comparator with hysteresis
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8552.asy)
XU1 REF1 IN1 Vcc 0 OUT AD8552 ;pnba In+)In-)V+)V-)OUT
V1 N001 0 PWL(0 3.6 1 2.5 2 2.5 3 2.5 4 2.5 5 3.6 6 3.7 7 3.7 8 3.8 9 3.9)
R1 N001 IN1 220k
R2 IN1 0 180k
R3 OUT REF1 150k
R5 Vcc REF1 32k
V2 Vcc 0 5
R4 REF1 0 10k
.tran 0 10 0 0.001
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 948 680
WIRE 256 176 128 176
WIRE 880 176 736 176
WIRE 256 192 256 176
WIRE 880 192 880 176
WIRE 128 272 128 176
WIRE 464 272 464 256
WIRE 736 272 736 176
WIRE 256 288 256 272
WIRE 432 288 256 288
WIRE 256 304 256 288
WIRE 576 304 496 304
WIRE 624 304 576 304
WIRE 880 304 880 272
WIRE 352 320 352 256
WIRE 432 320 352 320
WIRE 256 336 256 304
WIRE 880 336 880 304
WIRE 464 352 464 336
WIRE 352 384 352 320
WIRE 528 384 352 384
WIRE 624 384 624 304
WIRE 624 384 608 384
WIRE 128 432 128 352
WIRE 256 432 256 416
WIRE 256 432 128 432
WIRE 736 432 736 352
WIRE 736 432 256 432
WIRE 880 432 880 416
WIRE 880 432 736 432
WIRE 880 448 880 432
SYMBOL res 624 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 150k
SYMBOL OpAmps\\AD8552 464 240 R0
WINDOW 0 42 -11 Left 2
WINDOW 3 42 12 Left 2
SYMATTR InstName U1
SYMBOL res 864 176 R0
SYMATTR InstName R5
SYMATTR Value 32k
SYMBOL voltage 128 256 R0
WINDOW 3 -17 221 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PWL(0 3.6 1 2.5 2 2.5 3 2.5 4 2.5 5 3.6 6 3.7 7 3.7 8 3.8 9 3.9)
SYMATTR InstName V1
SYMBOL res 240 320 R0
SYMATTR InstName R2
SYMATTR Value 180k
SYMBOL res 240 176 R0
SYMATTR InstName R1
SYMATTR Value 220k
SYMBOL voltage 736 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 896 320 M0
SYMATTR InstName R4
SYMATTR Value 10k
FLAG 736 176 Vcc
FLAG 880 304 REF1
FLAG 464 256 Vcc
FLAG 464 352 0
FLAG 880 448 0
FLAG 352 256 REF1
FLAG 576 304 OUT
FLAG 256 304 IN1
TEXT 128 104 Left 2 ;Comparator with hysteresis
TEXT 128 136 Left 2 !.tran 0 10 0 0.001
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2108-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2108-3.0.asy)
L1 N001 OUT 1
C1 OUT 0 10
Rload OUT 0 8
V1 IN 0 5
XU1 IN IN N001 OUT 0 ADP2108-x.x Rtop=400K ;pnba Vin)EN)SW)FB)GND
.tran .5m startup
.lib ADP2108-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 144
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL ADP2108-3.0 352 224 R0
SYMATTR InstName U1
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 8
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 568 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3402.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3402.asy)
R3 N005 0 549K
R2 N004 N003 82K
R1 N006 0 30K
C3 OUT 0 22 Rser=.1
Rload OUT 0 6
R6 IN N002 100K
XU1 N006 0 IN N001 0 N002 OUT N005 N004 IN LTC3402 ;pnba Rt)MODE)Vin)SW)GND)Pgood)Vout)FB)Vc)_SHDN
R4 OUT N005 909K
C1 N003 0 470p
V1 IN 0 3
L1 IN N001 2.2
C2 N004 0 4.7p
.tran 250u startup
.lib LTC3402.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2588 1768
WIRE 1568 1248 1472 1248
WIRE 1664 1248 1568 1248
WIRE 1792 1248 1664 1248
WIRE 1824 1248 1792 1248
WIRE 1952 1248 1904 1248
WIRE 1472 1264 1472 1248
WIRE 1792 1296 1792 1248
WIRE 1952 1296 1952 1248
WIRE 1568 1344 1568 1248
WIRE 1472 1360 1472 1344
WIRE 1664 1376 1664 1248
WIRE 1696 1376 1664 1376
WIRE 2176 1376 2048 1376
WIRE 2288 1376 2176 1376
WIRE 2384 1376 2288 1376
WIRE 2176 1392 2176 1376
WIRE 2288 1392 2288 1376
WIRE 2384 1392 2384 1376
WIRE 1568 1440 1568 1424
WIRE 1696 1440 1568 1440
WIRE 2288 1488 2288 1456
WIRE 2384 1488 2384 1472
WIRE 1488 1504 1440 1504
WIRE 1584 1504 1568 1504
WIRE 1696 1504 1584 1504
WIRE 2176 1504 2176 1472
WIRE 2176 1504 2048 1504
WIRE 1440 1520 1440 1504
WIRE 1584 1520 1584 1504
WIRE 2176 1520 2176 1504
WIRE 1696 1568 1680 1568
WIRE 2080 1568 2048 1568
WIRE 2080 1584 2080 1568
WIRE 1440 1600 1440 1584
WIRE 1584 1600 1584 1584
WIRE 2176 1616 2176 1600
WIRE 1872 1664 1872 1648
WIRE 2080 1680 2080 1664
SYMBOL RES 2064 1568 R0
SYMATTR InstName R1
SYMATTR Value 30K
SYMBOL cap 1424 1520 R0
SYMATTR InstName C1
SYMATTR Value 470p
SYMBOL polcap 2272 1392 R0
SYMATTR InstName C3
SYMATTR Value 22
SYMATTR SpiceLine Rser=.1
SYMBOL cap 1568 1520 R0
SYMATTR InstName C2
SYMATTR Value 4.7p
SYMBOL res 2160 1376 R0
SYMATTR InstName R4
SYMATTR Value 909K
SYMBOL res 2368 1376 R0
SYMATTR InstName Rload
SYMATTR Value 6
SYMBOL PowerProducts\\LTC3402 1872 1472 R0
SYMATTR InstName U1
SYMBOL ind 1808 1264 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res 1584 1488 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 82K
SYMBOL res 1552 1328 R0
SYMATTR InstName R6
SYMATTR Value 100K
SYMBOL res 2160 1504 R0
SYMATTR InstName R3
SYMATTR Value 549K
SYMBOL VOLTAGE 1472 1248 R0
SYMATTR InstName V1
SYMATTR Value 3
FLAG 1872 1664 0
FLAG 2080 1680 0
FLAG 1584 1600 0
FLAG 1440 1600 0
FLAG 1472 1360 0
FLAG 2176 1616 0
FLAG 2288 1488 0
FLAG 2384 1488 0
FLAG 1680 1568 0
FLAG 2384 1376 OUT
FLAG 1472 1248 IN
TEXT 2296 1696 Left 2 !.tran 250u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0fd7fd881807_6244.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 2.5
V2 -V 0 -2.5
XU1 IN OUT +V -V OUT LTC6244 ;pnba IN+)IN-)VCC)VEE)OUT
V3 IN 0 PULSE(-1 1 0 1n 1n 10u 20u)
.tran 100u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6244.asy)
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 256 208 256
WIRE 208 336 208 256
WIRE 256 336 208 336
WIRE 384 352 384 256
WIRE 384 352 320 352
WIRE 416 352 384 352
WIRE 256 368 144 368
WIRE -80 384 -80 368
WIRE 32 384 32 368
WIRE 144 384 144 368
WIRE 288 400 288 384
WIRE -80 480 -80 464
WIRE 32 480 32 464
WIRE 144 480 144 464
FLAG -80 480 0
FLAG 32 480 0
FLAG -80 368 +V
FLAG 144 480 0
FLAG 144 368 IN
FLAG 416 352 OUT
FLAG 288 320 +V
FLAG 32 368 -V
FLAG 288 400 -V
SYMBOL voltage -80 368 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage 32 368 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL LTC6244 288 352 R0
SYMATTR InstName U1
SYMBOL voltage 144 368 R0
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 1n 1n 10u 20u)
TEXT 384 560 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\5f59fa59019a_3_jikken_ic_ib.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 C B 0 0 2SC1815-Y
V1 C 0 10V
I1 0 B 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc oct I1 1p 400u 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 592 -112 272 -112
WIRE 272 128 272 -112
WIRE 272 144 272 128
WIRE 192 192 -96 192
WIRE 208 192 192 192
WIRE 592 192 592 -112
WIRE 272 256 272 240
WIRE -96 272 -96 192
WIRE -96 496 -96 352
WIRE 272 496 272 256
WIRE 592 496 592 272
SYMBOL voltage 592 176 R0
SYMATTR InstName V1
SYMATTR Value 10V
SYMBOL npn 208 144 R0
WINDOW 0 65 35 Left 2
SYMATTR InstName Q1
SYMATTR Value 2SC1815-Y
SYMBOL current -96 352 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 0
FLAG -96 496 0
FLAG 272 496 0
FLAG 592 496 0
FLAG 272 256 E
FLAG 272 128 C
FLAG 192 192 B
TEXT -80 -24 Left 2 !.dc oct I1 1p 400u 100
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3225-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Note: \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capacitance is scaled down from its real value;\n2. Load capacitor initial condion can be given to represent the specific \nresidual voltage at the beginning of the charging.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3225-1.asy)
V1 IN 0 2.7
XU1 N001 N002 N004 IN NC_01 0 N003 0 IN OUT LTC3225-1 ;pnba C+)C-)Cx)_SHDN)Pgood)Vsel)Prog)GND)Vin)Cout
C1 N001 N002 1
R1 N003 0 12K
C2 OUT N004 .1m ic=1.5
C3 N004 0 .3m ic=1.2
.tran 2m startup
.lib LTC3225-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 680
WIRE 112 0 16 0
WIRE 240 0 112 0
WIRE 240 16 240 0
WIRE 16 32 16 0
WIRE 112 80 112 0
WIRE 128 80 112 80
WIRE 400 80 352 80
WIRE 400 96 400 80
WIRE 16 144 16 112
WIRE 400 176 400 160
WIRE 400 176 352 176
WIRE 128 272 112 272
WIRE 400 272 352 272
WIRE 400 288 400 272
WIRE 32 368 16 368
WIRE 128 368 112 368
WIRE 400 368 400 352
WIRE 400 368 352 368
WIRE 400 384 400 368
WIRE 240 448 240 432
WIRE 400 464 400 448
SYMBOL cap 384 384 R0
SYMATTR InstName C3
SYMATTR Value .3m ic=1.2
SYMBOL cap 384 288 R0
SYMATTR InstName C2
SYMATTR Value .1m ic=1.5
SYMBOL cap 384 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\LTC3225-1 240 224 R0
SYMATTR InstName U1
SYMBOL voltage 16 16 R0
SYMATTR InstName V1
SYMATTR Value 2.7
SYMBOL res 128 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 12K
FLAG 240 448 0
FLAG 16 144 0
FLAG 400 464 0
FLAG 16 368 0
FLAG 112 272 0
FLAG 16 0 IN
FLAG 400 272 OUT
TEXT 552 456 Left 2 !.tran 2m startup
TEXT -72 472 Left 2 ;Note: \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capacitance is scaled down from its real value;\n2. Load capacitor initial condion can be given to represent the specific \nresidual voltage at the beginning of the charging.
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8017.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 2.5
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -2.5
Rload OUT 0 10K
XU1 IN N001 +V -V OUT AD8017 ;pnba 1)2)61)99)50
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8017.asy)
.lib AD8017.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1240 700
WIRE -16 -1056 -32 -1056
WIRE 80 -1056 64 -1056
WIRE 96 -1056 80 -1056
WIRE 192 -1056 176 -1056
WIRE -256 -944 -256 -960
WIRE -144 -944 -144 -960
WIRE 80 -944 80 -1056
WIRE 96 -944 80 -944
WIRE 192 -928 192 -1056
WIRE 192 -928 160 -928
WIRE 320 -928 192 -928
WIRE 96 -912 -16 -912
WIRE 320 -912 320 -928
WIRE -16 -896 -16 -912
WIRE -256 -848 -256 -864
WIRE -144 -848 -144 -864
WIRE 320 -816 320 -832
WIRE -16 -800 -16 -816
FLAG -256 -960 +V
FLAG -256 -848 0
FLAG -16 -800 0
FLAG 320 -928 OUT
FLAG -16 -912 IN
FLAG 128 -960 +V
FLAG -144 -960 -V
FLAG 128 -896 -V
FLAG -32 -1056 0
FLAG 320 -816 0
FLAG -144 -848 0
SYMBOL voltage -256 -960 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage -16 -912 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 80 -1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 192 -1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage -144 -960 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 304 -928 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL AD8017 128 -992 R0
SYMATTR InstName U1
TEXT 336 -720 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\2343ac5ffc03_Draft5.asc
* Generated by LTspice 26.0.1 for Windows.
R1 2 4 20
R2 5 4 10
R3 2 1 20
R5 0 4 10
I1 3 2 6
V1 5 1 70
V2 1 0 10
R4 3 0 2
.dc v1 70 70 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 32 0 32
WIRE 480 32 288 32
WIRE 0 112 0 32
WIRE 48 112 0 112
WIRE 160 112 128 112
WIRE 176 112 160 112
WIRE 288 112 256 112
WIRE 352 112 288 112
WIRE 480 112 480 32
WIRE 480 112 432 112
WIRE 0 176 0 112
WIRE 288 192 288 112
WIRE 480 192 480 112
WIRE 0 368 0 256
WIRE 288 368 288 272
WIRE 288 368 0 368
WIRE 320 368 288 368
WIRE 480 368 480 272
WIRE 480 368 400 368
FLAG 288 368 0
FLAG 288 112 1
FLAG 480 112 2
FLAG 480 368 3
FLAG 0 112 4
FLAG 160 112 5
SYMBOL res 304 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 20
SYMBOL res 144 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL res 448 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 20
SYMBOL res 16 272 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL current 480 272 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 6
SYMBOL voltage 160 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 70
SYMBOL voltage 288 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL res 416 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 2
TEXT -52 418 Left 2 !.dc v1 70 70 1