* Z:\home\khalils\Downloads\files\data\raw_asc\3d19cbd891a5_tape.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N002 0 SINE(0 1 10000 0 0 0)
R1 N002 0 10000
C1 N003 N002 100nF
R2 N001 N003 5700
R3 N003 0 10000
Q1 N001 N003 N005 0 NPN
R4 N005 0 47000
V2 N001 0 3.3
A1 0 0 N005 0 0 0 N004 0 AND
Q2 N001 N007 N008 0 NPN
C2 N009 N008 4700nF
R5 N008 N008 240
R6 N008 N008 2200
V3 N006 0 PULSE(0 3.3 0 0 0 0.00005 0.0001 1000)
R7 N010 0 4700
R8 N007 N006 270
R9 N010 N009 240
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.0005s
* Good info here: http://www.zxdesign.info/cassette.shtml
* ds099.pdf p61:
* LVTTL/LVCMOS33, V_IL < 0.8V, V_IH > 2.0V
* LVCMOS25, V_IL < 0.7V, V_IH > 1.7V
* Output, want at least 1.2V swing centred on 1.4V\nBefore transistor, want 1.2V swing centred on 2.1V\nR3=R2/(vin/vout-1)=R2/(3.3/2.1-1)=1.75*R2\nR2=R3(vin/vout-1)=R3(1.5714-1)=0.5714*R3
* C1 should really be about 4.uF
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1736 980
WIRE 848 -240 832 -240
WIRE 848 -224 848 -240
WIRE 752 -80 752 -240
WIRE 752 -80 560 -80
WIRE 864 -80 752 -80
WIRE 560 -16 560 -80
WIRE 752 16 752 -80
WIRE 240 64 -80 64
WIRE 352 64 240 64
WIRE 560 64 416 64
WIRE 688 64 560 64
WIRE 1216 112 1040 112
WIRE 752 128 752 112
WIRE 976 128 752 128
WIRE -80 144 -80 64
WIRE 240 144 240 64
WIRE 560 224 560 144
WIRE 752 224 752 208
WIRE 752 224 560 224
WIRE 752 288 752 224
WIRE 864 432 864 -80
WIRE 864 432 128 432
WIRE 128 624 128 432
WIRE -160 672 -192 672
WIRE -48 672 -80 672
WIRE 64 672 32 672
WIRE 192 720 128 720
WIRE 304 720 192 720
WIRE -192 736 -192 672
WIRE 192 816 192 800
WIRE 304 816 304 720
WIRE 304 816 192 816
WIRE 320 816 304 816
WIRE 448 816 384 816
WIRE 976 816 528 816
WIRE 192 832 192 816
WIRE 976 832 976 816
WIRE 192 944 192 912
WIRE 304 944 304 816
WIRE 304 944 192 944
WIRE 976 960 976 912
FLAG -80 224 0
FLAG 240 224 0
FLAG 752 288 0
FLAG 848 -224 0
FLAG -192 736 0
FLAG 976 960 0
SYMBOL voltage -80 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 10000 0 0 0)
SYMBOL res 224 128 R0
SYMATTR InstName R1
SYMATTR Value 10000
SYMBOL cap 416 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100nF
SYMBOL res 544 -32 R0
SYMATTR InstName R2
SYMATTR Value 5700
SYMBOL res 544 48 R0
SYMATTR InstName R3
SYMATTR Value 10000
SYMBOL npn 688 16 R0
SYMATTR InstName Q1
SYMBOL res 736 112 R0
SYMATTR InstName R4
SYMATTR Value 47000
SYMBOL voltage 736 -240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL Digital\\and 1008 64 R0
SYMATTR InstName A1
SYMBOL npn 64 624 R0
SYMATTR InstName Q2
SYMBOL cap 384 800 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4700nF
SYMBOL res 176 704 R0
SYMATTR InstName R5
SYMATTR Value 240
SYMBOL res 176 816 R0
SYMATTR InstName R6
SYMATTR Value 2200
SYMBOL voltage -64 672 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 3.3 0 0 0 0.00005 0.0001 1000)
SYMBOL res 960 816 R0
SYMATTR InstName R7
SYMATTR Value 4700
SYMBOL res 48 656 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 270
SYMBOL res 544 800 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 240
TEXT -112 248 Left 2 !.tran 0.0005s
TEXT -224 -240 Left 2 ;Good info here: http://www.zxdesign.info/cassette.shtml
TEXT -216 -168 Left 2 ;ds099.pdf p61:
TEXT -88 -136 Left 2 ;LVTTL/LVCMOS33, V_IL < 0.8V, V_IH > 2.0V
TEXT -8 -104 Left 2 ;LVCMOS25, V_IL < 0.7V, V_IH > 1.7V
TEXT 1080 -232 Left 2 ;Output, want at least 1.2V swing centred on 1.4V\nBefore transistor, want 1.2V swing centred on 2.1V\nR3=R2/(vin/vout-1)=R2/(3.3/2.1-1)=1.75*R2\nR2=R3(vin/vout-1)=R3(1.5714-1)=0.5714*R3
TEXT 184 0 Left 2 ;C1 should really be about 4.uF