* Z:\home\khalils\Downloads\files\data\raw_asc\01a1ad6d7bbf_AD4001_THDS_V00.asc
* Generated by LTspice 26.0.1 for Windows.
* Anti-Aliasing Filter
* Driver Supply
* ADC Supply
* ADC Driver
* Simulation Setup
* Simulation Parameters
* Anti Aliasing Filter
* Simulation cycles\nSample size\nADC reference voltage\nADC supply\nDriver VCC\nDriver VEE\nDC offset voltage\nSample frequency\nSample Period\nInput frequency\nInput amplitude\nMax time step\nSimulation end
* Rval1\nCval1\nRval2\nCval2
* Input
* Driver Parameters
* U2 Rf\nU2 Rg
* AD4001_THDS_V00
* This circuit may be used to obtain THD results for the AD4001 series differential ADC\n using the AD4003 macro-model with an AD4807-2 driver in a non-inverting single ended configuration.\n Additional driver models may be inserted via the component menu. Schematic redraw may\n be required. Simulation results produced by the .four SPICE command may be accessed by \nview->SPICE error log and are displayed at the end of the file. For all other performance \ncharacteristics and specifications refer to the AD4001 datasheet located at\nhttps://www.analog.com/en/products/ad4001.html#product-overview
* Library below included based on ModelFile attribute of instance XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4003.asy)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4807-2.asy)
V7 VCC 0 {vcc_val}
R6 N005 N001 {Rg_val}
V8 VEE 0 {vee_val}
C2 ADCINN 0 {Cval2}
V9 VDD 0 {vdd_val}
R1 ADCINP N001 {Rval1}
XU2 N003 N005 VCC VEE N004 VCC ADA4807 ;pnba 100)101)102)103)104)106
V2 N003 0 {voff}
R4 N004 N005 {Rf_val}
V6 REF 0 {vref_val}
C1 ADCINP 0 {Cval1}
V4 N002 0 PULSE(0 {vdd_val} 1u 1n 1n 10n {ts})
V1 VINP 0 SINE({voff} {vmag} {fin} 0 0 0)
XU1 VINP N001 VCC VEE N001 VCC ADA4807 ;pnba 100)101)102)103)104)106
XU3 REF VDD ADCINP MP_01 0 ADCINN VSAMPLED N002 AD4003 EN_Hi_Z=1 ;pnba REF)Vdd)IN+))GND)IN-)Vout)CNV
R2 ADCINN N004 {Rval2}
.param M=3
.param N=4096
.param vref_val=5
.param vdd_val=1.8
.param vcc_val=15
.param vee_val=-15
.param voff=vref_val/{2}
.param fs=2e6
.param ts=1/fs
.param fin= fs*M/N
.param vmag=.93*vref_val/2
.param tmax=1/(fs)
.param END_SIM=M*(1/fin)
.save v(vsampled)
.option plotwinsize=0 numdgt=15
.four {fin} 5 -1 v(vsampled)
.param Rval1=200
.param Cval1=180p
.param Rval2=Rval1
.param Cval2=Cval1
.tran 0 {END_SIM+1/fin} {1/fin} {tmax}
.param Rf_val=500
.param Rg_val=500
.lib AD4003.sub
.lib ADA4807.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3184 1252
WIRE 528 -320 400 -320
WIRE 624 -320 528 -320
WIRE -512 -256 -704 -256
WIRE 400 -256 400 -320
WIRE -608 -128 -608 -160
WIRE -704 -112 -704 -256
WIRE -624 -112 -704 -112
WIRE 400 -112 400 -176
WIRE -512 -96 -512 -256
WIRE -512 -96 -560 -96
WIRE -448 -96 -512 -96
WIRE -304 -96 -448 -96
WIRE -144 -96 -224 -96
WIRE 16 -96 -144 -96
WIRE -720 -80 -960 -80
WIRE -624 -80 -720 -80
WIRE 624 -80 624 -320
WIRE -144 -48 -144 -96
WIRE -608 -32 -608 -64
WIRE -576 -32 -576 -64
WIRE 880 -32 880 -192
WIRE 880 -32 752 -32
WIRE 16 16 16 -96
WIRE 160 16 16 16
WIRE 352 16 160 16
WIRE 352 48 352 16
WIRE 400 48 352 48
WIRE -448 64 -448 -96
WIRE -448 64 -848 64
WIRE -144 64 -144 16
WIRE -144 64 -224 64
WIRE 1024 64 752 64
WIRE 400 80 352 80
WIRE -144 112 -144 64
WIRE 160 112 16 112
WIRE 352 112 352 80
WIRE 352 112 160 112
WIRE 880 160 752 160
WIRE -960 176 -960 -80
WIRE -608 192 -608 160
WIRE -576 192 -576 160
WIRE -800 208 -816 208
WIRE -624 208 -720 208
WIRE -512 224 -560 224
WIRE -304 224 -512 224
WIRE -144 224 -144 176
WIRE -144 224 -224 224
WIRE 16 224 16 112
WIRE 16 224 -144 224
WIRE -624 240 -704 240
WIRE 624 240 624 208
WIRE -608 288 -608 256
WIRE -960 304 -960 256
WIRE -848 384 -848 64
WIRE -816 384 -848 384
WIRE -704 384 -704 240
WIRE -704 384 -736 384
WIRE -640 384 -704 384
WIRE -512 384 -512 224
WIRE -512 384 -560 384
WIRE 880 480 880 160
WIRE -2048 496 -2048 400
WIRE -1792 496 -1792 400
WIRE -1520 496 -1520 400
WIRE 880 656 880 560
WIRE -2048 672 -2048 576
WIRE -1792 672 -1792 576
WIRE -1520 672 -1520 576
IOPIN 1024 64 Out
RECTANGLE Normal 0 448 -352 -304 4
RECTANGLE Normal -1360 704 -2208 288 4
RECTANGLE Normal -368 448 -864 -304 4
RECTANGLE Normal -2208 -592 -1360 -432
RECTANGLE Normal -1360 272 -2208 -416 4
RECTANGLE Normal -880 448 -1072 -304 4
SYMBOL voltage -704 208 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value {voff}
SYMBOL res -208 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {Rval2}
SYMBOL Opamps\\ADA4807-2 -592 224 M180
SYMATTR InstName U2
SYMBOL voltage 400 -272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V6
SYMATTR Value {vref_val}
SYMBOL res -208 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {Rval1}
SYMBOL voltage -1792 480 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V8
SYMATTR Value {vee_val}
SYMBOL voltage 880 464 R0
WINDOW 3 58 -156 VRight 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 {vdd_val} 1u 1n 1n 10n {ts})
SYMATTR InstName V4
SYMBOL voltage -960 160 R0
WINDOW 0 -32 56 VBottom 2
WINDOW 3 -46 -162 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE({voff} {vmag} {fin} 0 0 0)
SYMBOL voltage -2048 480 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V7
SYMATTR Value {vcc_val}
SYMBOL voltage -1520 480 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V9
SYMATTR Value {vdd_val}
SYMBOL ADC\\AD4003 656 64 R0
SYMATTR InstName U3
SYMBOL res -720 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value {Rg_val}
SYMBOL res -544 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {Rf_val}
SYMBOL cap -160 -48 R0
SYMATTR InstName C1
SYMATTR Value {Cval1}
SYMBOL Opamps\\ADA4807-2 -592 -96 R0
SYMATTR InstName U1
SYMBOL cap -128 176 R180
WINDOW 0 -22 54 Left 2
WINDOW 3 -59 -2 Left 2
SYMATTR InstName C2
SYMATTR Value {Cval2}
FLAG 624 240 0
FLAG 880 -192 VDD
FLAG 160 16 ADCINP
FLAG 160 112 ADCINN
FLAG 880 656 0
FLAG 528 -320 REF
FLAG -224 64 0
FLAG -1792 672 0
FLAG -2048 400 VCC
FLAG -1792 400 VEE
FLAG -1520 400 VDD
FLAG -1520 672 0
FLAG -2048 672 0
FLAG -960 304 0
FLAG -720 -80 VINP
FLAG -816 208 0
FLAG 1024 64 VSAMPLED
FLAG -608 -160 VCC
FLAG -608 -32 VEE
FLAG -576 -32 VCC
FLAG -608 288 VCC
FLAG -608 160 VEE
FLAG -576 160 VCC
FLAG 400 -112 0
TEXT -264 -328 Left 2 ;Anti-Aliasing Filter
TEXT -2000 320 Left 2 ;Driver Supply
TEXT -1592 320 Left 2 ;ADC Supply
TEXT -672 -328 Left 2 ;ADC Driver
TEXT -2176 -352 Left 2 !.param M=3\n.param N=4096\n.param vref_val=5\n.param vdd_val=1.8\n.param vcc_val=15\n.param vee_val=-15\n.param voff=vref_val/{2}\n.param fs=2e6\n.param ts=1/fs\n.param fin= fs*M/N\n.param vmag=.93*vref_val/2\n.param tmax=1/(fs)\n.param END_SIM=M*(1/fin)
TEXT -2176 -456 Left 2 !.save v(vsampled)
TEXT -2176 -480 Left 2 !.option plotwinsize=0 numdgt=15
TEXT -2176 -504 Left 2 !.four {fin} 5 -1 v(vsampled)
TEXT -2176 72 Left 2 !.param Rval1=200\n.param Cval1=180p
TEXT -2176 128 Left 2 !.param Rval2=Rval1\n.param Cval2=Cval1
TEXT -2184 -560 Left 3 ;Simulation Setup
TEXT -2176 -528 Left 2 !.tran 0 {END_SIM+1/fin} {1/fin} {tmax}
TEXT -2176 -384 Left 3 ;Simulation Parameters
TEXT -2176 48 Left 2 ;Anti Aliasing Filter
TEXT -1704 -352 Left 2 ;Simulation cycles\nSample size\nADC reference voltage\nADC supply\nDriver VCC\nDriver VEE\nDC offset voltage\nSample frequency\nSample Period\nInput frequency\nInput amplitude\nMax time step\nSimulation end
TEXT -1704 80 Left 2 ;Rval1\nCval1\nRval2\nCval2
TEXT -1072 -328 Left 2 ;Input
TEXT -2176 184 Left 2 ;Driver Parameters
TEXT -2176 208 Left 2 !.param Rf_val=500\n.param Rg_val=500
TEXT -1704 216 Left 2 ;U2 Rf\nU2 Rg
TEXT -2208 -840 Left 4 ;AD4001_THDS_V00
TEXT -2208 -800 Left 2 ;This circuit may be used to obtain THD results for the AD4001 series differential ADC\n using the AD4003 macro-model with an AD4807-2 driver in a non-inverting single ended configuration.\n Additional driver models may be inserted via the component menu. Schematic redraw may\n be required. Simulation results produced by the .four SPICE command may be accessed by \nview->SPICE error log and are displayed at the end of the file. For all other performance \ncharacteristics and specifications refer to the AD4001 datasheet located at\nhttps://www.analog.com/en/products/ad4001.html#product-overview