Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\0af5aee00722_6703-2.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N003 0 N002 N001 LT6703-2 ;pnba OUT)GND)-IN)Vs
V1 N001 0 5
V2 N002 0 PULSE(390m 410m 0 .5m .5m 0 1m)
R1 N001 N003 10K
.tran 3m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT6703-2.asy)
.lib LTC6.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 32 -112 32
WIRE 336 32 208 32
WIRE -112 48 -112 32
WIRE 336 48 336 32
WIRE 208 80 208 32
WIRE 128 128 -16 128
WIRE -112 144 -112 128
WIRE 336 144 336 128
WIRE 336 144 288 144
WIRE -16 240 -16 128
WIRE 208 288 208 256
WIRE -16 336 -16 320
FLAG -112 144 0
FLAG -16 336 0
FLAG 208 288 0
SYMBOL LT6703-2 208 144 R0
SYMATTR InstName U1
SYMBOL voltage -112 32 R0
WINDOW 3 26 96 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL voltage -16 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(390m 410m 0 .5m .5m 0 1m)
SYMBOL res 320 32 R0
SYMATTR InstName R1
SYMATTR Value 10K
TEXT 416 368 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4223A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4223A.asy)
V2 VIB 0 PULSE(5 0 0 1n 1n 5u 10u)
V5 N001 0 12
V6 N002 0 12
C5 VOB 0 2n
V1 VIA 0 PULSE(0 5 0 1n 1n 5u 10u)
XU1 VIA VIB VDD1 0 0 0 VOB N002 0 VOA N001 ADuM4223A ;pnba VIA)VIB)VDD1)GND1)DISABLE)GNDB)VOB)VDDB)GNDA)VOA)VDDA
C1 0 VDD1 10n
C3 VOA 0 2n
V3 VDD1 0 5
.tran 50u
.lib ADuM4223A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1216 680
WIRE 656 16 368 16
WIRE 688 16 656 16
WIRE -48 32 -608 32
WIRE 64 32 -48 32
WIRE 688 32 688 16
WIRE -608 80 -608 32
WIRE 560 80 368 80
WIRE -48 112 -464 112
WIRE 64 112 -48 112
WIRE 688 112 688 96
WIRE 432 144 368 144
WIRE -176 192 -336 192
WIRE -64 192 -176 192
WIRE 64 192 -64 192
WIRE -608 224 -608 160
WIRE -464 224 -464 192
WIRE -336 224 -336 192
WIRE 560 224 368 224
WIRE -176 272 -176 192
WIRE -128 272 -176 272
WIRE 0 272 -64 272
WIRE 64 272 0 272
WIRE 432 288 368 288
WIRE -336 320 -336 304
WIRE 0 352 0 272
WIRE 64 352 0 352
WIRE 656 352 368 352
WIRE 688 352 656 352
WIRE 688 368 688 352
WIRE 0 384 0 352
WIRE 688 448 688 432
SYMBOL voltage -464 96 R0
WINDOW 0 20 108 Left 2
WINDOW 3 39 40 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(5 0 0 1n 1n 5u 10u)
SYMBOL cap 672 368 R0
SYMATTR InstName C5
SYMATTR Value 2n
SYMBOL cap 672 32 R0
SYMATTR InstName C3
SYMATTR Value 2n
SYMBOL voltage -336 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 560 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 12
SYMBOL cap -64 256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage -608 64 R0
WINDOW 0 30 80 Left 2
WINDOW 3 18 -5 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 1n 1n 5u 10u)
SYMBOL ADuM4223A 224 112 R0
SYMATTR InstName U1
SYMBOL voltage 560 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 12
FLAG -336 320 0
FLAG -608 224 0
FLAG -464 224 0
FLAG 688 112 0
FLAG 688 448 0
FLAG 656 352 VOB
FLAG 656 16 VOA
FLAG 0 384 0
FLAG 432 288 0
FLAG 432 144 0
FLAG -48 32 VIA
FLAG -48 112 VIB
FLAG 560 304 0
FLAG 560 160 0
FLAG -64 192 VDD1
TEXT 64 440 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\2fb018b0ef5b_Assignment_3a__i_.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 SINE(0 5 1000) Rser=0.001
R1 N002 0 1000
D1 N001 N002 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5ms
* Positive Half Wave Rectifier Circuit (Practical)
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 64 80 64
WIRE 352 64 256 64
WIRE 80 112 80 64
WIRE 352 112 352 64
WIRE 80 240 80 192
WIRE 176 240 80 240
WIRE 352 240 352 192
WIRE 352 240 176 240
WIRE 176 272 176 240
FLAG 176 272 0
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1000)
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL diode 192 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
TEXT 16 272 Left 2 !.tran 5ms
TEXT -24 8 Left 2 ;Positive Half Wave Rectifier Circuit (Practical)
* Z:\home\khalils\Downloads\files\data\raw_asc\574b57668bd2_IPS.asc
* Generated by LTspice 26.0.1 for Windows.
* Inverting amplifier with 10x gain.\nFor gain adjustments, vary R1.\n100mv-200mv > 1v - 2v
* buffer
* preamp
R3 N001 IN 1k
R2 N004 N003 10k
XU1 0 N003 +V -V N004 NE5532 ;pnba In+)In-)V+)V-)OUT
XU2 0 N001 +V -V N002 NE5532 ;pnba In+)In-)V+)V-)OUT
C4 N002 N001 100n
R4 N002 N001 1k
C1 OUT N004 22
R1 N003 N002 1k
.lib NE5532.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1812 680
WIRE 272 16 240 16
WIRE 384 16 352 16
WIRE 576 32 560 32
WIRE 688 32 656 32
WIRE 240 64 240 16
WIRE 320 64 240 64
WIRE 384 64 384 16
WIRE 608 96 304 96
WIRE 816 96 608 96
WIRE 304 144 304 96
WIRE 128 160 80 160
WIRE 240 160 240 64
WIRE 240 160 208 160
WIRE 272 160 240 160
WIRE 608 160 608 96
WIRE 384 176 384 64
WIRE 384 176 336 176
WIRE 464 176 384 176
WIRE 560 176 560 32
WIRE 560 176 544 176
WIRE 576 176 560 176
WIRE 272 192 240 192
WIRE 688 192 688 32
WIRE 688 192 640 192
WIRE 752 192 688 192
WIRE 576 208 560 208
WIRE 304 288 304 208
WIRE 608 288 608 224
WIRE 608 288 304 288
WIRE 816 288 608 288
WIRE 240 336 240 192
WIRE 560 336 560 208
WIRE 560 336 240 336
WIRE 816 336 560 336
IOPIN 816 96 In
IOPIN 816 288 In
IOPIN 816 336 In
IOPIN 80 160 In
IOPIN 816 192 Out
RECTANGLE Normal 448 336 112 -32 2
RECTANGLE Normal 736 336 464 -32 2
RECTANGLE Normal 928 640 -880 -112 2
RECTANGLE Normal -832 336 -336 -32 2
SYMBOL res 368 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 672 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL cap 384 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL res 224 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL cap 816 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 22µ
SYMBOL OpAmps\\opamp2 608 128 R0
SYMATTR InstName U1
SYMATTR Value NE5532
SYMBOL OpAmps\\opamp2 304 112 R0
SYMATTR InstName U2
SYMATTR Value NE5532
SYMBOL res 560 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 816 96 +V
FLAG 816 288 -V
FLAG 816 336 GND
FLAG 80 160 IN
FLAG 816 192 OUT
TEXT -808 8 Left 2 !.lib NE5532.sub
TEXT -808 72 Left 2 ;Inverting amplifier with 10x gain.\nFor gain adjustments, vary R1.\n100mv-200mv > 1v - 2v
TEXT 232 -48 Left 2 ;buffer
TEXT 560 -48 Left 2 ;preamp
* Z:\tmp\asc_dec_bjh7r6w2\155f97ea00f2_L1_C4_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R4 Vo1 N004 10k
R2 0 N003 10k
V4 0 Vss 0
XU2 N002 N001 Vcc Vss voIdeal level5 Avol=1Meg GBW=10Meg Phimargin=45 SlewPos=10Meg SlewNeg=10Meg En=0 Enk=0 In=0 Ink=0 Rcm=500Meg Ccm=1p Rdiff=500k Cdiff=2p Ro=1k Vos=0 Ibp=2n Ibn=1n Iq=1m Rail=0 Ilimit=25m ;pnba In+)In-)V+)V-)OUT
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp5.asy)
.lib UniversalOpAmp5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2516 10852
WIRE 0 -400 -32 -400
WIRE 0 -368 0 -400
WIRE 112 -288 112 -304
WIRE 0 -272 0 -288
WIRE 80 -272 0 -272
WIRE 0 -256 0 -272
WIRE 208 -256 144 -256
WIRE 240 -256 208 -256
WIRE 80 -240 48 -240
WIRE 112 -192 112 -224
WIRE 0 -144 0 -176
WIRE 48 -128 48 -240
WIRE 112 -128 48 -128
WIRE 208 -128 208 -256
WIRE 208 -128 192 -128
WIRE 48 -112 48 -128
WIRE 304 -80 304 -112
WIRE 400 -80 400 -112
WIRE 304 16 304 0
WIRE 400 16 400 0
WIRE 144 160 144 144
WIRE 32 176 32 160
WIRE 112 176 32 176
WIRE 32 192 32 176
WIRE 240 192 176 192
WIRE 256 192 240 192
WIRE 112 208 80 208
WIRE 144 256 144 224
WIRE 32 304 32 272
WIRE 80 320 80 208
WIRE 144 320 80 320
WIRE 240 320 240 192
WIRE 240 320 224 320
WIRE 80 336 80 320
WIRE 80 448 80 416
WIRE 80 448 48 448
SYMBOL res 240 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res 48 288 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 400 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL OpAmps\\UniversalOpAmp5 112 -256 R0
SYMATTR InstName U2
FLAG 304 16 0
FLAG 400 -112 0
FLAG 304 -112 Vcc
FLAG 144 144 Vcc
FLAG 400 16 Vss
FLAG 144 256 Vss
FLAG 256 192 Vo1
FLAG 32 304 0
FLAG 48 448 Vref
FLAG 112 -304 Vcc
FLAG 112 -192 Vss
FLAG 0 -144 0
FLAG -32 -400 Vin
FLAG 240 -256 voIdeal
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3406-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3406-1.5.asy)
V1 IN 0 5
L1 N001 OUT 4.7
XU1 IN 0 N001 IN OUT LTC3406-x.x top=330K bot=220K ;pnba Run)GND)SW)Vin)Vout
Rload OUT 0 10
C1 OUT 0 22
.tran 500u startup
.lib LTC3406-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 700
WIRE 176 64 96 64
WIRE 352 64 176 64
WIRE 96 80 96 64
WIRE 352 80 352 64
WIRE 176 144 176 64
WIRE 208 144 176 144
WIRE 512 144 496 144
WIRE 624 144 592 144
WIRE 672 144 624 144
WIRE 768 144 672 144
WIRE 672 160 672 144
WIRE 768 160 768 144
WIRE 96 176 96 160
WIRE 672 256 672 224
WIRE 768 256 768 240
WIRE 624 304 624 144
WIRE 624 304 496 304
WIRE 352 384 352 368
SYMBOL ind 496 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL RES 752 144 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL PowerProducts\\LTC3406-1.5 352 224 R0
SYMATTR InstName U1
SYMBOL polcap 656 160 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL VOLTAGE 96 64 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 96 176 0
FLAG 352 384 0
FLAG 672 256 0
FLAG 768 256 0
FLAG 768 144 OUT
FLAG 96 64 IN
TEXT 568 368 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\46707cacbc79_Input_Voltage_Polarity_Protection.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N003 N002 N002 PMOS
D1 N003 N002 1N5819
V1 N001 0 -5.5
R1 N003 0 100
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 5 0.1 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 64 0 64
WIRE 304 64 272 64
WIRE 384 64 304 64
WIRE 304 80 304 64
WIRE 0 96 0 64
WIRE 256 176 256 112
WIRE 304 176 304 144
WIRE 304 176 256 176
WIRE 0 288 0 176
WIRE 256 288 256 256
SYMBOL pmos 176 112 R270
SYMATTR InstName M1
SYMBOL schottky 320 144 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMATTR Description Zener Diode
SYMATTR Type zener
SYMBOL voltage 0 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -5.5
SYMBOL res 240 160 R0
SYMATTR InstName R1
SYMATTR Value 100
FLAG 256 288 0
FLAG 0 288 0
TEXT -34 312 Left 2 !.tran 0 5 0.1 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG2412.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nOnly one channel included\nCrosstalk parameter not included
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG2412.asy)
XU1 vIN vD vS -V 0 +V ADG2412 ;pnba IN)D)S)Vss)GND)Vdd
V1 +V 0 15
V2 -V 0 -15
V3 vS 0 10
R1 vD 0 301
C1 vD 0 36p
V4 vIN 0 pulse(0 5 0 20n 20n 10u 20u)
.tran 75u
.lib ADG2412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 80 224 48
WIRE -208 144 -208 128
WIRE -48 160 -80 160
WIRE 96 160 32 160
WIRE 128 160 96 160
WIRE 352 160 320 160
WIRE 400 160 352 160
WIRE 496 160 400 160
WIRE 400 192 400 160
WIRE 496 208 496 160
WIRE 96 224 -16 224
WIRE 128 224 96 224
WIRE -208 240 -208 224
WIRE 400 288 400 272
WIRE 496 288 496 272
WIRE -208 336 -208 320
WIRE -16 336 -16 224
WIRE 288 352 288 336
WIRE 160 368 160 336
WIRE -208 432 -208 416
WIRE -16 480 -16 416
SYMBOL res 384 176 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -208 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -16 320 R0
WINDOW 3 19 116 Left 2
SYMATTR Value pulse(0 5 0 20n 20n 10u 20u)
SYMATTR InstName V4
SYMBOL voltage 48 160 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL cap 480 208 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL ADG2412 224 208 R0
SYMATTR InstName U1
SYMBOL voltage -208 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
FLAG -208 432 0
FLAG -208 240 0
FLAG -208 128 +V
FLAG -208 320 -V
FLAG -80 160 0
FLAG -16 480 0
FLAG 400 288 0
FLAG 496 288 0
FLAG 224 48 +V
FLAG 160 368 -V
FLAG 288 352 0
FLAG 96 160 vS
FLAG 96 224 vIN
FLAG 352 160 vD
TEXT 8 464 Left 2 !.tran 75u
TEXT -224 -56 Left 2 ;Note:\nSwitch shown for a logic 0 input\nOnly one channel included\nCrosstalk parameter not included
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP163.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP163.asy)
R2 N002 0 100K
R1 OUT N002 230K
XU1 IN 0 N001 OUT N002 ADP16xa ;pnba Vin)GND)En)Vout)Adj
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
V1 IN 0 5
C1 OUT 0 1
Rload OUT 0 330
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -112 96
WIRE 432 96 352 96
WIRE 544 96 432 96
WIRE 624 96 544 96
WIRE -112 112 -112 96
WIRE 432 112 432 96
WIRE 544 112 544 96
WIRE 624 112 624 96
WIRE -112 208 -112 192
WIRE 160 208 16 208
WIRE 432 208 432 192
WIRE 432 208 352 208
WIRE 544 208 544 176
WIRE 624 208 624 192
WIRE 16 224 16 208
WIRE 432 224 432 208
WIRE 256 272 256 256
WIRE 16 320 16 304
WIRE 432 320 432 304
SYMBOL res 608 96 R0
SYMATTR InstName Rload
SYMATTR Value 330
SYMBOL cap 528 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP163 256 208 R0
SYMATTR InstName U1
SYMBOL voltage -112 96 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 416 96 R0
SYMATTR InstName R1
SYMATTR Value 230K
SYMBOL res 416 208 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
FLAG -112 208 0
FLAG 256 272 0
FLAG 432 320 0
FLAG 544 208 0
FLAG 624 208 0
FLAG 624 96 OUT
FLAG -112 96 IN
FLAG 16 320 0
TEXT 512 248 Left 2 !.tran 4m
* Z:\home\khalils\Downloads\files\data\raw_asc\0bbefe8fe9ce_6993-2.asc
* Generated by LTspice 26.0.1 for Windows.
* LTC6993-2 Retriggerable 10ms One Shot\nRising Edge Triggered, Positive Output Pulse\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6993-2.asy)
R3 N004 0 392K
XU1 N001 0 N003 N004 N002 OUT LTC6993-2 ;pnba TRIG)GND)SET)DIV)V+)OUT
R4 OUT 0 100K
V2 N001 0 PULSE(0 3.3 1m 1n 1n 1m 8m 3)
V1 N002 0 5
R2 N002 N004 1000K
R1 N003 0 121K
.tran 50m startup
.lib LTC6993-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -192 96 -208 96
WIRE 96 96 -112 96
WIRE 608 96 320 96
WIRE 608 112 608 96
WIRE 96 176 80 176
WIRE 384 176 320 176
WIRE 512 176 384 176
WIRE 384 192 384 176
WIRE 512 192 512 176
WIRE 608 208 608 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 336 256 320 256
WIRE 336 288 336 256
WIRE 384 288 384 272
WIRE 384 288 336 288
WIRE 512 288 512 272
WIRE 384 304 384 288
WIRE 384 400 384 384
SYMBOL voltage -96 96 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 3.3 1m 1n 1n 1m 8m 3)
SYMATTR InstName V2
SYMBOL SpecialFunctions\\LTC6993-2 208 176 R0
SYMATTR InstName U1
SYMBOL res 368 288 R0
SYMATTR InstName R3
SYMATTR Value 392K
SYMBOL voltage 512 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 121K
SYMBOL res 368 176 R0
SYMATTR InstName R2
SYMATTR Value 1000K
SYMBOL res 592 96 R0
SYMATTR InstName R4
SYMATTR Value 100K
FLAG -208 96 0
FLAG 512 288 0
FLAG 608 96 OUT
FLAG 80 176 0
FLAG 608 208 0
FLAG 384 400 0
FLAG -16 256 0
TEXT 512 360 Left 2 !.tran 50m startup
TEXT 216 56 Bottom 2 ;LTC6993-2 Retriggerable 10ms One Shot\nRising Edge Triggered, Positive Output Pulse\nStartup Modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1528.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1528.asy)
C1 OUT 0 3.3
Rload OUT 0 500
XU1 OUT OUT 0 0 IN LT1528 ;pnba OUT)Sense)GND)_SHDN)IN
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT1528.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 176 -208 176
WIRE 368 176 320 176
WIRE 432 176 368 176
WIRE 528 176 432 176
WIRE -208 192 -208 176
WIRE 432 192 432 176
WIRE 528 192 528 176
WIRE 32 272 16 272
WIRE 368 272 368 176
WIRE 368 272 320 272
WIRE -208 288 -208 272
WIRE 432 288 432 256
WIRE 528 288 528 272
WIRE 176 368 176 336
SYMBOL PowerProducts\\LT1528 176 224 R0
SYMATTR InstName U1
SYMBOL res 512 176 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL voltage -208 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 416 192 R0
SYMATTR InstName C1
SYMATTR Value 3.3
FLAG -208 288 0
FLAG 176 368 0
FLAG 432 288 0
FLAG 528 288 0
FLAG -208 176 IN
FLAG 528 176 OUT
FLAG 16 272 0
TEXT 368 384 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\23ada078ffff_Fig26_18_ID_VSG.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot d(Id(M1)) to get gm
M1 0 N002 N003 N001 P_50n l=50n w=1u
VSG 0 N002 0
VBS N001 0 0
VSD 0 N003 100m
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSG 0 500m 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 688
WIRE 320 96 320 80
WIRE 320 192 320 176
WIRE 400 192 320 192
WIRE 448 80 320 80
WIRE 448 112 448 80
WIRE 448 304 448 208
WIRE 528 160 448 160
WIRE 672 80 448 80
WIRE 672 160 608 160
WIRE 672 160 672 80
WIRE 672 208 672 160
WIRE 672 304 448 304
WIRE 672 304 672 288
WIRE 720 80 672 80
WIRE 720 112 720 80
SYMBOL voltage 320 80 R0
WINDOW 0 -89 56 Left 0
WINDOW 3 24 104 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSG
SYMATTR Value 0
SYMBOL pmos4 400 112 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=50n w=1u
SYMATTR InstName M1
SYMATTR Value P_50n
SYMBOL voltage 512 160 M90
WINDOW 0 -32 56 VBottom 0
WINDOW 3 -6 99 VBottom 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VBS
SYMATTR Value 0
SYMBOL voltage 672 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 41 57 Left 0
WINDOW 3 41 85 Left 0
SYMATTR InstName VSD
SYMATTR Value 100m
FLAG 720 112 0
TEXT 424 336 Left 0 !.dc VSG 0 500m 1m
TEXT 424 360 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot d(Id(M1)) to get gm
* Z:\home\khalils\Downloads\files\data\raw_asc\ca630f240af6_opto.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Optos\PC817A.asy)
V1 N001 0 PULSE(0 3.3 0.001 0 0 0.001)
R1 N001 N003 400
XU1 N003 0 N002 N004 PC817 Igain=1m ;pnba A)K)C)E
R2 N004 0 4k7
V2 N002 0 5
.tran 0.01
.lib PC817.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 -48 -464 -48
WIRE -64 0 -64 -48
WIRE 736 48 416 48
WIRE -64 112 -64 80
WIRE 96 112 -64 112
WIRE 416 112 416 48
WIRE 416 112 288 112
WIRE -464 128 -464 -48
WIRE 736 144 736 48
WIRE 96 208 16 208
WIRE 464 208 288 208
WIRE 464 224 464 208
WIRE -464 272 -464 208
WIRE 464 336 464 304
WIRE 736 336 736 224
WIRE 736 336 464 336
WIRE 736 352 736 336
WIRE 16 384 16 208
WIRE 464 400 464 336
SYMBOL voltage 736 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 ""
SYMATTR SpiceLine ""
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res -80 -16 R0
SYMATTR InstName R1
SYMATTR Value 400
SYMBOL Optos\\PC817A 192 160 R0
SYMATTR InstName U1
SYMBOL voltage -464 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 ""
SYMATTR SpiceLine ""
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0.001 0 0 0.001)
SYMBOL res 448 208 R0
SYMATTR InstName R2
SYMATTR Value 4k7
SYMATTR SpiceLine ""
FLAG 16 384 0
FLAG -464 272 0
FLAG 464 400 0
TEXT -496 424 Left 2 !.tran 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP160-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP160-3.3.asy)
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
Rload OUT 0 330
V1 IN 0 5
C1 OUT 0 1
XU1 IN 0 N001 OUT ADP16xfd K=303u ;pnba Vin)GND)En)Vout
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -64 96
WIRE 416 96 352 96
WIRE 512 96 416 96
WIRE -64 112 -64 96
WIRE 416 112 416 96
WIRE 512 112 512 96
WIRE -64 208 -64 192
WIRE 160 208 16 208
WIRE 416 208 416 176
WIRE 512 208 512 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL cap 400 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
SYMBOL ADP160-3.3 256 208 R0
SYMATTR InstName U1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 330
SYMBOL voltage -64 96 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -64 208 0
FLAG 256 272 0
FLAG 416 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG -64 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m