* Z:\home\khalils\Downloads\files\data\raw_asc\3964a3f25607_AnalogIn.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N003 0 SINE(2.5 2.5 10) Rser=1
D1 N006 N002 BAT54
D2 0 N006 BAT54
V2 N002 0 3.3
R2 N004 N006 1.7k
R3 N003 N005 5k
R4 N005 0 5k
V3 N001 0 5v
C2 N001 0 100nF
XU1 N005 N004 N001 0 N004 LM358/NS ;pnba In+)In-)V+)V-)OUT
R1 N006 0 3.3k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 1 0 1e-6 startup
.lib opamp.sub
.SUBCKT MCP6001 1 2 3 4 5
* | | | | |
* | | | | Output
* | | | Negative Supply
* | | Positive Supply
* | Inverting Input
* Non-inverting Input
*
********************************************************************************
* Software License Agreement *
* *
* The software supplied herewith by Microchip Technology Incorporated (the *
* "Company") is intended and supplied to you, the Company's customer, for use *
* soley and exclusively on Microchip products. *
* *
* The software is owned by the Company and/or its supplier, and is protected *
* under applicable copyright laws. All rights are reserved. Any use in *
* violation of the foregoing restrictions may subject the user to criminal *
* sanctions under applicable laws, as well as to civil liability for the *
* breach of the terms and conditions of this license. *
* *
* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER *
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED *
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO *
* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR *
* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. *
********************************************************************************
*
* Macromodel for the MCP6001/2/4 op amp family:
* MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004
*
* Revision History:
* REV A: 21-Jun-02, Created model
* REV B: 16-Jul-02, Improved output stage
* REV C: 03-Jan-03, Added MCP6001
* REV D: 19-Aug-06, Added over temperature, improved output stage,
* fixed overdrive recovery time
* REV E: 27-Jul-07, Updated output impedance for better model stability w/cap load
* REV F: 09-Jul-12, Added MCP6001R, MCP6001U
*
* Recommendations:
* Use PSPICE (other simulators may require translation)
* For a quick, effective design, use a combination of: data sheet
* specs, bench testing, and simulations with this macromodel
* For high impedance circuits, set GMIN=100F in .OPTIONS
*
* Supported:
* Typical performance for temperature range (-40 to 125) degrees Celsius
* DC, AC, Transient, and Noise analyses.
* Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,
* open loop gain, voltage ranges, supply current, ... , etc.
* Temperature effects for Ibias, Iquiescent, Iout short circuit
* current, Vsat on both rails, Slew Rate vs. Temp and P.S.
*
* Not Supported:
* Some Variation in specs vs. Power Supply Voltage
* Monte Carlo (Vos, Ib), Process variation
* Distortion (detailed non-linear behavior)
* Behavior outside normal operating region
*
* Input Stage
V10 3 10 -500M
R10 10 11 6.90K
R11 10 12 6.90K
C11 11 12 0.2p
C12 1 0 6.00P
E12 71 14 POLY(4) 20 0 21 0 26 0 27 0 1.00M 20.1 20.1 1 1
G12 1 0 62 0 1m
M12 11 14 15 15 NMI L=2.00U W=42.0U
M14 12 2 15 15 NMI L=2.00U W=42.0U
G14 2 0 62 0 1m
C14 2 0 6.00P
I15 15 4 50.0U
V16 16 4 -300M
GD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1))
V13 3 13 -300M
GD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1))
R70 1 0 20.6T
R71 2 0 20.6T
R72 1 2 20T
I80 1 2 0.5p
*
* Noise, PSRR, and CMRR
I20 21 20 423U
D20 20 0 DN1
D21 0 21 DN1
G26 0 26 POLY(1) 3 4 110U -49U
R26 26 0 1
G27 0 27 POLY(2) 1 0 2 0 -440U 39.7U 39.7U
R27 27 0 1
*
* Open Loop Gain, Slew Rate
G30 0 30 POLY(1) 12 11 0 1
R30 30 0 1K
G31 0 31 POLY(1) 3 4 86 5.25
R31 31 0 1 TC=2.8m
GD31 30 31 TABLE {V(30,31)} ((-11,-1)(-10,-10n)(0,0)(1m,1000))
G32 32 0 POLY(1) 3 4 113.7 3.5
R32 32 0 1 TC=2.65m
GD32 30 32 TABLE {V(30,32)} ((-1m,-1000)(0,0)(10,10n)(11,1))
G33 0 33 30 0 1m
R33 33 0 1k
G34 0 34 33 0 425M
R34 34 0 1K
C34 34 0 74U
G37 0 37 34 0 1m
R37 37 0 1K
C37 37 0 41.6P
G38 0 38 37 0 1m
R38 39 0 1K
L38 38 39 100U
E38 35 0 38 0 1
G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(16,1n))(16.1,1))
G36 33 0 TABLE {V(35,4)} ((-16.1,-1)((-16,-1n)(0,0)(1,1n))
*
* Output Stage
R80 50 0 100MEG
G50 0 50 57 96 2
R58 57 96 0.50
R57 57 0 750
C58 5 0 2.00P
G57 0 57 POLY(3) 3 0 4 0 35 0 0 0.67M 0.67M 1.5M
GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
E55 55 0 POLY(2) 3 0 51 0 -0.7m 1 -40.0M
E56 56 0 POLY(2) 4 0 52 0 1.2m 1 -37.0M
R51 51 0 1k
R52 52 0 1k
GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))
GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))
G53 3 0 POLY(1) 51 0 -49U 1M
G54 0 4 POLY(1) 52 0 -49U -1M
*
* Current Limit
G99 96 5 99 0 1
R98 0 98 1 TC=-2.8M,2.63U
G97 0 98 TABLE { V(96,5) } ((-11.0,-10.0M)(-1.00M,-9.9M)(0,0)(1.00M,9.9M)(11.0,10.0M))
E97 99 0 VALUE { V(98)*((V(3)-V(4))*359M + 310M)}
D98 4 5 DESD
D99 5 3 DESD
*
* Temperature / Voltage Sensitive IQuiscent
R61 0 61 100 TC 3.11M 4.51U
G61 3 4 61 0 1
G60 0 61 TABLE {V(3, 4)}
+ ((0,0)(900M,0.0106U)(1.00,0.20U)(1.3,0.63U)
+ (1.5,0.66U)(1.6,1.06U)(5.5,1.10U))
*
* Temp Sensitive offset voltage
I73 0 70 DC 1uA
R74 0 70 1 TC=2
E75 1 71 70 0 1
*
* Temp Sensistive IBias
I62 0 62 DC 1uA
R62 0 62 REXP 58.2u
* Voltage on R62 used for G12, G14 in input stage
*
* Models
.MODEL NMI NMOS
.MODEL DESD D N=1 IS=1.00E-15
.MODEL DL D N=1 IS=1F
.MODEL DN1 D IS=1P KF=146E-18 AF=1
.MODEL REXP RES TCE=10.1
.ENDS MCP6001
* LMX24_LM2902 - Rev. A
* Created by Paul Goedeke; November 16, 2018
* Created with Green-Williams-Lis Op Amp Macro-model Architecture
* Copyright 2018 by Texas Instruments Corporation
******************************************************
* MACRO-MODEL SIMULATED PARAMETERS:
******************************************************
* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)
* UNITY GAIN BANDWIDTH (GBW)
* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
* DIFFERENTIAL INPUT IMPEDANCE (Zid)
* COMMON-MODE INPUT IMPEDANCE (Zic)
* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
* QUIESCENT CURRENT (Iq)
* SETTLING TIME VS. CAPACITIVE LOAD (ts)
* SLEW RATE (SR)
* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
* LARGE SIGNAL RESPONSE
* OVERLOAD RECOVERY TIME (tor)
* INPUT BIAS CURRENT (Ib)
* INPUT OFFSET CURRENT (Ios)
* INPUT OFFSET VOLTAGE (Vos)
* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)
* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
******************************************************
.subckt LMX24_LM2902 IN+ IN- VCC VEE OUT
******************************************************
* MODEL DEFINITIONS:
.model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0)
.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)
.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)
.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
.model R_NOISELESS RES(T_ABS=-273.15)
******************************************************
I_OS ESDn MID -18N
I_B 37 MID -20N
V_GRp 57 MID 180
V_GRn 58 MID -180
V_ISCp 51 MID 40
V_ISCn 52 MID -40
V_ORn 45 VCLP -1.2
V11 56 44 0
V_ORp 43 VCLP 1.2
V12 55 42 0
V4 33 OUT 0
VCM_MIN 79 VEE_B 0
VCM_MAX 80 VCC_B -1.5
I_Q VCC VEE 175U
V_OS 86 37 1.8M
R61 MID 22 R_NOISELESS 8.001K
C16 22 23 19.89P
R58 23 22 R_NOISELESS 100MEG
GVCCS2 23 MID VEE_B MID -992.9M
R57 MID 23 R_NOISELESS 1
XU3 VCC_B VEE_B 24 25 26 27 MID PHASEREV_0
XU1 VIMON MID CRS CRS_DIST_0
C21 28 29 313.8N
C22 30 31 636.6F
R70 31 MID R_NOISELESS 2.5
R67 31 30 R_NOISELESS 10K
R66 30 MID R_NOISELESS 1
XU2 31 MID MID 32 VCCS_LIM_ZO_0
GVCCS4 30 MID 29 MID -4.3
R65 29 MID R_NOISELESS 3.03K
R64 29 28 R_NOISELESS 10K
R63 28 MID R_NOISELESS 1
GVCCS3 28 MID CL_CLAMP 33 -90
R62 32 MID R_NOISELESS 1
C29 34 MID 47F
R78 MID 34 R_NOISELESS 1MEG
GVCCS9 34 MID 35 MID -1U
XU5 36 MID MID CLAMP CRS MID VCCS_LIM_2_EN_0
C28 38 MID 1P
R77 39 38 R_NOISELESS 100
C27 40 MID 1P
R76 41 40 R_NOISELESS 100
R75 MID 42 R_NOISELESS 1
GVCCS8 42 MID 43 MID -1
R74 44 MID R_NOISELESS 1
GVCCS7 44 MID 45 MID -1
Xi_nn ESDn MID FEMT_0
Xi_np MID 37 FEMT_0
Xe_n ESDp 37 VNSE_0
C25 35 MID 47F
R69 MID 35 R_NOISELESS 1MEG
GVCCS6 35 MID VSENSE MID -1U
C20 CLAMP MID 9N
R68 MID CLAMP R_NOISELESS 1MEG
R44 MID 36 R_NOISELESS 1MEG
XVCCS_LIM_1 46 27 MID 36 VCCS_LIM_1_0
Rdummy MID 33 R_NOISELESS 25K
Rx 33 32 R_NOISELESS 250K
R56 MID 47 R_NOISELESS 1K
C15 47 48 1.592P
R55 48 47 R_NOISELESS 100MEG
GVCCS1 48 MID VCC_B MID -100M
R54 MID 48 R_NOISELESS 1
R49 MID 49 R_NOISELESS 4.616K
C14 49 50 26.53P
R48 50 49 R_NOISELESS 100MEG
G_adjust 50 MID ESDp MID -685.2M
Rsrc MID 50 R_NOISELESS 1
XIQPos VIMON MID MID VCC VCCS_LIMIT_IQ_0
XIQNeg MID VIMON VEE MID VCCS_LIMIT_IQ_0
C_DIFF ESDp ESDn 1P
XCL_AMP 51 52 VIMON MID 53 54 CLAMP_AMP_LO_0
SOR_SWp CLAMP 55 CLAMP 55 S_VSWITCH_1
SOR_SWn 56 CLAMP 56 CLAMP S_VSWITCH_2
XGR_AMP 57 58 59 MID 60 61 CLAMP_AMP_HI_0
R39 57 MID R_NOISELESS 1T
R37 58 MID R_NOISELESS 1T
R42 VSENSE 59 R_NOISELESS 1M
C19 59 MID 1F
R38 60 MID R_NOISELESS 1
R36 MID 61 R_NOISELESS 1
R40 60 62 R_NOISELESS 1M
R41 61 63 R_NOISELESS 1M
C17 62 MID 1F
C18 MID 63 1F
XGR_SRC 62 63 CLAMP MID VCCS_LIM_GR_0
R21 53 MID R_NOISELESS 1
R20 MID 54 R_NOISELESS 1
R29 53 64 R_NOISELESS 1M
R30 54 65 R_NOISELESS 1M
C9 64 MID 1F
C8 MID 65 1F
XCL_SRC 64 65 CL_CLAMP MID VCCS_LIM_4_0
R22 51 MID R_NOISELESS 1T
R19 MID 52 R_NOISELESS 1T
XCLAWp VIMON MID 66 VCC_B VCCS_LIM_CLAW+_0
XCLAWn MID VIMON VEE_B 67 VCCS_LIM_CLAW-_0
R12 66 VCC_B R_NOISELESS 1K
R16 66 68 R_NOISELESS 1M
R13 VEE_B 67 R_NOISELESS 1K
R17 69 67 R_NOISELESS 1M
C6 69 MID 1F
C5 MID 68 1F
G2 VCC_CLP MID 68 MID -1M
R15 VCC_CLP MID R_NOISELESS 1K
G3 VEE_CLP MID 69 MID -1M
R14 MID VEE_CLP R_NOISELESS 1K
XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID 70 71 CLAMP_AMP_LO_0
R26 VCC_CLP MID R_NOISELESS 1T
R23 VEE_CLP MID R_NOISELESS 1T
R25 70 MID R_NOISELESS 1
R24 MID 71 R_NOISELESS 1
R27 70 72 R_NOISELESS 1M
R28 71 73 R_NOISELESS 1M
C11 72 MID 1F
C10 MID 73 1F
XCLAW_SRC 72 73 CLAW_CLAMP MID VCCS_LIM_3_0
H2 41 MID V11 -1
H3 39 MID V12 1
C12 SW_OL MID 100P
R32 74 SW_OL R_NOISELESS 100
R31 74 MID R_NOISELESS 1
XOL_SENSE MID 74 40 38 OL_SENSE_0
S1 28 29 SW_OL MID S_VSWITCH_3
H1 75 MID V4 1K
S7 VEE OUT VEE OUT S_VSWITCH_4
S6 OUT VCC OUT VCC S_VSWITCH_5
R11 MID 76 R_NOISELESS 1T
R18 76 VOUT_S R_NOISELESS 100
C7 VOUT_S MID 10P
E5 76 MID OUT MID 1
C13 VIMON MID 10P
R33 75 VIMON R_NOISELESS 100
R10 MID 75 R_NOISELESS 1T
R47 77 VCLP R_NOISELESS 100
C24 VCLP MID 100P
E4 77 MID CL_CLAMP MID 1
R46 MID CL_CLAMP R_NOISELESS 1K
G9 CL_CLAMP MID CLAW_CLAMP MID -1M
R45 MID CLAW_CLAMP R_NOISELESS 1K
G8 CLAW_CLAMP MID 34 MID -1M
R43 MID VSENSE R_NOISELESS 1K
G15 VSENSE MID CLAMP MID -1M
C4 46 MID 1F
R9 46 78 R_NOISELESS 1M
R7 MID 79 R_NOISELESS 1T
R6 80 MID R_NOISELESS 1T
R8 MID 78 R_NOISELESS 1
XVCM_CLAMP 26 MID 78 MID 80 79 VCCS_EXT_LIM_0
E1 MID 0 81 0 1
R89 VEE_B 0 R_NOISELESS 1
R5 82 VEE_B R_NOISELESS 1M
C3 82 0 1F
R60 81 82 R_NOISELESS 1MEG
C1 81 0 1
R3 81 0 R_NOISELESS 1T
R59 83 81 R_NOISELESS 1MEG
C2 83 0 1F
R4 VCC_B 83 R_NOISELESS 1M
R88 VCC_B 0 R_NOISELESS 1
G17 VEE_B 0 VEE 0 -1
G16 VCC_B 0 VCC 0 -1
R_PSR 84 24 R_NOISELESS 1K
G_PSR 24 84 47 22 -1M
R2 25 ESDn R_NOISELESS 1M
R1 84 85 R_NOISELESS 1M
R_CMR 86 85 R_NOISELESS 1K
G_CMR 85 86 49 MID -1M
C_CMn ESDn MID 2P
C_CMp MID ESDp 2P
R53 ESDn MID R_NOISELESS 1T
R52 MID ESDp R_NOISELESS 1T
R35 IN- ESDn R_NOISELESS 10M
R34 IN+ ESDp R_NOISELESS 10M
.MODEL S_VSWITCH_1 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)
.MODEL S_VSWITCH_2 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)
.MODEL S_VSWITCH_3 VSWITCH (RON=1M ROFF=1T VON=500M VOFF=100M)
.MODEL S_VSWITCH_4 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)
.MODEL S_VSWITCH_5 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)
.ENDS LMX24_LM2902
*
.SUBCKT PHASEREV_0 VCC VEE VIN+ VIN- VOUT+ VOUT- MID
E1 VOUT+ MID VALUE={IF(V(VIN+,MID)<V(VEE,MID)-0.3,V(VCC,MID),V(VIN+,MID))}
E2 VOUT- MID VALUE={IF(V(VIN-,MID)<V(VEE,MID)-0.3,V(VCC,MID),V(VIN-,MID))}
.ENDS
*
.SUBCKT CRS_DIST_0 VIMON MID OUT
V1 VREF MID -40M
ESHF VSHF MID VIMON VREF 1
GZC MID ZC VALUE = {SGN(V(VSHF,MID))}
R1 ZC MID 1
C1 ZC MID 2U
GCR MID OUT VALUE = {IF((ABS(V(ZC,MID))<=0.9),0,1)}
R2 OUT MID 1
.ENDS
*
.SUBCKT VCCS_LIM_ZO_0 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 4E3
.PARAM IPOS = 1E6
.PARAM INEG = -1E6
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIM_2_EN_0 VC+ VC- IOUT+ IOUT- EN MID
.PARAM GAIN = 8.4E-4
.PARAM IPOS = 0.0048
.PARAM INEG = -0.0048
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(EN,MID)*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT FEMT_0 1 2
.PARAM FLWF=1E-3
.PARAM NLFF=500
.PARAM NVRF=500
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
.ENDS
*
.SUBCKT VNSE_0 1 2
.PARAM FLW=10
.PARAM NLF=80
.PARAM NVR=35
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
.PARAM RNV={1.184*PWR(NVR,2)}
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
.ENDS
*
.SUBCKT VCCS_LIM_1_0 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-4
.PARAM IPOS = .5
.PARAM INEG = -.5
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIMIT_IQ_0 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-3
G1 IOUT- IOUT+ VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
.ENDS
*
.SUBCKT CLAMP_AMP_LO_0 VC+ VC- VIN COM VO+ VO-
.PARAM G=1
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*
.SUBCKT CLAMP_AMP_HI_0 VC+ VC- VIN COM VO+ VO-
.PARAM G=10
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS
*
.SUBCKT VCCS_LIM_GR_0 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 0.013
.PARAM INEG = -0.013
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIM_4_0 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 1.04
.PARAM INEG = -1.04
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT VCCS_LIM_CLAW+_0 VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =
+(0, 1.17E-03)
+(0.0046251, 1.17E-3)
+(0.15716, 1.21E-3)
+(1.3309, 1.28E-3)
+(35.075, 2.12E-3)
+(35.680, 2.55E-3)
+(36.033, 2.84E-3)
+(37.416, 7.97E-3)
.ENDS
*
.SUBCKT VCCS_LIM_CLAW-_0 VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =
+(0.010, 2.50E-5)
+(0.070, 2.50E-5)
+(0.090, 5.80E-4)
+(0.100, 6.06E-4)
+(0.760, 7.14E-4)
+(1.440, 7.62E-4)
+(8.000, 1.10E-3)
+(13.60, 1.55E-3)
+(15.45, 1.75E-3)
+(17.26, 2.15E-3)
+(18.87, 2.94E-3)
+(21.58, 4.50E-3)
+(25.53, 1.02E-2)
.ENDS
*
.SUBCKT VCCS_LIM_3_0 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 0.435
.PARAM INEG = -0.435
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS
*
.SUBCKT OL_SENSE_0 COM SW+ OLN OLP
GSW+ COM SW+ VALUE = {IF((V(OLN,COM)>10E-3 | V(OLP,COM)>10E-3),1,0)}
.ENDS
*
.SUBCKT VCCS_EXT_LIM_0 VIN+ VIN- IOUT- IOUT+ VP+ VP-
.PARAM GAIN = 1
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
.ENDS
*
* TLV2371
*****************************************************************************
* (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer.
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: Analog eLab Design Center, Texas Instruments Inc.
* Part: TLV2371
* Date: 01JUL2011
* Model Type: ALL IN ONE
* Simulator: PSPICE
* Simulator Version: 16.0.0.p001
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SLOS270D - MARCH 2001 - REVISED JANUARY 2005
*
* Model Version: 1.0
*
*****************************************************************************
*
* Updates:
*
* Version 1.0 :
* Release to Web
*
*****************************************************************************
* THIS MODEL IS APPLICABLE TO TLV2370,TLV2371, TlV2372
* BEGIN MODEL TLV2371
* PINOUT ORDER +IN -IN +V -V OUT
* PINOUT ORDER 3 4 6 2 1
* BEGIN NOTES
* FOR MORE ACCURATE CURRENTS
* IF LOOKING AT BIAS CURRENT
* USE GMIN-1E-13
* MODEL TEMPERATURE RANGE IS
* -40 C TO +125 C, NOT ALL
* PARAMETERS TRACK THOSE OF
* THE REAL PART VS TEMPERATURE
* END NOTES
* BEGIN FEATURES
* OPEN LOOP GAIN AND PHASE
* INPUT VOLTAGE NOISE W 1/F
* INPUT CURRENT NOISE
* INPUT BIAS CURRENT
* INPUT BIAS CURRENT VS TEMPERATURE
* INPUT CAPACITANCE
* INPUT COMMON MODE VOLTAGE RANGE
* INPUT VOS SHIFT WITH VCM
* INPUT CLAMPS TO RAILS
* CMRR WITH FREQUENCY EFFECTS
* PSRR WITH FREQUENCY EFFECTS
* SLEW RATE
* QUIESCENT CURRENT
* HIGH CLOAD EFFECTS
* CLASS AB BIAS IN OUTPUT STAGE
* OUTPUT CURRENT THROUGH SUPPLIES
* OUTPUT CURRENT LIMITING
* OUTPUT CLAMPS TO RAILS
* OUTPUT SWING VS OUTPUT CURRENT
* END FEATURES
*****************************************************************************
.SUBCKT TLV2371 3 4 6 2 1
VEN 5 2 2
REN 5 2 1E12
Q20 7 8 9 QLN
R3 10 11 2
R4 12 11 2
R10 8 13 1E3
R11 14 15 1E3
R12 16 6 4
R13 2 17 4
R16 18 19 200
R17 20 21 4
R18 9 22 4
D5 23 6 DD
D6 2 23 DD
D7 24 0 DIN
D8 25 0 DIN
I8 0 24 0.1E-3
I9 0 25 0.1E-3
E2 9 0 2 0 1
E3 21 0 6 0 1
D9 26 0 DVN
D10 27 0 DVN
I10 0 26 0.1E-3
I11 0 27 0.1E-3
E4 28 4 26 27 0.025
G2 29 4 24 25 2.9E-7
R22 2 6 100E6
E5 30 0 21 0 1
E6 31 0 9 0 1
E7 32 0 33 0 1
R30 30 34 1E5
R31 31 35 1E5
R32 32 36 1E5
R33 0 34 10
R34 0 35 10
R35 0 36 10
E10 37 3 36 0 0.01
R36 38 33 1E3
R37 33 39 1E3
C6 30 34 0.2E-12
C7 31 35 0.2E-12
C8 32 36 0.2E-12
E11 40 37 35 0 0.8
E12 29 40 34 0 0.8
E14 41 9 21 9 0.5
D11 18 21 DD
D12 9 18 DD
M1 42 43 17 17 NOUT L=3U W=80U
M2 44 45 16 16 POUT L=3U W=80U
M3 46 46 20 20 POUT L=3U W=80U
M4 47 48 10 10 PIN L=3U W=110U
M5 49 50 12 12 PIN L=3U W=110U
M8 51 51 22 22 NOUT L=3U W=80U
R43 52 45 100
R44 53 43 100
G3 18 41 54 41 0.2E-3
R45 41 18 120E6
C12 19 23 10E-12
R46 9 47 2E3
R47 9 49 2E3
C13 47 49 1E-12
C14 29 0 4E-12
C15 28 0 4E-12
C16 23 0 0.5E-12
D13 43 7 DD
D14 55 45 DD
Q15 55 15 21 QLP
V18 29 56 0
M19 57 58 21 21 PIN L=6U W=500U
E17 39 0 29 0 1
E18 38 0 4 0 1
M23 58 58 21 21 PIN L=6U W=500U
V21 57 11 0
R59 23 44 1
R60 42 23 1
J1 59 29 59 JNC
J2 59 28 59 JNC
J3 28 60 28 JNC
J4 29 60 29 JNC
C21 29 61 2E-12
E20 62 41 49 47 1
R62 62 54 1E4
C23 54 41 0.1E-12
G7 63 41 18 41 -1E-3
G8 41 64 18 41 1E-3
G9 41 65 51 9 1E-3
G10 66 41 21 46 1E-3
D17 66 63 DD
D18 64 65 DD
R66 63 66 100E6
R67 65 64 100E6
R68 66 21 1E3
R69 9 65 1E3
E23 21 52 21 66 1
E24 53 9 65 9 1
R70 64 41 1E6
R71 65 41 1E6
R72 41 66 1E6
R73 41 63 1E6
G11 6 2 67 0 315E-6
R75 40 29 1E9
R76 37 40 1E9
R77 3 37 1E9
R78 4 28 1E9
R79 41 54 1E9
R81 52 21 1E9
R82 9 53 1E9
R83 33 0 1E9
G14 58 9 67 0 55U
G15 46 51 67 0 80U
E48 68 18 67 0 30
E49 69 41 67 0 -30
V49 70 69 15
V50 71 68 -15
R127 68 0 1E12
R128 69 0 1E12
M41 41 71 18 72 PSW L=1.5U W=150U
M42 18 70 41 73 NSW L=1.5U
R129 72 0 1E12
R130 73 0 1E12
M43 74 5 9 9 NEN L=3U W=300U
M44 75 76 9 9 NEN L=3U W=3000U
R131 74 21 1E4
R132 75 77 1E6
V51 77 9 1
M45 78 78 21 21 PEN L=6U W=60U
M46 5 78 21 21 PEN L=6U W=60U
I20 78 9 0.1E-6
C26 5 0 1E-12
E50 67 0 79 9 1
V52 75 79 1.111E-6
R133 9 79 1E12
C32 21 74 3E-15
C33 77 75 3E-15
I21 6 2 30E-6
L1 23 1 4E-9
R150 23 1 400
V78 21 59 0
V79 60 9 0
R155 46 21 1E8
R156 9 51 1E8
R157 17 43 1E8
R158 16 45 1E8
RG1 0 67 1E9
R159 61 28 100
R225 50 28 25E3
R226 48 56 25E3
M48 80 81 2 2 NIQS L=3U W=1000U
R297 80 6 61.5E3
E94 81 2 67 0 2
M49 82 74 9 9 NEN L=3U W=300U
M50 76 82 9 9 NEN L=3U W=300U
R298 82 77 1E4
R299 76 77 1E4
C35 77 82 40E-12
M51 83 84 85 85 NIN L=3U W=110U
M52 86 87 88 88 NIN L=3U W=110U
R300 89 85 2
R301 89 88 2
R302 83 21 2E3
R303 86 21 2E3
C36 83 86 1E-12
G36 18 41 90 41 0.2E-3
R304 41 90 1E9
C37 90 41 0.1E-12
E97 91 41 86 83 1
R305 91 90 1E4
V115 92 56 1E-3
R306 28 87 25E3
R307 92 84 25E3
M53 93 94 95 95 PIN L=6U W=500U
R308 95 57 2E3
V116 21 94 1.25
M54 93 93 9 9 NIN L=3U W=500U
M55 89 93 9 9 NIN L=3U W=500U
E98 21 14 6 16 1
E99 13 9 17 2 1
C105 77 76 130E-12
R233 78 21 1E12
R334 93 9 1E12
R335 58 21 1E12
R336 94 21 1E12
R337 2 81 1E12
G37 28 0 96 0 6.6E-12
I48 28 0 1E-12
I49 0 97 1E-3
D46 97 0 DD
V119 97 98 0.7
R633 0 98 1E6
E100 99 0 98 0 -571
R634 0 99 1E6
D47 100 96 DD
V120 99 100 83.5
G38 29 0 96 0 6.6E-12
I50 29 0 1E-12
R635 0 96 1E6
R636 96 100 1E11
.MODEL DVN D KF=8E-12 IS=1E-16
.MODEL DD D
.MODEL DIN D
.MODEL QLN NPN
.MODEL QLP PNP
.MODEL JNC NJF
.MODEL POUT PMOS KP=200U VTO=-0.7
.MODEL NOUT NMOS KP=200U VTO=0.7
.MODEL PIN PMOS KP=200U VTO=-0.7
.MODEL NIN NMOS KP=200U VTO=0.7
.MODEL NIQS NMOS KP=200U VTO=0.7 IS=1E-18
.MODEL NEN NMOS KP=200U VTO=0.5 IS=1E-18
.MODEL PEN PMOS KP=200U VTO=-0.7 IS=1E-18
.MODEL PSW PMOS KP=200U VTO=-7.5 IS=1E-18
.MODEL NSW NMOS KP=200U VTO=7.5 IS=1E-18
.ENDS
* END MODEL TLV2371
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
* 7:00 A.M.--7:00 P.M. U.S. Central Time
* (800) 272-9959
* For Applications support, contact the Internet address:
* amps-apps@galaxy.nsc.com
*//////////////////////////////////////////////////////////
*LM358 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM358/NS 1 2 99 50 28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain = 100dB
*High bandwidth = 1MHz
*Low input offset voltage = 2mV
*Wide supply range = +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
* supply current is 1/2 of total device current.
* Output crossover distortion with dual supplies
* is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 5N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4940 10468
WIRE 352 -208 -384 -208
WIRE 608 -176 -176 -176
WIRE 352 -144 352 -208
WIRE 480 -144 352 -144
WIRE 208 -128 16 -128
WIRE 208 -112 208 -128
WIRE 416 -96 288 -96
WIRE 352 -64 352 -144
WIRE 288 -48 288 -96
WIRE 320 -48 288 -48
WIRE 416 -32 416 -96
WIRE 416 -32 384 -32
WIRE 448 -32 416 -32
WIRE 208 -16 208 -32
WIRE 320 -16 208 -16
WIRE 448 -16 448 -32
WIRE 608 0 608 -176
WIRE 208 16 208 -16
WIRE -384 112 -384 -208
WIRE -176 112 -176 -176
WIRE 16 112 16 -128
WIRE 448 112 448 64
WIRE 608 112 608 64
WIRE 608 112 448 112
WIRE 448 144 448 112
WIRE 608 160 608 112
FLAG 16 192 0
FLAG -176 192 0
FLAG 208 96 0
FLAG 448 224 0
FLAG 608 224 0
FLAG 352 0 0
FLAG -384 192 0
FLAG 480 -80 0
SYMBOL voltage 16 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(2.5 2.5 10)
SYMATTR SpiceLine Rser=1
SYMBOL schottky 624 64 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL schottky 624 224 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage -176 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 432 -32 R0
SYMATTR InstName R2
SYMATTR Value 1.7k
SYMBOL res 192 -128 R0
SYMATTR InstName R3
SYMATTR Value 5k
SYMBOL res 192 0 R0
SYMATTR InstName R4
SYMATTR Value 5k
SYMBOL voltage -384 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V3
SYMATTR Value 5v
SYMBOL cap 464 -144 R0
SYMATTR InstName C2
SYMATTR Value 100nF
SYMBOL Opamps\\opamp2 352 -96 R0
SYMATTR InstName U1
SYMATTR Value LM358/NS
SYMBOL res 432 128 R0
SYMATTR InstName R1
SYMATTR Value 3.3k
TEXT -210 248 Left 2 !.tran 0 1 0 1e-6 startup
TEXT 408 328 Left 2 !.lib opamp.sub
TEXT 720 -160 Left 2 !.SUBCKT MCP6001 1 2 3 4 5\n\n*               | | | | |\n\n*               | | | | Output\n\n*               | | | Negative Supply\n\n*               | | Positive Supply\n\n*               | Inverting Input\n\n*               Non-inverting Input\n\n*\n\n********************************************************************************\n\n* Software License Agreement                                                   *\n\n*                                                                              *\n\n* The software supplied herewith by Microchip Technology Incorporated (the     *\n\n* "Company") is intended and supplied to you, the Company's customer, for use  *\n\n* soley and exclusively on Microchip products.                                 *\n\n*                                                                              *\n\n* The software is owned by the Company and/or its supplier, and is protected   *\n\n* under applicable copyright laws. All rights are reserved. Any use in         *\n\n* violation of the foregoing restrictions may subject the user to criminal     *\n\n* sanctions under applicable laws, as well as to civil liability for the       *\n\n* breach of the terms and conditions of this license.                          *\n\n*                                                                              *\n\n* THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER    *\n\n* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED        *\n\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO  *\n\n* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR    *\n\n* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.     *\n\n********************************************************************************\n\n*\n\n* Macromodel for the MCP6001/2/4 op amp family:\n\n*   MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004\n\n*\n\n* Revision History:\n\n*   REV A: 21-Jun-02, Created model\n\n*   REV B: 16-Jul-02, Improved output stage\n\n*   REV C: 03-Jan-03, Added MCP6001\n\n*   REV D: 19-Aug-06, Added over temperature, improved output stage, \n\n*                     fixed overdrive recovery time\n\n*   REV E: 27-Jul-07, Updated output impedance for better model stability w/cap load\n\n*   REV F: 09-Jul-12, Added MCP6001R, MCP6001U\n\n*\n\n* Recommendations:\n\n*   Use PSPICE (other simulators may require translation)\n\n*   For a quick, effective design, use a combination of: data sheet\n\n*     specs, bench testing, and simulations with this macromodel\n\n*   For high impedance circuits, set GMIN=100F in .OPTIONS\n\n*\n\n* Supported:\n\n*   Typical performance for temperature range (-40 to 125) degrees Celsius\n\n*   DC, AC, Transient, and Noise analyses.\n\n*   Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,\n\n*     open loop gain, voltage ranges, supply current, ... , etc.\n\n*   Temperature effects for Ibias, Iquiescent, Iout short circuit \n\n*   current, Vsat on both rails, Slew Rate vs. Temp and P.S.\n\n*\n\n* Not Supported:\n\n*   Some Variation in specs vs. Power Supply Voltage\n\n*   Monte Carlo (Vos, Ib), Process variation\n\n*   Distortion (detailed non-linear behavior)\n\n*   Behavior outside normal operating region\n\n*\n\n* Input Stage\n\nV10  3 10 -500M\n\nR10 10 11 6.90K \n\nR11 10 12 6.90K \n\nC11 11 12 0.2p\n\nC12 1  0 6.00P \n\nE12 71 14 POLY(4) 20 0 21 0 26 0 27 0   1.00M 20.1 20.1 1 1\n\nG12 1 0 62 0 1m \n\nM12 11 14 15 15 NMI L=2.00U W=42.0U\n\nM14 12  2 15 15 NMI L=2.00U W=42.0U\n\nG14 2 0 62 0 1m \n\nC14  2  0 6.00P \n\nI15 15  4 50.0U\n\nV16 16  4 -300M\n\nGD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1)) \n\nV13  3 13 -300M\n\nGD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1n)(2m,1m)(3m,1)) \n\nR70 1 0 20.6T  \n\nR71 2 0 20.6T \n\nR72 1 2 20T \n\nI80 1 2 0.5p\n\n*\n\n* Noise, PSRR, and CMRR\n\nI20 21 20 423U\n\nD20 20  0 DN1\n\nD21  0 21 DN1\n\nG26  0 26 POLY(1) 3 4   110U -49U\n\nR26 26  0 1\n\nG27  0 27 POLY(2) 1 0 2 0   -440U 39.7U 39.7U\n\nR27 27  0 1\n\n*\n\n* Open Loop Gain, Slew Rate\n\nG30  0 30 POLY(1) 12 11   0 1\n\nR30 30  0 1K\n\nG31  0 31 POLY(1) 3 4 86 5.25\n\nR31 31  0 1 TC=2.8m\n\nGD31 30 31 TABLE {V(30,31)} ((-11,-1)(-10,-10n)(0,0)(1m,1000))\n\nG32 32  0 POLY(1) 3 4 113.7 3.5\n\nR32 32  0 1 TC=2.65m\n\nGD32 30 32 TABLE {V(30,32)} ((-1m,-1000)(0,0)(10,10n)(11,1))\n\nG33 0 33 30 0 1m\n\nR33 33 0 1k\n\nG34  0 34 33 0 425M\n\nR34  34 0 1K\n\nC34  34 0 74U\n\nG37  0 37 34 0 1m\n\nR37  37 0 1K\n\nC37  37 0 41.6P \n\nG38  0 38 37 0 1m\n\nR38  39 0 1K\n\nL38  38 39 100U\n\nE38  35 0 38 0 1\n\nG35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(16,1n))(16.1,1))\n\nG36 33 0 TABLE {V(35,4)} ((-16.1,-1)((-16,-1n)(0,0)(1,1n))\n\n*\n\n* Output Stage \n\nR80 50 0 100MEG\n\nG50 0 50 57 96 2\n\nR58 57  96 0.50\n\nR57 57  0 750\n\nC58  5  0 2.00P\n\nG57  0 57 POLY(3) 3 0 4 0 35 0   0 0.67M 0.67M 1.5M\n\nGD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))\n\nGD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))\n\nE55 55  0 POLY(2) 3 0 51 0 -0.7m 1 -40.0M\n\nE56 56  0 POLY(2) 4 0 52 0 1.2m 1 -37.0M\n\nR51 51 0 1k\n\nR52 52 0 1k\n\nGD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))\n\nGD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) \n\nG53  3  0 POLY(1) 51 0  -49U 1M\n\nG54  0  4 POLY(1) 52 0  -49U -1M\n\n*\n\n* Current Limit \n\nG99 96 5 99 0 1 \n\nR98 0 98 1 TC=-2.8M,2.63U \n\nG97 0 98 TABLE { V(96,5) } ((-11.0,-10.0M)(-1.00M,-9.9M)(0,0)(1.00M,9.9M)(11.0,10.0M)) \n\nE97 99 0 VALUE { V(98)*((V(3)-V(4))*359M + 310M)} \n\nD98 4 5 DESD \n\nD99 5 3 DESD \n\n*\n\n* Temperature / Voltage Sensitive IQuiscent\n\nR61 0 61 100 TC 3.11M 4.51U\n\nG61 3 4 61 0 1\n\nG60 0 61 TABLE {V(3, 4)} \n\n+ ((0,0)(900M,0.0106U)(1.00,0.20U)(1.3,0.63U)\n\n+ (1.5,0.66U)(1.6,1.06U)(5.5,1.10U))\n\n*\n\n* Temp Sensitive offset voltage \n\nI73 0 70 DC 1uA \n\nR74 0 70 1 TC=2 \n\nE75 1 71 70 0 1 \n\n*\n\n* Temp Sensistive IBias \n\nI62 0 62 DC 1uA \n\nR62 0 62 REXP 58.2u \n\n* Voltage on R62 used for G12, G14 in input stage\n\n*\n\n* Models\n\n.MODEL NMI NMOS\n\n.MODEL DESD  D   N=1 IS=1.00E-15 \n\n.MODEL DL  D   N=1 IS=1F \n\n.MODEL DN1 D   IS=1P KF=146E-18 AF=1\n\n.MODEL REXP RES TCE=10.1 \n\n.ENDS MCP6001
TEXT 2008 -200 Left 2 !* LMX24_LM2902 - Rev. A\n\n* Created by Paul Goedeke; November 16, 2018\n\n* Created with Green-Williams-Lis Op Amp Macro-model Architecture\n\n* Copyright 2018 by Texas Instruments Corporation\n\n******************************************************\n\n* MACRO-MODEL SIMULATED PARAMETERS:\n\n******************************************************\n\n* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY  WITH RL, CL EFFECTS (Aol)\n\n* UNITY GAIN BANDWIDTH (GBW)\n\n* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)\n\n* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)\n\n* DIFFERENTIAL INPUT IMPEDANCE (Zid)\n\n* COMMON-MODE INPUT IMPEDANCE (Zic)\n\n* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)\n\n* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)\n\n* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)\n\n* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)\n\n* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)\n\n* SHORT-CIRCUIT OUTPUT CURRENT (Isc)\n\n* QUIESCENT CURRENT (Iq)\n\n* SETTLING TIME VS. CAPACITIVE LOAD (ts)\n\n* SLEW RATE (SR)\n\n* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD\n\n* LARGE SIGNAL RESPONSE\n\n* OVERLOAD RECOVERY TIME (tor)\n\n* INPUT BIAS CURRENT (Ib)\n\n* INPUT OFFSET CURRENT (Ios)\n\n* INPUT OFFSET VOLTAGE (Vos)\n\n* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)\n\n* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)\n\n* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)\n\n******************************************************\n\n.subckt LMX24_LM2902 IN+ IN- VCC VEE OUT\n\n******************************************************\n\n* MODEL DEFINITIONS:\n\n.model BB_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=0)\n\n.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)\n\n.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3)\n\n.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)\n\n.model R_NOISELESS RES(T_ABS=-273.15)\n\n******************************************************\n\n\n\n\nI_OS        ESDn MID -18N\n\nI_B         37 MID -20N\n\nV_GRp       57 MID 180\n\nV_GRn       58 MID -180\n\nV_ISCp      51 MID 40\n\nV_ISCn      52 MID -40\n\nV_ORn       45 VCLP -1.2\n\nV11         56 44 0\n\nV_ORp       43 VCLP 1.2\n\nV12         55 42 0\n\nV4          33 OUT 0\n\nVCM_MIN     79 VEE_B 0\n\nVCM_MAX     80 VCC_B -1.5\n\nI_Q         VCC VEE 175U\n\nV_OS        86 37 1.8M\n\nR61         MID 22 R_NOISELESS 8.001K \n\nC16         22 23 19.89P \n\nR58         23 22 R_NOISELESS 100MEG \n\nGVCCS2      23 MID VEE_B MID  -992.9M\n\nR57         MID 23 R_NOISELESS 1 \n\nXU3         VCC_B VEE_B 24 25 26 27 MID PHASEREV_0\n\nXU1         VIMON MID CRS CRS_DIST_0\n\nC21         28 29 313.8N  \n\nC22         30 31 636.6F  \n\nR70         31 MID R_NOISELESS 2.5 \n\nR67         31 30 R_NOISELESS 10K \n\nR66         30 MID R_NOISELESS 1 \n\nXU2         31 MID MID 32 VCCS_LIM_ZO_0\n\nGVCCS4      30 MID 29 MID  -4.3\n\nR65         29 MID R_NOISELESS 3.03K \n\nR64         29 28 R_NOISELESS 10K \n\nR63         28 MID R_NOISELESS 1 \n\nGVCCS3      28 MID CL_CLAMP 33  -90\n\nR62         32 MID R_NOISELESS 1 \n\nC29         34 MID 47F \n\nR78         MID 34 R_NOISELESS 1MEG \n\nGVCCS9      34 MID 35 MID  -1U\n\nXU5         36 MID MID CLAMP CRS MID VCCS_LIM_2_EN_0\n\nC28         38 MID 1P \n\nR77         39 38 R_NOISELESS 100 \n\nC27         40 MID 1P \n\nR76         41 40 R_NOISELESS 100 \n\nR75         MID 42 R_NOISELESS 1 \n\nGVCCS8      42 MID 43 MID  -1\n\nR74         44 MID R_NOISELESS 1 \n\nGVCCS7      44 MID 45 MID  -1\n\nXi_nn       ESDn MID FEMT_0\n\nXi_np       MID 37 FEMT_0\n\nXe_n        ESDp 37 VNSE_0\n\nC25         35 MID 47F \n\nR69         MID 35 R_NOISELESS 1MEG \n\nGVCCS6      35 MID VSENSE MID  -1U\n\nC20         CLAMP MID 9N \n\nR68         MID CLAMP R_NOISELESS 1MEG \n\nR44         MID 36 R_NOISELESS 1MEG \n\nXVCCS_LIM_1 46 27 MID 36 VCCS_LIM_1_0\n\nRdummy      MID 33 R_NOISELESS 25K \n\nRx          33 32 R_NOISELESS 250K \n\nR56         MID 47 R_NOISELESS 1K \n\nC15         47 48 1.592P \n\nR55         48 47 R_NOISELESS 100MEG \n\nGVCCS1      48 MID VCC_B MID  -100M\n\nR54         MID 48 R_NOISELESS 1 \n\nR49         MID 49 R_NOISELESS 4.616K \n\nC14         49 50 26.53P \n\nR48         50 49 R_NOISELESS 100MEG \n\nG_adjust    50 MID ESDp MID  -685.2M\n\nRsrc        MID 50 R_NOISELESS 1 \n\nXIQPos      VIMON MID MID VCC VCCS_LIMIT_IQ_0\n\nXIQNeg      MID VIMON VEE MID VCCS_LIMIT_IQ_0\n\nC_DIFF      ESDp ESDn 1P \n\nXCL_AMP     51 52 VIMON MID 53 54 CLAMP_AMP_LO_0\n\nSOR_SWp     CLAMP 55 CLAMP 55  S_VSWITCH_1\n\nSOR_SWn     56 CLAMP 56 CLAMP  S_VSWITCH_2\n\nXGR_AMP     57 58 59 MID 60 61 CLAMP_AMP_HI_0\n\nR39         57 MID R_NOISELESS 1T \n\nR37         58 MID R_NOISELESS 1T \n\nR42         VSENSE 59 R_NOISELESS 1M \n\nC19         59 MID 1F \n\nR38         60 MID R_NOISELESS 1 \n\nR36         MID 61 R_NOISELESS 1 \n\nR40         60 62 R_NOISELESS 1M \n\nR41         61 63 R_NOISELESS 1M \n\nC17         62 MID 1F \n\nC18         MID 63 1F \n\nXGR_SRC     62 63 CLAMP MID VCCS_LIM_GR_0\n\nR21         53 MID R_NOISELESS 1 \n\nR20         MID 54 R_NOISELESS 1 \n\nR29         53 64 R_NOISELESS 1M \n\nR30         54 65 R_NOISELESS 1M \n\nC9          64 MID 1F \n\nC8          MID 65 1F \n\nXCL_SRC     64 65 CL_CLAMP MID VCCS_LIM_4_0\n\nR22         51 MID R_NOISELESS 1T \n\nR19         MID 52 R_NOISELESS 1T \n\nXCLAWp      VIMON MID 66 VCC_B VCCS_LIM_CLAW+_0\n\nXCLAWn      MID VIMON VEE_B 67 VCCS_LIM_CLAW-_0\n\nR12         66 VCC_B R_NOISELESS 1K \n\nR16         66 68 R_NOISELESS 1M \n\nR13         VEE_B 67 R_NOISELESS 1K \n\nR17         69 67 R_NOISELESS 1M \n\nC6          69 MID 1F \n\nC5          MID 68 1F \n\nG2          VCC_CLP MID 68 MID  -1M\n\nR15         VCC_CLP MID R_NOISELESS 1K \n\nG3          VEE_CLP MID 69 MID  -1M\n\nR14         MID VEE_CLP R_NOISELESS 1K \n\nXCLAW_AMP   VCC_CLP VEE_CLP VOUT_S MID 70 71 CLAMP_AMP_LO_0\n\nR26         VCC_CLP MID R_NOISELESS 1T \n\nR23         VEE_CLP MID R_NOISELESS 1T \n\nR25         70 MID R_NOISELESS 1 \n\nR24         MID 71 R_NOISELESS 1 \n\nR27         70 72 R_NOISELESS 1M \n\nR28         71 73 R_NOISELESS 1M \n\nC11         72 MID 1F \n\nC10         MID 73 1F \n\nXCLAW_SRC   72 73 CLAW_CLAMP MID VCCS_LIM_3_0\n\nH2          41 MID V11 -1\n\nH3          39 MID V12 1\n\nC12         SW_OL MID 100P \n\nR32         74 SW_OL R_NOISELESS 100 \n\nR31         74 MID R_NOISELESS 1 \n\nXOL_SENSE   MID 74 40 38 OL_SENSE_0\n\nS1          28 29 SW_OL MID  S_VSWITCH_3\n\nH1          75 MID V4 1K\n\nS7          VEE OUT VEE OUT  S_VSWITCH_4\n\nS6          OUT VCC OUT VCC  S_VSWITCH_5\n\nR11         MID 76 R_NOISELESS 1T \n\nR18         76 VOUT_S R_NOISELESS 100 \n\nC7          VOUT_S MID 10P \n\nE5          76 MID OUT MID  1\n\nC13         VIMON MID 10P \n\nR33         75 VIMON R_NOISELESS 100 \n\nR10         MID 75 R_NOISELESS 1T \n\nR47         77 VCLP R_NOISELESS 100 \n\nC24         VCLP MID 100P \n\nE4          77 MID CL_CLAMP MID  1\n\nR46         MID CL_CLAMP R_NOISELESS 1K \n\nG9          CL_CLAMP MID CLAW_CLAMP MID  -1M\n\nR45         MID CLAW_CLAMP R_NOISELESS 1K \n\nG8          CLAW_CLAMP MID 34 MID  -1M\n\nR43         MID VSENSE R_NOISELESS 1K \n\nG15         VSENSE MID CLAMP MID  -1M\n\nC4          46 MID 1F \n\nR9          46 78 R_NOISELESS 1M \n\nR7          MID 79 R_NOISELESS 1T \n\nR6          80 MID R_NOISELESS 1T \n\nR8          MID 78 R_NOISELESS 1 \n\nXVCM_CLAMP  26 MID 78 MID 80 79 VCCS_EXT_LIM_0\n\nE1          MID 0 81 0  1\n\nR89         VEE_B 0 R_NOISELESS 1 \n\nR5          82 VEE_B R_NOISELESS 1M \n\nC3          82 0 1F \n\nR60         81 82 R_NOISELESS 1MEG \n\nC1          81 0 1 \n\nR3          81 0 R_NOISELESS 1T \n\nR59         83 81 R_NOISELESS 1MEG \n\nC2          83 0 1F \n\nR4          VCC_B 83 R_NOISELESS 1M \n\nR88         VCC_B 0 R_NOISELESS 1 \n\nG17         VEE_B 0 VEE 0  -1\n\nG16         VCC_B 0 VCC 0  -1\n\nR_PSR       84 24 R_NOISELESS 1K \n\nG_PSR       24 84 47 22  -1M\n\nR2          25 ESDn R_NOISELESS 1M \n\nR1          84 85 R_NOISELESS 1M \n\nR_CMR       86 85 R_NOISELESS 1K \n\nG_CMR       85 86 49 MID  -1M\n\nC_CMn       ESDn MID 2P \n\nC_CMp       MID ESDp 2P \n\nR53         ESDn MID R_NOISELESS 1T \n\nR52         MID ESDp R_NOISELESS 1T \n\nR35         IN- ESDn R_NOISELESS 10M \n\nR34         IN+ ESDp R_NOISELESS 10M \n\n\n.MODEL S_VSWITCH_1 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)\n\n.MODEL S_VSWITCH_2 VSWITCH (RON=10M ROFF=1T VON=10M VOFF=0)\n\n.MODEL S_VSWITCH_3 VSWITCH (RON=1M ROFF=1T VON=500M VOFF=100M)\n\n.MODEL S_VSWITCH_4 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)\n\n.MODEL S_VSWITCH_5 VSWITCH (RON=50 ROFF=1T VON=500M VOFF=450M)\n\n\n.ENDS LMX24_LM2902\n\n*\n\n.SUBCKT PHASEREV_0  VCC VEE VIN+ VIN- VOUT+ VOUT- MID\n\nE1 VOUT+ MID VALUE={IF(V(VIN+,MID)<V(VEE,MID)-0.3,V(VCC,MID),V(VIN+,MID))}\n\nE2 VOUT- MID VALUE={IF(V(VIN-,MID)<V(VEE,MID)-0.3,V(VCC,MID),V(VIN-,MID))}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT CRS_DIST_0  VIMON MID OUT\n\nV1 VREF MID -40M\n\nESHF VSHF MID VIMON VREF 1\n\nGZC MID ZC VALUE = {SGN(V(VSHF,MID))}\n\nR1 ZC MID 1\n\nC1 ZC MID 2U\n\nGCR MID OUT VALUE = {IF((ABS(V(ZC,MID))<=0.9),0,1)}\n\nR2 OUT MID 1\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_ZO_0  VC+ VC- IOUT+ IOUT-\n\n.PARAM GAIN = 4E3\n\n.PARAM IPOS = 1E6\n\n.PARAM INEG = -1E6\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_2_EN_0  VC+ VC- IOUT+ IOUT- EN MID\n\n.PARAM GAIN = 8.4E-4\n\n.PARAM IPOS = 0.0048\n\n.PARAM INEG = -0.0048\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(EN,MID)*V(VC+,VC-),INEG,IPOS)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT FEMT_0  1 2\n\n.PARAM FLWF=1E-3\n\n.PARAM NLFF=500\n\n.PARAM NVRF=500\n\n.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}\n\n.PARAM RNVF={1.184*PWR(NVRF,2)}\n\n.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16\n\nI1 0 7 10E-3\n\nI2 0 8 10E-3\n\nD1 7 0 DVNF\n\nD2 8 0 DVNF\n\nE1 3 6 7 8 {GLFF}\n\nR1 3 0 1E9\n\nR2 3 0 1E9\n\nR3 3 6 1E9\n\nE2 6 4 5 0 10\n\nR4 5 0 {RNVF}\n\nR5 5 0 {RNVF}\n\nR6 3 4 1E9\n\nR7 4 0 1E9\n\nG1 1 2 3 4 1E-6\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VNSE_0  1 2\n\n.PARAM FLW=10\n\n.PARAM NLF=80\n\n.PARAM NVR=35\n\n.PARAM GLF={PWR(FLW,0.25)*NLF/1164}\n\n.PARAM RNV={1.184*PWR(NVR,2)}\n\n.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16\n\nI1 0 7 10E-3\n\nI2 0 8 10E-3\n\nD1 7 0 DVN\n\nD2 8 0 DVN\n\nE1 3 6 7 8 {GLF}\n\nR1 3 0 1E9\n\nR2 3 0 1E9\n\nR3 3 6 1E9\n\nE2 6 4 5 0 10\n\nR4 5 0 {RNV}\n\nR5 5 0 {RNV}\n\nR6 3 4 1E9\n\nR7 4 0 1E9\n\nE3 1 2 3 4 1\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_1_0  VC+ VC- IOUT+ IOUT-\n\n.PARAM GAIN = 1E-4\n\n.PARAM IPOS = .5\n\n.PARAM INEG = -.5\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIMIT_IQ_0  VC+ VC- IOUT+ IOUT-\n\n.PARAM GAIN = 1E-3\n\nG1 IOUT- IOUT+ VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT CLAMP_AMP_LO_0  VC+ VC- VIN COM VO+ VO-\n\n.PARAM G=1\n\nGVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}\n\nGVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT CLAMP_AMP_HI_0  VC+ VC- VIN COM VO+ VO-\n\n.PARAM G=10\n\nGVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}\n\nGVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_GR_0  VC+ VC- IOUT+ IOUT-\n\n.PARAM GAIN = 1\n\n.PARAM IPOS = 0.013\n\n.PARAM INEG = -0.013\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_4_0  VC+ VC- IOUT+ IOUT-\n\n.PARAM GAIN = 1\n\n.PARAM IPOS = 1.04\n\n.PARAM INEG = -1.04\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_CLAW+_0  VC+ VC- IOUT+ IOUT-\n\nG1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =\n\n+(0, 1.17E-03)\n\n+(0.0046251, 1.17E-3)\n\n+(0.15716, 1.21E-3)\n\n+(1.3309, 1.28E-3)\n\n+(35.075, 2.12E-3)\n\n+(35.680, 2.55E-3)\n\n+(36.033, 2.84E-3)\n\n+(37.416, 7.97E-3)\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_LIM_CLAW-_0  VC+ VC- IOUT+ IOUT-\n\nG1 IOUT+ IOUT- TABLE {ABS(V(VC+,VC-))} =\n\n+(0.010, 2.50E-5)\n\n+(0.070, 2.50E-5)\n\n+(0.090, 5.80E-4)\n\n+(0.100, 6.06E-4)\n\n+(0.760, 7.14E-4) \n\n+(1.440, 7.62E-4)\n\n+(8.000, 1.10E-3)\n\n+(13.60, 1.55E-3)\n\n+(15.45, 1.75E-3)\n\n+(17.26, 2.15E-3)\n\n+(18.87, 2.94E-3)\n\n+(21.58, 4.50E-3)\n\n+(25.53, 1.02E-2)\n\n.ENDS\n\n*\n\n\n\n\n\n.SUBCKT VCCS_LIM_3_0  VC+ VC- IOUT+ IOUT-\n\n.PARAM GAIN = 1\n\n.PARAM IPOS = 0.435\n\n.PARAM INEG = -0.435\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT OL_SENSE_0  COM SW+ OLN  OLP\n\nGSW+ COM SW+ VALUE = {IF((V(OLN,COM)>10E-3 | V(OLP,COM)>10E-3),1,0)}\n\n.ENDS\n\n*\n\n\n\n\n.SUBCKT VCCS_EXT_LIM_0  VIN+ VIN- IOUT- IOUT+ VP+ VP-\n\n.PARAM GAIN = 1\n\nG1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}\n\n.ENDS\n\n*
TEXT 2984 -208 Left 2 !* TLV2371\n\n*****************************************************************************\n\n* (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.                                            \n\n*****************************************************************************\n\n** This model is designed as an aid for customers of Texas Instruments.\n\n** TI and its licensors and suppliers make no warranties, either expressed\n\n** or implied, with respect to this model, including the warranties of \n\n** merchantability or fitness for a particular purpose.  The model is\n\n** provided solely on an "as is" basis.  The entire risk as to its quality\n\n** and performance is with the customer.\n\n*****************************************************************************\n\n*\n\n* This model is subject to change without notice. Texas Instruments\n\n* Incorporated is not responsible for updating this model.\n\n*\n\n*****************************************************************************\n\n*\n\n** Released by: Analog eLab Design Center, Texas Instruments Inc.\n\n* Part: TLV2371\n\n* Date: 01JUL2011\n\n* Model Type: ALL IN ONE\n\n* Simulator: PSPICE\n\n* Simulator Version: 16.0.0.p001\n\n* EVM Order Number: N/A\n\n* EVM Users Guide: N/A\n\n* Datasheet: SLOS270D - MARCH 2001 - REVISED JANUARY 2005\n\n*\n\n* Model Version: 1.0\n\n*\n\n*****************************************************************************\n\n*\n\n* Updates:\n\n*\n\n* Version 1.0 : \n\n* Release to Web\n\n*\n\n*****************************************************************************\n\n* THIS MODEL IS APPLICABLE TO TLV2370,TLV2371, TlV2372\n\n* BEGIN MODEL TLV2371\n\n* PINOUT ORDER +IN -IN +V -V OUT\n\n* PINOUT ORDER  3   4   6  2  1\n\n* BEGIN NOTES\n\n* FOR MORE ACCURATE CURRENTS\n\n* IF LOOKING AT BIAS CURRENT\n\n* USE GMIN-1E-13\n\n* MODEL TEMPERATURE RANGE IS\n\n* -40 C TO +125 C, NOT ALL\n\n* PARAMETERS TRACK THOSE OF\n\n* THE REAL PART VS TEMPERATURE\n\n* END NOTES\n\n* BEGIN FEATURES\n\n* OPEN LOOP GAIN AND PHASE\n\n* INPUT VOLTAGE NOISE W 1/F\n\n* INPUT CURRENT NOISE\n\n* INPUT BIAS CURRENT\n\n* INPUT BIAS CURRENT VS TEMPERATURE\n\n* INPUT CAPACITANCE\n\n* INPUT COMMON MODE VOLTAGE RANGE\n\n* INPUT VOS SHIFT WITH VCM\n\n* INPUT CLAMPS TO RAILS\n\n* CMRR WITH FREQUENCY EFFECTS\n\n* PSRR WITH FREQUENCY EFFECTS\n\n* SLEW RATE\n\n* QUIESCENT CURRENT\n\n* HIGH CLOAD EFFECTS\n\n* CLASS AB BIAS IN OUTPUT STAGE\n\n* OUTPUT CURRENT THROUGH SUPPLIES\n\n* OUTPUT CURRENT LIMITING\n\n* OUTPUT CLAMPS TO RAILS\n\n* OUTPUT SWING VS OUTPUT CURRENT\n\n* END FEATURES\n\n*****************************************************************************\n\n.SUBCKT TLV2371 3 4 6 2 1\n\nVEN 5 2 2\n\nREN 5 2 1E12\n\nQ20 7 8 9 QLN\n\nR3 10 11 2\n\nR4 12 11 2\n\nR10 8 13 1E3\n\nR11 14 15 1E3\n\nR12 16 6 4\n\nR13 2 17 4\n\nR16 18 19 200\n\nR17 20 21 4\n\nR18 9 22 4\n\nD5 23 6 DD\n\nD6 2 23 DD\n\nD7 24 0 DIN\n\nD8 25 0 DIN\n\nI8 0 24 0.1E-3\n\nI9 0 25 0.1E-3\n\nE2 9 0 2 0 1\n\nE3 21 0 6 0 1\n\nD9 26 0 DVN\n\nD10 27 0 DVN\n\nI10 0 26 0.1E-3\n\nI11 0 27 0.1E-3\n\nE4 28 4 26 27 0.025\n\nG2 29 4 24 25 2.9E-7\n\nR22 2 6 100E6\n\nE5 30 0 21 0 1\n\nE6 31 0 9 0 1\n\nE7 32 0 33 0 1\n\nR30 30 34 1E5\n\nR31 31 35 1E5\n\nR32 32 36 1E5\n\nR33 0 34 10\n\nR34 0 35 10\n\nR35 0 36 10\n\nE10 37 3 36 0 0.01\n\nR36 38 33 1E3\n\nR37 33 39 1E3\n\nC6 30 34 0.2E-12\n\nC7 31 35 0.2E-12\n\nC8 32 36 0.2E-12\n\nE11 40 37 35 0 0.8\n\nE12 29 40 34 0 0.8\n\nE14 41 9 21 9 0.5\n\nD11 18 21 DD\n\nD12 9 18 DD\n\nM1 42 43 17 17 NOUT L=3U W=80U\n\nM2 44 45 16 16 POUT L=3U W=80U\n\nM3 46 46 20 20 POUT L=3U W=80U\n\nM4 47 48 10 10 PIN L=3U W=110U\n\nM5 49 50 12 12 PIN L=3U W=110U\n\nM8 51 51 22 22 NOUT L=3U W=80U\n\nR43 52 45 100\n\nR44 53 43 100\n\nG3 18 41 54 41 0.2E-3\n\nR45 41 18 120E6\n\nC12 19 23 10E-12\n\nR46 9 47 2E3\n\nR47 9 49 2E3\n\nC13 47 49 1E-12\n\nC14 29 0 4E-12\n\nC15 28 0 4E-12\n\nC16 23 0 0.5E-12\n\nD13 43 7 DD\n\nD14 55 45 DD\n\nQ15 55 15 21 QLP\n\nV18 29 56 0\n\nM19 57 58 21 21 PIN L=6U W=500U\n\nE17 39 0 29 0 1\n\nE18 38 0 4 0 1\n\nM23 58 58 21 21 PIN L=6U W=500U\n\nV21 57 11 0\n\nR59 23 44 1\n\nR60 42 23 1\n\nJ1 59 29 59 JNC\n\nJ2 59 28 59 JNC\n\nJ3 28 60 28 JNC\n\nJ4 29 60 29 JNC\n\nC21 29 61 2E-12\n\nE20 62 41 49 47 1\n\nR62 62 54 1E4\n\nC23 54 41 0.1E-12\n\nG7 63 41 18 41 -1E-3\n\nG8 41 64 18 41 1E-3\n\nG9 41 65 51 9 1E-3\n\nG10 66 41 21 46 1E-3\n\nD17 66 63 DD\n\nD18 64 65 DD\n\nR66 63 66 100E6\n\nR67 65 64 100E6\n\nR68 66 21 1E3\n\nR69 9 65 1E3\n\nE23 21 52 21 66 1\n\nE24 53 9 65 9 1\n\nR70 64 41 1E6\n\nR71 65 41 1E6\n\nR72 41 66 1E6\n\nR73 41 63 1E6\n\nG11 6 2 67 0 315E-6\n\nR75 40 29 1E9\n\nR76 37 40 1E9\n\nR77 3 37 1E9\n\nR78 4 28 1E9\n\nR79 41 54 1E9\n\nR81 52 21 1E9\n\nR82 9 53 1E9\n\nR83 33 0 1E9\n\nG14 58 9 67 0 55U\n\nG15 46 51 67 0 80U\n\nE48 68 18 67 0 30\n\nE49 69 41 67 0 -30\n\nV49 70 69 15\n\nV50 71 68 -15\n\nR127 68 0 1E12\n\nR128 69 0 1E12\n\nM41 41 71 18 72 PSW L=1.5U W=150U\n\nM42 18 70 41 73 NSW L=1.5U\n\nR129 72 0 1E12\n\nR130 73 0 1E12\n\nM43 74 5 9 9 NEN L=3U W=300U\n\nM44 75 76 9 9 NEN L=3U W=3000U\n\nR131 74 21 1E4\n\nR132 75 77 1E6\n\nV51 77 9 1\n\nM45 78 78 21 21 PEN L=6U W=60U\n\nM46 5 78 21 21 PEN L=6U W=60U\n\nI20 78 9 0.1E-6\n\nC26 5 0 1E-12\n\nE50 67 0 79 9 1\n\nV52 75 79 1.111E-6\n\nR133 9 79 1E12\n\nC32 21 74 3E-15\n\nC33 77 75 3E-15\n\nI21 6 2 30E-6\n\nL1 23 1 4E-9\n\nR150 23 1 400\n\nV78 21 59 0\n\nV79 60 9 0\n\nR155 46 21 1E8\n\nR156 9 51 1E8\n\nR157 17 43 1E8\n\nR158 16 45 1E8\n\nRG1 0 67 1E9\n\nR159 61 28 100\n\nR225 50 28 25E3\n\nR226 48 56 25E3\n\nM48 80 81 2 2 NIQS L=3U W=1000U\n\nR297 80 6 61.5E3\n\nE94 81 2 67 0 2\n\nM49 82 74 9 9 NEN L=3U W=300U\n\nM50 76 82 9 9 NEN L=3U W=300U\n\nR298 82 77 1E4\n\nR299 76 77 1E4\n\nC35 77 82 40E-12\n\nM51 83 84 85 85 NIN L=3U W=110U\n\nM52 86 87 88 88 NIN L=3U W=110U\n\nR300 89 85 2\n\nR301 89 88 2\n\nR302 83 21 2E3\n\nR303 86 21 2E3\n\nC36 83 86 1E-12\n\nG36 18 41 90 41 0.2E-3\n\nR304 41 90 1E9\n\nC37 90 41 0.1E-12\n\nE97 91 41 86 83 1\n\nR305 91 90 1E4\n\nV115 92 56 1E-3\n\nR306 28 87 25E3\n\nR307 92 84 25E3\n\nM53 93 94 95 95 PIN L=6U W=500U\n\nR308 95 57 2E3\n\nV116 21 94 1.25\n\nM54 93 93 9 9 NIN L=3U W=500U\n\nM55 89 93 9 9 NIN L=3U W=500U\n\nE98 21 14 6 16 1\n\nE99 13 9 17 2 1\n\nC105 77 76 130E-12\n\nR233 78 21 1E12\n\nR334 93 9 1E12\n\nR335 58 21 1E12\n\nR336 94 21 1E12\n\nR337 2 81 1E12\n\nG37 28 0 96 0 6.6E-12\n\nI48 28 0 1E-12\n\nI49 0 97 1E-3\n\nD46 97 0 DD\n\nV119 97 98 0.7\n\nR633 0 98 1E6\n\nE100 99 0 98 0 -571\n\nR634 0 99 1E6\n\nD47 100 96 DD\n\nV120 99 100 83.5\n\nG38 29 0 96 0 6.6E-12\n\nI50 29 0 1E-12\n\nR635 0 96 1E6\n\nR636 96 100 1E11\n\n.MODEL DVN D KF=8E-12 IS=1E-16\n\n.MODEL DD D\n\n.MODEL DIN D\n\n.MODEL QLN NPN\n\n.MODEL QLP PNP\n\n.MODEL JNC NJF\n\n.MODEL POUT PMOS KP=200U VTO=-0.7\n\n.MODEL NOUT NMOS KP=200U VTO=0.7\n\n.MODEL PIN PMOS KP=200U VTO=-0.7\n\n.MODEL NIN NMOS KP=200U VTO=0.7\n\n.MODEL NIQS NMOS KP=200U VTO=0.7 IS=1E-18\n\n.MODEL NEN NMOS KP=200U VTO=0.5 IS=1E-18\n\n.MODEL PEN PMOS KP=200U VTO=-0.7 IS=1E-18\n\n.MODEL PSW PMOS KP=200U VTO=-7.5 IS=1E-18\n\n.MODEL NSW NMOS KP=200U VTO=7.5 IS=1E-18\n\n.ENDS\n\n* END MODEL TLV2371
TEXT 4088 -192 Left 2 !*//////////////////////////////////////////////////////////////////////\n* (C) National Semiconductor, Inc.\n* Models developed and under copyright by:\n* National Semiconductor, Inc.  \n \n*/////////////////////////////////////////////////////////////////////\n* Legal Notice: This material is intended for free software support.\n* The file may be copied, and distributed; however, reselling the \n*  material is illegal\n \n*////////////////////////////////////////////////////////////////////\n* For ordering or technical information on these models, contact:\n* National Semiconductor's Customer Response Center\n*                 7:00 A.M.--7:00 P.M.  U.S. Central Time\n*                                (800) 272-9959\n* For Applications support, contact the Internet address:\n*  amps-apps@galaxy.nsc.com\n \n*//////////////////////////////////////////////////////////\n*LM358 DUAL OPERATIONAL AMPLIFIER MACRO-MODEL\n*//////////////////////////////////////////////////////////\n*\n* connections:      non-inverting input\n*                   |   inverting input\n*                   |   |   positive power supply\n*                   |   |   |   negative power supply\n*                   |   |   |   |   output\n*                   |   |   |   |   |\n*                   |   |   |   |   |\n.SUBCKT LM358/NS    1   2  99  50  28\n*\n*Features:\n*Eliminates need for dual supplies\n*Large DC voltage gain =             100dB\n*High bandwidth =                     1MHz\n*Low input offset voltage =            2mV\n*Wide supply range =       +-1.5V to +-16V\n*\n*NOTE: Model is for single device only and simulated\n*      supply current is 1/2 of total device current.\n*      Output crossover distortion with dual supplies\n*      is not modeled.\n*\n****************INPUT STAGE**************\n*\nIOS 2 1 5N\n*^Input offset current\nR1 1 3 500K\nR2 3 2 500K\nI1 99 4 100U\nR3 5 50 517\nR4 6 50 517\nQ1 5 2 4 QX\nQ2 6 7 4 QX\n*Fp2=1.2 MHz\nC4 5 6 128.27P\n*\n***********COMMON MODE EFFECT***********\n*\nI2 99 50 75U\n*^Quiescent supply current\nEOS 7 1 POLY(1) 16 49 2E-3 1\n*Input offset voltage.^\nR8 99 49 60K\nR9 49 50 60K\n*\n*********OUTPUT VOLTAGE LIMITING********\nV2 99 8 1.63\nD1 9 8 DX\nD2 10 9 DX\nV3 10 50 .635\n*\n**************SECOND STAGE**************\n*\nEH 99 98 99 49 1\nG1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459\n*Fp1=7.86 Hz\nR5 98 9 101.2433MEG\nC3 98 9 200P\n*\n***************POLE STAGE***************\n*\n*Fp=2 MHz\nG3 98 15 9 49 1E-6\nR12 98 15 1MEG\nC5 98 15 7.9577E-14\n*\n*********COMMON-MODE ZERO STAGE*********\n*\n*Fpcm=10 KHz\nG4 98 16 3 49 5.6234E-8               \nL2 98 17 15.9M\nR13 17 16 1K\n*\n**************OUTPUT STAGE**************\n*\nF6 50 99 POLY(1) V6 300U 1\nE1 99 23 99 15 1\nR16 24 23 17.5\nD5 26 24 DX\nV6 26 22 .63V\nR17 23 25 17.5\nD6 25 27 DX\nV7 22 27 .63V\nV5 22 21 0.27V\nD4 21 15 DX\nV4 20 22 0.27V\nD3 15 20 DX\nL3 22 28 500P\nRL3 22 28 100K\n*\n***************MODELS USED**************\n*\n.MODEL DX D(IS=1E-15)\n.MODEL QX PNP(BF=1.111E3)\n*\n.ENDS\n*