* Z:\home\khalils\Downloads\files\data\raw_asc\ADG5243F.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vdd 0 15
V2 Vss 0 -15
V3 INx 0 PULSE(0 3 0 20n 20n 50u 200u)
C1 SF 0 12p
V6 VS1B 0 PULSE(0 40 50u 10u 50u 15u)
V7 VS1A 0 0
R3 0 D1 1k
C2 D1 0 5.1p
V5 _EN 0 0
R2 0 D2 1k
C5 D2 0 5.1p
R4 0 D3 1k
C6 D3 0 5.1p
C7 FF 0 12p
V4 VS2B 0 5
V8 VS2A 0 -10
V9 VS3B 0 SINE(0 10 10K)
V10 VS3A 0 5
V11 NegFV 0 -10
V12 PosFV 0 10
XU1 INx INx VS1A D1 VS1B VS2B D2 VS2A NegFV SF FF PosFV VS3A D3 VS3B Vss Vdd 0 _EN N001 ADG5243F ;pnba IN1/F1)IN2/F2)S1A)D1)S1B)S2B)D2)S2A)NEGFV)SF)FF)POSFV)S3A)D3)S3B)VSS)VDD)GND)_EN/F0)IN3
V13 N001 0 3
.tran 500u
* Switch Voltage Supplies
* Digital Input Voltage
* Simulation Commands
* --->Transient Analysis
* Switch Analog Inputs
* Note:\nInterrupt Flag recovery time with pull-up resistor not included\nCrosstalk between adjacent channel not included\nOn reistance curve modeled at 15V supplies\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG5243F.asy)
.lib ADG5243F.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2200 1060
WIRE -240 -400 -240 -416
WIRE -128 -400 -128 -416
WIRE -16 -400 -16 -416
WIRE 96 -400 96 -416
WIRE 592 -400 592 -432
WIRE 720 -400 720 -432
WIRE 496 -320 464 -320
WIRE -240 -304 -240 -320
WIRE -128 -304 -128 -320
WIRE -16 -304 -16 -320
WIRE 96 -304 96 -320
WIRE 864 -288 816 -288
WIRE 944 -288 864 -288
WIRE 1024 -288 944 -288
WIRE 944 -272 944 -288
WIRE 1024 -272 1024 -288
WIRE 496 -256 464 -256
WIRE 496 -192 464 -192
WIRE 1024 -192 1024 -208
WIRE -240 -176 -240 -192
WIRE -112 -176 -112 -192
WIRE 864 -160 816 -160
WIRE 1168 -160 864 -160
WIRE 1248 -160 1168 -160
WIRE 1168 -144 1168 -160
WIRE 1248 -144 1248 -160
WIRE 496 -128 464 -128
WIRE -240 -80 -240 -96
WIRE -112 -80 -112 -96
WIRE 496 -64 464 -64
WIRE 1248 -64 1248 -80
WIRE 864 -32 816 -32
WIRE 1392 -32 864 -32
WIRE 1472 -32 1392 -32
WIRE 1392 -16 1392 -32
WIRE 1472 -16 1472 -32
WIRE 496 0 464 0
WIRE 496 48 464 48
WIRE 848 48 816 48
WIRE 1472 64 1472 48
WIRE -240 112 -240 96
WIRE -112 112 -112 96
WIRE 496 112 464 112
WIRE 864 112 816 112
WIRE 1008 112 864 112
WIRE 496 176 400 176
WIRE 848 176 816 176
WIRE 896 176 848 176
WIRE 1008 192 1008 176
WIRE -240 208 -240 192
WIRE -112 208 -112 192
WIRE 400 208 400 176
WIRE 896 256 896 240
WIRE 560 272 560 240
WIRE 672 288 672 240
WIRE 752 304 752 240
WIRE 400 320 400 288
WIRE -240 352 -240 336
WIRE -112 352 -112 336
WIRE -240 448 -240 432
WIRE -112 448 -112 432
WIRE -240 592 -240 576
WIRE -112 592 -112 576
WIRE -240 688 -240 672
WIRE -112 688 -112 672
FLAG -240 -304 0
FLAG -128 -304 0
FLAG -128 -416 Vdd
FLAG -240 -416 Vss
FLAG -112 -80 0
FLAG 752 304 0
FLAG 896 256 0
FLAG 848 176 SF
FLAG -240 208 0
FLAG -112 208 0
FLAG -112 96 VS1B
FLAG -240 96 VS1A
FLAG 1024 -192 0
FLAG 944 -192 0
FLAG -112 -192 INx
FLAG 464 48 INx
FLAG 464 -320 VS1A
FLAG 672 288 Vss
FLAG 720 -432 Vdd
FLAG 864 -288 D1
FLAG -240 -80 0
FLAG -240 -192 _EN
FLAG 848 48 _EN
FLAG 464 -192 VS2A
FLAG 464 112 INx
FLAG 464 -128 VS2B
FLAG 464 -64 VS3A
FLAG 464 0 VS3B
FLAG 464 -256 VS1B
FLAG 1248 -64 0
FLAG 1168 -64 0
FLAG 864 -160 D2
FLAG 1472 64 0
FLAG 1392 64 0
FLAG 864 -32 D3
FLAG 1008 192 0
FLAG 864 112 FF
FLAG -240 448 0
FLAG -112 448 0
FLAG -240 688 0
FLAG -112 688 0
FLAG -240 336 VS2A
FLAG -112 336 VS2B
FLAG -240 576 VS3A
FLAG -112 576 VS3B
FLAG -16 -304 0
FLAG 96 -304 0
FLAG 96 -416 NegFV
FLAG -16 -416 PosFV
FLAG 592 -432 PosFV
FLAG 560 272 NegFV
FLAG 400 320 0
SYMBOL voltage -128 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -240 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -112 -192 M0
WINDOW 3 -370 99 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 20n 20n 50u 200u)
SYMATTR InstName V3
SYMBOL cap 880 176 R0
SYMATTR InstName C1
SYMATTR Value 12p
SYMBOL voltage -112 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value PULSE(0 40 50u 10u 50u 15u)
SYMBOL voltage -240 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value 0
SYMBOL res 928 -176 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL cap 1008 -272 R0
SYMATTR InstName C2
SYMATTR Value 5.1p
SYMBOL voltage -240 -192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 0
SYMBOL res 1152 -48 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL cap 1232 -144 R0
SYMATTR InstName C5
SYMATTR Value 5.1p
SYMBOL res 1376 80 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL cap 1456 -16 R0
SYMATTR InstName C6
SYMATTR Value 5.1p
SYMBOL cap 992 112 R0
SYMATTR InstName C7
SYMATTR Value 12p
SYMBOL voltage -112 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL voltage -240 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value -10
SYMBOL voltage -112 576 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V9
SYMATTR Value SINE(0 10 10K)
SYMBOL voltage -240 576 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V10
SYMATTR Value 5
SYMBOL voltage 96 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V11
SYMATTR Value -10
SYMBOL voltage -16 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V12
SYMATTR Value 10
SYMBOL ADG5243F 656 16 R0
SYMATTR InstName U1
SYMBOL voltage 400 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V13
SYMATTR Value 3
TEXT -264 -584 Left 2 !.tran 500u
TEXT -264 -520 Left 2 ;Switch Voltage Supplies
TEXT -264 -256 Left 2 ;Digital Input Voltage
TEXT -264 -608 Left 2 ;Simulation Commands
TEXT -120 -584 Left 2 ;--->Transient Analysis
TEXT -272 0 Left 2 ;Switch Analog Inputs
TEXT -264 -760 Left 2 ;Note:\nInterrupt Flag recovery time with pull-up resistor not included\nCrosstalk between adjacent channel not included\nOn reistance curve modeled at 15V supplies\nSwitch shown for a logic 0 input