* Z:\home\khalils\Downloads\files\data\raw_asc\AD4880.asc
* Generated by LTspice 26.0.1 for Windows.
V4 Refin 0 {VREF}
C9 0 ADC_out 0.1p
C10 0 ADC_out_dsp 0.1p
V1 VOCM 0 1.5
V2 _DIS 0 3.3
V_FS1 N006 0 {fs}
V_SEL1 N008 0 {sel}
V_DEC1 N007 0 {decimation}
V6 VS+ 0 5
V7 VS- 0 -1
V14 VDD33 0 3.3
V15 CNV 0 PULSE(0 1.1 {ACQ_delay} 0.2n 0.2n {0.9*(1/fs)} {1/fs})
Vin_n N003 Vin_n SINE(0 {input_Vpp/4} {input_freq}) AC 0.5 0
Vin_cm N003 0 {input_cm} AC 0
Vin_p Vin_p N003 SINE(0 {input_Vpp/4} {input_freq}) AC 0.5 0
C1 N001 N002 {Cfb}
C2 N004 N005 {Cfb}
XU1 N001 N002 NC_01 NC_02 Vin_p Vin_n NC_03 NC_04 N004 N005 _DIS CNV ADC_out ADC_out ADC_out_dsp VS+ VS- VOCM Refin VDD33 N006 N008 N007 0 AD4880 ;pnba ))))))))))_DISABLE_FDA)))))))VOCM))))))GND
.param VREF=3
* External voltage reference
.tran 0 20u 0.1u
* .noise V(ADC_out_dsp) Vin_p dec 100 10 1G
.meas NOISE output_noise_rms INTEG V(onoise) FROM 10 TO {Fmax_noise_integration}
.meas NOISE full_scale_sine_rms PARAM 2*VREF/(2*sqrt(2))
.meas NOISE dynamic_range PARAM 20*log10(full_scale_sine_rms/output_noise_rms)
.param Fmax_noise_integration = 1G
.meas NOISE ENOB PARAM (dynamic_range - 1.76)/6.02
* .ac dec 1000 1k 1G
* .noise V(ADC_out) Vin_p dec 100 10 1G
* AD4880 Digital Filtering Configuration
* ADC output pre-digital filtering
* ADC output post digital filtering (AC and NOISE simulations only)
* SEL input:\n The voltage applied at this input selects the\n digital filter type.\n 0V = No Filter \n 1V = Sinc1 \n 2V = Sinc5\n 3V = Sinc5 + Comp
* DEC input:\n The voltage applied at this pin sets\n the N value for decimation.\n For Sinc1 and Sinc5 Filters Decimation = N\n For Sinc5 +Comp Decimation = (N * 2)\n 2 = N = 2 \n 4 = N = 4 \n 8 = N = 8\n 16 =........\n ...............\n 256 = N = 256 (Max Setting for Sinc5 and Sinc5 + Comp)\n 512 = N = 512 (Sinc1 Only)\n 1024 = N = 1024 (Sinc1 Only)
* --> AD4880 digital filter output (ADC_out_dsp)\n does not support transient simulations
* Other signals
* Simulation commands
* Measurements
* Supplies
* FS input:\n A voltage equal to the sampling frequency in Hertz\n must be supplied at this input.
* Results can be found in the "SPICE Output Log" (View->"Spice Output Log" or Ctrl+L").
* 3dB bandwidth (AC analysis)
* Noise parameters: dynamic range and ENOB (NOISE analysis)
* --> Noise simulation with output BEFORE digital filtering (ADC_out)
* --> Noise simulation with output AFTER digital filtering (ADC_out_DSP)
.param decimation 4
* Input signal
.meas AC ADC_out_max MAX MAG(V(ADC_out))
.meas AC bw_3db FIND frequency WHEN mag(V(ADC_out))=(ADC_out_max/sqrt(2))
.param sel 3
* The default configuration (sel=3, decimation=4, fs=40MHz) results in a \nSinc5 + Compensation filter with a 3dB bandwidth of ~2MHz.
* --> SNR
* AD4880 must be used with an external 3V reference.\nThis parameter is used in the Dynamic Range calculations.
.param input_Vpp={5/1.03}
.param input_freq = 250k
.param input_cm = 1.5
.param fs = 40MEG
.param ACQ_delay = 0.1u
* --> ADC Sampling rate. For AD4880 min is 1.25 Msps, max 40 Msps
* --> Delay from simulation start to first sampling pulse
* Convert signal
.param Cfb = 220pF
* FDA feedback filtering
* --> 220pF result in a 3dB BW of 1 MHz for G=1.03
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4880.asy)
.lib AD4880.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 12976 6356
WIRE 4896 3056 4880 3056
WIRE 5168 3056 5152 3056
WIRE 4112 3072 4096 3072
WIRE 4336 3072 4320 3072
WIRE 4544 3072 4528 3072
WIRE 4880 3104 4880 3056
WIRE 5152 3104 5152 3056
WIRE 4096 3120 4096 3072
WIRE 4320 3120 4320 3072
WIRE 4528 3120 4528 3072
WIRE 4880 3216 4880 3184
WIRE 5152 3216 5152 3184
WIRE 4096 3232 4096 3200
WIRE 4320 3232 4320 3200
WIRE 4528 3232 4528 3200
WIRE 4416 3664 4320 3664
WIRE 4416 3680 4416 3664
WIRE 4416 3776 4416 3760
WIRE 5040 3808 4832 3808
WIRE 5120 3808 5040 3808
WIRE 5120 3840 5120 3808
WIRE 3504 3856 3488 3856
WIRE 3632 3856 3616 3856
WIRE 4320 3856 4320 3664
WIRE 4672 3856 4624 3856
WIRE 3488 3904 3488 3856
WIRE 3616 3904 3616 3856
WIRE 4320 3904 4320 3856
WIRE 4624 3904 4624 3856
WIRE 5120 3952 5120 3920
WIRE 3248 4032 3168 4032
WIRE 3248 4096 3168 4096
WIRE 2160 4176 2112 4176
WIRE 2624 4176 2160 4176
WIRE 2112 4208 2112 4176
WIRE 5040 4224 4944 4224
WIRE 5136 4224 5040 4224
WIRE 5040 4256 5040 4224
WIRE 2624 4288 2624 4176
WIRE 3248 4288 2624 4288
WIRE 4832 4288 4832 3808
WIRE 4832 4288 4672 4288
WIRE 2112 4336 2112 4288
WIRE 2112 4336 1904 4336
WIRE 5040 4352 5040 4320
WIRE 1904 4368 1904 4336
WIRE 2112 4368 2112 4336
WIRE 3248 4384 2624 4384
WIRE 4704 4384 4672 4384
WIRE 4944 4384 4944 4224
WIRE 4944 4384 4704 4384
WIRE 4704 4432 4704 4384
WIRE 4704 4432 4672 4432
WIRE 5040 4464 4672 4464
WIRE 5120 4464 5040 4464
WIRE 1904 4496 1904 4448
WIRE 2112 4496 2112 4448
WIRE 2160 4496 2112 4496
WIRE 2624 4496 2624 4384
WIRE 2624 4496 2160 4496
WIRE 5040 4496 5040 4464
WIRE 3248 4576 3168 4576
WIRE 5040 4592 5040 4560
WIRE 3248 4640 3168 4640
WIRE 3248 4704 3200 4704
WIRE 3248 4752 3200 4752
WIRE 3936 4832 3936 4800
WIRE 4320 5056 4320 4800
WIRE 4320 5056 4224 5056
WIRE 4448 5056 4448 4800
WIRE 4544 5056 4448 5056
WIRE 4224 5104 4224 5056
WIRE 4384 5104 4384 4800
WIRE 4544 5104 4544 5056
WIRE 4224 5200 4224 5184
WIRE 4384 5200 4384 5184
WIRE 4544 5200 4544 5184
FLAG 4416 3776 0
FLAG 5040 4352 0
FLAG 5040 4592 0
FLAG 5136 4224 ADC_out
FLAG 5120 4464 ADC_out_dsp
FLAG 4880 3216 0
FLAG 4896 3056 VOCM
FLAG 5152 3216 0
FLAG 5168 3056 _DIS
FLAG 4224 5200 0
FLAG 4384 5200 0
FLAG 4544 5200 0
FLAG 4096 3232 0
FLAG 4320 3232 0
FLAG 4112 3072 VS+
FLAG 4336 3072 VS-
FLAG 4528 3232 0
FLAG 4544 3072 VDD33
FLAG 5120 3952 0
FLAG 5040 3808 CNV
FLAG 4672 3856 VDD33
FLAG 4320 3856 Refin
FLAG 1904 4496 0
FLAG 2160 4176 Vin_p
FLAG 2160 4496 Vin_n
FLAG 3936 4832 0
FLAG 3504 3856 VS+
FLAG 3632 3856 VS-
FLAG 3200 4752 VOCM
FLAG 3200 4704 _DIS
SYMBOL voltage 4416 3664 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value {VREF}
SYMBOL cap 5024 4320 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C9
SYMATTR Value 0.1p
SYMBOL cap 5024 4560 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C10
SYMATTR Value 0.1p
SYMBOL voltage 4880 3088 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL voltage 5152 3088 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL voltage 4224 5088 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -86 14 Left 2
WINDOW 3 -80 45 Left 2
SYMATTR InstName V_FS1
SYMATTR Value {fs}
SYMBOL voltage 4384 5088 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -102 15 Left 2
WINDOW 3 -96 50 Left 2
SYMATTR InstName V_SEL1
SYMATTR Value {sel}
SYMBOL voltage 4544 5088 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -102 20 Left 2
WINDOW 3 -198 51 Left 2
SYMATTR InstName V_DEC1
SYMATTR Value {decimation}
SYMBOL voltage 4096 3104 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 5
SYMBOL voltage 4320 3104 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value -1
SYMBOL voltage 4528 3104 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V14
SYMATTR Value 3.3
SYMBOL voltage 5120 3824 R0
WINDOW 123 0 0 Left 0
WINDOW 39 36 120 Left 2
WINDOW 3 13 96 Left 2
SYMATTR Value PULSE(0 1.1 {ACQ_delay} 0.2n 0.2n {0.9*(1/fs)} {1/fs})
SYMATTR InstName V15
SYMBOL voltage 2112 4352 R0
WINDOW 123 47 66 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 15 95 Left 2
WINDOW 0 48 37 Left 2
SYMATTR Value2 AC 0.5 0
SYMATTR Value SINE(0 {input_Vpp/4} {input_freq})
SYMATTR InstName Vin_n
SYMBOL voltage 1904 4352 R0
WINDOW 123 41 74 Left 2
WINDOW 39 0 0 Left 0
WINDOW 0 42 49 Left 2
WINDOW 3 30 98 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName Vin_cm
SYMATTR Value {input_cm}
SYMBOL voltage 2112 4192 R0
WINDOW 123 42 70 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 15 95 Left 2
WINDOW 0 43 45 Left 2
SYMATTR Value2 AC 0.5 0
SYMATTR Value SINE(0 {input_Vpp/4} {input_freq})
SYMATTR InstName Vin_p
SYMBOL cap 3152 4032 R0
WINDOW 0 -22 10 Left 2
WINDOW 3 -56 54 Left 2
SYMATTR InstName C1
SYMATTR Value {Cfb}
SYMBOL cap 3152 4576 R0
WINDOW 0 -22 10 Left 2
WINDOW 3 -56 54 Left 2
SYMATTR InstName C2
SYMATTR Value {Cfb}
SYMBOL AD4880 3648 4320 R0
SYMATTR InstName U1
TEXT 4048 3640 Left 2 !.param VREF=3
TEXT 4016 3496 Left 4 ;External voltage reference
TEXT 1840 3320 Left 2 !.tran 0 20u 0.1u
TEXT 1840 3440 Left 2 ;.noise V(ADC_out_dsp) Vin_p dec 100 10 1G
TEXT 1864 5208 Left 2 !.meas NOISE output_noise_rms INTEG V(onoise) FROM 10 TO {Fmax_noise_integration}
TEXT 1864 5248 Left 2 !.meas NOISE full_scale_sine_rms PARAM 2*VREF/(2*sqrt(2))
TEXT 1864 5288 Left 2 !.meas NOISE dynamic_range PARAM 20*log10(full_scale_sine_rms/output_noise_rms)
TEXT 1864 5168 Left 2 !.param Fmax_noise_integration = 1G
TEXT 1864 5328 Left 2 !.meas NOISE ENOB PARAM (dynamic_range - 1.76)/6.02
TEXT 1840 3360 Left 2 ;.ac dec 1000 1k 1G
TEXT 1840 3400 Left 2 ;.noise V(ADC_out) Vin_p dec 100 10 1G
TEXT 3424 5000 Left 4 ;AD4880 Digital Filtering Configuration
TEXT 4960 4184 Left 4 ;ADC output pre-digital filtering
TEXT 4952 4424 Left 4 ;ADC output post digital filtering (AC and NOISE simulations only)
TEXT 3472 5168 Left 2 ;SEL input:\n  The voltage applied at this input selects the\n  digital filter type.\n    0V = No Filter \n    1V = Sinc1 \n    2V = Sinc5\n    3V = Sinc5 + Comp
TEXT 3472 5400 Left 2 ;DEC input:\n  The voltage applied at this pin sets\n  the N value for decimation.\n  For Sinc1 and Sinc5 Filters Decimation = N\n  For Sinc5 +Comp Decimation = (N * 2)\n  2 = N = 2 \n  4 = N = 4 \n  8 = N = 8\n  16 =........\n  ...............\n  256 =   N = 256 (Max Setting for Sinc5 and Sinc5 + Comp)\n  512 =   N = 512 (Sinc1 Only)\n  1024 = N = 1024 (Sinc1 Only)
TEXT 2408 3320 Left 2 ;--> AD4880 digital filter output (ADC_out_dsp)\n     does not support transient simulations
TEXT 4832 2992 Left 2 ;Other signals
TEXT 1808 3264 Left 2 ;Simulation commands
TEXT 1824 4912 Left 2 ;Measurements
TEXT 4032 2992 Left 2 ;Supplies
TEXT 3472 5056 Left 2 ;FS input:\n  A voltage equal to the sampling frequency in Hertz\n  must be supplied at this input.
TEXT 1848 4960 Left 2 ;Results can be found in the "SPICE Output Log" (View->"Spice Output Log" or Ctrl+L").
TEXT 1848 5016 Left 2 ;3dB bandwidth (AC analysis)
TEXT 1840 5128 Left 2 ;Noise parameters: dynamic range and ENOB (NOISE analysis)
TEXT 2408 3400 Left 2 ;--> Noise simulation with output BEFORE digital filtering (ADC_out)
TEXT 2408 3440 Left 2 ;--> Noise simulation with output AFTER digital filtering (ADC_out_DSP)
TEXT 4168 5384 Left 2 !.param decimation 4
TEXT 1848 3832 Left 4 ;Input signal
TEXT 1864 5048 Left 2 !.meas AC ADC_out_max MAX MAG(V(ADC_out))
TEXT 1864 5080 Left 2 !.meas AC bw_3db FIND frequency WHEN mag(V(ADC_out))=(ADC_out_max/sqrt(2))
TEXT 4168 5352 Left 2 !.param sel 3
TEXT 4168 5288 Left 2 ;The default configuration (sel=3, decimation=4, fs=40MHz) results in a \nSinc5 + Compensation filter with a 3dB bandwidth of ~2MHz.
TEXT 2976 5288 Left 2 ;--> SNR
TEXT 4040 3576 Left 2 ;AD4880 must be used with an external 3V reference.\nThis parameter is used in the Dynamic Range calculations.
TEXT 1872 3888 Left 2 !.param input_Vpp={5/1.03}\n.param input_freq = 250k\n.param input_cm = 1.5
TEXT 5136 3984 Left 2 !.param fs = 40MEG\n.param ACQ_delay = 0.1u
TEXT 5472 3976 Left 2 ;--> ADC Sampling rate. For AD4880 min is 1.25 Msps, max 40 Msps
TEXT 5472 4008 Left 2 ;--> Delay from simulation start to first sampling pulse
TEXT 4920 3672 Left 4 ;Convert signal
TEXT 2648 3808 Left 2 !.param Cfb = 220pF
TEXT 2624 3752 Left 4 ;FDA feedback filtering
TEXT 2696 3840 Left 2 ;--> 220pF result in a 3dB BW of 1 MHz for G=1.03
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RECTANGLE Normal 4752 3808 4016 3520 2
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RECTANGLE Normal 3280 3504 1808 3280 2
RECTANGLE Normal 3296 5392 1824 4928 2
RECTANGLE Normal 4752 3296 4032 3008 2
RECTANGLE Normal 2576 4752 1840 3856 2
RECTANGLE Normal 6256 4048 4928 3696 2
RECTANGLE Normal 5040 5760 3424 5024 2
RECTANGLE Normal 5008 5424 4160 5264 2
RECTANGLE Normal 3360 3872 2624 3776 2