Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1172.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1172.asy)
L1 IN N001 150 Rser=0.02 Rpar=5000
R1 OUT N002 10.7K
R3 N003 N004 1K
V1 IN 0 5
C3 N004 0 1
Rload OUT 0 24
R2 N002 0 1.24K
D1 N001 OUT MBRS360
C1 OUT 0 500 Rser=0.05
XU1 N003 N002 0 N001 IN LT1172 ;pnba Vc)FB)GND)SW)Vin
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 25m startup
.lib LT1172.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2824 1472
WIRE 1824 880 1616 880
WIRE 1872 880 1824 880
WIRE 1984 880 1952 880
WIRE 2032 880 1984 880
WIRE 2176 880 2096 880
WIRE 2304 880 2176 880
WIRE 2432 880 2304 880
WIRE 1616 896 1616 880
WIRE 2304 896 2304 880
WIRE 2432 896 2432 880
WIRE 2176 928 2176 880
WIRE 1824 944 1824 880
WIRE 1616 992 1616 976
WIRE 2304 992 2304 960
WIRE 2432 992 2432 976
WIRE 1984 1024 1984 880
WIRE 1984 1024 1952 1024
WIRE 2176 1088 2176 1008
WIRE 2176 1088 1952 1088
WIRE 2176 1104 2176 1088
WIRE 1968 1152 1952 1152
WIRE 2064 1152 2048 1152
WIRE 2064 1168 2064 1152
WIRE 2176 1200 2176 1184
WIRE 1824 1248 1824 1232
WIRE 2064 1248 2064 1232
SYMBOL RES 2160 912 R0
SYMATTR InstName R1
SYMATTR Value 10.7K
SYMBOL RES 2416 880 R0
SYMATTR InstName Rload
SYMATTR Value 24
SYMBOL CAP 2048 1168 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL POWERPRODUCTS\\LT1172 1824 1088 R0
SYMATTR InstName U1
SYMBOL RES 1952 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL RES 2160 1088 R0
SYMATTR InstName R2
SYMATTR Value 1.24K
SYMBOL schottky 2032 896 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMBOL polcap 2288 896 R0
SYMATTR InstName C1
SYMATTR Value 500
SYMATTR SpiceLine Rser=0.05
SYMBOL IND 1856 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL VOLTAGE 1616 880 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 2432 880 OUT
FLAG 2176 1200 0
FLAG 2304 992 0
FLAG 2432 992 0
FLAG 2064 1248 0
FLAG 1824 1248 0
FLAG 1616 992 0
FLAG 1616 880 IN
TEXT 2144 1248 Left 2 !.tran 25m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4051.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 2.5
Vin IN 0 SINE(0 1 1K)
R1 N001 0 10K
R2 OUT N001 10K
XU1 IN N001 +V -V OUT ADA4051 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -2.5
Rload OUT 0 10K
.tran 10m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4051.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 128 -1152 128 -1168
WIRE 240 -1152 240 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 128 -1056 128 -1072
WIRE 240 -1056 240 -1072
WIRE 576 -1056 576 -1072
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
FLAG 128 -1168 +V
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 240 -1168 -V
FLAG 576 -1056 -V
FLAG 416 -1232 0
FLAG 768 -992 0
FLAG 240 -1056 0
FLAG 128 -1056 0
SYMBOL voltage 128 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL Opamps\\ADA4051 576 -1168 R0
SYMATTR InstName U1
SYMBOL voltage 240 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
TEXT 784 -896 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\14ea000dd9af_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
A1 N002 0 0 0 0 In Qa 0 MODULATOR space={10k} mark={100k}
V2 N002 0 PULSE(0 1 0 {tb})
B1 N001 0 V=V(In)*{amp}
.param amp=1
.step param amp list 0.5 0.707 1 1.414
.param tb = 1m
.tran 0 {tb} 0
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 96 64 96
WIRE 64 128 64 96
WIRE -224 192 -304 192
WIRE -176 192 -176 48
WIRE -176 192 -224 192
WIRE -448 256 -528 256
WIRE -224 256 -304 256
WIRE -176 256 -224 256
WIRE -528 304 -528 256
WIRE -528 400 -528 384
WIRE -176 400 -176 256
SYMBOL voltage -528 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -85 148 Left 2
SYMATTR Value PULSE(0 1 0 {tb})
SYMATTR InstName V2
SYMBOL SpecialFunctions\\modulate2 -448 256 M180
WINDOW 3 -79 126 Left 2
SYMATTR Value space={10k} mark={100k}
SYMATTR InstName A1
SYMBOL bv 64 112 R0
SYMATTR InstName B1
SYMATTR Value V=V(In)*{amp}
FLAG 64 208 0
FLAG -528 400 0
FLAG -224 192 In
FLAG -224 256 Qa
TEXT 40 280 Left 2 !.param amp=1\n.step param amp list 0.5 0.707 1 1.414\n.param tb = 1m
TEXT -584 80 Left 2 !.tran 0 {tb} 0
TEXT -576 56 Left 2 !.options plotwinsize=0
* Z:\home\khalils\Downloads\files\data\raw_asc\3da8108634dd_1784.asc
* Generated by LTspice 26.0.1 for Windows.
* Single Supply Full Wave Rectifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1784.asy)
V3 IN 0 SINE(0 1 10)
R1 N002 +V 1K
XU1 0 N001 N002 +V 0 NC_01 LT1784 ;pnba IN+)IN-)OUT)VCC)VEE)SHDN
R2 N001 IN 1K
D1 N002 OUT BAT54
R3 OUT N001 1K
V1 +V 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 300m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 16 -48 -96 -48
WIRE 128 -48 96 -48
WIRE 192 -48 128 -48
WIRE 336 -48 272 -48
WIRE 416 -48 336 -48
WIRE -96 -32 -96 -48
WIRE 336 -16 336 -48
WIRE -96 64 -96 48
WIRE 192 64 192 48
WIRE 224 64 192 64
WIRE 336 64 336 48
WIRE 336 64 304 64
WIRE 192 112 192 64
WIRE 128 160 128 -48
WIRE 160 160 128 160
WIRE 336 192 336 64
WIRE 336 192 304 192
WIRE -48 208 -48 192
WIRE 160 224 128 224
WIRE 192 288 192 272
WIRE -48 304 -48 288
SYMBOL res 288 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL schottky 320 48 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 112 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 320 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -96 -48 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 10)
SYMBOL voltage -48 192 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT1784 192 192 R0
SYMATTR InstName U1
FLAG -48 304 0
FLAG 192 48 +V
FLAG -48 192 +V
FLAG -96 64 0
FLAG 128 224 0
FLAG 416 -48 OUT
FLAG 192 288 0
FLAG -96 -48 IN
TEXT 376 272 Left 2 !.tran 300m
TEXT 224 -104 Bottom 2 ;Single Supply Full Wave Rectifier
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5075.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5075.asy)
C3 0 N006 1
C2 OUT 0 12
D1 OUT N001 MBRS140
C4 0 N005 1
L1 N001 0 4.7
R1 N004 N005 15.8K
V1 IN 0 5
R3 N003 N002 50K
C5 N003 0 15p
Rload OUT 0 200
C1 N002 0 2n
XU1 IN N001 N003 0 N006 IN 0 N004 N005 NC_01 NC_02 IN ADP5075 CL=880m CS=153.85m Ron=330m IQ=1.8m ;pnba PVin)SW)Comp)GND)Vreg)EN)Sync/Freq)FB)Vref)Slew)SS)AVin
R2 OUT N004 115K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 4.5m startup
.lib ADP5075.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1432 816
WIRE 96 -48 -48 -48
WIRE 416 -48 96 -48
WIRE -48 -32 -48 -48
WIRE 96 16 96 -48
WIRE 112 16 96 16
WIRE 416 16 416 -48
WIRE 416 16 400 16
WIRE -48 64 -48 48
WIRE 96 128 96 16
WIRE 112 128 96 128
WIRE 448 128 400 128
WIRE 544 128 448 128
WIRE 656 128 608 128
WIRE 720 128 656 128
WIRE 816 128 720 128
WIRE 448 144 448 128
WIRE 720 144 720 128
WIRE 816 144 816 128
WIRE -80 240 -128 240
WIRE 48 240 0 240
WIRE 112 240 48 240
WIRE 448 240 448 224
WIRE 448 240 400 240
WIRE 720 240 720 208
WIRE 816 240 816 224
WIRE -128 256 -128 240
WIRE 48 256 48 240
WIRE 448 256 448 240
WIRE -128 336 -128 320
WIRE 48 336 48 320
WIRE 448 352 400 352
WIRE 528 352 448 352
WIRE 656 352 656 128
WIRE 656 352 608 352
WIRE 448 368 448 352
WIRE 448 464 448 448
WIRE 448 464 400 464
WIRE 528 464 448 464
WIRE 608 464 592 464
WIRE 112 576 96 576
WIRE 432 576 400 576
WIRE 512 576 496 576
SYMBOL res 432 352 R0
SYMATTR InstName R1
SYMATTR Value 15.8K
SYMBOL cap 704 144 R0
SYMATTR InstName C2
SYMATTR Value 12
SYMBOL cap -144 256 R0
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL res 16 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 50K
SYMBOL PowerProducts\\ADP5075 256 288 R0
SYMATTR InstName U1
SYMBOL res 800 128 R0
SYMATTR InstName Rload
SYMATTR Value 200
SYMBOL cap 32 256 R0
SYMATTR InstName C5
SYMATTR Value 15p
SYMBOL cap 496 560 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 592 448 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL VOLTAGE -48 -48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 624 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 115K
SYMBOL schottky 608 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL ind 432 128 R0
WINDOW 0 42 41 Left 2
WINDOW 3 39 68 Left 2
SYMATTR InstName L1
SYMATTR Value 4.7
FLAG 448 256 0
FLAG 720 240 0
FLAG 816 240 0
FLAG 608 464 0
FLAG 96 576 0
FLAG 512 576 0
FLAG -48 64 0
FLAG -48 -48 IN
FLAG 816 128 OUT
FLAG -128 336 0
FLAG 48 336 0
TEXT 696 616 Left 2 !.tran 4.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4412HV.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4412HV.asy)
MQ1 N003 N004 N002 N002 FDC638P
XU1 N003 0 0 N005 N004 N002 LTC4412 ;pnba Vin)GND)CTL)STAT)Gate)Sense
V2 N001 0 PWL(0 0 1 7)
V1 N003 0 5
R2 N002 0 100
C1 N002 0 10
R1 N002 N005 470K
D1 N001 N002 1N5819
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.lib LTC4412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2500 1716
WIRE 1760 1024 1360 1024
WIRE 2096 1024 1824 1024
WIRE 1360 1040 1360 1024
WIRE 1968 1104 1552 1104
WIRE 2096 1104 2096 1024
WIRE 2096 1104 2064 1104
WIRE 2144 1104 2096 1104
WIRE 2272 1104 2144 1104
WIRE 2368 1104 2272 1104
WIRE 2272 1120 2272 1104
WIRE 2368 1120 2368 1104
WIRE 1360 1136 1360 1120
WIRE 2144 1184 2144 1104
WIRE 1552 1216 1552 1104
WIRE 1680 1216 1552 1216
WIRE 2096 1216 2096 1104
WIRE 2096 1216 1936 1216
WIRE 2272 1216 2272 1184
WIRE 2368 1216 2368 1200
WIRE 1552 1232 1552 1216
WIRE 1680 1296 1664 1296
WIRE 2048 1296 2048 1152
WIRE 2048 1296 1936 1296
WIRE 1552 1328 1552 1312
WIRE 1680 1376 1664 1376
WIRE 2144 1376 2144 1264
WIRE 2144 1376 1936 1376
SYMBOL PowerProducts\\LTC4412HV 1808 1296 R0
SYMATTR InstName U1
SYMBOL voltage 1360 1024 R0
SYMATTR InstName V2
SYMATTR Value PWL(0 0 1 7)
SYMBOL RES 2128 1168 R0
SYMATTR InstName R1
SYMATTR Value 470K
SYMBOL cap 2256 1120 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL schottky 1760 1040 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMBOL res 2352 1104 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL VOLTAGE 1552 1216 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PMOS 1968 1152 R270
WINDOW 0 90 48 VCenter 2
WINDOW 3 63 45 VCenter 2
SYMATTR InstName Q1
SYMATTR Value FDC638P
FLAG 1664 1376 0
FLAG 1664 1296 0
FLAG 2272 1216 0
FLAG 2368 1216 0
FLAG 1552 1328 0
FLAG 1360 1136 0
TEXT 2208 1368 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\edfd2651496d_mos_param_visibility.asc
* Generated by LTspice 26.0.1 for Windows.
M2 out in vdd vdd PMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
M3 out in 0 0 NMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
V2 vdd 0 5
V1 in 0 2.5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.model PMOS1 pmos level=2 nsub=4e15 tox=50n
.model NMOS1 nmos level=2 nsub=4e15 tox=50n
* .dc V1 0 5 .01
* How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1404 948
WIRE 48 400 48 320
WIRE 48 544 48 480
WIRE 64 32 64 -32
WIRE 64 176 64 112
WIRE 112 320 48 320
WIRE 256 320 112 320
WIRE 256 320 256 160
WIRE 256 464 256 320
WIRE 352 160 256 160
WIRE 352 464 256 464
WIRE 400 -32 64 -32
WIRE 400 80 400 -32
WIRE 400 144 400 80
WIRE 400 320 400 240
WIRE 400 384 400 320
WIRE 400 544 400 480
WIRE 496 192 400 192
WIRE 496 432 400 432
WIRE 560 320 400 320
FLAG 112 320 in
FLAG 400 544 0
FLAG 496 432 0
FLAG 496 192 vdd
FLAG 400 80 vdd
FLAG 560 320 out
FLAG 64 176 0
FLAG 48 544 0
SYMBOL pmos4 352 240 M180
WINDOW 0 59 69 Left 0
WINDOW 3 57 27 Left 0
WINDOW 123 57 -1 Left 0
SYMATTR InstName M2
SYMATTR Value PMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
SYMBOL nmos4 352 384 R0
WINDOW 123 56 100 Left 0
SYMATTR InstName M3
SYMATTR Value NMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
SYMBOL voltage 64 16 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 48 384 R0
SYMATTR InstName V1
SYMATTR Value 2.5
TEXT 24 -104 Left 0 !.op
TEXT 24 624 Left 0 !.model PMOS1 pmos level=2 nsub=4e15 tox=50n\n.model NMOS1 nmos level=2 nsub=4e15 tox=50n
TEXT 24 -136 Left 0 ;.dc V1 0 5 .01
TEXT 16 -608 Left 0 ;How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1728-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC1728-5.asy)
V4 N001 0 5
V2 N005 0 PWL(0 5 4 5 5 4.5 6 5)
V1 N004 0 PWL(0 1.05 7 1.05 8 0.95 9 1.05)
R1 N002 N001 10K
XU1 N002 0 N004 N005 N003 LTC1728-5 ;pnba _RST)GND)VccA)Vcc5)Vcc3
V3 N003 0 PWL(0 3.3 1 3.3 2 3.0 3 3.3)
.tran 10
.lib LTC1728-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1100 756
WIRE -176 144 -240 144
WIRE 48 144 -96 144
WIRE 464 144 272 144
WIRE -240 176 -240 144
WIRE 464 176 464 144
WIRE 48 208 32 208
WIRE 48 272 -80 272
WIRE 384 272 272 272
WIRE 464 272 464 256
WIRE -240 288 -240 256
WIRE -80 288 -80 272
WIRE 384 304 384 272
WIRE -80 384 -80 368
WIRE 384 400 384 384
SYMBOL LTC1728-5 160 240 R0
SYMATTR InstName U1
SYMBOL voltage -80 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 1.05 7 1.05 8 0.95 9 1.05)
SYMBOL voltage -240 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL res -80 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 464 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 3.3 1 3.3 2 3.0 3 3.3)
SYMBOL voltage 384 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PWL(0 5 4 5 5 4.5 6 5)
SYMATTR InstName V2
FLAG 32 208 0
FLAG 464 272 0
FLAG 384 400 0
FLAG -80 384 0
FLAG -240 288 0
TEXT 632 456 Left 2 !.tran 10
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1127.asc
* Generated by LTspice 26.0.1 for Windows.
* Low Noise, Wide Bandwidth Instrumentation Amplifier
* Library below included based on ModelFile attribute of instance XU1, XU2, XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1127.asy)
V1 +V 0 15
XU3 IN- N003 +V -V N001 LT1126 ;pnba In+)In-)V+)V-)OUT
R4 N002 N001 620
V4 IN+ 0 SINE(0 1 10)
R7 0 N004 10K
R3 N005 N006 6.2K
XU1 IN+ N005 +V -V N006 LT1126 ;pnba In+)In-)V+)V-)OUT
R5 OUT N002 10K
R6 N004 N006 620
R1 N001 N003 6.2K
XU2 N004 N002 +V -V OUT LT1126 ;pnba In+)In-)V+)V-)OUT
V3 IN- IN+ SINE(0 1m 100)
V2 -V 0 -15
R2 N003 N005 6.2K
.tran .3
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 176 -48 176 -64
WIRE 80 -32 -32 -32
WIRE 144 -32 80 -32
WIRE 304 -16 208 -16
WIRE 368 -16 304 -16
WIRE 464 -16 448 -16
WIRE 480 -16 464 -16
WIRE 592 -16 560 -16
WIRE 144 0 112 0
WIRE 304 0 304 -16
WIRE 176 32 176 16
WIRE -32 80 -32 -32
WIRE 112 96 112 0
WIRE 304 96 304 80
WIRE 304 96 112 96
WIRE 304 112 304 96
WIRE 528 112 528 96
WIRE 464 128 464 -16
WIRE 496 128 464 128
WIRE 592 144 592 -16
WIRE 592 144 560 144
WIRE 624 144 592 144
WIRE 496 160 464 160
WIRE 528 192 528 176
WIRE -256 208 -256 192
WIRE -128 208 -128 192
WIRE 304 208 304 192
WIRE 304 208 112 208
WIRE 304 224 304 208
WIRE 176 288 176 272
WIRE -256 304 -256 288
WIRE -128 304 -128 288
WIRE 112 304 112 208
WIRE 144 304 112 304
WIRE 304 320 304 304
WIRE 304 320 208 320
WIRE 368 320 304 320
WIRE 464 320 464 160
WIRE 464 320 448 320
WIRE 496 320 464 320
WIRE 592 320 576 320
WIRE -32 336 -32 160
WIRE 80 336 -32 336
WIRE 144 336 80 336
WIRE -32 352 -32 336
WIRE 176 368 176 352
WIRE -32 448 -32 432
SYMBOL voltage -32 64 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1m 100)
SYMBOL voltage -128 192 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 288 208 R0
SYMATTR InstName R3
SYMATTR Value 6.2K
SYMBOL opamps\\LT1127 176 256 R0
SYMATTR InstName U1
SYMBOL voltage -32 336 R0
SYMATTR InstName V4
SYMATTR Value SINE(0 1 10)
SYMBOL res 464 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 620
SYMBOL voltage -256 192 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 576 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL opamps\\LT1127 176 48 M180
SYMATTR InstName U3
SYMBOL res 288 -16 R0
SYMATTR InstName R1
SYMATTR Value 6.2K
SYMBOL opamps\\LT1127 528 80 R0
SYMATTR InstName U2
SYMBOL res 288 96 R0
SYMATTR InstName R2
SYMATTR Value 6.2K
SYMBOL res 592 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 10K
SYMBOL res 464 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 620
FLAG -128 304 0
FLAG 176 272 +V
FLAG -128 192 +V
FLAG 176 368 -V
FLAG -256 304 0
FLAG -256 192 -V
FLAG -32 448 0
FLAG 528 96 +V
FLAG 528 192 -V
FLAG 176 32 +V
FLAG 176 -64 -V
FLAG 592 320 0
FLAG 624 144 OUT
FLAG 80 336 IN+
FLAG 80 -32 IN-
TEXT 424 424 Left 2 !.tran .3
TEXT 168 -112 Bottom 2 ;Low Noise, Wide Bandwidth Instrumentation Amplifier
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7185-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7185-3.asy)
R3 OUT 0 6
C1 N001 N002 10n
C3 N001 0 1
V1 IN 0 -3.5
C2 OUT 0 4.7 Rser=5m
C4 N003 0 1
XU1 OUT OUT N001 N002 IN 0 N003 IN ADP7185-3 ;pnba Vout)Sense)VA)VAFB)EN)GND)Vreg)Vin
.tran 200m startup
.lib ADP7185-3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 16 -48
WIRE 96 -48 32 -48
WIRE 112 -48 96 -48
WIRE 400 -48 368 -48
WIRE 432 -48 400 -48
WIRE 496 -48 432 -48
WIRE 512 -48 496 -48
WIRE 16 -32 16 -48
WIRE 432 -32 432 -48
WIRE 512 -32 512 -48
WIRE 400 16 400 -48
WIRE 400 16 368 16
WIRE 432 48 432 32
WIRE 16 64 16 48
WIRE 512 64 512 48
WIRE 96 80 96 -48
WIRE 112 80 96 80
WIRE 464 80 368 80
WIRE 384 144 368 144
WIRE 464 144 464 80
WIRE 464 144 448 144
WIRE 464 160 464 144
WIRE 176 224 176 208
WIRE 304 224 304 208
WIRE 464 240 464 224
WIRE 176 320 176 288
SYMBOL voltage 16 -48 R0
SYMATTR InstName V1
SYMATTR Value -3.5
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=5m
SYMBOL cap 160 224 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 496 -48 R0
SYMATTR InstName R3
SYMATTR Value 6
SYMBOL cap 448 160 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 448 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL ADP7185-3 240 48 R0
SYMATTR InstName U1
FLAG 16 64 0
FLAG 432 48 0
FLAG 304 224 0
FLAG 512 64 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 464 240 0
FLAG 176 320 0
TEXT 136 352 Left 2 !.tran 200m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX16171.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX16171.asy)
XU1 N002 IN IN IN 0 OUT MAX16171 ;pnba GATE)SRC)IN)EN)GND)OUT
V1 IN 0 12
V2 N001 0 PWL(0 0 6m 0 +1m 1)
S1 0 OUT N001 0 SCSW
C1 IN 0 0.1
MQ1 OUT N002 IN IN IPD068N10N3
C2 OUT 0 100
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
.model SCSW SW(Ron=2 Roff=200 Vt=.5 Vh=-.4)
.lib MAX16171.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1532 680
WIRE -208 -192 -224 -192
WIRE -32 -192 -208 -192
WIRE 160 -192 -32 -192
WIRE 304 -192 160 -192
WIRE 512 -192 400 -192
WIRE 640 -192 512 -192
WIRE 816 -192 640 -192
WIRE 832 -192 816 -192
WIRE 832 -176 832 -192
WIRE 992 -160 880 -160
WIRE -224 -144 -224 -192
WIRE 640 -144 640 -192
WIRE 992 -144 992 -160
WIRE 832 -80 832 -96
WIRE 992 -48 992 -64
WIRE 640 -32 640 -80
WIRE -224 -16 -224 -64
WIRE 160 0 160 -192
WIRE 320 0 320 -144
WIRE -32 96 -32 -192
WIRE -32 96 -96 96
WIRE 64 96 -32 96
WIRE 512 144 512 -192
WIRE 512 144 416 144
WIRE -96 160 -96 96
WIRE -32 192 -32 96
WIRE 64 192 -32 192
WIRE -96 272 -96 224
WIRE 240 336 240 288
SYMBOL nmos 400 -144 M270
WINDOW 0 52 47 VTop 2
WINDOW 3 -16 79 VLeft 2
SYMATTR InstName Q1
SYMATTR Value IPD068N10N3
SYMBOL cap -112 160 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL voltage 992 -160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 6m 0 +1m 1)
SYMBOL cap 624 -144 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMBOL MAX16171 240 144 R0
SYMATTR InstName U1
SYMBOL voltage -224 -160 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL sw 832 -80 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SCSW
FLAG 240 336 0
FLAG -96 272 0
FLAG 640 -32 0
FLAG -224 -16 0
FLAG -208 -192 IN
FLAG 816 -192 OUT
FLAG 832 -80 0
FLAG 880 -112 0
FLAG 992 -48 0
TEXT 560 272 Left 2 !.tran 20m startup
TEXT 560 232 Left 2 !.model SCSW SW(Ron=2 Roff=200 Vt=.5 Vh=-.4)