* Z:\home\khalils\Downloads\files\data\raw_asc\0e8f5883c680_wijekoon_neuron.asc
* Generated by LTspice 26.0.1 for Windows.
M1 0 post_synaptic_input N002 0 NMOS l=180n w=2.3u
M2 N002 N002 VDD VDD PMOS l=180n w=2.3u
M3 post_synaptic_input N002 VDD VDD PMOS l=180n w=1u
C1 post_synaptic_input 0 35f
M4 0 N003 post_synaptic_input 0 NMOS l=3.96u w=1.3u
M7 N003 N002 VDD VDD PMOS l=2.52u w=1.3u
M6 0 N003 N003 0 NMOS l=3.24u w=1.3u
C2 N003 0 550f
M8 N003 spike_out d VDD PMOS l=180n w=1.3u
M5 c N001 post_synaptic_input 0 NMOS l=180n w=1u
M12 spike_out post_synaptic_input N004 0 NMOS l=180n w=1.3u
M9 VDD spike_out N001 VDD PMOS l=684n w=1u
M10 spike_out spike_out VDD VDD PMOS l=234n w=1.8u
M11 N004 Vth N001 0 NMOS l=774n w=1u
M13 N004 N004 0 0 NMOS l=540n w=2.3u
M14 0 Vbias N004 N005 NMOS l=540n w=2.3u
V1 VDD 0 0.9
V2 c 0 0.5
V4 Vth 0 0.4
V5 Vbias 0 0.3
V6 d 0 0.07
I1 post_synaptic_input 0 PULSE(0 0.1uA 100ns 0.1ns 0.1ns 10ns 100ns 0A)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include p18_cmos_models_tt.inc
.tran 0.1n 2u
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1880 680
WIRE 1728 -224 1040 -224
WIRE 160 -112 128 -112
WIRE 320 -112 160 -112
WIRE 368 -112 320 -112
WIRE 464 -112 368 -112
WIRE 512 -112 464 -112
WIRE 688 -112 688 -176
WIRE 688 -112 512 -112
WIRE 816 -112 688 -112
WIRE 1280 -112 816 -112
WIRE 1376 -112 1280 -112
WIRE 1648 -112 1376 -112
WIRE 1696 -112 1648 -112
WIRE 1504 -96 1424 -96
WIRE 848 -64 784 -64
WIRE 1280 -64 1280 -112
WIRE 1376 -64 1280 -64
WIRE 1696 -64 1696 -112
WIRE 1696 -64 1648 -64
WIRE 160 -48 160 -112
WIRE 368 -48 368 -112
WIRE 512 -48 512 -112
WIRE 848 -48 848 -64
WIRE 224 -32 208 -32
WIRE 416 -32 224 -32
WIRE 560 -32 416 -32
WIRE 928 -32 896 -32
WIRE 1504 -32 1504 -96
WIRE 1520 -32 1504 -32
WIRE 1600 -32 1520 -32
WIRE 128 0 128 -112
WIRE 160 0 128 0
WIRE 320 0 320 -112
WIRE 368 0 320 0
WIRE 464 0 464 -112
WIRE 512 0 464 0
WIRE 816 0 816 -112
WIRE 848 0 816 0
WIRE 1648 16 1648 -16
WIRE 1728 16 1728 -224
WIRE 1728 16 1648 16
WIRE 1376 32 1376 -16
WIRE 1520 32 1520 -32
WIRE 1520 32 1376 32
WIRE 928 48 928 -32
WIRE 1088 48 928 48
WIRE 1200 48 1088 48
WIRE 1376 48 1376 32
WIRE 1376 48 1200 48
WIRE 1728 48 1728 16
WIRE 1824 64 1776 64
WIRE 160 80 160 48
WIRE 224 80 224 -32
WIRE 224 80 160 80
WIRE 512 80 512 48
WIRE 752 80 512 80
WIRE 1280 96 1200 96
WIRE 1728 96 1664 96
WIRE 992 128 528 128
WIRE 1152 128 992 128
WIRE 1040 144 1040 -224
WIRE 1328 144 1200 144
WIRE 1472 144 1328 144
WIRE 1728 144 1472 144
WIRE 160 160 160 80
WIRE 1472 160 1472 144
WIRE 1472 160 1392 160
WIRE 1552 160 1472 160
WIRE 272 176 208 176
WIRE 368 176 368 48
WIRE 368 176 272 176
WIRE 384 176 368 176
WIRE 528 176 528 128
WIRE 528 176 384 176
WIRE 992 176 928 176
WIRE 1728 176 1600 176
WIRE 384 192 384 176
WIRE 720 192 576 192
WIRE 752 192 752 80
WIRE 752 192 720 192
WIRE 768 192 752 192
WIRE 848 192 848 48
WIRE 848 192 768 192
WIRE 160 208 128 208
WIRE 768 208 768 192
WIRE 848 208 848 192
WIRE 1408 208 1392 208
WIRE 528 224 464 224
WIRE 720 240 656 240
WIRE 992 240 992 224
WIRE 1328 240 1328 144
WIRE 1344 240 1328 240
WIRE 1552 240 1552 208
WIRE 1408 256 1408 208
WIRE 1408 256 1392 256
WIRE 1472 256 1408 256
WIRE 1552 256 1472 256
WIRE 128 288 128 208
WIRE 160 288 160 256
WIRE 160 288 128 288
WIRE 384 288 384 256
WIRE 384 288 160 288
WIRE 464 288 464 224
WIRE 464 288 384 288
WIRE 528 288 528 272
WIRE 528 288 464 288
WIRE 656 288 656 240
WIRE 656 288 528 288
WIRE 720 288 656 288
WIRE 848 288 848 272
WIRE 848 288 720 288
WIRE 928 288 928 176
WIRE 928 288 848 288
WIRE 976 288 928 288
WIRE 1280 288 1280 96
WIRE 1280 288 976 288
WIRE 1472 288 1472 256
WIRE 1472 288 1280 288
WIRE 1664 288 1664 96
WIRE 1664 288 1472 288
WIRE 272 320 272 176
WIRE 272 320 80 320
WIRE 976 352 976 288
WIRE 1088 352 1088 48
WIRE 1408 352 1088 352
FLAG 976 352 0
FLAG 688 -176 VDD
FLAG 208 -464 VDD
FLAG 208 -384 0
FLAG 1408 352 spike_out
FLAG 1728 176 Vbias
FLAG 1824 64 Vth
FLAG 992 240 c
FLAG 784 -64 d
FLAG 80 320 post_synaptic_input
FLAG 384 -384 0
FLAG 1168 -384 0
FLAG 528 -384 0
FLAG 672 -384 0
FLAG 384 -464 c
FLAG 1168 -464 post_synaptic_input
FLAG 528 -464 Vth
FLAG 672 -464 Vbias
FLAG 800 -384 0
FLAG 800 -464 d
SYMBOL nmos4 208 256 R180
SYMATTR InstName M1
SYMATTR Value2 l=180n w=2.3u
SYMBOL pmos4 208 48 R180
SYMATTR InstName M2
SYMATTR Value2 l=180n w=2.3u
SYMBOL pmos4 416 48 R180
SYMATTR InstName M3
SYMATTR Value2 l=180n w=1u
SYMBOL cap 368 192 R0
SYMATTR InstName C1
SYMATTR Value 35f
SYMBOL nmos4 576 272 R180
SYMATTR InstName M4
SYMATTR Value2 l=3.96u w=1.3u
SYMBOL pmos4 560 48 R180
SYMATTR InstName M7
SYMATTR Value2 l=2.52u w=1.3u
SYMBOL nmos4 768 288 R180
SYMATTR InstName M6
SYMATTR Value2 l=3.24u w=1.3u
SYMBOL cap 832 208 R0
SYMATTR InstName C2
SYMATTR Value 550f
SYMBOL pmos4 896 48 R180
SYMATTR InstName M8
SYMATTR Value2 l=180n w=1.3u
SYMBOL nmos4 1040 224 R180
SYMATTR InstName M5
SYMATTR Value2 l=180n w=1u
SYMBOL nmos4 1152 48 R0
SYMATTR InstName M12
SYMATTR Value2 l=180n w=1.3u
SYMBOL pmos4 1600 -112 R0
SYMATTR InstName M9
SYMATTR Value2 l=684n w=1u
SYMBOL pmos4 1424 -16 R180
SYMATTR InstName M10
SYMATTR Value2 l=234n w=1.8u
SYMBOL nmos4 1776 144 R180
SYMATTR InstName M11
SYMATTR Value2 l=774n w=1u
SYMBOL nmos4 1344 160 R0
SYMATTR InstName M13
SYMATTR Value2 l=540n w=2.3u
SYMBOL nmos4 1600 256 R180
SYMATTR InstName M14
SYMATTR Value2 l=540n w=2.3u
SYMBOL voltage 208 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0.9
SYMBOL voltage 384 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0.5
SYMBOL voltage 528 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0.4
SYMBOL voltage 672 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 0.3
SYMBOL voltage 800 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 0.07
SYMBOL current 1168 -464 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(0 0.1uA 100ns 0.1ns 0.1ns 10ns 100ns 0A)
TEXT 144 472 Left 2 !.include p18_cmos_models_tt.inc
TEXT 152 448 Left 2 !.tran 0.1n 2u
TEXT 168 416 Left 2 !.op