* Z:\home\khalils\Downloads\files\data\raw_asc\249427656a29_voltron_spice_110524.asc
* Generated by LTspice 26.0.1 for Windows.
* Bitline to array0
* Bitline to array1
* Word line in array 0
* Word line in array 1
* CMOS Sense Amplifier
* To pull the bit lines up to VDD, we have to add a PMOS sense amplifier or PSA. The signal ACT is\ncommon to all of the PSAs of the array (as NLAT for the NSA). The signal sense_P is active\nlow and indicates that the PSA is firing. the PSA is usually fired after the NSA because the \nmatching of the NMOS is better than tha matching of the PMOS.
* CMOS book, Circuit Design, Layout, and Simulation by R. Jacob Baker
* Simulation Configuations
* Looping through different Vdd values
* // Select a few volts only
M13 VDDby2 EqNot bitline1 VDD pmos45hp l=0.16um w={pretw}
Cmbit3 N005 0 144fF
M1 N006 sense_N 0 0 nmos45lp l=0.27um w=0.22um
M6 VDDby2 Eq bitline1 0 nmos45hp l=0.16um w={prentw}
M8 N007 ra3 mb3 0 nmos45lp l=0.085um w=0.055um
M9 ACT sense_p VDD VDD pmos45lp l=0.27um w=0.22um
R2 bitline1 N005 10000
R3 N002 mb0 1000
M2 bitline1 bitline0 NLAT 0 nmos45hp l=0.16um w={ntw}
Cmbit1 mb3 0 24fF
M3 bitline0 bitline1 N006 0 nmos45hp l=0.16um w={ntw}
Veq1 EqNot 0 PWL(0n 1.5 0.6n 0 25.6n 0 26.2n {vdd} 133n {vdd} 133.6n 0)
M4 bitline1 Eq bitline0 0 nmos45hp l=0.16um w={prentw}
M12 bitline0 EqNot VDDby2 VDD pmos45hp l=0.16um w={pretw}
M5 bitline0 Eq VDDby2 0 nmos45hp l=0.16um w={prentw}
Cmbit2 N001 0 144fF
M10 bitline1 bitline0 N004 VDD pmos45hp l=0.16um w={tw}
VDDby2 VDDby2 0 {vddhalf}
M11 bitline0 bitline1 ACT VDD pmos45hp l=0.16um w={tw}
R1 N001 bitline0 10000
R4 0 N003 30000
Vsn sense_N 0 PWL(34n 0 34.005n {vdd} 133n {vdd} 133.005n 0) Rser=100 Cpar=10fF
Veq2 Eq 0 PWL(0n 0 0.6n 1.5 25.6n 1.5 26.2n 0 133n 0 133.6n {vdd})
VDD VDD 0 {vdd}
R5 N005 N007 1000
Cmbit0 mb0 N003 24fF
M7 N001 ra0 N002 0 nmos45lp l=0.085um w=0.555um
R7 NLAT N006 25000
Vsp sense_P 0 PWL(34n {vdd} 34.05n 0 133n 0 133.005n {vdd}) Rser=100 Cpar=10fF
Vra0 ra0 0 PWL(30n 0 30.5n 2.9 130n 2.9 130.5n 0) Rser=2048 Cpar=0.6pF
R6 N004 ACT 25000
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.ic v(bitline0)={vddhalf} v(bitline1)={vddhalf} v(mb0)={vdd}
.tran 230ns uic
.step param X list 1 2 3 4
.param vdd=table(X, 1, 1.35V, 2, 1.1V, 3, 1.35V, 4, 1.1V)
.param vddhalf=table(X, 1, 0.675V, 2, 0.55V, 3, 0.675V, 4, 0.55V)
.param tw = 2.5um
.param ntw = 1um
.param pretw=2.5um
.param prentw=2.5um
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1952 1352
WIRE 656 -1216 656 -1248
WIRE 768 -1088 656 -1248
WIRE 656 -1072 656 -1120
WIRE 1120 -992 1120 -1008
WIRE 1664 -976 1664 -1008
WIRE 1792 -976 1792 -1008
WIRE 544 -944 336 -944
WIRE 608 -944 608 -1136
WIRE 608 -944 544 -944
WIRE 976 -944 608 -944
WIRE 656 -912 656 -992
WIRE 656 -896 656 -912
WIRE 1120 -896 1120 -912
WIRE -384 -864 -384 -896
WIRE 1664 -864 1664 -896
WIRE 1792 -864 1792 -896
WIRE 768 -848 768 -1088
WIRE 832 -848 768 -848
WIRE 544 -832 512 -832
WIRE 656 -832 624 -832
WIRE 512 -800 512 -832
WIRE 768 -768 768 -848
WIRE -384 -752 -384 -784
WIRE 432 -736 384 -736
WIRE 640 -736 432 -736
WIRE 832 -656 688 -656
WIRE 912 -656 832 -656
WIRE 960 -656 912 -656
WIRE 832 -624 832 -656
WIRE 1040 -624 1040 -656
WIRE 912 -608 880 -608
WIRE 992 -608 960 -608
WIRE 1312 -528 1120 -528
WIRE 64 -512 64 -528
WIRE 768 -512 768 -688
WIRE 832 -512 832 -528
WIRE 832 -512 768 -512
WIRE 912 -512 960 -608
WIRE 912 -512 832 -512
WIRE 960 -512 912 -608
WIRE 1040 -512 1040 -528
WIRE 1040 -512 960 -512
WIRE 1120 -512 1120 -528
WIRE 1120 -512 1040 -512
WIRE 64 -416 64 -432
WIRE 768 -416 768 -512
WIRE 912 -416 768 -416
WIRE 1120 -416 1120 -512
WIRE 1120 -416 1008 -416
WIRE 640 -368 608 -368
WIRE 880 -368 640 -368
WIRE 928 -368 880 -368
WIRE 1056 -368 928 -368
WIRE 1296 -368 1056 -368
WIRE 880 -352 880 -368
WIRE 1056 -352 1056 -368
WIRE 768 -320 768 -416
WIRE 768 -304 768 -320
WIRE 800 -304 768 -304
WIRE 944 -304 896 -304
WIRE 976 -304 944 -304
WIRE 1120 -304 1120 -416
WIRE 1120 -304 1072 -304
WIRE 1312 -304 1312 -528
WIRE 1120 -288 1120 -304
WIRE 48 -256 48 -272
WIRE 944 -256 944 -304
WIRE 896 -208 672 -208
WIRE 1040 -208 896 -208
WIRE 896 -176 896 -208
WIRE 1040 -176 1040 -208
WIRE 48 -160 48 -176
WIRE 1312 -144 1312 -224
WIRE 1360 -144 1312 -144
WIRE 768 -128 768 -304
WIRE 816 -128 768 -128
WIRE 944 -128 944 -256
WIRE 944 -128 912 -128
WIRE 960 -128 944 -128
WIRE 1120 -128 1120 -288
WIRE 1120 -128 1056 -128
WIRE 1360 -96 1360 -144
WIRE 768 -48 768 -128
WIRE 832 -48 768 -48
WIRE 912 -48 832 -48
WIRE 1040 -48 976 -48
WIRE 1120 -48 1120 -128
WIRE 1120 -48 1040 -48
WIRE 832 -32 832 -48
WIRE 1040 -32 1040 -48
WIRE -400 -16 -400 -48
WIRE 912 48 976 -48
WIRE 912 48 880 48
WIRE 976 48 912 -48
WIRE 992 48 976 48
WIRE -400 96 -400 64
WIRE 832 96 832 64
WIRE 832 96 720 96
WIRE 848 96 832 96
WIRE 960 96 928 96
WIRE 1040 96 1040 64
WIRE 1040 96 960 96
WIRE 1216 128 1200 128
WIRE 1312 128 1312 -144
WIRE 1312 128 1296 128
WIRE 1200 160 1200 128
WIRE 672 176 416 176
WIRE 1088 272 880 272
WIRE 1152 272 1152 240
WIRE 1152 272 1088 272
WIRE 1552 272 1152 272
WIRE 1200 304 1200 256
WIRE 1200 320 1200 304
WIRE 1312 432 1312 128
SYMBOL voltage 64 -528 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq2
SYMATTR Value PWL(0n 0 0.6n 1.5 25.6n 1.5 26.2n 0 133n 0 133.6n {vdd})
SYMBOL nmos4 1008 -368 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value nmos45hp
SYMATTR Value2 l=0.16um w={prentw}
SYMBOL voltage -384 -880 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=10fF
SYMATTR Value PWL(34n {vdd} 34.05n 0 133n 0 133.005n {vdd})
SYMATTR InstName Vsp
SYMBOL nmos4 976 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value nmos45hp
SYMATTR Value2 l=0.16um w={prentw}
SYMBOL res 1312 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1000
SYMBOL cap 816 -848 R0
WINDOW 3 41 47 Left 2
SYMATTR Value 144fF
SYMATTR InstName Cmbit2
SYMBOL pmos4 640 -656 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value pmos45lp
SYMATTR Value2 l=0.27um w=0.22um
SYMBOL nmos4 1152 160 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value nmos45lp
SYMATTR Value2 l=0.085um w=0.055um
SYMBOL cap 1344 -96 R0
WINDOW 3 41 47 Left 2
SYMATTR Value 144fF
SYMATTR InstName Cmbit3
SYMBOL res 944 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 25000
SYMBOL nmos4 880 -32 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value nmos45hp
SYMATTR Value2 l=0.16um w={ntw}
SYMBOL nmos4 800 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value nmos45hp
SYMATTR Value2 l=0.16um w={prentw}
SYMBOL voltage -400 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=10fF
SYMATTR Value PWL(34n 0 34.005n {vdd} 133n {vdd} 133.005n 0)
SYMATTR InstName Vsn
SYMBOL pmos4 880 -528 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value pmos45hp
SYMATTR Value2 l=0.16um w={tw}
SYMBOL pmos4 816 -176 M90
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M12
SYMATTR Value pmos45hp
SYMATTR Value2 l=0.16um w={pretw}
SYMBOL pmos4 960 -176 M90
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M13
SYMATTR Value pmos45hp
SYMATTR Value2 l=0.16um w={pretw}
SYMBOL voltage 1792 -992 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 41 53 Left 2
SYMATTR Value {vddhalf}
SYMATTR InstName VDDby2
SYMBOL res 1056 -672 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 25000
SYMBOL nmos4 992 -32 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value nmos45hp
SYMATTR Value2 l=0.16um w={ntw}
SYMBOL voltage 48 -272 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq1
SYMATTR Value PWL(0n 1.5 0.6n 0 25.6n 0 26.2n {vdd} 133n {vdd} 133.6n 0)
SYMBOL pmos4 992 -528 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value pmos45hp
SYMATTR Value2 l=0.16um w={tw}
SYMBOL res 1296 -320 R0
WINDOW 3 36 68 Left 2
SYMATTR Value 10000
SYMATTR InstName R2
SYMBOL res 752 -784 R0
WINDOW 3 36 68 Left 2
SYMATTR Value 10000
SYMATTR InstName R1
SYMBOL cap 640 -896 R0
WINDOW 3 41 47 Left 2
SYMATTR Value 24fF
SYMATTR InstName Cmbit0
SYMBOL res 528 -848 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 30000
SYMBOL voltage 1120 -1008 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra0
SYMATTR Value PWL(30n 0 30.5n 2.9 130n 2.9 130.5n 0)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pF
SYMBOL nmos4 672 96 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value nmos45lp
SYMATTR Value2 l=0.27um w=0.22um
SYMBOL nmos4 608 -1216 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value nmos45lp
SYMATTR Value2 l=0.085um w=0.555um
SYMBOL voltage 1664 -992 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 40 53 Left 2
SYMATTR Value {vdd}
SYMATTR InstName VDD
SYMBOL cap 1184 320 R0
WINDOW 3 41 47 Left 2
SYMATTR Value 24fF
SYMATTR InstName Cmbit1
SYMBOL res 640 -1088 R0
SYMATTR InstName R3
SYMATTR Value 1000
FLAG 720 144 0
FLAG 1664 -864 0
FLAG 1664 -1008 VDD
FLAG 1792 -864 0
FLAG 1792 -1008 VDDby2
FLAG -384 -752 0
FLAG -384 -896 sense_P
FLAG 1040 16 0
FLAG 832 16 0
FLAG 960 -416 0
FLAG 848 -304 0
FLAG 1024 -304 0
FLAG 640 -368 Eq
FLAG 944 -256 VDDby2
FLAG 416 176 sense_N
FLAG 720 192 0
FLAG 768 -320 bitline0
FLAG 1120 -288 bitline1
FLAG 656 -1168 0
FLAG 512 -800 0
FLAG 656 -912 mb0
FLAG 544 -944 ra0
FLAG 1200 208 0
FLAG 1200 384 0
FLAG 1200 304 mb3
FLAG 1088 272 ra3
FLAG 1120 -896 0
FLAG 1120 -1008 ra0
FLAG 688 -704 VDD
FLAG 1040 -576 VDD
FLAG 832 -576 VDD
FLAG 688 -752 VDD
FLAG 432 -736 sense_p
FLAG 912 -656 ACT
FLAG 960 96 NLAT
FLAG -400 96 0
FLAG -400 -48 sense_N
FLAG 832 -784 0
FLAG 1360 -32 0
FLAG 672 -208 EqNot
FLAG 864 -128 VDD
FLAG 1008 -128 VDD
FLAG 48 -160 0
FLAG 48 -272 EqNot
FLAG 64 -416 0
FLAG 64 -528 Eq
TEXT -240 520 Left 2 !.include cmosedu_models.txt
TEXT 800 -952 VLeft 2 ;Bitline to array0
TEXT 1296 96 VLeft 2 ;Bitline to array1
TEXT -72 488 Left 2 !.ic v(bitline0)={vddhalf} v(bitline1)={vddhalf} v(mb0)={vdd}
TEXT -240 488 Left 2 !.tran 230ns uic
TEXT 288 -960 Left 2 ;Word line in array 0
TEXT 832 256 Left 2 ;Word line in array 1
TEXT 1200 744 Left 3 ;CMOS Sense Amplifier
TEXT 760 816 Left 2 ;To pull the bit lines up to VDD, we have to add a PMOS sense amplifier or PSA. The signal ACT is\ncommon to all of the PSAs of the array (as NLAT for the NSA). The signal sense_P is active\nlow and indicates that the PSA is firing. the PSA is usually fired after the NSA because the \nmatching of the NMOS is better than tha matching of the PMOS.
TEXT 760 968 Left 2 ;CMOS book, Circuit Design, Layout, and Simulation  by R. Jacob Baker
TEXT -64 408 Left 4 ;Simulation Configuations
TEXT -552 680 Left 3 ;Looping through different Vdd values
TEXT -544 808 Left 2 !.step param X list 1 2 3 4
TEXT -560 752 Left 2 ;// Select a few volts only
TEXT -560 880 Left 2 !.param vdd=table(X, 1, 1.35V, 2, 1.1V, 3, 1.35V, 4, 1.1V)
TEXT -560 928 Left 2 !.param vddhalf=table(X, 1, 0.675V, 2, 0.55V, 3, 0.675V, 4, 0.55V)
TEXT 360 544 Left 2 !.param tw = 2.5um
TEXT 360 592 Left 2 !.param ntw = 1um
TEXT 360 648 Left 2 !.param pretw=2.5um
TEXT 360 696 Left 2 !.param prentw=2.5um