* Z:\home\khalils\Downloads\files\data\raw_asc\12fed324fdf7_Counter_2bits.asc
* Generated by LTspice 26.0.1 for Windows.
A1 D1 0 CLK_INTERNAL 0 Reset D1 OUT[0] 0 DFLOP TAU=1N
A2 D2 0 D1 0 Reset D2 OUT[1] 0 DFLOP TAU=1N
A3 S1 x 0 0 0 0 RESET 0 SRFLOP TAU=1N
A5 D3 0 D2 0 Reset D3 S1 0 DFLOP TAU=1N
+13ms {p_Vdd} 13.99ms {p_Vdd} 14ms 0 31.99ms 0
+32ms {p_Vdd} 32.99ms {p_Vdd} 33ms 0 43.99ms 0
+44ms {p_Vdd} 44.99ms {p_Vdd} 45ms 0)
;Btest reset 0 V={IF(TIME<0.1MS,1,
;+IF(V(CLK)/2>=0.5,0,1))}
;Btest reset 0 V={IF(V(CLK)/2>=0.5,0,1)}
;.LIB Counter_2bits.LIB
;*.SUBCKT COUNTER_2BITS CLK RESET OUT[0] OUT[1]
;Xcounter CLK_INTERNAL RESET SEL[0] SEL[1] COUNTER_2BITS
;+vdd = {p_vdd}
;Btest reset 0 V={IF(TIME<0.1MS,1,
;V2 1 0 SINE(0 1 1k) ; input test source
;B2 2 0 V=buf(V(1)) tripdv=0.1 tripdt=10n ; b-source equivalent to a BUF a-device (with state transition time accuracy control)
Vclk clk 0 PWL(0 0 6.99ms 0 7ms {p_Vdd} 7.99ms {p_Vdd} 8ms 0 12.99ms 0
Bx x 0 V={up(V(clk))*P_VDD}
V1 CLK_INTERNAL 0 PULSE(0 5 300U 1n 1n 300U 500U)
.tran 50m
.PARAM p_Vdd=15
.func up(s) buf( ddt(s)) ; generates pulse on rising edge of s
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1604 1336
WIRE 416 256 272 256
WIRE 576 256 416 256
WIRE -384 272 -496 272
WIRE -240 272 -384 272
WIRE -32 272 -128 272
WIRE 128 272 -32 272
WIRE -384 320 -384 288
WIRE -16 320 -16 288
WIRE 400 320 400 272
WIRE -496 368 -496 272
WIRE -464 368 -496 368
WIRE -224 368 -224 256
WIRE -224 368 -304 368
WIRE -128 368 -128 272
WIRE -96 368 -128 368
WIRE 96 368 96 224
WIRE 96 368 64 368
WIRE 272 368 272 256
WIRE 320 368 272 368
WIRE 544 368 480 368
WIRE -848 384 -848 336
WIRE -464 416 -544 416
WIRE -240 416 -240 272
WIRE -240 416 -288 416
WIRE -96 416 -240 416
WIRE 128 416 128 272
WIRE 128 416 80 416
WIRE 320 416 128 416
WIRE 576 416 576 256
WIRE 576 416 496 416
WIRE -96 480 -96 464
WIRE -80 480 -96 480
WIRE -464 496 -464 464
WIRE -384 496 -384 464
WIRE -208 496 -384 496
WIRE -16 496 -16 464
WIRE -16 496 -208 496
WIRE 400 496 400 464
WIRE 400 496 -16 496
WIRE -848 512 -848 464
WIRE -80 528 -80 480
WIRE 320 528 320 464
WIRE -208 544 -208 496
WIRE -704 624 -720 624
WIRE 544 624 544 368
WIRE 544 624 -704 624
WIRE -720 704 -720 624
WIRE -592 704 -720 704
WIRE -208 704 -496 704
WIRE -592 752 -672 752
WIRE -464 752 -480 752
WIRE -464 800 -464 752
WIRE -592 816 -592 784
SYMBOL Digital\\dflop -16 320 R0
WINDOW 3 8 12 Left 2
SYMATTR InstName A2
SYMATTR Value TAU=1N
SYMBOL Digital\\dflop 400 320 R0
WINDOW 3 8 12 Left 2
SYMATTR InstName A5
SYMATTR Value TAU=1N
SYMBOL Digital\\srflop -544 656 R0
WINDOW 3 -40 28 Left 2
SYMATTR InstName A3
SYMATTR Value TAU=1N
SYMBOL voltage -848 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 300U 1n 1n 300U 500U)
SYMBOL Digital\\dflop -384 320 R0
WINDOW 3 8 12 Left 2
SYMATTR InstName A1
SYMATTR Value TAU=1N
FLAG -544 416 CLK_INTERNAL
FLAG -224 256 OUT[0]
FLAG 96 224 OUT[1]
FLAG -848 512 0
FLAG -848 336 CLK_INTERNAL
FLAG -208 544 Reset
FLAG -384 272 D1
FLAG -32 272 D2
FLAG -464 496 0
FLAG -80 528 0
FLAG -384 288 0
FLAG -16 288 0
FLAG -208 704 RESET
FLAG -672 752 x
FLAG 416 256 D3
FLAG 320 528 0
FLAG 400 272 0
FLAG -704 624 S1
FLAG -592 816 0
FLAG -464 800 0
TEXT -720 552 Left 2 !.tran 50m
TEXT 120 704 Left 2 !.PARAM p_Vdd=15\n \nVclk clk 0 PWL(0 0 6.99ms 0 7ms {p_Vdd} 7.99ms {p_Vdd} 8ms 0 12.99ms 0\n+13ms {p_Vdd} 13.99ms {p_Vdd} 14ms 0 31.99ms 0\n+32ms {p_Vdd} 32.99ms {p_Vdd} 33ms 0 43.99ms 0\n+44ms {p_Vdd} 44.99ms {p_Vdd} 45ms 0)\n \n;Btest reset 0 V={IF(TIME<0.1MS,1,\n;+IF(V(CLK)/2>=0.5,0,1))}\n \n;Btest reset 0 V={IF(V(CLK)/2>=0.5,0,1)}\n;.LIB Counter_2bits.LIB\n;*.SUBCKT COUNTER_2BITS CLK RESET OUT[0] OUT[1]\n;Xcounter CLK_INTERNAL RESET SEL[0] SEL[1] COUNTER_2BITS\n;+vdd = {p_vdd}\n;Btest reset 0 V={IF(TIME<0.1MS,1,\n \n.func up(s) buf( ddt(s)) ; generates pulse on rising edge of s\n \nBx x 0 V={up(V(clk))*P_VDD}\n \n;V2 1 0 SINE(0 1 1k) ; input test source\n;B2 2 0 V=buf(V(1)) tripdv=0.1 tripdt=10n ; b-source equivalent to a BUF a-device (with state transition time accuracy control)