Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7102-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7102-2.5.asy)
Rload OUT 0 12
C1 OUT 0 2.2 Rser=1.5m
R1 OUT N001 100k
V1 IN 0 3.5
XU1 IN OUT IN N001 OUT 0 ADP7102 Vref=2.5 ;pnba Vin)Sense)EN)PG)Vout)GND
.tran 3m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ADP7102-2.5 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.5
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 12
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 288 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP162-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP162-3.3.asy)
V1 IN 0 5
C1 OUT 0 1
XU1 IN 0 N001 OUT ADP16xf K=303u ;pnba Vin)GND)En)Vout
R1 OUT 0 330
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -48 96
WIRE 400 96 352 96
WIRE 496 96 400 96
WIRE -48 112 -48 96
WIRE 400 112 400 96
WIRE 496 112 496 96
WIRE -48 208 -48 192
WIRE 160 208 16 208
WIRE 400 208 400 176
WIRE 496 208 496 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL cap 384 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -48 96 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADP162-3.3 256 208 R0
SYMATTR InstName U1
SYMBOL res 480 96 R0
SYMATTR InstName R1
SYMATTR Value 330
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
FLAG -48 208 0
FLAG 256 272 0
FLAG 400 208 0
FLAG 496 208 0
FLAG 496 96 OUT
FLAG -48 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m
* Z:\tmp\asc_dec_bjh7r6w2\18c1ff88d3ee_Draft12_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R8 N017 Va 10k
XU2 0 N011 N013 N016 Va LT1001 ;pnba In+)In-)V+)V-)OUT
R5 N011 N008 1k
XU3 N002 N003 N005 N004 N006 LT1001 ;pnba In+)In-)V+)V-)OUT
XU1 N012 N007 N009 N015 N008 LT1001 ;pnba In+)In-)V+)V-)OUT
V3 N016 NC_01 -15
R6 N003 N001 100
R4 N008 N007 10k
R3 N007 N014 10k
* Library below included based on ModelFile attribute of instance XU2, XU3, XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1404 776
WIRE 624 -592 272 -592
WIRE 512 -528 368 -528
WIRE 624 -432 624 -512
WIRE 624 -432 544 -432
WIRE 656 -432 624 -432
WIRE 512 -400 512 -528
WIRE 544 -400 544 -432
WIRE 656 -400 656 -432
WIRE 496 -368 384 -368
WIRE 592 -368 560 -368
WIRE 528 -320 528 -336
WIRE 656 -320 528 -320
WIRE 592 -256 592 -368
WIRE 896 -256 592 -256
WIRE 624 -208 272 -208
WIRE -64 -48 -192 -48
WIRE 48 -48 16 -48
WIRE 96 32 96 -224
WIRE 96 32 -32 32
WIRE -32 80 -32 32
WIRE -656 96 -912 96
WIRE -448 96 -448 -16
WIRE -448 96 -576 96
WIRE -192 96 -192 -48
WIRE -192 96 -448 96
WIRE -64 96 -192 96
WIRE 48 112 48 -48
WIRE 48 112 0 112
WIRE 96 112 48 112
WIRE 240 112 176 112
WIRE 288 112 240 112
WIRE 416 112 352 112
WIRE -64 128 -112 128
WIRE 400 160 400 -64
WIRE 400 160 320 160
WIRE 320 176 320 160
WIRE 240 192 240 112
WIRE 288 192 240 192
WIRE -656 208 -784 208
WIRE -448 208 -448 96
WIRE -448 208 -576 208
WIRE -32 208 -32 144
WIRE 416 208 416 112
WIRE 416 208 352 208
WIRE 448 208 416 208
WIRE 624 208 624 -208
WIRE 624 208 448 208
WIRE 832 208 624 208
WIRE 288 224 176 224
WIRE -112 304 -112 128
WIRE 320 304 320 240
WIRE 832 304 832 208
WIRE 944 304 912 304
WIRE 992 304 944 304
WIRE 1136 304 1056 304
WIRE 176 336 176 224
WIRE 1008 384 1008 64
WIRE 944 400 944 304
WIRE 976 400 944 400
WIRE 1136 416 1040 416
WIRE 976 432 848 432
WIRE 528 480 528 -320
WIRE 1008 512 1008 448
WIRE 848 592 848 432
SYMBOL res 928 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 10k
SYMBOL Opamps\\OP07 320 144 R0
SYMATTR InstName U2
SYMBOL res 192 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL Opamps\\OP07 592 -368 R90
SYMATTR InstName U3
SYMBOL Opamps\\OP07 -32 48 R0
SYMATTR InstName U1
SYMBOL voltage 320 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value -15
SYMBOL res 640 -496 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R6
SYMATTR Value 100
SYMBOL res 32 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res -560 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
FLAG 176 336 0
FLAG 448 208 Va
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4122A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4122A.asy)
V2 N002 0 15
R2 OUT N004 10
XU1 N001 IN 0 0 N003 N002 0 N004 ADuM4122x Vrun2=4.3 ;pnba Vdd1)Vin)GND1)GND2)Vout)Vdd2)_SRC)Vout_SRC
V1 N001 0 5
C1 OUT 0 2n
V3 IN 0 PULSE(0 5 0 2n 2n 998n 2u)
R1 OUT N003 10
.tran 10u
.lib ADuM4122x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -16 0 -16
WIRE 480 -16 320 -16
WIRE 0 0 0 -16
WIRE 480 0 480 -16
WIRE 160 48 160 -16
WIRE 320 48 320 -16
WIRE 0 96 0 80
WIRE 480 96 480 80
WIRE 112 160 -304 160
WIRE 400 160 368 160
WIRE 496 160 480 160
WIRE 544 160 496 160
WIRE 576 160 544 160
WIRE -304 176 -304 160
WIRE 544 176 544 160
WIRE 112 240 96 240
WIRE 400 240 368 240
WIRE 496 240 496 160
WIRE 496 240 480 240
WIRE 544 256 544 240
WIRE -304 272 -304 256
WIRE 160 352 160 336
WIRE 320 352 320 336
SYMBOL res 496 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage 0 -16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 528 176 R0
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL voltage 480 -16 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 496 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL voltage -304 160 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 2n 2n 998n 2u)
SYMBOL ADuM4122A 240 160 R0
SYMATTR InstName U1
FLAG 544 256 0
FLAG 480 96 0
FLAG 0 96 0
FLAG -304 272 0
FLAG 320 352 0
FLAG 160 352 0
FLAG 96 240 0
FLAG -304 160 IN
FLAG 576 160 OUT
TEXT 416 336 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7104-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7104-1.5.asy)
V1 IN 0 PWL(0 0 20u 3.3)
R1 OUT N001 100k
Rload OUT 0 5
XU1 IN OUT IN N001 OUT 0 ADP7104-1.5 ;pnba Vin)Sense)EN)PG)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
.tran 3m startup
.lib ADP7104-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -144 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -144 48 -144 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -144 144 -144 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL voltage -144 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 20u 3.3)
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL ADP7104-1.5 224 128 R0
SYMATTR InstName U1
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
FLAG 224 304 0
FLAG -144 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -144 32 IN
FLAG 560 128 OUT
TEXT 432 288 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3020-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3020-1.5.asy)
V1 N001 0 PWL(0 0 1 10)
Rload OUT 0 100
XU1 OUT MP_01 MP_02 0 N001 MP_03 N001 LT3020-1.5 ;pnba OUT)))GND)_SHDN))IN
C1 OUT 0 2.2
.tran 1
.lib LT3020.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 160 -176 160
WIRE 16 160 0 160
WIRE 368 160 304 160
WIRE 464 160 368 160
WIRE 368 176 368 160
WIRE 464 176 464 160
WIRE -176 192 -176 160
WIRE 0 256 0 160
WIRE 16 256 0 256
WIRE 368 272 368 240
WIRE 464 272 464 256
WIRE -176 288 -176 272
WIRE 160 336 160 320
SYMBOL res 448 160 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 352 176 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL PowerProducts\\LT3020-1.5 160 192 R0
SYMATTR InstName U1
SYMBOL voltage -176 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
FLAG 160 336 0
FLAG 368 272 0
FLAG 464 272 0
FLAG -176 288 0
FLAG 464 160 OUT
TEXT 384 352 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1842.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 5
V2 N002 0 PULSE(0 3.3 0 .5m .5m 0 1m)
R1 N001 N003 10K
XU1 N004 0 N002 N002 N006 N005 N001 N003 LTC1842 ;pnba OUTA)GND)INA+)INB+)Hyst)Ref)Vcc)OUTB
R2 N001 N004 10K
.tran 3m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LTC1842.asy)
.lib LTC1842.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1436 800
WIRE 928 64 736 64
WIRE 1056 64 928 64
WIRE 1152 64 1056 64
WIRE 736 80 736 64
WIRE 1056 80 1056 64
WIRE 1152 80 1152 64
WIRE 928 112 928 64
WIRE 848 160 816 160
WIRE 736 176 736 160
WIRE 1056 176 1056 160
WIRE 1056 176 1008 176
WIRE 608 240 576 240
WIRE 816 240 816 160
WIRE 816 240 688 240
WIRE 848 240 816 240
WIRE 1152 256 1152 160
WIRE 1152 256 1008 256
WIRE 848 304 832 304
WIRE 976 400 976 384
WIRE 880 416 880 384
FLAG 736 176 0
FLAG 576 240 0
FLAG 880 416 0
SYMBOL voltage 736 64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 704 240 R90
WINDOW 3 32 56 VTop 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 3.3 0 .5m .5m 0 1m)
SYMATTR InstName V2
SYMBOL res 1040 64 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL LTC1842 928 240 R0
SYMATTR InstName U1
SYMBOL res 1136 64 R0
SYMATTR InstName R2
SYMATTR Value 10K
TEXT 1096 352 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\c3bbbc4710fc_Current_measure.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N003 N001 N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R1 N001 0 0.105
R2 N002 N003 10k
R4 N003 0 2k
I1 0 N001 SINE(3 0.01 10)
XU2 N008 N006 N007 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R3 N005 0 0.005
R5 N007 N008 36k
R6 N008 0 2k
I2 0 N005 SINE(0 10 10)
R7 N006 N005 2k
R8 N004 N006 120k
V1 N004 0 3.3
.lib opamp.sub
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 868
WIRE -16 16 -368 16
WIRE -16 96 -16 16
WIRE 256 96 -16 96
WIRE -368 112 -368 16
WIRE 384 112 320 112
WIRE 256 128 192 128
WIRE -16 144 -16 96
WIRE 384 144 384 112
WIRE 192 240 192 128
WIRE 384 240 384 224
WIRE 384 240 192 240
WIRE -368 272 -368 192
WIRE -16 272 -16 224
WIRE -16 272 -368 272
WIRE 384 272 384 240
WIRE -16 336 -16 272
WIRE 384 384 384 352
WIRE 448 448 192 448
WIRE -32 480 -384 480
WIRE 448 544 448 528
WIRE -32 560 -32 480
WIRE 64 560 -32 560
WIRE 192 560 192 528
WIRE 192 560 144 560
WIRE 240 560 192 560
WIRE -384 576 -384 480
WIRE 368 576 304 576
WIRE 240 592 176 592
WIRE -32 608 -32 560
WIRE 368 608 368 576
WIRE 176 704 176 592
WIRE 368 704 368 688
WIRE 368 704 176 704
WIRE -384 736 -384 656
WIRE -32 736 -32 688
WIRE -32 736 -384 736
WIRE 368 736 368 704
WIRE -32 800 -32 736
WIRE 368 848 368 816
FLAG 384 384 0
FLAG -16 336 0
FLAG 368 848 0
FLAG -32 800 0
FLAG 448 544 0
SYMBOL Opamps\\opamp 288 176 M180
SYMATTR InstName U1
SYMBOL res -32 128 R0
SYMATTR InstName R1
SYMATTR Value 0.105
SYMBOL res 368 128 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 368 256 R0
SYMATTR InstName R4
SYMATTR Value 2k
SYMBOL current -368 192 R180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value SINE(3 0.01 10)
SYMBOL Opamps\\opamp 272 640 M180
SYMATTR InstName U2
SYMBOL res -48 592 R0
SYMATTR InstName R3
SYMATTR Value 0.005
SYMBOL res 352 592 R0
SYMATTR InstName R5
SYMATTR Value 36k
SYMBOL res 352 720 R0
SYMATTR InstName R6
SYMATTR Value 2k
SYMBOL current -384 656 R180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I2
SYMATTR Value SINE(0 10 10)
SYMBOL res 160 544 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value 2k
SYMBOL res 176 432 R0
SYMATTR InstName R8
SYMATTR Value 120k
SYMBOL voltage 448 432 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
TEXT 552 416 Left 0 !.lib opamp.sub
TEXT 552 480 Left 0 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\17041e3d44b2_quantizer.asc
* Generated by LTspice 26.0.1 for Windows.
R2 OUT 0 1k
B1 OUT 0 V=int( (N_DIGITS_PER_VOLT+.1)*V(X))*1/N_DIGITS_PER_VOLT
V1 X 0 SINE(0 1 1k 0 0 0 3)
R1 X 0 1k
.tran 0 .005 0 1u
.param N_DIGITS_PER_VOLT = 8
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1036 680
WIRE 48 48 0 48
WIRE 112 48 48 48
WIRE 384 48 320 48
WIRE 432 48 384 48
WIRE 0 96 0 48
WIRE 112 112 112 48
WIRE 320 112 320 48
WIRE 432 128 432 48
WIRE 0 224 0 176
WIRE 112 224 112 192
WIRE 320 240 320 192
WIRE 432 240 432 208
SYMBOL res 416 112 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL bv 320 96 R0
WINDOW 3 -222 258 Left 2
SYMATTR Value V=int( (N_DIGITS_PER_VOLT+.1)*V(X))*1/N_DIGITS_PER_VOLT
SYMATTR InstName B1
SYMBOL voltage 0 80 R0
WINDOW 3 16 199 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value SINE(0 1 1k 0 0 0 3)
SYMATTR InstName V1
SYMBOL res 96 96 R0
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 0 224 0
FLAG 320 240 0
FLAG 112 224 0
FLAG 432 240 0
FLAG 48 48 X
FLAG 384 48 OUT
TEXT 144 40 Left 2 !.tran 0 .005 0 1u
TEXT 208 400 Left 2 !.param N_DIGITS_PER_VOLT = 8
* Z:\home\khalils\Downloads\files\data\raw_asc\d8a95a3e65c7_Sources.asc
* Generated by LTspice 26.0.1 for Windows.
* Logic 0: 0V\nLogic 1: 5V
* 2-Bits: How many unique numbers can you form?\n00\n01\n10\n11
V2 N002 0 5
V3 N3 0 PULSE(0 5 0 1n 1n 0.5m 1m)
V4 N4 0 PULSE(0 5 0 1n 1n 1m 2m)
V1 N001 0 0
.tran 4m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1336 680
WIRE 576 -32 576 -48
WIRE 112 16 112 -48
WIRE 368 16 368 -48
WIRE 576 16 576 -32
WIRE 112 144 112 96
WIRE 720 144 720 128
WIRE 720 176 720 144
SYMBOL voltage 368 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 112 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL voltage 720 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1n 1n 1m 2m)
SYMBOL voltage 576 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 1n 1n 0.5m 1m)
FLAG 112 144 0
FLAG 368 96 0
FLAG 576 96 0
FLAG 720 256 0
FLAG 576 -32 N3
FLAG 720 144 N4
TEXT -48 -152 Left 2 ;Logic 0: 0V\nLogic 1: 5V
TEXT 216 -144 Left 2 ;2-Bits: How many unique numbers can you form?\n00\n01\n10\n11
TEXT -50 280 Left 2 !.tran 4m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1026.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N001 N003 N004 OUT- 0 IN N002 OUT+ LT1026 ;pnba C1-)C2+)C2-)-Vout)GND)Vin)C1+)+Vout
C1 N002 N001 1
C2 N003 N004 1
C3 0 OUT- 1
C4 OUT+ 0 1
V1 IN 0 {V}
.tran 3m startup
.step param V list 4 5 6
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1026.asy)
.lib LT1026.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1912 2056
WIRE 1328 1568 1200 1568
WIRE 1520 1568 1392 1568
WIRE 1200 1696 1200 1568
WIRE 1232 1696 1200 1696
WIRE 1584 1696 1488 1696
WIRE 1648 1696 1584 1696
WIRE 1584 1712 1584 1696
WIRE 1232 1760 1152 1760
WIRE 1520 1760 1520 1568
WIRE 1520 1760 1488 1760
WIRE 1584 1792 1584 1776
WIRE 1232 1824 1152 1824
WIRE 1664 1824 1488 1824
WIRE 1664 1840 1664 1824
WIRE 1152 1888 1120 1888
WIRE 1232 1888 1152 1888
WIRE 1520 1888 1488 1888
WIRE 1152 1904 1152 1888
WIRE 1520 1920 1520 1888
WIRE 1664 1936 1664 1920
WIRE 1152 1984 1152 1968
FLAG 1152 1984 0
FLAG 1520 1920 0
FLAG 1584 1792 0
FLAG 1664 1936 0
FLAG 1664 1824 IN
FLAG 1648 1696 OUT+
FLAG 1120 1888 OUT-
SYMBOL PowerProducts\\LT1026 1360 1792 R0
SYMATTR InstName U1
SYMBOL polcap 1392 1552 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL polcap 1136 1760 R0
WINDOW 0 38 20 Left 2
WINDOW 3 36 46 Left 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL polcap 1136 1968 M180
WINDOW 0 29 53 Left 2
WINDOW 3 31 15 Left 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL polcap 1568 1712 R0
WINDOW 3 29 59 Left 2
SYMATTR Value 1
SYMATTR InstName C4
SYMBOL voltage 1664 1824 R0
SYMATTR InstName V1
SYMATTR Value {V}
TEXT 1416 1976 Left 2 !.tran 3m startup\n.step param V list 4 5 6
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4413.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4413.asy)
VWall N001 0 5
R2 N003 N004 470K
RLoad N002 0 10
VBattery N005 0 3.6
Vcc N004 0 5
XU1 N001 0 0 0 N005 N002 MP_01 MP_02 N003 N002 LTC4413 ;pnba INA)ENBA)GND)ENBB)INB)OUTB)))STAT)OUTA
C2 N002 0 4.7
.tran 1m startup
.lib LTC4413.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 144 -112 144
WIRE 288 144 272 144
WIRE 384 144 288 144
WIRE 480 144 384 144
WIRE -112 160 -112 144
WIRE 384 160 384 144
WIRE 480 160 480 144
WIRE 16 208 0 208
WIRE -112 256 -112 240
WIRE 384 256 384 224
WIRE 480 256 480 240
WIRE 16 272 0 272
WIRE 352 272 272 272
WIRE 352 288 352 272
WIRE 16 336 0 336
WIRE 352 384 352 368
WIRE 16 400 -112 400
WIRE 288 400 288 144
WIRE 288 400 272 400
WIRE -112 416 -112 400
WIRE 352 480 352 464
WIRE -112 512 -112 496
SYMBOL res 464 144 R0
SYMATTR InstName Load
SYMATTR Value 10
SYMBOL voltage -112 144 R0
WINDOW 0 17 15 Left 2
WINDOW 3 21 97 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Wall
SYMATTR Value 5
SYMBOL LTC4413 144 272 R0
SYMATTR InstName U1
SYMBOL cap 368 160 R0
WINDOW 0 24 16 Left 2
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL voltage -112 400 R0
WINDOW 0 17 15 Left 2
WINDOW 3 21 97 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Battery
SYMATTR Value 3.6
SYMBOL voltage 352 368 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 5
SYMBOL res 336 272 R0
SYMATTR InstName R2
SYMATTR Value 470K
FLAG 0 208 0
FLAG -112 256 0
FLAG 0 272 0
FLAG 384 256 0
FLAG 480 256 0
FLAG 352 480 0
FLAG 0 336 0
FLAG -112 512 0
TEXT 48 480 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3007-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3007-5.asy)
Rload OUT 0 500
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 1
XU1 IN OUT OUT 0 IN LT3008-5 ;pnba IN)OUT)Sense)GND)_SHDN
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT3007-5 176 96 R0
SYMATTR InstName U1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 336 248 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-2.8.asy)
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-2.8 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
C1 OUT 0 10
V1 IN 0 3.3
L1 N001 N002 1.5 Rser=80m
Rload OUT 0 50
.tran 400u startup
.lib ADP2504-2.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2504-2.8 176 176 R0
SYMATTR InstName U1
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 432 392 Left 2 !.tran 400u startup
TEXT 176 8 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled