* Z:\home\khalils\Downloads\files\data\raw_asc\77d07ea4c84a_pluto-b.asc
* Generated by LTspice 26.0.1 for Windows.
* Bitline to array0
* Bitline to array1
* Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
* Word line in array 0
* Word line in array 1
* .step param X 0.0v 1.5v 0.1v
* DRAM Circuit Parameters
* ohm
* Bitline Resistance
* Cell Array
* Sense Amp.
* Voltage
* Wordline Activation
* 1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
* Technology Scaling
* Wordline Parasitics
* bitline enable
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
VDD_source2 VDDby2 0 {core_voltage/2}
VDD_source1 PV 0 {plate_voltage}
CBL_cap_1 N004 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vbl_en1 bl_en 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 40n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M13 N003 N002 FF VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
R1 N001 bitline0 {mc(bitline_R, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 0 0) Rser=100 Cpar=1fF
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
R2 bitline1 N004 {mc(bitline_R, process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
M8 N004 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M14 FF bl_en ACT 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M12 N002 N003 FF VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M7 N001 ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 0 0) Rser=100 Cpar=1fF
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include ./transistor_model.pm
.tran 120ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=512
.param core_voltage=1.1V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=512
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.ic V(ff)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2520
WIRE -1392 -1648 -1392 -1664
WIRE -1392 -1552 -1392 -1568
WIRE 768 -1392 624 -1392
WIRE 624 -1360 624 -1392
WIRE 304 -1280 96 -1280
WIRE 576 -1280 304 -1280
WIRE 624 -1232 624 -1264
WIRE 624 -1232 384 -1232
WIRE 1392 -1232 1392 -1248
WIRE -608 -1152 -608 -1184
WIRE -240 -1152 -240 -1184
WIRE 384 -1152 384 -1232
WIRE -1584 -1136 -1584 -1152
WIRE 384 -1136 384 -1152
WIRE 1392 -1136 1392 -1152
WIRE -1104 -1120 -1104 -1136
WIRE -1584 -1040 -1584 -1056
WIRE -608 -1040 -608 -1072
WIRE -240 -1040 -240 -1072
WIRE -1104 -1024 -1104 -1040
WIRE 384 -976 384 -1072
WIRE 768 -848 768 -1392
WIRE 832 -848 768 -848
WIRE 1328 -800 1328 -880
WIRE 768 -768 768 -848
WIRE 432 -736 384 -736
WIRE 640 -736 432 -736
WIRE 1328 -704 1328 -800
WIRE 832 -656 688 -656
WIRE 912 -656 832 -656
WIRE 1040 -656 912 -656
WIRE 1312 -656 1040 -656
WIRE 1488 -656 1408 -656
WIRE 1568 -656 1488 -656
WIRE 1696 -656 1568 -656
WIRE -800 -624 -800 -656
WIRE -512 -624 -512 -656
WIRE -208 -624 -208 -656
WIRE 832 -624 832 -656
WIRE 1040 -624 1040 -656
WIRE 1488 -624 1488 -656
WIRE 1696 -624 1696 -656
WIRE 912 -608 880 -608
WIRE 992 -608 960 -608
WIRE 1568 -608 1536 -608
WIRE 1648 -608 1616 -608
WIRE 1312 -528 1120 -528
WIRE -800 -512 -800 -544
WIRE -512 -512 -512 -544
WIRE -208 -512 -208 -544
WIRE 768 -512 768 -688
WIRE 832 -512 832 -528
WIRE 832 -512 768 -512
WIRE 912 -512 960 -608
WIRE 912 -512 832 -512
WIRE 960 -512 912 -608
WIRE 1040 -512 1040 -528
WIRE 1040 -512 960 -512
WIRE 1120 -512 1120 -528
WIRE 1120 -512 1040 -512
WIRE 1488 -512 1488 -528
WIRE 1568 -512 1616 -608
WIRE 1568 -512 1488 -512
WIRE 1616 -512 1568 -608
WIRE 1696 -512 1696 -528
WIRE 1696 -512 1616 -512
WIRE 768 -416 768 -512
WIRE 912 -416 768 -416
WIRE 1120 -416 1120 -512
WIRE 1120 -416 1008 -416
WIRE 640 -368 608 -368
WIRE 880 -368 640 -368
WIRE 928 -368 880 -368
WIRE 1056 -368 928 -368
WIRE 1296 -368 1056 -368
WIRE 880 -352 880 -368
WIRE 1056 -352 1056 -368
WIRE 768 -320 768 -416
WIRE 768 -304 768 -320
WIRE 800 -304 768 -304
WIRE 944 -304 896 -304
WIRE 976 -304 944 -304
WIRE 1120 -304 1120 -416
WIRE 1120 -304 1072 -304
WIRE 1312 -304 1312 -528
WIRE 1120 -288 1120 -304
WIRE 944 -256 944 -304
WIRE 944 -240 944 -256
WIRE 768 -192 768 -304
WIRE 832 -192 768 -192
WIRE 912 -192 832 -192
WIRE 1040 -192 976 -192
WIRE 1120 -192 1120 -288
WIRE 1120 -192 1040 -192
WIRE 832 -176 832 -192
WIRE 1040 -176 1040 -192
WIRE 1312 -144 1312 -224
WIRE 1360 -144 1312 -144
WIRE 912 -96 976 -192
WIRE 912 -96 880 -96
WIRE 976 -96 912 -192
WIRE 992 -96 976 -96
WIRE 1360 -96 1360 -144
WIRE 832 -48 832 -80
WIRE 832 -48 720 -48
WIRE 960 -48 832 -48
WIRE 1040 -48 1040 -80
WIRE 1040 -48 960 -48
WIRE 672 32 416 32
WIRE 1312 128 1312 -144
WIRE 1312 128 1200 128
WIRE 1200 160 1200 128
WIRE 1088 272 880 272
WIRE 1152 272 1152 240
WIRE 1152 272 1088 272
WIRE 1200 304 1200 256
WIRE 1200 320 1200 304
WIRE 1312 432 1312 128
SYMBOL cap 1184 320 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL pmos4 992 -528 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL cap 1344 -96 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL pmos4 880 -528 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage -608 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0 0)
SYMATTR InstName Vsp
SYMBOL voltage -512 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL nmos4 672 -48 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL nmos4 800 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL pmos4 640 -656 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL nmos4 576 -1360 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -1392 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -1104 -1136 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage -240 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 0 0)
SYMATTR InstName Vsn
SYMBOL voltage 1392 -1248 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vbl_en1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 40n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 1408 -704 R90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M14
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 976 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL pmos4 1536 -528 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M13
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL nmos4 992 -176 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL voltage -1584 -1152 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -208 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 880 -176 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL res 1296 -320 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL res 752 -784 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL cap 816 -848 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL nmos4 1152 160 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 1008 -368 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL pmos4 1648 -528 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M12
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL cap 368 -1136 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
FLAG -1104 -1024 0
FLAG -1104 -1136 Eq
FLAG 720 0 0
FLAG -608 -1040 0
FLAG -608 -1184 sense_P
FLAG 1040 -128 0
FLAG 832 -128 0
FLAG 960 -416 0
FLAG 848 -304 0
FLAG 1024 -304 0
FLAG 640 -368 Eq
FLAG 944 -256 VDDby2
FLAG 416 32 sense_N
FLAG 720 48 0
FLAG 768 -320 bitline0
FLAG 1120 -288 bitline1
FLAG 624 -1312 0
FLAG 384 -1152 mb0
FLAG 304 -1280 ra0
FLAG 1200 208 0
FLAG 1200 384 0
FLAG 1200 304 mb3
FLAG 1088 272 ra3
FLAG -1392 -1552 0
FLAG -1392 -1664 ra0
FLAG 688 -704 VDD
FLAG 1040 -576 VDD
FLAG 832 -576 VDD
FLAG 688 -752 VDD
FLAG 432 -736 sense_p
FLAG 912 -656 ACT
FLAG 960 -48 NLAT
FLAG -240 -1040 0
FLAG -240 -1184 sense_N
FLAG 832 -784 0
FLAG 1360 -32 0
FLAG -1584 -1152 ra3
FLAG -1584 -1040 0
FLAG -800 -512 0
FLAG -800 -656 VDD
FLAG -512 -512 0
FLAG -512 -656 VDDby2
FLAG 384 -976 PV
FLAG -208 -512 0
FLAG -208 -656 PV
FLAG 1696 -576 VDD
FLAG 1488 -576 VDD
FLAG 1568 -656 FF
FLAG 1360 -656 0
FLAG 1328 -800 bl_en
FLAG 1392 -1136 0
FLAG 1392 -1248 bl_en
TEXT -376 136 Left 2 !.include ./transistor_model.pm
TEXT 800 -952 VLeft 2 ;Bitline to array0
TEXT 1296 96 VLeft 2 ;Bitline to array1
TEXT -448 104 Left 2 !.tran 120ns uic
TEXT -392 216 Left 2 ;Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
TEXT 48 -1296 Left 2 ;Word line in array 0
TEXT 832 256 Left 2 ;Word line in array 1
TEXT -368 168 Left 2 ;.step param X 0.0v 1.5v 0.1v
TEXT -832 80 Left 2 !.param process_var=0.05
TEXT -832 40 Left 2 !.step param run 1 100 1
TEXT -832 456 Left 2 !.param cell_cap={24.0fF*cell_cap_factor}
TEXT -832 496 Left 2 !.param bitline_cap={85fF*bl_cap_factor}
TEXT -920 168 Left 2 ;DRAM Circuit Parameters
TEXT -832 536 Left 2 !.param access_tran_L={85nm*access_tran_L_factor}
TEXT -832 576 Left 2 !.param access_tran_W={55nm*access_tran_W_factor}
TEXT -824 1264 Left 2 !.param bitline_R=R_per_cell*cells_per_BL
TEXT -552 1200 Left 2 ;ohm
TEXT -824 1200 Left 2 !.param R_per_cell=40
TEXT -824 1168 Left 2 ;Bitline Resistance
TEXT -824 760 Left 2 !.param SA_nmos_L={160nm*SA_nmos_L_factor}
TEXT -824 784 Left 2 !.param SA_nmos_W={1900nm*SA_nmos_W_factor}
TEXT -824 816 Left 2 !.param SA_pmos_L={160nm*SA_pmos_L_factor}
TEXT -824 840 Left 2 !.param SA_pmos_W={1330nm*SA_pmos_W_factor}
TEXT -824 880 Left 2 !.param SA_eq_L=96.3nm
TEXT -824 904 Left 2 !.param SA_eq_W=541nm
TEXT -824 944 Left 2 !.param SA_nset_L={270nm*SA_nset_L_factor}
TEXT -824 968 Left 2 !.param SA_nset_W={220nm*SA_nset_W_factor}
TEXT -824 1008 Left 2 !.param SA_pset_L={270nm*SA_pset_L_factor}
TEXT -824 1032 Left 2 !.param SA_pset_W={220nm*SA_pset_W_factor}
TEXT -824 1232 Left 2 !.param cells_per_BL=512
TEXT -832 424 Left 2 ;Cell Array
TEXT -824 728 Left 2 ;Sense Amp.
TEXT -832 224 Left 2 ;Voltage
TEXT -832 248 Left 2 !.param core_voltage=1.1V
TEXT -832 288 Left 2 !.param wordline_voltage=2.9V
TEXT -832 616 Left 2 !.param cell0_charge=core_voltage*cells_charge_state
TEXT -832 656 Left 2 !.param cells_charge_state=0.8
TEXT -832 320 Left 2 !.param pv_modifier=0.5
TEXT -832 360 Left 2 !.param plate_voltage={core_voltage*pv_modifier}
TEXT -824 1080 Left 2 !.param psense_act=4ns
TEXT -824 1104 Left 2 !.param nsense_act=4ns
TEXT -816 1520 Left 2 ;Wordline Activation
TEXT -816 1552 Left 2 !.param wl0_act=1.0
TEXT -824 1640 Left 2 !.param tech_node=7
TEXT -576 1640 Left 2 ;1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
TEXT -824 1608 Left 2 ;Technology Scaling
TEXT -824 1672 Left 2 !.param cell_cap_factor={0.95**tech_node}
TEXT -824 1704 Left 2 !.param bl_cap_factor={0.95**tech_node}
TEXT -824 1736 Left 2 !.param access_tran_L_factor={0.95**tech_node}
TEXT -824 1768 Left 2 !.param access_tran_W_factor={0.85**tech_node}
TEXT -824 1800 Left 2 !.param SA_nmos_L_factor={0.93**tech_node}
TEXT -824 1824 Left 2 !.param SA_nmos_W_factor={0.93**tech_node}
TEXT -824 1856 Left 2 !.param SA_pmos_L_factor={0.93**tech_node}
TEXT -824 1880 Left 2 !.param SA_pmos_W_factor={0.93**tech_node}
TEXT -824 1912 Left 2 !.param SA_nset_L_factor={0.93**tech_node}
TEXT -824 1936 Left 2 !.param SA_nset_W_factor={0.93**tech_node}
TEXT -824 1968 Left 2 !.param SA_pset_L_factor={0.93**tech_node}
TEXT -824 1992 Left 2 !.param SA_pset_W_factor={0.95**tech_node}
TEXT -824 1448 Left 2 !.param wordline_C={WL_C_per_cell*cells_per_LWL}
TEXT -824 1384 Left 2 !.param WL_C_per_cell=0.07fF
TEXT -824 1328 Left 2 ;Wordline Parasitics
TEXT -824 1352 Left 2 !.param cells_per_LWL=512
TEXT -824 1416 Left 2 !.param WL_R_per_cell=40ohm
TEXT -824 1480 Left 2 !.param wordline_R={WL_R_per_cell*cells_per_LWL}
TEXT -824 2024 Left 2 !.param WL_cap_factor={0.95**tech_node}
TEXT -824 2056 Left 2 !.param WL_res_factor={0.95**tech_node}
TEXT 1472 -936 Right 2 ;bitline enable
TEXT 1712 -696 Left 2 !.ic V(ff)=0