* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5050_chan1_2.asc
* Generated by LTspice 26.0.1 for Windows.
* The schematic simulates channels 1 and 2 in parallel.\nNotice how the SS12, COMP, and FB pins are configured\nThis is DIFFERENT then the real world. Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
* Library below included based on ModelFile attribute of instance XU3, XU4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5050_chan1_2.asy)
A1 N012 0 0 0 0 N013 N009 0 SCHMITT Vt=0.5 vh=8m Vhigh=5 Vlow=0
C2 OUT 0 8.12
R3 N004 0 1.82K
R11 N016 0 22K
Rload OUT 0 2
M2 N015 N016 0 0 BSC080N03MS
L1 N003 OUT 2.2
R7 N011 0 31.6K
C1 N001 N003 0.1
R6 N006 0 22K
R9 N017 N019 600k
XU4 N020 N013 N017 N002 IN N014 N015 N016 N010 N005 N018 0 MP_07 MP_08 N019 ADP5050_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)))SS12
R1 IN N002 10K
R10 N019 0 100K
R2 N002 0 10K
C6 N014 N015 0.1
R8 N007 N008 10K
C4 N005 N004 2.2n
R14 N020 0 31.6K
R4 OUT N010 34.8K
R5 N010 0 23.2K
L2 N015 OUT 2.2
V1 IN 0 12
C3 N007 0 1
C8 N017 0 1
V3 N012 0 PULSE(0 5 0 10n 10n 833n 1.666u)
C7 OUT 0 8.12
C5 OUT N010 47p
XU3 N011 N009 N007 N002 IN N001 N003 N006 N010 N005 N008 0 MP_05 MP_06 N007 ADP5050_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)))SS12
R16 N017 N018 10K
M1 N003 N006 0 0 BSC080N03MS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m startup
.lib ADP5050_chan1_2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 1460
WIRE -336 -96 -432 -96
WIRE -192 -96 -336 -96
WIRE 80 -96 -192 -96
WIRE 496 -96 368 -96
WIRE -432 -80 -432 -96
WIRE -336 -80 -336 -96
WIRE 496 -80 496 -96
WIRE -336 16 -336 0
WIRE -224 16 -336 16
WIRE 80 16 -224 16
WIRE 496 16 496 -16
WIRE 496 16 368 16
WIRE 560 16 496 16
WIRE 688 16 640 16
WIRE 768 16 688 16
WIRE 896 16 768 16
WIRE 976 16 896 16
WIRE 1024 16 976 16
WIRE -432 32 -432 0
WIRE -336 32 -336 16
WIRE 896 32 896 16
WIRE 496 48 496 16
WIRE 768 48 768 16
WIRE 688 112 688 16
WIRE 896 112 896 96
WIRE 1024 112 1024 96
WIRE -336 128 -336 112
WIRE -96 128 -112 128
WIRE 0 128 -16 128
WIRE 80 128 64 128
WIRE 432 128 368 128
WIRE 448 128 432 128
WIRE 496 160 496 144
WIRE 64 192 64 128
WIRE 64 192 -128 192
WIRE 432 224 432 208
WIRE -32 240 -64 240
WIRE 80 240 48 240
WIRE 80 352 -496 352
WIRE 688 352 688 176
WIRE 688 352 368 352
WIRE 768 352 768 128
WIRE 768 352 688 352
WIRE 768 368 768 352
WIRE -64 416 -64 240
WIRE 80 416 -64 416
WIRE -16 464 -32 464
WIRE 80 464 64 464
WIRE 448 464 368 464
WIRE 496 464 448 464
WIRE 768 464 768 448
WIRE 496 480 496 464
WIRE 224 512 224 496
WIRE -64 544 -64 416
WIRE 448 544 448 464
WIRE 448 544 -64 544
WIRE 496 560 496 544
WIRE -496 592 -496 352
WIRE -496 592 -656 592
WIRE -896 608 -1040 608
WIRE -720 608 -816 608
WIRE -496 624 -656 624
WIRE -720 672 -720 640
WIRE -192 720 -192 -96
WIRE 80 720 -192 720
WIRE 496 720 368 720
WIRE 496 736 496 720
WIRE -224 832 -224 16
WIRE 80 832 -224 832
WIRE 496 832 496 800
WIRE 496 832 368 832
WIRE 560 832 496 832
WIRE 896 832 640 832
WIRE 976 832 976 16
WIRE 976 832 896 832
WIRE 896 848 896 832
WIRE 496 864 496 832
WIRE 896 928 896 912
WIRE -128 944 -128 192
WIRE 80 944 -128 944
WIRE 432 944 368 944
WIRE 448 944 432 944
WIRE 496 976 496 960
WIRE 432 1040 432 1024
WIRE -32 1056 -64 1056
WIRE 80 1056 48 1056
WIRE -496 1168 -496 624
WIRE 80 1168 -496 1168
WIRE 688 1168 688 352
WIRE 688 1168 368 1168
WIRE -64 1216 -64 1056
WIRE -64 1216 -320 1216
WIRE -320 1232 -320 1216
WIRE 80 1232 -144 1232
WIRE -16 1280 -32 1280
WIRE 80 1280 64 1280
WIRE 448 1280 368 1280
WIRE 496 1280 448 1280
WIRE 496 1296 496 1280
WIRE -320 1328 -320 1312
WIRE -144 1328 -144 1232
WIRE -144 1328 -320 1328
WIRE 224 1328 224 1312
WIRE -320 1344 -320 1328
WIRE -64 1360 -64 1216
WIRE 448 1360 448 1280
WIRE 448 1360 -64 1360
WIRE 496 1376 496 1360
WIRE -320 1440 -320 1424
SYMBOL res 80 1264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 31.6K
SYMBOL res -352 16 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res -336 1216 R0
SYMATTR InstName R9
SYMATTR Value 600k
SYMBOL cap 880 32 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C2
SYMATTR Value 8.12
SYMBOL ind 544 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 2.2
SYMBOL res -48 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL cap 880 848 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C7
SYMATTR Value 8.12
SYMBOL cap 480 736 R0
SYMATTR InstName C6
SYMATTR Value 0.1
SYMBOL cap 480 480 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 80 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL VOLTAGE -432 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 480 1296 R0
SYMATTR InstName C8
SYMATTR Value 1
SYMBOL res 752 352 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL voltage -800 608 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 -76 50 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 10n 10n 833n 1.666u)
SYMBOL res -352 -96 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL Digital\\schmitt -720 544 R0
WINDOW 0 -34 73 VRight 2
WINDOW 123 26 118 Left 2
WINDOW 39 26 146 Left 2
SYMATTR InstName A1
SYMATTR Value2 Vt=0.5 vh=8m
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR Description Behavioral Schmitt-Triggered inverter
SYMATTR Type schmtinv
SYMBOL res 752 32 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL res 1008 0 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL nmos 448 48 R0
SYMATTR InstName M1
SYMATTR Value BSC080N03MS
SYMBOL ADP5050_chan1_2 224 192 R0
SYMATTR InstName U3
SYMBOL res 0 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL res -336 1328 R0
SYMATTR InstName R10
SYMATTR Value 100K
SYMBOL cap 480 -80 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL ADP5050_chan1_2 224 1008 R0
SYMATTR InstName U4
SYMBOL res 416 928 R0
SYMATTR InstName R11
SYMATTR Value 22K
SYMBOL cap 672 112 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL ind 544 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res 416 112 R0
SYMATTR InstName R6
SYMATTR Value 22K
SYMBOL res -48 1072 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R16
SYMATTR Value 10K
SYMBOL cap 64 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL nmos 448 864 R0
SYMATTR InstName M2
SYMATTR Value BSC080N03MS
FLAG 224 512 0
FLAG -336 128 0
FLAG 496 160 0
FLAG 896 112 0
FLAG 768 464 0
FLAG 432 224 0
FLAG 496 560 0
FLAG -32 464 0
FLAG -112 128 0
FLAG 896 16 OUT
FLAG 1024 112 0
FLAG -432 32 0
FLAG -432 -96 IN
FLAG 224 1328 0
FLAG 496 976 0
FLAG 896 928 0
FLAG 496 1376 0
FLAG -32 1280 0
FLAG -720 672 0
FLAG -1040 608 0
FLAG -320 1440 0
FLAG 432 1040 0
TEXT 584 1304 Left 2 !.tran 3m startup
TEXT -1336 312 Left 2 ;The schematic simulates channels 1 and 2 in parallel.\nNotice how the SS12, COMP, and FB pins are configured\nThis is DIFFERENT then the real world.  Channels are synced\nto out of phase clocks in order to simulate their phase relationship.