Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1307B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1307b.asy)
D1 N001 OUT MBRS140
C2 OUT 0 33 Rser=0.02
R1 OUT N004 1Meg
Rload OUT 0 100
C1 N002 0 680p
XU1 N003 N004 IN 0 N001 IN N005 N006 LT1307B ;pnba Vc)FB)_SHDN)GND)SW)Vin)LBI)LBO
L1 IN N001 10 Rser=0.02 Rpar=5000
V1 IN 0 1.8
R2 N004 0 324K
R3 N003 N002 100K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LT1307B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1716 968
WIRE 528 464 416 464
WIRE 704 464 528 464
WIRE 752 464 704 464
WIRE 880 464 832 464
WIRE 928 464 880 464
WIRE 1040 464 992 464
WIRE 1168 464 1040 464
WIRE 1264 464 1168 464
WIRE 416 480 416 464
WIRE 1168 480 1168 464
WIRE 1264 480 1264 464
WIRE 704 512 704 464
WIRE 1040 512 1040 464
WIRE 416 576 416 560
WIRE 528 576 528 464
WIRE 560 576 528 576
WIRE 880 576 880 464
WIRE 880 576 848 576
WIRE 1168 576 1168 544
WIRE 1264 576 1264 560
WIRE 464 656 432 656
WIRE 560 656 544 656
WIRE 1040 656 1040 592
WIRE 1040 656 848 656
WIRE 432 672 432 656
WIRE 1040 672 1040 656
WIRE 560 736 544 736
WIRE 864 736 848 736
WIRE 432 752 432 736
WIRE 1040 768 1040 752
WIRE 704 816 704 800
SYMBOL RES 560 640 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL SCHOTTKY 928 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL RES 1248 464 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL VOLTAGE 416 464 R0
WINDOW 3 26 94 Left 2
SYMATTR Value 1.8
SYMATTR InstName V1
SYMBOL PowerProducts\\LT1307B 704 656 R0
SYMATTR InstName U1
SYMBOL RES 1024 656 R0
SYMATTR InstName R2
SYMATTR Value 324K
SYMBOL CAP 416 672 R0
SYMATTR InstName C1
SYMATTR Value 680p
SYMBOL RES 1024 496 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL POLCAP 1152 480 R0
SYMATTR InstName C2
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02
SYMBOL IND 736 480 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 1264 464 OUT
FLAG 1040 768 0
FLAG 1168 576 0
FLAG 1264 576 0
FLAG 432 752 0
FLAG 416 576 0
FLAG 704 816 0
FLAG 416 464 IN
TEXT 960 824 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2634d873b17c_Draft6.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1401.asy)
R2 VIn N001 R
R1 Out N002 R
V1 VIn 0 V
M2 N003 N002 0 0 NMOS
C1 N004 0 C
R3 N001 N004 R
M1 Out N003 VIn VIn PMOS
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 ADG1401 ;pnba Vdd)Vss)IN)S)D)GND
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib ADG1401.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 808
WIRE -32 -16 -64 -16
WIRE -32 64 -32 -16
WIRE -32 64 -160 64
WIRE 16 64 -32 64
WIRE 512 64 16 64
WIRE 656 64 608 64
WIRE 752 64 656 64
WIRE 656 112 656 64
WIRE -160 192 -160 144
WIRE 16 192 16 144
WIRE 656 224 656 192
WIRE 656 224 464 224
WIRE 528 256 528 112
WIRE 16 336 16 272
WIRE 464 336 464 224
WIRE 480 336 464 336
WIRE 16 432 16 400
WIRE 448 432 16 432
WIRE 528 432 528 352
WIRE 528 432 448 432
WIRE 448 464 448 432
IOPIN 752 64 Out
IOPIN -64 -16 In
SYMBOL pmos 608 112 M270
SYMATTR InstName M1
SYMBOL voltage -160 48 R0
SYMATTR InstName V1
SYMBOL res 640 96 R0
SYMATTR InstName R1
SYMBOL res 0 48 R0
SYMATTR InstName R2
SYMBOL nmos 480 256 R0
SYMATTR InstName M2
SYMBOL res 0 176 R0
SYMATTR InstName R3
SYMBOL cap 0 336 R0
SYMATTR InstName C1
SYMBOL Switches\\ADG1401 240 272 R0
SYMATTR InstName U1
FLAG 448 464 0
FLAG -160 192 0
FLAG 752 64 Out
FLAG -64 -16 VIn
* Z:\home\khalils\Downloads\files\data\raw_asc\09a944ab809e_Fig11_4_long.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Vout and Id(M1)
* 10/1
* 10/1
M1 Vout Vin 0 0 N_1u l=1u w=10u
M2 Vout Vin VDD VDD P_1u l=1u w=10u
Vin Vin 0 0
VDD VDD 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vin 0 5
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 192 -368 192 -384
WIRE 192 -352 192 -368
WIRE 448 -304 448 -352
WIRE 400 -288 368 -288
WIRE 192 -240 192 -272
WIRE 320 -176 304 -176
WIRE 368 -176 368 -288
WIRE 368 -176 320 -176
WIRE 448 -176 448 -208
WIRE 624 -176 448 -176
WIRE 656 -176 624 -176
WIRE 208 -96 208 -112
WIRE 368 -96 368 -176
WIRE 400 -96 368 -96
WIRE 448 -32 448 -80
WIRE 208 0 208 -16
SYMBOL nmos4 400 -176 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL voltage 192 -368 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL pmos4 400 -208 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M2
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
SYMBOL voltage 208 -112 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -60 74 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vin
SYMATTR Value 0
FLAG 208 0 0
FLAG 624 -176 Vout
FLAG 208 -112 Vin
FLAG 448 -128 0
FLAG 192 -240 0
FLAG 192 -368 VDD
FLAG 448 -256 VDD
FLAG 448 -32 0
FLAG 448 -352 VDD
FLAG 320 -176 Vin
TEXT 264 8 Left 2 !.dc Vin 0 5
TEXT 264 32 Left 2 !.include cmosedu_models.txt
TEXT 496 -360 Left 2 ;Plot Vout and Id(M1)
TEXT 344 -320 Left 2 ;10/1
TEXT 344 -72 Left 2 ;10/1
* Z:\home\khalils\Downloads\files\data\raw_asc\31d813d99f65_I_controlled_I_source.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
R4 Out In 15e6
R5 N002 N003 15e6
XU2 Out N002 VDD VSS N001 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V2 VSS 0 -1.8
R6 Out N001 15e6
R7 N001 N002 15e6
XU1 0 In VDD VSS N003 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V1 VDD 0 1.8
R2 In N003 750
.tran 220u
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2152 1172
WIRE 800 304 752 304
WIRE 752 336 752 304
WIRE 1264 336 1120 336
WIRE 1520 336 1264 336
WIRE 880 352 832 352
WIRE 960 352 880 352
WIRE 1024 352 960 352
WIRE 1120 352 1120 336
WIRE 1120 352 1104 352
WIRE 1520 368 1520 336
WIRE 800 384 800 304
WIRE 832 384 832 352
WIRE 960 400 960 352
WIRE 1120 416 1120 352
WIRE 1136 416 1120 416
WIRE 1264 432 1264 416
WIRE 1264 432 1200 432
WIRE 1136 448 1120 448
WIRE 1264 448 1264 432
WIRE 816 512 816 448
WIRE 960 512 960 480
WIRE 960 512 816 512
WIRE 1024 512 960 512
WIRE 1120 512 1120 448
WIRE 1120 512 1104 512
WIRE 1120 528 1120 512
WIRE 1264 528 1120 528
IOPIN 880 352 In
IOPIN 1520 368 Out
SYMBOL res 1120 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 15e6
SYMBOL voltage 592 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL OpAmps\\UniversalOpAmp 1168 432 M180
SYMATTR InstName U2
SYMBOL res 944 384 R0
SYMATTR InstName R2
SYMATTR Value 750
SYMBOL res 1248 320 R0
SYMATTR InstName R6
SYMATTR Value 15e6
SYMBOL res 1248 432 R0
SYMATTR InstName R7
SYMATTR Value 15e6
SYMBOL OpAmps\\UniversalOpAmp 816 416 R90
SYMATTR InstName U1
SYMBOL voltage 592 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -1.8
SYMBOL res 1120 496 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 15e6
FLAG 592 304 0
FLAG 592 224 VDD
FLAG 592 496 0
FLAG 592 416 VSS
FLAG 752 336 0
FLAG 848 416 VDD
FLAG 784 416 VSS
FLAG 1168 400 VSS
FLAG 1168 464 VDD
FLAG 880 352 In
FLAG 1520 368 Out
TEXT 560 328 Left 2 !.tran 220u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-SD.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-SD.asy)
Rload OUT 0 500
XU1 IN 0 IN OUT OUT LT1761-SD ;pnba IN)GND)_SHDN)ADJ)OUT
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 16 48 0 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 336 144 336 48
WIRE 336 144 304 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1761-SD 160 96 R0
SYMATTR InstName U1
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -208 48 IN
TEXT 368 232 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\2eda83ddcaa3_NMOSvtc.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N002 0 1.8
M1 N001 N002 0 N003 NMOS l=1080nm w=1080nm
V1 N001 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V1 0 1.80 0.1 V2 0 1.8 0.2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 64 176 64
WIRE 176 96 176 64
WIRE 176 208 176 176
WIRE 128 288 0 288
WIRE 176 288 176 256
WIRE 0 352 0 288
WIRE 176 368 176 304
WIRE 0 496 0 432
SYMBOL nmos4 128 208 R0
SYMATTR InstName M1
SYMATTR Value2 l=1080nm w=1080nm
SYMBOL voltage 176 192 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL voltage 0 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
FLAG 0 496 0
FLAG 176 368 0
FLAG 272 64 0
TEXT -272 80 Left 2 !.dc V1 0 1.80 0.1 V2 0 1.8 0.2
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1636.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1636.asy)
R1 OUT 0 10K
V4 N002 0 PULSE(0 5 0 1u 1u .5m 1m)
V1 +V 0 5
V3 N001 0 SINE(2.5 1 10K)
XU1 N001 OUT +V 0 OUT N002 LT1636 ;pnba In+)In-)V+)V-)OUT)SHDN
.tran 3m startup
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2152 680
WIRE 368 80 128 80
WIRE -160 128 -160 112
WIRE 192 144 192 128
WIRE 128 192 128 80
WIRE 160 192 128 192
WIRE -160 224 -160 208
WIRE 368 224 368 80
WIRE 368 224 304 224
WIRE 416 224 368 224
WIRE 368 240 368 224
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 320 192 304
WIRE 368 336 368 320
WIRE 240 352 240 304
WIRE 0 368 0 352
WIRE 240 448 240 432
SYMBOL voltage -160 112 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 352 224 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL opamps\\LT1636 192 224 R0
SYMATTR InstName U1
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(2.5 1 10K)
SYMBOL voltage 240 336 R0
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1u 1u .5m 1m)
FLAG -160 224 0
FLAG 192 128 +V
FLAG -160 112 +V
FLAG 0 368 0
FLAG 240 448 0
FLAG 192 320 0
FLAG 368 336 0
FLAG 416 224 OUT
TEXT 472 328 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG801.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 1 input.\nPin Capacitance and Charge Injection are not included.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG801.asy)
C1 D 0 33p
XU1 +V IN S D 0 ADG801 ;pnba Vdd)IN)S)D)GND
VS S 0 3
R1 D 0 47
V1 +V 0 5
V2 IN 0 PULSE(0 3 0 10n 10n 980n 2u)
.tran 10u
.lib ADG801.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -272 -16 -288 -16
WIRE -240 -16 -272 -16
WIRE -32 -16 -48 -16
WIRE 0 -16 -32 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -272 48 -368 48
WIRE -240 48 -272 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 33p
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL ADG801 -144 32 R0
SYMATTR InstName U1
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 47
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
FLAG -272 -16 S
FLAG -272 48 IN
FLAG -32 -16 D
TEXT 72 224 Left 2 !.tran 10u
TEXT -592 -232 Left 2 ;Note:\nSwitch shown for a logic 1 input.\nPin Capacitance and Charge Injection are not included.
* Z:\home\khalils\Downloads\files\data\raw_asc\2224fe056646_Fig16_67.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot -I(VGS)
M1 N001 VGS N003 N002 N_50n l=50n w=500n
R1 N003 0 1G
R2 N001 0 1G
VGS VGS 0 0
VB N002 0 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.dc VB 0 2 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1748 680
WIRE 384 -128 384 -144
WIRE 384 -96 384 -128
WIRE 384 16 384 -16
WIRE 576 -144 384 -144
WIRE 624 -336 624 -368
WIRE 624 -224 624 -256
WIRE 624 -96 624 -128
WIRE 624 16 624 -16
WIRE 736 -176 624 -176
WIRE 880 -176 816 -176
WIRE 880 -112 880 -176
SYMBOL voltage 384 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 39 90 Left 0
WINDOW 0 39 62 Left 0
SYMATTR Value 0
SYMATTR InstName VGS
SYMBOL res 608 -112 R0
SYMATTR InstName R1
SYMATTR Value 1G
SYMBOL res 640 -240 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R2
SYMATTR Value 1G
SYMBOL nmos4 576 -224 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
WINDOW 123 -114 109 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 720 -176 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName VB
SYMATTR Value 1
FLAG 384 16 0
FLAG 384 -128 VGS
FLAG 880 -112 0
FLAG 624 16 0
FLAG 624 -368 0
TEXT 376 80 Left 0 !.lib cmosedu_models.txt
TEXT 376 56 Left 0 !.dc VB 0 2 1m
TEXT 416 -264 Left 0 ;Plot -I(VGS)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6654-4.096.asc
* Generated by LTspice 26.0.1 for Windows.
* Turn on and off 5mA of sink current\nand then on and off 5mA of source current
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6654-4.096.asy)
V3 N001 0 PULSE(0 1 100u 10n 10n 200u 10m)
XU1 0 IN OUT LT6654-4.096 ;pnba GND)IN)OUT
S1 0 OUT N002 0 5mA
V1 IN 0 5
C1 OUT 0 1
S2 OUT IN N001 0 5mA
V2 N002 0 PULSE(0 1 600u 10n 10n 200u 10m)
.tran 1m
.model 5mA SW(Ron=10 Roff=1Meg Vt=.5 Vh=-.1 Ilimit=5m level=2)
.lib LT6654-4.096.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4212 1120
WIRE 2288 256 1840 256
WIRE 2288 272 2288 256
WIRE 2640 288 2336 288
WIRE 2752 288 2720 288
WIRE 2352 336 2336 336
WIRE 1840 384 1840 256
WIRE 1840 384 1744 384
WIRE 1872 384 1840 384
WIRE 2176 384 2096 384
WIRE 2288 384 2288 352
WIRE 2288 384 2176 384
WIRE 2352 384 2288 384
WIRE 1744 400 1744 384
WIRE 2176 400 2176 384
WIRE 2288 400 2288 384
WIRE 2640 416 2336 416
WIRE 2752 416 2720 416
WIRE 2352 464 2336 464
WIRE 1984 480 1984 448
WIRE 2176 480 2176 464
WIRE 1744 496 1744 480
WIRE 2288 496 2288 480
SYMBOL voltage 2624 288 M90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 1 100u 10n 10n 200u 10m)
SYMATTR InstName V3
SYMBOL voltage 1744 384 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL sw 2288 496 R180
WINDOW 0 -19 97 Right 2
WINDOW 3 -12 12 Right 2
SYMATTR InstName S1
SYMATTR Value 5mA
SYMBOL sw 2288 368 R180
WINDOW 0 -9 107 Right 2
WINDOW 3 -9 6 Right 2
SYMATTR InstName S2
SYMATTR Value 5mA
SYMBOL cap 2160 400 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL LT6654-4.096 1984 384 R0
SYMATTR InstName U1
SYMBOL voltage 2624 416 M90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 600u 10n 10n 200u 10m)
FLAG 1984 480 0
FLAG 2352 384 OUT
FLAG 1744 384 IN
FLAG 1744 496 0
FLAG 2176 480 0
FLAG 2288 496 0
FLAG 2352 464 0
FLAG 2752 416 0
FLAG 2352 336 0
FLAG 2752 288 0
TEXT 2112 552 Left 2 !.tran 1m\n.model 5mA SW(Ron=10 Roff=1Meg Vt=.5 Vh=-.1 Ilimit=5m level=2)
TEXT 2024 248 Bottom 2 ;Turn on and off 5mA of sink current\nand then on and off 5mA of source current
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1073.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1073.asy)
R2 N002 0 25K
L1 IN N001 33 Rser=0.02 Rpar=5000
R1 OUT N002 500K
V1 IN 0 2.8
C2 OUT 0 100 Rser=0.02
XU1 IN IN N001 0 0 MP_01 MP_02 N002 LT1073 top=1K bot=1T ;pnba Ilim)Vin)SW1)SW2)GND)))FB
D1 N001 OUT MBRS140
Rload OUT 0 25
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT1073.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2392 1424
WIRE 1376 912 1232 912
WIRE 1504 912 1376 912
WIRE 1568 912 1504 912
WIRE 1680 912 1648 912
WIRE 1728 912 1680 912
WIRE 1840 912 1792 912
WIRE 1952 912 1840 912
WIRE 2064 912 1952 912
WIRE 1232 928 1232 912
WIRE 1952 928 1952 912
WIRE 2064 928 2064 912
WIRE 1840 944 1840 912
WIRE 1376 960 1376 912
WIRE 1504 960 1504 912
WIRE 1232 1024 1232 1008
WIRE 1952 1024 1952 992
WIRE 2064 1024 2064 1008
WIRE 1680 1040 1680 912
WIRE 1680 1040 1568 1040
WIRE 1840 1104 1840 1024
WIRE 1840 1104 1568 1104
WIRE 1840 1120 1840 1104
WIRE 1584 1168 1568 1168
WIRE 1840 1216 1840 1200
WIRE 1440 1264 1440 1248
SYMBOL RES 1824 1104 R0
SYMATTR InstName R2
SYMATTR Value 25K
SYMBOL IND 1552 928 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL res 2048 912 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL VOLTAGE 1232 912 R0
SYMATTR InstName V1
SYMATTR Value 2.8
SYMBOL POLCAP 1936 928 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL schottky 1728 928 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL RES 1824 928 R0
SYMATTR InstName R1
SYMATTR Value 500K
SYMBOL POWERPRODUCTS\\LT1073 1440 1104 R0
WINDOW 0 72 -160 Left 2
SYMATTR InstName U1
FLAG 1584 1168 0
FLAG 1440 1264 0
FLAG 1232 1024 0
FLAG 2064 1024 0
FLAG 1952 1024 0
FLAG 1840 1216 0
FLAG 2064 912 OUT
FLAG 1232 912 IN
TEXT 1704 1280 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\9c1ccbe8aa58_solar_cell_MPP.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N001 0 DiodeSolarCell
I1 0 N001 7A
R1 N001 Array_out 0.010
V1 Array_out 0 0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0.1 45
.model DiodeSolarCell D LEVEL=1 IS=8.0411e-10 N=72.2592 EG=80.2077 XTI=216.7776
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1572 680
WIRE 0 64 -112 64
WIRE 112 64 0 64
WIRE 288 64 192 64
WIRE 416 64 288 64
WIRE -112 80 -112 64
WIRE 0 160 0 64
WIRE 416 160 416 64
WIRE -112 320 -112 160
WIRE 0 320 0 224
WIRE 0 320 -112 320
WIRE 416 320 416 240
WIRE 416 320 0 320
WIRE 0 352 0 320
SYMBOL voltage 416 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL diode -16 160 R0
SYMATTR InstName D1
SYMATTR Value DiodeSolarCell
SYMBOL res 96 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 0.010
SYMBOL current -112 160 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 7A
FLAG 0 352 0
FLAG 288 64 Array_out
TEXT -176 328 Left 2 !.dc V1 0.1 45
TEXT -176 424 Left 2 !.model DiodeSolarCell D LEVEL=1 IS=8.0411e-10 N=72.2592 EG=80.2077 XTI=216.7776
* Z:\home\khalils\Downloads\files\data\raw_asc\296c265b1005_AC-equiv__Q1_Rin.asc
* Generated by LTspice 26.0.1 for Windows.
* Rin
* Rb
Vs N002 0
RQ1re vb P001
RE1 P001 0
IQ1Beta-ib N001 vb
R11 vb 0
Rs vb N002 1k
R21 vb 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 512 -32 512 -64
WIRE 288 96 160 96
WIRE 368 96 288 96
WIRE 512 96 512 48
WIRE 512 96 368 96
WIRE 80 128 80 96
WIRE 288 128 288 96
WIRE 368 128 368 96
WIRE 512 128 512 96
WIRE 512 160 512 128
WIRE 80 240 80 208
WIRE 288 240 288 208
WIRE 288 240 80 240
WIRE 368 240 368 208
WIRE 368 240 288 240
WIRE 288 272 288 240
WIRE 512 336 512 320
IOPIN 512 128 Out
LINE Normal 240 144 240 32 2
LINE Normal 448 144 448 32 2
LINE Normal 272 64 176 64
LINE Normal 480 64 400 64
LINE Normal 480 64 480 64
LINE Normal 272 64 256 48
LINE Normal 256 80 272 64
LINE Normal 480 64 464 48
LINE Normal 464 80 480 64
SYMBOL res 496 224 R0
SYMATTR InstName RE1
SYMATTR Value ""
SYMBOL res 352 112 R0
WINDOW 0 -36 97 Left 2
SYMATTR InstName R21
SYMATTR Value ""
SYMBOL voltage 80 112 R0
WINDOW 0 -12 56 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vs
SYMATTR Value ""
SYMBOL res 496 144 R0
WINDOW 0 36 49 Left 2
SYMATTR InstName Q1re
SYMATTR Value ""
SYMBOL res 176 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rs
SYMATTR Value 1k
SYMBOL res 272 112 R0
WINDOW 0 -34 99 Left 2
SYMATTR InstName R11
SYMATTR Value ""
SYMBOL current 512 -32 R0
SYMATTR InstName Q1Beta-ib
SYMATTR Value ""
FLAG 288 272 0
FLAG 512 336 0
FLAG 512 128 vb
TEXT 184 40 Left 2 ;Rin
TEXT 400 40 Left 2 ;Rb
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1328.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1328.asy)
V1 +V 0 5
I1 N001 0 PULSE(7u 100u 0 10n 10n .5u 1u)
C3 0 N002 1000p
C1 N003 N004 10n Rser=.1
C2 N003 0 330p
XU1 N001 N003 N004 0 N005 +V 0 N002 LT1328 ;pnba IN)FILT)FILT_SW)GND)DATA)VCC)MODE)Vbias
.tran 10u
.lib LT1328.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -528 -144 -624 -144
WIRE -208 -144 -448 -144
WIRE 64 -144 48 -144
WIRE 144 -144 128 -144
WIRE -272 -80 -352 -80
WIRE -208 -80 -272 -80
WIRE 80 -80 48 -80
WIRE -352 -64 -352 -80
WIRE -208 -16 -272 -16
WIRE 80 -16 48 -16
WIRE -528 0 -528 -16
WIRE -352 16 -352 0
WIRE -208 48 -240 48
WIRE 80 48 48 48
WIRE -528 96 -528 80
SYMBOL cap 128 -160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1000p
SYMBOL cap -368 -64 R0
WINDOW 0 27 13 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C2
SYMATTR Value 330p
SYMBOL voltage -528 -16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT1328 -80 -48 R0
SYMATTR InstName U1
SYMBOL current -448 -144 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2
WINDOW 123 32 40 VTop 2
WINDOW 39 32 40 VTop 2
SYMATTR InstName I1
SYMATTR Value PULSE(7u 100u 0 10n 10n .5u 1u)
SYMBOL cap -288 -80 R0
WINDOW 0 27 13 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMATTR SpiceLine Rser=.1
FLAG -528 96 0
FLAG -528 -16 +V
FLAG -240 48 0
FLAG 80 -16 +V
FLAG -624 -144 0
FLAG -352 16 0
FLAG 144 -144 0
FLAG 80 -80 0
TEXT 80 88 Left 2 !.tran 10u