Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4604A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4604A.asy)
XU1 0 IN N004 N001 N003 N002 OUT IN LTM4604 ;pnba GND)Track)Run/SS)Pgood)FB)Comp)Vout)Vin
C1 OUT 0 44
Rload OUT 0 0.625
R1 N003 0 2.37K
V1 IN 0 3.3
.tran 1.2m startup
.lib LTM4604.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1260 692
WIRE 448 64 144 64
WIRE 768 64 448 64
WIRE 144 80 144 64
WIRE 448 96 448 64
WIRE 272 144 256 144
WIRE 800 144 624 144
WIRE 880 144 800 144
WIRE 800 160 800 144
WIRE 880 160 880 144
WIRE 144 176 144 160
WIRE 272 208 256 208
WIRE 640 208 624 208
WIRE 736 208 720 208
WIRE 800 256 800 224
WIRE 880 256 880 240
WIRE 272 272 256 272
WIRE 768 272 768 64
WIRE 768 272 624 272
WIRE 448 336 448 320
SYMBOL PowerProducts\\LTM4604A 448 208 R0
SYMATTR InstName U1
SYMBOL cap 784 160 R0
SYMATTR InstName C1
SYMATTR Value 44
SYMBOL res 624 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 2.37K
SYMBOL voltage 144 64 R0
WINDOW 0 23 25 Left 2
WINDOW 3 30 90 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 864 144 R0
SYMATTR InstName Rload
SYMATTR Value 0.625
FLAG 144 176 0
FLAG 448 336 0
FLAG 880 256 0
FLAG 736 208 0
FLAG 880 144 OUT
FLAG 144 64 IN
FLAG 800 256 0
TEXT 688 328 Left 2 !.tran 1.2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\92c58ffeb60a_Draft4P.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 1.8
VGS N001 VG 0.6
M1 N001 VG VD N001 pch l=lset w=wset
VUDS VD 0 0.9
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmos018.txt
.step param lset 0.2u 10u 0.1u
.meas DC ID1 FIND Id(M1) WHEN V(VD)=0.5
.meas DC ID2 FIND Id(M1) WHEN V(VD)=1.3
.meas DC ID0 FIND Id(M1) WHEN V(VD)=0.9
.meas rout param (1.3-0.5)/(ID2-ID1)
.meas lambda param 1/(ID0*rout)
.dc UDS 0.5 1.3 100m
.param wset=9.2*lset
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 928 680
WIRE 256 64 64 64
WIRE 272 64 256 64
WIRE 576 64 272 64
WIRE 64 80 64 64
WIRE 256 96 256 64
WIRE 576 128 576 64
WIRE 272 144 272 64
WIRE 272 144 256 144
WIRE 64 176 64 160
WIRE 160 176 64 176
WIRE 208 176 160 176
WIRE 256 208 256 192
WIRE 256 208 224 208
WIRE 576 288 576 208
SYMBOL voltage 576 112 R0
WINDOW 0 37 39 Left 2
WINDOW 3 38 72 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL pmos4 208 96 R0
WINDOW 0 76 21 Left 2
WINDOW 3 76 46 Left 2
WINDOW 123 77 75 Left 2
SYMATTR InstName M1
SYMATTR Value pch
SYMATTR Value2 l=lset w=wset
SYMBOL voltage 64 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 45 Left 2
WINDOW 3 38 76 Left 2
SYMATTR InstName VGS
SYMATTR Value 0.6
SYMBOL voltage 256 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 41 41 Left 2
WINDOW 3 44 71 Left 2
SYMATTR InstName UDS
SYMATTR Value 0.9
FLAG 256 288 0
FLAG 576 288 0
FLAG 160 176 VG
FLAG 224 208 VD
TEXT 32 -240 Left 2 !.lib cmos018.txt
TEXT 32 -208 Left 2 !.step param lset 0.2u 10u 0.1u
TEXT 32 -144 Left 2 !.meas DC ID1 FIND Id(M1) WHEN V(VD)=0.5
TEXT 32 -120 Left 2 !.meas DC ID2 FIND Id(M1) WHEN V(VD)=1.3
TEXT 32 -96 Left 2 !.meas DC ID0 FIND Id(M1) WHEN V(VD)=0.9
TEXT 32 -72 Left 2 !.meas rout param (1.3-0.5)/(ID2-ID1)
TEXT 32 -48 Left 2 !.meas lambda param 1/(ID0*rout)
TEXT 32 -16 Left 2 !.dc UDS 0.5 1.3 100m
TEXT 32 -184 Left 2 !.param wset=9.2*lset
* Z:\home\khalils\Downloads\files\data\raw_asc\29bd96a07291_CMOS_Potential_Divider.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout Vout 0 N001 NMOS l=5 w=15
M2 Vout Vout VDD VDD PMOS l=5 w=15
V1 VDD 0 5V
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL NMOS NMOS(VT0=0.83 LAMBDA=0.06 KP=50U)
.MODEL PMOS PMOS(VT0=0.91 LAMBDA=0.06 KP=17U)
.tran 600N
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 -48 128 -64
WIRE 144 -48 128 -48
WIRE 144 16 144 -48
WIRE 144 16 128 16
WIRE 80 32 32 32
WIRE 144 64 144 16
WIRE 144 64 128 64
WIRE -176 80 -176 16
WIRE 32 128 32 32
WIRE 128 128 128 112
WIRE 128 128 32 128
WIRE 192 128 128 128
WIRE 128 160 128 128
WIRE 144 208 128 208
WIRE 32 240 32 128
WIRE 80 240 32 240
WIRE 144 240 144 208
WIRE 144 240 128 240
WIRE -176 288 -176 160
WIRE 128 336 128 256
FLAG -176 288 0
FLAG -176 16 VDD
FLAG 128 -64 VDD
FLAG 192 128 Vout
IOPIN 192 128 Out
FLAG 128 336 0
SYMBOL nmos4 80 160 R0
SYMATTR InstName M1
SYMATTR Value2 l=5 w=15
SYMBOL pmos4 80 112 M180
SYMATTR InstName M2
SYMATTR Value2 l=5 w=15
SYMBOL voltage -176 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5V
TEXT -264 -192 Left 2 !.MODEL NMOS NMOS(VT0=0.83 LAMBDA=0.06 KP=50U)\n.MODEL PMOS PMOS(VT0=0.91 LAMBDA=0.06 KP=17U)
TEXT -224 -112 Left 2 !.tran 600N
* Z:\home\khalils\Downloads\files\data\raw_asc\113b7ebd37f6_1255.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1255.asy)
R1 N001 N003 .036
D2 N009 N005 BZX84C12L
MQ2 N002 N004 N008 N008 Si9936DY
XU1 N002 N004 0 N006 N007 N001 N005 N003 LTC1255 ;pnba DS1)G1)GND)IN1)IN2)Vs)G2)DS2
V3 N007 0 PULSE(0 5 0 100n 100n 2.5m 5m)
V1 N001 0 5
D1 N008 N004 BZX84C12L
V2 N006 0 PULSE(0 5 0 100n 100n 2.5m 5m)
R4 N008 0 100
MQ1 N003 N005 N009 N009 Si9936DY
R3 N001 N002 .036
R2 N009 0 100
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
.lib LTC1255.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE -352 80 -464 80
WIRE 176 80 -352 80
WIRE 544 80 176 80
WIRE -464 96 -464 80
WIRE -352 112 -352 80
WIRE 544 112 544 80
WIRE 176 176 176 80
WIRE -464 192 -464 176
WIRE -352 224 -352 192
WIRE 48 224 -352 224
WIRE 544 224 544 192
WIRE 544 224 304 224
WIRE -288 304 -304 304
WIRE 48 304 -288 304
WIRE 400 304 304 304
WIRE 496 304 400 304
WIRE -288 336 -288 304
WIRE 400 336 400 304
WIRE 48 384 -112 384
WIRE 336 384 304 384
WIRE -352 416 -352 320
WIRE -288 416 -288 400
WIRE -288 416 -352 416
WIRE -112 416 -112 384
WIRE 400 416 400 400
WIRE 544 416 544 320
WIRE 544 416 400 416
WIRE -352 432 -352 416
WIRE 544 432 544 416
WIRE 176 448 176 432
WIRE 336 496 336 384
WIRE -112 512 -112 496
WIRE -352 528 -352 512
WIRE 544 528 544 512
WIRE 336 592 336 576
SYMBOL zener 384 400 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value BZX84C12L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL nmos -304 224 M0
WINDOW 0 0 14 Right 2
WINDOW 3 0 54 Right 2
SYMATTR InstName Q2
SYMATTR Value Si9936DY
SYMBOL res 528 96 R0
SYMATTR InstName R1
SYMATTR Value .036
SYMBOL voltage -112 400 R0
SYMATTR Value PULSE(0 5 0 100n 100n 2.5m 5m)
SYMATTR InstName V2
SYMBOL res -368 96 R0
SYMATTR InstName R3
SYMATTR Value .036
SYMBOL res -368 416 R0
SYMATTR InstName R4
SYMATTR Value 100
SYMBOL voltage 336 480 R0
SYMATTR Value PULSE(0 5 0 100n 100n 2.5m 5m)
SYMATTR InstName V3
SYMBOL PowerProducts\\LTC1255 176 304 R0
SYMATTR InstName U1
SYMBOL zener -304 400 M180
WINDOW 0 25 70 Left 2
WINDOW 3 27 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C12L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL nmos 496 224 R0
WINDOW 0 59 30 Left 2
WINDOW 3 63 60 Left 2
SYMATTR InstName Q1
SYMATTR Value Si9936DY
SYMBOL voltage -464 80 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 528 416 R0
SYMATTR InstName R2
SYMATTR Value 100
FLAG -464 192 0
FLAG -112 512 0
FLAG 544 528 0
FLAG 176 448 0
FLAG -352 528 0
FLAG 336 592 0
TEXT 568 640 Left 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL40502-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL40502-2.8.asy)
Rload vOUT 0 14
V1 vIN 0 3.3
XU1 vIN 0 vIN vOUT ADPL40502-2.8 ;pnba Vin)GND)EN)Vout
C1 vOUT 0 1 Rser=1m
.tran 1m startup
.lib ADPL40502-2.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2808 1464
WIRE 1824 880 1728 880
WIRE 1984 880 1824 880
WIRE 1728 896 1728 880
WIRE 1984 896 1984 880
WIRE 1728 992 1728 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL ADPL40502-2.8 1984 1024 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1728 880 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1u
SYMATTR SpiceLine Rser=1m
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 14
FLAG 2256 1024 vOUT
FLAG 2256 1136 0
FLAG 1728 992 0
FLAG 1728 880 vIN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 1m startup
* Z:\tmp\asc_dec_bjh7r6w2\17ec22966542_2863-2_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
L7 N006 N005 50n Rser=10
V1 N004 0 3.3
L5 N002 N001 50n Rser=10
L3 N013 N012 50n Rser=10
V5 COM 0 SINE(0 20 10K)
C7 N002 N006 100p
C8 N003 N007 100p
C6 N001 N005 100p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2868 952
WIRE 1312 -80 1168 -80
WIRE 1376 -80 1312 -80
WIRE 1520 -80 1456 -80
WIRE 1584 -80 1520 -80
WIRE 1728 -80 1664 -80
WIRE 1840 -80 1728 -80
WIRE 1312 -32 1312 -80
WIRE 1520 -32 1520 -80
WIRE 1728 -32 1728 -80
WIRE 944 -16 656 -16
WIRE 656 0 656 -16
WIRE 1312 80 1312 32
WIRE 1312 80 1216 80
WIRE 1376 80 1312 80
WIRE 1520 80 1520 32
WIRE 1520 80 1456 80
WIRE 1584 80 1520 80
WIRE 1728 80 1728 32
WIRE 1728 80 1664 80
WIRE 1808 80 1728 80
WIRE 656 96 656 80
WIRE 1120 112 1216 80
WIRE 1120 112 1072 112
WIRE 816 128 480 128
WIRE 480 144 480 128
WIRE 1168 144 1168 -80
WIRE 1168 144 1072 144
WIRE 1216 256 1072 256
WIRE 1280 256 1216 256
WIRE 1424 256 1360 256
WIRE 1488 256 1424 256
WIRE 1632 256 1568 256
WIRE 1888 256 1632 256
WIRE 1216 304 1216 256
WIRE 1424 304 1424 256
WIRE 1632 304 1632 256
WIRE 1840 400 1840 -80
WIRE 1216 416 1216 368
WIRE 1216 416 1152 416
WIRE 1296 416 1216 416
WIRE 1424 416 1424 368
WIRE 1424 416 1376 416
WIRE 1488 416 1424 416
WIRE 1632 416 1632 368
WIRE 1632 416 1568 416
WIRE 1728 416 1728 288
WIRE 1728 416 1632 416
WIRE 1808 432 1808 80
WIRE 1440 576 1408 576
WIRE 1552 576 1520 576
SYMBOL ind 1472 96 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 123 -16 56 VBottom 2
SYMATTR InstName L7
SYMATTR Value 50n
SYMATTR Value2 Rser=10
SYMBOL voltage 656 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ind 1472 -96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 53 56 VTop 2
SYMATTR InstName L5
SYMATTR Value 50n
SYMATTR Value2 Rser=10
SYMBOL ind 1392 432 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 123 -16 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 50n
SYMATTR Value2 Rser=10
SYMBOL voltage 1536 576 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V5
SYMATTR Value SINE(0 20 10K)
SYMBOL cap 1504 -32 R0
SYMATTR InstName C7
SYMATTR Value 100p
SYMBOL cap 1712 -32 R0
SYMATTR InstName C8
SYMATTR Value 100p
SYMBOL cap 1296 -32 R0
SYMATTR InstName C6
SYMATTR Value 100p
FLAG 656 96 0
FLAG 1408 576 0
FLAG 1552 576 COM
* Z:\home\khalils\Downloads\files\data\raw_asc\3246344028f2_Fig26_18_ID_VDS.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1) and 1/d(Id(M1)) for output resistance
VDS N001 0 0
VGS N002 0 400m
M1 N001 N002 0 0 N_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VDS 0 1
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 640 80 448 80
WIRE 448 112 448 80
WIRE 640 112 640 80
WIRE 496 160 448 160
WIRE 400 192 288 192
WIRE 288 208 288 192
WIRE 448 224 448 208
WIRE 640 224 640 192
WIRE 288 304 288 288
SYMBOL voltage 288 192 R0
WINDOW 0 -90 57 Left 0
WINDOW 3 -90 85 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 400m
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 640 96 R0
WINDOW 0 41 55 Left 0
WINDOW 3 41 83 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 0
FLAG 288 304 0
FLAG 448 224 0
FLAG 640 224 0
FLAG 496 160 0
TEXT 384 272 Left 0 !.dc VDS 0 1
TEXT 384 296 Left 0 !.include cmosedu_models.txt
TEXT 224 56 Left 0 ;Plot Id(M1) and 1/d(Id(M1)) for output resistance
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1044.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1044.asy)
V1 N002 0 5
Rload N007 0 1K
C5 N007 0 10
XU1 N001 N003 0 N006 N007 N005 N004 N002 LTC1044 ;pnba Boost)Cap+)GND)Cap-)Vout)LV)OSC)Vin
C6 N003 N006 10
C1 0 N004 100p
.tran 100m startup
.lib LTC1044.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3548 1780
WIRE 3008 1440 2976 1440
WIRE 3488 1440 3264 1440
WIRE 3488 1456 3488 1440
WIRE 3008 1504 2912 1504
WIRE 3312 1504 3264 1504
WIRE 3392 1504 3376 1504
WIRE 2912 1536 2912 1504
WIRE 3008 1568 2976 1568
WIRE 3296 1568 3264 1568
WIRE 3488 1568 3488 1536
WIRE 2912 1632 2912 1600
WIRE 3008 1632 2912 1632
WIRE 3328 1632 3264 1632
WIRE 3440 1632 3328 1632
WIRE 3328 1648 3328 1632
WIRE 3440 1648 3440 1632
WIRE 3328 1744 3328 1712
WIRE 3440 1744 3440 1728
SYMBOL cap 3376 1488 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL VOLTAGE 3488 1440 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 3312 1648 R0
SYMATTR InstName C5
SYMATTR Value 10
SYMBOL POWERPRODUCTS\\LTC1044 3136 1536 R0
SYMATTR InstName U1
SYMBOL cap 2896 1536 R0
SYMATTR InstName C6
SYMATTR Value 10
SYMBOL res 3424 1632 R0
SYMATTR InstName Rload
SYMATTR Value 1K
FLAG 3488 1568 0
FLAG 2976 1568 0
FLAG 3328 1744 0
FLAG 3392 1504 0
FLAG 3440 1744 0
TEXT 3032 1752 Left 2 !.tran 100m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8057.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8057.asy)
R1 N002 0 6.98K
C2 OUT 0 22 Rser=10m
C1 N001 0 4.7
XU1 0 OUT 0 N002 IN N001 IN NC_01 LTM8057 ;pnba GND)Vout1)Vout-)ADJ)Vin)Bias)Run)SS
V1 IN 0 24
Rload OUT 0 16.7
.tran 2m startup
.lib LTM8057.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 32 -96 32
WIRE 0 32 -16 32
WIRE 384 32 320 32
WIRE 480 32 384 32
WIRE -96 48 -96 32
WIRE 384 48 384 32
WIRE 480 48 480 32
WIRE -16 128 -16 32
WIRE 0 128 -16 128
WIRE 384 128 384 112
WIRE 384 128 320 128
WIRE -96 144 -96 128
WIRE 384 144 384 128
WIRE 480 144 480 128
WIRE -80 224 -96 224
WIRE 0 224 -16 224
WIRE 336 224 320 224
WIRE 432 224 416 224
WIRE 336 320 320 320
SYMBOL cap 368 48 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=10m
SYMBOL voltage -96 32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 320 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 6.98K
SYMBOL res 464 32 R0
SYMATTR InstName Rload
SYMATTR Value 16.7
SYMBOL PowerProducts\\LTM8057 160 176 R0
SYMATTR InstName U1
SYMBOL cap -16 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.7
FLAG 336 320 0
FLAG -96 144 0
FLAG -96 224 0
FLAG 432 224 0
FLAG 480 144 0
FLAG -96 32 IN
FLAG 480 32 OUT
FLAG 384 144 0
TEXT 416 328 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\dcb42a4f5a69_LightDetector__OpAmp_.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 5
I1 N001 out PULSE(100u 230u 0 4 1 0 5)
R1 out 0 10k
C1 out_ema 0 10m
R3 out_ema 0 1Meg
R4 out 0 1Meg
C2 out 0 14p
C3 out_ema 0 14p
XU1 N002 out N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R2 N002 out_ema 1
.tran 0 10 0 0.01
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 48 32 48
WIRE 32 80 32 48
WIRE 224 80 224 48
WIRE 224 208 224 160
WIRE 368 208 224 208
WIRE 592 208 368 208
WIRE 672 208 592 208
WIRE 704 208 672 208
WIRE 224 240 224 208
WIRE 368 320 368 208
WIRE 384 320 368 320
WIRE 464 336 448 336
WIRE 384 352 368 352
WIRE 368 384 368 352
WIRE 464 384 464 336
WIRE 464 384 368 384
WIRE 464 480 464 464
WIRE 592 480 464 480
WIRE 672 480 592 480
WIRE 704 480 672 480
WIRE 464 496 464 480
FLAG 32 160 0
FLAG 224 320 0
FLAG 224 208 phototransistor
IOPIN 224 208 In
FLAG 464 560 0
FLAG 592 272 0
FLAG 592 544 0
FLAG 672 288 0
FLAG 672 560 0
FLAG 704 480 out_ema
IOPIN 704 480 Out
FLAG 704 208 out
IOPIN 704 208 Out
SYMBOL voltage 32 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL current 224 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(100u 230u 0 4 1 0 5)
SYMBOL res 208 224 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 448 496 R0
SYMATTR InstName C1
SYMATTR Value 10m
SYMBOL res 656 464 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL res 656 192 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL cap 576 208 R0
SYMATTR InstName C2
SYMATTR Value 14p
SYMBOL cap 576 480 R0
SYMATTR InstName C3
SYMATTR Value 14p
SYMBOL Opamps\\opamp 416 400 M180
SYMATTR InstName U1
SYMBOL res 448 368 R0
SYMATTR InstName R2
SYMATTR Value 1
TEXT -2 344 Left 2 !.tran 0 10 0 0.01
TEXT 0 320 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3401.asc
* Generated by LTspice 26.0.1 for Windows.
L1 IN N001 4.7 Rpar=5K
R1 N006 0 15K
R2 N004 N003 40.2K
C1 N003 0 470p
C2 N004 0 20p
R3 OUT N005 909K
R4 N005 0 549K
V1 IN 0 1.2
C3 OUT 0 22 Rser=.1
R5 IN N002 5K
XU1 N006 0 IN N001 0 N002 OUT N005 N004 IN LTC3401 ;pnba Rt)MODE)Vin)SW)GND)Pgood)Vout)FB)Vc)_SHDN
Rload OUT 0 20
.tran 750u startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3401.asy)
.lib LTC3401.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2592 2488
WIRE 1600 1920 1472 1920
WIRE 1680 1920 1600 1920
WIRE 1808 1920 1680 1920
WIRE 1856 1920 1808 1920
WIRE 1968 1920 1936 1920
WIRE 1472 1936 1472 1920
WIRE 1808 1968 1808 1920
WIRE 1968 1968 1968 1920
WIRE 1600 1984 1600 1920
WIRE 1472 2032 1472 2016
WIRE 1680 2048 1680 1920
WIRE 1712 2048 1680 2048
WIRE 2208 2048 2064 2048
WIRE 2320 2048 2208 2048
WIRE 2432 2048 2320 2048
WIRE 2208 2064 2208 2048
WIRE 2320 2064 2320 2048
WIRE 2432 2064 2432 2048
WIRE 1600 2112 1600 2064
WIRE 1712 2112 1600 2112
WIRE 2320 2160 2320 2128
WIRE 2432 2160 2432 2144
WIRE 1504 2176 1456 2176
WIRE 1600 2176 1584 2176
WIRE 1712 2176 1600 2176
WIRE 2208 2176 2208 2144
WIRE 2208 2176 2064 2176
WIRE 1456 2192 1456 2176
WIRE 2208 2192 2208 2176
WIRE 1600 2208 1600 2176
WIRE 1712 2240 1680 2240
WIRE 2096 2240 2064 2240
WIRE 2096 2256 2096 2240
WIRE 1456 2288 1456 2256
WIRE 1600 2288 1600 2272
WIRE 2208 2288 2208 2272
WIRE 1888 2336 1888 2320
WIRE 2096 2352 2096 2336
FLAG 2096 2352 0
FLAG 1888 2336 0
FLAG 1456 2288 0
FLAG 1600 2288 0
FLAG 2208 2288 0
FLAG 1472 2032 0
FLAG 2320 2160 0
FLAG 2432 2160 0
FLAG 2432 2048 OUT
FLAG 1680 2240 0
FLAG 1472 1920 IN
SYMBOL ind 1840 1936 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rpar=5K
SYMBOL RES 2080 2240 R0
SYMATTR InstName R1
SYMATTR Value 15K
SYMBOL res 1600 2160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 40.2K
SYMBOL cap 1440 2192 R0
SYMATTR InstName C1
SYMATTR Value 470p
SYMBOL cap 1584 2208 R0
SYMATTR InstName C2
SYMATTR Value 20p
SYMBOL res 2192 2048 R0
SYMATTR InstName R3
SYMATTR Value 909K
SYMBOL res 2192 2176 R0
SYMATTR InstName R4
SYMATTR Value 549K
SYMBOL VOLTAGE 1472 1920 R0
SYMATTR InstName V1
SYMATTR Value 1.2
SYMBOL polcap 2304 2064 R0
SYMATTR InstName C3
SYMATTR Value 22
SYMATTR SpiceLine Rser=.1
SYMBOL res 1584 1968 R0
SYMATTR InstName R5
SYMATTR Value 5K
SYMBOL POWERPRODUCTS\\LTC3401 1888 2144 R0
SYMATTR InstName U1
SYMBOL res 2416 2048 R0
SYMATTR InstName Rload
SYMATTR Value 20
TEXT 2224 2360 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\529d58fe383c_parte1.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 N_1u l=1u w=3u
Vgs N002 0 1
Vds N001 0 2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vds 0 5 0.01 Vgs 0 5 0.5
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 80 256 80
WIRE 304 128 256 128
WIRE 208 160 32 160
WIRE 32 176 32 160
WIRE 304 176 304 128
WIRE 304 176 256 176
WIRE 448 192 448 80
WIRE 256 224 256 176
WIRE 32 288 32 256
WIRE 448 320 448 272
FLAG 32 288 0
FLAG 256 224 0
FLAG 448 320 0
SYMBOL nmos4 208 80 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=3u
SYMBOL voltage 32 160 R0
SYMATTR InstName Vgs
SYMATTR Value 1
SYMBOL voltage 448 176 R0
SYMATTR InstName Vds
SYMATTR Value 2
TEXT 104 296 Left 2 !.dc Vds 0 5 0.01 Vgs 0 5 0.5
TEXT 72 48 Left 2 !.include cmosedu_models.txt
* Z:\home\khalils\Downloads\files\data\raw_asc\d2bf1a526ba9_Clamp1.asc
* Generated by LTspice 26.0.1 for Windows.
B1 out 0 V = V(Vo)
B2 Vmax 0 V = {max}
B3 Vmin 0 V = {min}
B4 V3 0 V = if(V(Vmax)>V(in),V(in),V(Vmax))
B5 Vo 0 V = if(V(V3)>V(Vmin),V(V3),V(Vmin))
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 704 -80 624 -80
WIRE -608 16 -608 -48
WIRE -400 16 -400 -48
WIRE -240 16 -240 -48
WIRE 208 16 208 -48
WIRE 624 16 624 -80
WIRE -608 192 -608 96
WIRE -400 192 -400 96
WIRE -240 192 -240 96
WIRE 208 192 208 96
WIRE 624 192 624 96
WIRE -432 320 -576 320
FLAG 624 192 0
FLAG 704 -80 out
IOPIN 704 -80 Out
FLAG -608 192 0
FLAG -400 192 0
FLAG -576 320 in
IOPIN -576 320 In
FLAG -608 -48 Vmax
FLAG -400 -48 Vmin
FLAG -240 192 0
FLAG -240 -48 V3
FLAG 208 192 0
FLAG 208 -48 Vo
SYMBOL bv 624 0 R0
SYMATTR InstName B1
SYMATTR Value V = V(Vo)
SYMBOL bv -608 0 R0
WINDOW 3 -60 232 Left 0
SYMATTR Value V = {max}
SYMATTR InstName B2
SYMBOL bv -400 0 R0
WINDOW 3 -52 229 Left 0
SYMATTR Value V = {min}
SYMATTR InstName B3
SYMBOL bv -240 0 R0
WINDOW 3 -46 228 Left 0
SYMATTR Value V = if(V(Vmax)>V(in),V(in),V(Vmax))
SYMATTR InstName B4
SYMBOL bv 208 0 R0
WINDOW 3 -46 228 Left 0
SYMATTR Value V = if(V(V3)>V(Vmin),V(V3),V(Vmin))
SYMATTR InstName B5