Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\34f34aa41f90_CompPentoCarG1Step.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 0 N003 N002 0 N001 EL34Pent Pentrode ;pnba Cathode)G1)G2)G3)Anode
Vg2 N002 0 350
Vp N001 0 0
Vg1 N003 0 0
XU2 0 N003 N002 0 N001 7591Pent Pentrode ;pnba Cathode)G1)G2)G3)Anode
.dc Vp 0 500 100 Vg1 0 -50 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 64 -144 64
WIRE 288 64 48 64
WIRE 368 80 144 80
WIRE 208 96 -64 96
WIRE 48 112 48 64
WIRE 288 112 288 64
WIRE -144 128 -144 64
WIRE 0 160 -16 160
WIRE 240 160 224 160
WIRE 144 176 144 80
WIRE 144 176 96 176
WIRE 368 176 368 80
WIRE 368 176 336 176
WIRE -64 192 -64 96
WIRE 0 192 -64 192
WIRE 144 192 144 176
WIRE 208 192 208 96
WIRE 240 192 208 192
WIRE -64 208 -64 192
WIRE 224 256 224 160
WIRE 256 256 256 240
WIRE 256 256 224 256
WIRE -144 304 -144 208
WIRE -64 304 -64 288
WIRE -64 304 -144 304
WIRE -16 304 -16 160
WIRE -16 304 -64 304
WIRE 16 304 16 240
WIRE 16 304 -16 304
WIRE 144 304 144 272
WIRE 144 304 16 304
WIRE 224 304 224 256
WIRE 224 304 144 304
WIRE 16 320 16 304
SYMBOL Valve\\Pentode 48 176 R0
WINDOW 0 -71 -61 Left 0
WINDOW 38 34 105 Center 0
SYMATTR InstName U1
SYMATTR SpiceModel EL34Pent
SYMBOL voltage 144 176 R0
WINDOW 0 -19 60 Left 0
SYMATTR InstName Vg2
SYMATTR Value 350
SYMBOL Valve\\Pentode 288 176 R0
WINDOW 0 -66 -63 Left 0
WINDOW 38 5 104 Center 0
SYMATTR InstName U2
SYMATTR SpiceModel 7591Pent
SYMBOL voltage -144 112 R0
WINDOW 0 -16 57 Left 0
SYMATTR InstName Vp
SYMATTR Value 0
SYMBOL voltage -64 192 R0
WINDOW 0 -18 61 Left 0
SYMATTR InstName Vg1
SYMATTR Value 0
FLAG 16 320 0
TEXT 40 320 Left 0 !.dc Vp 0 500 100 Vg1 0 -50 10
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3565.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 out 2.2
R1 out N002 931K
V1 IN 0 4
R2 N002 0 294K
R3 N005 0 191K
C1 out 0 22
C2 N004 0 680p Rser=12.1K
R4 IN N003 100K
C3 out N002 22p
XU1 N005 IN IN N001 0 IN IN N003 N002 N004 LTC3565 ;pnba Rt)RUN)Mode)SW)GND)PVin)SVin)Pgood)FB)Ith
Rload out 0 2
.tran 1.5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3565.asy)
.lib LTC3565.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2460 1764
WIRE 1456 1264 1392 1264
WIRE 1648 1264 1456 1264
WIRE 1744 1264 1648 1264
WIRE 1392 1280 1392 1264
WIRE 1648 1296 1648 1264
WIRE 1744 1296 1744 1264
WIRE 1456 1344 1456 1264
WIRE 1552 1344 1456 1344
WIRE 1872 1344 1840 1344
WIRE 1984 1344 1952 1344
WIRE 2080 1344 1984 1344
WIRE 2160 1344 2080 1344
WIRE 2240 1344 2160 1344
WIRE 1984 1360 1984 1344
WIRE 2080 1360 2080 1344
WIRE 2160 1360 2160 1344
WIRE 2240 1360 2240 1344
WIRE 1392 1376 1392 1360
WIRE 1456 1456 1456 1344
WIRE 1552 1456 1456 1456
WIRE 1984 1456 1984 1440
WIRE 1984 1456 1840 1456
WIRE 2080 1456 2080 1424
WIRE 2080 1456 1984 1456
WIRE 2160 1456 2160 1424
WIRE 2240 1456 2240 1440
WIRE 1456 1472 1456 1456
WIRE 1984 1472 1984 1456
WIRE 1456 1568 1456 1552
WIRE 1552 1568 1456 1568
WIRE 1856 1568 1840 1568
WIRE 1936 1568 1920 1568
WIRE 1984 1568 1984 1552
WIRE 1648 1632 1648 1616
WIRE 1744 1648 1744 1616
WIRE 1648 1728 1648 1712
FLAG 1744 1648 0
FLAG 1392 1376 0
FLAG 1648 1728 0
FLAG 2240 1456 0
FLAG 1984 1568 0
FLAG 2160 1456 0
FLAG 1936 1568 0
FLAG 1392 1264 IN
FLAG 2240 1344 out
SYMBOL ind 1856 1360 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL RES 1968 1344 R0
SYMATTR InstName R1
SYMATTR Value 931K
SYMBOL VOLTAGE 1392 1264 R0
SYMATTR InstName V1
SYMATTR Value 4
SYMBOL res 1968 1456 R0
SYMATTR InstName R2
SYMATTR Value 294K
SYMBOL res 1632 1616 R0
SYMATTR InstName R3
SYMATTR Value 191K
SYMBOL cap 2144 1360 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL cap 1856 1552 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 39 68 30 VTop 2
SYMATTR InstName C2
SYMATTR Value 680p
SYMATTR SpiceLine Rser=12.1K
SYMBOL res 1440 1456 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL cap 2064 1360 R0
SYMATTR InstName C3
SYMATTR Value 22p
SYMBOL LTC3565 1696 1456 R0
SYMATTR InstName U1
SYMBOL res 2224 1344 R0
SYMATTR InstName Rload
SYMATTR Value 2
TEXT 2040 1648 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2386-16.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\LTC2386-16.asy)
V5 N002 0 5
V3 N008 0 PULSE(0 1.8 100n .2n .2n 9.8n 100n)
V2 N007 0 PWL(0 5 100u 0)
V1 N003 0 PWL(0 0 100u 5)
R1 N004 N003 10
XU1 N004 N002 0 N005 N001 N008 N006 LTC2386-16 ;pnba IN+)Vdd)GND)Vout)REFBUF)CNV)IN-
V4 N001 0 4.096
C1 0 N005 10p
R2 N006 N007 10
.tran 110u
.lib LTC2386-16.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 12540 5124
WIRE 10752 3008 10512 3008
WIRE 10752 3040 10752 3008
WIRE 10752 3152 10752 3120
WIRE 10512 3200 10512 3008
WIRE 10880 3248 10640 3248
WIRE 9856 3280 9824 3280
WIRE 9984 3280 9936 3280
WIRE 10144 3280 10064 3280
WIRE 10880 3280 10880 3248
WIRE 10144 3328 10144 3280
WIRE 10288 3328 10144 3328
WIRE 10720 3344 10640 3344
WIRE 10816 3344 10784 3344
WIRE 10288 3360 10144 3360
WIRE 10880 3392 10880 3360
WIRE 9856 3408 9824 3408
WIRE 9984 3408 9936 3408
WIRE 10144 3408 10144 3360
WIRE 10144 3408 10064 3408
WIRE 10768 3440 10640 3440
WIRE 10512 3520 10512 3488
WIRE 10768 3584 10768 3440
WIRE 10768 3744 10768 3664
SYMBOL voltage 9952 3408 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 5 100u 0)
SYMBOL res 10080 3392 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL voltage 9952 3280 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 100u 5)
SYMBOL res 10080 3264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL LTC2386-16 10544 3344 R0
SYMATTR InstName U1
SYMBOL voltage 10880 3264 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL cap 10784 3328 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage 10768 3568 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1.8 100n .2n .2n 9.8n 100n)
SYMBOL voltage 10752 3024 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 4.096
FLAG 10768 3744 0
FLAG 10752 3152 0
FLAG 10880 3392 0
FLAG 10512 3520 0
FLAG 9824 3280 0
FLAG 9824 3408 0
FLAG 10816 3344 0
TEXT 10896 3656 Left 2 !.tran 110u
* Z:\home\khalils\Downloads\files\data\raw_asc\f0bda7996e02_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T1 N001 0 0 N002 Td=50n Z0=50
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T2 0 0 N002 0 Td=50n Z0=150
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=50n Z0=150
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\93d1dafb4976_NAND3.asc
* Generated by LTspice 26.0.1 for Windows.
D1 mix A 1N4148
R1 V+ mix 10k
Q1 Q N001 0 0 BC547B
R2 V+ Q 1k
D2 mix B 1N4148
D4 mix N001 1N4148
D5 mix C 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
* NAND3 - DTL
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 -48 288 -80
WIRE 288 -48 128 -48
WIRE 384 -48 288 -48
WIRE 32 64 16 64
WIRE 128 64 128 32
WIRE 128 64 96 64
WIRE 384 80 384 32
WIRE 448 80 384 80
WIRE 384 96 384 80
WIRE 128 128 128 64
WIRE 32 144 16 144
WIRE 128 144 128 128
WIRE 128 144 96 144
WIRE 224 144 128 144
WIRE 320 144 288 144
WIRE 32 208 16 208
WIRE 128 208 128 144
WIRE 128 208 96 208
WIRE 384 224 384 192
FLAG 384 224 0
FLAG 448 80 Q
IOPIN 448 80 Out
FLAG 16 64 A
IOPIN 16 64 In
FLAG 16 144 B
IOPIN 16 144 In
FLAG 288 -80 V+
IOPIN 288 -80 In
FLAG 128 128 mix
FLAG 16 208 C
IOPIN 16 208 In
SYMBOL diode 96 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 112 -64 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL npn 320 96 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL res 368 -64 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL diode 96 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL diode 224 160 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D4
SYMATTR Value 1N4148
SYMBOL diode 96 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D5
SYMATTR Value 1N4148
TEXT 336 -104 Left 6 ;NAND3 - DTL
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3022.asc
* Generated by LTspice 26.0.1 for Windows.
R1 OUT N001 698
R2 N001 0 200
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 .9
C1 OUT 0 10
XU1 MP_01 MP_02 OUT MP_03 MP_04 MP_05 N001 MP_06 IN 0 MP_07 IN LT3022 ;pnba ))OUT))))ADJ))_SHDN)GND))IN
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3022.asy)
.lib LT3022.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 160 -208 160
WIRE 16 160 0 160
WIRE 352 160 304 160
WIRE 464 160 352 160
WIRE 560 160 464 160
WIRE -208 176 -208 160
WIRE 464 176 464 160
WIRE 560 176 560 160
WIRE 0 256 0 160
WIRE 16 256 0 256
WIRE 352 256 352 240
WIRE 352 256 304 256
WIRE -208 272 -208 256
WIRE 352 272 352 256
WIRE 464 272 464 240
WIRE 560 272 560 256
WIRE 160 336 160 320
WIRE 352 368 352 352
FLAG 160 336 0
FLAG 352 368 0
FLAG 464 272 0
FLAG 560 272 0
FLAG -208 272 0
FLAG 560 160 OUT
FLAG -208 160 IN
SYMBOL res 336 144 R0
SYMATTR InstName R1
SYMATTR Value 698
SYMBOL res 336 256 R0
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL voltage -208 160 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 544 160 R0
SYMATTR InstName Rload
SYMATTR Value .9
SYMBOL cap 448 176 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT3022 160 192 R0
SYMATTR InstName U1
TEXT 480 352 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\24e40238c921_2934-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2934-1.asy)
R3 N001 N002 750K
MQ1 N006 N007 0 0 BSS123
R1 N002 N004 11.8K
R5 N001 N003 10K
V1 N001 0 PULSE(0 3.3 0 3.3 3.3 2)
XU1 N002 N004 N001 0 N003 N005 N006 N001 LTC2934-1 ;pnba ADJ)PFI)RT)GND)_PFO)_RST)_MR)VCC
V2 N007 0 PWL(0 0 3.999 0 4 5 4.599 5 4.6 0)
R2 N004 0 237K
R4 N001 N005 10K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10
.lib LTC2934-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 -32 -384 -32
WIRE 240 -32 -48 -32
WIRE 368 -32 240 -32
WIRE 416 -32 368 -32
WIRE 512 -32 416 -32
WIRE -384 -16 -384 -32
WIRE -48 -16 -48 -32
WIRE 416 32 416 -32
WIRE 512 32 512 -32
WIRE 240 48 240 -32
WIRE -384 80 -384 64
WIRE -48 80 -48 64
WIRE 128 80 -48 80
WIRE -48 96 -48 80
WIRE 368 96 368 -32
WIRE 368 96 352 96
WIRE 416 176 416 112
WIRE 416 176 352 176
WIRE -48 192 -48 176
WIRE 128 192 -48 192
WIRE -48 208 -48 192
WIRE 512 256 512 112
WIRE 512 256 352 256
WIRE 128 272 80 272
WIRE 80 288 80 272
WIRE -48 304 -48 288
WIRE 240 336 240 304
WIRE 32 368 -48 368
WIRE -48 384 -48 368
WIRE 80 400 80 384
WIRE -48 480 -48 464
SYMBOL res 400 16 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL voltage -48 368 R0
WINDOW 123 24 146 Left 0
WINDOW 39 24 125 Left 0
SYMATTR Value PWL(0 0 3.999 0 4 5 4.599 5 4.6 0)
SYMATTR InstName V2
SYMBOL res -64 80 R0
SYMATTR InstName R1
SYMATTR Value 11.8K
SYMBOL nmos 32 288 R0
SYMATTR InstName Q1
SYMATTR Value BSS123
SYMBOL res -64 -32 R0
SYMATTR InstName R3
SYMATTR Value 750K
SYMBOL res -64 192 R0
SYMATTR InstName R2
SYMATTR Value 237K
SYMBOL LTC2934-1 240 176 R0
SYMATTR InstName U1
SYMBOL voltage -384 -32 R0
WINDOW 123 24 146 Left 0
WINDOW 39 24 125 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0 3.3 3.3 2)
SYMBOL res 496 16 R0
SYMATTR InstName R4
SYMATTR Value 10K
FLAG -48 304 0
FLAG 240 336 0
FLAG -384 80 0
FLAG 80 400 0
FLAG -48 480 0
TEXT 424 392 Left 0 !.tran 10
* Z:\home\khalils\Downloads\files\data\raw_asc\10ad88b64f63_mosswitchA4.asc
* Generated by LTspice 26.0.1 for Windows.
* Pull to GND or tristate
Q1 N002 N003 N001 0 BC857C
R3 N001 0 100k
R1 N002 0 100
R2 N003 N004 1k
V1 N001 0 17
Q2 N004 0 0 0 BC847C
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 888 872
WIRE -240 -208 -480 -208
WIRE -32 -208 -240 -208
WIRE 368 -208 64 -208
WIRE 16 -112 16 -144
WIRE -240 -96 -240 -208
WIRE 16 0 16 -32
WIRE -240 48 -240 -16
WIRE -48 48 -240 48
WIRE 368 160 368 -208
WIRE -480 176 -480 -208
WIRE -480 272 -480 256
WIRE -240 272 -240 48
WIRE -240 272 -480 272
WIRE 16 272 16 96
WIRE 16 272 -240 272
WIRE 368 272 368 240
WIRE 368 272 16 272
WIRE -480 288 -480 272
SYMBOL res 352 144 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL npn -48 0 R0
SYMATTR InstName Q2
SYMATTR Value BC847C
SYMBOL res 0 -128 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL pnp 64 -144 M270
SYMATTR InstName Q1
SYMATTR Value BC857C
SYMBOL res -256 -112 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL voltage -480 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 17
FLAG -480 288 0
TEXT -456 352 Left 2 !.tran 1
TEXT -264 16 VRight 2 ;Pull to GND or tristate
* Z:\tmp\asc_dec_bjh7r6w2\01a47e5b8044_TS4_NORMALIZADO_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
C31 N012 0 2.59
R22 N005 V22 1
R42 Vo N006 1
C1 V2 N002 4.1911
XU8 N006 0 Vo opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R6 V2 N010 1
XU3 N003 0 V3 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R2 N003 V2 1
XU5 N004 0 V22 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2228 680
WIRE 320 -144 128 -144
WIRE 688 -144 400 -144
WIRE 416 32 384 32
WIRE 496 32 480 32
WIRE 608 32 576 32
WIRE 688 32 688 -144
WIRE 688 32 672 32
WIRE 960 48 944 48
WIRE 1136 48 1104 48
WIRE 1216 48 1200 48
WIRE 1328 48 1296 48
WIRE 1408 48 1408 -128
WIRE 1408 48 1392 48
WIRE 2080 96 2032 96
WIRE 2192 96 2160 96
WIRE 1872 112 1744 112
WIRE 128 128 128 32
WIRE 144 128 128 128
WIRE 240 144 240 32
WIRE 240 144 208 144
WIRE 288 144 240 144
WIRE 384 144 384 32
WIRE 384 144 368 144
WIRE 400 144 384 144
WIRE 128 160 96 160
WIRE 144 160 128 160
WIRE 496 160 496 32
WIRE 496 160 464 160
WIRE 576 160 576 32
WIRE 592 160 576 160
WIRE 960 160 960 48
WIRE 960 160 928 160
WIRE 1008 160 960 160
WIRE 1104 160 1104 48
WIRE 1104 160 1088 160
WIRE 1120 160 1104 160
WIRE 1744 160 1744 112
WIRE 1776 160 1744 160
WIRE 400 176 368 176
WIRE 688 176 688 32
WIRE 688 176 656 176
WIRE 736 176 688 176
WIRE 848 176 816 176
WIRE 1216 176 1216 48
WIRE 1216 176 1184 176
WIRE 1296 176 1296 48
WIRE 1312 176 1296 176
WIRE 1872 176 1872 112
WIRE 1872 176 1840 176
WIRE 1920 176 1872 176
WIRE 2032 176 2032 96
WIRE 2032 176 2000 176
WIRE 2064 176 2032 176
WIRE 592 192 576 192
WIRE 1120 192 1088 192
WIRE 1408 192 1408 48
WIRE 1408 192 1376 192
WIRE 1520 192 1408 192
WIRE 1696 192 1600 192
WIRE 1776 192 1696 192
WIRE 2192 192 2192 96
WIRE 2192 192 2128 192
WIRE 1312 208 1296 208
WIRE 2064 208 2032 208
WIRE 368 224 368 176
WIRE 576 224 576 192
WIRE 1088 240 1088 192
WIRE 1296 240 1296 208
WIRE 2032 256 2032 208
WIRE 128 272 128 160
WIRE 192 272 128 272
WIRE 496 272 496 160
WIRE 496 272 272 272
WIRE 1216 288 1216 176
WIRE 1216 288 992 288
SYMBOL cap 1680 192 R0
SYMATTR InstName C31
SYMATTR Value 2.59
SYMBOL res 1312 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R22
SYMATTR Value 1
SYMBOL res 2176 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R42
SYMATTR Value 1
SYMBOL cap 480 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.1911
SYMBOL Opamps\\opamp 2096 128 R0
SYMATTR InstName U8
SYMBOL res 288 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 1
SYMBOL Opamps\\opamp 624 112 R0
SYMATTR InstName U3
SYMBOL res 592 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL Opamps\\opamp 1152 112 R0
SYMATTR InstName U5
FLAG 496 272 V2
FLAG 688 176 V3
FLAG 576 224 0
FLAG 368 224 0
FLAG 1216 288 V22
FLAG 960 48 V21
FLAG 1408 192 V23
FLAG 1296 240 0
FLAG 1088 240 0
FLAG 1696 256 0
FLAG 2032 256 0
FLAG 2192 192 Vo
* Z:\home\khalils\Downloads\files\data\raw_asc\0abb011940e2_ProportionalSummingCircuit.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD712.asy)
Vin1 IN 0
XU2 IN OUT +V -V OUT AD712 ;pnba In+)In-)V+)V-)OUT
R1 OUT 0 5.1k
V1 +V 0 15
V2 -V 0 -15
.dc Vin1 -2 2 0.5
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1716 680
WIRE 1536 -240 1536 -256
WIRE 1648 -240 1648 -256
WIRE 1536 -144 1536 -160
WIRE 1648 -144 1648 -160
WIRE 480 32 368 32
WIRE 368 128 368 32
WIRE 384 128 368 128
WIRE 480 144 480 32
WIRE 480 144 448 144
WIRE 512 144 480 144
WIRE 528 144 512 144
WIRE 384 160 272 160
WIRE 272 176 272 160
WIRE 512 208 512 144
WIRE 272 272 272 256
SYMBOL AD712 416 80 R0
SYMATTR InstName U2
SYMBOL voltage 1536 -256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 1648 -256 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 272 160 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin1
SYMATTR Value ""
SYMBOL res 496 192 R0
SYMATTR InstName R1
SYMATTR Value 5.1k
FLAG 1536 -256 +V
FLAG 1536 -144 0
FLAG 272 272 0
FLAG 528 144 OUT
FLAG 272 160 IN
FLAG 416 112 +V
FLAG 1648 -256 -V
FLAG 416 176 -V
FLAG 1648 -144 0
FLAG 512 288 0
TEXT 232 336 Left 2 !.dc Vin1 -2 2 0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\0c0bdffea4f7_cmos_nand.asc
* Generated by LTspice 26.0.1 for Windows.
M2 P001 vin2 vgnd vgnd NMOS
M3 vdd vin1 vout vdd PMOS
M1 vout vin1 P001 vgnd NMOS
M4 vdd vin2 vout vdd PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 -96 32 -96
WIRE 192 -96 192 -272
WIRE 192 -96 112 -96
WIRE 352 -96 192 -96
WIRE 416 -96 352 -96
WIRE 112 -48 112 -96
WIRE 112 -48 32 -48
WIRE 416 -48 416 -96
WIRE 416 -48 352 -48
WIRE -16 -16 -176 -16
WIRE 304 -16 256 -16
WIRE 256 0 256 -16
WIRE 256 0 64 0
WIRE 32 32 32 0
WIRE 192 32 32 32
WIRE 352 32 352 0
WIRE 352 32 192 32
WIRE 192 64 192 32
WIRE 512 64 192 64
WIRE 192 80 192 64
WIRE -176 96 -176 -16
WIRE -176 96 -272 96
WIRE 336 128 192 128
WIRE -176 144 -176 96
WIRE 96 144 -176 144
WIRE 96 160 96 144
WIRE 144 160 96 160
WIRE 64 176 64 0
WIRE 64 176 -48 176
WIRE 336 224 336 128
WIRE 336 224 192 224
WIRE 64 256 64 176
WIRE 144 256 64 256
WIRE 192 288 192 272
WIRE 336 288 336 224
WIRE 336 288 192 288
WIRE 192 304 192 288
SYMBOL pmos4 -16 -96 R0
SYMATTR InstName M3
SYMBOL nmos4 144 176 R0
SYMATTR InstName M2
SYMBOL nmos4 144 80 R0
SYMATTR InstName M1
SYMBOL pmos4 304 -96 R0
SYMATTR InstName M4
FLAG 512 64 vout
FLAG 192 -272 vdd
FLAG -272 96 vin1
FLAG -48 176 vin2
FLAG 192 304 vgnd
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1610.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1610.asy)
Rload OUT 0 100
R2 N003 0 324K
C2 OUT 0 22 Rser=0.05
D1 N001 OUT MBRS140
XU1 N004 N003 N002 0 N001 IN 0 N004 LT1610 ;pnba Vc)FB)_SHDN)PGND)SW)Vin)GND)COMP
R1 OUT N003 1Meg
V1 IN 0 1.5
L1 IN N001 4.7 Rser=0.02 Rpar=5000
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT1610.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1492 944
WIRE 624 464 464 464
WIRE 672 464 624 464
WIRE 784 464 752 464
WIRE 832 464 784 464
WIRE 976 464 896 464
WIRE 1088 464 976 464
WIRE 1184 464 1088 464
WIRE 464 480 464 464
WIRE 1088 480 1088 464
WIRE 1184 480 1184 464
WIRE 976 496 976 464
WIRE 624 544 624 464
WIRE 784 544 784 464
WIRE 464 576 464 560
WIRE 1088 576 1088 544
WIRE 1184 576 1184 560
WIRE 560 624 544 624
WIRE 976 624 976 576
WIRE 976 624 848 624
WIRE 976 640 976 624
WIRE 560 688 528 688
WIRE 864 688 848 688
WIRE 976 736 976 720
WIRE 784 784 784 768
WIRE 528 800 528 688
WIRE 624 800 624 768
WIRE 624 800 528 800
SYMBOL POWERPRODUCTS\\LT1610 704 656 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 464 464 R0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL SCHOTTKY 832 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL RES 960 480 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL IND 656 480 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL RES 1168 464 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL POLCAP 1072 480 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=0.05
SYMBOL RES 960 624 R0
SYMATTR InstName R2
SYMATTR Value 324K
FLAG 464 576 0
FLAG 1184 576 0
FLAG 1088 576 0
FLAG 976 736 0
FLAG 784 784 0
FLAG 1184 464 OUT
FLAG 464 464 IN
FLAG 864 688 0
TEXT 1000 800 Left 2 !.tran 2m startup