* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5053_chan1_2.asc
* Generated by LTspice 26.0.1 for Windows.
* The schematic simulates channels 1 and 2 in parallel.\nNotice how the SS12, COMP, and FB pins are configured\nThis is DIFFERENT than the real world. Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
* Rlim is the resistor generally placed on DL pin to set current limit
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5053_chan1_2.asy)
A1 N013 0 0 0 0 N014 N010 0 SCHMITT Vt=0.5 vh=8m Vhigh=5 Vlow=0
C2 OUT 0 8.12
XU2 N012 N010 N007 N002 IN N001 N003 N006 N009 N005 N008 0 N011 MP_06 N007 ADP505x_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)Rlim))SS12
C4 N005 N004 2.2n
R14 N022 0 31.6K
R5 N009 0 23.2K
V2 N013 0 PULSE(0 5 0 10n 10n 833n 1.666u)
R1 IN N002 10K
R4 OUT N009 34.8K
C3 N007 0 1
C1 N001 N003 0.1
Rload OUT 0 2
R10 N021 0 100K
C5 OUT N009 47p
M2 N016 N017 0 0 BSC080N03MS
L2 N016 OUT 2.2
R8 N007 N008 10K
C8 N018 0 1
C7 OUT 0 8.12
R2 N002 0 10K
R16 N018 N019 10K
R6 N011 0 22K
R3 N004 0 1.82K
R13 N020 0 22K
XU1 N022 N014 N018 N002 IN N015 N016 N017 N009 N005 N019 0 N020 MP_05 N021 ADP505x_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)Rlim))SS12
R7 N012 0 31.6K
C6 N015 N016 0.1
R9 N018 N021 600k
V1 IN 0 12
M1 N003 N006 0 0 BSC080N03MS
L1 N003 OUT 2.2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m startup
.lib ADP505x_chan1_2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 1460
WIRE -336 -96 -432 -96
WIRE -192 -96 -336 -96
WIRE 80 -96 -192 -96
WIRE 448 -96 368 -96
WIRE -432 -80 -432 -96
WIRE -336 -80 -336 -96
WIRE 448 -80 448 -96
WIRE -336 16 -336 0
WIRE -224 16 -336 16
WIRE 80 16 -224 16
WIRE 448 16 448 -16
WIRE 448 16 368 16
WIRE 512 16 448 16
WIRE 640 16 592 16
WIRE 720 16 640 16
WIRE 848 16 720 16
WIRE 928 16 848 16
WIRE 976 16 928 16
WIRE -432 32 -432 0
WIRE -336 32 -336 16
WIRE 848 32 848 16
WIRE 448 48 448 16
WIRE 720 48 720 16
WIRE 640 112 640 16
WIRE 848 112 848 96
WIRE 976 112 976 96
WIRE -336 128 -336 112
WIRE -96 128 -112 128
WIRE 0 128 -16 128
WIRE 80 128 64 128
WIRE 400 128 368 128
WIRE 448 160 448 144
WIRE 64 192 64 128
WIRE 64 192 -128 192
WIRE -32 240 -64 240
WIRE 80 240 48 240
WIRE 640 240 640 176
WIRE 640 240 368 240
WIRE 720 240 720 128
WIRE 720 240 640 240
WIRE 720 256 720 240
WIRE 80 352 -496 352
WIRE 384 352 368 352
WIRE 480 352 464 352
WIRE 720 352 720 336
WIRE -64 416 -64 240
WIRE 80 416 -64 416
WIRE -16 464 -32 464
WIRE 80 464 64 464
WIRE 400 464 368 464
WIRE 448 464 400 464
WIRE 448 480 448 464
WIRE 224 512 224 496
WIRE -64 544 -64 416
WIRE 400 544 400 464
WIRE 400 544 -64 544
WIRE 448 560 448 544
WIRE -496 592 -496 352
WIRE -496 592 -656 592
WIRE -896 608 -1040 608
WIRE -720 608 -816 608
WIRE -496 624 -656 624
WIRE -720 672 -720 640
WIRE -192 720 -192 -96
WIRE 80 720 -192 720
WIRE 448 720 368 720
WIRE 448 736 448 720
WIRE -224 832 -224 16
WIRE 80 832 -224 832
WIRE 448 832 448 800
WIRE 448 832 368 832
WIRE 512 832 448 832
WIRE 848 832 592 832
WIRE 928 832 928 16
WIRE 928 832 848 832
WIRE 848 848 848 832
WIRE 448 864 448 832
WIRE 848 928 848 912
WIRE -128 944 -128 192
WIRE 80 944 -128 944
WIRE 400 944 368 944
WIRE 448 976 448 960
WIRE -32 1056 -64 1056
WIRE 80 1056 48 1056
WIRE 640 1056 640 240
WIRE 640 1056 368 1056
WIRE -496 1168 -496 624
WIRE 80 1168 -496 1168
WIRE 384 1168 368 1168
WIRE 480 1168 464 1168
WIRE -64 1216 -64 1056
WIRE -64 1216 -320 1216
WIRE -320 1232 -320 1216
WIRE 80 1232 -144 1232
WIRE -16 1280 -32 1280
WIRE 80 1280 64 1280
WIRE 400 1280 368 1280
WIRE 448 1280 400 1280
WIRE 448 1296 448 1280
WIRE -320 1328 -320 1312
WIRE -144 1328 -144 1232
WIRE -144 1328 -320 1328
WIRE 224 1328 224 1312
WIRE -320 1344 -320 1328
WIRE -64 1360 -64 1216
WIRE 400 1360 400 1280
WIRE 400 1360 -64 1360
WIRE 448 1376 448 1360
WIRE -320 1440 -320 1424
SYMBOL res 0 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL ind 496 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res 704 240 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL res 368 368 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 22K
SYMBOL res -48 1072 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R16
SYMATTR Value 10K
SYMBOL res 704 32 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL cap 624 112 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL res 368 1184 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R13
SYMATTR Value 22K
SYMBOL nmos 400 864 R0
SYMATTR InstName M2
SYMATTR Value BSC080N03MS
SYMBOL cap 432 480 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 64 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL res -336 1328 R0
SYMATTR InstName R10
SYMATTR Value 100K
SYMBOL Digital\\schmitt -720 544 R0
WINDOW 0 23 17 Left 2
WINDOW 123 26 118 Left 2
WINDOW 39 26 146 Left 2
SYMATTR InstName A1
SYMATTR Value2 Vt=0.5 vh=8m
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR Description Behavioral Schmitt-Triggered inverter
SYMATTR Type schmtinv
SYMBOL ADP5053_chan1_2 224 192 R0
SYMATTR InstName U2
SYMBOL cap 432 736 R0
SYMATTR InstName C6
SYMATTR Value 0.1
SYMBOL res -48 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL VOLTAGE -432 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 832 32 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C2
SYMATTR Value 8.12
SYMBOL ind 496 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 2.2
SYMBOL res -352 -96 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 960 0 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL res -352 16 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL cap 432 1296 R0
SYMATTR InstName C8
SYMATTR Value 1
SYMBOL res 80 1264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 31.6K
SYMBOL voltage -800 608 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 35 139 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10n 10n 833n 1.666u)
SYMBOL res -336 1216 R0
SYMATTR InstName R9
SYMATTR Value 600k
SYMBOL cap 432 -80 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL ADP5053_chan1_2 224 1008 R0
SYMATTR InstName U1
SYMBOL res 80 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL nmos 400 48 R0
SYMATTR InstName M1
SYMATTR Value BSC080N03MS
SYMBOL cap 832 848 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C7
SYMATTR Value 8.12
FLAG 224 512 0
FLAG -336 128 0
FLAG 448 160 0
FLAG 848 112 0
FLAG 720 352 0
FLAG 480 352 0
FLAG 448 560 0
FLAG -32 464 0
FLAG -112 128 0
FLAG 848 16 OUT
FLAG 976 112 0
FLAG -432 32 0
FLAG -432 -96 IN
FLAG 224 1328 0
FLAG 448 976 0
FLAG 848 928 0
FLAG 480 1168 0
FLAG 448 1376 0
FLAG -32 1280 0
FLAG -720 672 0
FLAG -1040 608 0
FLAG -320 1440 0
TEXT 656 1328 Left 2 !.tran 3m startup
TEXT -1336 312 Left 2 ;The schematic simulates channels 1 and 2 in parallel.\nNotice how the SS12, COMP, and FB pins are configured\nThis is DIFFERENT than the real world.  Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
TEXT 384 416 Left 2 ;Rlim is the resistor generally placed on DL pin to set current limit