Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\1a6935f954fd_Simulazione_LT1719_condizionata.asc
* Generated by LTspice 26.0.1 for Windows.
* Vs = Tensione di soglia
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT1719.asy)
R2 Vsig 0 47
Vs Vs 0 0.1
C1 Vin 0 50p
V1 3V3 0 3.3
D1 Vsig Vin RB511VM-30
V2 Vsig 0 PULSE(0 {Vmax} 0 1n 1n 1n 0 1)
R3 Vin 0 180
XU1 3V3 Vin Vs 0 0 0 OUT 3V3 LT1719 ;pnba V+)In+)In-)V-)GND)SHDN)OUT)VS+
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 50n
.step param Vmax 500m 2 500m
.lib opamp.sub
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 -256 -64 -304
WIRE 160 -256 160 -304
WIRE -64 -144 -64 -176
WIRE 160 -144 160 -176
WIRE -672 96 -704 96
WIRE -608 96 -672 96
WIRE -512 96 -608 96
WIRE -368 96 -448 96
WIRE -320 96 -368 96
WIRE -272 96 -320 96
WIRE 176 112 176 80
WIRE 192 112 176 112
WIRE 128 128 96 128
WIRE 176 128 176 112
WIRE 192 128 192 112
WIRE -704 144 -704 96
WIRE -608 144 -608 96
WIRE -368 144 -368 96
WIRE -272 144 -272 96
WIRE 128 144 128 128
WIRE 144 144 128 144
WIRE 304 160 208 160
WIRE 144 176 96 176
WIRE 160 208 160 192
WIRE 176 208 176 192
WIRE 176 208 160 208
WIRE 192 208 192 192
WIRE 192 208 176 208
WIRE 176 224 176 208
WIRE -704 256 -704 224
WIRE -656 256 -704 256
WIRE -608 256 -608 224
WIRE -608 256 -656 256
WIRE -368 256 -368 224
WIRE -304 256 -368 256
WIRE -272 256 -272 208
WIRE -272 256 -304 256
WIRE -656 288 -656 256
WIRE -304 288 -304 256
SYMBOL voltage -704 128 R0
WINDOW 3 -131 -131 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 {Vmax} 0 1n 1n 1n 0 1)
SYMATTR InstName V2
SYMBOL res -624 128 R0
SYMATTR InstName R2
SYMATTR Value 47
SYMBOL Comparators\\LT1719 176 96 R0
SYMATTR InstName U1
SYMBOL schottky -512 112 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RB511VM-30
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage -64 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vs
SYMATTR Value 0.1
SYMBOL res -384 128 R0
SYMATTR InstName R3
SYMATTR Value 180
SYMBOL voltage 160 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap -288 144 R0
SYMATTR InstName C1
SYMATTR Value 50p
FLAG 176 224 0
FLAG 160 -144 0
FLAG 160 -304 3V3
FLAG 176 80 3V3
FLAG 304 160 OUT
FLAG -656 288 0
FLAG -672 96 Vsig
FLAG 96 176 Vin
FLAG -64 -144 0
FLAG -64 -304 Vs
FLAG 96 128 Vs
FLAG -304 288 0
FLAG -320 96 Vin
TEXT -824 -208 Left 2 !.tran 50n
TEXT -200 -88 Left 2 ;Vs = Tensione di soglia
TEXT -824 -152 Left 2 !.step param Vmax 500m 2 500m
TEXT -824 -104 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7102-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7102-3.3.asy)
Rload OUT 0 16
R1 OUT N001 100k
C1 OUT 0 2.2 Rser=1.5m
XU1 IN OUT IN N001 OUT 0 ADP7102 Vref=3.3 ;pnba Vin)Sense)EN)PG)Vout)GND
V1 IN 0 4.3
.tran 3m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 16
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 4.3
SYMBOL ADP7102-3.3 224 128 R0
SYMATTR InstName U1
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1517-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1517-3.3.asy)
C1 OUT 0 6.8
Rload OUT 0 500
C2 N002 N001 .1
V1 IN 0 3
XU1 IN 0 OUT N002 N001 LTC1517-3.3 ;pnba Vin)GND)Vout)Cap+)Cap-
.tran 2m startup
.lib LTC1517-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3300 2376
WIRE 2832 1872 2784 1872
WIRE 2944 1872 2896 1872
WIRE 2784 1936 2784 1872
WIRE 2944 1936 2944 1872
WIRE 2736 2048 2624 2048
WIRE 3056 2048 2992 2048
WIRE 3152 2048 3056 2048
WIRE 2624 2064 2624 2048
WIRE 3056 2064 3056 2048
WIRE 3152 2064 3152 2048
WIRE 2624 2160 2624 2144
WIRE 3056 2160 3056 2128
WIRE 3152 2160 3152 2144
WIRE 2864 2192 2864 2160
SYMBOL cap 3040 2064 R0
SYMATTR InstName C1
SYMATTR Value 6.8
SYMBOL VOLTAGE 2624 2048 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL PowerProducts\\LTC1517-3.3 2864 2048 R0
SYMATTR InstName U1
SYMBOL cap 2896 1856 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL RES 3136 2048 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG 3056 2160 0
FLAG 2864 2192 0
FLAG 2624 2160 0
FLAG 3152 2160 0
FLAG 3152 2048 OUT
FLAG 2624 2048 IN
TEXT 3000 2232 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\fb573c8c95a3_steptest.asc
* Generated by LTspice 26.0.1 for Windows.
D1 V1 R 1N4148
R2 R 0 {R2}
R1 R 0 {R1}
V1 V1 0 {Vcc}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.op
.param Vcc=5 R1=1k R2=1k
.meas vd1 param V(V1)-V(R)
.meas pd param vd1*I(D1)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 64 112 64
WIRE 272 64 224 64
WIRE 384 64 272 64
WIRE 112 112 112 64
WIRE 272 112 272 64
WIRE 384 112 384 64
WIRE 112 224 112 192
WIRE 272 224 272 192
WIRE 272 224 112 224
WIRE 384 224 384 192
WIRE 384 224 272 224
WIRE 112 240 112 224
SYMBOL diode 160 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 368 96 R0
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL voltage 112 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vcc}
SYMBOL res 256 96 R0
SYMATTR InstName R1
SYMATTR Value {R1}
FLAG 112 240 0
FLAG 112 64 V1
FLAG 272 64 R
TEXT 144 296 Left 2 !.op
TEXT 144 264 Left 2 !.param Vcc=5 R1=1k R2=1k
TEXT 536 80 Left 2 !.meas vd1 param V(V1)-V(R)
TEXT 536 120 Left 2 !.meas pd param vd1*I(D1)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8625S.asc
* Generated by LTspice 26.0.1 for Windows.
* 2MHz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8625S.asy)
C2 OUT 0 470 Rser=5m
L1 SW OUT 1 Rser=6m
R2 PGFB 0 49.9k
R1 N001 0 47k
R5 SET 0 33.2k
V1 IN 0 12
Rload OUT 0 0.4
R4 N002 N003 499
XU1 SW N004 0 CLKout IN NC_01 IN IN N004 N004 SET N003 OUT PGFB N001 PG LT8625S ;pnba SW)Sync/Mode)GND)CLKout)PVin)BST)SVin)EN/UVLO)INTVcc)PHMode)SET)Vc)OUTS)PGFB)RT)PG
R3 OUT PGFB 280k
C3 N002 0 2n
C1 SET 0 1
R6 OUT PG 100k
.tran 1.5m startup
.lib LT8625S.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1080 680
WIRE 96 -128 -64 -128
WIRE 272 -128 96 -128
WIRE -64 -112 -64 -128
WIRE 272 -112 272 -128
WIRE 96 -64 96 -128
WIRE 128 -64 96 -64
WIRE -64 -16 -64 -32
WIRE 96 32 96 -64
WIRE 128 32 96 32
WIRE 448 32 416 32
WIRE 512 32 448 32
WIRE 688 32 592 32
WIRE -32 128 -64 128
WIRE 128 128 48 128
WIRE 448 128 416 128
WIRE 512 128 448 128
WIRE 688 128 688 32
WIRE 688 128 592 128
WIRE 768 128 688 128
WIRE 880 128 768 128
WIRE 976 128 880 128
WIRE 976 144 976 128
WIRE 880 160 880 128
WIRE 768 176 768 128
WIRE -80 224 -96 224
WIRE 16 224 -16 224
WIRE 128 224 96 224
WIRE 688 224 688 128
WIRE 688 224 416 224
WIRE 880 240 880 224
WIRE 976 240 976 224
WIRE 128 320 96 320
WIRE 464 320 416 320
WIRE 768 320 768 256
WIRE 768 320 464 320
WIRE 768 336 768 320
WIRE 96 416 96 320
WIRE 128 416 96 416
WIRE 448 416 416 416
WIRE 592 416 448 416
WIRE 672 416 592 416
WIRE 672 432 672 416
WIRE 768 432 768 416
WIRE 592 448 592 416
WIRE 96 512 96 416
WIRE 128 512 96 512
WIRE 448 512 416 512
WIRE 592 528 592 512
WIRE 672 528 672 512
WIRE 272 592 272 576
SYMBOL voltage -64 -128 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 752 320 R0
SYMATTR InstName R2
SYMATTR Value 49.9k
SYMBOL res 0 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 499
SYMBOL res 960 128 R0
SYMATTR InstName Rload
SYMATTR Value 0.4
SYMBOL cap -16 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 2n
SYMBOL res 752 160 R0
SYMATTR InstName R3
SYMATTR Value 280k
SYMBOL res 656 416 R0
SYMATTR InstName R5
SYMATTR Value 33.2k
SYMBOL cap 864 160 R0
SYMATTR InstName C2
SYMATTR Value 470
SYMATTR SpiceLine Rser=5m
SYMBOL LT8625S 272 192 R0
SYMATTR InstName U1
SYMBOL res 64 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 47k
SYMBOL res 608 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 100k
SYMBOL cap 576 448 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ind 496 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=6m
FLAG -64 -16 0
FLAG -64 128 0
FLAG 272 592 0
FLAG 768 432 0
FLAG 976 240 0
FLAG -96 224 0
FLAG 976 128 OUT
FLAG -64 -128 IN
FLAG 672 528 0
FLAG 592 528 0
FLAG 880 240 0
FLAG 448 512 CLKout
FLAG 448 32 PG
FLAG 448 128 SW
FLAG 464 320 PGFB
FLAG 448 416 SET
TEXT 728 552 Left 2 !.tran 1.5m startup
TEXT 48 104 Left 2 ;2MHz
* Z:\home\khalils\Downloads\files\data\raw_asc\126d185ee445_Simulation_Bonus.asc
* Generated by LTspice 26.0.1 for Windows.
M3 N004 N003 N005 N005 Mosfet3
M4 N001 N002 N004 N004 Mosfet4
V2 N005 0 -15
M1 N002 N002 N003 N003 Mosfet1
R1 N001 N002 5.3k
M2 N003 N003 N005 N005 Mosfet2
V1 N001 0 15
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model Mosfet1 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
.model Mosfet2 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
.model Mosfet3 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
.model Mosfet4 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1464 868
WIRE 480 -192 432 -192
WIRE 432 -176 432 -192
WIRE 480 -176 480 -192
WIRE 432 -64 432 -96
WIRE 432 -64 160 -64
WIRE 704 -64 432 -64
WIRE 160 112 160 -64
WIRE 160 224 160 192
WIRE 432 224 160 224
WIRE 160 272 160 224
WIRE 704 272 704 -64
WIRE 160 320 96 320
WIRE 768 320 704 320
WIRE 432 352 432 224
WIRE 432 352 208 352
WIRE 656 352 432 352
WIRE 96 384 96 320
WIRE 160 384 160 368
WIRE 160 384 96 384
WIRE 704 384 704 368
WIRE 768 384 768 320
WIRE 768 384 704 384
WIRE 160 432 160 384
WIRE 432 432 160 432
WIRE 160 464 160 432
WIRE 704 464 704 384
WIRE 160 512 96 512
WIRE 768 512 704 512
WIRE 432 544 432 432
WIRE 432 544 208 544
WIRE 656 544 432 544
WIRE 96 576 96 512
WIRE 160 576 160 560
WIRE 160 576 96 576
WIRE 704 576 704 560
WIRE 768 576 768 512
WIRE 768 576 704 576
WIRE 160 624 160 576
WIRE 432 624 160 624
WIRE 704 624 704 576
WIRE 704 624 432 624
WIRE 432 672 432 624
WIRE 432 816 432 752
SYMBOL nmos4 208 272 M0
SYMATTR InstName M1
SYMATTR Value Mosfet1
SYMBOL nmos4 656 464 R0
SYMATTR InstName M3
SYMATTR Value Mosfet3
SYMBOL voltage 432 -80 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL nmos4 656 272 R0
SYMATTR InstName M4
SYMATTR Value Mosfet4
SYMBOL voltage 432 656 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 144 96 R0
SYMATTR InstName R1
SYMATTR Value 5.3k
SYMBOL nmos4 208 464 M0
SYMATTR InstName M2
SYMATTR Value Mosfet2
FLAG 432 816 0
FLAG 480 -176 0
TEXT 824 296 Left 2 !.model Mosfet1 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
TEXT 824 320 Left 2 !.model Mosfet2 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
TEXT 824 344 Left 2 !.model Mosfet3 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
TEXT 824 368 Left 2 !.model Mosfet4 NMOS(Kp = 0.02, Vto= 1, Lambda = 0)
TEXT 824 280 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\8f05eda526ea_inverter.asc
* Generated by LTspice 26.0.1 for Windows.
* CMOS INVERTER
M2 Y A 0 0 NMOS
M1 Y A vdd vdd PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 64 256 48
WIRE 288 64 256 64
WIRE 208 80 176 80
WIRE 288 112 288 64
WIRE 288 112 256 112
WIRE 176 160 176 80
WIRE 176 160 160 160
WIRE 288 160 256 160
WIRE 288 208 256 208
WIRE 176 240 176 160
WIRE 208 240 176 240
WIRE 288 256 288 208
WIRE 288 256 256 256
WIRE 256 272 256 256
IOPIN 256 48 In
IOPIN 160 160 In
IOPIN 288 160 Out
IOPIN 256 272 In
SYMBOL nmos4 208 160 R0
SYMATTR InstName M2
SYMBOL pmos4 208 160 M180
SYMATTR InstName M1
FLAG 256 48 vdd
FLAG 160 160 A
FLAG 288 160 Y
FLAG 256 272 gnd
TEXT 48 -80 Left 2 ;CMOS INVERTER
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5423.asc
* Generated by LTspice 26.0.1 for Windows.
V1 0 N007 24
V2 N001 0 24
R1 N006 0 1k
R2 N002 0 1k
R3 0 N005 1k
R4 OUT N003 1k
V4 IN 0 PULSE(1 2 100u 1u 1u 1m)
R5 N004 OUT 10
R6 OUT 0 1k
XU1 N001 N001 0 MP_01 MP_02 MP_03 N006 NC_04 N002 N002 MP_05 N007 N005 MP_06 N003 N004 IN AD5423 RANGE = 0, OVRNG_EN = 0, NEG_OFFSET_EN = 0 SR_EN = 0, SR_STEP = 0, SR_CLOCK = 0 VIOUT_PULLDOWN_EN = 0, HART_EN = 0 ;pnba AVDD1)AVDD2)GND))))REFOUT)CHART)VLDO)VLOGIC))AVSS)-VSENSE))+VSENSE)VIOUT)INPUT
.tran 200u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5423.asy)
.lib AD5423.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2016 1328
WIRE -96 -320 -96 -384
WIRE 160 -320 160 -384
WIRE -96 -160 -96 -240
WIRE 32 -160 -96 -160
WIRE 160 -160 160 -240
WIRE 272 -160 160 -160
WIRE -96 -96 -96 -160
WIRE 32 -96 32 -160
WIRE 160 -96 160 -160
WIRE 272 -96 272 -160
WIRE 528 96 464 96
WIRE 816 96 608 96
WIRE -176 224 -512 224
WIRE 576 224 528 224
WIRE 816 224 816 96
WIRE 816 224 656 224
WIRE 864 224 816 224
WIRE 816 240 816 224
WIRE -512 288 -512 224
WIRE 544 352 464 352
WIRE 816 352 816 320
WIRE 816 352 624 352
WIRE -512 432 -512 368
WIRE 816 432 816 352
WIRE 464 464 416 464
WIRE 464 528 464 464
WIRE -16 640 -16 560
WIRE 208 640 208 560
WIRE 464 656 464 608
WIRE -16 800 -16 720
FLAG 208 640 0
FLAG -16 800 0
FLAG -96 -384 0
FLAG 464 656 0
FLAG 160 -384 0
FLAG -512 432 0
FLAG 816 432 0
FLAG -512 224 IN
FLAG 864 224 OUT
SYMBOL voltage -16 736 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL voltage -96 -224 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 24
SYMBOL res 448 512 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 144 -224 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 640 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 624 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage -512 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(1 2 100u 1u 1u 1m)
SYMBOL res 560 208 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL res 800 224 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL AD5423 80 224 R0
SYMATTR InstName U1
TEXT 504 -64 Left 2 !.tran 200u
* Z:\home\khalils\Downloads\files\data\raw_asc\c6f172b45764_Assignment_3a__v_.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Half Wave Rectifier Circuit (with 10microF Capacitor) (Ideal)
R1 N002 0 1000
V1 N001 0 SINE(0 311 50) Rser=0.001
C1 N002 0 0.00001
D1 N001 N002 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 64 80 64
WIRE 352 64 256 64
WIRE 464 64 352 64
WIRE 80 112 80 64
WIRE 352 112 352 64
WIRE 464 128 464 64
WIRE 80 240 80 192
WIRE 176 240 80 240
WIRE 352 240 352 192
WIRE 352 240 176 240
WIRE 464 240 464 192
WIRE 464 240 352 240
WIRE 176 272 176 240
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
SYMBOL diode 192 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL cap 448 128 R0
SYMATTR InstName C1
SYMATTR Value 0.00001
FLAG 176 272 0
TEXT 16 272 Left 2 !.tran 0.05
TEXT 264 8 Center 2 ;Positive Half Wave Rectifier Circuit (with 10microF Capacitor) (Ideal)
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5685R.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc I1 0 40m 1m
* .ac oct 100 1u 1G
* Gain parameter can be 1 or 2
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5685R.asy)
XU2 vDAC Vdd 0 vOUT AD5685R Gain=2 ;pnba Vdac)Vdd)GND)Vout
CLOAD vOUT 0 10n
V1 Vdd 0 5
I1 0 0 100 AC 1
Vdac vDAC 0 PWL(0 0.625 10u 0.625 +1u 1.875)
Vdac1 NC_01 0 1.25
.tran 200u
.lib AD5685R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -240 -208 -240 -240
WIRE -240 -80 -240 -128
WIRE -240 -32 -240 -80
WIRE -800 112 -1008 112
WIRE -528 112 -800 112
WIRE -368 112 -528 112
WIRE 192 112 0 112
WIRE 272 112 192 112
WIRE 464 112 272 112
WIRE -800 144 -800 112
WIRE 272 160 272 112
WIRE -1008 256 -1008 224
WIRE -800 256 -800 224
WIRE 272 256 272 224
WIRE 464 256 464 240
WIRE 464 256 272 256
WIRE 272 272 272 256
WIRE -240 288 -240 256
SYMBOL cap 256 160 R0
SYMATTR InstName CLOAD
SYMATTR Value 10n
SYMBOL voltage -1008 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac1
SYMATTR Value 1.25
SYMBOL AD5685R -208 112 R0
SYMATTR InstName U2
SYMBOL current 464 160 R0
WINDOW 123 24 108 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName I1
SYMATTR Value 100
SYMBOL voltage -800 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac
SYMATTR Value PWL(0 0.625 10u 0.625 +1u 1.875)
SYMBOL voltage -240 -112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 192 112 vOUT
FLAG -800 256 0
FLAG -528 112 vDAC
FLAG -240 -240 0
FLAG -240 288 0
FLAG 272 272 0
FLAG -240 -80 Vdd
FLAG -1008 256 0
FLAG 464 160 0
TEXT -160 312 Left 2 !.tran 200u
TEXT -160 360 Left 2 ;.dc I1 0 40m 1m
TEXT -160 408 Left 2 ;.ac oct 100 1u 1G
TEXT -632 368 Left 2 ;Gain parameter can be 1 or 2
* Z:\home\khalils\Downloads\files\data\raw_asc\d4bcf01d8c8f_Draft100.asc
* Generated by LTspice 26.0.1 for Windows.
* plus
* input 0-3v3 square wave input.\nfrom mcu/ oscillator etc
* ie. integrator
* https://sound-au.com/articles/cmpd-vs-darl.htm
* Library below included based on ModelFile attribute of instance XU1, XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1006.asy)
C1 P001 N003 50n
R1 P001 VOUT 2k
VIN1 N001 0 PULSE(-1 1 0 100n 100n 0.2ms 0.4ms 14)
XU1 0 N003 VCC VEE VOUT LT1006 ;pnba In+)In-)V+)V-)OUT
XU3 VOUT N001 VCC VEE N002 LT1006 ;pnba In+)In-)V+)V-)OUT
R14 N002 N003 10k
V2 0 VEE 8
V1 VCC 0 8
.tran 6ms
.include standard.bjt
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3300 1956
WIRE 544 -288 464 -288
WIRE 832 192 336 192
WIRE 368 272 80 272
WIRE 528 288 432 288
WIRE 624 288 608 288
WIRE 688 288 624 288
WIRE 832 288 832 192
WIRE 864 288 832 288
WIRE 336 304 336 192
WIRE 368 304 336 304
WIRE 624 400 624 288
WIRE 656 400 624 400
WIRE 80 416 80 272
WIRE 832 416 832 288
WIRE 832 416 720 416
WIRE 1008 416 832 416
WIRE 656 432 624 432
WIRE 624 480 624 432
SYMBOL voltage 464 -384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 42 41 Left 2
SYMATTR Value 8
SYMATTR InstName V1
SYMBOL voltage 80 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -271 -43 Left 2
WINDOW 0 -23 -10 Left 2
SYMATTR Value PULSE(-1 1 0 100n 100n 0.2ms 0.4ms 14)
SYMATTR InstName VIN1
SYMBOL OpAmps\\LT1006 688 352 R0
SYMATTR InstName U1
SYMBOL OpAmps\\LT1006 400 224 R0
SYMATTR InstName U3
SYMBOL voltage 464 -304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 42 41 Left 2
SYMATTR Value 8
SYMATTR InstName V2
SYMBOL cap 752 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 50n
SYMBOL res 736 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 2k
SYMBOL res 512 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R14
SYMATTR Value 10k
FLAG 464 -368 VCC
FLAG 80 496 0
FLAG 544 -288 0
FLAG 624 480 0
FLAG 688 384 VCC
FLAG 400 256 VCC
FLAG 864 288 VOUT
FLAG 464 -208 VEE
FLAG 688 448 VEE
FLAG 400 320 VEE
TEXT 688 -392 Left 2 !.tran 6ms
TEXT 544 392 Left 2 ;plus
TEXT 384 768 Left 2 ;input 0-3v3 square wave input.\nfrom mcu/ oscillator etc
TEXT 240 -88 Left 2 !.include standard.bjt
TEXT 520 168 Left 2 ;ie. integrator
TEXT 400 848 Left 2 ;https://sound-au.com/articles/cmpd-vs-darl.htm
* Z:\home\khalils\Downloads\files\data\raw_asc\4ae271d1741b_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
VCE N001 0 0
Ib 0 N002 0
Q1 N001 N002 0 0 2N2222
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc VCE 0 5 0.01 Ib 0uA 50uA 10uA
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 528 32 208 32
WIRE 144 80 -48 80
WIRE 528 128 528 32
WIRE -48 192 -48 80
WIRE 208 272 208 128
WIRE 208 272 -48 272
WIRE 528 272 528 208
WIRE 528 272 208 272
WIRE 208 336 208 272
SYMBOL voltage 528 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCE
SYMATTR Value 0
SYMBOL current -48 272 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Ib
SYMATTR Value 0
SYMBOL npn 144 32 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
FLAG 208 336 0
TEXT -98 360 Left 2 !.dc VCE 0 5 0.01 Ib 0uA 50uA 10uA
* Z:\home\khalils\Downloads\files\data\raw_asc\6eb51c736fd0_Diode-Clipper-6.asc
* Generated by LTspice 26.0.1 for Windows.
D1 b 0 VS-E5TH1506
R1 b a 10
Rload 0 b 5k
V1 a 0 SINE(0 24V 100kHz)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 50u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 144 -96 144
WIRE 208 144 112 144
WIRE 336 144 208 144
WIRE 480 144 336 144
WIRE 480 208 480 144
WIRE -96 224 -96 144
WIRE 208 224 208 144
WIRE -96 368 -96 304
WIRE 48 368 -96 368
WIRE 208 368 208 288
WIRE 208 368 48 368
WIRE 480 368 480 288
WIRE 480 368 208 368
WIRE 48 400 48 368
SYMBOL Misc\\EuropeanResistor 496 304 R180
WINDOW 0 -66 73 Left 2
WINDOW 3 -47 36 Left 2
SYMATTR InstName Rload
SYMATTR Value 5k
SYMBOL Misc\\EuropeanResistor 128 128 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL diode 192 224 R0
WINDOW 3 -53 170 Left 2
WINDOW 0 32 2 Left 2
SYMATTR Value VS-E5TH1506
SYMATTR InstName D1
SYMBOL Misc\\signal -96 208 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 38 63 Left 2
SYMATTR Value SINE(0 24V 100kHz)
SYMATTR InstName V1
FLAG -96 144 a
FLAG 336 144 b
FLAG 48 400 0
TEXT -136 408 Left 2 !.tran 50u