* Z:\tmp\asc_dec_bjh7r6w2\013807eeb9de_pluto-a_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
R2 bitline1 N006 {mc(bitline_R, process_var)}
M9 ACT N005 VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
R3 bl_ival bl_ival 1m
M7 N001 N002 N003 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Veq1 Eq1 0 PULSE({core_voltage*1.2} {core_voltage*1.2} 0 0 0 0)
CBL_starting_value_cap bl_ival 0 10f V=1
VDD_source1 PV 0 {plate_voltage}
M5 bitline0 Eq2 VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2520
WIRE 800 -1536 768 -1536
WIRE 864 -1536 800 -1536
WIRE 768 -1440 768 -1456
WIRE 864 -1440 864 -1536
WIRE 864 -1440 768 -1440
WIRE 768 -1392 624 -1392
WIRE 624 -1360 624 -1392
WIRE 576 -1280 304 -1280
WIRE 624 -1232 624 -1264
WIRE 624 -1232 384 -1232
WIRE 384 -1152 384 -1232
WIRE -3504 -1104 -3504 -1120
WIRE -3504 -1008 -3504 -1024
WIRE 768 -848 768 -1392
WIRE -208 -624 -208 -656
WIRE -208 -512 -208 -544
WIRE 768 -496 768 -656
WIRE 640 -464 432 -464
WIRE 832 -384 688 -384
WIRE 912 -384 832 -384
WIRE 1040 -384 912 -384
WIRE 832 -352 832 -384
WIRE 1040 -352 1040 -384
WIRE 912 -336 880 -336
WIRE 992 -336 960 -336
WIRE 1312 -256 1120 -256
WIRE 768 -240 768 -416
WIRE 832 -240 832 -256
WIRE 832 -240 768 -240
WIRE 912 -240 960 -336
WIRE 912 -240 832 -240
WIRE 960 -240 912 -336
WIRE 1040 -240 1040 -256
WIRE 1040 -240 960 -240
WIRE 1120 -240 1120 -256
WIRE 1120 -240 1040 -240
WIRE 768 -144 768 -240
WIRE 912 -144 768 -144
WIRE 1120 -144 1120 -240
WIRE 1120 -144 1008 -144
WIRE 640 -96 608 -96
WIRE 880 -96 640 -96
WIRE 928 -96 880 -96
WIRE 1056 -96 928 -96
WIRE 1296 -96 1056 -96
WIRE 880 -80 880 -96
WIRE 1056 -80 1056 -96
WIRE 768 -48 768 -144
WIRE 768 -32 768 -48
WIRE 800 -32 768 -32
WIRE 944 -32 896 -32
WIRE 976 -32 944 -32
WIRE 1120 -32 1120 -144
WIRE 1120 -32 1072 -32
WIRE 1312 -32 1312 -256
WIRE 1120 -16 1120 -32
WIRE 944 16 944 -32
WIRE 944 32 944 16
WIRE 768 80 768 -32
WIRE 832 80 768 80
WIRE 912 80 832 80
WIRE 1040 80 976 80
WIRE 1120 80 1120 -16
WIRE 1120 80 1040 80
WIRE 832 96 832 80
WIRE 1312 128 1312 48
WIRE 1360 128 1312 128
WIRE 912 176 976 80
WIRE 976 176 912 80
WIRE 1360 176 1360 128
WIRE 1312 400 1312 128
WIRE 1312 400 1200 400
WIRE 1200 432 1200 400
WIRE 1088 544 880 544
WIRE 1152 544 1152 512
WIRE 1152 544 1088 544
WIRE 1200 576 1200 528
WIRE 1200 592 1200 576
WIRE 1312 704 1312 400
SYMBOL pmos4 992 -256 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL res 1296 -48 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL pmos4 640 -384 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL res 752 -1552 R0
SYMATTR InstName R3
SYMATTR Value 1m
SYMBOL nmos4 576 -1360 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1184 592 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -3504 -1120 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq1
SYMATTR Value PULSE({core_voltage*1.2} {core_voltage*1.2} 0 0 0 0)
SYMBOL cap 864 -1520 R270
WINDOW 3 -2 50 VBottom 2
WINDOW 0 37 156 VTop 2
SYMATTR Value 10f
SYMATTR InstName BL_starting_value_cap
SYMATTR SpiceLine V=1
SYMBOL voltage -208 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 800 -80 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
FLAG -3504 -1008 0
FLAG -3504 -1120 Eq1
FLAG 960 -144 0
FLAG 848 -32 0
FLAG 640 -96 Eq2
FLAG 944 16 VDDby2
FLAG 768 -48 bitline0
FLAG 1120 -16 bitline1
FLAG 624 -1312 0
FLAG 1200 480 0
FLAG 1200 656 0
FLAG 1200 576 mb3
FLAG 1088 544 ra3
FLAG 688 -432 VDD
FLAG 1040 -304 VDD
FLAG 832 -304 VDD
FLAG 688 -480 VDD
FLAG 912 -384 ACT
FLAG -208 -512 0
FLAG -208 -656 PV
FLAG 928 -1536 0
FLAG 800 -1536 bl_ival