* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4361-2.asc
* Generated by LTspice 26.0.1 for Windows.
* To model avalanche behavior of NFET
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4361-2.asy)
V2 N003 0 PWL(0u 0 100m 0 +1u 20 150m 20 +10u 0 200m 0 +1u -20 250m -20 +10u 0 400m 0 +1u 5 800m 5 +1u 20 900m 20 +10u 5)
R1 N005 N001 25m
R2 N002 0 10
V1 N010 0 5
MQ1 N004 N008 N005 N005 FDS4953
S1 0 N002 N006 0 SHORT
D1 N002 N001 Davalanche
XU1 N008 N005 N001 N007 0 N002 N009 0 LTC4361-2 ;pnba GP)In)Sense)Gate)_On)Out)_Pwrgd)Gnd
L1 N003 N004 1 Rser=150m
MQ2 N001 N007 N002 N002 Si4892DY
V3 N006 0 PWL(0us 0V 1200m 0 +5n 1 1201m 1 +5n 0)
R3 N010 N009 1K
C1 N002 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1500m startup
.model SHORT SW(Ron=1 Roff=1T Vt=0.5 Vh=-0.4)
.model Davalanche D(Vfwd=0.7 Vrev=32 Ron=0.1 Rrev=0.1 epsilon=.1 revepsilon=.1)
.lib LTC4361-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 9052 3716
WIRE 5744 -1584 5680 -1584
WIRE 5856 -1584 5808 -1584
WIRE 5184 -1488 4704 -1488
WIRE 5344 -1488 5264 -1488
WIRE 5488 -1488 5440 -1488
WIRE 5504 -1488 5488 -1488
WIRE 5600 -1488 5584 -1488
WIRE 5680 -1488 5680 -1584
WIRE 5680 -1488 5600 -1488
WIRE 5712 -1488 5680 -1488
WIRE 5856 -1488 5856 -1584
WIRE 5856 -1488 5808 -1488
WIRE 5984 -1488 5856 -1488
WIRE 6048 -1488 5984 -1488
WIRE 6144 -1488 6048 -1488
WIRE 6272 -1488 6144 -1488
WIRE 6048 -1472 6048 -1488
WIRE 6144 -1472 6144 -1488
WIRE 6272 -1472 6272 -1488
WIRE 6576 -1456 6320 -1456
WIRE 6672 -1456 6656 -1456
WIRE 6336 -1408 6320 -1408
WIRE 5792 -1392 5792 -1440
WIRE 6048 -1376 6048 -1408
WIRE 6144 -1376 6144 -1392
WIRE 6272 -1376 6272 -1392
WIRE 5600 -1344 5600 -1488
WIRE 5648 -1344 5600 -1344
WIRE 5984 -1344 5984 -1488
WIRE 5984 -1344 5936 -1344
WIRE 5488 -1264 5488 -1488
WIRE 5648 -1264 5488 -1264
WIRE 5424 -1184 5424 -1440
WIRE 5648 -1184 5424 -1184
WIRE 5968 -1184 5936 -1184
WIRE 6112 -1184 6048 -1184
WIRE 6112 -1152 6112 -1184
WIRE 5648 -1120 5616 -1120
WIRE 4704 -1072 4704 -1488
WIRE 5792 -1040 5792 -1056
WIRE 6112 -1040 6112 -1072
WIRE 4704 -976 4704 -992
SYMBOL voltage 4704 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR Value PWL(0u 0 100m 0 +1u 20 150m 20 +10u 0 200m 0 +1u -20 250m -20 +10u 0 400m 0 +1u 5 800m 5 +1u 20 900m 20 +10u 5)
SYMATTR InstName V2
SYMBOL res 6128 -1488 R0
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL cap 6032 -1472 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL nmos 5712 -1440 R270
WINDOW 0 74 50 VLeft 2
WINDOW 3 -14 71 VLeft 2
SYMATTR InstName Q2
SYMATTR Value Si4892DY
SYMBOL res 5488 -1472 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 25m
SYMBOL voltage 6560 -1456 M90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PWL(0us 0V 1200m 0 +5n 1 1201m 1 +5n 0)
SYMATTR InstName V3
SYMBOL diode 5808 -1600 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value Davalanche
SYMBOL voltage 6112 -1168 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 6064 -1200 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL LTC4361-2 5792 -1216 R0
SYMATTR InstName U1
SYMBOL pmos 5344 -1440 R270
WINDOW 0 54 43 VTop 2
WINDOW 3 -13 76 VLeft 2
SYMATTR InstName Q1
SYMATTR Value FDS4953
SYMBOL sw 6272 -1376 R180
WINDOW 0 -13 114 Right 2
WINDOW 3 -32 7 Right 2
SYMATTR InstName S1
SYMATTR Value SHORT
SYMBOL ind 5168 -1472 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -16 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=150m
FLAG 5792 -1040 0
FLAG 4704 -976 0
FLAG 6112 -1040 0
FLAG 6336 -1408 0
FLAG 6672 -1456 0
FLAG 6272 -1376 0
FLAG 6144 -1376 0
FLAG 6048 -1376 0
FLAG 5616 -1120 0
TEXT 5696 -896 Left 2 !.tran 1500m startup\n.model SHORT SW(Ron=1 Roff=1T Vt=0.5 Vh=-0.4)\n.model Davalanche D(Vfwd=0.7 Vrev=32 Ron=0.1 Rrev=0.1 epsilon=.1 revepsilon=.1)
TEXT 5784 -1624 Bottom 2 ;To model avalanche behavior of NFET