Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT4320-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LT4320-1.asy)
C1 OUT 0 200
XU1 N001 N003 N005 N006 0 OUT N004 N002 LT4320-1 ;pnba IN2)TG2)BG2)BG1)Outn)Outp)TG1)IN1
MQ1 OUT N003 N001 N001 IPD220N06L3
MQ2 OUT N004 N002 N002 IPD220N06L3
MQ4 N002 N005 0 0 IPD220N06L3
MQ3 N001 N006 0 0 IPD220N06L3
V1 N002 N001 SINE(0 36 400) Rser=.5
Rload OUT 0 32
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 12.5m
.lib LT4320-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1320 1428
WIRE 48 -112 0 -112
WIRE 656 -112 144 -112
WIRE -64 -16 -304 -16
WIRE 416 -16 -64 -16
WIRE 448 -16 416 -16
WIRE 656 -16 656 -112
WIRE 656 -16 544 -16
WIRE 720 -16 656 -16
WIRE 848 -16 720 -16
WIRE 720 0 720 -16
WIRE 848 0 848 -16
WIRE -304 16 -304 -16
WIRE 0 48 0 -112
WIRE 96 48 0 48
WIRE 416 48 416 -16
WIRE 416 48 384 48
WIRE 720 96 720 64
WIRE 848 96 848 80
WIRE 64 112 64 -64
WIRE 96 112 64 112
WIRE 464 112 464 32
WIRE 464 112 384 112
WIRE -304 128 -304 96
WIRE -144 128 -304 128
WIRE 0 128 0 48
WIRE 0 128 -144 128
WIRE 96 176 32 176
WIRE 656 176 656 -16
WIRE 656 176 384 176
WIRE 96 240 64 240
WIRE 416 240 384 240
WIRE 32 288 32 176
WIRE 64 288 64 240
WIRE 304 288 64 288
WIRE -64 336 -64 -16
WIRE -48 336 -64 336
WIRE 416 336 416 240
WIRE 416 336 48 336
WIRE 304 384 304 288
WIRE -144 432 -144 128
WIRE 224 432 -144 432
WIRE 416 432 416 336
WIRE 416 432 320 432
WIRE 448 432 416 432
SYMBOL LT4320-1 240 144 R0
SYMATTR InstName U1
SYMBOL nmos 544 32 M270
WINDOW 0 56 43 VTop 2
WINDOW 3 -15 73 VLeft 2
SYMATTR InstName Q2
SYMATTR Value IPD220N06L3
SYMBOL nmos 224 384 M90
WINDOW 0 5 48 VBottom 2
WINDOW 3 54 48 VTop 2
SYMATTR InstName Q3
SYMATTR Value IPD220N06L3
SYMBOL nmos 144 -64 M270
WINDOW 0 55 44 VTop 2
WINDOW 3 -14 71 VLeft 2
SYMATTR InstName Q1
SYMATTR Value IPD220N06L3
SYMBOL res 832 -16 R0
SYMATTR InstName Rload
SYMATTR Value 32
SYMBOL nmos -48 288 M90
WINDOW 0 4 52 VBottom 2
WINDOW 3 57 43 VTop 2
SYMATTR InstName Q4
SYMATTR Value IPD220N06L3
SYMBOL voltage -304 0 R0
WINDOW 123 24 138 Left 2
WINDOW 39 42 56 Left 2
SYMATTR SpiceLine Rser=.5
SYMATTR InstName V1
SYMATTR Value SINE(0 36 400)
SYMBOL cap 704 0 R0
SYMATTR InstName C1
SYMATTR Value 200
FLAG 848 -16 OUT
FLAG 720 96 0
FLAG 848 96 0
FLAG 448 432 0
TEXT 704 384 Left 2 !.tran 12.5m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2139-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2139-3.0.asy)
Rload OUT 0 5
L1 N001 OUT 1 Rser=60m
C1 OUT 0 10
XU1 IN IN N001 OUT 0 IN ADP2139-x.x Rtop=400K ;pnba Vin)EN)SW)Vout)GND)Mode
V1 IN 0 5
.tran .5m startup
.lib ADP2139-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL ADP2139-3.0 352 224 R0
SYMATTR InstName U1
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 5
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 600 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\041af22a3cbd_Draft9.asc
* Generated by LTspice 26.0.1 for Windows.
;.op dec 10000000 10Meg 300Meg
;.step param Ctest list 10p 20p 30p
C2 N001 N003 20p
R1 0 N002 1000000
D1 N001 0 MV2201
V2 N002 N001 {Vtest}
C1 0 N001 20p
V1 N003 0 AC 1 0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.step param Vtest list 1 2 3 4 5
.ac dec 10000000 10Meg 300Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1300 680
WIRE -80 -48 -112 -48
WIRE 16 -48 0 -48
WIRE 128 -48 96 -48
WIRE -112 64 -112 -48
WIRE -32 64 -112 64
WIRE 128 64 128 -48
WIRE 128 64 32 64
WIRE -240 160 -320 160
WIRE -112 160 -112 64
WIRE -112 160 -176 160
WIRE -80 160 -112 160
WIRE 16 160 -16 160
WIRE 128 160 128 64
WIRE 128 160 16 160
WIRE -320 224 -320 160
WIRE 16 240 16 160
WIRE -320 368 -320 304
SYMBOL cap -176 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 20p
SYMBOL voltage 16 -48 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vtest}
SYMBOL cap -16 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 20p
SYMBOL voltage -320 208 R0
WINDOW 3 -128 70 Left 2
WINDOW 123 -128 42 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMBOL varactor -32 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MV2201
SYMATTR Type diode
SYMBOL res 112 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000000
FLAG -320 368 0
FLAG 16 240 0
TEXT 888 -56 Left 2 !.step param Vtest list 1 2 3 4 5
TEXT -576 40 Left 2 !.ac dec 10000000 10Meg 300Meg
TEXT 568 360 Left 2 !;.op dec 10000000 10Meg 300Meg
TEXT 888 8 Left 2 !;.step param Ctest list 10p 20p 30p
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX44281U.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX44281U.asy)
XU1 IN Vcc 0 OUT MAX44281U ;pnba IN)VDD)GND)OUT
Vcc Vcc 0 3.3
RL OUT 0 10k
V1 IN 0 SINE(165m 50m 10k)
CL OUT 0 1p
.tran 100u
.lib MAX44281U.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 448 192 416 192
WIRE 544 192 528 192
WIRE 544 208 544 192
WIRE 416 240 416 192
WIRE 416 272 416 240
WIRE 384 304 304 304
WIRE 576 304 448 304
WIRE 672 304 576 304
WIRE 576 336 576 304
WIRE 416 352 416 336
WIRE 672 352 672 304
WIRE 304 416 304 304
WIRE 576 448 576 416
WIRE 672 448 672 416
WIRE 304 512 304 496
SYMBOL voltage 432 192 R270
WINDOW 123 0 0 Left 2
WINDOW 0 47 35 VRight 2
WINDOW 3 -45 40 VRight 2
SYMATTR InstName Vcc
SYMATTR Value 3.3
SYMBOL cap 656 352 R0
SYMATTR InstName CL
SYMATTR Value 1p
SYMBOL voltage 304 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 31 94 Left 2
SYMATTR Value SINE(165m 50m 10k)
SYMATTR InstName V1
SYMBOL MAX44281U 416 240 R0
SYMATTR InstName U1
SYMBOL res 560 320 R0
SYMATTR InstName RL
SYMATTR Value 10k
FLAG 672 304 OUT
FLAG 416 240 Vcc
FLAG 544 208 0
FLAG 304 512 0
FLAG 576 448 0
FLAG 304 304 IN
FLAG 672 448 0
FLAG 416 352 0
TEXT 288 560 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\07662abea9f7_Vswitch.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This shows an example of suppling a .model statement as a SPICE\ndirective directly on the schematic to define a voltage controlled switch.
R1 N001 OUT 1K
V1 IN 0 PULSE(0 1 0 .5m .5m 0 1m)
V2 N001 0 3.3
S1 0 OUT IN 0 MYSW
.model MYSW SW(Ron=1 Roff=1Meg Vt=.5 Vh=-.4)
.tran 3m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1276 680
WIRE 224 144 192 144
WIRE 336 144 304 144
WIRE 192 176 192 144
WIRE 144 192 -208 192
WIRE 336 192 336 144
WIRE -208 208 -208 192
WIRE 144 240 128 240
WIRE 192 272 192 256
WIRE 336 304 336 272
WIRE -208 320 -208 288
SYMBOL sw 192 272 M180
WINDOW 0 12 104 Left 2
WINDOW 3 17 11 Left 2
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL voltage 336 176 R0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 320 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -208 192 R0
WINDOW 3 13 107 Left 2
SYMATTR Value PULSE(0 1 0 .5m .5m 0 1m)
SYMATTR InstName V1
FLAG 336 304 0
FLAG 192 272 0
FLAG 128 240 0
FLAG -208 320 0
FLAG -208 192 IN
FLAG 192 144 OUT
TEXT -224 400 Left 2 !.model MYSW SW(Ron=1 Roff=1Meg Vt=.5 Vh=-.4)
TEXT 192 344 Left 2 !.tran 3m
TEXT 96 432 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT 56 88 Bottom 2 ;This shows an example of suppling a .model statement as a SPICE\ndirective directly on the schematic to define a voltage controlled switch.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2054.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC2054.asy)
R2 N001 0 10K
V3 N003 0 SINE(0 1 1K)
R1 N002 N001 10K
XU1 N003 N001 N002 +V -V LTC2054 ;pnba IN+)IN-)OUT)VCC)VEE
V1 +V 0 2.5
V2 -V 0 -2.5
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -48 -16 -64 -16
WIRE 48 -16 32 -16
WIRE 112 -16 48 -16
WIRE 208 -16 192 -16
WIRE -256 80 -256 64
WIRE -128 80 -128 64
WIRE 48 80 48 -16
WIRE 80 80 48 80
WIRE 208 96 208 -16
WIRE 208 96 144 96
WIRE 80 112 -16 112
WIRE -16 144 -16 112
WIRE -256 176 -256 160
WIRE -128 176 -128 160
WIRE -16 240 -16 224
SYMBOL res 48 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage -16 128 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL opamps\\LTC2054 112 96 R0
SYMATTR InstName U1
SYMBOL voltage -128 64 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 208 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -256 64 R0
SYMATTR InstName V2
SYMATTR Value -2.5
FLAG -128 176 0
FLAG 112 64 +V
FLAG -128 64 +V
FLAG 112 128 -V
FLAG -256 176 0
FLAG -256 64 -V
FLAG -16 240 0
FLAG -64 -16 0
TEXT 232 248 Left 2 !.tran 3m
* Z:\tmp\asc_dec_bjh7r6w2\07a27e47a686_Circ1_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R3 N005 N001 {(8/9)}
V1 N004 0 AC 1 0
R6 0 Vo 1
R4 N003 N005 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2000 680
WIRE 944 -32 368 -32
WIRE 1616 -16 1136 -16
WIRE 1792 -16 1680 -16
WIRE 1952 -16 1792 -16
WIRE 944 0 832 0
WIRE 1792 64 1792 -16
WIRE 1792 144 1792 128
WIRE 128 160 -192 160
WIRE 368 160 368 -32
WIRE 368 160 272 160
WIRE 416 160 368 160
WIRE 576 160 496 160
WIRE 656 160 576 160
WIRE 832 160 832 0
WIRE 832 160 736 160
WIRE 928 160 832 160
WIRE -192 224 -192 160
WIRE 1792 224 1792 144
WIRE 832 288 832 160
WIRE 832 288 768 288
WIRE 576 304 576 160
WIRE 704 304 576 304
WIRE 1376 320 768 320
WIRE -192 384 -192 304
SYMBOL res 512 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {(8/9)}
SYMBOL voltage -192 208 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL res 1808 160 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R6
SYMATTR Value 1
SYMBOL res 752 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1
FLAG 1952 -16 Vo
FLAG 1792 224 0
FLAG -192 384 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ba977df796df_Assignment_3b__iii_.asc
* Generated by LTspice 26.0.1 for Windows.
* Negative Half Wave Rectifier Circuit (with 1microF Capacitor) (Ideal)
V1 N001 0 SINE(0 311 50) Rser=0.001
C1 N002 0 0.000001
R1 N002 0 1000
D1 N002 N001 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 320 64 208 64
WIRE 480 64 384 64
WIRE 608 64 480 64
WIRE 208 112 208 64
WIRE 480 112 480 64
WIRE 608 128 608 64
WIRE 208 240 208 192
WIRE 304 240 208 240
WIRE 480 240 480 192
WIRE 480 240 304 240
WIRE 608 240 608 192
WIRE 608 240 480 240
WIRE 304 272 304 240
SYMBOL cap 592 128 R0
SYMATTR InstName C1
SYMATTR Value 0.000001
SYMBOL res 464 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL voltage 208 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
SYMBOL diode 384 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG 304 272 0
TEXT 144 272 Left 2 !.tran 0.05
TEXT -8 8 Left 2 ;Negative Half Wave Rectifier Circuit (with 1microF Capacitor) (Ideal)
* Z:\home\khalils\Downloads\files\data\raw_asc\9cf86e9b4b8b_lab2Scheme.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1097.asy)
;tran 0 10ms 0 1ms
V1 N003 0 12
XU1 N006 N001 N003 N007 N002 LT1097 ;pnba In+)In-)V+)V-)OUT
V2 0 N007 12
C N001 N005 15.1n
R1 N005 N004 987
Rd 0 N006 10.1k
V3 N004 0 PULSE(-1.6 1.6 0 .5m .5m 1u 0.2m) AC 25m
R N002 N001 9.93k
.ac dec 100 1 10meg
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 -2992 -208 -2992
WIRE -64 -2992 -96 -2992
WIRE 160 -2944 -144 -2944
WIRE -144 -2880 -144 -2944
WIRE -400 -2864 -448 -2864
WIRE -304 -2864 -320 -2864
WIRE -208 -2864 -208 -2992
WIRE -208 -2864 -240 -2864
WIRE -176 -2864 -208 -2864
WIRE -64 -2848 -64 -2992
WIRE -64 -2848 -112 -2848
WIRE 160 -2848 160 -2864
WIRE 272 -2848 160 -2848
WIRE -176 -2832 -224 -2832
WIRE 160 -2832 160 -2848
WIRE -448 -2784 -448 -2864
WIRE -224 -2784 -224 -2832
WIRE -144 -2752 -144 -2816
WIRE 160 -2752 -144 -2752
WIRE -448 -2640 -448 -2704
WIRE -224 -2640 -224 -2704
WIRE -224 -2640 -448 -2640
WIRE 272 -2640 272 -2848
WIRE 272 -2640 -224 -2640
WIRE -224 -2560 -224 -2640
SYMBOL Misc\\battery 160 -2848 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL Misc\\battery 160 -2960 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 20 23 Left 2
WINDOW 3 26 85 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap -240 -2880 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C
SYMATTR Value 15.1n
SYMBOL voltage -448 -2800 R0
WINDOW 3 -84 107 Left 2
WINDOW 39 0 0 Left 0
WINDOW 0 -61 33 Left 2
SYMATTR Value PULSE(-1.6 1.6 0 .5m .5m 1u 0.2m)
SYMATTR InstName V3
SYMATTR Value2 AC 25m
SYMBOL OpAmps\\LT1097 -144 -2912 R0
SYMATTR InstName U1
SYMBOL res -80 -3008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R
SYMATTR Value 9.93k
SYMBOL res -304 -2880 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 987
SYMBOL res -208 -2688 R180
WINDOW 0 36 76 Left 2
WINDOW 3 35 40 Left 2
SYMATTR InstName Rd
SYMATTR Value 10.1k
FLAG -224 -2560 0
TEXT -536 -2536 Left 2 !;tran 0 10ms 0 1ms
TEXT -488 -3112 Left 2 !.ac dec 100 1 10meg
* Z:\home\khalils\Downloads\files\data\raw_asc\LT7101.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT7101.asy)
L1 N002 OUT 47 Rser=5m
V1 IN 0 50
C6 N003 0 1 IC=0 Rser=20m
Rload OUT 0 10
C2 N001 N002 0.1 Rser=15m
XU1 MP_01 MP_02 IN MP_03 MP_04 0 0 NC_05 N003 OUT 0 0 NC_06 NC_07 NC_08 NC_09 NC_10 NC_11 0 OUT N003 MP_12 MP_13 N002 MP_14 MP_15 N001 MP_16 MP_17 IN MP_18 MP_19 MP_20 MP_21 0 LT7101 ;pnba ))Run)))SGND)OVLO)Rind)Ith)Vfb)Freq)PLLin/Mode)CLKOut)Pgood)SS)Ictrl)Imon)VPRG1)VPRG2)ExtVcc)IntVcc)))SW)))Boost)))Vin)))))PGND
C1 OUT 0 47 Rser=15m
.tran 1.8m startup
.lib LT7101.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 6140 3124
WIRE 592 -256 496 -256
WIRE 624 -256 592 -256
WIRE 1040 -256 1008 -256
WIRE 496 -240 496 -256
WIRE 592 -176 592 -256
WIRE 624 -176 592 -176
WIRE 1040 -176 1040 -192
WIRE 1040 -176 1008 -176
WIRE 1104 -176 1040 -176
WIRE 1216 -176 1184 -176
WIRE 1296 -176 1216 -176
WIRE 1296 -160 1296 -176
WIRE 496 -144 496 -160
WIRE 624 -96 608 -96
WIRE 1040 -96 1008 -96
WIRE 1216 -96 1216 -176
WIRE 1216 -96 1040 -96
WIRE 1216 -80 1216 -96
WIRE 1296 -64 1296 -80
WIRE 624 -16 608 -16
WIRE 1040 -16 1040 -96
WIRE 1040 -16 1008 -16
WIRE 1216 0 1216 -16
WIRE 1072 64 1008 64
WIRE 1072 144 1072 64
WIRE 1072 144 1008 144
WIRE 1072 160 1072 144
WIRE 1072 240 1072 224
WIRE 624 304 608 304
WIRE 1024 304 1008 304
WIRE 752 400 752 384
WIRE 880 400 880 384
SYMBOL LT7101 816 48 R0
SYMATTR InstName U1
SYMBOL ind 1088 -160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMATTR SpiceLine Rser=5m
SYMBOL cap 1200 -80 R0
SYMATTR Value 47
SYMATTR SpiceLine Rser=15m
SYMATTR InstName C1
SYMBOL cap 1056 160 R0
SYMATTR Value 1
SYMATTR SpiceLine Rser=20m
SYMATTR Value2 IC=0
SYMATTR InstName C6
SYMBOL voltage 496 -256 R0
SYMATTR InstName V1
SYMATTR Value 50
SYMBOL res 1280 -176 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 1024 -256 R0
SYMATTR Value 0.1
SYMATTR SpiceLine Rser=15m
SYMATTR InstName C2
FLAG 496 -144 0
FLAG 496 -256 IN
FLAG 1296 -176 OUT
FLAG 608 -96 0
FLAG 608 304 0
FLAG 1296 -64 0
FLAG 1216 0 0
FLAG 752 400 0
FLAG 880 400 0
FLAG 1024 304 0
FLAG 1072 240 0
FLAG 608 -16 0
TEXT 1152 352 Left 2 !.tran 1.8m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1389-4.096.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1389-4.096.asy)
XU1 N002 0 LT1389-4.096 ;pnba VCC)VEE
V2 N001 0 PULSE(0 10 2m 10n 10n 10m 2)
R1 N001 N002 3.9Meg
.tran 20m
.lib LT1389-4.096.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3476 836
WIRE 704 -272 528 -272
WIRE 960 -272 784 -272
WIRE 528 -240 528 -272
WIRE 960 -224 960 -272
WIRE 528 -112 528 -160
WIRE 960 -112 960 -160
SYMBOL res 688 -256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 3.9Meg
SYMBOL LT1389-4.096 960 -192 R0
SYMATTR InstName U1
SYMBOL voltage 528 -256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 2m 10n 10n 10m 2)
FLAG 960 -112 0
FLAG 528 -112 0
TEXT 1040 -80 Left 2 !.tran 20m
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8665.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8665.asy)
V1 +V 0 8
Rload OUT 0 10K
Vin IN 0 SINE(0 1 1K)
XU1 IN N001 +V -V OUT AD8665 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -8
.tran 10m
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 8
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL AD8665 576 -1168 R0
SYMATTR InstName U1
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -8
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
TEXT 688 -952 Left 2 !.tran 10m
* Z:\tmp\asc_dec_bjh7r6w2\058f8c9d6702_BoyleNoise1001_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
V2 -V 0 -15
V1 N003 0 ac 1
XU2 N003 N001 +V -V N002 LT1001 ;pnba In+)In-)V+)V-)OUT
R2 N001 0 10
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1001.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 192 -64 160 -64
WIRE 288 -64 272 -64
WIRE 304 -64 288 -64
WIRE 416 -64 384 -64
WIRE 352 32 352 16
WIRE 288 48 288 -64
WIRE 320 48 288 48
WIRE 416 64 416 -64
WIRE 416 64 384 64
WIRE 656 64 416 64
WIRE 320 80 112 80
WIRE 352 112 352 96
WIRE -272 128 -272 112
WIRE -160 128 -160 112
WIRE 192 192 160 192
WIRE 288 192 272 192
WIRE 304 192 288 192
WIRE 416 192 384 192
WIRE 496 192 480 192
WIRE -272 224 -272 208
WIRE -160 224 -160 208
WIRE 288 304 288 192
WIRE 320 304 288 304
WIRE 416 320 416 192
WIRE 112 336 112 80
WIRE 320 336 112 336
WIRE 112 352 112 336
WIRE 112 448 112 432
SYMBOL voltage -160 112 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 112 336 R0
SYMATTR InstName V1
SYMATTR Value ac 1
SYMBOL opamps\\LT1001 352 0 R0
SYMATTR InstName U2
SYMBOL res 288 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 10
FLAG 352 16 +V
FLAG 352 112 -V
FLAG -160 224 0
FLAG -272 224 0
FLAG -272 112 +V
FLAG -160 112 -V
FLAG 112 448 0
FLAG 480 192 0
FLAG 160 -64 0
FLAG 160 192 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-1.8.asy)
Rload OUT 0 500
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10
XU1 IN 0 IN N001 OUT LT1761-1.8 ;pnba IN)GND)_SHDN)BYP)OUT
C2 OUT N001 .01
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 48 -240 48
WIRE 16 48 -16 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -240 64 -240 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE -16 144 -16 48
WIRE 16 144 -16 144
WIRE 336 144 336 128
WIRE 336 144 304 144
WIRE -240 160 -240 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT1761-1.8 160 96 R0
SYMATTR InstName U1
SYMBOL cap 320 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -240 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
FLAG -240 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -240 48 IN
TEXT 368 232 Left 2 !.tran 1