* Z:\home\khalils\Downloads\files\data\raw_asc\ADAQ4216.asc
* Generated by LTspice 26.0.1 for Windows.
* IN+, IN-: Analog inputs. Transients from sampling caps are simulated. Input range is +/-VREF
* REF: For 5V VREF VDD should be 5.4V +/-100mV
* VDD: For REF=4.096V VDD=4.75V to 5.25V For REF=4.5V VDD= 4.8V to 5.25V
* Digital Out: Digital representation of output. +/-2^23 This can be used to drive DAC inputs
* Vout: Analog output +/-VREF
* CNV: 2MHz max 0V-1.8V logic level
* RSTn: Resets ADC. Tie to 1.8V for normal operation
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\ADAQ4216.asy)
V7 N003 0 5
V9 N004 0 4.096
V3 N002 0 -18
R1 0 OUT 10k
V12 N007 0 5
V11 N012 0 PWL(0 0 100n 0 200n 1.8)
V8 N011 0 -1
V13 N010 0 PULSE(0 1.8 500n .2n .2n 19.8n 500n)
R2 N008 0 10k
V5 N006 0 3.3
V10 N005 0 5
V6 N009 0 3.3
V1 IN+ 0 SINE(0 0.075 2k)
V2 IN- 0 SINE(0 0.075 2k 0 0 180)
XU1 N001 N002 IN+ IN- N006 N009 N003 N011 N004 N005 N010 OUT N008 N012 0 N007 ADAQ4216 ;pnba VDD_H)VSS_H)IN+)IN-)A0)A1)VDD_FDA)VSS_FDA)REF)VDD_5V)CNV)VOUT)BUSY)_RST)GND)PDB_FDA
V4 N001 0 18
.tran 0 1m 0 10n
.lib ADAQ4216.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2100 788
WIRE -144 -432 -144 -480
WIRE -80 -336 -80 -480
WIRE 128 -336 128 -368
WIRE 448 -336 448 -368
WIRE 544 -336 544 -368
WIRE -144 -224 -144 -352
WIRE -80 -224 -80 -256
WIRE 128 -224 128 -256
WIRE 448 -224 448 -256
WIRE 544 -224 544 -256
WIRE -336 64 -816 64
WIRE -288 64 -336 64
WIRE -816 96 -816 64
WIRE 768 112 704 112
WIRE 768 128 768 112
WIRE -336 144 -592 144
WIRE -288 144 -336 144
WIRE -592 192 -592 144
WIRE -816 208 -816 176
WIRE 768 240 768 208
WIRE 736 288 704 288
WIRE -592 304 -592 272
WIRE -144 464 -144 432
WIRE 192 464 192 432
WIRE 496 464 496 432
WIRE -80 560 -80 432
WIRE 192 560 192 544
WIRE 496 560 496 544
WIRE 560 560 560 432
WIRE 128 576 128 432
WIRE 432 624 432 432
WIRE 560 656 560 640
WIRE -144 672 -144 544
WIRE -80 672 -80 640
WIRE 128 672 128 656
WIRE 432 720 432 704
SYMBOL voltage 128 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value 5
SYMBOL voltage 128 560 R0
SYMATTR InstName V8
SYMATTR Value -1
SYMBOL res 480 448 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 752 224 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -80 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V3
SYMATTR Value -18
SYMBOL voltage -80 544 R0
SYMATTR InstName V6
SYMATTR Value 3.3
SYMBOL voltage -592 176 R0
SYMATTR InstName V2
SYMATTR Value SINE(0 0.075 2k 0 0 180)
SYMBOL voltage 448 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V9
SYMATTR Value 4.096
SYMBOL voltage -144 448 R0
SYMATTR InstName V5
SYMATTR Value 3.3
SYMBOL ADAQ4216 80 80 R0
SYMATTR InstName U1
SYMBOL voltage 544 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V10
SYMATTR Value 5
SYMBOL voltage -144 -336 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V4
SYMATTR Value 18
SYMBOL voltage 192 448 R0
SYMATTR InstName V12
SYMATTR Value 5
SYMBOL voltage 432 608 R0
WINDOW 0 15 18 Left 2
WINDOW 3 18 94 Left 2
SYMATTR InstName V11
SYMATTR Value PWL(0 0 100n 0 200n 1.8)
SYMBOL voltage 560 544 R0
SYMATTR InstName V13
SYMATTR Value PULSE(0 1.8 500n .2n .2n 19.8n 500n)
SYMBOL voltage -816 80 R0
SYMATTR InstName V1
SYMATTR Value SINE(0 0.075 2k)
FLAG -816 208 0
FLAG -592 304 0
FLAG -80 -480 0
FLAG -144 -480 0
FLAG 736 288 0
FLAG 768 240 0
FLAG -144 672 0
FLAG -80 672 0
FLAG 128 -368 0
FLAG 128 672 0
FLAG 448 -368 0
FLAG 544 -368 0
FLAG 432 720 0
FLAG 496 560 0
FLAG 560 656 0
FLAG 192 560 0
FLAG 768 112 OUT
FLAG -336 64 IN+
FLAG -336 144 IN-
TEXT 760 720 Left 2 !.tran 0 1m 0 10n
TEXT 1000 -240 Left 2 ;IN+, IN-: Analog inputs. Transients from sampling caps are simulated. Input range is +/-VREF
TEXT 1056 -208 Left 2 ;REF: For 5V VREF VDD should be 5.4V +/-100mV
TEXT 1048 -176 Left 2 ;VDD: For REF=4.096V VDD=4.75V to 5.25V For REF=4.5V VDD= 4.8V to 5.25V
TEXT 976 -144 Left 2 ;Digital Out: Digital representation of output. +/-2^23 This can be used to drive DAC inputs
TEXT 1048 -112 Left 2 ;Vout: Analog output +/-VREF
TEXT 1048 -80 Left 2 ;CNV: 2MHz max 0V-1.8V logic level
TEXT 1040 -48 Left 2 ;RSTn: Resets ADC. Tie to 1.8V for normal operation