Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8047A.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 10
C1 N001 0 4.7
R1 N003 0 6.19K
C2 OUT 0 22
Rload OUT 0 32
XU1 0 OUT 0 N003 IN N001 IN N002 LTM8047 ;pnba GND)Vout+)Vout-)Adj)Vin)Bias)Run)SS
.tran 2.5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8047A.asy)
.lib LTM8047.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 48 -16 48
WIRE 288 48 112 48
WIRE -16 64 -16 48
WIRE 288 64 288 48
WIRE 112 112 112 48
WIRE 128 112 112 112
WIRE -16 160 -16 144
WIRE 480 192 448 192
WIRE 576 192 480 192
WIRE 48 208 32 208
WIRE 128 208 112 208
WIRE 480 208 480 192
WIRE 576 208 576 192
WIRE 128 304 112 304
WIRE 480 320 480 272
WIRE 480 320 448 320
WIRE 576 320 576 288
WIRE 576 320 480 320
WIRE 576 336 576 320
WIRE 32 400 16 400
WIRE 128 400 112 400
WIRE 288 464 288 448
FLAG -16 160 0
FLAG 32 208 0
FLAG 16 400 0
FLAG 288 464 0
FLAG 576 336 0
FLAG 576 192 OUT
FLAG -16 48 IN
SYMBOL voltage -16 48 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL cap 112 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL res 128 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 6.19K
SYMBOL cap 464 208 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL res 560 192 R0
SYMATTR InstName Rload
SYMATTR Value 32
SYMBOL PowerProducts\\LTM8047A 288 256 R0
SYMATTR InstName U1
TEXT 528 416 Left 2 !.tran 2.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\235a903f0439_Butterworth_2nd.asc
* Generated by LTspice 26.0.1 for Windows.
R3 N001 N002 2.2k
C2 N005 0 0.6n
R4 0 N001 220k
R2 N004 N003 4.7k
R1 N005 N004 47k
C1 N004 0 14n
XU1 N005 N001 Vcc -Vcc N002 TL072 ;pnba In+)In-)V+)V-)OUT
V3 N003 0 AC
R5 0 N002 10k
V2 0 -Vcc 12
V1 Vcc 0 12
.ac oct 100 1 150k
.lib ..\..\01_models\TL072.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 688 0 688 -16
WIRE 224 16 48 16
WIRE 688 96 688 80
WIRE 768 96 688 96
WIRE 768 112 768 96
WIRE 688 128 688 96
WIRE 48 144 48 16
WIRE 96 144 48 144
WIRE 320 160 160 160
WIRE 528 160 320 160
WIRE -256 176 -320 176
WIRE -144 176 -176 176
WIRE -112 176 -144 176
WIRE 16 176 -32 176
WIRE 96 176 16 176
WIRE 320 192 320 160
WIRE -320 240 -320 176
WIRE 688 240 688 208
WIRE 528 256 528 160
WIRE -144 272 -144 176
WIRE 16 272 16 176
WIRE 224 320 224 16
WIRE 320 320 320 272
WIRE 320 320 224 320
WIRE 320 352 320 320
WIRE -320 464 -320 320
WIRE -144 464 -144 336
WIRE -144 464 -320 464
WIRE 16 464 16 336
WIRE 16 464 -144 464
WIRE 320 464 320 432
WIRE 320 464 16 464
WIRE 528 464 528 336
WIRE 528 464 320 464
WIRE 16 496 16 464
SYMBOL res 544 352 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL res 336 288 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 2.2k
SYMBOL voltage -320 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value AC
SYMBOL res -16 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 47k
SYMBOL voltage 688 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res -160 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 4.7k
SYMBOL cap -160 272 R0
SYMATTR InstName C1
SYMATTR Value 14n
SYMBOL res 336 448 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 220k
SYMBOL voltage 688 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL Opamps\\opamp2 128 96 R0
SYMATTR InstName U1
SYMATTR Value TL072
SYMBOL cap 0 272 R0
SYMATTR InstName C2
SYMATTR Value 0.6n
FLAG 16 496 0
FLAG 768 112 0
FLAG 688 -16 Vcc
FLAG 688 240 -Vcc
FLAG 128 128 Vcc
FLAG 128 192 -Vcc
TEXT -352 520 Left 2 !.ac oct 100 1 150k
TEXT -320 -72 Left 2 !.lib ..\\..\\01_models\\TL072.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1565.asc
* Generated by LTspice 26.0.1 for Windows.
* SCHEMATIC PARAMETERS-\nvvar controls the offset voltage\nfvar controls the frequency response\ngvar controls the gain\n \nEach parameter can be varied from -1 to +1 to see variations in the filter.\nFor "typical" performance, set the paramters to 0.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\FilterProducts\LTC1565.asy)
V1 N004 0 5
E1 N002 CMI IN 0 -0.5
V3 CMI 0 2.0
E2 OUT 0 OUTP OUTM 1
V2 IN 0 PWL(0 -1 10u -1 11u 1) AC 1 0
C1 N003 0 .1
E3 N001 CMI IN 0 0.5
XU1 N001 N002 N003 0 SDX N004 OUTM OUTP LTC1565 vvar={vvar} fvar={fvar} gvar={gvar} ;pnba +IN)-IN)GND)V-)_SHDN)V+)-OUT)+OUT
.ac oct 100 10e3 5e6
.param fvar=0 vvar=0 gvar=0
.step param fvar list -1 0 1
.lib LTC1565.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1160 692
WIRE -96 80 -256 80
WIRE 464 80 416 80
WIRE -256 96 -256 80
WIRE -352 112 -672 112
WIRE -304 112 -352 112
WIRE -96 112 -96 80
WIRE -32 112 -96 112
WIRE 304 112 256 112
WIRE 368 112 304 112
WIRE 416 112 416 80
WIRE -672 128 -672 112
WIRE 368 128 368 112
WIRE -304 176 -304 160
WIRE -32 192 -96 192
WIRE 304 192 256 192
WIRE 368 192 368 176
WIRE 368 192 304 192
WIRE -256 208 -256 176
WIRE -176 208 -256 208
WIRE 416 208 416 192
WIRE -96 224 -96 192
WIRE -96 224 -256 224
WIRE -672 240 -672 208
WIRE -256 240 -256 224
WIRE -352 256 -352 112
WIRE -304 256 -352 256
WIRE -32 272 -96 272
WIRE 416 272 256 272
WIRE -176 288 -176 208
WIRE -96 288 -96 272
WIRE 416 288 416 272
WIRE -304 320 -304 304
WIRE -256 352 -256 320
WIRE -176 352 -176 288
WIRE -176 352 -256 352
WIRE -32 352 -96 352
WIRE 288 352 256 352
WIRE -256 384 -256 352
WIRE 416 384 416 368
WIRE -96 400 -96 352
WIRE -256 480 -256 464
SYMBOL cap -112 288 R0
WINDOW 3 29 47 Left 2
SYMATTR Value .1
SYMATTR InstName C1
SYMBOL e -256 80 R0
SYMATTR InstName E3
SYMATTR Value 0.5
SYMBOL voltage 416 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL FilterProducts\\LTC1565 112 224 R0
SYMATTR InstName U1
SYMATTR SpiceLine vvar={vvar} fvar={fvar} gvar={gvar}
SYMBOL e 416 96 R0
SYMATTR InstName E2
SYMATTR Value 1
SYMBOL voltage -672 112 R0
WINDOW 123 41 58 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1 0
SYMATTR InstName V2
SYMATTR Value PWL(0 -1 10u -1 11u 1)
SYMBOL voltage -256 368 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 2.0
SYMBOL e -256 224 R0
SYMATTR InstName E1
SYMATTR Value -0.5
FLAG -96 400 0
FLAG 416 384 0
FLAG -672 240 0
FLAG -256 480 0
FLAG 416 208 0
FLAG 304 112 OUTP
FLAG 304 192 OUTM
FLAG 464 80 OUT
FLAG -672 112 IN
FLAG -176 288 CMI
FLAG 288 352 SDX
FLAG -304 176 0
FLAG -304 320 0
TEXT -712 -80 Left 2 !.ac oct 100 10e3 5e6\n.param fvar=0 vvar=0 gvar=0\n.step param fvar list  -1 0 1
TEXT -232 -192 Left 2 ;SCHEMATIC PARAMETERS-\nvvar controls the offset voltage\nfvar controls the frequency response\ngvar controls the gain\n \nEach parameter can be varied from -1 to +1 to see variations in the filter.\nFor "typical" performance, set the paramters to 0.
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8672.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
Vin IN 0 SINE(0 1 100K)
R1 N001 0 1K
R2 OUT N001 1K
V2 -V 0 -15
Rload OUT 0 2K
XU1 IN N001 +V -V OUT AD8672 ;pnba In+)In-)V+)V-)OUT
.tran 100u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8672.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1200 144 -1216
WIRE 256 -1200 256 -1216
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 144 -1104 144 -1120
WIRE 256 -1104 256 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
FLAG 144 -1216 +V
FLAG 144 -1104 0
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1216 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 768 -992 0
FLAG 256 -1104 0
SYMBOL voltage 144 -1216 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 256 -1216 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 2K
SYMBOL Opamps\\AD8672 576 -1168 R0
SYMATTR InstName U1
TEXT 680 -944 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\6a023e5176fa_FailedCapacitor.asc
* Generated by LTspice 26.0.1 for Windows.
C4 N004 N003 1e-9
D5 N004 N006 D
C3 N001 N005 1e-9
D1 0 N005 D
D4 N001 N004 D
V2 N002 0 PULSE(0 10 0.0015625 0 0 1e-3 2e-3 2)
D3 N003 N001 D
V1 0 N007 PULSE(0 15000 0 0 0 3.125e-5 6.25e-5 30)
C2 N003 0 1e-9
D2 N005 N003 D
C1 N005 N007 1e-9
C5 N006 N001 1e-9
S1 N001 N005 N002 0 switchshort
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2e-3
.plot V(C1)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 -144 48 -144
WIRE -16 -128 -64 -128
WIRE 64 -112 64 -144
WIRE -16 -96 -16 -128
WIRE -64 -80 -64 -128
WIRE 192 -80 96 -80
WIRE 48 -64 48 -144
WIRE 48 0 48 -16
WIRE 48 0 -64 0
WIRE -240 48 -336 48
WIRE -80 48 -240 48
WIRE -32 48 -80 48
WIRE 80 48 32 48
WIRE 224 48 80 48
WIRE 272 48 224 48
WIRE 384 48 336 48
WIRE 528 48 384 48
WIRE -80 112 -144 112
WIRE 80 112 -80 112
WIRE 96 112 96 0
WIRE 96 112 80 112
WIRE 112 112 96 112
WIRE 192 112 192 -80
WIRE 192 112 176 112
WIRE 224 112 192 112
WIRE 384 112 224 112
WIRE 416 112 384 112
WIRE 528 112 480 112
WIRE -336 160 -336 128
WIRE -208 160 -208 112
WIRE -208 160 -336 160
SYMBOL sw 96 -96 R0
SYMATTR InstName S1
SYMATTR Value switchshort
SYMBOL cap -144 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1e-9
SYMBOL voltage -336 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 15000 0 0 0 3.125e-5 6.25e-5 30)
SYMBOL cap 32 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1e-9
SYMBOL diode 400 112 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMBOL cap 176 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1e-9
SYMBOL cap 336 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1e-9
SYMBOL diode 208 48 R0
SYMATTR InstName D3
SYMBOL diode -96 48 R0
SYMATTR InstName D1
SYMBOL diode 512 48 R0
SYMATTR InstName D5
SYMBOL cap 480 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 1e-9
SYMBOL voltage -64 16 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0.0015625 0 0 1e-3 2e-3 2)
SYMBOL diode 96 112 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
FLAG -240 48 0
FLAG -16 -96 0
FLAG 64 -112 0
TEXT -368 168 Left 2 !.tran 2e-3
TEXT -856 160 Left 2 !.plot V(C1)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4601A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4601A.asy)
C2 OUT 0 570
Rload OUT 0 .125
C3 N010 0 .001
R2 N007 0 392K
XU1 IN 0 OUT 0 N005 N005 OUT 0 N001 N003 N006 N011 N009 N008 N007 N004 N002 N010 NC_01 N006 LTM4601 ;pnba Vin)PGND)Vout)Vosns-)Vout_LCL)DiffVout)Vosns+)SGND)Pgood)FB)DRVcc)MARG1)MARG0)Fset)MPGM)Comp)Run)Track/SS)PLLIN)INTVcc
R1 N003 0 40.2K
V1 IN 0 12
C1 OUT N003 100p
R4 IN N002 100K
R3 OUT N001 100K
.tran 750u startup
.lib LTM4601.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1032 680
WIRE 432 -32 -160 -32
WIRE -176 -16 -256 -16
WIRE 128 -16 -176 -16
WIRE -256 0 -256 -16
WIRE 128 0 128 -16
WIRE -160 48 -160 -32
WIRE -144 48 -160 48
WIRE 16 48 -64 48
WIRE 432 48 432 -32
WIRE 432 48 400 48
WIRE 592 48 432 48
WIRE 672 48 592 48
WIRE 592 64 592 48
WIRE -256 96 -256 80
WIRE -176 112 -176 -16
WIRE -80 112 -176 112
WIRE 16 112 0 112
WIRE 432 112 400 112
WIRE 496 112 432 112
WIRE 496 128 496 112
WIRE 592 144 592 128
WIRE 16 176 0 176
WIRE 432 176 400 176
WIRE 496 224 496 208
WIRE 16 240 0 240
WIRE 432 240 432 176
WIRE 432 240 400 240
WIRE 672 272 672 48
WIRE 672 272 576 272
WIRE 720 272 672 272
WIRE 720 288 720 272
WIRE 0 304 0 240
WIRE 16 304 0 304
WIRE 576 304 576 272
WIRE 576 304 400 304
WIRE -80 368 -96 368
WIRE 16 368 0 368
WIRE 576 368 400 368
WIRE 576 384 576 368
WIRE 720 384 720 368
WIRE 720 384 576 384
WIRE 720 400 720 384
WIRE 16 432 0 432
WIRE 416 432 400 432
WIRE -64 496 -80 496
WIRE 16 496 0 496
WIRE 416 496 400 496
WIRE 128 576 128 560
WIRE 288 576 288 560
SYMBOL PowerProducts\\LTM4601A 208 256 R0
SYMATTR InstName U1
SYMBOL res 480 112 R0
SYMATTR InstName R1
SYMATTR Value 40.2K
SYMBOL cap 416 48 R0
WINDOW 0 34 18 Left 2
WINDOW 3 35 47 Left 2
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL cap 576 64 R0
SYMATTR InstName C2
SYMATTR Value 570
SYMBOL res -96 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL voltage -256 -16 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res -160 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap 0 480 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL res 704 272 R0
SYMATTR InstName Rload
SYMATTR Value .125
SYMBOL res 16 384 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 392K
FLAG 128 576 0
FLAG 288 576 0
FLAG 496 224 0
FLAG -96 368 0
FLAG 592 144 0
FLAG 720 400 0
FLAG -256 96 0
FLAG -80 496 0
FLAG 720 272 OUT
FLAG -256 -16 IN
TEXT 472 496 Left 2 !.tran 750u startup
* Z:\tmp\asc_dec_bjh7r6w2\04d445d90134_Draft27_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
XU2 N003 N001 VCC VEE VOUT OP27 ;pnba In+)In-)V+)V-)OUT
R2 N001 N002 10k
R1 N003 P10V 10k
R4 0 N003 10k
VIN N002 0 SINE(0 10 50)
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP27.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 384 -64 384 -112
WIRE 384 -64 368 -64
WIRE 448 -64 448 -112
WIRE 368 80 368 -64
WIRE 448 96 448 -64
WIRE -64 32 -144 32
WIRE -144 48 -144 32
WIRE -64 48 -64 32
WIRE 288 80 48 80
WIRE 384 80 368 80
WIRE 48 96 48 80
WIRE 528 96 448 96
WIRE 384 112 368 112
WIRE 368 144 368 112
SYMBOL OpAmps\\OP27 416 32 R0
SYMATTR InstName U2
SYMBOL res 384 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 384 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 384 240 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL voltage 48 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 2
SYMATTR Value SINE(0 10 50)
SYMATTR InstName VIN
FLAG 48 176 0
FLAG -64 48 0
FLAG 528 96 VOUT
FLAG -144 -48 VCC
FLAG 416 64 VCC
FLAG -144 128 VEE
FLAG 416 128 VEE
FLAG 368 224 0
FLAG 288 144 P10V
* Z:\home\khalils\Downloads\files\data\raw_asc\f0bda7996e02_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T1 N001 0 0 N002 Td=50n Z0=50
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T2 0 0 N002 0 Td=50n Z0=150
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=50n Z0=150
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\4b068f9fb94a_nor.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N003 B Y N002 PMOS
V1 N001 0 5
M3 Y B 0 0 NMOS
M4 Y A 0 0 NMOS
M2 N001 A N003 N002 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -80 -16 -80
WIRE -16 -48 -16 -80
WIRE 160 -16 160 -80
WIRE 304 32 160 32
WIRE 112 64 80 64
WIRE 128 64 112 64
WIRE -80 128 -176 128
WIRE 80 128 80 64
WIRE 80 128 -80 128
WIRE 160 160 160 80
WIRE 304 208 304 32
WIRE 304 208 160 208
WIRE 112 240 -176 240
WIRE 416 256 160 256
WIRE 160 288 160 256
WIRE 160 288 32 288
WIRE 288 288 160 288
WIRE 32 320 32 288
WIRE 288 320 288 288
WIRE 112 336 112 240
WIRE 176 336 112 336
WIRE 64 368 32 368
WIRE 320 368 288 368
WIRE -80 400 -80 128
WIRE -16 400 -80 400
WIRE 176 400 176 336
WIRE 240 400 176 400
WIRE 32 448 32 416
WIRE 64 448 64 368
WIRE 64 448 32 448
WIRE 160 448 64 448
WIRE 288 448 288 416
WIRE 288 448 160 448
WIRE 320 448 320 368
WIRE 320 448 288 448
WIRE 160 480 160 448
IOPIN 416 256 Out
IOPIN -176 128 In
IOPIN -176 240 In
SYMBOL pmos4 112 -16 R0
SYMATTR InstName M2
SYMBOL nmos4 -16 320 R0
SYMATTR InstName M4
SYMBOL nmos4 240 320 R0
SYMATTR InstName M3
SYMBOL voltage -16 -64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL pmos4 112 160 R0
SYMATTR InstName M1
FLAG 416 256 Y
FLAG -176 128 A
FLAG -176 240 B
FLAG 160 480 0
FLAG -16 32 0
* Z:\home\khalils\Downloads\files\data\raw_asc\247f1eb1a05d_halvwave_current.asc
* Generated by LTspice 26.0.1 for Windows.
* positive values using function "uramp"
* pos. halvwave using function "limit"\nupper_limut is below amplitude for demo
* REF: HELP (F1) / LTspice / Circuit elements / B. Arbitrary
V1 sin 0 SINE(0 5 50)
B1 0 N001 I=limit({lower_limit},v(sin),{upper_limit})
B2 0 N002 I=uramp(v(sin))
R_Load1 N002 0 1
R_Load N001 0 1
.tran 100m
.params lower_limit = 0 upper_limit = 4.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 956 680
WIRE 16 -32 -144 -32
WIRE -144 16 -144 -32
WIRE 16 16 16 -32
WIRE -368 112 -368 64
WIRE -144 144 -144 96
WIRE 16 144 16 96
WIRE -368 224 -368 192
WIRE 16 240 -144 240
WIRE -144 288 -144 240
WIRE 16 288 16 240
WIRE -144 416 -144 368
WIRE 16 416 16 368
SYMBOL voltage -368 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 50)
SYMBOL res 0 0 R0
SYMATTR InstName R_Load
SYMATTR Value 1
SYMBOL res 0 272 R0
SYMATTR InstName R_Load1
SYMATTR Value 1
SYMBOL bi2 -144 16 R0
WINDOW 3 -9 169 Left 0
SYMATTR InstName B1
SYMATTR Value I=limit({lower_limit},v(sin),{upper_limit})
SYMBOL bi2 -144 288 R0
WINDOW 3 -29 163 Left 0
SYMATTR InstName B2
SYMATTR Value I=uramp(v(sin))
FLAG -368 224 0
FLAG -368 64 sin
FLAG -144 144 0
FLAG 16 144 0
FLAG -144 416 0
FLAG 16 416 0
TEXT -350 270 Left 0 !.tran 100m
TEXT 184 368 Left 0 ;positive values using function "uramp"
TEXT 120 -24 Left 0 !.params lower_limit = 0  upper_limit = 4.5
TEXT 200 64 Left 0 ;pos. halvwave using function "limit"\nupper_limut is below amplitude for demo
TEXT 352 224 Left 0 ;REF: HELP (F1) / LTspice / Circuit elements / B. Arbitrary
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7170.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7170.asy)
XU1 IN N002 IN N001 OUT 0 ADM7170 ;pnba Vin)Sense)EN)SS)Vout)GND
C1 OUT 0 4.7 Rser=1.5m
R2 N002 0 10K
C2 0 N001 1n
Rload OUT 0 15
V1 IN 0 3.5
R1 OUT N002 15K
.tran 5m startup
.lib ADM7170.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 400 32 352 32
WIRE 528 32 400 32
WIRE 624 32 528 32
WIRE -32 48 -32 32
WIRE 528 48 528 32
WIRE 624 48 624 32
WIRE 400 80 400 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 528 144 528 112
WIRE 624 144 624 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 400 224 400 160
WIRE 400 224 352 224
WIRE 400 240 400 224
WIRE 224 304 224 288
WIRE 400 336 400 320
SYMBOL PowerProducts\\ADM7170 224 128 R0
SYMATTR InstName U1
SYMBOL res 384 224 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 384 64 R0
SYMATTR InstName R1
SYMATTR Value 15K
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.5
SYMBOL cap 512 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1.5m
SYMBOL cap 16 208 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res 608 32 R0
SYMATTR InstName Rload
SYMATTR Value 15
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 624 144 0
FLAG 528 144 0
FLAG -32 32 IN
FLAG 624 32 OUT
FLAG 400 336 0
TEXT 568 288 Left 2 !.tran 5m startup
* Z:\tmp\asc_dec_bjh7r6w2\09998451391a_5a_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 1.2
M1 VdN N003 0 0 nch l=0.18u w=3u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 16 -64 16
WIRE 288 48 176 48
WIRE 32 144 32 16
WIRE 80 144 32 144
WIRE 32 160 32 144
WIRE 176 176 176 48
WIRE 176 192 176 176
WIRE 80 208 80 144
WIRE 80 208 32 208
WIRE -16 224 -96 224
WIRE -16 240 -16 224
WIRE 208 240 176 240
WIRE 128 272 48 272
WIRE 48 288 48 272
WIRE 176 304 176 288
WIRE 208 304 208 240
WIRE 208 304 176 304
WIRE 176 320 176 304
SYMBOL voltage -64 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.2
SYMBOL nmos4 128 192 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.18u w=3u
SYMATTR Value nch
FLAG 288 128 0
FLAG -64 96 0
FLAG 176 320 0
FLAG 32 256 0
FLAG 48 368 0
FLAG 176 176 VdN