Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1790-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1790-2.5.asy)
Rload OUT 0 1K
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 1
XU1 IN 0 OUT LT1790-25 ;pnba IN)GND)OUT
.tran 1
.lib LT1790.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 48 -176 48
WIRE 336 48 288 48
WIRE 432 48 336 48
WIRE -176 64 -176 48
WIRE 336 64 336 48
WIRE 432 64 432 48
WIRE -176 160 -176 144
WIRE 336 160 336 128
WIRE 432 160 432 144
WIRE 160 176 160 160
SYMBOL PowerProducts\\LT1790-2.5 160 48 R0
SYMATTR InstName U1
SYMBOL cap 320 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 416 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL voltage -176 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
FLAG -176 160 0
FLAG 336 160 0
FLAG 432 160 0
FLAG 160 176 0
FLAG 432 48 OUT
FLAG -176 48 IN
TEXT 280 224 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\02ea5393bd18_DFF.asc
* Generated by LTspice 26.0.1 for Windows.
* D Flip-Flop
* binary
* binary
* binary
* binary
* 2026-01-02
* <Revision History>\n2025-01-03: Initial version\n2026-01-02: Changed to .machine base state machine instead of Ltspice default DFF to avoid unexpected behaviour.
A1 o 0 0 0 0 xQ 0 0 BUF
A2 o 0 0 0 0 0 Q 0 BUF
R1 o 0 1k
.machine
.state LO 0
.state LATCH 1
.state HI 2
.rule LO LATCH V(clk)>.5
.rule LATCH HI V(clk)>.9
.rule * LO V(clk)<.5
.output (o) IF((state==1),V(D),V(Q))
.endmachine
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1208 680
WIRE -16 -496 -192 -496
WIRE 752 -496 704 -496
WIRE 848 -496 752 -496
WIRE 896 -496 848 -496
WIRE 976 -496 960 -496
WIRE 752 -464 752 -496
WIRE 896 -464 896 -480
WIRE -32 -368 -160 -368
WIRE 848 -368 848 -496
WIRE 896 -368 848 -368
WIRE 976 -368 960 -368
WIRE 752 -352 752 -384
WIRE 896 -336 896 -352
IOPIN -192 -496 In
IOPIN -160 -368 In
IOPIN 976 -496 Out
IOPIN 976 -368 Out
SYMBOL Digital\\inv 896 -432 R0
SYMATTR InstName A1
SYMBOL res 736 -480 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL Digital\\buf1 896 -560 R0
SYMATTR InstName A2
FLAG -192 -496 D
FLAG -160 -368 CLK
FLAG 976 -496 Q
FLAG 976 -368 xQ
FLAG 896 -336 0
FLAG 896 -464 0
FLAG 752 -352 0
FLAG 704 -496 o
TEXT -256 -648 Left 3 ;D Flip-Flop
TEXT -232 -520 Left 1 ;binary
TEXT -200 -392 Left 1 ;binary
TEXT 968 -520 Left 1 ;binary
TEXT 976 -392 Left 1 ;binary
TEXT 976 -656 Left 2 ;2026-01-02
TEXT 144 -528 Left 2 !.machine\n.state LO 0\n.state LATCH 1\n.state HI 2\n.rule LO LATCH V(clk)>.5\n.rule LATCH HI  V(clk)>.9\n.rule * LO V(clk)<.5\n.output (o) IF((state==1),V(D),V(Q))  \n.endmachine
TEXT -264 -200 Left 2 ;<Revision History>\n2025-01-03: Initial version\n2026-01-02: Changed to .machine base state machine instead of Ltspice default DFF to avoid unexpected behaviour.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3122.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3122.asy)
C1 N002 0 4.7
R2 N004 0 113K
C2 N006 0 390p Rser=210K Cpar=10p
R3 OUT N004 1.02Meg
XU1 N001 0 IN N002 N002 N005 N006 N004 IN 0 OUT N003 LTC3122 ;pnba SW)PGND)Vin)PWM)Vcc)Rt)Vc)FB)_SD)SGND)Vout)CAP
V1 IN 0 5
R1 N005 0 57.6K
C3 OUT N003 .1
L1 IN N001 3.3 Rser=10m
C4 OUT 0 22 V=25 Irms=0 Rser=0.003 Lser=0 mfg="TDK" pn="C575OX5RIE226M" type="X5R"
Rload OUT 0 15
.tran 11m startup
.lib LTC3122.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1072 680
WIRE 64 -48 -80 -48
WIRE 176 -48 64 -48
WIRE 272 -48 256 -48
WIRE -80 -32 -80 -48
WIRE 176 0 176 -48
WIRE 272 0 272 -48
WIRE -80 64 -80 48
WIRE 64 64 64 -48
WIRE 80 64 64 64
WIRE 400 64 368 64
WIRE 672 64 400 64
WIRE 784 64 672 64
WIRE 880 64 784 64
WIRE 400 80 400 64
WIRE 880 80 880 64
WIRE 784 96 784 64
WIRE -16 160 -32 160
WIRE 64 160 48 160
WIRE 80 160 64 160
WIRE 400 160 400 144
WIRE 400 160 368 160
WIRE 672 160 672 64
WIRE 784 176 784 160
WIRE 880 176 880 160
WIRE 64 256 64 160
WIRE 80 256 64 256
WIRE 672 256 672 240
WIRE 672 256 368 256
WIRE 672 272 672 256
WIRE -16 352 -32 352
WIRE 80 352 64 352
WIRE 496 352 368 352
WIRE 576 352 560 352
WIRE 672 368 672 352
WIRE 176 432 176 416
WIRE 272 432 272 416
SYMBOL cap 768 96 R0
SYMATTR InstName C4
SYMATTR Value 22
SYMATTR SpiceLine V=25 Irms=0 Rser=0.003 Lser=0 mfg="TDK" pn="C575OX5RIE226M" type="X5R"
SYMBOL res 864 64 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 80 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 57.6K
SYMBOL cap 384 80 R0
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL cap 496 368 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
WINDOW 39 -21 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 390p
SYMATTR SpiceLine Rser=210K Cpar=10p
SYMBOL ind 160 -32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 3.3
SYMATTR SpiceLine Rser=10m
SYMBOL res 656 256 R0
SYMATTR InstName R2
SYMATTR Value 113K
SYMBOL res 656 144 R0
SYMATTR InstName R3
SYMATTR Value 1.02Meg
SYMBOL cap 48 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL PowerProducts\\LTC3122 224 208 R0
SYMATTR InstName U1
FLAG 176 432 0
FLAG 272 432 0
FLAG -32 160 0
FLAG -80 64 0
FLAG -32 352 0
FLAG 576 352 0
FLAG 672 368 0
FLAG 784 176 0
FLAG 880 176 0
FLAG 880 64 OUT
FLAG -80 -48 IN
TEXT 832 344 Left 2 !.tran 11m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4195-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\ADuM4195-1.asy)
V2 Vin 0 5 AC 1
V3 Shtdn 0 0
XU1 Vdd2 Vin Shtdn 0 0 Vout Vdd1 ADuM4195-1 ;pnba VDD2)VIN)SHTDN)GND2)GND1)VOUT)VDD1
V4 Vdd1 0 5
V1 Vdd2 0 5
.tran 1m
.lib ADuM4195-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3080 680
WIRE -1776 -448 -2096 -448
WIRE -1728 -448 -1776 -448
WIRE -1376 -448 -1424 -448
WIRE -1232 -448 -1376 -448
WIRE -1232 -432 -1232 -448
WIRE -2096 -416 -2096 -448
WIRE -1776 -384 -2000 -384
WIRE -1728 -384 -1776 -384
WIRE -1376 -384 -1424 -384
WIRE -1296 -384 -1376 -384
WIRE -2000 -352 -2000 -384
WIRE -1776 -304 -1872 -304
WIRE -1728 -304 -1776 -304
WIRE -1872 -272 -1872 -304
WIRE -1728 -240 -1760 -240
WIRE -1392 -240 -1424 -240
WIRE -2096 -160 -2096 -336
WIRE -2000 -160 -2000 -272
WIRE -1872 -160 -1872 -192
SYMBOL voltage -1872 -288 R0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL ADuM4195-1 -1568 -352 R0
SYMATTR InstName U1
SYMBOL voltage -2000 -368 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 26 126 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMATTR Value2 AC 1
SYMBOL voltage -1232 -448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 43 29 Left 2
WINDOW 3 46 61 Left 2
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL voltage -2096 -432 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -1392 -240 0
FLAG -2096 -160 0
FLAG -1872 -160 0
FLAG -1776 -448 Vdd2
FLAG -1760 -240 0
FLAG -1232 -352 0
FLAG -2000 -160 0
FLAG -1776 -384 Vin
FLAG -1376 -384 Vout
FLAG -1376 -448 Vdd1
FLAG -1776 -304 Shtdn
TEXT -1728 -128 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1740-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1740-1.5.asy)
Rload OUT 0 0.75
C2 N002 0 10n
C1 OUT 0 4.7 Rser=3m
V1 IN 0 1.8
XU1 IN OUT IN N002 OUT N001 MP_01 0 ADP1740-1.5 ;pnba Vin)Sense)EN)SS)Vout)PG))GND
R1 IN N001 100k
.tran 10m startup
.lib ADP1740-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE -112 32 -128 32
WIRE -16 32 -112 32
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 416 32 368 32
WIRE 496 32 416 32
WIRE 528 32 496 32
WIRE -128 48 -128 32
WIRE -16 48 -16 32
WIRE 416 48 416 32
WIRE 528 48 528 32
WIRE 80 96 80 32
WIRE 96 96 80 96
WIRE -128 144 -128 128
WIRE 416 144 416 112
WIRE 528 144 528 128
WIRE -16 176 -16 128
WIRE 96 176 -16 176
WIRE 16 240 0 240
WIRE 96 240 80 240
WIRE 368 240 368 32
WIRE 368 240 352 240
WIRE 224 304 224 288
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.75
SYMBOL ADP1740-1.5 224 128 R0
SYMATTR InstName U1
SYMBOL cap 400 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL res -32 32 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap 80 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
FLAG 224 304 0
FLAG -128 144 0
FLAG 0 240 0
FLAG -112 32 IN
FLAG 528 144 0
FLAG 416 144 0
FLAG 496 32 OUT
TEXT 128 352 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4352.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4352.asy)
R1 N002 N006 100K
XU1 N001 N005 N005 0 N006 N007 0 N002 0 N003 N004 N001 LTC4352 ;pnba Vin)Vcc)UV)OV)_Status)_Fault)Rev)Out)GND)CPO)Gate)Source
V2 N008 0 PULSE(0 5 1m 45m 45m 100m 200m)
Rload N002 0 3
V1 N001 0 PULSE(0 12 1m 30m 65m 10m 200m)
C1 0 N005 .1
MQ1 N002 N004 N001 N001 Si4864DY
R2 N002 N007 100K
C2 N003 N001 .1
C3 0 N002 100
D1 N008 N002 MBR735
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m
.lib LTC4352.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1608 1284
WIRE 672 0 0 0
WIRE 784 0 672 0
WIRE 880 0 784 0
WIRE 1008 0 976 0
WIRE 1104 0 1008 0
WIRE 1200 0 1104 0
WIRE 1296 0 1200 0
WIRE 0 16 0 0
WIRE 1200 48 1200 0
WIRE 576 64 560 64
WIRE 672 64 672 0
WIRE 672 64 640 64
WIRE 0 112 0 96
WIRE 560 128 560 64
WIRE 672 128 672 64
WIRE 784 128 784 0
WIRE 896 128 896 48
WIRE 1008 128 1008 0
WIRE 1104 160 1104 0
WIRE 464 192 368 192
WIRE 496 192 464 192
WIRE 368 208 368 192
WIRE 1296 256 1296 0
WIRE 1360 256 1296 256
WIRE 1488 256 1360 256
WIRE 464 272 464 192
WIRE 496 272 464 272
WIRE 1104 272 1104 240
WIRE 1104 272 1072 272
WIRE 1360 272 1360 256
WIRE 1488 272 1488 256
WIRE 368 288 368 272
WIRE 496 352 464 352
WIRE 1200 352 1200 128
WIRE 1200 352 1072 352
WIRE 1360 368 1360 336
WIRE 1488 368 1488 352
WIRE 464 432 464 352
WIRE 496 432 464 432
WIRE 464 480 464 432
WIRE 784 496 784 464
WIRE 800 560 448 560
WIRE 1296 560 1296 256
WIRE 1296 560 864 560
WIRE 448 576 448 560
WIRE 448 672 448 656
SYMBOL cap 352 272 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 1184 32 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap 576 48 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL schottky 800 576 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBR735
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 1344 336 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value 100
SYMBOL res 1088 144 R0
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL voltage 448 560 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 5 1m 45m 45m 100m 200m)
SYMATTR InstName V2
SYMBOL res 1472 256 R0
SYMATTR InstName Rload
SYMATTR Value 3
SYMBOL LTC4352 784 304 R0
WINDOW 0 4 -51 Center 2
WINDOW 3 10 70 Center 2
SYMATTR InstName U1
SYMBOL voltage 0 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 12 1m 30m 65m 10m 200m)
SYMATTR InstName V1
SYMBOL nmos 976 48 M270
WINDOW 0 85 40 VTop 2
WINDOW 3 68 93 VLeft 2
SYMATTR InstName Q1
SYMATTR Value Si4864DY
FLAG 0 112 0
FLAG 1488 368 0
FLAG 368 288 0
FLAG 464 480 0
FLAG 784 496 0
FLAG 448 672 0
FLAG 1360 368 0
TEXT 1344 624 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4891-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4891-2.asy)
V1 +V 0 2.5
R1 N001 0 10K
XU1 IN N001 +V -V OUT ADA4891-1 ;pnba In+)In-)V+)V-)OUT
Vin IN 0 SINE(0 1 10K)
V2 -V 0 -2.5
Rload OUT 0 10K
R2 OUT N001 10K
.tran 1m
.lib ADA4891-1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1136 144 -1152
WIRE 256 -1136 256 -1152
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1040 144 -1056
WIRE 256 -1040 256 -1056
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 144 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage 256 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL ADA4891-2 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 144 -1152 +V
FLAG 144 -1040 0
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1152 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 768 -992 0
FLAG 256 -1040 0
TEXT 752 -936 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\995fffebf1b2_Basic_opamp1.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 in 0 V+ V- out opatyp1 ;pnba In+)In-)V+)V-)OUT
V1 V+ 0 -5
V2 V- 0 5
VS in 0 0
.subckt opatyp1 ip im vp vm out
.param GAIN=10000
.param ROUT=10
* Gain stage and limiter
B1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))
* Lowpass
R1 out0 0 1k
C1 out0 0 1p
* Output resistance
G1 out 0 out0 0 {1/ROUT}
Rout out 0 {ROUT}
.ends
.dc VS -10m 10m 0.1m
* Basic Opamp Subcircuit
* Model with infinite power supply rejection (PSRR)
* opamp2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1504 680
WIRE 128 128 128 112
WIRE 96 144 64 144
WIRE 256 160 160 160
WIRE -16 176 -32 176
WIRE 96 176 -16 176
WIRE -32 192 -32 176
WIRE 128 208 128 192
WIRE -32 288 -32 272
WIRE -32 400 -32 384
WIRE 112 400 112 384
WIRE -32 496 -32 480
WIRE 112 496 112 480
FLAG 64 144 0
FLAG 128 112 V+
FLAG 128 208 V-
FLAG -32 288 0
FLAG -32 496 0
FLAG 112 496 0
FLAG -32 384 V+
FLAG 112 384 V-
FLAG 256 160 out
FLAG -16 176 in
SYMBOL Opamps\\opamp2 128 96 R0
SYMATTR InstName U1
SYMATTR Value opatyp1
SYMBOL voltage -32 384 R0
SYMATTR InstName V1
SYMATTR Value -5
SYMBOL voltage 112 384 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -32 176 R0
SYMATTR InstName VS
SYMATTR Value 0
TEXT 368 136 Left 0 !.subckt opatyp1 ip im vp vm out\n.param GAIN=10000\n.param ROUT=10\n* Gain stage and limiter\nB1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))\n* Lowpass\nR1 out0 0 1k\nC1 out0 0 1p\n* Output resistance\nG1 out 0 out0 0 {1/ROUT}\nRout out 0 {ROUT}\n.ends
TEXT -88 32 Left 0 !.dc VS -10m 10m 0.1m
TEXT -88 -24 Left 0 ;Basic Opamp Subcircuit
TEXT 280 72 Left 0 ;Model with infinite power supply rejection (PSRR)
TEXT 216 304 Left 0 ;opamp2
LINE Normal 160 224 256 288
LINE Normal 176 256 160 224
LINE Normal 160 224 176 256
LINE Normal 192 224 160 224
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4618.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4618.asy)
R1 N003 0 28K
Rload OUT 0 .4
C2 OUT 0 47 Rser=6m
V1 IN 0 12
C1 N002 0 .001
XU1 0 NC_01 NC_02 NC_03 OUT MP_04 MP_05 N001 0 N001 N003 NC_06 N002 NC_07 IN 0 LTM4618 ;pnba Mode/PLLin)Pgood)SW)ExtVcc)Vout)))IntVcc)SGND)FREQ)FB)Comp)Track/SS)Run)Vin)PGND
.tran 1m startup
.lib LTM4618.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 -80 32 -80
WIRE 176 -64 -80 -64
WIRE -80 -48 -80 -64
WIRE 176 -48 176 -64
WIRE 272 -48 272 -80
WIRE -80 48 -80 32
WIRE 32 96 32 -80
WIRE 48 96 32 96
WIRE 48 192 32 192
WIRE 480 192 400 192
WIRE 592 192 480 192
WIRE 480 208 480 192
WIRE 592 208 592 192
WIRE 480 304 480 272
WIRE 592 304 592 288
WIRE -48 384 -64 384
WIRE 48 384 16 384
WIRE 416 384 400 384
WIRE 512 384 496 384
WIRE 176 448 176 432
WIRE 272 448 272 432
SYMBOL res 400 400 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 28K
SYMBOL cap 464 208 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMATTR SpiceLine Rser=6m
SYMBOL res 576 192 R0
SYMATTR InstName Rload
SYMATTR Value .4
SYMBOL cap 16 368 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .001
SYMBOL PowerProducts\\LTM4618 224 192 R0
SYMATTR InstName U1
SYMBOL voltage -80 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 176 448 0
FLAG 272 448 0
FLAG -64 384 0
FLAG 512 384 0
FLAG -80 48 0
FLAG 32 192 0
FLAG 592 304 0
FLAG 480 304 0
FLAG -80 -64 IN
FLAG 592 192 OUT
TEXT 528 448 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3530.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 N002 4.7 Rser=26m
V1 IN 0 2.8
R1 IN N003 1Meg
C1 N003 0 2n
R2 OUT N006 340k
R3 N006 0 200k
C2 N006 N009 470p
C3 OUT 0 22
R4 N007 0 33.2k
R5 N005 0 100k
C4 N005 0 10n
C5 N004 N006 100p
XU1 N007 N005 N001 N002 0 OUT IN N003 N006 N008 LTC3530 ;pnba Rt)Burst)SW1)SW2)GND)Vout)Vin)_SHDN/SS)FB)Vc
Rload OUT 0 6.6
R6 OUT N004 4.75k
R7 N009 N008 15k
.tran 2m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3530.asy)
.lib LTC3530.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 836
WIRE 144 32 80 32
WIRE 272 32 224 32
WIRE 80 80 80 32
WIRE 272 80 272 32
WIRE -96 144 -288 144
WIRE 0 144 -96 144
WIRE 384 144 352 144
WIRE 496 144 384 144
WIRE 592 144 496 144
WIRE 688 144 592 144
WIRE -288 160 -288 144
WIRE 384 160 384 144
WIRE 592 160 592 144
WIRE 688 160 688 144
WIRE 496 192 496 144
WIRE -96 240 -96 224
WIRE -96 240 -112 240
WIRE 0 240 -96 240
WIRE -288 256 -288 240
WIRE 384 256 384 240
WIRE 592 256 592 224
WIRE 688 256 688 240
WIRE -128 336 -224 336
WIRE 0 336 -128 336
WIRE 384 336 384 320
WIRE 384 336 352 336
WIRE 496 336 496 272
WIRE 496 336 384 336
WIRE 608 336 496 336
WIRE -224 352 -224 336
WIRE -128 352 -128 336
WIRE 496 352 496 336
WIRE 608 352 608 336
WIRE 0 432 -64 432
WIRE 384 432 352 432
WIRE 496 432 496 416
WIRE 496 432 464 432
WIRE -224 448 -224 432
WIRE -128 448 -128 416
WIRE 608 448 608 432
WIRE -64 464 -64 432
WIRE 176 512 176 496
WIRE -64 560 -64 544
FLAG -288 256 0
FLAG -176 240 0
FLAG 608 448 0
FLAG 592 256 0
FLAG 688 256 0
FLAG 688 144 OUT
FLAG -288 144 IN
FLAG -64 560 0
FLAG 176 512 0
FLAG -224 448 0
FLAG -128 448 0
SYMBOL ind 128 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=26m
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 2.8
SYMBOL res -112 128 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL cap -112 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL res 480 176 R0
WINDOW 3 27 97 Left 2
SYMATTR Value 340k
SYMATTR InstName R2
SYMBOL res 592 336 R0
WINDOW 3 30 87 Left 2
SYMATTR Value 200k
SYMATTR InstName R3
SYMBOL cap 480 352 R0
WINDOW 3 40 38 Left 2
WINDOW 39 85 54 Top 2
SYMATTR Value 470p
SYMATTR InstName C2
SYMBOL cap 576 160 R0
SYMATTR InstName C3
SYMATTR Value 22
SYMBOL res -80 448 R0
SYMATTR InstName R4
SYMATTR Value 33.2k
SYMBOL res -240 336 R0
SYMATTR InstName R5
SYMATTR Value 100k
SYMBOL cap -144 352 R0
SYMATTR InstName C4
SYMATTR Value 10n
SYMBOL cap 368 256 R0
WINDOW 3 39 37 Left 2
WINDOW 39 22 66 Left 2
SYMATTR Value 100p
SYMATTR InstName C5
SYMBOL LTC3530 176 288 R0
SYMATTR InstName U1
SYMBOL res 672 144 R0
SYMATTR InstName Rload
SYMATTR Value 6.6
SYMBOL res 368 144 R0
SYMATTR InstName R6
SYMATTR Value 4.75k
SYMBOL res 480 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 15k
TEXT 360 520 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7170-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7170-2.5.asy)
Rload OUT 0 7.5
C2 N001 0 1n
XU1 IN OUT IN N001 OUT 0 ADM7170-2.5 ;pnba Vin)Sense)EN)SS)Vout)GND
V1 IN 0 3
C1 OUT 0 4.7 Rser=1.5m
.tran 5m startup
.lib ADM7170-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1.5m
SYMBOL ADM7170-2.5 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 7.5
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
TEXT 408 264 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3009-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3009-1.8.asy)
XU1 IN OUT MP_01 0 IN LT3009-1.8 ;pnba IN)OUT))GND)_SHDN
Rload OUT 0 180
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 1
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 416 48 320 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 180
SYMBOL PowerProducts\\LT3009-1.8 176 96 R0
SYMATTR InstName U1
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 408 216 Left 2 !.tran 1