* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4682.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 12
C1 OUT0 0 330 x3
C2 OUT1 0 330 x3
R1 OUT0 0 33m
R2 OUT1 0 33m
R3 N013 N015 10K
R4 N011 N015 10K
R5 Sync N015 10K
C3 OUT2 0 330 x3
C4 OUT3 0 330 x3
R6 OUT2 0 33m
R7 OUT3 0 33m
R8 N014 N016 10K
R9 N012 N016 10K
C5 N019 0 220p
C6 N021 0 220p
C7 N005 0 220p
C8 N003 0 220p
C9 N002 0 4.7n
C10 N004 0 4.7n
C11 N020 0 4.7n
C12 N018 0 4.7n
R10 IN N001 100k
R11 IN N006 100k
R12 IN N022 100k
R13 IN N017 100k
XU1 OUT0 0 IN OUT1 N018 N019 IN OUT0 NC_01 NC_02 Sync IN NC_03 NC_04 N016 NC_05 N011 N013 NC_06 Sync NC_07 NC_08 N008 NC_09 NC_10 NC_11 OUT2 N015 N021 N020 0 OUT1 N022 N009 0 N002 NC_12 NC_13 IN NC_14 0 N012 N014 N010 N007 N004 NC_15 N017 0 OUT3 IN IN N003 N005 OUT3 0 N001 N006 OUT2 LTM4682 Vi01n=5.5 Vi01of=5 Vo0=.5 Vo1=.75 ILM0=0 ILM1=0 OC0=1 OC1=1 MD01=1 FLT01=0 RTY01=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K SYC01=0 F01=500K PH0=0 PH1=180 Tn0=.3m Tn0r=.5m Tn1=.3m Tn1r=.5m Tof0=.2m Tof0f=.3m Tof1=.2m Tof1f=.3m Vo0r=0 Vo1r=0 Vi23n=5.5 Vi23of=5 Vo2=1 Vo3=1.25 ILM2=0 ILM3=1 OC2=1 OC3=1 MD23=1 FLT23=0 RTY23=.1m gm2=3m gm3=3m Rth2=5K Rth3=5K SYC23=0 F23=500K PH2=0 PH3=180 Tn2=.3m Tn2r=.5m Tn3=.3m Tn3r=.5m Tof2=.2m Tof2f=.3m Tof3=.2m Tof3f=.3m Vo2r=0 Vo3r=0 ;pnba Vosns0+)Vosns0-)VIN_Vbias)Vout1)Comp0a)Comp0b)Vin23)Vout0)Vtrim0_cfg)Vtrim1_cfg)SYNC_01)SVin_23)Vtrim3_cfg)IntVcc_23)VDD33_23)VDD25_23)Run0)Run1)Fswph_23_cfg)SYNC_23)Vout0_cfg)Vout1_cfg)SW2)Fswph_01_cfg)VDD25_01)Vtrim2_cfg)Vosns2+)VDD33_01)Comp1b)Comp1a)Vosns1-)Vosns1+)PGood1)SW1)Vosns2-)Comp2a)Vout2_cfg)IntVcc_01)Vin01)Vbias)PGND)Run2)Run3)SW3)SW0)Comp3a)Vout3_cfg)PGood0)SGND)Vout3)Runp)SVin_01)Comp2b)Comp3b)Vosns3+)Vosns3-)PGood2)PGood3)Vout2
.tran 1.8m startup
* Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time related parameters.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LTM4681. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope discribed in the datasheet, the resulting simulation outcomes are not meaningful. Only \nChannels 0 and 1 have been listed. Parameters for Channels 2 and 3 follow accordingly.\n \n Vi01n & Vi01of; Vi23n & Vi23of -- in volts, set the unit start/stop input voltages\n F01 & F23-- in Hz, sets switching frequency as one of values of 250K, 350K, \n 425K, 500K, 575K, 650K, 750K, 1000K. FSWPH_CFG pin needs to float \n (or short to VDD25), to make the value be in effect;\n PH0 & PH1; PH2 & PH3 -- in degree, set phase angle related to SYNC signal. \n Certain combinations are restricted as in datasheet. FSWPH_CFG \n pin needs to float (or short to VDD25), to make the value be in effect;\n Tn0 & Tn0r; Tn1 & Tn1r -- in sec, set delay and soft-start timers for \n channel0 and channel1. Initialization time is not modeled;\n Tof0 & Tof0f; Tof1 & Tof1f -- in sec, set delay and soft-off timers for \n channel0 and channel1;\n Vo0 & Vo1; Vo2 & Vo3 -- in volt, set output voltages respectively;\n V0r & V1r; V2r & V3r -- set maximum output range, with value \n 0 for 3.6Vmax; 1 for 2.75Vmax\n ILM0 & ILM1; ILM2 & ILM3 -- set maximum sensed peak current range, with value 0\n for low, and 1 for high;\n OC0 & OC1; OC2 & OC3 -- set ratio of peak current limit to the maximum value defined\n by Ilimit_range. It must be one of values: 0.5, 0.572, 0.642, \n 0.714, 0.786, 0.858, 0.928, 1;\n MD01 & MD23 -- sets light load operation mode: 0 for discontinuous, 1 for forced continuous;\n FLT01 & FLT23 -- sets the response mode of the unit to occuring faults:\n 0 for ignore, 1 for latch up, 2 for Hiccup after Retry_delay time;\n RTY01 & RTY23 -- in sec, sets the timer before the unit turns on after a fault;\n gm0 & gm1; gm2 & gm3 -- transconductance of the error amplifier. It must be between 1m mho and 5.73m mho;\n Rth0 &Rth1; Rth2 & Rth3 -- Compensation resistor. It must be set between 0k ohms and 62k ohms;\n SYC01 & SYC23 - value 0 for configuring module as Master, value 1 for Slave
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4682.asy)
.lib LTM4682.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3828 960
WIRE 144 -1136 -960 -1136
WIRE 1440 -1136 144 -1136
WIRE -688 -1120 -720 -1120
WIRE 1168 -1120 1136 -1120
WIRE -720 -1104 -720 -1120
WIRE 1136 -1104 1136 -1120
WIRE -288 -1088 -288 -1104
WIRE -144 -1088 -144 -1104
WIRE 560 -1088 560 -1104
WIRE 704 -1088 704 -1104
WIRE 16 -1008 0 -1008
WIRE -720 -992 -720 -1024
WIRE -288 -992 -288 -1024
WIRE -144 -992 -144 -1024
WIRE 0 -992 0 -1008
WIRE 144 -992 144 -1136
WIRE 560 -992 560 -1024
WIRE 704 -992 704 -1024
WIRE 1136 -992 1136 -1024
WIRE -960 -928 -960 -1136
WIRE -864 -928 -960 -928
WIRE -960 -832 -960 -928
WIRE -960 -832 -1488 -832
WIRE -864 -832 -960 -832
WIRE 1312 -832 1264 -832
WIRE 1440 -832 1440 -1136
WIRE 1440 -832 1312 -832
WIRE -1488 -784 -1488 -832
WIRE -960 -736 -960 -832
WIRE -864 -736 -960 -736
WIRE 1312 -736 1312 -832
WIRE 1312 -736 1264 -736
WIRE -1488 -672 -1488 -704
WIRE -864 -640 -896 -640
WIRE 1296 -640 1264 -640
WIRE -1104 -544 -1200 -544
WIRE -960 -544 -1104 -544
WIRE -864 -544 -960 -544
WIRE 1360 -544 1264 -544
WIRE 1504 -544 1360 -544
WIRE 1600 -544 1504 -544
WIRE -1200 -512 -1200 -544
WIRE 1600 -512 1600 -544
WIRE -1104 -496 -1104 -544
WIRE 1504 -496 1504 -544
WIRE -960 -448 -960 -544
WIRE -864 -448 -960 -448
WIRE 1360 -448 1360 -544
WIRE 1360 -448 1264 -448
WIRE -1200 -352 -1200 -432
WIRE -1104 -352 -1104 -432
WIRE -1104 -352 -1200 -352
WIRE -864 -352 -1104 -352
WIRE 1504 -352 1504 -432
WIRE 1504 -352 1264 -352
WIRE 1600 -352 1600 -432
WIRE 1600 -352 1504 -352
WIRE -1104 -320 -1104 -352
WIRE 1504 -320 1504 -352
WIRE -864 -256 -896 -256
WIRE 1312 -256 1264 -256
WIRE -1104 -160 -1200 -160
WIRE -960 -160 -1104 -160
WIRE -864 -160 -960 -160
WIRE 1360 -160 1264 -160
WIRE 1504 -160 1360 -160
WIRE 1600 -160 1504 -160
WIRE -1200 -128 -1200 -160
WIRE 1600 -128 1600 -160
WIRE -1104 -112 -1104 -160
WIRE 1504 -112 1504 -160
WIRE -960 -64 -960 -160
WIRE -864 -64 -960 -64
WIRE 1360 -64 1360 -160
WIRE 1360 -64 1264 -64
WIRE -1200 32 -1200 -48
WIRE -1104 32 -1104 -48
WIRE -1104 32 -1200 32
WIRE -864 32 -1104 32
WIRE 1504 32 1504 -48
WIRE 1504 32 1264 32
WIRE 1600 32 1600 -48
WIRE 1600 32 1504 32
WIRE -1104 64 -1104 32
WIRE 1504 64 1504 32
WIRE -864 128 -1072 128
WIRE 1440 128 1264 128
WIRE -864 224 -976 224
WIRE 1344 224 1264 224
WIRE -1072 272 -1072 128
WIRE -976 272 -976 224
WIRE 1344 272 1344 224
WIRE 1440 272 1440 128
WIRE -1072 416 -1072 352
WIRE -976 416 -976 352
WIRE -976 416 -1072 416
WIRE -864 416 -976 416
WIRE 1344 416 1344 352
WIRE 1344 416 1264 416
WIRE 1440 416 1440 352
WIRE 1440 416 1344 416
WIRE 144 592 144 576
WIRE 288 592 288 576
WIRE -720 608 -720 576
WIRE -288 608 -288 576
WIRE -144 608 -144 576
WIRE 0 608 0 576
WIRE 16 608 0 608
WIRE 576 608 576 576
WIRE 720 608 720 576
WIRE 1152 608 1152 576
WIRE 0 624 0 608
WIRE -288 688 -288 672
WIRE -144 688 -144 672
WIRE 576 688 576 672
WIRE 720 688 720 672
WIRE -720 704 -720 688
WIRE -688 704 -720 704
WIRE 1152 704 1152 688
WIRE 1184 704 1152 704
WIRE -976 720 -976 416
WIRE 0 720 0 704
WIRE 0 720 -976 720
FLAG -1488 -672 0
FLAG -1104 -320 0
FLAG -1104 64 0
FLAG 144 592 0
FLAG 288 592 0
FLAG 1504 -320 0
FLAG 1504 64 0
FLAG -1488 -832 IN
FLAG -1200 -544 OUT0
FLAG -1200 -160 OUT1
FLAG 1600 -544 OUT2
FLAG 1600 -160 OUT3
FLAG -144 688 0
FLAG 720 688 0
FLAG 704 -1104 0
FLAG -144 -1104 0
FLAG -288 -1104 0
FLAG 560 -1104 0
FLAG 576 688 0
FLAG -288 688 0
FLAG 16 608 Sync
FLAG 16 -1008 Sync
FLAG -688 -1120 IN
FLAG 1168 -1120 IN
FLAG 1184 704 IN
FLAG -688 704 IN
SYMBOL voltage -1488 -800 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap -1120 -496 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 x3
SYMATTR InstName C1
SYMATTR Value 330
SYMBOL cap -1120 -112 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 x3
SYMATTR InstName C2
SYMATTR Value 330
SYMBOL res -1216 -528 R0
SYMATTR InstName R1
SYMATTR Value 33m
SYMBOL res -1216 -144 R0
SYMATTR InstName R2
SYMATTR Value 33m
SYMBOL res -992 256 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res -1088 256 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res -16 608 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL cap 1488 -496 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 x3
SYMATTR InstName C3
SYMATTR Value 330
SYMBOL cap 1488 -112 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 x3
SYMATTR InstName C4
SYMATTR Value 330
SYMBOL res 1584 -528 R0
SYMATTR InstName R6
SYMATTR Value 33m
SYMBOL res 1584 -144 R0
SYMATTR InstName R7
SYMATTR Value 33m
SYMBOL res 1328 256 R0
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL res 1424 256 R0
SYMATTR InstName R9
SYMATTR Value 10K
SYMBOL cap -160 608 R0
SYMATTR InstName C5
SYMATTR Value 220p
SYMBOL cap 704 608 R0
SYMATTR InstName C6
SYMATTR Value 220p
SYMBOL cap 688 -1024 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C7
SYMATTR Value 220p
SYMBOL cap -160 -1024 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C8
SYMATTR Value 220p
SYMBOL cap -304 -1024 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C9
SYMATTR Value 4.7n
SYMBOL cap 544 -1024 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C10
SYMATTR Value 4.7n
SYMBOL cap 560 608 R0
SYMATTR InstName C11
SYMATTR Value 4.7n
SYMBOL cap -304 608 R0
SYMATTR InstName C12
SYMATTR Value 4.7n
SYMBOL res -736 -1120 R0
SYMATTR InstName R10
SYMATTR Value 100k
SYMBOL res 1120 -1120 R0
SYMATTR InstName R11
SYMATTR Value 100k
SYMBOL res 1136 704 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R12
SYMATTR Value 100k
SYMBOL res -736 704 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R13
SYMATTR Value 100k
SYMBOL LTM4682 -608 -448 R0
SYMATTR InstName U1
SYMATTR SpiceLine Vi01n=5.5 Vi01of=5 Vo0=.5 Vo1=.75 ILM0=0 ILM1=0 OC0=1 OC1=1 MD01=1 FLT01=0 RTY01=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K SYC01=0 F01=500K PH0=0 PH1=180 Tn0=.3m Tn0r=.5m Tn1=.3m Tn1r=.5m Tof0=.2m Tof0f=.3m Tof1=.2m Tof1f=.3m Vo0r=0 Vo1r=0
SYMATTR SpiceLine2 Vi23n=5.5 Vi23of=5 Vo2=1 Vo3=1.25 ILM2=0 ILM3=1 OC2=1 OC3=1 MD23=1 FLT23=0 RTY23=.1m gm2=3m gm3=3m Rth2=5K Rth3=5K SYC23=0 F23=500K PH2=0 PH3=180 Tn2=.3m Tn2r=.5m Tn3=.3m Tn3r=.5m Tof2=.2m Tof2f=.3m Tof3=.2m Tof3f=.3m Vo2r=0 Vo3r=0
TEXT 1520 608 Left 2 !.tran 1.8m startup
TEXT 1768 -584 Left 1 ;Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time related parameters.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LTM4681. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope discribed in the datasheet, the resulting simulation outcomes are not meaningful. Only \nChannels 0 and 1 have been listed. Parameters for Channels 2 and 3 follow accordingly.\n \n     Vi01n & Vi01of; Vi23n & Vi23of -- in volts, set the unit start/stop input voltages\n     F01 & F23-- in Hz, sets switching frequency as one of values of 250K, 350K, \n                425K, 500K, 575K, 650K, 750K, 1000K. FSWPH_CFG pin needs to float \n                (or short to VDD25), to make the value be in effect;\n     PH0 & PH1; PH2 & PH3 -- in degree,  set phase angle related to SYNC signal. \n                Certain combinations are restricted as in datasheet. FSWPH_CFG \n                pin needs to float (or short to VDD25), to make the value be in effect;\n     Tn0 & Tn0r; Tn1 & Tn1r -- in sec, set delay and soft-start timers for \n                channel0 and channel1. Initialization time is not modeled;\n     Tof0 & Tof0f; Tof1 & Tof1f -- in sec, set delay and soft-off timers for \n                channel0 and channel1;\n     Vo0 & Vo1; Vo2 & Vo3 -- in volt, set output voltages respectively;\n     V0r & V1r; V2r & V3r -- set maximum output range, with value \n                                                   0 for 3.6Vmax; 1 for 2.75Vmax\n     ILM0 & ILM1; ILM2 & ILM3 -- set maximum sensed peak current range, with value 0\n                           for low, and 1 for high;\n     OC0 & OC1; OC2 & OC3 -- set ratio of peak current limit to the maximum value defined\n                      by Ilimit_range. It must be one of values: 0.5, 0.572, 0.642, \n                      0.714, 0.786, 0.858, 0.928, 1;\n     MD01 & MD23 -- sets light load operation mode: 0 for discontinuous, 1 for forced continuous;\n     FLT01 & FLT23 -- sets the response mode of the unit to occuring faults:\n                                 0 for ignore, 1 for latch up, 2 for Hiccup after Retry_delay time;\n     RTY01 & RTY23 -- in sec, sets the timer before the unit turns on after a fault;\n     gm0 & gm1; gm2 & gm3 -- transconductance of the error amplifier. It must be between 1m mho and 5.73m mho;\n     Rth0 &Rth1; Rth2 & Rth3 -- Compensation resistor. It must be set between 0k ohms and 62k ohms;\n     SYC01 & SYC23 - value 0 for configuring module as Master, value 1 for Slave