* Z:\home\khalils\Downloads\files\data\raw_asc\audioamp.asc
* Generated by LTspice 26.0.1 for Windows.
* .ac oct 10 1 100Meg
* To look at gain and phase margins:\n i) comment the .tran line\n ii) uncomment the .ac line\n iv) re-run the simulation\n iii) plot V(A)/V(B)
* This example schematic is supplied for informational/educational purposes only.
* <-- To see the output of a .four statement, select View=>Spice Error Log
Q8 A N013 N014 0 2N2219A
V1 N001 0 10
C1 N003 N002 10p
C2 N006 N005 100p
R6 N010 0 5K
R1 N009 IN 5K
V4 A B AC 1
Q3 N006 N005 N004 0 2N3906
C3 N006 N012 .001
R9 N006 N008 2K
R3 N011 N014 1K
R8 N001 N004 100
R7 B N010 50K
Q7 N001 N007 A 0 2N2219A
Q1 N002 N009 N011 0 2N3904
Q5 N001 N006 N007 0 2N3904
V2 N014 0 -10
R11 N012 N014 5K
Q6 N013 N012 A 0 2N3906
Q4 N006 N008 N012 0 2N3904
R4 N003 N002 9K
Q2 N001 N010 N011 0 2N3904
R10 N008 N012 1K
R13 N013 N014 1K
R14 A 0 8
R2 N001 N002 200
R5 N005 N003 1K
V3 IN 0 SINE(0 .7 1K)
R12 N007 A 1K
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10m
.options maxstep=10u
.fourier 1K V(a)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2344 2032
WIRE 944 928 784 928
WIRE 1392 928 944 928
WIRE 1744 928 1392 928
WIRE 1904 928 1744 928
WIRE 2000 928 1904 928
WIRE 1392 944 1392 928
WIRE 784 960 784 928
WIRE 2000 960 2000 928
WIRE 1024 976 992 976
WIRE 1136 976 1088 976
WIRE 1392 1040 1392 1024
WIRE 2000 1072 2000 1040
WIRE 784 1088 784 1040
WIRE 992 1088 992 976
WIRE 992 1088 784 1088
WIRE 1024 1088 992 1088
WIRE 1136 1088 1136 976
WIRE 1136 1088 1104 1088
WIRE 1168 1088 1136 1088
WIRE 1280 1088 1248 1088
WIRE 1328 1088 1280 1088
WIRE 1744 1120 1744 928
WIRE 1280 1168 1280 1088
WIRE 1296 1168 1280 1168
WIRE 1392 1168 1392 1136
WIRE 1392 1168 1360 1168
WIRE 1520 1168 1392 1168
WIRE 1616 1168 1520 1168
WIRE 1680 1168 1616 1168
WIRE 1392 1184 1392 1168
WIRE 1904 1200 1904 928
WIRE 1520 1232 1520 1168
WIRE 1616 1248 1616 1168
WIRE 1744 1248 1744 1216
WIRE 1840 1248 1744 1248
WIRE 1744 1264 1744 1248
WIRE 1392 1280 1392 1264
WIRE 1456 1280 1392 1280
WIRE 784 1312 784 1088
WIRE 944 1312 944 928
WIRE 624 1360 560 1360
WIRE 720 1360 704 1360
WIRE 1024 1360 1008 1360
WIRE 1088 1360 1024 1360
WIRE 1200 1360 1168 1360
WIRE 1232 1360 1200 1360
WIRE 1328 1360 1312 1360
WIRE 1744 1360 1744 1344
WIRE 1744 1360 1328 1360
WIRE 1904 1360 1904 1296
WIRE 1904 1360 1744 1360
WIRE 2080 1360 1904 1360
WIRE 1392 1376 1392 1280
WIRE 1024 1392 1024 1360
WIRE 2080 1392 2080 1360
WIRE 560 1408 560 1360
WIRE 1744 1440 1744 1360
WIRE 784 1456 784 1408
WIRE 864 1456 784 1456
WIRE 944 1456 944 1408
WIRE 944 1456 864 1456
WIRE 1392 1488 1392 1456
WIRE 1520 1488 1520 1328
WIRE 1520 1488 1392 1488
WIRE 1616 1488 1616 1312
WIRE 1616 1488 1520 1488
WIRE 1680 1488 1616 1488
WIRE 1024 1504 1024 1472
WIRE 1904 1504 1904 1360
WIRE 2080 1504 2080 1472
WIRE 864 1520 864 1456
WIRE 560 1536 560 1488
WIRE 1392 1536 1392 1488
WIRE 1744 1552 1744 1536
WIRE 1840 1552 1744 1552
WIRE 1744 1568 1744 1552
WIRE 864 1664 864 1600
WIRE 1392 1664 1392 1616
WIRE 1392 1664 864 1664
WIRE 1744 1664 1744 1648
WIRE 1744 1664 1392 1664
WIRE 1904 1664 1904 1600
WIRE 1904 1664 1744 1664
WIRE 2000 1664 1904 1664
WIRE 2000 1712 2000 1664
WIRE 2000 1808 2000 1792
SYMBOL res 720 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5K
SYMBOL res 768 944 R0
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL pnp 1328 1136 M180
WINDOW 0 72 68 Left 2
WINDOW 3 72 28 Left 2
SYMATTR InstName Q3
SYMATTR Value 2N3906
SYMBOL PNP 1680 1536 M180
WINDOW 0 64 68 Left 2
WINDOW 3 68 28 Left 2
SYMATTR InstName Q6
SYMATTR Value 2N3906
SYMBOL npn 1008 1312 M0
WINDOW 0 54 32 Left 2
WINDOW 3 51 65 Left 2
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL npn 1840 1504 R0
SYMATTR InstName Q8
SYMATTR Value 2N2219A
SYMBOL res 1728 1552 R0
SYMATTR InstName R13
SYMATTR Value 1K
SYMBOL res 1376 1360 R0
SYMATTR InstName R10
SYMATTR Value 1K
SYMBOL cap 1360 1152 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL npn 1456 1232 R0
SYMATTR InstName Q4
SYMATTR Value 2N3904
SYMBOL RES 1376 1520 R0
SYMATTR InstName R11
SYMATTR Value 5K
SYMBOL res 1376 928 R0
SYMATTR InstName R8
SYMATTR Value 100
SYMBOL npn 720 1312 R0
WINDOW 0 54 32 Left 2
WINDOW 3 52 69 Left 2
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 848 1504 R0
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL voltage 560 1392 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 .7 1K)
SYMBOL cap 1088 960 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL cap 1600 1248 R0
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL res 1728 1248 R0
SYMATTR InstName R12
SYMATTR Value 1K
SYMBOL res 1264 1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL voltage 1328 1360 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V4
SYMATTR Value AC 1
SYMBOL NPN 1680 1120 R0
WINDOW 0 60 24 Left 2
WINDOW 3 60 68 Left 2
SYMATTR InstName Q5
SYMATTR Value 2N3904
SYMBOL res 1184 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 50K
SYMBOL npn 1840 1200 R0
SYMATTR InstName Q7
SYMATTR Value 2N2219A
SYMBOL VOLTAGE 2000 944 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 1376 1168 R0
SYMATTR InstName R9
SYMATTR Value 2K
SYMBOL res 1008 1376 R0
SYMATTR InstName R6
SYMATTR Value 5K
SYMBOL res 1120 1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 9K
SYMBOL voltage 2000 1696 R0
SYMATTR InstName V2
SYMATTR Value -10
SYMBOL res 2064 1376 R0
SYMATTR InstName R14
SYMATTR Value 8
FLAG 2000 1072 0
FLAG 2000 1808 0
FLAG 2080 1504 0
FLAG 1024 1504 0
FLAG 560 1536 0
FLAG 1328 1360 A
FLAG 1200 1360 B
FLAG 560 1360 IN
TEXT 976 1752 Left 2 !.tran 10m
TEXT 976 1784 Left 2 !.options maxstep=10u
TEXT 976 1848 Left 2 ;.ac oct 10 1 100Meg
TEXT 560 1712 Left 2 ;To look at gain and phase margins:\n     i) comment the .tran line\n    ii) uncomment the .ac line\n   iv) re-run the simulation\n   iii) plot V(A)/V(B)
TEXT 1248 1872 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT 976 1816 Left 2 !.fourier 1K V(a)
TEXT 1160 1816 Left 2 ;<-- To see the output of a .four statement, select View=>Spice Error Log