* Z:\home\khalils\Downloads\files\data\raw_asc\fce214325827_puf_reliability.asc
* Generated by LTspice 26.0.1 for Windows.
* Access transistor
* Cross-coupled PMOS
* Cross-coupled NMOS
Vdd Vdd 0 PULSE(0 1.2 0n 100p 100p 10n 20n)
M3 response response_comp N001 N001 PMOS2
M4 response_comp response 0 0 NMOS1
Vchallenge V_challenge 0 PULSE(0 1.2 1n 100p 100p 40n 80n)
MX2 response net_mid Vdd Vdd PMOS1
M5 response response_comp 0 0 NMOS2
MX3 response_comp net_mid Vdd Vdd PMOS2
MX4 net_mid response 0 0 NMOS1
MX1 net_mid V_challenge Vdd Vdd PMOS_ACC
M2 response_comp response N001 N001 PMOS1
M1 N001 V_challenge Vdd Vdd PMOS
MX5 net_mid response_comp 0 0 NMOS2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.param seed=0
.param baseW=2u
.param baseL=0.18u
.func w_rand(seed) {baseW * (1 + 0.2*(rand(seed)-0.5)*2)}
.func vth_rand(seed, sign) {sign*0.45 + 0.1*(rand(seed)-0.5)*2}
.model NMOS1 NMOS (LEVEL=3 VTO={vth_rand(seed+1, 1)} W={w_rand(seed+2)} L=0.18u)
.model NMOS2 NMOS (LEVEL=3 VTO={vth_rand(seed+3, 1)} W={w_rand(seed+4)} L=0.18u)
.model PMOS1 PMOS (LEVEL=3 VTO={vth_rand(seed+5, -1)} W={w_rand(seed+6)} L=0.18u)
.model PMOS2 PMOS (LEVEL=3 VTO={vth_rand(seed+7, -1)} W={w_rand(seed+8)} L=0.18u)
.model PMOS_ACC PMOS (LEVEL=3 VTO=-0.5 W=10u L=0.18u)
.tran 0.1n 50n
.step param seed 1 10 1
.options post
.meas response_val FIND V(response) AT=25n
.meas response_val_comp FIND V(response_comp) AT=25n
.meas digital_response param 'V(response) > 0.6'
.meas digital_response_comp param 'V(response_comp) > 0.6'
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2228 2036
WIRE 240 0 144 0
WIRE 240 48 240 0
WIRE 240 48 224 48
WIRE 256 48 240 48
WIRE 224 64 224 48
WIRE 176 80 128 80
WIRE 256 112 256 48
WIRE 256 112 224 112
WIRE 224 240 224 160
WIRE 224 240 112 240
WIRE 432 240 224 240
WIRE 112 272 112 240
WIRE 128 272 112 272
WIRE 432 272 432 240
WIRE 432 272 416 272
WIRE 64 288 16 288
WIRE 528 288 480 288
WIRE 128 320 128 272
WIRE 128 320 112 320
WIRE 416 320 416 272
WIRE 432 320 416 320
WIRE 16 384 16 288
WIRE 432 384 432 368
WIRE 432 384 16 384
WIRE 528 384 528 288
WIRE 608 384 608 368
WIRE 608 384 528 384
WIRE 112 432 112 368
WIRE 528 432 528 384
WIRE 528 432 112 432
WIRE -80 448 -80 416
WIRE 16 448 16 384
WIRE 16 448 -80 448
WIRE 112 448 112 432
WIRE 432 448 432 384
WIRE 128 496 112 496
WIRE 432 496 416 496
WIRE 16 528 16 448
WIRE 64 528 16 528
WIRE 528 528 528 432
WIRE 528 528 480 528
WIRE 112 560 112 544
WIRE 128 560 128 496
WIRE 128 560 112 560
WIRE 416 560 416 496
WIRE 432 560 432 544
WIRE 432 560 416 560
WIRE 128 592 128 560
WIRE 256 592 128 592
WIRE 416 592 416 560
WIRE 416 592 256 592
WIRE 256 608 256 592
SYMBOL pmos4 64 368 M180
SYMATTR InstName M2
SYMATTR Value PMOS1
SYMBOL pmos4 176 160 M180
SYMATTR InstName M1
SYMBOL nmos4 480 448 M0
SYMATTR InstName M5
SYMATTR Value NMOS2
SYMBOL nmos4 64 448 R0
SYMATTR InstName M4
SYMATTR Value NMOS1
SYMBOL pmos4 480 368 R180
SYMATTR InstName M3
SYMATTR Value PMOS2
FLAG 256 608 0
FLAG 128 80 V_challenge
FLAG 144 0 Vdd
FLAG -80 416 response
FLAG 608 368 response_comp
TEXT 1120 1208 Left 2 !.param seed=0\n.param baseW=2u\n.param baseL=0.18u\n \n.func w_rand(seed) {baseW * (1 + 0.2*(rand(seed)-0.5)*2)}\n.func vth_rand(seed, sign) {sign*0.45 + 0.1*(rand(seed)-0.5)*2}\n.model NMOS1 NMOS (LEVEL=3 VTO={vth_rand(seed+1, 1)}  W={w_rand(seed+2)} L=0.18u)\n.model NMOS2 NMOS (LEVEL=3 VTO={vth_rand(seed+3, 1)}  W={w_rand(seed+4)} L=0.18u)\n.model PMOS1 PMOS (LEVEL=3 VTO={vth_rand(seed+5, -1)} W={w_rand(seed+6)} L=0.18u)\n.model PMOS2 PMOS (LEVEL=3 VTO={vth_rand(seed+7, -1)} W={w_rand(seed+8)} L=0.18u)\n.model PMOS_ACC PMOS (LEVEL=3 VTO=-0.5 W=10u L=0.18u)\nVdd Vdd 0 PULSE(0 1.2 0n 100p 100p 10n 20n)\nVchallenge V_challenge 0 PULSE(0 1.2 1n 100p 100p 40n 80n)\n* Access transistor\nMX1 net_mid V_challenge Vdd Vdd PMOS_ACC\n \n* Cross-coupled PMOS\nMX2 response       net_mid Vdd Vdd PMOS1\nMX3 response_comp  net_mid Vdd Vdd PMOS2\n \n* Cross-coupled NMOS\nMX4 net_mid response       0 0 NMOS1\nMX5 net_mid response_comp 0 0 NMOS2\n.tran 0.1n 50n\n.step param seed 1 10 1\n.options post\n.meas response_val        FIND V(response)        AT=25n\n.meas response_val_comp   FIND V(response_comp)   AT=25n\n.meas digital_response       param 'V(response) > 0.6'\n.meas digital_response_comp  param 'V(response_comp) > 0.6'