* Z:\home\khalils\Downloads\files\data\raw_asc\AD4030-24.asc
* Generated by LTspice 26.0.1 for Windows.
* IN+, IN-: Analog inputs. Transients from sampling caps are simulated. Input range is +/-VREF
* REF: For 5V VREF VDD should be 5.4V +/-100mV
* VDD: For REF=4.096V VDD=4.75V to 5.25V For REF=4.5V VDD= 4.8V to 5.25V
* Digital Out: Digital representation of output. +/-2^23 This can be used to drive DAC inputs
* Vout: Analog output +/-VREF
* CNV: 2MHz max 0V-1.8V logic level
* RSTn: Resets ADC. Tie to 1.8V for normal operation
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4030-24.asy)
Cfilt1 IN+ 0 1n
V7 REF 0 5
XU1 IN+ N001 0 Vout REF CNV IN- _RST vOrto Busy AD4030-24 ;pnba IN+)VDD)GND)VOrti)REF)CNV)IN-)_RST)VOrto)Busy
V3 CNV 0 PULSE(0 1.8 500n .2n .2n 19.8n 500n)
V8 N001 0 5.4
R1 Vout 0 10k
Rfilt2 IN- input- 33
VinP input+ 0 SINE(2.5 2 2k)
Cfilt2 0 IN- 1n
Rfilt1 input+ IN+ 33
VinN input- 0 SINE(2.5 2 2k 0 0 180)
V4 _RST 0 PWL(0 0 1n 0 2n 1.8)
.tran 0 2m
.lib AD4030-24.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 12540 5124
WIRE 10576 3040 10480 3040
WIRE 10672 3040 10576 3040
WIRE 10672 3072 10672 3040
WIRE 10480 3168 10480 3040
WIRE 9552 3184 9456 3184
WIRE 9776 3184 9552 3184
WIRE 9888 3184 9856 3184
WIRE 10016 3184 9888 3184
WIRE 10672 3184 10672 3152
WIRE 9456 3200 9456 3184
WIRE 9888 3216 9888 3184
WIRE 10960 3216 10608 3216
WIRE 10960 3248 10960 3216
WIRE 10640 3264 10608 3264
WIRE 10016 3296 10016 3184
WIRE 10128 3296 10016 3296
WIRE 10256 3296 10128 3296
WIRE 9456 3312 9456 3280
WIRE 9456 3312 9424 3312
WIRE 10672 3312 10608 3312
WIRE 10720 3312 10672 3312
WIRE 10816 3312 10800 3312
WIRE 9888 3328 9888 3280
WIRE 9920 3328 9888 3328
WIRE 10128 3328 10016 3328
WIRE 10256 3328 10128 3328
WIRE 9456 3344 9456 3312
WIRE 9888 3360 9888 3328
WIRE 10640 3360 10608 3360
WIRE 10960 3360 10960 3328
WIRE 10304 3408 10304 3376
WIRE 10784 3408 10608 3408
WIRE 10960 3408 10784 3408
WIRE 10960 3440 10960 3408
WIRE 9456 3456 9456 3424
WIRE 9552 3456 9456 3456
WIRE 9776 3456 9552 3456
WIRE 9888 3456 9888 3424
WIRE 9888 3456 9856 3456
WIRE 10016 3456 10016 3328
WIRE 10016 3456 9888 3456
WIRE 10304 3456 10304 3408
WIRE 10480 3472 10480 3456
WIRE 10304 3568 10304 3536
WIRE 10960 3568 10960 3520
SYMBOL res 9872 3440 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt2
SYMATTR Value 33
SYMBOL voltage 10304 3440 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PWL(0 0 1n 0 2n 1.8)
SYMBOL voltage 9456 3440 R180
WINDOW 0 74 12 Right 2
WINDOW 3 -45 59 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VinN
SYMATTR Value SINE(2.5 2 2k 0 0 180)
SYMBOL cap 9872 3360 R0
SYMATTR InstName Cfilt2
SYMATTR Value 1n
SYMBOL res 10704 3328 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage 10960 3424 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -456 100 Left 2
SYMATTR Value PULSE(0 1.8 500n .2n .2n 19.8n 500n)
SYMATTR InstName V3
SYMBOL voltage 10672 3056 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V7
SYMATTR Value 5
SYMBOL voltage 10960 3232 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value 5.4
SYMBOL cap 9872 3216 R0
SYMATTR InstName Cfilt1
SYMATTR Value 1n
SYMBOL res 9760 3168 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt1
SYMATTR Value 33
SYMBOL AD4030-24 10512 3312 R0
SYMATTR InstName U1
SYMBOL voltage 9456 3184 R0
WINDOW 0 -17 7 Right 2
WINDOW 3 202 66 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VinP
SYMATTR Value SINE(2.5 2 2k)
FLAG 9424 3312 0
FLAG 9552 3184 input+
FLAG 9552 3456 input-
FLAG 9920 3328 0
FLAG 10960 3568 0
FLAG 10304 3568 0
FLAG 10672 3184 0
FLAG 10960 3360 0
FLAG 10480 3472 0
FLAG 10816 3312 0
FLAG 10128 3296 IN+
FLAG 10128 3328 IN-
FLAG 10672 3312 Vout
FLAG 10784 3408 CNV
FLAG 10304 3408 _RST
FLAG 10576 3040 REF
FLAG 10640 3264 vOrto
FLAG 10640 3360 Busy
TEXT 10792 3632 Left 2 !.tran 0 2m
TEXT 9472 2856 Left 2 ;IN+, IN-: Analog inputs. Transients from sampling caps are simulated. Input range is +/-VREF
TEXT 9528 2888 Left 2 ;REF: For 5V VREF VDD should be 5.4V +/-100mV
TEXT 9520 2920 Left 2 ;VDD: For REF=4.096V VDD=4.75V to 5.25V For REF=4.5V VDD= 4.8V to 5.25V
TEXT 9448 2952 Left 2 ;Digital Out: Digital representation of output. +/-2^23 This can be used to drive DAC inputs
TEXT 9520 2984 Left 2 ;Vout: Analog output +/-VREF
TEXT 9520 3016 Left 2 ;CNV: 2MHz max 0V-1.8V logic level
TEXT 9512 3048 Left 2 ;RSTn: Resets ADC. Tie to 1.8V for normal operation