Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8572.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8572.asy)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -2.5
XU1 IN N001 +V -V OUT AD8572 ;pnba In+)In-)V+)V-)OUT
Vin IN 0 SINE(0 1 10K)
V1 +V 0 2.5
Rload OUT 0 10K
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 160 -1136 160 -1152
WIRE 272 -1136 272 -1152
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 160 -1040 160 -1056
WIRE 272 -1040 272 -1056
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL Opamps\\AD8572 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 272 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 160 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 752 -992 0
FLAG 160 -1152 +V
FLAG 160 -1040 0
FLAG 272 -1152 -V
FLAG 272 -1040 0
TEXT 696 -928 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1878.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1878.asy)
R1 OUT N002 887K
C1 N003 0 220p
XU1 IN N003 N002 0 N001 IN IN LTC1878 ;pnba Run)Ith)FB)GND)SW)Vin)Mode
C2 OUT 0 47
L1 N001 OUT 10
C3 OUT N002 20p
V1 IN 0 5
Rload OUT 0 10
R2 N002 0 280K
.tran 750u startup
.lib LTC1878.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1084 700
WIRE 176 64 48 64
WIRE 352 64 176 64
WIRE 48 80 48 64
WIRE 352 80 352 64
WIRE 544 112 512 112
WIRE 656 112 624 112
WIRE 752 112 656 112
WIRE 880 112 752 112
WIRE 992 112 880 112
WIRE 656 128 656 112
WIRE 752 128 752 112
WIRE 880 128 880 112
WIRE 992 128 992 112
WIRE 176 144 176 64
WIRE 208 144 176 144
WIRE 512 144 512 112
WIRE 512 144 496 144
WIRE 48 176 48 160
WIRE 656 224 656 192
WIRE 656 224 496 224
WIRE 752 224 752 208
WIRE 752 224 656 224
WIRE 880 224 880 192
WIRE 992 224 992 208
WIRE 752 240 752 224
WIRE 176 304 176 144
WIRE 208 304 176 304
WIRE 512 304 496 304
WIRE 592 304 576 304
WIRE 752 336 752 320
WIRE 352 400 352 368
SYMBOL polcap 864 128 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMBOL ind 528 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL cap 512 320 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 220p
SYMBOL res 736 224 R0
SYMATTR InstName R2
SYMATTR Value 280K
SYMBOL res 976 112 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL POWERPRODUCTS\\LTC1878 352 224 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 48 64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 640 128 R0
SYMATTR InstName C3
SYMATTR Value 20p
SYMBOL RES 736 112 R0
SYMATTR InstName R1
SYMATTR Value 887K
FLAG 48 176 0
FLAG 352 400 0
FLAG 592 304 0
FLAG 880 224 0
FLAG 752 336 0
FLAG 992 224 0
FLAG 992 112 OUT
FLAG 48 64 IN
TEXT 808 400 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\13492e62e963_current_gain.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
V2 N005 0 -15
R1 0 N001 1k
R2 N001 N003 10k
V1 N002 0 15
XU1 N004 N001 N002 N005 N003 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V3 N004 0 10m
.tran 100ms
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 0 48 0
WIRE 224 0 64 0
WIRE 224 32 224 0
WIRE 144 144 144 112
WIRE 64 160 64 0
WIRE 112 160 64 160
WIRE 224 176 224 112
WIRE 224 176 176 176
WIRE 288 176 224 176
WIRE 112 192 64 192
WIRE 64 240 64 192
WIRE 64 240 48 240
WIRE 144 240 144 208
SYMBOL voltage 64 240 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 10m
SYMBOL res -48 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL Opamps\\UniversalOpamp2 144 176 R0
SYMATTR InstName U1
SYMBOL voltage 144 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 144 128 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 208 16 R0
SYMATTR InstName R2
SYMATTR Value 10k
FLAG -32 240 0
FLAG 144 320 0
FLAG 144 32 0
FLAG -32 0 0
TEXT -52 344 Left 2 !.tran 100ms
* Z:\home\khalils\Downloads\files\data\raw_asc\166c3f2ffea1_1.2.2.asc
* Generated by LTspice 26.0.1 for Windows.
Vi N003 0 PULSE(0 5 0 50us 50us 0 100us)
VCC N001 0 5
Rb N004 N003 1K
Rc N002 N001 1K
Q1 N002 N004 0 0 2N2222
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 400us
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 544 -128 368 -128
WIRE 368 -32 368 -48
WIRE 368 -32 336 -32
WIRE 336 128 336 -32
WIRE 544 128 544 -128
WIRE 112 176 -16 176
WIRE 272 176 192 176
WIRE -16 272 -16 176
WIRE -16 496 -16 352
WIRE 336 496 336 224
WIRE 336 496 -16 496
WIRE 544 496 544 208
WIRE 544 496 336 496
WIRE 336 528 336 496
FLAG 336 528 0
SYMBOL voltage -16 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vi
SYMATTR Value PULSE(0 5 0 50us 50us 0 100us)
SYMBOL voltage 544 112 R0
SYMATTR InstName VCC
SYMATTR Value 5
SYMBOL res 208 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rb
SYMATTR Value 1K
SYMBOL res 384 -32 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Rc
SYMATTR Value 1K
SYMBOL npn 272 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
TEXT -50 552 Left 2 !.tran 400us
* Z:\home\khalils\Downloads\files\data\raw_asc\29aa4a5afab5_Q1.asc
* Generated by LTspice 26.0.1 for Windows.
M2 N001 N002 0 0 nch_tt l=180n w=240n
C1 N001 0 1p IC=1.8
Vdd N002 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.tran 30ns
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 688 32 416 32
WIRE 416 112 416 32
WIRE 688 144 688 32
WIRE 368 192 160 192
WIRE 160 240 160 192
WIRE 160 448 160 320
WIRE 416 448 416 208
WIRE 416 448 160 448
WIRE 688 448 688 208
WIRE 688 448 416 448
WIRE 416 480 416 448
SYMBOL cap 672 144 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMATTR SpiceLine IC=1.8
SYMBOL voltage 160 224 R0
SYMATTR InstName Vdd
SYMATTR Value 1.8
SYMBOL nmos 368 112 R0
SYMATTR InstName M2
SYMATTR Value nch_tt
SYMATTR Value2 l=180n w=240n
FLAG 416 480 0
TEXT -136 176 Left 2 !.include TSMC180.lib
TEXT -82 216 Left 2 !.tran 30ns
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2139-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2139-1.8.asy)
XU1 IN IN N001 OUT 0 IN ADP2139-x.x Rtop=208K ;pnba Vin)EN)SW)Vout)GND)Mode
Rload OUT 0 3
V1 IN 0 5
L1 N001 OUT 1 Rser=60m
C1 OUT 0 10
.tran .5m startup
.lib ADP2139-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 3
SYMBOL ADP2139-1.8 352 224 R0
SYMATTR InstName U1
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 600 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1995.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N002 NC_01 NC_02 -V 0 OUT +V NC_03 NC_04 N001 LT1995 ;pnba P1)P2)P4)Vee)Ref)OUT)VCC)M4)M2)M1
V1 +V 0 +15
V2 -V 0 -15
V3 N001 N002 PULSE(-1 1 0 1n 1n .5u 1u)
.tran 3u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1995.asy)
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 48 -256 48
WIRE 400 48 352 48
WIRE 96 64 96 48
WIRE 272 64 272 48
WIRE 352 64 352 48
WIRE -496 144 -496 128
WIRE -384 144 -384 128
WIRE -256 144 -256 48
WIRE -496 240 -496 224
WIRE -384 240 -384 224
WIRE -256 336 -256 224
WIRE 96 336 96 320
WIRE 96 336 -256 336
WIRE 272 336 272 320
WIRE 352 352 352 320
FLAG 352 352 0
FLAG 272 48 +V
FLAG 272 336 -V
FLAG -496 128 +V
FLAG -496 240 0
FLAG -384 240 0
FLAG -384 128 -V
FLAG 400 48 OUT
SYMBOL opamps\\LT1995 272 192 R0
SYMATTR InstName U1
SYMBOL voltage -496 128 R0
SYMATTR InstName V1
SYMATTR Value +15
SYMBOL voltage -384 128 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -256 128 R0
WINDOW 0 14 8 Left 2
WINDOW 3 15 104 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 1n 1n .5u 1u)
TEXT 400 296 Left 2 !.tran 3u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3204-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3204-3.3.asy)
XU1 0 IN OUT N001 N002 IN LTC3204-3.3 ;pnba GND)Vin)Vout)C+)C-)_SHDN
C1 N001 N002 2.2
Rload OUT 0 100
V1 IN 0 2.4
C2 OUT 0 2.2
.tran 1m startup
.lib LTC3204-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 160 -96 160
WIRE 16 160 0 160
WIRE 384 160 272 160
WIRE 480 160 384 160
WIRE -96 176 -96 160
WIRE 384 176 384 160
WIRE 480 176 480 160
WIRE 0 240 0 160
WIRE 16 240 0 240
WIRE 304 240 272 240
WIRE 384 272 384 240
WIRE 480 272 480 256
WIRE -96 288 -96 256
WIRE 16 320 0 320
WIRE 304 320 304 304
WIRE 304 320 272 320
SYMBOL res 464 160 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL PowerProducts\\LTC3204-3.3 144 240 R0
SYMATTR InstName U1
SYMBOL voltage -96 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.4
SYMBOL cap 288 240 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL cap 368 176 R0
SYMATTR InstName C2
SYMATTR Value 2.2
FLAG 384 272 0
FLAG 480 272 0
FLAG 0 320 0
FLAG -96 288 0
FLAG -96 160 IN
FLAG 480 160 OUT
TEXT 384 320 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\7db40aa0e673_E3d.asc
* Generated by LTspice 26.0.1 for Windows.
;ac dec 10 1 10Meg
RD N001 Vout 8000
M2 Vout N002 N004 N003 NMOS l=0.36u w=18u
VB N002 0 1.1
VDD N001 0 3.3
VIN N005 0 0.6 AC 1
M1 N004 N005 0 N006 NMOS l=0.18u w=18u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VIN 0 3.3 0.001
.model NMOS NMOS (LEVEL=1 KP=150u VTO=0.5 LAMBDA=0 GAMMA=0 PHI=0.6)
.meas DC Av_0p6 FIND deriv(V(vout))/deriv(V(vin)) WHEN V(vout)=0.6
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 892 680
WIRE 96 -256 -64 -256
WIRE 96 -128 96 -176
WIRE 96 -96 96 -128
WIRE 48 -16 -48 -16
WIRE 96 -16 96 -48
WIRE 96 32 96 0
WIRE 48 112 -48 112
WIRE 96 112 96 80
IOPIN 96 -128 Out
SYMBOL res 80 -272 R0
SYMATTR InstName RD
SYMATTR Value 8000
SYMBOL nmos4 48 -96 R0
SYMATTR InstName M2
SYMATTR Value2 l=0.36u w=18u
SYMBOL voltage -48 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName VIN
SYMATTR Value 0.6
SYMBOL voltage -64 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 3.3
SYMBOL nmos4 48 32 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.18u w=18u
SYMBOL voltage -48 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VB
SYMATTR Value 1.1
FLAG 96 128 0
FLAG -48 64 0
FLAG -48 192 0
FLAG -64 -176 0
FLAG 96 -128 Vout
TEXT -88 -384 Left 2 !.dc VIN 0 3.3 0.001
TEXT -88 -360 Left 2 !;ac dec 10 1 10Meg
TEXT -88 -336 Left 2 !.model NMOS NMOS (LEVEL=1 KP=150u VTO=0.5 LAMBDA=0 GAMMA=0 PHI=0.6)
TEXT -88 -312 Left 2 !.meas DC Av_0p6 FIND deriv(V(vout))/deriv(V(vin)) WHEN V(vout)=0.6
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1007A.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain 1000 Amplifier with .01% Accuracy
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1007A.asy)
V3 IN 0 SINE(0 1m .01)
R1 OUT N001 355K
R2 N001 0 365
XU1 IN N001 +V -V OUT LT1007 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
V2 -V 0 -15
.tran 300
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 160 96 128 96
WIRE 272 96 240 96
WIRE -272 176 -272 160
WIRE -144 176 -144 160
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 272 240 272 96
WIRE 272 240 224 240
WIRE 304 240 272 240
WIRE 160 256 0 256
WIRE -272 272 -272 256
WIRE -144 272 -144 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 365
SYMBOL opamps\\LT1007A 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -272 160 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -144 160 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 355K
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1m .01)
FLAG -144 272 0
FLAG 192 192 +V
FLAG -144 160 +V
FLAG 192 288 -V
FLAG -272 272 0
FLAG -272 160 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 304 240 OUT
FLAG 0 256 IN
TEXT 272 424 Left 2 !.tran 300
TEXT 136 8 Bottom 2 ;Gain 1000 Amplifier with .01% Accuracy
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3001.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3001.asy)
C1 OUT 0 100 V=10 Irms=2.2 Rser=0.025 Lser=0 mfg="KEMET" pn="T520V107M010ASE025" type="Tantalum"
K1 L1 L2 1
L1 IN N002 40 Rser=500m Cpar=1p
V1 IN 0 24
Rload OUT 0 5
R3 N002 N003 154K
D1 N001 OUT MBRS360
L2 0 N001 4.4 Rser=20m Cpar=.2p
XU1 IN 0 N003 N002 IN LT3001 ;pnba EN/UVLO)GND)RFB)SW)Vin
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LT3001.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 48 16 -48 16
WIRE 416 16 48 16
WIRE 560 16 464 16
WIRE 688 16 624 16
WIRE 784 16 688 16
WIRE -48 32 -48 16
WIRE 416 32 416 16
WIRE 464 32 464 16
WIRE 688 32 688 16
WIRE 784 32 784 16
WIRE -48 128 -48 112
WIRE 464 128 464 112
WIRE 688 128 688 96
WIRE 784 128 784 112
WIRE 48 144 48 16
WIRE 96 144 48 144
WIRE 416 144 416 112
WIRE 416 144 320 144
WIRE 416 176 416 144
WIRE 48 272 48 144
WIRE 96 272 48 272
WIRE 416 272 416 256
WIRE 416 272 320 272
WIRE 208 336 208 320
SYMBOL res 400 160 R0
SYMATTR InstName R3
SYMATTR Value 154K
SYMBOL LT3001 208 208 R0
SYMATTR InstName U1
SYMBOL polcap 672 32 R0
WINDOW 3 24 56 Left 2
SYMATTR Value 100
SYMATTR InstName C1
SYMATTR SpiceLine V=10 Irms=2.2 Rser=0.025 Lser=0 mfg="KEMET" pn="T520V107M010ASE025" type="Tantalum"
SYMATTR Description Capacitor
SYMATTR Type cap
SYMBOL voltage -48 16 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 768 16 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL ind2 480 128 R180
WINDOW 0 -4 72 Right 2
WINDOW 3 -1 33 Right 2
SYMATTR InstName L2
SYMATTR Value 4.4
SYMATTR Type ind
SYMATTR SpiceLine Rser=20m Cpar=.2p
SYMBOL ind2 400 16 R0
WINDOW 0 0 39 Right 2
WINDOW 3 0 77 Right 2
SYMATTR InstName L1
SYMATTR Value 40
SYMATTR Type ind
SYMATTR SpiceLine Rser=500m Cpar=1p
SYMBOL schottky 560 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMATTR Description Diode
SYMATTR Type diode
FLAG 208 336 0
FLAG -48 128 0
FLAG -48 16 IN
FLAG 464 128 0
FLAG 688 128 0
FLAG 784 128 0
FLAG 784 16 OUT
TEXT 440 8 Bottom 2 !K1 L1 L2 1
TEXT 560 312 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1469.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1469.asy)
V3 N003 0 SINE(0 1 1K)
R2 N001 0 1K
V2 -V 0 -15
V1 +V 0 15
R1 N002 N001 1K
XU1 N003 N001 +V -V N002 LT1468 ;pnba In+)In-)V+)V-)OUT
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -288 144 -288 128
WIRE -160 144 -160 128
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -288 240 -288 224
WIRE -160 240 -160 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL opamps\\LT1469 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -160 128 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -288 128 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
FLAG -160 240 0
FLAG 192 192 +V
FLAG -160 128 +V
FLAG 192 288 -V
FLAG -288 240 0
FLAG -288 128 -V
FLAG 16 96 0
FLAG 0 368 0
TEXT 240 352 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
V1 IN 0 3.3
Rload OUT 0 50
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-5.0 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
.tran 400u startup
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-5.0.asy)
.lib ADP2504-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2504-5.0 176 176 R0
SYMATTR InstName U1
TEXT 392 384 Left 2 !.tran 400u startup
TEXT 176 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-3.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-3.5.asy)
V1 IN 0 3.3
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-3.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
Rload OUT 0 50
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
.tran 400u startup
.lib ADP2503-3.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ADP2503-3.5 176 176 R0
SYMATTR InstName U1
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 424 376 Left 2 !.tran 400u startup
TEXT 168 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7104-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7104-5.0.asy)
XU1 IN OUT IN N001 OUT 0 ADP7104-5.0 ;pnba Vin)Sense)EN)PG)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
Rload OUT 0 15
V1 IN 0 PWL(0 0 20u 6)
R1 OUT N001 100k
.tran 3m startup
.lib ADP7104-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -128 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -128 48 -128 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -128 144 -128 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL ADP7104-5.0 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 20u 6)
FLAG 224 304 0
FLAG -128 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -128 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup