Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\034a2c45fe7e_Draft14.asc
* Generated by LTspice 26.0.1 for Windows.
;tran 100m
R Vout 0 220 tol=1 pwr=0.1
C Vout Vin 3.3
Vi Vin 0 AC 1
.ac dec 100 10 1000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 80 64 80
WIRE 176 80 128 80
WIRE 288 80 240 80
WIRE 336 80 288 80
WIRE 64 144 64 80
WIRE 336 144 336 80
WIRE 64 240 64 224
WIRE 336 240 336 224
WIRE 336 240 64 240
WIRE 64 256 64 240
SYMBOL cap 240 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C
SYMATTR Value 3.3u
SYMBOL res 320 128 R0
SYMATTR InstName R
SYMATTR Value 220
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL voltage 64 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vi
SYMATTR Value ""
SYMATTR Value2 AC 1
FLAG 64 256 0
FLAG 128 80 Vin
FLAG 288 80 Vout
TEXT 30 280 Left 2 !;tran 100m
TEXT 152 256 Left 2 !.ac dec 100 10 1000
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-3.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-3.5.asy)
Rload OUT 0 50
V1 IN 0 3.3
C1 OUT 0 10
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-3.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
L1 N001 N002 1.5 Rser=80m
.tran 400u startup
.lib ADP2504-3.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 384 224 320 224
WIRE 496 224 384 224
WIRE 384 240 384 224
WIRE 496 240 496 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 384 336 384 304
WIRE 496 336 496 320
SYMBOL ADP2504-3.5 176 176 R0
SYMATTR InstName U1
SYMBOL cap 368 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL res 480 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 384 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 496 336 0
FLAG 496 224 OUT
FLAG -64 64 IN
TEXT 432 376 Left 2 !.tran 400u startup
TEXT 192 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\2b3e4cffba17_Integrator.asc
* Generated by LTspice 26.0.1 for Windows.
C1 Vout N001 1
V1 N002 0 SINE(2 2 1 0 0 0 0)
R1 N001 N002 1
XU1 N001 0 Vout opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
.lib opamp.sub
.tran 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 112 176 112
WIRE 320 112 288 112
WIRE 64 192 16 192
WIRE 176 192 176 112
WIRE 176 192 144 192
WIRE 208 192 176 192
WIRE 320 208 320 112
WIRE 320 208 272 208
WIRE 384 208 320 208
WIRE 208 224 176 224
WIRE 16 240 16 192
WIRE 16 352 16 320
WIRE 176 352 176 224
WIRE 176 352 16 352
WIRE 16 368 16 352
SYMBOL res 160 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage 16 224 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value SINE(2 2 1 0 0 0 0)
SYMATTR InstName V1
SYMBOL cap 288 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL Opamps\\opamp 240 144 R0
SYMATTR InstName U1
FLAG 16 368 0
FLAG 384 208 Vout
TEXT -112 24 Left 2 !.lib opamp.sub
TEXT -112 392 Left 2 !.tran 10
* Z:\tmp\asc_dec_bjh7r6w2\13201ff6b543_pad_buffer_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
AX1 N007 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac * fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac * fac* fac * fac* fac * fac }
AX6 N008 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac } wp={wpad * mp * fac* fac }
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1168 680
WIRE 48 224 -16 224
WIRE 144 224 48 224
WIRE 240 224 144 224
WIRE 336 224 240 224
WIRE 432 224 336 224
WIRE 528 224 432 224
WIRE 624 224 528 224
WIRE 720 224 624 224
WIRE 48 304 48 224
WIRE 144 304 144 224
WIRE 240 304 240 224
WIRE 336 304 336 224
WIRE 432 304 432 224
WIRE 528 304 528 224
WIRE 624 304 624 224
WIRE 720 304 720 224
WIRE 32 320 -16 320
WIRE 128 320 80 320
WIRE 224 320 176 320
WIRE 416 320 368 320
WIRE 512 320 464 320
WIRE 608 320 560 320
WIRE 704 320 656 320
WIRE 48 432 48 336
WIRE 48 432 -16 432
WIRE 144 432 144 336
WIRE 144 432 48 432
WIRE 240 432 240 336
WIRE 240 432 144 432
WIRE 336 432 336 336
WIRE 336 432 240 432
WIRE 432 432 432 336
WIRE 432 432 336 432
WIRE 528 432 528 336
WIRE 528 432 432 432
WIRE 624 432 624 336
WIRE 624 432 528 432
WIRE 720 432 720 336
WIRE 720 432 624 432
SYMBOL inv 48 320 R0
SYMATTR InstName X1
SYMATTR SpiceLine wn={wpad* fac * fac * fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac * fac* fac * fac* fac * fac }
SYMBOL inv 528 320 R0
SYMATTR InstName X6
SYMATTR SpiceLine wn={wpad* fac * fac } wp={wpad * mp * fac* fac }
FLAG -16 224 vdd
FLAG -16 320 in
FLAG -16 432 vss
* Z:\home\khalils\Downloads\files\data\raw_asc\0bfadf1a75fb_balance_inductance_v2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XL2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Contrib\Wurth\EMC-Components\CommonModeChokes\WE-CMB.asy)
D1 N002 N003 1N5817
V1 N006 0 PULSE(0 18 0 0 0 0.001 0.003)
C2 N005 0 99000 Rser=0.2,IC=3.3
M1 N005 N006 N001 N001 BSB012N03LX3
XL2 0 0 N004 N002 XS_744821201_1m ;pnba 1)2)4)3
R1 N001 N004 1.5
C5 N003 0 99000 Rser=0.2,IC=0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100
.lib Contrib/Wurth/WE-CMB.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1372 852
WIRE 736 -368 464 -368
WIRE 1008 -352 832 -352
WIRE 1200 -352 1072 -352
WIRE 736 -304 736 -368
WIRE 736 -176 736 -224
WIRE 832 -176 832 -352
WIRE 1200 -64 1200 -352
WIRE 272 -48 -16 -48
WIRE 464 -48 464 -368
WIRE 464 -48 368 -48
WIRE -16 -16 -16 -48
WIRE 352 48 352 0
WIRE -16 272 -16 48
WIRE 352 272 352 128
WIRE 352 272 -16 272
WIRE 736 272 736 16
WIRE 736 272 352 272
WIRE 832 272 832 16
WIRE 832 272 736 272
WIRE 1200 272 1200 0
WIRE 1200 272 832 272
WIRE -16 320 -16 272
SYMBOL res 720 -320 R0
SYMATTR InstName R1
SYMATTR Value 1.5
SYMBOL voltage 352 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 18 0 0 0 0.001 0.003)
SYMBOL nmos 272 0 R270
SYMATTR InstName M1
SYMATTR Value BSB012N03LX3
SYMBOL cap -32 -16 R0
SYMATTR InstName C2
SYMATTR Value 99000
SYMATTR SpiceLine Rser=0.2,IC=3.3
SYMBOL cap 1184 -64 R0
SYMATTR InstName C5
SYMATTR Value 99000
SYMATTR SpiceLine Rser=0.2,IC=0
SYMBOL schottky 1008 -368 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N5817
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL Contrib\\Wurth\\EMC-Components\\CommonModeChokes\\WE-CMB 784 -80 R270
SYMATTR InstName L2
FLAG -16 320 0
TEXT -40 616 Left 2 !.tran 100
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1762-0.9.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1762-0.9.asy)
C2 N003 0 10n
C4 OUT 0 10
V1 IN 0 1.1
C3 N002 0 1
R1 OUT 0 .6
C1 N004 0 1
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1762 Radj=6K ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
R2 N001 IN 50K
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL voltage -128 -32 R0
SYMATTR InstName V1
SYMATTR Value 1.1
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP1762-0.9 224 176 R0
SYMATTR InstName U1
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 432 384 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1179.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
R1 N002 N001 10K
R2 N001 0 10K
V3 N003 0 SINE(1.25 .1 1K)
XU1 N003 N001 +V -V N002 LT1178 ;pnba In+)In-)V+)V-)OUT
.tran 3m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1179.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -160 160 -160 144
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE -160 256 -160 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
FLAG -160 256 0
FLAG 192 192 +V
FLAG -160 144 +V
FLAG 192 288 -V
FLAG 16 96 0
FLAG 0 368 0
SYMBOL voltage -160 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(1.25 .1 1K)
SYMBOL opamps\\LT1179 192 176 R0
SYMATTR InstName U1
TEXT 248 360 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\3ef7bf86a0eb_exam5_06_NPN.asc
* Generated by LTspice 26.0.1 for Windows.
RC N001 VO 5k
RB N002 VI 150k
VCC N001 0 5
Q1 VO N002 0 0 2N3904
VI VI 0 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc VI 0 5 .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 -16 -128 -16
WIRE 272 0 272 -16
WIRE 272 112 272 80
WIRE 400 112 272 112
WIRE 272 128 272 112
WIRE 96 176 16 176
WIRE 208 176 176 176
WIRE -128 208 -128 -16
WIRE 16 208 16 176
WIRE -128 368 -128 288
WIRE 16 368 16 288
WIRE 16 368 -128 368
WIRE 272 368 272 224
WIRE 272 368 16 368
WIRE 16 400 16 368
IOPIN 400 112 Out
IOPIN 16 176 Out
SYMBOL voltage -128 192 R0
WINDOW 0 -21 55 Left 2
WINDOW 3 12 7 Left 2
SYMATTR InstName VCC
SYMATTR Value 5
SYMBOL res 256 -16 R0
SYMATTR InstName RC
SYMATTR Value 5k
SYMBOL npn 208 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 192 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RB
SYMATTR Value 150k
SYMBOL voltage 16 192 R0
SYMATTR InstName VI
SYMATTR Value 0
FLAG 16 400 0
FLAG 400 112 VO
FLAG 16 176 VI
TEXT -88 24 Left 2 !.dc VI 0 5 .01
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3311-0.85.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3311-0.85.asy)
R5 N006 0 274K
Rload OUT 0 0.142
XU1 IN IN N002 OUT 0 0 N006 N001 IN N005 N003 LTC3311-0.85 ;pnba Vin)EN)SW)OUT)Agnd)Pgnd)Rt)Pgood)Mode/Sync)Ith)SSTT
C1 OUT 0 47 x2
C2 N003 0 3.3n
C3 N004 0 330p
R3 OUT N001 500K
V1 IN 0 3.3
L1 N002 OUT 80n Rser=2m
R4 N005 N004 4.99k
.tran .4m startup
.lib LTC3311-0.85.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2648 1864
WIRE 1536 1248 1376 1248
WIRE 1712 1248 1536 1248
WIRE 1376 1264 1376 1248
WIRE 1712 1280 1712 1248
WIRE 1536 1328 1536 1248
WIRE 1552 1328 1536 1328
WIRE 1904 1328 1872 1328
WIRE 2016 1328 1984 1328
WIRE 1376 1360 1376 1344
WIRE 1536 1424 1536 1328
WIRE 1552 1424 1536 1424
WIRE 1904 1424 1872 1424
WIRE 2016 1424 2016 1328
WIRE 2016 1424 1984 1424
WIRE 2096 1424 2016 1424
WIRE 2208 1424 2096 1424
WIRE 2096 1440 2096 1424
WIRE 2208 1440 2208 1424
WIRE 1472 1520 1456 1520
WIRE 1552 1520 1536 1520
WIRE 2016 1520 2016 1424
WIRE 2016 1520 1872 1520
WIRE 2096 1536 2096 1504
WIRE 2208 1536 2208 1520
WIRE 1424 1616 1360 1616
WIRE 1552 1616 1504 1616
WIRE 1904 1616 1872 1616
WIRE 1360 1632 1360 1616
WIRE 1904 1632 1904 1616
WIRE 1648 1680 1648 1664
WIRE 1776 1680 1776 1664
WIRE 1360 1712 1360 1696
WIRE 1904 1728 1904 1712
SYMBOL res 2192 1424 R0
SYMATTR InstName Rload
SYMATTR Value 0.142
SYMBOL res 2000 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500K
SYMBOL LTC3311-0.85 1712 1456 R0
SYMATTR InstName U1
SYMBOL cap 2080 1440 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 x2
SYMATTR InstName C1
SYMATTR Value 47
SYMBOL res 1888 1616 R0
SYMATTR InstName R5
SYMATTR Value 274K
SYMBOL cap 1536 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 3.3n
SYMBOL res 1520 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 4.99k
SYMBOL ind 1888 1440 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 80n
SYMATTR SpiceLine Rser=2m
SYMBOL VOLTAGE 1376 1248 R0
SYMATTR Value 3.3
SYMATTR InstName V1
SYMBOL cap 1344 1632 R0
SYMATTR InstName C3
SYMATTR Value 330p
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1376 1360 0
FLAG 2208 1536 0
FLAG 1456 1520 0
FLAG 2208 1424 OUT
FLAG 1376 1248 IN
FLAG 1360 1712 0
FLAG 2096 1536 0
FLAG 1904 1728 0
TEXT 2048 1616 Left 2 !.tran .4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1047.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
R1 N002 N001 220K
R2 N001 IN 220K
V3 IN 0 SINE(0 1 1K)
XU1 0 N001 +V 0 N003 LTC1047 ;pnba In+)In-)V+)V-)OUT
D1 N003 N002 1N4148
XU2 N002 OUT +V 0 OUT LTC1047 ;pnba In+)In-)V+)V-)OUT
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m
* Precise DC Full-Wave Rectifier(Absolute Value Circuit)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1047.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 576 128 464 128
WIRE 32 144 -112 144
WIRE 128 144 112 144
WIRE 256 144 128 144
WIRE 432 144 336 144
WIRE -112 160 -112 144
WIRE -224 176 -224 160
WIRE 512 192 512 176
WIRE 192 208 192 192
WIRE 464 208 464 128
WIRE 480 208 464 208
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 576 224 576 128
WIRE 576 224 544 224
WIRE 608 224 576 224
WIRE 352 240 224 240
WIRE 432 240 432 144
WIRE 432 240 416 240
WIRE 480 240 432 240
WIRE -112 256 -112 240
WIRE 160 256 128 256
WIRE -224 272 -224 256
WIRE 512 272 512 256
WIRE 192 288 192 272
FLAG -224 272 0
FLAG 192 192 +V
FLAG -224 160 +V
FLAG -112 256 0
FLAG 192 288 0
FLAG 512 176 +V
FLAG 512 272 0
FLAG 128 256 0
FLAG 608 224 OUT
FLAG -112 144 IN
SYMBOL voltage -224 160 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 352 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 220K
SYMBOL res 128 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 220K
SYMBOL voltage -112 144 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL opamps\\LTC1047 192 176 R0
SYMATTR InstName U1
SYMBOL diode 352 256 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL opamps\\LTC1047 512 160 R0
SYMATTR InstName U2
TEXT 544 320 Left 2 !.tran 3m
TEXT 200 88 Bottom 2 ;Precise DC Full-Wave Rectifier(Absolute Value Circuit)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG821.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 1 input.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG821.asy)
VS N001 0 3
V1 +V 0 5
R1 N002 0 47
V2 N003 0 PULSE(0 2.4 0 10n 10n 980n 2u)
XU1 +V N003 NC_01 N001 N002 NC_02 NC_03 0 ADG821 ;pnba VDD)IN1)IN2)S1)D1)S2)D2)GND
C1 N002 0 33p
.tran 10u
.lib ADG821.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -432 -16 -464 -16
WIRE -256 -16 -352 -16
WIRE 0 -16 -32 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE 112 32 112 -16
WIRE -256 48 -432 48
WIRE -592 112 -592 64
WIRE -432 112 -432 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -592 272 -592 192
WIRE -432 272 -432 192
WIRE -144 336 -144 304
SYMBOL ADG821 -144 32 R0
SYMATTR InstName U1
SYMBOL voltage -432 96 R0
WINDOW 3 -261 238 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 2.4 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 33p
SYMBOL voltage -592 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 47
SYMBOL voltage -336 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
FLAG -592 272 0
FLAG -592 64 +V
FLAG -464 -16 0
FLAG -144 -112 +V
FLAG -144 336 0
FLAG -432 272 0
FLAG 0 112 0
FLAG 112 112 0
TEXT 96 336 Left 2 !.tran 10u
TEXT -712 -200 Left 2 ;Note:\nSwitch shown for a logic 1 input.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7142.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7142.asy)
Rload OUT 0 22
C1 OUT 0 2.2 Rser=3m
C2 N001 0 4.7n
XU1 IN N002 IN N001 OUT 0 ADP7118 Vref=1.2 ;pnba Vin)ADJ)EN)SS)Vout)GND
V1 IN 0 4.3
R1 OUT N002 17.4k
R2 N002 0 10K
.tran 6m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 400 32 352 32
WIRE 528 32 400 32
WIRE 624 32 528 32
WIRE -32 48 -32 32
WIRE 528 48 528 32
WIRE 624 48 624 32
WIRE 400 80 400 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 528 144 528 112
WIRE 624 144 624 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 400 224 400 160
WIRE 400 224 352 224
WIRE 400 240 400 224
WIRE 224 304 224 288
WIRE 400 336 400 320
SYMBOL ADP7142 224 128 R0
SYMATTR InstName U1
SYMBOL res 384 64 R0
SYMATTR InstName R1
SYMATTR Value 17.4k
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL res 608 32 R0
SYMATTR InstName Rload
SYMATTR Value 22
SYMBOL cap 512 48 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=3m
SYMBOL res 384 224 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 4.3
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG -32 32 IN
FLAG 624 144 0
FLAG 528 144 0
FLAG 624 32 OUT
FLAG 400 336 0
TEXT 520 272 Left 2 !.tran 6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-2.asy)
C1 OUT 0 10
C2 OUT N001 .01
V1 IN 0 PWL(0 0 1 10)
R3 OUT 0 500
XU1 IN 0 IN N001 OUT LT1761-2 ;pnba IN)GND)_SHDN)BYP)OUT
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 48 -224 48
WIRE 16 48 -16 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE -16 144 -16 48
WIRE 16 144 -16 144
WIRE 336 144 336 128
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL cap 320 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL PowerProducts\\LT1761-2 160 96 R0
SYMATTR InstName U1
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 496 48 R0
SYMATTR InstName R3
SYMATTR Value 500
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG -224 48 IN
FLAG 512 48 OUT
TEXT 368 240 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\4bf63d45a38a_Sim-Idss.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N002 0 15
J1 N001 0 0 MPF102A
R1 N002 N001 510
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.model MPF102A NJF(Beta=1.61m Betatce=-.5 Rd=1 Rs=1 Lambda=2m Vto=-3.41 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=11.73E-18 Af=1)
.dc V1 0 15 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2632 680
WIRE 160 96 128 96
WIRE 288 96 240 96
WIRE 288 112 288 96
WIRE 80 160 32 160
WIRE 32 224 32 160
WIRE 128 224 128 192
WIRE 288 224 288 192
SYMBOL njf 80 96 R0
SYMATTR InstName J1
SYMATTR Value MPF102A
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 510
SYMBOL voltage 288 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
FLAG 32 224 0
FLAG 128 224 0
FLAG 288 224 0
TEXT -160 40 Left 2 !.model MPF102A NJF(Beta=1.61m Betatce=-.5 Rd=1 Rs=1 Lambda=2m Vto=-3.41 Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7 Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=11.73E-18 Af=1)
TEXT 264 256 Left 2 !.dc V1 0 15 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\571c8326d453_zd6v8.asc
* Generated by LTspice 26.0.1 for Windows.
*SRC=1N4736A;DI_1N4736A;Diodes;Zener <=10V; 6.80V 1.00W Diodes Inc. Zener
*SYM=HZEN
* Terminals A K
* You can save the model into a file, e.g. z_diodes.lib.\nThen just add a SPICE-line to your schematic to include this file\n \n.include z_diode.lib
+ CJO=123p VJ=0.750 M=0.330 TT=50.1n )
XD1 0 vz DI_1N4736A ;pnba +)-
D1 1 2 DF
R1 N001 vz 1k
DZ 3 1 DR
VZ 2 3 6.05
V1 N001 0 10
.SUBCKT DI_1N4736A 1 2
.MODEL DF D ( IS=60.6p RS=0.620 N=1.10
.MODEL DR D ( IS=12.1f RS=0.209 N=1.00 )
.ENDS
.op
.dc V1 -10 10 .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -208 160 -208 80
WIRE -208 288 -208 240
WIRE -128 80 -208 80
WIRE 16 80 -48 80
WIRE 16 176 16 80
WIRE 16 288 16 240
SYMBOL res -144 96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL zener 0 240 M180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMATTR Value DI_1N4736A
SYMATTR Prefix X
SYMBOL voltage -208 144 R0
SYMATTR InstName V1
SYMATTR Value 10
FLAG 16 288 0
FLAG -208 288 0
FLAG 16 80 vz
TEXT -272 368 Left 0 !*SRC=1N4736A;DI_1N4736A;Diodes;Zener <=10V; 6.80V 1.00W Diodes Inc. Zener\n*SYM=HZEN\n.SUBCKT DI_1N4736A 1 2\n* Terminals A K\nD1 1 2 DF\nDZ 3 1 DR\nVZ 2 3 6.05\n.MODEL DF D ( IS=60.6p RS=0.620 N=1.10\n+ CJO=123p VJ=0.750 M=0.330 TT=50.1n )\n.MODEL DR D ( IS=12.1f RS=0.209 N=1.00 )\n.ENDS
TEXT -200 -16 Left 0 !.op
TEXT -200 -40 Left 0 !.dc V1 -10 10 .01
TEXT -232 -200 Left 0 ;You can save the model into a file, e.g. z_diodes.lib.\nThen just add a SPICE-line to your schematic to  include this file\n \n.include z_diode.lib