Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\1a78975d4cbc_SwitchModule.asc
* Generated by LTspice 26.0.1 for Windows.
S4 Out N001 VDD/2 RST SW
S1 VrefP N001 Bit VDD/2 SW
S3 Vin Out RST VDD/2 SW
S2 N001 VrefM VDD/2 Bit SW
.model SW SW
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 -32 -208 -32
WIRE -80 -32 -80 -112
WIRE -80 -32 -96 -32
WIRE -64 -32 -80 -32
WIRE 176 -32 16 -32
WIRE -160 32 -160 16
WIRE -112 32 -112 16
WIRE -80 32 -112 32
WIRE -48 32 -48 16
WIRE -48 32 -80 32
WIRE 0 32 0 16
WIRE -80 64 -80 32
WIRE 176 144 176 -32
WIRE 176 144 160 144
WIRE 192 144 176 144
WIRE 288 144 272 144
WIRE 96 208 96 192
WIRE 144 208 144 192
WIRE 176 208 144 208
WIRE 208 208 208 192
WIRE 208 208 176 208
WIRE 256 208 256 192
WIRE 176 240 176 208
IOPIN 176 240 In
IOPIN -80 64 In
SYMBOL sw 176 144 R270
WINDOW 0 45 40 VLeft 0
WINDOW 3 46 84 VLeft 0
SYMATTR InstName S2
SYMBOL sw -80 -32 R270
WINDOW 0 45 40 VLeft 0
WINDOW 3 46 84 VLeft 0
SYMATTR InstName S4
SYMBOL sw -192 -32 R270
WINDOW 0 45 81 VRight 0
WINDOW 3 52 36 VRight 0
SYMATTR InstName S3
SYMBOL sw 64 144 R270
WINDOW 0 45 81 VRight 0
WINDOW 3 52 36 VRight 0
SYMATTR InstName S1
FLAG 176 240 Bit
FLAG 80 144 VrefP
FLAG 96 208 VDD/2
FLAG 256 208 VDD/2
FLAG -80 64 RST
FLAG -160 32 VDD/2
FLAG 0 32 VDD/2
FLAG -208 -32 Vin
FLAG -80 -112 Out
FLAG 288 144 VrefM
TEXT -336 184 Left 0 !.model SW SW
* Z:\home\khalils\Downloads\files\data\raw_asc\b55271bdf653_1047.asc
* Generated by LTspice 26.0.1 for Windows.
* Precise DC Full-Wave Rectifier(Absolute Value Circuit)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1047.asy)
XU1 0 N001 +V 0 N003 LTC1047 ;pnba In+)In-)V+)V-)OUT
V3 IN 0 SINE(0 1 1K)
R2 N001 IN 220K
R1 N002 N001 220K
XU2 N002 OUT +V 0 OUT LTC1047 ;pnba In+)In-)V+)V-)OUT
D1 N003 N002 1N4148
V1 +V 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 576 128 464 128
WIRE 32 144 -112 144
WIRE 128 144 112 144
WIRE 256 144 128 144
WIRE 432 144 336 144
WIRE -112 160 -112 144
WIRE -224 176 -224 160
WIRE 512 192 512 176
WIRE 192 208 192 192
WIRE 464 208 464 128
WIRE 480 208 464 208
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 576 224 576 128
WIRE 576 224 544 224
WIRE 608 224 576 224
WIRE 352 240 224 240
WIRE 432 240 432 144
WIRE 432 240 416 240
WIRE 480 240 432 240
WIRE -112 256 -112 240
WIRE 160 256 128 256
WIRE -224 272 -224 256
WIRE 512 272 512 256
WIRE 192 288 192 272
SYMBOL diode 352 256 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL opamps\\LTC1047 192 176 R0
SYMATTR InstName U1
SYMBOL res 352 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 220K
SYMBOL res 128 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 220K
SYMBOL opamps\\LTC1047 512 160 R0
SYMATTR InstName U2
SYMBOL voltage -224 160 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -112 144 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
FLAG -224 272 0
FLAG 192 192 +V
FLAG -224 160 +V
FLAG -112 256 0
FLAG 192 288 0
FLAG 512 176 +V
FLAG 512 272 0
FLAG 128 256 0
FLAG 608 224 OUT
FLAG -112 144 IN
TEXT 544 320 Left 2 !.tran 3m
TEXT 200 88 Bottom 2 ;Precise DC Full-Wave Rectifier(Absolute Value Circuit)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5.5
C2 OUT 0 1
Rload OUT 0 100
C1 IN 0 1
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=43478 ;pnba Vout))Sense)GND)En)))Vin
.tran 10m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-2.8.asy)
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP124-2.8 256 208 R0
SYMATTR InstName U1
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1152cc6feb50_DC_analog_to_pulse_wave.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N002 N004 0 0 NPN
R2 N001 N002 1k
V2 N003 0 SINE(0 5 10)
V1 N001 0 5
R1 N004 N003 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -128 -64 -128
WIRE -64 -80 -64 -128
WIRE -64 32 -64 0
WIRE 144 64 144 -128
WIRE 144 176 144 144
WIRE -32 224 -144 224
WIRE 80 224 48 224
WIRE -144 240 -144 224
WIRE -144 336 -144 320
WIRE 144 336 144 272
SYMBOL res 64 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -144 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 5 10)
SYMBOL npn 80 176 R0
SYMATTR InstName Q1
SYMBOL res 128 48 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -64 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
FLAG 144 336 0
FLAG -64 32 0
FLAG -144 336 0
* Z:\tmp\asc_dec_bjh7r6w2\1616bd2242d5_4B_1Sw555_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
r3 8 5 5k
r4 8 N001 4k
R2_1 N001 2 1g
R4_1 4 N001 1g
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1704 916
WIRE -576 304 -576 256
WIRE -576 320 -576 304
WIRE -576 448 -576 400
WIRE -576 496 -576 448
WIRE -576 624 -576 576
WIRE -560 256 -576 256
WIRE -544 304 -576 304
WIRE -496 368 -576 448
WIRE -448 256 -480 256
WIRE -448 256 -480 304
WIRE -448 400 -448 256
WIRE -448 624 -576 624
WIRE -448 624 -448 480
WIRE -352 528 -352 496
WIRE -352 624 -448 624
WIRE -352 624 -352 608
WIRE -240 528 -240 496
WIRE -240 624 -352 624
WIRE -240 624 -240 608
WIRE -128 528 -128 496
WIRE -128 624 -240 624
WIRE -128 624 -128 608
WIRE -64 512 -64 496
WIRE -64 624 -128 624
WIRE -64 624 -64 592
WIRE 112 624 -64 624
SYMBOL res -464 240 R90
WINDOW 0 17 104 VBottom 0
WINDOW 3 -10 8 VTop 0
SYMATTR InstName r3
SYMATTR Value 5k
SYMBOL res -464 384 R0
WINDOW 0 -38 43 Left 0
WINDOW 3 -38 67 Left 0
SYMATTR InstName r4
SYMATTR Value 4k
SYMBOL res -336 624 R180
WINDOW 0 36 85 Left 0
WINDOW 3 41 48 Left 0
SYMATTR InstName R2_1
SYMATTR Value 1g
SYMBOL res -256 512 R0
WINDOW 0 -47 25 Left 0
WINDOW 3 -40 62 Left 0
SYMATTR InstName R4_1
SYMATTR Value 1g
FLAG -496 368 N1
FLAG -544 304 5
FLAG -480 304 8
FLAG -240 496 4
FLAG -128 496 6
FLAG -64 496 S
FLAG -352 496 2
* Z:\tmp\asc_dec_bjh7r6w2\07193af8c4bf_PowerMux_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
XM1 N002 N003 N001 SIA483DJ ;pnba D)G)S
XM6 V1 N003 N001 SIA483DJ ;pnba D)G)S
R1 3V3 N007 47k
V2 V2 0 12V
R12 N012 N011 1k
M4 N010 N009 N013 N013 RJK005N03
R6 N001 N003 47k
C3 N001 N003 100nF
R11 N006 N005 1k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2412 1560
WIRE 1136 384 1120 384
WIRE 1264 384 1232 384
WIRE 1328 384 1264 384
WIRE 1376 384 1328 384
WIRE 1952 384 1472 384
WIRE 1264 432 1264 384
WIRE 1328 432 1328 384
WIRE 1216 528 1216 432
WIRE 1264 528 1264 496
WIRE 1264 528 1216 528
WIRE 1296 528 1264 528
WIRE 1328 528 1328 512
WIRE 1328 528 1296 528
WIRE 1392 528 1392 432
WIRE 1392 528 1328 528
WIRE 1296 544 1296 528
WIRE 1296 656 1296 624
WIRE 1024 736 880 736
WIRE 1184 736 1104 736
WIRE 1248 736 1184 736
WIRE 1296 816 1296 752
WIRE 448 1024 448 1008
WIRE 592 1024 448 1024
WIRE 448 1040 448 1024
WIRE 1216 1104 1216 1024
WIRE 1264 1104 1264 1088
WIRE 1264 1104 1216 1104
WIRE 1328 1104 1264 1104
WIRE 1392 1104 1392 1024
WIRE 1392 1104 1328 1104
WIRE 1392 1136 1392 1104
WIRE 1056 1232 1056 1168
WIRE 1152 1232 1056 1232
WIRE 1280 1232 1152 1232
WIRE 1152 1280 1152 1232
WIRE 1392 1280 1392 1216
WIRE 592 1344 592 1024
WIRE 880 1360 880 1088
WIRE 880 1360 672 1360
WIRE 944 1360 880 1360
WIRE 1072 1360 1024 1360
WIRE 1104 1360 1072 1360
WIRE 1280 1360 1280 1232
WIRE 1344 1360 1280 1360
WIRE 1072 1424 1072 1360
WIRE 1072 1520 1072 1504
WIRE 1152 1520 1152 1376
WIRE 1392 1520 1392 1376
SYMBOL pmos 1472 432 M270
SYMATTR InstName M1
SYMATTR Value SIA483DJ
SYMATTR Prefix X
SYMBOL pmos 1136 432 R270
SYMATTR InstName M6
SYMATTR Value SIA483DJ
SYMATTR Prefix X
SYMBOL res 432 912 R0
SYMATTR InstName R1
SYMATTR Value 47k
SYMBOL voltage -80 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12V
SYMBOL res 1040 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 1k
SYMBOL nmos 1344 1280 R0
WINDOW 3 125 141 VLeft 2
SYMATTR Value RJK005N03
SYMATTR InstName M4
SYMBOL res 1312 416 R0
SYMATTR InstName R6
SYMATTR Value 47k
SYMBOL cap 1248 432 R0
SYMATTR InstName C3
SYMATTR Value 100nF
SYMBOL res 1120 720 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 1k
FLAG -80 480 0
FLAG -80 400 V2
FLAG 1184 816 0
FLAG 1296 816 0
FLAG 1072 1520 0
FLAG 1152 1520 0
FLAG 1120 384 V1
FLAG -80 576 3V3
FLAG 448 928 3V3
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6657-1.25.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6657-1.25.asy)
C2 IN 0 .1
XU1 IN IN OUT 0 LT6657-1.25 ;pnba IN)_SHDN)OUT)GND
C1 OUT 0 1
V1 IN 0 PWL(0 0 3m 3 7m 3 10m 0)
R1 OUT 0 250
.tran 10m
.lib LT6657.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1652 680
WIRE 224 96 -176 96
WIRE 288 96 224 96
WIRE 320 96 288 96
WIRE 672 96 608 96
WIRE 768 96 672 96
WIRE -176 112 -176 96
WIRE 224 112 224 96
WIRE 672 112 672 96
WIRE 768 112 768 96
WIRE 224 192 224 176
WIRE -176 208 -176 192
WIRE 288 208 288 96
WIRE 320 208 288 208
WIRE 672 208 672 176
WIRE 768 208 768 192
WIRE 464 288 464 256
SYMBOL LT6657-1.25 464 128 R0
SYMATTR InstName U1
SYMBOL voltage -176 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 3m 3 7m 3 10m 0)
SYMBOL cap 656 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 208 112 R0
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL res 752 96 R0
SYMATTR InstName R1
SYMATTR Value 250
FLAG 672 208 0
FLAG 464 288 0
FLAG -176 208 0
FLAG 768 96 OUT
FLAG 768 208 0
FLAG 224 192 0
FLAG -176 96 IN
TEXT 672 360 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\46955dc77761_1078.asc
* Generated by LTspice 26.0.1 for Windows.
* Absolute Value Circuit(Full-Wave Rectifier)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1078.asy)
XU1 0 N001 +V 0 N003 LT1078 ;pnba In+)In-)V+)V-)OUT
R1 N002 N001 200K
V3 IN 0 SINE(0 1 100)
R2 N001 IN 200K
V1 +V 0 5
D1 N003 N002 1N4148
XU2 N002 OUT +V 0 OUT LT1078 ;pnba In+)In-)V+)V-)OUT
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 30m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 -80 96
WIRE 128 96 112 96
WIRE 224 96 128 96
WIRE 384 96 304 96
WIRE -80 112 -80 96
WIRE 528 128 432 128
WIRE -192 160 -192 144
WIRE 480 192 480 176
WIRE -80 208 -80 192
WIRE 192 208 192 192
WIRE 432 208 432 128
WIRE 448 208 432 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 528 224 528 128
WIRE 528 224 512 224
WIRE 576 224 528 224
WIRE 304 240 224 240
WIRE 384 240 384 96
WIRE 384 240 368 240
WIRE 448 240 384 240
WIRE 160 256 128 256
WIRE -192 272 -192 240
WIRE 480 272 480 256
WIRE 192 288 192 272
SYMBOL opamps\\LT1078 192 176 R0
SYMATTR InstName U1
SYMBOL diode 304 256 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL voltage -192 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -80 96 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 200K
SYMBOL opamps\\LT1078 480 160 R0
SYMATTR InstName U2
SYMBOL res 320 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 200K
FLAG -192 272 0
FLAG 192 192 +V
FLAG -192 144 +V
FLAG -80 208 0
FLAG 192 288 0
FLAG 480 176 +V
FLAG 480 272 0
FLAG -80 96 IN
FLAG 576 224 OUT
FLAG 128 256 0
TEXT 398 346 Left 0 !.tran 30m
TEXT 392 32 Bottom 0 ;Absolute Value Circuit(Full-Wave Rectifier)
* Z:\home\khalils\Downloads\files\data\raw_asc\f5df787cc85e_Circuito4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 AC 1
C1 N003 0 10n
L1 N002 N003 1m
R1 N002 N001 50
.ac dec 10000 1 10Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 80 -16 80
WIRE 160 80 112 80
WIRE 272 80 240 80
WIRE -16 112 -16 80
WIRE 272 128 272 80
WIRE -16 240 -16 192
WIRE 272 240 272 192
WIRE 272 240 -16 240
WIRE -16 272 -16 240
SYMBOL ind 144 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1m
SYMBOL res 128 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL cap 256 128 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage -16 96 R0
WINDOW 123 19 105 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
FLAG -16 272 0
TEXT -48 296 Left 2 !.ac dec 10000 1 10Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\a05064142cd7_circuito2.4SANTI.asc
* Generated by LTspice 26.0.1 for Windows.
R4 Vout N002 925
XU1 N004 N001 Vcc+ Vcc- N003 LM324 ;pnba In+)In-)V+)V-)OUT
V3 Vcc+ 0 12
XU2 N003 N002 Vcc+ Vcc- Vout LM6181/NS ;pnba In+)In-)V+)V-)OUT
R2 Vout N001 90k
V2 Vcc- 0 -12
V1 N004 0 SINE(0 1 10k) AC 1
R1 N001 0 10k
R3 N002 0 45
.ac dec 1000 10 100000000
.inc LM324.lib
.inc E:\Documentos\GitHub\lab3SRA\LM6181.MOD
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1508 680
WIRE -528 -80 -560 -80
WIRE 32 -80 -448 -80
WIRE -352 48 -384 48
WIRE -224 48 -272 48
WIRE -176 48 -224 48
WIRE -48 48 -96 48
WIRE -384 80 -384 48
WIRE -224 192 -224 48
WIRE -192 192 -224 192
WIRE -688 208 -720 208
WIRE -560 208 -560 -80
WIRE -560 208 -608 208
WIRE -512 208 -560 208
WIRE -48 208 -48 48
WIRE -48 208 -128 208
WIRE 32 208 32 -80
WIRE 32 208 -48 208
WIRE -192 224 -448 224
WIRE -720 240 -720 208
WIRE -512 240 -560 240
WIRE -560 368 -560 240
WIRE -560 512 -560 448
WIRE -288 512 -288 464
WIRE -160 512 -160 464
SYMBOL voltage -560 352 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 10k)
SYMATTR Value2 AC 1
SYMBOL res -432 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 90k
SYMBOL res -256 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 45
SYMBOL OpAmps\\opamp2 -160 144 R0
SYMATTR InstName U2
SYMATTR Value LM6181/NS
SYMBOL voltage -288 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -12
SYMBOL res -592 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res -80 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 925
SYMBOL voltage -160 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 12
SYMBOL OpAmps\\opamp2 -480 160 R0
SYMATTR InstName U1
SYMATTR Value LM324
FLAG -384 80 0
FLAG -720 240 0
FLAG -560 512 0
FLAG -288 512 0
FLAG -160 512 0
FLAG -288 384 Vcc-
FLAG -480 256 Vcc-
FLAG -160 240 Vcc-
FLAG -160 384 Vcc+
FLAG -160 176 Vcc+
FLAG -480 192 Vcc+
FLAG 32 208 Vout
TEXT -1464 664 Left 2 !.ac dec 1000 10 100000000
TEXT -1464 568 Left 2 !.inc LM324.lib
TEXT -1464 616 Left 2 !.inc E:\\Documentos\\GitHub\\lab3SRA\\LM6181.MOD
* Z:\tmp\asc_dec_bjh7r6w2\1154c63b0138_6269_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 N002 N001 20K
Cparasitic N002 N001 150f
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4472 1028
WIRE -2576 -608 -2640 -608
WIRE -2448 -608 -2512 -608
WIRE -2640 -512 -2640 -608
WIRE -2640 -512 -2784 -512
WIRE -2576 -512 -2640 -512
WIRE -2448 -512 -2448 -608
WIRE -2448 -512 -2496 -512
WIRE -2640 -352 -2640 -512
WIRE -2624 -352 -2640 -352
WIRE -2448 -320 -2448 -512
SYMBOL res -2480 -528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 20K
SYMBOL cap -2512 -624 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cparasitic
SYMATTR Value 150f
FLAG -2592 -400 V+
* Z:\home\khalils\Downloads\files\data\raw_asc\b6698de94a32_relax_osc.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
XU2 N003 N001 Vcc 0 N002 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N003 0 10K
R4 N002 N001 560
C1 N001 0 22n
V1 Vcc 0 5
R1 N002 N003 7.5k
R3 N003 Vcc 10K
.tran 0 1m 0
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 112 128 112
WIRE 240 112 224 112
WIRE 256 112 240 112
WIRE 416 112 336 112
WIRE 128 144 128 112
WIRE 240 208 240 112
WIRE 320 208 240 208
WIRE 416 224 416 112
WIRE 416 224 384 224
WIRE 320 240 272 240
WIRE 160 384 128 384
WIRE 272 384 272 240
WIRE 272 384 240 384
WIRE 304 384 272 384
WIRE 416 384 416 224
WIRE 416 384 384 384
WIRE 272 416 272 384
WIRE 272 528 272 496
SYMBOL voltage -64 288 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 256 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL cap 224 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 22n
SYMBOL OpAmps\\UniversalOpAmp2 352 224 R0
SYMATTR InstName U2
SYMBOL res 256 400 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 400 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 7.5k
SYMBOL res 352 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 560
FLAG 272 528 0
FLAG -64 384 0
FLAG -64 304 Vcc
FLAG 352 192 Vcc
FLAG 352 256 0
FLAG 128 144 0
FLAG 128 384 Vcc
TEXT 272 656 Left 2 !.tran 0 1m 0
* Z:\home\khalils\Downloads\files\data\raw_asc\99c1304a7eda_invsumopamp.asc
* Generated by LTspice 26.0.1 for Windows.
* Non-inverting Summing Amplifier\nSee https://www.electronics-tutorials.ws/opamp/opamp_4.html
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
V4 N005 0 SINE(0 5 2k)
V2 0 N006 12
XU1 N004 N002 N001 N006 Output level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V3 N003 0 SINE(0 5 1k)
R1 N002 0 1K tol=1 pwr=0.1
R4 N004 N005 20K tol=1 pwr=0.1
V1 N001 0 12
R2 Output N002 1K tol=1 pwr=0.1
R3 N004 N003 10K tol=1 pwr=0.1
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 -32 96 -32
WIRE 96 16 96 -32
WIRE 432 48 240 48
WIRE 560 48 512 48
WIRE -128 112 -496 112
WIRE 192 112 -48 112
WIRE -496 144 -496 112
WIRE 352 144 352 -32
WIRE 240 160 240 48
WIRE 320 160 240 160
WIRE 96 176 96 96
WIRE 96 176 16 176
WIRE 560 176 560 48
WIRE 560 176 384 176
WIRE 640 176 560 176
WIRE 192 192 192 112
WIRE 320 192 192 192
WIRE -128 224 -304 224
WIRE 192 224 192 192
WIRE 192 224 -48 224
WIRE -304 256 -304 224
WIRE 96 256 96 176
WIRE 240 256 240 160
WIRE 96 384 96 336
WIRE 352 384 352 208
WIRE 352 384 96 384
WIRE -496 464 -496 224
WIRE -304 464 -304 336
WIRE -304 464 -496 464
WIRE 16 464 16 176
WIRE 16 464 -304 464
WIRE 192 464 16 464
WIRE 240 464 240 336
WIRE 240 464 192 464
WIRE 192 496 192 464
IOPIN 640 176 Out
SYMBOL voltage 96 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL res 224 240 R0
SYMATTR InstName R1
SYMATTR Value 1K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL res 528 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL res -32 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL voltage -304 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value SINE(0 5 2k)
SYMBOL OpAmps\\UniversalOpAmp 352 176 R0
SYMATTR InstName U1
SYMBOL res -32 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 20K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL voltage -496 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 5 1k)
SYMBOL voltage 96 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 640 176 Output
FLAG 192 496 0
TEXT -672 -16 Left 2 ;Non-inverting Summing Amplifier\nSee https://www.electronics-tutorials.ws/opamp/opamp_4.html
* Z:\home\khalils\Downloads\files\data\raw_asc\2007e83f53a7_ADG774A.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nOff Isolation is -69 dB at 10MHz\nQinj not included\nOnly one channel included\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG774A.asy)
XU2 N004 N001 N002 N003 +V 0 0 ADG774A ;pnba IN)SA)D)SB)Vdd)GND)_EN
V3 N004 0 PULSE(0 3 0 20n 20n 10u 20u)
V2 N003 0 0
C1 N002 0 36p
V1 N001 0 3
V5 +V 0 5
R1 N002 0 49.9
.tran 100u
.lib ADG774A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1696 -272 -1920 -272
WIRE -1920 -256 -1920 -272
WIRE -1408 -240 -1504 -240
WIRE -1296 -240 -1408 -240
WIRE -1408 -224 -1408 -240
WIRE -1296 -224 -1296 -240
WIRE -1696 -208 -1840 -208
WIRE -1840 -192 -1840 -208
WIRE -1920 -160 -1920 -176
WIRE -1696 -144 -1760 -144
WIRE -1472 -144 -1504 -144
WIRE -1472 -128 -1472 -144
WIRE -1408 -128 -1408 -144
WIRE -1296 -128 -1296 -160
WIRE -1840 -96 -1840 -112
WIRE -1760 -80 -1760 -144
WIRE -1600 -16 -1600 -32
WIRE -1760 32 -1760 0
SYMBOL cap -1312 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL ADG774A -1600 -192 R0
SYMATTR InstName U2
SYMBOL voltage -2144 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL voltage -1840 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage -1760 -96 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 20n 20n 10u 20u)
SYMATTR InstName V3
SYMBOL res -1424 -240 R0
SYMATTR InstName R1
SYMATTR Value 49.9
SYMBOL voltage -1920 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
FLAG -1920 -160 0
FLAG -1840 -96 0
FLAG -1760 32 0
FLAG -1600 -368 +V
FLAG -1408 -128 0
FLAG -1600 -16 0
FLAG -1296 -128 0
FLAG -1472 -128 0
FLAG -2144 -64 0
FLAG -2144 -144 +V
TEXT -1360 -40 Left 2 !.tran 100u
TEXT -2160 -472 Left 2 ;Note:\nOff Isolation is -69 dB at 10MHz\nQinj not included\nOnly one channel included\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\5ca0263121e0_quiz_q5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 PULSE(0 5 1u 1n 1n 19u 20u)
R1 N002 N001 1k
C1 N002 0 1n
.tran 20u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 80 128 80
WIRE 608 80 432 80
WIRE 608 96 608 80
WIRE 128 192 128 160
WIRE 608 208 608 160
SYMBOL res 448 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 128 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1u 1n 1n 19u 20u)
SYMBOL cap 592 96 R0
SYMATTR InstName C1
SYMATTR Value 1n
FLAG 128 192 0
FLAG 608 208 0
TEXT 88 232 Left 2 !.tran 20u