* Z:\home\khalils\Downloads\files\data\raw_asc\ADHV4710.asc
* Generated by LTspice 26.0.1 for Windows.
* For LTspice User Guide - ADHV4710 Model go to:\nhttps://wiki.analog.com/resources/quick-start
* ADHV4710 Example Circuit
* Ccomp_H must=Ccomp_L.\nCcomp_H, Ccomp_L value entered as parameter.\nRslew value entered as parameter.\nSetIQ value entered as parameter.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADHV4710.asy)
VCC_5V N002 0 5
Ccomp_H OUT N006 {Ccomp}
VIN IN 0 PULSE(0.702 -0.702 0 5n 5n 30u 60u)
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 0 N008 NC_07 NC_08 NC_09 NC_10 N007 OUT N006 N005 N001 N004 N003 IN NC_11 N002 N002 ADHV4710 Ccomp={Ccomp} Rslew={Rslew} SetIQ={SetIQ} ;pnba 1)2)3)4)5)6)7)8)9)10)11)12)13)14)15)16)17)18)19)20)21)22)23
Rslew N004 N003 {Rslew}
VHVCC N005 0 50
Ccomp_L OUT N007 {Ccomp}
R3 OUT N001 56k
C1 OUT 0 1n
VHVEE N008 0 -50
R2 N001 0 1k
.param Rslew=1m Ccomp=0p SetIQ=12m
.tran 0 180u 0
.lib ADHV4710.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1488 680
WIRE 160 -144 128 -144
WIRE 272 -144 240 -144
WIRE 464 -144 272 -144
WIRE 784 -144 544 -144
WIRE 128 -128 128 -144
WIRE -176 -48 -192 -48
WIRE -64 -48 -96 -48
WIRE -16 -48 -64 -48
WIRE 144 -48 128 -48
WIRE 240 -48 224 -48
WIRE 352 -48 320 -48
WIRE 448 -48 432 -48
WIRE -192 -32 -192 -48
WIRE 448 -32 448 -48
WIRE -64 32 -64 -48
WIRE -16 32 -16 -48
WIRE 128 32 128 -48
WIRE 240 32 240 -48
WIRE 272 32 272 -144
WIRE 320 32 320 -48
WIRE 592 112 512 112
WIRE 704 112 656 112
WIRE 704 144 704 112
WIRE 704 144 512 144
WIRE 784 144 784 -144
WIRE 784 144 704 144
WIRE 848 144 784 144
WIRE 592 176 512 176
WIRE 704 176 704 144
WIRE 704 176 656 176
WIRE 848 176 848 144
WIRE 848 256 848 240
WIRE -32 368 -32 336
WIRE 272 384 272 336
WIRE 320 416 320 336
WIRE 352 416 320 416
WIRE 448 416 432 416
WIRE 448 432 448 416
WIRE 272 448 272 384
WIRE 272 544 272 528
SYMBOL voltage 336 -48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName HVCC
SYMATTR Value 50
SYMBOL ADHV4710 224 80 R0
SYMATTR InstName U1
SYMBOL cap 832 176 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL cap 656 96 R90
WINDOW 0 -20 78 VCenter 2
WINDOW 3 -20 -41 VCenter 2
SYMATTR InstName Ccomp_H
SYMATTR Value {Ccomp}
SYMBOL res 240 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rslew
SYMATTR Value {Rslew}
SYMBOL voltage 272 432 R0
SYMATTR InstName VIN
SYMATTR Value PULSE(0.702 -0.702 0 5n 5n 30u 60u)
SYMBOL cap 656 160 R90
WINDOW 0 45 76 VCenter 2
WINDOW 3 43 -40 VCenter 2
SYMATTR InstName Ccomp_L
SYMATTR Value {Ccomp}
SYMBOL voltage -80 -48 R90
WINDOW 0 -43 57 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName VCC_5V
SYMATTR Value 5
SYMBOL res 256 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 560 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 56k
SYMBOL voltage 336 416 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName HVEE
SYMATTR Value -50
FLAG -32 368 0
FLAG 448 432 0
FLAG 848 256 0
FLAG 848 144 OUT
FLAG 448 -32 0
FLAG -192 -32 0
FLAG 128 -128 0
FLAG 272 544 0
FLAG 272 384 IN
TEXT 352 -208 Left 2 !.param Rslew=1m Ccomp=0p SetIQ=12m
TEXT -248 -328 Left 2 ;For LTspice User Guide - ADHV4710 Model go to:\nhttps://wiki.analog.com/resources/quick-start
TEXT -248 -368 Left 3 ;ADHV4710 Example Circuit
TEXT -248 -256 Left 2 !.tran 0 180u 0
TEXT 352 -328 Left 2 ;Ccomp_H must=Ccomp_L.\nCcomp_H, Ccomp_L value entered as parameter.\nRslew value entered as parameter.\nSetIQ value entered as parameter.