* Z:\home\khalils\Downloads\files\data\raw_asc\1dcec7e67aad_Exp_1_block.asc
* Generated by LTspice 26.0.1 for Windows.
R3 VSQR N001 100k
R1 N002 VSQR 1.25k
C1 VRAMP N002 10n
R2 N001 VRAMP 20k
Rpull1 VDD PWM 4.7k
CBIAS VRAMP_B VRAMP 0.1m
RBIAS VRAMP_B VBIAS 10k
Rpull2 VSQR VDD 4.7k
XCMP2 VCTRL VRAMP_B VDD 0 PWM LTC6752 ;pnba +In)-In)VCC)VEE)Q
XCMP1 N001 VCM VDD 0 VSQR LTC6752 ;pnba +In)-In)VCC)VEE)Q
XU1 VCM N002 VDD 0 VRAMP level3a Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
* Experiment 1 - Ramp Generator and PWM Modulator
* Library below included based on ModelFile attribute of instance XCMP2, XCMP1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LTC6752.asy)
.lib LTC7.lib
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp3.asy)
.lib UniversalOpAmp3a.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1172 1076
WIRE 560 304 32 304
WIRE 304 352 240 352
WIRE 336 352 304 352
WIRE 432 352 400 352
WIRE 464 352 432 352
WIRE 560 352 560 304
WIRE 560 352 528 352
WIRE 720 400 336 400
WIRE 240 448 240 432
WIRE 32 464 32 304
WIRE 64 464 32 464
WIRE 176 464 176 352
WIRE 176 464 128 464
WIRE 208 464 176 464
WIRE 432 464 432 352
WIRE 448 464 432 464
WIRE 304 480 304 352
WIRE 304 480 272 480
WIRE 336 480 336 400
WIRE 336 480 304 480
WIRE 560 480 560 352
WIRE 560 480 512 480
WIRE 640 480 560 480
WIRE 720 480 640 480
WIRE 208 496 192 496
WIRE 448 496 432 496
WIRE 192 528 192 496
WIRE 240 528 240 512
WIRE 432 528 432 496
WIRE 480 544 480 512
WIRE 528 544 480 544
WIRE 640 544 640 480
WIRE 640 544 608 544
WIRE 720 576 512 576
WIRE 480 592 480 544
WIRE 512 672 512 576
WIRE 512 672 384 672
WIRE 544 672 544 656
WIRE 592 672 544 672
WIRE 688 672 672 672
WIRE 544 688 544 672
WIRE 304 704 304 480
WIRE 320 704 304 704
WIRE 384 704 384 672
WIRE 512 704 384 704
WIRE 688 720 688 672
WIRE 688 720 576 720
WIRE 720 720 688 720
WIRE 512 736 480 736
WIRE 480 752 480 736
WIRE 544 768 544 752
FLAG 240 432 VDD
IOPIN 240 432 In
FLAG 544 768 0
FLAG 480 448 0
FLAG 240 528 0
FLAG 720 480 VSQR
IOPIN 720 480 Out
FLAG 720 720 PWM
IOPIN 720 720 Out
FLAG 480 752 VCTRL
IOPIN 480 752 In
FLAG 192 528 VCM
IOPIN 192 528 In
FLAG 432 528 VCM
IOPIN 432 528 In
FLAG 480 592 VDD
IOPIN 480 592 In
FLAG 544 656 VDD
IOPIN 544 656 In
FLAG 720 400 VRAMP
IOPIN 720 400 Out
FLAG 384 784 VBIAS
IOPIN 384 784 In
FLAG 720 576 VRAMP_B
IOPIN 720 576 Out
SYMBOL res2 528 336 R90
WINDOW 0 0 32 VBottom 1
WINDOW 3 32 32 VTop 0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL res2 128 448 R90
WINDOW 0 0 32 VBottom 1
WINDOW 3 32 32 VTop 0
SYMATTR InstName R1
SYMATTR Value 1.25k
SYMBOL cap 240 336 R90
WINDOW 0 0 32 VBottom 1
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res2 400 336 R90
WINDOW 0 0 32 VBottom 1
WINDOW 3 32 32 VTop 0
SYMATTR InstName R2
SYMATTR Value 20k
SYMBOL res 576 688 R270
WINDOW 0 32 56 VTop 1
WINDOW 3 0 56 VBottom 0
SYMATTR InstName Rpull1
SYMATTR Value 4.7k
SYMBOL cap 384 688 R90
WINDOW 0 0 32 VBottom 1
WINDOW 3 32 32 VTop 0
SYMATTR InstName CBIAS
SYMATTR Value 0.1m
SYMBOL res 368 688 R0
WINDOW 0 36 40 Left 1
WINDOW 3 36 76 Left 0
SYMATTR InstName RBIAS
SYMATTR Value 10k
SYMBOL res 624 528 R90
WINDOW 0 0 56 VBottom 1
WINDOW 3 32 56 VTop 0
SYMATTR InstName Rpull2
SYMATTR Value 4.7k
SYMBOL Comparators/LTC6752 544 656 R0
SYMATTR InstName CMP2
SYMBOL Comparators/LTC6752 480 544 M180
SYMATTR InstName CMP1
SYMBOL OpAmps\\UniversalOpAmp3 240 480 R0
SYMATTR InstName U1
TEXT 0 208 Left 2 ;Experiment 1 - Ramp Generator and PWM Modulator
LINE Normal 704 352 704 768 1