Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8642-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8642-1.asy)
V1 IN 0 12
C2 N004 N005 47n
C4 OUT 0 220 X2
R1 RT 0 17.8K
R3 N006 0 100K
C3 N003 0 1
C5 OUT N006 47p
XU2 NC_01 N003 N004 IN NC_02 0 N002 N005 0 0 NC_03 0 IN IN RT SS N006 LT8642-1 ;pnba Bias)INTVcc)BST)Vin1)CLKOUT)GND1)Vc)SW)Sync/Mode)GND2)PG)GND)Vin2)EN/UV)Rt)TR/SS)FB
Rload OUT 0 12 m=100
R2 OUT N006 100K
L1 N005 OUT 0.56
C6 N002 N001 150p
C1 SS 0 1n
R4 N001 0 11K
.tran 1m startup
.lib LT8642-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1848 740
WIRE 96 -80 0 -80
WIRE 256 -80 96 -80
WIRE 416 -80 256 -80
WIRE 0 -64 0 -80
WIRE 256 -64 256 -80
WIRE 96 0 96 -80
WIRE 112 0 96 0
WIRE 416 0 416 -80
WIRE 416 0 400 0
WIRE 0 32 0 16
WIRE 112 80 96 80
WIRE 416 80 400 80
WIRE -96 160 -112 160
WIRE 0 160 -16 160
WIRE 112 160 64 160
WIRE 32 240 16 240
WIRE 112 240 96 240
WIRE 112 320 96 320
WIRE 432 320 400 320
WIRE -16 400 -32 400
WIRE 80 400 64 400
WIRE 112 400 80 400
WIRE 432 400 432 384
WIRE 432 400 400 400
WIRE 480 400 432 400
WIRE 576 400 560 400
WIRE 688 400 576 400
WIRE 784 400 688 400
WIRE 880 400 784 400
WIRE 688 416 688 400
WIRE 784 416 784 400
WIRE 880 416 880 400
WIRE 0 480 -32 480
WIRE 80 480 64 480
WIRE 112 480 80 480
WIRE 576 480 400 480
WIRE 688 480 688 464
WIRE 688 480 576 480
WIRE 576 496 576 480
WIRE 784 512 784 480
WIRE 880 512 880 496
WIRE 304 560 304 544
WIRE 576 592 576 576
SYMBOL cap 96 256 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 64 496 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL voltage 0 -80 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL ind 464 416 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.56
SYMBOL cap 768 416 R0
WINDOW 0 40 17 Left 2
WINDOW 123 24 80 Left 2
SYMATTR InstName C4
SYMATTR Value2 X2
SYMATTR Value 220
SYMBOL res 80 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 17.8K
SYMBOL LT8642-1 256 240 R0
SYMATTR InstName U2
SYMBOL res 0 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 11K
SYMBOL cap 64 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 150p
SYMBOL cap 672 400 R0
WINDOW 0 32 17 Left 2
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL cap 416 320 R0
WINDOW 0 32 17 Left 2
WINDOW 3 32 47 Left 2
SYMATTR InstName C2
SYMATTR Value 47n
SYMBOL res 864 400 R0
WINDOW 123 36 100 Left 2
SYMATTR InstName Rload
SYMATTR Value 12
SYMATTR Value2 m=100
SYMBOL res 560 480 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 560 384 R0
SYMATTR InstName R2
SYMATTR Value 100K
FLAG 304 560 0
FLAG -32 400 0
FLAG 0 32 0
FLAG 784 512 0
FLAG 576 592 0
FLAG 880 512 0
FLAG 880 400 OUT
FLAG 0 -80 IN
FLAG 96 80 0
FLAG 416 80 0
FLAG -32 480 0
FLAG -112 160 0
FLAG 16 240 0
FLAG 80 480 SS
FLAG 80 400 RT
FLAG 96 320 0
TEXT 176 616 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0d121eeba1b6_ADA4000-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4000-1.asy)
R1 N001 0 10K
R2 OUT N001 10K
Vin IN 0 SINE(0 1 500K)
V1 +V 0 15
XU1 IN N001 +V -V OUT ADA4000 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -15
.tran 20u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 736 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 432 -976 432 -992
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 500K)
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL Opamps\\ADA4000-1 576 -1168 R0
SYMATTR InstName U1
FLAG 144 -1168 +V
FLAG 432 -976 0
FLAG 736 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 256 -1056 0
FLAG 144 -1056 0
TEXT 744 -984 Left 2 !.tran 20u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG841.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input.\nCharge injection not included.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG841.asy)
VS S 0 3
V2 IN 0 PULSE(0 2.4 0 10n 10n 980n 2u)
R1 D 0 47
V1 +V 0 3.3
C1 D 0 33p
XU1 +V IN S D 0 ADG841 ;pnba Vdd)IN)S)D)GND
.tran 10u
.lib ADG841.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2844 1336
WIRE -144 -96 -144 -112
WIRE -368 -16 -400 -16
WIRE -272 -16 -288 -16
WIRE -240 -16 -272 -16
WIRE -32 -16 -48 -16
WIRE 0 -16 -32 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -272 48 -368 48
WIRE -240 48 -272 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL ADG841 -144 32 R0
SYMATTR InstName U1
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 2.4 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 47
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 33p
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
FLAG -272 -16 S
FLAG -272 48 IN
FLAG -32 -16 D
TEXT -16 176 Left 2 !.tran 10u
TEXT -592 -232 Left 2 ;Note:\nSwitch shown for a logic 0 input.\nCharge injection not included.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP172-2.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP172-2.2.asy)
XU1 OUT IN IN 0 ADP172-2.2 ;pnba Vout)Vin)En)GND
RLOAD OUT 0 7.32
V1 IN 0 3.6
C1 OUT 0 1
.tran 2m startup
.lib ADP172-2.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 80 -48 80
WIRE 48 80 -32 80
WIRE 64 80 48 80
WIRE 304 80 256 80
WIRE 336 80 304 80
WIRE 384 80 336 80
WIRE -48 96 -48 80
WIRE 304 96 304 80
WIRE 304 176 304 160
WIRE 384 176 384 160
WIRE -48 192 -48 176
WIRE 48 192 48 80
WIRE 64 192 48 192
WIRE 272 192 256 192
SYMBOL ADP172-2.2 160 192 R0
SYMATTR InstName U1
SYMBOL voltage -48 80 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL cap 288 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 368 64 R0
SYMATTR InstName RLOAD
SYMATTR Value 7.32
FLAG -48 192 0
FLAG 304 176 0
FLAG 272 192 0
FLAG 384 176 0
FLAG -32 80 IN
FLAG 336 80 OUT
TEXT 160 256 Center 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0415259cbfc7_1_a_Diodo_Analisis_temp_diferentes.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 5
D1 N001 0 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -2 2 0.01
.temp 27 35 56 78
.model 1N4148 D(Is=700n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 48 -96 48
WIRE -96 112 -96 48
WIRE 112 112 112 48
WIRE -96 256 -96 192
WIRE 16 256 -96 256
WIRE 112 256 112 176
WIRE 112 256 16 256
WIRE 16 304 16 256
SYMBOL voltage -96 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL diode 96 112 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG 16 304 0
TEXT 88 288 Left 2 !.dc V1 -2 2 0.01
TEXT 88 320 Left 2 !.temp 27 35 56 78
TEXT -480 352 Left 2 !.model 1N4148 D(Is=700n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-3.5.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
V1 IN 0 3.3
Rload OUT 0 50
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-3.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
.tran 400u startup
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-3.5.asy)
.lib ADP2503-3.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2503-3.5 176 176 R0
SYMATTR InstName U1
TEXT 424 376 Left 2 !.tran 400u startup
TEXT 168 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1085-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1085-12.asy)
V1 IN 0 PWL(0 0 1 20) Rser=0.1
Rload OUT 0 10
XU1 0 OUT IN LT1085-12 ;pnba GND)OUT)IN
C1 OUT 0 10
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1952 896 1808 896
WIRE 2064 896 1952 896
WIRE 1344 912 1344 896
WIRE 1952 912 1952 896
WIRE 2064 912 2064 896
WIRE 1344 1008 1344 992
WIRE 1952 1008 1952 976
WIRE 2064 1008 2064 992
WIRE 1680 1024 1680 992
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 20)
SYMATTR SpiceLine Rser=0.1
SYMBOL cap 1936 912 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1085-12 1680 896 R0
SYMATTR InstName U1
SYMBOL RES 2048 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 2064 896 OUT
FLAG 2064 1008 0
FLAG 1344 1008 0
FLAG 1952 1008 0
FLAG 1344 896 IN
FLAG 1680 1024 0
TEXT 1968 1088 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\033f19c81984_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc Vin -0.4 1 0.001
* .op
* .ac dec 20 1k 100G
* .tran 80n
Vbn N002 0 0.6
M1 OUT N003 0 0 nch l=180n w=10u m=2
V1 VDD 0 1.8
Vpb VDD N001 0.8
M2 OUT N001 VDD VDD pch l=180n w=10u m=2
Vin N003 N002 SINE(0 {Vin} 100Meg) AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib 'C:\Program Files\LTC\LTspiceXVII\lib\cmp\log018.l' TT
.noise V(OUT) Vin dec 20 1 100G
.param Vin 12.5m
.step param Vin list 12.5m 25m 50m 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1076 680
WIRE -272 32 -352 32
WIRE -176 32 -272 32
WIRE -96 32 -176 32
WIRE -16 32 -96 32
WIRE -96 96 -96 32
WIRE -144 112 -272 112
WIRE -16 144 -16 32
WIRE -16 144 -96 144
WIRE -352 224 -352 176
WIRE -96 256 -96 192
WIRE -16 256 -96 256
WIRE -96 336 -96 256
WIRE -16 384 -96 384
WIRE -272 416 -352 416
WIRE -144 416 -192 416
WIRE -96 464 -96 432
WIRE -16 464 -16 384
WIRE -16 464 -96 464
WIRE -352 512 -352 416
WIRE -96 592 -96 464
IOPIN -16 256 Out
IOPIN -352 176 In
DATAFLAG -96 256 ""
SYMBOL voltage -272 16 R0
SYMATTR InstName Vpb
SYMATTR Value 0.8
SYMBOL pmos4 -144 192 M180
SYMATTR InstName M2
SYMATTR Value pch
SYMATTR Value2 l=180n w=10u m=2
SYMBOL voltage -176 416 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 60 56 VTop 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value SINE(0 {Vin} 100Meg)
SYMATTR Value2 AC 1
SYMBOL voltage -352 208 R0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL nmos4 -144 336 R0
SYMATTR InstName M1
SYMATTR Value nch
SYMATTR Value2 l=180n w=10u m=2
SYMBOL voltage -352 496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vbn
SYMATTR Value 0.6
FLAG -352 592 0
FLAG -96 592 0
FLAG -352 304 0
FLAG -16 256 OUT
FLAG -352 176 VDD
FLAG -176 32 VDD
TEXT 72 -24 Left 2 !.lib 'C:\\Program Files\\LTC\\LTspiceXVII\\lib\\cmp\\log018.l' TT
TEXT 72 8 Left 2 ;.dc Vin -0.4 1 0.001
TEXT 72 32 Left 2 ;.op
TEXT 80 64 Left 2 ;.ac dec 20 1k 100G
TEXT 80 88 Left 2 ;.tran 80n
TEXT 80 112 Left 2 !.noise V(OUT) Vin dec 20 1 100G
TEXT 80 136 Left 2 !.param Vin 12.5m
TEXT 80 168 Left 2 !.step param Vin list 12.5m 25m 50m 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\OP747.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP747.asy)
V2 -V 0 -15
R1 N001 0 10K
XU1 IN N001 +V -V OUT OP747 ;pnba In+)In-)V+)V-)OUT
R2 OUT N001 10K
Rload OUT 0 10K
Vin IN 0 SINE(0 1 1K)
V1 +V 0 15
.tran 10m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1248 416 -1248
WIRE 528 -1248 512 -1248
WIRE 544 -1248 528 -1248
WIRE 656 -1248 624 -1248
WIRE 112 -1152 112 -1168
WIRE 240 -1152 240 -1168
WIRE 576 -1136 576 -1152
WIRE 528 -1120 528 -1248
WIRE 544 -1120 528 -1120
WIRE 656 -1104 656 -1248
WIRE 656 -1104 608 -1104
WIRE 720 -1104 656 -1104
WIRE 544 -1088 368 -1088
WIRE 720 -1088 720 -1104
WIRE 368 -1072 368 -1088
WIRE 112 -1056 112 -1072
WIRE 240 -1056 240 -1072
WIRE 576 -1056 576 -1072
WIRE 720 -992 720 -1008
WIRE 368 -976 368 -992
SYMBOL Opamps\\OP747 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 704 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 112 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 528 -1264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 240 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 640 -1264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 368 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
FLAG 112 -1168 +V
FLAG 112 -1056 0
FLAG 368 -976 0
FLAG 720 -1104 OUT
FLAG 368 -1088 IN
FLAG 576 -1152 +V
FLAG 240 -1168 -V
FLAG 576 -1056 -V
FLAG 416 -1248 0
FLAG 720 -992 0
FLAG 240 -1056 0
TEXT 736 -952 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\01fed173e32d_6090.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6090.asy)
V2 +V 0 70
V4 IN 0 SINE(1.25 1.35 10K)
R1 OUT N002 435K
C1 OUT N002 10p
V3 N001 0 2.5
R3 N002 0 16.9K
XU1 NC_01 N002 IN NC_02 NC_03 OUT NC_04 NC_05 LTC6090 ;pnba COM)IN-)IN+)V-)_TF)OUT)V+)_OD
R2 N001 N002 16.2K
V1 -V 0 -70
.tran 250u
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1128 680
WIRE 208 -96 96 -96
WIRE 384 -96 320 -96
WIRE 528 -96 448 -96
WIRE -160 -80 -160 -96
WIRE -32 -80 -32 -96
WIRE 96 -80 96 -96
WIRE 208 -80 208 -96
WIRE -160 16 -160 0
WIRE -32 16 -32 0
WIRE 96 16 96 0
WIRE 208 16 208 0
WIRE 320 16 320 -96
WIRE 320 16 208 16
WIRE 384 16 320 16
WIRE 528 16 528 -96
WIRE 528 16 464 16
WIRE 208 32 208 16
WIRE 368 112 368 96
WIRE 208 128 208 112
WIRE 320 160 320 16
WIRE 352 160 320 160
WIRE 528 192 528 16
WIRE 528 192 512 192
WIRE 576 192 528 192
WIRE 352 224 48 224
WIRE 48 240 48 224
WIRE 368 304 368 272
WIRE 48 336 48 320
SYMBOL cap 448 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage -160 -96 R0
SYMATTR InstName V2
SYMATTR Value 70
SYMBOL voltage 48 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value SINE(1.25 1.35 10K)
SYMBOL res 480 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 435K
SYMBOL LTC6090 416 192 R0
SYMATTR InstName U1
SYMBOL voltage -32 -96 R0
SYMATTR InstName V1
SYMATTR Value -70
SYMBOL res 192 -96 R0
SYMATTR InstName R2
SYMATTR Value 16.2K
SYMBOL res 192 16 R0
SYMATTR InstName R3
SYMATTR Value 16.9K
SYMBOL voltage 96 -96 R0
SYMATTR InstName V3
SYMATTR Value 2.5
FLAG -32 16 0
FLAG -32 -96 -V
FLAG -160 16 0
FLAG -160 -96 +V
FLAG 368 304 -V
FLAG 368 96 +V
FLAG 576 192 OUT
FLAG 96 16 0
FLAG 208 128 0
FLAG 48 336 0
FLAG 48 224 IN
TEXT 528 328 Left 2 !.tran 250u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3012.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3012.asy)
XU1 IN OUT IN N001 0 LT3012 ;pnba IN)OUT)_SHDN)ADJ)GND
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 3.3
R2 N001 0 249K
Rload OUT 0 100
R1 OUT N001 750K
.tran 1
.lib LT3012.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 128 -96 128
WIRE 80 128 -64 128
WIRE 112 128 80 128
WIRE 432 128 400 128
WIRE 576 128 432 128
WIRE 624 128 576 128
WIRE 672 128 624 128
WIRE 432 144 432 128
WIRE 672 144 672 128
WIRE -96 160 -96 128
WIRE 576 160 576 128
WIRE 80 224 80 128
WIRE 112 224 80 224
WIRE 432 224 400 224
WIRE 432 240 432 224
WIRE 576 240 576 224
WIRE 672 240 672 224
WIRE -96 272 -96 240
WIRE 256 304 256 288
WIRE 432 336 432 320
SYMBOL voltage -96 144 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 656 128 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL res 416 224 R0
SYMATTR InstName R2
SYMATTR Value 249K
SYMBOL cap 560 160 R0
SYMATTR InstName C1
SYMATTR Value 3.3
SYMBOL LT3012 256 160 R0
SYMATTR InstName U1
SYMBOL res 416 128 R0
SYMATTR InstName R1
SYMATTR Value 750K
FLAG 256 304 0
FLAG -96 272 0
FLAG 672 240 0
FLAG 576 240 0
FLAG 432 336 0
FLAG 624 128 OUT
FLAG -64 128 IN
TEXT 584 312 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\c0207012c6dd_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 N003 0 0 BC547C
V1 N002 0 PULSE(0 5 0 1n 1n 1 2)
R2 P001 N001 998.7
R1 N003 N002 9.9k
V2 P001 0 5
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0 2.00000017 1.9999999 1u
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1344 680
WIRE 304 128 304 64
WIRE 128 176 80 176
WIRE 240 176 208 176
WIRE 80 224 80 176
WIRE 192 304 80 304
WIRE 304 304 304 224
WIRE 304 304 192 304
WIRE 192 336 192 304
SYMBOL npn2 240 128 R0
SYMATTR InstName Q1
SYMATTR Value BC547C
SYMBOL res 224 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 9.9k
SYMBOL voltage 304 0 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 288 -32 R0
SYMATTR InstName R2
SYMATTR Value 998.7
SYMBOL voltage 80 208 R0
WINDOW 3 -371 48 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 0 1n 1n 1 2)
SYMATTR InstName V1
FLAG 192 336 0
FLAG 304 -96 0
TEXT 112 272 Left 2 !.tran 0 2.00000017 1.9999999 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\eb7a640b0484_MOSFET_transfer.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 MC8
VDS N001 0 5
VGS N002 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VGS 0 1 0.01
.model MC8 NMOS (KP=60e-3 VTO=0.5 LAMBDA=0)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1412 680
WIRE 320 80 160 80
WIRE 160 112 160 80
WIRE 320 128 320 80
WIRE 240 160 160 160
WIRE 112 192 32 192
WIRE 32 208 32 192
WIRE 160 288 160 208
WIRE 240 288 240 160
WIRE 320 288 320 208
WIRE 32 320 32 288
SYMBOL nmos4 112 112 R0
SYMATTR InstName M1
SYMATTR Value MC8
SYMBOL voltage 320 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 5
SYMBOL voltage 32 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 0
FLAG 32 320 0
FLAG 160 288 0
FLAG 320 288 0
FLAG 240 288 0
TEXT 8 368 Left 2 !.dc VGS 0 1 0.01
TEXT 8 400 Left 2 !.model MC8 NMOS (KP=60e-3 VTO=0.5 LAMBDA=0)
* Z:\home\khalils\Downloads\files\data\raw_asc\15b3bfcd6e37_Lab2_NonIdeal.asc
* Generated by LTspice 26.0.1 for Windows.
* Ac 325
G4 N005 0 N001 0 {1/N}
Riron N004 0 30k
Rsec N006 N005 5
Vs N002 0 Sin(0 325 50)
R2 N001 0 1G
G1 0 N001 N004 0 1
Rs N003 N002 50
Rprimary N004 N003 70
Rload N006 0 100
G3 N004 0 N001 0 1
G2 0 N001 N005 0 {1/N}
.tran 50m
.param N=15 ; turns ratio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 160 0 112 0
WIRE 544 0 448 0
WIRE 160 16 160 0
WIRE 448 16 448 0
WIRE 304 32 208 32
WIRE 400 32 304 32
WIRE 304 128 304 32
WIRE 304 128 208 128
WIRE 400 128 304 128
WIRE 208 160 208 128
WIRE 304 160 304 128
WIRE 400 160 400 128
WIRE -176 176 -336 176
WIRE -48 176 -96 176
WIRE 160 176 160 96
WIRE 160 176 32 176
WIRE 448 176 448 96
WIRE 592 176 448 176
WIRE 720 176 672 176
WIRE -336 192 -336 176
WIRE 720 192 720 176
WIRE -32 224 -288 224
WIRE 112 224 112 0
WIRE 160 224 112 224
WIRE 544 224 544 0
WIRE 544 224 448 224
WIRE 656 224 544 224
WIRE -32 256 -32 224
WIRE 32 256 -32 256
WIRE 112 256 112 224
WIRE 112 256 32 256
WIRE 208 256 208 240
WIRE 304 256 304 240
WIRE 400 256 400 240
WIRE 656 272 656 224
WIRE 720 272 656 272
WIRE -336 288 -336 272
WIRE -288 288 -288 224
WIRE -288 288 -336 288
WIRE 720 288 720 272
RECTANGLE Normal 576 312 48 -96 2
SYMBOL g 400 144 M0
WINDOW 0 -10 9 Right 2
WINDOW 3 -15 96 Right 2
SYMATTR InstName G2
SYMATTR Value {1/N}
SYMBOL res 16 160 R0
SYMATTR InstName Riron
SYMATTR Value 30k
SYMBOL g 208 144 R0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL res 704 176 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL g 160 0 M0
WINDOW 0 -10 10 Right 2
WINDOW 3 -16 104 Right 2
SYMATTR InstName G3
SYMATTR Value 1
SYMBOL res 48 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rprimary
SYMATTR Value 70
SYMBOL res 288 144 R0
SYMATTR InstName R2
SYMATTR Value 1G
SYMBOL voltage -336 176 R0
SYMATTR InstName Vs
SYMATTR Value Sin(0 325 50)
SYMBOL res 688 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rsec
SYMATTR Value 5
SYMBOL res -80 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rs
SYMATTR Value 50
SYMBOL g 448 0 R0
WINDOW 0 13 18 Left 2
WINDOW 3 12 101 Left 2
SYMATTR InstName G4
SYMATTR Value {1/N}
FLAG -336 288 0
FLAG 400 256 0
FLAG 208 256 0
FLAG 208 80 0
FLAG 400 80 0
FLAG 304 256 0
FLAG 720 288 0
TEXT 528 336 Left 2 !.tran 50m
TEXT 192 296 Left 2 !.param N=15 ; turns ratio
TEXT -288 296 Left 2 ;Ac 325