* Z:\home\khalils\Downloads\files\data\raw_asc\1e8f086f832d_Fig13_23.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot q+2.5 d+1.25 clock
* Plot q+2.5 d+1.25 clock
M14 N001 clock_b N004 VDD P_50n l=50n w=1u
Vclock_b clock_b 0 PULSE 1 0 0 10p 10p 1.1n 2.2n
M7 D clock_b N002 0 N_50n l=50n w=500n
M13 N004 clock N001 0 N_50n l=50n w=500n
M5 N003 N004 0 0 N_50n l=50n w=500n
VDD VDD 0 1
M11 Q_bar Q 0 0 N_50n l=50n w=500n
M1 N004 N002 0 0 N_50n l=50n w=500n
M3 N002 clock D VDD P_50n l=50n w=1u
M12 Q_bar Q VDD VDD P_50n l=50n w=1u
M8 N003 clock_b N002 VDD P_50n l=50n w=1u
M16 Q_bar clock N001 VDD P_50n l=50n w=1u
M9 Q N001 0 0 N_50n l=50n w=500n
M2 N004 N002 VDD VDD P_50n l=50n w=1u
M6 N003 N004 VDD VDD P_50n l=50n w=1u
VD D 0 PULSE 0 1 300p 10p 10p 700p 1.9n
M15 N001 clock_b Q_bar 0 N_50n l=50n w=500n
M4 N002 clock N003 0 N_50n l=50n w=500n
M10 Q N001 VDD VDD P_50n l=50n w=1u
Vclock clock 0 PULSE 0 1 0 10p 10p 1.1n 2.2n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10n uic
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1824 680
WIRE 1120 -688 1120 -720
WIRE 1120 -688 1088 -688
WIRE 1216 -688 1216 -720
WIRE 1632 -688 1216 -688
WIRE 1120 -656 1120 -688
WIRE 1216 -656 1216 -688
WIRE 272 -640 272 -672
WIRE 272 -640 240 -640
WIRE 368 -640 368 -672
WIRE 768 -640 368 -640
WIRE 272 -608 272 -640
WIRE 368 -608 368 -640
WIRE 1296 -608 1264 -608
WIRE 1504 -608 1472 -608
WIRE 448 -560 416 -560
WIRE 656 -560 624 -560
WIRE 1088 -496 1088 -688
WIRE 1264 -496 1264 -608
WIRE 1264 -496 1088 -496
WIRE 1344 -496 1344 -528
WIRE 1440 -496 1344 -496
WIRE 1472 -496 1472 -608
WIRE 1472 -496 1440 -496
WIRE 1552 -496 1552 -528
WIRE 1632 -496 1632 -688
WIRE 1632 -496 1552 -496
WIRE 1728 -496 1632 -496
WIRE 912 -480 912 -512
WIRE 912 -480 800 -480
WIRE 240 -448 240 -640
WIRE 416 -448 416 -560
WIRE 416 -448 240 -448
WIRE 496 -448 496 -480
WIRE 576 -448 496 -448
WIRE 624 -448 624 -560
WIRE 624 -448 576 -448
WIRE 704 -448 704 -480
WIRE 768 -448 768 -640
WIRE 768 -448 704 -448
WIRE 912 -448 912 -480
WIRE 1008 -448 1008 -512
WIRE 1088 -448 1088 -496
WIRE 1088 -448 1008 -448
WIRE 1264 -416 1264 -496
WIRE 1296 -416 1264 -416
WIRE 1472 -416 1472 -496
WIRE 1504 -416 1472 -416
WIRE 64 -400 64 -464
WIRE 64 -400 0 -400
WIRE 160 -400 160 -464
WIRE 240 -400 240 -448
WIRE 240 -400 160 -400
WIRE 416 -368 416 -448
WIRE 448 -368 416 -368
WIRE 624 -368 624 -448
WIRE 656 -368 624 -368
WIRE 1344 -352 1344 -400
WIRE 1552 -352 1552 -400
WIRE 496 -304 496 -352
WIRE 704 -304 704 -352
WIRE 1440 -304 1440 -496
WIRE 1728 -304 1440 -304
WIRE 576 -256 576 -448
WIRE 800 -256 800 -480
WIRE 800 -256 576 -256
WIRE 16 -240 16 -256
WIRE 16 -224 16 -240
WIRE 160 -176 160 -192
WIRE 160 -160 160 -176
WIRE 352 -160 352 -192
WIRE 480 -160 480 -192
WIRE 16 -112 16 -144
WIRE 160 -48 160 -80
WIRE 352 -48 352 -80
WIRE 480 -48 480 -80
SYMBOL pmos4 448 -480 M180
WINDOW 0 88 9 Invisible 2
WINDOW 3 168 20 Invisible 2
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 16 -240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 368 -720 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M8
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 272 -560 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M4
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 1008 -560 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M14
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 1504 -528 M180
WINDOW 0 88 9 Invisible 2
WINDOW 3 168 20 Invisible 2
SYMATTR InstName M12
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 1296 -528 M180
WINDOW 0 88 9 Invisible 2
WINDOW 3 168 20 Invisible 2
SYMATTR InstName M10
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 1296 -496 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M9
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 480 -176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 19 101 Left 2
SYMATTR Value PULSE 1 0 0 10p 10p 1.1n 2.2n
SYMATTR InstName Vclock_b
SYMBOL nmos4 64 -352 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M7
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 1504 -496 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M11
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 656 -448 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 912 -400 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M13
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 1216 -768 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M16
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 656 -480 M180
WINDOW 0 88 9 Invisible 2
WINDOW 3 168 20 Invisible 2
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 160 -512 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 448 -448 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 160 -176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -161 204 Left 2
SYMATTR Value PULSE 0 1 300p 10p 10p 700p 1.9n
SYMATTR InstName VD
SYMBOL nmos4 1120 -608 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M15
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 352 -176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -99 164 Left 2
SYMATTR Value PULSE 0 1 0 10p 10p 1.1n 2.2n
SYMATTR InstName Vclock
FLAG 496 -400 0
FLAG 16 -112 0
FLAG 16 -240 VDD
FLAG 496 -528 VDD
FLAG 496 -304 0
FLAG 496 -576 VDD
FLAG 704 -400 0
FLAG 704 -528 VDD
FLAG 704 -304 0
FLAG 704 -576 VDD
FLAG 112 -400 0
FLAG 0 -400 D
FLAG 144 -352 clock_b
FLAG 160 -48 0
FLAG 160 -176 D
FLAG 480 -48 0
FLAG 480 -192 clock_b
FLAG 352 -48 0
FLAG 352 -192 clock
FLAG 112 -464 VDD
FLAG 80 -512 clock
FLAG 320 -608 0
FLAG 352 -560 clock
FLAG 320 -672 VDD
FLAG 288 -720 clock_b
FLAG 1344 -448 0
FLAG 1344 -576 VDD
FLAG 1344 -352 0
FLAG 1344 -624 VDD
FLAG 1552 -448 0
FLAG 1552 -576 VDD
FLAG 1552 -352 0
FLAG 1552 -624 VDD
FLAG 960 -448 0
FLAG 992 -400 clock
FLAG 1728 -496 Q_bar
FLAG 1728 -304 Q
FLAG 960 -512 VDD
FLAG 928 -560 clock_b
FLAG 1168 -656 0
FLAG 1200 -608 clock_b
FLAG 1168 -720 VDD
FLAG 1136 -768 clock
TEXT 992 -200 Left 2 !.tran 10n uic
TEXT 992 -176 Left 2 !.include cmosedu_models.txt
TEXT 232 -712 Right 2 ;Plot q+2.5 d+1.25 clock
TEXT 1080 -760 Right 2 ;Plot q+2.5 d+1.25 clock