Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1551LCS8-4.1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1551LCS8-4.1.asy)
C3 OUT 0 10
XU1 0 IN N002 OUT N003 0 N001 OUT LTC1551LCS8-4.1 ;pnba SHDN)Vin)C+)Vout)C-)GND)CPout)REG
Rload OUT 0 1K
V1 IN 0 5
C1 N003 N002 .1
C2 N001 0 .1
.tran 1m
.lib LTC1551LCS8-4.1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1600 908
WIRE 544 32 144 32
WIRE 240 112 224 112
WIRE 544 112 544 32
WIRE 544 112 528 112
WIRE 240 176 -80 176
WIRE 560 176 528 176
WIRE 656 176 624 176
WIRE -80 192 -80 176
WIRE 240 240 224 240
WIRE 544 240 528 240
WIRE -80 288 -80 272
WIRE 144 304 144 32
WIRE 144 304 16 304
WIRE 240 304 144 304
WIRE 544 304 528 304
WIRE 16 320 16 304
WIRE 144 336 144 304
WIRE 16 416 16 400
WIRE 144 416 144 400
WIRE 224 416 224 240
WIRE 368 416 224 416
WIRE 544 416 544 304
WIRE 544 416 432 416
SYMBOL PowerProducts\\LTC1551LCS8-4.1 384 208 R0
SYMATTR InstName U1
SYMBOL cap 432 400 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL cap 128 336 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL voltage -80 176 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 560 192 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL res 0 304 R0
SYMATTR InstName Rload
SYMATTR Value 1K
FLAG 656 176 0
FLAG 544 240 0
FLAG 16 416 0
FLAG 144 416 0
FLAG -80 288 0
FLAG 224 112 0
FLAG 16 304 OUT
FLAG -80 176 IN
TEXT 544 488 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3221-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3221-3.3.asy)
XU1 N001 N002 IN 0 IN OUT LTC3221-3.3 ;pnba C+)C-)_SHDN)GND)Vin)Vout
V1 IN 0 2.5
C2 OUT 0 4.7
Rload OUT 0 55
C1 N001 N002 1
.tran 1m startup
.lib LTC3221-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 96 0 96
WIRE 96 96 80 96
WIRE 464 96 352 96
WIRE 560 96 464 96
WIRE 0 112 0 96
WIRE 464 112 464 96
WIRE 560 112 560 96
WIRE 80 192 80 96
WIRE 96 192 80 192
WIRE 384 192 352 192
WIRE 0 208 0 192
WIRE 384 208 384 192
WIRE 464 208 464 176
WIRE 560 208 560 192
WIRE 96 288 80 288
WIRE 384 288 384 272
WIRE 384 288 352 288
SYMBOL res 544 96 R0
SYMATTR InstName Rload
SYMATTR Value 55
SYMBOL voltage 0 96 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL cap 368 208 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\LTC3221-3.3 224 192 R0
SYMATTR InstName U1
SYMBOL cap 448 112 R0
SYMATTR InstName C2
SYMATTR Value 4.7
FLAG 0 208 0
FLAG 560 208 0
FLAG 464 208 0
FLAG 560 96 OUT
FLAG 0 96 IN
FLAG 80 288 0
TEXT 424 320 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1275d14e8401_SolenoidValveControlCircuit.asc
* Generated by LTspice 26.0.1 for Windows.
D2 drain 12V RR1LAM6S
R3 VREF drain 3k
V2 12V 0 12
M1 drain gate 0 0 RSQ045N03
R4 12V VREF 12k
R1 gate 0 10k
L1 OUTPUT 12V 10
R2 gate CTL 200
V3 VREF 0 5
D1 CTL 0 STW8B12C
R5 OUTPUT drain 10
V1 CTL 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 448 -160 320 -160
WIRE 544 -160 544 -208
WIRE 544 -160 448 -160
WIRE 592 -160 544 -160
WIRE 704 -160 672 -160
WIRE 544 -144 544 -160
WIRE 704 -144 704 -160
WIRE 448 -80 448 -160
WIRE 144 -48 128 -48
WIRE 192 -48 144 -48
WIRE 320 -48 320 -80
WIRE 320 -48 192 -48
WIRE 544 -48 544 -64
WIRE 736 -48 544 -48
WIRE 752 -48 736 -48
WIRE 192 -32 192 -48
WIRE 320 -16 320 -48
WIRE 192 64 192 48
WIRE 320 64 240 64
WIRE 448 64 448 -16
WIRE 448 64 320 64
WIRE 544 64 544 32
WIRE 544 64 448 64
WIRE -240 96 -288 96
WIRE -288 128 -288 96
WIRE 240 128 240 64
WIRE 240 144 240 128
WIRE -160 224 -160 96
WIRE -160 224 -192 224
WIRE -128 224 -160 224
WIRE 48 224 -48 224
WIRE 144 224 48 224
WIRE 192 224 144 224
WIRE 240 304 240 240
WIRE -160 320 -160 224
WIRE 48 336 48 304
WIRE 240 336 240 304
WIRE -160 432 -160 384
IOPIN -192 224 In
IOPIN 144 -48 Out
IOPIN 544 -208 In
IOPIN 736 -48 Out
SYMBOL LED -176 320 R0
SYMATTR InstName D1
SYMATTR Value STW8B12C
SYMBOL nmos 192 144 R0
SYMATTR InstName M1
SYMATTR Value RSQ045N03
SYMBOL res 304 -32 R0
SYMATTR InstName R3
SYMATTR Value 3k
SYMBOL res 304 -176 R0
SYMATTR InstName R4
SYMATTR Value 12k
SYMBOL voltage 576 -160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL voltage 192 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL diode 464 -16 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value RR1LAM6S
SYMBOL res 528 -64 R0
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL ind 560 -48 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL res -32 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL res 32 208 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -144 96 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -192 224 CTL
FLAG 240 336 0
FLAG 144 -48 VREF
FLAG 544 -208 12V
FLAG -160 432 0
FLAG 48 336 0
FLAG 736 -48 OUTPUT
FLAG -288 128 0
FLAG 704 -144 0
FLAG 192 64 0
FLAG 144 224 gate
FLAG 240 128 drain
FLAG 240 304 source
TEXT -310 458 Left 2 !.tran 10
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG742.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG742.asy)
V4 N003 0 PULSE(0 3 0 10n 10n 980n 2u)
XU2 N003 N002 N001 0 +V ADG742 ;pnba IN)D)S)GND)Vdd
R1 N002 0 300
C1 N002 0 35p
V1 +V 0 5
VS N001 0 3
.tran 10u
.lib ADG742.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -240 -16 -288 -16
WIRE 0 -16 -48 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -240 48 -368 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL ADG742 -144 32 R0
SYMATTR InstName U2
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V4
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
TEXT -536 200 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1402.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 15V dual supply\nPin Capacitance not included
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1402.asy)
V1 vS 0 10
XU1 v+ v- vIN vS vD 0 ADG1402 ;pnba Vdd)Vss)IN)S)D)GND
V4 v- 0 -15
V3 v+ 0 15
R1 vD 0 301
V2 vIN 0 PULSE(3 0 0 1u 1u 5m 10m)
.tran 30m
.lib ADG1402.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 936 832
WIRE 240 160 240 96
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 464 256 464 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -320 336 -320 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 288 448 288 400
WIRE -320 464 -320 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
WIRE 192 464 192 400
SYMBOL voltage -320 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL ADG1402 240 272 R0
SYMATTR InstName U1
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -20 198 Left 2
SYMATTR Value PULSE(3 0 0 1u 1u 5m 10m)
SYMATTR InstName V2
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 288 448 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG -192 304 v-
FLAG 240 96 v+
FLAG -192 464 0
FLAG 192 464 v-
FLAG -320 304 v+
FLAG -320 464 0
TEXT 440 512 Left 2 !.tran 30m
TEXT -360 -16 Left 2 ;Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 15V dual supply\nPin Capacitance not included
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4219-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4219-12.asy)
C1 N004 0 .1
V1 IN 0 12
XU1 NC_01 IN 0 0 N004 N004 0 OUT MP_02 MP_03 MP_04 MP_05 NC_06 N002 NC_07 NC_08 N003 NC_09 LTC4219-12 ;pnba Sense)Vdd)_EN1)_EN2)Timer)IntVcc)GND)Out)))))Gate)_PG)_FLT)FB)Imon)Iset
V2 N001 0 PULSE(0 1 240m 1m 1m 10m)
S1 0 OUT N001 0 SHORT
C2 OUT 0 330
R1 N003 0 20K
R2 OUT N002 20K
.tran 600m startup
.model SHORT SW(Ron=10m Roff=1K Vt=.5 Vh=-.4)
.lib LTC4219-12.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1592 680
WIRE 80 16 -48 16
WIRE 416 16 368 16
WIRE 512 16 416 16
WIRE 624 16 512 16
WIRE -48 32 -48 16
WIRE 416 32 416 16
WIRE 512 32 512 16
WIRE 624 32 624 16
WIRE 848 48 672 48
WIRE 944 48 928 48
WIRE 80 80 48 80
WIRE -48 128 -48 112
WIRE 512 128 512 96
WIRE 624 128 624 112
WIRE 80 144 48 144
WIRE 416 144 416 112
WIRE 416 144 368 144
WIRE 384 208 368 208
WIRE 480 208 464 208
WIRE 432 272 368 272
WIRE 432 336 432 272
WIRE 432 336 368 336
WIRE 432 352 432 336
WIRE 224 400 224 384
WIRE 432 432 432 416
SYMBOL res 368 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 20K
SYMBOL voltage -48 16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 400 16 R0
SYMATTR InstName R2
SYMATTR Value 20K
SYMBOL cap 496 32 R0
SYMATTR InstName C2
SYMATTR Value 330
SYMBOL voltage 832 48 R270
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 240m 1m 1m 10m)
SYMBOL sw 624 128 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SHORT
SYMBOL cap 416 352 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL LTC4219-12 224 176 R0
SYMATTR InstName U1
FLAG 432 432 0
FLAG 224 400 0
FLAG 480 208 0
FLAG -48 128 0
FLAG 512 128 0
FLAG 624 128 0
FLAG 672 96 0
FLAG 944 48 0
FLAG -48 16 IN
FLAG 624 16 OUT
FLAG 48 80 0
FLAG 48 144 0
TEXT 560 296 Left 2 !.tran 600m startup\n.model SHORT SW(Ron=10m Roff=1K Vt=.5 Vh=-.4)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3070-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3070-1.asy)
Rload OUT 0 .18
R1 N001 N002 50K
V2 IN 0 1.2
C1 0 N005 .01
C3 OUT 0 20
XU1 0 N001 0 0 N001 N005 N004 N003 IN OUT OUT N001 P001 N002 LT3070-1 ;pnba GND)V00)V01)V02)Bias)Ref/BYP)MargTol)MargSel)IN)Sense)Out)En)VIOC)PWRGD
V1 N001 0 3
C2 0 P001 .01
.tran 2m startup
.lib LT3070-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1252 1304
WIRE 480 64 80 64
WIRE 480 80 480 64
WIRE 288 112 -48 112
WIRE -48 128 -48 112
WIRE 288 128 288 112
WIRE 80 176 80 64
WIRE 128 176 80 176
WIRE 480 176 480 160
WIRE 480 176 448 176
WIRE -48 224 -48 208
WIRE 80 288 80 176
WIRE 80 288 -48 288
WIRE 128 288 80 288
WIRE 496 288 448 288
WIRE 592 288 496 288
WIRE -48 304 -48 288
WIRE 592 304 592 288
WIRE -48 400 -48 384
WIRE 80 400 80 288
WIRE 128 400 80 400
WIRE 496 400 496 288
WIRE 496 400 448 400
WIRE 592 400 592 384
WIRE 496 480 496 464
WIRE 128 512 96 512
WIRE 480 512 448 512
WIRE 128 624 96 624
WIRE 480 624 448 624
WIRE 64 736 48 736
WIRE 464 736 448 736
WIRE 544 736 528 736
WIRE 288 816 288 784
SYMBOL voltage -48 288 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL cap 480 400 R0
WINDOW 3 26 56 Left 2
SYMATTR Value 20
SYMATTR InstName C3
SYMBOL cap 528 720 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .01
SYMBOL LT3070-1 288 448 R0
SYMATTR InstName U1
SYMBOL cap 64 752 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL res 464 64 R0
SYMATTR InstName R1
SYMATTR Value 50K
SYMBOL voltage -48 112 R0
SYMATTR InstName V2
SYMATTR Value 1.2
SYMBOL res 576 288 R0
SYMATTR InstName Rload
SYMATTR Value .18
FLAG 544 736 0
FLAG 96 624 0
FLAG 96 512 0
FLAG -48 224 0
FLAG -48 400 0
FLAG 48 736 0
FLAG 496 480 0
FLAG 592 400 0
FLAG -48 112 IN
FLAG 592 288 OUT
FLAG 288 816 0
TEXT 608 784 Left 2 !.tran 2m startup
* Z:\tmp\asc_dec_bjh7r6w2\071d43a8b810_6248_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R3 OUT- N003 1K
V2 N004 0 PULSE(0 1 0 10n 10n 5u 10us 25)
XU1 OUT- 0 N006 N001 +V LTC6247 ;pnba 1)4)3)2)7
XU2 OUT+ 0 N005 N003 +V LTC6247 ;pnba 1)4)3)2)7
C1 OUT- N001 68p
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6248.asy)
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 888 688
WIRE -10976 -3072 -11040 -3072
WIRE -10880 -3072 -10912 -3072
WIRE -11136 -2976 -11216 -2976
WIRE -11040 -2976 -11040 -3072
WIRE -11040 -2976 -11056 -2976
WIRE -10992 -2976 -11040 -2976
WIRE -10880 -2976 -10880 -3072
WIRE -10880 -2976 -10912 -2976
WIRE -10864 -2976 -10880 -2976
WIRE -10768 -2976 -10784 -2976
WIRE -10688 -2976 -10768 -2976
WIRE -10592 -2976 -10608 -2976
WIRE -10560 -2976 -10592 -2976
WIRE -11568 -2944 -11584 -2944
WIRE -11312 -2944 -11488 -2944
WIRE -11264 -2944 -11312 -2944
WIRE -11264 -2896 -11280 -2896
WIRE -10768 -2896 -10768 -2976
WIRE -10736 -2896 -10768 -2896
WIRE -10592 -2880 -10592 -2976
WIRE -10592 -2880 -10672 -2880
WIRE -10736 -2864 -10768 -2864
WIRE -11216 -2848 -11280 -2848
WIRE -10704 -2832 -10704 -2848
WIRE -11312 -2816 -11312 -2944
WIRE -11264 -2816 -11312 -2816
WIRE -11040 -2816 -11040 -2976
WIRE -10992 -2816 -11040 -2816
WIRE -10880 -2800 -10880 -2976
WIRE -10880 -2800 -10928 -2800
WIRE -10560 -2800 -10880 -2800
WIRE -10992 -2784 -11040 -2784
WIRE -11440 -2768 -11440 -2784
WIRE -11264 -2768 -11312 -2768
WIRE -11312 -2752 -11312 -2768
WIRE -10960 -2752 -10960 -2768
WIRE -11136 -2720 -11216 -2720
WIRE -11040 -2720 -11040 -2784
WIRE -11040 -2720 -11056 -2720
WIRE -10928 -2720 -11040 -2720
WIRE -10592 -2720 -10592 -2880
WIRE -10592 -2720 -10848 -2720
WIRE -11040 -2688 -11040 -2720
WIRE -10768 -2688 -10768 -2864
WIRE -11040 -2608 -11040 -2624
WIRE -10768 -2592 -10768 -2608
SYMBOL RES -10880 -2992 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL VOLTAGE -11472 -2944 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 123 74 56 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 10n 10n 5u 10us 25)
SYMBOL LTC6248 -10960 -2800 R0
WINDOW 3 68 19 Center 2
SYMATTR InstName U1
SYMBOL LTC6248 -10704 -2880 R0
WINDOW 3 57 35 Center 2
SYMATTR InstName U2
SYMBOL cap -10912 -3088 R90
WINDOW 0 0 29 VBottom 2
WINDOW 3 35 25 VTop 2
SYMATTR InstName C1
SYMATTR Value 68p
FLAG -11440 -2784 +V
FLAG -10960 -2752 0
FLAG -10704 -2832 0
FLAG -11040 -2608 0
FLAG -11584 -2944 0
FLAG -11280 -2848 0
FLAG -11280 -2896 0
FLAG -10560 -2976 OUT+
FLAG -10560 -2800 OUT-
FLAG -10960 -2832 +V
FLAG -10704 -2912 +V
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3484-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3484-2.asy)
D1 N001 OUT D
L2 0 N001 {10u*10.2*10.2} Rpar=1Meg
V1 IN 0 5
XU1 N002 IN IN N003 MP_01 IN 0 LT3484-2 ;pnba _Done)Charge)Vin)SW))Vbat)GND
C1 OUT 0 .01
L1 IN N003 10 Rpar=2K Rser=.1
K1 L1 L2 1
R3 N002 IN 10K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT3484-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2772 1752
WIRE 1808 1264 1648 1264
WIRE 1936 1264 1808 1264
WIRE 2064 1264 1936 1264
WIRE 2224 1264 2112 1264
WIRE 2368 1264 2288 1264
WIRE 1808 1296 1808 1264
WIRE 1936 1296 1936 1264
WIRE 2064 1296 2064 1264
WIRE 2112 1296 2112 1264
WIRE 2368 1296 2368 1264
WIRE 1648 1360 1648 1264
WIRE 1664 1360 1648 1360
WIRE 1760 1360 1744 1360
WIRE 2368 1376 2368 1360
WIRE 2112 1392 2112 1376
WIRE 2064 1408 2064 1376
WIRE 2064 1408 1984 1408
WIRE 1648 1456 1648 1360
WIRE 1760 1456 1648 1456
WIRE 1648 1472 1648 1456
WIRE 1872 1552 1872 1520
WIRE 1648 1568 1648 1552
SYMBOL cap 2352 1296 R0
WINDOW 3 27 55 Left 2
SYMATTR Value .01
SYMATTR InstName C1
SYMBOL ind2 2048 1280 R0
WINDOW 0 -6 35 Right 2
WINDOW 3 -4 73 Right 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rpar=2K Rser=.1
SYMBOL ind2 2128 1392 R180
WINDOW 0 -3 72 Right 2
WINDOW 3 0 43 Right 2
SYMATTR InstName L2
SYMATTR Value {10u*10.2*10.2}
SYMATTR SpiceLine Rpar=1Meg
SYMBOL diode 2224 1280 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL PowerProducts\\LT3484-2 1872 1408 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1648 1456 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 1760 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
FLAG 2368 1376 0
FLAG 1872 1552 0
FLAG 1648 1568 0
FLAG 2112 1392 0
FLAG 1648 1264 IN
FLAG 2368 1264 OUT
TEXT 2048 1480 Left 2 !.tran 2m startup
TEXT 2088 1264 Bottom 2 !K1 L1 L2 1
* Z:\home\khalils\Downloads\files\data\raw_asc\3d5e34efd539_comparator_99.asc
* Generated by LTspice 26.0.1 for Windows.
* All parameters that will be optimized\nshould be listed in tables\nwith arbitrary values.
V2 N001 0 {Vcomp}
M2 Vdd Vin Vout Vdd PMOS l={L2} w={W2} ad={W2*L2} as={W2*L2} pd={2*W1+2*L1} ps={2*W1+2*L1} m=1
M1 Vout N001 0 0 NMOS l={L1} w={W1} ad={W1*L1} as={W1*L1} pd={2*W1+2*L1} ps={2*W1+2*L1} m=1
V3 Vin 0
V1 Vdd 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.param W1=2.9u
.param W2=2.6u
.param Vcomp=648.0m
.param L1=1.7u
.param L2=2.1u
.dc V3 0 1.8 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4496 2148
WIRE -80 -480 -112 -480
WIRE -64 -480 -80 -480
WIRE -272 -416 -336 -416
WIRE -224 -416 -272 -416
WIRE -112 -416 -112 -480
WIRE -64 -416 -112 -416
WIRE -336 -384 -336 -416
WIRE -64 -368 -64 -416
WIRE -64 -368 -112 -368
WIRE -224 -336 -224 -416
WIRE -160 -336 -224 -336
WIRE -656 -320 -656 -384
WIRE -336 -256 -336 -304
WIRE -112 -240 -112 -320
WIRE 32 -240 -112 -240
WIRE -656 -192 -656 -240
WIRE -112 -192 -112 -240
WIRE -240 -176 -336 -176
WIRE -336 -144 -336 -176
WIRE -80 -144 -112 -144
WIRE -240 -112 -240 -176
WIRE -160 -112 -240 -112
WIRE -112 -80 -112 -96
WIRE -80 -80 -80 -144
WIRE -80 -80 -112 -80
WIRE -112 -32 -112 -80
WIRE -336 -16 -336 -64
SYMBOL voltage -336 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vcomp}
SYMBOL voltage -656 -336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL pmos4 -160 -416 R0
SYMATTR InstName M2
SYMATTR Value2 l={L2} w={W2} ad={W2*L2} as={W2*L2} pd={2*W1+2*L1} ps={2*W1+2*L1} m=1
SYMBOL voltage -336 -400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
SYMBOL nmos4 -160 -192 R0
SYMATTR InstName M1
SYMATTR Value2 l={L1} w={W1} ad={W1*L1} as={W1*L1} pd={2*W1+2*L1} ps={2*W1+2*L1} m=1
FLAG -656 -192 0
FLAG -80 -480 Vdd
FLAG -656 -384 Vdd
FLAG -112 -32 0
FLAG -336 -16 0
FLAG -336 -256 0
FLAG -272 -416 Vin
FLAG 32 -240 Vout
TEXT -360 -728 Left 2 !.param W1=2.9u
TEXT -360 -704 Left 2 !.param W2=2.6u
TEXT -360 -632 Left 2 !.param Vcomp=648.0m
TEXT -360 -680 Left 2 !.param L1=1.7u
TEXT -360 -656 Left 2 !.param L2=2.1u
TEXT 72 -680 Left 2 !.dc V3 0 1.8 0.01
TEXT -384 -848 Left 2 ;All parameters that will be optimized\nshould be listed in tables\nwith arbitrary values.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-3.0.asy)
C2 OUT 0 1
V1 IN 0 5.5
Rload OUT 0 100
C1 IN 0 1
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=40000 ;pnba Vout))Sense)GND)En)))Vin
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL ADP124-3.0 256 208 R0
SYMATTR InstName U1
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\25a23fe35071_FirstAnd.asc
* Generated by LTspice 26.0.1 for Windows.
* 74HCT00
* The following parameters are accepted, but don't have any effect.
* Rout=50 Iout=20m
* Ref = threshhold
A1 0 in1 0 in2 0 out 0 0 AND td=10n trise=10n tfall=10n vhigh=5 Ref=1.5
V2 in2 0 PULSE(0 5 150n 100n 100n 100n 500n)
R2 out N001 1k
V3 N001 0 2.5
V1 in1 0 PULSE(0 5 100n 5n 5n 400n 500n)
.tran 0 1u 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 996 680
WIRE -288 208 -288 144
WIRE -288 320 -288 288
WIRE -128 208 -128 176
WIRE -128 320 -128 288
WIRE 48 144 -288 144
WIRE 48 176 -128 176
WIRE 400 176 112 176
WIRE 400 224 400 176
WIRE 400 352 400 304
WIRE 400 464 400 432
WIRE 480 176 400 176
IOPIN 480 176 Out
SYMBOL voltage -128 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 150n 100n 100n 100n 500n)
SYMBOL voltage -288 192 R0
WINDOW 3 -25 187 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 100n 5n 5n 400n 500n)
SYMATTR InstName V1
SYMBOL voltage 400 336 R0
SYMATTR InstName V3
SYMATTR Value 2.5
SYMBOL Digital\\and 80 96 R0
WINDOW 3 -6 114 Left 0
SYMATTR Value td=10n
SYMATTR InstName A1
SYMATTR Value2 trise=10n tfall=10n
SYMATTR SpiceLine vhigh=5 Ref=1.5
SYMBOL res 384 208 R0
SYMATTR InstName R2
SYMATTR Value 1k
FLAG -288 320 0
FLAG -128 320 0
FLAG 480 176 out
FLAG -288 144 in1
FLAG -128 176 in2
FLAG 400 464 0
TEXT -304 56 Left 0 !.tran 0 1u 0 1n
TEXT 8 56 Left 0 ;74HCT00
TEXT -296 -24 Left 0 ;The following parameters are accepted, but don't have any effect.
TEXT -296 8 Left 0 ;Rout=50 Iout=20m
TEXT 16 248 Left 0 ;Ref = threshhold