Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8610AB.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8610AB.asy)
Rload OUT 0 1.42
C2 N001 0 1
C3 N003 N005 .1
R1 N006 0 60.4K
L1 N005 OUT 4.7 Rser=3m
V1 IN 0 24
C1 N004 0 .001
XU1 MP_01 N004 N006 IN IN MP_02 0 MP_03 N005 MP_04 MP_05 N003 N001 OUT NC_06 N007 0 LT8610AB ;pnba )TR/SS)Rt)EN/UV)Vin))PGND))SW)))BST)INTVcc)Bias)PG)FB)GND
R2 OUT N007 1Meg
C4 OUT 0 47 x2 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
C5 OUT N007 10p
R3 N007 0 243K
.tran 750u startup
.lib LT8610AB.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1028 680
WIRE 96 -64 0 -64
WIRE 256 -64 96 -64
WIRE 0 -48 0 -64
WIRE 256 -48 256 -64
WIRE 96 0 96 -64
WIRE 112 0 96 0
WIRE 448 0 400 0
WIRE 528 0 512 0
WIRE 0 48 0 32
WIRE 112 96 96 96
WIRE 592 96 400 96
WIRE 432 192 400 192
WIRE 432 208 432 192
WIRE 32 288 16 288
WIRE 112 288 96 288
WIRE 432 288 432 272
WIRE 432 288 400 288
WIRE 480 288 432 288
WIRE 592 288 592 96
WIRE 592 288 560 288
WIRE 704 288 592 288
WIRE 800 288 704 288
WIRE 896 288 800 288
WIRE 592 304 592 288
WIRE 704 304 704 288
WIRE 800 304 800 288
WIRE 896 304 896 288
WIRE 16 384 0 384
WIRE 112 384 96 384
WIRE 592 384 400 384
WIRE 704 384 704 368
WIRE 704 384 592 384
WIRE 592 400 592 384
WIRE 800 400 800 368
WIRE 896 400 896 384
WIRE 192 448 192 432
WIRE 320 448 320 432
WIRE 592 496 592 480
SYMBOL ind 464 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL PowerProducts\\LT8610AB 256 192 R0
SYMATTR InstName U1
SYMBOL cap 784 304 R0
WINDOW 123 24 64 Left 2
WINDOW 3 35 35 Left 2
SYMATTR Value2 x2
SYMATTR Value 47
SYMATTR InstName C4
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL res 112 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 60.4K
SYMBOL cap 688 304 R0
SYMATTR InstName C5
SYMATTR Value 10p
SYMBOL cap 448 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 576 384 R0
SYMATTR InstName R3
SYMATTR Value 243K
SYMBOL cap 96 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .001
SYMBOL voltage 0 -64 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 880 288 R0
SYMATTR InstName Rload
SYMATTR Value 1.42
SYMBOL cap 416 208 R0
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL res 576 288 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
FLAG 192 448 0
FLAG 320 448 0
FLAG 0 384 0
FLAG 16 288 0
FLAG 0 48 0
FLAG 528 0 0
FLAG 800 400 0
FLAG 592 496 0
FLAG 896 400 0
FLAG 896 288 OUT
FLAG 0 -64 IN
TEXT 776 464 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1701B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1701B.asy)
V1 IN 0 5
XU1 N001 0 N004 N003 IN LTC1701B ;pnba SW)GND)FB)Ith/Run)Vin
C1 OUT 0 47 Rser=.1
Rload OUT 0 10
R2 N004 0 121K
R4 N003 N002 5.1K
R3 IN N003 1Meg
C2 N002 0 330p
R1 OUT N004 121K
L1 N001 OUT 4.7
D1 0 N001 1N5817
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran .5m startup
.lib LTC1701B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2596 1504
WIRE 1600 1184 1424 1184
WIRE 1696 1184 1600 1184
WIRE 2032 1184 1984 1184
WIRE 2080 1184 2032 1184
WIRE 2192 1184 2160 1184
WIRE 2304 1184 2192 1184
WIRE 2416 1184 2304 1184
WIRE 1424 1200 1424 1184
WIRE 1600 1200 1600 1184
WIRE 2032 1200 2032 1184
WIRE 2192 1200 2192 1184
WIRE 2304 1200 2304 1184
WIRE 2416 1200 2416 1184
WIRE 2032 1280 2032 1264
WIRE 1424 1296 1424 1280
WIRE 2304 1296 2304 1264
WIRE 2416 1296 2416 1280
WIRE 1504 1312 1472 1312
WIRE 1600 1312 1600 1280
WIRE 1600 1312 1584 1312
WIRE 1696 1312 1600 1312
WIRE 2192 1312 2192 1280
WIRE 2192 1312 1984 1312
WIRE 2192 1328 2192 1312
WIRE 1472 1344 1472 1312
WIRE 1472 1424 1472 1408
WIRE 1840 1424 1840 1392
WIRE 2192 1424 2192 1408
SYMBOL PowerProducts\\LTC1701B 1840 1248 R0
SYMATTR InstName U1
SYMBOL res 2400 1184 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL polcap 2288 1200 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMATTR SpiceLine Rser=.1
SYMBOL res 1600 1296 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 5.1K
SYMBOL ind 2064 1200 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL res 2176 1312 R0
SYMATTR InstName R2
SYMATTR Value 121K
SYMBOL cap 1456 1344 R0
SYMATTR InstName C2
SYMATTR Value 330p
SYMBOL RES 2176 1184 R0
SYMATTR InstName R1
SYMATTR Value 121K
SYMBOL VOLTAGE 1424 1184 R0
WINDOW 3 25 99 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL diode 2016 1264 M180
WINDOW 0 27 63 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N5817
SYMBOL res 1584 1184 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
FLAG 2032 1280 0
FLAG 2304 1296 0
FLAG 2192 1424 0
FLAG 1840 1424 0
FLAG 1472 1424 0
FLAG 1424 1296 0
FLAG 2416 1296 0
FLAG 2416 1184 OUT
FLAG 1424 1184 IN
TEXT 1984 1488 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8337-1.asc
* Generated by LTspice 26.0.1 for Windows.
* 2MHz
* 15V
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8337-1.asy)
V1 IN 0 7.2
C6 OUT 0 22 x4 Rser=10m
R3 N003 N005 100k
R1 OUT N004 1Meg
R2 N004 0 71.5k
Rload OUT 0 25
R4 N007 0 47.5k
XU1 0 N007 0 N004 OUT N001 N002 N006 IN IN N003 LT8337-1 ;pnba SYNC/MODE)RT)GND)FB)VOUT)SW)BST)INTVcc)VIN)EN/UVLO)VC
C4 N005 0 220p
L1 IN N001 2.2 Rser=9m
C1 N006 0 1
C2 N001 N002 0.1
.tran 1.6m startup
.lib LT8337-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1352 740
WIRE -192 0 -336 0
WIRE -96 0 -192 0
WIRE -64 0 -96 0
WIRE 48 0 16 0
WIRE 192 0 48 0
WIRE -336 16 -336 0
WIRE 192 16 192 0
WIRE -96 96 -96 0
WIRE 48 96 48 0
WIRE 192 96 192 80
WIRE -336 112 -336 96
WIRE -192 176 -192 0
WIRE -160 176 -192 176
WIRE 336 176 256 176
WIRE 464 176 336 176
WIRE 592 176 464 176
WIRE 336 192 336 176
WIRE 592 192 592 176
WIRE 464 208 464 176
WIRE -160 240 -320 240
WIRE -320 256 -320 240
WIRE 464 288 464 272
WIRE 592 288 592 272
WIRE -160 304 -192 304
WIRE 336 304 336 272
WIRE 336 304 256 304
WIRE 336 320 336 304
WIRE -320 368 -320 336
WIRE -80 400 -80 384
WIRE 176 400 176 384
WIRE 48 416 48 384
WIRE 336 416 336 400
WIRE -320 480 -320 432
WIRE -80 480 -80 464
WIRE 48 528 48 496
SYMBOL res -336 240 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL cap -96 400 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap -336 368 R0
SYMATTR InstName C4
SYMATTR Value 220p
SYMBOL cap 176 16 R0
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL res 320 304 R0
SYMATTR InstName R2
SYMATTR Value 71.5k
SYMBOL res 576 176 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL res 32 400 R0
SYMATTR InstName R4
SYMATTR Value 47.5k
SYMBOL LT8337-1 48 240 R0
SYMATTR InstName U1
SYMBOL ind -80 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=9m
SYMBOL voltage -336 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 7.2
SYMBOL cap 448 208 R0
WINDOW 3 40 35 Left 2
WINDOW 123 42 55 Left 2
WINDOW 0 40 9 Left 2
SYMATTR Value 22
SYMATTR Value2 x4
SYMATTR InstName C6
SYMATTR SpiceLine Rser=10m
SYMBOL res 320 176 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
FLAG -80 480 0
FLAG 176 400 0
FLAG -336 112 0
FLAG 336 416 0
FLAG 592 288 0
FLAG -336 0 IN
FLAG 592 176 OUT
FLAG 48 528 0
FLAG -320 480 0
FLAG 464 288 0
FLAG -192 304 0
TEXT 368 496 Left 2 !.tran 1.6m startup
TEXT 72 512 Left 2 ;2MHz
TEXT 312 152 Left 2 ;15V
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX17553C.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vIN 0 24
L1 N001 vOUT 220 Rser=3.7
C2 vOUT 0 4.7
R5 vOUT N005 698k
R6 N005 0 49.9k
Rload vOUT 0 240
R1 vIN N002 3.32Meg
R3 N002 N004 953k
XU1 0 vIN N002 N004 N005 N001 N003 N006 MAX17553C ;pnba GND)IN)EN/UV)HYST)FB/VO)LX)_RESET)RT
R2 N002 0 287k
R4 vOUT N003 100k
R7 N006 0 118k
.tran 4m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX17553C.asy)
.lib MAX17553C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 992 680
WIRE -176 -32 -192 -32
WIRE 48 -32 -176 -32
WIRE 176 -32 48 -32
WIRE 512 -32 464 -32
WIRE 624 -32 592 -32
WIRE 704 -32 624 -32
WIRE 768 -32 704 -32
WIRE 864 -32 768 -32
WIRE 896 -32 864 -32
WIRE 48 -16 48 -32
WIRE 624 -16 624 -32
WIRE 768 -16 768 -32
WIRE 896 -16 896 -32
WIRE -192 16 -192 -32
WIRE 624 64 624 48
WIRE 896 80 896 64
WIRE 48 96 48 64
WIRE 48 96 -64 96
WIRE 176 96 48 96
WIRE -64 112 -64 96
WIRE 48 112 48 96
WIRE -192 128 -192 96
WIRE 512 128 464 128
WIRE 704 128 704 -32
WIRE 704 128 592 128
WIRE -64 224 -64 192
WIRE 48 224 48 192
WIRE 176 224 48 224
WIRE 768 224 768 64
WIRE 768 224 464 224
WIRE 768 256 768 224
WIRE 176 320 48 320
WIRE 48 336 48 320
WIRE 768 352 768 336
WIRE 320 384 320 368
WIRE 48 432 48 416
FLAG -192 128 0
FLAG 320 384 0
FLAG 624 64 0
FLAG 896 80 0
FLAG 768 352 0
FLAG -176 -32 vIN
FLAG 864 -32 vOUT
FLAG -64 224 0
FLAG 48 432 0
SYMBOL voltage -192 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL ind 496 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 220
SYMATTR SpiceLine Rser=3.7
SYMBOL cap 608 -16 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL res 752 -32 R0
SYMATTR InstName R5
SYMATTR Value 698k
SYMBOL res 752 240 R0
SYMATTR InstName R6
SYMATTR Value 49.9k
SYMBOL res 880 -32 R0
SYMATTR InstName Rload
SYMATTR Value 240
SYMBOL res 32 -32 R0
SYMATTR InstName R1
SYMATTR Value 3.32Meg
SYMBOL res 32 96 R0
SYMATTR InstName R3
SYMATTR Value 953k
SYMBOL MAX17553C 320 144 R0
SYMATTR InstName U1
SYMBOL res -80 96 R0
SYMATTR InstName R2
SYMATTR Value 287k
SYMBOL res 608 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL res 32 320 R0
SYMATTR InstName R7
SYMATTR Value 118k
TEXT 480 392 Left 2 !.tran 4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\32686b297ab2_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Vbe N003 5.6K
R2 N001 N002 1K
V1 N001 0 5
Q1 Vce Vbe 0 0 NPN
V2 N003 0 SINE(0 5 5 0 0 0 2)
R3 N002 Vce 1K
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V2 0 5 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 640 -144 320 -144
WIRE 320 -96 320 -144
WIRE 640 32 640 -144
WIRE 320 80 320 -16
WIRE 320 224 320 160
WIRE 416 224 416 208
WIRE 416 224 320 224
WIRE 320 240 320 224
WIRE 80 288 -48 288
WIRE 208 288 208 240
WIRE 208 288 160 288
WIRE 256 288 208 288
WIRE -48 320 -48 288
WIRE -48 432 -48 400
WIRE 320 432 320 336
WIRE 320 432 -48 432
WIRE 640 432 640 112
WIRE 640 432 320 432
WIRE 320 480 320 432
SYMBOL res 304 -112 R0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 640 16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 304 64 R0
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL voltage -48 304 R0
SYMATTR InstName V2
SYMATTR Value SINE(0 5 5 0 0 0 2)
SYMBOL res 176 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5.6K
SYMBOL npn 256 240 R0
SYMATTR InstName Q1
FLAG 320 480 0
FLAG 208 240 Vbe
FLAG 416 208 Vce
TEXT -32 160 Left 2 !.dc V2 0 5 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1108-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1108-12.asy)
XU1 IN IN N001 0 0 N002 N003 OUT LT1108 top=753K bot=87.4K ;pnba Ilim)Vin)SW1)SW2)GND)AO)SET)Sense
Rload OUT 0 50
D1 N001 OUT MBRS360
V1 IN 0 5
C2 OUT 0 100 Rser=0.02
L1 IN N001 33 Rser=0.02 Rpar=5000
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LT1108.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2456 1432
WIRE 1472 912 1264 912
WIRE 1600 912 1472 912
WIRE 1632 912 1600 912
WIRE 1744 912 1712 912
WIRE 1792 912 1744 912
WIRE 1904 912 1856 912
WIRE 1968 912 1904 912
WIRE 1264 928 1264 912
WIRE 1968 928 1968 912
WIRE 1472 960 1472 912
WIRE 1600 960 1600 912
WIRE 1264 1024 1264 1008
WIRE 1392 1024 1376 1024
WIRE 1744 1024 1744 912
WIRE 1744 1024 1680 1024
WIRE 1968 1024 1968 1008
WIRE 1904 1104 1904 912
WIRE 1904 1104 1680 1104
WIRE 1904 1120 1904 1104
WIRE 1392 1184 1376 1184
WIRE 1696 1184 1680 1184
WIRE 1904 1200 1904 1184
WIRE 1536 1264 1536 1248
SYMBOL schottky 1792 928 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMBOL POLCAP 1888 1120 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL res 1952 912 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL PowerProducts\\LT1108-12 1536 1104 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1264 912 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL IND 1616 928 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 1968 912 OUT
FLAG 1904 1200 0
FLAG 1968 1024 0
FLAG 1264 1024 0
FLAG 1696 1184 0
FLAG 1536 1264 0
FLAG 1264 912 IN
TEXT 1712 1248 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG787.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nCharge Injection not included\nOnly One channel included\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG787.asy)
V1 N004 0 PULSE(0 3 25u 1n 1n 20u)
V2 N001 0 3
V4 N003 0 0
V3 +V 0 5
R1 N002 0 49.9
C1 N002 0 36p
XU1 N004 N001 N002 N003 +V 0 ADG787 ;pnba IN)SA)D)SB)Vdd)GND
.tran 75u
.lib ADG787.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 0 -48 -48
WIRE -144 64 -512 64
WIRE -512 96 -512 64
WIRE 128 96 48 96
WIRE 256 96 128 96
WIRE -144 128 -400 128
WIRE 128 128 128 96
WIRE 256 128 256 96
WIRE -512 192 -512 176
WIRE -400 192 -400 128
WIRE -144 192 -288 192
WIRE 128 240 128 208
WIRE 256 240 256 192
WIRE -400 304 -400 272
WIRE -288 304 -288 192
WIRE -512 336 -512 288
WIRE -48 336 -48 304
WIRE -512 432 -512 416
WIRE -288 448 -288 384
SYMBOL voltage -512 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL voltage -400 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL voltage -288 288 R0
WINDOW 3 24 102 Left 2
SYMATTR Value PULSE(0 3 25u 1n 1n 20u)
SYMATTR InstName V1
SYMBOL ADG787 -48 144 R0
SYMATTR InstName U1
SYMBOL voltage -512 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res 112 112 R0
SYMATTR InstName R1
SYMATTR Value 49.9
SYMBOL cap 240 128 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG 128 240 0
FLAG 256 240 0
FLAG -48 336 0
FLAG -288 448 0
FLAG -512 192 0
FLAG -48 -48 +V
FLAG -512 432 0
FLAG -512 288 +V
FLAG -400 304 0
TEXT -264 424 Left 2 !.tran 75u
TEXT -520 -136 Left 2 ;Note:\nCharge Injection not included\nOnly One channel included\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\024ac841a257_Fig9_24_pmos.asc
* Generated by LTspice 26.0.1 for Windows.
VSG 0 N001 1.15
VSD 0 N002 0
M1 0 N001 N002 0 P_1u l=2u w=30u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSD 0 5 1m
.lib cmosedu_models.txt
* Plot Id(M1) and 1/d(Id(M1)) (to get ro)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1224 688
WIRE 320 96 320 80
WIRE 320 192 320 176
WIRE 400 192 320 192
WIRE 448 80 320 80
WIRE 448 112 448 80
WIRE 448 304 448 208
WIRE 672 80 448 80
WIRE 672 160 448 160
WIRE 672 160 672 80
WIRE 672 192 672 160
WIRE 672 304 448 304
WIRE 672 304 672 272
WIRE 848 80 672 80
WIRE 848 112 848 80
FLAG 848 112 0
SYMBOL voltage 320 80 R0
WINDOW 0 -93 54 Left 0
WINDOW 3 -93 82 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSG
SYMATTR Value 1.15
SYMBOL voltage 672 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 54 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VSD
SYMATTR Value 0
SYMBOL pmos4 400 112 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=2u w=30u
SYMATTR InstName M1
SYMATTR Value P_1u
TEXT 384 336 Left 0 !.dc VSD 0 5 1m
TEXT 384 360 Left 0 !.lib cmosedu_models.txt
TEXT 368 48 Left 0 ;Plot Id(M1) and 1/d(Id(M1)) (to get ro)
* Z:\home\khalils\Downloads\files\data\raw_asc\210ba7ef6f62_Basic_opamp1.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain stage and limiter
* Lowpass
* Output resistance
* Basic Opamp Subcircuit
* Model with infinite power supply rejection (PSRR)
* opamp2
VS in 0 0
G1 out 0 out0 0 {1/ROUT}
V1 V+ 0 -5
Rout out 0 {ROUT}
R1 out0 0 1k
V2 V- 0 5
XU1 in 0 V+ V- out opatyp1 ;pnba In+)In-)V+)V-)OUT
C1 out0 0 1p
B1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))
.subckt opatyp1 ip im vp vm out
.param GAIN=10000
.param ROUT=10
.ends
.dc VS -10m 10m 0.1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1504 680
WIRE 128 128 128 112
WIRE 96 144 64 144
WIRE 256 160 160 160
WIRE -16 176 -32 176
WIRE 96 176 -16 176
WIRE -32 192 -32 176
WIRE 128 208 128 192
WIRE -32 288 -32 272
WIRE -32 400 -32 384
WIRE 112 400 112 384
WIRE -32 496 -32 480
WIRE 112 496 112 480
LINE Normal 160 224 256 288
LINE Normal 176 256 160 224
LINE Normal 160 224 176 256
LINE Normal 192 224 160 224
SYMBOL voltage -32 176 R0
SYMATTR InstName VS
SYMATTR Value 0
SYMBOL voltage 112 384 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -32 384 R0
SYMATTR InstName V1
SYMATTR Value -5
SYMBOL Opamps\\opamp2 128 96 R0
SYMATTR InstName U1
SYMATTR Value opatyp1
FLAG 64 144 0
FLAG 128 112 V+
FLAG 128 208 V-
FLAG -32 288 0
FLAG -32 496 0
FLAG 112 496 0
FLAG -32 384 V+
FLAG 112 384 V-
FLAG 256 160 out
FLAG -16 176 in
TEXT 368 136 Left 0 !.subckt opatyp1 ip im vp vm out\n.param GAIN=10000\n.param ROUT=10\n* Gain stage and limiter\nB1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))\n* Lowpass\nR1 out0 0 1k\nC1 out0 0 1p\n* Output resistance\nG1 out 0 out0 0 {1/ROUT}\nRout out 0 {ROUT}\n.ends
TEXT -88 32 Left 0 !.dc VS -10m 10m 0.1m
TEXT -88 -24 Left 0 ;Basic Opamp Subcircuit
TEXT 280 72 Left 0 ;Model with infinite power supply rejection (PSRR)
TEXT 216 304 Left 0 ;opamp2
* Z:\home\khalils\Downloads\files\data\raw_asc\553324c7bb65_Draft_Diode_1N4148.asc
* Generated by LTspice 26.0.1 for Windows.
* Analyse
* Bibliothek
* Parameter
R1 IN1 IN2 {R1}
D1 IN2 0 1N4148
V1 IN1 0 PULSE(0 1 0 .5m .5m 0 1m)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m
.lib elk.lib
.param R1=10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 64 96 64
WIRE 192 64 144 64
WIRE 336 64 272 64
WIRE 400 64 336 64
WIRE 144 80 144 64
WIRE 336 80 336 64
WIRE 144 176 144 160
WIRE 336 176 336 144
WIRE 336 176 144 176
WIRE 144 192 144 176
IOPIN 96 64 In
IOPIN 400 64 Out
SYMBOL diode 320 80 R0
WINDOW 0 38 31 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 176 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 1 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL voltage 144 64 R0
WINDOW 3 -323 96 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 17 19 Left 2
SYMATTR Value PULSE(0 1 0 .5m .5m 0 1m)
SYMATTR InstName V1
FLAG 144 192 0
FLAG 96 64 IN1
FLAG 400 64 IN2
TEXT -8 -48 Left 2 !.tran 2m
TEXT 168 -48 Left 2 !.lib elk.lib
TEXT 344 -48 Left 2 !.param R1=10
TEXT -8 -72 Left 2 ;Analyse
TEXT 168 -72 Left 2 ;Bibliothek
TEXT 344 -72 Left 2 ;Parameter
* Z:\home\khalils\Downloads\files\data\raw_asc\8c80d33e249f_vtn_setup.asc
* Generated by LTspice 26.0.1 for Windows.
* SETUP TO CALCULATE VTN
vgs vgs 0 0.65
vdd vdd 0 1.8
M2 vdd vgs 0 0 NMOS l=0.18u w=0.36u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.include tsmc180.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -272 160 -272 80
WIRE -208 208 -272 208
WIRE -672 224 -672 176
WIRE -560 224 -560 176
WIRE -320 240 -368 240
WIRE -272 288 -272 256
WIRE -208 288 -208 208
WIRE -208 288 -272 288
WIRE -672 352 -672 304
WIRE -560 352 -560 304
WIRE -272 352 -272 288
IOPIN -672 176 In
IOPIN -368 240 In
IOPIN -560 176 In
IOPIN -272 80 In
SYMBOL voltage -672 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vgs
SYMATTR Value 0.65
SYMBOL nmos4 -320 160 R0
WINDOW 123 1 100 Left 2
SYMATTR Value2 l=0.18u w=0.36u
SYMATTR InstName M2
SYMBOL voltage -560 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vdd
SYMATTR Value 1.8
FLAG -272 352 0
FLAG -672 352 0
FLAG -672 176 vgs
FLAG -368 240 vgs
FLAG -560 352 0
FLAG -560 176 vdd
FLAG -272 80 vdd
TEXT -736 24 Left 2 !.op
TEXT -736 0 Left 2 !.include tsmc180.txt
TEXT -592 -40 Left 2 ;SETUP TO CALCULATE VTN
* Z:\home\khalils\Downloads\files\data\raw_asc\2eb450a2315e_Fig_8-5_LTC6244_AC.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6244.asy)
R1 N001 0 1k
V2 -V 0 -5
V1 +V 0 5
V3 IN 0 AC 1
R2 N001 OUT 100K
XU1 IN N001 +V -V OUT LTC6244 ;pnba IN+)IN-)VCC)VEE)OUT
.ac dec 100 0.1 1000Meg
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 240 256 240
WIRE 432 240 384 240
WIRE 256 336 256 240
WIRE 304 336 256 336
WIRE 432 352 432 240
WIRE 432 352 368 352
WIRE 464 352 432 352
WIRE 304 368 144 368
WIRE -32 400 -32 368
WIRE 64 400 64 368
WIRE 144 400 144 368
WIRE 256 400 256 336
WIRE 336 400 336 384
WIRE -32 512 -32 480
WIRE 64 512 64 480
WIRE 144 512 144 480
WIRE 256 512 256 480
SYMBOL res 240 384 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -32 384 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 64 384 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 288 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL voltage 144 384 R0
WINDOW 0 15 11 Left 2
WINDOW 3 11 105 Left 2
WINDOW 123 17 108 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL LTC6244 336 352 R0
SYMATTR InstName U1
FLAG -32 512 0
FLAG 64 512 0
FLAG -32 368 +V
FLAG 144 512 0
FLAG 144 368 IN
FLAG 464 352 OUT
FLAG 336 320 +V
FLAG 64 368 -V
FLAG 336 400 -V
FLAG 256 512 0
TEXT -72 272 Left 2 !.ac dec 100 0.1 1000Meg
* Z:\tmp\asc_dec_bjh7r6w2\093148bae00b_Draft1_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N003 vb 220k
R6 N003 N005 R=V(alpha_lin)*{Rlin}
R4 vb 0 50k
R1 N002 vc 22k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -128 -272 -192 -272
WIRE 256 -272 -48 -272
WIRE 384 -272 256 -272
WIRE -192 -240 -192 -272
WIRE 384 -224 384 -272
WIRE -192 -144 -192 -160
WIRE 128 -144 -192 -144
WIRE -192 -112 -192 -144
WIRE 128 -112 128 -144
WIRE 256 -112 256 -272
WIRE 384 -112 384 -144
WIRE -192 16 -192 -32
WIRE 256 48 256 -32
WIRE 256 96 256 48
WIRE 128 144 128 -32
WIRE 176 144 128 144
WIRE 192 144 176 144
WIRE 256 240 256 192
WIRE 128 288 128 144
WIRE 256 288 256 240
WIRE 128 416 128 368
WIRE 256 416 256 368
WIRE 256 416 128 416
WIRE 128 464 128 416
SYMBOL res 112 -128 R0
SYMATTR InstName R2
SYMATTR Value 220k
SYMBOL res -208 -128 R0
SYMATTR InstName R6
SYMATTR Value R=V(alpha_lin)*{Rlin}
SYMBOL res 112 272 R0
SYMATTR InstName R4
SYMATTR Value 50k
SYMBOL res 240 -128 R0
SYMATTR InstName R1
SYMATTR Value 22k
FLAG 384 -32 0
FLAG 128 464 0
FLAG 176 144 vb
FLAG 256 48 vc
FLAG 256 240 ve