Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7102-9.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7102-9.0.asy)
Rload OUT 0 50
XU1 IN OUT IN N001 OUT 0 ADP7102 Vref=9 ;pnba Vin)Sense)EN)PG)Vout)GND
R1 OUT N001 100k
C1 OUT 0 2.2 Rser=1.5m
V1 IN 0 10
.tran 3m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL ADP7102-9.0 224 128 R0
SYMATTR InstName U1
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3525-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3525-5.asy)
L1 IN N001 10
XU1 IN 0 IN OUT MP_01 N001 LTC3525-5 ;pnba _SHDN)GND)Vin)Vout))SW
V1 IN 0 1
R1 OUT 0 100
C1 OUT 0 10
.tran 2m startup
.lib LTC3525-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 64 0 64
WIRE 320 64 192 64
WIRE 0 160 0 64
WIRE 0 160 -112 160
WIRE 32 160 0 160
WIRE 320 160 320 64
WIRE 320 160 288 160
WIRE -112 176 -112 160
WIRE -112 272 -112 256
WIRE 0 304 0 160
WIRE 32 304 0 304
WIRE 320 304 288 304
WIRE 416 304 320 304
WIRE 320 320 320 304
WIRE 416 320 416 304
WIRE 160 384 160 368
WIRE 320 416 320 384
WIRE 416 416 416 400
SYMBOL ind 96 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL cap 304 320 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 400 304 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL PowerProducts\\LTC3525-5 160 208 R0
SYMATTR InstName U1
SYMBOL voltage -112 160 R0
SYMATTR InstName V1
SYMATTR Value 1
FLAG 320 416 0
FLAG 160 384 0
FLAG -112 272 0
FLAG 416 416 0
FLAG -112 160 IN
FLAG 416 304 OUT
TEXT 72 464 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7171.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7171.asy)
C2 0 N001 1n
R2 N002 0 10K
XU1 IN N002 IN N001 OUT 0 ADM7171 ;pnba Vin)Sense)EN)SS)Vout)GND
R1 OUT N002 15K
C1 OUT 0 4.7 Rser=1.5m
Rload OUT 0 4
V1 IN 0 3.5
.tran 5m startup
.lib ADM7171.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 400 32 352 32
WIRE 528 32 400 32
WIRE 624 32 528 32
WIRE -32 48 -32 32
WIRE 528 48 528 32
WIRE 624 48 624 32
WIRE 400 80 400 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 528 144 528 112
WIRE 624 144 624 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 400 224 400 160
WIRE 400 224 352 224
WIRE 400 240 400 224
WIRE 224 304 224 288
WIRE 400 336 400 320
SYMBOL res 608 32 R0
SYMATTR InstName Rload
SYMATTR Value 4
SYMBOL res 384 224 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL ADM7171 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.5
SYMBOL cap 512 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1.5m
SYMBOL cap 16 208 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res 384 64 R0
SYMATTR InstName R1
SYMATTR Value 15K
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 624 144 0
FLAG 528 144 0
FLAG -32 32 IN
FLAG 624 32 OUT
FLAG 400 336 0
TEXT 568 288 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\07f4dd94cd71_TerceraEtapa.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N002 Vo +VCC -VCC Vo TL08X ;pnba In+)In-)V+)V-)OUT
V1 +VCC 0 15
V2 0 -VCC 15
V3 Vi 0 AC 1 Rser=50
R1 N001 Vi {mc(22680,0.01)}
R2 N002 N001 {mc(22680,0.01)}
C1 N002 0 {mc(2.7n,0.1)}
C2 Vo N001 {mc(12n,0.1)}
C3 Vi 0 12pF
R5 Vi 0 10Meg
C4 Vo 0 12pF
R6 Vo 0 10Meg
.lib C:\Users\Lucas\Documents\LTspiceXVII\Librerias\Opamps_Comparators_ST.lib
.ac dec 200 1 500k
;.step param run 1 100 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 112 256 112
WIRE 624 112 448 112
WIRE -112 144 -112 128
WIRE 32 208 32 160
WIRE 160 224 144 224
WIRE 256 224 256 112
WIRE 256 224 240 224
WIRE 288 224 256 224
WIRE 384 224 368 224
WIRE 512 224 384 224
WIRE -112 240 -112 224
WIRE -112 240 -192 240
WIRE 624 240 624 112
WIRE 624 240 576 240
WIRE 704 240 624 240
WIRE 720 240 704 240
WIRE -192 256 -192 240
WIRE -112 256 -112 240
WIRE 512 256 464 256
WIRE 384 272 384 224
WIRE 32 320 32 288
WIRE -112 352 -112 336
WIRE 464 352 464 256
WIRE 624 352 624 240
WIRE 624 352 464 352
WIRE 160 416 160 224
WIRE 160 416 112 416
WIRE 208 416 160 416
WIRE 704 416 704 240
WIRE 704 416 656 416
WIRE 752 416 704 416
WIRE 208 432 208 416
WIRE 752 432 752 416
WIRE 112 448 112 416
WIRE 656 448 656 416
WIRE 384 480 384 336
WIRE 112 528 112 512
WIRE 160 528 112 528
WIRE 208 528 208 512
WIRE 208 528 160 528
WIRE 656 528 656 512
WIRE 704 528 656 528
WIRE 752 528 752 512
WIRE 752 528 704 528
WIRE 160 544 160 528
WIRE 704 544 704 528
FLAG -192 256 0
FLAG -112 128 +VCC
FLAG -112 352 -VCC
FLAG 32 320 0
FLAG 32 160 Vi
FLAG 544 272 +VCC
FLAG 544 208 -VCC
FLAG 384 480 0
FLAG 720 240 Vo
FLAG 144 224 Vi
FLAG 160 544 0
FLAG 704 544 0
SYMBOL Opamps\\opamp2 544 304 M180
WINDOW 3 -32 -77 Left 2
SYMATTR Value TL08X
SYMATTR InstName U1
SYMBOL voltage -112 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -112 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL voltage 32 192 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR Value2 AC 1
SYMATTR SpiceLine Rser=50
SYMATTR InstName V3
SYMATTR Value ""
SYMBOL res 256 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -55 90 VTop 2
SYMATTR InstName R1
SYMATTR Value {mc(22680,0.01)}
SYMBOL res 384 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 43 99 VTop 2
SYMATTR InstName R2
SYMATTR Value {mc(22680,0.01)}
SYMBOL cap 368 272 R0
WINDOW 3 -148 60 Left 2
SYMATTR Value {mc(2.7n,0.1)}
SYMATTR InstName C1
SYMBOL cap 448 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {mc(12n,0.1)}
SYMBOL cap 96 448 R0
SYMATTR InstName C3
SYMATTR Value 12pF
SYMBOL res 192 416 R0
SYMATTR InstName R5
SYMATTR Value 10Meg
SYMBOL cap 640 448 R0
SYMATTR InstName C4
SYMATTR Value 12pF
SYMBOL res 736 416 R0
SYMATTR InstName R6
SYMATTR Value 10Meg
TEXT -128 -24 Left 2 !.lib C:\\Users\\Lucas\\Documents\\LTspiceXVII\\Librerias\\Opamps_Comparators_ST.lib
TEXT -136 0 Left 2 !.ac dec 200 1 500k
TEXT -128 24 Left 2 !;.step param run 1 100 1
* Z:\home\khalils\Downloads\files\data\raw_asc\0ea8c2a41f96_UMX5601_pin_diode.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc V1 0 50 .1
* The UMX5601 mdoel require the options below for convergence.\n \nAttribute in the standard diode symbol has to be changed.\nPrefix:X
XD1 vd 0 UMX5601 ;pnba +)-
R1 N001 vd 5k
V1 N001 0 PWL(0 50 10n 50 11n -50)
.include UMX5601.txt
.op
.options gminsteps=0 noopiter
.tran 0 20000n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1076 1500
WIRE 144 80 -48 80
WIRE 304 80 224 80
WIRE -48 128 -48 80
WIRE 304 128 304 80
WIRE -48 256 -48 208
WIRE 304 256 304 192
WIRE 304 256 -48 256
WIRE -48 288 -48 256
SYMBOL voltage -48 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 50 10n 50 11n -50)
SYMBOL diode 288 128 R0
SYMATTR InstName D1
SYMATTR Value UMX5601
SYMATTR Prefix X
SYMBOL res 128 96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 5k
FLAG -48 288 0
FLAG 304 80 vd
TEXT -80 -128 Left 0 !.include UMX5601.txt
TEXT -80 -88 Left 0 !.op
TEXT -80 -48 Left 0 ;.dc V1  0 50 .1
TEXT -80 -168 Left 0 !.options gminsteps=0   noopiter
TEXT -80 -16 Left 0 !.tran 0 20000n 0 1n
TEXT -80 -328 Left 0 ;The UMX5601 mdoel require the options below for convergence.\n \nAttribute in the standard diode symbol has to be changed.\nPrefix:X
* Z:\home\khalils\Downloads\files\data\raw_asc\TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T1 IN 0 0 OUT Td=50n Z0=50
T2 0 0 OUT 0 Td=30n Z0=150
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\1239ccccabfd_NOR_gate.asc
* Generated by LTspice 26.0.1 for Windows.
V3 N001 0 5
M2 OUT V2 0 0 NMOS
M1 OUT V1 0 0 NMOS
V2 V2 0 PULSE(0 5 0 10ns 10ns 3ms 6ms)
V1 V1 0 PULSE(0 5 0 10ns 10ns 1ms 2ms)
M3 N002 V1 N001 N001 PMOS
M4 OUT V2 N002 N002 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1464 680
WIRE 1040 -304 1040 -352
WIRE 992 -288 880 -288
WIRE 1040 -144 1040 -208
WIRE 992 -128 880 -128
WIRE 1040 32 1040 -48
WIRE 1216 32 1040 32
WIRE 144 64 -128 64
WIRE 144 96 0 96
WIRE 1040 128 1040 32
WIRE 1040 128 896 128
WIRE 1184 128 1040 128
WIRE -128 192 -128 64
WIRE 0 192 0 96
WIRE 848 208 752 208
WIRE 1376 208 1232 208
WIRE 1040 224 896 224
WIRE 1184 224 1040 224
WIRE 1040 256 1040 224
IOPIN 144 64 Out
IOPIN 144 96 Out
IOPIN 880 -288 In
IOPIN 880 -128 In
IOPIN 1376 208 In
IOPIN 752 208 In
IOPIN 1216 32 Out
SYMBOL voltage 0 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10ns 10ns 3ms 6ms)
SYMBOL voltage -128 176 R0
WINDOW 3 -408 54 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 10ns 10ns 1ms 2ms)
SYMBOL nmos 1232 128 M0
SYMATTR InstName M2
SYMBOL pmos 992 -48 M180
SYMATTR InstName M4
SYMBOL nmos 848 128 R0
SYMATTR InstName M1
SYMBOL voltage 1040 -336 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL pmos 992 -208 M180
SYMATTR InstName M3
FLAG -128 272 0
FLAG 0 272 0
FLAG 144 64 V1
FLAG 144 96 V2
FLAG 1040 256 0
FLAG 1040 -432 0
FLAG 880 -288 V1
FLAG 880 -128 V2
FLAG 1376 208 V2
FLAG 752 208 V1
FLAG 1216 32 OUT
TEXT -538 296 Left 2 !.tran 20ms
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6703-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT6703-3.asy)
XU1 N003 0 N002 N001 LT6703-3 ;pnba OUT)GND)+IN)Vs
R1 N001 N002 1Meg
R2 N002 0 154K
R3 N001 N003 1Meg
V1 N001 0 PWL(0 0 1 3.3)
.tran 1
.lib LTC6.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 16 -208 16
WIRE 208 16 16 16
WIRE 336 16 208 16
WIRE -208 32 -208 16
WIRE 16 32 16 16
WIRE 336 32 336 16
WIRE 208 80 208 16
WIRE -208 128 -208 112
WIRE 16 128 16 112
WIRE 128 128 16 128
WIRE 16 144 16 128
WIRE 336 144 336 112
WIRE 336 144 288 144
WIRE 16 240 16 224
WIRE 208 288 208 256
SYMBOL res 0 128 R0
SYMATTR InstName R2
SYMATTR Value 154K
SYMBOL LT6703-3 208 144 R0
SYMATTR InstName U1
SYMBOL res 0 16 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL voltage -208 16 R0
WINDOW 3 26 96 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PWL(0 0 1 3.3)
SYMATTR InstName V1
SYMBOL res 320 16 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
FLAG -208 128 0
FLAG 208 288 0
FLAG 16 240 0
TEXT 360 208 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\MAXM17225.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAXM17225.asy)
R1 OUT 0 100
XU1 0 N001 OUT IN NC_01 IN IN MAXM17225 ;pnba GND)RSEL)OUT)EN)LX)IN)INS
C1 OUT 0 10 Rser=5m
V1 IN 0 1.5
R2 N001 0 133K
.tran 4.5m startup
.lib MAXM17225.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 960 680
WIRE -80 -32 -112 -32
WIRE 16 -32 -80 -32
WIRE 64 -32 16 -32
WIRE 384 -32 320 -32
WIRE 464 -32 384 -32
WIRE 496 -32 464 -32
WIRE -112 0 -112 -32
WIRE 384 0 384 -32
WIRE 496 0 496 -32
WIRE 16 64 16 -32
WIRE 64 64 16 64
WIRE 384 96 384 64
WIRE 496 96 496 80
WIRE -112 112 -112 80
WIRE 16 160 16 64
WIRE 64 160 16 160
WIRE 384 160 320 160
WIRE 384 192 384 160
WIRE 208 256 208 224
WIRE 384 288 384 272
SYMBOL res 480 -16 R0
WINDOW 123 36 60 Left 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage -112 -16 R0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL cap 368 0 R0
SYMATTR SpiceLine Rser=5m
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL MAXM17225 192 64 R0
SYMATTR InstName U1
SYMBOL res 368 176 R0
SYMATTR InstName R2
SYMATTR Value 133K
FLAG -112 112 0
FLAG 384 96 0
FLAG 496 96 0
FLAG -80 -32 IN
FLAG 464 -32 OUT
FLAG 384 288 0
FLAG 208 256 0
TEXT 128 344 Left 2 !.tran 4.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7158-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7158-2.8.asy)
C2 N003 0 1
C3 N004 0 1
Rload OUT 0 2.8
XU1 OUT MP_01 OUT N002 N001 N003 N003 N004 IN 0 ADP7158_9 Vreg=3.211 Vref=2.816 ;pnba Vout))Vout_Sense)Byp)EN)Ref_Sense)Ref)Vreg)Vin)GND
V1 IN 0 3.5
R1 IN N001 100K
C4 N002 0 1
C1 OUT 0 10
.tran 5m startup
.lib ADP7158_9.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -160 32
WIRE 80 32 -32 32
WIRE 416 32 400 32
WIRE 464 32 416 32
WIRE 560 32 464 32
WIRE -160 48 -160 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE 416 128 416 32
WIRE 416 128 400 128
WIRE -160 144 -160 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 0 224 -16 224
WIRE 80 224 64 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL ADP7158-2.8 240 176 R0
SYMATTR InstName U1
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 448 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 448 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 544 32 R0
SYMATTR InstName Rload
SYMATTR Value 2.8
SYMBOL voltage -160 32 R0
SYMATTR InstName V1
SYMATTR Value 3.5
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG -16 224 0
FLAG -160 144 0
FLAG 560 144 0
FLAG -160 32 IN
FLAG 560 32 OUT
TEXT 504 368 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3008-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3008-3.3.asy)
C1 OUT 0 1
XU1 IN OUT OUT 0 IN LT3008-3.3 ;pnba IN)OUT)Sense)GND)_SHDN
Rload OUT 0 330
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 330
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT3008-3.3 176 96 R0
SYMATTR InstName U1
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 336 248 Left 2 !.tran 1
* Z:\tmp\asc_dec_bjh7r6w2\1987fd1c7fe1_Simulacion_cuadrada_1000rads_Gamberale_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
XU2 0 Vc V+ V- N001 TL081 ;pnba In+)In-)V+)V-)OUT
R4 Vc Vb 10K
V2 V- 0 -15
R2 Vo Va 200K
Vi N003 0 PULSE(-0.1 0.1 0 1n 1n 3.142m 6.283m)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -80 -32 -112 -32
WIRE -64 -32 -80 -32
WIRE -16 -32 -32 -32
WIRE 32 -32 -16 -32
WIRE -608 16 -736 16
WIRE -496 16 -608 16
WIRE -736 48 -736 16
WIRE -608 64 -608 16
WIRE -112 64 -112 -32
WIRE -96 64 -112 64
WIRE 32 64 32 -32
WIRE 32 64 -16 64
WIRE -336 80 -464 80
WIRE -144 96 -160 96
WIRE -464 128 -464 80
WIRE -432 128 -464 128
WIRE -144 128 -144 96
WIRE -112 128 -112 64
WIRE -112 128 -144 128
WIRE -96 128 -112 128
WIRE -832 144 -864 144
WIRE -736 144 -736 128
WIRE -736 144 -752 144
WIRE -720 144 -736 144
WIRE -608 144 -608 128
WIRE -608 144 -640 144
WIRE -576 144 -608 144
WIRE -336 144 -368 144
WIRE 32 144 32 64
WIRE 32 144 -32 144
WIRE 80 144 32 144
WIRE -496 160 -496 16
WIRE -496 160 -512 160
WIRE -432 160 -496 160
WIRE -96 160 -128 160
WIRE -736 176 -736 144
WIRE -576 176 -608 176
WIRE -144 176 -144 128
WIRE -144 176 -192 176
WIRE -864 192 -864 144
WIRE -128 208 -128 160
WIRE -608 240 -608 176
WIRE -864 288 -864 272
SYMBOL OpAmps\\opamp2 -544 96 R0
SYMATTR InstName U2
SYMATTR Value TL081
SYMBOL res -624 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 51 53 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL voltage 192 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 0 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -20 49 VBottom 2
SYMATTR InstName R2
SYMATTR Value 200K
SYMBOL voltage -864 176 R0
WINDOW 123 21 135 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 13 101 Left 2
SYMATTR Value PULSE(-0.1 0.1 0 1n 1n 3.142m 6.283m)
SYMATTR InstName Vi
FLAG -128 208 0
FLAG -864 288 0
FLAG -608 240 0
FLAG -736 240 0
FLAG 80 144 Vo
FLAG -112 128 Va
FLAG -736 144 Vb
FLAG -608 144 Vc
FLAG 192 0 V+
FLAG -64 112 V+
FLAG -400 112 V+
FLAG -544 128 V+
FLAG 192 80 0
FLAG 192 224 0
FLAG 192 144 V-
FLAG -64 176 V-
FLAG -400 176 V-
FLAG -544 192 V-
* Z:\home\khalils\Downloads\files\data\raw_asc\0e3fc9753ca8_PWMGenerator_with555Timer.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N002 1k
D1 N001 N005 D
D2 N006 N001 D
C1 N003 0 110n
C2 N004 0 1n
V1 N002 0 5
XU1 0 N003 out N002 N004 N003 N001 N002 NE555 ;pnba GND)TRIG)OUT)RST)CV)THRS)DIS)Vcc
R2 N003 N005 10k
R3 N006 N003 10k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Misc\NE555.asy)
.lib NE555.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 680
WIRE 784 -32 384 -32
WIRE 752 32 -64 32
WIRE 480 80 448 80
WIRE 752 80 752 32
WIRE 752 80 704 80
WIRE 448 96 448 80
WIRE -64 128 -64 32
WIRE -64 128 -160 128
WIRE -16 128 -64 128
WIRE 96 128 64 128
WIRE 384 128 384 -32
WIRE 384 128 96 128
WIRE 480 144 432 144
WIRE 784 144 784 -32
WIRE 784 144 704 144
WIRE 96 176 96 128
WIRE 384 176 384 128
WIRE -64 208 -64 128
WIRE 480 208 448 208
WIRE 736 208 704 208
WIRE 480 272 464 272
WIRE 752 272 704 272
WIRE 96 288 96 240
WIRE 128 288 96 288
WIRE 240 288 208 288
WIRE 272 288 240 288
WIRE 384 288 384 240
WIRE 384 288 352 288
WIRE 432 320 432 144
WIRE 736 320 736 208
WIRE 736 320 432 320
WIRE 240 336 240 288
WIRE 432 336 432 320
WIRE 432 336 240 336
WIRE 448 336 448 208
WIRE 864 336 448 336
WIRE 240 352 240 336
WIRE 752 368 752 272
WIRE -64 448 -64 288
WIRE 128 448 -64 448
WIRE 240 448 240 416
WIRE 240 448 128 448
WIRE 752 464 752 432
WIRE 128 480 128 448
WIRE -160 544 -160 128
WIRE 464 544 464 272
WIRE 464 544 -160 544
FLAG 128 480 0
FLAG 448 96 0
FLAG 864 336 out
FLAG 752 464 0
SYMBOL res 80 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL diode 80 176 R0
SYMATTR InstName D1
SYMBOL diode 400 240 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL cap 224 352 R0
SYMATTR InstName C1
SYMATTR Value 110n
SYMBOL cap 736 368 R0
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL voltage -64 192 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL Misc\\NE555 592 176 R0
SYMATTR InstName U1
SYMBOL res 224 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 368 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
TEXT 952 224 Left 2 !.tran 10m