* Z:\home\khalils\Downloads\files\data\raw_asc\LT8722.asc
* Generated by LTspice 26.0.1 for Windows.
* Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) MOSI is used as input for SPIS_DAC. Since LTspice cannot convert digital data into analog,\nthe SPIS_DAC signal must be converted first into equivalent analog voltage before starting the\nsimulation.\nExample, 0xFF000000 = 2.5V while 0x00000000 = 1.25V and 0x00FFFFFF = 30nV.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LT8722. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope described in the datasheet, the resulting simulation outcomes are not meaningful.\n \n ENABLE_REQ -- 1 or 0, sets the ENABLE_REQ command to either 1 or 0.\n SWEN_REQ -- 1 or 0, sets the SWEN_REQ command to either 1 or 0.\n VCC_VREG -- 1 or 0, set the regulation voltage of Vcc pin 1 for 3.4V, 0 for 3.1V\n FREQ_SET -- 0 to 7, set the switching frequency of the Buck converter, 0 --> 500Khz, 1 --> 1Mhz\n 2 --> 1.5Mhz, 3 --> 2Mhz, 4 --> 2.5Mhz and 5,6,7 --> 3Mhz.\n FREQ_ADJ -- 0 to 3, adjusts the switching frequency of the Buck converter +/- 15% above the \n set frequency,\n 0 --> 0%, 1 --> +15%, 2 --> -15%, and 3 --> 0%.\n SYS_DC -- selects the duty cycle control range,\n 0 --> 20% to 80%, 1 --> 15% to 85%, and 2, 3 --> 10% to 90%.\n DAC_ILIMP -- 0 to 462 where 0 corresponds to 6.8A while 462 to 637.44mA with 13.28mA per \n step.\n DAC_ILIMN -- 48 to 511 where 48 corresponds to -637.44mA while 511 to 6.8A with -13.28mA \n per step.\n OV_CLAMP -- 0 to 15, sets the positive output voltage limit, See details on the datasheet.\n UV_CLAMP -- 0 to 15, sets the negative output voltage limit. See details on the datasheet.\n VC_INT -- 0 to 7, sets the initial peak inductor current limit. See details on the datasheet.\n AMUX -- 0 to 15, selects which signal Aout pit will output. See details on the datasheet.\n AMUX_TEST -- 0 or 1, provides additonal setting for signal selection on Aout Pin,\n See details on the datasheet.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8722.asy)
V3 N003 0 PULSE(0 3.3 2.5m 10n 1n 1 2 1)
C3 N001 0 1
C1 N005 N007 0.1
L1 N007 TEC- 1
V5 IN 0 15
V4 N002 0 2.7
XU2 0 N001 N005 IN 0 N007 0 TEC+ 0 NC_01 N006 TEC- N004 N002 IN 0 LT8722 ENABLE_REQ=1 SWEN_REQ=1 VCC_VREG=1 SW_FREQ_SET=7 SW_FREQ_ADJ=0 SYS_DC=2 DAC_ILIMP=0 DAC_ILIMN=511 OV_CLAMP=15 UV_CLAMP=0 VC_INT=3 AMUX_TEST=0 AMUX=3 ;pnba SYNC)VCC)BST)VIN)_CS)SW)SCK)LDR)MISO)AOUT)MOSI)SFB)SWEN)VDDIO)EN)GND
C4 TEC+ 0 150n Rser=2m
V2 N006 0 PWL(0 2.5 +80u 2.5 +4m 0 +4m 2.5 +4m 0)
C2 TEC- 0 1 Rser=2m
RTEC TEC+ TEC- 3
R1 N004 N003 20k
.tran 12.5m startup
.lib LT8722.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1684 936
WIRE -1264 -32 -1328 -32
WIRE -1200 -32 -1264 -32
WIRE -944 -32 -1200 -32
WIRE -1328 0 -1328 -32
WIRE -944 0 -944 -32
WIRE -1200 64 -1200 -32
WIRE -1152 64 -1200 64
WIRE -736 64 -752 64
WIRE -656 64 -672 64
WIRE -1328 96 -1328 80
WIRE -1152 160 -1456 160
WIRE -640 160 -752 160
WIRE -528 160 -640 160
WIRE -496 160 -528 160
WIRE -640 176 -640 160
WIRE -1456 192 -1456 160
WIRE -496 208 -496 160
WIRE -1280 256 -1360 256
WIRE -1152 256 -1200 256
WIRE -720 256 -752 256
WIRE -720 272 -720 256
WIRE -1456 288 -1456 272
WIRE -1360 288 -1360 256
WIRE -1152 352 -1264 352
WIRE -720 352 -720 336
WIRE -720 352 -752 352
WIRE -656 352 -720 352
WIRE -528 352 -576 352
WIRE -496 352 -496 288
WIRE -496 352 -528 352
WIRE -496 368 -496 352
WIRE -1360 384 -1360 368
WIRE -1264 384 -1264 352
WIRE -1152 448 -1168 448
WIRE -624 448 -496 352
WIRE -624 448 -752 448
WIRE -496 448 -496 432
WIRE -1264 480 -1264 464
WIRE -1152 544 -1168 544
WIRE -1152 640 -1168 640
WIRE -736 640 -752 640
WIRE -944 720 -944 704
SYMBOL cap -656 176 R0
WINDOW 3 34 45 Left 2
WINDOW 0 36 10 Left 2
SYMATTR Value 150n
SYMATTR InstName C4
SYMATTR SpiceLine Rser=2m
SYMBOL voltage -1456 176 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V4
SYMATTR Value 2.7
SYMBOL voltage -1264 368 M0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 2.5 +80u 2.5 +4m 0 +4m 2.5 +4m 0)
SYMBOL voltage -1328 -16 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V5
SYMATTR Value 15
SYMBOL cap -736 48 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL LT8722 -944 352 R0
SYMATTR InstName U2
SYMBOL res -512 192 R0
SYMATTR InstName RTEC
SYMATTR Value 3
SYMBOL cap -512 368 R0
SYMATTR Value 1
SYMATTR InstName C2
SYMATTR SpiceLine Rser=2m
SYMBOL voltage -1360 272 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
WINDOW 3 -322 100 Left 2
SYMATTR Value PULSE(0 3.3 2.5m 10n 1n 1 2 1)
SYMATTR InstName V3
SYMBOL ind -672 368 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL res -1184 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 20k
SYMBOL cap -736 272 R0
WINDOW 0 35 17 Left 2
WINDOW 3 34 49 Left 2
SYMATTR InstName C1
SYMATTR Value 0.1
FLAG -496 448 0
FLAG -944 720 0
FLAG -1264 480 0
FLAG -528 160 TEC+
FLAG -528 352 TEC-
FLAG -1168 448 0
FLAG -1168 544 0
FLAG -1168 640 0
FLAG -1360 384 0
FLAG -1456 288 0
FLAG -1328 96 0
FLAG -1264 -32 IN
FLAG -656 64 0
FLAG -640 240 0
FLAG -736 640 0
TEXT -1032 768 Left 2 !.tran 12.5m startup
TEXT -288 24 Left 2 ;Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) MOSI is used as input for SPIS_DAC. Since LTspice cannot convert digital data into analog,\nthe SPIS_DAC signal must be converted first into equivalent analog voltage before starting the\nsimulation.\nExample, 0xFF000000 = 2.5V while 0x00000000 = 1.25V and 0x00FFFFFF = 30nV.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LT8722. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope described in the datasheet, the resulting simulation outcomes are not meaningful.\n \n     ENABLE_REQ -- 1 or 0, sets the ENABLE_REQ command to either 1 or 0.\n     SWEN_REQ -- 1 or 0, sets the SWEN_REQ command to either 1 or 0.\n     VCC_VREG -- 1 or 0, set the regulation voltage of Vcc pin 1 for 3.4V, 0 for 3.1V\n     FREQ_SET -- 0 to 7, set the switching frequency of the Buck converter, 0 --> 500Khz, 1 --> 1Mhz\n                2 --> 1.5Mhz, 3 --> 2Mhz, 4 --> 2.5Mhz and 5,6,7 --> 3Mhz.\n     FREQ_ADJ -- 0 to 3, adjusts the switching frequency of the Buck converter +/- 15% above the \n               set frequency,\n               0 --> 0%, 1 --> +15%, 2 --> -15%, and 3 --> 0%.\n     SYS_DC -- selects the duty cycle control range,\n               0 --> 20% to 80%, 1 --> 15% to 85%, and 2, 3  --> 10% to 90%.\n     DAC_ILIMP -- 0 to 462 where 0 corresponds to 6.8A while 462 to 637.44mA with 13.28mA  per \n               step.\n     DAC_ILIMN -- 48 to 511 where 48 corresponds to -637.44mA while 511 to 6.8A with -13.28mA \n               per step.\n     OV_CLAMP -- 0 to 15, sets the positive output voltage limit, See details on the datasheet.\n     UV_CLAMP -- 0 to 15, sets the negative output voltage limit. See details on the datasheet.\n     VC_INT -- 0 to 7, sets the initial peak inductor current limit. See details on the datasheet.\n     AMUX -- 0 to 15, selects which signal Aout pit will output. See details on the datasheet.\n     AMUX_TEST -- 0 or 1, provides additonal setting for signal selection on Aout Pin,\n               See details on the datasheet.