Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1170.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1170.asy)
Rload OUT 0 10
R1 N003 N004 1K
L1 IN N001 150 Rser=0.02 Rpar=5000
V1 IN 0 5
R3 OUT N002 10.7K
D1 N001 OUT MBRS360
C2 OUT 0 500 Rser=0.05
R2 N002 0 1.24K
C1 N004 0 1
XU1 N003 N002 0 N001 IN LT1170 ;pnba Vc)FB)GND)SW)Vin
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 15m startup
.lib LT1170.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 896 1616 896
WIRE 1888 896 1824 896
WIRE 2000 896 1968 896
WIRE 2048 896 2000 896
WIRE 2176 896 2112 896
WIRE 2304 896 2176 896
WIRE 2416 896 2304 896
WIRE 1616 912 1616 896
WIRE 2304 912 2304 896
WIRE 2416 912 2416 896
WIRE 1824 944 1824 896
WIRE 2176 960 2176 896
WIRE 1616 1008 1616 992
WIRE 2304 1008 2304 976
WIRE 2416 1008 2416 992
WIRE 2000 1024 2000 896
WIRE 2000 1024 1952 1024
WIRE 2176 1088 2176 1040
WIRE 2176 1088 1952 1088
WIRE 2176 1104 2176 1088
WIRE 1968 1152 1952 1152
WIRE 2064 1152 2048 1152
WIRE 2064 1168 2064 1152
WIRE 2176 1200 2176 1184
WIRE 1824 1248 1824 1232
WIRE 2064 1248 2064 1232
SYMBOL RES 2160 1088 R0
SYMATTR InstName R2
SYMATTR Value 1.24K
SYMBOL POWERPRODUCTS\\LT1170 1824 1088 R0
SYMATTR InstName U1
SYMBOL CAP 2048 1168 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL RES 2400 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL RES 2160 944 R0
SYMATTR InstName R3
SYMATTR Value 10.7K
SYMBOL polcap 2288 912 R0
SYMATTR InstName C2
SYMATTR Value 500
SYMATTR SpiceLine Rser=0.05
SYMBOL IND 1872 912 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL VOLTAGE 1616 896 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL schottky 2048 912 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMBOL RES 1952 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1K
FLAG 1616 1008 0
FLAG 1824 1248 0
FLAG 2064 1248 0
FLAG 2416 1008 0
FLAG 2304 1008 0
FLAG 2176 1200 0
FLAG 2416 896 OUT
FLAG 1616 896 IN
TEXT 2168 1248 Left 2 !.tran 15m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\OP482.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP482.asy)
V1 N003 0 SINE(0 1 1k)
R3 N002 N001 10k
XU1 N003 N001 V+ V- N002 OP482 ;pnba In+)In-)V+)V-)OUT
V2 V+ 0 15
V3 0 V- 15
R2 N001 0 10k
R1 N002 0 10k
.tran 5m
.lib OP482.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 -32 -32 -32
WIRE 192 -32 128 -32
WIRE 256 -32 192 -32
WIRE 416 -32 336 -32
WIRE -272 -16 -272 -64
WIRE -32 48 -32 -32
WIRE -272 96 -272 64
WIRE -160 96 -272 96
WIRE 256 96 256 64
WIRE 192 112 192 -32
WIRE 224 112 192 112
WIRE -160 128 -160 96
WIRE 416 128 416 -32
WIRE 416 128 288 128
WIRE 432 128 416 128
WIRE 224 144 80 144
WIRE -272 160 -272 96
WIRE 432 160 432 128
WIRE 80 192 80 144
WIRE 256 192 256 160
WIRE -272 304 -272 240
WIRE 80 368 80 272
WIRE 432 368 432 240
SYMBOL res 352 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL OP482 256 64 R0
SYMATTR InstName U1
SYMBOL res 416 144 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -272 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 144 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -272 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage 80 176 R0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
FLAG 256 64 V+
FLAG 256 192 V-
FLAG -32 48 0
FLAG 80 368 0
FLAG 432 368 0
FLAG -160 128 0
FLAG -272 -64 V+
FLAG -272 304 V-
TEXT 104 328 Left 2 !.tran 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6655LN-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LTC6655LN-2.5.asy)
C3 vOUT 0 10
C1 vIN 0 1
C2 N001 0 10
XU1 vIN vIN 0 N001 vOUT LTC6655LN-2.5 ;pnba _SHDN)IN)GND)NR)OUT_F
V1 vIN 0 5
.tran 5m startup
.lib LTC6655LN-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1144 680
WIRE -64 144 -176 144
WIRE 32 144 -64 144
WIRE 80 144 32 144
WIRE 560 144 368 144
WIRE -176 176 -176 144
WIRE -64 192 -64 144
WIRE 560 192 560 144
WIRE 32 208 32 144
WIRE 80 208 32 208
WIRE 464 208 368 208
WIRE -176 288 -176 256
WIRE -64 288 -64 256
WIRE 224 288 224 240
WIRE 464 288 464 272
WIRE 560 288 560 256
SYMBOL LTC6655LN-2.5 224 176 R0
SYMATTR InstName U1
SYMBOL cap 448 208 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL cap -80 192 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -176 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 544 192 R0
SYMATTR InstName C3
SYMATTR Value 10
FLAG -64 288 0
FLAG -176 288 0
FLAG 464 288 0
FLAG 560 288 0
FLAG 560 144 vOUT
FLAG -176 144 vIN
FLAG 224 288 0
TEXT -192 360 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\5964af2bd28f_VA-R1.asc
* Generated by LTspice 26.0.1 for Windows.
D1 b a RRE02VSM4S
R1 b 0 1000
V1 a 0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0 100
.step temp list 0 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 128 -144 128
WIRE 240 128 80 128
WIRE -144 192 -144 128
WIRE 240 192 240 128
WIRE -144 352 -144 272
WIRE 48 352 -144 352
WIRE 240 352 240 272
WIRE 240 352 48 352
WIRE 48 368 48 352
SYMBOL diode 80 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value RRE02VSM4S
SYMBOL voltage -144 176 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value ""
SYMATTR InstName V1
SYMBOL Misc\\EuropeanResistor 224 176 R0
SYMATTR InstName R1
SYMATTR Value 1000
FLAG -144 128 a
FLAG 240 128 b
FLAG 48 368 0
TEXT -144 392 Left 2 !.dc V1 0 100
TEXT -152 424 Left 2 !.step temp list 0 100
* Z:\home\khalils\Downloads\files\data\raw_asc\1eeb6da50e3d_scheme5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1037.asy)
C3 0 N006 20n
V1 0 N002 15
R3 Vout N001 397.9k
R1 N006 Vin 0.7958k
C2 N003 N001 10n
V2 N005 0 15
R4 0 N004 1G
R2 N003 N006 0.7958k
XU1 N003 N004 N005 N002 Vout LT1037 ;pnba In+)In-)V+)V-)OUT
C1 N001 Vin 10n
R5 N004 Vout 1m
V3 Vin 0 AC 1
.ac dec 100 10 100k
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 80 48 -32 48
WIRE 304 48 160 48
WIRE 384 112 192 112
WIRE 480 112 464 112
WIRE 192 128 192 112
WIRE -144 144 -288 144
WIRE -128 144 -144 144
WIRE -32 144 -32 48
WIRE -32 144 -64 144
WIRE 0 144 -32 144
WIRE 80 144 64 144
WIRE 160 144 80 144
WIRE -288 160 -288 144
WIRE 304 160 304 48
WIRE 304 160 224 160
WIRE 336 160 304 160
WIRE 480 160 480 112
WIRE 512 160 480 160
WIRE 160 176 128 176
WIRE 512 176 512 160
WIRE 192 208 192 192
WIRE 384 208 192 208
WIRE 480 208 480 160
WIRE 480 208 464 208
WIRE -144 256 -144 144
WIRE -128 256 -144 256
WIRE -32 256 -48 256
WIRE -16 256 -32 256
WIRE 80 256 80 144
WIRE 80 256 64 256
WIRE 128 256 128 176
WIRE 176 256 128 256
WIRE 304 256 304 160
WIRE 304 256 256 256
WIRE 128 272 128 256
WIRE -32 320 -32 256
WIRE -32 416 -32 384
SYMBOL res 160 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 1m
SYMBOL res 144 368 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 1G
SYMBOL cap -16 384 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value 20n
SYMBOL cap 64 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap -64 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 80 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 0.7958k
SYMBOL OpAmps\\LT1037 192 224 M180
SYMATTR InstName U1
SYMBOL res -32 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 0.7958k
SYMBOL res 176 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 397.9k
SYMBOL voltage -288 144 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL voltage 368 208 R270
WINDOW 0 35 49 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL voltage 480 112 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 28 28 VTop 2
SYMATTR InstName V1
SYMATTR Value 15
FLAG -32 416 0
FLAG 128 352 0
FLAG 512 176 0
FLAG -288 240 0
FLAG -288 144 Vin
FLAG 336 160 Vout
TEXT 192 328 Left 2 !.ac dec 100 10 100k
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1236.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1236.asy)
V5 N002 0 SINE(0 10 2k)
R1 N001 0 1K
R2 N003 0 1K
XU1 N004 N001 N002 N003 -V 0 +V ADG1236 ;pnba IN)SA)D)SB)Vss)GND)Vdd
V4 N004 0 pulse(0 3.3 0 1u 1u 5m 10m)
V2 -V 0 -15
V1 +V 0 15
.tran 30m
.lib ADG1236.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -752 -368 -800 -368
WIRE -800 -320 -800 -368
WIRE -1216 -256 -1216 -272
WIRE -1056 -256 -1072 -256
WIRE -896 -256 -976 -256
WIRE -656 -224 -704 -224
WIRE -544 -224 -576 -224
WIRE -1008 -192 -1072 -192
WIRE -896 -192 -928 -192
WIRE -1216 -160 -1216 -176
WIRE -896 -128 -1072 -128
WIRE -1216 -48 -1216 -64
WIRE -1072 -16 -1072 -128
WIRE -736 0 -736 -16
WIRE -864 16 -864 -16
WIRE -832 16 -864 16
WIRE -1216 48 -1216 32
WIRE -1072 80 -1072 64
SYMBOL voltage -672 -224 R270
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 47 41 VRight 2
WINDOW 3 -46 -22 VRight 2
SYMATTR InstName V5
SYMATTR Value SINE(0 10 2k)
SYMBOL voltage -1216 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -1216 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res -960 -240 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res -912 -176 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -1072 -32 R0
SYMATTR InstName V4
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMBOL ADG1236 -800 -176 R0
SYMATTR InstName U1
FLAG -1216 48 0
FLAG -1216 -160 0
FLAG -1216 -272 +V
FLAG -1216 -64 -V
FLAG -544 -224 0
FLAG -1072 80 0
FLAG -1072 -256 0
FLAG -1072 -192 0
FLAG -752 -368 +V
FLAG -736 0 0
FLAG -832 16 -V
TEXT -656 -8 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\27d4f9a5184d_MonteCarlo.asc
* Generated by LTspice 26.0.1 for Windows.
* Monte Carlo Simulation in LTspice
* mc(val, tol) is a function that uses a random number generator \n to return a value between val-tol*val and val+tol*val\n \nOther functions of interest:\n \nflat(x): a function that uses a random number generator \n to return a value between -x and x;\n \ngauss(x): a function that uses a random number generator \n to return a value with a Gaussian distribution\n and sigma x.
C3 N004 N003 {mc(250p, tol)}
L1 N004 0 {mc(10u, tol)}
R2 0 N004 141
L2 N002 0 {mc(10u, tol)}
R1 N002 N001 141
V1 N001 0 AC 1
C2 N002 0 {mc(1n, tol)}
C1 N004 0 {mc(1n, tol)}
L3 N003 N002 {mc(40u, tol)}
.ac oct 100 300K 10Meg
.step param X 0 20 1 ; a dummy paramter to cycle Monte Carlo runs
.param tol=.05 ; +/- 5% component tolerance
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1516 692
WIRE -288 -496 -448 -496
WIRE -96 -496 -208 -496
WIRE -32 -496 -96 -496
WIRE 112 -496 -32 -496
WIRE 320 -496 192 -496
WIRE 544 -496 384 -496
WIRE 624 -496 544 -496
WIRE 848 -496 624 -496
WIRE -448 -480 -448 -496
WIRE -96 -464 -96 -496
WIRE -32 -464 -32 -496
WIRE 544 -464 544 -496
WIRE 624 -464 624 -496
WIRE 848 -464 848 -496
WIRE -448 -368 -448 -400
WIRE -96 -368 -96 -384
WIRE -32 -368 -32 -400
WIRE 544 -368 544 -384
WIRE 624 -368 624 -400
WIRE 848 -368 848 -384
SYMBOL ind 560 -480 M0
SYMATTR InstName L1
SYMATTR Value {mc(10u, tol)}
SYMBOL res 832 -368 M180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R2
SYMATTR Value 141
SYMBOL voltage -448 -496 R0
SYMATTR InstName V1
SYMATTR Value AC 1
SYMBOL res -192 -512 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 141
SYMBOL cap 608 -464 R0
SYMATTR InstName C1
SYMATTR Value {mc(1n, tol)}
SYMBOL ind 208 -480 M270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName L3
SYMATTR Value {mc(40u, tol)}
SYMBOL cap -48 -464 R0
SYMATTR InstName C2
SYMATTR Value {mc(1n, tol)}
SYMBOL cap 384 -512 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C3
SYMATTR Value {mc(250p, tol)}
SYMBOL ind -80 -480 M0
SYMATTR InstName L2
SYMATTR Value {mc(10u, tol)}
FLAG 624 -368 0
FLAG -448 -368 0
FLAG 544 -368 0
FLAG -32 -368 0
FLAG -96 -368 0
FLAG 848 -368 0
TEXT -408 -264 Left 0 !.ac oct 100 300K 10Meg
TEXT -408 -296 Left 0 !.step param X 0 20 1 ; a dummy paramter to cycle Monte Carlo runs
TEXT -408 -328 Left 0 !.param tol=.05 ; +/- 5% component tolerance
TEXT 56 -592 Left 0 ;Monte Carlo Simulation in LTspice
TEXT -152 -200 Left 0 ;mc(val, tol) is a function that uses a random number generator \n                     to return a value between val-tol*val and val+tol*val\n \nOther functions of interest:\n \nflat(x): a function that uses a random number generator \n         to return a value between -x and x;\n \ngauss(x): a function that uses a random number generator \n          to return a value with a Gaussian distribution\n          and sigma x.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT9890.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\CurrentMonitors\LT9890.asy)
R1 OUT 0 200
XU1 N001 0 MP_01 OUT IN LT9890 ;pnba IM)GND))IOUT)IP
V1 IN 0 12
I1 N001 0 150 load
.tran 0 1m 0 startup
.lib LT9890.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -96 64
WIRE 480 64 384 64
WIRE -96 112 -96 64
WIRE 480 112 480 64
WIRE -96 240 -96 192
WIRE 288 336 288 304
WIRE 480 336 480 192
WIRE 480 336 288 336
WIRE 128 352 128 304
WIRE 128 352 80 352
WIRE 288 368 288 336
WIRE 128 400 128 352
WIRE 128 560 128 480
SYMBOL current 480 112 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 24 108 Left 2
SYMATTR Value 150
SYMATTR SpiceLine load
SYMATTR InstName I1
SYMBOL LT9890 208 160 R0
SYMATTR InstName U1
SYMBOL res 112 384 R0
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL voltage -96 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 288 368 0
FLAG 128 560 0
FLAG -96 240 0
FLAG -96 64 IN
FLAG 80 352 OUT
TEXT -128 584 Left 2 !.tran 0 1m 0 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX42403A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX42403A.asy)
C2 N001 N002 0.1
V1 vIN 0 12
C3 vOUT 0 47 Rser=2m
C1 N003 0 2.2
XU1 0 0 vIN vIN N002 N001 N003 N003 N004 PGOOD N003 MAX42403A ;pnba GND)PGND)EN)SUP)LX)BST)BIAS)SPS)FB)PGOOD)SYNC
L1 N002 vOUT 6.8 Rser=17.6m
R1 PGOOD N003 20k
Rload vOUT 0 0.95
R3 N004 0 15.8k
R2 vOUT N004 49.9k
C4 vOUT N004 33p
.tran 3m startup
.lib MAX42403A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 64 -144 48 -144
WIRE 144 -144 64 -144
WIRE 176 -144 144 -144
WIRE 512 -144 464 -144
WIRE 48 -128 48 -144
WIRE 512 -128 512 -144
WIRE 144 -96 144 -144
WIRE 176 -96 144 -96
WIRE 48 -32 48 -48
WIRE 512 -32 512 -64
WIRE 512 -32 464 -32
WIRE 608 -32 512 -32
WIRE 736 -32 688 -32
WIRE 832 -32 736 -32
WIRE 960 -32 832 -32
WIRE 1024 -32 960 -32
WIRE 1056 -32 1024 -32
WIRE 736 -16 736 -32
WIRE 1056 -16 1056 -32
WIRE 832 0 832 -32
WIRE 960 0 960 -32
WIRE 176 16 112 16
WIRE 736 64 736 48
WIRE 1056 80 1056 64
WIRE 832 96 832 80
WIRE 832 96 464 96
WIRE 960 96 960 64
WIRE 960 96 832 96
WIRE 112 128 112 16
WIRE 176 128 112 128
WIRE 832 128 832 96
WIRE 480 224 464 224
WIRE 832 224 832 208
WIRE 112 272 112 128
WIRE 112 272 32 272
WIRE 176 272 112 272
WIRE 32 288 32 272
WIRE 512 288 464 288
WIRE 608 288 512 288
WIRE 320 352 320 336
WIRE 32 368 32 352
WIRE 112 400 112 272
WIRE 496 400 112 400
WIRE 608 400 608 288
WIRE 608 400 576 400
SYMBOL cap 720 -16 R0
SYMATTR InstName C3
SYMATTR Value 47
SYMATTR SpiceLine Rser=2m
SYMBOL res 816 -16 R0
SYMATTR InstName R2
SYMATTR Value 49.9k
SYMBOL cap 944 0 R0
SYMATTR InstName C4
SYMATTR Value 33p
SYMBOL cap 16 288 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL res 592 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 20k
SYMBOL res 1040 -32 R0
SYMATTR InstName Rload
SYMATTR Value 0.95
SYMBOL cap 496 -128 R0
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL MAX42403A 320 96 R0
SYMATTR InstName U1
SYMBOL voltage 48 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 816 112 R0
SYMATTR InstName R3
SYMATTR Value 15.8k
SYMBOL ind 592 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 6.8
SYMATTR SpiceLine Rser=17.6m
FLAG 48 -32 0
FLAG 32 368 0
FLAG 320 352 0
FLAG 736 64 0
FLAG 1056 80 0
FLAG 64 -144 vIN
FLAG 1024 -32 vOUT
FLAG 480 224 0
FLAG 832 224 0
FLAG 512 288 PGOOD
TEXT 648 376 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2120-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 OUT 2.2
C1 OUT 0 10
R1 OUT N001 100K
V1 IN 0 5
Rload OUT 0 1.8
C2 OUT 0 10
XU1 IN IN N002 0 0 OUT IN N001 IN IN ADP2120-1.8 ;pnba Vin)Pvin)SW)PGND)GND)FB)TRK)Pgood)Sync/Mode)EN
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2120-1.8.asy)
.lib ADP2120-1.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 0 48 0
WIRE 288 0 128 0
WIRE 48 16 48 0
WIRE 288 16 288 0
WIRE 128 64 128 0
WIRE 160 64 128 64
WIRE 496 64 416 64
WIRE 688 64 576 64
WIRE 48 112 48 96
WIRE 128 144 128 64
WIRE 160 144 128 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 624 144 560 144
WIRE 688 144 688 64
WIRE 688 144 624 144
WIRE 768 144 688 144
WIRE 560 160 560 144
WIRE 624 160 624 144
WIRE 768 160 768 144
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 560 224 416 224
WIRE 624 224 560 224
WIRE 560 256 560 224
WIRE 768 256 768 240
WIRE 128 304 128 224
WIRE 160 304 128 304
WIRE 688 304 688 144
WIRE 688 304 416 304
WIRE 288 368 288 352
FLAG 560 256 0
FLAG 288 368 0
FLAG 48 112 0
FLAG 768 144 OUT
FLAG 768 256 0
FLAG 48 0 IN
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL cap 544 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL voltage 48 0 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 752 144 R0
SYMATTR Value 1.8
SYMATTR InstName Rload
SYMBOL cap 608 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL ADP2120-1.8 288 272 R0
SYMATTR InstName U1
TEXT 504 344 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-4.2.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-4.2.asy)
L1 N001 N002 1.5 Rser=80m
Rload OUT 0 50
V1 IN 0 3.3
C1 OUT 0 10
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-4.2 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
.tran 400u startup
.lib ADP2504-4.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2504-4.2 176 176 R0
SYMATTR InstName U1
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 344 392 Left 2 !.tran 400u startup
TEXT 168 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\0720c893ee62_beta_fig8_.asc
* Generated by LTspice 26.0.1 for Windows.
+IS=20F VAF=50 IKR=12M BR=10 NC=2 VAR=10 RB=280
+RE=1 RC=40 VJE=0.48 TR=0.3U TF=0.5N CJE=12P
+VJC=0.7 MJE=0.5 CJC=6P MJC=0.33 ISC=47P KF=2F
V2 N001 0 {Vcc}
V1 N003 0 5
Q1 N002 N004 0 0 trans_BC547B
R2 N001 N002 560
R1 N003 N004 100k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 5 0.2
.step param Vcc list 2 5 10
.model trans_BC547B NPN BF=500 NE=1.3 ISE=9.72F IKF=80M
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2620 680
WIRE 448 -80 288 -80
WIRE 288 -64 288 -80
WIRE 448 48 448 -80
WIRE 288 80 288 16
WIRE 80 128 -16 128
WIRE 224 128 160 128
WIRE -16 144 -16 128
WIRE -16 240 -16 224
WIRE 288 240 288 176
WIRE 288 240 -16 240
WIRE 448 240 448 128
WIRE 448 240 288 240
WIRE 288 272 288 240
SYMBOL voltage -16 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 272 -80 R0
SYMATTR InstName R2
SYMATTR Value 560
SYMBOL voltage 448 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vcc}
SYMBOL res 64 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL npn 224 80 R0
SYMATTR InstName Q1
SYMATTR Value trans_BC547B
FLAG 288 272 0
TEXT -16 264 Left 2 !.dc V1 0 5 0.2
TEXT 472 176 Left 2 !.step param Vcc list 2 5 10
TEXT 32 -192 Left 2 !.model trans_BC547B NPN BF=500 NE=1.3 ISE=9.72F IKF=80M\n+IS=20F VAF=50 IKR=12M BR=10 NC=2 VAR=10 RB=280\n+RE=1 RC=40 VJE=0.48 TR=0.3U TF=0.5N CJE=12P\n+VJC=0.7 MJE=0.5 CJC=6P MJC=0.33 ISC=47P KF=2F
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6274.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6274.asy)
V2 -V 0 -15
R1 N003 N002 1K
V1 +V 0 15
V3 N001 0 SINE(0 10 3Meg)
R2 N002 N001 1K
XU1 0 N002 +V -V N003 LT6275 ;pnba In+)In-)V+)V-)OUT
.tran 10u
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -112 0 -112
WIRE 256 -112 224 -112
WIRE 288 -112 256 -112
WIRE 416 -112 368 -112
WIRE 0 -96 0 -112
WIRE -336 -80 -336 -96
WIRE -176 -80 -176 -96
WIRE 0 0 0 -16
WIRE 336 0 336 -16
WIRE -336 16 -336 0
WIRE -176 16 -176 0
WIRE 256 16 256 -112
WIRE 304 16 256 16
WIRE 416 32 416 -112
WIRE 416 32 368 32
WIRE 304 48 288 48
WIRE 336 80 336 64
SYMBOL voltage 0 -112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 10 3Meg)
SYMBOL res 384 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL opamps\\LT6274 336 32 R0
SYMATTR InstName U1
SYMBOL res 240 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -336 -96 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -176 -96 R0
SYMATTR InstName V2
SYMATTR Value -15
FLAG -336 16 0
FLAG -176 16 0
FLAG -336 -96 +V
FLAG -176 -96 -V
FLAG 336 -16 +V
FLAG 336 80 -V
FLAG 0 0 0
FLAG 288 48 0
TEXT 432 136 Left 2 !.tran 10u