Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\0f2f7c7dd9f7_Double_and__stagger__tuned__amp_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 Q1c 1mh
C2 N001 Q1c 1n
R1 N001 N004 10k
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 724
WIRE 224 -80 224 -112
WIRE 224 -80 -96 -80
WIRE 224 -48 224 -80
WIRE 336 -48 224 -48
WIRE 336 16 336 -48
WIRE 448 16 336 16
WIRE 784 16 624 16
WIRE 224 32 224 -48
WIRE -96 80 -96 -80
WIRE 448 96 336 96
WIRE 704 96 624 96
WIRE 224 160 224 96
WIRE 336 160 336 96
WIRE 336 160 224 160
WIRE 224 224 224 160
WIRE 224 256 224 224
WIRE -96 304 -96 160
SYMBOL ind 432 0 R0
SYMATTR InstName L1
SYMATTR Value 1mh
SYMATTR Type ind
SYMBOL cap 208 32 R0
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL res -112 64 R0
SYMATTR InstName R1
SYMATTR Value 10k
FLAG 224 224 Q1c
* Z:\home\khalils\Downloads\files\data\raw_asc\36fca00c4745_eje1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 0 {rs}
R2 o2 0 {rp}
L2 o2 0 {Lp}
L1 o1 N001 {Ls}
I1 0 o2 AC 1e-3
V1 o1 0 AC 1e-3
.ac dec 1000 1e6 100e6
.net V(o2) I1 Ri2=50
.net V(o1) V1 Ri1=50
.param rs = 1.571
.param Ls = 1.000e-06
.param rp = 2513.274
.param Lp = 1.000e-06
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -112 32 -160 32
WIRE -48 32 -112 32
WIRE 192 32 128 32
WIRE 224 32 192 32
WIRE 320 32 224 32
WIRE -48 64 -48 32
WIRE 128 112 128 32
WIRE 224 112 224 32
WIRE 320 112 320 32
WIRE -160 144 -160 32
WIRE -48 176 -48 144
WIRE 128 288 128 192
WIRE 224 288 224 192
WIRE 320 288 320 192
WIRE -160 304 -160 224
WIRE -48 304 -48 256
SYMBOL res 304 96 R0
SYMATTR InstName R2
SYMATTR Value {rp}
SYMBOL ind 208 96 R0
SYMATTR InstName L2
SYMATTR Value {Lp}
SYMBOL ind -64 48 R0
SYMATTR InstName L1
SYMATTR Value {Ls}
SYMBOL res -64 160 R0
SYMATTR InstName R1
SYMATTR Value {rs}
SYMBOL voltage -160 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1e-3
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL current 128 192 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value ""
SYMATTR Value2 AC 1e-3
FLAG -48 304 0
FLAG 224 288 0
FLAG 320 288 0
FLAG 128 288 0
FLAG -160 304 0
FLAG 192 32 o2
FLAG -112 32 o1
TEXT -88 352 Left 2 !.ac dec 1000 1e6 100e6
TEXT -264 392 Left 2 !.net V(o2) I1 Ri2=50
TEXT -264 424 Left 2 !.net V(o1) V1 Ri1=50
TEXT -248 -56 Left 2 !.param rs  =  1.571 \n.param Ls  =  1.000e-06
TEXT 120 -64 Left 2 !.param rp  =  2513.274 \n.param Lp  =  1.000e-06
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX20336.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\MAX20336.asy)
R1 vCOM 0 49.9
V1 vNO 0 SINE(0 5.5 20)
V2 vVccEN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
XU1 vVccEN vCOM vNO 0 MAX20336 ;pnba VccEN)COM)NO)GND
.tran 1
.lib MAX20336.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE -112 224 -144 224
WIRE 80 224 -32 224
WIRE 112 224 80 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 464 256 464 224
WIRE 64 288 16 288
WIRE 112 288 64 288
WIRE 16 336 16 288
WIRE 464 352 464 336
WIRE 224 416 224 400
WIRE 16 464 16 416
SYMBOL voltage -16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5.5 20)
SYMBOL voltage 16 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL MAX20336 224 272 R0
SYMATTR InstName U1
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 49.9
FLAG -144 224 0
FLAG 16 464 0
FLAG 464 352 0
FLAG 224 416 0
FLAG 384 224 vCOM
FLAG 80 224 vNO
FLAG 64 288 vVccEN
TEXT -288 72 Left 2 !.tran 1
TEXT -288 8 Left 2 ;Note:\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\551a7cb94ec1_exp2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vin 0 PULSE(0 1.8 1n 1n 1n 20n 40n) Rser=0
M1 vout vin N001 N001 PMOS
M2 vout vin 0 0 NMOS
V2 N001 0 1.8 Rser=0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* .dc V1 0 1.8 0.01
.tran 0 100n 0 10n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 784 -240 512 -240
WIRE 512 -208 512 -240
WIRE 784 -208 784 -240
WIRE 464 -192 304 -192
WIRE 512 -32 512 -112
WIRE 528 -32 512 -32
WIRE 144 0 -32 0
WIRE 304 0 304 -192
WIRE 304 0 144 0
WIRE 528 48 528 -32
WIRE 144 128 144 0
WIRE 528 128 528 48
WIRE 304 208 304 0
WIRE 480 208 304 208
FLAG 784 -128 0
FLAG 528 48 vout
FLAG -32 0 vin
FLAG 144 208 0
FLAG 528 224 0
SYMBOL voltage 144 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1.8 1n 1n 1n 20n 40n)
SYMBOL pmos 464 -112 M180
SYMATTR InstName M1
SYMBOL nmos 480 128 R0
SYMATTR InstName M2
SYMBOL voltage 784 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR SpiceLine Rser=0
SYMATTR InstName V2
SYMATTR Value 1.8
TEXT 72 336 Left 2 ;.dc V1 0 1.8 0.01
TEXT 440 312 Left 2 !.tran 0 100n 0 10n
* Z:\home\khalils\Downloads\files\data\raw_asc\1571cdc38848_nor.asc
* Generated by LTspice 26.0.1 for Windows.
M2 out in2 P001 vdd PMOS l=90n w=400n
M1 P001 in1 vdd N001 PMOS l=90n w=400n
M3 out in1 0 N002 NMOS l=90n w=200n
M4 out in2 0 N003 NMOS l=90n w=200n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 -128 288 -144
WIRE 384 -128 288 -128
WIRE 288 -112 288 -128
WIRE 240 -96 64 -96
WIRE 288 -64 288 -96
WIRE 240 0 80 0
WIRE 384 32 384 -128
WIRE 384 32 288 32
WIRE 64 96 64 -96
WIRE 64 96 48 96
WIRE 288 128 288 80
WIRE 448 128 288 128
WIRE 80 160 80 0
WIRE 80 160 48 160
WIRE 288 160 288 128
WIRE 288 160 224 160
WIRE 368 160 288 160
WIRE 224 176 224 160
WIRE 368 176 368 160
WIRE 64 256 64 96
WIRE 176 256 64 256
WIRE 224 256 224 224
WIRE 320 256 304 256
WIRE 368 256 368 224
WIRE 80 304 80 160
WIRE 304 304 304 256
WIRE 304 304 80 304
WIRE 224 336 224 272
WIRE 288 336 224 336
WIRE 368 336 368 272
WIRE 368 336 288 336
WIRE 288 352 288 336
IOPIN 48 96 In
IOPIN 48 160 In
IOPIN 448 128 Out
IOPIN 288 -144 In
SYMBOL nmos4 320 176 R0
SYMATTR InstName M4
SYMATTR Value2 l=90n w=200n
SYMBOL nmos4 176 176 R0
SYMATTR InstName M3
SYMATTR Value2 l=90n w=200n
SYMBOL pmos4 240 80 M180
SYMATTR InstName M2
SYMATTR Value2 l=90n w=400n
SYMBOL pmos4 240 -16 M180
SYMATTR InstName M1
SYMATTR Value2 l=90n w=400n
FLAG 48 96 in1
FLAG 48 160 in2
FLAG 448 128 out
FLAG 288 -144 vdd
FLAG 288 352 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1167.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1167.asy)
V1 +V 0 15
R1 N002 N001 1K
V2 -V 0 -15
V3 N003 0 SINE(0 10m 1K)
XU1 N001 N003 0 -V 0 OUT +V N002 LT1167 ;pnba Rg)In-)In+)V-)Ref)Out)V+)Rg
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 384 16 288 16
WIRE 576 16 464 16
WIRE 32 32 32 16
WIRE 144 32 144 16
WIRE 32 128 32 112
WIRE 144 128 144 112
WIRE 288 128 288 16
WIRE 304 128 288 128
WIRE 576 128 576 16
WIRE 576 128 560 128
WIRE 224 176 -16 176
WIRE -16 192 -16 176
WIRE 224 192 224 176
WIRE 304 192 224 192
WIRE 592 192 560 192
WIRE 304 256 224 256
WIRE 592 256 560 256
WIRE -16 288 -16 272
WIRE 224 288 224 256
WIRE 224 288 -16 288
WIRE -16 304 -16 288
WIRE 304 320 288 320
WIRE 592 320 560 320
SYMBOL opamps\\LT1167 432 224 R0
SYMATTR InstName U1
SYMBOL res 480 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage 32 16 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 144 16 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -16 176 R0
WINDOW 3 39 86 Left 2
SYMATTR Value SINE(0 10m 1K)
SYMATTR InstName V3
FLAG 144 128 0
FLAG 144 16 +V
FLAG 32 128 0
FLAG 32 16 -V
FLAG 592 192 +V
FLAG 288 320 -V
FLAG -16 304 0
FLAG 592 256 OUT
FLAG 592 320 0
TEXT 584 384 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\29aa4a5afab5_Q1.asc
* Generated by LTspice 26.0.1 for Windows.
M2 N001 N002 0 0 nch_tt l=180n w=240n
Vdd N002 0 1.8
C1 N001 0 1p IC=1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.tran 30ns
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 688 32 416 32
WIRE 416 112 416 32
WIRE 688 144 688 32
WIRE 368 192 160 192
WIRE 160 240 160 192
WIRE 160 448 160 320
WIRE 416 448 416 208
WIRE 416 448 160 448
WIRE 688 448 688 208
WIRE 688 448 416 448
WIRE 416 480 416 448
SYMBOL nmos 368 112 R0
SYMATTR InstName M2
SYMATTR Value nch_tt
SYMATTR Value2 l=180n w=240n
SYMBOL cap 672 144 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMATTR SpiceLine IC=1.8
SYMBOL voltage 160 224 R0
SYMATTR InstName Vdd
SYMATTR Value 1.8
FLAG 416 480 0
TEXT -136 176 Left 2 !.include TSMC180.lib
TEXT -82 216 Left 2 !.tran 30ns
* Z:\home\khalils\Downloads\files\data\raw_asc\4efd76086f8b_Fig23_4.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot VREF
M6B VREF VREF 0 0 N_1u l=2u w=10u
R1 VDD VREF 1Meg TC1=0.002
VDD VDD 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.dc VDD 4 6
.step temp 0 100 25
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1784 680
WIRE 1376 -96 1376 -160
WIRE 1104 -32 1104 -64
WIRE 1104 -16 1104 -32
WIRE 1376 0 1376 -16
WIRE 1488 0 1376 0
WIRE 1376 16 1376 0
WIRE 1376 16 1312 16
WIRE 1376 32 1376 16
WIRE 1312 112 1312 16
WIRE 1328 112 1312 112
WIRE 1376 160 1376 128
SYMBOL nmos4 1328 32 R0
WINDOW 123 56 100 Left 0
WINDOW 0 69 31 Left 0
SYMATTR Value2 l=2u w=10u
SYMATTR InstName M6B
SYMATTR Value N_1u
SYMBOL voltage 1104 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL res 1360 -112 R0
SYMATTR InstName R1
SYMATTR Value 1MEG TC1=0.002
FLAG 1104 64 0
FLAG 1104 -32 VDD
FLAG 1376 80 0
FLAG 1376 160 0
FLAG 1376 -160 VDD
FLAG 1488 0 VREF
TEXT 1016 136 Left 0 !.include cmosedu_models.txt
TEXT 1160 -152 Left 0 ;Plot VREF
TEXT 1016 112 Left 0 !.dc VDD 4 6
TEXT 1016 160 Left 0 !.step temp 0 100 25
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1501-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1501-5.asy)
C1 OUT 0 220 Rser=0.05
XU1 IN IN N001 0 N002 N003 N004 OUT LT1501-5 ;pnba _SHDN)Vin)Isense)GND)SW)LBO)LBI)FB
V1 IN 0 3
L1 N001 N002 33
R1 OUT 0 30
D1 N002 OUT 1N5818
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT1501-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2080 1544
WIRE 1296 1072 1264 1072
WIRE 1408 1072 1376 1072
WIRE 1440 1072 1408 1072
WIRE 1552 1072 1504 1072
WIRE 1632 1072 1552 1072
WIRE 1632 1088 1632 1072
WIRE 992 1120 896 1120
WIRE 1104 1120 992 1120
WIRE 896 1136 896 1120
WIRE 1104 1136 1104 1120
WIRE 1264 1136 1264 1072
WIRE 1632 1184 1632 1168
WIRE 1408 1200 1408 1072
WIRE 1408 1200 1360 1200
WIRE 992 1216 992 1120
WIRE 1008 1216 992 1216
WIRE 896 1232 896 1216
WIRE 1376 1264 1360 1264
WIRE 1008 1312 992 1312
WIRE 1552 1328 1552 1072
WIRE 1552 1328 1360 1328
WIRE 1552 1344 1552 1328
WIRE 1184 1408 1184 1392
WIRE 1552 1424 1552 1408
SYMBOL polcap 1536 1344 R0
SYMATTR InstName C1
SYMATTR Value 220
SYMATTR SpiceLine Rser=0.05
SYMBOL VOLTAGE 896 1120 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL PowerProducts\\LT1501-5 1184 1264 R0
SYMATTR InstName U1
SYMBOL schottky 1440 1088 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5818
SYMBOL res 1616 1072 R0
SYMATTR InstName R1
SYMATTR Value 30
SYMBOL ind 1280 1088 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
FLAG 1184 1408 0
FLAG 896 1232 0
FLAG 1632 1184 0
FLAG 1552 1424 0
FLAG 1632 1072 OUT
FLAG 896 1120 IN
TEXT 1552 1480 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\39a806741e3c_Adder.asc
* Generated by LTspice 26.0.1 for Windows.
* Vo = Vx + Vy
* THE ADDER CIRCUIT
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
R3 N003 N002 1k
XU2 0 N003 V+ V- OUTPUT level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N001 Vx 1k
R4 OUTPUT N003 1k
R5 N001 Vy 1k
R1 N002 N001 1k
XU1 0 N001 V+ V- N002 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V1 Vx 0 3V
V2 Vy 0 2V
V4 V- 0 -12V
V3 V+ 0 12V
.tran 10ms
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 32 0 32
WIRE 112 32 96 32
WIRE 304 48 272 48
WIRE 416 48 384 48
WIRE -128 112 -176 112
WIRE -32 112 -48 112
WIRE -32 160 -32 112
WIRE 0 160 0 32
WIRE 0 160 -32 160
WIRE 16 160 0 160
WIRE 112 176 112 32
WIRE 112 176 80 176
WIRE 144 176 112 176
WIRE 272 176 272 48
WIRE 272 176 224 176
WIRE 304 176 272 176
WIRE 16 192 0 192
WIRE 416 192 416 48
WIRE 416 192 368 192
WIRE 464 192 416 192
WIRE -128 208 -176 208
WIRE -32 208 -32 160
WIRE -32 208 -48 208
WIRE 304 208 288 208
WIRE 0 256 0 192
WIRE 288 256 288 208
IOPIN -528 -112 Out
IOPIN -400 -112 Out
IOPIN -272 -112 Out
IOPIN -160 -112 Out
IOPIN -176 112 In
IOPIN -176 208 In
IOPIN 48 144 In
IOPIN 336 160 In
IOPIN 48 208 In
IOPIN 336 224 In
IOPIN 464 192 BiDir
SYMBOL res 240 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL voltage -528 -128 R0
SYMATTR InstName V1
SYMATTR Value 3V
SYMBOL res -32 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL voltage -160 -128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value -12V
SYMBOL voltage -400 -128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 2V
SYMBOL res 400 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res -32 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL Opamps\\UniversalOpamp2 336 192 R0
SYMATTR InstName U2
SYMBOL Opamps\\UniversalOpamp2 48 176 R0
SYMATTR InstName U1
SYMBOL voltage -272 -128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 12V
SYMBOL res 112 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 0 256 0
FLAG 288 256 0
FLAG -528 -32 0
FLAG -400 -32 0
FLAG -272 -32 0
FLAG -160 -32 0
FLAG -528 -112 Vx
FLAG -400 -112 Vy
FLAG -272 -112 V+
FLAG -160 -112 V-
FLAG -176 112 Vx
FLAG -176 208 Vy
FLAG 48 144 V+
FLAG 336 160 V+
FLAG 48 208 V-
FLAG 336 224 V-
FLAG 464 192 OUTPUT
TEXT 456 224 Left 2 ;Vo = Vx + Vy
TEXT -400 288 Left 2 !.tran 10ms
TEXT -176 -264 Left 6 ;THE ADDER CIRCUIT
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8630.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8630.asy)
Vin IN 0 SINE(0 1 10K)
Rload OUT 0 10K
R1 N001 0 10K
XU1 IN N001 +V -V OUT AD8630 ;pnba In+)In-)V+)V-)OUT
R2 OUT N001 10K
V1 +V 0 2.5
V2 -V 0 -2.5
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 352 -864 336 -864
WIRE 448 -864 432 -864
WIRE 464 -864 448 -864
WIRE 560 -864 544 -864
WIRE 112 -768 112 -784
WIRE 224 -768 224 -784
WIRE 448 -768 448 -864
WIRE 464 -768 448 -768
WIRE 560 -752 560 -864
WIRE 560 -752 528 -752
WIRE 688 -752 560 -752
WIRE 464 -736 352 -736
WIRE 688 -736 688 -752
WIRE 352 -720 352 -736
WIRE 112 -672 112 -688
WIRE 224 -672 224 -688
WIRE 688 -640 688 -656
WIRE 352 -624 352 -640
SYMBOL voltage 224 -784 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL Opamps\\AD8630 496 -816 R0
SYMATTR InstName U1
SYMBOL voltage 352 -736 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 112 -784 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 560 -880 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 672 -752 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL res 448 -880 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
FLAG 112 -784 +V
FLAG 112 -672 0
FLAG 352 -624 0
FLAG 688 -752 OUT
FLAG 352 -736 IN
FLAG 496 -784 +V
FLAG 224 -784 -V
FLAG 496 -720 -V
FLAG 336 -864 0
FLAG 688 -640 0
FLAG 224 -672 0
TEXT 704 -544 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\cf2a95dfa53d_AND.asc
* Generated by LTspice 26.0.1 for Windows.
M6 Vout N003 0 0 C5NNMOS l=0.6u w=3.6u
VA N002 0 PULSE(0 5 0 1n 1n 5u 10u)
M2 N005 N004 0 0 C5NNMOS l=0.6u w=3.6u
M3 N001 N002 N003 N001 C5NPMOS l=0.6u w=7.2u
V1 N001 0 5
VB N004 0 PULSE(0 5 0 1n 1n 10u 20u)
M4 N001 N004 N003 N001 C5NPMOS l=0.6u w=7.2u
M1 N003 N002 N005 0 C5NNMOS l=0.6u w=3.6u
M5 N001 N003 Vout N001 C5NPMOS l=0.6u w=7.2u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include D:\NIELIT\ENGR3426\ENGR3426\engr3426.sub
.tran 100u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1200 680
WIRE 672 -160 256 -160
WIRE 896 -160 672 -160
WIRE 1040 -160 896 -160
WIRE 672 -112 672 -160
WIRE 160 -64 48 -64
WIRE 256 -64 256 -160
WIRE 256 -64 160 -64
WIRE 416 -64 256 -64
WIRE 512 -64 416 -64
WIRE 672 0 672 -32
WIRE 48 32 48 -64
WIRE 416 32 416 -64
WIRE 896 48 896 -160
WIRE 160 80 160 -64
WIRE 160 80 48 80
WIRE 512 80 512 -64
WIRE 512 80 416 80
WIRE 1040 96 1040 -160
WIRE 1040 96 896 96
WIRE -64 112 -496 112
WIRE 0 112 -64 112
WIRE 848 128 704 128
WIRE -112 144 -272 144
WIRE 368 144 368 112
WIRE 368 144 -112 144
WIRE -496 192 -496 112
WIRE -272 192 -272 144
WIRE 896 192 896 144
WIRE 1088 192 896 192
WIRE 48 208 48 128
WIRE 160 208 48 208
WIRE 416 208 416 128
WIRE 416 208 160 208
WIRE 896 224 896 192
WIRE 160 256 160 208
WIRE 704 256 704 128
WIRE 704 256 160 256
WIRE 160 272 160 256
WIRE 1056 272 896 272
WIRE 704 304 704 256
WIRE 848 304 704 304
WIRE -496 320 -496 272
WIRE -272 320 -272 272
WIRE 288 320 160 320
WIRE -64 352 -64 112
WIRE 112 352 -64 352
WIRE 160 416 160 368
WIRE 288 464 288 320
WIRE 288 464 160 464
WIRE -112 496 -112 144
WIRE 112 496 -112 496
WIRE 288 512 288 464
WIRE 288 512 160 512
WIRE 896 512 896 320
WIRE 896 512 288 512
WIRE 1056 512 1056 272
WIRE 1056 512 896 512
WIRE 160 544 160 512
IOPIN 1088 192 Out
SYMBOL voltage -496 176 R0
WINDOW 3 -238 189 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VA
SYMATTR Value PULSE(0 5 0 1n 1n 5u 10u)
SYMBOL nmos4 112 272 R0
SYMATTR InstName M1
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL pmos4 0 32 R0
SYMATTR InstName M3
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL voltage 672 -128 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -272 176 R0
WINDOW 3 -99 191 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VB
SYMATTR Value PULSE(0 5 0 1n 1n 10u 20u)
SYMBOL pmos4 848 48 R0
SYMATTR InstName M5
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL nmos4 848 224 R0
SYMATTR InstName M6
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL nmos4 112 416 R0
SYMATTR InstName M2
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL pmos4 368 32 R0
SYMATTR InstName M4
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
FLAG -496 320 0
FLAG -272 320 0
FLAG 672 0 0
FLAG 160 544 0
FLAG 1088 192 Vout
TEXT -760 544 Left 2 !.include D:\\NIELIT\\ENGR3426\\ENGR3426\\engr3426.sub
TEXT -760 568 Left 2 !.tran 100u
* Z:\tmp\asc_dec_bjh7r6w2\0a6b04c06a8b_Draft1_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N004 82k
V1 0 -6V 6
R2 N001 N003 R
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 680
WIRE 336 -32 80 -32
WIRE 80 0 80 -32
WIRE 80 0 -32 0
WIRE 336 0 336 -32
WIRE 80 80 80 0
WIRE 208 80 80 80
WIRE -32 112 -32 0
WIRE 80 112 80 80
WIRE 208 112 208 80
WIRE 880 112 880 64
WIRE 336 128 336 80
WIRE 720 144 448 144
WIRE 208 224 208 192
WIRE 288 224 208 224
WIRE 720 256 720 144
WIRE 720 256 592 256
WIRE 880 256 880 192
WIRE 880 256 816 256
WIRE -32 272 -32 192
WIRE 288 272 288 224
WIRE 400 272 288 272
WIRE 80 288 80 192
WIRE 208 288 208 224
WIRE 816 288 816 256
WIRE 880 304 880 256
WIRE 880 448 880 384
SYMBOL res 64 96 R0
SYMATTR InstName R1
SYMATTR Value 82k
SYMBOL voltage 880 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 6
SYMBOL res 192 96 R0
SYMATTR InstName R2
FLAG 816 288 0
FLAG 880 448 -6V
FLAG -32 272 0
FLAG 336 128 0
FLAG 720 256 Vout
* Z:\home\khalils\Downloads\files\data\raw_asc\2b073a265daf_Comparator2.asc
* Generated by LTspice 26.0.1 for Windows.
* Comparators
A1 1 2 0 0 0 _s1 s1 0 SCHMITT Vhigh=5 trise=10n Vt=0 Vh=1m
R1 b1 0 10
B1 0 b1 I=IF(V(1,2)>0, .5, 0)
V1 1 0 PWL(0 -1 200n 1 400n -1)
V2 2 0 0
C1 b1 0 1n
.tran 0 1u 0 2n
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 96 -112 96
WIRE 144 96 0 96
WIRE 240 96 144 96
WIRE 144 144 144 96
WIRE -448 160 -448 128
WIRE -112 160 -112 96
WIRE 240 160 240 96
WIRE -448 272 -448 240
WIRE -112 288 -112 240
WIRE 144 288 144 224
WIRE 240 288 240 224
WIRE -448 352 -448 320
WIRE -32 400 -64 400
WIRE 80 400 32 400
WIRE -32 432 -64 432
WIRE 80 432 32 432
WIRE -448 464 -448 432
SYMBOL voltage -448 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 -1 200n 1 400n -1)
SYMBOL Digital\\diffschmitt -32 352 R0
SYMATTR InstName A1
SYMATTR Value2 Vhigh=5 trise=10n
SYMATTR SpiceLine Vt=0 Vh=1m
SYMBOL cap 224 160 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL bi -112 240 M180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName B1
SYMATTR Value I=IF(V(1,2)>0, .5, 0)
SYMBOL res 128 128 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage -448 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
FLAG -112 288 0
FLAG 144 288 0
FLAG 240 288 0
FLAG -448 272 0
FLAG -64 432 2
FLAG -64 400 1
FLAG -448 128 1
FLAG -448 464 0
FLAG -448 320 2
FLAG 80 400 s1
FLAG 80 432 _s1
FLAG 0 96 b1
TEXT -464 32 Left 0 !.tran 0 1u 0 2n
TEXT -464 56 Left 0 !.options plotwinsize=0
TEXT -136 -16 Left 0 ;Comparators
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1540.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 PWL(0 0 1 3.3)
R1 +V N001 4.32Meg
XU1 0 0 N001 N002 N002 N002 +V OUT LTC1540 ;pnba GND)V-)In+)In-)HYST)REF)V+)OUT
R2 N001 0 3Meg
.tran 1
* Nanopower 2.9V Vcc Threshold Detector
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LTC1540.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1144 800
WIRE 320 80 96 80
WIRE 576 80 320 80
WIRE 96 96 96 80
WIRE 320 96 320 80
WIRE 576 144 576 80
WIRE 96 192 96 176
WIRE 320 192 320 176
WIRE 480 192 320 192
WIRE 320 208 320 192
WIRE 688 208 640 208
WIRE 480 224 512 192
WIRE 512 224 480 192
WIRE 480 256 480 224
WIRE 512 256 480 256
WIRE 480 288 480 256
WIRE 512 288 480 288
WIRE 320 304 320 288
WIRE 544 368 544 336
WIRE 608 368 608 336
FLAG 96 192 0
FLAG 576 80 +V
FLAG 544 368 0
FLAG 608 368 0
FLAG 320 304 0
FLAG 688 208 OUT
SYMBOL voltage 96 80 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 3.3)
SYMBOL res 304 80 R0
SYMATTR InstName R1
SYMATTR Value 4.32Meg
SYMBOL Comparators\\LTC1540 576 144 R0
SYMATTR InstName U1
SYMBOL res 304 192 R0
SYMATTR InstName R2
SYMATTR Value 3Meg
TEXT 696 264 Left 2 !.tran 1
TEXT 560 48 Bottom 2 ;Nanopower 2.9V Vcc Threshold Detector