* Z:\home\khalils\Downloads\files\data\raw_asc\167be54b12da_shiftreg64_1_.asc
* Generated by LTspice 26.0.1 for Windows.
A[0] d[0] 0 clk 0 0 0 d[1] 0 DFLOP td=1n
A[1] d[1] 0 clk 0 0 0 d[2] 0 DFLOP td=1n
A[2] d[2] 0 clk 0 0 0 d[3] 0 DFLOP td=1n
A[3] d[3] 0 clk 0 0 0 d[4] 0 DFLOP td=1n
A[4] d[4] 0 clk 0 0 0 d[5] 0 DFLOP td=1n
A[5] d[5] 0 clk 0 0 0 d[6] 0 DFLOP td=1n
A[6] d[6] 0 clk 0 0 0 d[7] 0 DFLOP td=1n
A[7] d[7] 0 clk 0 0 0 d[8] 0 DFLOP td=1n
A[8] d[8] 0 clk 0 0 0 d[9] 0 DFLOP td=1n
A[9] d[9] 0 clk 0 0 0 d[10] 0 DFLOP td=1n
A[10] d[10] 0 clk 0 0 0 d[11] 0 DFLOP td=1n
A[11] d[11] 0 clk 0 0 0 d[12] 0 DFLOP td=1n
A[12] d[12] 0 clk 0 0 0 d[13] 0 DFLOP td=1n
A[13] d[13] 0 clk 0 0 0 d[14] 0 DFLOP td=1n
A[14] d[14] 0 clk 0 0 0 d[15] 0 DFLOP td=1n
A[15] d[15] 0 clk 0 0 0 d[16] 0 DFLOP td=1n
A[16] d[16] 0 clk 0 0 0 d[17] 0 DFLOP td=1n
A[17] d[17] 0 clk 0 0 0 d[18] 0 DFLOP td=1n
A[18] d[18] 0 clk 0 0 0 d[19] 0 DFLOP td=1n
A[19] d[19] 0 clk 0 0 0 d[20] 0 DFLOP td=1n
A[20] d[20] 0 clk 0 0 0 d[21] 0 DFLOP td=1n
A[21] d[21] 0 clk 0 0 0 d[22] 0 DFLOP td=1n
A[22] d[22] 0 clk 0 0 0 d[23] 0 DFLOP td=1n
A[23] d[23] 0 clk 0 0 0 d[24] 0 DFLOP td=1n
A[24] d[24] 0 clk 0 0 0 d[25] 0 DFLOP td=1n
A[25] d[25] 0 clk 0 0 0 d[26] 0 DFLOP td=1n
A[26] d[26] 0 clk 0 0 0 d[27] 0 DFLOP td=1n
A[27] d[27] 0 clk 0 0 0 d[28] 0 DFLOP td=1n
A[28] d[28] 0 clk 0 0 0 d[29] 0 DFLOP td=1n
A[29] d[29] 0 clk 0 0 0 d[30] 0 DFLOP td=1n
A[30] d[30] 0 clk 0 0 0 d[31] 0 DFLOP td=1n
A[31] d[31] 0 clk 0 0 0 d[32] 0 DFLOP td=1n
A[32] d[32] 0 clk 0 0 0 d[33] 0 DFLOP td=1n
A[33] d[33] 0 clk 0 0 0 d[34] 0 DFLOP td=1n
A[34] d[34] 0 clk 0 0 0 d[35] 0 DFLOP td=1n
A[35] d[35] 0 clk 0 0 0 d[36] 0 DFLOP td=1n
A[36] d[36] 0 clk 0 0 0 d[37] 0 DFLOP td=1n
A[37] d[37] 0 clk 0 0 0 d[38] 0 DFLOP td=1n
A[38] d[38] 0 clk 0 0 0 d[39] 0 DFLOP td=1n
A[39] d[39] 0 clk 0 0 0 d[40] 0 DFLOP td=1n
A[40] d[40] 0 clk 0 0 0 d[41] 0 DFLOP td=1n
A[41] d[41] 0 clk 0 0 0 d[42] 0 DFLOP td=1n
A[42] d[42] 0 clk 0 0 0 d[43] 0 DFLOP td=1n
A[43] d[43] 0 clk 0 0 0 d[44] 0 DFLOP td=1n
A[44] d[44] 0 clk 0 0 0 d[45] 0 DFLOP td=1n
A[45] d[45] 0 clk 0 0 0 d[46] 0 DFLOP td=1n
A[46] d[46] 0 clk 0 0 0 d[47] 0 DFLOP td=1n
A[47] d[47] 0 clk 0 0 0 d[48] 0 DFLOP td=1n
A[48] d[48] 0 clk 0 0 0 d[49] 0 DFLOP td=1n
A[49] d[49] 0 clk 0 0 0 d[50] 0 DFLOP td=1n
A[50] d[50] 0 clk 0 0 0 d[51] 0 DFLOP td=1n
A[51] d[51] 0 clk 0 0 0 d[52] 0 DFLOP td=1n
A[52] d[52] 0 clk 0 0 0 d[53] 0 DFLOP td=1n
A[53] d[53] 0 clk 0 0 0 d[54] 0 DFLOP td=1n
A[54] d[54] 0 clk 0 0 0 d[55] 0 DFLOP td=1n
A[55] d[55] 0 clk 0 0 0 d[56] 0 DFLOP td=1n
A[56] d[56] 0 clk 0 0 0 d[57] 0 DFLOP td=1n
A[57] d[57] 0 clk 0 0 0 d[58] 0 DFLOP td=1n
A[58] d[58] 0 clk 0 0 0 d[59] 0 DFLOP td=1n
A[59] d[59] 0 clk 0 0 0 d[60] 0 DFLOP td=1n
A[60] d[60] 0 clk 0 0 0 d[61] 0 DFLOP td=1n
A[61] d[61] 0 clk 0 0 0 d[62] 0 DFLOP td=1n
A[62] d[62] 0 clk 0 0 0 d[63] 0 DFLOP td=1n
A[63] d[63] 0 clk 0 0 0 d[64] 0 DFLOP td=1n
V2 clk 0 PULSE(0 0.5 250n 1n 1n 500n 1000n)
V1 d[0] 0 PULSE(0 0.75 10n 1n 1n 1000n 3000n)
.tran 100u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 944 680
WIRE -96 -80 -144 -80
WIRE -80 -80 -96 -80
WIRE -144 -48 -144 -80
WIRE 112 32 48 32
WIRE 368 32 272 32
WIRE 112 80 48 80
IOPIN 48 32 In
IOPIN 368 32 Out
SYMBOL voltage -144 -64 R0
WINDOW 3 4 -66 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 0.75 10n 1n 1n 1000n 3000n)
SYMATTR InstName V1
SYMBOL Digital\\dflop 192 -16 R0
WINDOW 3 8 12 Left 0
SYMATTR Value td=1n
SYMATTR InstName A[0:63]
SYMBOL voltage -64 112 R0
WINDOW 3 -23 156 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 0.5 250n 1n 1n 500n 1000n)
SYMATTR InstName V2
FLAG 48 32 d[0:63]
FLAG 48 80 clk
FLAG -144 32 0
FLAG -64 208 0
FLAG -64 128 clk
FLAG -96 -80 d[0]
FLAG 368 32 d[1:64]
TEXT -248 -176 Left 0 !.tran 100u