* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4284.asc
* Generated by LTspice 26.0.1 for Windows.
V1 0 VEE PWL(0 0 10u 48)
M1 OUT N010 N012 N012 PSMN7R6100BSE
RS1 N012 VEE 5m
RD N009 OUT 100K
RDT N008 OUT 392K
RDB N008 VEE 10K
R6 N001 PGIO2 100K
R7 N001 PGIO1 100K
RRT N002 0 392K
RRB VEE N002 10K
RIN 0 N001 4K
RUV3 0 N004 200K
RUV1 N004 VEE 10K
CTMR TMR VEE 2.2n
CL 0 OUT 2000
M2A OUT N014 N015 N015 IPT020N10N3
RM1 GATE1 N010 10
RG1 GATE1 P001 1k
CG1 P001 VEE 10n
RM2B GATE2 N016 10
RM2A GATE2 N014 10
CUV N004 VEE 10n
CR N007 VEE 470n
ROV2 0 N006 523K
ROV1 N006 VEE 10K
COV N006 VEE 10n
M2B OUT N016 N015 N015 IPT020N10N3
RS2 N015 VEE 0.33m
CG2 N013 VEE 220n
RG2 GATE2 N013 150
ROT N003 N005 1.4k
ROB N005 VEE 10k
S1 0 OUT N011 0 SSHORT
V2 N011 0 PWL(0 0 1.2 0 +10n 0 +20m 0 +10n 0)
XU1 VEE N004 N004 N006 N003 N005 MP_01 MP_02 MP_03 MP_04 VEE VEE MP_05 VEE N012 MP_06 N015 GATE1 GATE2 N009 N008 N002 N007 TMR MP_07 MP_08 MP_09 MP_10 PGIO1 PGIO2 VEE INTVCC MP_11 MP_12 MP_13 MP_14 MP_15 MP_16 MP_17 INTVCC MP_18 INTVCC N001 N001 LTC4284 A6=1 A5=0 A4=1 A3=1 A2=0 B7=0 B6=0 B5=0 B4=0 B3=0 B2=0 B1=1 B0=1 D7=0 D6=0 D5=1 D4=1 D3=0 D2=1 D1=0 D0=0 E7=1 E6=1 E5=0 E4=1 E3=0 E2=0 E1=0 F7=0 ;pnba _EN)UVL)UVH)OV)Vref)Voutth)))))Vee)Sense2-))Sense1-)Sense1+))Sense2+)Gate1)Gate2)Drain)Drns)Rtns)Ramp)Tmr)))))PGIO1)PGIO2)PGIO3)PGIO4))))))))Mode))IntVcc)Vin)Vz
CVCC VEE INTVCC 1
CIN N001 VEE .1
B1 0 OUT I=if(V(PGIO1,Vee)<.5 & time > .1,MIN(Power/MAX(V(0,OUT),12),Imax),0)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1.6
.model SSHORT SW(Ron=10m Roff=1k vt=.5 vh=-200m)
* UV ON = -43V\nUV OFF = -38.5V\nOV OFF = -75V
* Ratio 1/40.2
* 1/40.2
* VOUT LOW = -36.1V
* 2500W Constant Power Switched Load
.param Power=2500
.param VminLoad=12
.param Imax=120
* LOW STRESS STAGED START MODE
* Non Default Bits:\n(set as params on symbol)\n \nILIM = 0011b (D7-D4)\nFB = 10b (D3,D2)\nFTBD_DL = 01b (E5,4)
* LINE REGULATED\nINPUT STEPS LIMITED TO <4V
* (USE PARALLEL MODE OR HIGH STRESS STAGED START MODE\nTO RIDE THROUGH LARGE INPUT STEPS)
* Note: All bits must be set to 0 or 1\nUndefined behaivor for other values\n \nSee datasheet for further description.\n \nBit Name Default\n Description\n \nCONTROL_1 (0x0A)\n \nA6 DVDT 1\n 1->Enable DVDT startup\nA5 THERM_TMR 0\n 1->Turns off 2 uA TMR pulldown\nA4 FET_BAD_TURN_OFF 1\n 1-> Turn MOSFET Off after FET_BAD\nA3 PWRG_RESET_CNTRL 1\n 1-> Vout Low resets Power Good\n 0-> MOSFET Off resets Power Good\nA2 PGIO2_ACLB 0\n 1-> PGIO2 configured as inverted ACL\n 0-> PGIO2 configured as inverted second Power Good\n \nCONTROL_2 (0x0B)\n \nB7 EXT_FAULT_RETRY 0\n 1->Enables Auto Retry after EXT_FAULT\nB6 PGI_RETRY 0\n 1->Enables Auto Retry after PGI_FAULT\nB5-4 FET_BAD_RETRY 00 \n Configures FET_BAD Retry\n B5,B4 Number of Retries\n 00 0 (Latch-Off)\n 01 1\n 10 7\n 11 infinite\n \nB3-2 OC_RETRY 00\n Configures OC (Over Current) Retry\n B3,B2 Number of Retries\n 00 0 (Latch-Off)\n 01 1\n 10 7\n 11 infinite\n \nB1 UV_RETRY 1\n 1-> Enables Auto Retry after UV_FAULT\nB0 OV_RETRY 1\n 1-> Enables Auto Retry after OV_FAULT
* CONFIG_1 (0x0D) \n \nD7-4 ILIM 0000\n Configures Current Limit Voltage (VILIM)\n (VILIM(FAST) = 2*VILIM)\n D7,D6,D5,D4 VILIM\n 0000 15m 1000 23m\n 0001 16m 1001 24m\n 0010 17m 1010 25m\n 0011 18m 1011 26m\n 0100 19m 1100 27m\n 0101 20m 1101 28m\n 0110 21m 1110 29m\n 0111 22m 1111 30m\n \nD3-2 FB 00\n Configures Current Limit Foldback\n D3,D2 Foldback Factor\n 00 100% (no foldback)\n 01 50%\n 10 20%\n 11 10%\n \nD1 FB_DIS 0\n 1->Foldback after Startup Disabled\nD0 LPFB 0\n 1->Load Power Foldback after Startup Enabled
* CONFIG_2 (0x0E) \n \nE7-6 VDTH 11\n Configures Drain Voltage threshold\n for starting FET bad timer\n \n E7,E6 VD,FET(TH)\n 00 72 mV\n 01 102 mV\n 10 143 mV\n 11 203 mV\n \nE5-4 FTBD_DL 00\n Configures FET_BAD filtering timer delay\n \n E5,E4 TDL(FETBAD)\n 00 0.256 sec\n 01 0.512 sec\n 10 1.02 sec\n 11 2.05 sec\n \nE3-1 COOLING_DL 000\n Configures Cooling delay before retry\n for OC_FAULT, FET_BAD_FAULT or EXT_FAULT\n \n E3,E2,E1 TDL(RTRY)\n 000 0.512 sec 100 8.19 sec\n 001 1.02 sec 101 16.4 sec\n 010 2.05 sec 110 32.8 sec\n 011 4.1 sec 111 65.5 sec\n \nCONFIG_3 (0x0F) \n \nF7 EXTFLT_TURN_OFF 0\n 1->Turn MOSFET off after External Fault
* Ratio
* LTC4284 Programing Parameters
* Use PWL(0 0 1.2 0 +10n 1 +20m 1 +10n 0) to short the output at 1.2sec
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4284.asy)
.lib LTC4284.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2876 6124
WIRE -16 -1056 -16 -1104
WIRE -304 -928 -1232 -928
WIRE -192 -928 -304 -928
WIRE -16 -928 -16 -976
WIRE -16 -928 -128 -928
WIRE -304 -896 -304 -928
WIRE 592 -816 544 -816
WIRE 736 -816 672 -816
WIRE 944 -816 736 -816
WIRE 1216 -816 1024 -816
WIRE -304 -768 -304 -832
WIRE -208 -768 -304 -768
WIRE -1040 -752 -1040 -800
WIRE -816 -752 -816 -800
WIRE -16 -736 -16 -928
WIRE 80 -736 -16 -736
WIRE 1152 -736 80 -736
WIRE -304 -672 -304 -768
WIRE -208 -672 -208 -768
WIRE -16 -672 -16 -736
WIRE 80 -672 80 -736
WIRE 736 -672 736 -816
WIRE 1328 -640 864 -640
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WIRE -1168 -608 -1232 -608
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WIRE -416 -608 -1040 -608
WIRE 1264 -576 864 -576
WIRE 1328 -560 1328 -640
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WIRE -416 -544 -1040 -544
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WIRE 1152 -512 1152 -736
WIRE 1152 -512 1120 -512
WIRE -816 -480 -816 -672
WIRE -416 -480 -816 -480
WIRE 928 -448 864 -448
WIRE 976 -448 928 -448
WIRE 1152 -448 1152 -512
WIRE 1152 -448 1056 -448
WIRE 1264 -448 1264 -576
WIRE 1328 -448 1328 -480
WIRE 1328 -448 1264 -448
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WIRE -416 -416 -512 -416
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WIRE 1328 -272 1328 -320
WIRE 928 -256 864 -256
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WIRE 704 -192 704 -224
WIRE 320 -176 256 -176
WIRE 400 -176 400 -224
WIRE 400 -176 320 -176
WIRE 928 -176 928 -256
WIRE 1040 -176 1040 -256
WIRE 400 -160 400 -176
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WIRE 256 -144 256 -176
WIRE -1472 -64 -1472 -960
WIRE 1328 -48 1328 -80
WIRE 1392 -32 1376 -32
WIRE 1040 -16 1040 -96
WIRE 1216 -16 1216 -384
WIRE 1216 -16 1040 -16
WIRE 400 0 400 -16
WIRE 256 16 256 -64
WIRE 1408 16 1376 16
WIRE 1408 32 1408 16
WIRE -1472 64 -1472 16
WIRE -752 64 -752 -144
WIRE -752 64 -1472 64
WIRE -304 64 -752 64
WIRE -64 64 -64 -224
WIRE -64 64 -304 64
WIRE -48 64 -64 64
WIRE 48 64 48 -224
WIRE 48 64 32 64
WIRE 240 64 48 64
WIRE 704 64 704 -112
WIRE 704 64 336 64
WIRE 1408 144 1408 112
WIRE 288 160 240 160
WIRE 416 160 368 160
WIRE 480 160 416 160
WIRE 528 160 528 -224
WIRE 528 160 480 160
WIRE 576 160 528 160
WIRE 240 176 240 160
WIRE 416 192 416 160
WIRE 576 208 576 160
WIRE 1104 240 1104 176
WIRE 240 272 240 240
WIRE 1424 272 1424 240
WIRE 416 288 416 272
WIRE -304 336 -304 64
WIRE -176 336 -176 -224
WIRE -176 336 -304 336
WIRE -48 336 -176 336
WIRE 160 336 160 -224
WIRE 160 336 32 336
WIRE 336 336 160 336
WIRE 400 336 336 336
WIRE 704 336 704 64
WIRE 704 336 496 336
WIRE 704 400 704 336
WIRE 832 400 704 400
WIRE 928 400 928 -96
WIRE 928 400 832 400
WIRE 1104 400 1104 304
WIRE 1104 400 928 400
WIRE 1328 400 1328 32
WIRE 1328 400 1104 400
WIRE 1424 400 1424 352
WIRE 1424 400 1328 400
WIRE 1552 400 1424 400
WIRE 576 432 576 288
WIRE 336 480 336 336
WIRE 560 480 336 480
WIRE 832 480 832 400
WIRE 832 480 656 480
FLAG -1472 -960 0
FLAG 544 -816 0
FLAG -16 -1104 0
FLAG -1040 -800 0
FLAG 1104 176 0
FLAG -816 -800 0
FLAG 1328 -80 0
FLAG 1408 144 0
FLAG 1392 -32 0
FLAG -1296 -144 VEE
FLAG 1328 -272 VEE
FLAG 1040 -16 VEE
FLAG 1424 240 0
FLAG 1552 400 OUT
FLAG 928 -320 INTVCC
FLAG 928 -512 PGIO1
FLAG 928 -448 PGIO2
FLAG 240 272 VEE
FLAG 400 0 VEE
FLAG -208 -768 INTVCC
FLAG 320 -176 GATE1
FLAG 480 160 GATE2
FLAG -512 -416 TMR
SYMBOL voltage -1472 -80 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 10u 48)
SYMBOL nmos 336 16 R90
WINDOW 0 -18 -6 VRight 2
WINDOW 3 73 50 VCenter 2
SYMATTR InstName M1
SYMATTR Value PSMN7R6100BSE
SYMBOL res 48 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RS1
SYMATTR Value 5m
SYMBOL res 688 -208 R0
SYMATTR InstName RD
SYMATTR Value 100K
SYMBOL res 912 -192 R0
SYMATTR InstName RDT
SYMATTR Value 392K
SYMBOL res 1024 -192 R0
SYMATTR InstName RDB
SYMATTR Value 10K
SYMBOL res 1072 -464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 100K
SYMBOL res 1136 -528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 100K
SYMBOL res 688 -832 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RRT
SYMATTR Value 392K
SYMBOL res 1040 -832 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RRB
SYMATTR Value 10K
SYMBOL res -32 -1072 R0
SYMATTR InstName RIN
SYMATTR Value 4K
SYMBOL res -1056 -768 R0
SYMATTR InstName RUV3
SYMATTR Value 200K
SYMBOL res -1056 -368 R0
SYMATTR InstName RUV1
SYMATTR Value 10K
SYMBOL cap -688 -336 R0
SYMATTR InstName CTMR
SYMATTR Value 2.2n
SYMBOL cap 1088 240 R0
WINDOW 123 24 36 Left 2
SYMATTR InstName CL
SYMATTR Value 2000u
SYMBOL nmos 496 288 R90
WINDOW 0 -12 -20 VRight 2
WINDOW 3 78 51 VCenter 2
SYMATTR InstName M2A
SYMATTR Value IPT020N10N3
SYMBOL res 240 -160 R0
SYMATTR InstName RM1
SYMATTR Value 10
SYMBOL res 384 -176 R0
SYMATTR InstName RG1
SYMATTR Value 1k
SYMBOL cap 384 -80 R0
SYMATTR InstName CG1
SYMATTR Value 10n
SYMBOL res 560 192 R0
SYMATTR InstName RM2B
SYMATTR Value 10
SYMBOL res 400 176 R0
SYMATTR InstName RM2A
SYMATTR Value 10
SYMBOL cap -1104 -624 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName CUV
SYMATTR Value 10n
SYMBOL cap -576 -320 R0
SYMATTR InstName CR
SYMATTR Value 470n
SYMBOL res -832 -768 R0
SYMATTR InstName ROV2
SYMATTR Value 523K
SYMBOL res -832 -368 R0
SYMATTR InstName ROV1
SYMATTR Value 10K
SYMBOL cap -928 -352 R0
SYMATTR InstName COV
SYMATTR Value 10n
SYMBOL nmos 656 432 R90
WINDOW 0 -15 -19 VRight 2
WINDOW 3 78 51 VCenter 2
SYMATTR InstName M2B
SYMATTR Value IPT020N10N3
SYMBOL res 48 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RS2
SYMATTR Value 0.33m
SYMBOL cap 224 176 R0
SYMATTR InstName CG2
SYMATTR Value 220n
SYMBOL res 384 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG2
SYMATTR Value 150
SYMBOL res 1312 -576 R0
SYMATTR InstName ROT
SYMATTR Value 1.4k
SYMBOL res 1312 -416 R0
SYMATTR InstName ROB
SYMATTR Value 10k
SYMBOL sw 1328 -64 M0
SYMATTR InstName S1
SYMATTR Value SSHORT
SYMBOL voltage 1408 16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 1.2 0 +10n 0 +20m 0 +10n 0)
SYMBOL LTC4284 224 -448 R0
SYMATTR InstName U1
SYMATTR SpiceLine D7=0 D6=0 D5=1 D4=1 D3=0 D2=1 D1=0 D0=0
SYMATTR SpiceLine2 E7=1 E6=1 E5=0 E4=1 E3=0 E2=0 E1=0 F7=0
SYMBOL cap -320 -896 R0
SYMATTR InstName CVCC
SYMATTR Value 1u
SYMBOL cap -128 -944 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName CIN
SYMATTR Value .1u
SYMBOL bi 1424 272 R0
SYMATTR InstName B1
SYMATTR Value I=if(V(PGIO1,Vee)<.5 & time > .1,MIN(Power/MAX(V(0,OUT),12),Imax),0)
TEXT 1688 552 Left 2 !.tran 1.6
TEXT 1320 -152 Left 2 !.model SSHORT SW(Ron=10m Roff=1k vt=.5 vh=-200m)
TEXT -688 -776 Left 2 ;UV ON = -43V\nUV OFF = -38.5V\nOV OFF = -75V
TEXT 976 -280 Left 2 ;Ratio 1/40.2
TEXT 752 -848 Left 2 ;1/40.2
TEXT 1392 -560 Left 2 ;VOUT LOW = -36.1V
TEXT 1496 176 Left 4 ;2500W Constant Power Switched Load
TEXT 1504 216 Left 2 !.param Power=2500\n.param VminLoad=12\n.param Imax=120
TEXT -1392 176 Left 3 ;LOW STRESS STAGED START MODE
TEXT -1296 392 Left 3 ;Non Default Bits:\n(set as params on symbol)\n \nILIM = 0011b          (D7-D4)\nFB = 10b                 (D3,D2)\nFTBD_DL = 01b    (E5,4)
TEXT -1280 -64 Left 3 ;LINE REGULATED\nINPUT STEPS LIMITED TO <4V
TEXT -1392 232 Left 3 ;(USE PARALLEL MODE OR HIGH STRESS STAGED START MODE\nTO RIDE THROUGH LARGE INPUT STEPS)
TEXT -1400 704 Left 2 ;Note: All bits must be set to 0 or 1\nUndefined behaivor for other values\n \nSee datasheet for further description.\n \nBit  Name   Default\n      Description\n \nCONTROL_1 (0x0A)\n                                                     \nA6   DVDT 1\n                                                  1->Enable DVDT startup\nA5   THERM_TMR 0\n                                                  1->Turns off 2 uA TMR pulldown\nA4   FET_BAD_TURN_OFF 1\n                                                  1-> Turn MOSFET Off after FET_BAD\nA3   PWRG_RESET_CNTRL 1\n                                                  1-> Vout Low resets Power Good\n                                                  0-> MOSFET Off resets Power Good\nA2   PGIO2_ACLB  0\n                                                  1-> PGIO2 configured as inverted ACL\n                                                  0-> PGIO2 configured as inverted second Power Good\n \nCONTROL_2 (0x0B)\n \nB7   EXT_FAULT_RETRY 0\n                                                  1->Enables Auto Retry after EXT_FAULT\nB6   PGI_RETRY 0\n                                                  1->Enables Auto Retry after PGI_FAULT\nB5-4 FET_BAD_RETRY 00  \n                                                        Configures FET_BAD Retry\n     B5,B4  Number of Retries\n     00     0 (Latch-Off)\n     01     1\n     10     7\n     11     infinite\n \nB3-2 OC_RETRY 00\n                                                       Configures OC (Over Current) Retry\n     B3,B2  Number of Retries\n     00     0 (Latch-Off)\n     01     1\n     10     7\n     11     infinite\n \nB1   UV_RETRY 1\n                                                  1-> Enables Auto Retry after UV_FAULT\nB0   OV_RETRY 1\n                                                  1-> Enables Auto Retry after OV_FAULT
TEXT -392 744 Left 2 ;CONFIG_1 (0x0D) \n \nD7-4 ILIM 0000\n                            Configures Current Limit Voltage (VILIM)\n                         (VILIM(FAST) = 2*VILIM)\n     D7,D6,D5,D4 VILIM\n     0000    15m      1000    23m\n     0001    16m      1001    24m\n     0010    17m      1010    25m\n     0011    18m      1011    26m\n     0100    19m      1100    27m\n     0101    20m      1101    28m\n     0110    21m      1110    29m\n     0111    22m      1111    30m\n \nD3-2 FB  00\n                            Configures Current Limit Foldback\n    D3,D2  Foldback Factor\n    00     100% (no foldback)\n    01     50%\n    10     20%\n    11     10%\n \nD1   FB_DIS 0\n                          1->Foldback after Startup Disabled\nD0   LPFB  0\n                          1->Load Power Foldback after Startup Enabled
TEXT 448 736 Left 2 ;CONFIG_2 (0x0E) \n \nE7-6 VDTH 11\n                              Configures Drain Voltage threshold\n                              for starting FET bad timer\n \n    E7,E6  VD,FET(TH)\n     00     72  mV\n     01     102 mV\n     10     143 mV\n     11     203 mV\n \nE5-4 FTBD_DL 00\n                            Configures FET_BAD filtering timer delay\n \n    E5,E4  TDL(FETBAD)\n     00     0.256 sec\n     01     0.512 sec\n     10     1.02 sec\n     11     2.05 sec\n \nE3-1 COOLING_DL   000\n                            Configures Cooling delay before retry\n                             for OC_FAULT, FET_BAD_FAULT or EXT_FAULT\n \n    E3,E2,E1 TDL(RTRY)\n     000    0.512 sec      100    8.19 sec\n     001    1.02 sec      101    16.4 sec\n     010    2.05 sec      110    32.8 sec\n     011    4.1  sec      111    65.5 sec\n \nCONFIG_3 (0x0F) \n \nF7  EXTFLT_TURN_OFF  0\n                           1->Turn MOSFET off after External Fault
TEXT 760 -880 Left 2 ;Ratio
TEXT -344 624 Left 5 ;LTC4284 Programing Parameters
TEXT 1448 72 Left 2 ;Use PWL(0 0 1.2 0 +10n 1 +20m 1 +10n 0) to short the output at 1.2sec