* Z:\home\khalils\Downloads\files\data\raw_asc\33ac06dfd425_UniversalOpamp.asc
* Generated by LTspice 26.0.1 for Windows.
* A linear single pole opamp with no internal nodes\nor output voltage range limit.\nAvol=DC gain GBW=GBW product Vos=offset voltage\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
* A single pole opamp with one internal node,\nslew rate limit and output voltage and current limit.\nAvol=DC gain GBW=GBW product\nSlew=Slewrate limit ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
* A dominate pole opamp with a delay, slew rate limit,\noutput voltage and current limit, and a programable\nphase margin. Implemented in 7 internal nodes.\nAvol=DC gain GBW=GBW product\nSlew=Slewrate limit ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nphimargin=phase margin\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
* A two pole opamp with two internal nodes,\nslew rate limit and output voltage and current limit\nand a programable phase margin.\nAvol=DC gain GBW=GBW product\nSlew=Slewrate limit ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nphimargin=phase margin\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
* This example schematic is supplied for informational/educational purposes only.
* This demonstrates the use of the symbol UniversalOpamp. You set the SpiceModel to be higher to simulate more aspects of opamp behavior.\nLevel1 is merely a transconductance working into an R||C and doesn't use power from the supplies. Level2 adds slewrate, current and\nvoltage limits. Level3a adds a second pole. Level3b adds a delay to the dominate pole response. Noise is modeled at all levels.
* Library below included based on ModelFile attribute of instance XU1, XU2, XU3, XU4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
XU2 N001 0 +V -V 2 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V3 N001 0 ac 1
XU3 N001 0 +V -V 3b level3b Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -15
XU4 N001 0 +V -V 3a level3a Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
XU1 N001 0 +V -V 1 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.ac oct 10 .1 100Meg
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 1112
WIRE 32 224 32 -176
WIRE 32 400 32 224
WIRE 32 416 32 400
WIRE 32 512 32 496
WIRE 96 -208 80 -208
WIRE 96 -176 32 -176
WIRE 96 192 80 192
WIRE 96 224 32 224
WIRE 128 -224 128 -240
WIRE 128 -144 128 -160
WIRE 128 176 128 160
WIRE 128 256 128 240
WIRE 224 -192 160 -192
WIRE 224 208 160 208
WIRE 960 288 960 -144
WIRE 960 400 32 400
WIRE 960 400 960 288
WIRE 1024 256 1008 256
WIRE 1024 288 960 288
WIRE 1040 -176 1024 -176
WIRE 1040 -144 960 -144
WIRE 1040 448 1040 432
WIRE 1040 544 1040 528
WIRE 1056 240 1056 224
WIRE 1056 320 1056 304
WIRE 1072 -192 1072 -208
WIRE 1072 -112 1072 -128
WIRE 1136 448 1136 432
WIRE 1136 544 1136 528
WIRE 1152 272 1088 272
WIRE 1168 -160 1104 -160
SYMBOL opamps\\UniversalOpamp 128 -192 R0
WINDOW 38 24 27 Left 0
SYMATTR SpiceModel level1
SYMATTR InstName U1
SYMBOL voltage 1040 432 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL opamps\\UniversalOpamp 1072 -160 R0
WINDOW 38 24 27 Left 0
SYMATTR SpiceModel level3a
SYMATTR InstName U4
SYMBOL opamps\\UniversalOpamp 128 208 R0
WINDOW 38 24 27 Left 0
SYMATTR InstName U2
SYMBOL opamps\\UniversalOpamp 1056 272 R0
WINDOW 38 24 27 Left 0
SYMATTR SpiceModel level3b
SYMATTR InstName U3
SYMBOL voltage 32 400 R0
WINDOW 0 25 22 Left 0
WINDOW 3 27 90 Left 0
SYMATTR InstName V3
SYMATTR Value ac 1
SYMBOL voltage 1136 432 R0
SYMATTR InstName V2
SYMATTR Value -15
FLAG 128 -240 +V
FLAG 128 -144 -V
FLAG 80 -208 0
FLAG 1136 544 0
FLAG 1040 544 0
FLAG 1040 432 +V
FLAG 1136 432 -V
FLAG 32 512 0
FLAG 128 160 +V
FLAG 128 256 -V
FLAG 80 192 0
FLAG 1056 224 +V
FLAG 1056 320 -V
FLAG 1008 256 0
FLAG 1072 -208 +V
FLAG 1072 -112 -V
FLAG 1024 -176 0
FLAG 224 -192 1
FLAG 224 208 2
FLAG 1152 272 3b
FLAG 1168 -160 3a
TEXT 152 464 Left 0 !.ac oct 10 .1 100Meg
TEXT 264 -272 Left 0 ;A linear single pole opamp with no internal nodes\nor output voltage range limit.\nAvol=DC gain   GBW=GBW product   Vos=offset voltage\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
TEXT 272 104 Left 0 ;A single pole opamp with one internal node,\nslew rate limit and output voltage and current limit.\nAvol=DC gain  GBW=GBW product\nSlew=Slewrate limit  ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
TEXT 1224 104 Left 0 ;A dominate pole opamp with a delay, slew rate limit,\noutput voltage and current limit, and a programable\nphase margin.  Implemented in 7 internal nodes.\nAvol=DC gain  GBW=GBW product\nSlew=Slewrate limit  ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nphimargin=phase margin\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
TEXT 1224 -296 Left 0 ;A two pole opamp with two internal nodes,\nslew rate limit and output voltage and current limit\nand a programable phase margin.\nAvol=DC gain  GBW=GBW product\nSlew=Slewrate limit  ilimit=current limit\nrail=output stage saturation voltage\nVos=offset voltage\nphimargin=phase margin\nen=equiv. input noise voltage density\nenk=equiv. input noise voltage density corner freq.\nin=equiv. input noise current density\nink=equiv. input noise current density corner freq.\nRin=Input resistance
TEXT 96 536 Left 0 ;This example schematic is supplied for informational/educational purposes only.
TEXT 152 -416 Left 0 ;This demonstrates the use of the symbol UniversalOpamp.  You set the SpiceModel to be higher to simulate more aspects of opamp behavior.\nLevel1 is merely a transconductance working into an R||C and doesn't use power from the supplies.  Level2 adds slewrate, current and\nvoltage limits.  Level3a adds a second pole.  Level3b adds a delay to the dominate pole response.  Noise is modeled at all levels.