Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3685.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N004 OUT 4.7 Rpar=2K
D1 0 N004 MBRS340
C1 OUT 0 22
V1 IN 0 30
R1 OUT N008 316K
R2 N008 0 100K
C2 N004 N006 .47
C3 N002 0 470p
R3 N003 N002 14K
R4 N005 0 40.2K
R5 OUT N007 100K
R6 IN N001 500K
C4 N001 0 .01
Rload OUT 0 1.65
XU1 OUT N006 N004 IN N001 0 N007 N008 N003 N005 0 LT3685 ;pnba BD)BOOST)SW)VIN)RUN/SS)SYNC)PG)FB)VC)RT)GND
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3685.asy)
.lib LT3685.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1236 740
WIRE -352 64 -448 64
WIRE 96 64 -352 64
WIRE -448 80 -448 64
WIRE -352 80 -352 64
WIRE 96 112 96 64
WIRE -64 160 -352 160
WIRE 560 160 256 160
WIRE -448 176 -448 160
WIRE -352 176 -352 160
WIRE -240 240 -256 240
WIRE -160 240 -176 240
WIRE -64 240 -80 240
WIRE 288 240 256 240
WIRE 384 240 288 240
WIRE 448 240 384 240
WIRE 560 240 560 160
WIRE 560 240 528 240
WIRE 656 240 560 240
WIRE 752 240 656 240
WIRE 848 240 752 240
WIRE -352 256 -352 240
WIRE 288 256 288 240
WIRE 384 256 384 240
WIRE 752 256 752 240
WIRE 848 256 848 240
WIRE 560 272 560 240
WIRE -208 320 -256 320
WIRE -64 320 -128 320
WIRE 288 320 256 320
WIRE 384 336 384 320
WIRE 656 336 656 240
WIRE 752 352 752 320
WIRE 848 352 848 336
WIRE -64 400 -96 400
WIRE 560 400 560 352
WIRE 560 400 256 400
WIRE 560 416 560 400
WIRE 32 464 32 448
WIRE 160 464 160 448
WIRE 560 512 560 496
WIRE -96 544 -96 400
WIRE 656 544 656 416
WIRE 656 544 -96 544
FLAG 384 336 0
FLAG 752 352 0
FLAG 560 512 0
FLAG -256 240 0
FLAG -448 176 0
FLAG 160 464 0
FLAG 848 352 0
FLAG -256 320 0
FLAG -352 256 0
FLAG 848 240 OUT
FLAG -448 64 IN
FLAG 32 464 0
SYMBOL ind 432 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rpar=2K
SYMBOL schottky 368 320 M180
WINDOW 0 28 62 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 736 256 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL voltage -448 64 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL res 544 256 R0
SYMATTR InstName R1
SYMATTR Value 316K
SYMBOL res 544 400 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap 272 256 R0
WINDOW 3 30 49 Left 2
SYMATTR Value .47
SYMATTR InstName C2
SYMBOL cap -176 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 470p
SYMBOL res -64 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 14K
SYMBOL res -112 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 40.2K
SYMBOL res 640 320 R0
SYMATTR InstName R5
SYMATTR Value 100K
SYMBOL res -368 64 R0
SYMATTR InstName R6
SYMATTR Value 500K
SYMBOL cap -368 176 R0
SYMATTR InstName C4
SYMATTR Value .01
SYMBOL res 832 240 R0
SYMATTR InstName Rload
SYMATTR Value 1.65
SYMBOL LT3685 96 288 R0
SYMATTR InstName U1
TEXT 312 472 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1194.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1194.asy)
V4 N001 0 {VC}
V3 IN 0 SINE(0 350m 200K)
V2 -V 0 -5
V1 +V 0 5
XU1 IN 0 +V -V OUT 0 N001 N001 LT1194 ;pnba In+)In-)V+)V-)OUT)REF)VOS1)VOS2
.tran 7.5u
.step param VC list -5 -4 -3 -2
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -96 112 -96 96
WIRE -416 144 -432 144
WIRE -256 144 -336 144
WIRE -160 144 -256 144
WIRE -160 176 -208 176
WIRE 16 176 -32 176
WIRE -208 208 -208 176
WIRE -160 208 -208 208
WIRE -208 224 -208 208
WIRE -128 256 -128 240
WIRE -96 256 -96 240
WIRE -96 256 -128 256
WIRE -64 256 -64 240
WIRE -464 288 -464 272
WIRE -336 288 -336 272
WIRE -128 288 -128 256
WIRE -464 384 -464 368
WIRE -336 384 -336 368
WIRE -128 384 -128 368
SYMBOL opamps\\LT1194 -96 176 R0
SYMATTR InstName U1
SYMBOL voltage -128 272 R0
SYMATTR InstName V4
SYMATTR Value {VC}
SYMBOL voltage -464 272 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage -336 272 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -320 144 R90
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
SYMATTR Value SINE(0 350m 200K)
SYMATTR InstName V3
FLAG -336 384 0
FLAG -96 96 +V
FLAG -336 272 +V
FLAG -64 256 -V
FLAG -464 384 0
FLAG -464 272 -V
FLAG -432 144 0
FLAG -208 224 0
FLAG 16 176 OUT
FLAG -256 144 IN
FLAG -128 384 0
TEXT 16 336 Left 2 !.tran 7.5u\n.step param VC list -5 -4 -3 -2
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1369.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Supply Rail Current Sense
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1369.asy)
V1 +V 0 5
I1 N003 0 SINE(.2 .1 1K)
XU1 N003 N001 +V 0 N002 LT1368 ;pnba In+)In-)V+)V-)OUT
R3 N004 0 20K
C1 OUT 0 .1
R2 +V N003 .1
XU2 N004 OUT +V 0 OUT LT1368 ;pnba In+)In-)V+)V-)OUT
MQ1 N004 N002 N001 N001 BSS84
R1 N001 +V 200
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1388 720
WIRE 32 16 -112 16
WIRE 80 16 32 16
WIRE 176 16 160 16
WIRE 384 16 176 16
WIRE -112 32 -112 16
WIRE 32 32 32 16
WIRE 224 80 224 64
WIRE 176 96 176 16
WIRE 192 96 176 96
WIRE 384 96 384 16
WIRE 608 96 496 96
WIRE 336 112 256 112
WIRE -112 128 -112 112
WIRE 32 128 32 112
WIRE 192 128 32 128
WIRE 32 144 32 128
WIRE 224 160 224 144
WIRE 544 160 544 144
WIRE 496 176 496 96
WIRE 512 176 496 176
WIRE 608 192 608 96
WIRE 608 192 576 192
WIRE 672 192 608 192
WIRE 720 192 672 192
WIRE 384 208 384 192
WIRE 512 208 384 208
WIRE 672 208 672 192
WIRE 384 224 384 208
WIRE 32 240 32 224
WIRE 544 240 544 224
WIRE 672 288 672 272
WIRE 384 320 384 304
SYMBOL opamps\\LT1369 544 128 R0
SYMATTR InstName U2
SYMBOL voltage -112 16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 176 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL res 16 16 R0
SYMATTR InstName R2
SYMATTR Value .1
SYMBOL pmos 336 192 M180
WINDOW 0 61 66 Left 2
WINDOW 3 59 31 Left 2
SYMATTR InstName Q1
SYMATTR Value BSS84
SYMBOL cap 656 208 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL current 32 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(.2 .1 1K)
SYMBOL opamps\\LT1369 224 48 R0
SYMATTR InstName U1
SYMBOL res 368 208 R0
SYMATTR InstName R3
SYMATTR Value 20K
FLAG -112 128 0
FLAG 224 64 +V
FLAG 720 192 OUT
FLAG 32 240 0
FLAG 224 160 0
FLAG 32 16 +V
FLAG 384 320 0
FLAG 544 144 +V
FLAG 544 240 0
FLAG 672 288 0
TEXT 464 312 Left 2 !.tran 3m
TEXT 408 -16 Bottom 2 ;Positive Supply Rail Current Sense
* Z:\home\khalils\Downloads\files\data\raw_asc\218af745b589_StageA_BandPassDeliyannisFriendNoPosFB_LT6233.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 IN 422
C1 OUT N001 3.9E-9
R5 OUT N002 5.49E3
C2 N002 N001 3.9E-9
R2 N001 REF 324
XU1 REF N002 OUT V+ V- NC_01 LT6233 ;pnba IN+)IN-)OUT)VCC)VEE)EN_L
* This subcircuit is not simulatable. \nPlease open one of the \n"Filter Design*.asc" schematics to \nsimulate your Filter Wizard design.\n \nR and C values for this subcircuit\nare set in the top level \n"Filter Design*.asc" schematic
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6233.asy)
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4112 860
WIRE 48 -128 -16 -128
WIRE 176 -128 112 -128
WIRE 480 -128 176 -128
WIRE 176 -64 176 -128
WIRE 320 64 320 -32
WIRE 320 112 320 64
WIRE -160 128 -176 128
WIRE -128 128 -160 128
WIRE -16 128 -16 -128
WIRE -16 128 -48 128
WIRE 48 128 -16 128
WIRE 176 128 176 16
WIRE 176 128 112 128
WIRE 288 128 288 112
WIRE 288 128 176 128
WIRE 304 128 288 128
WIRE 480 128 480 -128
WIRE 544 128 480 128
WIRE 576 128 544 128
WIRE 432 144 352 144
WIRE 480 144 480 128
WIRE 480 144 432 144
WIRE 288 160 240 160
WIRE 304 160 288 160
WIRE -16 176 -16 128
WIRE 288 176 288 160
WIRE 320 224 320 176
WIRE -16 288 -16 256
WIRE 240 288 240 160
WIRE 320 304 320 224
FLAG 320 -32 V+
FLAG 320 304 V-
FLAG 544 128 OUT
FLAG -160 128 IN
FLAG 240 288 REF
FLAG -16 288 REF
SYMBOL res -32 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 422
SYMBOL cap 112 -144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 3.9E-9
SYMBOL res 160 -80 R0
SYMATTR InstName R5
SYMATTR Value 5.49E3
SYMBOL cap 112 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 3.9E-9
SYMBOL res -32 160 R0
SYMATTR InstName R2
SYMATTR Value 324
SYMBOL Opamps\LT6233 320 144 R0
SYMATTR InstName U1
TEXT -176 504 Left 4 ;This subcircuit is not simulatable.  \nPlease open one of the \n"Filter Design*.asc" schematics to \nsimulate your Filter Wizard design.\n \nR and C values for this subcircuit\nare set in the top level \n"Filter Design*.asc" schematic
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1187.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1187.asy)
XU1 N001 0 +V -V N002 0 N003 NC_01 LT1187 ;pnba In+)In-)V+)V-)OUT)REF)FB)_SHDN
V1 +V 0 5
V3 N001 0 SINE(0 10m 100K)
V2 -V 0 -5
R2 N003 0 1K
R1 N002 N003 1K
.tran 1m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -288 96 -544 96
WIRE -544 112 -544 96
WIRE -112 112 -112 96
WIRE -288 128 -288 96
WIRE -176 128 -288 128
WIRE -176 160 -288 160
WIRE 0 176 -48 176
WIRE -176 192 -224 192
WIRE -544 208 -544 192
WIRE -288 208 -288 160
WIRE -288 208 -544 208
WIRE -768 224 -768 208
WIRE -640 224 -640 208
WIRE -544 224 -544 208
WIRE -176 224 -208 224
WIRE -112 256 -112 240
WIRE -768 320 -768 304
WIRE -640 320 -640 304
WIRE -304 336 -320 336
WIRE -208 336 -208 224
WIRE -208 336 -224 336
WIRE -144 336 -208 336
WIRE 0 336 0 176
WIRE 0 336 -64 336
SYMBOL voltage -768 208 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage -544 96 R0
SYMATTR Value SINE(0 10m 100K)
SYMATTR InstName V3
SYMBOL res -48 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -640 208 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res -208 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL opamps\\LT1187 -112 176 R0
SYMATTR InstName U1
FLAG -640 320 0
FLAG -112 96 +V
FLAG -640 208 +V
FLAG -112 256 -V
FLAG -768 320 0
FLAG -768 208 -V
FLAG -320 336 0
FLAG -544 224 0
FLAG -224 192 0
TEXT -56 416 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\35d6eef04a45_rectification-v3.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 SINE(0 10 50 0 0 0 0)
R1 N003 0 20
L1 N002 N003 10m
C1 N003 0 0.01
D1 N001 N002 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -16 64 -240 64
WIRE 144 64 48 64
WIRE 336 64 224 64
WIRE 496 64 336 64
WIRE 336 128 336 64
WIRE -240 144 -240 64
WIRE 496 144 496 64
WIRE -240 336 -240 224
WIRE 336 336 336 208
WIRE 336 336 -240 336
WIRE 496 336 496 208
WIRE 496 336 336 336
WIRE -240 368 -240 336
SYMBOL ind 128 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10m
SYMBOL cap 480 144 R0
SYMATTR InstName C1
SYMATTR Value 0.01
SYMBOL diode -16 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL res 320 112 R0
SYMATTR InstName R1
SYMATTR Value 20
SYMBOL voltage -240 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 50 0 0 0 0)
FLAG -240 368 0
TEXT -272 392 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4451.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4451.asy)
V1 IN 0 24
XU1 0 IN OUT NC_01 IN 0 LTC4451 ;pnba Vcc)IN)OUT)STATUS)SHDN#)GND
C1 IN 0 0.1
R1 OUT 0 3.48
C2 OUT 0 22
.tran 1m startup
.lib LTC4451.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -192 96 -208 96
WIRE -96 96 -192 96
WIRE -32 96 -96 96
WIRE 16 96 -32 96
WIRE 608 96 480 96
WIRE 688 96 608 96
WIRE 720 96 688 96
WIRE -208 144 -208 96
WIRE 608 144 608 96
WIRE 720 144 720 96
WIRE -96 160 -96 96
WIRE -32 176 -32 96
WIRE 16 176 -32 176
WIRE 608 256 608 208
WIRE 720 256 720 224
WIRE -208 272 -208 224
WIRE -96 272 -96 224
WIRE 144 304 144 272
WIRE 352 304 352 272
WIRE 352 304 144 304
WIRE 352 336 352 304
SYMBOL voltage -208 128 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL LTC4451 240 160 R0
SYMATTR InstName U1
SYMBOL cap -112 160 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL cap 592 144 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL res 704 128 R0
SYMATTR InstName R1
SYMATTR Value 3.48
FLAG 352 336 0
FLAG -96 272 0
FLAG 608 256 0
FLAG -208 272 0
FLAG -192 96 IN
FLAG 688 96 OUT
FLAG 720 256 0
TEXT -216 360 Left 2 !.tran 1m startup
* Z:\tmp\asc_dec_bjh7r6w2\135b863a5f2a_Fig20_42_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Vo N001 0 0
M3 N002 N003 N006 0 N_50n l=100n w=2.5u
M2 N005 N002 0 0 N_50n l=100n w=2.5u
M4 N001 N004 N005 0 N_50n l=100n w=2.5u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1820 680
WIRE 864 -160 864 -224
WIRE 864 -144 864 -160
WIRE 864 32 864 -48
WIRE 864 48 864 32
WIRE 928 -160 864 -160
WIRE 928 128 928 -160
WIRE 1104 -240 1088 -240
WIRE 1104 32 864 32
WIRE 1152 -64 912 -64
WIRE 1392 -240 1376 -240
WIRE 1440 -64 1440 -224
WIRE 1440 64 1440 32
WIRE 1536 -64 1440 -64
WIRE 1536 128 928 128
WIRE 1584 -144 1584 -192
WIRE 1584 16 1488 16
WIRE 1584 16 1584 -48
WIRE 1584 48 1584 16
WIRE 1584 176 1584 144
WIRE 1760 -192 1584 -192
WIRE 1760 -160 1760 -192
WIRE 1760 -64 1760 -80
SYMBOL voltage 1760 -176 R0
SYMATTR InstName Vo
SYMATTR Value 0
SYMBOL nmos4 912 -144 M0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=100n w=2.5u
SYMATTR InstName M3
SYMATTR Value N_50n
SYMBOL nmos4 1536 48 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=100n w=2.5u
SYMATTR InstName M2
SYMATTR Value N_50n
SYMBOL nmos4 1536 -144 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=100n w=2.5u
SYMATTR InstName M4
SYMATTR Value N_50n
FLAG 1584 96 0
FLAG 1584 176 0
FLAG 1760 -64 0
FLAG 864 -96 0
FLAG 1584 -96 0
FLAG 864 -320 VDD
FLAG 816 -240 Vbiasp
FLAG 1088 -240 Vbiasp
FLAG 864 -272 VDD
FLAG 1440 -320 VDD
FLAG 1376 -240 Vbiasp
FLAG 1440 -272 VDD
FLAG 1440 -16 0
FLAG 1440 64 0
* Z:\tmp\asc_dec_bjh7r6w2\17b6a739896a_the_circuit_finale_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N009 N010 {r}
Vgs N004 0 PULSE(0 0.1 0 0.5m 0.5m 0 1m)
XM1 N002 N006 N009 2n7000 ;pnba D)G)S
XMcasc output N001 N002 2n7000 ;pnba D)G)S
Rd2 Vdd N011 15.5k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1940 1232
WIRE 1392 -112 1392 -144
WIRE 1392 0 1392 -32
WIRE 1392 32 1392 0
WIRE 1344 112 1248 112
WIRE 1248 208 1248 192
WIRE 1392 352 1392 128
WIRE 1392 352 928 352
WIRE 704 416 704 304
WIRE 928 416 928 352
WIRE 528 496 256 496
WIRE 656 496 608 496
WIRE 1088 496 976 496
WIRE 1184 496 1168 496
WIRE 704 560 704 512
WIRE 928 576 928 512
WIRE 528 624 528 592
WIRE 704 704 704 640
WIRE 928 704 928 656
WIRE 928 704 704 704
WIRE 528 736 528 704
WIRE 592 736 528 736
WIRE 528 752 528 736
WIRE 704 752 704 704
WIRE 592 832 592 736
WIRE 256 1104 256 496
WIRE 256 1216 256 1184
SYMBOL res 912 560 R0
SYMATTR InstName R2
SYMATTR Value {r}
SYMBOL voltage 256 1088 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vgs
SYMATTR Value PULSE(0 0.1 0 0.5m 0.5m 0 1m)
SYMBOL nmos 976 416 M0
SYMATTR InstName M1
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL nmos 1344 32 R0
SYMATTR InstName Mcasc
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL res 512 608 R0
SYMATTR InstName Rd2
SYMATTR Value 15.5k
FLAG 256 1216 0
FLAG 1392 -144 Vdd
FLAG 1248 208 0
FLAG 528 592 Vdd
FLAG 1392 0 output
* Z:\home\khalils\Downloads\files\data\raw_asc\20179abfe57b_Ex3.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N002 Vout 1p
M1 N001 N002 Vout 0 nch l=0.18u w=10u
I1 Vout 0 1m
Vin N002 0 1 AC 1 0
VDD N001 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib 'C:\Program Files\LTC\LTspiceXVII\lib\cmp\log018.l' TT
.op
.ac dec 10 0.9k 1.1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 64 240 64
WIRE 240 112 240 64
WIRE 336 160 240 160
WIRE 160 192 48 192
WIRE 192 192 160 192
WIRE 240 224 240 208
WIRE 256 224 240 224
WIRE 48 240 48 192
WIRE 240 256 240 224
WIRE 240 256 160 256
WIRE 448 256 448 64
WIRE 48 400 48 320
WIRE 240 400 240 336
WIRE 240 400 48 400
WIRE 272 400 240 400
WIRE 336 400 336 160
WIRE 336 400 272 400
WIRE 448 400 448 336
WIRE 448 400 336 400
WIRE 272 416 272 400
IOPIN 256 224 Out
SYMBOL current 240 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 1m
SYMBOL voltage 48 224 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1 0
SYMATTR InstName Vin
SYMATTR Value 1
SYMBOL voltage 448 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.8
SYMBOL nmos4 192 112 R0
SYMATTR InstName M1
SYMATTR Value nch
SYMATTR Value2 l=0.18u w=10u
SYMBOL cap 144 192 R0
SYMATTR InstName C1
SYMATTR Value 1p
FLAG 272 416 0
FLAG 256 224 Vout
TEXT 40 456 Left 2 !.lib 'C:\\Program Files\\LTC\\LTspiceXVII\\lib\\cmp\\log018.l' TT
TEXT 40 488 Left 2 !.op
TEXT 40 528 Left 2 !.ac dec 10 0.9k 1.1k
* Z:\home\khalils\Downloads\files\data\raw_asc\c6f172b45764_Assignment_3a__v_.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Half Wave Rectifier Circuit (with 10microF Capacitor) (Ideal)
R1 N002 0 1000
V1 N001 0 SINE(0 311 50) Rser=0.001
D1 N001 N002 1N4148
C1 N002 0 0.00001
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 64 80 64
WIRE 352 64 256 64
WIRE 464 64 352 64
WIRE 80 112 80 64
WIRE 352 112 352 64
WIRE 464 128 464 64
WIRE 80 240 80 192
WIRE 176 240 80 240
WIRE 352 240 352 192
WIRE 352 240 176 240
WIRE 464 240 464 192
WIRE 464 240 352 240
WIRE 176 272 176 240
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
SYMBOL diode 192 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL cap 448 128 R0
SYMATTR InstName C1
SYMATTR Value 0.00001
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
FLAG 176 272 0
TEXT 16 272 Left 2 !.tran 0.05
TEXT 264 8 Center 2 ;Positive Half Wave Rectifier Circuit (with 10microF Capacitor) (Ideal)
* Z:\home\khalils\Downloads\files\data\raw_asc\AD820.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD820.asy)
V2 -V 0 -15
XU1 IN N001 +V -V OUT AD820 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10K
R2 OUT N001 10K
V1 +V 0 15
Vin IN 0 SINE(0 1 10K)
.tran 1m
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 704 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 432 -976 432 -992
SYMBOL AD820 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 704 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 256 -1056 0
TEXT 688 -1000 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\3ebc97d4b157_current.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N002 0 12V
XU1 N003 N001 N002 0 OUT LT1001 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10k
R2 OUT N001 100k
R3 N003 IN 10k
R4 0 N003 100k
R5 OUT N004 1k
R6 N004 0 1k
R7 0 IN 1R
I1 0 IN PULSE(0 1 0 10)
.tran 0 10 0 .01
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1001.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 964 680
WIRE -96 16 -160 16
WIRE -32 16 -96 16
WIRE 352 48 304 48
WIRE 480 48 432 48
WIRE -96 96 -96 16
WIRE 528 96 384 96
WIRE -32 112 -32 16
WIRE 160 112 -32 112
WIRE 304 112 304 48
WIRE 304 112 240 112
WIRE -160 128 -160 16
WIRE 384 128 384 96
WIRE -32 144 -32 112
WIRE 304 144 304 112
WIRE 352 144 304 144
WIRE 480 160 480 48
WIRE 480 160 416 160
WIRE 608 160 480 160
WIRE 640 160 608 160
WIRE 352 176 304 176
WIRE 640 192 640 160
WIRE -32 240 -32 224
WIRE -32 256 -32 240
WIRE 160 256 -32 256
WIRE 304 256 304 176
WIRE 304 256 240 256
WIRE 304 272 304 256
WIRE -160 304 -160 208
WIRE -32 304 -32 256
WIRE -32 304 -160 304
WIRE 528 304 528 96
WIRE 640 304 640 272
WIRE 384 416 384 192
WIRE 416 416 384 416
WIRE 528 416 528 384
WIRE 528 416 416 416
WIRE 304 432 304 352
WIRE 416 432 416 416
WIRE 640 432 640 384
FLAG -96 96 0
FLAG 416 432 0
FLAG 608 160 OUT
FLAG 304 432 0
FLAG 640 432 0
FLAG -32 240 IN
SYMBOL voltage 528 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12V
SYMBOL Opamps\\LT1001 384 96 R0
SYMATTR InstName U1
SYMBOL res 256 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -48 59 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 448 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL res 256 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 320 368 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL res 624 176 R0
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL res 624 288 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res -48 128 R0
SYMATTR InstName R7
SYMATTR Value 1R
SYMBOL current -160 128 R0
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value PULSE(0 1 0 10)
TEXT -184 328 Left 2 !.tran 0 10 0 .01
* Z:\home\khalils\Downloads\files\data\raw_asc\e075b24d89db_ts14.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N003 0 1
V1 N001 0 SINE(0 1 1 0 0 0 1000) AC 1 0 Rser=1
L2 N002 N003 1
C1 N002 0 2
L1 N001 N002 1
.net I(R1) V1
.ac dec 1000 0.001 1000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 960 680
WIRE 336 32 80 32
WIRE 496 32 416 32
WIRE 608 32 496 32
WIRE 784 32 688 32
WIRE 496 80 496 32
WIRE 784 96 784 32
WIRE 80 112 80 32
WIRE 80 304 80 192
WIRE 496 304 496 144
WIRE 496 304 80 304
WIRE 784 304 784 176
WIRE 784 304 496 304
WIRE 496 320 496 304
SYMBOL ind 320 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL cap 480 80 R0
SYMATTR InstName C1
SYMATTR Value 2
SYMBOL ind 592 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 1
SYMBOL voltage 80 96 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 24 180 Left 2
SYMATTR Value SINE(0 1 1 0 0 0 1000)
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMBOL res 768 80 R0
SYMATTR InstName R1
SYMATTR Value 1
FLAG 496 320 0
TEXT 72 424 Left 2 !.net I(R1) V1
TEXT 64 448 Left 2 !.ac dec 1000 0.001 1000