* Z:\home\khalils\Downloads\files\data\raw_asc\6718d64aa74c_Fig18_18.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Vout
Vinp Vinp 0 500m
VDD VDD 0 1
M3 N001 N001 VDD VDD P_50n l=50n w=1u
M6 N003 N001 0 0 N_50n l=50n w=500n
M5 Vout N002 VDD VDD P_50n l=50n w=1u
Vinm Vinm 0 500m
M1 N001 Vinm N003 0 N_50n l=50n w=500n
M7 Vout N002 0 0 N_50n l=50n w=500n
M4 N002 N001 VDD VDD P_50n l=50n w=1u
M2 N002 Vinp N003 0 N_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vinp 0 1 1m Vinm 0 1 200m
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1496 680
WIRE 1184 -560 1184 -608
WIRE 224 -544 224 -560
WIRE 576 -544 576 -592
WIRE 928 -544 928 -592
WIRE 224 -528 224 -544
WIRE 688 -528 624 -528
WIRE 880 -528 688 -528
WIRE 576 -432 576 -448
WIRE 688 -432 688 -528
WIRE 688 -432 576 -432
WIRE 928 -432 928 -448
WIRE 1136 -432 1136 -544
WIRE 1136 -432 928 -432
WIRE 1184 -432 1184 -464
WIRE 1280 -432 1184 -432
WIRE 224 -416 224 -448
WIRE 576 -416 576 -432
WIRE 928 -416 928 -432
WIRE 304 -400 304 -416
WIRE 1184 -400 1184 -432
WIRE 1136 -320 1136 -432
WIRE 304 -304 304 -320
WIRE 576 -288 576 -320
WIRE 752 -288 576 -288
WIRE 928 -288 928 -320
WIRE 928 -288 752 -288
WIRE 240 -272 240 -288
WIRE 752 -272 752 -288
WIRE 1184 -256 1184 -304
WIRE 688 -192 688 -432
WIRE 704 -192 688 -192
WIRE 240 -176 240 -192
WIRE 752 -144 752 -176
SYMBOL nmos4 976 -416 M0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M2
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 880 -448 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 224 -544 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL nmos4 528 -416 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 304 -416 R0
WINDOW 0 25 19 Left 2
WINDOW 3 27 91 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vinm
SYMATTR Value 500m
SYMBOL voltage 240 -288 R0
WINDOW 0 34 41 Left 2
WINDOW 3 31 90 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vinp
SYMATTR Value 500m
SYMBOL nmos4 704 -272 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M6
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 624 -448 R180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 1136 -464 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 1136 -400 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M7
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
FLAG 240 -176 0
FLAG 240 -288 Vinp
FLAG 576 -368 0
FLAG 224 -416 0
FLAG 224 -544 VDD
FLAG 576 -496 VDD
FLAG 752 -144 0
FLAG 576 -592 VDD
FLAG 928 -496 VDD
FLAG 928 -368 0
FLAG 928 -592 VDD
FLAG 304 -304 0
FLAG 304 -416 Vinm
FLAG 752 -224 0
FLAG 528 -336 Vinm
FLAG 976 -336 Vinp
FLAG 1184 -512 VDD
FLAG 1184 -608 VDD
FLAG 1184 -352 0
FLAG 1184 -256 0
FLAG 1280 -432 Vout
TEXT 320 -144 Left 2 !.dc Vinp 0  1  1m  Vinm 0 1  200m
TEXT 320 -120 Left 2 !.include cmosedu_models.txt
TEXT 240 -616 Left 2 ;Plot Vout