* Z:\home\khalils\Downloads\files\data\raw_asc\f0bac87d316d_crow_22nm_wl_model.asc
* Generated by LTspice 26.0.1 for Windows.
* Bitline to array0
* Bitline to array1
* Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
* Word line in array 0
* Word line in array 1
* .step param X 0.0v 1.5v 0.1v
* Word line in array 1
* DRAM Circuit Parameters
* ohm
* Bitline Resistance
* Cell Array
* Sense Amp.
* Voltage
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Wordline Activation
* 1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
* Technology Scaling
* Wordline Parasitics
* Write Logic
* write_driver_inv
* write_driver
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} {wl0_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M22 N002 write1 VDD VDD PMOS l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
M13 N001 ra2 mb2 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
R1 N001 bitline0 {mc(bitline_R, process_var)}
cell_cap_3 mb2 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell2_charge}
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
M12 N001 ra1 mb1 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
Vwrite0 write0 0 PULSE(0 {wr0_voltage} 5n) Rser=100 Cpar=1fF
cell_cap_5 mb5 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell4_charge}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act}) Rser=100 Cpar=1fF
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
M20 bitline1 CSEL N002 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
Vra7 ra7 0 PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source1 PV 0 {plate_voltage}
M16 N001 ra6 mb6 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M24 N003 write0 VDD VDD PMOS l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
M14 N001 ra4 mb4 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
CBL_cap_1 N004 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
M15 N001 ra5 mb5 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_8 mb8 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell7_charge}
M8 N004 ra3 mb3 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
R2 bitline1 N004 {mc(bitline_R, process_var)}
Vra1 ra1 0 PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Vra5 ra5 0 PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act}) Rser=100 Cpar=1fF
Vcsel CSEL 0 PULSE(0 {core_voltage*2} {20n + csel_act}) Rser=100 Cpar=1fF
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
Vra4 ra4 0 PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
Vra6 ra6 0 PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
cell_cap_7 mb7 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell6_charge}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M21 N002 write1 0 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
VDD_source VDD 0 {core_voltage}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
cell_cap_4 mb4 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell3_charge}
M23 N003 write0 0 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
M7 N001 ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vra8 ra8 0 PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
cell_cap_1 mb1 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell1_charge}
Vra3 ra2 0 PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
cell_cap_6 mb6 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell5_charge}
M17 N001 ra7 mb7 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
VDD_source2 VDDby2 0 {core_voltage/2}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M19 bitline0 CSEL N003 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
Vwrite1 write1 0 PULSE(0 {wr1_voltage} 5n) Rser=100 Cpar=1fF
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
M18 N001 ra8 mb8 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include ../DRAM_models/transistor_model.pm
.tran 220ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={255nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={255nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=1024
.param core_voltage=0.95V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cell0_charge_state
.param cell1_charge=core_voltage*other_cells_charge_state
.param cell2_charge=core_voltage*other_cells_charge_state
.param cell3_charge=core_voltage*other_cells_charge_state
.param cell4_charge=core_voltage*other_cells_charge_state
.param cell5_charge=core_voltage*other_cells_charge_state
.param cell6_charge=core_voltage*other_cells_charge_state
.param cell7_charge=core_voltage*other_cells_charge_state
.param cell0_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param wl1_act=1.0
.param wl2_act=1.0
.param wl3_act=1.0
.param wl4_act=1.0
.param wl5_act=1.0
.param wl6_act=1.0
.param wl7_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=1024
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.param wr0_voltage=0V
.param wr1_voltage=0V
.param other_cells_charge_state=0.8
.param wl0_act_time=20ns
.param other_wls_act_time=20ns
.param SA_nWR_L={70nm*SA_nWR_L_factor}
.param SA_nWR_W={840nm*SA_nWR_W_factor}
.param SA_nWR_L_factor={0.93**tech_node}
.param SA_nWR_W_factor={0.93**tech_node}
.param SA_pWR_L={70nm*SA_pWR_L_factor}
.param SA_pWR_W={840nm*SA_pWR_W_factor}
.param csel_act=400ns
.param SA_pWR_L_factor={0.93**tech_node}
.param SA_pWR_W_factor={0.93**tech_node}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2960
WIRE 768 -4832 464 -4832
WIRE 464 -4800 464 -4832
WIRE 304 -4720 96 -4720
WIRE 416 -4720 304 -4720
WIRE 464 -4576 464 -4704
WIRE 464 -4560 464 -4576
WIRE 464 -4464 464 -4496
WIRE 768 -4400 768 -4832
WIRE 768 -4400 464 -4400
WIRE 464 -4368 464 -4400
WIRE 304 -4288 96 -4288
WIRE 416 -4288 304 -4288
WIRE 464 -4144 464 -4272
WIRE 464 -4128 464 -4144
WIRE 464 -4032 464 -4064
WIRE 768 -3952 768 -4400
WIRE 768 -3952 464 -3952
WIRE 464 -3920 464 -3952
WIRE 304 -3840 96 -3840
WIRE 416 -3840 304 -3840
WIRE 464 -3696 464 -3824
WIRE 464 -3680 464 -3696
WIRE 464 -3584 464 -3616
WIRE 768 -3504 768 -3952
WIRE 768 -3504 464 -3504
WIRE 464 -3472 464 -3504
WIRE 304 -3392 96 -3392
WIRE 416 -3392 304 -3392
WIRE 464 -3248 464 -3376
WIRE 464 -3232 464 -3248
WIRE 464 -3136 464 -3168
WIRE 768 -3008 768 -3504
WIRE 768 -3008 464 -3008
WIRE 464 -2976 464 -3008
WIRE 304 -2896 96 -2896
WIRE 416 -2896 304 -2896
WIRE 464 -2752 464 -2880
WIRE 464 -2736 464 -2752
WIRE 464 -2640 464 -2672
WIRE -800 -2608 -800 -2624
WIRE -1456 -2576 -1456 -2592
WIRE -800 -2512 -800 -2528
WIRE 768 -2496 768 -3008
WIRE 768 -2496 464 -2496
WIRE -1456 -2480 -1456 -2496
WIRE 464 -2464 464 -2496
WIRE 304 -2384 96 -2384
WIRE 416 -2384 304 -2384
WIRE -1456 -2304 -1456 -2320
WIRE -800 -2304 -800 -2320
WIRE 464 -2240 464 -2368
WIRE 464 -2224 464 -2240
WIRE -1456 -2208 -1456 -2224
WIRE -800 -2208 -800 -2224
WIRE 464 -2128 464 -2160
WIRE 768 -1984 768 -2496
WIRE 768 -1984 464 -1984
WIRE -2624 -1952 -2624 -1968
WIRE 464 -1952 464 -1984
WIRE -1456 -1936 -1456 -1952
WIRE -832 -1936 -832 -1952
WIRE 304 -1872 96 -1872
WIRE 416 -1872 304 -1872
WIRE -2624 -1856 -2624 -1872
WIRE -1456 -1840 -1456 -1856
WIRE -832 -1840 -832 -1856
WIRE 464 -1728 464 -1856
WIRE 464 -1712 464 -1728
WIRE -1392 -1648 -1392 -1664
WIRE -832 -1648 -832 -1664
WIRE 464 -1616 464 -1648
WIRE -1392 -1552 -1392 -1568
WIRE -832 -1552 -832 -1568
WIRE 768 -1392 768 -1984
WIRE 768 -1392 624 -1392
WIRE 624 -1360 624 -1392
WIRE 304 -1280 96 -1280
WIRE 576 -1280 304 -1280
WIRE 624 -1232 624 -1264
WIRE 624 -1232 384 -1232
WIRE -608 -1152 -608 -1184
WIRE -240 -1152 -240 -1184
WIRE 384 -1152 384 -1232
WIRE 384 -1136 384 -1152
WIRE -1696 -1120 -1696 -1136
WIRE -1104 -1120 -1104 -1136
WIRE -608 -1040 -608 -1072
WIRE -240 -1040 -240 -1072
WIRE -1696 -1024 -1696 -1040
WIRE -1104 -1024 -1104 -1040
WIRE 384 -976 384 -1072
WIRE 768 -848 768 -1392
WIRE 832 -848 768 -848
WIRE 768 -768 768 -848
WIRE 432 -736 384 -736
WIRE 640 -736 432 -736
WIRE 832 -656 688 -656
WIRE 912 -656 832 -656
WIRE 1040 -656 912 -656
WIRE -1776 -640 -1776 -672
WIRE -1408 -640 -1408 -672
WIRE -800 -624 -800 -656
WIRE -512 -624 -512 -656
WIRE -208 -624 -208 -656
WIRE 832 -624 832 -656
WIRE 1040 -624 1040 -656
WIRE 912 -608 880 -608
WIRE 992 -608 960 -608
WIRE 1808 -576 1760 -576
WIRE -1776 -528 -1776 -560
WIRE -1408 -528 -1408 -560
WIRE 1312 -528 1120 -528
WIRE -800 -512 -800 -544
WIRE -512 -512 -512 -544
WIRE -208 -512 -208 -544
WIRE 768 -512 768 -688
WIRE 832 -512 832 -528
WIRE 832 -512 768 -512
WIRE 912 -512 960 -608
WIRE 912 -512 832 -512
WIRE 960 -512 912 -608
WIRE 1040 -512 1040 -528
WIRE 1040 -512 960 -512
WIRE 1120 -512 1120 -528
WIRE 1120 -512 1040 -512
WIRE 1472 -496 1472 -544
WIRE 1312 -448 1312 -528
WIRE 1392 -448 1312 -448
WIRE 1712 -448 1712 -496
WIRE 1712 -448 1488 -448
WIRE 1808 -448 1808 -576
WIRE 1872 -448 1808 -448
WIRE 768 -416 768 -512
WIRE 912 -416 768 -416
WIRE 1120 -416 1120 -512
WIRE 1120 -416 1008 -416
WIRE 1712 -384 1712 -448
WIRE 640 -368 608 -368
WIRE 880 -368 640 -368
WIRE 928 -368 880 -368
WIRE 1056 -368 928 -368
WIRE 1296 -368 1056 -368
WIRE 880 -352 880 -368
WIRE 1056 -352 1056 -368
WIRE 144 -320 96 -320
WIRE 768 -320 768 -416
WIRE 768 -304 768 -320
WIRE 800 -304 768 -304
WIRE 944 -304 896 -304
WIRE 976 -304 944 -304
WIRE 1120 -304 1120 -416
WIRE 1120 -304 1072 -304
WIRE 1312 -304 1312 -448
WIRE 1808 -304 1808 -448
WIRE 1808 -304 1760 -304
WIRE 1120 -288 1120 -304
WIRE 944 -256 944 -304
WIRE 400 -240 400 -288
WIRE 944 -240 944 -256
WIRE 768 -224 768 -304
WIRE 768 -224 624 -224
WIRE 96 -192 96 -320
WIRE 96 -192 32 -192
WIRE 192 -192 192 -240
WIRE 384 -192 192 -192
WIRE 624 -192 624 -224
WIRE 624 -192 480 -192
WIRE 768 -192 768 -224
WIRE 832 -192 768 -192
WIRE 912 -192 832 -192
WIRE 1040 -192 976 -192
WIRE 1120 -192 1120 -288
WIRE 1120 -192 1040 -192
WIRE 832 -176 832 -192
WIRE 1040 -176 1040 -192
WIRE 1312 -144 1312 -224
WIRE 1360 -144 1312 -144
WIRE 192 -128 192 -192
WIRE 912 -96 976 -192
WIRE 912 -96 880 -96
WIRE 976 -96 912 -192
WIRE 992 -96 976 -96
WIRE 1360 -96 1360 -144
WIRE 96 -48 96 -192
WIRE 144 -48 96 -48
WIRE 832 -48 832 -80
WIRE 832 -48 720 -48
WIRE 960 -48 832 -48
WIRE 1040 -48 1040 -80
WIRE 1040 -48 960 -48
WIRE 672 32 416 32
WIRE 1312 128 1312 -144
WIRE 1312 128 1200 128
WIRE 1200 160 1200 128
WIRE 1088 272 880 272
WIRE 1152 272 1152 240
WIRE 1152 272 1088 272
WIRE 1200 304 1200 256
WIRE 1200 320 1200 304
WIRE 1312 432 1312 128
SYMBOL voltage -1456 -2592 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra7
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL cap 448 -4128 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_7
SYMATTR SpiceLine IC={-plate_voltage + cell6_charge}
SYMBOL pmos4 144 -240 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M24
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL nmos4 416 -1952 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -1456 -1952 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra4
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL cap 816 -848 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL voltage -608 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act})
SYMATTR InstName Vsp
SYMBOL voltage -1408 -656 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {wr1_voltage} 5n)
SYMATTR InstName Vwrite1
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL nmos4 416 -4368 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M17
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -1776 -656 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {wr0_voltage} 5n)
SYMATTR InstName Vwrite0
SYMBOL nmos4 800 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL cap 448 -2224 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_3
SYMATTR SpiceLine IC={-plate_voltage + cell2_charge}
SYMBOL nmos4 976 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL voltage -1104 -1136 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL cap 448 -2736 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_4
SYMATTR SpiceLine IC={-plate_voltage + cell3_charge}
SYMBOL nmos4 1152 160 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL res 1296 -320 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -2624 -1968 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -208 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL voltage -800 -2624 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra8
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 880 -176 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL voltage -832 -1952 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra3
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -1392 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} {wl0_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 416 -4800 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M18
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -240 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act})
SYMATTR InstName Vsn
SYMBOL nmos4 416 -2976 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M14
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 416 -3472 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M15
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 576 -1360 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL res 752 -784 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL pmos4 1760 -496 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M22
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL nmos4 416 -3920 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M16
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1344 -96 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL nmos4 144 -128 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M23
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL nmos4 1008 -368 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL cap 1184 320 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL cap 448 -4560 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_8
SYMATTR SpiceLine IC={-plate_voltage + cell7_charge}
SYMBOL nmos4 480 -240 R90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M19
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL cap 448 -1712 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_1
SYMATTR SpiceLine IC={-plate_voltage + cell1_charge}
SYMBOL pmos4 640 -656 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL voltage -1456 -2320 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra5
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 416 -2464 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M13
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL pmos4 880 -528 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL nmos4 992 -176 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL voltage -512 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL cap 448 -3680 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_6
SYMATTR SpiceLine IC={-plate_voltage + cell5_charge}
SYMBOL nmos4 1760 -384 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M21
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL voltage -1696 -1136 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vcsel
SYMATTR Value PULSE(0 {core_voltage*2} {20n + csel_act})
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMBOL voltage -800 -2320 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra6
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL cap 448 -3232 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_5
SYMATTR SpiceLine IC={-plate_voltage + cell4_charge}
SYMBOL pmos4 992 -528 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL voltage -832 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL cap 368 -1136 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 672 -48 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL nmos4 1392 -496 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M20
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
FLAG -1104 -1024 0
FLAG -1104 -1136 Eq
FLAG 720 0 0
FLAG -608 -1040 0
FLAG -608 -1184 sense_P
FLAG 1040 -128 0
FLAG 832 -128 0
FLAG 960 -416 0
FLAG 848 -304 0
FLAG 1024 -304 0
FLAG 640 -368 Eq
FLAG 944 -256 VDDby2
FLAG 416 32 sense_N
FLAG 720 48 0
FLAG 768 -320 bitline0
FLAG 1120 -288 bitline1
FLAG 624 -1312 0
FLAG 384 -1152 mb0
FLAG 304 -1280 ra0
FLAG 1200 208 0
FLAG 1200 384 0
FLAG 1200 304 mb3
FLAG 1088 272 ra3
FLAG -1392 -1552 0
FLAG -1392 -1664 ra0
FLAG 688 -704 VDD
FLAG 1040 -576 VDD
FLAG 832 -576 VDD
FLAG 688 -752 VDD
FLAG 432 -736 sense_p
FLAG 912 -656 ACT
FLAG 960 -48 NLAT
FLAG -240 -1040 0
FLAG -240 -1184 sense_N
FLAG -832 -1664 ra1
FLAG -832 -1552 0
FLAG 832 -784 0
FLAG 1360 -32 0
FLAG 464 -1904 0
FLAG 464 -1728 mb1
FLAG 304 -1872 ra1
FLAG -2624 -1968 ra3
FLAG -2624 -1856 0
FLAG -800 -512 0
FLAG -800 -656 VDD
FLAG -512 -512 0
FLAG -512 -656 VDDby2
FLAG -832 -1952 ra2
FLAG -832 -1840 0
FLAG 464 -2416 0
FLAG 464 -2240 mb2
FLAG 304 -2384 ra2
FLAG -1456 -1952 ra4
FLAG -1456 -1840 0
FLAG 464 -2928 0
FLAG 464 -2752 mb4
FLAG 304 -2896 ra4
FLAG -1456 -2320 ra5
FLAG -1456 -2208 0
FLAG 464 -3424 0
FLAG 464 -3248 mb5
FLAG 304 -3392 ra5
FLAG -800 -2320 ra6
FLAG -800 -2208 0
FLAG 464 -3872 0
FLAG 464 -3696 mb6
FLAG 304 -3840 ra6
FLAG -1456 -2592 ra7
FLAG -1456 -2480 0
FLAG 464 -4320 0
FLAG 464 -4144 mb7
FLAG 304 -4288 ra7
FLAG -800 -2624 ra8
FLAG -800 -2512 0
FLAG 464 -4752 0
FLAG 464 -4576 mb8
FLAG 304 -4720 ra8
FLAG 464 -4464 PV
FLAG 464 -4032 PV
FLAG 464 -3584 PV
FLAG 464 -3136 PV
FLAG 464 -2640 PV
FLAG 464 -2128 PV
FLAG 464 -1616 PV
FLAG 384 -976 PV
FLAG -208 -512 0
FLAG -208 -656 PV
FLAG 400 -288 CSEL
FLAG 432 -192 0
FLAG 1440 -448 0
FLAG -1776 -528 0
FLAG -1776 -672 write0
FLAG -1408 -528 0
FLAG -1408 -672 write1
FLAG 1712 -288 0
FLAG 1712 -544 VDD
FLAG 1712 -592 VDD
FLAG 1712 -336 0
FLAG 1472 -544 CSEL
FLAG 1872 -448 write1
FLAG 192 -32 0
FLAG 192 -288 VDD
FLAG 192 -336 VDD
FLAG 192 -80 0
FLAG 32 -192 write0
FLAG -1696 -1024 0
FLAG -1696 -1136 CSEL
TEXT -376 136 Left 2 !.include ../DRAM_models/transistor_model.pm
TEXT 800 -952 VLeft 2 ;Bitline to array0
TEXT 1296 96 VLeft 2 ;Bitline to array1
TEXT -448 104 Left 2 !.tran 220ns uic
TEXT -392 216 Left 2 ;Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
TEXT 48 -1296 Left 2 ;Word line in array 0
TEXT 832 256 Left 2 ;Word line in array 1
TEXT -368 168 Left 2 ;.step param X 0.0v 1.5v 0.1v
TEXT 48 -1888 Left 2 ;Word line in array 1
TEXT -832 80 Left 2 !.param process_var=0.05
TEXT -832 40 Left 2 !.step param run 1 100 1
TEXT -832 456 Left 2 !.param cell_cap={24.0fF*cell_cap_factor}
TEXT -832 496 Left 2 !.param bitline_cap={85fF*bl_cap_factor}
TEXT -920 168 Left 2 ;DRAM Circuit Parameters
TEXT -832 536 Left 2 !.param access_tran_L={85nm*access_tran_L_factor}
TEXT -832 576 Left 2 !.param access_tran_W={55nm*access_tran_W_factor}
TEXT -816 1584 Left 2 !.param bitline_R=R_per_cell*cells_per_BL
TEXT -576 1520 Left 2 ;ohm
TEXT -816 1520 Left 2 !.param R_per_cell=40
TEXT -816 1488 Left 2 ;Bitline Resistance
TEXT -824 976 Left 2 !.param SA_nmos_L={160nm*SA_nmos_L_factor}
TEXT -824 1000 Left 2 !.param SA_nmos_W={1900nm*SA_nmos_W_factor}
TEXT -824 1032 Left 2 !.param SA_pmos_L={160nm*SA_pmos_L_factor}
TEXT -824 1056 Left 2 !.param SA_pmos_W={1330nm*SA_pmos_W_factor}
TEXT -824 1096 Left 2 !.param SA_eq_L=96.3nm
TEXT -824 1120 Left 2 !.param SA_eq_W=541nm
TEXT -824 1160 Left 2 !.param SA_nset_L={255nm*SA_nset_L_factor}
TEXT -824 1184 Left 2 !.param SA_nset_W={220nm*SA_nset_W_factor}
TEXT -824 1224 Left 2 !.param SA_pset_L={255nm*SA_pset_L_factor}
TEXT -824 1248 Left 2 !.param SA_pset_W={220nm*SA_pset_W_factor}
TEXT -816 1552 Left 2 !.param cells_per_BL=1024
TEXT -832 424 Left 2 ;Cell Array
TEXT -824 944 Left 2 ;Sense Amp.
TEXT -832 224 Left 2 ;Voltage
TEXT -832 248 Left 2 !.param core_voltage=0.95V
TEXT -832 288 Left 2 !.param wordline_voltage=2.9V
TEXT -832 616 Left 2 !.param cell0_charge=core_voltage*cell0_charge_state
TEXT -832 656 Left 2 !.param cell1_charge=core_voltage*other_cells_charge_state
TEXT -832 688 Left 2 !.param cell2_charge=core_voltage*other_cells_charge_state
TEXT 48 -2400 Left 2 ;Word line in array 1
TEXT -832 720 Left 2 !.param cell3_charge=core_voltage*other_cells_charge_state
TEXT 48 -2912 Left 2 ;Word line in array 1
TEXT -832 752 Left 2 !.param cell4_charge=core_voltage*other_cells_charge_state
TEXT 48 -3408 Left 2 ;Word line in array 1
TEXT -832 784 Left 2 !.param cell5_charge=core_voltage*other_cells_charge_state
TEXT 48 -3856 Left 2 ;Word line in array 1
TEXT -832 816 Left 2 !.param cell6_charge=core_voltage*other_cells_charge_state
TEXT 48 -4304 Left 2 ;Word line in array 1
TEXT -832 840 Left 2 !.param cell7_charge=core_voltage*other_cells_charge_state
TEXT 48 -4736 Left 2 ;Word line in array 1
TEXT -832 872 Left 2 !.param cell0_charge_state=0.8
TEXT -832 320 Left 2 !.param pv_modifier=0.5
TEXT -832 360 Left 2 !.param plate_voltage={core_voltage*pv_modifier}
TEXT -816 1400 Left 2 !.param psense_act=4ns
TEXT -816 1424 Left 2 !.param nsense_act=4ns
TEXT -808 1840 Left 2 ;Wordline Activation
TEXT -808 1872 Left 2 !.param wl0_act=1.0
TEXT -808 1904 Left 2 !.param wl1_act=1.0
TEXT -808 1936 Left 2 !.param wl2_act=1.0
TEXT -808 1968 Left 2 !.param wl3_act=1.0
TEXT -808 2000 Left 2 !.param wl4_act=1.0
TEXT -808 2032 Left 2 !.param wl5_act=1.0
TEXT -808 2064 Left 2 !.param wl6_act=1.0
TEXT -808 2096 Left 2 !.param wl7_act=1.0
TEXT -808 2280 Left 2 !.param tech_node=7
TEXT -560 2280 Left 2 ;1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
TEXT -808 2248 Left 2 ;Technology Scaling
TEXT -808 2312 Left 2 !.param cell_cap_factor={0.95**tech_node}
TEXT -808 2344 Left 2 !.param bl_cap_factor={0.95**tech_node}
TEXT -808 2376 Left 2 !.param access_tran_L_factor={0.95**tech_node}
TEXT -808 2408 Left 2 !.param access_tran_W_factor={0.85**tech_node}
TEXT -808 2440 Left 2 !.param SA_nmos_L_factor={0.93**tech_node}
TEXT -808 2464 Left 2 !.param SA_nmos_W_factor={0.93**tech_node}
TEXT -808 2496 Left 2 !.param SA_pmos_L_factor={0.93**tech_node}
TEXT -808 2520 Left 2 !.param SA_pmos_W_factor={0.93**tech_node}
TEXT -808 2552 Left 2 !.param SA_nset_L_factor={0.93**tech_node}
TEXT -808 2576 Left 2 !.param SA_nset_W_factor={0.93**tech_node}
TEXT -808 2608 Left 2 !.param SA_pset_L_factor={0.93**tech_node}
TEXT -808 2632 Left 2 !.param SA_pset_W_factor={0.95**tech_node}
TEXT -816 1768 Left 2 !.param wordline_C={WL_C_per_cell*cells_per_LWL}
TEXT -816 1704 Left 2 !.param WL_C_per_cell=0.07fF
TEXT -816 1648 Left 2 ;Wordline Parasitics
TEXT -816 1672 Left 2 !.param cells_per_LWL=1024
TEXT -816 1736 Left 2 !.param WL_R_per_cell=40ohm
TEXT -816 1800 Left 2 !.param wordline_R={WL_R_per_cell*cells_per_LWL}
TEXT -808 2664 Left 2 !.param WL_cap_factor={0.95**tech_node}
TEXT -808 2696 Left 2 !.param WL_res_factor={0.95**tech_node}
TEXT -800 2856 Left 2 ;Write Logic
TEXT -800 2888 Left 2 !.param wr0_voltage=0V
TEXT -800 2912 Left 2 !.param wr1_voltage=0V
TEXT -832 904 Left 2 !.param other_cells_charge_state=0.8
TEXT -808 2144 Left 2 !.param wl0_act_time=20ns
TEXT -808 2176 Left 2 !.param other_wls_act_time=20ns
TEXT -824 1288 Left 2 !.param SA_nWR_L={70nm*SA_nWR_L_factor}
TEXT -824 1312 Left 2 !.param SA_nWR_W={840nm*SA_nWR_W_factor}
TEXT -808 2728 Left 2 !.param SA_nWR_L_factor={0.93**tech_node}
TEXT -808 2752 Left 2 !.param SA_nWR_W_factor={0.93**tech_node}
TEXT -824 1344 Left 2 !.param SA_pWR_L={70nm*SA_pWR_L_factor}
TEXT -824 1368 Left 2 !.param SA_pWR_W={840nm*SA_pWR_W_factor}
TEXT 1704 -680 Left 2 ;write_driver_inv
TEXT 200 -424 Right 2 ;write_driver
TEXT -800 2944 Left 2 !.param csel_act=400ns
TEXT -808 2776 Left 2 !.param SA_pWR_L_factor={0.93**tech_node}
TEXT -808 2800 Left 2 !.param SA_pWR_W_factor={0.93**tech_node}