Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4841.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4841.asy)
V4 IN 0 SINE(2.5 1 250K)
V2 +V 0 5
XU1 IN OUT +V 0 OUT NC_01 ADA4841 ;pnba NI)IN)+V)-V)OUT)_D
.tran 500u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1244 700
WIRE 640 -1200 528 -1200
WIRE 560 -1136 560 -1152
WIRE 240 -1120 240 -1136
WIRE 528 -1120 528 -1200
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1200
WIRE 640 -1104 608 -1104
WIRE 736 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 560 -1056 560 -1072
WIRE 240 -1024 240 -1040
WIRE 432 -976 432 -992
SYMBOL Opamps\\ADA4841 576 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 240 -1136 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V4
SYMATTR Value SINE(2.5 1 250K)
FLAG 240 -1136 +V
FLAG 240 -1024 0
FLAG 432 -976 0
FLAG 736 -1104 OUT
FLAG 560 -1056 0
FLAG 432 -1088 IN
FLAG 560 -1152 +V
TEXT 720 -992 Left 2 !.tran 500u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1083.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1083.asy)
C1 OUT 0 10
XU1 N001 OUT IN LT1083 ;pnba ADJ)OUT)IN
R1 OUT N001 121
Rload OUT 0 10
R2 N001 0 365
V1 IN 0 PWL(0 0 1 10) Rser=0.1
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1440 896
WIRE 1856 896 1808 896
WIRE 1952 896 1856 896
WIRE 2064 896 1952 896
WIRE 1856 912 1856 896
WIRE 2064 912 2064 896
WIRE 1440 928 1440 896
WIRE 1952 928 1952 896
WIRE 1952 1008 1952 992
WIRE 2064 1008 2064 992
WIRE 1680 1024 1680 992
WIRE 1856 1024 1856 992
WIRE 1856 1024 1680 1024
WIRE 1440 1040 1440 1008
WIRE 1856 1040 1856 1024
WIRE 1856 1136 1856 1120
SYMBOL RES 1840 896 R0
SYMATTR InstName R1
SYMATTR Value 121
SYMBOL RES 1840 1024 R0
SYMATTR InstName R2
SYMATTR Value 365
SYMBOL cap 1936 928 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1083 1680 896 R0
SYMATTR InstName U1
SYMBOL RES 2048 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL VOLTAGE 1440 912 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
FLAG 2064 896 OUT
FLAG 1856 1136 0
FLAG 2064 1008 0
FLAG 1440 1040 0
FLAG 1952 1008 0
FLAG 1440 896 IN
TEXT 1992 1088 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\SSM2141.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\SSM2141.asy)
V2 +V 0 15
V3 -V 0 -15
V1 IN N001 SINE(0 1 1K)
XU2 0 IN N001 -V OUT OUT +V SSM2141 ;pnba Ref)-IN)+IN)Vee)SENSE)OUT)Vcc
.tran 3m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1512
WIRE 1952 832 1952 816
WIRE 1824 880 1648 880
WIRE 2048 880 2016 880
WIRE 1408 896 1408 880
WIRE 1520 896 1520 880
WIRE 1648 896 1648 880
WIRE 2048 944 2048 880
WIRE 2048 944 2016 944
WIRE 2064 944 2048 944
WIRE 1408 992 1408 976
WIRE 1520 992 1520 976
WIRE 1648 1008 1648 976
WIRE 1824 1008 1648 1008
WIRE 2032 1008 2016 1008
WIRE 1952 1072 1952 1056
SYMBOL VOLTAGE 1648 880 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1K)
SYMBOL voltage 1520 880 R0
SYMATTR InstName V3
SYMATTR Value -15
SYMBOL voltage 1408 880 R0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL opamps\\SSM2141 1952 944 R0
SYMATTR InstName U2
FLAG 2064 944 OUT
FLAG 1648 880 IN
FLAG 2032 1008 0
FLAG 1520 992 0
FLAG 1408 992 0
FLAG 1952 816 +V
FLAG 1408 880 +V
FLAG 1520 880 -V
FLAG 1952 1072 -V
TEXT 2032 1096 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\44bb3376cf75_Draft8.asc
* Generated by LTspice 26.0.1 for Windows.
vds1 N001 0 -1.2
M1 N001 N002 0 N001 PMOS l=90nm w=405nm
vgs1 N002 0 -1.2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc vds1 0 -1.2 0.2 vgs1 0 -1.2 0.2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -112 64 -192 64
WIRE 96 64 -112 64
WIRE -192 112 -192 64
WIRE -256 160 -352 160
WIRE -112 160 -112 64
WIRE -112 160 -192 160
WIRE 96 160 96 64
WIRE -256 192 -256 160
WIRE -240 192 -256 192
WIRE -48 208 -192 208
WIRE -48 240 -48 208
WIRE -48 240 -80 240
WIRE 16 240 -48 240
WIRE -48 256 -48 240
WIRE 16 256 16 240
WIRE 96 256 96 240
WIRE 96 256 16 256
WIRE -352 272 -352 240
WIRE -80 272 -80 240
WIRE -80 272 -352 272
SYMBOL voltage -352 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vgs1
SYMATTR Value -1.2
SYMBOL pmos4 -240 112 R0
SYMATTR InstName M1
SYMATTR Value2 l=90nm w=405nm
SYMBOL voltage 96 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vds1
SYMATTR Value -1.2
FLAG -48 256 0
TEXT -384 280 Left 2 !.dc vds1 0 -1.2 0.2 vgs1 0 -1.2 0.2
* Z:\home\khalils\Downloads\files\data\raw_asc\234111d064e4_serout.asc
* Generated by LTspice 26.0.1 for Windows.
V1 serin 0 EXP(0 5 0 0.000001 0.000052 0.0000001)
Q1 N002 N003 0 0 BC547B
R1 N003 serin 100000
V2 N001 0 5
R2 N001 N002 1000
Q2 output N004 0 0 BC547B
R3 N004 N002 22000
R4 N001 output 47000
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0 0.0001 0
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -1664 -1728 -2064 -1728
WIRE -1504 -1728 -1664 -1728
WIRE -2064 -1632 -2064 -1648
WIRE -1920 -1632 -2064 -1632
WIRE -1664 -1632 -1664 -1648
WIRE -1568 -1632 -1664 -1632
WIRE -1504 -1616 -1504 -1728
WIRE -2368 -1584 -2368 -1648
WIRE -2240 -1584 -2368 -1584
WIRE -2128 -1584 -2160 -1584
WIRE -1920 -1584 -1920 -1632
WIRE -1824 -1584 -1920 -1584
WIRE -1728 -1584 -1744 -1584
WIRE -2368 -1552 -2368 -1584
WIRE -2064 -1472 -2064 -1536
WIRE -2064 -1472 -2368 -1472
WIRE -1664 -1472 -1664 -1536
WIRE -1664 -1472 -2064 -1472
WIRE -1504 -1472 -1504 -1536
WIRE -1504 -1472 -1664 -1472
WIRE -2064 -1440 -2064 -1472
FLAG -1568 -1632 output
FLAG -2064 -1440 0
FLAG -2368 -1648 serin
SYMBOL voltage -2368 -1568 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR Value EXP(0 5 0 0.000001 0.000052 0.0000001)
SYMATTR InstName V1
SYMBOL npn -2128 -1632 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL res -2144 -1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100000
SYMBOL voltage -1504 -1632 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 44 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res -2080 -1744 R0
SYMATTR InstName R2
SYMATTR Value 1000
SYMBOL npn -1728 -1632 R0
SYMATTR InstName Q2
SYMATTR Value BC547B
SYMBOL res -1728 -1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 22000
SYMBOL res -1680 -1744 R0
SYMATTR InstName R4
SYMATTR Value 47000
TEXT -2400 -1416 Left 2 !.tran 0 0.0001 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3495B-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3495B-1.asy)
V1 IN 0 3.6 Rser=0.1
R1 OUT N003 909K
XU1 0 MP_01 IN IN IN N003 OUT N002 MP_02 N001 LT3495B-1 ;pnba GND))Vcc)CTRL)_SHDN)FB)Vout)CAP))SW
C1 N002 0 2.2
Rload OUT 0 500
C2 OUT 0 1
D1 N001 N002 1N5817
L1 IN N001 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT3495B-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1456
WIRE 1616 880 1520 880
WIRE 1648 880 1616 880
WIRE 1760 880 1728 880
WIRE 1792 880 1760 880
WIRE 1888 880 1856 880
WIRE 2016 880 1888 880
WIRE 1520 896 1520 880
WIRE 2016 896 2016 880
WIRE 1760 944 1760 880
WIRE 1888 944 1888 880
WIRE 2016 976 2016 960
WIRE 1520 992 1520 976
WIRE 1616 1008 1616 880
WIRE 1680 1008 1616 1008
WIRE 2000 1008 1968 1008
WIRE 2112 1008 2000 1008
WIRE 2208 1008 2112 1008
WIRE 2112 1024 2112 1008
WIRE 2208 1024 2208 1008
WIRE 2000 1040 2000 1008
WIRE 1616 1088 1616 1008
WIRE 1680 1088 1616 1088
WIRE 2112 1120 2112 1088
WIRE 2208 1120 2208 1104
WIRE 1616 1168 1616 1088
WIRE 1680 1168 1616 1168
WIRE 2000 1168 2000 1120
WIRE 2000 1168 1968 1168
WIRE 1824 1248 1824 1232
SYMBOL schottky 1792 896 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5817
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 2000 896 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL ind 1632 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL PowerProducts\\LT3495B-1 1824 1088 R0
SYMATTR InstName U1
SYMBOL res 2192 1008 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL RES 1984 1024 R0
SYMATTR InstName R1
SYMATTR Value 909K
SYMBOL cap 2096 1024 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL VOLTAGE 1520 880 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMATTR SpiceLine Rser=0.1
FLAG 2208 1008 OUT
FLAG 1824 1248 0
FLAG 1520 992 0
FLAG 1520 880 IN
FLAG 2016 976 0
FLAG 2112 1120 0
FLAG 2208 1120 0
TEXT 2032 1208 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\6682cea32465_Draft01.asc
* Generated by LTspice 26.0.1 for Windows.
* anti-parallel diodes of bjt and discrete are reasonably robust against ESD.\nfaster than optocoupler. albeit gnd referenced.\nalso makes a good rough level-shift, signal comparator.
V1 N001 0 SINE(0 15 50)
V2 VCC 0 5
Q1 N003 N002 0 0 NPN
V4 P15V 0 15
R9 N003 VCC 10k
D3 0 N002 D
R1 N002 N001 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.2s
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5720 1740
WIRE 1216 -256 1120 -256
WIRE 1344 -256 1296 -256
WIRE 2000 -240 1792 -240
WIRE 1120 -208 1120 -256
WIRE 1344 -192 1344 -256
WIRE 1680 -192 1344 -192
WIRE 1728 -192 1680 -192
WIRE 1504 -128 1120 -128
WIRE 1680 -128 1504 -128
WIRE 1792 -128 1792 -144
WIRE 1792 -128 1680 -128
WIRE 2000 -128 1792 -128
WIRE 1504 -64 1504 -128
SYMBOL voltage 784 -448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value 5
SYMATTR InstName V2
SYMBOL voltage 608 -432 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value 15
SYMATTR InstName V4
SYMBOL npn 1728 -240 R0
SYMATTR InstName Q1
SYMBOL res 1312 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 1808 -224 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R9
SYMATTR Value 10k
SYMBOL diode 1696 -128 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMBOL voltage 1120 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value SINE(0 15 50)
SYMATTR InstName V1
FLAG 784 -352 0
FLAG 784 -432 VCC
FLAG 608 -336 0
FLAG 608 -416 P15V
FLAG 1792 -320 VCC
FLAG 1504 -64 0
TEXT 992 -416 Left 2 !.tran 0.2s
TEXT 1952 -400 Left 2 ;anti-parallel diodes of bjt and discrete are reasonably robust against ESD.\nfaster than optocoupler. albeit gnd referenced.\nalso makes a good rough level-shift, signal comparator.
* Z:\home\khalils\Downloads\files\data\raw_asc\8b1fc00fbe51_1.asc
* Generated by LTspice 26.0.1 for Windows.
R5 N005 N004 1
R3 N006 N003 1
C2 N007 0 {1/w0}
R2 N002 0 1
C1 N002 N001 {1/w0}
XU1 N004 N006 N005 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R1 N001 N007 1
C3 N006 0 {1/w0}
V2 N003 0 AC 1 0
R4 N004 N003 1
V1 N001 0 AC 1 0
.ac dec 100 1m 1000
.param f0=1 w0=8
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1128 680
WIRE 80 80 -16 80
WIRE 96 80 80 80
WIRE 288 80 160 80
WIRE 384 80 288 80
WIRE 592 80 528 80
WIRE 736 80 672 80
WIRE 848 80 736 80
WIRE 1024 80 928 80
WIRE 80 128 80 80
WIRE 208 128 80 128
WIRE -16 144 -16 80
WIRE 208 144 208 128
WIRE 288 144 288 80
WIRE 736 208 736 80
WIRE 864 208 736 208
WIRE 1024 224 1024 80
WIRE 1024 224 928 224
WIRE 288 240 288 224
WIRE 288 240 64 240
WIRE 528 240 528 80
WIRE 608 240 528 240
WIRE 736 240 688 240
WIRE 864 240 736 240
WIRE 528 288 528 240
WIRE 736 288 736 240
WIRE -16 304 -16 224
WIRE 64 304 64 240
WIRE 64 304 -16 304
WIRE 96 304 64 304
WIRE 208 304 208 224
WIRE 208 304 160 304
WIRE 384 304 208 304
WIRE 528 416 528 368
WIRE 736 416 736 352
SYMBOL voltage 528 272 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL res 688 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1
SYMBOL res 944 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL voltage -16 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL OpAmps\\opamp 896 160 R0
SYMATTR InstName U1
SYMBOL cap 160 288 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {1/w0}
SYMBOL res 272 128 R0
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL res 192 128 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL cap 720 288 R0
SYMATTR InstName C3
SYMATTR Value {1/w0}
SYMBOL cap 160 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {1/w0}
SYMBOL res 704 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1
FLAG -16 304 0
FLAG 736 416 0
FLAG 528 416 0
TEXT -50 354 Left 2 !.ac dec 100 1m 1000
TEXT -48 400 Left 2 !.param f0=1 w0=8
TEXT -48 456 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\16aec6202adc_Draft11.asc
* Generated by LTspice 26.0.1 for Windows.
C1 b N001 3.3
R a b 220 tol=1 pwr=0.1
C2 N001 0 3.3
VE a 0 10
.ic v(b)=0
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 64 64 64
WIRE 304 64 240 64
WIRE 336 64 304 64
WIRE 64 160 64 64
WIRE 336 160 336 144
WIRE 336 176 336 160
WIRE 336 256 336 240
WIRE 64 336 64 240
WIRE 224 336 224 128
WIRE 224 336 64 336
WIRE 304 336 224 336
WIRE 336 336 336 320
WIRE 336 336 304 336
WIRE 64 352 64 336
SYMBOL res 320 48 R0
SYMATTR InstName R
SYMATTR Value 220
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL cap 320 256 R0
SYMATTR InstName C2
SYMATTR Value 3.3u
SYMBOL cap 320 176 R0
SYMATTR InstName C1
SYMATTR Value 3.3u
SYMBOL voltage 64 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName E
SYMATTR Value 10
FLAG 64 352 0
FLAG 240 64 SW
FLAG 304 64 a
FLAG 336 160 b
FLAG 304 336 c
TEXT 280 352 Left 2 !.ic v(b)=0
TEXT 30 384 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\d354764498cf_Backup_spice.asc
* Generated by LTspice 26.0.1 for Windows.
C1 filterout N001 3nF
C2 N001 N002 189nF
R1 N002 input 1k
R2 filterout N001 50k
R4 Vdd Vout 5k
V1 Vdd 0 5
V2 0 Vss 0V
XU1 0 N001 Vdd 0 filterout level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
M1 Vout filterout 0 0 PMOS
V3 input 0 ac 25mV
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* Filter for A5
.ac dec 10 1hz 200kHz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 680
WIRE -288 -272 -288 -304
WIRE -288 -272 -400 -272
WIRE -288 -256 -288 -272
WIRE -144 -256 -144 -320
WIRE -288 -112 -288 -176
WIRE -144 -112 -144 -176
WIRE 128 -112 64 -112
WIRE 320 -112 208 -112
WIRE 800 -80 800 -144
WIRE 64 -16 64 -112
WIRE 128 -16 64 -16
WIRE 320 -16 320 -112
WIRE 320 -16 192 -16
WIRE 800 32 800 0
WIRE 864 32 800 32
WIRE -400 48 -400 -272
WIRE 160 48 -400 48
WIRE 800 64 800 32
WIRE 160 112 160 48
WIRE -288 128 -400 128
WIRE -208 128 -288 128
WIRE -80 128 -128 128
WIRE 64 128 64 -16
WIRE 64 128 -16 128
WIRE 128 128 64 128
WIRE -400 144 -400 128
WIRE 256 144 192 144
WIRE 320 144 320 -16
WIRE 320 144 256 144
WIRE 752 144 320 144
WIRE 128 160 80 160
WIRE 80 192 80 160
WIRE 160 224 160 176
WIRE 800 240 800 160
WIRE -400 256 -400 224
FLAG 80 192 0
FLAG -288 -304 Vdd
FLAG -144 -320 Vss
FLAG -144 -112 0
FLAG -288 -112 0
FLAG 160 224 0
FLAG -400 256 0
FLAG 800 -144 Vdd
FLAG 800 240 0
FLAG 864 32 Vout
FLAG -288 128 input
FLAG 256 144 filterout
SYMBOL cap 192 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 3nF
SYMBOL cap -16 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 189nF
SYMBOL res -112 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 224 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50k
SYMBOL res 784 -96 R0
SYMATTR InstName R4
SYMATTR Value 5k
SYMBOL voltage -288 -272 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -144 -160 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value 0V
SYMBOL Opamps\\UniversalOpamp2 160 144 R0
SYMATTR InstName U1
SYMBOL pmos 752 64 R0
SYMATTR InstName M1
SYMBOL voltage -400 128 R0
SYMATTR InstName V3
SYMATTR Value ac 25mV
TEXT 104 -216 Left 2 ;Filter for A5
TEXT -434 360 Left 2 !.ac dec 10 1hz 200kHz
* Z:\home\khalils\Downloads\files\data\raw_asc\0785d0e341a4_2934-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2934-2.asy)
XU1 N002 N004 N001 0 N003 N005 N006 N001 LTC2934-2 ;pnba ADJ)PFI)RT)GND)_PFO)_RST)_MR)VCC
MQ1 N006 N007 0 0 BSS123
V1 N001 0 PWL(0 0 3.6 3.6 16 3.6 19.6 0 20.1 0 23.7 3.6)
V2 N007 0 PWL(0 0 7.999 0 8 3.6 8.499 3.6 8.5 0 24.999 0 25 3.6 25.5 3.6 25.501 0)
R1 N002 N004 11.8K
R3 N001 N002 750K
R2 N004 0 237K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20
.lib LTC2934-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 892 680
WIRE -48 -32 -592 -32
WIRE 240 -32 -48 -32
WIRE 368 -32 240 -32
WIRE -592 -16 -592 -32
WIRE -48 -16 -48 -32
WIRE 240 48 240 -32
WIRE -592 80 -592 64
WIRE -48 80 -48 64
WIRE 128 80 -48 80
WIRE -48 96 -48 80
WIRE 368 96 368 -32
WIRE 368 96 352 96
WIRE 368 176 352 176
WIRE -48 192 -48 176
WIRE 128 192 -48 192
WIRE -48 208 -48 192
WIRE 368 256 352 256
WIRE 128 272 96 272
WIRE 96 288 96 272
WIRE -48 320 -48 288
WIRE 240 336 240 304
WIRE 48 368 -16 368
WIRE -16 384 -16 368
WIRE 96 400 96 384
WIRE -16 480 -16 464
SYMBOL res -64 192 R0
SYMATTR InstName R2
SYMATTR Value 237K
SYMBOL voltage -592 -32 R0
WINDOW 123 24 146 Left 0
WINDOW 39 24 125 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 3.6 3.6 16 3.6 19.6 0 20.1 0 23.7 3.6)
SYMBOL nmos 48 288 R0
SYMATTR InstName Q1
SYMATTR Value BSS123
SYMBOL LTC2934-2 240 176 R0
SYMATTR InstName U1
SYMBOL res -64 -32 R0
SYMATTR InstName R3
SYMATTR Value 750K
SYMBOL voltage -16 368 R0
WINDOW 123 24 146 Left 0
WINDOW 39 24 125 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 0 7.999 0 8 3.6 8.499 3.6 8.5 0 24.999 0 25 3.6 25.5 3.6 25.501 0)
SYMBOL res -64 80 R0
SYMATTR InstName R1
SYMATTR Value 11.8K
FLAG -48 320 0
FLAG 240 336 0
FLAG -16 480 0
FLAG -592 80 0
FLAG 96 400 0
TEXT 448 544 Left 0 !.tran 20
* Z:\home\khalils\Downloads\files\data\raw_asc\1b7026001943_current_mirros.asc
* Generated by LTspice 26.0.1 for Windows.
* Range of R1 is defined until saturation.\nHere, the R1max is around 11k to produce the same current in I1. Hence, Mirroring the current I1.\nAbove 11k, the currents Ic1 and Ic2 starts to become different.\nVc = Vcc - IcRc
R1 N001 N003 15k
Q2 N002 N002 0 0 NPN
Q1 N003 N002 0 0 NPN
V1 N001 0 12V
I1 0 N002 1mA
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1624 680
WIRE 96 -64 -80 -64
WIRE 96 -48 96 -64
WIRE 368 0 368 -48
WIRE 96 80 96 32
WIRE 240 80 96 80
WIRE 96 128 96 80
WIRE 368 128 368 80
WIRE 240 176 240 80
WIRE 240 176 160 176
WIRE 304 176 240 176
WIRE -80 320 -80 -64
WIRE 96 320 96 224
WIRE 96 320 -80 320
WIRE 240 320 96 320
WIRE 368 320 368 224
WIRE 368 320 240 320
WIRE 448 320 448 -48
WIRE 448 320 368 320
WIRE 240 368 240 320
DATAFLAG 176 176 ""
DATAFLAG 144 320 ""
DATAFLAG 96 48 ""
DATAFLAG 368 -32 ""
DATAFLAG 368 96 ""
DATAFLAG 368 256 ""
DATAFLAG 288 176 ""
DATAFLAG 176 320 ""
SYMBOL npn 304 128 R0
SYMATTR InstName Q1
SYMBOL current 96 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 1mA
SYMBOL npn 160 128 M0
SYMATTR InstName Q2
SYMBOL voltage 352 -48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12V
SYMBOL res 352 -16 R0
SYMATTR InstName R1
SYMATTR Value 15k
FLAG 240 368 0
TEXT 512 48 Left 2 !.op
TEXT 488 112 Left 2 ;Range of R1 is defined until saturation.\nHere, the R1max is around 11k to produce the same current in I1. Hence, Mirroring the current I1.\nAbove 11k, the currents Ic1 and Ic2 starts to become different.\nVc = Vcc - IcRc
* Z:\home\khalils\Downloads\files\data\raw_asc\edfd2651496d_mos_param_visibility.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc V1 0 5 .01
* How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
M2 out in vdd vdd PMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
V2 vdd 0 5
V1 in 0 2.5
M3 out in 0 0 NMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.model PMOS1 pmos level=2 nsub=4e15 tox=50n
.model NMOS1 nmos level=2 nsub=4e15 tox=50n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1404 948
WIRE 48 400 48 320
WIRE 48 544 48 480
WIRE 64 32 64 -32
WIRE 64 176 64 112
WIRE 112 320 48 320
WIRE 256 320 112 320
WIRE 256 320 256 160
WIRE 256 464 256 320
WIRE 352 160 256 160
WIRE 352 464 256 464
WIRE 400 -32 64 -32
WIRE 400 80 400 -32
WIRE 400 144 400 80
WIRE 400 320 400 240
WIRE 400 384 400 320
WIRE 400 544 400 480
WIRE 496 192 400 192
WIRE 496 432 400 432
WIRE 560 320 400 320
SYMBOL voltage 48 384 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL pmos4 352 240 M180
WINDOW 0 59 69 Left 0
WINDOW 3 57 27 Left 0
WINDOW 123 57 -1 Left 0
SYMATTR InstName M2
SYMATTR Value PMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
SYMBOL voltage 64 16 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL nmos4 352 384 R0
WINDOW 123 56 100 Left 0
SYMATTR InstName M3
SYMATTR Value NMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
FLAG 112 320 in
FLAG 400 544 0
FLAG 496 432 0
FLAG 496 192 vdd
FLAG 400 80 vdd
FLAG 560 320 out
FLAG 64 176 0
FLAG 48 544 0
TEXT 24 -104 Left 0 !.op
TEXT 24 624 Left 0 !.model PMOS1 pmos level=2 nsub=4e15 tox=50n\n.model NMOS1 nmos level=2 nsub=4e15 tox=50n
TEXT 24 -136 Left 0 ;.dc V1 0 5 .01
TEXT 16 -608 Left 0 ;How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc