Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8061-8.4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 12
C1 OUT 0 .1m
C3 N001 0 4.7
XU1 N001 N001 N001 N002 N003 0 N005 N004 OUT IN OUT MP_01 0 LTM8061-8.4 ;pnba Vin)VinC/CLP)RUN)_CHRG)_Fault)TMR)RNG/SS)NTC)BAT)VinA)Bias))GND
.tran 3m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8061-8.4.asy)
.lib LTM8061-8.4.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 80 -64 -32 -64
WIRE 384 -64 368 -64
WIRE 496 -64 384 -64
WIRE -32 -48 -32 -64
WIRE 496 -48 496 -64
WIRE 80 32 64 32
WIRE 384 32 384 -64
WIRE 384 32 368 32
WIRE 496 32 496 16
WIRE -32 48 -32 32
WIRE 64 128 64 32
WIRE 80 128 64 128
WIRE 384 128 368 128
WIRE -16 224 -32 224
WIRE 64 224 64 128
WIRE 64 224 48 224
WIRE 80 224 64 224
WIRE 384 224 368 224
WIRE 80 320 64 320
WIRE 384 320 368 320
WIRE 80 416 64 416
WIRE 384 416 368 416
FLAG 64 416 0
FLAG -32 48 0
FLAG 496 32 0
FLAG -32 -64 IN
FLAG 496 -64 OUT
FLAG -32 224 0
FLAG 64 320 0
SYMBOL voltage -32 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 480 -48 R0
SYMATTR InstName C1
SYMATTR Value .1m
SYMBOL cap 48 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL PowerProducts\\LTM8061-8.4 224 176 R0
SYMATTR InstName U1
TEXT 472 416 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\bb8037c4049d_Twin_T.asc
* Generated by LTspice 26.0.1 for Windows.
* Twin T
C2 N004 Vin2 {C2}
R1 N003 Vin2 {R2}
C1 Vout2 N004 {C2}
R2 Vout2 N003 {R2}
R3 0 N004 {R2/2}
V1 Vin2 0 SINE(0 10 500) AC 1
C3 0 N003 {2*C2}
.param R2=67725 C2=10n
.ac dec 100 1 20000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 956 680
WIRE 96 -192 -272 -192
WIRE 688 -192 224 -192
WIRE 416 -96 352 -96
WIRE 480 -96 416 -96
WIRE 416 -64 416 -96
WIRE 560 32 560 -96
WIRE 272 64 272 -96
WIRE 272 128 272 64
WIRE 416 128 336 128
WIRE 496 128 416 128
WIRE 560 128 560 32
WIRE -272 144 -272 -192
WIRE 96 144 96 -192
WIRE 96 144 -272 144
WIRE 416 160 416 128
WIRE 224 288 224 -192
WIRE 688 288 688 -192
WIRE 688 288 224 288
IOPIN 272 64 In
IOPIN 560 32 Out
IOPIN -208 -96 Out
SYMBOL res 576 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL cap 336 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL cap 432 0 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value {2*C2}
SYMBOL voltage -208 -112 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value SINE(0 10 500)
SYMBOL res 368 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R2}
SYMBOL res 432 256 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value {R2/2}
SYMBOL cap 560 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {C2}
FLAG 416 0 0
FLAG 416 240 0
FLAG 272 64 Vin2
FLAG 560 32 Vout2
FLAG -208 -16 0
FLAG -208 -96 Vin2
TEXT -232 104 Left 2 !.param R2=67725 C2=10n
TEXT -232 48 Left 2 !.ac dec 100 1 20000
TEXT 368 -160 Left 2 ;Twin T
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1763-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1763-1.2.asy)
R2 N001 IN 50K
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1763 Radj=8K ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
C1 N004 0 1
C4 OUT 0 10
R1 OUT 0 .6
C2 N003 0 10n
C3 N002 0 1
V1 IN 0 1.5
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
SYMBOL voltage -128 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL ADP1763-1.2 224 176 R0
SYMATTR InstName U1
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 504 280 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8646S.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8646S.asy)
L1 N002 OUT 2.2 Rser=10m
Rload OUT 0 .625
R2 OUT N004 1Meg
R4 N005 N006 7.5k
R3 N004 0 243K
V1 IN 0 12
XU1 OUT NC_01 NC_02 IN IN 0 IN N002 N001 0 N003 0 NC_03 N004 0 NC_04 N005 LT8646S ;pnba BIAS)INTVCC)BST)VIN1)VIN2)GND1)EN/UV)SW)RT)GND2)TR/SS)MODE)PG)FB)GND)CLKOUT)VC
C5 OUT N004 2.2p
R1 N001 0 41.2K
C1 N003 0 1n
C2 N006 0 330p
C4 OUT 0 100 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
.tran 1m startup
.lib LT8646S.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1848 760
WIRE 96 -80 0 -80
WIRE 208 -80 96 -80
WIRE 416 -80 208 -80
WIRE 0 -64 0 -80
WIRE 208 -64 208 -80
WIRE 96 0 96 -80
WIRE 112 0 96 0
WIRE 416 0 416 -80
WIRE 416 0 400 0
WIRE 0 32 0 16
WIRE 112 96 96 96
WIRE 416 96 400 96
WIRE 544 192 400 192
WIRE 112 288 96 288
WIRE 16 384 0 384
WIRE 112 384 96 384
WIRE 432 384 400 384
WIRE 544 384 544 192
WIRE 544 384 512 384
WIRE 656 384 544 384
WIRE 752 384 656 384
WIRE 848 384 752 384
WIRE 544 400 544 384
WIRE 656 400 656 384
WIRE 752 400 752 384
WIRE 848 400 848 384
WIRE 32 480 0 480
WIRE 112 480 96 480
WIRE 544 480 400 480
WIRE 656 480 656 464
WIRE 656 480 544 480
WIRE 544 496 544 480
WIRE 752 496 752 464
WIRE 848 496 848 480
WIRE 256 560 256 544
WIRE 336 560 336 544
WIRE 544 592 544 576
WIRE 336 656 336 640
WIRE 336 736 336 720
SYMBOL cap 96 496 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 528 480 R0
SYMATTR InstName R3
SYMATTR Value 243K
SYMBOL res 832 384 R0
SYMATTR InstName Rload
SYMATTR Value .625
SYMBOL ind 416 400 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=10m
SYMBOL cap 736 400 R0
SYMATTR InstName C4
SYMATTR Value 100
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL res 528 384 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage 0 -80 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 320 656 R0
SYMATTR Value 330p
SYMATTR InstName C2
SYMBOL res 320 544 R0
SYMATTR InstName R4
SYMATTR Value 7.5k
SYMBOL LT8646S 256 240 R0
SYMATTR InstName U1
SYMBOL res 112 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 41.2K
SYMBOL cap 640 400 R0
SYMATTR InstName C5
SYMATTR Value 2.2p
FLAG 256 560 0
FLAG 0 384 0
FLAG 0 32 0
FLAG 752 496 0
FLAG 544 592 0
FLAG 848 496 0
FLAG 848 384 OUT
FLAG 0 -80 IN
FLAG 96 96 0
FLAG 416 96 0
FLAG 0 480 0
FLAG 96 288 0
FLAG 336 736 0
TEXT 704 576 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0c6b576e1d4a_Power_Transistors.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N003 N006 0 0 NPN
R2 N001 N003 3300
R1 N006 N005 10k
V1 N005 0 V
V2 N001 0 V
Q2 N004 N008 0 0 NPN
R5 N002 N004 330
R6 N008 N007 1k
V3 N007 0 V
V4 N002 0 V
M1 N009 N011 N015 N015 NMOS
R3 N009 N013 330
V5 N013 N015 V
M2 N010 N012 N016 N016 NMOS
R4 N010 N014 330
V6 N014 N016 V
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V1 0 100 1 V2 0 100 10
* .dc V5 0 5 0.5
* .dc V6 0 5 0.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2488 1304
WIRE 464 0 240 0
WIRE 1440 0 1216 0
WIRE 464 80 464 0
WIRE 1440 80 1440 0
WIRE 240 96 240 0
WIRE 1216 96 1216 0
WIRE 240 208 240 176
WIRE 1216 208 1216 176
WIRE -80 256 -160 256
WIRE 176 256 0 256
WIRE 896 256 816 256
WIRE 1152 256 976 256
WIRE -160 304 -160 256
WIRE 816 304 816 256
WIRE -160 464 -160 384
WIRE 240 464 240 304
WIRE 240 464 -160 464
WIRE 464 464 464 160
WIRE 464 464 240 464
WIRE 816 464 816 384
WIRE 1216 464 1216 304
WIRE 1216 464 816 464
WIRE 1440 464 1440 160
WIRE 1440 464 1216 464
WIRE 240 528 240 464
WIRE 1216 528 1216 464
WIRE 576 816 240 816
WIRE 1472 816 1136 816
WIRE 240 960 240 816
WIRE 1136 960 1136 816
WIRE 576 976 576 816
WIRE 1472 976 1472 816
WIRE 192 1040 128 1040
WIRE 1088 1040 1008 1040
WIRE 576 1152 576 1056
WIRE 1472 1152 1472 1056
WIRE 240 1296 240 1056
WIRE 240 1296 128 1296
WIRE 576 1296 576 1232
WIRE 576 1296 240 1296
WIRE 1136 1296 1136 1056
WIRE 1136 1296 1008 1296
WIRE 1472 1296 1472 1232
WIRE 1472 1296 1136 1296
FLAG 240 528 0
FLAG 1216 528 0
SYMBOL npn 176 208 R0
SYMATTR InstName Q1
SYMBOL res 224 80 R0
SYMATTR InstName R2
SYMATTR Value 3300
SYMBOL res 16 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -160 288 R0
SYMATTR InstName V1
SYMBOL voltage 464 64 R0
SYMATTR InstName V2
SYMBOL npn 1152 208 R0
SYMATTR InstName Q2
SYMBOL res 1200 80 R0
SYMATTR InstName R5
SYMATTR Value 330
SYMBOL res 992 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL voltage 816 288 R0
SYMATTR InstName V3
SYMBOL voltage 1440 64 R0
SYMATTR InstName V4
SYMBOL nmos 192 960 R0
SYMATTR InstName M1
SYMBOL res 560 960 R0
SYMATTR InstName R3
SYMATTR Value 330
SYMBOL voltage 576 1136 R0
SYMATTR InstName V5
SYMBOL nmos 1088 960 R0
SYMATTR InstName M2
SYMBOL res 1456 960 R0
SYMATTR InstName R4
SYMATTR Value 330
SYMBOL voltage 1472 1136 R0
SYMATTR InstName V6
TEXT -200 -120 Left 2 !.dc V1 0 100 1 V2 0 100 10
TEXT -168 752 Left 2 ;.dc V5 0 5 0.5
TEXT 912 744 Left 2 ;.dc V6 0 5 0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\89245e335ab4_P-_E_Mosfet.asc
* Generated by LTspice 26.0.1 for Windows.
* D
* S
* G
* Enhancement Mode P Channel MOSFET
V2 N001 0 -1.8
M2 N001 N002 0 0 PMOS
V1 N002 0 -1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V1 0 -1.8 0.1 V2 0 -1.8 0.2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 528 128 336 128
WIRE 288 208 128 208
WIRE 128 240 128 208
WIRE 128 336 128 320
WIRE 336 336 336 224
WIRE 336 336 128 336
WIRE 528 336 528 208
WIRE 528 336 336 336
WIRE 336 368 336 336
SYMBOL voltage 528 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -1.8
SYMBOL voltage 128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -1.8
SYMBOL pmos 288 128 R0
SYMATTR InstName M2
FLAG 336 368 0
TEXT 96 392 Left 2 !.dc V1 0 -1.8 0.1 V2 0 -1.8 0.2
TEXT 416 128 Bottom 2 ;D
TEXT 424 336 Top 2 ;S
TEXT 200 208 Bottom 2 ;G
TEXT 88 80 Left 2 ;Enhancement Mode P Channel MOSFET
* Z:\home\khalils\Downloads\files\data\raw_asc\31fb91408a68_Draft5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
V2 N001 N002 0.25
R4 N003 N006 200
R1 N002 N003 1k
D1 N005 Ipv 1N4148
XU1 N006 N004 +Vs 0 N005 LT1001 ;pnba In+)In-)V+)V-)OUT
R2 Ipv N004 3k
R3 N004 0 1k
C1 N001 N003 2.5m IC = 0
V1 +Vs 0 5
D2 0 N003 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 20
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE 336 96 80 96
WIRE 80 144 80 96
WIRE 336 144 336 96
WIRE 80 256 80 208
WIRE 192 256 80 256
WIRE 336 256 336 208
WIRE 336 256 272 256
WIRE 416 256 336 256
WIRE 336 288 336 256
WIRE 416 304 416 256
WIRE 336 384 336 352
WIRE 512 448 480 448
WIRE 656 464 576 464
WIRE 736 464 720 464
WIRE 752 464 736 464
WIRE 416 480 416 384
WIRE 512 480 416 480
WIRE 384 592 368 592
WIRE 480 592 480 448
WIRE 480 592 464 592
WIRE 576 592 480 592
WIRE 736 592 736 464
WIRE 736 592 656 592
WIRE 368 624 368 592
IOPIN 752 464 Out
SYMBOL res 400 288 R0
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL OpAmps\\OP07 544 400 R0
SYMATTR InstName U1
SYMBOL cap 320 144 R0
WINDOW 39 24 84 Left 2
SYMATTR InstName C1
SYMATTR Value 2.5m
SYMATTR SpiceLine IC =  0
SYMBOL Misc\\cell 896 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 480 576 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 176 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 672 576 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 3k
SYMBOL zener 352 352 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL diode 656 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL Misc\\cell 80 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0.25
FLAG 544 432 +Vs
FLAG 544 496 0
FLAG 336 384 0
FLAG 368 624 0
FLAG 896 240 0
FLAG 896 176 +Vs
FLAG 752 464 Ipv
TEXT 72 648 Left 2 !.tran 20
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3528B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3528B.asy)
Rload OUT 0 8.25
XU1 IN N002 NC_01 OUT N001 0 0 IN LTC3528B ;pnba _SHDN)FB)Pgood)Vout)SW)PGND)SGND)Vin
C1 OUT 0 10 Rser=1m
V1 IN 0 2
C2 OUT N002 33p
R1 OUT N002 499K
R2 N002 0 287K
L1 IN N001 4.7 Rpar=5K
.tran 500u startup
.lib LTC3528B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 64 -96 64
WIRE 64 64 -32 64
WIRE 96 64 64 64
WIRE 192 64 176 64
WIRE -96 80 -96 64
WIRE 64 112 64 64
WIRE 192 112 192 64
WIRE -96 176 -96 160
WIRE -32 192 -32 64
WIRE -16 192 -32 192
WIRE 320 192 272 192
WIRE 432 192 320 192
WIRE 528 192 432 192
WIRE 608 192 528 192
WIRE 320 208 320 192
WIRE 432 208 432 192
WIRE 528 208 528 192
WIRE 608 208 608 192
WIRE 320 304 320 288
WIRE 320 304 272 304
WIRE 432 304 432 272
WIRE 432 304 320 304
WIRE 528 304 528 272
WIRE 608 304 608 288
WIRE 320 320 320 304
WIRE 64 400 64 384
WIRE 192 400 192 384
WIRE 320 416 320 400
SYMBOL PowerProducts\\LTC3528B 128 256 R0
SYMATTR InstName U1
SYMBOL cap 512 208 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=1m
SYMBOL res 592 192 R0
SYMATTR InstName Rload
SYMATTR Value 8.25
SYMBOL cap 416 208 R0
SYMATTR InstName C2
SYMATTR Value 33p
SYMBOL res 304 192 R0
SYMATTR InstName R1
SYMATTR Value 499K
SYMBOL ind 80 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rpar=5K
SYMBOL voltage -96 64 R0
WINDOW 0 20 15 Left 2
WINDOW 3 25 97 Left 2
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL res 304 304 R0
SYMATTR InstName R2
SYMATTR Value 287K
FLAG -96 176 0
FLAG 64 400 0
FLAG 320 416 0
FLAG 528 304 0
FLAG 608 304 0
FLAG 192 400 0
FLAG 608 192 OUT
FLAG -96 64 IN
TEXT 464 400 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\20aa1bd47027_RLC_only.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PULSE(-5 5 0 0 0 0.0025m 0.05m)
C1 N001 IN 1nF
L1 N001 RLC_only 1mH
R1 0 RLC_only 100
.tran 1ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1428 680
WIRE -256 144 -368 144
WIRE -112 144 -192 144
WIRE 256 144 -32 144
WIRE 320 144 256 144
WIRE 256 240 256 144
WIRE -368 256 -368 144
WIRE -368 432 -368 336
WIRE -64 432 -368 432
WIRE 256 432 256 320
WIRE 256 432 -64 432
WIRE -64 480 -64 432
IOPIN 320 144 Out
IOPIN -368 144 In
SYMBOL res 272 336 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage -368 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(-5 5 0 0 0 0.0025m 0.05m)
SYMBOL ind -128 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1mH
SYMBOL cap -192 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1nF
FLAG -64 480 0
FLAG 320 144 RLC_only
FLAG -368 144 IN
TEXT -536 352 Left 2 !.tran 1ms
* Z:\tmp\asc_dec_bjh7r6w2\107f2aa32e23_DAC_Filter_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N001 0 1n
R3 N002 N001 3.3k
V2 +5V 0 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1152 680
WIRE -416 -128 -416 -176
WIRE -272 -128 -272 -176
WIRE 496 -32 336 -32
WIRE 736 -32 576 -32
WIRE -416 80 -416 16
WIRE -304 80 -304 16
WIRE 208 80 176 80
WIRE 336 80 336 -32
WIRE 336 80 288 80
WIRE 384 80 336 80
WIRE 512 80 464 80
WIRE 624 80 512 80
WIRE 736 80 736 -32
WIRE 736 80 688 80
WIRE 816 80 736 80
WIRE 336 128 336 80
WIRE 592 176 592 144
WIRE 512 192 512 80
WIRE 560 192 512 192
WIRE -416 208 -416 160
WIRE -304 208 -304 160
WIRE 736 208 736 80
WIRE 336 224 336 192
WIRE 560 224 496 224
WIRE 496 272 496 224
SYMBOL cap 320 128 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 592 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 3.3k
SYMBOL voltage -304 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
FLAG -416 -128 0
FLAG 336 224 0
FLAG 496 272 0
FLAG 176 80 DAC_Out
FLAG -304 208 0
FLAG -304 16 +5V
FLAG -416 208 0
FLAG -416 16 -5V
FLAG 592 144 +5V
FLAG -272 -128 0
* Z:\tmp\asc_dec_bjh7r6w2\089413953cd8_Cohn_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
L6 N005 0 {Lm}
C5 N002 0 {C3}
L5 N003 N005 {L}
L2 N004 0 {Lm}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2300 1728
WIRE 1360 1168 1232 1168
WIRE 1664 1168 1536 1168
WIRE 1760 1168 1664 1168
WIRE 2080 1168 1952 1168
WIRE 2080 1184 2080 1168
WIRE 1360 1200 1360 1168
WIRE 1536 1200 1536 1168
WIRE 1760 1200 1760 1168
WIRE 1952 1200 1952 1168
WIRE 1664 1280 1664 1168
WIRE 1360 1296 1360 1280
WIRE 1456 1296 1360 1296
WIRE 1536 1296 1536 1280
WIRE 1536 1296 1456 1296
WIRE 1760 1296 1760 1280
WIRE 1872 1296 1760 1296
WIRE 1952 1296 1952 1280
WIRE 1952 1296 1872 1296
WIRE 2080 1296 2080 1248
WIRE 2240 1296 2080 1296
WIRE 1456 1328 1456 1296
WIRE 1872 1328 1872 1296
WIRE 2080 1328 2080 1296
WIRE 1456 1424 1456 1408
WIRE 1664 1424 1664 1344
WIRE 1872 1424 1872 1408
SYMBOL ind 1856 1312 R0
SYMATTR InstName L6
SYMATTR Value {Lm}
SYMBOL cap 1648 1280 R0
SYMATTR InstName C5
SYMATTR Value {C3}
SYMBOL ind 1936 1184 R0
SYMATTR InstName L5
SYMATTR Value {L}
SYMBOL ind 1440 1312 R0
SYMATTR InstName L2
SYMATTR Value {Lm}
FLAG 1872 1424 0
FLAG 1456 1424 0
FLAG 1664 1424 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4251.asc
* Generated by LTspice 26.0.1 for Windows.
M1 OUT N003 N005 N005 IRF530
R6 N005 IN 20m
R4 0 N002 402K
C1 N002 IN 10n
R7 N002 IN 32.4K
V1 IN 0 PWL(0 0 1m 0 1.001m -48 220m -48 221m -70)
C3 N006 IN 18n
R2 N003 N006 10
Rload 0 OUT 50
C5 0 OUT 100
XU1 N005 IN N001 N004 N002 N003 LTC4251 ;pnba Sense)Vee)Vin)Timer)UV/OV)Gate
C2 N004 IN 150n
C4 N001 IN 1
R1 0 N001 10K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 400m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4251.asy)
.lib LTC4251.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4692 2996
WIRE 2016 1744 2016 1728
WIRE 2640 1744 2640 1728
WIRE 2496 1760 2496 1728
WIRE 1456 1824 1456 1728
WIRE 2016 1856 2016 1824
WIRE 2272 1856 2016 1856
WIRE 2496 1856 2496 1824
WIRE 2640 1856 2640 1824
WIRE 2640 1856 2496 1856
WIRE 2768 1856 2640 1856
WIRE 2496 1872 2496 1856
WIRE 2016 1888 2016 1856
WIRE 864 1936 864 1728
WIRE 1456 1952 1456 1904
WIRE 1600 1952 1456 1952
WIRE 1824 1952 1600 1952
WIRE 2384 1952 2208 1952
WIRE 2448 1952 2384 1952
WIRE 2384 1968 2384 1952
WIRE 2272 2000 2272 1856
WIRE 1456 2032 1456 1952
WIRE 1600 2048 1600 1952
WIRE 1744 2096 1728 2096
WIRE 1824 2096 1808 2096
WIRE 2496 2096 2496 1968
WIRE 2496 2096 2208 2096
WIRE 2384 2112 2384 2048
WIRE 2496 2112 2496 2096
WIRE 864 2208 864 2016
WIRE 1456 2208 1456 2112
WIRE 1456 2208 864 2208
WIRE 1600 2208 1600 2112
WIRE 1600 2208 1456 2208
WIRE 1728 2208 1728 2096
WIRE 1728 2208 1600 2208
WIRE 2016 2208 2016 2160
WIRE 2016 2208 1728 2208
WIRE 2272 2208 2272 2064
WIRE 2272 2208 2016 2208
WIRE 2384 2208 2384 2176
WIRE 2384 2208 2272 2208
WIRE 2496 2208 2496 2192
WIRE 2496 2208 2384 2208
FLAG 864 2208 IN
FLAG 2768 1856 OUT
FLAG 864 1728 0
FLAG 1456 1728 0
FLAG 2016 1728 0
FLAG 2496 1728 0
FLAG 2640 1728 0
SYMBOL nmos 2448 1872 R0
WINDOW 0 101 14 Right 2
WINDOW 3 140 76 Right 2
SYMATTR InstName M1
SYMATTR Value IRF530
SYMBOL res 2512 2096 M0
WINDOW 0 -38 37 Left 2
WINDOW 3 -56 78 Left 2
SYMATTR InstName R6
SYMATTR Value 20m
SYMBOL res 1440 1808 R0
SYMATTR InstName R4
SYMATTR Value 402K
SYMBOL cap 1584 2048 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 1440 2016 R0
SYMATTR InstName R7
SYMATTR Value 32.4K
SYMBOL voltage 864 2032 M180
WINDOW 3 24 16 Left 2
WINDOW 0 24 96 Left 2
SYMATTR Value PWL(0 0 1m 0 1.001m -48 220m -48 221m -70)
SYMATTR InstName V1
SYMBOL cap 2368 2112 R0
SYMATTR InstName C3
SYMATTR Value 18n
SYMBOL res 2368 1952 R0
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL res 2624 1728 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 2480 1760 R0
SYMATTR InstName C5
SYMATTR Value 100
SYMBOL LTC4251 2016 2016 R0
SYMATTR InstName U1
SYMBOL cap 1808 2080 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 150n
SYMBOL cap 2256 2000 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 2000 1728 R0
SYMATTR InstName R1
SYMATTR Value 10K
TEXT 2632 2176 Left 2 !.tran 400m