Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\c39f421a49fd_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N003 0 SINE(3 1 10)
R1 N004 N003 1Meg
R2 N001 N004 1Meg
R3 N001 0 1k
R4 N002 N001 5.6k
V2 N002 0 V
XU1 N004 NC_01 N002 0 N005 LM324 ;pnba In+)In-)V+)V-)OUT
R5 N004 0 10k
R6 N005 N004 68k
.tran 1
.include LM324
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 -160 240 -160
WIRE 448 -160 432 -160
WIRE 576 -160 448 -160
WIRE 240 -144 240 -160
WIRE 240 -144 160 -144
WIRE 240 -96 240 -144
WIRE 80 32 32 32
WIRE 240 32 240 -16
WIRE 240 32 160 32
WIRE 416 32 240 32
WIRE 464 32 416 32
WIRE 656 48 528 48
WIRE 448 112 448 -160
WIRE 496 112 496 80
WIRE 496 112 448 112
WIRE 32 128 32 32
WIRE 416 144 416 32
WIRE 512 144 416 144
WIRE 656 144 656 48
WIRE 656 144 592 144
FLAG 32 208 0
FLAG 80 -144 0
FLAG 656 -160 0
FLAG 416 224 0
FLAG 496 16 0
SYMBOL voltage 32 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(3 1 10)
SYMBOL res 176 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL res 224 -112 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL res 176 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 448 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 5.6k
SYMBOL voltage 560 -160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMBOL OpAmps\\opamp2 496 112 M180
SYMATTR InstName U1
SYMATTR Value LM324
SYMBOL res 400 128 R0
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL res 608 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 68k
TEXT -2 248 Left 2 !.tran 1
TEXT 0 0 Left 2 !.include LM324
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1764A-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1764A-3.3.asy)
C1 OUT 0 10 Rser=.1
Rload OUT 0 500
XU1 IN IN 0 OUT OUT LT1764-3.3 ;pnba _SHDN)IN)GND)OUT)Sense
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT1764.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -224 48
WIRE 16 48 0 48
WIRE 320 48 304 48
WIRE 384 48 320 48
WIRE 512 48 384 48
WIRE -224 64 -224 48
WIRE 384 64 384 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 320 144 320 48
WIRE 320 144 304 144
WIRE -224 160 -224 144
WIRE 384 160 384 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL cap 368 64 R0
WINDOW 39 24 84 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=.1
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1764A-3.3 160 96 R0
SYMATTR InstName U1
FLAG -224 160 0
FLAG 384 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -224 48 IN
TEXT 368 240 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\4996de7a7335_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
;.op
;.ac dec 1001 1 1G
;.dc V3 -0.5 0.5 1m
RC1 VCC wy1 10k
R3 N004 VEE 10k
Q2 wy2 0 N002 0 BC547C
V2 0 VEE 10
V1 VCC 0 10
R2 N003 VEE 10k
Q1 wy1 N001 N002 0 BC547C
RC2 VCC wy2 10k
R1 0 N003 10k
Q3 N002 N003 N004 0 BC547C
V3 N001 0 AC 1
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1172 1204
WIRE 288 96 288 32
WIRE 288 96 160 96
WIRE 416 96 288 96
WIRE 160 144 160 96
WIRE 416 144 416 96
WIRE 160 288 160 224
WIRE 160 288 48 288
WIRE 416 288 416 224
WIRE 528 288 416 288
WIRE 160 384 160 288
WIRE 416 384 416 288
WIRE -64 432 -112 432
WIRE 96 432 16 432
WIRE 352 432 304 432
WIRE 304 464 304 432
WIRE -112 512 -112 432
WIRE 160 544 160 480
WIRE 368 544 160 544
WIRE 416 544 416 480
WIRE 416 544 368 544
WIRE 160 592 112 592
WIRE 112 624 112 592
WIRE 160 624 160 592
WIRE 960 624 960 544
WIRE 368 688 368 544
WIRE 160 736 160 704
WIRE 304 736 160 736
WIRE 960 768 960 704
WIRE 1152 768 960 768
WIRE 160 800 160 736
WIRE 368 800 368 784
WIRE 1152 832 1152 768
WIRE 960 880 960 768
WIRE 160 944 160 880
WIRE 272 944 160 944
WIRE 368 944 368 880
WIRE 368 944 272 944
WIRE 272 1008 272 944
WIRE 960 1056 960 960
SYMBOL npn 96 384 R0
SYMATTR InstName Q1
SYMATTR Value BC547C
SYMBOL voltage 960 864 R0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL res 144 784 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 352 784 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL voltage 960 608 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL voltage 32 432 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL npn 304 688 R0
SYMATTR InstName Q3
SYMATTR Value BC547C
SYMBOL res 144 608 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL npn 352 384 R0
SYMATTR InstName Q2
SYMATTR Value BC547C
SYMBOL res 144 128 R0
SYMATTR InstName RC1
SYMATTR Value 10k
SYMBOL res 400 128 R0
SYMATTR InstName RC2
SYMATTR Value 10k
FLAG 304 464 0
FLAG 288 32 VCC
FLAG 48 288 wy1
FLAG 528 288 wy2
FLAG -112 512 0
FLAG 112 624 0
FLAG 272 1008 VEE
FLAG 1152 832 0
FLAG 960 544 VCC
FLAG 960 1056 VEE
TEXT -132 1148 Left 2 !;.op
TEXT -134 1168 Left 2 !;.ac dec 1001 1 1G
TEXT -136 1188 Left 2 !;.dc V3 -0.5 0.5 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\1bbb0c3108a2_clamp_cir.asc
* Generated by LTspice 26.0.1 for Windows.
* Limiter / Clamp circuit
V1 W1 0 SINE(0 3 100 0 0 0)
R1 +2 W1 10k
V2 W2 0 0
D2 +2 0 1N914
D1 W2 +2 1N914
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 -16 64 -48
WIRE 64 -16 48 -16
WIRE 208 -16 64 -16
WIRE 432 -16 288 -16
WIRE 448 -16 432 -16
WIRE 64 32 64 -16
WIRE 64 144 64 112
WIRE 432 144 432 -16
WIRE 432 144 240 144
WIRE 240 192 240 144
WIRE 432 192 432 144
WIRE 240 304 240 256
WIRE 240 304 192 304
WIRE 240 320 240 304
WIRE 432 320 432 256
WIRE 240 432 240 400
IOPIN 48 -16 In
IOPIN 64 -48 In
IOPIN 448 -16 In
IOPIN 192 304 In
SYMBOL res 304 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL diode 256 256 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL voltage 64 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 3 100 0 0 0)
SYMBOL diode 416 192 R0
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL voltage 240 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
FLAG 432 320 0
FLAG 64 144 0
FLAG 240 432 0
FLAG 48 -16 W1
FLAG 64 -48 +1
FLAG 448 -16 +2
FLAG 192 304 W2
TEXT 40 -136 Left 2 ;Limiter / Clamp circuit
TEXT -56 240 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1963-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 1K
XU1 IN IN 0 OUT OUT LT1963-1.5 ;pnba _SHDN)IN)GND)OUT)SENSE
C1 OUT 0 10 Rser=50m
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1963-1.5.asy)
.lib LT1963.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 352 48 320 48
WIRE 400 48 352 48
WIRE 560 48 400 48
WIRE -208 64 -208 48
WIRE 400 64 400 48
WIRE 560 64 560 48
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 400 160 400 128
WIRE 560 160 560 144
WIRE 176 240 176 208
FLAG -208 160 0
FLAG 400 160 0
FLAG 560 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 560 48 OUT
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 544 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL PowerProducts\\LT1963-1.5 176 96 R0
SYMATTR InstName U1
SYMBOL cap 384 64 R0
WINDOW 3 40 33 Left 2
WINDOW 39 24 59 Left 2
SYMATTR Value 10
SYMATTR SpiceLine Rser=50m
SYMATTR InstName C1
TEXT 376 216 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\eb9597d8df02_SCHEMATIC.asc
* Generated by LTspice 26.0.1 for Windows.
M1 0 N002 N001 N001 PMOS l=1u w=10u
vsg N001 N002 0.6
vsd N001 0 0.9
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include tsmc180.txt
.dc vsd 0 1.8 0.1 vsg 0.2 1 0.2
* .op
* EDIC WINTER INTERNSHIP\nMohammed Ahmed Majid\nGP5405, 23EEBEA666
* IO Characterstics of PMOS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 0 96 0
WIRE 416 0 256 0
WIRE 416 32 416 0
WIRE 256 96 256 0
WIRE 336 96 256 96
WIRE 256 112 256 96
WIRE 208 128 192 128
WIRE 336 160 336 96
WIRE 336 160 256 160
WIRE 96 192 96 0
WIRE 256 256 256 208
WIRE 368 256 256 256
WIRE 416 256 416 112
WIRE 416 256 368 256
WIRE 192 272 192 128
WIRE 192 272 96 272
WIRE 368 288 368 256
FLAG 368 288 0
SYMBOL pmos4 208 208 M180
WINDOW 123 61 8 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=1u w=10u
SYMBOL voltage 96 176 R0
WINDOW 3 23 109 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vsg
SYMATTR Value 0.6
SYMBOL voltage 416 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vsd
SYMATTR Value 0.9
TEXT -264 0 Left 2 !.include tsmc180.txt
TEXT -264 24 Left 2 !.dc vsd 0 1.8 0.1 vsg 0.2 1 0.2
TEXT -264 48 Left 2 ;.op
TEXT -264 -96 Left 2 ;EDIC WINTER INTERNSHIP\nMohammed Ahmed Majid\nGP5405, 23EEBEA666
TEXT 104 -56 Left 2 ;IO Characterstics of PMOS
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1328.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
XU1 N001 N003 N004 0 N005 +V 0 N002 LT1328 ;pnba IN)FILT)FILT_SW)GND)DATA)VCC)MODE)Vbias
C1 N003 N004 10n Rser=.1
C2 N003 0 330p
C3 0 N002 1000p
I1 N001 0 PULSE(7u 100u 0 10n 10n .5u 1u)
.tran 10u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1328.asy)
.lib LT1328.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -528 -144 -624 -144
WIRE -208 -144 -448 -144
WIRE 64 -144 48 -144
WIRE 144 -144 128 -144
WIRE -272 -80 -352 -80
WIRE -208 -80 -272 -80
WIRE 80 -80 48 -80
WIRE -352 -64 -352 -80
WIRE -208 -16 -272 -16
WIRE 80 -16 48 -16
WIRE -528 0 -528 -16
WIRE -352 16 -352 0
WIRE -208 48 -240 48
WIRE 80 48 48 48
WIRE -528 96 -528 80
FLAG -528 96 0
FLAG -528 -16 +V
FLAG -240 48 0
FLAG 80 -16 +V
FLAG -624 -144 0
FLAG -352 16 0
FLAG 144 -144 0
FLAG 80 -80 0
SYMBOL voltage -528 -16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT1328 -80 -48 R0
SYMATTR InstName U1
SYMBOL cap -288 -80 R0
WINDOW 0 27 13 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMATTR SpiceLine Rser=.1
SYMBOL cap -368 -64 R0
WINDOW 0 27 13 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C2
SYMATTR Value 330p
SYMBOL cap 128 -160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1000p
SYMBOL current -448 -144 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2
WINDOW 123 32 40 VTop 2
WINDOW 39 32 40 VTop 2
SYMATTR InstName I1
SYMATTR Value PULSE(7u 100u 0 10n 10n .5u 1u)
TEXT 80 88 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1073-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1073-5.asy)
C2 OUT 0 100 Rser=0.02
XU1 IN IN N001 0 0 MP_01 MP_02 OUT LT1073 top=904K bot=40K ;pnba Ilim)Vin)SW1)SW2)GND)))FB
L1 IN N001 33 Rser=0.02 Rpar=5000
Rload OUT 0 50
D1 N001 OUT MBRS140
V1 IN 0 2.8
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT1073.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2392 1424
WIRE 1376 912 1216 912
WIRE 1504 912 1376 912
WIRE 1568 912 1504 912
WIRE 1680 912 1648 912
WIRE 1728 912 1680 912
WIRE 1840 912 1792 912
WIRE 1904 912 1840 912
WIRE 1216 928 1216 912
WIRE 1904 928 1904 912
WIRE 1376 960 1376 912
WIRE 1504 960 1504 912
WIRE 1216 1024 1216 1008
WIRE 1904 1024 1904 1008
WIRE 1680 1040 1680 912
WIRE 1680 1040 1568 1040
WIRE 1840 1104 1840 912
WIRE 1840 1104 1568 1104
WIRE 1840 1120 1840 1104
WIRE 1584 1168 1568 1168
WIRE 1840 1200 1840 1184
WIRE 1440 1264 1440 1248
SYMBOL schottky 1728 928 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL res 1888 912 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL PowerProducts\\LT1073-5 1440 1104 R0
SYMATTR InstName U1
SYMBOL POLCAP 1824 1120 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL VOLTAGE 1216 912 R0
SYMATTR InstName V1
SYMATTR Value 2.8
SYMBOL IND 1552 928 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 1584 1168 0
FLAG 1440 1264 0
FLAG 1216 1024 0
FLAG 1904 1024 0
FLAG 1840 1200 0
FLAG 1904 912 OUT
FLAG 1216 912 IN
TEXT 1720 1256 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3025-4.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3025-4.asy)
XU1 IN 0 N001 OUT OUT N001 LTC3025-4 ;pnba BIAS)GND)IN)OUT)Sense)_SHDN
C1 OUT 0 1
Rload OUT 0 3.6
V2 IN 0 3.6
V1 N001 0 PWL(0 0 1 5.5)
.tran 1
.lib LTC3025.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 192 -256 192
WIRE 368 192 336 192
WIRE 432 192 368 192
WIRE 512 192 432 192
WIRE -256 208 -256 192
WIRE 432 208 432 192
WIRE 512 208 512 192
WIRE 32 272 -160 272
WIRE 48 272 32 272
WIRE 368 272 368 192
WIRE 368 272 336 272
WIRE -160 288 -160 272
WIRE -256 304 -256 288
WIRE 432 304 432 272
WIRE 512 304 512 288
WIRE 32 352 32 272
WIRE 48 352 32 352
WIRE 368 352 336 352
WIRE -160 384 -160 368
SYMBOL voltage -160 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 5.5)
SYMBOL voltage -256 192 R0
SYMATTR InstName V2
SYMATTR Value 3.6
SYMBOL cap 416 208 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\LTC3025-4 192 272 R0
SYMATTR InstName U1
SYMBOL res 496 192 R0
SYMATTR InstName Rload
SYMATTR Value 3.6
FLAG 368 352 0
FLAG 512 304 0
FLAG 432 304 0
FLAG -160 384 0
FLAG -256 304 0
FLAG -256 192 IN
FLAG 512 192 OUT
TEXT 432 368 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX15062B.asc
* Generated by LTspice 26.0.1 for Windows.
* Cout Derated
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX15062B.asy)
XU1 LX 0 _RESET 0 IN OUT VCC IN MAX15062B ;pnba LX)GND)_RESET)MODE)Vin)VOUT)VCC)EN/UVLO
Rload OUT 0 16.7
V1 IN 0 24
L1 LX OUT 47 Rser=0.579
R1 VCC _RESET 100k
C1 VCC 0 1
Cout OUT 0 8.9 Rser=2.5m
.tran 8m startup
.lib MAX15062B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 0 -32 -32 -32
WIRE 64 -32 0 -32
WIRE 80 -32 64 -32
WIRE 400 -32 368 -32
WIRE 432 -32 400 -32
WIRE 544 -32 512 -32
WIRE 608 -32 544 -32
WIRE 704 -32 608 -32
WIRE -32 -16 -32 -32
WIRE 608 -16 608 -32
WIRE 704 -16 704 -32
WIRE 64 80 64 -32
WIRE 80 80 64 80
WIRE 400 80 368 80
WIRE 608 80 608 48
WIRE 704 80 704 64
WIRE -32 96 -32 64
WIRE -48 192 -64 192
WIRE 48 192 16 192
WIRE 80 192 48 192
WIRE 544 192 544 -32
WIRE 544 192 368 192
WIRE 80 304 64 304
WIRE 416 304 368 304
WIRE 464 304 416 304
WIRE 560 304 544 304
SYMBOL res 560 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ind 416 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMATTR SpiceLine Rser=0.579
SYMBOL cap 16 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 592 -16 R0
SYMATTR InstName Cout
SYMATTR Value 8.9
SYMATTR SpiceLine Rser=2.5m
SYMBOL res 688 -32 R0
SYMATTR InstName Rload
SYMATTR Value 16.7
SYMBOL MAX15062B 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -32 -32 R0
SYMATTR InstName V1
SYMATTR Value 24
FLAG -32 96 0
FLAG 608 80 0
FLAG 704 80 0
FLAG 0 -32 IN
FLAG 704 -32 OUT
FLAG 64 304 0
FLAG 400 80 0
FLAG -64 192 0
FLAG 48 192 VCC
FLAG 560 304 VCC
FLAG 416 304 _RESET
FLAG 400 -32 LX
TEXT 592 376 Left 2 !.tran 8m startup
TEXT 592 128 Left 2 ;Cout Derated
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1154.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1154.asy)
R2 N004 N003 100K
R3 N006 N005 51K
V1 N001 0 PULSE(0 5 0 1u 1u 5m 10m)
Rload N008 0 10
MQ1 N004 N007 N008 N008 Si9936DY
V3 N005 0 5
R1 N002 N004 .036
V2 N002 0 PWL(0 5 1 16)
C1 N002 N003 .1
XU1 N001 0 N006 0 0 N007 N003 N002 LTC1154 ;pnba IN)_EN)STATUS)GND)SD)G)DS)Vs
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1 startup
.lib LTC1154.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 680
WIRE 16 128 -512 128
WIRE 336 128 304 128
WIRE 544 128 336 128
WIRE 656 128 544 128
WIRE -512 144 -512 128
WIRE 336 144 336 128
WIRE 656 144 656 128
WIRE 16 224 -16 224
WIRE 336 224 336 208
WIRE 336 224 304 224
WIRE 400 224 336 224
WIRE 544 224 544 208
WIRE 544 224 480 224
WIRE -512 240 -512 224
WIRE 544 240 544 224
WIRE 656 240 656 224
WIRE -80 320 -144 320
WIRE 16 320 0 320
WIRE 496 320 304 320
WIRE -144 336 -144 320
WIRE 544 352 544 336
WIRE 16 416 -16 416
WIRE 336 416 304 416
WIRE -144 432 -144 416
WIRE 544 448 544 432
SYMBOL cap 320 144 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL nmos 496 240 R0
WINDOW 0 55 5 Left 2
WINDOW 3 54 62 Left 2
SYMATTR InstName Q1
SYMATTR Value Si9936DY
SYMBOL res 528 112 R0
SYMATTR InstName R1
SYMATTR Value .036
SYMBOL res 496 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL voltage 656 128 R0
WINDOW 123 32 56 VTop 2
WINDOW 39 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value PWL(0 5 1 16)
SYMBOL res 16 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 51K
SYMBOL voltage -512 128 R0
SYMATTR Value PULSE(0 5 0 1u 1u 5m 10m)
SYMATTR InstName V1
SYMBOL res 528 336 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL PowerProducts\\LTC1154 160 272 R0
SYMATTR InstName U1
SYMBOL voltage -144 320 R0
SYMATTR InstName V3
SYMATTR Value 5
FLAG -16 416 0
FLAG -512 240 0
FLAG -16 224 0
FLAG 544 448 0
FLAG 336 416 0
FLAG 656 240 0
FLAG -144 432 0
TEXT 344 504 Left 2 !.tran 1 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1422.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1422.asy)
C1 N002 0 35p
V3 N001 0 10
V1 +V 0 15
V4 N003 0 pulse(0 3.3 0 1u 1u 5m 10m)
V2 -V 0 -15
R1 N002 0 300
XU1 N003 N002 N001 -V 0 +V ADG1422 ;pnba IN)D)S)Vss)GND)Vdd
.tran 30m
.lib ADG1422.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -112 -112 -112 -128
WIRE -464 -48 -464 -64
WIRE -336 -48 -368 -48
WIRE -208 -48 -256 -48
WIRE 48 -48 -16 -48
WIRE 144 -48 48 -48
WIRE 48 -16 48 -48
WIRE 144 0 144 -48
WIRE -208 16 -336 16
WIRE -464 48 -464 32
WIRE 48 80 48 64
WIRE 144 80 144 64
WIRE -336 96 -336 16
WIRE -464 144 -464 128
WIRE -160 144 -160 128
WIRE -64 144 -64 128
WIRE -464 240 -464 224
WIRE -336 240 -336 176
SYMBOL voltage -336 80 R0
WINDOW 3 19 116 Left 2
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMATTR InstName V4
SYMBOL voltage -240 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -464 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL ADG1422 -112 0 R0
SYMATTR InstName U1
SYMBOL cap 128 0 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL voltage -464 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 32 -32 R0
SYMATTR InstName R1
SYMATTR Value 300
FLAG -464 240 0
FLAG -464 48 0
FLAG -464 -64 +V
FLAG -464 128 -V
FLAG -368 -48 0
FLAG -160 144 -V
FLAG -112 -128 +V
FLAG -64 144 0
FLAG -336 240 0
FLAG 48 80 0
FLAG 144 80 0
TEXT 48 232 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\312d42cdc4b5_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ISO7637-2.asy)
R1 N001 NC_01 R
R2 N001 NC_02 R
R3 NC_03 NC_04 R
XU1 NC_05 NC_06 Pulse1_12V ;pnba +)-
.lib ISO7637-2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 0 128 0
WIRE 128 80 128 0
WIRE 224 80 224 0
SYMBOL res 208 64 R0
SYMATTR InstName R2
SYMBOL ISO7637-2 384 0 R0
SYMATTR InstName U1
SYMBOL res 352 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMBOL res 112 64 R0
SYMATTR InstName R1
* Z:\home\khalils\Downloads\files\data\raw_asc\6f29094d76c5_WavQuestion.asc
* Generated by LTspice 26.0.1 for Windows.
* 1 KHz. Relaxation Oscillator
A1 N001 0 0 0 0 N002 0 0 SCHMITT Vhigh=5,Td=7e-9,Trise=2e-9,Vh=.4
C1 N001 0 100n
R1 N002 N001 15K tol=1 pwr=0.1
.tran 0 50m 0 100n
.wave beispiel1.wav 16 44100 V(N001)
.wave beispiel2.wav 16 44100 V(N002)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 304 64 320
WIRE 64 240 64 208
WIRE 64 80 112 80
WIRE 144 320 64 320
WIRE 64 320 64 336
WIRE 240 208 240 80
WIRE 240 80 192 80
WIRE 208 208 240 208
WIRE 144 224 144 320
WIRE 144 208 64 208
WIRE 64 208 64 80
SYMBOL Digital\\schmtinv 144 144 R0
WINDOW 3 15 91 Left 0
SYMATTR Value Vhigh=5,Td=7e-9,Trise=2e-9,Vh=.4
SYMATTR InstName A1
SYMBOL res 208 64 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 15K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL cap 48 240 R0
SYMATTR InstName C1
SYMATTR Value 100n
FLAG 64 336 0
TEXT 238 306 Left 0 !.tran 0 50m 0 100n
TEXT 240 280 Left 0 ;1 KHz. Relaxation Oscillator
TEXT 320 160 Left 0 !.wave beispiel1.wav 16 44100 V(N001)
TEXT 320 192 Left 0 !.wave beispiel2.wav 16 44100 V(N002)