Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL42005-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL42005-2.5.asy)
XU1 IN OUT IN N001 OUT 0 ADPL42005-2.5 ;pnba Vin)Sense)EN)PG)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
V1 IN 0 5
R1 OUT N001 100k
Rload OUT 0 5
.tran 3m startup
.lib ADPL42005-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADPL42005-2.5 224 128 R0
SYMATTR InstName U1
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 288 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1aeeef0a64c3_VNH_Current_sense.asc
* Generated by LTspice 26.0.1 for Windows.
R2 0 N002 680
R3 N004 VNH_CS2 10K
R1 N002 VNH_CS 10K
S1 N003 N002 N001 0 MySwitch
V2 N001 0 PULSE(0 1 0 0 0 0.1ms 1ms)
C2 VNH_CS2 0 10n
I1 0 N003 PULSE(0 1mA 0 0 0 0.1ms 1ms)
V1 N004 0 PULSE(0 630mV 0 0 0 0.01ms 0.05ms)
C1 VNH_CS 0 10n
.tran 0 0.002 0
.model MySwitch SW(Ron=0.0001 Roff=10Meg Vt=0 Vh=0 Lser=0 Vser=0)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1436 680
WIRE 320 -32 320 -64
WIRE 320 64 320 48
WIRE 32 112 -80 112
WIRE 48 112 32 112
WIRE 224 112 128 112
WIRE 304 112 224 112
WIRE 448 112 384 112
WIRE 560 112 528 112
WIRE 32 160 32 112
WIRE 224 160 224 112
WIRE 32 256 32 224
WIRE 224 256 224 240
WIRE 560 256 560 112
WIRE 32 448 -48 448
WIRE 48 448 32 448
WIRE 192 448 128 448
WIRE 32 480 32 448
WIRE 32 560 32 544
WIRE 192 560 192 528
SYMBOL res 144 432 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res 144 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 320 64 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 0 0 0.1ms 1ms)
SYMBOL cap 16 480 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 240 256 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 680
SYMBOL sw 400 112 R90
SYMATTR InstName S1
SYMATTR Value MySwitch
SYMBOL cap 16 160 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage 192 432 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 630mV 0 0 0 0.01ms 0.05ms)
SYMBOL current 528 112 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(0 1mA 0 0 0 0.1ms 1ms)
FLAG 32 256 0
FLAG 224 256 0
FLAG -80 112 VNH_CS
FLAG 32 560 0
FLAG 192 560 0
FLAG -48 448 VNH_CS2
FLAG 560 256 0
FLAG 368 64 0
FLAG 320 -64 0
TEXT -24 352 Left 2 !.tran 0 0.002 0
TEXT 560 40 Left 2 !.model MySwitch SW(Ron=0.0001 Roff=10Meg Vt=0 Vh=0 Lser=0 Vser=0)
* Z:\home\khalils\Downloads\files\data\raw_asc\07e3932f7d56_Draft3.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 12
R3 N001 N002 1527
R4 N004 0 1000
R2 N003 0 10000
R1 N001 N003 10000
M1 N002 N003 N004 N004 N4007
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include 4007.lib
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1072 680
WIRE 256 64 80 64
WIRE 288 64 256 64
WIRE 432 64 368 64
WIRE 432 96 432 64
WIRE 80 144 80 64
WIRE 256 144 256 64
WIRE 256 272 256 224
WIRE 256 272 192 272
WIRE 80 352 80 224
WIRE 144 352 80 352
WIRE 256 368 192 368
WIRE 80 416 80 352
WIRE 256 416 256 368
WIRE 80 544 80 496
WIRE 256 544 256 496
WIRE 256 544 80 544
WIRE 256 576 256 544
SYMBOL res 64 128 R0
SYMATTR InstName R1
SYMATTR Value 10000
SYMBOL res 240 128 R0
SYMATTR InstName R3
SYMATTR Value 1527
SYMBOL res 64 400 R0
SYMATTR InstName R2
SYMATTR Value 10000
SYMBOL nmos 144 272 R0
SYMATTR InstName M1
SYMATTR Value N4007
SYMBOL voltage 272 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 240 400 R0
WINDOW 3 47 72 Left 2
SYMATTR InstName R4
SYMATTR Value 1000
FLAG 432 96 0
FLAG 256 576 0
TEXT 448 328 Left 2 !.include 4007.lib
TEXT -264 240 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\3f6a8a43517e_1844-SD.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1844-SD.asy)
XU2 IN 0 IN N001 OUT LTC1844-SD ;pnba IN)GND)_SHDN)ADJ)OUT
R2 OUT N001 164K
R1 N001 0 100K
I1 OUT 0 {iload} load
V1 IN 0 5
.dc v1 5 2 10m
.measure DC vdrop WHEN V(out)=3.2
.measure DC dropout param Vdrop-3.2
.step param iload list 1u 10m 25m 50m 75m 100m 125m 150m
.lib LTC1844-SD.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1940 1316
WIRE 64 80 -80 80
WIRE 80 80 64 80
WIRE 416 80 368 80
WIRE 560 80 416 80
WIRE -80 96 -80 80
WIRE 560 96 560 80
WIRE 416 112 416 80
WIRE -80 192 -80 176
WIRE 560 192 560 176
WIRE 64 240 64 80
WIRE 80 240 64 240
WIRE 416 240 416 192
WIRE 416 240 368 240
WIRE 416 256 416 240
WIRE 224 304 224 288
WIRE 416 352 416 336
SYMBOL voltage -80 80 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL LTC1844-SD 224 160 R0
SYMATTR InstName U2
SYMBOL res 400 240 R0
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL res 400 96 R0
SYMATTR InstName R2
SYMATTR Value 164K
SYMBOL current 560 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 19 82 Left 2
WINDOW 3 39 36 Left 2
SYMATTR SpiceLine load
SYMATTR InstName I1
SYMATTR Value {iload}
FLAG 224 304 0
FLAG 416 352 0
FLAG -80 192 0
FLAG 560 192 0
FLAG 560 80 OUT
FLAG -80 80 IN
TEXT 744 120 Left 2 !.dc v1 5 2 10m
TEXT 744 208 Left 2 !.measure DC vdrop WHEN V(out)=3.2\n.measure DC dropout param Vdrop-3.2
TEXT 744 160 Left 2 !.step param iload list 1u 10m 25m 50m 75m 100m 125m 150m
* Z:\home\khalils\Downloads\files\data\raw_asc\1c9428612c7f_template1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 0 1k
V1 N002 0 SINE(2 1 1KHz)
V2 VCC 0 5v
XU1 N002 N001 VCC 0 N001 OP727 ;pnba In+)In-)V+)V-)OUT
.tran 1ms
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP727.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 48 -48 48
WIRE 48 96 48 -16
WIRE -48 112 -48 48
WIRE 16 112 -48 112
WIRE 176 128 176 48
WIRE 176 128 80 128
WIRE 16 144 -304 144
WIRE 176 160 176 128
WIRE 48 240 48 160
WIRE -304 288 -304 224
WIRE 176 288 176 240
FLAG 176 288 0
FLAG -304 288 0
FLAG 48 240 0
FLAG 48 -16 VCC
FLAG -304 -48 VCC
FLAG -304 32 0
SYMBOL res 160 144 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -304 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(2 1 1KHz)
SYMBOL voltage -304 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5v
SYMBOL Opamps\\OP727 48 64 R0
SYMATTR InstName U1
TEXT -338 312 Left 2 !.tran 1ms
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7159-02.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7159-02.asy)
R2 N005 0 100K
C2 N002 0 1
XU1 OUT MP_01 OUT N002 N001 N005 N003 N004 IN 0 ADP7158_9 Vreg=2.611 Vref=1.216 ;pnba Vout))Vout_Sense)Byp)EN)Ref_Sense)Ref)Vreg)Vin)GND
C3 OUT 0 10
C1 N004 0 1
R3 IN N001 100K
C4 N003 0 1
R1 N003 N005 66.5K
V1 IN 0 3.0
R4 OUT 0 2.0
.tran 5m startup
.lib ADP7158_9.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -144 32
WIRE 80 32 -32 32
WIRE 416 32 400 32
WIRE 464 32 416 32
WIRE 560 32 464 32
WIRE -144 48 -144 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE 416 128 416 32
WIRE 416 128 400 128
WIRE -144 144 -144 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 0 224 -16 224
WIRE 80 224 64 224
WIRE 464 224 400 224
WIRE 560 224 464 224
WIRE 464 240 464 224
WIRE 560 240 560 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 432 320 400 320
WIRE 560 320 560 304
WIRE 432 336 432 320
WIRE 464 336 464 320
WIRE 464 336 432 336
WIRE 464 352 464 336
WIRE 240 400 240 384
WIRE 464 448 464 432
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 448 336 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL voltage -144 32 R0
SYMATTR InstName V1
SYMATTR Value 3.0
SYMBOL res 544 32 R0
SYMATTR InstName R4
SYMATTR Value 2.0
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 544 240 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 448 48 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL res 448 224 R0
SYMATTR InstName R1
SYMATTR Value 66.5K
SYMBOL ADP7159-02 240 176 R0
SYMATTR InstName U1
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
FLAG 240 400 0
FLAG 560 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG -16 224 0
FLAG -144 144 0
FLAG 560 144 0
FLAG 464 448 0
FLAG -144 32 IN
FLAG 560 32 OUT
TEXT 552 400 Left 2 !.tran 5m startup
* Z:\tmp\asc_dec_bjh7r6w2\178f7a0bf4bc_HWrecFiltt_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 0 1
D1 N002 N003 MUR460
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 160 -16 160
WIRE 192 160 176 160
WIRE 272 160 256 160
WIRE 320 160 272 160
WIRE -16 176 -16 160
WIRE 80 176 80 160
WIRE 176 176 176 160
WIRE 320 176 320 160
WIRE 272 192 272 160
WIRE -16 288 -16 256
WIRE 80 288 80 256
WIRE 176 288 176 256
WIRE 272 288 272 256
WIRE 320 288 320 256
SYMBOL ind2 64 160 R0
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR Type ind
SYMBOL diode 192 144 M90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D1
SYMATTR Value MUR460
FLAG -16 288 0
FLAG 80 288 0
FLAG 176 288 0
FLAG 320 288 0
FLAG 272 288 0
* Z:\tmp\asc_dec_bjh7r6w2\080cc0d086d0_Rotary_Switches_3_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
S1 1 N001 31 0 SW1
S2 2 N001 32 0 SW1
R1 1 0 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2372 1284
WIRE 944 -304 800 -304
WIRE 1168 -304 944 -304
WIRE 1392 -304 1168 -304
WIRE 800 -288 800 -304
WIRE 944 -224 944 -304
WIRE 1168 -224 1168 -304
WIRE 1024 -208 992 -208
WIRE 1248 -208 1216 -208
WIRE 800 -192 800 -208
WIRE 992 -128 992 -160
WIRE 1216 -128 1216 -160
WIRE 944 -80 944 -144
WIRE 976 -80 944 -80
WIRE 1168 -80 1168 -144
WIRE 1200 -80 1168 -80
WIRE 944 -48 944 -80
WIRE 1168 -48 1168 -80
WIRE 944 64 944 32
WIRE 1168 64 1168 32
SYMBOL sw 944 -128 R180
SYMATTR InstName S1
SYMATTR Value SW1
SYMBOL sw 1168 -128 R180
SYMATTR InstName S2
SYMATTR Value SW1
SYMBOL res 928 -64 R0
SYMATTR InstName R1
SYMATTR Value 1
FLAG 944 64 0
FLAG 1168 64 0
FLAG 992 -128 0
FLAG 1216 -128 0
FLAG 1024 -208 31
FLAG 1248 -208 32
FLAG 976 -80 1
FLAG 1200 -80 2
FLAG 800 -192 0
* Z:\home\khalils\Downloads\files\data\raw_asc\684c7e638e74_OTA.asc
* Generated by LTspice 26.0.1 for Windows.
Ci v+ v- {ci} Rser=0
G1 0 io v- v+ {gm}
Ro io 0 {1/go}
Co io 0 {co} Rser=0
.param gm = 1
.param ci = .1p co = .25p go = 1/5Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 80 -64 80
WIRE 48 80 -16 80
WIRE 192 80 96 80
WIRE 272 80 192 80
WIRE 352 80 272 80
WIRE 96 128 96 80
WIRE 192 128 192 80
WIRE 272 128 272 80
WIRE -16 144 -16 80
WIRE 48 144 48 80
WIRE -16 256 -16 208
WIRE -16 256 -64 256
WIRE 48 256 48 192
WIRE 48 256 -16 256
WIRE 96 256 96 208
WIRE 192 256 192 192
WIRE 192 256 96 256
WIRE 272 256 272 208
WIRE 272 256 192 256
IOPIN 352 80 Out
IOPIN -64 80 In
IOPIN -64 256 In
SYMBOL cap 176 128 R0
SYMATTR InstName Co
SYMATTR Value {co}
SYMATTR SpiceLine Rser=0
SYMBOL g2 96 112 R0
SYMATTR InstName G1
SYMATTR Value {gm}
SYMBOL cap -32 144 R0
SYMATTR InstName Ci
SYMATTR Value {ci}
SYMATTR SpiceLine Rser=0
SYMBOL res 256 112 R0
SYMATTR InstName Ro
SYMATTR Value {1/go}
FLAG 352 80 io
FLAG -64 80 v+
FLAG -64 256 v-
FLAG 192 256 0
TEXT -40 288 Left 2 !.param gm = 1
TEXT -40 320 Left 2 !.param ci = .1p co = .25p go = 1/5Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC694.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1086-5.asy)
* Library below included based on ModelFile attribute of instance XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC694.asy)
C1 N001 0 100
R3 N001 N006 10K
V2 N002 0 3 Rser=10m
V4 N004 0 PULSE(0 2 0.4 1u 1u 20m 40m) Rser=0.1
XU3 OUT N001 0 N005 N006 N003 _Reset N002 LTC694 ;pnba Vout)Vcc)GND)PFI)_PFO)WDI)_Reset)Vbatt
XU1 0 N001 IN LT1086-5 ;pnba ADJ)OUT)IN
V1 IN 0 PWL(20u 0 25u 7.5) Rser=10m
R1 IN N005 51K
R4 OUT 0 100
R2 N005 0 10K
V3 N003 N004 PULSE(0 2 0 1u 1u 20m 40m 6) Rser=0.1
.tran 0.7
.lib LT1083.lib
.lib LTC694.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1212 680
WIRE 1136 -144 -336 -144
WIRE -272 -64 -288 -64
WIRE -160 -64 -192 -64
WIRE -128 -64 -160 -64
WIRE 256 -64 224 -64
WIRE 368 -64 336 -64
WIRE 1136 0 1136 -144
WIRE -720 32 -1056 32
WIRE -640 32 -720 32
WIRE -336 32 -336 -144
WIRE -336 32 -384 32
WIRE -128 32 -336 32
WIRE 272 32 224 32
WIRE -1056 48 -1056 32
WIRE -336 48 -336 32
WIRE -720 128 -720 32
WIRE -336 128 -336 112
WIRE -128 128 -144 128
WIRE 400 128 224 128
WIRE 832 128 480 128
WIRE 944 128 912 128
WIRE -1056 144 -1056 128
WIRE -512 176 -512 128
WIRE -720 224 -720 208
WIRE -128 224 -720 224
WIRE 1136 224 1136 80
WIRE 1136 224 224 224
WIRE -720 240 -720 224
WIRE -720 336 -720 320
SYMBOL VOLTAGE 240 -64 R270
WINDOW 123 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value 3
SYMATTR SpiceLine Rser=10m
SYMBOL res -176 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100
SYMBOL cap -352 48 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMBOL VOLTAGE 384 128 R270
WINDOW 123 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 2 0 1u 1u 20m 40m 6)
SYMATTR SpiceLine Rser=0.1
SYMBOL PowerProducts\\LT1086-5 -512 32 R0
SYMATTR InstName U1
SYMBOL VOLTAGE -1056 32 R0
WINDOW 123 24 117 Left 2
SYMATTR Value PWL(20u 0 25u 7.5)
SYMATTR InstName V1
SYMATTR SpiceLine Rser=10m
SYMBOL LTC694 48 96 R0
SYMATTR InstName U3
SYMBOL res -736 112 R0
SYMATTR InstName R1
SYMATTR Value 51K
SYMBOL res -736 224 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL VOLTAGE 816 128 R270
WINDOW 123 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V4
SYMATTR Value PULSE(0 2 0.4 1u 1u 20m 40m)
SYMATTR SpiceLine Rser=0.1
SYMBOL res 1120 -16 R0
SYMATTR InstName R3
SYMATTR Value 10K
FLAG -144 128 0
FLAG -160 -64 OUT
FLAG -1056 144 0
FLAG -336 128 0
FLAG -512 176 0
FLAG -1056 32 IN
FLAG 368 -64 0
FLAG -288 -64 0
FLAG -720 336 0
FLAG 272 32 _Reset
FLAG 944 128 0
TEXT 504 288 Left 2 !.tran 0.7
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6252.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6252.asy)
V4 IN 0 SINE(2.5 1 250K)
V2 +V 0 5
XU1 OUT 0 IN OUT NC_01 +V LTC6252 ;pnba 1)2)3)4)5)6
.tran 500u
.lib LTC6252.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 656 -1200 512 -1200
WIRE 560 -1136 560 -1152
WIRE 240 -1120 240 -1136
WIRE 512 -1120 512 -1200
WIRE 544 -1120 512 -1120
WIRE 656 -1104 656 -1200
WIRE 656 -1104 608 -1104
WIRE 736 -1104 656 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 560 -1056 560 -1072
WIRE 240 -1024 240 -1040
WIRE 432 -976 432 -992
SYMBOL LTC6252 576 -1104 R0
WINDOW 3 35 19 Left 2
WINDOW 0 40 -14 Left 2
SYMATTR InstName U1
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V4
SYMATTR Value SINE(2.5 1 250K)
SYMBOL voltage 240 -1136 R0
SYMATTR InstName V2
SYMATTR Value 5
FLAG 240 -1136 +V
FLAG 240 -1024 0
FLAG 432 -976 0
FLAG 736 -1104 OUT
FLAG 560 -1056 0
FLAG 432 -1088 IN
FLAG 560 -1152 +V
TEXT 720 -992 Left 2 !.tran 500u
* Z:\home\khalils\Downloads\files\data\raw_asc\2660db64d82c_ADA4177.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -15
XU1 IN N001 +V -V OUT ADA4177 ;pnba In+)In-)V+)V-)OUT
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4177.asy)
.lib ADA4177.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 512 -1232 496 -1232
WIRE 544 -1232 512 -1232
WIRE 656 -1232 624 -1232
WIRE 128 -1136 128 -1152
WIRE 240 -1136 240 -1152
WIRE 512 -1120 512 -1232
WIRE 544 -1120 512 -1120
WIRE 656 -1104 656 -1232
WIRE 656 -1104 608 -1104
WIRE 720 -1104 656 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 128 -1040 128 -1056
WIRE 240 -1040 240 -1056
WIRE 432 -976 432 -992
FLAG 128 -1152 +V
FLAG 128 -1040 0
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 240 -1152 -V
FLAG 576 -1072 -V
FLAG 400 -1232 0
FLAG 240 -1040 0
SYMBOL voltage 128 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 240 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL OpAmps\\ADA4177 576 -1104 R0
SYMATTR InstName U1
TEXT 704 -992 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\13ddae750e5d_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
+ 10,33k, 11,47k, 12,68k, 13,100k, 14,150k, 15,220k, 16,330k, 17,470k, 18,680k, 19,1meg)
+ 10,33k, 11,47k, 12,68k, 13,100k, 14,150k, 15,220k, 16,330k, 17,470k, 18,680k, 19,1meg)
+ 10,33k, 11,47k, 12,68k, 13,100k, 14,150k, 15,220k, 16,330k, 17,470k, 18,680k, 19,1meg)
+ 10,33k, 11,47k, 12,68k, 13,100k, 14,150k, 15,220k, 16,330k, 17,470k, 18,680k, 19,1meg)
V1 N001 0 9
R1 N001 N002 {RA}
R4 N004 0 {RD}
R2 N002 N003 {RB}
R3 N003 N004 {RC}
.param RA=table(ram4 , 1,1k, 2,1.5k, 3,2.2k, 4,3.3k, 5,4.7k, 6,6.8k, 7,10k, 8,15k, 9,22k,
.param ram1=int(mc(6.5,1)+7)
.param ram2=int(mc(6.5,1)+7)
.param ram3=int(mc(6.2,1)+7)
.param ram4=int(mc(6.5,1)+7)
.param RB=table(ram3 , 1,1k, 2,1.5k, 3,2.2k, 4,3.3k, 5,4.7k, 6,6.8k, 7,10k, 8,15k, 9,22k,
.param RC=table(ram2 , 1,1k, 2,1.5k, 3,2.2k, 4,3.3k, 5,4.7k, 6,6.8k, 7,10k, 8,15k, 9,22k,
.param RD=table(ram1 , 1,1k, 2,1.5k, 3,2.2k, 4,3.3k, 5,4.7k, 6,6.8k, 7,10k, 8,15k, 9,22k,
.op
.meas OP RA_val PARAM RA
.step param iterations 0 100 1
.meas OP RB_val PARAM RB
.meas OP RC_val PARAM RC
.meas OP RD_val PARAM RD
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1056 680
WIRE -1200 -32 -1424 -32
WIRE -1424 -16 -1424 -32
WIRE -1200 112 -1200 48
WIRE -1200 272 -1200 192
WIRE -1200 400 -1200 352
SYMBOL res -1216 -48 R0
SYMATTR InstName R1
SYMATTR Value {RA}
SYMBOL res -1216 96 R0
SYMATTR InstName R2
SYMATTR Value {RB}
SYMBOL voltage -1424 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL res -1216 384 R0
SYMATTR InstName R4
SYMATTR Value {RD}
SYMBOL res -1216 256 R0
SYMATTR InstName R3
SYMATTR Value {RC}
FLAG -1200 480 0
FLAG -1424 64 0
TEXT -824 64 Left 2 !.param RA=table(ram4 ,  1,1k,  2,1.5k,  3,2.2k,  4,3.3k,  5,4.7k,  6,6.8k,  7,10k,  8,15k,  9,22k,  \n+  10,33k,  11,47k,  12,68k,  13,100k, 14,150k,  15,220k,  16,330k,  17,470k,  18,680k,  19,1meg)
TEXT 688 248 Left 2 !.param ram1=int(mc(6.5,1)+7)
TEXT 688 192 Left 2 !.param ram2=int(mc(6.5,1)+7)
TEXT 688 136 Left 2 !.param ram3=int(mc(6.2,1)+7)
TEXT 688 88 Left 2 !.param ram4=int(mc(6.5,1)+7)
TEXT -824 120 Left 2 !.param RB=table(ram3 ,  1,1k,  2,1.5k,  3,2.2k,  4,3.3k,  5,4.7k,  6,6.8k,  7,10k,  8,15k,  9,22k,  \n+  10,33k,  11,47k,  12,68k,  13,100k, 14,150k,  15,220k,  16,330k,  17,470k,  18,680k,  19,1meg)
TEXT -824 184 Left 2 !.param RC=table(ram2 ,  1,1k,  2,1.5k,  3,2.2k,  4,3.3k,  5,4.7k,  6,6.8k,  7,10k,  8,15k,  9,22k,  \n+  10,33k,  11,47k,  12,68k,  13,100k, 14,150k,  15,220k,  16,330k,  17,470k,  18,680k,  19,1meg)
TEXT -824 240 Left 2 !.param RD=table(ram1 ,  1,1k,  2,1.5k,  3,2.2k,  4,3.3k,  5,4.7k,  6,6.8k,  7,10k,  8,15k,  9,22k,  \n+  10,33k,  11,47k,  12,68k,  13,100k, 14,150k,  15,220k,  16,330k,  17,470k,  18,680k,  19,1meg)
TEXT -488 -216 Left 2 !.op
TEXT -840 440 Left 2 !.meas OP RA_val PARAM RA
TEXT -704 -72 Left 2 !.step param iterations 0 100 1
TEXT -496 440 Left 2 !.meas OP RB_val PARAM RB
TEXT -160 440 Left 2 !.meas OP RC_val PARAM RC
TEXT 176 440 Left 2 !.meas OP RD_val PARAM RD
* Z:\home\khalils\Downloads\files\data\raw_asc\d4c73f554478_TS0.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 V1 {R3}
C1 N002 N003 {1/R3}
V1 V1 N003 SINE(0 1 0 0 0 0 1000) AC 1 0
R2 V2 N001 {R3}
XU1 N001 N002 V2 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R3 0 N002 {R3}
.ac dec 100 .1 10
.param R3=1
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 888 680
WIRE 208 32 64 32
WIRE 352 32 288 32
WIRE 640 32 352 32
WIRE 752 32 720 32
WIRE 64 96 64 32
WIRE 352 128 352 32
WIRE 400 128 352 128
WIRE 752 144 752 32
WIRE 752 144 464 144
WIRE 800 144 752 144
WIRE 400 160 352 160
WIRE 64 240 64 176
WIRE 160 240 64 240
WIRE 256 240 224 240
WIRE 352 240 352 160
WIRE 352 240 256 240
WIRE 256 288 256 240
WIRE 256 400 256 368
IOPIN 64 32 In
IOPIN 800 144 Out
SYMBOL voltage 64 80 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 24 152 Left 2
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 0 0 0 0 1000)
SYMBOL res 736 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R3}
SYMBOL res 304 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R3}
SYMBOL OpAmps\\opamp 432 80 R0
SYMATTR InstName U1
SYMBOL cap 224 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {1/R3}
SYMBOL res 272 384 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value {R3}
FLAG 256 400 0
FLAG 64 32 V1
FLAG 800 144 V2
TEXT 488 272 Left 2 !.ac dec 100 .1 10
TEXT 496 312 Left 2 !.param R3=1
TEXT 496 344 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\235855e9681d_Fig_2-81_F-Source.asc
* Generated by LTspice 26.0.1 for Windows.
F1 0 N002 V1 -2
R2 N002 0 1
V1 N001 0 SINE(0 1 1K)
R1 N001 0 100
.tran 3m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 112 176 112
WIRE 176 144 176 112
WIRE 272 144 272 112
WIRE 368 144 320 144
WIRE 480 144 448 144
WIRE 624 144 560 144
WIRE 176 256 176 224
WIRE 224 256 176 256
WIRE 272 256 272 224
WIRE 272 256 224 256
WIRE 224 272 224 256
SYMBOL res 464 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL f 368 144 R270
WINDOW 0 32 40 VTop 2
WINDOW 3 -32 40 VBottom 2
SYMATTR InstName F1
SYMATTR Value V1 -2
SYMBOL res 192 128 M0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 272 128 M0
WINDOW 3 -123 148 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value SINE(0 1 1K)
SYMATTR InstName V1
FLAG 624 144 0
FLAG 320 144 0
FLAG 224 272 0
TEXT 448 280 Left 2 !.tran 3m