Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1981.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 3.3
V2 N003 0 PULSE(0 3 0 100n 100n 2.5m 5m)
MQ1 N001 N004 N005 N005 Si4838DY
R1 0 N005 10
XU1 N002 0 N003 N004 N001 LTC1981 ;pnba GDR)GND)_SHDN)Gate)Vcc
R2 N001 N002 100K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1981.asy)
.lib LTC1981.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 336 0 -48 0
WIRE -48 16 -48 0
WIRE -48 112 -48 96
WIRE 32 112 -48 112
WIRE 336 112 336 0
WIRE 336 112 256 112
WIRE 544 112 336 112
WIRE 544 128 544 112
WIRE 32 192 0 192
WIRE 336 192 336 112
WIRE 544 224 544 208
WIRE 32 272 -176 272
WIRE 288 272 256 272
WIRE -176 288 -176 272
WIRE 336 320 336 288
WIRE -176 384 -176 368
WIRE 336 416 336 400
FLAG 544 224 0
FLAG 0 192 0
FLAG -176 384 0
FLAG 336 416 0
SYMBOL voltage 544 112 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage -176 272 R0
SYMATTR Value PULSE(0 3 0 100n 100n 2.5m 5m)
SYMATTR InstName V2
SYMBOL nmos 288 192 R0
WINDOW 3 53 80 Left 2
SYMATTR Value Si4838DY
SYMATTR InstName Q1
SYMBOL res 352 416 R180
WINDOW 0 -35 89 Left 2
WINDOW 3 -33 43 Left 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL LTC1981 144 192 R0
SYMATTR InstName U1
SYMBOL res -64 0 R0
SYMATTR InstName R2
SYMATTR Value 100K
TEXT 440 352 Left 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3630.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3630.asy)
XU1 N001 MP_01 IN MP_02 N002 N003 0 0 OUT N003 NC_03 NC_04 LTC3630 ;pnba SW))Vin))Run)Vprg2)Vprg1)GND)FB)SS)Iset)FBO
R2 N002 0 15K
R1 IN N002 200K
C1 OUT 0 100 x2 V=4 Irms=1.5 Rser=0.04 Lser=0 mfg="KEMET" pn="T520B107M004ASE040" type="Tantalum"
Rload OUT 0 6.6
L1 N001 OUT 47 Rser=50m
V1 IN 0 24
.tran 5m startup
.lib LTC3630.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 32 -112 32
WIRE 96 32 -16 32
WIRE 416 32 384 32
WIRE 528 32 496 32
WIRE 576 32 528 32
WIRE 688 32 576 32
WIRE -112 48 -112 32
WIRE 576 48 576 32
WIRE 688 48 688 32
WIRE -16 128 -16 112
WIRE 96 128 -16 128
WIRE 528 128 528 32
WIRE 528 128 384 128
WIRE -112 144 -112 128
WIRE -16 144 -16 128
WIRE 576 144 576 112
WIRE 688 144 688 128
WIRE 96 224 80 224
WIRE 432 224 384 224
WIRE -16 240 -16 224
WIRE 96 320 80 320
WIRE 400 416 384 416
WIRE 80 480 80 320
WIRE 432 480 432 224
WIRE 432 480 80 480
SYMBOL ind 400 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMATTR SpiceLine Rser=50m
SYMBOL res 672 32 R0
SYMATTR InstName Rload
SYMATTR Value 6.6
SYMBOL PowerProducts\\LTC3630 240 224 R0
SYMATTR InstName U1
SYMBOL res -32 128 R0
SYMATTR InstName R2
SYMATTR Value 15K
SYMBOL res -32 16 R0
SYMATTR InstName R1
SYMATTR Value 200K
SYMBOL voltage -112 32 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL polcap 560 48 R0
WINDOW 3 38 37 Left 2
WINDOW 123 23 64 Left 2
SYMATTR Value 100
SYMATTR Value2 x2
SYMATTR InstName C1
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=4 Irms=1.5 Rser=0.04 Lser=0 mfg="KEMET" pn="T520B107M004ASE040" type="Tantalum"
FLAG 400 416 0
FLAG 80 224 0
FLAG -112 144 0
FLAG 576 144 0
FLAG 688 144 0
FLAG -112 32 IN
FLAG 688 32 OUT
FLAG -16 240 0
TEXT 512 304 Left 2 !.tran 5m startup
* Z:\tmp\asc_dec_bjh7r6w2\009a2771507c_Active-Low-Pass-Buttersworth-Filter_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N002 N003 Vp Vm Vout level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N002 N001 110k
R3 Vout N003 845
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 916 680
WIRE -144 32 -304 32
WIRE 80 32 -80 32
WIRE -304 128 -304 32
WIRE -304 128 -352 128
WIRE -256 128 -304 128
WIRE -128 128 -176 128
WIRE -16 128 -128 128
WIRE 80 144 80 32
WIRE 80 144 48 144
WIRE 160 144 80 144
WIRE -128 160 -128 128
WIRE -16 160 -48 160
WIRE 80 192 80 144
WIRE -128 256 -128 224
WIRE -48 288 -48 160
WIRE 80 288 80 272
WIRE 80 288 -48 288
WIRE 80 304 80 288
SYMBOL OpAmps\\UniversalOpAmp 16 144 M180
SYMATTR InstName U1
SYMBOL res -160 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 110k
SYMBOL res 64 176 R0
SYMATTR InstName R3
SYMATTR Value 845
FLAG -128 256 0
FLAG 16 176 Vp
FLAG 16 112 Vm
FLAG 160 144 Vout
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1706-82.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1706-82.asy)
V1 N001 0 3.3
V7 N008 0 PULSE(0 2.4 0 1n 1n 8m 16m)
V5 N005 0 PULSE(0 2.4 0 1n 1n 2m 4m)
C1 OUT 0 .1
G1 0 OUT N007 N004 1
V2 N007 0 .8
XU1 N005 N006 N001 0 N004 OUT N002 N003 N008 LTC1706-82 ;pnba VID2)VID3)Vcc)GND)FB)Sense)VID0)VID1)VID4
V3 N002 0 PULSE(0 2.4 0 1n 1n .5m 1m)
V4 N003 0 PULSE(0 2.4 0 1n 1n 1m 2m)
V6 N006 0 PULSE(0 2.4 0 1n 1n 4m 8m)
.tran 16m
.lib LTC1706-82.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2536 1332
WIRE 944 736 864 736
WIRE 1328 736 944 736
WIRE 864 752 864 736
WIRE 1168 784 1008 784
WIRE 1008 800 1008 784
WIRE 1168 816 1168 784
WIRE 1328 816 1328 736
WIRE 864 832 864 816
WIRE 1856 880 1392 880
WIRE 1008 896 1008 880
WIRE 1856 896 1856 880
WIRE 1744 928 1392 928
WIRE 1744 960 1744 928
WIRE 1104 976 992 976
WIRE 1632 976 1392 976
WIRE 944 992 944 736
WIRE 1856 992 1856 976
WIRE 992 1008 992 976
WIRE 1632 1008 1632 976
WIRE 1536 1024 1392 1024
WIRE 1536 1056 1536 1024
WIRE 1744 1056 1744 1040
WIRE 992 1072 992 1056
WIRE 1440 1072 1392 1072
WIRE 1632 1104 1632 1088
WIRE 1440 1120 1440 1072
WIRE 1248 1136 1248 1120
WIRE 1536 1152 1536 1136
WIRE 944 1168 944 1072
WIRE 992 1168 992 1152
WIRE 1440 1216 1440 1200
SYMBOL g2 944 976 M0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL voltage 1008 784 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage 1856 880 R0
SYMATTR InstName V3
SYMATTR Value PULSE(0 2.4 0 1n 1n .5m 1m)
SYMBOL voltage 1536 1040 R0
SYMATTR InstName V6
SYMATTR Value PULSE(0 2.4 0 1n 1n 4m 8m)
SYMBOL voltage 1744 944 R0
SYMATTR InstName V4
SYMATTR Value PULSE(0 2.4 0 1n 1n 1m 2m)
SYMBOL voltage 1440 1104 R0
SYMATTR InstName V7
SYMATTR Value PULSE(0 2.4 0 1n 1n 8m 16m)
SYMBOL cap 848 752 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL voltage 992 1056 R0
SYMATTR InstName V2
SYMATTR Value .8
SYMBOL PowerProducts\\LTC1706-82 1248 976 R0
SYMATTR InstName U1
SYMBOL voltage 1632 992 R0
SYMATTR InstName V5
SYMATTR Value PULSE(0 2.4 0 1n 1n 2m 4m)
FLAG 1008 896 0
FLAG 1248 1136 0
FLAG 992 1168 0
FLAG 944 1168 0
FLAG 1856 992 0
FLAG 1744 1056 0
FLAG 1632 1104 0
FLAG 1536 1152 0
FLAG 864 832 0
FLAG 864 736 OUT
FLAG 1440 1216 0
TEXT 1904 1184 Left 2 !.tran 16m
* Z:\home\khalils\Downloads\files\data\raw_asc\RH117H.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\RH117H.asy)
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1009.asy)
XU1 N001 OUT IN RH117H ;pnba ADJ)OUT)IN
V1 IN 0 SINE(10 100m 100K)
R1 OUT N001 121
Rload OUT 0 10
XU2 N002 0 NC_01 LT1009 ;pnba VCC)VEE)ADJ
R2 N001 N002 121
.tran 50u
.options plotwinsize=0
.lib LTC.lib
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 680
WIRE 64 128 -256 128
WIRE 368 128 320 128
WIRE 512 128 368 128
WIRE -256 144 -256 128
WIRE 512 144 512 128
WIRE 368 160 368 128
WIRE -256 240 -256 224
WIRE 512 240 512 224
WIRE 192 256 192 224
WIRE 368 256 368 240
WIRE 368 256 192 256
WIRE 368 288 368 256
WIRE 368 384 368 368
WIRE 368 464 368 448
SYMBOL res 352 144 R0
SYMATTR InstName R1
SYMATTR Value 121
SYMBOL RH117H 192 128 R0
SYMATTR InstName U1
SYMBOL res 496 128 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL res 352 272 R0
SYMATTR InstName R2
SYMATTR Value 121
SYMBOL voltage -256 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(10 100m 100K)
SYMBOL References\\LT1009 368 416 R0
SYMATTR InstName U2
FLAG -256 240 0
FLAG 512 240 0
FLAG 368 464 0
FLAG -256 128 IN
FLAG 512 128 OUT
TEXT 496 336 Left 2 !.tran 50u\n.options plotwinsize=0
* Z:\tmp\asc_dec_bjh7r6w2\089413953cd8_Cohn_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
L4 N002 N006 {2*L}
R1 IN N004 {R}
C2 IN 0 {C2}
C3 N003 OUT {C1}
C1 N001 IN {C1}
V1 N004 0 AC 2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2300 1728
WIRE 1360 1168 1232 1168
WIRE 1664 1168 1536 1168
WIRE 1760 1168 1664 1168
WIRE 2080 1168 1952 1168
WIRE 1232 1184 1232 1168
WIRE 2080 1184 2080 1168
WIRE 1360 1200 1360 1168
WIRE 1760 1200 1760 1168
WIRE 1952 1200 1952 1168
WIRE 1664 1280 1664 1168
WIRE 1072 1296 1024 1296
WIRE 1184 1296 1152 1296
WIRE 1232 1296 1232 1248
WIRE 1232 1296 1184 1296
WIRE 1360 1296 1360 1280
WIRE 1456 1296 1360 1296
WIRE 1760 1296 1760 1280
WIRE 1872 1296 1760 1296
WIRE 1952 1296 1952 1280
WIRE 1952 1296 1872 1296
WIRE 2080 1296 2080 1248
WIRE 2240 1296 2080 1296
WIRE 2240 1312 2240 1296
WIRE 1024 1328 1024 1296
WIRE 1232 1328 1232 1296
WIRE 1872 1328 1872 1296
WIRE 2080 1328 2080 1296
WIRE 1024 1424 1024 1408
WIRE 1232 1424 1232 1392
WIRE 1664 1424 1664 1344
SYMBOL ind 1744 1184 R0
SYMATTR InstName L4
SYMATTR Value {2*L}
SYMBOL RES 1168 1280 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL cap 1216 1328 R0
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL cap 2064 1184 R0
SYMATTR InstName C3
SYMATTR Value {C1}
SYMBOL cap 1216 1184 R0
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL VOLTAGE 1024 1312 R0
WINDOW 3 25 97 Left 0
SYMATTR Value AC 2
SYMATTR InstName V1
FLAG 1232 1424 0
FLAG 1024 1424 0
FLAG 2240 1296 OUT
FLAG 1184 1296 IN
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8053.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8053.asy)
V1 IN 0 24
Rload OUT 0 3
C1 OUT 0 100 Rser=10m
R1 N003 0 41.2K
XU1 N001 IN N001 IN NC_01 N003 N002 OUT 0 0 N004 NC_02 LTM8053 ;pnba BIAS)RUN)AUX)VIN)SHARE)RT)TR/SS)VOUT)GND)SYNC)FB)PG
R2 0 N004 60.4K
C2 N002 0 0.001
.tran 1m startup
.lib LTM8053.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 -64 -144 -64
WIRE 192 -64 0 -64
WIRE -144 -48 -144 -64
WIRE 192 -32 192 -64
WIRE 0 0 0 -64
WIRE 32 0 0 0
WIRE 384 0 352 0
WIRE -144 48 -144 32
WIRE 32 64 16 64
WIRE 384 64 384 0
WIRE 384 64 352 64
WIRE -64 128 -96 128
WIRE 32 128 0 128
WIRE 544 128 352 128
WIRE 656 128 544 128
WIRE 544 144 544 128
WIRE 656 144 656 128
WIRE 544 240 544 208
WIRE 656 240 656 224
WIRE -80 256 -96 256
WIRE 32 256 0 256
WIRE 368 256 352 256
WIRE 464 256 448 256
WIRE 192 320 192 304
SYMBOL res 16 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 41.2K
SYMBOL LTM8053 192 144 R0
SYMATTR InstName U1
SYMBOL voltage -144 -64 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 464 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 60.4K
SYMBOL res 640 128 R0
SYMATTR InstName Rload
SYMATTR Value 3
SYMBOL cap 0 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 0.001
SYMBOL cap 528 144 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMATTR SpiceLine Rser=10m
FLAG -144 48 0
FLAG -96 256 0
FLAG 192 320 0
FLAG 656 240 0
FLAG -144 -64 IN
FLAG 656 128 OUT
FLAG 544 240 0
FLAG 16 64 0
FLAG -96 128 0
FLAG 464 256 0
TEXT 392 352 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\3348241c1bb5_RL.asc
* Generated by LTspice 26.0.1 for Windows.
R out 0 1200
L N001 out 1
V0 N001 0 SINE(0 AC 1 1.9)
.ac dec 100 1.9 1900000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 96 96 96
WIRE 304 96 256 96
WIRE 304 128 304 96
WIRE 96 144 96 96
WIRE 304 224 304 208
IOPIN 304 96 Out
SYMBOL res 288 112 R0
SYMATTR InstName R
SYMATTR Value 1200
SYMBOL ind 160 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L
SYMATTR Value 1
SYMBOL voltage 96 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -40 127 Left 2
SYMATTR InstName V0
SYMATTR Value SINE(0 AC 1 1.9)
FLAG 96 224 0
FLAG 304 224 0
FLAG 304 96 out
TEXT 176 32 Left 2 !.ac dec 100 1.9 1900000
* Z:\home\khalils\Downloads\files\data\raw_asc\1ae695552e20_2_resistenze.asc
* Generated by LTspice 26.0.1 for Windows.
R2 0 N002 2000
R1 N002 N001 1000
V1 N001 0 10
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 112 48 112
WIRE 208 112 160 112
WIRE 336 112 288 112
WIRE 48 240 48 112
WIRE 128 240 48 240
WIRE 336 240 336 112
WIRE 336 240 208 240
WIRE 336 272 336 240
SYMBOL res 304 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 2000
SYMBOL voltage 112 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 176 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
FLAG 336 272 0
TEXT 46 306 Left 2 !.op
* Z:\tmp\asc_dec_bjh7r6w2\0b22dd78401b_3_diff_pair_cs-as-opamp-step_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
C2 vout 0 0.5p
C1 vout 0 0.5p
R2 vout N001 10Meg
Mp1 vgatep vgatep VDD VDD PMOS-SH l=1u w=10u
VCM vin 0 SINE(0 100m 1k 0) AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1092 740
WIRE -752 -64 -976 -64
WIRE -672 -64 -752 -64
WIRE -560 -64 -672 -64
WIRE -320 -64 -560 -64
WIRE -672 0 -672 -64
WIRE -512 16 -624 16
WIRE -480 16 -512 16
WIRE -368 16 -480 16
WIRE -752 48 -752 -64
WIRE -672 48 -752 48
WIRE 224 80 144 80
WIRE 288 80 224 80
WIRE 416 80 368 80
WIRE 480 80 416 80
WIRE 672 80 560 80
WIRE 736 80 672 80
WIRE 0 128 0 -64
WIRE 0 128 -48 128
WIRE -672 176 -672 96
WIRE -512 176 -512 16
WIRE -512 176 -672 176
WIRE 224 192 224 80
WIRE 736 192 736 80
WIRE -672 224 -672 176
WIRE -592 272 -672 272
WIRE -48 288 -48 176
WIRE 48 288 -48 288
WIRE 144 288 144 80
WIRE 144 288 48 288
WIRE 224 288 224 256
WIRE 144 304 144 288
WIRE 736 320 736 272
WIRE -592 384 -592 272
WIRE 144 400 144 368
WIRE -48 432 -48 288
WIRE 0 480 -48 480
WIRE 0 624 0 480
WIRE 416 736 416 80
SYMBOL cap 128 304 R0
SYMATTR InstName C2
SYMATTR Value 0.5p
SYMBOL cap 208 192 R0
SYMATTR InstName C1
SYMATTR Value 0.5p
SYMBOL res 272 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 10Meg
SYMBOL pmos4 -624 96 R180
WINDOW 123 56 100 Left 2
SYMATTR Value2 l=1u w=10u
SYMATTR InstName Mp1
SYMATTR Value PMOS-SH
SYMBOL voltage 736 176 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName VCM
SYMATTR Value SINE(0 100m 1k 0)
FLAG 736 320 0
FLAG 224 288 0
FLAG -480 16 vgatep
FLAG -560 -64 VDD
FLAG 144 400 0
FLAG 48 288 vout
FLAG 672 80 vin
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1574.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1574.asy)
Rload OUT 0 15
XU1 N002 MP_01 MP_02 0 N001 IN IN IN LTC1574 top=1K bot=1T ;pnba FB)))GND)SW)Vin)Ipgm)_SHDN
R1 N002 0 31.5K
C1 OUT 0 100 Rser=0.02
V1 IN 0 9
L1 N001 OUT 100 Rser=0.02 Rpar=5000
R2 OUT N002 93.5K
.tran 3m startup
.lib LTC1574.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1492 912
WIRE 480 528 384 528
WIRE 624 528 480 528
WIRE 384 544 384 528
WIRE 624 544 624 528
WIRE 784 560 768 560
WIRE 896 560 864 560
WIRE 1024 560 896 560
WIRE 1120 560 1024 560
WIRE 896 576 896 560
WIRE 1024 576 1024 560
WIRE 1120 576 1120 560
WIRE 480 608 480 528
WIRE 496 608 480 608
WIRE 768 608 768 560
WIRE 768 608 752 608
WIRE 384 640 384 624
WIRE 480 672 480 608
WIRE 496 672 480 672
WIRE 896 672 896 656
WIRE 896 672 752 672
WIRE 1024 672 1024 640
WIRE 1120 672 1120 656
WIRE 896 688 896 672
WIRE 624 768 624 736
SYMBOL RES 880 560 R0
SYMATTR InstName R2
SYMATTR Value 93.5K
SYMBOL RES 880 672 R0
SYMATTR InstName R1
SYMATTR Value 31.5K
SYMBOL POLCAP 1008 576 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL RES 1104 560 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL POWERPRODUCTS\\LTC1574 624 624 R0
SYMATTR InstName U1
SYMBOL IND 768 576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL VOLTAGE 384 528 R0
SYMATTR InstName V1
SYMATTR Value 9
FLAG 1120 560 OUT
FLAG 1024 672 0
FLAG 1120 672 0
FLAG 624 768 0
FLAG 896 768 0
FLAG 384 640 0
FLAG 384 528 IN
TEXT 1064 720 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\05ed3dd5cbcc_VA-R3-DEMO.asc
* Generated by LTspice 26.0.1 for Windows.
R1 b 0 500
V1 a 0
D1 b a RR2L4S
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0 100
.step temp list -13 37
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 128 -144 128
WIRE 240 128 80 128
WIRE -144 192 -144 128
WIRE 240 192 240 128
WIRE -144 352 -144 272
WIRE 48 352 -144 352
WIRE 240 352 240 272
WIRE 240 352 48 352
WIRE 48 368 48 352
SYMBOL Misc\\EuropeanResistor 224 176 R0
SYMATTR InstName R1
SYMATTR Value 500
SYMBOL diode 80 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value RR2L4S
SYMBOL voltage -144 176 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value ""
SYMATTR InstName V1
FLAG -144 128 a
FLAG 240 128 b
FLAG 48 368 0
TEXT -144 392 Left 2 !.dc V1 0 100
TEXT -152 424 Left 2 !.step temp list -13 37
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6656-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6656-2.5.asy)
V1 N001 0 PWL(0 0 1m 0 +100n 3)
C1 N002 0 1
XU1 0 N001 N002 LT6656-2.5 ;pnba GND)IN)OUT
.tran 20m
.lib LT6656-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 836
WIRE 96 160 -176 160
WIRE 480 160 320 160
WIRE -176 176 -176 160
WIRE 480 176 480 160
WIRE 208 256 208 224
WIRE 480 256 480 240
WIRE -176 272 -176 256
SYMBOL voltage -176 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m 0 +100n 3)
SYMBOL cap 464 176 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL LT6656-2.5 208 160 R0
SYMATTR InstName U1
FLAG 480 256 0
FLAG 208 256 0
FLAG -176 272 0
TEXT 344 304 Left 2 !.tran 20m
* Z:\home\khalils\Downloads\files\data\raw_asc\34db140b21c4_3PhaseRect.asc
* Generated by LTspice 26.0.1 for Windows.
* This is a 3-Phase rectifier circuit.\nReference: Schuler, 7th edition, page 71.\nRun the simulation and probe the waveform across R1.\nLeft-click the vertical axis and change the bottom axis limit to 0 V.\nThe low ripple content of three-phase rectification is apparent.
V2 N004 N005 SINE(0 170 60 0 0 120)
D6 0 N004 D
D1 N002 N001 D
D2 0 N002 D
V1 N003 N005 SINE(0 170 60)
D4 0 N003 D
D5 N004 N001 D
R1 N001 0 10
V3 N002 N005 SINE(0 170 60 0 0 -120)
D3 N003 N001 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 33.3333e-3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 416 48 336 48
WIRE 496 48 416 48
WIRE 544 48 496 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 496 64 496 48
WIRE 272 80 -80 80
WIRE 224 128 80 128
WIRE 544 144 544 48
WIRE 272 160 272 80
WIRE 336 160 336 128
WIRE 336 160 272 160
WIRE 224 176 224 128
WIRE 416 176 416 128
WIRE 416 176 224 176
WIRE -80 192 -80 80
WIRE 80 192 80 128
WIRE 496 192 496 128
WIRE 496 192 288 192
WIRE 336 224 336 160
WIRE 416 224 416 176
WIRE 496 224 496 192
WIRE 496 240 496 224
WIRE -80 288 -80 272
WIRE 80 288 80 272
WIRE 80 288 -80 288
WIRE 336 304 336 288
WIRE 416 304 416 288
WIRE 416 304 336 304
WIRE 496 304 496 288
WIRE 496 304 416 304
WIRE 544 304 544 224
WIRE 544 304 496 304
WIRE 544 336 544 304
WIRE 80 352 80 288
WIRE 80 464 80 432
WIRE 288 464 288 192
WIRE 288 464 80 464
SYMBOL voltage 80 448 R180
WINDOW 0 36 54 Left 0
WINDOW 3 -122 -39 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 170 60 0 0 120)
SYMBOL diode 352 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D2
SYMBOL diode 512 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D6
SYMBOL diode 352 128 R180
WINDOW 0 27 63 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMBOL diode 432 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D4
SYMBOL diode 432 128 R180
WINDOW 0 28 64 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D3
SYMBOL voltage 80 176 R0
WINDOW 3 -76 -69 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 56 Left 0
SYMATTR Value SINE(0 170 60)
SYMATTR InstName V1
SYMBOL diode 512 128 R180
WINDOW 0 24 64 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D5
SYMBOL voltage -80 176 R0
WINDOW 3 -105 139 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 57 Left 0
SYMATTR Value SINE(0 170 60 0 0 -120)
SYMATTR InstName V3
SYMBOL res 528 128 R0
SYMATTR InstName R1
SYMATTR Value 10
FLAG 544 336 0
TEXT 344 408 Left 0 !.tran 33.3333e-3
TEXT -128 -104 Left 0 ;This is a 3-Phase rectifier circuit.\nReference: Schuler, 7th edition, page 71.\nRun the simulation and probe the waveform across R1.\nLeft-click the vertical axis and change the bottom axis limit to 0 V.\nThe low ripple content of three-phase rectification is apparent.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2139-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2139-3.0.asy)
Rload OUT 0 5
C1 OUT 0 10
L1 N001 OUT 1 Rser=60m
XU1 IN IN N001 OUT 0 IN ADP2139-x.x Rtop=400K ;pnba Vin)EN)SW)Vout)GND)Mode
V1 IN 0 5
.tran .5m startup
.lib ADP2139-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADP2139-3.0 352 224 R0
SYMATTR InstName U1
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 600 352 Left 2 !.tran .5m startup