* Z:\home\khalils\Downloads\files\data\raw_asc\0fa9f5e557d5_InstructionMemoryFinal.asc
* Generated by LTspice 26.0.1 for Windows.
R3 VDD BL8 40K
R4 VDD BL7 40K
R5 VDD BL6 40K
R6 VDD BL5 40K
R7 VDD BL4 40K
R8 VDD BL3 40K
R9 VDD BL2 40K
R10 VDD BL1 40K
R11 VDD BL0 40K
M81 BL6 WL0 0 0 ROMN W=10u L=0.5u
M86 BL1 WL0 0 0 ROMN W=10u L=0.5u
M1 BL7 WL3 0 0 ROMN W=10u L=0.5u
M7 BL7 WL7 0 0 ROMN W=10u L=0.5u
M10 BL8 WL4 0 0 ROMN W=10u L=0.5u
M5 BL6 WL1 0 0 ROMN W=10u L=0.5u
M6 BL0 WL0 0 0 ROMN W=10u L=0.5u
M11 BL1 WL1 0 0 ROMN W=10u L=0.5u
M18 BL7 WL0 0 0 ROMN W=10u L=0.5u
M19 BL5 WL2 0 0 ROMN W=10u L=0.5u
M20 BL4 WL2 0 0 ROMN W=10u L=0.5u
M21 BL3 WL2 0 0 ROMN W=10u L=0.5u
M2 BL8 WL7 0 0 ROMN W=10u L=0.5u
M12 BL6 WL7 0 0 ROMN W=10u L=0.5u
M3 BL7 WL6 0 0 ROMN W=10u L=0.5u
M4 BL8 WL6 0 0 ROMN W=10u L=0.5u
M13 BL6 WL6 0 0 ROMN W=10u L=0.5u
M14 BL7 WL5 0 0 ROMN W=10u L=0.5u
M15 BL8 WL5 0 0 ROMN W=10u L=0.5u
M16 BL6 WL5 0 0 ROMN W=10u L=0.5u
M17 BL0 WL2 0 0 ROMN W=10u L=0.5u
M22 BL4 WL3 0 0 ROMN W=10u L=0.5u
M23 BL3 WL3 0 0 ROMN W=10u L=0.5u
M8 BL7 WL8 0 0 ROMN W=10u L=0.5u
M9 BL8 WL8 0 0 ROMN W=10u L=0.5u
M24 BL6 WL8 0 0 ROMN W=10u L=0.5u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* Instr 0: 100111100 (SRAM value: 0011)\nInstr 1: 110111101 (SRAM value: 0101)\nInstr 2: 111000110\nInstr 3: 101100111\nInstr 4: 011111111\nInstr 5: 000111111\nInstr 6: 000111111\nInstr 7: 000111111
* NO-OP
* NO-OP
* NO-OP
* LOAD SRAM address 0 to Register 0
* STORE register 2 to SRAM address 1
* END OF PROGRAM: The rest of the instructions above are NO-OPS.
* LOAD SRAM address 1 to Register 1
* ADD Register 1 to Register 2 and put result in Register 3
* MULT Register 0 and Register 1 and put result in Register 2
* NO-OP
.MODEL ROMN NMOS (LEVEL=7 TOX=8e-9 U0 = 1300
+CGSO=3.4E-10 CGDO=3.4E-10 CJ=6.8e-4 CJSW=1.26e-10
+MJ=0.5 MJSW=0.5 CGBO=5.75E-10 RSH=33.8)
.MODEL ROMP PMOS (LEVEL=7 TOX=8e-9 CGDO=5.3752E-11
+U0= 440 CGSO=5.3752E-11 CGBO=3.3650E-10 CJ=4.8447E-04
+MJ=0.5027 CJSW=1.6457E-10 MJSW=0.217168 RSH=29.8)
.ic V(BL8)=5 V(BL7)=0 V(BL6)=0 V(BL5)=5 V(BL4)=5 V(BL3)=5 V(BL2)=5 V(BL1)=0 V(BL0)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2308 1584
WIRE 304 -448 304 -512
WIRE 480 -448 480 -512
WIRE 640 -448 640 -512
WIRE 816 -448 816 -512
WIRE 992 -448 992 -512
WIRE 1168 -448 1168 -512
WIRE 1328 -448 1328 -512
WIRE 1504 -448 1504 -512
WIRE 1680 -448 1680 -512
WIRE 304 -320 304 -368
WIRE 480 -320 480 -368
WIRE 640 -320 640 -368
WIRE 816 -320 816 -368
WIRE 992 -320 992 -368
WIRE 1168 -320 1168 -368
WIRE 1328 -320 1328 -368
WIRE 1504 -320 1504 -368
WIRE 1680 -320 1680 -368
WIRE 224 -240 48 -240
WIRE 400 -240 224 -240
WIRE 560 -240 400 -240
WIRE 1904 -240 560 -240
WIRE 304 -192 304 -320
WIRE 480 -192 480 -320
WIRE 640 -192 640 -320
WIRE 208 -160 208 -192
WIRE 384 -160 384 -192
WIRE 544 -160 544 -192
WIRE 224 -48 48 -48
WIRE 400 -48 224 -48
WIRE 560 -48 400 -48
WIRE 1904 -48 560 -48
WIRE 304 0 304 -192
WIRE 480 0 480 -192
WIRE 640 0 640 -192
WIRE 208 32 208 0
WIRE 384 32 384 0
WIRE 544 32 544 0
WIRE 224 144 48 144
WIRE 400 144 224 144
WIRE 560 144 400 144
WIRE 1904 144 560 144
WIRE 304 192 304 0
WIRE 480 192 480 0
WIRE 640 192 640 0
WIRE 208 224 208 192
WIRE 384 224 384 192
WIRE 544 224 544 192
WIRE 224 336 48 336
WIRE 400 336 224 336
WIRE 560 336 400 336
WIRE 1904 336 560 336
WIRE 304 384 304 192
WIRE 480 384 480 192
WIRE 640 384 640 192
WIRE 208 416 208 384
WIRE 384 416 384 384
WIRE 544 416 544 384
WIRE 224 528 48 528
WIRE 1904 528 224 528
WIRE 304 576 304 384
WIRE 208 608 208 576
WIRE 400 704 48 704
WIRE 912 704 400 704
WIRE 1088 704 912 704
WIRE 1904 704 1088 704
WIRE 480 752 480 384
WIRE 992 752 992 -320
WIRE 1168 752 1168 -320
WIRE 384 784 384 752
WIRE 896 784 896 752
WIRE 1072 784 1072 752
WIRE 736 896 48 896
WIRE 912 896 736 896
WIRE 1088 896 912 896
WIRE 1600 896 1088 896
WIRE 1904 896 1600 896
WIRE 816 944 816 -320
WIRE 992 944 992 752
WIRE 1168 944 1168 752
WIRE 1680 944 1680 -320
WIRE 720 976 720 944
WIRE 896 976 896 944
WIRE 1072 976 1072 944
WIRE 1584 976 1584 944
WIRE 560 1088 48 1088
WIRE 1424 1088 560 1088
WIRE 1904 1088 1424 1088
WIRE 640 1136 640 384
WIRE 1504 1136 1504 -320
WIRE 544 1168 544 1136
WIRE 1408 1168 1408 1136
WIRE 400 1280 48 1280
WIRE 560 1280 400 1280
WIRE 1424 1280 560 1280
WIRE 1600 1280 1424 1280
WIRE 1904 1280 1600 1280
WIRE 304 1328 304 576
WIRE 480 1328 480 752
WIRE 640 1328 640 1136
WIRE 816 1328 816 944
WIRE 992 1328 992 944
WIRE 1168 1328 1168 944
WIRE 1328 1328 1328 -320
WIRE 1504 1328 1504 1136
WIRE 1680 1328 1680 944
WIRE 384 1360 384 1328
WIRE 544 1360 544 1328
WIRE 1408 1360 1408 1328
WIRE 1584 1360 1584 1328
FLAG 304 -512 VDD
FLAG 480 -512 VDD
FLAG 640 -512 VDD
FLAG 816 -512 VDD
FLAG 992 -512 VDD
FLAG 1168 -512 VDD
FLAG 1328 -512 VDD
FLAG 1504 -512 VDD
FLAG 1680 -512 VDD
FLAG 1904 -48 WL7
IOPIN 1904 -48 In
FLAG 1904 144 WL6
IOPIN 1904 144 In
FLAG 1904 336 WL5
IOPIN 1904 336 In
FLAG 1904 528 WL4
IOPIN 1904 528 In
FLAG 1904 704 WL3
IOPIN 1904 704 In
FLAG 1904 896 WL2
IOPIN 1904 896 In
FLAG 1904 1088 WL1
IOPIN 1904 1088 In
FLAG 1904 1280 WL0
IOPIN 1904 1280 In
FLAG 544 1360 0
FLAG 1408 1360 0
FLAG 304 -320 BL8
IOPIN 304 -320 Out
FLAG 480 -320 BL7
IOPIN 480 -320 Out
FLAG 640 -320 BL6
IOPIN 640 -320 Out
FLAG 816 -320 BL5
IOPIN 816 -320 Out
FLAG 992 -320 BL4
IOPIN 992 -320 Out
FLAG 1168 -320 BL3
IOPIN 1168 -320 Out
FLAG 1328 -320 BL2
IOPIN 1328 -320 Out
FLAG 1504 -320 BL1
IOPIN 1504 -320 Out
FLAG 1680 -320 BL0
IOPIN 1680 -320 Out
FLAG 384 784 0
FLAG 384 32 0
FLAG 208 608 0
FLAG 544 1168 0
FLAG 1584 1360 0
FLAG 1408 1168 0
FLAG 384 1360 0
FLAG 720 976 0
FLAG 896 976 0
FLAG 1072 976 0
FLAG 208 32 0
FLAG 544 32 0
FLAG 384 224 0
FLAG 208 224 0
FLAG 544 224 0
FLAG 384 416 0
FLAG 208 416 0
FLAG 544 416 0
FLAG 1584 976 0
FLAG 896 784 0
FLAG 1072 784 0
FLAG 1904 -240 WL8
IOPIN 1904 -240 In
FLAG 384 -160 0
FLAG 208 -160 0
FLAG 544 -160 0
SYMBOL res 288 -464 R0
SYMATTR InstName R3
SYMATTR Value 40K
SYMBOL res 464 -464 R0
SYMATTR InstName R4
SYMATTR Value 40K
SYMBOL res 624 -464 R0
SYMATTR InstName R5
SYMATTR Value 40K
SYMBOL res 800 -464 R0
SYMATTR InstName R6
SYMATTR Value 40K
SYMBOL res 976 -464 R0
SYMATTR InstName R7
SYMATTR Value 40K
SYMBOL res 1152 -464 R0
SYMATTR InstName R8
SYMATTR Value 40K
SYMBOL res 1312 -464 R0
SYMATTR InstName R9
SYMATTR Value 40K
SYMBOL res 1488 -464 R0
SYMATTR InstName R10
SYMATTR Value 40K
SYMBOL res 1664 -464 R0
SYMATTR InstName R11
SYMATTR Value 40K
SYMBOL nmos 640 1280 R90
SYMATTR InstName M81
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 1504 1280 R90
SYMATTR InstName M86
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 480 704 R90
SYMATTR InstName M1
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 480 -48 R90
SYMATTR InstName M7
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 304 528 R90
SYMATTR InstName M10
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 640 1088 R90
SYMATTR InstName M5
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 1680 1280 R90
SYMATTR InstName M6
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 1504 1088 R90
SYMATTR InstName M11
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 480 1280 R90
SYMATTR InstName M18
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 816 896 R90
SYMATTR InstName M19
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 992 896 R90
SYMATTR InstName M20
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 1168 896 R90
SYMATTR InstName M21
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 304 -48 R90
SYMATTR InstName M2
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 640 -48 R90
SYMATTR InstName M12
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 480 144 R90
SYMATTR InstName M3
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 304 144 R90
SYMATTR InstName M4
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 640 144 R90
SYMATTR InstName M13
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 480 336 R90
SYMATTR InstName M14
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 304 336 R90
SYMATTR InstName M15
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 640 336 R90
SYMATTR InstName M16
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 1680 896 R90
SYMATTR InstName M17
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 992 704 R90
SYMATTR InstName M22
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 1168 704 R90
SYMATTR InstName M23
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 480 -240 R90
SYMATTR InstName M8
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 304 -240 R90
SYMATTR InstName M9
SYMATTR Value ROMN  W=10u L=0.5u
SYMBOL nmos 640 -240 R90
SYMATTR InstName M24
SYMATTR Value ROMN  W=10u L=0.5u
TEXT 1848 -528 Left 2 ;Instr 0:    100111100  (SRAM value: 0011)\nInstr 1:    110111101  (SRAM value: 0101)\nInstr 2:    111000110\nInstr 3:    101100111\nInstr 4:    011111111\nInstr 5:    000111111\nInstr 6:    000111111\nInstr 7:    000111111
TEXT 64 -16 Left 2 ;NO-OP
TEXT 64 168 Left 2 ;NO-OP
TEXT 64 368 Left 2 ;NO-OP
TEXT -136 1304 Left 2 ;LOAD SRAM address 0 to Register 0
TEXT -224 552 Left 2 ;STORE register 2 to SRAM address 1
TEXT -496 464 Left 2 ;END OF PROGRAM: The rest of the instructions above are NO-OPS.
TEXT -136 1120 Left 2 ;LOAD SRAM address 1 to Register 1
TEXT -344 728 Left 2 ;ADD Register 1 to Register 2 and put result in Register 3
TEXT -376 928 Left 2 ;MULT Register 0 and Register 1 and put result in Register 2
TEXT 64 -208 Left 2 ;NO-OP
TEXT -544 -488 Left 2 !.MODEL ROMN NMOS  (LEVEL=7 TOX=8e-9 U0 = 1300\n+CGSO=3.4E-10 CGDO=3.4E-10 CJ=6.8e-4  CJSW=1.26e-10\n+MJ=0.5 MJSW=0.5 CGBO=5.75E-10 RSH=33.8)\n.MODEL ROMP PMOS  (LEVEL=7 TOX=8e-9  CGDO=5.3752E-11\n+U0= 440    CGSO=5.3752E-11  CGBO=3.3650E-10 CJ=4.8447E-04\n+MJ=0.5027 CJSW=1.6457E-10  MJSW=0.217168 RSH=29.8)
TEXT -800 -304 Left 2 !.ic V(BL8)=5 V(BL7)=0 V(BL6)=0 V(BL5)=5 V(BL4)=5 V(BL3)=5 V(BL2)=5 V(BL1)=0 V(BL0)=0