* Z:\home\khalils\Downloads\files\data\raw_asc\397485dc1168_LDO_45nm_90_OL.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
M3 N001 N004 N003 N003 NMOS l=nL_Diff w=nW_Diff
C1 N005 0 1
MPass Out N002 Vdd Vdd PMOS l=L_pass w=W_pass
V3 N004 N005 AC 1
CLoad Out 0 {CLoad}
M2 N002 N001 Vdd Vdd PMOS l=pL_Diff w=pW_Diff
M8 Out Bias 0 0 NMOS l={L_Mirr} w={W_Mirr}
M6 Bias Bias 0 0 NMOS l={L_Mirr} w={W_Mirr}
M1 N001 N001 Vdd Vdd PMOS l=pL_Diff w=pW_Diff
M5 N003 Bias 0 0 NMOS l={L_Mirr} w={W_Mirr}
V1 Vdd 0 1.4 AC 0
M4 N002 VRef N003 N003 NMOS l=nL_Diff w=nW_Diff
V2 VRef 0 1
ILoad Out 0 {ILoad}
I1 Vdd Bias {IBias}
R1 Out N005 1G
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include "45nm_HP.sp"
.param IBias 50u
.param ILoad 10m
.param CLoad 1u
.ac dec 20 10 1G
.param L_Mirr 270n
.param W_Mirr 2u
.param pL_Diff 90n
.param pW_Diff 670n
.param nL_Diff 90n
.param nW_Diff 290n
.param L_pass 90n
.param W_pass 270u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1484 996
WIRE 32 0 -16 0
WIRE 320 0 320 -80
WIRE 320 0 32 0
WIRE 368 0 320 0
WIRE 624 0 368 0
WIRE 688 0 624 0
WIRE 32 64 32 0
WIRE 320 64 320 0
WIRE 624 64 624 0
WIRE 128 80 80 80
WIRE 272 80 128 80
WIRE 576 80 496 80
WIRE -608 112 -608 16
WIRE -464 112 -464 16
WIRE -240 112 -240 -16
WIRE -16 112 -16 0
WIRE 32 112 -16 112
WIRE 368 112 368 0
WIRE 368 112 320 112
WIRE 688 112 688 0
WIRE 688 112 624 112
WIRE 32 192 32 160
WIRE 128 192 128 80
WIRE 128 192 32 192
WIRE 320 192 320 160
WIRE 496 192 496 80
WIRE 496 192 320 192
WIRE -608 272 -608 192
WIRE -464 272 -464 192
WIRE 32 288 32 192
WIRE 320 288 320 192
WIRE 64 336 32 336
WIRE 320 336 288 336
WIRE 624 336 624 160
WIRE 672 336 624 336
WIRE 784 336 672 336
WIRE 880 336 784 336
WIRE 1056 336 880 336
WIRE -16 368 -80 368
WIRE 464 368 368 368
WIRE 32 400 32 384
WIRE 64 400 64 336
WIRE 64 400 32 400
WIRE 288 400 288 336
WIRE 320 400 320 384
WIRE 320 400 288 400
WIRE 784 432 784 336
WIRE 880 432 880 336
WIRE 32 448 32 400
WIRE 176 448 32 448
WIRE 320 448 320 400
WIRE 320 448 176 448
WIRE -240 496 -240 192
WIRE -144 496 -240 496
WIRE -240 528 -240 496
WIRE 176 528 176 448
WIRE 624 528 624 336
WIRE -240 576 -288 576
WIRE 224 576 176 576
WIRE 672 576 624 576
WIRE -144 608 -144 496
WIRE -144 608 -192 608
WIRE 48 608 -144 608
WIRE 128 608 48 608
WIRE 576 608 464 608
WIRE 784 608 784 496
WIRE 832 608 784 608
WIRE 880 608 880 512
WIRE 880 608 832 608
WIRE -288 640 -288 576
WIRE -240 640 -240 624
WIRE -240 640 -288 640
WIRE 176 640 176 624
WIRE 224 640 224 576
WIRE 224 640 176 640
WIRE 624 640 624 624
WIRE 672 640 672 576
WIRE 672 640 624 640
WIRE -240 688 -240 640
WIRE 176 688 176 640
WIRE 624 688 624 640
WIRE 832 688 832 608
WIRE -80 800 -80 368
WIRE 320 800 -80 800
WIRE 496 800 400 800
WIRE 576 800 496 800
WIRE 1056 800 1056 336
WIRE 1056 800 656 800
WIRE 496 848 496 800
WIRE 496 976 496 912
DATAFLAG 1024 336 ""
DATAFLAG 32 224 ""
DATAFLAG 176 448 ""
DATAFLAG 416 192 ""
SYMBOL voltage 304 800 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 -60 56 VBottom 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL nmos4 368 288 M0
WINDOW 3 -40 100 Left 2
WINDOW 0 -6 122 Left 2
SYMATTR InstName M4
SYMATTR Value2 l=nL_Diff w=nW_Diff
SYMBOL res 672 784 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1G
SYMBOL pmos4 576 160 M180
WINDOW 0 54 4 Left 2
WINDOW 3 -28 100 Left 2
SYMATTR InstName MPass
SYMATTR Value2 l=L_pass w=W_pass
SYMBOL cap 768 432 R0
WINDOW 3 -88 7 Left 2
SYMATTR Value {CLoad}
SYMATTR InstName CLoad
SYMBOL pmos4 80 160 R180
WINDOW 3 82 11 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=pL_Diff w=pW_Diff
SYMBOL nmos4 576 528 R0
WINDOW 3 -34 -4 Left 2
SYMATTR InstName M8
SYMATTR Value2 l={L_Mirr} w={W_Mirr}
SYMBOL voltage -464 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL nmos4 -16 288 R0
WINDOW 3 -71 66 Left 2
SYMATTR InstName M3
SYMATTR Value2 l=nL_Diff w=nW_Diff
SYMBOL current 880 432 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName ILoad
SYMATTR Value {ILoad}
SYMBOL nmos4 -192 528 M0
WINDOW 3 56 60 Left 2
SYMATTR InstName M6
SYMATTR Value2 l={L_Mirr} w={W_Mirr}
SYMBOL current -240 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value {IBias}
SYMBOL voltage -608 96 R0
WINDOW 123 24 180 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 24 152 Left 2
SYMATTR Value2 AC 0
SYMATTR Value 1.4
SYMATTR InstName V1
SYMBOL cap 480 848 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL pmos4 272 160 M180
WINDOW 3 -63 66 Left 2
WINDOW 0 -65 44 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=pL_Diff w=pW_Diff
SYMBOL nmos4 128 528 R0
WINDOW 3 58 10 Left 2
SYMATTR InstName M5
SYMATTR Value2 l={L_Mirr} w={W_Mirr}
FLAG 176 688 0
FLAG -240 688 0
FLAG 624 688 0
FLAG 832 688 0
FLAG -240 -16 Vdd
FLAG 320 -80 Vdd
FLAG -608 272 0
FLAG -464 272 0
FLAG -608 16 Vdd
FLAG -464 16 VRef
FLAG 464 368 VRef
FLAG 48 608 Bias
FLAG 464 608 Bias
FLAG 432 272 OTA_Out
FLAG 672 336 Out
FLAG 496 976 0
TEXT 832 -192 Left 2 !.include "45nm_HP.sp"
TEXT 1168 112 Left 2 !.param IBias 50u
TEXT 1168 88 Left 2 !.param ILoad 10m
TEXT 1168 64 Left 2 !.param CLoad 1u
TEXT -568 552 Left 2 ;.op
TEXT -568 536 Left 2 !.ac dec 20 10 1G
TEXT 840 120 Left 2 !.param L_Mirr 270n\n.param W_Mirr 2u
TEXT 840 8 Left 2 !.param pL_Diff 90n\n.param pW_Diff 670n\n.param nL_Diff 90n\n.param nW_Diff 290n
TEXT 840 -48 Left 2 !.param L_pass 90n\n.param W_pass 270u