Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4807-4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
V2 IN 0 SINE(0 0.5 250K)
R1 N001 0 1K
R2 OUT N001 1K
V3 -V 0 -5
XU1 IN N001 +V -V OUT ADA4807-4 ;pnba In+)In-)V+)V-)OUT
.tran 50u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4807-4.asy)
.lib ADA4807-4.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 512 -1232 496 -1232
WIRE 544 -1232 512 -1232
WIRE 640 -1232 624 -1232
WIRE 176 -1136 176 -1152
WIRE 288 -1136 288 -1152
WIRE 512 -1120 512 -1232
WIRE 544 -1120 512 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 704 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 176 -1040 176 -1056
WIRE 288 -1040 288 -1056
WIRE 432 -976 432 -992
FLAG 176 -1152 +V
FLAG 176 -1040 0
FLAG 432 -976 0
FLAG 704 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 288 -1152 -V
FLAG 288 -1040 0
FLAG 400 -1232 0
FLAG 576 -1072 -V
SYMBOL voltage 176 -1152 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 0.5 250K)
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 288 -1152 R0
SYMATTR InstName V3
SYMATTR Value -5
SYMBOL opamps\\ADA4807-4 576 -1168 R0
SYMATTR InstName U1
TEXT 728 -976 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG772.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSwitch shown for a logic 0 input\nOnly one channel is modeled\nBandwidth is 424 MHz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG772.asy)
V1 vSA 0 2
V3 vIN 0 PULSE(0 3 0 1n 1n 20u 40u)
R1 vD 0 301
V2 vSB 0 0
XU1 vIN vSA vD vSB +V 0 ADG772 ;pnba IN)SA)D)SB)Vdd)GND
V4 +V 0 3.3
C1 vD 0 36p
.tran 100u
.lib ADG772.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1728 -272 -2032 -272
WIRE -1696 -272 -1728 -272
WIRE -2032 -256 -2032 -272
WIRE -1472 -240 -1504 -240
WIRE -1424 -240 -1472 -240
WIRE -1312 -240 -1424 -240
WIRE -1424 -224 -1424 -240
WIRE -1312 -224 -1312 -240
WIRE -1728 -208 -1920 -208
WIRE -1696 -208 -1728 -208
WIRE -1920 -192 -1920 -208
WIRE -2032 -160 -2032 -176
WIRE -1728 -144 -1776 -144
WIRE -1696 -144 -1728 -144
WIRE -1424 -128 -1424 -144
WIRE -1312 -128 -1312 -160
WIRE -1920 -96 -1920 -112
WIRE -1776 -80 -1776 -144
WIRE -1600 -16 -1600 -32
WIRE -1776 32 -1776 0
SYMBOL voltage -2032 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL voltage -2208 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 3.3
SYMBOL res -1440 -240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG772 -1600 -192 R0
SYMATTR InstName U1
SYMBOL cap -1328 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -1920 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage -1776 -96 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 1n 1n 20u 40u)
SYMATTR InstName V3
FLAG -2032 -160 0
FLAG -1920 -96 0
FLAG -1776 32 0
FLAG -1600 -368 +V
FLAG -1424 -128 0
FLAG -1600 -16 0
FLAG -1312 -128 0
FLAG -2208 -176 0
FLAG -2208 -256 +V
FLAG -1728 -272 vSA
FLAG -1728 -208 vSB
FLAG -1728 -144 vIN
FLAG -1472 -240 vD
TEXT -1480 -24 Left 2 !.tran 100u
TEXT -2056 -584 Left 2 ;Notes:\nSwitch shown for a logic 0 input\nOnly one channel is modeled\nBandwidth is 424 MHz
* Z:\home\khalils\Downloads\files\data\raw_asc\055c327d6dc0_nand.asc
* Generated by LTspice 26.0.1 for Windows.
M5 P001 in2 0 N003 NMOS l=90n w=200n
M3 out in1 P001 0 NMOS l=90n w=200n
M1 out in1 vdd N001 PMOS l=90n w=400n
M2 out in2 vdd N002 PMOS l=90n w=400n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 -208 -176 -208
WIRE -64 -176 -64 -240
WIRE 80 -176 80 -240
WIRE -144 -160 -208 -160
WIRE -112 -160 -144 -160
WIRE 16 -160 16 -208
WIRE 32 -160 16 -160
WIRE -64 -128 -64 -160
WIRE 80 -128 80 -160
WIRE -176 -64 -176 -208
WIRE -176 -64 -208 -64
WIRE -64 -48 -64 -80
WIRE 0 -48 -64 -48
WIRE 80 -48 80 -80
WIRE 80 -48 0 -48
WIRE 176 -48 80 -48
WIRE 0 -16 0 -48
WIRE 80 32 0 32
WIRE -144 64 -144 -160
WIRE -48 64 -144 64
WIRE -176 160 -176 -64
WIRE -48 160 -176 160
WIRE 0 160 0 128
WIRE 0 192 0 176
WIRE 80 192 80 32
WIRE 80 192 0 192
WIRE 0 240 0 192
IOPIN -208 -160 In
IOPIN -208 -64 In
IOPIN 176 -48 Out
IOPIN 80 -240 In
IOPIN -64 -240 In
SYMBOL pmos4 32 -80 M180
SYMATTR InstName M2
SYMATTR Value2 l=90n w=400n
SYMBOL pmos4 -112 -80 M180
SYMATTR InstName M1
SYMATTR Value2 l=90n w=400n
SYMBOL nmos4 -48 -16 R0
SYMATTR InstName M3
SYMATTR Value2 l=90n w=200n
SYMBOL nmos4 -48 80 R0
SYMATTR InstName M5
SYMATTR Value2 l=90n w=200n
FLAG -208 -160 in1
FLAG -208 -64 in2
FLAG 176 -48 out
FLAG 80 -240 vdd
FLAG -64 -240 vdd
FLAG 0 240 0
* Z:\home\khalils\Downloads\files\data\raw_asc\316e85d67676_Ej2.asc
* Generated by LTspice 26.0.1 for Windows.
L1 VRL V1 {289/243/Ww}
RL VRL 0 1
I1 0 V1 AC 1
C3 0 VRL {7/17/Ww}
C1 V1 0 {27/17/Ww}
C2 VRL V1 {27/289/Ww}
.param Ww = 2*pi
.net V(VRL) I1
.ac dec 1000 0.001 10000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 0 272 0
WIRE 384 0 368 0
WIRE 144 48 -16 48
WIRE 272 48 272 0
WIRE 272 48 144 48
WIRE 384 48 384 0
WIRE 480 48 384 48
WIRE 640 48 480 48
WIRE 272 96 272 48
WIRE 288 96 272 96
WIRE 384 96 384 48
WIRE 384 96 352 96
WIRE -16 112 -16 48
WIRE 640 128 640 48
WIRE 144 144 144 48
WIRE 480 144 480 48
WIRE -16 240 -16 192
WIRE 144 240 144 208
WIRE 144 240 -16 240
WIRE 304 240 144 240
WIRE 480 240 480 208
WIRE 480 240 304 240
WIRE 640 240 640 208
WIRE 640 240 480 240
WIRE 304 288 304 240
SYMBOL cap 352 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {27/289/Ww}
SYMBOL ind 384 -16 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 -47 53 VTop 2
SYMATTR InstName L1
SYMATTR Value {289/243/Ww}
SYMBOL cap 496 208 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value {7/17/Ww}
SYMBOL cap 128 144 R0
SYMATTR InstName C1
SYMATTR Value {27/17/Ww}
SYMBOL res 624 112 R0
SYMATTR InstName RL
SYMATTR Value 1
SYMBOL current -16 192 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value ""
SYMATTR Value2 AC 1
FLAG 304 288 0
FLAG 144 48 V1
FLAG 640 48 VRL
TEXT -16 328 Left 2 !.param Ww = 2*pi
TEXT -16 360 Left 2 !.net V(VRL) I1
TEXT -88 384 Left 2 !.ac dec 1000 0.001 10000
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1374.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1374.asy)
Rload OUT 0 2
R3 N006 0 10K
XU1 IN N001 N004 0 OUT N005 N003 N002 LT1374 top=10 bot=1T ;pnba Vin)Boost)FB)GND)BIAS)Vc)_SHDN)SW
C3 N006 N005 .005
D1 0 N002 MBRS340
C1 OUT 0 100
V1 IN 0 12
D2 OUT N001 1N914
R2 0 N004 4.99K
R1 OUT N004 5.36K
C2 N001 N002 .27
L1 N002 OUT 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT1374.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2928 1440
WIRE 2064 880 1888 880
WIRE 2176 880 2064 880
WIRE 2272 880 2240 880
WIRE 2064 896 2064 880
WIRE 1760 944 1568 944
WIRE 1568 960 1568 944
WIRE 1760 976 1760 944
WIRE 1888 976 1888 880
WIRE 2064 976 2064 960
WIRE 2064 976 2016 976
WIRE 2160 976 2064 976
WIRE 2272 976 2272 880
WIRE 2272 976 2240 976
WIRE 2320 976 2272 976
WIRE 2432 976 2320 976
WIRE 2544 976 2432 976
WIRE 2064 992 2064 976
WIRE 2432 992 2432 976
WIRE 2544 992 2544 976
WIRE 2016 1040 2016 976
WIRE 2016 1040 1984 1040
WIRE 1568 1056 1568 1040
WIRE 2064 1072 2064 1056
WIRE 2320 1072 2320 976
WIRE 2432 1088 2432 1056
WIRE 2544 1088 2544 1072
WIRE 2272 1104 2272 976
WIRE 2272 1104 1984 1104
WIRE 1664 1168 1632 1168
WIRE 2320 1168 2320 1152
WIRE 2320 1168 1984 1168
WIRE 2320 1184 2320 1168
WIRE 2000 1232 1984 1232
WIRE 2080 1232 2064 1232
WIRE 2176 1232 2160 1232
WIRE 2320 1280 2320 1264
WIRE 1824 1312 1824 1296
SYMBOL schottky 2048 1056 M180
WINDOW 0 37 52 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL ind 2144 992 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5
SYMBOL cap 2048 896 R0
SYMATTR InstName C2
SYMATTR Value .27
SYMBOL res 2528 976 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL cap 2064 1216 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .005
SYMBOL diode 2240 864 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL res 2064 1248 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL VOLTAGE 1568 944 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL POWERPRODUCTS\\LT1374 1824 1136 R0
SYMATTR InstName U1
SYMBOL res 2304 1280 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 4.99K
SYMBOL RES 2304 1056 R0
SYMATTR InstName R1
SYMATTR Value 5.36K
SYMBOL polcap 2416 992 R0
SYMATTR InstName C1
SYMATTR Value 100
FLAG 2176 1232 0
FLAG 1824 1312 0
FLAG 2320 1280 0
FLAG 2064 1072 0
FLAG 2432 1088 0
FLAG 1568 1056 0
FLAG 2544 1088 0
FLAG 2544 976 OUT
FLAG 1568 944 IN
TEXT 2320 1336 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0b10691921b3_Assignment_2b__ii_.asc
* Generated by LTspice 26.0.1 for Windows.
* Negative Clamper Circuit (with Bias)
V2 0 N003 2
R1 N002 0 1000
D1 N002 N003 1N4148
V1 N001 0 SINE(0 5 1000)
C1 N002 N001 0.000001
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5ms
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 176 80 64 80
WIRE 320 80 240 80
WIRE 416 80 320 80
WIRE 320 96 320 80
WIRE 64 160 64 80
WIRE 416 160 416 80
WIRE 320 192 320 160
WIRE 64 288 64 240
WIRE 176 288 64 288
WIRE 320 288 320 272
WIRE 320 288 176 288
WIRE 416 288 416 240
WIRE 416 288 320 288
WIRE 176 320 176 288
SYMBOL res 400 144 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL cap 240 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.000001
SYMBOL voltage 64 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1000)
SYMBOL Misc\\battery 320 288 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 2
SYMBOL diode 304 96 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG 176 320 0
TEXT 8 328 Left 2 !.tran 5ms
TEXT 24 16 Left 2 ;Negative Clamper Circuit (with Bias)
* Z:\home\khalils\Downloads\files\data\raw_asc\0dfd12ecc166_preamp.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU7, XU8 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
R1 V1st N003 6.2K
R4 V2nd N001 56K tol=5
R3 N001 V1st 8.6K tol=5
XU7 0 N001 +V -V V2nd level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
XU8 0 N002 +V -V Vout level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R6 N002 V2nd 8.6K tol=5
R5 Vout N002 56K tol=5
R2 N003 0 62K
XU1 Vi N003 +V -V V1st LF411/MC ;pnba In+)In-)V+)V-)OUT
.tran .0005
.inc MJE15034.LIB
.inc MJE15035.LIB
.inc LF411.LIB
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3868 1556
WIRE 864 144 848 144
WIRE 976 144 944 144
WIRE 1344 144 1312 144
WIRE 1472 144 1424 144
WIRE 272 176 208 176
WIRE 272 240 272 176
WIRE 448 240 272 240
WIRE 768 240 736 240
WIRE 848 240 848 144
WIRE 864 240 848 240
WIRE 1200 240 1184 240
WIRE 1312 240 1312 144
WIRE 1312 240 1280 240
WIRE 1344 240 1312 240
WIRE 608 256 512 256
WIRE 688 256 608 256
WIRE 736 256 736 240
WIRE 736 256 688 256
WIRE 976 256 976 144
WIRE 976 256 928 256
WIRE 1056 256 976 256
WIRE 1184 256 1184 240
WIRE 1184 256 1056 256
WIRE 1472 256 1472 144
WIRE 1472 256 1408 256
WIRE 1568 256 1472 256
WIRE 448 272 416 272
WIRE 864 272 832 272
WIRE 1344 272 1312 272
WIRE 608 304 608 256
WIRE 832 320 832 272
WIRE 1312 320 1312 272
WIRE 416 400 416 272
WIRE 608 400 608 384
WIRE 608 400 416 400
WIRE 608 416 608 400
IOPIN 208 176 In
IOPIN 1568 256 Out
IOPIN 496 -48 In
IOPIN 496 0 In
SYMBOL res 592 400 R0
SYMATTR InstName R2
SYMATTR Value 62K
SYMBOL res 592 288 R0
SYMATTR InstName R1
SYMATTR Value 6.2K
SYMBOL Opamps\\opamp2 480 320 M180
SYMATTR InstName U1
SYMATTR Value LF411/MC
SYMBOL res 864 224 R90
WINDOW 0 0 56 Invisible 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 8.6K
SYMATTR SpiceLine tol=5
SYMBOL Opamps\\UniversalOpamp2 1376 256 R0
SYMATTR InstName U8
SYMBOL res 1440 128 R90
WINDOW 0 0 56 Invisible 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 56K
SYMATTR SpiceLine tol=5
SYMBOL Opamps\\UniversalOpamp2 896 256 R0
SYMATTR InstName U7
SYMBOL res 1296 224 R90
WINDOW 0 0 56 Invisible 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 8.6K
SYMATTR SpiceLine tol=5
SYMBOL res 960 128 R90
WINDOW 0 0 56 Invisible 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 56K
SYMATTR SpiceLine tol=5
FLAG 208 176 Vi
FLAG 688 256 V1st
FLAG 832 320 0
FLAG 1056 256 V2nd
FLAG 1312 320 0
FLAG 608 496 0
FLAG 480 288 +V
FLAG 480 224 -V
FLAG 896 288 -V
FLAG 1376 288 -V
FLAG 896 224 +V
FLAG 1376 224 +V
FLAG 1568 256 Vout
FLAG 496 -48 +V
FLAG 496 0 -V
TEXT 168 520 Left 2 !.tran .0005
TEXT 176 592 Left 2 !.inc MJE15034.LIB\n.inc MJE15035.LIB
TEXT 448 576 Left 2 !.inc LF411.LIB
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC7050-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC7050-1.asy)
R2 N009 N010 100
V4 N011 0 PULSE(0 5 0 1n 1n 100n 1u)
L2 N007 N008 0.1
Rload1 N002 0 100m
C2 N008 0 200
V6 N005 0 1
C1 N002 0 200
V5 N010 0 1
Rload2 N008 0 100m
V2 N003 0 5
XU1 N003 N006 N003 0 MP_01 MP_02 N011 N003 N003 IN N001 0 N004 NC_03 NC_04 N009 N007 LTC7050-1 RTon=8m RBon=1.5m OV=18 ;pnba Vcc)PWM1)Run1)SGND)))PWM2)Run2)PVcc)Vin)SW1)PGND)Isns1)Fltb1)Fltb2)Isns2)SW2
V1 IN 0 12
R1 N004 N005 100
V3 N006 0 PULSE(0 5 0 1n 1n 100n 1u)
L1 N001 N002 0.1
.tran 300u
.lib LTC7050-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 920 728
WIRE 192 -16 -32 -16
WIRE 560 -16 480 -16
WIRE 720 -16 640 -16
WIRE 816 -16 720 -16
WIRE -32 0 -32 -16
WIRE 720 0 720 -16
WIRE 816 0 816 -16
WIRE 160 80 48 80
WIRE 192 80 160 80
WIRE 512 80 480 80
WIRE 624 80 592 80
WIRE -32 96 -32 80
WIRE 48 96 48 80
WIRE 624 96 624 80
WIRE 720 96 720 64
WIRE 816 96 816 80
WIRE 160 176 160 80
WIRE 192 176 160 176
WIRE 48 192 48 176
WIRE 624 192 624 176
WIRE 192 272 -224 272
WIRE 560 272 480 272
WIRE 720 272 640 272
WIRE 816 272 720 272
WIRE -224 288 -224 272
WIRE 720 288 720 272
WIRE 816 288 816 272
WIRE 160 368 160 176
WIRE 192 368 160 368
WIRE 512 368 480 368
WIRE 624 368 592 368
WIRE -224 384 -224 368
WIRE 624 384 624 368
WIRE 720 384 720 352
WIRE 816 384 816 368
WIRE 192 464 -224 464
WIRE -224 480 -224 464
WIRE 624 480 624 464
WIRE 160 560 160 368
WIRE 192 560 160 560
WIRE 512 560 480 560
WIRE -224 576 -224 560
WIRE 336 640 336 608
SYMBOL voltage 48 80 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL ind 544 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.1
SYMBOL cap 704 288 R0
WINDOW 0 33 12 Left 2
SYMATTR InstName C2
SYMATTR Value 200
SYMBOL ind 544 288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.1
SYMBOL res 496 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL res 496 384 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL voltage -224 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 1n 1n 100n 1u)
SYMBOL res 800 -16 R0
SYMATTR InstName Rload1
SYMATTR Value 100m
SYMBOL voltage -32 -16 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage -224 464 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1n 1n 100n 1u)
SYMBOL cap 704 0 R0
WINDOW 0 33 14 Left 2
SYMATTR InstName C1
SYMATTR Value 200
SYMBOL LTC7050-1 336 272 R0
SYMATTR InstName U1
SYMBOL res 800 272 R0
SYMATTR InstName Rload2
SYMATTR Value 100m
SYMBOL voltage 624 368 R0
SYMATTR InstName V5
SYMATTR Value 1
SYMBOL voltage 624 80 R0
SYMATTR InstName V6
SYMATTR Value 1
FLAG -32 96 0
FLAG 48 192 0
FLAG -224 384 0
FLAG 624 480 0
FLAG 512 560 0
FLAG 336 640 0
FLAG 624 192 0
FLAG 720 96 0
FLAG 720 384 0
FLAG 816 96 0
FLAG 816 384 0
FLAG -224 576 0
FLAG -32 -16 IN
TEXT 704 568 Left 2 !.tran 300u
* Z:\tmp\asc_dec_bjh7r6w2\05361c32bfeb_llc_5th_eq_vo-vg_and_Zin_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
C1 Vo N006 {Cf}
B7 N003 N002 I={Omega_s * C } * V(V_SNS_VC)
B12 N010 N012 V= {krc} * I(V_SNS_IS)
B3 N004 N005 V=2* {ks} * V(Vo)
B6 N008 N009 V={Omega_s * L} * I(V_SNS_IS)
B4 N012 N011 V= 2 * {kc} * V(Vo)
V_SNS_IS N003 N001 0
R2 N005 0 {Rs}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2152 800
WIRE 544 -336 384 -336
WIRE 544 -288 544 -336
WIRE -64 -192 -192 -192
WIRE 80 -192 -16 -192
WIRE 544 -160 544 -208
WIRE -192 -128 -192 -192
WIRE -80 -128 -192 -128
WIRE 80 -128 80 -192
WIRE 80 -128 -16 -128
WIRE -192 -16 -192 -128
WIRE -192 -16 -368 -16
WIRE -80 -16 -192 -16
WIRE 80 -16 80 -128
WIRE 80 -16 0 -16
WIRE 192 -16 80 -16
WIRE 384 -16 384 -336
WIRE 384 -16 272 -16
WIRE 800 -16 688 -16
WIRE 1040 -16 800 -16
WIRE 1152 -16 1040 -16
WIRE 1200 -16 1152 -16
WIRE 544 32 544 -80
WIRE 1152 48 1152 -16
WIRE 688 64 688 -16
WIRE 1040 64 1040 -16
WIRE -144 144 -768 144
WIRE 544 144 544 112
WIRE 544 144 -144 144
WIRE -144 176 -144 144
WIRE 544 176 544 144
WIRE 688 208 688 144
WIRE 800 208 688 208
WIRE 1040 208 1040 128
WIRE 1040 208 800 208
WIRE 1152 208 1152 128
WIRE 1152 208 1040 208
WIRE 688 240 688 208
WIRE -672 320 -768 320
WIRE -464 320 -592 320
WIRE -192 320 -384 320
WIRE 384 320 256 320
WIRE 544 352 544 256
WIRE 544 496 544 432
WIRE 384 640 384 320
WIRE 544 640 544 576
WIRE 544 640 384 640
SYMBOL cap 1024 64 R0
SYMATTR InstName C1
SYMATTR Value {Cf}
SYMBOL bi2 -80 -16 R270
WINDOW 0 32 40 VTop 2
WINDOW 3 -32 40 VBottom 2
SYMATTR InstName B7
SYMATTR Value I={Omega_s * C } * V(V_SNS_VC)
SYMBOL bv 544 592 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName B12
SYMATTR Value V= {krc} * I(V_SNS_IS)
SYMBOL bv 544 -176 R0
SYMATTR InstName B3
SYMATTR Value V=2* {ks} * V(Vo)
SYMBOL bv -480 320 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName B6
SYMATTR Value V={Omega_s * L} * I(V_SNS_IS)
SYMBOL bv 544 448 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName B4
SYMATTR Value V= 2 * {kc} * V(Vo)
SYMBOL voltage 176 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V_SNS_IS
SYMATTR Value 0
SYMBOL res 528 16 R0
SYMATTR InstName R2
SYMATTR Value {Rs}
FLAG -144 176 0
FLAG 1200 -16 Vo
* Z:\home\khalils\Downloads\files\data\raw_asc\592e925ca8cd_current-limiting-npn.asc
* Generated by LTspice 26.0.1 for Windows.
* Sizing:\nR2 sets max current -> set max current through the load: Imax = 20 mA\nFind R2 at max current assuming its voltage drop is Vbe and Q2 is still not conducting -> R2 = 0.6V/Imax = 30 ohm\nFind base current at the limiting condition where Q2 is still not conducting -> Ib = Ic/100 = 200 uA\nFind R1 using KVL -> 12 = R1*Ib + 0.6 + 0.6 -> R1 = (12 - 1.2)/20 u = 54k ohm\n \nNow see what happens when R load changes -> max current through the circuit is fixed at 20 mA\nPossible application -> LED driver circuit\n \nAfter running the simulation:\n1) CTRL + L or View SPICE error log\n2) Right click -> Plot .step ed .meas data
* Current limiting circuit using NPN transistors
R1 N002 Vcc 54k
Q2 N002 N003 0 0 2N3904
Q1 N001 N002 N003 0 2N3904
R3 Vcc N001 {R_load}
V1 Vcc 0 12
R2 0 N003 30
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 1
.step param R_load 100 1k 50
.meas Load_current AVG I(R3)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1828 680
WIRE -128 -48 -128 -96
WIRE 288 -16 288 -64
WIRE -128 64 -128 32
WIRE 288 128 288 64
WIRE 48 176 -32 176
WIRE 160 176 128 176
WIRE 224 176 160 176
WIRE 160 256 160 176
WIRE 288 304 288 224
WIRE 288 304 224 304
WIRE 288 352 288 304
WIRE 160 464 160 352
WIRE 288 464 288 432
SYMBOL npn 224 256 M0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL npn 224 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 144 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 54k
SYMBOL voltage -128 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 304 448 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 30
SYMBOL res 272 -32 R0
SYMATTR InstName R3
SYMATTR Value {R_load}
FLAG 288 464 0
FLAG 160 464 0
FLAG -128 64 0
FLAG -128 -96 Vcc
FLAG 288 -64 Vcc
FLAG -32 176 Vcc
TEXT 544 -128 Left 2 ;Sizing:\nR2 sets max current -> set max current through the load: Imax = 20 mA\nFind R2 at max current assuming its voltage drop is Vbe and Q2 is still not conducting -> R2 = 0.6V/Imax = 30 ohm\nFind base current at the limiting condition where Q2 is still not conducting -> Ib = Ic/100 = 200 uA\nFind R1 using KVL -> 12 = R1*Ib + 0.6 + 0.6 -> R1 = (12 - 1.2)/20 u = 54k ohm\n \nNow see what happens when R load changes -> max current through the circuit is fixed at 20 mA\nPossible application -> LED driver circuit\n \nAfter running the simulation:\n1) CTRL + L or View SPICE error log\n2) Right click -> Plot .step ed .meas data
TEXT 544 368 Left 2 !.tran 1
TEXT 544 256 Left 2 !.step param R_load 100 1k 50
TEXT 544 312 Left 2 !.meas Load_current AVG I(R3)
TEXT 56 -288 Left 4 ;Current limiting circuit using NPN transistors
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4661-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4661-2.asy)
R2 OUT N001 10K
Vin IN 0 SINE(0 1 1K)
V1 +V 0 9
R1 N001 0 10K
Rload OUT 0 10K
V2 -V 0 -9
XU1 IN N001 +V -V OUT ADA4661-2 ;pnba In+)In-)V+)V-)OUT
.tran 10m
.lib ADA4661-2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -9
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL ADA4661-2 576 -1168 R0
SYMATTR InstName U1
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
TEXT 704 -960 Left 2 !.tran 10m