* Z:\home\khalils\Downloads\files\data\raw_asc\818897fefe0f_Ejemplo_de_modulador_triangular_en_LTSPICE.asc
* Generated by LTspice 26.0.1 for Windows.
R5 N001 Va 6.2k
R2 N005 0 100k
V1 VCC 0 12
R3 Va N003 390k
R4 Vb N003 100k
V2 Vr 0 SINE(6.1 1.8 10k)
C1 Vb N001 470p
XU1 N002 N001 VCC 0 Vb ADTL082 ;pnba In+)In-)V+)V-)OUT
XU4 N005 N002 VCC 0 N002 ADTL082 ;pnba In+)In-)V+)V-)OUT
V3 N005 0 6
XU2 N003 N002 VCC 0 Va LM393A ;pnba In+)In-)V+)V-)OUT
R1 VCC Va 1k
XU5 Vr Vb VCC 0 N004 LM393A ;pnba In+)In-)V+)V-)OUT
R6 VCC N004 10k
.tran 0 100u 20u startup
.model IRF9540 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0
+ Tox=100n Uo=300 Phi=.6 Rs=64.15m Kp=10.18u W=1.5 L=2u
+ Vto=-3.646 Rd=62.45m Rds=444.4K Cbd=2.029n Pb=.8 Mj=.5 Fc=.5
+ Cgso=1.033n Cgdo=469.4p Rg=.3371 Is=54.08E-18 N=2 Tt=140n)
.model 1N4002 D (Is=14.11n N=1.984 Rs=33.89E-3 Ikf=94.81 Xti=3 Eg=1.110 Cjo=51.17E-12)
*//////////////////////////////////////////////////////////
*LM324 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
.SUBCKT LM324 1 2 99 50 28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain = 100dB
*High bandwidth = 1MHz
*Low input offset voltage = 1mV
*Wide supply range = +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
* supply current is 1/4 of total device current.
* Output crossover distortion with dual supplies
* is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 5N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*$
***********************
* LM393A VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
* REV (N/A)
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OPEN COLLECTOR OUTPUT
* | | | | |
.SUBCKT LM393A 1 2 3 4 5
*
F1 9 3 V1 1
IEE 3 7 DC 100.0E-6
VI1 21 1 DC .75
VI2 22 2 DC .75
Q1 9 21 7 QIN
Q2 8 22 7 QIN
Q3 9 8 4 QMO
Q4 8 8 4 QMI
.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
.MODEL QMI NPN(IS=800.0E-18 BF=1002)
.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
E1 10 4 9 4 1
V1 10 11 DC 0
Q5 5 11 4 QOC
.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)
DP 4 3 DX
RP 3 4 46.3E3
.MODEL DX D(IS=800.0E-18)
*
.ENDS
* LM311
*****************************************************************************
* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
* Released by: Texas Instruments Inc.
* Part: LM311
* Date: 08/16/2021
* Model Type: TRANSIENT
* Simulator: PSpice
* Simulator Version: 17.4
* Datasheet: SLCS007K - SEPTEMBER 1973 - REVISED MARCH 2017
*
*****************************************************************************
*
* Updates:
*
* Version 1.0 : Release to Web
* 2.0 : Improving Model Specifications
*
*****************************************************************************
* Notes:
* The following parameters are modeled:
* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhys
* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply
* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply
* When the current sourced from STROB is >2mA, the output is high
* V_VOS can be edited to model the BAL pin (currently set to typical 2mV offset)
* Modeled based off of typical EC table specs
*****************************************************************************
* source LM311
.SUBCKT LM311 IN+ IN- VCC+ VCC- STROB COL_OUT EMIT_OUT
X_U4 CMP N840186 Prop_Delay
X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE
X_U5 COL_OUT EMIT_OUT N21237 INRANGE 0 STROB V+_BUFFER V-_BUFFER VCC+ N884250
+ Output_Stage
X_U6 VCC+ V+_BUFFER VCC- V-_BUFFER Supply_Buffer
X_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER 0 HPA_COMPHYS
I_IS N843683 VCC- DC 5.1m
X_U7 N21237 0 V+_BUFFER V-_BUFFER Supply_Enable
X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer
I_IBP IN+ VCC- DC 100n
I_IBN IN- VCC- DC 100n
V_VOS N785573 IN+BUFF 2mV
R_RIS N843683 VCC+ 1u TC=0,0
C_CINPL VCC- IN+ 0.5p TC=0,0
C_CINNL VCC- IN- 0.5p TC=0,0
C_CINPH IN+ VCC+ 0.5p TC=0,0
C_CINNH IN- VCC+ 0.5p TC=0,0
R_RS N856907 CMP 50 TC=0,0
R_RT 0 N856913 50 TC=0,0
T_TPD N856907 0 N856913 0 Z0=50 TD=125n
X_S1 CMP 0 N857434 N840186 Top_Level_S1
X_S2 CMP 0 N857434 N856913 Top_Level_S2
E_E1 N884250 V-_BUFFER N857434 V-_BUFFER 2
.ENDS
*$
.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF
X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1
.ENDS
*$
.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER
X_U5 N16973 N20377 N16955 1V 0 VCC_Range
X_U15 N20310 N16973 POR 1V 0 VCC_Range
X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference
V_VS_MIN_SET N20310 0 3.49
V_VS_MAX_SET N20377 0 30.01
V_VLOGIC 1V 0 1
V_VS_MIN_SET1 N777117 0 3.49
X_U16 N777117 N16973 N777171 1V 0 VCC_Range
X_U17 N16955 N777171 EN 1V 0 ORGATE
.ENDS
*$
.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER
X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1
.ENDS
*$
.SUBCKT Output_Stage COL_OUT EMIT_OUT EN IN_RANGE POR STROB V+_BUFFER V-_BUFFER
+ VCC+ VIN
X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID
X_U3 VIN DS_OUT V+_BUFFER V-_BUFFER VCC+ VSS_NEW DIGLEVSHIFT
X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLY
V_VLOGIC 1V 0 1
V_V1 VCC+ VSS_NEW 1
X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ
X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE
X_U9 CONTROL_HIZ N789513 1V 0 INVERTER
X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE
L_L1 N778484 COL_OUT 1n
C_COUTH COL_OUT VCC+ 0.045p TC=0,0
C_COUTL EMIT_OUT COL_OUT 0.045p TC=0,0
X_SVOL CTRL_OUT VSS_NEW EMIT_OUT N850209 Output_Stage_SVOL
R_ROUTL N850209 N778496 150 TC=0,0
X_H1 V+_BUFFER N857381 N864891 VSS_NEW Output_Stage_H1
X_U11 N864896 DS_OUT CTRL_OUT VCC+ VSS_NEW ORGATE
X_U1 N863109 STROB N864245 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPS N863109 V+_BUFFER 0.01
X_U12 STROB N864069 N864233 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPS1 N864069 V-_BUFFER -0.01
X_U13 N864245 N864233 N864257 VCC+ VSS_NEW ORGATE
X_U14 N864257 N864882 VCC+ VSS_NEW INVERTER
X_U15 N864891 N864882 N864896 VCC+ VSS_NEW ANDGATE
R_RS1 N857381 STROB 500 TC=0,0
.ENDS
*$
.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER
V_VCMNP N20415 V-_BUFFER 0.49
V_VCMPN N32047 V+_BUFFER -1.49
X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPP N20155 V+_BUFFER -1.49
V_VCMNN N20539 V-_BUFFER 0.49
X_U21 N32047 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393
X_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393
X_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393
X_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE
.ENDS
*$
.SUBCKT Prop_Delay VIN VOUT
T_TPD N03175 0 VOUT 0 Z0=50 TD=115n
R_RT 0 VOUT 50 TC=0,0
R_RS N03175 VIN 50 TC=0,0
.ENDS
*$
.subckt Top_Level_S1 1 2 3 4
S_S1 3 4 1 2 _S1
RS_S1 1 2 1G
.MODEL _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.0V Von=1.0V
.ends Top_Level_S1
*$
.subckt Top_Level_S2 1 2 3 4
S_S2 3 4 1 2 _S2
RS_S2 1 2 1G
.MODEL _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0
.ends Top_Level_S2
*$
.subckt Output_Stage_SMID 1 2 3 4
S_SMID 3 4 1 2 _SMID
RS_SMID 1 2 1G
.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SMID
*$
.subckt Output_Stage_SHIZ 1 2 3 4
S_SHIZ 3 4 1 2 _SHIZ
RS_SHIZ 1 2 1G
.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SHIZ
*$
.subckt Output_Stage_SVOL 1 2 3 4
S_SVOL 3 4 1 2 _SVOL
RS_SVOL 1 2 1G
.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SVOL
*$
.subckt Output_Stage_H1 1 2 3 4
H_H1 3 4 VH_H1 250
VH_H1 1 2 0V
.ends Output_Stage_H1
*$
.SUBCKT ANDGATE 1 2 3 VDD VSS
E1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 4 3 1
C1 3 0 1e-12
.ENDS
*$
.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EVH VH 0 VALUE = { ( V(VHYS)/2) }
EINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }
EOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }
R1 OUT OUT_OUT 1
C1 OUT_OUT 0 1e-12
.ENDS
*$
.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEW
*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }
E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }
*
R1 3 2 1
*C1 2 0 1e-12
.ENDS
*$
.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) }
R1 OUT 2 1
C1 2 0 1e-12
.ENDS
*$
.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT VIN_INV 1 2 VDD VSS
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
C1 2 0 1e-12
.ENDS
*$
.SUBCKT INVERTER 1 2 VDD VSS
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
C1 1 0 1e-12
.ENDS
*$
.SUBCKT MID_SUPPLY OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT 0 VALUE = {V(VMID)}
.ENDS
*$
.SUBCKT ORGATE 1 2 3 VDD VSS
E1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) }
R1 4 3 1
C1 3 0 1e-12
.ENDS
*$
.SUBCKT NOR_GATE 1 2 OUT VDD VSS
EOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 OUT 2 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSS
EOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }
.ENDS
*$
.SUBCKT PORCHECK 1 2 OUT VDD VSS
EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) }
R1 OUT 2 1
C1 2 0 1e-12
.ENDS
*$
.SUBCKT Difference 1 2 OUT VDD VSS
EOUT OUT1 0 VALUE = { V(1)- V(2)}
R1 OUT1 OUT 1
*C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW
EVDD_NEW VDD_NEW 0 VALUE = {V(1)}
EVSS_NEW VSS_NEW 0 VALUE = {V(2)}
.ENDS
*$
.SUBCKT VCC_Range 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }
R1 OUT OUT2 1
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT VINRANGE_393 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.ENDS
*$
.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSS
EOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}
R1 OUT OUT2 1
C1 OUT 0 1e-12
.ENDS
*$
.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUT
EOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}
C1 OUT 0 1e-12
.ENDS
*$
.SUBCKT NORGATE 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.ENDS
*$
.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n
*$
.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n
*$
.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT
V_VLATCH N00729 V- 1.25
R_RPU N00729 LEHYST 40k TC=0,0
E_EIN VLE V-_BUF LEHYST V- 1
R_R1 V-_BUF LATCH_OUT 1k TC=0,0
R_R2 V-_BUF VLE 1k TC=0,0
R_R3 V-_BUF HYST_OUT 1k TC=0,0
E_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }
*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }
E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)
+(0.5,0.0636)
+(0.55,0.0636)
+(0.6,0.0636)
+(0.65,0.0636)
+(0.7,0.0635)
+(0.71,0.0636)
+(0.72,0.0635)
+(0.73,0.0636)
+(0.74,0.0634)
+(0.75,0.0635)
+(0.76,0.0638)
+(0.77,0.0637)
+(0.78,0.0637)
+(0.79,0.0637)
+(0.8,0.0636)
+(0.81,0.0636)
+(0.82,0.0636)
+(0.83,0.0636)
+(0.84,0.0425)
+(0.85,0.0411)
+(0.86,0.0398)
+(0.87,0.0386)
+(0.88,0.0371)
+(0.89,0.0359)
+(0.9,0.0347)
+(0.91,0.0334)
+(0.92,0.032)
+(0.93,0.0309)
+(0.94,0.0296)
+(1,0.0223)
+(1.05,0.0164)
+(1.1,0.0108)
+(1.15,0.0056)
+(1.2,0.0007)
+(1.25,0)
.ENDS
*$
.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBAD
GIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }
RIS VCC1 VCC 1
*RIS2 VCC VEE 100000000
.ENDS
*$
.SUBCKT 4ORGATE 1 2 3 4 5 VDD VSS
E1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 5 6 1
.ENDS
*$
* Library below included based on ModelFile attribute of instance XU1, XU4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADTL082.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5364 9380
WIRE -32 -944 -128 -944
WIRE 112 -944 32 -944
WIRE -304 -864 -304 -912
WIRE -224 -816 -256 -816
WIRE -448 -768 -448 -816
WIRE -480 -752 -528 -752
WIRE -48 -752 -48 -784
WIRE -304 -736 -304 -784
WIRE -304 -736 -416 -736
WIRE -256 -736 -256 -816
WIRE -256 -736 -304 -736
WIRE -224 -736 -256 -736
WIRE -128 -736 -128 -944
WIRE -128 -736 -144 -736
WIRE -80 -736 -128 -736
WIRE -480 -720 -496 -720
WIRE 112 -720 112 -944
WIRE 112 -720 -16 -720
WIRE 160 -720 112 -720
WIRE -80 -704 -128 -704
WIRE -448 -672 -448 -704
WIRE -656 -640 -656 -752
WIRE -48 -640 -48 -688
WIRE -496 -592 -496 -720
WIRE -432 -592 -496 -592
WIRE -304 -592 -304 -736
WIRE -304 -592 -352 -592
WIRE 224 -512 224 -576
WIRE -496 -496 -496 -592
WIRE -384 -496 -496 -496
WIRE 112 -496 112 -720
WIRE 112 -496 -304 -496
WIRE 192 -496 112 -496
WIRE 272 -480 256 -480
WIRE 320 -480 272 -480
WIRE 192 -464 64 -464
WIRE -656 -432 -656 -560
WIRE 64 -400 64 -464
WIRE 96 -400 64 -400
WIRE -528 -384 -528 -752
WIRE -128 -384 -128 -704
WIRE -128 -384 -528 -384
WIRE 64 -368 64 -400
WIRE 224 -336 224 -448
WIRE -448 -224 -448 -272
WIRE 64 -224 64 -288
WIRE -528 -208 -528 -384
WIRE -480 -208 -528 -208
WIRE -128 -192 -128 -384
WIRE -128 -192 -416 -192
WIRE -624 -176 -816 -176
WIRE -480 -176 -624 -176
WIRE -624 -160 -624 -176
WIRE -816 -144 -816 -176
WIRE -448 -112 -448 -160
WIRE -816 -32 -816 -64
WIRE -624 -16 -624 -80
FLAG -624 -16 0
FLAG -656 -432 0
FLAG -48 -640 0
FLAG -448 -112 0
FLAG 224 -336 0
FLAG -448 -672 0
FLAG -656 -752 VCC
IOPIN -656 -752 BiDir
FLAG -448 -816 VCC
IOPIN -448 -816 BiDir
FLAG -48 -784 VCC
IOPIN -48 -784 BiDir
FLAG -448 -272 VCC
IOPIN -448 -272 BiDir
FLAG -224 -816 Va
IOPIN -224 -816 Out
FLAG 160 -720 Vb
IOPIN 160 -720 Out
FLAG 64 -224 0
FLAG 224 -576 VCC
IOPIN 224 -576 BiDir
FLAG 96 -400 Vr
IOPIN 96 -400 Out
FLAG -816 -32 0
FLAG -304 -912 VCC
IOPIN -304 -912 BiDir
FLAG 272 -560 VCC
IOPIN 272 -560 BiDir
SYMBOL res -128 -752 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 6.2k
SYMBOL res -640 -176 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage -656 -656 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res -336 -608 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 390k
SYMBOL res -288 -512 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage 64 -384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(6.1 1.8 10k)
SYMBOL cap 32 -960 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 470p
SYMBOL OpAmps\\ADTL082 -48 -784 R0
SYMATTR InstName U1
SYMBOL OpAmps\\ADTL082 -448 -256 R0
SYMATTR InstName U4
SYMBOL voltage -816 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 6
SYMBOL OpAmps\\opamp2 -448 -800 R0
SYMATTR InstName U2
SYMATTR Value LM393A
SYMBOL res -320 -880 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL OpAmps\\opamp2 224 -544 R0
SYMATTR InstName U5
SYMATTR Value LM393A
SYMBOL res 256 -576 R0
SYMATTR InstName R6
SYMATTR Value 10k
TEXT -784 88 Left 2 !.tran 0 100u 20u startup
TEXT 1032 -968 Left 2 !.model IRF9540 PMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0\n+ Tox=100n Uo=300 Phi=.6 Rs=64.15m Kp=10.18u W=1.5 L=2u\n+ Vto=-3.646 Rd=62.45m Rds=444.4K Cbd=2.029n Pb=.8 Mj=.5 Fc=.5\n+ Cgso=1.033n Cgdo=469.4p Rg=.3371 Is=54.08E-18 N=2 Tt=140n)
TEXT 1040 -848 Left 2 !.model 1N4002 D (Is=14.11n N=1.984 Rs=33.89E-3 Ikf=94.81 Xti=3 Eg=1.110 Cjo=51.17E-12)
TEXT 1400 -704 Left 2 !*//////////////////////////////////////////////////////////\n*LM324 Low Power Quad OPERATIONAL AMPLIFIER MACRO-MODEL\n*//////////////////////////////////////////////////////////\n*\n* connections:      non-inverting input\n*                   |   inverting input\n*                   |   |   positive power supply\n*                   |   |   |   negative power supply\n*                   |   |   |   |   output\n*                   |   |   |   |   |\n*                   |   |   |   |   |\n.SUBCKT LM324    1   2  99  50  28\n*\n*Features:\n*Eliminates need for dual supplies\n*Large DC voltage gain =             100dB\n*High bandwidth =                     1MHz\n*Low input offset voltage =            1mV\n*Wide supply range =        +-1.5V to +-16V\n*\n*NOTE: Model is for single device only and simulated\n*      supply current is 1/4 of total device current.\n*      Output crossover distortion with dual supplies\n*      is not modeled.\n*\n****************INPUT STAGE**************\n*\nIOS 2 1 5N\n*^Input offset current\nR1 1 3 500K\nR2 3 2 500K\nI1 99 4 100U\nR3 5 50 517\nR4 6 50 517\nQ1 5 2 4 QX\nQ2 6 7 4 QX\n*Fp2=1.2 MHz\nC4 5 6 128.27P\n*\n***********COMMON MODE EFFECT***********\n*\nI2 99 50 75U\n*^Quiescent supply current\nEOS 7 1 POLY(1) 16 49 2E-3 1\n*Input offset voltage.^\nR8 99 49 60K\nR9 49 50 60K\n*\n*********OUTPUT VOLTAGE LIMITING********\nV2 99 8 1.63\nD1 9 8 DX\nD2 10 9 DX\nV3 10 50 .635\n*\n**************SECOND STAGE**************\n*\nEH 99 98 99 49 1\nG1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459\n*Fp1=7.86 Hz\nR5 98 9 101.2433MEG\nC3 98 9 200P\n*\n***************POLE STAGE***************\n*\n*Fp=2 MHz\nG3 98 15 9 49 1E-6\nR12 98 15 1MEG\nC5 98 15 7.9577E-14\n*\n*********COMMON-MODE ZERO STAGE*********\n*\n*Fpcm=10 KHz\nG4 98 16 3 49 5.6234E-8               \nL2 98 17 15.9M\nR13 17 16 1K\n*\n**************OUTPUT STAGE**************\n*\nF6 50 99 POLY(1) V6 300U 1\nE1 99 23 99 15 1\nR16 24 23 17.5\nD5 26 24 DX\nV6 26 22 .63V\nR17 23 25 17.5\nD6 25 27 DX\nV7 22 27 .63V\nV5 22 21 0.27V\nD4 21 15 DX\nV4 20 22 0.27V\nD3 15 20 DX\nL3 22 28 500P\nRL3 22 28 100K\n*\n***************MODELS USED**************\n*\n.MODEL DX D(IS=1E-15)\n.MODEL QX PNP(BF=1.111E3)\n*\n.ENDS\n*$\n \n***********************
TEXT 2512 -672 Left 2 !* LM393A VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT\n* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17\n* REV (N/A)\n* CONNECTIONS:   NON-INVERTING INPUT\n*                | INVERTING INPUT\n*                | | POSITIVE POWER SUPPLY\n*                | | | NEGATIVE POWER SUPPLY\n*                | | | | OPEN COLLECTOR OUTPUT\n*                | | | | |\n.SUBCKT LM393A   1 2 3 4 5\n*\n  F1    9  3 V1 1\n  IEE   3  7 DC 100.0E-6\n  VI1  21  1 DC .75\n  VI2  22  2 DC .75\n  Q1    9 21  7 QIN\n  Q2    8 22  7 QIN\n  Q3    9  8  4 QMO\n  Q4    8  8  4 QMI\n.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)\n.MODEL QMI NPN(IS=800.0E-18 BF=1002)\n.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)\n  E1   10  4  9  4  1\n  V1   10 11 DC 0\n  Q5    5 11  4 QOC\n.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)\n  DP    4  3 DX\n  RP 3  4 46.3E3\n.MODEL DX  D(IS=800.0E-18)\n*\n.ENDS
TEXT 3432 -688 Left 2 !* LM311\n*****************************************************************************\n* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.   \n*****************************************************************************\n** This model is designed as an aid for customers of Texas Instruments.\n** TI and its licensors and suppliers make no warranties, either expressed\n** or implied, with respect to this model, including the warranties of\n** merchantability or fitness for a particular purpose.  The model is\n** provided solely on an "as is" basis.  The entire risk as to its quality\n** and performance is with the customer\n*****************************************************************************\n*\n* This model is subject to change without notice. Texas Instruments\n* Incorporated is not responsible for updating this model.\n*\n*****************************************************************************\n*\n* Released by: Texas Instruments Inc.\n* Part: LM311\n* Date: 08/16/2021\n* Model Type:  TRANSIENT\n* Simulator: PSpice\n* Simulator Version: 17.4\n* Datasheet: SLCS007K - SEPTEMBER 1973 - REVISED MARCH 2017\n*\n*****************************************************************************\n*\n* Updates:\n*\n* Version 1.0 : Release to Web\n*         2.0 : Improving Model Specifications\n*\n*****************************************************************************\n* Notes:\n* The following parameters are modeled: \n* Iq, tpd, Ibias, Vcm, Vs, tr, tf, Vhys\n* If the input or supply rail goes beyond the abs max limits, the output will float at mid supply\n* If one or both inputs go beyond the commmon mode limit, the output will float at mid supply\n* When the current sourced from STROB is >2mA, the output is high\n* V_VOS can be edited to model the BAL pin (currently set to typical 2mV offset)\n* Modeled based off of typical EC table specs\n*****************************************************************************\n* source LM311\n.SUBCKT LM311 IN+ IN- VCC+ VCC- STROB COL_OUT EMIT_OUT    \nX_U4 CMP N840186 Prop_Delay  \nX_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE  \nX_U5 COL_OUT EMIT_OUT N21237 INRANGE 0 STROB V+_BUFFER V-_BUFFER VCC+ N884250\n+  Output_Stage  \nX_U6 VCC+ V+_BUFFER VCC- V-_BUFFER Supply_Buffer  \nX_U3         N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER 0 HPA_COMPHYS\nI_IS         N843683 VCC- DC 5.1m  \nX_U7 N21237 0 V+_BUFFER V-_BUFFER Supply_Enable  \nX_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer  \nI_IBP         IN+ VCC- DC 100n  \nI_IBN         IN- VCC- DC 100n  \nV_VOS         N785573 IN+BUFF 2mV\nR_RIS         N843683 VCC+  1u TC=0,0 \nC_CINPL         VCC- IN+  0.5p  TC=0,0 \nC_CINNL         VCC- IN-  0.5p  TC=0,0 \nC_CINPH         IN+ VCC+  0.5p  TC=0,0 \nC_CINNH         IN- VCC+  0.5p  TC=0,0 \nR_RS         N856907 CMP  50 TC=0,0 \nR_RT         0 N856913  50 TC=0,0 \nT_TPD         N856907 0 N856913 0 Z0=50 TD=125n  \nX_S1    CMP 0 N857434 N840186 Top_Level_S1 \nX_S2    CMP 0 N857434 N856913 Top_Level_S2 \nE_E1         N884250 V-_BUFFER N857434 V-_BUFFER 2\n.ENDS\n*$ \n.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF  \nX_U1         IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 \n.ENDS\n*$ \n.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER  \nX_U5         N16973 N20377 N16955 1V 0 VCC_Range\nX_U15         N20310 N16973 POR 1V 0 VCC_Range\nX_U13         V+_BUFFER V-_BUFFER N16973 1V 0 Difference\nV_VS_MIN_SET         N20310 0 3.49\nV_VS_MAX_SET         N20377 0 30.01\nV_VLOGIC         1V 0 1\nV_VS_MIN_SET1         N777117 0 3.49\nX_U16         N777117 N16973 N777171 1V 0 VCC_Range\nX_U17         N16955 N777171 EN 1V 0 ORGATE \n.ENDS\n*$\n.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER  \nX_U1         V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 \n.ENDS\n*$\n.SUBCKT Output_Stage COL_OUT EMIT_OUT EN IN_RANGE POR STROB V+_BUFFER V-_BUFFER\n+  VCC+ VIN  \nX_SMID    CONTROL_MID 0 N778484 MID Output_Stage_SMID \nX_U3         VIN DS_OUT V+_BUFFER V-_BUFFER VCC+ VSS_NEW DIGLEVSHIFT\nX_U7         MID V+_BUFFER V-_BUFFER MID_SUPPLY\nV_VLOGIC         1V 0 1\nV_V1         VCC+ VSS_NEW 1\nX_SHIZ    CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ \nX_U8          POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE\nX_U9         CONTROL_HIZ N789513 1V 0 INVERTER\nX_U10         N789513 POR CONTROL_MID 1V 0 ORGATE \nL_L1         N778484 COL_OUT  1n  \nC_COUTH         COL_OUT VCC+  0.045p  TC=0,0 \nC_COUTL         EMIT_OUT COL_OUT  0.045p  TC=0,0 \nX_SVOL    CTRL_OUT VSS_NEW EMIT_OUT N850209 Output_Stage_SVOL \nR_ROUTL         N850209 N778496  150 TC=0,0 \nX_H1    V+_BUFFER N857381 N864891 VSS_NEW Output_Stage_H1 \nX_U11         N864896 DS_OUT CTRL_OUT VCC+ VSS_NEW ORGATE \nX_U1         N863109 STROB N864245 V+_BUFFER V-_BUFFER VINRANGE_393\nV_VCMPS         N863109 V+_BUFFER 0.01\nX_U12         STROB N864069 N864233 V+_BUFFER V-_BUFFER VINRANGE_393\nV_VCMPS1         N864069 V-_BUFFER -0.01\nX_U13         N864245 N864233 N864257 VCC+ VSS_NEW ORGATE \nX_U14         N864257 N864882 VCC+ VSS_NEW INVERTER\nX_U15         N864891 N864882 N864896 VCC+ VSS_NEW ANDGATE\nR_RS1         N857381 STROB  500 TC=0,0 \n.ENDS\n*$\n.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER  \nV_VCMNP         N20415 V-_BUFFER 0.49\nV_VCMPN         N32047 V+_BUFFER -1.49\nX_U1         N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393\nV_VCMPP         N20155 V+_BUFFER -1.49\nV_VCMNN         N20539 V-_BUFFER 0.49\nX_U21         N32047 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393\nX_U22         INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393\nX_U23         INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393\nX_U24         N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE \n.ENDS\n*$\n.SUBCKT Prop_Delay VIN VOUT  \nT_TPD         N03175 0 VOUT 0 Z0=50 TD=115n  \nR_RT         0 VOUT  50 TC=0,0 \nR_RS         N03175 VIN  50 TC=0,0 \n.ENDS\n*$\n.subckt Top_Level_S1 1 2 3 4  \nS_S1         3 4 1 2 _S1\nRS_S1         1 2 1G\n.MODEL         _S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.0V Von=1.0V\n.ends Top_Level_S1\n*$\n.subckt Top_Level_S2 1 2 3 4  \nS_S2         3 4 1 2 _S2\nRS_S2         1 2 1G\n.MODEL         _S2 VSWITCH Roff=1e6 Ron=1.0 Voff=1 Von=0\n.ends Top_Level_S2\n*$\n.subckt Output_Stage_SMID 1 2 3 4  \nS_SMID         3 4 1 2 _SMID\nRS_SMID         1 2 1G\n.MODEL         _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0\n.ends Output_Stage_SMID\n*$\n.subckt Output_Stage_SHIZ 1 2 3 4  \nS_SHIZ         3 4 1 2 _SHIZ\nRS_SHIZ         1 2 1G\n.MODEL         _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0\n.ends Output_Stage_SHIZ\n*$\n.subckt Output_Stage_SVOL 1 2 3 4  \nS_SVOL         3 4 1 2 _SVOL\nRS_SVOL         1 2 1G\n.MODEL         _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0\n.ends Output_Stage_SVOL\n*$\n.subckt Output_Stage_H1 1 2 3 4  \nH_H1         3 4 VH_H1 250\nVH_H1         1 2 0V\n.ends Output_Stage_H1\n*$\n.SUBCKT ANDGATE 1 2 3 VDD VSS\nE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 4 3 1\nC1 3 0 1e-12\n.ENDS\n*$\n.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS\nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEVH VH 0 VALUE = { ( V(VHYS)/2) }\nEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }\nEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }\nR1 OUT OUT_OUT 1\nC1 OUT_OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEW\n*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }\nE1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }\n*\nR1 3 2 1\n*C1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) }\nR1 OUT 2 1\nC1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT VIN_INV 1 2 VDD VSS\nE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }\nC1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT INVERTER 1 2 VDD VSS\nE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }\nC1 1 0 1e-12\n.ENDS\n*$\n.SUBCKT MID_SUPPLY OUT VDD VSS\nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT 0 VALUE = {V(VMID)}\n.ENDS\n*$\n.SUBCKT ORGATE 1 2 3 VDD VSS\nE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) }\nR1 4 3 1\nC1 3 0 1e-12\n.ENDS\n*$\n.SUBCKT NOR_GATE 1 2 OUT VDD VSS\nEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 OUT 2 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSS\nEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }\n.ENDS\n*$\n.SUBCKT PORCHECK 1 2 OUT VDD VSS \nEOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) }\nR1 OUT 2 1\nC1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT Difference 1 2 OUT VDD VSS \nEOUT OUT1 0 VALUE = { V(1)- V(2)}\nR1 OUT1 OUT 1\n*C1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW \nEVDD_NEW VDD_NEW 0 VALUE = {V(1)}\nEVSS_NEW VSS_NEW 0 VALUE = {V(2)}\n.ENDS\n*$\n.SUBCKT VCC_Range 1 2 OUT VDD VSS \nEOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }\nR1 OUT OUT2 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT VINRANGE_393 1 2 OUT VDD VSS \nEOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSS\nEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}\nR1 OUT OUT2 1\nC1 OUT 0 1e-12 \n.ENDS\n*$\n.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN  VSS OUT\nEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT NORGATE 1 2 OUT VDD VSS\nEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n \n*$\n.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n \n*$\n.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT\nV_VLATCH         N00729 V- 1.25\nR_RPU         N00729 LEHYST  40k TC=0,0 \nE_EIN         VLE V-_BUF LEHYST V- 1\nR_R1         V-_BUF LATCH_OUT  1k TC=0,0 \nR_R2         V-_BUF VLE  1k TC=0,0\nR_R3         V-_BUF HYST_OUT  1k TC=0,0  \nE_ELATCH   LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }\n*E_EHYST     HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }\nE_EHYST     HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)\n+(0.5,0.0636)\n+(0.55,0.0636)\n+(0.6,0.0636)\n+(0.65,0.0636)\n+(0.7,0.0635)\n+(0.71,0.0636)\n+(0.72,0.0635)\n+(0.73,0.0636)\n+(0.74,0.0634)\n+(0.75,0.0635)\n+(0.76,0.0638)\n+(0.77,0.0637)\n+(0.78,0.0637)\n+(0.79,0.0637)\n+(0.8,0.0636)\n+(0.81,0.0636)\n+(0.82,0.0636)\n+(0.83,0.0636)\n+(0.84,0.0425)\n+(0.85,0.0411)\n+(0.86,0.0398)\n+(0.87,0.0386)\n+(0.88,0.0371)\n+(0.89,0.0359)\n+(0.9,0.0347)\n+(0.91,0.0334)\n+(0.92,0.032)\n+(0.93,0.0309)\n+(0.94,0.0296)\n+(1,0.0223)\n+(1.05,0.0164)\n+(1.1,0.0108)\n+(1.15,0.0056)\n+(1.2,0.0007)\n+(1.25,0)\n.ENDS\n*$\n.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBAD\nGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }\nRIS VCC1 VCC 1\n*RIS2 VCC VEE 100000000\n.ENDS\n*$\n.SUBCKT 4ORGATE 1 2 3 4 5 VDD VSS\nE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 5 6 1\n.ENDS\n*$