* Z:\home\khalils\Downloads\files\data\raw_asc\fra_eg7_LT8618_zout.asc
* Generated by LTspice 26.0.1 for Windows.
* This example shows an output impedance FRA (@z1).\nOptionally, a gain FRA can also be included in the same .fra simulation by enabling the @1 FRA\nby right-clicking it and un-checking the box labeled "Disable this Analyzer"
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8618.asy)
@1 OUT N003 delay=7.5m fstart=800 fend=100k oct=2 fcoarse=2k nmax=4 pp0=40m pp1=10m f0=781.25 f1=3.125K tavgmin=250 tsettle=125 enabled=0
@z1 OUT 0 zm delay=1m fstart=800 fend=10Meg oct=2 fcoarse=2k nmax=4 pp0=40m pp1=10m f0=781.25 f1=3.125K tavgmin=100 tsettle=125
R5 N004 N005 5m
L1 N002 OUT 120 Rser=.2
R1 N006 0 110K
C4 N005 0 22 Rser=10m
R2 N003 FB 1.62Meg
I1 OUT 0 PULSE(0 50m 300u 100u 100u 1)
C2 INTVCC 0 1
V1 IN 0 12
R3 FB 0 301K
L2 OUT N004 1n
C3 N001 N002 47n
R4 OUT N007 100K
C1 OUT 0 100p
XU1 INTVCC N002 OUT N001 N006 FB TRSS N007 IN IN 0 LT8604C LT8604=0 DFN=1 VOUT33=0 ;pnba INTVCC)SW)Bias)BST)Rt)FB)TR/SS)PG)EN/UV)Vin)GND
.ic V(OUT)=4.95 V(TRSS)=3.5 V(INTVCC)=3.5
.fra
.lib LT8604C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1500 680
WIRE 96 0 -32 0
WIRE 112 0 96 0
WIRE 432 0 400 0
WIRE -32 16 -32 0
WIRE 432 16 432 0
WIRE 96 96 96 0
WIRE 112 96 96 96
WIRE 432 96 432 80
WIRE 432 96 400 96
WIRE 496 96 432 96
WIRE 608 96 576 96
WIRE 656 96 608 96
WIRE 784 96 656 96
WIRE 848 96 784 96
WIRE 896 96 848 96
WIRE 992 96 896 96
WIRE 1088 96 992 96
WIRE -32 112 -32 96
WIRE 656 112 656 96
WIRE 784 112 784 96
WIRE 896 112 896 96
WIRE 64 192 32 192
WIRE 112 192 64 192
WIRE 608 192 608 96
WIRE 608 192 400 192
WIRE 656 192 656 176
WIRE 784 192 784 176
WIRE 896 208 896 192
WIRE 464 288 400 288
WIRE 656 288 656 272
WIRE 656 288 464 288
WIRE 1088 288 1088 96
WIRE 896 304 896 288
WIRE 992 304 992 96
WIRE 656 320 656 288
WIRE 80 384 48 384
WIRE 112 384 80 384
WIRE 896 384 896 368
WIRE 992 384 992 368
WIRE 1088 384 1088 368
WIRE 656 416 656 400
WIRE 16 480 0 480
WIRE 112 480 96 480
WIRE 464 480 400 480
WIRE 608 480 608 192
WIRE 608 480 544 480
WIRE 256 544 256 528
SYMBOL res 640 176 R0
SYMATTR InstName R2
SYMATTR Value 1.62Meg
SYMBOL cap 416 16 R0
SYMATTR InstName C3
SYMATTR Value 47n
SYMBOL LT8618 256 192 R0
SYMATTR InstName U1
SYMBOL cap 976 304 R0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL fra 784 176 R0
SYMATTR InstName @z1
SYMATTR SpiceLine zm delay=1m fstart=800 fend=10Meg oct=2 fcoarse=2k nmax=4 pp0=40m pp1=10m f0=781.25 f1=3.125K tavgmin=100 tsettle=125
SYMBOL res 560 464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL res 640 304 R0
SYMATTR InstName R3
SYMATTR Value 301K
SYMBOL fra 656 176 R0
SYMATTR InstName @1
SYMATTR SpiceLine delay=7.5m fstart=800 fend=100k oct=2 fcoarse=2k nmax=4 pp0=40m pp1=10m f0=781.25 f1=3.125K tavgmin=250 tsettle=125 enabled=0
SYMBOL res 880 192 R0
SYMATTR InstName R5
SYMATTR Value 5m
SYMBOL cap 880 304 R0
SYMATTR InstName C4
SYMATTR Value 22
SYMATTR SpiceLine Rser=10m
SYMBOL voltage -32 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL current 1088 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(0 50m 300u 100u 100u 1)
SYMBOL res 112 464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 110K
SYMBOL cap 32 208 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL ind 480 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 120
SYMATTR SpiceLine Rser=.2
SYMBOL ind 880 96 R0
SYMATTR InstName L2
SYMATTR Value 1n
FLAG 256 544 0
FLAG 0 480 0
FLAG -32 112 0
FLAG -32 192 0
FLAG 896 384 0
FLAG 656 416 0
FLAG 1088 384 0
FLAG 848 96 OUT
FLAG -32 0 IN
FLAG 464 288 FB
FLAG 992 384 0
FLAG 784 192 0
FLAG 80 384 TRSS
FLAG 64 192 INTVCC
TEXT 576 0 Left 2 !.ic V(OUT)=4.95 V(TRSS)=3.5 V(INTVCC)=3.5
TEXT 576 -40 Left 2 !.fra
TEXT -24 -160 Left 2 ;This example shows an output impedance FRA (@z1).\nOptionally, a gain FRA can also be included in the same .fra simulation by enabling the @1 FRA\nby right-clicking it and un-checking the box labeled "Disable this Analyzer"