Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4257.asc
* Generated by LTspice 26.0.1 for Windows.
* Diode Bridge
* Set for Class 4 Load
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4257.asy)
D2 IN N004 MURS120
D1 0 N001 MURS120
R2 N001 N003 100K
VPSE 0 N004 PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 8 555m 8 560m 4 610m 4 611m 17 621m 17 622m 8 627m 8 628m 17 638m 17 639m 8 659m 8 660m 57)
XU1 MP_01 N002 MP_02 IN OUT N003 MP_03 N001 LTC4257 ;pnba )Rclass))Vin)Vout)_PWRGD))GND
Rclass N002 IN 30.9
Rload N001 OUT 1.3K
Cload N001 OUT 100 Rser=10m
C1 N001 IN .1 Rser=10m
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.8
.lib LTC4257.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1516 692
WIRE -528 208 -1344 208
WIRE -464 208 -528 208
WIRE -352 208 -400 208
WIRE 336 208 -352 208
WIRE 400 208 336 208
WIRE 512 208 400 208
WIRE 656 208 512 208
WIRE -528 240 -528 208
WIRE 400 256 400 208
WIRE -1344 272 -1344 208
WIRE -352 288 -352 208
WIRE 336 288 336 208
WIRE 336 288 320 288
WIRE 656 304 656 208
WIRE 512 320 512 208
WIRE -128 368 -144 368
WIRE -32 368 -48 368
WIRE 400 368 400 336
WIRE 400 368 320 368
WIRE -1344 448 -1344 352
WIRE -480 448 -1344 448
WIRE -352 448 -352 352
WIRE -352 448 -416 448
WIRE -144 448 -144 368
WIRE -144 448 -352 448
WIRE -32 448 -144 448
WIRE 512 448 512 384
WIRE 512 448 320 448
WIRE 656 448 656 384
WIRE 656 448 512 448
SYMBOL diode -464 192 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MURS120
SYMBOL res 640 288 R0
SYMATTR InstName Rload
SYMATTR Value 1.3K
SYMBOL LTC4257 144 368 R0
WINDOW 0 0 -63 Center 2
WINDOW 3 0 78 Center 2
SYMATTR InstName U1
SYMBOL cap 496 320 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName Cload
SYMATTR Value 100
SYMBOL res 384 240 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap -368 288 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res -32 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rclass
SYMATTR Value 30.9
SYMBOL diode -416 464 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value MURS120
SYMBOL voltage -1344 256 R0
WINDOW 3 37 54 Left 2
WINDOW 123 25 90 Left 2
SYMATTR Value PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 8 555m 8 560m 4 610m 4
SYMATTR Value2 611m 17 621m 17 622m 8 627m 8 628m 17 638m 17 639m 8 659m 8 660m 57)
SYMATTR InstName VPSE
FLAG 656 448 OUT
FLAG -528 240 0
FLAG -352 448 IN
TEXT 376 512 Left 2 !.tran 0.8
TEXT -448 400 Bottom 2 ;Diode Bridge
TEXT -144 488 Top 2 ;Set for Class 4 Load
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8513.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8513.asy)
Rload OUT 0 10K
V1 +V 0 5
XU1 IN N001 +V -V OUT AD8510 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -5
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 176 -1136 176 -1152
WIRE 272 -1136 272 -1152
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 176 -1040 176 -1056
WIRE 272 -1040 272 -1056
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL Opamps\\AD8513 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 176 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 272 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 176 -1152 +V
FLAG 176 -1040 0
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 272 -1152 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 752 -992 0
FLAG 272 -1040 0
TEXT 688 -952 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\162a12761f6b_trigger_bv.asc
* Generated by LTspice 26.0.1 for Windows.
* Triggered BV-source made with TRIGGER PWL
* triggered time ramp
* any trigger source
V1 tt 0 TRIGGER V(trig)>0.5 PWL(0 0 1 1)
B1 trig_bv 0 V=1+5*(1-exp(-10*V(tt)))
V2 trig 0 PULSE(0 1 .3 1n 1n .6 2)
.tran 4
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1312 680
WIRE -96 128 -160 128
WIRE 384 128 320 128
WIRE -160 176 -160 128
WIRE 320 176 320 128
WIRE -160 304 -160 256
WIRE 320 304 320 256
WIRE 96 368 -160 368
WIRE -160 416 -160 368
WIRE -160 528 -160 496
IOPIN 96 368 Out
LINE Normal -240 336 -240 128 2
LINE Normal 32 336 -240 336 2
LINE Normal 32 480 32 336 2
LINE Normal 48 464 32 480 2
LINE Normal 48 464 48 464 2
LINE Normal 16 464 32 480 2
LINE Normal 16 464 16 464 2
LINE Normal 0 128 288 128 2
LINE Normal 0 240 0 128 2
LINE Normal -16 224 0 240 2
LINE Normal 16 224 0 240 2
LINE Normal -192 128 -240 128 2
SYMBOL bv -160 400 R0
SYMATTR InstName B1
SYMATTR Value V=1+5*(1-exp(-10*V(tt)))
SYMBOL voltage -160 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value TRIGGER V(trig)>0.5 PWL(0 0 1 1)
SYMBOL voltage 320 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 .3 1n 1n .6 2)
FLAG -160 304 0
FLAG 320 304 0
FLAG -96 128 tt
FLAG 384 128 trig
FLAG -160 528 0
FLAG 96 368 trig_bv
TEXT -240 -8 Left 0 !.tran 4
TEXT -56 -48 Left 0 ;Triggered BV-source made with TRIGGER PWL
TEXT -240 16 Left 0 !.options plotwinsize=0
TEXT -224 88 Left 0 ;triggered time ramp
TEXT 280 88 Left 0 ;any trigger source
* Z:\home\khalils\Downloads\files\data\raw_asc\2eda83ddcaa3_NMOSvtc.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N002 0 1.8
M1 N001 N002 0 N003 NMOS l=1080nm w=1080nm
V1 N001 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V1 0 1.80 0.1 V2 0 1.8 0.2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 64 176 64
WIRE 176 96 176 64
WIRE 176 208 176 176
WIRE 128 288 0 288
WIRE 176 288 176 256
WIRE 0 352 0 288
WIRE 176 368 176 304
WIRE 0 496 0 432
SYMBOL voltage 0 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL nmos4 128 208 R0
SYMATTR InstName M1
SYMATTR Value2 l=1080nm w=1080nm
SYMBOL voltage 176 192 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
FLAG 0 496 0
FLAG 176 368 0
FLAG 272 64 0
TEXT -272 80 Left 2 !.dc V1 0 1.80 0.1 V2 0 1.8 0.2
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4440-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4440-5.asy)
V1 N001 0 5
XU1 N001 0 N002 0 N003 N001 LTC4440-5 ;pnba VCC)GND)INP)TS)TG)BOOST
V2 N002 0 PULSE(0 8 0 1n 1n 1u 2u)
.tran 50u
.lib LTC4440-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2336 1256
WIRE 1424 -144 1104 -144
WIRE 1008 -80 976 -80
WIRE 1104 -80 1104 -144
WIRE 1104 -80 1088 -80
WIRE 1136 -80 1104 -80
WIRE 1424 -80 1424 -144
WIRE 1424 -80 1392 -80
WIRE 1136 0 976 0
WIRE 1424 0 1392 0
WIRE 976 64 976 0
WIRE 1136 80 1104 80
WIRE 1424 80 1392 80
WIRE 976 160 976 144
SYMBOL voltage 976 48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 8 0 1n 1n 1u 2u)
SYMBOL PowerProducts\\LTC4440-5 1264 0 R0
SYMATTR InstName U1
SYMBOL voltage 1104 -80 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value 5
FLAG 1104 80 0
FLAG 976 -80 0
FLAG 1424 80 0
FLAG 976 160 0
TEXT 1376 176 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2118-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2118-2.5.asy)
C1 OUT 0 100
Rload1 OUT 0 .833
R1 OUT N001 100K
L1 N002 OUT 1
V1 IN 0 5
XU1 IN IN IN OUT 0 0 N002 IN IN IN N001 ADP2118-x.x Rtop=760k Rbot=240k Ctop=4p ;pnba Sync/Mode)FREQ)TRK)FB)GND)PGND)SW)Pvin)Vin)EN)Pgood
.tran 2m startup
.lib ADP2118-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1104 680
WIRE 128 0 48 0
WIRE 288 0 128 0
WIRE 48 16 48 0
WIRE 288 32 288 0
WIRE 128 64 128 0
WIRE 160 64 128 64
WIRE 496 64 416 64
WIRE 640 64 576 64
WIRE 48 112 48 96
WIRE 128 144 128 64
WIRE 160 144 128 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 640 144 640 64
WIRE 640 144 560 144
WIRE 704 144 640 144
WIRE 560 160 560 144
WIRE 704 160 704 144
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 560 224 416 224
WIRE 560 256 560 224
WIRE 704 256 704 240
WIRE 128 304 128 224
WIRE 160 304 128 304
WIRE 640 304 640 144
WIRE 640 304 416 304
WIRE 128 384 128 304
WIRE 160 384 128 384
WIRE 288 432 288 416
SYMBOL cap 544 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C1
SYMATTR Value 100
SYMBOL ADP2118-2.5 288 272 R0
SYMATTR InstName U1
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL res 688 144 R0
SYMATTR InstName Rload1
SYMATTR Value .833
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL voltage 48 0 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 560 256 0
FLAG 288 432 0
FLAG 48 112 0
FLAG 704 144 OUT
FLAG 704 256 0
FLAG 48 0 IN
TEXT 504 384 Left 2 !.tran 2m startup
* Z:\tmp\asc_dec_bjh7r6w2\00ce4231d683_EJ2_2_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 N003 AC 1 0
R1 Vo N002 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 0 16 0
WIRE 144 0 112 0
WIRE 16 32 16 0
WIRE 16 32 -64 32
WIRE 144 32 144 0
WIRE 240 32 224 32
WIRE 336 32 240 32
WIRE 16 80 16 32
WIRE 32 80 16 80
WIRE 144 80 144 32
WIRE 144 80 96 80
WIRE -64 96 -64 32
WIRE 240 96 240 32
WIRE 336 96 336 32
WIRE -64 256 -64 176
WIRE 96 256 -64 256
WIRE 240 256 240 176
WIRE 240 256 96 256
WIRE 336 256 336 160
WIRE 96 288 96 256
SYMBOL voltage -64 80 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL res 240 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1
FLAG 336 32 Vo
* Z:\home\khalils\Downloads\files\data\raw_asc\OP282.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP282.asy)
C3 N003 0 0.15
XU1 N003 N001 V+ V- OUT OP282 ;pnba In+)In-)V+)V-)OUT
R2 N002 IN 1Meg
V1 V+ 0 5
V2 V- 0 -5
R1 N003 N002 1Meg
V3 IN 0 SINE(0 0.1 0.1)
C2 OUT N001 0.01
R3 OUT N001 2Meg
C1 OUT N002 0.15
.tran 0 10 0
.lib OP282.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 400 -208 304 -208
WIRE 560 -208 464 -208
WIRE 304 -112 304 -208
WIRE 384 -112 304 -112
WIRE 560 -112 560 -208
WIRE 560 -112 464 -112
WIRE 384 -16 368 -16
WIRE 368 16 368 -16
WIRE 304 32 304 -112
WIRE 336 32 304 32
WIRE 512 48 400 48
WIRE 560 48 560 -112
WIRE 560 48 512 48
WIRE -32 64 -48 64
WIRE 64 64 -32 64
WIRE 208 64 144 64
WIRE 224 64 208 64
WIRE 320 64 304 64
WIRE 336 64 320 64
WIRE -48 96 -48 64
WIRE 320 96 320 64
WIRE 368 128 368 80
WIRE 384 128 368 128
WIRE 320 176 320 160
WIRE -48 208 -48 176
WIRE 208 224 208 64
WIRE 320 224 208 224
WIRE 560 224 560 48
WIRE 560 224 384 224
WIRE 48 336 32 336
WIRE 160 336 144 336
WIRE 32 368 32 336
WIRE 144 368 144 336
WIRE 32 464 32 448
WIRE 144 464 144 448
SYMBOL OP282 368 -16 R0
SYMATTR InstName U1
SYMBOL voltage -48 80 R0
WINDOW 3 48 60 Left 2
WINDOW 123 47 83 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0 0.1 0.1)
SYMATTR InstName V3
SYMBOL voltage 32 352 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 160 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL cap 384 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.15u
SYMBOL cap 464 -224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 123 79 33 VBottom 2
SYMATTR InstName C2
SYMATTR Value 0.01u
SYMBOL res 320 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL voltage 144 352 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL cap 304 96 R0
SYMATTR InstName C3
SYMATTR Value 0.15u
SYMBOL res 480 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 2Meg
FLAG 32 464 0
FLAG 144 464 0
FLAG 48 336 V+
FLAG 160 336 V-
FLAG 384 -16 V+
FLAG 384 128 V-
FLAG 320 176 0
FLAG -48 208 0
FLAG -32 64 IN
FLAG 512 48 OUT
TEXT 472 424 Left 2 !.tran 0 10 0
* Z:\home\khalils\Downloads\files\data\raw_asc\0d121eeba1b6_ADA4000-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4000-1.asy)
V1 +V 0 15
R2 OUT N001 10K
R1 N001 0 10K
Vin IN 0 SINE(0 1 500K)
V2 -V 0 -15
XU1 IN N001 +V -V OUT ADA4000 ;pnba In+)In-)V+)V-)OUT
.tran 20u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 736 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 432 -976 432 -992
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 500K)
SYMBOL Opamps\\ADA4000-1 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 144 -1168 +V
FLAG 432 -976 0
FLAG 736 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 256 -1056 0
FLAG 144 -1056 0
TEXT 744 -984 Left 2 !.tran 20u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4623.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4623.asy)
C1 N002 0 .005
R1 N003 0 40.2K
C2 OUT 0 47 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
V1 IN 0 12
XU1 NC_01 N001 N001 N003 N002 NC_02 IN NC_03 OUT 0 0 IN IN MP_04 MP_05 MP_06 NC_07 NC_08 NC_09 LTM4623 ;pnba FREQ)INTVcc)Mode)FB)Track/SS)COMP)Run)Pgood)Vout)GND)SGND)Vin)SVin))))CLKIN)CLKOUT)PhMode
Rload OUT 0 .5
.tran 1.5m startup
.lib LTM4623.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 -112 48 -112
WIRE 64 -96 -64 -96
WIRE 192 -96 64 -96
WIRE 320 -96 192 -96
WIRE -64 -80 -64 -96
WIRE 192 -80 192 -96
WIRE 320 -80 320 -96
WIRE 64 -16 64 -96
WIRE 80 -16 64 -16
WIRE -64 16 -64 0
WIRE 48 80 48 -112
WIRE 80 80 48 80
WIRE 448 80 448 -112
WIRE 448 80 432 80
WIRE -16 176 -32 176
WIRE 80 176 48 176
WIRE 576 176 432 176
WIRE 672 176 576 176
WIRE 576 192 576 176
WIRE 672 192 672 176
WIRE 496 272 432 272
WIRE 496 288 496 272
WIRE 576 288 576 256
WIRE 672 288 672 272
WIRE 496 384 496 368
WIRE 192 544 192 528
WIRE 320 544 320 528
SYMBOL voltage -64 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL PowerProducts\\LTM4623 256 224 R0
SYMATTR InstName U1
SYMBOL cap 560 192 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL cap 48 160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .005
SYMBOL res 480 272 R0
SYMATTR InstName R1
SYMATTR Value 40.2K
SYMBOL res 656 176 R0
SYMATTR InstName Rload
SYMATTR Value .5
FLAG 192 544 0
FLAG 320 544 0
FLAG -64 16 0
FLAG -64 -96 IN
FLAG -32 176 0
FLAG 496 384 0
FLAG 672 288 0
FLAG 576 288 0
FLAG 672 176 OUT
TEXT 480 456 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\287903d9a274_6203.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6203.asy)
R2 N001 0 1K
V2 -V 0 -5
V1 +V 0 5
XU1 IN N001 OUT +V -V LT6202 ;pnba IN+)IN-)OUT)VCC)VEE
V3 IN 0 SINE(0 1 1Meg)
R1 OUT N001 1K
.tran 10u
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -208 144 -208 128
WIRE -80 144 -80 128
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -208 240 -208 224
WIRE -80 240 -80 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 304 240 256 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1Meg)
SYMBOL voltage -80 128 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -208 128 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL opamps\\LT6203 192 240 R0
SYMATTR InstName U1
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1K
FLAG -80 240 0
FLAG 192 192 +V
FLAG -80 128 +V
FLAG 192 288 -V
FLAG -208 240 0
FLAG -208 128 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 304 240 OUT
FLAG 0 256 IN
TEXT 280 344 Left 0 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7150-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7150-2.8.asy)
XU1 N004 OUT N002 0 N003 N003 N001 IN ADM7150_1 Vreg=3.5 Vref=2.812 ;pnba Vreg)Vout)Byp)GND)Ref_Sense)Ref)EN)Vin
C4 N003 0 1
C3 OUT 0 10
R3 IN N001 100K
R5 OUT 0 18
V1 IN 0 6.2
C2 N002 0 1
C1 N004 0 10 Rser=10m Lser=1n
.tran 5m startup
.lib ADM7150_1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 856
WIRE -32 32 -160 32
WIRE 80 32 -32 32
WIRE 464 32 400 32
WIRE 560 32 464 32
WIRE -160 48 -160 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE -160 144 -160 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 0 224 -16 224
WIRE 80 224 64 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap 448 240 R0
WINDOW 0 36 14 Left 2
WINDOW 3 36 50 Left 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL ADM7150-2.8 240 176 R0
SYMATTR InstName U1
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR Value2 Rser=10m
SYMATTR SpiceLine Lser=1n
SYMBOL voltage -160 32 R0
SYMATTR InstName V1
SYMATTR Value 6.2
SYMBOL res 544 32 R0
SYMATTR InstName R5
SYMATTR Value 18
SYMBOL cap 448 48 R0
SYMATTR InstName C3
SYMATTR Value 10
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG -16 224 0
FLAG -160 144 0
FLAG 560 144 0
FLAG -160 32 IN
FLAG 560 32 OUT
TEXT 552 448 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\000640553d14_gm_sweep.asc
* Generated by LTspice 26.0.1 for Windows.
* .AC LIST 1K
* Plot Id(M1) or I(V2) to get "gm" at 1KHz.
* Plot transfer_function to get "gm" at DC.
* Plot Id(M1). This is not gm!
* Sweeping transconductance "gm" versus a control voltage.
* Gerneral hint for plots:\nMake the plot window active. \n"PlotSettings->Add Trace" and select an item\nor "right mouse button ->Add Trace" and select an item.
M1 0 0 N002 N002 BSS84
V2 N001 N002 0
V1 N001 0 {bias} AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.step param bias 0 3 0.01
.OP
.TF I(V2) V1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 288 96 240
WIRE 96 112 -96 112
WIRE 96 384 96 448
WIRE 96 448 16 448
WIRE -96 288 -96 112
WIRE -96 368 -96 448
WIRE 48 304 16 304
WIRE 16 304 16 448
WIRE 16 448 -96 448
WIRE -96 480 -96 448
WIRE 96 160 96 112
SYMBOL pmos 48 384 M180
SYMATTR InstName M1
SYMATTR Value BSS84
SYMBOL voltage 96 144 R0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage -96 272 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {bias}
SYMATTR Value2 AC 1
FLAG -96 480 0
TEXT -112 -216 Left 0 !.step param bias 0 3 0.01
TEXT -112 -160 Left 0 !.OP
TEXT -112 -120 Left 0 !.TF I(V2) V1
TEXT -112 -80 Left 0 ;.AC LIST 1K
TEXT 56 -80 Left 0 ;Plot Id(M1) or I(V2) to get "gm" at 1KHz.
TEXT 56 -120 Left 0 ;Plot transfer_function to get "gm" at DC.
TEXT 56 -160 Left 0 ;Plot Id(M1). This is not gm!
TEXT -112 -272 Left 0 ;Sweeping transconductance "gm" versus a control voltage.
TEXT -104 -16 Left 0 ;Gerneral hint for plots:\nMake the plot window active. \n"PlotSettings->Add Trace" and select an item\nor "right mouse button  ->Add Trace" and select an item.
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX4162.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX4162.asy)
CL OUT 0 15p
V1 IN 0 SINE(0 50m 1k)
RL OUT 0 10k
Vee 0 Vee 2.5
XU1 IN OUT Vcc Vee OUT MAX4162 ;pnba In+)In-)V+)V-)OUT
Vcc Vcc 0 2.5
.tran 1m
.lib MAX4162.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 144 288 144 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 144 400 144 368
WIRE 144 400 112 400
WIRE 400 400 304 400
WIRE 112 416 112 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 144 448 144 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 144 544 144 528
WIRE 304 592 304 576
SYMBOL voltage 144 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL MAX4162 432 320 R0
SYMATTR InstName U1
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 144 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 1k)
FLAG 720 384 OUT
FLAG 144 272 Vcc
FLAG 144 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 112 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
TEXT 96 632 Left 2 !.tran 1m