Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\0e011e894b96_1637.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Supply Rail Current Sense
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1637.asy)
I1 N002 0 SINE(1 1 1K)
Q1 N001 N004 OUT 0 2N3904
R1 OUT 0 2K
XU1 N001 N003 +V 0 N004 NC_01 LT1637 ;pnba In+)In-)V+)V-)OUT)SHDN
R2 +V N002 .2
V1 +V 0 5
R4 N003 N002 200
R3 N001 +V 200
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -80 48 -80 32
WIRE -32 48 -80 48
WIRE 64 48 48 48
WIRE 336 48 64 48
WIRE -80 80 -80 48
WIRE 144 144 144 128
WIRE -288 160 -288 144
WIRE 336 176 336 48
WIRE -80 192 -80 160
WIRE -32 192 -80 192
WIRE 112 192 48 192
WIRE 272 224 256 224
WIRE -288 256 -288 240
WIRE 64 256 64 48
WIRE 112 256 64 256
WIRE -80 272 -80 192
WIRE 336 288 336 272
WIRE 416 288 336 288
WIRE 336 304 336 288
WIRE 144 320 144 304
WIRE -80 384 -80 352
WIRE 336 400 336 384
SYMBOL res -96 64 R0
SYMATTR InstName R2
SYMATTR Value .2
SYMBOL current -80 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(1 1 1K)
SYMBOL res 320 288 R0
SYMATTR InstName R1
SYMATTR Value 2K
SYMBOL npn 272 176 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL opamps\\LT1637 144 224 R0
SYMATTR InstName U1
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 64 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL res 64 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 200
FLAG -288 256 0
FLAG 144 128 +V
FLAG -288 144 +V
FLAG 144 320 0
FLAG 336 400 0
FLAG -80 32 +V
FLAG -80 384 0
FLAG 416 288 OUT
TEXT 424 392 Left 2 !.tran 3m
TEXT 128 -16 Bottom 2 ;Positive Supply Rail Current Sense
* Z:\tmp\asc_mix_bvbm4pog\mix_26.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 1
Rload OUT 0 1K
XU1 OUT OUT N002 0 IN MP_01 MP_02 IN LT1962-5 ;pnba OUT)SENSE)BYP)GND)_SHDN)))IN
M1 N001 N003 0 N001 PMOS l=180n w=270n
VG N003 0
VD N001 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.lib tsmc018.lib
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1962-5.asy)
.lib LT1962-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1568 592
WIRE 352 32 320 32
WIRE 416 32 352 32
WIRE 512 32 416 32
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 416 48 416 32
WIRE 512 48 512 32
WIRE -208 64 -208 48
WIRE 352 96 352 32
WIRE 352 96 320 96
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 416 144 416 112
WIRE 512 144 512 128
WIRE -208 160 -208 144
WIRE 352 160 320 160
WIRE 176 240 176 208
WIRE 1168 16 1024 16
WIRE 1168 48 1168 16
WIRE 1024 128 1024 16
WIRE 1088 128 1024 128
WIRE 1088 176 1088 128
WIRE 1088 176 1024 176
WIRE 976 208 896 208
WIRE 896 320 896 288
WIRE 1024 320 1024 224
WIRE 1024 320 896 320
WIRE 1168 320 1168 128
WIRE 1168 320 1024 320
WIRE 1024 352 1024 320
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 48 R0
SYMATTR InstName C1
SYMATTR Value 1u
SYMBOL res 496 32 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL LT1962-5 176 96 R0
SYMATTR InstName U1
SYMBOL pmos4 976 128 R0
SYMATTR InstName M1
SYMATTR Value2 l=180n w=270n
SYMBOL voltage 896 192 R0
SYMATTR InstName VG
SYMATTR Value ""
SYMBOL voltage 1168 32 R0
SYMATTR InstName VD
SYMATTR Value ""
FLAG -208 160 0
FLAG 416 144 0
FLAG 512 144 0
FLAG 176 240 0
FLAG 512 32 OUT
FLAG -208 48 IN
FLAG 1024 352 0
TEXT 384 232 Left 2 !.tran 1
TEXT 656 160 Left 2 !.lib tsmc018.lib
TEXT 656 200 Left 2 !.dc VG -1.8 1.8 0.01 VD -0.01 -1.8 -0.9
* Z:\tmp\asc_dec_bjh7r6w2\0321c85b4b85_5400-5_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V3 IN 0 AC 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1472
WIRE 1936 688 1936 624
WIRE 2016 688 1936 688
WIRE 1936 816 1936 688
WIRE 1952 816 1936 816
WIRE 1952 880 1744 880
WIRE 1392 896 1392 880
WIRE 1520 896 1520 880
WIRE 1744 896 1744 880
WIRE 1952 944 1936 944
WIRE 1392 992 1392 976
WIRE 1520 992 1520 976
WIRE 1744 992 1744 976
WIRE 1920 1008 1872 1008
WIRE 1952 1008 1920 1008
WIRE 1920 1120 1920 1008
SYMBOL voltage 1520 880 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 1744 880 R0
SYMATTR InstName V3
SYMATTR Value AC 1
FLAG 1520 992 0
FLAG 1520 880 +V
FLAG 1392 992 0
FLAG 1392 880 -V
FLAG 1744 992 0
FLAG 1744 880 IN
FLAG 1872 1008 0
FLAG 1936 944 0
* Z:\home\khalils\Downloads\files\data\raw_asc\06986fcd7f4e_Draft1a.asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 N002 D
M1 N001 N004 N002 N002 BSC060N10NS3
D2 N002 N001 D
L1 N002 N003 72e-6
V1 N001 0 15
C1 N003 0 1000e-6
R1 N003 0 2
V2 N004 N002 PULSE(0 5 0 0 0 1e-6 2e-6)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 10e-3 0 1e-9
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 -432 -80 -432
WIRE 176 -432 64 -432
WIRE -80 -352 -80 -432
WIRE -80 -352 -240 -352
WIRE 0 -352 -80 -352
WIRE 176 -352 176 -432
WIRE 176 -352 96 -352
WIRE 224 -352 176 -352
WIRE 304 -352 224 -352
WIRE 496 -352 384 -352
WIRE 720 -352 496 -352
WIRE 112 -304 80 -304
WIRE 112 -224 112 -304
WIRE -240 -208 -240 -352
WIRE 496 -208 496 -352
WIRE 720 -208 720 -352
WIRE 224 -192 224 -352
WIRE 176 -144 176 -352
WIRE 176 -144 112 -144
WIRE -240 -32 -240 -128
WIRE 224 -32 224 -128
WIRE 224 -32 -240 -32
WIRE 496 -32 496 -144
WIRE 496 -32 224 -32
WIRE 720 -32 720 -128
WIRE 720 -32 496 -32
WIRE 736 -32 720 -32
WIRE 224 0 224 -32
SYMBOL diode 208 -128 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL ind 288 -336 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 72e-6
SYMBOL voltage -240 -224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL cap 480 -208 R0
SYMATTR InstName C1
SYMATTR Value 1000e-6
SYMBOL nmos 0 -304 R270
WINDOW 3 -196 46 Left 2
SYMATTR Value BSC060N10NS3
SYMATTR InstName M1
SYMBOL voltage 112 -240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 0 0 1e-6 2e-6)
SYMBOL diode 64 -448 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMBOL res 704 -224 R0
SYMATTR InstName R1
SYMATTR Value 2
FLAG 224 0 0
TEXT -272 -24 Left 2 !.tran 0 10e-3 0 1e-9
* Z:\home\khalils\Downloads\files\data\raw_asc\0a2292c5498b_Interview01.asc
* Generated by LTspice 26.0.1 for Windows.
* 5.92
* 4.5
* 6.8
* Q1. Explain the principle of this circuit.\nQ2. What's the reason for having Q1 and Q2 in that topology?\nQ3. Can we replace D3 with something else?\nQ4. What would have happened if the diodes were reversed?
* R1=1 65mV drop instead of 650mV
D2 0 N006 MMBZ6V8ALY
R3 N002 N003 750
R1 c N001 1
V1 N001 0 10
D1 N006 N002 STZ5_6N
C1 c 0 4.7m
Q2 N004 N005 N007 0 BCW60A
R2 c N002 390
R4 N007 0 R=if(time>300m,100,500)
Q1 N002 N003 N005 0 2N2222
D3 0 N003 PTZ6_8B
RL c N004 33
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 500m
.ic V(c)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1808 1000
WIRE -48 128 -96 128
WIRE 80 128 80 96
WIRE 80 128 32 128
WIRE 288 128 80 128
WIRE 784 128 288 128
WIRE 288 160 288 128
WIRE -96 192 -96 128
WIRE 288 272 288 240
WIRE 496 272 288 272
WIRE 656 272 496 272
WIRE 496 288 496 272
WIRE 784 288 784 128
WIRE 288 400 288 272
WIRE 656 400 656 272
WIRE 80 416 80 128
WIRE 496 448 496 368
WIRE 592 448 496 448
WIRE 784 464 784 368
WIRE 496 512 496 448
WIRE 656 512 656 496
WIRE 720 512 656 512
WIRE 288 544 288 464
WIRE 784 576 784 560
WIRE -96 656 -96 272
WIRE 80 656 80 480
WIRE 80 656 -96 656
WIRE 288 656 288 608
WIRE 288 656 80 656
WIRE 496 656 496 576
WIRE 496 656 288 656
WIRE 784 656 496 656
WIRE 80 688 80 656
SYMBOL res 768 272 R0
SYMATTR InstName RL
SYMATTR Value 33
SYMBOL res 480 272 R0
SYMATTR InstName R3
SYMATTR Value 750
SYMBOL zener 304 608 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value MMBZ6V8ALY
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 64 416 R0
SYMATTR InstName C1
SYMATTR Value 4.7m
SYMBOL res 272 144 R0
SYMATTR InstName R2
SYMATTR Value 390
SYMBOL voltage -96 176 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL npn 720 464 R0
SYMATTR InstName Q2
SYMATTR Value BCW60A
SYMBOL zener 512 576 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value PTZ6_8B
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 48 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL npn 592 400 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL zener 304 464 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value STZ5_6N
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 768 560 R0
SYMATTR InstName R4
SYMATTR Value R=if(time>300m,100,500)
FLAG 80 688 0
FLAG 80 96 c
TEXT 312 432 Left 2 ;5.92
TEXT 320 576 Left 2 ;4.5
TEXT -130 714 Left 2 !.tran 500m
TEXT 552 576 Left 2 ;6.8
TEXT -456 752 Left 5 ;Q1. Explain the principle of this circuit.\nQ2. What's the reason for having Q1 and Q2 in that topology?\nQ3. Can we replace D3 with something else?\nQ4. What would have happened if the diodes were reversed?
TEXT 32 48 Left 2 !.ic V(c)=0
TEXT 32 -8 Left 2 ;R1=1 65mV drop instead of 650mV
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP125.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP125.asy)
V1 IN 0 5.5
R1 OUT N001 200k
XU1 OUT MP_01 N001 0 IN MP_02 MP_03 IN ADP125 ;pnba Vout))Adj)GND)En)))Vin
R2 N001 0 100k
Rload OUT 0 100
C2 OUT 0 1
C1 IN 0 1
.tran 10m startup
.lib ADP125.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 496 96 384 96
WIRE 576 96 496 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 384 112 384 96
WIRE 496 112 496 96
WIRE 576 112 576 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 192
WIRE 384 208 352 208
WIRE 496 208 496 176
WIRE 576 208 576 192
WIRE 384 224 384 208
WIRE 256 272 256 256
WIRE 384 320 384 304
SYMBOL cap 480 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 368 96 R0
SYMATTR InstName R1
SYMATTR Value 200k
SYMBOL res 560 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL res 368 208 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL ADP125 256 208 R0
SYMATTR InstName U1
FLAG 0 208 0
FLAG 256 272 0
FLAG 384 320 0
FLAG 496 208 0
FLAG 576 208 0
FLAG 576 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT -8 304 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\124000622116_CmosLinTest_1.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N002 In N001 N001 PMOS
V1 N003 0 SINE(0 10m 1e6) AC 1
R1 In N002 1e5 tol=1 pwr=0.1
C2 Out N002 10n
V2 N001 0 10
C1 In N003 1n
M2 N002 In 0 0 NMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 10u 0 1n
.Fourier 1e6 V(In)
.Fourier 1e6 V(Out)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -256 80 -272 80
WIRE -256 128 -256 80
WIRE -256 224 -256 192
WIRE -256 368 -256 304
WIRE -160 80 -256 80
WIRE -160 192 -160 80
WIRE -160 304 -160 192
WIRE -128 192 -160 192
WIRE -48 80 -160 80
WIRE -48 304 -160 304
WIRE 0 64 0 48
WIRE 0 192 -48 192
WIRE 0 192 0 160
WIRE 0 224 0 192
WIRE 0 368 -256 368
WIRE 0 368 0 320
WIRE 32 192 0 192
WIRE 112 192 96 192
WIRE 112 192 112 176
WIRE 160 336 160 320
WIRE 192 48 0 48
WIRE 192 176 192 48
WIRE 192 320 160 320
WIRE 192 320 192 256
WIRE 192 368 0 368
WIRE 192 368 192 320
IOPIN -272 80 In
IOPIN 112 176 Out
SYMBOL cap 96 176 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL voltage 192 160 M0
WINDOW 0 4 10 Left 0
WINDOW 3 15 56 Right 0
WINDOW 123 -67 188 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL res -144 176 M90
WINDOW 0 -2 49 VBottom 0
WINDOW 3 46 51 VTop 0
SYMATTR InstName R1
SYMATTR Value 1e5
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL cap -240 128 M0
WINDOW 0 -33 0 Left 0
WINDOW 3 -47 31 Left 0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL nmos -48 224 R0
SYMATTR InstName M2
SYMBOL voltage -256 208 M0
WINDOW 0 -15 57 Left 0
WINDOW 3 51 161 VLeft 0
WINDOW 123 -81 108 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10m 1e6)
SYMATTR Value2 AC 1
SYMBOL pmos -48 160 M180
SYMATTR InstName M1
FLAG -272 80 In
FLAG 160 336 0
FLAG 112 176 Out
TEXT -192 32 Left 0 !.tran 0 10u 0 1n
TEXT -240 384 Left 0 !.Fourier 1e6 V(In)
TEXT 8 384 Left 0 !.Fourier 1e6 V(Out)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3523-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3523-2.asy)
R1 OUT1 N004 634K
R2 N004 0 365K
C2 OUT2 0 10
Rload2 OUT2 0 6
L1 IN N001 4.7
L2 N002 OUT2 4.7
R3 OUT2 N003 511K
C1 OUT1 0 10
C3 OUT2 N003 10p
XU1 N004 IN NC_01 OUT1 N001 0 0 N002 IN NC_02 NC_03 N003 IN 0 IN IN LTC3523-2 ;pnba FB1)Vin1)Pgood1)Vout)SW1)GND1)GND2)SW2)Vin2)Mode)Pgood2)FB2)_SHDN2)GND3)Vbat)_SHDN1
R4 N003 0 511K
Rload1 OUT1 0 16.5
V1 IN 0 2
.tran .6m startup
.lib LTC3523-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 16 -64 -64 -64
WIRE 160 -64 16 -64
WIRE 240 -64 160 -64
WIRE 320 -64 240 -64
WIRE 400 -64 320 -64
WIRE -64 -48 -64 -64
WIRE 160 -48 160 -64
WIRE 240 -48 240 -64
WIRE 320 -48 320 -64
WIRE 16 16 16 -64
WIRE 96 16 16 16
WIRE 400 16 400 -64
WIRE 400 16 384 16
WIRE 16 32 16 16
WIRE -64 48 -64 32
WIRE 16 128 16 112
WIRE 96 128 16 128
WIRE 400 128 384 128
WIRE 512 128 480 128
WIRE 576 128 512 128
WIRE 672 128 576 128
WIRE 752 128 672 128
WIRE 576 144 576 128
WIRE 672 144 672 128
WIRE 752 144 752 128
WIRE 512 160 512 128
WIRE -96 240 -240 240
WIRE 0 240 -96 240
WIRE 96 240 0 240
WIRE 512 240 512 224
WIRE 512 240 384 240
WIRE 576 240 576 224
WIRE 576 240 512 240
WIRE 672 240 672 208
WIRE 752 240 752 224
WIRE -240 256 -240 240
WIRE -96 256 -96 240
WIRE 0 256 0 240
WIRE 576 256 576 240
WIRE -240 352 -240 336
WIRE -96 352 -96 320
WIRE 0 352 0 336
WIRE 96 352 0 352
WIRE 576 352 576 336
WIRE 0 368 0 352
WIRE 0 464 0 448
WIRE 160 544 160 528
WIRE 240 544 240 528
WIRE 320 544 320 528
SYMBOL ind 0 16 R0
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL cap -112 256 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL cap 656 144 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL res -16 352 R0
SYMATTR InstName R2
SYMATTR Value 365K
SYMBOL res -256 240 R0
SYMATTR InstName Rload1
SYMATTR Value 16.5
SYMBOL voltage -64 -64 R0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL cap 496 160 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL res 560 128 R0
SYMATTR InstName R3
SYMATTR Value 511K
SYMBOL PowerProducts\\LTC3523-2 240 240 R0
SYMATTR InstName U1
SYMBOL ind 384 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 4.7
SYMBOL res 560 240 R0
SYMATTR InstName R4
SYMATTR Value 511K
SYMBOL res 736 128 R0
SYMATTR InstName Rload2
SYMATTR Value 6
SYMBOL res -16 240 R0
SYMATTR InstName R1
SYMATTR Value 634K
FLAG 240 544 0
FLAG 160 544 0
FLAG 320 544 0
FLAG -64 48 0
FLAG 0 464 0
FLAG -96 352 0
FLAG -240 352 0
FLAG 576 352 0
FLAG 672 240 0
FLAG 752 240 0
FLAG -64 -64 IN
FLAG -240 240 OUT1
FLAG 752 128 OUT2
TEXT 520 464 Left 2 !.tran .6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\79cfbe7038b8_Vbe_break.asc
* Generated by LTspice 26.0.1 for Windows.
*Choose Is of diode 10^-10 lower than Is of transistor
* With external diode
* With subcircuit
* Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal transistor operation.
R3 in N002 1k
XQ2 0 N002 N004 Q2N2907 ;pnba C)B)E
V1 in 0 0
D1 E B DEB
Q1 0 N001 N003 0 2N2907
Q1 C B E 2N2907
R1 in N001 1k
D1 N003 N001 VBEDIO
R2 N003 0 1k
R4 N004 0 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 -10 10 0.1
.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
.SUBCKT Q2N2907 C B E
.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1480 744
WIRE 304 224 304 288
WIRE 304 480 -128 480
WIRE 208 208 208 176
WIRE 208 176 240 176
WIRE 208 176 48 176
WIRE -128 480 -128 304
WIRE -128 176 -128 224
WIRE -32 176 -128 176
WIRE -128 512 -128 480
WIRE 304 128 304 48
WIRE 304 48 448 48
WIRE 448 48 448 480
WIRE 448 480 304 480
WIRE 304 416 304 480
WIRE 208 272 208 288
WIRE 208 288 304 288
WIRE 304 288 304 336
WIRE 960 224 960 336
WIRE 816 176 896 176
WIRE 960 128 960 48
WIRE 960 48 1104 48
WIRE 1104 48 1104 480
WIRE 1104 480 960 480
WIRE 960 416 960 480
WIRE 736 176 672 176
WIRE 960 512 960 480
RECTANGLE Normal 416 320 96 96
SYMBOL res 720 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL pnp 896 128 R0
WINDOW 3 79 79 Left 0
SYMATTR Value Q2N2907
SYMATTR InstName Q2
SYMATTR Prefix X
SYMBOL pnp 240 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL diode 224 272 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMATTR Value VBEDIO
SYMBOL res 944 320 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res -48 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -128 208 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL res 288 320 R0
SYMATTR InstName R2
SYMATTR Value 1k
FLAG -128 512 0
FLAG -128 176 in
FLAG 672 176 in
FLAG 960 512 0
TEXT -128 -200 Left 0 !.dc V1 -10 10 0.1
TEXT -144 -8 Left 0 !.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
TEXT 640 -136 Left 0 !.SUBCKT Q2N2907  C B E\nQ1 C B E  2N2907\nD1 E B DEB\n*Choose Is of diode 10^-10 lower than Is of transistor\n.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)\n.ENDS
TEXT -136 -56 Left 0 ;With external diode
TEXT 640 -184 Left 0 ;With subcircuit
TEXT -144 -424 Left 0 ;Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal  transistor operation.
* Z:\home\khalils\Downloads\files\data\raw_asc\3265425743bd_1.1.1.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 MC14007_N
VDS N001 0 0
VGS N002 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model MC14007_N NMOS (Vto=1.6 Kp=1.1m)
.model MC14007_P PMOS (Vto=-1.3 Kp=1.4m)
.dc VDS 0 5 0.01 VGS 0 5 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 32 -432 32
WIRE -432 64 -432 32
WIRE -480 144 -624 144
WIRE -624 176 -624 144
WIRE -176 176 -176 32
WIRE -624 320 -624 256
WIRE -432 320 -432 160
WIRE -432 320 -624 320
WIRE -176 320 -176 256
WIRE -176 320 -432 320
WIRE -432 368 -432 320
SYMBOL voltage -176 160 R0
SYMATTR InstName VDS
SYMATTR Value 0
SYMBOL voltage -624 160 R0
SYMATTR InstName VGS
SYMATTR Value 0
SYMBOL nmos -480 64 R0
SYMATTR InstName M1
SYMATTR Value MC14007_N
FLAG -432 368 0
TEXT 16 -72 Left 1 !.model MC14007_N NMOS (Vto=1.6 Kp=1.1m)
TEXT 16 -48 Left 1 !.model MC14007_P PMOS (Vto=-1.3 Kp=1.4m)
TEXT -768 392 Left 2 !.dc VDS 0 5 0.01 VGS 0 5 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG752.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG752.asy)
V1 SA 0 3
C1 D 0 36p
V3 IN 0 PULSE(0 3 0 20n 20n 10u 20u)
R1 D 0 301
V2 SB 0 0
V4 +V 0 5
XU1 IN SA D SB +V 0 ADG752 ;pnba IN)SA)D)SB)Vdd)GND
.tran 100u
.lib ADG752.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1728 -272 -2032 -272
WIRE -1696 -272 -1728 -272
WIRE -2032 -256 -2032 -272
WIRE -1472 -240 -1504 -240
WIRE -1424 -240 -1472 -240
WIRE -1312 -240 -1424 -240
WIRE -1424 -224 -1424 -240
WIRE -1312 -224 -1312 -240
WIRE -1728 -208 -1920 -208
WIRE -1696 -208 -1728 -208
WIRE -1920 -192 -1920 -208
WIRE -2032 -160 -2032 -176
WIRE -1728 -144 -1776 -144
WIRE -1696 -144 -1728 -144
WIRE -1424 -128 -1424 -144
WIRE -1312 -128 -1312 -160
WIRE -1920 -96 -1920 -112
WIRE -1776 -80 -1776 -144
WIRE -1600 -16 -1600 -32
WIRE -1776 32 -1776 0
SYMBOL voltage -2032 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL cap -1328 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -1920 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL res -1440 -240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -2032 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL voltage -1776 -96 R0
WINDOW 3 24 136 Left 2
SYMATTR Value PULSE(0 3 0 20n 20n 10u 20u)
SYMATTR InstName V3
SYMBOL ADG752 -1600 -192 R0
SYMATTR InstName U1
FLAG -2032 -160 0
FLAG -1920 -96 0
FLAG -1776 32 0
FLAG -1600 -368 +V
FLAG -1424 -128 0
FLAG -1600 -16 0
FLAG -1312 -128 0
FLAG -2032 16 0
FLAG -2032 -64 +V
FLAG -1728 -272 SA
FLAG -1728 -208 SB
FLAG -1728 -144 IN
FLAG -1472 -240 D
TEXT -1960 8 Left 2 !.tran 100u
TEXT -2088 -480 Left 2 ;Note:\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\0ae4273b13cd_BVco.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Ctrl 0 1k
B2 Out2 0 I={cos(v(ctrl)**2*1e3*time)/1e3}
V1 Ctrl 0 PWL(0 0 1m {pi*2})
B1 Out1 0 V={sin(v(ctrl)*5e3*time)}
R3 Out2 0 1k
R2 Out1 0 1k
.tran 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -208 224 -208 208
WIRE -208 336 -208 304
WIRE -208 352 -208 336
WIRE -144 208 -208 208
WIRE -144 224 -144 208
WIRE -144 336 -208 336
WIRE -144 336 -144 304
WIRE -112 208 -144 208
WIRE 0 192 0 160
WIRE 0 336 -144 336
WIRE 0 336 0 272
WIRE 64 160 0 160
WIRE 112 160 64 160
WIRE 112 192 112 160
WIRE 112 336 0 336
WIRE 112 336 112 272
WIRE 224 208 224 160
WIRE 224 336 112 336
WIRE 224 336 224 288
WIRE 288 160 224 160
WIRE 368 160 288 160
WIRE 368 224 368 160
WIRE 368 336 224 336
WIRE 368 336 368 304
IOPIN -112 208 Out
SYMBOL bv 0 176 R0
WINDOW 3 -182 182 Left 0
WINDOW 0 -15 60 Left 0
SYMATTR Value V={sin(v(ctrl)*5e3*time)}
SYMATTR InstName B1
SYMBOL res 96 176 R0
WINDOW 0 -37 37 Left 0
WINDOW 3 -32 73 Left 0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -208 208 R0
WINDOW 0 -16 58 Left 0
WINDOW 3 -49 -43 VRight 0
WINDOW 123 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m {pi*2})
SYMBOL res -160 208 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL bi 224 208 R0
WINDOW 3 -115 151 Left 0
SYMATTR Value I={cos(v(ctrl)**2*1e3*time)/1e3}
SYMATTR InstName B2
SYMBOL res 352 208 R0
WINDOW 0 -43 32 Left 0
WINDOW 3 -42 62 Left 0
SYMATTR InstName R3
SYMATTR Value 1k
FLAG -208 352 0
FLAG -112 208 Ctrl
FLAG 64 160 Out1
FLAG 288 160 Out2
TEXT -202 178 Left 0 !.tran 1m