* Z:\home\khalils\Downloads\files\data\raw_asc\013807eeb9de_pluto-a.asc
* Generated by LTspice 26.0.1 for Windows.
* Bitline to array0
* Bitline to array1
* Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
* Word line in array 0
* Word line in array 1
* .step param X 0.0v 1.5v 0.1v
* DRAM Circuit Parameters
* ohm
* Bitline Resistance
* Cell Array
* Sense Amp.
* Voltage
* Wordline Activation
* 1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
* Technology Scaling
* Wordline Parasitics
* bitline enable
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
R3 bl_ival bl_ival 1m
R1 bitline bitline0 {mc(bitline_R, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
VDD_source VDD 0 {core_voltage}
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 0 0) Rser=100 Cpar=1fF
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
R2 bitline1 N001 {mc(bitline_R, process_var)}
Veq0 Eq0 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
M7 bitline ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
CBL_cap_1 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M5 bitline0 Eq2 VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
CBL_cap_0 bitline 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
M8 N001 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
CBL_starting_value_cap bl_ival 0 10f V=1
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 0 0) Rser=100 Cpar=1fF
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
Veq1 Eq1 0 PULSE({core_voltage*1.2} {core_voltage*1.2} 0 0 0 0)
VDD_source1 PV 0 {plate_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
M4 bitline1 Eq2 bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Vbl_en bl_en 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M12 NC_01 bl_en NC_02 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
Veq2 Eq2 0 PULSE(0 0 0 0 0 0)
M6 VDDby2 Eq2 bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include ./transistor_model.pm
.tran 120ns uic
.param process_var=0.25
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=512
.param core_voltage=1.1V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=512
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.ic V(bitline)=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2520
WIRE -1392 -1888 -1392 -1904
WIRE -1392 -1792 -1392 -1808
WIRE -1392 -1648 -1392 -1664
WIRE -1392 -1552 -1392 -1568
WIRE 800 -1536 768 -1536
WIRE 864 -1536 800 -1536
WIRE 768 -1440 768 -1456
WIRE 864 -1440 864 -1536
WIRE 864 -1440 768 -1440
WIRE 768 -1392 624 -1392
WIRE 624 -1360 624 -1392
WIRE 304 -1280 96 -1280
WIRE 576 -1280 304 -1280
WIRE 624 -1232 624 -1264
WIRE 624 -1232 384 -1232
WIRE -608 -1152 -608 -1184
WIRE -240 -1152 -240 -1184
WIRE 384 -1152 384 -1232
WIRE -1584 -1136 -1584 -1152
WIRE 384 -1136 384 -1152
WIRE -4256 -1104 -4256 -1120
WIRE -3504 -1104 -3504 -1120
WIRE -2576 -1104 -2576 -1120
WIRE -1584 -1040 -1584 -1056
WIRE -608 -1040 -608 -1072
WIRE -240 -1040 -240 -1072
WIRE -4256 -1008 -4256 -1024
WIRE -3504 -1008 -3504 -1024
WIRE -2576 -1008 -2576 -1024
WIRE 384 -976 384 -1072
WIRE 768 -848 768 -1392
WIRE 832 -848 768 -848
WIRE 768 -656 768 -848
WIRE -800 -624 -800 -656
WIRE -512 -624 -512 -656
WIRE -208 -624 -208 -656
WIRE 1456 -560 1408 -560
WIRE 1584 -560 1456 -560
WIRE -800 -512 -800 -544
WIRE -512 -512 -512 -544
WIRE -208 -512 -208 -544
WIRE 768 -496 768 -656
WIRE 432 -464 384 -464
WIRE 640 -464 432 -464
WIRE 832 -384 688 -384
WIRE 912 -384 832 -384
WIRE 1040 -384 912 -384
WIRE 832 -352 832 -384
WIRE 1040 -352 1040 -384
WIRE 912 -336 880 -336
WIRE 992 -336 960 -336
WIRE 1312 -256 1120 -256
WIRE 768 -240 768 -416
WIRE 832 -240 832 -256
WIRE 832 -240 768 -240
WIRE 912 -240 960 -336
WIRE 912 -240 832 -240
WIRE 960 -240 912 -336
WIRE 1040 -240 1040 -256
WIRE 1040 -240 960 -240
WIRE 1120 -240 1120 -256
WIRE 1120 -240 1040 -240
WIRE 768 -144 768 -240
WIRE 912 -144 768 -144
WIRE 1120 -144 1120 -240
WIRE 1120 -144 1008 -144
WIRE 640 -96 608 -96
WIRE 880 -96 640 -96
WIRE 928 -96 880 -96
WIRE 1056 -96 928 -96
WIRE 1296 -96 1056 -96
WIRE 880 -80 880 -96
WIRE 1056 -80 1056 -96
WIRE 768 -48 768 -144
WIRE 768 -32 768 -48
WIRE 800 -32 768 -32
WIRE 944 -32 896 -32
WIRE 976 -32 944 -32
WIRE 1120 -32 1120 -144
WIRE 1120 -32 1072 -32
WIRE 1312 -32 1312 -256
WIRE 1120 -16 1120 -32
WIRE 944 16 944 -32
WIRE 944 32 944 16
WIRE 768 80 768 -32
WIRE 832 80 768 80
WIRE 912 80 832 80
WIRE 1040 80 976 80
WIRE 1120 80 1120 -16
WIRE 1120 80 1040 80
WIRE 832 96 832 80
WIRE 1040 96 1040 80
WIRE 1312 128 1312 48
WIRE 1360 128 1312 128
WIRE 912 176 976 80
WIRE 912 176 880 176
WIRE 976 176 912 80
WIRE 992 176 976 176
WIRE 1360 176 1360 128
WIRE 832 224 832 192
WIRE 832 224 720 224
WIRE 960 224 832 224
WIRE 1040 224 1040 192
WIRE 1040 224 960 224
WIRE 672 304 416 304
WIRE 1312 400 1312 128
WIRE 1312 400 1200 400
WIRE 1200 432 1200 400
WIRE 1088 544 880 544
WIRE 1152 544 1152 512
WIRE 1152 544 1088 544
WIRE 1200 576 1200 528
WIRE 1200 592 1200 576
WIRE 1312 704 1312 400
SYMBOL voltage -512 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL nmos4 576 -1360 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -208 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL pmos4 640 -384 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL nmos4 672 224 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL nmos4 880 96 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL voltage -2576 -1120 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq0
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL res 752 -1552 R0
SYMATTR InstName R3
SYMATTR Value 1m
SYMBOL cap 864 -1520 R270
WINDOW 3 -2 50 VBottom 2
WINDOW 0 37 156 VTop 2
SYMATTR Value 10f
SYMATTR InstName BL_starting_value_cap
SYMATTR SpiceLine V=1
SYMBOL nmos4 976 -80 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL res 752 -512 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL cap 816 -848 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL nmos4 992 96 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 800 -80 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1008 -96 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL voltage -1392 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -1584 -1152 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL cap 1184 592 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL nmos4 1584 -640 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL res 1296 -48 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL cap 368 -1136 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL voltage -608 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0 0)
SYMATTR InstName Vsp
SYMBOL voltage -3504 -1120 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq1
SYMATTR Value PULSE({core_voltage*1.2} {core_voltage*1.2} 0 0 0 0)
SYMBOL voltage -4256 -1120 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq2
SYMATTR Value PULSE(0 0 0 0 0 0)
SYMBOL voltage -1392 -1904 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vbl_en
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 992 -256 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 880 -256 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL cap 1344 176 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL nmos4 1152 432 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -240 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 0 0)
SYMATTR InstName Vsn
FLAG -3504 -1008 0
FLAG -3504 -1120 Eq1
FLAG 720 272 0
FLAG -608 -1040 0
FLAG -608 -1184 sense_P
FLAG 1040 144 0
FLAG 832 144 0
FLAG 960 -144 0
FLAG 848 -32 0
FLAG 1024 -32 0
FLAG 640 -96 Eq2
FLAG 944 16 VDDby2
FLAG 416 304 sense_N
FLAG 720 320 0
FLAG 768 -48 bitline0
FLAG 1120 -16 bitline1
FLAG 624 -1312 0
FLAG 384 -1152 mb0
FLAG 304 -1280 ra0
FLAG 1200 480 0
FLAG 1200 656 0
FLAG 1200 576 mb3
FLAG 1088 544 ra3
FLAG -1392 -1552 0
FLAG -1392 -1664 ra0
FLAG 688 -432 VDD
FLAG 1040 -304 VDD
FLAG 832 -304 VDD
FLAG 688 -480 VDD
FLAG 432 -464 sense_p
FLAG 912 -384 ACT
FLAG 960 224 NLAT
FLAG -240 -1040 0
FLAG -240 -1184 sense_N
FLAG 832 -784 0
FLAG 1360 240 0
FLAG -1584 -1152 ra3
FLAG -1584 -1040 0
FLAG -800 -512 0
FLAG -800 -656 VDD
FLAG -512 -512 0
FLAG -512 -656 VDDby2
FLAG 384 -976 PV
FLAG -208 -512 0
FLAG -208 -656 PV
FLAG 1632 -592 0
FLAG -1392 -1792 0
FLAG -1392 -1904 bl_en
FLAG 1456 -560 bl_en
FLAG -2576 -1008 0
FLAG -2576 -1120 Eq0
FLAG -4256 -1008 0
FLAG -4256 -1120 Eq2
FLAG 928 -1536 0
FLAG 800 -1536 bl_ival
FLAG 768 -656 bitline
TEXT -704 128 Left 2 !.include ./transistor_model.pm
TEXT 800 -952 VLeft 2 ;Bitline to array0
TEXT 1296 368 VLeft 2 ;Bitline to array1
TEXT -776 96 Left 2 !.tran 120ns uic
TEXT -744 216 Left 2 ;Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
TEXT 48 -1296 Left 2 ;Word line in array 0
TEXT 832 528 Left 2 ;Word line in array 1
TEXT -696 160 Left 2 ;.step param X 0.0v 1.5v 0.1v
TEXT -1160 72 Left 2 !.param process_var=0.25
TEXT -1160 32 Left 2 !.step param run 1 100 1
TEXT -1160 448 Left 2 !.param cell_cap={24.0fF*cell_cap_factor}
TEXT -1160 488 Left 2 !.param bitline_cap={85fF*bl_cap_factor}
TEXT -1248 160 Left 2 ;DRAM Circuit Parameters
TEXT -1160 528 Left 2 !.param access_tran_L={85nm*access_tran_L_factor}
TEXT -1160 568 Left 2 !.param access_tran_W={55nm*access_tran_W_factor}
TEXT -1152 1256 Left 2 !.param bitline_R=R_per_cell*cells_per_BL
TEXT -880 1192 Left 2 ;ohm
TEXT -1152 1192 Left 2 !.param R_per_cell=40
TEXT -1152 1160 Left 2 ;Bitline Resistance
TEXT -1152 752 Left 2 !.param SA_nmos_L={160nm*SA_nmos_L_factor}
TEXT -1152 776 Left 2 !.param SA_nmos_W={1900nm*SA_nmos_W_factor}
TEXT -1152 808 Left 2 !.param SA_pmos_L={160nm*SA_pmos_L_factor}
TEXT -1152 832 Left 2 !.param SA_pmos_W={1330nm*SA_pmos_W_factor}
TEXT -1152 872 Left 2 !.param SA_eq_L=96.3nm
TEXT -1152 896 Left 2 !.param SA_eq_W=541nm
TEXT -1152 936 Left 2 !.param SA_nset_L={270nm*SA_nset_L_factor}
TEXT -1152 960 Left 2 !.param SA_nset_W={220nm*SA_nset_W_factor}
TEXT -1152 1000 Left 2 !.param SA_pset_L={270nm*SA_pset_L_factor}
TEXT -1152 1024 Left 2 !.param SA_pset_W={220nm*SA_pset_W_factor}
TEXT -1152 1224 Left 2 !.param cells_per_BL=512
TEXT -1160 416 Left 2 ;Cell Array
TEXT -1152 720 Left 2 ;Sense Amp.
TEXT -1160 216 Left 2 ;Voltage
TEXT -1160 240 Left 2 !.param core_voltage=1.1V
TEXT -1160 280 Left 2 !.param wordline_voltage=2.9V
TEXT -1160 608 Left 2 !.param cell0_charge=core_voltage*cells_charge_state
TEXT -1160 648 Left 2 !.param cells_charge_state=0.8
TEXT -1160 312 Left 2 !.param pv_modifier=0.5
TEXT -1160 352 Left 2 !.param plate_voltage={core_voltage*pv_modifier}
TEXT -1152 1072 Left 2 !.param psense_act=4ns
TEXT -1152 1096 Left 2 !.param nsense_act=4ns
TEXT -1144 1512 Left 2 ;Wordline Activation
TEXT -1144 1544 Left 2 !.param wl0_act=1.0
TEXT -1152 1632 Left 2 !.param tech_node=7
TEXT -904 1632 Left 2 ;1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
TEXT -1152 1600 Left 2 ;Technology Scaling
TEXT -1152 1664 Left 2 !.param cell_cap_factor={0.95**tech_node}
TEXT -1152 1696 Left 2 !.param bl_cap_factor={0.95**tech_node}
TEXT -1152 1728 Left 2 !.param access_tran_L_factor={0.95**tech_node}
TEXT -1152 1760 Left 2 !.param access_tran_W_factor={0.85**tech_node}
TEXT -1152 1792 Left 2 !.param SA_nmos_L_factor={0.93**tech_node}
TEXT -1152 1816 Left 2 !.param SA_nmos_W_factor={0.93**tech_node}
TEXT -1152 1848 Left 2 !.param SA_pmos_L_factor={0.93**tech_node}
TEXT -1152 1872 Left 2 !.param SA_pmos_W_factor={0.93**tech_node}
TEXT -1152 1904 Left 2 !.param SA_nset_L_factor={0.93**tech_node}
TEXT -1152 1928 Left 2 !.param SA_nset_W_factor={0.93**tech_node}
TEXT -1152 1960 Left 2 !.param SA_pset_L_factor={0.93**tech_node}
TEXT -1152 1984 Left 2 !.param SA_pset_W_factor={0.95**tech_node}
TEXT -1152 1440 Left 2 !.param wordline_C={WL_C_per_cell*cells_per_LWL}
TEXT -1152 1376 Left 2 !.param WL_C_per_cell=0.07fF
TEXT -1152 1320 Left 2 ;Wordline Parasitics
TEXT -1152 1344 Left 2 !.param cells_per_LWL=512
TEXT -1152 1408 Left 2 !.param WL_R_per_cell=40ohm
TEXT -1152 1472 Left 2 !.param wordline_R={WL_R_per_cell*cells_per_LWL}
TEXT -1152 2016 Left 2 !.param WL_cap_factor={0.95**tech_node}
TEXT -1152 2048 Left 2 !.param WL_res_factor={0.95**tech_node}
TEXT 1392 -544 Left 2 ;bitline enable
TEXT 768 -1680 Left 2 !.ic V(bitline)=1