* Z:\home\khalils\Downloads\files\data\raw_asc\052b7d484206_hw7_prob2.asc
* Generated by LTspice 26.0.1 for Windows.
* Phasor-domain testbench schematic for checking your work on Problem 2:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nI(V2) in the report is the phasor loop current flowing clockwise, and V(vx) \nin the report is the phasor voltage Vx\n \nthere is nothing to plot for this verification testbench\n \nthe angular frequency of operation for this testbench is 40 rps, which is \n40/(2*pi) ~ 6.3662 Hz\n \nnote that Problem 2 is asking for Vx(t), so your answer should be a time-\ndomain waveform; this phasor-domain testbench is only to be used for \nverifying your phasor-domain work\n \nthe inductor series resistance (Rser) has been set to zero; do not change \nthis!
E1 vx 0 vxpos vxneg 1
L1 N003 vxpos 100m Rser=0
R2 0 vxneg 5
V1 N001 0 0 AC 100 0
V2 N001 N002 0
R1 N002 N003 10
L2 vxneg N005 200m Rser=0
C1 N004 vxpos 5m
V3 N004 N005 0 AC 40 -30
.options plotwinsize=0 numdgt=15 measdgt=15
.ac list {40/(2*pi)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 432 -112 352 -112
WIRE 496 -112 432 -112
WIRE -608 -80 -672 -80
WIRE -464 -80 -528 -80
WIRE -336 -80 -384 -80
WIRE -208 -80 -256 -80
WIRE -176 -80 -208 -80
WIRE -48 -80 -112 -80
WIRE 352 -48 352 -112
WIRE -672 -32 -672 -80
WIRE -48 -32 -48 -80
WIRE 240 -32 224 -32
WIRE 304 -32 240 -32
WIRE 240 16 224 16
WIRE 304 16 240 16
WIRE -672 80 -672 48
WIRE -512 80 -672 80
WIRE -464 80 -512 80
WIRE -352 80 -384 80
WIRE -304 80 -352 80
WIRE -48 80 -48 48
WIRE -48 80 -224 80
WIRE 352 96 352 32
WIRE -512 112 -512 80
SYMBOL e 352 -64 R0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL ind -352 -64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100m
SYMATTR SpiceLine Rser=0
SYMBOL voltage -48 -48 R0
WINDOW 123 24 124 Left 2
SYMATTR Value2 AC 40 -30
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res -480 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 5
SYMBOL res -480 -64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage -672 -48 R0
WINDOW 123 24 124 Left 2
SYMATTR Value2 AC 100 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL cap -112 -96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 5m
SYMBOL ind -320 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 200m
SYMATTR SpiceLine Rser=0
SYMBOL voltage -624 -80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
FLAG -512 112 0
FLAG -208 -80 vxpos
FLAG -352 80 vxneg
FLAG 352 96 0
FLAG 240 -32 vxpos
FLAG 240 16 vxneg
FLAG 432 -112 vx
TEXT -592 -784 Left 2 ;Phasor-domain testbench schematic for checking your work on Problem 2:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nI(V2) in the report is the phasor loop current flowing clockwise, and V(vx) \nin the report is the phasor voltage Vx\n \nthere is nothing to plot for this verification testbench\n \nthe angular frequency of operation for this testbench is 40 rps, which is \n40/(2*pi) ~ 6.3662 Hz\n \nnote that Problem 2 is asking for Vx(t), so your answer should be a time-\ndomain waveform; this phasor-domain testbench is only to be used for \nverifying your phasor-domain work\n \nthe inductor series resistance (Rser) has been set to zero; do not change \nthis!
TEXT -432 328 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ac list {40/(2*pi)}