Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\abd349e5af71_transistor_vth.asc
* Generated by LTspice 26.0.1 for Windows.
* .step param Vgate 0.0V 3V 0.2V
M19 ds gate 0 gate pmos l=access_tran_L w=access_tran_W
V1 N001 0 10mV
R1 N002 gate 1k
I1 0 thresh_current {vth_current}
V2 N002 0 PULSE(0 30 0 1 0 0 1)
Rthresh_res thresh_current 0 100
R2 N001 ds 100
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include ../DRAM_models/transistor_model.pm
.tran 1
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param tech_node=7
.param vth_current={(access_tran_W/access_tran_L)*100nA}
.OPTIONS plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2520
WIRE -2240 -736 -2432 -736
WIRE -2432 -704 -2432 -736
WIRE -2240 -688 -2240 -736
WIRE -2384 -576 -2432 -576
WIRE -2704 -544 -2816 -544
WIRE -2560 -544 -2624 -544
WIRE -2512 -544 -2560 -544
WIRE -2480 -544 -2512 -544
WIRE -2816 -480 -2816 -544
WIRE -2432 -464 -2432 -528
WIRE -2512 -400 -2512 -544
WIRE -2384 -400 -2384 -576
WIRE -2384 -400 -2512 -400
WIRE -2800 -144 -2896 -144
WIRE -2800 -128 -2800 -144
WIRE -2896 -48 -2896 -144
WIRE -2800 -16 -2800 -48
WIRE -2896 16 -2896 -48
SYMBOL voltage -2240 -704 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 10mV
SYMBOL res -2720 -528 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -2816 -496 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 30 0 1 0 0 1)
SYMBOL current -2896 96 M180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value {vth_current}
SYMBOL nmos4 -2480 -624 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M19
SYMATTR Value pmos
SYMATTR Value2 l=access_tran_L w=access_tran_W
SYMBOL res -2816 -144 R0
SYMATTR InstName thresh_res
SYMATTR Value 100
SYMBOL res -2448 -720 R0
SYMATTR InstName R2
SYMATTR Value 100
FLAG -2240 -608 0
FLAG -2432 -464 0
FLAG -2816 -400 0
FLAG -2432 -624 ds
FLAG -2560 -544 gate
FLAG -2896 96 0
FLAG -2800 -16 0
FLAG -2896 -48 thresh_current
TEXT -2360 -264 Left 2 !.include ../DRAM_models/transistor_model.pm
TEXT -2352 -296 Left 2 !.tran 1
TEXT -2352 -224 Left 2 ;.step param Vgate 0.0V 3V 0.2V
TEXT -2352 -80 Left 2 !.param access_tran_L={85nm*access_tran_L_factor}
TEXT -2352 -48 Left 2 !.param access_tran_W={55nm*access_tran_W_factor}
TEXT -2352 8 Left 2 !.param access_tran_L_factor={0.95**tech_node}
TEXT -2352 40 Left 2 !.param access_tran_W_factor={0.85**tech_node}
TEXT -2344 -120 Left 2 !.param tech_node=7
TEXT -2352 96 Left 2 !.param vth_current={(access_tran_W/access_tran_L)*100nA}
TEXT -2352 -184 Left 2 !.OPTIONS plotwinsize=0
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX9636.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX9636.asy)
XU1 IN OUT Vcc Vee OUT Vcc MAX9636 ;pnba In+)In-)V+)V-)OUT)SHDN
CL OUT 0 15p
Vcc Vcc 0 2.5
Vee 0 Vee 2.5
RL OUT 0 10k
V1 IN 0 SINE(0 50m 10k)
.tran 100u
.lib MAX9636.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 64 288 64 272
WIRE 416 352 416 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 64 448 64 400
WIRE 416 448 416 416
WIRE 448 448 448 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 64 544 64 528
WIRE 304 592 304 576
SYMBOL MAX9636 432 400 R0
SYMATTR InstName U1
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 10k)
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
FLAG 720 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 416 320 Vcc
FLAG 416 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
FLAG 448 448 Vcc
TEXT 16 632 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\1defa79519ff_002-non-inverting-amplifier.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 Vin N002 N001 N003 Vout OP491 ;pnba In+)In-)V+)V-)OUT
V1 N003 0 -2.5
V2 N001 0 2.5
R2 N002 0 10k
R3 Vout N002 10k
V3 Vin 0 SINE(0 0.2 50)
.tran 0 60m 0 1u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP491.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 -176 208 -176
WIRE 208 -144 208 -176
WIRE 208 -48 208 -64
WIRE 144 32 112 32
WIRE 384 32 224 32
WIRE 272 112 272 -176
WIRE 0 128 -96 128
WIRE 112 128 112 32
WIRE 112 128 80 128
WIRE 240 128 112 128
WIRE 384 144 384 32
WIRE 384 144 304 144
WIRE 448 144 384 144
WIRE 240 160 96 160
WIRE 96 192 96 160
WIRE 96 208 96 192
WIRE 272 240 272 176
WIRE -96 272 -96 128
WIRE 96 320 96 288
WIRE 272 352 272 320
FLAG 272 352 0
FLAG 208 -48 0
FLAG -96 272 0
FLAG 96 192 Vin
IOPIN 96 192 In
FLAG 448 144 Vout
IOPIN 448 144 Out
FLAG 96 320 0
SYMBOL Opamps\\OP491 272 80 R0
SYMATTR InstName U1
SYMBOL voltage 272 224 R0
SYMATTR InstName V1
SYMATTR Value -2.5
SYMBOL voltage 208 -160 R0
SYMATTR InstName V2
SYMATTR Value 2.5
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 240 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL voltage 96 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 0.2 50)
TEXT 448 288 Left 2 !.tran 0 60m 0 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\6e3cc44b720d_4_50.asc
* Generated by LTspice 26.0.1 for Windows.
M13 NC_40 NC_41 NC_42 NC_43 NMOS
M10 N003 NC_30 NC_31 NC_32 NMOS
M7 NC_18 NC_19 NC_20 NC_21 NMOS
M14 NC_44 NC_45 NC_46 NC_47 PMOS
M1 N003 N002 NC_01 NC_02 PMOS
M2 N004 N002 N001 N001 PMOS
M6 NC_14 NC_15 NC_16 NC_17 NMOS
M12 NC_36 NC_37 NC_38 NC_39 NMOS
M4 NC_06 NC_07 NC_08 NC_09 PMOS
M9 NC_26 NC_27 NC_28 NC_29 NMOS
M8 NC_22 NC_23 NC_24 NC_25 NMOS
M3 N001 NC_03 NC_04 NC_05 PMOS
M11 N004 NC_33 NC_34 NC_35 NMOS
M5 NC_10 NC_11 NC_12 NC_13 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 948 680
WIRE 256 -112 256 -160
WIRE 416 -112 256 -112
WIRE 416 -64 416 -112
WIRE 368 -48 176 -48
WIRE 128 112 128 32
WIRE 416 112 416 32
SYMBOL pmos 368 32 M180
SYMATTR InstName M2
SYMBOL nmos 368 112 R0
SYMATTR InstName M11
SYMBOL pmos 768 -160 M180
SYMATTR InstName M14
SYMBOL pmos -16 -144 R180
SYMATTR InstName M4
SYMBOL nmos -208 -32 M0
SYMATTR InstName M7
SYMBOL pmos -304 -144 M180
SYMATTR InstName M5
SYMBOL pmos 208 -160 M180
SYMATTR InstName M3
SYMBOL nmos 816 208 R0
SYMATTR InstName M12
SYMBOL nmos 176 112 M0
SYMATTR InstName M10
SYMBOL pmos 176 32 R180
SYMATTR InstName M1
SYMBOL nmos -112 -32 R0
SYMATTR InstName M6
SYMBOL nmos -112 128 R0
SYMATTR InstName M9
SYMBOL nmos -208 128 M0
SYMATTR InstName M8
SYMBOL nmos 768 -48 R90
SYMATTR InstName M13
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2370-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2370-1.5.asy)
R1 OUT N001 10K
V1 IN 0 12
C1 OUT 0 10
L1 N002 OUT 10 Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
Rload OUT 0 20
XU1 NC_01 IN IN IN N002 OUT N001 0 ADP2370-1.5 IPSM=400m Rt=233333.3 Rb=266666.7 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=0 ;pnba FSEL)SYNC)EN)Vin)SW)FB)PG)PGND
.tran 500u startup
.lib ADP2370-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 916 692
WIRE 144 96 32 96
WIRE 176 96 144 96
WIRE 480 96 400 96
WIRE 688 96 560 96
WIRE 32 112 32 96
WIRE 144 176 144 96
WIRE 176 176 144 176
WIRE 432 176 400 176
WIRE 560 176 512 176
WIRE 688 176 688 96
WIRE 688 176 560 176
WIRE 752 176 688 176
WIRE 752 192 752 176
WIRE 32 208 32 192
WIRE 560 256 560 240
WIRE 560 256 400 256
WIRE 560 272 560 256
WIRE 752 288 752 272
WIRE 144 336 144 176
WIRE 176 336 144 336
WIRE 688 336 688 176
WIRE 688 336 400 336
SYMBOL VOLTAGE 32 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 576 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 736 176 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL ind 416 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
SYMBOL cap 544 176 R0
WINDOW 0 29 15 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2370-1.5 288 208 R0
SYMATTR InstName U1
FLAG 32 208 0
FLAG 32 96 IN
FLAG 560 272 0
FLAG 752 176 OUT
FLAG 752 288 0
TEXT 584 392 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1371.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1371.asy)
XU1 N005 N003 N006 0 N001 N002 IN LT1371 ;pnba Vc)FB)NFB)GND)SW)_SHDN)Vin
Rload OUT 0 50
R3 N004 N005 2K
L1 IN N001 4.7 Rser=0.02 Rpar=5000
R2 N003 0 6.19K
C4 N004 0 .047
D1 N001 OUT MBRS340
C2 OUT 0 22 Rser=.05
R1 OUT N003 53.6K
C3 N005 0 .0047
V1 IN 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT1371.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2752 1400
WIRE 1824 880 1472 880
WIRE 1888 880 1824 880
WIRE 2016 880 1968 880
WIRE 2064 880 2016 880
WIRE 2192 880 2128 880
WIRE 2320 880 2192 880
WIRE 2432 880 2320 880
WIRE 1472 896 1472 880
WIRE 2320 896 2320 880
WIRE 2432 896 2432 880
WIRE 2192 912 2192 880
WIRE 1824 928 1824 880
WIRE 1472 992 1472 976
WIRE 1680 992 1648 992
WIRE 2016 992 2016 880
WIRE 2016 992 1968 992
WIRE 2320 992 2320 960
WIRE 2432 992 2432 976
WIRE 2192 1072 2192 992
WIRE 2192 1072 1968 1072
WIRE 2192 1088 2192 1072
WIRE 1488 1152 1424 1152
WIRE 1584 1152 1568 1152
WIRE 1680 1152 1584 1152
WIRE 2000 1152 1968 1152
WIRE 1424 1168 1424 1152
WIRE 1584 1168 1584 1152
WIRE 2192 1184 2192 1168
WIRE 1824 1232 1824 1216
WIRE 1424 1248 1424 1232
WIRE 1584 1248 1584 1232
SYMBOL polcap 2304 896 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=.05
SYMBOL schottky 2064 896 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL CAP 1408 1168 R0
WINDOW 3 26 56 Left 2
SYMATTR Value .047
SYMATTR InstName C4
SYMBOL RES 1472 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 2K
SYMBOL CAP 1568 1168 R0
WINDOW 3 27 55 Left 2
SYMATTR Value .0047
SYMATTR InstName C3
SYMBOL res 2416 880 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL POWERPRODUCTS\\LT1371 1824 1072 R0
SYMATTR InstName U1
SYMBOL IND 1872 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL RES 2176 896 R0
SYMATTR InstName R1
SYMATTR Value 53.6K
SYMBOL VOLTAGE 1472 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL RES 2176 1072 R0
SYMATTR InstName R2
SYMATTR Value 6.19K
FLAG 2432 880 OUT
FLAG 2192 1184 0
FLAG 2320 992 0
FLAG 2432 992 0
FLAG 1424 1248 0
FLAG 1824 1232 0
FLAG 1472 992 0
FLAG 1584 1248 0
FLAG 1472 880 IN
TEXT 2032 1232 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\170b3c537b90_Cohn.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
C3 N003 OUT {C1}
L4 N002 N006 {2*L}
L2 N005 0 {Lm}
L6 N006 0 {Lm}
V1 N004 0 AC 2
C4 OUT 0 {C2}
R1 IN N004 {R}
C5 N002 0 {C3}
L5 N003 N006 {L}
L3 N002 N005 {2*L}
R2 OUT 0 {R}
L1 N001 N005 {L}
C2 IN 0 {C2}
C1 N001 IN {C1}
.ac oct 1000 10Meg 22Meg
.param x=.54 ; trimer postion
.param R=50
.param L=2.95u Lm=.27u C1=22p+x*25p C2=240p C3=34p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2316 1728
WIRE 1360 1168 1232 1168
WIRE 1664 1168 1536 1168
WIRE 1760 1168 1664 1168
WIRE 2080 1168 1952 1168
WIRE 1232 1184 1232 1168
WIRE 2080 1184 2080 1168
WIRE 1360 1200 1360 1168
WIRE 1536 1200 1536 1168
WIRE 1760 1200 1760 1168
WIRE 1952 1200 1952 1168
WIRE 1664 1280 1664 1168
WIRE 1072 1296 1024 1296
WIRE 1184 1296 1152 1296
WIRE 1232 1296 1232 1248
WIRE 1232 1296 1184 1296
WIRE 1360 1296 1360 1280
WIRE 1456 1296 1360 1296
WIRE 1536 1296 1536 1280
WIRE 1536 1296 1456 1296
WIRE 1760 1296 1760 1280
WIRE 1872 1296 1760 1296
WIRE 1952 1296 1952 1280
WIRE 1952 1296 1872 1296
WIRE 2080 1296 2080 1248
WIRE 2240 1296 2080 1296
WIRE 2240 1312 2240 1296
WIRE 1024 1328 1024 1296
WIRE 1232 1328 1232 1296
WIRE 1456 1328 1456 1296
WIRE 1872 1328 1872 1296
WIRE 2080 1328 2080 1296
WIRE 1024 1424 1024 1408
WIRE 1232 1424 1232 1392
WIRE 1456 1424 1456 1408
WIRE 1664 1424 1664 1344
WIRE 1872 1424 1872 1408
WIRE 2080 1424 2080 1392
WIRE 2240 1424 2240 1392
SYMBOL ind 1344 1184 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMBOL RES 1168 1280 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL ind 1440 1312 R0
SYMATTR InstName L2
SYMATTR Value {Lm}
SYMBOL cap 1648 1280 R0
SYMATTR InstName C5
SYMATTR Value {C3}
SYMBOL VOLTAGE 1024 1312 R0
WINDOW 3 25 97 Left 2
SYMATTR Value AC 2
SYMATTR InstName V1
SYMBOL cap 2064 1328 R0
SYMATTR InstName C4
SYMATTR Value {C2}
SYMBOL cap 1216 1328 R0
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL ind 1936 1184 R0
SYMATTR InstName L5
SYMATTR Value {L}
SYMBOL res 2224 1296 R0
SYMATTR InstName R2
SYMATTR Value {R}
SYMBOL ind 1856 1312 R0
SYMATTR InstName L6
SYMATTR Value {Lm}
SYMBOL cap 2064 1184 R0
SYMATTR InstName C3
SYMATTR Value {C1}
SYMBOL cap 1216 1184 R0
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL ind 1520 1184 R0
SYMATTR InstName L3
SYMATTR Value {2*L}
SYMBOL ind 1744 1184 R0
SYMATTR InstName L4
SYMATTR Value {2*L}
FLAG 2080 1424 0
FLAG 1872 1424 0
FLAG 1456 1424 0
FLAG 1232 1424 0
FLAG 1664 1424 0
FLAG 1024 1424 0
FLAG 2240 1424 0
FLAG 2240 1296 OUT
FLAG 1184 1296 IN
TEXT 1920 1480 Left 2 !.ac oct 1000 10Meg 22Meg
TEXT 1152 1472 Left 2 !.param x=.54 ; trimer postion\n.param R=50\n.param L=2.95u Lm=.27u C1=22p+x*25p C2=240p C3=34p
TEXT 1616 1584 Top 1 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\1a8a19a0847b_op_amp_intro.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
Vpn N003 0 -100V
V1 Vin 0 SINE(0 5 60)
R1 N002 Vin 1k
Vpp N001 0 100V
R2 Vo N002 5k
XU1 0 N002 N001 N003 Vo level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.tran 0 0.5 0 .01
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -48 -272 -48
WIRE 128 32 96 32
WIRE 432 32 208 32
WIRE 240 144 240 -48
WIRE -96 160 -128 160
WIRE -32 160 -96 160
WIRE 96 160 96 32
WIRE 96 160 48 160
WIRE 208 160 96 160
WIRE 432 176 432 32
WIRE 432 176 272 176
WIRE 480 176 432 176
WIRE 208 192 112 192
WIRE -272 240 -272 -48
WIRE -128 240 -128 160
WIRE 240 256 240 208
WIRE 112 272 112 192
WIRE -272 368 -272 320
WIRE -128 368 -128 320
WIRE 240 400 240 336
SYMBOL res 64 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 60)
SYMBOL voltage -272 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vpp
SYMATTR Value 100V
SYMBOL Opamps\\UniversalOpamp2 240 176 R0
SYMATTR InstName U1
SYMBOL voltage 240 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vpn
SYMATTR Value -100V
SYMBOL res 224 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 5k
FLAG -128 368 0
FLAG 112 272 0
FLAG 480 176 Vo
FLAG -96 160 Vin
FLAG -272 368 0
FLAG 240 400 0
TEXT -40 448 Left 2 !.tran 0 0.5 0 .01
* Z:\home\khalils\Downloads\files\data\raw_asc\db15bc703b02_PWM.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 LM393A ;pnba In+)In-)V+)V-)OUT
* LM393A VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17
* REV (N/A)
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OPEN COLLECTOR OUTPUT
* | | | | |
.SUBCKT LM393A 1 2 3 4 5
*
F1 9 3 V1 1
IEE 3 7 DC 100.0E-6
VI1 21 1 DC .75
VI2 22 2 DC .75
Q1 9 21 7 QIN
Q2 8 22 7 QIN
Q3 9 8 4 QMO
Q4 8 8 4 QMI
.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)
.MODEL QMI NPN(IS=800.0E-18 BF=1002)
.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)
E1 10 4 9 4 1
V1 10 11 DC 0
Q5 5 11 4 QOC
.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)
DP 4 3 DX
RP 3 4 46.3E3
.MODEL DX D(IS=800.0E-18)
*
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1792 680
SYMBOL OpAmps\\opamp2 -592 0 R0
SYMATTR InstName U1
SYMATTR Value LM393A
TEXT 784 -272 Left 2 !* LM393A VOLTAGE COMPARATOR "MACROMODEL" SUBCIRCUIT\n* CREATED USING PARTS VERSION 4.03 ON 03/07/90 AT 14:17\n* REV (N/A)\n* CONNECTIONS:   NON-INVERTING INPUT\n*                | INVERTING INPUT\n*                | | POSITIVE POWER SUPPLY\n*                | | | NEGATIVE POWER SUPPLY\n*                | | | | OPEN COLLECTOR OUTPUT\n*                | | | | |\n.SUBCKT LM393A   1 2 3 4 5\n*\n  F1    9  3 V1 1\n  IEE   3  7 DC 100.0E-6\n  VI1  21  1 DC .75\n  VI2  22  2 DC .75\n  Q1    9 21  7 QIN\n  Q2    8 22  7 QIN\n  Q3    9  8  4 QMO\n  Q4    8  8  4 QMI\n.MODEL QIN PNP(IS=800.0E-18 BF=2.000E3)\n.MODEL QMI NPN(IS=800.0E-18 BF=1002)\n.MODEL QMO NPN(IS=800.0E-18 BF=1000 CJC=1E-15 TR=807.4E-9)\n  E1   10  4  9  4  1\n  V1   10 11 DC 0\n  Q5    5 11  4 QOC\n.MODEL QOC NPN(IS=800.0E-18 BF=20.29E3 CJC=1E-15 TF=942.6E-12 TR=543.8E-9)\n  DP    4  3 DX\n  RP 3  4 46.3E3\n.MODEL DX  D(IS=800.0E-18)\n*\n.ENDS
* Z:\tmp\asc_dec_bjh7r6w2\1688e00a26ee_OQPSK_demod_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
A3 N004 0 N006 0 0 0 out 0 DFLOP
B2 N007 0 V=idt(V(Q_in), 0, V(sb))/{6*Ts}
A5 0 N008 0 N009 0 0 N005 0 AND
V5 N010 0 PULSE(0 1 {Tg+0.5/rc} {Ts/10} {Ts/10} {1/(rc)-Ts/10} {2/rc})
V2 sb 0 PULSE(0 1 {Tdx+1/rc+Ts/10} {Ts/10} {Ts/10} 0 {2/rc})
A6 0 N001 0 N003 0 0 N002 0 AND
B3 N001 0 V=(V(I_s)>={r})
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1944 996
WIRE 32 384 -48 384
WIRE 144 432 144 384
WIRE 144 560 144 512
WIRE 416 672 416 640
WIRE 496 384 144 384
WIRE 496 800 496 752
WIRE 496 912 496 880
WIRE 560 752 496 752
WIRE 736 64 672 64
WIRE 880 112 880 64
WIRE 880 240 880 192
WIRE 1072 784 1072 96
WIRE 1104 752 1104 464
WIRE 1136 64 880 64
WIRE 1136 96 1072 96
WIRE 1136 432 880 432
WIRE 1136 464 1104 464
WIRE 1136 752 1104 752
WIRE 1136 784 1072 784
WIRE 1248 64 1200 64
WIRE 1248 240 1248 64
WIRE 1248 432 1200 432
WIRE 1248 432 1248 272
WIRE 1264 768 1200 768
WIRE 1264 816 1264 768
WIRE 1264 928 1264 896
WIRE 1280 240 1248 240
WIRE 1280 272 1248 272
WIRE 1360 352 1360 288
WIRE 1360 480 1360 432
WIRE 1424 240 1344 240
WIRE 1424 288 1360 288
WIRE 1680 240 1584 240
SYMBOL Digital\\dflop 1504 192 R0
SYMATTR InstName A3
SYMBOL bv 144 416 R0
SYMATTR InstName B2
SYMATTR Value V=idt(V(Q_in), 0, V(sb))/{6*Ts}
SYMBOL Digital\\and 1168 384 R0
SYMATTR InstName A5
SYMBOL voltage 1264 800 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -343 114 Left 0
SYMATTR Value PULSE(0 1 {Tg+0.5/rc} {Ts/10} {Ts/10} {1/(rc)-Ts/10} {2/rc})
SYMATTR InstName V5
SYMBOL voltage 496 784 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -29 165 Left 0
SYMATTR Value PULSE(0 1 {Tdx+1/rc+Ts/10} {Ts/10} {Ts/10} 0 {2/rc})
SYMATTR InstName V2
SYMBOL Digital\\and 1168 16 R0
SYMATTR InstName A6
SYMBOL bv 880 96 R0
SYMATTR InstName B3
SYMATTR Value V=(V(I_s)>={r})
FLAG -48 384 Q_in
FLAG 144 560 0
FLAG 496 912 0
FLAG 560 752 sb
FLAG 880 240 0
FLAG 736 64 I_s
FLAG 416 672 0
FLAG 1264 928 0
FLAG 1680 240 out
FLAG 1360 480 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3484-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3484-1.asy)
C1 OUT 0 .01
L1 IN N003 10 Rpar=2K Rser=.1
V1 IN 0 5
D1 N001 OUT D
L2 0 N001 {10u*10.2*10.2} Rpar=1Meg
XU1 N002 IN IN N003 MP_01 IN 0 LT3484-1 ;pnba _Done)Charge)Vin)SW))Vbat)GND
R1 N002 IN 10K
K1 L1 L2 1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LT3484-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2772 1752
WIRE 1808 1264 1648 1264
WIRE 1936 1264 1808 1264
WIRE 2064 1264 1936 1264
WIRE 2224 1264 2112 1264
WIRE 2352 1264 2288 1264
WIRE 2352 1280 2352 1264
WIRE 1808 1296 1808 1264
WIRE 1936 1296 1936 1264
WIRE 2064 1296 2064 1264
WIRE 2112 1296 2112 1264
WIRE 1648 1360 1648 1264
WIRE 1664 1360 1648 1360
WIRE 1760 1360 1744 1360
WIRE 2352 1376 2352 1344
WIRE 2112 1392 2112 1376
WIRE 2064 1408 2064 1376
WIRE 2064 1408 1984 1408
WIRE 1648 1456 1648 1360
WIRE 1760 1456 1648 1456
WIRE 1648 1472 1648 1456
WIRE 1872 1536 1872 1520
WIRE 1648 1568 1648 1552
SYMBOL res 1760 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL VOLTAGE 1648 1456 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LT3484-1 1872 1408 R0
SYMATTR InstName U1
SYMBOL cap 2336 1280 R0
WINDOW 3 27 55 Left 2
SYMATTR Value .01
SYMATTR InstName C1
SYMBOL ind2 2048 1280 R0
WINDOW 0 -6 35 Right 2
WINDOW 3 -4 73 Right 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rpar=2K Rser=.1
SYMBOL diode 2224 1280 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL ind2 2128 1392 R180
WINDOW 0 -3 72 Right 2
WINDOW 3 0 43 Right 2
SYMATTR InstName L2
SYMATTR Value {10u*10.2*10.2}
SYMATTR SpiceLine Rpar=1Meg
FLAG 2352 1376 0
FLAG 1872 1536 0
FLAG 1648 1568 0
FLAG 2112 1392 0
FLAG 2352 1264 OUT
FLAG 1648 1264 IN
TEXT 2048 1480 Left 2 !.tran 5m startup
TEXT 2088 1264 Bottom 2 !K1 L1 L2 1