Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\21dd10917d69_PentoCarG1Step.asc
* Generated by LTspice 26.0.1 for Windows.
Vg2 N002 0 360
Vg1 N003 0 0
XU1 0 N003 N002 0 N001 EL34Pent Pentrode ;pnba Cathode)G1)G2)G3)Anode
Vp N001 0 0
.dc Vp 0 2K 100 Vg1 0 -40 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 96 -144 96
WIRE 48 112 48 96
WIRE -144 128 -144 96
WIRE 0 160 -16 160
WIRE 144 176 96 176
WIRE 0 192 -64 192
WIRE 144 192 144 176
WIRE -64 208 -64 192
WIRE -16 256 -16 160
WIRE 16 256 16 240
WIRE 16 256 -16 256
WIRE -16 272 -16 256
WIRE -144 304 -144 208
WIRE -64 304 -64 288
WIRE -64 304 -144 304
WIRE 16 304 16 256
WIRE 16 304 -64 304
WIRE 144 304 144 272
WIRE 144 304 16 304
WIRE 16 320 16 304
SYMBOL voltage 144 176 R0
WINDOW 0 -47 15 Left 0
WINDOW 3 -20 61 Left 0
SYMATTR InstName Vg2
SYMATTR Value 360
SYMBOL Valve\\Pentode 48 176 R0
WINDOW 0 -77 -52 Left 0
WINDOW 38 37 111 Center 0
SYMATTR InstName U1
SYMATTR SpiceModel EL34Pent
SYMBOL voltage -144 112 R0
WINDOW 0 -16 57 Left 0
SYMATTR InstName Vp
SYMATTR Value 0
SYMBOL voltage -64 192 R0
WINDOW 0 -18 61 Left 0
SYMATTR InstName Vg1
SYMATTR Value 0
FLAG -16 272 0
TEXT -152 320 Left 0 !.dc Vp 0 2K 100 Vg1 0 -40 5
* Z:\home\khalils\Downloads\files\data\raw_asc\2709c148c038_NAND3.asc
* Generated by LTspice 26.0.1 for Windows.
M4 Out In3 Vdd Vdd P_2u l=2u w=24u
M6 Out In1 Vdd Vdd P_2u l=2u w=24u
M5 Out In2 Vdd Vdd P_2u l=2u w=24u
M1 Out In1 n1 n1 N_2u l=2u w=18u
M2 n1 In2 n2 n2 N_2u l=2u w=18u
M3 n2 In3 Vss Vss N_2u l=2u w=18u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include "../MOSFET models/2um_CMOS.modlib"
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 872
WIRE -32 48 -256 48
WIRE 192 48 192 16
WIRE 192 48 -32 48
WIRE -256 64 -256 48
WIRE -240 64 -256 64
WIRE -32 64 -32 48
WIRE -16 64 -32 64
WIRE 192 64 192 48
WIRE 208 64 192 64
WIRE -304 80 -320 80
WIRE -80 80 -96 80
WIRE 144 80 128 80
WIRE -240 112 -240 64
WIRE -240 112 -256 112
WIRE -16 112 -16 64
WIRE -16 112 -32 112
WIRE 208 112 208 64
WIRE 208 112 192 112
WIRE -256 176 -256 160
WIRE -32 176 -32 160
WIRE -32 176 -256 176
WIRE 192 176 192 160
WIRE 192 176 -32 176
WIRE 368 176 192 176
WIRE 192 192 192 176
WIRE 208 240 192 240
WIRE 128 272 128 80
WIRE 128 272 -384 272
WIRE 144 272 128 272
WIRE 208 288 208 240
WIRE 208 288 192 288
WIRE 192 304 192 288
WIRE 272 304 192 304
WIRE 192 320 192 304
WIRE 208 368 192 368
WIRE -96 400 -96 80
WIRE -96 400 -384 400
WIRE 144 400 -96 400
WIRE 208 416 208 368
WIRE 208 416 192 416
WIRE 192 432 192 416
WIRE 272 432 192 432
WIRE 192 448 192 432
WIRE 208 496 192 496
WIRE -320 528 -320 80
WIRE -320 528 -384 528
WIRE 144 528 -320 528
WIRE 208 544 208 496
WIRE 208 544 192 544
WIRE 192 576 192 544
IOPIN 192 16 In
IOPIN 192 576 In
IOPIN -384 272 In
IOPIN -384 400 In
IOPIN 368 176 Out
IOPIN -384 528 In
SYMBOL nmos4 144 320 R0
WINDOW 0 78 81 Left 2
WINDOW 3 76 25 Left 2
WINDOW 123 78 53 Left 2
SYMATTR InstName M2
SYMATTR Value N_2u
SYMATTR Value2 l=2u w=18u
SYMBOL pmos4 -304 160 M180
WINDOW 0 75 15 Left 2
WINDOW 3 73 70 Left 2
WINDOW 123 75 43 Left 2
SYMATTR InstName M4
SYMATTR Value P_2u
SYMATTR Value2 l=2u w=24u
SYMBOL nmos4 144 192 R0
WINDOW 0 78 81 Left 2
WINDOW 3 76 25 Left 2
WINDOW 123 78 53 Left 2
SYMATTR InstName M1
SYMATTR Value N_2u
SYMATTR Value2 l=2u w=18u
SYMBOL pmos4 144 160 M180
WINDOW 0 75 15 Left 2
WINDOW 3 73 70 Left 2
WINDOW 123 75 43 Left 2
SYMATTR InstName M6
SYMATTR Value P_2u
SYMATTR Value2 l=2u w=24u
SYMBOL pmos4 -80 160 M180
WINDOW 0 75 15 Left 2
WINDOW 3 73 70 Left 2
WINDOW 123 75 43 Left 2
SYMATTR InstName M5
SYMATTR Value P_2u
SYMATTR Value2 l=2u w=24u
SYMBOL nmos4 144 448 R0
WINDOW 0 78 81 Left 2
WINDOW 3 76 25 Left 2
WINDOW 123 78 53 Left 2
SYMATTR InstName M3
SYMATTR Value N_2u
SYMATTR Value2 l=2u w=18u
FLAG 192 16 Vdd
FLAG 192 576 Vss
FLAG -384 272 In1
FLAG -384 400 In2
FLAG 368 176 Out
FLAG -384 528 In3
FLAG 272 304 n1
FLAG 272 432 n2
TEXT -312 672 Left 2 !.include "../MOSFET models/2um_CMOS.modlib"
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1964-SD.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1964-SD.asy)
V1 IN 0 PWL(0 0 1 -10)
C1 OUT 0 1
Rload OUT 0 1K
XU1 0 IN IN OUT OUT LT1964-SD ;pnba GND)IN)_SHDN)ADJ)OUT
.tran 1
.lib LT1964.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL PowerProducts\\LT1964-SD 176 96 R0
SYMATTR InstName U1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 -10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 384 240 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3548-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3548-1.asy)
XU1 1.8V IN IN N002 0 IN N001 MP_01 IN 1.575V LTC3548-1 ;pnba Vsense1)Run1)Vin)SW1)GND)Mode)SW2))Run2)Vsense2
V1 IN 0 5
L2 N001 1.575V 4.7
L1 N002 1.8V 2.2
C1 1.575V 0 4.7
Rload1 1.8V 0 4
Rload2 1.575V 0 10
C2 1.8V 0 10
.tran 200u startup
.lib LTC3548-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1076 708
WIRE 176 32 48 32
WIRE 272 32 176 32
WIRE 352 32 272 32
WIRE 432 32 352 32
WIRE 48 48 48 32
WIRE 272 64 272 32
WIRE 352 64 352 32
WIRE 432 64 432 32
WIRE 176 128 176 32
WIRE 208 128 176 128
WIRE 48 144 48 128
WIRE 208 224 128 224
WIRE 544 224 496 224
WIRE 128 240 128 224
WIRE 544 240 544 224
WIRE 128 336 128 320
WIRE 128 336 -16 336
WIRE 208 336 128 336
WIRE 544 336 544 320
WIRE 544 336 496 336
WIRE 656 336 544 336
WIRE -16 352 -16 336
WIRE 128 352 128 336
WIRE 544 352 544 336
WIRE 656 352 656 336
WIRE 352 400 352 384
WIRE -16 448 -16 432
WIRE 128 448 128 416
WIRE 544 448 544 416
WIRE 656 448 656 432
SYMBOL ind 144 224 M0
WINDOW 0 5 28 Right 2
WINDOW 3 7 83 Right 2
SYMATTR InstName L2
SYMATTR Value 4.7
SYMBOL res 640 336 R0
SYMATTR InstName Rload1
SYMATTR Value 4
SYMBOL PowerProducts\\LTC3548-1 352 224 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 48 32 R0
WINDOW 3 25 98 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL ind 528 224 R0
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL polcap 528 352 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL res -32 336 R0
SYMATTR InstName Rload2
SYMATTR Value 10
SYMBOL polcap 112 352 R0
SYMATTR InstName C1
SYMATTR Value 4.7
FLAG 48 144 0
FLAG 352 400 0
FLAG 544 448 0
FLAG 656 448 0
FLAG 48 32 IN
FLAG 656 336 1.8V
FLAG 128 448 0
FLAG -16 448 0
FLAG -16 336 1.575V
TEXT 264 464 Left 2 !.tran 200u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2aee8309a19b_1-Bit_SRAM.asc
* Generated by LTspice 26.0.1 for Windows.
M2 N005 N001 N014 N015 NMOS
M7 N012 N005 0 N019 NMOS
M4 OUT NC_01 N011 N008 PMOS
M9 N012 N006 N006 N007 NMOS
V3 N017 0 PULSE(0 5 0 5n 5n 10m 20m)
VREAD N001 0 PULSE(0 5 0 5n 5n 40m 80m)
M1 OUT N013 N002 N003 PMOS
M3 N002 N005 N006 N004 PMOS
M6 0 N013 N011 N018 NMOS
M10 N017 N001 N013 N016 NMOS
M5 N011 OUT OUT N009 NMOS
M8 N006 N012 N012 N010 PMOS
V1 N002 0 5
V2 N014 0 PULSE(0 5 0 5n 5n 20m 40m)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 180m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1216 680
WIRE 256 -48 -144 -48
WIRE 704 -48 256 -48
WIRE 384 64 272 64
WIRE 512 64 384 64
WIRE 272 112 272 80
WIRE 512 112 512 80
WIRE 464 144 448 144
WIRE 272 160 96 160
WIRE 96 192 96 160
WIRE 512 224 512 160
WIRE 656 224 512 224
WIRE 96 240 96 192
WIRE 256 240 96 240
WIRE 96 272 96 240
WIRE 96 272 0 272
WIRE 208 272 96 272
WIRE 512 272 512 224
WIRE 512 272 400 272
WIRE 608 272 512 272
WIRE 256 288 256 240
WIRE 656 288 656 224
WIRE 608 320 608 288
WIRE 0 352 0 320
WIRE 208 352 208 320
WIRE 400 352 400 320
WIRE 96 368 0 368
WIRE 208 368 96 368
WIRE 496 368 400 368
WIRE 608 368 496 368
WIRE -144 416 -144 -48
WIRE 320 416 320 80
WIRE 688 416 320 416
WIRE 704 416 704 -48
WIRE 448 432 448 144
WIRE 448 432 160 432
WIRE 96 448 96 368
WIRE 272 448 96 448
WIRE 352 448 352 352
WIRE 496 448 496 368
WIRE 496 448 352 448
WIRE -160 464 -192 464
WIRE -80 464 -112 464
WIRE 160 464 160 432
WIRE 160 464 -64 464
WIRE 320 464 320 416
WIRE 688 464 688 416
WIRE 736 464 704 464
WIRE 848 464 784 464
WIRE 272 528 272 496
WIRE 448 528 448 432
WIRE 496 528 496 496
WIRE 384 544 272 544
WIRE 496 544 384 544
IOPIN 96 192 Out
SYMBOL voltage 256 -32 R180
WINDOW 0 24 96 Left 2
WINDOW 3 -10 186 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName READ
SYMATTR Value PULSE(0 5 0 5n 5n 40m 80m)
SYMBOL nmos4 320 544 R180
SYMATTR InstName M6
SYMBOL nmos4 448 448 R0
SYMATTR InstName M7
SYMBOL pmos4 320 160 R180
SYMATTR InstName M1
SYMBOL voltage 384 80 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -192 448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 5n 5n 20m 40m)
SYMBOL nmos4 -64 416 R90
SYMATTR InstName M2
SYMBOL pmos4 352 272 R0
SYMATTR InstName M8
SYMBOL nmos4 656 368 R180
SYMATTR InstName M9
SYMBOL nmos4 256 368 R180
SYMATTR InstName M5
SYMBOL nmos4 784 416 R90
SYMATTR InstName M10
SYMBOL voltage 848 448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 5n 5n 10m 20m)
SYMBOL pmos4 464 64 R0
SYMATTR InstName M3
SYMBOL pmos4 -48 272 R0
SYMATTR InstName M4
FLAG 384 -16 0
FLAG 384 544 0
FLAG 96 192 OUT
FLAG -192 544 0
FLAG 848 544 0
FLAG 256 -128 0
TEXT -224 568 Left 2 !.tran 180m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1169.asc
* Generated by LTspice 26.0.1 for Windows.
* Unity-Gain Buffer with Extended Load Capacitance Drive Capability
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1169.asy)
C1 N002 N001 .1
V3 IN 0 PULSE(0 1 0 1u 1u .5m 1m)
R2 OUT N002 33
Cload 0 OUT .1
V1 +V 0 15
R1 OUT N001 1K
V2 -V 0 -15
XU1 IN N001 +V -V N002 LT1169 ;pnba In+)In-)V+)V-)OUT
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 256 32 128 32
WIRE 400 32 336 32
WIRE -240 112 -240 96
WIRE -112 112 -112 96
WIRE 128 112 128 32
WIRE 176 112 128 112
WIRE 272 112 240 112
WIRE -240 208 -240 192
WIRE -112 208 -112 192
WIRE 192 208 192 192
WIRE 128 224 128 112
WIRE 160 224 128 224
WIRE 272 240 272 112
WIRE 272 240 224 240
WIRE 304 240 272 240
WIRE 400 240 400 32
WIRE 400 240 384 240
WIRE 448 240 400 240
WIRE 160 256 0 256
WIRE 448 256 448 240
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 448 336 448 320
WIRE 0 368 0 352
SYMBOL voltage -240 96 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 0 1u 1u .5m 1m)
SYMBOL cap 432 320 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName Cload
SYMATTR Value .1
SYMBOL opamps\\LT1169 192 176 R0
SYMATTR InstName U1
SYMBOL res 352 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -112 96 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL cap 240 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 400 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 33
FLAG -112 208 0
FLAG 192 192 +V
FLAG -112 96 +V
FLAG 192 288 -V
FLAG -240 208 0
FLAG -240 96 -V
FLAG 0 368 0
FLAG 448 336 0
FLAG 0 256 IN
FLAG 448 240 OUT
TEXT 392 392 Left 2 !.tran 3m
TEXT 40 -24 Bottom 2 ;Unity-Gain Buffer with Extended Load Capacitance Drive Capability
* Z:\home\khalils\Downloads\files\data\raw_asc\19aa72b9e44b_pwm-highpass.asc
* Generated by LTspice 26.0.1 for Windows.
C3 N005 N003 4800p
R2 N005 N004 301
R1 N003 N002 301
C1 N002 N001 100n
V1 N001 0 SINE(1 1 100 0 0 0 10)
C2 N004 0 100n
R3 N004 N002 1100
.tran 0 10mS 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 980 680
WIRE 400 240 176 240
WIRE 544 240 464 240
WIRE 704 240 544 240
WIRE 848 240 784 240
WIRE 912 240 848 240
WIRE 544 272 544 240
WIRE 848 288 848 240
WIRE 176 304 176 240
WIRE 400 384 320 384
WIRE 544 384 544 352
WIRE 544 384 464 384
WIRE 704 384 544 384
WIRE 848 384 848 352
WIRE 848 384 784 384
WIRE 912 384 848 384
WIRE 176 480 176 384
WIRE 320 480 320 384
WIRE 320 480 176 480
WIRE 176 496 176 480
SYMBOL res 800 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 301
SYMBOL cap 864 352 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value 4800p
SYMBOL cap 464 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL voltage 176 288 R0
SYMATTR InstName V1
SYMATTR Value SINE(1 1 100 0 0 0 10)
SYMBOL res 560 368 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 1100
SYMBOL cap 464 368 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL res 800 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 301
FLAG 176 496 0
TEXT 168 136 Left 2 !.tran 0 10mS 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1572.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1572.asy)
Rload OUT 0 25
L1 IN N001 150 Rser=0.02 Rpar=5000
XU1 N003 N004 0 N001 IN N001 OUT LT1572 ;pnba Vc)FB)GND)SW)Vin)Anode)Cathode
R3 N003 N002 1K
C1 OUT 0 100 Rser=0.05
C2 N002 0 1
R2 N004 0 1.24K
V1 IN 0 5
R1 OUT N004 10.7K
.tran 15m startup
.lib LT1572.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2608 1416
WIRE 1712 880 1552 880
WIRE 1728 880 1712 880
WIRE 1824 880 1808 880
WIRE 1936 880 1824 880
WIRE 1552 896 1552 880
WIRE 1712 944 1712 880
WIRE 1824 944 1824 880
WIRE 1936 944 1936 880
WIRE 1552 992 1552 976
WIRE 2048 1024 2000 1024
WIRE 2176 1024 2048 1024
WIRE 2288 1024 2176 1024
WIRE 2048 1040 2048 1024
WIRE 2176 1040 2176 1024
WIRE 2288 1040 2288 1024
WIRE 1552 1088 1520 1088
WIRE 1648 1088 1632 1088
WIRE 1520 1104 1520 1088
WIRE 2176 1136 2176 1104
WIRE 2288 1136 2288 1120
WIRE 2048 1152 2048 1120
WIRE 2048 1152 2000 1152
WIRE 2048 1168 2048 1152
WIRE 1520 1184 1520 1168
WIRE 2048 1264 2048 1248
WIRE 1824 1280 1824 1232
SYMBOL POWERPRODUCTS\\LT1572 1824 1088 R0
WINDOW 3 8 168 Left 2
SYMATTR InstName U1
SYMBOL RES 1648 1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL VOLTAGE 1552 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL RES 2032 1152 R0
SYMATTR InstName R2
SYMATTR Value 1.24K
SYMBOL RES 2272 1024 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL CAP 1504 1104 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL polcap 2160 1040 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.05
SYMBOL RES 2032 1024 R0
SYMATTR InstName R1
SYMATTR Value 10.7K
SYMBOL IND 1712 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 2288 1024 OUT
FLAG 2048 1264 0
FLAG 2176 1136 0
FLAG 2288 1136 0
FLAG 1520 1184 0
FLAG 1824 1280 0
FLAG 1552 992 0
FLAG 1552 880 IN
TEXT 2192 1208 Left 2 !.tran 15m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7158-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7158-2.8.asy)
C4 N002 0 1
Rload OUT 0 2.8
V1 IN 0 3.5
C2 N003 0 1
R1 IN N001 100K
XU1 OUT MP_01 OUT N002 N001 N003 N003 N004 IN 0 ADP7158_9 Vreg=3.211 Vref=2.816 ;pnba Vout))Vout_Sense)Byp)EN)Ref_Sense)Ref)Vreg)Vin)GND
C1 OUT 0 10
C3 N004 0 1
.tran 5m startup
.lib ADP7158_9.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -160 32
WIRE 80 32 -32 32
WIRE 416 32 400 32
WIRE 464 32 416 32
WIRE 560 32 464 32
WIRE -160 48 -160 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE 416 128 416 32
WIRE 416 128 400 128
WIRE -160 144 -160 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 0 224 -16 224
WIRE 80 224 64 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap 448 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 448 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 544 32 R0
SYMATTR InstName Rload
SYMATTR Value 2.8
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL ADP7158-2.8 240 176 R0
SYMATTR InstName U1
SYMBOL voltage -160 32 R0
SYMATTR InstName V1
SYMATTR Value 3.5
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG -16 224 0
FLAG -160 144 0
FLAG 560 144 0
FLAG -160 32 IN
FLAG 560 32 OUT
TEXT 504 368 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2660db64d82c_ADA4177.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4177.asy)
R2 OUT N001 10K
XU1 IN N001 +V -V OUT ADA4177 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10K
Vin IN 0 SINE(0 1 10K)
V1 +V 0 15
V2 -V 0 -15
.tran 1m
.lib ADA4177.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 512 -1232 496 -1232
WIRE 544 -1232 512 -1232
WIRE 656 -1232 624 -1232
WIRE 128 -1136 128 -1152
WIRE 240 -1136 240 -1152
WIRE 512 -1120 512 -1232
WIRE 544 -1120 512 -1120
WIRE 656 -1104 656 -1232
WIRE 656 -1104 608 -1104
WIRE 720 -1104 656 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 128 -1040 128 -1056
WIRE 240 -1040 240 -1056
WIRE 432 -976 432 -992
SYMBOL OpAmps\\ADA4177 576 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 240 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 128 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 128 -1152 +V
FLAG 128 -1040 0
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 240 -1152 -V
FLAG 576 -1072 -V
FLAG 400 -1232 0
FLAG 240 -1040 0
TEXT 704 -992 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\5b5b5f866690_Current-mirrors.asc
* Generated by LTspice 26.0.1 for Windows.
* Sizing:\n \n1) Set reference current -> 1 mA\n2) Iref = (Vcc-Vbe)/R1 -> R1 = (Vcc-Vbe)/R1 = (12-0.6)/1m =11.4k\n \nOutput resistance Rout = ?
* The following relation holds: Io/Iref = R3/R4\n \nSizing:\n1) Set Iref = I(R2) = 1mA\n2) Set V(R3) = 1 V -> R3 = 1k ohm\n3) If we want Io = 2 Iref -> R3/R4 = 2 -> R4 = 500 ohm\n4) R is given by R = (Vcc - Vbe - V(R3))/Iref = (12-0.6-1)/1m = 10.4 k ohm
* Io
* Iref
* Current mirrors
* DC sweep analysis
Q2 N001 N001 0 0 2N3904
R1 Vcc N001 11.4k
Q4 N002 N002 N003 0 2N3904
Q1 VL N001 0 0 2N3904
R4 N004 0 500
R3 N003 0 1k
R2 Vcc N002 10.4k
V1 Vcc 0 12
V2 VL 0 1
Q3 VL N002 N004 0 2N3904
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V2 0 10 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1348 1060
WIRE -144 -128 -144 -144
WIRE -32 -128 -32 -144
WIRE -144 -16 -144 -48
WIRE -32 -16 -32 -48
WIRE 112 160 112 128
WIRE 112 256 112 240
WIRE 192 256 112 256
WIRE 112 288 112 256
WIRE 304 288 304 128
WIRE 192 336 192 256
WIRE 192 336 176 336
WIRE 240 336 192 336
WIRE 112 416 112 384
WIRE 304 416 304 384
WIRE 112 624 112 592
WIRE 112 720 112 704
WIRE 192 720 112 720
WIRE 112 752 112 720
WIRE 304 752 304 592
WIRE 192 800 192 720
WIRE 192 800 176 800
WIRE 240 800 192 800
WIRE 112 896 112 848
WIRE 304 896 304 848
WIRE 112 1008 112 976
WIRE 304 1008 304 976
RECTANGLE Normal 1248 464 0 48 2
RECTANGLE Normal 1248 1056 0 464 2
SYMBOL res 96 880 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL npn 176 752 M0
SYMATTR InstName Q4
SYMATTR Value 2N3904
SYMBOL npn 240 288 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 96 144 R0
SYMATTR InstName R1
SYMATTR Value 11.4k
SYMBOL npn 240 752 R0
SYMATTR InstName Q3
SYMATTR Value 2N3904
SYMBOL npn 176 288 M0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL voltage -32 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL res 96 608 R0
SYMATTR InstName R2
SYMATTR Value 10.4k
SYMBOL voltage -144 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 288 880 R0
SYMATTR InstName R4
SYMATTR Value 500
FLAG 112 416 0
FLAG 304 416 0
FLAG -144 -16 0
FLAG -32 -16 0
FLAG 304 1008 0
FLAG 112 1008 0
FLAG -32 -144 VL
FLAG 304 128 VL
FLAG 304 592 VL
FLAG 112 592 Vcc
FLAG 112 128 Vcc
FLAG -144 -144 Vcc
TEXT 96 8 Left 2 !.dc V2 0 10 0.1
TEXT 472 88 Left 2 ;Sizing:\n \n1) Set reference current -> 1 mA\n2) Iref = (Vcc-Vbe)/R1 -> R1 = (Vcc-Vbe)/R1 = (12-0.6)/1m =11.4k\n \nOutput resistance Rout = ?
TEXT 464 584 Left 2 ;The following relation holds: Io/Iref = R3/R4\n \nSizing:\n1) Set Iref = I(R2) = 1mA\n2) Set V(R3) = 1 V -> R3 = 1k ohm\n3) If we want Io = 2 Iref -> R3/R4 = 2 -> R4 = 500 ohm\n4) R is given by R = (Vcc - Vbe - V(R3))/Iref = (12-0.6-1)/1m = 10.4 k ohm
TEXT 320 696 Left 2 ;Io
TEXT 48 656 Left 2 ;Iref
TEXT 448 -120 Left 4 ;Current mirrors
TEXT 104 -24 Left 2 ;DC sweep analysis