Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4637.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4637.asy)
V2 -V 0 -15
R2 OUT N001 10K
Rload OUT 0 10K
Vin IN 0 SINE(0 1 1K)
XU1 IN N001 +V -V OUT ADA4637 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
R1 N001 0 10K
.tran 10m
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL ADA4637 576 -1168 R0
SYMATTR InstName U1
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
TEXT 688 -960 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\32f049f043ad_Nested.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 0 {L}
C1 N001 0 {C}
I1 0 N001 AC 1
R1 N001 0 10K
.step param L 90u 200u .5u
.step param C 40p 60p 10p
.ac list 2Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 320 80 272
WIRE 80 208 80 144
WIRE 80 144 224 144
WIRE 224 144 224 192
WIRE 224 272 224 320
WIRE -32 320 -32 272
WIRE -32 192 -32 144
WIRE -32 144 80 144
WIRE 224 144 336 144
WIRE 336 144 336 192
WIRE 336 272 336 320
FLAG 224 320 0
FLAG 80 320 0
FLAG -32 320 0
FLAG 336 320 0
SYMBOL ind 208 176 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMBOL cap 64 208 R0
SYMATTR InstName C1
SYMATTR Value {C}
SYMBOL current -32 272 M180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName I1
SYMATTR Value AC 1
SYMBOL res 320 176 R0
SYMATTR InstName R1
SYMATTR Value 10K
TEXT 16 376 Left 0 !.step param L 90u 200u .5u\n.step param C 40p 60p 10p
TEXT 16 448 Left 0 !.ac list 2Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1581-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Vout
* +
* -
* Remote Load Sensing
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1581-2.5.asy)
Rpar2 N006 0 10m
Rpar1 N003 N002 10m
C1 N003 N006 22
XU1 N005 N006 N003 N002 N001 N004 LT1581-2.5 ;pnba ADJ)GND)SENSE)OUTPUT)POWER)CONTROL
V1 N004 0 12
C2 N005 N006 20
Iload N003 N006 PULSE(400m 7 150u 100n 100n 200u 600u)
V2 N001 0 5
.tran 500u
.lib LT1584.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1492 680
WIRE 16 -96 -192 -96
WIRE -192 -80 -192 -96
WIRE 16 -48 16 -96
WIRE -192 16 -192 0
WIRE 272 16 256 16
WIRE 368 16 352 16
WIRE -96 96 -192 96
WIRE -192 112 -192 96
WIRE 368 176 368 16
WIRE 368 176 256 176
WIRE 560 176 368 176
WIRE -192 208 -192 192
WIRE 368 208 368 176
WIRE 560 208 560 176
WIRE 144 256 144 240
WIRE 16 336 16 240
WIRE 144 336 144 320
WIRE 144 336 16 336
WIRE 368 336 368 272
WIRE 368 336 144 336
WIRE 560 336 560 288
WIRE 560 336 368 336
WIRE 368 352 368 336
WIRE 368 448 368 432
SYMBOL current 560 208 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 108 Left 2
SYMATTR InstName Iload
SYMATTR Value PULSE(400m 7 150u 100n 100n 200u 600u)
SYMBOL cap 128 256 R0
SYMATTR InstName C2
SYMATTR Value 20
SYMBOL PowerProducts\\LT1581-2.5 80 96 R0
SYMATTR InstName U1
SYMBOL res 352 336 R0
SYMATTR InstName Rpar2
SYMATTR Value 10m
SYMBOL voltage -192 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL cap 352 208 R0
WINDOW 39 24 84 Left 2
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 368 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rpar1
SYMATTR Value 10m
SYMBOL voltage -192 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
FLAG -192 208 0
FLAG -192 16 0
FLAG 368 448 0
TEXT 616 400 Left 2 !.tran 500u
TEXT 464 248 Left 2 ;Vout
TEXT 480 200 Left 2 ;+
TEXT 488 296 Left 2 ;-
TEXT 88 -120 Bottom 2 ;Remote Load Sensing
* Z:\home\khalils\Downloads\files\data\raw_asc\4390d8985897_current_driven_antenna_with_esd.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 0 1 Rser=1
V1 NC_01 NC_02 SINE(0 5 8000)
D3 0 N001 D
D4 N001 0 D
I1 N001 0 SINE(0 .02 8k)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran .001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 416 80 144 80
WIRE 752 80 416 80
WIRE 144 112 144 80
WIRE 704 176 672 176
WIRE 720 176 704 176
WIRE 752 176 752 80
WIRE 752 176 736 176
WIRE 768 176 752 176
WIRE 416 192 416 80
WIRE 736 240 736 176
WIRE 736 240 704 240
WIRE 416 288 416 272
WIRE 496 288 496 240
WIRE 496 288 416 288
WIRE 672 288 672 176
WIRE 672 288 496 288
WIRE 768 288 768 240
WIRE 768 288 672 288
WIRE 144 304 144 192
WIRE 416 304 416 288
WIRE 416 304 144 304
FLAG 416 304 0
SYMBOL ind 400 176 R0
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=1
SYMBOL voltage 208 320 R0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 8000)
SYMBOL diode 688 176 R0
SYMATTR InstName D3
SYMBOL diode 752 176 R0
SYMATTR InstName D4
SYMBOL current 144 112 R0
SYMATTR InstName I1
SYMATTR Value SINE(0 .02 8k)
TEXT 568 256 Left 2 !.tran .001
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-4.5.asy)
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-4.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
V1 IN 0 3.3
L1 N001 N002 1.5 Rser=80m
Rload OUT 0 50
C1 OUT 0 10
.tran 400u startup
.lib ADP2504-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL ADP2504-4.5 176 176 R0
SYMATTR InstName U1
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG 480 224 OUT
FLAG -64 64 IN
TEXT 432 376 Left 2 !.tran 400u startup
TEXT 160 -8 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
T1 IN 0 0 OUT Td=50n Z0=50
T2 0 0 OUT 0 Td=30n Z0=150
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\c08a83427e01_Assignment_3a__ii_.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Half Wave Rectifier Circuit (Ideal)
V1 N001 0 SINE(0 311 50) Rser=0.001
R1 N002 0 1000
D1 N001 N002 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 64 80 64
WIRE 352 64 256 64
WIRE 80 112 80 64
WIRE 352 112 352 64
WIRE 80 240 80 192
WIRE 176 240 80 240
WIRE 352 240 352 192
WIRE 352 240 176 240
WIRE 176 272 176 240
SYMBOL diode 192 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
FLAG 176 272 0
TEXT 16 272 Left 2 !.tran 0.05
TEXT 240 8 Center 2 ;Positive Half Wave Rectifier Circuit (Ideal)
* Z:\home\khalils\Downloads\files\data\raw_asc\455c5c727fda_Lab04Pt2.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout N002 X 0 NMOS l=0.1u w=6u
M2 X N003 Y 0 NMOS l=0.1u w=6u
M3 N001 N002 Vout N001 PMOS l=0.1u w=2.65u
M4 N001 N003 Vout N001 PMOS l=0.1u w=2.65u
M5 N001 N004 Vout N001 PMOS l=0.1u w=2.65u
M6 Y N004 0 0 NMOS l=0.1u w=6u
V1 N001 0 2.5
VC N004 0 2.5
VA N002 0 2.5
VB N003 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model nmos nmos level=1 vto=0.4 kp=432u phi=0.88 gamma=0.2 lambda=0
.model pmos pmos level=1 vto=-0.4 kp=108u phi=0.88 gamma=0.2 lambda=0
.dc V1 0 2.5 0.001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 -80 -112 -80
WIRE 48 -80 -48 -80
WIRE 112 -80 48 -80
WIRE 208 -80 112 -80
WIRE 288 -80 208 -80
WIRE 336 -80 288 -80
WIRE -48 -32 -48 -80
WIRE -48 -32 -112 -32
WIRE 112 -32 112 -80
WIRE 112 -32 48 -32
WIRE 288 -32 288 -80
WIRE 288 -32 208 -32
WIRE -160 0 -176 0
WIRE 0 0 -48 0
WIRE 160 0 144 0
WIRE 48 16 -112 16
WIRE 208 16 48 16
WIRE 144 32 144 0
WIRE 144 32 -64 32
WIRE 208 32 208 16
WIRE 240 32 208 32
WIRE -176 48 -176 0
WIRE -32 48 -176 48
WIRE 48 48 48 16
WIRE 144 96 48 96
WIRE 336 96 336 -80
WIRE -32 128 -32 48
WIRE 0 128 -32 128
WIRE 48 160 48 144
WIRE 80 160 48 160
WIRE -48 176 -48 0
WIRE -48 176 -176 176
WIRE -32 176 -48 176
WIRE 48 176 48 160
WIRE 144 224 144 96
WIRE 144 224 48 224
WIRE -32 256 -32 176
WIRE 0 256 -32 256
WIRE 48 288 48 272
WIRE 80 288 48 288
WIRE -64 304 -64 32
WIRE -64 304 -176 304
WIRE -32 304 -64 304
WIRE 48 304 48 288
WIRE 144 352 144 224
WIRE 144 352 48 352
WIRE -32 384 -32 304
WIRE 0 384 -32 384
WIRE 144 400 144 352
WIRE 336 400 336 176
WIRE 336 400 144 400
WIRE 48 416 48 400
WIRE 144 416 144 400
WIRE 144 416 48 416
WIRE 48 432 48 416
FLAG 48 432 0
FLAG -176 384 0
FLAG 80 160 X
IOPIN 80 160 Out
FLAG 80 288 Y
IOPIN 80 288 Out
FLAG 240 32 Vout
IOPIN 240 32 Out
FLAG -176 128 0
FLAG -176 256 0
SYMBOL nmos4 0 48 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.1u w=6u
SYMBOL nmos4 0 176 R0
SYMATTR InstName M2
SYMATTR Value2 l=0.1u w=6u
SYMBOL pmos4 -160 -80 R0
SYMATTR InstName M3
SYMATTR Value2 l=0.1u w=2.65u
SYMBOL pmos4 0 -80 R0
SYMATTR InstName M4
SYMATTR Value2 l=0.1u w=2.65u
SYMBOL pmos4 160 -80 R0
SYMATTR InstName M5
SYMATTR Value2 l=0.1u w=2.65u
SYMBOL nmos4 0 304 R0
SYMATTR InstName M6
SYMATTR Value2 l=0.1u w=6u
SYMBOL voltage 336 80 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage -176 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VC
SYMATTR Value 2.5
SYMBOL voltage -176 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VA
SYMATTR Value 2.5
SYMBOL voltage -176 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VB
SYMATTR Value 0
TEXT -368 488 Left 2 !.model nmos nmos level=1 vto=0.4 kp=432u phi=0.88 gamma=0.2 lambda=0
TEXT -368 512 Left 2 !.model pmos pmos level=1 vto=-0.4 kp=108u phi=0.88 gamma=0.2 lambda=0
TEXT -368 536 Left 2 !.dc V1 0 2.5 0.001
* Z:\tmp\asc_dec_bjh7r6w2\04ef7db4b713_lm741_noninverting_amplifier_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R3 N001 0 10k
R4 0 N003 {R_shunt}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 988 680
WIRE 272 0 208 0
WIRE 112 128 112 0
WIRE 112 128 80 128
WIRE 128 128 112 128
WIRE 272 144 272 0
WIRE 272 144 192 144
WIRE 416 144 272 144
WIRE 128 160 96 160
WIRE 416 256 416 224
WIRE 96 288 96 160
WIRE 96 288 80 288
WIRE 112 288 96 288
WIRE 224 288 192 288
SYMBOL res 400 128 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 208 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {R_shunt}
FLAG 160 112 12V
FLAG 160 176 0
FLAG 416 256 0
FLAG 224 288 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1763-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1763-5.asy)
C1 OUT 0 10
Rload OUT 0 500
C2 OUT N001 .01
V1 IN 0 PWL(0 0 1 10)
XU1 OUT OUT 0 N001 IN MP_01 MP_02 IN LT1763-5 ;pnba OUT)Sense)GND)BYP)_SHDN)))IN
.tran 1
.lib LT1763.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 32 304 32
WIRE 352 32 320 32
WIRE 432 32 352 32
WIRE 528 32 432 32
WIRE 0 48 -208 48
WIRE 16 48 0 48
WIRE 432 48 432 32
WIRE 528 48 528 32
WIRE -208 64 -208 48
WIRE 352 64 352 32
WIRE 320 96 320 32
WIRE 320 96 304 96
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 432 144 432 112
WIRE 528 144 528 128
WIRE -208 160 -208 144
WIRE 352 160 352 128
WIRE 352 160 304 160
WIRE 160 240 160 208
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 416 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL cap 336 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL PowerProducts\\LT1763-5 160 96 R0
SYMATTR InstName U1
FLAG -208 160 0
FLAG 432 144 0
FLAG 528 144 0
FLAG 160 240 0
FLAG 528 32 OUT
FLAG -208 48 IN
TEXT 408 208 Left 2 !.tran 1
* Z:\tmp\asc_dec_bjh7r6w2\0c10b18b77d7_doble-par_allB_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 0 10k
V4 N003 0 SINE(0 10m 1k) AC 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 940 680
WIRE 224 -80 80 -80
WIRE 176 -48 80 -48
WIRE 176 0 176 -48
WIRE 224 96 224 -80
WIRE 368 96 224 96
WIRE 176 112 176 80
WIRE 80 128 80 16
WIRE 368 128 368 96
WIRE -112 192 -112 16
WIRE -48 192 -112 192
WIRE -48 208 -48 192
WIRE 368 256 368 208
WIRE -48 320 -48 288
SYMBOL res 352 112 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL rui\\shortcuts\\voltage -48 192 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value SINE(0 10m 1k)
SYMATTR Value2 AC 1
FLAG -48 320 0
FLAG 368 256 0
FLAG 176 112 0
FLAG 80 128 0
FLAG -16 48 -50
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6658-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6658-3.asy)
C2 OUT2 0 1
C3 OUT1 0 1
V3 IN 0 PWL(0 0 100u 0 +2u 5.5)
C1 N001 0 1
XU1 IN IN IN IN N001 OUT1 OUT1 OUT2 OUT2 0 N002 LT6658-3 ;pnba Vin)Vin1)Vin2)_OD)Bypass)Vout1_F)Vout1_S)Vout2_F)Vout2_S)Gnd)NR
.tran 500u
.lib LT6658.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1448 1048
WIRE 16 -16 -336 -16
WIRE 128 -16 16 -16
WIRE 224 -16 128 -16
WIRE 320 -16 224 -16
WIRE -336 0 -336 -16
WIRE 128 0 128 -16
WIRE 224 0 224 -16
WIRE 320 0 320 -16
WIRE 432 64 416 64
WIRE 512 64 432 64
WIRE 512 80 512 64
WIRE -336 96 -336 80
WIRE 432 144 432 64
WIRE 432 144 416 144
WIRE 512 160 512 144
WIRE 16 192 16 -16
WIRE 48 192 16 192
WIRE 432 224 416 224
WIRE 496 224 432 224
WIRE 496 240 496 224
WIRE 432 304 432 224
WIRE 432 304 416 304
WIRE 496 320 496 304
WIRE 128 400 128 384
WIRE 224 400 224 384
WIRE 320 400 320 384
WIRE 224 480 224 464
SYMBOL cap 208 400 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -336 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 0 100u 0 +2u 5.5)
SYMBOL cap 480 240 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 496 80 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL LT6658-3 224 192 R0
SYMATTR InstName U1
FLAG 128 400 0
FLAG 224 480 0
FLAG -336 96 0
FLAG 512 160 0
FLAG 496 320 0
FLAG 496 224 OUT1
FLAG 512 64 OUT2
FLAG -336 -16 IN
TEXT 464 464 Left 2 !.tran 500u
* Z:\home\khalils\Downloads\files\data\raw_asc\24b805479d29_Bridge_Rectifier_Circuit.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N001 N002 D
D2 N003 N002 D
V1 N001 N003 SINE(0 24 60 0)
D4 0 N001 D
D3 0 N003 D
R1 N002 0 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 0 64 0
WIRE 320 0 256 0
WIRE 448 0 384 0
WIRE 608 0 448 0
WIRE 256 64 256 0
WIRE 448 64 448 0
WIRE 64 80 64 0
WIRE 608 144 608 0
WIRE 256 192 256 128
WIRE 256 192 192 192
WIRE 320 192 256 192
WIRE 448 192 448 128
WIRE 448 192 384 192
WIRE 192 240 192 192
WIRE 64 288 64 160
WIRE 448 288 448 192
WIRE 448 288 64 288
SYMBOL diode 464 128 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL res 592 128 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL diode 320 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL diode 320 208 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D3
SYMBOL diode 272 128 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMBOL voltage 64 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 24 60 0)
FLAG 192 240 0
FLAG 608 224 0
TEXT 24 296 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6559.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6559.asy)
V2 -V 0 -5
R2 OUT N001 301
R1 OUT 0 150
V1 +V 0 5
V3 IN 0 PULSE(-1 1 0 .1n .1n 10u 20u)
R3 N001 0 182
XU1 IN N001 +V -V OUT -V LT6559 ;pnba In+)In-)V+)V-)OUT)SHDN
.tran 100u
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -80 240 -80 224
WIRE 16 240 16 224
WIRE 336 256 224 256
WIRE 448 256 416 256
WIRE -80 336 -80 320
WIRE 16 336 16 320
WIRE 128 384 112 384
WIRE 224 384 224 256
WIRE 224 384 208 384
WIRE 256 384 224 384
WIRE 448 416 448 256
WIRE 448 416 400 416
WIRE 528 416 448 416
WIRE 528 432 528 416
WIRE 256 448 -128 448
WIRE -128 464 -128 448
WIRE 288 512 288 496
WIRE 336 512 336 496
WIRE 336 512 288 512
WIRE 288 528 288 512
WIRE 528 528 528 512
WIRE -128 560 -128 544
SYMBOL res 512 416 R0
SYMATTR InstName R1
SYMATTR Value 150
SYMBOL voltage -128 448 R0
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 .1n .1n 10u 20u)
SYMBOL voltage -80 224 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 16 224 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 432 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 301
SYMBOL res 224 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 182
SYMBOL LT6559 288 416 R0
SYMATTR InstName U1
FLAG -80 336 0
FLAG -80 224 +V
FLAG 16 336 0
FLAG -128 560 0
FLAG 528 416 OUT
FLAG 528 528 0
FLAG 112 384 0
FLAG -128 448 IN
FLAG 288 336 +V
FLAG 16 224 -V
FLAG 288 528 -V
TEXT 488 592 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX4434.asc
* Generated by LTspice 26.0.1 for Windows.
Vee 0 Vee 2.5
Vcc Vcc 0 2.5
RL OUT 0 10k
V1 IN 0 SINE(0 50m 100k)
CL OUT 0 15p
XU1 IN OUT Vcc Vee OUT MAX4434 ;pnba In+)In-)V+)V-)OUT
.tran 10u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX4434.asy)
.lib MAX4434.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 144 288 144 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 144 400 144 368
WIRE 144 400 112 400
WIRE 400 400 304 400
WIRE 112 416 112 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 144 448 144 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 144 544 144 528
WIRE 304 592 304 576
FLAG 720 384 OUT
FLAG 144 272 Vcc
FLAG 144 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 112 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
SYMBOL voltage 144 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL voltage 144 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 100k)
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL MAX4434 432 320 R0
SYMATTR InstName U1
TEXT 96 632 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\42fb0c58451f_lab2_task2.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 N002 0 0 2SC4081UB
VEK N001 0 5
VEB N002 0 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc EK 0 5 0.001 EB 0.7 0.78 0.02
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 192 272 192
WIRE 192 256 192 192
WIRE -32 304 -48 304
WIRE 128 304 48 304
WIRE 192 432 192 352
FLAG 304 192 0
FLAG -48 304 0
FLAG 192 432 0
SYMBOL npn 128 256 R0
SYMATTR InstName Q1
SYMATTR Value 2SC4081UB
SYMBOL voltage 176 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName EK
SYMATTR Value 5
SYMBOL voltage 64 304 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName EB
SYMATTR Value 0
TEXT -136 456 Left 2 !.dc EK 0 5 0.001 EB 0.7 0.78 0.02