* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3888.asc
* Generated by LTspice 26.0.1 for Windows.
* *************** READ ME **********************************************************************\n \nThis model does not cover the PMBUS and SPI functions of this IC.\nTherefore, many things controlled by the PMBUS are configured by CTRL + right click on the IC.\nShare_CLK is NOT modelled. The SYNC pin can only be used as an input and\nit is grounded when it is not used. CLK_OUT pin is provided to allow clock out function.\nResistor setting pins like Vout_CFG are not modeled.\nVout and PWM_config must be set by CTRL by right-clicking on the IC.\n \nFrequency_Switch sets the frequency in kHz between 250 and 1000.\nPWM_config controls the phasing and master/slave configuration of the 8 channels.\nA decimal number is used for the 3-bit binary number. The description starts on page 72 of the datasheet.\n \n# (PWM0: PWM1)\n7 (7 phase: 1 Phase)\n6 (6 phase: 2 Phase)\n5 (6 phase: 1 phase)\n4 (5 phase: 3 phase)\n3 (4 phase: 4 phase)\n2 (4 phase: 3 phase)\n1 (4 phase: 2 phase)\n0 (3 phase: 3 phase)\n \nVout0 and Vout1 program the output voltage in a range from 0.3 to 3.45V\nVout_trans_rate0 and Vout_trans_rate1 program the rate of movement of VOUT as the part is starting or margining (V/ms).\nGM0 and GM1 program the gain the Error Amplifier in range from 1 to 5.73mS\nIout_Cal_Gain should match the voltage gain of the chosen current sense (V/A)\nRith0 and Rith1 program the compensation resistor in series \n with Cithr on the output of the error amplifier in a range from 1k to 62k ohm\nTon_Min=45n programs the minimum on time of the PWM outputs\n \nOC_Limit0 and OC_Limit1 program the peak current limit of the each phase used for that converter. \n \nTon_Delay0 and Ton_Delay1 set the delay from when the RUN pin goes high until the soft-start begins\nToff_Delay0 and Toff_Delay1 set the delay from when the RUN pin goes low until the turn-off ramp begins\n \nVOUT_UV_Fault_Limit0 and VOUT_UV_Fault_Limit1 program the undervoltage fault limit for the Pgood output\nVOUT_OV_Fault_Limit0 and VOUT_OV_Fault_Limit1 program the overvoltage fault limit for the Pgood output\n \nSlave0 and Slave1 set slave channel. 0 disable,1 enable. If enabled the error amplifier is open circuit
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3888.asy)
* Library below included based on ModelFile attribute of instance XU5, XU2, XU3, XU4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC7050.asy)
L1 N008 OUT0 0.2 Rser=20m
C2 OUT0 0 220 m=7 Rser=2.5m
XU5 N001 N031 N001 0 N032 N034 N036 N001 N001 IN N028 0 N024 N004 N004 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
R8 N023 N003 500
XU1 N012 N015 N006 N007 N020 0 OUT0 N017 N021 N026 N013 N014 N027 0 N022 N018 OUT1 0 N030 N002 N004 N023 N035 N033 N036 N034 N031 N024 PWM7 N005 N009 IN N003 N019 0 LTC3888 Frequency_Switch=500 Vout0=2.5 Vout1=3 PWM_config=3 GM0=3.02m GM1=3.02m Ton_Rise0=300u Ton_Rise1=300u Toff_Fall0=300u Toff_Fall1=300u Ton_Delay0=0 Ton_Delay1=0 Toff_Delay0=0 Toff_Delay1=0 Rith0=5K Rith1=5K OC_Limit0=50 OC_Limit1=50 Ton_Min=45n VOUT_UV_Fault_Limit0=2.2 VOUT_UV_Fault_Limit1=2.8 VOUT_OV_Fault_Limit0=2.6 VOUT_OV_Fault_Limit1=3.1 Iout_Cal_Gain=5m Slave0=0 Slave1=0 ;pnba PWM0)PWM1)ISENSE0)ISENSE1)PWM2)VSENSE0-)VSENSE0+)ISENSE2)ITH0)ITHR0)PGOOD0)PGOOD1)ITHR1)SYNC)ITH1)CLKOUT)VSENSE1+)VSENSE1-)PWM3)RUN0)RUN1)ISENSE3)PWM4)ISENSE4)PWM5)ISENSE5)PWM6)ISENSE6)PWM7)VDD33)INTVCC)VIN)IREF)ISENSE7)GND
R12 N019 N003 500
Rload1 OUT1 0 25m
R15 N005 N018 10K
L5 N010 OUT1 0.2 Rser=20m
R14 N003 N034 500
XU3 N001 N030 N001 0 N029 N033 N035 N001 N001 IN N025 0 N023 N002 N002 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
XU4 N001 N015 N001 0 N016 N019 PWM7 N001 N001 IN N010 0 N007 N004 N004 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
Rload0 OUT0 0 20.8m
R6 N005 N013 100K
C6 N022 0 100p
L8 N032 OUT1 0.2 Rser=20m
C3 N009 0 4.7
L6 N016 OUT1 0.2 Rser=20m
R11 N007 N003 500
L3 N025 OUT0 0.2 Rser=20m
L4 N029 OUT0 0.2 Rser=20m
L2 N011 OUT0 0.2 Rser=20m
V1 IN 0 12
R13 N024 N003 500
C4 N021 0 100p
R4 N017 N003 500
L7 N028 OUT1 0.2 Rser=20m
R5 N006 N003 500
V2 N001 0 6
R9 N003 N033 500
C5 N026 0 3300p
C1 N005 0 2.2
C7 N027 0 3300p
C8 OUT1 0 220 m=7 Rser=2.5m
XU2 N001 N012 N001 0 N011 N017 N020 N001 N001 IN N008 0 N006 N002 N002 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
R2 N005 N014 100K
R1 N005 N002 100K
R7 N005 N004 100K
.tran 1m startup
.lib LTC3888.sub
.lib LTC7050.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
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SYMBOL res 1776 2192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R14
SYMATTR Value 500
SYMBOL res 688 1872 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 500
SYMBOL res 1536 816 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 100K
SYMBOL voltage 320 336 R0
SYMATTR InstName V2
SYMATTR Value 6
SYMBOL res -528 640 R0
SYMATTR InstName Rload0
SYMATTR Value 20.8m
SYMBOL ind 0 1632 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL cap 1088 1600 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 3300p
SYMBOL res 2992 640 R0
SYMATTR InstName Rload1
SYMATTR Value 25m
SYMBOL LTC7050 2288 928 R0
SYMATTR InstName U4
SYMBOL ind 2592 656 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L5
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL ind 2592 1632 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L7
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL ind 0 944 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL res 688 2064 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 500
SYMBOL LTC7050 320 1904 M0
SYMATTR InstName U3
SYMBOL ind 0 1920 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL ind 2592 944 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L6
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL ind 2592 1920 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L8
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL ind 0 656 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL res 1872 1264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 500
SYMBOL voltage 80 320 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 1888 2032 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R13
SYMATTR Value 500
SYMBOL res 1536 1008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R15
SYMATTR Value 10K
SYMBOL res 800 2160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 500
SYMBOL res 1536 912 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 1888 1840 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 500
SYMBOL cap 1424 624 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL res 976 944 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 100K
SYMBOL cap 1072 720 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL cap 1440 1600 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 3300p
SYMBOL LTC7050 2288 1904 R0
SYMATTR InstName U5
SYMBOL LTC3888 1264 1376 R0
SYMATTR InstName U1
SYMATTR SpiceLine Frequency_Switch=500 Vout0=2.5 Vout1=3 PWM_config=3 GM0=3.02m GM1=3.02m Ton_Rise0=300u Ton_Rise1=300u Toff_Fall0=300u Toff_Fall1=300u Ton_Delay0=0 Ton_Delay1=0 Toff_Delay0=0
SYMATTR SpiceLine2 Toff_Delay1=0 Rith0=5K Rith1=5K OC_Limit0=50 OC_Limit1=50 Ton_Min=45n VOUT_UV_Fault_Limit0=2.2 VOUT_UV_Fault_Limit1=2.8 VOUT_OV_Fault_Limit0=2.6 VOUT_OV_Fault_Limit1=3.1 Iout_Cal_Gain=5m Slave0=0 Slave1=0
SYMBOL cap 1440 1504 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 100p
SYMBOL cap -368 656 R0
WINDOW 3 40 52 Left 2
WINDOW 0 39 8 Left 2
WINDOW 123 40 77 Left 2
SYMATTR Value 220
SYMATTR InstName C2
SYMATTR Value2 m=7
SYMATTR SpiceLine Rser=2.5m
SYMBOL cap 2800 656 R0
WINDOW 3 40 52 Left 2
WINDOW 0 39 8 Left 2
WINDOW 123 40 77 Left 2
SYMATTR Value 220
SYMATTR InstName C8
SYMATTR Value2 m=7
SYMATTR SpiceLine Rser=2.5m
SYMBOL res 976 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap 1088 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100p
SYMBOL LTC7050 320 928 M0
SYMATTR InstName U2
SYMBOL res 688 1296 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 500
FLAG 80 432 0
FLAG 128 272 IN
FLAG 992 736 0
FLAG 1504 640 0
FLAG 1104 1024 0
FLAG 320 1280 0
FLAG 1264 2272 0
FLAG -352 752 0
FLAG -512 752 0
FLAG 160 1216 0
FLAG 1104 1424 0
FLAG 1008 1520 0
FLAG 1008 1616 0
FLAG 1520 1520 0
FLAG 1520 1616 0
FLAG -432 640 OUT0
FLAG 320 2256 0
FLAG 160 2192 0
FLAG 2288 1280 0
FLAG 2816 752 0
FLAG 3008 752 0
FLAG 2448 1216 0
FLAG 2928 640 OUT1
FLAG 2288 2256 0
FLAG 2448 2192 0
FLAG 1424 1424 0
FLAG 320 448 0
FLAG 1472 1712 PWM7
TEXT 2824 1064 Left 2 ;*************** READ ME **********************************************************************\n \nThis model does not cover the PMBUS and SPI functions of this IC.\nTherefore, many things controlled by the PMBUS are configured by CTRL + right click on the IC.\nShare_CLK is NOT modelled. The SYNC pin can only be used as an input and\nit is grounded when it is not used. CLK_OUT pin is provided to allow clock out function.\nResistor setting pins like Vout_CFG are not modeled.\nVout and PWM_config must be set by CTRL by right-clicking on the IC.\n \nFrequency_Switch sets the frequency in kHz between 250 and 1000.\nPWM_config controls the phasing and master/slave configuration of the 8 channels.\nA decimal number is used for the 3-bit binary number. The description starts on page 72 of the datasheet.\n \n# (PWM0: PWM1)\n7 (7 phase: 1 Phase)\n6 (6 phase: 2 Phase)\n5 (6 phase: 1 phase)\n4 (5 phase: 3 phase)\n3 (4 phase: 4 phase)\n2 (4 phase: 3 phase)\n1 (4 phase: 2 phase)\n0 (3 phase: 3 phase)\n \nVout0 and Vout1 program the output voltage in a range from 0.3 to 3.45V\nVout_trans_rate0 and Vout_trans_rate1 program the rate of movement of VOUT as the part is starting or margining (V/ms).\nGM0 and GM1 program the gain the Error Amplifier in range from 1 to 5.73mS\nIout_Cal_Gain should match the voltage gain of the chosen current sense (V/A)\nRith0 and Rith1 program the compensation resistor in series \n                with Cithr on the output of the error amplifier in a range from 1k to 62k ohm\nTon_Min=45n programs the minimum on time of the PWM outputs\n \nOC_Limit0 and OC_Limit1 program the peak current limit of the each phase used for that converter. \n \nTon_Delay0 and Ton_Delay1 set the delay from when the RUN pin goes high until the soft-start begins\nToff_Delay0 and Toff_Delay1 set the delay from when the RUN pin goes low until the turn-off ramp begins\n \nVOUT_UV_Fault_Limit0 and VOUT_UV_Fault_Limit1 program the undervoltage fault limit for the Pgood output\nVOUT_OV_Fault_Limit0 and VOUT_OV_Fault_Limit1 program the overvoltage fault limit for the Pgood output\n \nSlave0 and Slave1 set slave channel. 0 disable,1 enable. If enabled the error amplifier is open circuit
TEXT 2824 896 Left 2 !.tran 1m startup