Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\008583889490_4_2_1_b.asc
* Generated by LTspice 26.0.1 for Windows.
XOP N004 N001 N003 N005 N002 TL074 ;pnba In+)In-)V+)V-)OUT
V3 0 N005 15V
V2 N003 0 15V
Ri N004 0 10k
R1 N001 0 2k
Ro Vo N002 10k
R2 N002 N001 18k
V1 N004 0 AC 15mV
.inc TL074.txt
.ac dec 500 5k 5MegaHz
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 32 192 32
WIRE 384 32 336 32
WIRE 256 64 144 64
WIRE 256 96 256 64
WIRE 192 112 192 32
WIRE 224 112 192 112
WIRE 384 128 384 32
WIRE 384 128 288 128
WIRE 432 128 384 128
WIRE 560 128 512 128
WIRE 112 144 80 144
WIRE 224 144 112 144
WIRE 112 176 112 144
WIRE 192 176 192 112
WIRE 256 272 256 160
SYMBOL voltage 352 272 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value 15V
SYMBOL res 528 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Ro
SYMATTR Value 10k
SYMBOL res 176 160 R0
SYMATTR InstName R1
SYMATTR Value 2k
SYMBOL voltage 96 144 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 60 56 VTop 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 15mV
SYMBOL voltage 160 64 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value 15V
SYMBOL res 96 160 R0
SYMATTR InstName Ri
SYMATTR Value 10k
SYMBOL res 352 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 18k
SYMBOL Opamps\\opamp2 256 64 R0
SYMATTR InstName OP
SYMATTR Value TL074
FLAG 192 256 0
FLAG 112 256 0
FLAG 336 272 0
FLAG 64 64 0
FLAG 0 144 0
FLAG 560 128 Vo
TEXT 72 296 Left 2 !.inc TL074.txt
TEXT -24 336 Left 2 !.ac dec 500 5k 5MegaHz
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3020-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 PWL(0 0 1 10)
Rload OUT 0 100
C1 OUT 0 2.2
XU1 OUT MP_01 MP_02 0 N001 MP_03 N001 LT3020-1.5 ;pnba OUT)))GND)_SHDN))IN
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3020-1.5.asy)
.lib LT3020.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 160 -176 160
WIRE 16 160 0 160
WIRE 368 160 304 160
WIRE 464 160 368 160
WIRE 368 176 368 160
WIRE 464 176 464 160
WIRE -176 192 -176 160
WIRE 0 256 0 160
WIRE 16 256 0 256
WIRE 368 272 368 240
WIRE 464 272 464 256
WIRE -176 288 -176 272
WIRE 160 336 160 320
FLAG 160 336 0
FLAG 368 272 0
FLAG 464 272 0
FLAG -176 288 0
FLAG 464 160 OUT
SYMBOL voltage -176 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 448 160 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 352 176 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL PowerProducts\\LT3020-1.5 160 192 R0
SYMATTR InstName U1
TEXT 384 352 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\b12d010128c3_2_2_1_c.asc
* Generated by LTspice 26.0.1 for Windows.
Vi N001 0 5V
QNPN-Transistor P001 VBE 0 0 BC547B
RC P002 P001 200
VDD P002 0 10V
R1 N001 VBE R
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc VI 0 10 .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 80 32 80
WIRE 208 80 192 80
WIRE 240 80 208 80
WIRE 32 144 32 80
WIRE 32 256 32 224
WIRE 304 256 304 128
SYMBOL npn 240 32 R0
WINDOW 3 58 60 Left 2
SYMATTR Value BC547B
SYMATTR InstName NPN-Transistor
SYMBOL voltage 32 128 R0
SYMATTR InstName Vi
SYMATTR Value 5V
SYMBOL voltage 304 -32 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName VDD
SYMATTR Value 10V
SYMBOL res 288 -64 R0
SYMATTR InstName RC
SYMATTR Value 200
SYMBOL res 96 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
FLAG 304 256 0
FLAG 32 256 0
FLAG 304 -128 0
FLAG 208 80 VBE
TEXT 48 288 Left 2 !.dc VI 0 10 .01
* Z:\home\khalils\Downloads\files\data\raw_asc\06e6db310b37_ADC_R_2R_bit_1__mismatch.asc
* Generated by LTspice 26.0.1 for Windows.
S3 N001 Vrefp Bin Vtrip switmod
R3 Vtrip 0 100Meg
R2 Out_top Out_bot 10k
R4 VDD Vtrip 100Meg
R1 Out_top N001 20.1k
S4 Vrefm N001 Vtrip Bin switmod
.model switmod SW
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2740 696
WIRE 944 -752 912 -752
WIRE 1008 -784 912 -784
WIRE 1008 -784 1008 -864
WIRE 1008 -688 1008 -784
WIRE 1024 -864 1008 -864
WIRE 1024 -752 944 -752
WIRE 1024 -752 1024 -816
WIRE 1024 -736 1024 -752
WIRE 1024 -688 1008 -688
WIRE 1072 -1392 912 -1392
WIRE 1072 -1328 1072 -1392
WIRE 1072 -1216 1072 -1248
WIRE 1072 -1184 1072 -1216
WIRE 1072 -1040 1072 -1104
WIRE 1072 -928 1008 -928
WIRE 1072 -880 1072 -928
WIRE 1072 -784 1072 -800
WIRE 1072 -752 1072 -784
WIRE 1072 -624 1008 -624
WIRE 1072 -624 1072 -672
WIRE 1152 -1216 1072 -1216
WIRE 1184 -1216 1152 -1216
WIRE 1280 -784 1072 -784
WIRE 1408 -784 1360 -784
WIRE 1408 -768 1408 -784
WIRE 1408 -640 1408 -688
WIRE 1584 -784 1408 -784
WIRE 1584 -640 1408 -640
IOPIN 912 -1392 In
IOPIN 1008 -624 In
IOPIN 1008 -928 In
IOPIN 912 -784 In
IOPIN 1584 -784 Out
IOPIN 1584 -640 Out
SYMBOL res 1056 -1344 R0
SYMATTR InstName R4
SYMATTR Value 100MEG
SYMBOL sw 1072 -784 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S3
SYMBOL res 1392 -784 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 1056 -1200 R0
SYMATTR InstName R3
SYMATTR Value 100MEG
SYMBOL res 1376 -800 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 20.1k
SYMBOL sw 1072 -656 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S4
FLAG 1152 -1216 Vtrip
FLAG 1072 -1040 0
FLAG 912 -1392 VDD
FLAG 1008 -624 Vrefm
FLAG 1008 -928 Vrefp
FLAG 912 -784 Bin
FLAG 1584 -784 Out_top
FLAG 1584 -640 Out_bot
FLAG 944 -752 Vtrip
TEXT 1264 -1048 Left 0 !.model switmod SW
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4609.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 N002 5.6
C1 OUT 0 330
R1 N003 0 7.5m
R2 0 N009 2.74K
V1 IN 0 18
C2 N011 0 .002
R3 N006 N004 100K
Rload OUT 0 15
XU1 N009 OUT 0 N001 IN N002 N003 N003 0 N006 N004 N010 N005 N011 IN N007 N008 0 0 NC_01 LTM4609 ;pnba FB)Vout)SGND)SW2)Vin)SW1)Rsense)Sense+)Sense-)Pgood)INTVcc)PLLFLTR)STBYMD)SS)Run)Comp)PLLIN)FCB)PGND)EXTVcc
.tran 100m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4609.asy)
.lib LTM4609.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1268 680
WIRE 208 -96 176 -96
WIRE 320 -96 288 -96
WIRE 176 -48 176 -96
WIRE 320 -48 320 -96
WIRE 32 16 -80 16
WIRE 64 16 32 16
WIRE 560 16 448 16
WIRE 656 16 560 16
WIRE -80 32 -80 16
WIRE 560 32 560 16
WIRE 656 32 656 16
WIRE 32 80 32 16
WIRE 64 80 32 80
WIRE 464 80 448 80
WIRE -80 128 -80 112
WIRE 560 128 560 96
WIRE 656 128 656 112
WIRE 480 144 448 144
WIRE 512 144 480 144
WIRE 512 160 512 144
WIRE 64 208 -48 208
WIRE 480 208 480 144
WIRE 480 208 448 208
WIRE -48 240 -48 208
WIRE 64 272 48 272
WIRE 512 272 512 240
WIRE 512 272 448 272
WIRE 512 288 512 272
WIRE -48 336 -48 320
WIRE 64 336 -48 336
WIRE 464 336 448 336
WIRE 64 400 48 400
WIRE 464 400 448 400
WIRE 560 400 544 400
WIRE 64 464 48 464
WIRE 496 464 448 464
WIRE 496 480 496 464
WIRE 176 544 176 528
WIRE 320 544 320 528
WIRE 496 560 496 544
FLAG 464 80 0
FLAG 560 128 0
FLAG 656 128 0
FLAG 560 400 0
FLAG 512 288 0
FLAG 320 544 0
FLAG 176 544 0
FLAG -80 128 0
FLAG 496 560 0
FLAG -80 16 IN
FLAG 656 16 OUT
SYMBOL ind 192 -80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5.6
SYMBOL cap 544 32 R0
SYMATTR InstName C1
SYMATTR Value 330
SYMBOL res 496 144 R0
SYMATTR InstName R1
SYMATTR Value 7.5m
SYMBOL res 560 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 2.74K
SYMBOL voltage -80 16 R0
SYMATTR InstName V1
SYMATTR Value 18
SYMBOL cap 480 480 R0
SYMATTR InstName C2
SYMATTR Value .002
SYMBOL res -64 336 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 640 16 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL PowerProducts\\LTM4609 256 240 R0
SYMATTR InstName U1
TEXT 584 480 Left 2 !.tran 100m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL40505A.asc
* Generated by LTspice 26.0.1 for Windows.
C2 OUT N001 10n
C3 OUT 0 4.7
R1 OUT 0 2
R2 OUT N003 200k
R3 N003 0 301k
R4 IN N002 100k
XU1 IN OUT IN N003 N002 N001 IN 0 ADPL40505A ;pnba IN)OUT)EN)FB)POK)BYP)MODE)GND
V3 IN 0 1.7
.tran 10m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL40505A.asy)
.lib ADPL40505A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1988 1984
WIRE -64 1104 -144 1104
WIRE -16 1104 -64 1104
WIRE 80 1104 -16 1104
WIRE 96 1104 80 1104
WIRE 368 1104 320 1104
WIRE 448 1104 368 1104
WIRE 560 1104 448 1104
WIRE 656 1104 560 1104
WIRE -144 1120 -144 1104
WIRE 368 1120 368 1104
WIRE 560 1120 560 1104
WIRE 656 1120 656 1104
WIRE -16 1136 -16 1104
WIRE 448 1152 448 1104
WIRE 80 1200 80 1104
WIRE 96 1200 80 1200
WIRE 368 1200 368 1184
WIRE 368 1200 320 1200
WIRE -144 1216 -144 1200
WIRE 560 1216 560 1184
WIRE 656 1216 656 1200
WIRE -16 1280 -16 1216
WIRE 96 1280 -16 1280
WIRE 448 1280 448 1232
WIRE 448 1280 320 1280
WIRE 448 1312 448 1280
WIRE -64 1344 -64 1104
WIRE 96 1344 -64 1344
WIRE 208 1408 208 1392
WIRE 448 1408 448 1392
FLAG -144 1216 0
FLAG -144 1104 IN
FLAG 560 1216 0
FLAG 656 1216 0
FLAG 656 1104 OUT
FLAG 448 1408 0
FLAG 208 1408 0
SYMBOL cap 352 1120 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap 544 1120 R0
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL res 640 1104 R0
SYMATTR InstName R1
SYMATTR Value 2
SYMBOL res 432 1136 R0
SYMATTR InstName R2
SYMATTR Value 200k
SYMBOL res 432 1296 R0
SYMATTR InstName R3
SYMATTR Value 301k
SYMBOL res -32 1120 R0
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL ADPL40505A 208 1184 R0
SYMATTR InstName U1
SYMBOL voltage -144 1104 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 1.7
TEXT 96 1448 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6200.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6200.asy)
R1 OUT N001 1K
R2 N001 0 1K
V1 +V 0 5
V3 N002 0 SINE(0 1 1Meg)
V2 -V 0 -5
XU1 N002 N001 OUT +V -V NC_01 LT6200 ;pnba IN+)IN-)OUT)VCC)VEE)SHDN_L
.tran 10u
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -112 48 -128 48
WIRE 0 48 -32 48
WIRE 96 48 0 48
WIRE 208 48 176 48
WIRE 64 112 64 96
WIRE -416 160 -416 144
WIRE -288 160 -288 144
WIRE 0 160 0 48
WIRE 32 160 0 160
WIRE 208 192 208 48
WIRE 208 192 176 192
WIRE 256 192 208 192
WIRE 32 224 -176 224
WIRE -176 240 -176 224
WIRE -416 256 -416 240
WIRE -288 256 -288 240
WIRE 64 288 64 272
WIRE -176 336 -176 320
SYMBOL res -16 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 192 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -176 224 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1Meg)
SYMBOL voltage -416 144 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL opamps\\LT6200 64 192 R0
SYMATTR InstName U1
FLAG -288 256 0
FLAG 64 96 +V
FLAG -288 144 +V
FLAG 64 288 -V
FLAG -416 256 0
FLAG -416 144 -V
FLAG -128 48 0
FLAG -176 336 0
FLAG 256 192 OUT
TEXT 152 312 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL40502-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vIN 0 5
Rload vOUT 0 15
C1 vOUT 0 1 Rser=1m
XU1 vIN 0 vIN vOUT ADPL40502-3.0 ;pnba Vin)GND)EN)Vout
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL40502-3.0.asy)
.lib ADPL40502-3.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2808 1464
WIRE 1824 880 1728 880
WIRE 1984 880 1824 880
WIRE 1728 896 1728 880
WIRE 1984 896 1984 880
WIRE 1728 992 1728 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
FLAG 2256 1024 vOUT
FLAG 2256 1136 0
FLAG 1728 992 0
FLAG 1728 880 vIN
FLAG 1984 1168 0
FLAG 2160 1136 0
SYMBOL VOLTAGE 1728 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1u
SYMATTR SpiceLine Rser=1m
SYMBOL ADPL40502-3.0 1984 1024 R0
SYMATTR InstName U1
TEXT 2144 1200 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1071.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1071.asy)
XU1 N003 N002 0 N001 IN LT1071 ;pnba Vc)FB)GND)SW)Vin
R2 N002 0 1.24K
R3 N003 N004 1K
R1 OUT N002 10.7K
V1 IN 0 5
C1 OUT 0 500 Rser=15m
D1 N001 OUT MBRS360
L1 IN N001 150 Rser=0.02 Rpar=5000
C2 N004 0 1
Rload OUT 0 24
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 20m startup
.lib LT1071.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1480
WIRE 1824 880 1584 880
WIRE 1872 880 1824 880
WIRE 1984 880 1952 880
WIRE 2048 880 1984 880
WIRE 2160 880 2112 880
WIRE 2288 880 2160 880
WIRE 2400 880 2288 880
WIRE 1584 896 1584 880
WIRE 2288 896 2288 880
WIRE 2400 896 2400 880
WIRE 1824 944 1824 880
WIRE 2160 960 2160 880
WIRE 1584 992 1584 976
WIRE 2288 992 2288 960
WIRE 2400 992 2400 976
WIRE 1984 1024 1984 880
WIRE 1984 1024 1952 1024
WIRE 2160 1088 2160 1040
WIRE 2160 1088 1952 1088
WIRE 2160 1104 2160 1088
WIRE 1968 1152 1952 1152
WIRE 2064 1152 2048 1152
WIRE 2064 1168 2064 1152
WIRE 2160 1200 2160 1184
WIRE 1824 1248 1824 1232
WIRE 2064 1248 2064 1232
SYMBOL schottky 2048 896 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMBOL POWERPRODUCTS\\LT1071 1824 1088 R0
SYMATTR InstName U1
SYMBOL RES 1952 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL polcap 2272 896 R0
SYMATTR InstName C1
SYMATTR Value 500
SYMATTR SpiceLine Rser=15m
SYMBOL RES 2144 1088 R0
SYMATTR InstName R2
SYMATTR Value 1.24K
SYMBOL RES 2144 944 R0
SYMATTR InstName R1
SYMATTR Value 10.7K
SYMBOL VOLTAGE 1584 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 2384 880 R0
SYMATTR InstName Rload
SYMATTR Value 24
SYMBOL CAP 2048 1168 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL IND 1856 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 2400 880 OUT
FLAG 2160 1200 0
FLAG 2288 992 0
FLAG 2400 992 0
FLAG 2064 1248 0
FLAG 1824 1248 0
FLAG 1584 992 0
FLAG 1584 880 IN
TEXT 2104 1312 Left 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\172170e1cd68_1764.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10 Rser=100m
Rload OUT 0 500
XU1 IN IN 0 OUT OUT LT1764 ;pnba _SHDN)IN)GND)OUT)ADJ
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1764.asy)
.lib LT1764.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -224 48
WIRE 16 48 0 48
WIRE 320 48 304 48
WIRE 384 48 320 48
WIRE 544 48 384 48
WIRE -224 64 -224 48
WIRE 384 64 384 48
WIRE 544 64 544 48
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 320 144 320 48
WIRE 320 144 304 144
WIRE -224 160 -224 144
WIRE 384 160 384 128
WIRE 544 160 544 144
WIRE 160 240 160 208
FLAG -224 160 0
FLAG 384 160 0
FLAG 544 160 0
FLAG 160 240 0
FLAG 544 48 OUT
FLAG -224 48 IN
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 368 64 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 Rser=100m
SYMATTR InstName C1
SYMATTR Value 10u
SYMBOL res 528 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT1764 160 96 R0
SYMATTR InstName U1
TEXT 352 232 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1764-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1764-1.5.asy)
V1 IN 0 PWL(0 0 1 10)
XU1 IN IN 0 OUT OUT LT1764-1.5 ;pnba _SHDN)IN)GND)OUT)Sense
C1 OUT 0 10 Rser=100m
Rload OUT 0 500
.tran 1
.lib LT1764.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 16 48 0 48
WIRE 320 48 304 48
WIRE 384 48 320 48
WIRE 560 48 384 48
WIRE -208 64 -208 48
WIRE 384 64 384 48
WIRE 560 64 560 48
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 320 144 320 48
WIRE 320 144 304 144
WIRE -208 160 -208 144
WIRE 384 160 384 128
WIRE 560 160 560 144
WIRE 160 240 160 208
SYMBOL cap 368 64 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=100m
SYMATTR InstName C1
SYMATTR Value 10u
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1764-1.5 160 96 R0
SYMATTR InstName U1
SYMBOL res 544 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG -208 160 0
FLAG 384 160 0
FLAG 560 160 0
FLAG 160 240 0
FLAG -208 48 IN
FLAG 560 48 OUT
TEXT 376 216 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\199ed153eee7_2050HV.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC2050HV.asy)
V3 N003 0 SINE(0 1 1K)
XU1 N003 N001 +V -V N002 NC_01 LTC2050 ;pnba In+)In-)V+)V-)OUT)SHDN
R1 N002 N001 10K
V2 -V 0 -2.5
V1 +V 0 2.5
R2 N001 0 10K
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -48 -64 -64 -64
WIRE 48 -64 32 -64
WIRE 112 -64 48 -64
WIRE 224 -64 192 -64
WIRE -288 16 -288 0
WIRE -160 16 -160 0
WIRE 48 64 48 -64
WIRE 64 64 48 64
WIRE 224 96 224 -64
WIRE 224 96 208 96
WIRE -288 112 -288 96
WIRE -160 112 -160 96
WIRE 64 128 -96 128
WIRE -96 160 -96 128
WIRE 96 192 96 176
WIRE -96 256 -96 240
SYMBOL opamps\\LTC2050HV 96 96 R0
SYMATTR InstName U1
SYMBOL res 208 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -160 0 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage -288 0 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 48 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage -96 144 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
FLAG -160 112 0
FLAG 96 16 +V
FLAG -160 0 +V
FLAG 96 192 -V
FLAG -288 112 0
FLAG -288 0 -V
FLAG -96 256 0
FLAG -64 -64 0
TEXT 224 240 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\46faddf66dc0_final_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout Vin 0 0 NMOS l=0.36u w={w}
Rd Vdd Vout 31.8k
CL Vout 0 1p
V1 Vdd 0 1.8
V2 Vin 0 SINE(0.65 1m 1k) AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include tsmc180.txt
.param w 3.97u
;.step param w 0.18u 7.2u 0.18u
* DC Sweeping
* .op
* .tran 5m
* .tf V(Vout) V2
.ac dec 10 10 1gig
* EDIC Winter Internship Assignment\nCommon Source Amplifier with Resistive(Passive) Load\nMohammed Ahmed Majid\nGP5405, 23EEBEA666
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -32 240 -80
WIRE 240 80 240 48
WIRE 464 80 240 80
WIRE 528 80 464 80
WIRE 240 96 240 80
WIRE 464 112 464 80
WIRE -400 144 -400 96
WIRE -256 144 -256 96
WIRE 336 144 240 144
WIRE 192 176 112 176
WIRE 240 224 240 192
WIRE 336 224 336 144
WIRE 336 224 240 224
WIRE 464 224 464 176
WIRE -400 288 -400 224
WIRE -256 288 -256 224
WIRE 240 288 240 224
FLAG 240 288 0
FLAG 464 224 0
FLAG 528 80 Vout
IOPIN 528 80 Out
FLAG 112 176 Vin
FLAG 240 -80 Vdd
FLAG -256 96 Vin
FLAG -400 96 Vdd
FLAG -400 288 0
FLAG -256 288 0
SYMBOL nmos4 192 96 R0
WINDOW 123 248 144 Right 2
SYMATTR InstName M1
SYMATTR Value2 l=0.36u w={w}
SYMBOL res 224 -48 R0
SYMATTR InstName Rd
SYMATTR Value 31.8k
SYMBOL cap 448 112 R0
SYMATTR InstName CL
SYMATTR Value 1p
SYMBOL voltage -400 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL voltage -256 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0.65 1m 1k)
SYMATTR Value2 AC 1
TEXT -376 -144 Left 2 !.include tsmc180.txt
TEXT -376 -120 Left 2 !.param w 3.97u
TEXT -384 -96 Left 2 !;.step param w 0.18u 7.2u 0.18u
TEXT -552 -120 Left 2 ;DC Sweeping
TEXT -376 -72 Left 2 ;.op
TEXT -376 -48 Left 2 ;.tran 5m
TEXT -376 -24 Left 2 ;.tf V(Vout) V2
TEXT -376 0 Left 2 !.ac dec 10 10 1gig
TEXT -552 -304 Left 2 ;EDIC Winter Internship Assignment\nCommon Source Amplifier with Resistive(Passive) Load\nMohammed Ahmed Majid\nGP5405, 23EEBEA666
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1563-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\FilterProducts\LTC1563-2.asy)
V2 N001 0 3.3
C1 N007 0 .1
R4 OUT N003 10K
R1 N004 N002 10K
R3 N005 N003 10K
R2 N006 N002 10K
V1 IN 0 1.66 ac 1
R6 N003 N006 10K
XU1 N001 N002 N004 N006 N007 0 0 N003 N005 OUT N001 LTC1563-2 ;pnba _LP)SA)INVA)LPA)AGND)V-)_EN)SB)INVB)LPB)V+
R5 N002 IN 10K
.ac oct 10 1 100Meg
.lib LTC1563-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1124 2376
WIRE 240 1632 -16 1632
WIRE 560 1632 240 1632
WIRE -16 1648 -16 1632
WIRE 240 1680 240 1632
WIRE 256 1680 240 1680
WIRE 560 1680 560 1632
WIRE 560 1680 544 1680
WIRE -16 1744 -16 1728
WIRE 256 1760 16 1760
WIRE 592 1760 544 1760
WIRE 656 1760 592 1760
WIRE 784 1760 736 1760
WIRE 16 1840 16 1760
WIRE 144 1840 16 1840
WIRE 256 1840 224 1840
WIRE 576 1840 544 1840
WIRE 784 1840 784 1760
WIRE 784 1840 656 1840
WIRE -80 1920 -160 1920
WIRE 16 1920 16 1840
WIRE 16 1920 0 1920
WIRE 32 1920 16 1920
WIRE 128 1920 112 1920
WIRE 256 1920 128 1920
WIRE 784 1920 784 1840
WIRE 784 1920 544 1920
WIRE -160 1936 -160 1920
WIRE 176 2000 160 2000
WIRE 256 2000 240 2000
WIRE 784 2000 784 1920
WIRE -160 2032 -160 2016
WIRE 256 2080 240 2080
WIRE 560 2080 544 2080
WIRE 128 2144 128 1920
WIRE 784 2144 784 2080
WIRE 784 2144 128 2144
SYMBOL VOLTAGE -160 1920 R0
SYMATTR InstName V1
SYMATTR Value 1.66 ac 1
SYMBOL LTC1563-2 400 2016 R0
SYMATTR InstName U1
SYMBOL res 768 1984 R0
SYMATTR InstName R6
SYMATTR Value 10K
SYMBOL VOLTAGE -16 1632 R0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 240 1824 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 1744 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL cap 240 1984 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 128 1904 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 16 1904 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL res 560 1824 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
FLAG -16 1744 0
FLAG 240 2080 0
FLAG 560 2080 0
FLAG 160 2000 0
FLAG -160 2032 0
FLAG 592 1760 OUT
FLAG -160 1920 IN
TEXT 664 2184 Left 2 !.ac oct 10 1 100Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\094610952361_How-to-set-initial-conditions.asc
* Generated by LTspice 26.0.1 for Windows.
* Example of setting initial conditions
C1 OUT 0 1
R1 OUT 0 1
.ic V(OUT)=10
.tran 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 64 112 64
WIRE 112 112 112 64
WIRE 208 112 208 64
WIRE 112 224 112 176
WIRE 208 224 208 192
SYMBOL res 192 96 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL cap 96 112 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 208 224 0
FLAG 112 224 0
FLAG 112 64 OUT
TEXT -96 112 Left 2 !.ic V(OUT)=10
TEXT -88 64 Left 2 !.tran 5
TEXT -96 -88 Left 4 ;Example of setting initial conditions