Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1626.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1626.asy)
D1 0 N001 MBRS340
R4 N008 0 10K
R3 OUT N008 10K
R1 N002 OUT .1
V1 IN 0 5
R2 N006 N005 470
XU1 MP_01 IN N003 N004 N007 N006 OUT N002 N008 0 0 MP_02 MP_03 N001 LTC1626 ;pnba )Vin)LBout)LBin)Ct)Ith)Sense-)Sense+)FB)SHDN)GND)))SW
C2 N005 0 3900p
C4 N002 OUT 1000p
Rload OUT 0 2
C3 OUT 0 200 Rser=0.01
C1 N007 0 270p
L1 N001 N002 50
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LTC1626.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2568 1600
WIRE 1488 1056 1168 1056
WIRE 1760 1056 1696 1056
WIRE 1808 1056 1760 1056
WIRE 1920 1056 1888 1056
WIRE 1936 1056 1920 1056
WIRE 2032 1056 2016 1056
WIRE 2080 1056 2032 1056
WIRE 2144 1056 2080 1056
WIRE 2240 1056 2144 1056
WIRE 1168 1072 1168 1056
WIRE 2144 1072 2144 1056
WIRE 2240 1072 2240 1056
WIRE 1488 1088 1488 1056
WIRE 1760 1088 1760 1056
WIRE 1312 1136 1296 1136
WIRE 1696 1136 1696 1056
WIRE 1696 1136 1664 1136
WIRE 1168 1168 1168 1152
WIRE 2144 1168 2144 1136
WIRE 2240 1168 2240 1152
WIRE 1760 1184 1760 1152
WIRE 1312 1216 1296 1216
WIRE 1696 1216 1664 1216
WIRE 1920 1216 1920 1056
WIRE 1920 1216 1696 1216
WIRE 2080 1264 2080 1056
WIRE 1120 1296 1088 1296
WIRE 1216 1296 1184 1296
WIRE 1312 1296 1296 1296
WIRE 1696 1296 1696 1280
WIRE 1696 1296 1664 1296
WIRE 2032 1296 2032 1056
WIRE 2032 1296 1696 1296
WIRE 1168 1376 1104 1376
WIRE 1312 1376 1232 1376
WIRE 2080 1376 2080 1344
WIRE 2080 1376 1664 1376
WIRE 2080 1392 2080 1376
WIRE 1392 1456 1392 1440
WIRE 1584 1456 1584 1440
WIRE 2080 1488 2080 1472
SYMBOL POWERPRODUCTS\\LTC1626 1488 1216 R0
SYMATTR InstName U1
SYMBOL cap 1232 1360 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 270p
SYMBOL polcap 2128 1072 R0
SYMATTR InstName C3
SYMATTR Value 200
SYMATTR SpiceLine Rser=0.01
SYMBOL cap 1184 1280 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 3900p
SYMBOL schottky 1744 1152 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL res 2064 1248 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL cap 1680 1216 R0
WINDOW 0 39 15 Left 2
SYMATTR InstName C4
SYMATTR Value 1000p
SYMBOL res 2064 1376 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 2224 1056 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL RES 1920 1072 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value .1
SYMBOL ind 1792 1072 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 50
SYMBOL res 1312 1280 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 470
SYMBOL VOLTAGE 1168 1056 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 1760 1184 0
FLAG 1584 1456 0
FLAG 1104 1376 0
FLAG 1088 1296 0
FLAG 1168 1168 0
FLAG 2144 1168 0
FLAG 2240 1168 0
FLAG 2240 1056 OUT
FLAG 1392 1456 0
FLAG 2080 1488 0
FLAG 1168 1056 IN
TEXT 1656 1488 Left 2 !.tran 1.5m startup
* Z:\tmp\asc_dec_bjh7r6w2\09689b9458cf_TDA8425_spatial_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
XUR R- Ri Vor opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
Rfr Vor R- 54k
Vil Li 0 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 0 -96 0
WIRE 160 0 0 0
WIRE -96 16 -96 0
WIRE 160 32 96 32
WIRE -96 112 -96 96
WIRE 96 128 96 32
WIRE 144 128 96 128
WIRE 240 128 240 16
WIRE 240 128 224 128
WIRE 96 160 96 128
WIRE 96 272 96 240
WIRE 144 272 96 272
WIRE 240 272 224 272
WIRE 96 352 96 272
WIRE 160 352 96 352
WIRE 240 368 240 272
WIRE 240 368 224 368
WIRE 304 368 240 368
WIRE 0 384 -96 384
WIRE 160 384 0 384
SYMBOL Opamps\\opamp 192 304 R0
SYMATTR InstName UR
SYMBOL res 240 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfr
SYMATTR Value 54k
SYMBOL voltage -96 0 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName Vil
SYMATTR Value 5
FLAG -96 112 0
FLAG 304 368 Vor
FLAG 0 0 Li
FLAG 96 32 L-
FLAG 96 352 R-
FLAG 0 384 Ri
* Z:\home\khalils\Downloads\files\data\raw_asc\2ffdb1ab515b_LossyTransmLineRG58U.asc
* Generated by LTspice 26.0.1 for Windows.
* .AC LIN 10 100MEG 1G
* RG58U 4.7mm coaxial cable\nFrequency att.(100m) Ohms/m\n(20MHz R'=0.8Ohm extrapolated)\n50MHz 10.5dB R'=1.2 Ohm\n100MHz 15.2dB R'=1.75 Ohm\n200MHz 22.2dB R'=2.55 Ohm\n400MHz 32.5dB R'=3.5 Ohm\n800MHz 48.5dB R'=5.6 Ohm\n1GHz 55.2dB R'=6.35 Ohm
* Z0 = sqrt(L/C) impedance\nC = 1/(Vp*Z0) F/m capacitance per meter\nL = Z0/Vp H/m inductance per meter\nVp = c0 / sqrt(e0) velocity\nt/m = sqrt(L*C) propagation time(delay) per meter
* Cable RG58U/C, length 100m : R = const*sqrt(f) R'=0.8Ohm/m at 20MHz.
* This example:\nL=100m\nZ=sqrt(L/C)=50 Ohm \ntpd = L*sqrt(L*C) = 100m * 5ns/m = 500ns
* A Lossy TRansmission Line Example
O1 in1 0 out 0 mytr
R2 out 0 50
V1 N001 0 PULSE(0 1 0 1n 1n 200n 1000n) AC 2
R1 N001 in1 50
.tran 0 2000n 0 0.5n
.model mytr ltra(R=1.75 C=100p L=250n Len=100)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2544 1412
WIRE 1328 1248 1392 1248
WIRE 1488 1248 1520 1248
WIRE 1056 1216 1136 1216
WIRE 1488 1216 1568 1216
WIRE 1056 1376 1056 1344
WIRE 1056 1264 1056 1216
WIRE 1216 1216 1264 1216
WIRE 1264 1216 1392 1216
WIRE 1568 1216 1600 1216
WIRE 1600 1248 1600 1216
WIRE 1600 1328 1600 1376
SYMBOL VOLTAGE 1056 1248 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 200n 1000n)
SYMBOL RES 1120 1232 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL res 1584 1232 R0
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL LTLINE 1440 1232 R0
WINDOW 0 -24 -40 Left 0
SYMATTR InstName O1
SYMATTR Value mytr
FLAG 1520 1248 GND
FLAG 1328 1248 GND
FLAG 1056 1376 GND
FLAG 1264 1216 in1
FLAG 1568 1216 out
FLAG 1600 1376 0
TEXT 912 960 Left 0 !.tran 0 2000n 0 0.5n
TEXT 912 992 Left 0 !.model mytr ltra(R=1.75 C=100p L=250n Len=100)
TEXT 912 928 Left 0 ;.AC LIN 10 100MEG 1G
TEXT 1568 896 Left 0 ;RG58U 4.7mm coaxial cable\nFrequency  att.(100m)  Ohms/m\n(20MHz                          R'=0.8Ohm extrapolated)\n50MHz        10.5dB        R'=1.2 Ohm\n100MHz      15.2dB        R'=1.75 Ohm\n200MHz      22.2dB        R'=2.55 Ohm\n400MHz      32.5dB        R'=3.5 Ohm\n800MHz      48.5dB        R'=5.6 Ohm\n1GHz           55.2dB       R'=6.35 Ohm
TEXT 912 744 Left 0 ;Z0 = sqrt(L/C)               impedance\nC = 1/(Vp*Z0) F/m        capacitance per meter\nL = Z0/Vp H/m              inductance per meter\nVp = c0 / sqrt(e0)          velocity\nt/m = sqrt(L*C)              propagation time(delay) per meter
TEXT 912 704 Left 0 ;Cable RG58U/C, length 100m :  R = const*sqrt(f)  R'=0.8Ohm/m at 20MHz.
TEXT 912 1032 Left 0 ;This example:\nL=100m\nZ=sqrt(L/C)=50 Ohm \ntpd = L*sqrt(L*C) = 100m * 5ns/m = 500ns
TEXT 912 640 Left 0 ;A Lossy TRansmission Line Example
* Z:\home\khalils\Downloads\files\data\raw_asc\ADR5044.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\ADR5044.asy)
Rload OUT 0 10k
Rbias IN OUT 715
XU1 OUT 0 ADR5044 ;pnba 1)2
Vin IN 0 4.5
.dc TEMP -40 125 .1
.lib ADR5044.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 960
WIRE 32 64 -80 64
WIRE 208 64 112 64
WIRE 464 64 208 64
WIRE -80 112 -80 64
WIRE 208 112 208 64
WIRE 464 112 464 64
WIRE -80 224 -80 192
WIRE 208 224 208 176
WIRE 208 224 -80 224
WIRE 464 224 464 192
WIRE 464 224 208 224
WIRE -80 256 -80 224
SYMBOL res 448 96 R0
SYMATTR InstName Rload
SYMATTR Value 10k
SYMBOL voltage -80 96 R0
WINDOW 3 36 62 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 30 32 Left 2
SYMATTR Value 4.5
SYMATTR InstName Vin
SYMBOL res 16 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName Rbias
SYMATTR Value 715
SYMBOL ADR5044 208 144 R0
SYMATTR InstName U1
FLAG -80 64 IN
FLAG -80 256 0
FLAG 464 64 OUT
TEXT -88 -32 Left 2 !.dc TEMP -40 125 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\0021c2b98987_parte1.asc
* Generated by LTspice 26.0.1 for Windows.
RL Vo 0 10k
Rsaida Vo Von 100k
Rs Vin Vi 10
Rentrada 0 Vin 10
EAiVi Von 0 Vin 0 1000
Vs Vi 0 1mV
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 680
WIRE 640 64 496 64
WIRE 816 64 720 64
WIRE 880 64 816 64
WIRE 0 80 -48 80
WIRE 128 80 0 80
WIRE 272 80 208 80
WIRE 288 80 272 80
WIRE 496 128 496 64
WIRE 288 144 288 80
WIRE 448 144 288 144
WIRE 880 144 880 64
WIRE 288 160 288 144
WIRE -48 176 -48 80
WIRE 448 192 384 192
WIRE 288 256 288 240
WIRE 384 256 384 192
WIRE 384 256 288 256
WIRE -48 288 -48 256
WIRE 288 288 288 256
WIRE 496 288 496 208
WIRE 880 288 880 224
SYMBOL res 864 128 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL res 304 256 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Rentrada
SYMATTR Value 10
SYMBOL res 224 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rs
SYMATTR Value 10
SYMBOL res 736 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rsaida
SYMATTR Value 100k
SYMBOL voltage -48 160 R0
SYMATTR InstName Vs
SYMATTR Value 1mV
SYMBOL e 496 112 R0
SYMATTR InstName AiVi
SYMATTR Value 1000
FLAG -48 288 0
FLAG 288 288 0
FLAG 496 288 0
FLAG 880 288 0
FLAG 816 64 Vo
FLAG 0 80 Vi
FLAG 272 80 Vin
FLAG 496 64 Von
TEXT -80 312 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\d269eb600f60_equalizer.asc
* Generated by LTspice 26.0.1 for Windows.
M1 BLB PRE BL 0 NMOS l={mc(SA_eq_L,mc_variation)} w={mc(SA_eq_W, mc_variation)}
M2 BL PRE HV 0 NMOS l={mc(SA_eq_L_half,mc_variation)} w={mc(SA_eq_W_half,mc_variation)}
M3 HV ePRE BLB 0 NMOS l={mc(SA_eq_L_half,mc_variation)} w={mc(SA_eq_W_half,mc_variation)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 96 48 96
WIRE 400 96 288 96
WIRE -80 144 -112 144
WIRE 160 144 -80 144
WIRE 208 144 160 144
WIRE 160 160 160 144
WIRE 336 160 336 144
WIRE 48 208 48 96
WIRE 80 208 48 208
WIRE 208 208 176 208
WIRE 256 208 208 208
WIRE 400 208 400 96
WIRE 400 208 352 208
WIRE 208 224 208 208
FLAG 240 96 0
FLAG 128 208 0
FLAG 304 208 0
FLAG -80 144 PRE
IOPIN -80 144 BiDir
FLAG 48 96 BL
IOPIN 48 96 BiDir
FLAG 400 96 BLB
IOPIN 400 96 BiDir
FLAG 208 224 HV
IOPIN 208 224 BiDir
FLAG 336 144 ePRE
IOPIN 336 144 BiDir
SYMBOL nmos4 288 144 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_eq_L,mc_variation)} w={mc(SA_eq_W, mc_variation)}
SYMBOL nmos4 80 160 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_eq_L_half,mc_variation)} w={mc(SA_eq_W_half,mc_variation)}
SYMBOL nmos4 256 160 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_eq_L_half,mc_variation)} w={mc(SA_eq_W_half,mc_variation)}
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX42410A.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vIN 0 12
C1 N003 0 2.2
L1 N002 vOUT 2.2 Rser=4.3m
C3 vOUT 0 100 m=4 Rser=5m
Rload vOUT 0 0.33
C2 N001 N002 0.1
R1 PGOOD N003 20k
R2 vOUT N004 49.9k
R3 N004 0 15.8k
C4 vOUT N004 220p
XU1 0 0 vIN vIN N002 N001 N003 NC_01 N004 PGOOD N003 NC_02 vOUT MAX42410A ;pnba GND)PGND)EN)SUP)LX)BST)BIAS)SYNCOUT)FB)PGOOD)SYNC)VEA)OUT
.tran 3m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX42410A.asy)
.lib MAX42410A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1272 680
WIRE 80 -144 64 -144
WIRE 144 -144 80 -144
WIRE 176 -144 144 -144
WIRE 512 -144 464 -144
WIRE 64 -128 64 -144
WIRE 512 -128 512 -144
WIRE 144 -96 144 -144
WIRE 176 -96 144 -96
WIRE 64 -32 64 -48
WIRE 512 -32 512 -64
WIRE 512 -32 464 -32
WIRE 592 -32 512 -32
WIRE 720 -32 672 -32
WIRE 848 -32 720 -32
WIRE 960 -32 848 -32
WIRE 1024 -32 960 -32
WIRE 1056 -32 1024 -32
WIRE 720 -16 720 -32
WIRE 1056 -16 1056 -32
WIRE 848 0 848 -32
WIRE 960 0 960 -32
WIRE 176 16 144 16
WIRE 656 32 720 -32
WIRE 656 32 464 32
WIRE 720 64 720 48
WIRE 1056 80 1056 64
WIRE 848 96 848 80
WIRE 848 96 464 96
WIRE 960 96 960 64
WIRE 960 96 848 96
WIRE 848 128 848 96
WIRE 480 224 464 224
WIRE 848 224 848 208
WIRE 144 272 144 16
WIRE 144 272 64 272
WIRE 176 272 144 272
WIRE 64 288 64 272
WIRE 512 288 464 288
WIRE 608 288 512 288
WIRE 320 352 320 336
WIRE 64 368 64 352
WIRE 144 400 144 272
WIRE 496 400 144 400
WIRE 608 400 608 288
WIRE 608 400 576 400
FLAG 64 -32 0
FLAG 64 368 0
FLAG 320 352 0
FLAG 720 64 0
FLAG 1056 80 0
FLAG 80 -144 vIN
FLAG 1024 -32 vOUT
FLAG 480 224 0
FLAG 848 224 0
FLAG 512 288 PGOOD
SYMBOL voltage 64 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 48 288 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL ind 576 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=4.3m
SYMBOL cap 704 -16 R0
WINDOW 3 43 38 Left 2
WINDOW 123 48 63 Left 2
SYMATTR Value 100
SYMATTR Value2 m=4
SYMATTR InstName C3
SYMATTR SpiceLine Rser=5m
SYMBOL res 1040 -32 R0
SYMATTR InstName Rload
SYMATTR Value 0.33
SYMBOL cap 496 -128 R0
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL res 592 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 20k
SYMBOL res 832 -16 R0
SYMATTR InstName R2
SYMATTR Value 49.9k
SYMBOL res 832 112 R0
SYMATTR InstName R3
SYMATTR Value 15.8k
SYMBOL cap 944 0 R0
SYMATTR InstName C4
SYMATTR Value 220p
SYMBOL MAX42410A 320 96 R0
SYMATTR InstName U1
TEXT 648 376 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM7223C.asc
* Generated by LTspice 26.0.1 for Windows.
V1 inputA 0 PULSE(0 5 0 2n 2n 5u 10u)
V2 inputB 0 PULSE(5 0 0 2n 2n 5u 10u)
V3 VDD1 0 5
V5 VDDA 0 12
C2 VOB 0 2n
V6 VDDB 0 12
C1 VOA 0 2n
XU1 0 inputA inputB 0 VDD1 0 VOB VDDB 0 VOA VDDA ADuM7223C ;pnba GND1)VIA)VIB)DISABLE)VDD1)GNDB)VOB)VDDB)GNDA)VOA)VDDA
.tran 50u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM7223C.asy)
.lib ADuM7223C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1228 692
WIRE 416 16 368 16
WIRE 688 16 416 16
WIRE 64 32 -64 32
WIRE -64 48 -64 32
WIRE 416 80 368 80
WIRE 592 80 416 80
WIRE 592 96 592 80
WIRE 16 112 -448 112
WIRE 64 112 16 112
WIRE 688 128 688 96
WIRE 432 144 368 144
WIRE -448 160 -448 112
WIRE 592 176 592 160
WIRE 16 192 -288 192
WIRE 64 192 16 192
WIRE 416 224 368 224
WIRE 688 224 416 224
WIRE -448 256 -448 240
WIRE 64 272 -80 272
WIRE 416 288 368 288
WIRE 592 288 416 288
WIRE -288 304 -288 272
WIRE -80 304 -80 272
WIRE 592 304 592 288
WIRE 16 352 -80 352
WIRE 64 352 16 352
WIRE 432 352 368 352
WIRE 432 368 432 352
WIRE -80 384 -80 352
WIRE 592 384 592 368
WIRE -80 480 -80 464
FLAG -80 480 0
FLAG -448 256 0
FLAG -288 304 0
FLAG 592 176 0
FLAG 592 384 0
FLAG 416 288 VOB
FLAG 416 80 VOA
FLAG 432 368 0
FLAG 432 144 0
FLAG 16 192 inputB
FLAG 688 304 0
FLAG 688 128 0
FLAG 16 352 VDD1
FLAG -64 48 0
FLAG 416 224 VDDB
FLAG 16 112 inputA
FLAG 416 16 VDDA
FLAG -80 304 0
SYMBOL voltage -448 144 R0
WINDOW 0 30 80 Left 2
WINDOW 3 18 -5 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 2n 2n 5u 10u)
SYMBOL voltage -288 176 R0
WINDOW 0 20 108 Left 2
WINDOW 3 39 40 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(5 0 0 2n 2n 5u 10u)
SYMBOL voltage -80 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 32 90 Left 2
SYMATTR Value 5
SYMATTR InstName V3
SYMBOL voltage 688 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V5
SYMATTR Value 12
SYMBOL cap 576 304 R0
SYMATTR InstName C2
SYMATTR Value 2n
SYMBOL voltage 688 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 12
SYMBOL cap 576 96 R0
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL ADuM7223C 224 112 R0
SYMATTR InstName U1
TEXT 64 440 Left 2 !.tran 50u
* Z:\tmp\asc_dec_bjh7r6w2\144e3557fa56_AD8613_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R2 OUT N001 10K
V2 -V 0 -2.5
XU1 IN N001 +V -V OUT AD8613 ;pnba In+)In-)V+)V-)OUT
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8613.asy)
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL Opamps\\AD8613 576 -1168 R0
SYMATTR InstName U1
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
* Z:\home\khalils\Downloads\files\data\raw_asc\076e083f7095_Q4.asc
* Generated by LTspice 26.0.1 for Windows.
Vds N001 0 1.8
Vgs N002 0 {Vgs}
M1 N001 N002 0 0 nch_tt l=10u w=15u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
.dc Vds 0 1.8 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 624 -64 352 -64
WIRE 352 16 352 -64
WIRE 624 32 624 -64
WIRE 304 96 96 96
WIRE 96 144 96 96
WIRE 96 352 96 224
WIRE 352 352 352 112
WIRE 352 352 96 352
WIRE 624 352 624 112
WIRE 624 352 352 352
WIRE 352 384 352 352
SYMBOL nmos 304 16 R0
SYMATTR InstName M1
SYMATTR Value nch_tt
SYMATTR Value2 l=10u w=15u
SYMBOL voltage 96 128 R0
SYMATTR InstName Vgs
SYMATTR Value {Vgs}
SYMBOL voltage 624 16 R0
SYMATTR InstName Vds
SYMATTR Value 1.8
FLAG 352 384 0
TEXT -200 80 Left 2 !.include TSMC180.lib
TEXT -416 128 Left 2 !.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
TEXT -184 168 Left 2 !.dc Vds 0 1.8 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\614e972e4358_DivMod.asc
* Generated by LTspice 26.0.1 for Windows.
B1 INT_IN 0 V=ROUND(V(IN))
B2 DIV 0 V=INT(V(INT_IN)/{BASE})
B3 MOD 0 V=ROUND(V(INT_IN)-{BASE}*V(DIV))
.param BASE=2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2360 1444
WIRE 944 -80 848 -80
WIRE 848 -16 848 -80
WIRE 848 96 848 64
WIRE 464 160 272 160
WIRE 608 208 544 208
WIRE 656 208 608 208
WIRE 960 208 848 208
WIRE 544 240 544 208
WIRE 848 272 848 208
WIRE 544 368 544 320
WIRE 848 384 848 352
IOPIN 960 208 Out
IOPIN 272 160 In
IOPIN 944 -80 Out
SYMBOL bv 848 256 R0
SYMATTR InstName B2
SYMATTR Value V=INT(V(INT_IN)/{BASE})
SYMBOL bv 544 224 R0
SYMATTR InstName B1
SYMATTR Value V=ROUND(V(IN))
SYMBOL bv 848 -32 R0
SYMATTR InstName B3
SYMATTR Value V=ROUND(V(INT_IN)-{BASE}*V(DIV))
FLAG 960 208 DIV
FLAG 272 160 IN
FLAG 944 -80 MOD
FLAG 544 368 0
FLAG 608 208 INT_IN
FLAG 848 384 0
FLAG 848 96 0
TEXT 248 320 Left 2 !.param BASE=2
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7170-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7170-3.0.asy)
C2 N001 0 1n
C1 OUT 0 4.7 Rser=1.5m
XU1 IN OUT IN N001 OUT 0 ADM7170-3.0 ;pnba Vin)Sense)EN)SS)Vout)GND
V1 IN 0 3.5
Rload OUT 0 7.5
.tran 5m startup
.lib ADM7170-3.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
SYMBOL ADM7170-3.0 224 128 R0
SYMATTR InstName U1
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 7.5
SYMBOL cap 80 240 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1.5m
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.5
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
TEXT 376 264 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1617-1.asc
* Generated by LTspice 26.0.1 for Windows.
C2 0 OUT 4.7 Rser=0.02
D1 N002 0 MBR0530L
R1 N003 0 24.9K
R2 OUT N003 150K
V1 IN 0 3.3
C3 N001 N002 1
L1 OUT N002 22 Rser=0.6
L2 IN N001 22 Rser=0.6
XU1 N001 0 N003 IN IN LT1617-1 ;pnba SW)GND)NFB)_SHDN)Vin
Rload OUT 0 2K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
K1 L1 L2 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1617-1.asy)
.lib LT1617-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1544 896
WIRE 400 480 304 480
WIRE 512 480 400 480
WIRE 560 480 512 480
WIRE 672 480 640 480
WIRE 704 480 672 480
WIRE 816 480 768 480
WIRE 880 480 816 480
WIRE 1008 480 960 480
WIRE 1120 480 1008 480
WIRE 1216 480 1120 480
WIRE 304 496 304 480
WIRE 816 496 816 480
WIRE 1120 496 1120 480
WIRE 1216 496 1216 480
WIRE 1008 544 1008 480
WIRE 512 560 512 480
WIRE 672 560 672 480
WIRE 816 576 816 560
WIRE 304 592 304 576
WIRE 1120 592 1120 560
WIRE 1216 592 1216 576
WIRE 400 656 400 480
WIRE 432 656 400 656
WIRE 1008 656 1008 624
WIRE 1008 656 752 656
WIRE 1008 672 1008 656
WIRE 592 768 592 752
WIRE 1008 768 1008 752
FLAG 304 592 0
FLAG 592 768 0
FLAG 1216 592 0
FLAG 1120 592 0
FLAG 1008 768 0
FLAG 816 576 0
FLAG 1216 480 OUT
FLAG 304 480 IN
SYMBOL POLCAP 1104 560 M180
WINDOW 0 24 57 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=0.02
SYMBOL SCHOTTKY 800 496 R0
SYMATTR InstName D1
SYMATTR Value MBR0530L
SYMBOL RES 992 656 R0
SYMATTR InstName R1
SYMATTR Value 24.9K
SYMBOL RES 992 528 R0
SYMATTR InstName R2
SYMATTR Value 150K
SYMBOL VOLTAGE 304 480 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL polcap 704 464 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL ind2 976 496 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 22
SYMATTR SpiceLine Rser=0.6
SYMBOL ind2 544 496 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 22
SYMATTR SpiceLine Rser=0.6
SYMBOL PowerProducts\\LT1617-1 592 656 R0
SYMATTR InstName U1
SYMBOL RES 1200 480 R0
SYMATTR InstName Rload
SYMATTR Value 2K
TEXT 768 768 Left 2 !.tran 5m startup
TEXT 744 416 Center 2 !K1 L1 L2 1