Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1436.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1436.asy)
V1 +V 0 15
V4 N004 0 pulse(0 3.3 0 1u 1u 5m 10m)
V5 N002 0 SINE(0 10 2k)
XU1 N004 N001 N002 N003 N005 -V 0 +V ADG1436 ;pnba IN)SA)D)SB)EN)Vss)GND)Vdd
R2 N003 0 1K
R1 N001 0 1K
V2 -V 0 -15
V3 N005 0 5
.tran 30m
.lib ADG1436.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -752 -368 -800 -368
WIRE -1200 -336 -1200 -352
WIRE -800 -320 -800 -368
WIRE -1056 -256 -1072 -256
WIRE -896 -256 -976 -256
WIRE -1200 -240 -1200 -256
WIRE -656 -224 -704 -224
WIRE -544 -224 -576 -224
WIRE -1008 -192 -1072 -192
WIRE -896 -192 -928 -192
WIRE -1200 -144 -1200 -160
WIRE -896 -128 -960 -128
WIRE -624 -128 -704 -128
WIRE -624 -96 -624 -128
WIRE -960 -80 -960 -128
WIRE -1200 -48 -1200 -64
WIRE -736 0 -736 -16
WIRE -624 0 -624 -16
WIRE -960 16 -960 0
WIRE -864 16 -864 -16
WIRE -832 16 -864 16
SYMBOL voltage -624 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage -1200 -352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res -912 -176 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -1200 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -672 -224 R270
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 47 41 VRight 2
WINDOW 3 -46 -22 VRight 2
SYMATTR InstName V5
SYMATTR Value SINE(0 10 2k)
SYMBOL voltage -960 -96 M0
SYMATTR InstName V4
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMBOL ADG1436 -800 -176 R0
SYMATTR InstName U1
SYMBOL res -960 -240 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1K
FLAG -1200 -48 0
FLAG -1200 -240 0
FLAG -1200 -352 +V
FLAG -1200 -160 -V
FLAG -544 -224 0
FLAG -960 16 0
FLAG -1072 -256 0
FLAG -1072 -192 0
FLAG -752 -368 +V
FLAG -736 0 0
FLAG -832 16 -V
FLAG -624 0 0
TEXT -672 -360 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\134bb5b47ea8_VoltSecondSim1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 SINE(0 12 1000 0 0 0) AC 12 0
L1 N001 0 100mH
.tran 0.002
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 48 -112 48
WIRE -112 128 -112 48
WIRE 64 128 64 48
WIRE -112 240 -112 208
WIRE 64 240 64 208
SYMBOL voltage -112 112 R0
WINDOW 3 -295 22 Left 2
WINDOW 123 -132 60 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 12 1000 0 0 0)
SYMATTR Value2 AC 12 0
SYMBOL ind 48 112 R0
SYMATTR InstName L1
SYMATTR Value 100mH
FLAG -112 240 0
FLAG 64 240 0
TEXT -408 264 Left 2 !.tran 0.002
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8374-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8374-1.asy)
+ IS=2.256906516939e-020
+ N=2.423363452597
+ RS=0.1351156839844
+ XTI=23.3518044905306
+ EG=2.5000
R2 OUT N005 100m
R1 N004 OUT 287k
D1 N005 0 XP-G3 n=5
L1 N002 OUT 10 Rser=10m Rser=72m
C2 N001 N002 22n
C1 N003 0 2.2
C3 OUT 0 2.2 Rser=5m
XU1 N003 N001 N002 NC_01 N004 OUT N005 IN 0 0 NC_02 NC_03 IN LT8374-1 ;pnba INTVcc)BST)SW)CAP)FB)ISP)ISN)VIN)SYNC/SPRD)GND)CTRL)VC)AVIN
V1 IN 0 24
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.MODEL XP-G3 D
.lib LT8374-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1540 804
WIRE -48 -96 -208 -96
WIRE -16 -96 -48 -96
WIRE 448 -96 400 -96
WIRE -208 -80 -208 -96
WIRE -48 0 -48 -96
WIRE -16 0 -48 0
WIRE 448 0 448 -32
WIRE 448 0 400 0
WIRE 512 0 448 0
WIRE 656 0 592 0
WIRE 720 0 656 0
WIRE 800 0 720 0
WIRE -208 16 -208 0
WIRE 720 16 720 0
WIRE -128 96 -144 96
WIRE -16 96 -64 96
WIRE 512 96 400 96
WIRE 656 96 656 0
WIRE 656 96 592 96
WIRE 720 96 720 80
WIRE 800 192 800 0
WIRE 800 192 400 192
WIRE 800 208 800 192
WIRE 800 288 400 288
WIRE 800 336 800 288
WIRE -16 384 -32 384
WIRE 800 416 800 400
WIRE 192 480 192 464
SYMBOL cap 432 -96 R0
SYMATTR InstName C2
SYMATTR Value 22n
SYMBOL cap 704 16 R0
SYMATTR InstName C3
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=5m
SYMBOL LED 784 336 R0
WINDOW 123 43 68 Left 2
WINDOW 3 79 37 Left 2
SYMATTR Value2 n=5
SYMATTR Value XP-G3
SYMATTR InstName D1
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 496 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 287k
SYMBOL LT8374-1 192 96 R0
SYMATTR InstName U1
SYMBOL voltage -208 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL cap -64 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL res 784 192 R0
SYMATTR InstName R2
SYMATTR Value 100m
SYMBOL ind 496 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR Value2 Rser=10m
SYMATTR SpiceLine Rser=72m
FLAG -208 16 0
FLAG -32 384 0
FLAG 192 480 0
FLAG 720 96 0
FLAG 800 416 0
FLAG -208 -96 IN
FLAG 800 0 OUT
FLAG -144 96 0
TEXT 472 496 Left 2 !.tran 1m startup
TEXT 960 304 Left 2 !.MODEL XP-G3 D\n+ IS=2.256906516939e-020\n+ N=2.423363452597\n+ RS=0.1351156839844\n+ XTI=23.3518044905306\n+ EG=2.5000
* Z:\home\khalils\Downloads\files\data\raw_asc\a736bbcb28cb_EDM_Powersupply_Lpara.asc
* Generated by LTspice 26.0.1 for Windows.
M1 drain N005 0 0 NMOS
D1 N002 N001 1N914
L1 N003 N004 6.4
V1 N005 0 PULSE(0 5 0 2n 2n 2u 20u)
R4 drain N004 10
V4 N003 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include C:\Users\joey2\Documents\3e jaar\BAP\Github\EDM_Powersupply\Library\IPW65R037C6_mosfet\SimulationModel_CoolMOS_C6_MOSFET_650V_Spice.lib
.tran 0 140u 0 10u
.model 1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
.model NMOS NMOS(vto=2.5 kp=150)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1668 680
WIRE 1184 -144 1072 -144
WIRE 1344 -144 1248 -144
WIRE 752 -112 624 -112
WIRE 864 -112 800 -112
WIRE 624 -32 624 -112
WIRE 672 -32 624 -32
WIRE 768 -32 752 -32
WIRE 864 -32 864 -112
WIRE 864 -32 848 -32
WIRE 976 -32 864 -32
WIRE 624 32 624 -32
WIRE 624 48 624 32
WIRE 976 64 976 -32
WIRE 576 128 352 128
WIRE 624 160 624 144
WIRE 352 192 352 128
WIRE 624 256 624 160
WIRE 976 256 976 144
WIRE 976 256 624 256
WIRE 976 272 976 256
WIRE 352 320 352 272
SYMBOL res 656 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10
SYMBOL nmos 576 48 R0
SYMATTR InstName M1
SYMBOL diode 1248 -160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL voltage 352 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -51 153 VLeft 2
SYMATTR Value PULSE(0 5 0 2n 2n 2u 20u)
SYMATTR InstName V1
SYMBOL voltage 976 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL ind 864 -48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 6.4u
FLAG 352 320 0
FLAG 624 32 drain
FLAG 624 160 source
FLAG 976 272 0
TEXT 416 440 Left 2 !.include C:\\Users\\joey2\\Documents\\3e jaar\\BAP\\Github\\EDM_Powersupply\\Library\\IPW65R037C6_mosfet\\SimulationModel_CoolMOS_C6_MOSFET_650V_Spice.lib
TEXT 416 400 Left 2 !.tran 0 140u 0 10u
TEXT 952 -80 Left 2 !.model 1N914 D(Is=2.52n Rs=.568 N=1.752 Cjo=4p M=.4 tt=20n Iave=200m Vpk=75 mfg=OnSemi type=silicon)
TEXT 416 480 Left 2 !.model NMOS NMOS(vto=2.5 kp=150)
* Z:\home\khalils\Downloads\files\data\raw_asc\36d387ad9e0a_Filter01Fig.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
;tran 0.001 0.005 0
XU1 0 N001 Vpp Vnn o level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Vi i 0 AC 1.
R1 N001 i {R1}
C2 o N001 {C2}
RL o 0 {RL}
V1 Vpp 0 {Vs}
R2 o N001 {R2}
V2 0 Vnn {Vs}
.param Vs=?? R1=?? R2=?? C2=?? RL=??
.ac dec 10 1 100k
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 680
WIRE 144 0 64 0
WIRE 288 0 224 0
WIRE 64 96 64 0
WIRE 144 96 64 96
WIRE 288 96 288 0
WIRE 288 96 208 96
WIRE -96 144 -160 144
WIRE 64 144 64 96
WIRE 64 144 -16 144
WIRE 512 144 464 144
WIRE 464 160 464 144
WIRE 512 176 512 144
WIRE 64 208 64 144
WIRE 128 208 64 208
WIRE 288 224 288 96
WIRE 288 224 192 224
WIRE 320 224 288 224
WIRE -160 240 -160 144
WIRE 128 240 64 240
WIRE 320 256 320 224
WIRE 64 288 64 240
WIRE 320 352 320 336
WIRE -160 368 -160 320
SYMBOL voltage 512 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vs}
SYMBOL res 240 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL cap 208 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL res 0 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL voltage 512 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vs}
SYMBOL Opamps\\UniversalOpamp2 160 224 R0
SYMATTR InstName U1
SYMBOL res 304 240 R0
SYMATTR InstName RL
SYMATTR Value {RL}
SYMBOL voltage -160 224 R0
WINDOW 3 41 76 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 45 41 Left 2
SYMATTR Value AC 1.
SYMATTR InstName Vi
FLAG 512 64 Vpp
FLAG 464 160 0
FLAG 512 256 Vnn
FLAG 320 352 0
FLAG -160 368 0
FLAG 160 192 Vpp
FLAG 160 256 Vnn
FLAG 64 288 0
FLAG 320 224 o
FLAG -160 144 i
TEXT -176 408 Left 2 !.param Vs=?? R1=?? R2=??  C2=?? RL=??
TEXT -400 -160 Left 2 !;tran 0.001 0.005 0
TEXT -104 368 Left 2 !.ac dec 10 1 100k
* Z:\home\khalils\Downloads\files\data\raw_asc\20942bb7bd63_part2_a_1.asc
* Generated by LTspice 26.0.1 for Windows.
VGS gate 0 {X}
VDS drain 0 10
M1 drain gate 0 0 NMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model nmos NMOS (kp=100u, vt0=0.5, l=0.18u, w=.36u)
.dc VDS 0 10 0.01
.step param X list 2 5 7 9 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 48 96 48
WIRE 240 48 160 48
WIRE 96 112 96 48
WIRE 240 144 240 48
WIRE -64 192 -96 192
WIRE 48 192 -64 192
WIRE -96 208 -96 192
WIRE -96 336 -96 288
WIRE 96 336 96 208
WIRE 96 336 -96 336
WIRE 176 336 96 336
WIRE 240 336 240 224
WIRE 240 336 176 336
SYMBOL nmos 48 112 R0
SYMATTR InstName M1
SYMBOL voltage 240 128 R0
SYMATTR InstName VDS
SYMATTR Value 10
SYMBOL voltage -96 192 R0
SYMATTR InstName VGS
SYMATTR Value {X}
FLAG 96 336 0
FLAG -64 192 gate
FLAG 160 48 drain
FLAG 176 336 source
TEXT -104 376 Left 2 !.model nmos NMOS (kp=100u, vt0=0.5, l=0.18u, w=.36u)
TEXT -104 408 Left 2 !.dc VDS 0 10 0.01
TEXT -104 440 Left 2 !.step param X list 2 5 7 9 10
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP150-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP150-3.0.asy)
Rload OUT 0 30
V1 IN 0 5
C1 OUT 0 1
XU1 IN 0 IN MP_01 OUT ADP150-x.x T=1.8Meg ;pnba Vin)GND)EN))Vout
.tran 500u startup
.lib ADP150-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 880 1696 880
WIRE 1984 880 1824 880
WIRE 1696 896 1696 880
WIRE 1984 896 1984 880
WIRE 1696 992 1696 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL VOLTAGE 1696 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\ADP150-3.0 1984 1024 R0
SYMATTR InstName U1
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 30
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 2256 1024 OUT
FLAG 2256 1136 0
FLAG 1696 992 0
FLAG 1696 880 IN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8017.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8017.asy)
XU1 IN N001 +V -V OUT AD8017 ;pnba 1)2)61)99)50
Vin IN 0 SINE(0 1 10K)
Rload OUT 0 10K
V2 -V 0 -2.5
R1 N001 0 10K
R2 OUT N001 10K
V1 +V 0 2.5
.tran 1m
.lib AD8017.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1240 700
WIRE -16 -1056 -32 -1056
WIRE 80 -1056 64 -1056
WIRE 96 -1056 80 -1056
WIRE 192 -1056 176 -1056
WIRE -256 -944 -256 -960
WIRE -144 -944 -144 -960
WIRE 80 -944 80 -1056
WIRE 96 -944 80 -944
WIRE 192 -928 192 -1056
WIRE 192 -928 160 -928
WIRE 320 -928 192 -928
WIRE 96 -912 -16 -912
WIRE 320 -912 320 -928
WIRE -16 -896 -16 -912
WIRE -256 -848 -256 -864
WIRE -144 -848 -144 -864
WIRE 320 -816 320 -832
WIRE -16 -800 -16 -816
SYMBOL res 192 -1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 304 -928 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage -16 -912 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage -256 -960 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage -144 -960 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL AD8017 128 -992 R0
SYMATTR InstName U1
SYMBOL res 80 -1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
FLAG -256 -960 +V
FLAG -256 -848 0
FLAG -16 -800 0
FLAG 320 -928 OUT
FLAG -16 -912 IN
FLAG 128 -960 +V
FLAG -144 -960 -V
FLAG 128 -896 -V
FLAG -32 -1056 0
FLAG 320 -816 0
FLAG -144 -848 0
TEXT 336 -720 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1043.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1013.asy)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1043.asy)
V2 -V 0 -5
C1 N003 0 1000p
C2 S2A 0 .1
R2 N001 S2A 10K
XU2 0 N001 +V -V OUT LT1013 ;pnba In+)In-)V+)V-)OUT
C4 OUT N001 .1
V3 S1A 0 SINE(0 10m 100)
V1 +V 0 5
C3 N002 N004 .1
R1 OUT N001 10K
XU1 S1A S2A N002 0 0 N004 N003 +V -V LTC1043 ;pnba S1A)S2A)Ca+)S3A)S4A)Ca-)Cosc)Vdd)Vss
.tran 1 startup
.lib LT1013.sub
.lib LTC1043.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 896 680
WIRE 560 0 544 0
WIRE 656 0 624 0
WIRE 192 96 192 80
WIRE 384 96 352 96
WIRE 416 96 384 96
WIRE 448 96 416 96
WIRE 544 96 544 0
WIRE 544 96 528 96
WIRE 560 96 544 96
WIRE 656 96 656 0
WIRE 656 96 640 96
WIRE 416 144 416 96
WIRE 0 160 -176 160
WIRE 64 160 0 160
WIRE 352 160 352 96
WIRE 352 160 320 160
WIRE -176 176 -176 160
WIRE -400 208 -400 192
WIRE -304 208 -304 192
WIRE 592 208 592 192
WIRE 64 224 48 224
WIRE 352 224 320 224
WIRE 544 224 544 96
WIRE 560 224 544 224
WIRE 656 240 656 96
WIRE 656 240 624 240
WIRE 688 240 656 240
WIRE 352 256 352 224
WIRE 416 256 416 208
WIRE 416 256 352 256
WIRE 496 256 416 256
WIRE 560 256 496 256
WIRE -176 272 -176 256
WIRE 496 272 496 256
WIRE 352 288 320 288
WIRE 592 288 592 272
WIRE -400 304 -400 288
WIRE -304 304 -304 288
WIRE -16 352 -32 352
WIRE 64 352 48 352
WIRE 352 352 320 352
WIRE 192 432 192 416
SYMBOL voltage -400 192 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 656 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL cap 336 288 R0
WINDOW 3 25 57 Left 2
SYMATTR Value .1
SYMATTR InstName C3
SYMBOL voltage -176 160 R0
WINDOW 3 16 98 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value SINE(0 10m 100)
SYMATTR InstName V3
SYMBOL LTC1043 192 256 R0
SYMATTR InstName U1
SYMBOL cap 48 336 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1000p
SYMBOL cap 624 -16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value .1
SYMBOL opamps\\LT1013 592 176 R0
SYMATTR InstName U2
SYMBOL cap 400 144 R0
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL voltage -304 192 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 544 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG -32 352 0
FLAG -304 304 0
FLAG -304 192 +V
FLAG -400 304 0
FLAG -400 192 -V
FLAG 592 192 +V
FLAG 192 80 +V
FLAG 592 288 -V
FLAG 192 432 -V
FLAG -176 272 0
FLAG 48 224 0
FLAG 496 272 0
FLAG 0 160 S1A
FLAG 384 96 S2A
FLAG 688 240 OUT
TEXT 120 504 Left 2 !.tran 1 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0ea86558b792_up_5bitcounter-clamp.asc
* Generated by LTspice 26.0.1 for Windows.
A1 clk_buf clr 0 0 0 B[0] 0 0 counter cycles=2*{k}
A2 clk_buf clr 0 0 0 B[1] 0 0 counter cycles=4*{k}
A3 clk_buf clr 0 0 0 B[2] 0 0 counter cycles=8*{k}
A4 clk_buf clr 0 0 0 B[3] 0 0 counter cycles=16*{k}
A5 clk_buf clr 0 0 0 B[4] 0 0 counter cycles=32*{k}
A6 clk N001 0 0 0 0 clk_buf 0 AND
A7 B[0] B[1] B[2] B[3] B[4] N001 0 0 AND
.param k=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -160 -160 -208 -160
WIRE -160 -144 -160 -160
WIRE -144 -144 -160 -144
WIRE -144 -128 -208 -128
WIRE -144 -112 -192 -112
WIRE -192 -96 -192 -112
WIRE -192 -96 -208 -96
WIRE -144 -96 -176 -96
WIRE -32 -96 -80 -96
WIRE -144 -80 -160 -80
WIRE -32 -80 -48 -80
WIRE -176 -64 -176 -96
WIRE -176 -64 -208 -64
WIRE -48 -64 -48 -80
WIRE -32 -64 -48 -64
WIRE -48 -48 -48 -64
WIRE -32 -48 -48 -48
WIRE -160 -32 -160 -80
WIRE -160 -32 -208 -32
WIRE -48 -32 -48 -48
WIRE -32 -32 -48 -32
WIRE -16 -32 -16 -48
WIRE -16 -32 -32 -32
FLAG 208 304 0
FLAG 304 224 0
FLAG 320 272 B[0]
IOPIN 320 272 Out
FLAG 208 144 0
FLAG 304 64 0
FLAG 320 112 B[1]
IOPIN 320 112 Out
FLAG 208 -16 0
FLAG -32 -112 clk
IOPIN -32 -112 In
FLAG 304 -96 0
FLAG 320 -48 B[2]
IOPIN 320 -48 Out
FLAG -48 304 0
FLAG 48 224 0
FLAG 64 272 B[3]
IOPIN 64 272 Out
FLAG -48 144 0
FLAG 48 64 0
FLAG 64 112 B[4]
IOPIN 64 112 Out
FLAG -48 272 clr
IOPIN -48 272 In
FLAG 208 -48 clr
IOPIN 208 -48 In
FLAG 208 112 clr
IOPIN 208 112 In
FLAG 208 272 clr
IOPIN 208 272 In
FLAG -48 112 clr
IOPIN -48 112 In
FLAG -48 64 clk_buf
FLAG -48 224 clk_buf
FLAG 208 64 clk_buf
FLAG 208 -96 clk_buf
FLAG 208 224 clk_buf
FLAG -32 -32 0
FLAG 32 -64 0
FLAG 32 -96 clk_buf
FLAG -128 -80 0
FLAG -80 -128 0
FLAG -208 -96 B[2]
IOPIN -208 -96 Out
FLAG -208 -32 B[4]
IOPIN -208 -32 Out
FLAG -208 -64 B[3]
IOPIN -208 -64 Out
FLAG -208 -128 B[1]
IOPIN -208 -128 Out
FLAG -208 -160 B[0]
IOPIN -208 -160 Out
SYMBOL Digital\\srflop 256 176 R0
WINDOW 3 -25 142 Left 2
SYMATTR Value cycles=2*{k}
SYMATTR InstName A1
SYMATTR SpiceModel counter
SYMBOL Digital\\srflop 256 16 R0
WINDOW 3 -25 142 Left 2
SYMATTR Value cycles=4*{k}
SYMATTR InstName A2
SYMATTR SpiceModel counter
SYMBOL Digital\\srflop 256 -144 R0
WINDOW 3 -25 142 Left 2
SYMATTR Value cycles=8*{k}
SYMATTR InstName A3
SYMATTR SpiceModel counter
SYMBOL Digital\\srflop 0 176 R0
WINDOW 3 -25 142 Left 2
SYMATTR Value cycles=16*{k}
SYMATTR InstName A4
SYMATTR SpiceModel counter
SYMBOL Digital\\srflop 0 16 R0
WINDOW 3 -25 142 Left 2
SYMATTR Value cycles=32*{k}
SYMATTR InstName A5
SYMATTR SpiceModel counter
SYMBOL Digital\\and 0 -144 R0
SYMATTR InstName A6
SYMBOL Digital\\and -112 -176 R0
SYMATTR InstName A7
TEXT 48 -160 Left 2 !.param k=1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1261LCS8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1261LCS8.asy)
V1 IN 0 5
C2 OUT 0 3.3
R1 IN N003 3.3K
C1 N002 N004 .1
Rload OUT 0 1K
XU1 IN N002 N004 0 0 OUT N003 N001 LTC1261LCS8 ;pnba Vcc)C1+)C1-)GND)ADJ)OUT)REG)SHDN
.tran 1m
.lib LTC1261LCS8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2372 2180
WIRE 1680 1056 1536 1056
WIRE 2048 1056 1680 1056
WIRE 1536 1072 1536 1056
WIRE 2048 1088 2048 1056
WIRE 1680 1136 1680 1056
WIRE 1712 1136 1680 1136
WIRE 2016 1136 2000 1136
WIRE 1536 1168 1536 1152
WIRE 1712 1200 1648 1200
WIRE 2048 1200 2048 1168
WIRE 2048 1200 2000 1200
WIRE 1712 1264 1648 1264
WIRE 2096 1264 2000 1264
WIRE 2192 1264 2096 1264
WIRE 2096 1280 2096 1264
WIRE 2192 1280 2192 1264
WIRE 1712 1328 1696 1328
WIRE 2032 1328 2000 1328
WIRE 2096 1376 2096 1344
WIRE 2192 1376 2192 1360
SYMBOL VOLTAGE 1536 1056 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL RES 2176 1264 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL res 2032 1072 R0
SYMATTR InstName R1
SYMATTR Value 3.3K
SYMBOL cap 1632 1200 R0
WINDOW 0 33 18 Left 2
WINDOW 3 30 49 Left 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL cap 2080 1280 R0
SYMATTR InstName C2
SYMATTR Value 3.3
SYMBOL PowerProducts\\LTC1261LCS8 1856 1232 R0
SYMATTR InstName U1
FLAG 1696 1328 0
FLAG 1536 1168 0
FLAG 2096 1376 0
FLAG 2192 1376 0
FLAG 2032 1328 0
FLAG 1536 1056 IN
FLAG 2192 1264 OUT
TEXT 2152 1432 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\279d9e2ec2e7_class_phi2_paper.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N004 0 25
L3 N002 N003 357n
C3 0 N002 290p
V2 N001 0 24
V1 0 N005 PULSE(0 10 0 1n 1n 11n 36n)
C1 N004 N003 96.5p
S1 N002 0 0 N005 MYSW
D1 0 N002 D_ideal
L1 N001 N002 62.7n
C2 0 N006 95.7p
L2 N002 N006 80n
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model MYSW SW(Ron=30m Roff=1Meg Vt=5 Vh=-.4)
.tran 0 50u 49u
.model D_ideal D(Ron=0.1n Roff=1G Vfwd=0.7)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 192 64 112 64
WIRE 320 64 272 64
WIRE 400 64 320 64
WIRE 560 64 400 64
WIRE 640 64 560 64
WIRE 736 64 640 64
WIRE 848 64 816 64
WIRE 928 64 912 64
WIRE 112 80 112 64
WIRE 640 80 640 64
WIRE 928 128 928 64
WIRE 112 176 112 160
WIRE 320 176 320 64
WIRE 400 176 400 64
WIRE 272 192 208 192
WIRE 560 192 560 64
WIRE 640 192 640 160
WIRE 224 272 208 272
WIRE 272 272 272 240
WIRE 272 272 224 272
WIRE 320 272 320 256
WIRE 400 272 400 240
WIRE 560 272 560 256
WIRE 640 272 640 256
WIRE 928 272 928 208
WIRE 224 288 224 272
SYMBOL ind 176 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 62.7n
SYMBOL res 912 112 R0
SYMATTR InstName R1
SYMATTR Value 25
SYMBOL ind 624 64 R0
SYMATTR InstName L2
SYMATTR Value 80n
SYMBOL ind 720 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 357n
SYMBOL voltage 112 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 24
SYMBOL cap 912 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 96.5p
SYMBOL cap 656 256 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value 95.7p
SYMBOL voltage 208 288 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 10 0 1n 1n 11n 36n)
SYMBOL diode 416 240 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value D_ideal
SYMBOL sw 320 160 R0
WINDOW 0 -36 4 Left 2
WINDOW 3 -18 142 Left 2
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL cap 576 256 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value 290p
FLAG 320 272 0
FLAG 560 272 0
FLAG 640 272 0
FLAG 112 176 0
FLAG 928 272 0
FLAG 224 288 0
FLAG 400 272 0
TEXT 192 352 Left 2 !.model MYSW SW(Ron=30m Roff=1Meg Vt=5 Vh=-.4)
TEXT -188 372 Left 2 !.tran 0 50u 49u
TEXT 200 384 Left 2 !.model D_ideal D(Ron=0.1n Roff=1G Vfwd=0.7)