Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1818.asc
* Generated by LTspice 26.0.1 for Windows.
* 80MHz, 20dB Gain Block
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1818.asy)
XU2 N003 N001 OUT +V -V LT1818 ;pnba IN+)IN-)OUT)VCC)VEE
R3 OUT N001 432
XU1 IN N002 N003 +V -V LT1818 ;pnba IN+)IN-)OUT)VCC)VEE
V2 -V 0 -5
R4 N001 0 200
R2 N002 0 200
V1 +V 0 5
R1 N003 N002 432
V3 IN 0 AC 1
.ac oct 10 100K 500Meg
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 240 32 224 32
WIRE 336 32 320 32
WIRE 352 32 336 32
WIRE 464 32 432 32
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -160 160 -160 144
WIRE -64 160 -64 144
WIRE 400 192 400 176
WIRE 192 208 192 192
WIRE 336 208 336 32
WIRE 368 208 336 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 464 224 464 32
WIRE 464 224 432 224
WIRE 496 224 464 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 368 240 256 240
WIRE -160 256 -160 240
WIRE -64 256 -64 240
WIRE 160 256 32 256
WIRE 32 272 32 256
WIRE 400 272 400 256
WIRE 192 288 192 272
WIRE 32 368 32 352
SYMBOL voltage -160 144 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 336 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL opamps\\LT1818 192 240 R0
SYMATTR InstName U1
SYMBOL voltage 32 256 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL opamps\\LT1818 400 224 R0
SYMATTR InstName U2
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 432
SYMBOL res 448 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 432
SYMBOL voltage -64 144 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -64 256 0
FLAG 192 192 +V
FLAG -64 144 +V
FLAG 192 288 -V
FLAG -160 256 0
FLAG -160 144 -V
FLAG 16 96 0
FLAG 32 368 0
FLAG 400 176 +V
FLAG 400 272 -V
FLAG 224 32 0
FLAG 496 224 OUT
FLAG 32 256 IN
TEXT 232 344 Left 2 !.ac oct 10 100K 500Meg
TEXT 264 -32 Bottom 2 ;80MHz, 20dB Gain Block
* Z:\home\khalils\Downloads\files\data\raw_asc\5f59fa59019a_3_jikken_ic_ib.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 C B 0 0 2SC1815-Y
V1 C 0 10V
I1 0 B 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc oct I1 1p 400u 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 592 -112 272 -112
WIRE 272 128 272 -112
WIRE 272 144 272 128
WIRE 192 192 -96 192
WIRE 208 192 192 192
WIRE 592 192 592 -112
WIRE 272 256 272 240
WIRE -96 272 -96 192
WIRE -96 496 -96 352
WIRE 272 496 272 256
WIRE 592 496 592 272
FLAG -96 496 0
FLAG 272 496 0
FLAG 592 496 0
FLAG 272 256 E
FLAG 272 128 C
FLAG 192 192 B
SYMBOL npn 208 144 R0
WINDOW 0 65 35 Left 2
SYMATTR InstName Q1
SYMATTR Value 2SC1815-Y
SYMBOL voltage 592 176 R0
SYMATTR InstName V1
SYMATTR Value 10V
SYMBOL current -96 352 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 0
TEXT -80 -24 Left 2 !.dc oct I1 1p 400u 100
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1534.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSwitch shown for a logic 0 input\nQinj not included in the model\nOnly one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1534.asy)
V4 vIN 0 PULSE(0 1.8 0 20n 20n 10u 20u)
C1 vD 0 36p
V6 vSB 0 -8
V1 +V 0 5
V5 vSA 0 2.5
R1 vD 0 301
V2 -V 0 -8
XU1 vIN vSA vD vSB 0 -V 0 +V ADG1534 ;pnba IN)SA)D)SB)EN)Vss)GND)Vdd
.tran 120u
.lib ADG1534.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -800 -320 -800 -352
WIRE -1488 -256 -1488 -272
WIRE -1376 -256 -1376 -272
WIRE -928 -256 -960 -256
WIRE -896 -256 -928 -256
WIRE -672 -224 -704 -224
WIRE -640 -224 -672 -224
WIRE -560 -224 -640 -224
WIRE -928 -192 -1040 -192
WIRE -896 -192 -928 -192
WIRE -640 -192 -640 -224
WIRE -560 -176 -560 -224
WIRE -1488 -160 -1488 -176
WIRE -1376 -160 -1376 -176
WIRE -1200 -128 -1248 -128
WIRE -928 -128 -1120 -128
WIRE -896 -128 -928 -128
WIRE -640 -96 -640 -112
WIRE -560 -96 -560 -112
WIRE -896 -64 -928 -64
WIRE -864 16 -864 -16
WIRE -736 16 -736 -16
SYMBOL voltage -1104 -128 M270
WINDOW 3 -45 209 VLeft 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 44 74 VLeft 2
SYMATTR Value PULSE(0 1.8 0 20n 20n 10u 20u)
SYMATTR InstName V4
SYMBOL voltage -1024 -192 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value -8
SYMBOL res -656 -208 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -944 -256 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 2.5
SYMBOL ADG1534 -800 -176 R0
SYMATTR InstName U1
SYMBOL voltage -1376 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -8
SYMBOL cap -576 -176 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -1488 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -1376 -160 0
FLAG -1488 -160 0
FLAG -1488 -272 +V
FLAG -1376 -272 -V
FLAG -1248 -128 0
FLAG -1040 -256 0
FLAG -1120 -192 0
FLAG -800 -352 +V
FLAG -736 16 0
FLAG -864 16 -V
FLAG -640 -96 0
FLAG -560 -96 0
FLAG -928 -64 0
FLAG -928 -256 vSA
FLAG -928 -192 vSB
FLAG -928 -128 vIN
FLAG -672 -224 vD
TEXT -1496 -72 Left 2 !.tran 120u
TEXT -1496 -480 Left 2 ;Notes:\nSwitch shown for a logic 0 input\nQinj not included in the model\nOnly one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\3d080408f584_invertor.asc
* Generated by LTspice 26.0.1 for Windows.
M1 d g 0 0 NMOS l=32e-9 w=320e-9 ad=51200e-18 as=51200e-18 pd=960e-9 ps=960e-9
V1 N001 0 1
M2 N001 g d N001 PMOS l=32e-9 w=640e-9 ad=51200e-18 as=51200e-18 pd=960e-9 ps=960e-9
V2 g 0 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V2 0 1 0.001
.inc 32nm_bulk.pm
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 680
WIRE 240 -80 192 -80
WIRE 592 -80 240 -80
WIRE 192 -32 192 -80
WIRE 240 16 240 -80
WIRE 240 16 192 16
WIRE 144 48 112 48
WIRE 592 48 592 -80
WIRE 192 112 192 64
WIRE 192 144 192 112
WIRE 240 192 192 192
WIRE 96 224 0 224
WIRE 112 224 112 48
WIRE 112 224 96 224
WIRE 144 224 112 224
WIRE 192 304 192 240
WIRE 192 304 0 304
WIRE 240 304 240 192
WIRE 240 304 192 304
WIRE 336 304 240 304
WIRE 592 304 592 128
WIRE 592 304 336 304
WIRE 336 352 336 304
SYMBOL voltage 592 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMBOL voltage 0 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -315 130 Left 2
SYMATTR Value 1
SYMATTR InstName V2
SYMBOL nmos4 144 144 R0
SYMATTR InstName M1
SYMATTR Value2 l=32e-9 w=320e-9 ad=51200e-18 as=51200e-18 pd=960e-9 ps=960e-9
SYMBOL pmos4 144 -32 R0
SYMATTR InstName M2
SYMATTR Value2 l=32e-9 w=640e-9 ad=51200e-18 as=51200e-18 pd=960e-9 ps=960e-9
FLAG 336 352 0
FLAG 192 112 d
FLAG 96 224 g
TEXT -320 384 Left 2 !.dc V2 0 1 0.001
TEXT -632 0 Left 2 !.inc 32nm_bulk.pm
* Z:\home\khalils\Downloads\files\data\raw_asc\0544a8b8304e_calculs_amplification_2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
V4 N004 0 8
R3 N006 N005 22k
V3 0 N007 10
V5 N003 0 SINE(1.024 1.024 1)
R4 N005 0 8350
R1 N001 N003 1k
V1 N006 0 3.3
XU3 N005 N001 N004 N007 N002 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N002 N001 8k
.tran 10
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 680
WIRE 368 -32 320 -32
WIRE 592 -32 448 -32
WIRE 144 48 144 -64
WIRE 192 48 144 48
WIRE 320 48 320 -32
WIRE 320 48 272 48
WIRE 912 80 432 80
WIRE 432 112 432 80
WIRE 320 128 320 48
WIRE 400 128 320 128
WIRE 592 144 592 -32
WIRE 592 144 464 144
WIRE 912 144 912 80
WIRE 400 160 224 160
WIRE 48 192 -128 192
WIRE 224 192 224 160
WIRE 224 192 128 192
WIRE -128 208 -128 192
WIRE 224 224 224 192
WIRE 912 272 912 224
WIRE 912 272 832 272
WIRE 832 288 832 272
WIRE 912 320 912 272
WIRE 432 464 432 176
WIRE 912 464 912 400
WIRE 912 464 432 464
SYMBOL voltage 912 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL res 208 208 R0
SYMATTR InstName R4
SYMATTR Value 8350
SYMBOL res 288 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 144 -48 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value SINE(1.024 1.024 1)
SYMBOL res 464 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 8k
SYMBOL OpAmps\\UniversalOpAmp 432 144 R0
SYMATTR InstName U3
SYMBOL res 32 208 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 22k
SYMBOL voltage 912 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 8
SYMBOL voltage -128 192 R0
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 224 304 0
FLAG -128 288 0
FLAG 144 -144 0
FLAG 832 288 0
TEXT -160 328 Left 2 !.tran 10
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG721.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG721.asy)
V4 N003 0 PULSE(0 3 0 10n 10n 980n 2u)
XU2 N003 N002 N001 0 +V ADG721 ;pnba IN)D)S)GND)Vdd
C1 N002 0 35p
VS N001 0 3
V1 +V 0 5
R1 N002 0 300
.tran 10u
.lib ADG721.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -240 -16 -288 -16
WIRE 0 -16 -48 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -240 48 -368 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V4
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL ADG721 -144 32 R0
SYMATTR InstName U2
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
TEXT -536 200 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\5b7589bca825_BT-CE-IN.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 be 0 0 BC547B
V1 be 0 0
V2 N001 0 {Uce}
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 1V
.meas dc M1 find V(be)*1000 when Ib(Q1)=1mA
.meas dc M2 find V(be)*1000 when Ib(Q1)=3mA
.step param Uce list 5V 20V
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 32 224 32
WIRE 224 64 224 32
WIRE 368 96 368 32
WIRE 144 112 32 112
WIRE 160 112 144 112
WIRE 32 128 32 112
WIRE 32 224 32 208
WIRE 224 224 224 160
WIRE 368 224 368 176
SYMBOL npn 160 64 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL voltage 368 80 R0
WINDOW 3 44 63 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 34 24 Left 2
SYMATTR Value {Uce}
SYMATTR InstName V2
SYMBOL voltage 32 112 R0
WINDOW 3 24 32 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 35 30 Left 2
SYMATTR Value 0
SYMATTR InstName V1
FLAG 224 224 0
FLAG 32 224 0
FLAG 368 224 0
FLAG 144 112 be
TEXT 16 272 Left 2 !.dc V1 0 1V
TEXT 16 328 Left 2 !.meas dc M1 find V(be)*1000 when Ib(Q1)=1mA\n.meas dc M2 find V(be)*1000 when Ib(Q1)=3mA
TEXT 16 296 Left 2 !.step param Uce list 5V 20V
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3422.asc
* Generated by LTspice 26.0.1 for Windows.
R4 N002 0 549K
R5 OUT N002 931K
C3 OUT 0 22
R6 OUT 0 6.6
L1 IN N001 4.7
V1 IN 0 2
XU1 N001 IN N006 N003 IN N002 N004 N005 MP_01 OUT 0 LTC3422 ;pnba SW)Vin)Burst)SS)_SHDN)FB)Vc)Rt))Vout)GND
C5 N003 0 .01
R9 N005 0 28K
C1 N004 0 1000p Rser=15K Cpar=22p
C7 N006 0 2200p
R1 N006 0 301K
.tran 4m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3422.asy)
.lib LTC3422.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1584 2632
WIRE -512 224 -560 224
WIRE -384 224 -432 224
WIRE -384 272 -384 224
WIRE -560 336 -560 224
WIRE -560 336 -672 336
WIRE -528 336 -560 336
WIRE 0 336 -240 336
WIRE 112 336 0 336
WIRE 208 336 112 336
WIRE -672 352 -672 336
WIRE 112 352 112 336
WIRE 208 352 208 336
WIRE -560 432 -560 336
WIRE -528 432 -560 432
WIRE 0 432 0 416
WIRE 0 432 -240 432
WIRE -672 448 -672 432
WIRE 0 448 0 432
WIRE 112 448 112 416
WIRE 208 448 208 432
WIRE -608 528 -640 528
WIRE -528 528 -544 528
WIRE -144 528 -240 528
WIRE -64 528 -80 528
WIRE 0 544 0 528
WIRE -624 624 -640 624
WIRE -528 624 -544 624
WIRE -176 624 -240 624
WIRE -80 624 -176 624
WIRE -176 640 -176 624
WIRE -80 656 -80 624
WIRE -384 704 -384 688
WIRE -176 736 -176 720
WIRE -80 736 -80 720
FLAG 0 544 0
FLAG 112 448 0
FLAG 208 448 0
FLAG -672 448 0
FLAG -640 528 0
FLAG -640 624 0
FLAG -384 704 0
FLAG -64 528 0
FLAG -176 736 0
FLAG -80 736 0
FLAG 208 336 OUT
FLAG -672 336 IN
SYMBOL res -16 432 R0
SYMATTR InstName R4
SYMATTR Value 549K
SYMBOL res -16 320 R0
SYMATTR InstName R5
SYMATTR Value 931K
SYMBOL cap 96 352 R0
SYMATTR InstName C3
SYMATTR Value 22
SYMBOL res 192 336 R0
SYMATTR InstName R6
SYMATTR Value 6.6
SYMBOL ind -528 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL voltage -672 336 R0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL LTC3422 -384 480 R0
SYMATTR InstName U1
SYMBOL cap -544 512 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value .01
SYMBOL res -528 608 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 28K
SYMBOL cap -144 544 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
WINDOW 39 -31 35 VBottom 2
SYMATTR InstName C1
SYMATTR Value 1000p
SYMATTR SpiceLine Rser=15K Cpar=22p
SYMBOL cap -96 656 R0
SYMATTR InstName C7
SYMATTR Value 2200p
SYMBOL res -192 624 R0
WINDOW 3 29 88 Left 2
SYMATTR Value 301K
SYMATTR InstName R1
TEXT 16 640 Left 2 !.tran 4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0250f72b62db_Fig6_13.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1)
VDS N001 0 5
VGS N003 0 0
M1 N001 N003 0 N002 N_1u L=1u W=10u
VSB 0 N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VGS 0 2 1m VSB 0 5 1
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 352 208 352 192
WIRE 352 304 352 288
WIRE 400 192 352 192
WIRE 448 112 448 80
WIRE 448 272 448 208
WIRE 704 160 448 160
WIRE 704 272 704 240
WIRE 848 80 448 80
WIRE 848 112 848 80
WIRE 848 224 848 192
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 L=1u W=10u
SYMBOL voltage 848 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VDS
SYMATTR Value 5
SYMBOL voltage 704 256 R180
WINDOW 0 -37 57 Right 0
WINDOW 3 -49 27 Invisible 0
SYMATTR InstName VSB
SYMATTR Value 0
SYMBOL voltage 352 192 R0
WINDOW 0 -91 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VGS
SYMATTR Value 0
FLAG 352 304 0
FLAG 448 272 0
FLAG 848 224 0
FLAG 704 272 0
TEXT 448 320 Left 0 !.dc VGS 0 2 1m VSB 0 5 1
TEXT 448 344 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot Id(M1)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1706-81.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1706-81.asy)
G1 0 OUT N007 N004 100m
V7 N008 0 PULSE(0 2.4 0 1n 1n 8m 16m)
V4 N003 0 PULSE(0 2.4 0 1n 1n 1m 2m)
V2 N007 0 .8
V3 N002 0 PULSE(0 2.4 0 1n 1n .5m 1m)
XU1 N005 N006 N001 0 N004 OUT N002 N003 N008 LTC1706-81 ;pnba VID2)VID3)Vcc)GND)FB)Sense)VID0)VID1)VID4
V6 N006 0 PULSE(0 2.4 0 1n 1n 4m 8m)
C1 OUT 0 .1
V1 N001 0 3.3
V5 N005 0 PULSE(0 2.4 0 1n 1n 2m 4m)
.tran 16m
.lib LTC1706-81.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2536 1332
WIRE 944 736 864 736
WIRE 1328 736 944 736
WIRE 864 752 864 736
WIRE 1168 784 1008 784
WIRE 1008 800 1008 784
WIRE 1168 816 1168 784
WIRE 1328 816 1328 736
WIRE 864 832 864 816
WIRE 1856 880 1392 880
WIRE 1008 896 1008 880
WIRE 1856 896 1856 880
WIRE 1744 928 1392 928
WIRE 1744 960 1744 928
WIRE 1104 976 992 976
WIRE 1632 976 1392 976
WIRE 944 992 944 736
WIRE 1856 992 1856 976
WIRE 992 1008 992 976
WIRE 1632 1008 1632 976
WIRE 1536 1024 1392 1024
WIRE 1536 1056 1536 1024
WIRE 1744 1056 1744 1040
WIRE 992 1072 992 1056
WIRE 1440 1072 1392 1072
WIRE 1632 1104 1632 1088
WIRE 1440 1120 1440 1072
WIRE 1248 1136 1248 1120
WIRE 1536 1152 1536 1136
WIRE 944 1168 944 1072
WIRE 992 1168 992 1152
WIRE 1440 1216 1440 1200
SYMBOL voltage 1440 1104 R0
SYMATTR InstName V7
SYMATTR Value PULSE(0 2.4 0 1n 1n 8m 16m)
SYMBOL voltage 1536 1040 R0
SYMATTR InstName V6
SYMATTR Value PULSE(0 2.4 0 1n 1n 4m 8m)
SYMBOL voltage 1744 944 R0
SYMATTR InstName V4
SYMATTR Value PULSE(0 2.4 0 1n 1n 1m 2m)
SYMBOL voltage 1632 992 R0
SYMATTR InstName V5
SYMATTR Value PULSE(0 2.4 0 1n 1n 2m 4m)
SYMBOL PowerProducts\\LTC1706-81 1248 976 R0
SYMATTR InstName U1
SYMBOL g2 944 976 M0
SYMATTR InstName G1
SYMATTR Value 100m
SYMBOL voltage 992 1056 R0
SYMATTR InstName V2
SYMATTR Value .8
SYMBOL voltage 1856 880 R0
SYMATTR InstName V3
SYMATTR Value PULSE(0 2.4 0 1n 1n .5m 1m)
SYMBOL voltage 1008 784 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 848 752 R0
SYMATTR InstName C1
SYMATTR Value .1
FLAG 1008 896 0
FLAG 1248 1136 0
FLAG 992 1168 0
FLAG 944 1168 0
FLAG 1856 992 0
FLAG 1744 1056 0
FLAG 1632 1104 0
FLAG 1536 1152 0
FLAG 864 832 0
FLAG 864 736 OUT
FLAG 1440 1216 0
TEXT 1896 1192 Left 2 !.tran 16m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1219.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1219.asy)
C1 OUT 0 .1
XU1 IN OUT +V 0 OUT NC_01 LT1219 ;pnba In+)In-)V+)V-)OUT)SHDN
V3 IN 0 SINE(2.5 2.5 1K)
V1 +V 0 5
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 368 16 128 16
WIRE -160 96 -160 80
WIRE 192 96 192 80
WIRE 128 144 128 16
WIRE 160 144 128 144
WIRE 368 176 368 16
WIRE 368 176 304 176
WIRE 432 176 368 176
WIRE -160 192 -160 176
WIRE 368 192 368 176
WIRE 160 208 16 208
WIRE 16 240 16 208
WIRE 192 272 192 256
WIRE 368 272 368 256
WIRE 16 336 16 320
SYMBOL voltage 16 224 R0
SYMATTR InstName V3
SYMATTR Value SINE(2.5  2.5 1K)
SYMBOL voltage -160 80 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 352 192 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL opamps\\LT1219 192 176 R0
SYMATTR InstName U1
FLAG -160 192 0
FLAG 192 80 +V
FLAG -160 80 +V
FLAG 16 336 0
FLAG 192 272 0
FLAG 368 272 0
FLAG 432 176 OUT
FLAG 16 208 IN
TEXT 416 312 Left 2 !.tran 3m
* Z:\tmp\asc_dec_bjh7r6w2\029e5253788f_6992-3_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N003 0 487K
R4 PWMout 0 10K
V1 N002 0 3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 96 -96 96
WIRE 624 96 320 96
WIRE 624 112 624 96
WIRE 96 176 80 176
WIRE 368 176 320 176
WIRE 512 176 368 176
WIRE 368 192 368 176
WIRE 512 192 512 176
WIRE 624 208 624 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 336 256 320 256
WIRE 336 288 336 256
WIRE 368 288 368 272
WIRE 368 288 336 288
WIRE 512 288 512 272
WIRE 368 304 368 288
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 487K
SYMBOL res 608 96 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL voltage 512 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
FLAG 512 288 0
FLAG 624 96 PWMout
FLAG 80 176 0
FLAG -16 256 0
FLAG 624 208 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG801.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
VS S 0 3
V2 IN 0 PULSE(0 3 0 10n 10n 980n 2u)
R1 D 0 47
C1 D 0 33p
XU1 +V IN S D 0 ADG801 ;pnba Vdd)IN)S)D)GND
.tran 10u
* Note:\nSwitch shown for a logic 1 input.\nPin Capacitance and Charge Injection are not included.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG801.asy)
.lib ADG801.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -272 -16 -288 -16
WIRE -240 -16 -272 -16
WIRE -32 -16 -48 -16
WIRE 0 -16 -32 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -272 48 -368 48
WIRE -240 48 -272 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
FLAG -272 -16 S
FLAG -272 48 IN
FLAG -32 -16 D
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 47
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 33p
SYMBOL ADG801 -144 32 R0
SYMATTR InstName U1
TEXT 72 224 Left 2 !.tran 10u
TEXT -592 -232 Left 2 ;Note:\nSwitch shown for a logic 1 input.\nPin Capacitance and Charge Injection are not included.
* Z:\home\khalils\Downloads\files\data\raw_asc\7c138b4877f2_Draft3.asc
* Generated by LTspice 26.0.1 for Windows.
* CMOS Inverter
M1 VDD IN Out VDD PMOS
V2 VDD 0 5V
V1 IN 0 V
M2 Out IN 0 0 NMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 96 240 48
WIRE 288 96 240 96
WIRE 288 144 288 96
WIRE 288 144 240 144
WIRE 192 176 128 176
WIRE 128 208 128 176
WIRE 128 208 16 208
WIRE 240 208 240 192
WIRE 368 208 240 208
WIRE 240 224 240 208
WIRE 128 304 128 208
WIRE 192 304 128 304
WIRE -352 320 -352 240
WIRE -240 320 -240 240
WIRE 240 416 240 320
IOPIN 16 208 In
IOPIN 368 208 Out
IOPIN 240 48 In
IOPIN -240 160 In
IOPIN -352 160 In
SYMBOL nmos 192 224 R0
SYMATTR InstName M2
SYMBOL pmos4 192 96 R0
SYMATTR InstName M1
SYMBOL voltage -240 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5V
SYMBOL voltage -352 144 R0
SYMATTR InstName V1
FLAG 240 416 0
FLAG 16 208 IN
FLAG 368 208 Out
FLAG 240 48 VDD
FLAG -240 160 VDD
FLAG -352 160 IN
FLAG -352 320 0
FLAG -240 320 0
TEXT 32 64 Left 2 ;CMOS Inverter