Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1375.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1375.asy)
R2 OUT N006 5.36K
R1 N006 0 4.99K
C4 N004 0 10n
D1 0 N003 MBRS340
XU1 N001 IN N003 N002 MP_01 0 N006 N005 LT1375 top=1K bot=1T ;pnba Boost)Vin)SW)_SHDN))GND)FB)Vc
V1 IN 0 6.2
R3 N005 N004 1K
C1 N001 N003 .1
L1 N003 OUT 10 Rser=0.02 Rpar=5000
Rload OUT 0 10
C2 OUT 0 100 Rser=0.05
D2 OUT N001 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT1375.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2372 1144
WIRE 1328 672 1120 672
WIRE 1584 672 1456 672
WIRE 1664 672 1584 672
WIRE 1776 672 1728 672
WIRE 1120 688 1120 672
WIRE 1328 704 1328 672
WIRE 1456 704 1456 672
WIRE 1584 704 1584 672
WIRE 1120 784 1120 768
WIRE 1248 784 1232 784
WIRE 1584 784 1584 768
WIRE 1584 784 1536 784
WIRE 1664 784 1584 784
WIRE 1776 784 1776 672
WIRE 1776 784 1744 784
WIRE 1888 784 1776 784
WIRE 2000 784 1888 784
WIRE 1584 800 1584 784
WIRE 1776 800 1776 784
WIRE 1888 800 1888 784
WIRE 2000 800 2000 784
WIRE 1584 880 1584 864
WIRE 1888 896 1888 864
WIRE 2000 896 2000 880
WIRE 1072 912 1056 912
WIRE 1152 912 1136 912
WIRE 1248 912 1232 912
WIRE 1776 912 1776 880
WIRE 1776 912 1536 912
WIRE 1776 928 1776 912
WIRE 1392 1008 1392 992
WIRE 1776 1024 1776 1008
SYMBOL POLCAP 1872 800 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.05
SYMBOL DIODE 1728 656 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL POWERPRODUCTS\\LT1375 1392 848 R0
SYMATTR InstName U1
SYMBOL IND 1648 800 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL POLCAP 1568 704 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 1248 896 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL res 1760 784 R0
SYMATTR InstName R2
SYMATTR Value 5.36K
SYMBOL VOLTAGE 1120 672 R0
SYMATTR InstName V1
SYMATTR Value 6.2
SYMBOL cap 1136 896 R90
WINDOW 3 32 32 VTop 2
WINDOW 0 0 32 VBottom 2
SYMATTR Value 10n
SYMATTR InstName C4
SYMBOL RES 1760 912 R0
SYMATTR InstName R1
SYMATTR Value 4.99K
SYMBOL schottky 1568 864 M180
WINDOW 0 36 54 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL res 1984 784 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 1776 1024 0
FLAG 1584 880 0
FLAG 2000 896 0
FLAG 1888 896 0
FLAG 1392 1008 0
FLAG 1120 784 0
FLAG 1056 912 0
FLAG 2000 784 OUT
FLAG 1120 672 IN
TEXT 1520 1032 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\5a989c92049f_90nm_PMOS.asc
* Generated by LTspice 26.0.1 for Windows.
vsg N003 0 -1.2
M1 N001 N003 0 N002 PMOS l=90nm w=405nm
vsd N001 0 -1.2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc vsg 0 -1.2 .1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 64 224 64
WIRE 224 96 224 64
WIRE 368 96 368 64
WIRE 224 144 224 112
WIRE 176 176 80 176
WIRE 80 192 80 176
WIRE 208 272 80 272
WIRE 224 272 224 192
WIRE 224 272 208 272
WIRE 368 272 368 176
WIRE 368 272 224 272
WIRE 208 288 208 272
SYMBOL pmos4 176 96 R0
SYMATTR InstName M1
SYMATTR Value2 l=90nm w=405nm
SYMBOL voltage 80 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vsg
SYMATTR Value -1.2
SYMBOL voltage 368 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vsd
SYMATTR Value -1.2
FLAG 208 288 0
TEXT 48 312 Left 2 !.dc vsg 0 -1.2 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-5.asy)
V1 IN 0 PWL(0 0 1 10)
C2 OUT N001 .01
Rload OUT 0 500
C1 OUT 0 10
XU1 IN 0 IN N001 OUT LT1761-5 ;pnba IN)GND)_SHDN)BYP)OUT
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 48 -224 48
WIRE 16 48 -16 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE -16 144 -16 48
WIRE 16 144 -16 144
WIRE 336 144 336 128
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT1761-5 160 96 R0
SYMATTR InstName U1
SYMBOL cap 320 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG -224 48 IN
FLAG 512 48 OUT
TEXT 376 216 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2164-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2164-1.5.asy)
R4 N003 0 45.3K
L1 N002 OUT 1 Rser=6m
C1 N001 0 100n
C3 OUT 0 83 Rser=2m
V1 IN 0 5
R5 IN N001 10
R3 OUT N004 100K
Rload OUT 0 0.5
XU1 N001 N003 IN OUT 0 0 N002 IN N001 N001 N004 ADP2164-x.x Rtop=600K Rbot=400K ;pnba Sync)Rt)TRK)FB)GND)PGND)SW)Pvin)Vin)EN)Pgood
.tran 2m startup
.lib ADP2164-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 728
WIRE -80 -112 -304 -112
WIRE 176 -112 -80 -112
WIRE 400 -112 176 -112
WIRE -304 -96 -304 -112
WIRE -80 -96 -80 -112
WIRE 176 -80 176 -112
WIRE -304 0 -304 -16
WIRE -160 0 -176 0
WIRE -80 0 -80 -16
WIRE -80 0 -96 0
WIRE 0 0 -80 0
WIRE 400 0 400 -112
WIRE 400 0 352 0
WIRE -80 112 -80 0
WIRE 0 112 -80 112
WIRE 368 112 352 112
WIRE 480 112 448 112
WIRE 544 112 480 112
WIRE 640 112 544 112
WIRE 544 128 544 112
WIRE 640 128 640 112
WIRE -80 224 -80 112
WIRE 0 224 -80 224
WIRE 480 224 480 112
WIRE 480 224 352 224
WIRE 544 224 544 192
WIRE 640 224 640 208
WIRE -96 368 -112 368
WIRE 0 368 -16 368
WIRE 368 368 352 368
WIRE 480 368 480 224
WIRE 480 368 448 368
WIRE 112 496 112 480
WIRE 240 496 240 480
SYMBOL voltage -304 -112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 624 112 R0
SYMATTR InstName Rload
SYMATTR Value 0.5
SYMBOL ind 352 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=6m
SYMBOL cap 528 128 R0
SYMATTR InstName C3
SYMATTR Value 83
SYMATTR SpiceLine Rser=2m
SYMBOL res 464 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap -96 16 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL res -96 -112 R0
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL ADP2164-1.5 176 192 R0
SYMATTR InstName U1
SYMBOL res 0 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 45.3K
FLAG 112 496 0
FLAG -112 368 0
FLAG -304 0 0
FLAG 544 224 0
FLAG 640 224 0
FLAG 640 112 OUT
FLAG -304 -112 IN
FLAG 240 496 0
FLAG -176 0 0
TEXT 488 464 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\a978f030d617_half_wave_diode_rectifier_bb.asc
* Generated by LTspice 26.0.1 for Windows.
D1 CA-V CB-H 1N914
R1 CB-H N001 100
V1 N001 0 2.5
V2 CA-V 0 SINE(2.5 2.5 100)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
* Half-wave Diode Rectifier
.tran 20m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 144 -64 144
WIRE 256 144 160 144
WIRE 336 144 256 144
WIRE -64 176 -64 144
WIRE 256 192 256 144
WIRE 256 304 256 272
FLAG 336 144 CB-H
FLAG -64 144 CA-V
FLAG 256 384 0
FLAG -64 256 0
SYMBOL diode 96 160 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL res 240 176 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 256 288 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage -64 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(2.5 2.5 100)
TEXT 24 32 Left 2 ;Half-wave Diode Rectifier
TEXT -108 408 Left 2 !.tran 20m
* Z:\home\khalils\Downloads\files\data\raw_asc\01121b582a34_tlv431_window_comparator.asc
* Generated by LTspice 26.0.1 for Windows.
* Window comparator for 4.8V < 5V < 5.2V.\nBy adding R5, which is a small fraction of R3, the error introduced by the cathode current of U1 is minimized.\nDon't chose R5 too small. U1 should still be able to cope with the cathode current when it's fully conducting.
* R5 is 2% of R3 in this case.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\TLV431.asy)
R6 N001 Vout 1k
XU2 Vout 0 NC_02 TLV431 ;pnba K)A)R
R4 N004 0 20k
V1 N001 0 0
XU1 N002 0 NC_01 TLV431 ;pnba K)A)R
R3 N002 N004 56k
R5 N001 N002 1k
R2 N003 0 4.7k
R1 N001 N003 15k
.dc v1 0 10 0.01
.lib TLV431.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1300 680
WIRE 160 -144 32 -144
WIRE 384 -144 160 -144
WIRE 528 -144 384 -144
WIRE 384 -96 384 -144
WIRE 528 -96 528 -144
WIRE 384 0 384 -16
WIRE 384 0 272 0
WIRE 160 16 160 -144
WIRE 384 16 384 0
WIRE 528 32 528 -16
WIRE 272 96 272 0
WIRE 528 96 528 32
WIRE 160 128 160 96
WIRE 240 128 160 128
WIRE 384 128 384 96
WIRE 496 128 384 128
WIRE 32 144 32 -144
WIRE 160 144 160 128
WIRE 384 144 384 128
WIRE 32 272 32 224
WIRE 160 272 160 224
WIRE 272 272 272 160
WIRE 384 272 384 224
WIRE 528 272 528 160
SYMBOL res 144 0 R0
SYMATTR InstName R1
SYMATTR Value 15k
SYMBOL Parts_TCO\\TLV431 272 128 M0
SYMATTR InstName U1
SYMBOL res 144 128 R0
SYMATTR InstName R2
SYMATTR Value 4.7k
SYMBOL voltage 32 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL Parts_TCO\\TLV431 528 128 M0
SYMATTR InstName U2
SYMBOL res 512 -112 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res 368 -112 R0
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL res 368 128 R0
SYMATTR InstName R4
SYMATTR Value 20k
SYMBOL res 368 0 R0
SYMATTR InstName R3
SYMATTR Value 56k
FLAG 32 272 0
FLAG 160 272 0
FLAG 272 272 0
FLAG 384 272 0
FLAG 528 272 0
FLAG 528 32 Vout
TEXT -192 192 Left 2 !.dc v1 0 10 0.01
TEXT 40 -352 Left 2 ;Window comparator for 4.8V < 5V < 5.2V.\nBy adding R5, which is a small fraction of R3, the error introduced by the cathode current of U1 is minimized.\nDon't chose R5 too small.  U1 should still be able to cope with the cathode current when it's fully conducting.
TEXT 48 -264 Left 2 ;R5 is 2% of R3 in this case.
* Z:\home\khalils\Downloads\files\data\raw_asc\aadede894a5b_EJ2.asc
* Generated by LTspice 26.0.1 for Windows.
* Respuesta en frecuencia
C1 0 N001 1.58823
L1 N002 N001 1.1893
C3 N002 0 0.41176
C2 N002 N001 0.09342
RL 0 N002 1
I1 0 N001 AC 1
.ac dec 100 0.00001 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 680
WIRE 416 96 384 96
WIRE 528 96 480 96
WIRE 224 144 96 144
WIRE 384 144 384 96
WIRE 384 144 224 144
WIRE 528 144 528 96
WIRE 592 144 528 144
WIRE 784 144 592 144
WIRE 96 176 96 144
WIRE 784 176 784 144
WIRE 224 192 224 144
WIRE 384 192 384 144
WIRE 416 192 384 192
WIRE 528 192 528 144
WIRE 528 192 496 192
WIRE 592 192 592 144
WIRE 96 288 96 256
WIRE 224 288 224 256
WIRE 224 288 96 288
WIRE 592 288 592 256
WIRE 592 288 224 288
WIRE 784 288 784 256
WIRE 784 288 592 288
WIRE 224 336 224 288
SYMBOL cap 480 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 0.09342
SYMBOL ind 512 176 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 1.1893
SYMBOL cap 576 192 R0
WINDOW 0 -33 30 Left 2
WINDOW 3 37 31 Left 2
SYMATTR InstName C3
SYMATTR Value 0.41176
SYMBOL current 96 256 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 800 272 R180
WINDOW 0 40 58 Left 2
WINDOW 3 -27 59 Left 2
SYMATTR InstName RL
SYMATTR Value 1
SYMBOL cap 240 256 R180
WINDOW 0 41 37 Left 2
WINDOW 3 -102 34 Left 2
SYMATTR InstName C1
SYMATTR Value 1.58823
FLAG 224 336 0
TEXT 336 360 Left 2 !.ac dec 100 0.00001 100
TEXT 336 320 Left 2 ;Respuesta en frecuencia
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1810.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
R1 N002 N001 1K
R2 N001 N003 1K
C1 N002 N001 3p
C2 N003 0 150
R3 +V N004 5K
R4 N004 0 5K
C3 N004 IN 33
R5 IN 0 75
C4 N005 N002 1000
R6 N005 N006 75
T1 N006 0 OUT 0 Td=50n Z0=75
R7 OUT 0 75
V2 IN 0 AC 2 Rser=75
XU1 N004 N001 +V 0 N002 LT1810 ;pnba In+)In-)V+)V-)OUT
.ac oct 20 200K 200Meg
* 5V Single Supply Video Line Driver
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1810.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 160 -16 128 -16
WIRE 256 -16 224 -16
WIRE -192 48 -192 32
WIRE -48 80 -64 80
WIRE 32 80 16 80
WIRE 128 80 128 -16
WIRE 128 80 112 80
WIRE 144 80 128 80
WIRE 256 80 256 -16
WIRE 256 80 224 80
WIRE -192 144 -192 128
WIRE 32 192 16 192
WIRE 192 192 192 176
WIRE 192 192 112 192
WIRE 192 208 192 192
WIRE 128 224 128 80
WIRE 160 224 128 224
WIRE 256 240 256 80
WIRE 256 240 224 240
WIRE 304 240 256 240
WIRE 400 240 368 240
WIRE 512 240 480 240
WIRE 704 240 608 240
WIRE -112 256 -272 256
WIRE -64 256 -112 256
WIRE 16 256 16 192
WIRE 16 256 0 256
WIRE 160 256 16 256
WIRE 704 256 704 240
WIRE -272 272 -272 256
WIRE -112 272 -112 256
WIRE 16 272 16 256
WIRE 512 272 496 272
WIRE 624 272 608 272
WIRE 192 288 192 272
WIRE 704 352 704 336
WIRE -272 368 -272 352
WIRE -112 368 -112 352
WIRE 16 368 16 352
FLAG -192 144 0
FLAG 192 176 +V
FLAG -192 32 +V
FLAG -64 80 0
FLAG 192 288 0
FLAG 16 368 0
FLAG -112 368 0
FLAG 496 272 0
FLAG 624 272 0
FLAG 704 352 0
FLAG -272 368 0
FLAG 704 240 OUT
FLAG -272 256 IN
SYMBOL voltage -192 32 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 240 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 128 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap 224 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 3p
SYMBOL cap 16 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 150
SYMBOL res 128 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 5K
SYMBOL res 0 256 R0
SYMATTR InstName R4
SYMATTR Value 5K
SYMBOL cap 0 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 33
SYMBOL res -128 256 R0
SYMATTR InstName R5
SYMATTR Value 75
SYMBOL cap 368 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1000
SYMBOL res 384 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 75
SYMBOL tline 560 256 R0
WINDOW 3 -71 46 Left 2
SYMATTR Value Td=50n Z0=75
SYMATTR InstName T1
SYMBOL res 688 240 R0
SYMATTR InstName R7
SYMATTR Value 75
SYMBOL voltage -272 256 R0
WINDOW 3 24 104 Invisible 2
WINDOW 123 39 60 Left 2
WINDOW 39 26 99 Left 2
SYMATTR Value ""
SYMATTR Value2 AC 2
SYMATTR SpiceLine Rser=75
SYMATTR InstName V2
SYMBOL opamps\\LT1810 192 176 R0
SYMATTR InstName U1
TEXT 192 368 Left 2 !.ac oct 20 200K 200Meg
TEXT 272 -64 Bottom 2 ;5V Single Supply Video Line Driver
* Z:\home\khalils\Downloads\files\data\raw_asc\3c36bdb189dd_Fig17_29.asc
* Generated by LTspice 26.0.1 for Windows.
VDD VDD 0 1
M1 N001 Vcol 0 N001 P_50n l=50n w=1u
Vcol Vcol 0 500m
R2 VDD N001 10Meg
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.dc Vcol 0 750m 1m
* Plot I(M1) and d(I(M1))
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1556 680
WIRE 320 -80 320 -112
WIRE 320 32 320 0
WIRE 464 -64 464 -96
WIRE 464 48 464 16
WIRE 608 -96 464 -96
WIRE 656 -288 656 -336
WIRE 656 -176 656 -208
WIRE 656 -32 656 -80
WIRE 672 -176 656 -176
WIRE 672 -128 656 -128
WIRE 672 -128 672 -176
FLAG 320 32 0
FLAG 320 -112 VDD
FLAG 464 48 0
FLAG 464 -96 Vcol
FLAG 656 -336 VDD
FLAG 656 -32 0
SYMBOL voltage 320 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL pmos4 608 -176 R0
WINDOW 0 56 32 Invisible 0
WINDOW 123 84 21 Left 0
SYMATTR InstName M1
SYMATTR Value2 l=50n w=1u
SYMATTR Value P_50n
SYMBOL voltage 464 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 500m
SYMATTR InstName Vcol
SYMBOL res 640 -304 R0
SYMATTR InstName R2
SYMATTR Value 10MEG
TEXT 552 48 Left 0 !.lib cmosedu_models.txt
TEXT 552 24 Left 0 !.dc Vcol 0 750m 1m
TEXT 328 -264 Left 0 ;Plot I(M1) and d(I(M1))
* Z:\home\khalils\Downloads\files\data\raw_asc\3542073b1086_01_Crystal_AC-analysis.asc
* Generated by LTspice 26.0.1 for Windows.
R3 out 0 1Meg
L1 in N001 4.52
C2 out 0 12.5p
V1 N003 0 SINE(0 1m 77500) AC 1m 0
R1 N002 N001 50k
R2 in N003 10k
C1 out N002 1p
.ac oct 100 1000 1000000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 16 -128 16
WIRE 160 16 128 16
WIRE 256 16 240 16
WIRE 336 16 320 16
WIRE 464 16 336 16
WIRE -128 64 -128 16
WIRE 336 96 336 16
WIRE 464 112 464 16
WIRE -128 192 -128 144
WIRE -128 320 -128 272
WIRE 336 320 336 160
WIRE 464 320 464 192
SYMBOL voltage -128 176 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1m 77500)
SYMATTR Value2 AC 1m 0
SYMBOL cap 320 0 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL res 256 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50k
SYMBOL ind 32 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.52
SYMBOL res 448 96 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL cap 320 96 R0
SYMATTR InstName C2
SYMATTR Value 12.5p
SYMBOL res -144 48 R0
SYMATTR InstName R2
SYMATTR Value 10k
FLAG -128 320 0
FLAG 464 320 0
FLAG 464 16 out
FLAG -128 16 in
FLAG 336 320 0
TEXT -162 344 Left 2 !.ac oct 100 1000 1000000
* Z:\home\khalils\Downloads\files\data\raw_asc\2671e19db58b_MOS_TRANS.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 NMOS
VDS N001 0 5
VGS N002 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VDS 0 5 0.1 VGS 3 5 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 336 144 176 144
WIRE 128 288 128 224
SYMBOL voltage 128 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 5
SYMBOL voltage 336 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 5
SYMBOL nmos 128 144 R0
SYMATTR InstName M1
FLAG 336 224 0
FLAG 176 240 0
FLAG 128 368 0
TEXT 216 384 Left 2 !.dc VDS 0 5 0.1 VGS 3 5 1
* Z:\home\khalils\Downloads\files\data\raw_asc\3a87ba554160_S_H.asc
* Generated by LTspice 26.0.1 for Windows.
B2 N001 0 V=V(in)
C1 Vc 0 100pF
S1 N001 Vc N002 0 VCS1
B1 out 0 V=V(Vc)
B3 N002 0 V=V(clk)
.model VCS1 SW(Ron=1E-9 Roff=1E12 Vt=0)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 0 -128 0
WIRE 208 0 64 0
WIRE 272 0 208 0
WIRE 528 0 368 0
WIRE 0 112 0 48
WIRE -128 192 -128 0
WIRE 48 192 48 48
WIRE 368 192 368 0
WIRE -176 208 -256 208
WIRE 208 208 208 0
WIRE -176 256 -256 256
WIRE -128 352 -128 272
WIRE 48 352 48 272
WIRE 208 352 208 272
WIRE 368 352 368 272
IOPIN -256 208 In
IOPIN -256 256 In
IOPIN 528 0 Out
SYMBOL cap 192 208 R0
SYMATTR InstName C1
SYMATTR Value 100pF
SYMBOL bv 368 176 R0
SYMATTR InstName B1
SYMATTR Value V=V(Vc)
SYMBOL bv 48 176 R0
SYMATTR InstName B3
SYMATTR Value V=V(clk)
SYMBOL sw -32 0 R270
WINDOW 3 13 103 Left 0
SYMATTR Value VCS1
SYMATTR InstName S1
SYMBOL bv -128 176 R0
SYMATTR InstName B2
SYMATTR Value V=V(in)
FLAG 0 112 0
FLAG 208 352 0
FLAG 368 352 0
FLAG 272 0 Vc
FLAG -256 208 in
FLAG -256 256 clk
FLAG -128 352 0
FLAG 48 352 0
FLAG 528 0 out
TEXT -176 -152 Left 0 !.model VCS1 SW(Ron=1E-9 Roff=1E12 Vt=0)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1121.asc
* Generated by LTspice 26.0.1 for Windows.
* Note Abs. Max SHDN pin voltage 6.5
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1121.asy)
Rload OUT 0 100
C1 OUT 0 1
R2 OUT N001 10K
R1 N001 0 10K
XU1 OUT N001 0 MP_01 NC_02 MP_03 MP_04 IN LT1121 ;pnba OUT)ADJ)GND))_SHDN)))IN
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT1121.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 192 -224 192
WIRE 384 192 320 192
WIRE 480 192 384 192
WIRE 560 192 480 192
WIRE -224 208 -224 192
WIRE 480 208 480 192
WIRE 560 208 560 192
WIRE 384 288 384 272
WIRE 384 288 320 288
WIRE -224 304 -224 288
WIRE 384 304 384 288
WIRE 480 304 480 272
WIRE 560 304 560 288
WIRE 176 384 176 352
WIRE 384 400 384 384
SYMBOL PowerProducts\\LT1121 176 240 R0
SYMATTR InstName U1
SYMBOL voltage -224 192 R0
SYMATTR Value PWL(0 0 1 10)
SYMATTR InstName V1
SYMBOL res 368 288 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 368 176 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 544 192 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 464 208 R0
SYMATTR InstName C1
SYMATTR Value 1u
FLAG -224 304 0
FLAG 176 384 0
FLAG 384 400 0
FLAG 480 304 0
FLAG 560 304 0
FLAG 560 192 OUT
FLAG -224 192 IN
TEXT 480 384 Left 2 !.tran 1
TEXT -432 352 Left 2 ;Note Abs. Max SHDN pin voltage 6.5
* Z:\home\khalils\Downloads\files\data\raw_asc\2015f5394071_lc_tank_orientation.asc
* Generated by LTspice 26.0.1 for Windows.
* we can see that waveform of v3-v4 is the same as v1-gnd.\nthe point of setting ground in the inductor center tap \nis just for the phase inversion. \n \nIn a hartely oscillator, v4 is used as input to the amp\nand the amp will amplify and invert(common emitter) \nthen supply energy back at node v3.
C1 v1 0 0.001 IC=1 Rser=0 Lser=0 Rpar=0 Cpar=0
L3 v3 0 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
L1 v1 v2 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
C2 v3 v4 0.001 IC=1 Rser=0 Lser=0 Rpar=0 Cpar=0
L2 v2 0 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
L4 0 v4 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
.tran 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1944 680
WIRE 384 -224 256 -224
WIRE 448 -224 384 -224
WIRE 880 -224 784 -224
WIRE 976 -224 880 -224
WIRE 448 -192 448 -224
WIRE 976 -192 976 -224
WIRE 256 -128 256 -224
WIRE 784 -128 784 -224
WIRE 976 -96 976 -112
WIRE 1184 -96 976 -96
WIRE 448 -80 448 -112
WIRE 448 -64 448 -80
WIRE 976 -64 976 -96
WIRE 1184 -48 1184 -96
WIRE 256 48 256 -64
WIRE 384 48 256 48
WIRE 448 48 448 16
WIRE 448 48 384 48
WIRE 784 48 784 -64
WIRE 880 48 784 48
WIRE 976 48 976 16
WIRE 976 48 880 48
WIRE 384 80 384 48
SYMBOL ind 432 -208 R0
SYMATTR InstName L1
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
SYMBOL cap 768 -128 R0
SYMATTR InstName C2
SYMATTR Value 0.001 IC=1
SYMATTR SpiceLine Rser=0 Lser=0 Rpar=0 Cpar=0
SYMBOL ind 432 -80 R0
SYMATTR InstName L2
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
SYMBOL cap 240 -128 R0
SYMATTR InstName C1
SYMATTR Value 0.001 IC=1
SYMATTR SpiceLine Rser=0 Lser=0 Rpar=0 Cpar=0
SYMBOL ind 960 -80 R0
SYMATTR InstName L4
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
SYMBOL ind 960 -208 R0
SYMATTR InstName L3
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
FLAG 384 80 0
FLAG 384 -224 v1
FLAG 448 -80 v2
FLAG 1184 -48 0
FLAG 880 -224 v3
FLAG 880 48 v4
TEXT 592 112 Left 2 !.tran 0.1
TEXT 1264 -208 Left 2 ;we can see that waveform of v3-v4 is the same as v1-gnd.\nthe point of setting ground in the inductor center tap \nis just for the phase inversion. \n \nIn a hartely oscillator, v4 is used as input to the amp\nand the amp will amplify and invert(common emitter) \nthen supply energy back at node v3.