Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1528.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1528.asy)
C1 OUT 0 3.3
Rload OUT 0 500
XU1 OUT OUT 0 0 IN LT1528 ;pnba OUT)Sense)GND)_SHDN)IN
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT1528.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 176 -208 176
WIRE 368 176 320 176
WIRE 432 176 368 176
WIRE 528 176 432 176
WIRE -208 192 -208 176
WIRE 432 192 432 176
WIRE 528 192 528 176
WIRE 32 272 16 272
WIRE 368 272 368 176
WIRE 368 272 320 272
WIRE -208 288 -208 272
WIRE 432 288 432 256
WIRE 528 288 528 272
WIRE 176 368 176 336
SYMBOL cap 416 192 R0
SYMATTR InstName C1
SYMATTR Value 3.3
SYMBOL PowerProducts\\LT1528 176 224 R0
SYMATTR InstName U1
SYMBOL voltage -208 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 512 176 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG -208 288 0
FLAG 176 368 0
FLAG 432 288 0
FLAG 528 288 0
FLAG -208 176 IN
FLAG 528 176 OUT
FLAG 16 272 0
TEXT 368 384 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\59237495ac0c_Draft_Diode_1N4001.asc
* Generated by LTspice 26.0.1 for Windows.
* Analyse
* Bibliothek
* Parameter
R1 IN1 IN2 {R1}
V1 IN1 0 PULSE(0 1 0 .5m .5m 0 1m)
D1 IN2 0 1N4001
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m
.inc elk.lib
.meas TRAN as MAX V(in1/out1) FROM 0 TO 2m
.param R1=10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 80 0 80
WIRE 96 80 48 80
WIRE 240 80 176 80
WIRE 304 80 240 80
WIRE 48 96 48 80
WIRE 240 96 240 80
WIRE 48 192 48 176
WIRE 240 192 240 160
WIRE 240 192 48 192
WIRE 48 208 48 192
IOPIN 0 80 In
IOPIN 304 80 Out
SYMBOL diode 224 96 R0
WINDOW 0 38 31 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4001
SYMBOL voltage 48 80 R0
WINDOW 3 -323 96 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 17 20 Left 2
SYMATTR Value PULSE(0 1 0 .5m .5m 0 1m)
SYMATTR InstName V1
SYMBOL res 80 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 1 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value {R1}
FLAG 48 208 0
FLAG 0 80 IN1
FLAG 304 80 IN2
TEXT -96 -64 Left 2 !.tran 2m
TEXT 80 -64 Left 2 !.inc elk.lib
TEXT -96 -16 Left 2 !.meas TRAN as MAX V(in1/out1) FROM 0 TO 2m
TEXT 256 -64 Left 2 !.param R1=10
TEXT -96 -88 Left 2 ;Analyse
TEXT 80 -88 Left 2 ;Bibliothek
TEXT 256 -88 Left 2 ;Parameter
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4624.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4624.asy)
C2 OUT 0 47 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
C1 N003 0 .005
R1 N002 0 40.2K
XU1 NC_01 N001 N001 N002 N003 NC_02 IN NC_03 OUT 0 0 IN IN LTM4624 ;pnba FREQ)INTVcc)Mode)FB)Track/SS)COMP)Run)Pgood)Vout)GND)SGND)Vin)SVin
Rload OUT 0 .375
V1 IN 0 12
.tran 2m startup
.lib LTM4624.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 -16 256 -16
WIRE 256 0 256 -16
WIRE 64 64 -64 64
WIRE 80 64 64 64
WIRE 448 64 448 -16
WIRE 448 64 432 64
WIRE -64 80 -64 64
WIRE 64 144 64 64
WIRE 80 144 64 144
WIRE -64 176 -64 160
WIRE 64 224 64 144
WIRE 80 224 64 224
WIRE 592 224 432 224
WIRE 672 224 592 224
WIRE 592 240 592 224
WIRE 672 240 672 224
WIRE 496 304 432 304
WIRE 496 320 496 304
WIRE 592 336 592 304
WIRE 672 336 672 320
WIRE 0 384 -16 384
WIRE 80 384 64 384
WIRE 496 416 496 400
WIRE 192 464 192 448
WIRE 320 464 320 448
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL PowerProducts\\LTM4624 256 224 R0
SYMATTR InstName U1
SYMBOL cap 576 240 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL cap 64 368 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .005
SYMBOL res 480 304 R0
SYMATTR InstName R1
SYMATTR Value 40.2K
SYMBOL res 656 224 R0
SYMATTR InstName Rload
SYMATTR Value .375
FLAG 192 464 0
FLAG 320 464 0
FLAG -64 176 0
FLAG -64 64 IN
FLAG -16 384 0
FLAG 496 416 0
FLAG 672 336 0
FLAG 592 336 0
FLAG 672 224 OUT
TEXT 624 440 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\164025844b5c_Draft11.asc
* Generated by LTspice 26.0.1 for Windows.
;.op dec 10000000 10Meg 300Meg
;.step param Ctest list 10p 20p 30p
C1 N002 N001 21.65p
C2 0 N002 34.64p
V1 N001 0 AC 1 0
.step param Vtest list 0 1 2 3 4 5
.ac dec 10000000 10Meg 300Meg
.MODEL SMV1130-079LF d CJ0=25.8p Vj=10 M=3.7 Rs=0.8
.lib C:\Users\piyus\Projects\public\fm_radio\sims\varactor_model.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 948 680
WIRE -592 64 -672 64
WIRE -432 64 -528 64
WIRE -336 64 -368 64
WIRE -672 128 -672 64
WIRE -336 144 -336 64
WIRE -672 272 -672 208
SYMBOL cap -368 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 34.64p
SYMBOL voltage -672 112 R0
WINDOW 3 -128 70 Left 2
WINDOW 123 -128 42 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMBOL cap -528 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 21.65p
FLAG -672 272 0
FLAG -336 144 0
TEXT -144 -112 Left 2 !.step param Vtest list 0 1 2 3 4 5
TEXT -928 -56 Left 2 !.ac dec 10000000 10Meg 300Meg
TEXT 216 264 Left 2 !;.op dec 10000000 10Meg 300Meg
TEXT 536 -88 Left 2 !;.step param Ctest list 10p 20p 30p
TEXT -136 -8 Left 2 !.MODEL SMV1130-079LF d CJ0=25.8p Vj=10 M=3.7  Rs=0.8
TEXT -136 56 Left 2 !.lib C:\\Users\\piyus\\Projects\\public\\fm_radio\\sims\\varactor_model.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX17610.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 48
C2 OUT 0 15
S1 0 OUT N001 0 SHORT
V3 N001 0 PULSE(0 1 70m 1m 1m 100m)
R6 N004 N003 20K
R8 N006 0 1.5K
R7 N004 N005 20K
V2 N004 0 5
V4 N002 0 2
XU1 IN N006 0 NC_01 N002 N003 N005 OUT MAX17610 ;pnba IN)SETI)GND)CLMODE)EN)_FWD)_REV)OUT
.model SHORT SW(Ron=24 Roff=100K Vt=.5 Vh=-.4)
.tran 1.25 startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX17610.asy)
.lib MAX17610.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1800 680
WIRE -16 -352 -256 -352
WIRE 400 -352 272 -352
WIRE 512 -352 400 -352
WIRE 672 -352 560 -352
WIRE -256 -336 -256 -352
WIRE 400 -336 400 -352
WIRE 512 -336 512 -352
WIRE 672 -336 672 -352
WIRE 560 -320 560 -352
WIRE -256 -240 -256 -256
WIRE 400 -240 400 -272
WIRE 512 -240 512 -256
WIRE 672 -240 672 -256
WIRE -16 -160 -256 -160
WIRE 384 -160 272 -160
WIRE 496 -160 464 -160
WIRE -256 -144 -256 -160
WIRE 496 -112 496 -160
WIRE 576 -112 496 -112
WIRE 576 -80 576 -112
WIRE 384 -64 272 -64
WIRE 496 -64 496 -112
WIRE 496 -64 464 -64
WIRE -256 -48 -256 -64
WIRE 336 16 272 16
WIRE 576 16 576 0
WIRE 336 32 336 16
WIRE 336 128 336 112
WIRE 336 128 272 128
WIRE 336 160 336 128
FLAG -256 -240 0
FLAG 400 -240 0
FLAG 512 -352 OUT
FLAG -256 -352 IN
FLAG 512 -240 0
FLAG 560 -272 0
FLAG 672 -240 0
FLAG 336 160 0
FLAG 576 16 0
FLAG -256 -48 0
SYMBOL voltage -256 -352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 48
SYMBOL cap 384 -336 R0
SYMATTR InstName C2
SYMATTR Value 15
SYMBOL sw 512 -240 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SHORT
SYMBOL voltage 672 -352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 70m 1m 1m 100m)
SYMBOL res 480 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 20K
SYMBOL res 320 16 R0
SYMATTR InstName R8
SYMATTR Value 1.5K
SYMBOL res 480 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 20K
SYMBOL voltage 576 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -256 -160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value 2
SYMBOL MAX17610 128 -112 R0
SYMATTR InstName U1
TEXT 480 144 Left 2 !.model SHORT SW(Ron=24 Roff=100K Vt=.5 Vh=-.4)
TEXT 480 184 Left 2 !.tran 1.25 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7154-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 2.9
C1 OUT 0 10 Rser=10m Lser=1n
C2 N003 0 1
C3 N004 0 1
C4 N002 0 1
R1 IN N001 100K
Rload OUT 0 18
XU1 N004 OUT N002 0 N003 N003 N001 IN ADM7154_5 Vreg=2.6022 Vref=1.8154 ;pnba Vreg)Vout)Byp)GND)Ref_Sense)Ref)EN)Vin
.tran 5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7154-1.8.asy)
.lib ADM7154_5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -144 32
WIRE 80 32 -32 32
WIRE 464 32 400 32
WIRE 560 32 464 32
WIRE -144 48 -144 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE -144 144 -144 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE -16 224 -32 224
WIRE 80 224 48 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE -16 320 -32 320
WIRE 80 320 48 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -32 320 0
FLAG -32 224 0
FLAG -144 144 0
FLAG 560 144 0
FLAG -144 32 IN
FLAG 560 32 OUT
SYMBOL voltage -144 32 R0
SYMATTR InstName V1
SYMATTR Value 2.9
SYMBOL cap 448 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR Value2 Rser=10m
SYMATTR SpiceLine Lser=1n
SYMBOL cap 448 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 48 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 48 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL res 544 32 R0
SYMATTR InstName Rload
SYMATTR Value 18
SYMBOL ADM7154-1.8 240 176 R0
SYMATTR InstName U1
TEXT 432 384 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\3e1498122574_Fig6_19_NMOS_ID_VDS.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 N_50n L=50n W=500n
VGS N002 0 0
VDS N001 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VDS 0 1 1m VGS 0 1 250m
.lib cmosedu_models.txt
* Plot Id(M1)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 288 208 288 192
WIRE 288 304 288 288
WIRE 400 192 288 192
WIRE 448 112 448 80
WIRE 448 224 448 208
WIRE 496 160 448 160
WIRE 640 80 448 80
WIRE 640 112 640 80
WIRE 640 224 640 192
FLAG 288 304 0
FLAG 448 224 0
FLAG 640 224 0
FLAG 496 160 0
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 L=50n W=500n
SYMBOL voltage 288 192 R0
WINDOW 0 -90 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VGS
SYMATTR Value 0
SYMBOL voltage 640 96 R0
WINDOW 0 41 55 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VDS
SYMATTR Value 0
TEXT 384 272 Left 0 !.dc VDS 0 1 1m VGS 0 1 250m
TEXT 384 296 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot Id(M1)
* Z:\home\khalils\Downloads\files\data\raw_asc\61d9b327f701_iNMOS.asc
* Generated by LTspice 26.0.1 for Windows.
* body diode
* snubber
* binary
* Ideal NMOS
* on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
* Drain
* Source
* Gate
* 2025-7-21
* <Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
R1 D N003 {rsnb}
D1 S N002 myD
C1 N003 S {csnb}
L1 D N001 {esl}
L2 D N002 {esl}
S1 S N001 G S SW_iNMOS
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)
.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
.param ron=10m
.param esl=1f
.param rsnb=1k
.param csnb=10p
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1384 680
WIRE 288 -288 288 -320
WIRE 608 -288 288 -288
WIRE 928 -288 608 -288
WIRE 288 -240 288 -288
WIRE 608 -240 608 -288
WIRE 928 -192 928 -288
WIRE 288 -112 288 -160
WIRE 240 -96 96 -96
WIRE 608 -96 608 -160
WIRE 928 -80 928 -112
WIRE 240 -48 208 -48
WIRE 208 0 208 -48
WIRE 288 0 288 -32
WIRE 288 0 208 0
WIRE 288 80 288 0
WIRE 608 80 608 -32
WIRE 608 80 288 80
WIRE 928 80 928 -16
WIRE 928 80 608 80
WIRE 288 112 288 80
IOPIN 288 -320 BiDir
IOPIN 288 112 BiDir
IOPIN 96 -96 BiDir
SYMBOL ind 272 -256 R0
SYMATTR InstName L1
SYMATTR Value {esl}
SYMBOL res 912 -208 R0
SYMATTR InstName R1
SYMATTR Value {rsnb}
SYMBOL diode 624 -32 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value myD
SYMBOL ind 592 -256 R0
SYMATTR InstName L2
SYMATTR Value {esl}
SYMBOL sw 288 -16 M180
SYMATTR InstName S1
SYMATTR Value SW_iNMOS
SYMBOL cap 912 -80 R0
SYMATTR InstName C1
SYMATTR Value {csnb}
FLAG 288 -320 D
FLAG 288 112 S
FLAG 96 -96 G
TEXT 56 -440 Left 2 !.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)\n.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
TEXT 56 -568 Left 2 !.param ron=10m\n.param esl=1f\n.param rsnb=1k\n.param csnb=10p
TEXT 552 -320 Left 2 ;body diode
TEXT 888 -320 Left 2 ;snubber
TEXT 56 -120 Left 1 ;binary
TEXT 40 -624 Left 4 ;Ideal NMOS
TEXT 312 -568 Left 2 ;on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
TEXT 312 -344 Left 2 ;Drain
TEXT 312 136 Left 2 ;Source
TEXT 56 -64 Left 2 ;Gate
TEXT 1000 -624 Left 2 ;2025-7-21
TEXT 80 208 Left 2 ;<Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
* Z:\home\khalils\Downloads\files\data\raw_asc\386dc8c7eccd_BC549Cm.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 6
Q1 N001 N002 0 0 BC549C
I1 0 N002 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.lib BC549C.sub
.dc i1 0 100uA 10uA
.meas ib find Ic(Q1)/Ib(Q1) when Ic(Q1)=6/303
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1472 680
WIRE 704 112 464 112
WIRE 464 144 464 112
WIRE 704 144 704 112
WIRE 640 192 576 192
WIRE 576 208 576 192
WIRE 464 256 464 224
WIRE 704 272 704 240
WIRE 576 304 576 288
SYMBOL voltage 464 128 R0
SYMATTR InstName V1
SYMATTR Value 6
SYMBOL npn 640 144 R0
SYMATTR InstName Q1
SYMATTR Value BC549C
SYMBOL current 576 288 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName I1
SYMATTR Value 0
FLAG 464 256 0
FLAG 576 304 0
FLAG 704 272 0
TEXT 824 56 Left 2 !.lib BC549C.sub
TEXT 792 128 Left 2 !.dc i1 0 100uA 10uA\n.meas ib find Ic(Q1)/Ib(Q1) when Ic(Q1)=6/303
* Z:\home\khalils\Downloads\files\data\raw_asc\0d46e6bf5d62_piezo_3Resistor_voltage_divider_DC_offset_circuit.asc
* Generated by LTspice 26.0.1 for Windows.
V_PIEZO N002 0 SINE(0 20 1000)
R1 Vout_to_ESP32_ADC_pin N002 1Meg
R3 0 Vout_to_ESP32_ADC_pin 100K
R2 N001 Vout_to_ESP32_ADC_pin 100K
V_ESP32_MAX N001 0 3.3V
.tran 0.1u 5m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 680
WIRE 464 -176 176 -176
WIRE 176 -160 176 -176
WIRE 464 -80 464 -176
WIRE 288 96 176 96
WIRE 464 96 464 0
WIRE 464 96 368 96
WIRE 624 96 464 96
WIRE 176 192 176 96
WIRE 464 192 464 96
WIRE 176 368 176 272
WIRE 464 368 464 272
FLAG 176 368 0
FLAG 464 368 0
FLAG 176 -80 0
FLAG 624 96 Vout_to_ESP32_ADC_pin
SYMBOL voltage 176 176 R0
WINDOW 3 -229 68 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
WINDOW 0 -141 41 Left 2
SYMATTR Value SINE(0 20 1000)
SYMATTR InstName V_PIEZO
SYMBOL res 384 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL res 480 288 R180
WINDOW 0 -33 65 Left 2
WINDOW 3 -57 36 Left 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 448 -96 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL voltage 176 -176 R0
WINDOW 0 -213 51 Left 2
WINDOW 3 42 52 Left 2
SYMATTR InstName V_ESP32_MAX
SYMATTR Value 3.3V
TEXT -176 344 Left 2 !.tran 0.1u 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\7d660dff7a15_trans1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 5
C1 out 0 10n
R1 out N001 {res}
.tran 10u uic
.meas TRAN out FIND v(out) AT 0.5u
.step param res 10 100 10
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 128 32 32 32
WIRE 272 32 208 32
WIRE 288 32 272 32
WIRE 288 64 288 32
WIRE 32 80 32 32
WIRE 32 176 32 160
WIRE 288 176 288 128
SYMBOL res 224 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {res}
SYMBOL cap 272 64 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage 32 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 32 176 0
FLAG 288 176 0
FLAG 272 32 out
TEXT 8 208 Left 2 !.tran 10u uic
TEXT 8 232 Left 2 !.meas TRAN out FIND v(out) AT 0.5u
TEXT 8 256 Left 2 !.step param res 10 100 10
* Z:\home\khalils\Downloads\files\data\raw_asc\0250f72b62db_Fig6_13.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1)
M1 N001 N003 0 N002 N_1u L=1u W=10u
VDS N001 0 5
VGS N003 0 0
VSB 0 N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VGS 0 2 1m VSB 0 5 1
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 352 208 352 192
WIRE 352 304 352 288
WIRE 400 192 352 192
WIRE 448 112 448 80
WIRE 448 272 448 208
WIRE 704 160 448 160
WIRE 704 272 704 240
WIRE 848 80 448 80
WIRE 848 112 848 80
WIRE 848 224 848 192
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 L=1u W=10u
SYMBOL voltage 704 256 R180
WINDOW 0 -37 57 Right 0
WINDOW 3 -49 27 Invisible 0
SYMATTR InstName VSB
SYMATTR Value 0
SYMBOL voltage 352 192 R0
WINDOW 0 -91 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VGS
SYMATTR Value 0
SYMBOL voltage 848 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VDS
SYMATTR Value 5
FLAG 352 304 0
FLAG 448 272 0
FLAG 848 224 0
FLAG 704 272 0
TEXT 448 320 Left 0 !.dc VGS 0 2 1m VSB 0 5 1
TEXT 448 344 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot Id(M1)
* Z:\home\khalils\Downloads\files\data\raw_asc\1582966fb5e4__Fig1_20_AC_MSD.asc
* Generated by LTspice 26.0.1 for Windows.
Vin Vin 0 AC 1
E1 Vout 0 Vin N001 1
R1 N001 0 50
T1 Vin 0 N001 0 Td=10n Z0=50
.ac lin 1000 1k 200MEG
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1056 688
WIRE 752 256 704 256
WIRE 800 256 752 256
WIRE 704 288 704 256
WIRE 208 304 192 304
WIRE 272 304 208 304
WIRE 656 304 272 304
WIRE 192 320 192 304
WIRE 192 416 192 400
WIRE 272 480 272 304
WIRE 400 480 272 480
WIRE 656 480 656 352
WIRE 656 480 496 480
WIRE 656 496 656 480
WIRE 400 512 384 512
WIRE 528 512 496 512
WIRE 656 608 656 576
SYMBOL tline 448 496 R0
SYMATTR InstName T1
SYMATTR Value Td=10n Z0=50
SYMBOL res 640 480 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL e 704 272 R0
WINDOW 0 42 39 Left 0
WINDOW 3 44 69 Left 0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL voltage 192 304 R0
WINDOW 0 -73 38 Left 0
WINDOW 123 -82 95 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value2 AC 1
SYMATTR Value ""
FLAG 656 608 0
FLAG 528 512 0
FLAG 384 512 0
FLAG 192 416 0
FLAG 208 304 Vin
FLAG 752 256 Vout
FLAG 704 368 0
TEXT 304 392 Left 0 !.ac lin 1000 1k 200MEG
* Z:\tmp\asc_dec_bjh7r6w2\02095c9f83de_Type2_Phase_Detector_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
A4 0 N005 0 N007 0 0 N006 0 OR
Q1 N003 N002 ONE 0 2N3906
C1 Vout 0 1n
V1 Vin1 0 PULSE(0 1 0u 1n 1n 5u 10u)
R4 N008 N007 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2016 1028
WIRE 352 96 240 96
WIRE 416 96 352 96
WIRE 640 96 640 32
WIRE -32 144 -128 144
WIRE 80 144 -32 144
WIRE 320 144 256 144
WIRE 432 144 320 144
WIRE 576 144 512 144
WIRE -128 192 -128 144
WIRE 416 224 320 224
WIRE 640 240 640 192
WIRE 832 240 640 240
WIRE 960 240 944 240
WIRE 992 240 960 240
WIRE 1104 240 1072 240
WIRE 1168 240 1104 240
WIRE 80 272 0 272
WIRE 160 272 160 192
WIRE 160 272 144 272
WIRE -128 288 -128 272
WIRE 80 304 32 304
WIRE 640 304 640 240
WIRE 960 304 960 240
WIRE 1104 304 1104 240
WIRE 32 352 32 304
WIRE 320 352 32 352
WIRE 448 352 320 352
WIRE 576 352 528 352
WIRE 960 400 960 368
WIRE 1104 400 1104 368
WIRE 432 448 320 448
WIRE 640 464 640 400
WIRE 0 496 0 272
WIRE -32 624 -32 144
SYMBOL Digital\\or 112 224 R0
SYMATTR InstName A4
SYMBOL pnp 576 192 M180
SYMATTR InstName Q1
SYMATTR Value 2N3906
SYMBOL cap 1088 304 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL voltage -128 176 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0u 1n 1n 5u 10u)
SYMBOL res 544 336 R90
WINDOW 0 58 98 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
FLAG -128 288 0
FLAG 80 192 0
FLAG 416 96 Vo_LEAD
FLAG 432 448 Vo_LAG
FLAG 80 96 ONE
FLAG 640 32 ONE
FLAG 640 464 0
FLAG 1168 240 Vout
FLAG 416 224 Vo_LEAD_n
FLAG 960 400 0
FLAG 1104 400 0
FLAG -128 144 Vin1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7104-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7104-1.5.asy)
Rload OUT 0 5
R1 OUT N001 100k
V1 IN 0 PWL(0 0 20u 3.3)
XU1 IN OUT IN N001 OUT 0 ADP7104-1.5 ;pnba Vin)Sense)EN)PG)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
.tran 3m startup
.lib ADP7104-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -144 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -144 48 -144 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -144 144 -144 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ADP7104-1.5 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -144 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 20u 3.3)
FLAG 224 304 0
FLAG -144 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -144 32 IN
FLAG 560 128 OUT
TEXT 432 288 Left 2 !.tran 3m startup