* Z:\home\khalils\Downloads\files\data\raw_asc\052d9a592e22_Fig13_34.asc
* Generated by LTspice 26.0.1 for Windows.
M1 B A 0 0 N_50n l=50n w=500n
VDD VDD 0 1
M2 B A VDD VDD P_50n l=50n w=1u
M5 N001 B 0 0 N_50n l=50n w=500n
M6 N001 B VDD VDD P_50n l=50n w=1u
M7 D VDD A 0 N_50n l=50n w=500n
VD D 0 PULSE 0 1 500p 10p 10p 300p
M3 A 0 D VDD P_50n l=50n w=1u
M4 A 0 N001 0 N_50n l=50n w=500n
M8 N001 VDD A VDD P_50n l=50n w=1u
M9 N001 0 N002 0 N_50n l=50n w=500n
M10 N002 VDD N001 VDD P_50n l=50n w=1u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 1n 400p
.include cmosedu_models.txt
* Plot D A+1.25 B+2.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 272 -640 272 -672
WIRE 272 -640 240 -640
WIRE 368 -640 368 -672
WIRE 1008 -640 368 -640
WIRE -48 -608 -48 -624
WIRE 272 -608 272 -640
WIRE 368 -608 368 -640
WIRE -48 -592 -48 -608
WIRE 448 -560 416 -560
WIRE 768 -560 736 -560
WIRE -48 -480 -48 -512
WIRE 240 -448 240 -640
WIRE 352 -448 240 -448
WIRE 416 -448 416 -560
WIRE 416 -448 352 -448
WIRE 496 -448 496 -480
WIRE 640 -448 496 -448
WIRE 736 -448 736 -560
WIRE 736 -448 640 -448
WIRE 816 -448 816 -480
WIRE 1008 -448 1008 -640
WIRE 1008 -448 816 -448
WIRE 1024 -448 1024 -480
WIRE 1024 -448 1008 -448
WIRE 1024 -416 1024 -448
WIRE 1120 -416 1120 -480
WIRE 64 -400 64 -464
WIRE 64 -400 0 -400
WIRE 160 -400 160 -464
WIRE 240 -400 240 -448
WIRE 240 -400 160 -400
WIRE 0 -384 0 -400
WIRE 0 -368 0 -384
WIRE 416 -368 416 -448
WIRE 448 -368 416 -368
WIRE 736 -368 736 -448
WIRE 768 -368 736 -368
WIRE 496 -304 496 -352
WIRE 816 -304 816 -352
WIRE 0 -256 0 -288
FLAG 496 -400 0
FLAG -48 -480 0
FLAG -48 -608 VDD
FLAG 496 -528 VDD
FLAG 496 -304 0
FLAG 496 -576 VDD
FLAG 816 -400 0
FLAG 816 -528 VDD
FLAG 816 -304 0
FLAG 816 -576 VDD
FLAG 112 -400 0
FLAG 0 -400 D
FLAG 0 -256 0
FLAG 0 -384 D
FLAG 112 -464 VDD
FLAG 320 -608 0
FLAG 320 -672 VDD
FLAG 352 -448 A
FLAG 640 -448 B
FLAG 288 -720 VDD
FLAG 144 -352 VDD
FLAG 80 -512 0
FLAG 352 -560 0
FLAG 1072 -416 0
FLAG 1072 -480 VDD
FLAG 1040 -528 VDD
FLAG 1104 -368 0
SYMBOL nmos4 448 -448 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage -48 -608 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 448 -480 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 768 -448 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M5
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 768 -480 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 64 -352 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M7
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 0 -384 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -13 174 Left 2
SYMATTR Value PULSE 0 1 500p 10p 10p 300p
SYMATTR InstName VD
SYMBOL pmos4 160 -512 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 272 -560 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M4
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 368 -720 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M8
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 1024 -368 R270
WINDOW 0 86 42 Invisible 2
WINDOW 3 82 140 Invisible 2
SYMATTR InstName M9
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 1120 -528 R90
WINDOW 0 71 26 Invisible 2
WINDOW 3 75 133 Invisible 2
SYMATTR InstName M10
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
TEXT 544 -216 Left 2 !.tran 0 1n 400p
TEXT 544 -192 Left 2 !.include cmosedu_models.txt
TEXT 232 -696 Right 2 ;Plot D A+1.25 B+2.5