Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\acb9966715a8_twint-filter.asc
* Generated by LTspice 26.0.1 for Windows.
* 60Hz NOTCH FILTER
* INCLUDES
C3 N002 N006 {C1}
C2 N006 IN {C1}
R6 OUT N004 {RQ1}
R3 N005 N006 {R2}
V1 IN 0 AC 1
R4 N003 N005 {Rpot}
C1 N001 N003 {C2}
XU2 N003 N004 N003 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R5 N004 0 {RQ2}
R1 N002 N001 {R1}
XU1 OUT N002 OUT opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R2 N001 IN {R1}
.param Rnotch=5k
.param C1=0.1u
.param C2=2*C1
.ac dec 1000 0.1 10k
.param R1=26.5k
.param R2=(R1/2)-1k
.step param Rpot 0.5k 2k 0.5k
.param RQ1=4k
.param RQ2=26.5k
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1092 680
WIRE 976 64 816 64
WIRE 816 112 816 64
WIRE 848 112 816 112
WIRE 976 128 976 64
WIRE 976 128 912 128
WIRE 1024 128 976 128
WIRE 416 144 384 144
WIRE 432 144 416 144
WIRE 544 144 512 144
WIRE 576 144 544 144
WIRE 672 144 656 144
WIRE 848 144 672 144
WIRE 976 176 976 128
WIRE 544 192 544 144
WIRE 928 224 800 224
WIRE 928 272 928 224
WIRE 928 272 912 272
WIRE 544 288 544 256
WIRE 800 288 800 224
WIRE 800 288 544 288
WIRE 848 288 800 288
WIRE 976 304 976 256
WIRE 976 304 912 304
WIRE 544 320 544 288
WIRE 976 352 976 304
WIRE -272 384 -272 368
WIRE 544 416 544 400
WIRE -272 480 -272 464
WIRE 416 560 416 144
WIRE 448 560 416 560
WIRE 544 560 544 496
WIRE 544 560 512 560
WIRE 576 560 544 560
WIRE 672 560 672 144
WIRE 672 560 640 560
WIRE 976 560 976 432
SYMBOL cap 512 544 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {C1}
SYMBOL Opamps\\opamp 880 64 R0
SYMATTR InstName U1
SYMBOL cap 640 544 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value {C1}
SYMBOL res 960 160 R0
SYMATTR InstName R6
SYMATTR Value {RQ1}
SYMBOL cap 528 192 R0
SYMATTR InstName C1
SYMATTR Value {C2}
SYMBOL res 672 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL res 960 336 R0
SYMATTR InstName R5
SYMATTR Value {RQ2}
SYMBOL res 528 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R1}
SYMBOL voltage -272 368 R0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 528 304 R0
SYMATTR InstName R4
SYMATTR Value {Rpot}
SYMBOL res 528 400 R0
SYMATTR InstName R3
SYMATTR Value {R2}
SYMBOL Opamps\\opamp 880 224 M0
SYMATTR InstName U2
FLAG 976 560 0
FLAG -272 368 IN
FLAG -272 480 0
FLAG 384 144 IN
FLAG 1024 128 OUT
TEXT -448 8 Left 2 !.param Rnotch=5k
TEXT 352 72 Left 2 ;60Hz NOTCH FILTER
TEXT -632 64 Left 2 !.param C1=0.1u\n.param C2=2*C1
TEXT -624 312 Left 2 !.ac dec 1000 0.1 10k
TEXT -400 64 Left 2 !.param R1=26.5k\n.param R2=(R1/2)-1k\n.step param Rpot 0.5k 2k 0.5k
TEXT -400 168 Left 2 !.param RQ1=4k\n.param RQ2=26.5k
TEXT -632 -48 Left 2 !.lib opamp.sub
TEXT -632 -80 Left 2 ;INCLUDES
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2371-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2371-1.2.asy)
C1 OUT 0 10
R1 OUT N001 10K
V1 IN 0 12
Rload OUT 0 20
L1 N002 OUT 10 Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
XU1 NC_01 IN IN IN N002 OUT N001 0 ADP2371-1.2 IPSM=320m Rt=166666 Rb=333333 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=1 ;pnba FSEL)SYNC)EN)Vin)SW)FB)PG)PGND
.tran 500u startup
.lib ADP2371-1.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 936 692
WIRE 144 96 16 96
WIRE 176 96 144 96
WIRE 480 96 400 96
WIRE 688 96 560 96
WIRE 16 112 16 96
WIRE 144 176 144 96
WIRE 176 176 144 176
WIRE 432 176 400 176
WIRE 560 176 512 176
WIRE 688 176 688 96
WIRE 688 176 560 176
WIRE 752 176 688 176
WIRE 752 192 752 176
WIRE 16 208 16 192
WIRE 144 336 144 176
WIRE 560 256 560 240
WIRE 560 256 400 256
WIRE 560 272 560 256
WIRE 752 288 752 272
WIRE 176 336 144 336
WIRE 688 336 688 176
WIRE 688 336 400 336
SYMBOL cap 544 176 R0
WINDOW 0 29 15 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL VOLTAGE 16 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 576 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL ADP2371-1.2 288 208 R0
SYMATTR InstName U1
SYMBOL ind 416 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
SYMBOL res 736 176 R0
SYMATTR InstName Rload
SYMATTR Value 20
FLAG 16 208 0
FLAG 16 96 IN
FLAG 560 272 0
FLAG 752 176 OUT
FLAG 752 288 0
TEXT 504 384 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2934-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2934-1.asy)
R1 N002 N004 11.8K
R5 N001 N003 10K
R2 N004 0 237K
MQ1 N006 N007 0 0 BSS123
R4 N001 N005 10K
R3 N001 N002 750K
V2 N007 0 PWL(0 0 3.999 0 4 5 4.599 5 4.6 0)
V1 N001 0 PULSE(0 3.3 0 3.3 3.3 2)
XU1 N002 N004 N001 0 N003 N005 N006 N001 LTC2934-1 ;pnba ADJ)PFI)RT)GND)_PFO)_RST)_MR)VCC
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10
.lib LTC2934-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 -32 -384 -32
WIRE 240 -32 -48 -32
WIRE 368 -32 240 -32
WIRE 416 -32 368 -32
WIRE 512 -32 416 -32
WIRE -384 -16 -384 -32
WIRE -48 -16 -48 -32
WIRE 416 32 416 -32
WIRE 512 32 512 -32
WIRE 240 48 240 -32
WIRE -384 80 -384 64
WIRE -48 80 -48 64
WIRE 128 80 -48 80
WIRE -48 96 -48 80
WIRE 368 96 368 -32
WIRE 368 96 352 96
WIRE 416 176 416 112
WIRE 416 176 352 176
WIRE -48 192 -48 176
WIRE 128 192 -48 192
WIRE -48 208 -48 192
WIRE 512 256 512 112
WIRE 512 256 352 256
WIRE 128 272 80 272
WIRE 80 288 80 272
WIRE -48 304 -48 288
WIRE 240 336 240 304
WIRE 32 368 -48 368
WIRE -48 384 -48 368
WIRE 80 400 80 384
WIRE -48 480 -48 464
SYMBOL res 496 16 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res -64 80 R0
SYMATTR InstName R1
SYMATTR Value 11.8K
SYMBOL LTC2934-1 240 176 R0
SYMATTR InstName U1
SYMBOL nmos 32 288 R0
SYMATTR InstName Q1
SYMATTR Value BSS123
SYMBOL res 400 16 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL res -64 -32 R0
SYMATTR InstName R3
SYMATTR Value 750K
SYMBOL res -64 192 R0
SYMATTR InstName R2
SYMATTR Value 237K
SYMBOL voltage -384 -32 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0 3.3 3.3 2)
SYMBOL voltage -48 368 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR Value PWL(0 0 3.999 0 4 5 4.599 5 4.6 0)
SYMATTR InstName V2
FLAG -48 304 0
FLAG 240 336 0
FLAG -384 80 0
FLAG 80 400 0
FLAG -48 480 0
TEXT 424 392 Left 2 !.tran 10
* Z:\home\khalils\Downloads\files\data\raw_asc\c336b882f0f0_1997-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain = 1 Difference Amplifier
* V(Out) = 1mV/mA in RL
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1997-3.asy)
RL N001 0 10
R1 N002 N001 1
V1 V+ 0 15
VS N002 0 0
V2 V- 0 -15
R2 N003 N002 1
XU1 N003 MP_01 NC_02 MP_03 NC_04 0 0 V- Out NC_05 V+ NC_06 MP_07 NC_08 MP_09 N001 LT1997-3 ;pnba +INA))+INB))+INC)REF1)REF2)V-)OUT)_SHDN)V+)-INC))-INB))-INA
.dc VS 0 26.5 10m
.lib LT1997-3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1116 932
WIRE 48 48 -16 48
WIRE -272 80 -432 80
WIRE 48 80 48 48
WIRE 400 80 400 48
WIRE -432 112 -432 80
WIRE -272 160 -272 80
WIRE -208 160 -272 160
WIRE -16 160 -16 48
WIRE -16 160 -144 160
WIRE -432 208 -432 192
WIRE 624 208 496 208
WIRE -208 240 -144 160
WIRE -208 240 -272 240
WIRE -144 240 -208 160
WIRE -128 240 -144 240
WIRE -16 240 -48 240
WIRE -272 256 -272 240
WIRE 544 256 496 256
WIRE 544 288 544 256
WIRE 544 288 496 288
WIRE -528 304 -528 288
WIRE -400 304 -400 288
WIRE 544 304 544 288
WIRE -272 352 -272 336
WIRE -16 368 -16 240
WIRE 48 368 48 336
WIRE 48 368 -16 368
WIRE 400 384 400 336
WIRE -528 400 -528 384
WIRE -400 400 -400 384
SYMBOL res -32 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL res -288 240 R0
SYMATTR InstName RL
SYMATTR Value 10
SYMBOL res -288 144 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -528 288 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -400 288 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL LT1997-3 272 208 R0
SYMATTR InstName U1
SYMBOL voltage -432 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VS
SYMATTR Value 0
FLAG -528 400 0
FLAG -400 400 0
FLAG -528 288 V+
FLAG -400 288 V-
FLAG 400 48 V+
FLAG 400 384 V-
FLAG 544 304 0
FLAG -272 352 0
FLAG 624 208 Out
FLAG -432 208 0
TEXT 584 400 Left 2 !.dc VS 0 26.5 10m
TEXT -96 -16 Left 2 ;Gain = 1 Difference Amplifier
TEXT 544 144 Left 2 ;V(Out) = 1mV/mA in RL
* Z:\home\khalils\Downloads\files\data\raw_asc\44cd5ab44f8c_ComplexDiodeModel.asc
* Generated by LTspice 26.0.1 for Windows.
I1 v+ 0 PULSE(0 10 0 1 1) load
V1 illu 0 {illu}
R2 N001 v+ {rs_t}
B1 0 N001 I=Iph_T*v(illu)/1000
R3 illu 0 100Meg
R1 N001 0 {rsh_t}
D1 N001 0 SolarDiode
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
.temp 25
.temp 10 25 40 55 70
.step param illu list 200 400 600 800 1000
.param illu 1000
.param Voc 44.71
.param Isc 8.947
.param Vmp 37.23
.param Imp 8.06
.param Ki 0.0005
.param Kv -0.0034
.param K 1.38e-23
.param e 1.6e-19
.param a 1.3
.param n Voc/0.7
.param a_n a*n
.param voc_t voc*(1-kv*(25-temp))
.param isc_t isc*(1-ki*(25-temp))
.param vmp_t vmp*(1-kv*(25-temp))
.param imp_t imp*(1-ki*(25-temp))
.param rs_t (voc_t-vmp_t)/(16*imp_t)
.param rsh_t (5*vmp_t)/(isc_t-imp_t)
.param iph_t isc_t*(rsh_t+rs_t)/rsh_t
.param v_t (k*(temp+273.15))/e
.model solardiode d(is=io_t N=a_n Tnom=temp)
.param io_t ((rs_t+rsh_t)*isc_t-voc_t)/(rsh_t*exp(voc_t/(a_n*v_t)))
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -112 128 -128 128
WIRE -112 160 -112 128
WIRE -112 160 -192 160
WIRE -96 160 -112 160
WIRE 96 160 -16 160
WIRE 240 160 96 160
WIRE 400 160 240 160
WIRE -112 208 -128 208
WIRE -112 240 -112 208
WIRE -112 240 -192 240
WIRE 96 240 -112 240
WIRE 240 240 240 224
WIRE 240 240 96 240
WIRE 400 240 240 240
WIRE -192 256 -192 240
WIRE 432 320 336 320
WIRE 336 352 336 320
WIRE 432 352 432 320
WIRE 336 448 336 432
WIRE 432 448 432 432
SYMBOL diode 224 160 R0
SYMATTR InstName D1
SYMATTR Value SolarDiode
SYMBOL voltage 336 336 R0
SYMATTR InstName V1
SYMATTR Value {illu}
SYMBOL res 416 336 R0
SYMATTR InstName R3
SYMATTR Value 100Meg
SYMBOL res 80 144 R0
SYMATTR InstName R1
SYMATTR Value {rsh_t}
SYMBOL res 0 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {rs_t}
SYMBOL bi2 400 160 R0
SYMATTR InstName B1
SYMATTR Value I=Iph_T*v(illu)/1000
SYMBOL current -192 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 108 Left 2
SYMATTR SpiceLine load
SYMATTR InstName I1
SYMATTR Value PULSE(0 10 0 1 1)
FLAG -192 256 0
FLAG -128 128 v+
FLAG -128 208 v-
FLAG 336 448 0
FLAG 432 448 0
FLAG 432 320 illu
TEXT -184 -888 Left 2 !.tran 1\n \n.temp 25\n.temp 10 25 40 55 70\n \n.step param illu list 200 400 600 800 1000\n.param illu 1000\n \n.param Voc 44.71\n.param Isc 8.947\n.param Vmp 37.23\n.param Imp 8.06\n.param Ki 0.0005\n.param Kv -0.0034\n.param K 1.38e-23\n.param e 1.6e-19\n.param a 1.3\n.param n Voc/0.7\n.param a_n a*n\n \n.param voc_t voc*(1-kv*(25-temp))\n.param isc_t isc*(1-ki*(25-temp))\n.param vmp_t vmp*(1-kv*(25-temp))\n.param imp_t imp*(1-ki*(25-temp))\n.param rs_t (voc_t-vmp_t)/(16*imp_t)\n.param rsh_t (5*vmp_t)/(isc_t-imp_t)\n.param iph_t isc_t*(rsh_t+rs_t)/rsh_t\n.param v_t (k*(temp+273.15))/e
TEXT -168 56 Left 2 !.model solardiode d(is=io_t N=a_n Tnom=temp)
TEXT -192 -96 Left 2 !.param io_t ((rs_t+rsh_t)*isc_t-voc_t)/(rsh_t*exp(voc_t/(a_n*v_t)))
* Z:\home\khalils\Downloads\files\data\raw_asc\24ec339d7365_Fig6_13_PMOS.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1)
VSD 0 N003 2
VBS N001 0 0
M1 0 N002 N003 N001 P_1u L=1u W=10u
VSG 0 N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSG 0 2 1m VBS 0 5 1
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 688
WIRE 320 96 320 80
WIRE 320 192 320 176
WIRE 400 192 320 192
WIRE 448 80 320 80
WIRE 448 112 448 80
WIRE 448 304 448 208
WIRE 528 160 448 160
WIRE 672 80 448 80
WIRE 672 160 608 160
WIRE 672 160 672 80
WIRE 672 208 672 160
WIRE 672 304 448 304
WIRE 672 304 672 288
WIRE 720 80 672 80
WIRE 720 112 720 80
SYMBOL pmos4 400 112 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 L=1u W=10u
SYMATTR InstName M1
SYMATTR Value P_1u
SYMBOL voltage 320 80 R0
WINDOW 0 -89 56 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VSG
SYMATTR Value 0
SYMBOL voltage 512 160 M90
WINDOW 0 -32 56 VBottom 0
WINDOW 3 46 56 Invisible 0
SYMATTR InstName VBS
SYMATTR Value 0
SYMBOL voltage 672 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 41 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VSD
SYMATTR Value 2
FLAG 720 112 0
TEXT 424 336 Left 0 !.dc VSG 0 2 1m VBS 0 5 1
TEXT 424 360 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot Id(M1)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4219-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4219-12.asy)
V1 IN 0 12
C2 OUT 0 330
C1 N004 0 .1
R1 N003 0 20K
S1 0 OUT N001 0 SHORT
XU1 NC_01 IN 0 0 N004 N004 0 OUT MP_02 MP_03 MP_04 MP_05 NC_06 N002 NC_07 NC_08 N003 NC_09 LTC4219-12 ;pnba Sense)Vdd)_EN1)_EN2)Timer)IntVcc)GND)Out)))))Gate)_PG)_FLT)FB)Imon)Iset
R2 OUT N002 20K
V2 N001 0 PULSE(0 1 240m 1m 1m 10m)
.tran 600m startup
.model SHORT SW(Ron=10m Roff=1K Vt=.5 Vh=-.4)
.lib LTC4219-12.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1592 680
WIRE 80 16 -48 16
WIRE 416 16 368 16
WIRE 512 16 416 16
WIRE 624 16 512 16
WIRE -48 32 -48 16
WIRE 416 32 416 16
WIRE 512 32 512 16
WIRE 624 32 624 16
WIRE 848 48 672 48
WIRE 944 48 928 48
WIRE 80 80 48 80
WIRE -48 128 -48 112
WIRE 512 128 512 96
WIRE 624 128 624 112
WIRE 80 144 48 144
WIRE 416 144 416 112
WIRE 416 144 368 144
WIRE 384 208 368 208
WIRE 480 208 464 208
WIRE 432 272 368 272
WIRE 432 336 432 272
WIRE 432 336 368 336
WIRE 432 352 432 336
WIRE 224 400 224 384
WIRE 432 432 432 416
SYMBOL res 368 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 20K
SYMBOL sw 624 128 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SHORT
SYMBOL LTC4219-12 224 176 R0
SYMATTR InstName U1
SYMBOL res 400 16 R0
SYMATTR InstName R2
SYMATTR Value 20K
SYMBOL voltage 832 48 R270
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 240m 1m 1m 10m)
SYMBOL cap 496 32 R0
SYMATTR InstName C2
SYMATTR Value 330
SYMBOL voltage -48 16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 416 352 R0
SYMATTR InstName C1
SYMATTR Value .1
FLAG 432 432 0
FLAG 224 400 0
FLAG 480 208 0
FLAG -48 128 0
FLAG 512 128 0
FLAG 624 128 0
FLAG 672 96 0
FLAG 944 48 0
FLAG -48 16 IN
FLAG 624 16 OUT
FLAG 48 80 0
FLAG 48 144 0
TEXT 560 296 Left 2 !.tran 600m startup\n.model SHORT SW(Ron=10m Roff=1K Vt=.5 Vh=-.4)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7182-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7182-3.0.asy)
R1 OUT 0 50
V1 IN 0 -8
V2 N001 0 PULSE(0 2 200u 1n 1n 10m)
C1 IN 0 2.2
XU1 OUT MP_01 MP_02 N001 MP_03 0 IN ADP7182-x.x Rset=600k ;pnba Vout)))EN))GND)Vin
C2 OUT 0 2.2
.tran 1m
.lib ADP7182-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 -80 -48
WIRE 112 -48 32 -48
WIRE 432 -48 368 -48
WIRE 544 -48 432 -48
WIRE -80 -32 -80 -48
WIRE 32 -32 32 -48
WIRE 432 -32 432 -48
WIRE 544 -32 544 -48
WIRE -80 64 -80 48
WIRE 32 64 32 32
WIRE 432 64 432 32
WIRE 544 64 544 48
WIRE 112 144 32 144
WIRE 32 160 32 144
WIRE 32 256 32 240
WIRE 240 256 240 208
SYMBOL ADP7182-3.0 240 48 R0
SYMATTR InstName U1
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL cap 16 -32 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value -8
SYMBOL voltage 32 144 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
SYMBOL res 528 -48 R0
SYMATTR InstName R1
SYMATTR Value 50
FLAG -80 64 0
FLAG 32 64 0
FLAG 432 64 0
FLAG 32 256 0
FLAG 240 256 0
FLAG 544 64 0
FLAG 32 -48 IN
FLAG 432 -48 OUT
TEXT 528 248 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\54b6f076569f_nand.asc
* Generated by LTspice 26.0.1 for Windows.
M3 N001 B 0 0 NMOS l=200n w=1u
M4 VDD A OUT VDD PMOS l=200n w=1.5u
M2 VDD B OUT VDD PMOS l=200n w=1.5u
M1 OUT A N001 0 NMOS l=200n w=1u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 -32 272 -112
WIRE 336 -32 272 -32
WIRE 32 -16 32 -112
WIRE 96 -16 32 -16
WIRE 272 -16 272 -32
WIRE 32 0 32 -16
WIRE 336 32 336 -32
WIRE 336 32 272 32
WIRE 96 48 96 -16
WIRE 96 48 32 48
WIRE 224 64 176 64
WIRE -16 80 -48 80
WIRE 32 128 32 96
WIRE 272 128 272 80
WIRE 272 128 32 128
WIRE 272 160 272 128
WIRE 560 160 272 160
WIRE 272 192 272 160
WIRE 400 240 272 240
WIRE 400 256 400 240
WIRE 224 272 128 272
WIRE 272 336 272 288
WIRE 400 384 272 384
WIRE 400 400 400 384
WIRE 224 416 128 416
WIRE 272 480 272 432
IOPIN 32 -112 In
IOPIN 272 -112 In
IOPIN 128 272 In
IOPIN -48 80 In
IOPIN 176 64 In
IOPIN 128 416 In
IOPIN 560 160 Out
SYMBOL nmos4 224 192 R0
SYMATTR InstName M1
SYMATTR Value2 l=200n w=1u
SYMBOL pmos4 -16 0 R0
SYMATTR InstName M4
SYMATTR Value2 l=200n w=1.5u
SYMBOL nmos4 224 336 R0
SYMATTR InstName M3
SYMATTR Value2 l=200n w=1u
SYMBOL pmos4 224 -16 R0
SYMATTR InstName M2
SYMATTR Value2 l=200n w=1.5u
FLAG 400 256 0
FLAG 400 400 0
FLAG 272 480 0
FLAG 32 -112 VDD
FLAG 272 -112 VDD
FLAG 128 272 A
FLAG -48 80 A
FLAG 176 64 B
FLAG 128 416 B
FLAG 560 160 OUT
* Z:\tmp\asc_dec_bjh7r6w2\01b96876ad50_003-difference-amplifier_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N005 0 -15
R4 0 N004 5k
V4 Vin+ 0 SINE(0 0.2 50 {1/50/2})
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 112 48 112
WIRE 320 112 160 112
WIRE 208 192 208 -96
WIRE -64 208 -464 208
WIRE 48 208 48 112
WIRE 48 208 16 208
WIRE 176 208 48 208
WIRE 320 224 320 112
WIRE 320 224 240 224
WIRE 384 224 320 224
WIRE 176 240 96 240
WIRE -64 288 -240 288
WIRE 96 288 96 240
WIRE 96 288 16 288
WIRE -240 320 -240 288
WIRE 96 320 96 288
WIRE 208 320 208 256
WIRE -240 336 -240 320
WIRE 96 432 96 400
WIRE 208 432 208 400
WIRE -240 448 -240 416
SYMBOL voltage 208 304 R0
SYMATTR InstName V1
SYMATTR Value -15
SYMBOL res 112 416 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 5k
SYMBOL voltage -240 320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value SINE(0 0.2 50 {1/50/2})
FLAG 208 432 0
FLAG 384 224 Vout
FLAG 96 432 0
FLAG -240 320 Vin+
FLAG -240 448 0
* Z:\home\khalils\Downloads\files\data\raw_asc\430af1d5518a_Draft1_copy.asc
* Generated by LTspice 26.0.1 for Windows.
* .ac oct 10K 100K 500000K
D1 0 Limiter_Output 1N4148
RL1 Vout 0 50
C2 Vout 0 0.3979nC
C1 Limiter_Output 0 0.3979nC
R1 Limiter_Output RX_SIG 50
C3 Vout N001 0.0994787nC
L2 Vout 0 497.39nH
L3 Limiter_Output 0 497.39nH
L1 N001 Limiter_Output 1989.55nH
VAntenna RX_SIG 0 SINE(0 5 10000000) AC 0
D2 Limiter_Output 0 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5us
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1440 680
WIRE 80 240 -16 240
WIRE 256 240 160 240
WIRE 864 240 256 240
WIRE 912 240 864 240
WIRE 1040 240 992 240
WIRE 1152 240 1104 240
WIRE 1312 240 1152 240
WIRE -16 288 -16 240
WIRE 256 288 256 240
WIRE 256 288 208 288
WIRE 288 288 256 288
WIRE 864 288 864 240
WIRE 864 288 800 288
WIRE 1152 288 1152 240
WIRE 1152 288 1104 288
WIRE 1312 288 1312 240
WIRE 864 304 864 288
WIRE 1152 304 1152 288
WIRE 256 352 208 352
WIRE 288 352 256 352
WIRE 864 368 800 368
WIRE 1152 368 1104 368
WIRE -16 400 -16 368
WIRE 128 400 -16 400
WIRE 256 400 256 352
WIRE 256 400 128 400
WIRE 864 416 864 368
WIRE 912 416 864 416
WIRE 1152 416 1152 368
WIRE 1152 416 912 416
WIRE 1312 416 1312 368
WIRE 1312 416 1152 416
SYMBOL Cap 1104 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 0.0994787nC
SYMBOL Voltage -16 272 R0
WINDOW 123 24 118 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName Antenna
SYMATTR Value SINE(0 5 10000000)
SYMBOL Cap 848 304 R0
SYMATTR InstName C1
SYMATTR Value 0.3979nC
SYMBOL Ind 784 272 R0
WINDOW 0 -43 38 Left 2
WINDOW 3 -55 81 Left 2
SYMATTR InstName L3
SYMATTR Value 497.39nH
SYMBOL Res 176 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL Res 1296 272 R0
SYMATTR InstName RL1
SYMATTR Value 50
SYMBOL Cap 1136 304 R0
SYMATTR InstName C2
SYMATTR Value 0.3979nC
SYMBOL diode 272 288 R0
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL diode 224 352 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL ind 1088 272 R0
WINDOW 0 -31 35 Left 2
WINDOW 3 -51 86 Left 2
SYMATTR InstName L2
SYMATTR Value 497.39nH
SYMBOL Ind 1008 224 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 1989.55nH
FLAG 128 400 0
FLAG 256 240 Limiter_Output
FLAG -16 240 RX_SIG
FLAG 912 416 0
FLAG 1312 240 Vout
TEXT 368 464 Left 2 ;.ac oct 10K 100K 500000K
TEXT 368 536 Left 2 !.tran 5us
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7157-02.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7157-02.asy)
C3 OUT 0 10
R3 IN N001 100K
XU1 OUT MP_01 OUT N002 N001 N005 N003 N004 IN 0 ADP7157-02 Vreg=2.611 Vref=1.216 ;pnba Vout))Vout_Sense)Byp)EN)Ref_Sense)Ref)Vreg)Vin)GND
R1 N003 N005 66.5K
C4 N003 0 1
C1 N004 0 1
R4 OUT 0 2
C2 N002 0 1
V1 IN 0 3
R2 N005 0 100K
.tran 5m startup
.lib ADP7157-02.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -144 32
WIRE 80 32 -32 32
WIRE 416 32 400 32
WIRE 464 32 416 32
WIRE 560 32 464 32
WIRE -144 48 -144 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE 416 128 416 32
WIRE 416 128 400 128
WIRE -144 144 -144 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 0 224 -16 224
WIRE 80 224 64 224
WIRE 464 224 400 224
WIRE 560 224 464 224
WIRE 464 240 464 224
WIRE 560 240 560 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 432 320 400 320
WIRE 560 320 560 304
WIRE 432 336 432 320
WIRE 464 336 464 320
WIRE 464 336 432 336
WIRE 464 352 464 336
WIRE 240 400 240 384
WIRE 464 448 464 432
SYMBOL voltage -144 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL ADP7157-02 240 176 R0
SYMATTR InstName U1
SYMBOL res 544 32 R0
SYMATTR InstName R4
SYMATTR Value 2
SYMBOL res 448 336 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 448 224 R0
SYMATTR InstName R1
SYMATTR Value 66.5K
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 448 48 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL cap 544 240 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
FLAG 240 400 0
FLAG 560 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG -16 224 0
FLAG -144 144 0
FLAG 560 144 0
FLAG 464 448 0
FLAG -144 32 IN
FLAG 560 32 OUT
TEXT 552 400 Left 2 !.tran 5m startup