Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2164-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 OUT 1 Rser=6m
R4 N003 0 45.3K
V1 IN 0 5
Rload OUT 0 1
R3 OUT N004 100K
R5 IN N001 10
C3 OUT 0 60 Rser=2m
C1 N001 0 100n
XU1 N001 N003 IN OUT 0 0 N002 IN N001 N001 N004 ADP2164-x.x Rtop=818K Rbot=182K ;pnba Sync)Rt)TRK)FB)GND)PGND)SW)Pvin)Vin)EN)Pgood
.tran 2m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2164-3.3.asy)
.lib ADP2164-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 728
WIRE -64 -112 -288 -112
WIRE 176 -112 -64 -112
WIRE 384 -112 176 -112
WIRE -288 -96 -288 -112
WIRE -64 -96 -64 -112
WIRE 176 -80 176 -112
WIRE -288 0 -288 -16
WIRE -144 0 -160 0
WIRE -64 0 -64 -16
WIRE -64 0 -80 0
WIRE 0 0 -64 0
WIRE 384 0 384 -112
WIRE 384 0 352 0
WIRE -64 112 -64 0
WIRE 0 112 -64 112
WIRE 384 112 352 112
WIRE 496 112 464 112
WIRE 576 112 496 112
WIRE 672 112 576 112
WIRE 576 128 576 112
WIRE 672 128 672 112
WIRE -64 224 -64 112
WIRE 0 224 -64 224
WIRE 496 224 496 112
WIRE 496 224 352 224
WIRE 576 224 576 192
WIRE 672 224 672 208
WIRE -96 368 -112 368
WIRE 0 368 -16 368
WIRE 384 368 352 368
WIRE 496 368 496 224
WIRE 496 368 464 368
WIRE 112 496 112 480
WIRE 240 496 240 480
FLAG 112 496 0
FLAG -112 368 0
FLAG -288 0 0
FLAG 576 224 0
FLAG 672 224 0
FLAG 672 112 OUT
FLAG -288 -112 IN
FLAG 240 496 0
FLAG -160 0 0
SYMBOL ind 368 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=6m
SYMBOL res 0 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 45.3K
SYMBOL voltage -288 -112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 656 112 R0
SYMATTR InstName Rload
SYMATTR Value 1
SYMBOL res 480 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res -80 -112 R0
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL cap 560 128 R0
SYMATTR InstName C3
SYMATTR Value 60
SYMATTR SpiceLine Rser=2m
SYMBOL cap -80 16 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL ADP2164-3.3 176 192 R0
SYMATTR InstName U1
TEXT 488 432 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\a1b4efda2280_PMOS.asc
* Generated by LTspice 26.0.1 for Windows.
Vsupply vdd N003 {vdd}
C1 N002 N003 2p
R1 N001 N004 R
V2 N004 0 PULSE(0 {Vdd} 0 15n 15n 100n 200n)
M1 N002 N001 N003 N003 PMOS
M2 vdd N001 N002 N002 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.param vdd=5
.tran 300n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 -16 48 -16
WIRE 320 -16 176 -16
WIRE 272 64 240 64
WIRE 240 112 240 64
WIRE 240 112 192 112
WIRE 320 112 320 80
WIRE 464 112 320 112
WIRE 48 144 48 -16
WIRE 192 160 192 112
WIRE 320 160 320 112
WIRE 464 160 464 112
WIRE 240 240 240 112
WIRE 272 240 240 240
WIRE 48 288 48 224
WIRE 320 288 320 256
WIRE 320 288 48 288
WIRE 464 288 464 224
WIRE 464 288 320 288
WIRE 192 320 192 240
FLAG 192 400 0
FLAG 176 -16 vdd
SYMBOL voltage 48 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vsupply
SYMATTR Value {vdd}
SYMBOL cap 448 160 R0
SYMATTR InstName C1
SYMATTR Value 2p
SYMBOL res 176 144 R0
SYMATTR InstName R1
SYMBOL voltage 192 304 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 {Vdd} 0 15n 15n 100n 200n)
SYMBOL pmos 272 160 R0
SYMATTR InstName M1
SYMBOL pmos 272 -16 R0
SYMATTR InstName M2
TEXT 560 248 Left 2 !.param vdd=5
TEXT 560 288 Left 2 !.tran 300n
* Z:\tmp\asc_dec_bjh7r6w2\18002efd7322_Collpits_basico_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 8 6 7 0 MRF9411
C3 6 N001 10n
R2 8 6 18k
C2 7 0 11p
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1440 1008
WIRE 944 144 848 144
WIRE 1008 144 944 144
WIRE 1056 144 1008 144
WIRE 1056 160 1056 144
WIRE 848 192 848 144
WIRE 944 272 944 144
WIRE 1056 272 1056 240
WIRE 512 288 384 288
WIRE 656 288 512 288
WIRE 704 288 656 288
WIRE 384 320 384 288
WIRE 512 320 512 288
WIRE 656 320 656 288
WIRE 704 320 704 288
WIRE 800 320 704 320
WIRE 848 320 848 272
WIRE 848 320 800 320
WIRE 880 320 848 320
WIRE 512 400 512 384
WIRE 656 400 656 384
WIRE 752 400 656 400
WIRE 800 400 752 400
WIRE 944 400 944 368
WIRE 944 400 800 400
WIRE 656 448 656 400
WIRE 752 448 752 400
WIRE 944 448 944 400
WIRE 384 464 384 384
WIRE 512 544 512 480
WIRE 512 544 384 544
WIRE 656 544 656 512
WIRE 656 544 512 544
WIRE 752 544 752 528
WIRE 752 544 656 544
WIRE 848 560 848 320
WIRE 752 576 752 544
SYMBOL npn 880 272 R0
SYMATTR InstName Q1
SYMATTR Value MRF9411
SYMBOL cap 496 320 R0
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL res 832 176 R0
SYMATTR InstName R2
SYMATTR Value 18k
SYMBOL cap 640 448 R0
SYMATTR InstName C2
SYMATTR Value 11p
FLAG 800 320 6
FLAG 800 400 7
FLAG 1056 272 0
FLAG 752 576 0
FLAG 1008 144 8
* Z:\home\khalils\Downloads\files\data\raw_asc\2a806008e5b7_1992-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1992-1.asy)
R4 N005 N006 30K
R2 N003 N002 30K
V2 -V 0 0
C1 N003 0 10p
R1 N002 N001 30K
R3 N006 N007 30K
V3 N001 N007 SINE(0 0.5 10K)
V1 +V 0 2.7
C2 N005 0 10p
XU1 N002 N004 +V N003 N005 -V N004 N006 LTC1992-1 ;pnba IN-)VOCM)V+)OUT+)OUT-)V-)VMID)IN+
.tran 1m
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 768
WIRE 16 336 -48 336
WIRE 192 336 96 336
WIRE 320 336 192 336
WIRE 432 336 400 336
WIRE 496 368 496 352
WIRE 240 400 240 384
WIRE -272 432 -272 400
WIRE -160 432 -160 400
WIRE -48 432 -48 336
WIRE 192 432 192 336
WIRE 208 432 192 432
WIRE 432 448 432 336
WIRE 432 448 368 448
WIRE 496 448 496 432
WIRE 496 448 432 448
WIRE 208 464 192 464
WIRE 192 496 192 464
WIRE 208 496 192 496
WIRE 432 512 368 512
WIRE 496 512 432 512
WIRE 208 528 192 528
WIRE 496 528 496 512
WIRE -272 544 -272 512
WIRE -160 544 -160 512
WIRE 240 576 240 560
WIRE 496 608 496 592
WIRE -48 624 -48 512
WIRE 16 624 -48 624
WIRE 192 624 192 528
WIRE 192 624 96 624
WIRE 304 624 192 624
WIRE 432 624 432 512
WIRE 432 624 384 624
SYMBOL cap 480 528 R0
SYMATTR InstName C2
SYMATTR Value 10p
SYMBOL voltage -48 416 R0
WINDOW 123 40 100 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 0.5 10K)
SYMBOL voltage -272 416 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.7
SYMBOL res 400 608 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 30K
SYMBOL res 112 608 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 30K
SYMBOL res 416 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 30K
SYMBOL cap 480 432 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL res 112 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 30K
SYMBOL LTC1992-1 272 480 R0
SYMATTR InstName U1
SYMBOL voltage -160 416 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 0
FLAG -272 544 0
FLAG -160 544 0
FLAG -272 400 +V
FLAG -160 400 -V
FLAG 496 352 0
FLAG 496 608 0
FLAG 240 384 +V
FLAG 240 576 -V
TEXT 608 576 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\112b125786ee_Controlled_Cap_non_phys.asc
* Generated by LTspice 26.0.1 for Windows.
* Non Charge-preserving (non physical) Voltage Controlled Capacitors
* C=Cref*V(ctrl)
* C=Lref*V(ctrl)
* (usable e.g. for simulation of a depot of shares. C=price/share charge=$$)
Bc1 c1 0 I=V(ctrl)*I(Vs)-I(Vs)
I2 0 c2 PULSE(0 1 10n 10n 10n 999)
Cref c1 P001 1
Vs P001 0 0
Rdummy c2 0 1G
Bc2 c2 0 I=V(x1)*V(ctrl)
I1 0 c1 PULSE(0 1 10n 10n 10n 999)
Vctrl ctrl 0 PULSE(1 2 1 10n 10n)
Lref x1 0 1 Rser=0
G1 0 x1 c2 0 1
.tran 2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 -176 -128 -176
WIRE 432 -176 -32 -176
WIRE 560 -176 432 -176
WIRE -32 -144 -32 -176
WIRE 432 -96 432 -176
WIRE -32 -32 -32 -64
WIRE -368 0 -432 0
WIRE -432 32 -432 0
WIRE -160 96 -256 96
WIRE 96 96 -160 96
WIRE 432 96 96 96
WIRE 560 96 432 96
WIRE -32 144 -112 144
WIRE -256 176 -256 96
WIRE -112 176 -112 144
WIRE -32 176 -32 144
WIRE 96 176 96 96
WIRE 432 176 432 96
WIRE -160 192 -160 96
RECTANGLE Normal 208 0 -208 -192
RECTANGLE Normal 224 320 -288 48
SYMBOL cap -144 -176 R0
WINDOW 3 23 53 Left 0
WINDOW 0 35 20 Left 0
SYMATTR Value 1
SYMATTR InstName Cref
SYMBOL current 432 -16 R180
WINDOW 0 24 88 Left 0
WINDOW 3 -135 -37 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(0 1 10n 10n 10n 999)
SYMBOL g -112 160 R0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL bi -32 -144 R0
WINDOW 3 13 86 Left 0
SYMATTR Value I=V(ctrl)*I(Vs)-I(Vs)
SYMATTR InstName Bc1
SYMBOL voltage -128 -128 R0
WINDOW 0 -52 17 Left 0
WINDOW 3 -53 52 Left 0
SYMATTR InstName Vs
SYMATTR Value 0
SYMBOL current 432 256 R180
WINDOW 0 24 88 Left 0
WINDOW 3 -141 -37 Left 0
SYMATTR InstName I2
SYMATTR Value PULSE(0 1 10n 10n 10n 999)
SYMBOL voltage -432 16 R0
WINDOW 0 29 36 Left 0
WINDOW 3 -99 135 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vctrl
SYMATTR Value PULSE(1 2 1 10n 10n)
SYMBOL res -272 160 R0
WINDOW 0 -8 131 Left 0
SYMATTR InstName Rdummy
SYMATTR Value 1G
SYMBOL ind -48 160 R0
WINDOW 39 39 95 Left 0
WINDOW 3 41 66 Left 0
SYMATTR SpiceLine Rser=0
SYMATTR InstName Lref
SYMATTR Value 1
SYMBOL bi 96 176 R0
WINDOW 3 -58 125 Left 0
SYMATTR InstName Bc2
SYMATTR Value I=V(x1)*V(ctrl)
FLAG -112 256 0
FLAG -32 256 0
FLAG 96 256 0
FLAG -160 240 0
FLAG -32 144 x1
FLAG 560 96 c2
FLAG -432 112 0
FLAG -368 0 ctrl
FLAG 432 256 0
FLAG -256 256 0
FLAG -32 -32 0
FLAG -128 -32 0
FLAG 560 -176 c1
FLAG 432 -16 0
TEXT -412 -264 Left 0 !.tran 2
TEXT -248 -272 Left 0 ;Non Charge-preserving (non physical) Voltage Controlled Capacitors
TEXT 32 -112 Left 0 ;C=Cref*V(ctrl)
TEXT -96 72 Left 0 ;C=Lref*V(ctrl)
TEXT -256 -232 Left 0 ;(usable e.g. for simulation of a depot of shares. C=price/share charge=$$)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4077-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4077-1.asy)
V2 -V 0 -15
XU1 IN N001 +V -V OUT ADA4077-1 ;pnba In+)In-)V+)V-)OUT
Rload OUT 0 10K
Vin IN 0 SINE(0 1 10K)
R2 OUT N001 10K
V1 +V 0 15
R1 N001 0 10K
.tran 1m
.lib ADA4077-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 128 -1120 128 -1136
WIRE 240 -1120 240 -1136
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 128 -1024 128 -1040
WIRE 240 -1024 240 -1040
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL ADA4077-1 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 240 -1136 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 128 -1136 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
FLAG 128 -1136 +V
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 240 -1136 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 768 -992 0
FLAG 240 -1024 0
FLAG 128 -1024 0
TEXT 784 -896 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\f0bda7996e02_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T2 0 0 N002 0 Td=50n Z0=150
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T1 N001 0 0 N002 Td=50n Z0=50
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=50n Z0=150
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\302d67aaa474_Display_output_circuit.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
R2 N006 0 1k
R1 N001 N006 1k
R3 N004 N005 33k
V1 N001 0 3.3
XU2 N004 N003 N001 0 N003 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V_IN N002 0 SINE(0 1.5 50)
XU1 N006 N005 N001 0 N005 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
C1 N004 N002 10n
.tran 20s
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 -336 -368 -336
WIRE 80 -256 -32 -256
WIRE 336 -256 192 -256
WIRE 256 -208 256 -336
WIRE 192 -192 192 -256
WIRE 224 -192 192 -192
WIRE 336 -176 336 -256
WIRE 336 -176 288 -176
WIRE 416 -176 336 -176
WIRE 80 -160 80 -256
WIRE 96 -160 80 -160
WIRE 192 -160 160 -160
WIRE 224 -160 192 -160
WIRE -368 -128 -368 -336
WIRE -224 -128 -368 -128
WIRE 0 -128 -224 -128
WIRE 64 -112 -64 -112
WIRE -368 -80 -368 -128
WIRE 0 -64 0 -128
WIRE -64 -48 -64 -112
WIRE -32 -48 -64 -48
WIRE 64 -32 64 -112
WIRE 64 -32 32 -32
WIRE 192 -32 192 -80
WIRE 192 -32 64 -32
WIRE -224 -16 -224 -48
WIRE -32 -16 -224 -16
WIRE -224 16 -224 -16
SYMBOL res -240 0 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -368 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res -240 -144 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 160 -176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL OpAmps\\UniversalOpAmp2 256 -176 R0
SYMATTR InstName U2
SYMBOL res 176 -176 R0
SYMATTR InstName R3
SYMATTR Value 33k
SYMBOL voltage -32 -272 R0
WINDOW 0 -102 12 Left 2
WINDOW 3 -216 70 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V_IN
SYMATTR Value SINE(0 1.5 50)
SYMBOL OpAmps\\UniversalOpAmp2 0 -32 R0
SYMATTR InstName U1
FLAG -224 96 0
FLAG -368 0 0
FLAG 0 0 0
FLAG 256 -144 0
FLAG -32 -176 0
TEXT -402 120 Left 2 !.tran 20s
* Z:\tmp\asc_dec_bjh7r6w2\0ee497f66acf_Design_A_Transistor_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
D2 N001 N002 NSPW500BS
Vcontrol_1 Vcontrol 0 5V
Rc Vcc N001 150
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 3268 680
WIRE 400 -160 400 -224
WIRE 400 -32 400 -80
WIRE 400 -32 304 -32
WIRE 496 -32 400 -32
WIRE 304 0 304 -32
WIRE 496 0 496 -32
WIRE 304 96 304 64
WIRE 400 96 304 96
WIRE 496 96 400 96
WIRE -704 144 -704 80
WIRE 400 144 400 96
WIRE -544 160 -544 96
WIRE 336 192 96 192
WIRE -704 256 -704 224
WIRE -544 272 -544 240
SYMBOL LED 288 0 R0
WINDOW 0 -27 3 Left 2
WINDOW 3 -133 58 Left 2
SYMATTR InstName D2
SYMATTR Value NSPW500BS
SYMBOL voltage -544 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcontrol_1
SYMATTR Value 5V
SYMBOL res 384 -176 R0
SYMATTR InstName Rc
SYMATTR Value 150
FLAG 400 -224 Vcc
FLAG -704 256 0
FLAG -704 80 Vcc
FLAG -544 272 0
FLAG -544 96 Vcontrol
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1028A.asc
* Generated by LTspice 26.0.1 for Windows.
* Phono Preamplifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1028A.asy)
V3 IN 0 ac 1
C2 OUT N002 .33
R2 N001 0 10
R1 OUT N001 10K
V2 -V 0 -15
C3 IN 0 100p
C1 N002 N001 .1
V1 +V 0 15
R4 IN 0 47K
XU1 IN N001 +V -V OUT LT1028 ;pnba In+)In-)V+)V-)OUT
R3 N002 N001 787
.ac oct 10 10 20K
.lib LT1028.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 128 -48 96 -48
WIRE 240 -48 208 -48
WIRE -256 32 -256 16
WIRE -128 32 -128 16
WIRE 96 48 96 -48
WIRE 144 48 96 48
WIRE 240 48 240 -48
WIRE 240 48 208 48
WIRE 256 48 240 48
WIRE 336 48 320 48
WIRE -256 128 -256 112
WIRE -128 128 -128 112
WIRE 0 144 -16 144
WIRE 96 144 96 48
WIRE 96 144 80 144
WIRE 208 144 96 144
WIRE 336 144 336 48
WIRE 336 144 288 144
WIRE 192 208 192 192
WIRE 96 224 96 144
WIRE 160 224 96 224
WIRE 336 240 336 144
WIRE 336 240 224 240
WIRE 384 240 336 240
WIRE 0 256 -112 256
WIRE 96 256 0 256
WIRE 160 256 96 256
WIRE -112 272 -112 256
WIRE 0 272 0 256
WIRE 96 272 96 256
WIRE 192 288 192 272
WIRE -112 368 -112 352
WIRE 0 368 0 352
WIRE 96 368 96 336
SYMBOL res 304 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 224 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 787
SYMBOL cap 208 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL voltage -256 16 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res -16 256 R0
SYMATTR InstName R4
SYMATTR Value 47K
SYMBOL voltage -112 256 R0
SYMATTR InstName V3
SYMATTR Value ac 1
SYMBOL cap 320 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .33
SYMBOL voltage -128 16 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL opamps\\LT1028A 192 176 R0
SYMATTR InstName U1
SYMBOL cap 80 272 R0
SYMATTR InstName C3
SYMATTR Value 100p
SYMBOL res 96 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
FLAG -128 128 0
FLAG 192 192 +V
FLAG -128 16 +V
FLAG 192 288 -V
FLAG -256 128 0
FLAG -256 16 -V
FLAG -16 144 0
FLAG -112 368 0
FLAG 96 368 0
FLAG 0 368 0
FLAG -112 256 IN
FLAG 384 240 OUT
TEXT 200 360 Left 2 !.ac oct 10 10 20K
TEXT 40 -88 Bottom 2 ;Phono Preamplifier
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-2.85.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-2.85.asy)
C1 IN 0 1
C2 OUT 0 1
Rload OUT 0 100
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=42553.2 ;pnba Vout))Sense)GND)En)))Vin
V1 IN 0 5.5
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL ADP124-2.85 256 208 R0
SYMATTR InstName U1
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\3b9164f95d34_Noninverting_Summer.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
R3 N001 0 10k
R4 out N001 10k
V4 N004 0 2
R2 N002 N004 10k
R1 N002 N003 10k
XU1 N002 N001 vcc vee out level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V2 vee 0 -15
V3 N003 0 1
V1 vcc 0 15
.tran 5m
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -80 0 -112 0
WIRE 32 0 0 0
WIRE 112 0 32 0
WIRE 256 0 192 0
WIRE 160 80 144 80
WIRE -112 112 -112 0
WIRE 160 112 160 80
WIRE 32 128 32 0
WIRE 128 128 32 128
WIRE 256 144 256 0
WIRE 256 144 192 144
WIRE 320 144 256 144
WIRE 128 160 32 160
WIRE -96 224 -336 224
WIRE 32 224 32 160
WIRE 32 224 -16 224
WIRE 160 224 160 176
WIRE 160 224 144 224
WIRE -336 240 -336 224
WIRE 416 288 384 288
WIRE 544 288 512 288
WIRE -96 320 -224 320
WIRE 32 320 32 224
WIRE 32 320 -16 320
WIRE 416 336 416 288
WIRE 544 336 544 288
WIRE -336 352 -336 320
WIRE -224 352 -224 320
WIRE 416 448 416 416
WIRE 544 448 544 416
WIRE -224 464 -224 432
SYMBOL voltage 544 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -224 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 2
SYMBOL res 0 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL OpAmps\\UniversalOpAmp2 160 144 R0
SYMATTR InstName U1
SYMBOL voltage 416 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 16 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 0 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 208 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL voltage -336 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 1
FLAG 416 448 0
FLAG 544 448 0
FLAG 384 288 vcc
FLAG 512 288 vee
FLAG 144 80 vcc
FLAG 144 224 vee
FLAG 320 144 out
FLAG -336 352 0
FLAG -224 464 0
FLAG -112 112 0
TEXT 224 456 Left 2 !.tran 5m