Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1706-82.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1706-82.asy)
V2 N007 0 .8
V3 N002 0 PULSE(0 2.4 0 1n 1n .5m 1m)
XU1 N005 N006 N001 0 N004 OUT N002 N003 N008 LTC1706-82 ;pnba VID2)VID3)Vcc)GND)FB)Sense)VID0)VID1)VID4
G1 0 OUT N007 N004 1
C1 OUT 0 .1
V1 N001 0 3.3
V6 N006 0 PULSE(0 2.4 0 1n 1n 4m 8m)
V5 N005 0 PULSE(0 2.4 0 1n 1n 2m 4m)
V7 N008 0 PULSE(0 2.4 0 1n 1n 8m 16m)
V4 N003 0 PULSE(0 2.4 0 1n 1n 1m 2m)
.tran 16m
.lib LTC1706-82.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2536 1332
WIRE 944 736 864 736
WIRE 1328 736 944 736
WIRE 864 752 864 736
WIRE 1168 784 1008 784
WIRE 1008 800 1008 784
WIRE 1168 816 1168 784
WIRE 1328 816 1328 736
WIRE 864 832 864 816
WIRE 1856 880 1392 880
WIRE 1008 896 1008 880
WIRE 1856 896 1856 880
WIRE 1744 928 1392 928
WIRE 1744 960 1744 928
WIRE 1104 976 992 976
WIRE 1632 976 1392 976
WIRE 944 992 944 736
WIRE 1856 992 1856 976
WIRE 992 1008 992 976
WIRE 1632 1008 1632 976
WIRE 1536 1024 1392 1024
WIRE 1536 1056 1536 1024
WIRE 1744 1056 1744 1040
WIRE 992 1072 992 1056
WIRE 1440 1072 1392 1072
WIRE 1632 1104 1632 1088
WIRE 1440 1120 1440 1072
WIRE 1248 1136 1248 1120
WIRE 1536 1152 1536 1136
WIRE 944 1168 944 1072
WIRE 992 1168 992 1152
WIRE 1440 1216 1440 1200
SYMBOL voltage 992 1056 R0
SYMATTR InstName V2
SYMATTR Value .8
SYMBOL voltage 1856 880 R0
SYMATTR InstName V3
SYMATTR Value PULSE(0 2.4 0 1n 1n .5m 1m)
SYMBOL voltage 1440 1104 R0
SYMATTR InstName V7
SYMATTR Value PULSE(0 2.4 0 1n 1n 8m 16m)
SYMBOL g2 944 976 M0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL voltage 1632 992 R0
SYMATTR InstName V5
SYMATTR Value PULSE(0 2.4 0 1n 1n 2m 4m)
SYMBOL voltage 1744 944 R0
SYMATTR InstName V4
SYMATTR Value PULSE(0 2.4 0 1n 1n 1m 2m)
SYMBOL voltage 1008 784 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 848 752 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL PowerProducts\\LTC1706-82 1248 976 R0
SYMATTR InstName U1
SYMBOL voltage 1536 1040 R0
SYMATTR InstName V6
SYMATTR Value PULSE(0 2.4 0 1n 1n 4m 8m)
FLAG 1008 896 0
FLAG 1248 1136 0
FLAG 992 1168 0
FLAG 944 1168 0
FLAG 1856 992 0
FLAG 1744 1056 0
FLAG 1632 1104 0
FLAG 1536 1152 0
FLAG 864 832 0
FLAG 864 736 OUT
FLAG 1440 1216 0
TEXT 1904 1184 Left 2 !.tran 16m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-4.5.asy)
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-4.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
V1 IN 0 3.3
C1 OUT 0 10
Rload OUT 0 50
L1 N001 N002 1.5 Rser=80m
.tran 400u startup
.lib ADP2503-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ADP2503-4.5 176 176 R0
SYMATTR InstName U1
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 424 392 Left 2 !.tran 400u startup
TEXT 184 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP162-4.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP162-4.2.asy)
Rload OUT 0 420
V1 IN 0 5
XU1 IN 0 N001 OUT ADP16xf K=238.1u ;pnba Vin)GND)En)Vout
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
C1 OUT 0 1
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -48 96
WIRE 416 96 352 96
WIRE 512 96 416 96
WIRE -48 112 -48 96
WIRE 416 112 416 96
WIRE 512 112 512 96
WIRE -48 208 -48 192
WIRE 160 208 16 208
WIRE 416 208 416 176
WIRE 512 208 512 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 420
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
SYMBOL cap 400 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP162-4.2 256 208 R0
SYMATTR InstName U1
SYMBOL voltage -48 96 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -48 208 0
FLAG 256 272 0
FLAG 416 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG -48 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3441.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3441.asy)
R1 OUT N003 340K
C4 N003 OUT 150p
C2 OUT 0 22 Rser=10m
C1 N003 N006 250p
R2 N003 0 200K
V1 IN 0 3
Rload OUT 0 10
R3 N006 N005 5K
C3 N004 0 .001
R4 IN N004 500K
L1 N001 N002 4.7
XU1 N004 0 0 N001 N002 MP_01 0 OUT IN IN N005 N003 LTC3441 ;pnba _SHDN)GND)PGND)SW1)SW2))MODE)Vout)PVin)Vin)Vc)FB
.tran 1m startup
.lib LTC3441.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2728 2324
WIRE 1824 1232 1664 1232
WIRE 2048 1232 1904 1232
WIRE 1664 1328 1664 1232
WIRE 1696 1328 1664 1328
WIRE 2048 1328 2048 1232
WIRE 2048 1328 2016 1328
WIRE 1568 1408 1456 1408
WIRE 1664 1408 1568 1408
WIRE 1696 1408 1664 1408
WIRE 2208 1408 2016 1408
WIRE 2304 1408 2208 1408
WIRE 2416 1408 2304 1408
WIRE 2528 1408 2416 1408
WIRE 1456 1424 1456 1408
WIRE 2208 1424 2208 1408
WIRE 2416 1424 2416 1408
WIRE 2528 1424 2528 1408
WIRE 2304 1440 2304 1408
WIRE 1568 1456 1568 1408
WIRE 1664 1488 1664 1408
WIRE 1696 1488 1664 1488
WIRE 2208 1488 2016 1488
WIRE 1456 1520 1456 1504
WIRE 2416 1520 2416 1488
WIRE 2528 1520 2528 1504
WIRE 1568 1568 1568 1536
WIRE 1696 1568 1568 1568
WIRE 2032 1568 2016 1568
WIRE 2128 1568 2112 1568
WIRE 2208 1568 2208 1488
WIRE 2208 1568 2192 1568
WIRE 2304 1568 2304 1520
WIRE 2304 1568 2208 1568
WIRE 1568 1584 1568 1568
WIRE 2304 1584 2304 1568
WIRE 1696 1648 1680 1648
WIRE 2048 1648 2016 1648
WIRE 1568 1680 1568 1648
WIRE 2304 1680 2304 1664
WIRE 1856 1744 1856 1712
SYMBOL res 1552 1440 R0
SYMATTR InstName R4
SYMATTR Value 500K
SYMBOL cap 2192 1488 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C4
SYMATTR Value 150p
SYMBOL cap 1552 1584 R0
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL PowerProducts\\LTC3441 1856 1520 R0
SYMATTR InstName U1
SYMBOL res 2128 1552 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 5K
SYMBOL VOLTAGE 1456 1408 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 2288 1424 R0
SYMATTR InstName R1
SYMATTR Value 340K
SYMBOL cap 2400 1424 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=10m
SYMBOL res 2512 1408 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 2192 1552 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 250p
SYMBOL ind 1808 1248 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL res 2288 1568 R0
SYMATTR InstName R2
SYMATTR Value 200K
FLAG 2048 1648 0
FLAG 1456 1520 0
FLAG 2304 1680 0
FLAG 2416 1520 0
FLAG 2528 1520 0
FLAG 1568 1680 0
FLAG 2528 1408 OUT
FLAG 1680 1648 0
FLAG 1856 1744 0
FLAG 1456 1408 IN
TEXT 2392 1720 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\401cb315ac2f_diode.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N001 0 D
V1 N001 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0 10 .1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 112 32 112
WIRE 288 112 256 112
WIRE 32 144 32 112
WIRE 32 272 32 224
WIRE 288 272 288 112
WIRE 288 272 32 272
SYMBOL diode 192 128 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL voltage 32 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 288 272 0
TEXT 24 328 Left 2 !.dc V1 0 10 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\2d4b2ffad8ce_Mod_Generator.asc
* Generated by LTspice 26.0.1 for Windows.
D2 mod N001 D
B1 mod 0 V=V(low_freq)*V(high_freq)
V2 high_freq 0 SINE(0 1 1Meg 0 0 90)
V1 low_freq 0 PULSE(0 1.3 0 1n 1n 50u 100u)
C2 N001 0 2n
R2 N001 0 10k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.5e-3
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1668 680
WIRE 1168 -16 1088 -16
WIRE 1296 -16 1168 -16
WIRE 1168 16 1168 -16
WIRE 1296 16 1296 -16
WIRE -208 112 -208 16
WIRE 256 128 256 32
WIRE 640 144 640 32
WIRE 1168 160 1168 80
WIRE 1248 160 1168 160
WIRE 1296 160 1296 96
WIRE 1296 160 1248 160
WIRE 1248 208 1248 160
WIRE -208 288 -208 192
WIRE 256 304 256 208
WIRE 640 304 640 224
SYMBOL voltage -208 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1.3 0 1n 1n 50u 100u)
SYMBOL voltage 256 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 1Meg 0 0 90)
SYMBOL bv 640 128 R0
SYMATTR InstName B1
SYMATTR Value V=V(low_freq)*V(high_freq)
SYMBOL diode 1024 0 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMBOL res 1280 0 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL cap 1152 16 R0
SYMATTR InstName C2
SYMATTR Value 2n
FLAG -208 288 0
FLAG 256 304 0
FLAG -208 16 low_freq
FLAG 256 32 high_freq
FLAG 640 304 0
FLAG 640 32 mod
FLAG 1024 -16 mod
FLAG 1248 208 0
TEXT -240 312 Left 2 !.tran 0.5e-3
* Z:\home\khalils\Downloads\files\data\raw_asc\28072b3c10f7_TS10_3.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vx 0 AC 1
E1 TF 0 Vx 0 Laplace{(s^2+s+1)/((s^2+2*s+5)*(s+1))}
R1 TF 0 1
V2 N001 0 AC 1
R2 N001 0 {1/2}
C1 N001 0 1
R3 N003 0 {13/48}
C2 N003 0 {64/13}
R4 N003 N002 {1/16}
L1 N001 N002 {1/4}
.ac dec 10k 1m 100
* AC = 1\nV = I * Z\n1/Z = I
.param k1=75/52 k2=4489/4368 t1=6 t2=7/2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 400 -96 224 -96
WIRE 48 -64 48 -96
WIRE 224 -64 224 -96
WIRE 400 -64 400 -96
WIRE 176 16 176 0
WIRE 224 16 176 16
WIRE 48 48 48 16
WIRE 224 48 224 16
WIRE 400 48 400 16
WIRE 176 224 -64 224
WIRE 272 224 176 224
WIRE 384 224 352 224
WIRE 592 224 464 224
WIRE 176 272 176 224
WIRE 176 272 128 272
WIRE 224 272 176 272
WIRE 592 272 592 224
WIRE 592 272 544 272
WIRE 640 272 592 272
WIRE -64 288 -64 224
WIRE 128 288 128 272
WIRE 224 288 224 272
WIRE 544 288 544 272
WIRE 640 288 640 272
WIRE 128 384 128 352
WIRE 176 384 128 384
WIRE 224 384 224 368
WIRE 224 384 176 384
WIRE 544 384 544 352
WIRE 592 384 544 384
WIRE 640 384 640 368
WIRE 640 384 592 384
WIRE -64 432 -64 368
WIRE 176 432 176 384
WIRE 176 432 -64 432
WIRE 592 432 592 384
WIRE 592 432 176 432
WIRE -64 448 -64 432
FLAG 224 48 0
FLAG 48 48 0
FLAG 48 -96 Vx
FLAG 176 -48 Vx
FLAG 400 48 0
FLAG -64 448 0
FLAG 400 -96 TF
SYMBOL voltage 48 -80 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL e 224 -80 R0
WINDOW 3 -137 170 Left 2
SYMATTR Value Laplace{(s^2+s+1)/((s^2+2*s+5)*(s+1))}
SYMATTR InstName E1
SYMBOL res 384 -80 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -64 272 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V2
SYMATTR Value ""
SYMBOL res 208 272 R0
SYMATTR InstName R2
SYMATTR Value {1/2}
SYMBOL cap 112 288 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 624 272 R0
SYMATTR InstName R3
SYMATTR Value {13/48}
SYMBOL cap 528 288 R0
SYMATTR InstName C2
SYMATTR Value {64/13}
SYMBOL res 480 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {1/16}
SYMBOL ind 256 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value {1/4}
TEXT 8 112 Left 2 !.ac dec 10k 1m 100
TEXT -208 344 Left 2 ;AC = 1\nV = I * Z\n1/Z = I
TEXT -248 520 Left 2 !.param k1=75/52 k2=4489/4368 t1=6 t2=7/2
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8675.asc
* Generated by LTspice 26.0.1 for Windows.
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
XU1 IN N001 +V -V OUT AD8675 ;pnba In+)In-)V+)V-)OUT
Rload OUT 0 10K
V1 +V 0 15
V2 -V 0 -15
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8675.asy)
.lib AD8675.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 112 -1136 112 -1152
WIRE 224 -1136 224 -1152
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 112 -1040 112 -1056
WIRE 224 -1040 224 -1056
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 768 -992 0
FLAG 112 -1152 +V
FLAG 112 -1040 0
FLAG 224 -1152 -V
FLAG 224 -1040 0
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL Opamps\\AD8675 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 112 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 224 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
TEXT 736 -944 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\faa99329a21d_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
T1 N001 0 0 N002 Td=50n Z0=50
T2 0 0 N002 0 Td=30n Z0=150
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1765-0.55.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1765-0.55.asy)
V1 IN 0 1.1
C2 N003 0 10n
R2 N001 IN 50K
C1 N004 0 1
C4 OUT 0 22
C3 N002 0 1
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1765-0.55 ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
R1 OUT 0 .3
.tran 2m startup
.lib ADP1765-0.55.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL voltage -128 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .3
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 22
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL ADP1765-0.55 224 176 R0
SYMATTR InstName U1
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 432 384 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2680dc02d05b_Draft4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vdd 0 3.3
V2 N002 0 PULSE(0 3.3v 0 1p 1p 1u 2u)
M1 N001 N002 0 0 NMOS l=0.5u w=1u
M2 vdd N002 N001 vdd PMOS l=0.5u w=5u
C1 N001 0 50p
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.inc library.mod
.tran 20u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 272 192 256
WIRE 304 272 192 272
WIRE 144 304 144 240
WIRE 144 304 48 304
WIRE 192 304 192 272
WIRE 144 384 144 304
WIRE 48 416 48 304
FLAG 192 352 0
FLAG 192 400 0
FLAG 48 496 0
FLAG 480 272 0
FLAG 480 192 vdd
FLAG 192 160 vdd
FLAG 192 208 vdd
FLAG 304 336 0
SYMBOL voltage 480 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage 48 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3v 0 1p 1p 1u 2u)
SYMBOL nmos4 144 304 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.5u w=1u
SYMBOL pmos4 144 160 R0
WINDOW 3 60 73 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=0.5u w=5u
SYMBOL cap 288 272 R0
SYMATTR InstName C1
SYMATTR Value 50p
TEXT 16 48 Left 2 !.inc library.mod
TEXT 320 104 Left 2 !.tran 20u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3388-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3388-1.asy)
Rload OUT 0 24
XU1 N001 0 N002 IN N003 OUT N001 0 0 NC_01 0 LTC3388-1 ;pnba EN)STBY)CAP)Vin)SW)Vout)Vin2)D1)D0)Pgood)GND
L1 N003 OUT 100 Rser=10m Rpar=20K
C2 N002 IN 1
V1 IN 0 5
C1 OUT 0 47 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
.tran 5m startup
.lib LTC3388-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 -64 -16 -64
WIRE 160 -48 16 -48
WIRE 16 -32 16 -48
WIRE 160 0 160 -48
WIRE 256 0 256 -64
WIRE 16 48 16 32
WIRE 16 48 -80 48
WIRE 64 48 16 48
WIRE 384 48 352 48
WIRE 496 48 464 48
WIRE 544 48 496 48
WIRE 624 48 544 48
WIRE 544 64 544 48
WIRE 624 64 624 48
WIRE -80 80 -80 48
WIRE -16 144 -16 -64
WIRE 64 144 -16 144
WIRE 496 144 496 48
WIRE 496 144 352 144
WIRE 544 160 544 128
WIRE 624 160 624 144
WIRE -80 176 -80 160
WIRE 64 240 48 240
WIRE 384 240 352 240
WIRE 384 336 352 336
WIRE 208 400 208 384
SYMBOL cap 528 64 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL PowerProducts\\LTC3388-1 208 192 R0
SYMATTR InstName U1
SYMBOL res 608 48 R0
SYMATTR InstName Rload
SYMATTR Value 24
SYMBOL cap 0 -32 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL ind 368 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rser=10m Rpar=20K
SYMBOL voltage -80 64 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 208 400 0
FLAG -80 176 0
FLAG 48 240 0
FLAG 384 240 0
FLAG 384 336 0
FLAG 544 160 0
FLAG 624 160 0
FLAG -80 48 IN
FLAG 624 48 OUT
TEXT 472 280 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\211488120338_primeiraOrdem.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N003 N001 NC_01 NC_02 N001 opamp2 ;pnba In+)In-)V+)V-)OUT
C1 N003 0 C
R1 N003 N002 R
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 96 0 96
WIRE 0 160 0 96
WIRE 32 160 0 160
WIRE 128 176 128 96
WIRE 128 176 96 176
WIRE 176 176 128 176
WIRE -112 192 -144 192
WIRE 0 192 -32 192
WIRE 32 192 0 192
WIRE 0 224 0 192
SYMBOL res -16 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMBOL cap -16 224 R0
SYMATTR InstName C1
SYMBOL OpAmps\\opamp2 64 112 R0
SYMATTR InstName U1
FLAG 0 288 0