Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\7091588f3c2f_NAND.asc
* Generated by LTspice 26.0.1 for Windows.
M2 NAND B N001 N001 Sp2025P
M4 N002 B 0 0 Sp2025N
M1 NAND A N001 N001 Sp2025P
M3 NAND A N002 N002 Sp2025N
V1 N001 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 336 -160 128 -160
WIRE 560 -160 336 -160
WIRE 128 -96 128 -160
WIRE 336 -96 336 -160
WIRE 32 -80 16 -80
WIRE 80 -80 32 -80
WIRE 240 -80 224 -80
WIRE 288 -80 240 -80
WIRE 128 32 128 0
WIRE 224 32 128 32
WIRE 336 32 336 0
WIRE 336 32 224 32
WIRE 432 32 336 32
WIRE 32 48 -16 48
WIRE 224 64 224 32
WIRE 32 112 -16 112
WIRE 128 144 112 144
WIRE 176 144 128 144
WIRE 224 208 224 160
WIRE 128 288 112 288
WIRE 176 288 128 288
WIRE 224 352 224 304
IOPIN -16 48 In
IOPIN -16 112 In
IOPIN 432 32 Out
SYMBOL pmos 80 0 M180
SYMATTR InstName M1
SYMATTR Value Sp2025P
SYMBOL pmos 288 0 M180
SYMATTR InstName M2
SYMATTR Value Sp2025P
SYMBOL voltage 560 -176 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL nmos 176 64 R0
SYMATTR InstName M3
SYMATTR Value Sp2025N
SYMBOL nmos 176 208 R0
SYMATTR InstName M4
SYMATTR Value Sp2025N
FLAG 224 352 0
FLAG -16 48 A
FLAG -16 112 B
FLAG 128 144 A
FLAG 128 288 B
FLAG 32 -80 A
FLAG 240 -80 B
FLAG 432 32 NAND
FLAG 560 -80 0
* Z:\home\khalils\Downloads\files\data\raw_asc\5b6a66c7ce35_ev.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N002 N005 4.2R pwr=4.2
XU1 NC_01 N010 N006 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
C1 N003 N004 1F
Dled1 N003 N004 D
R1 N001 N007 4.2R pwr=4.2
C3 N008 N009 1F
Dled2 N003 N008 D
M1 N001 N003 0 0 NMOS
C2 N004 N008 1F
M2 N002 N003 0 0 NMOS
C4 N009 N010 1F
V2 N007 N010 14
D3 N005 N006 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1384 788
WIRE 224 -112 80 -112
WIRE 1216 -112 1216 -128
WIRE 1216 -112 976 -112
WIRE 80 -96 80 -112
WIRE 272 -32 176 -32
WIRE 544 -32 272 -32
WIRE 752 -32 544 -32
WIRE 928 -32 752 -32
WIRE 272 64 272 -32
WIRE 544 64 544 -32
WIRE 752 64 752 -32
WIRE 272 144 272 128
WIRE 544 144 544 128
WIRE 544 144 272 144
WIRE 1216 160 1216 -48
WIRE 1312 160 1216 160
WIRE 272 208 272 144
WIRE 1376 224 1312 224
WIRE 80 320 80 -16
WIRE 272 352 272 272
WIRE 752 352 752 128
WIRE 752 352 272 352
WIRE 1376 384 1376 224
WIRE 272 528 272 416
WIRE 80 736 80 400
WIRE 272 736 272 592
WIRE 272 736 80 736
WIRE 1312 736 1312 400
WIRE 1312 736 272 736
SYMBOL cap 256 352 R0
SYMATTR InstName C3
SYMATTR Value 1F
SYMBOL cap 256 208 R0
SYMATTR InstName C2
SYMATTR Value 1F
SYMBOL LED 528 64 R0
SYMATTR InstName led1
SYMBOL LED 736 64 R0
SYMATTR InstName led2
SYMBOL diode 1296 160 R0
SYMATTR InstName D3
SYMBOL Misc\\battery 80 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 14
SYMBOL cap 256 528 R0
SYMATTR InstName C4
SYMATTR Value 1F
SYMBOL res 1200 -144 R0
SYMATTR InstName R2
SYMATTR Value 4.2R
SYMATTR SpiceLine pwr=4.2
SYMBOL res 64 -112 R0
SYMATTR InstName R1
SYMATTR Value 4.2R
SYMATTR SpiceLine pwr=4.2
SYMBOL OpAmps\\opamp 1344 320 R0
SYMATTR InstName U1
SYMBOL nmos 176 -112 R0
SYMATTR InstName M1
SYMBOL cap 256 64 R0
SYMATTR InstName C1
SYMATTR Value 1F
SYMBOL nmos 928 -112 R0
SYMATTR InstName M2
FLAG 224 -16 0
FLAG 976 -16 0
* Z:\home\khalils\Downloads\files\data\raw_asc\279d9e2ec2e7_class_phi2_paper.asc
* Generated by LTspice 26.0.1 for Windows.
V1 0 N005 PULSE(0 10 0 1n 1n 11n 36n)
V2 N001 0 24
S1 N002 0 0 N005 MYSW
L1 N001 N002 62.7n
L2 N002 N006 80n
L3 N002 N003 357n
C1 N004 N003 96.5p
C2 0 N006 95.7p
C3 0 N002 290p
R1 N004 0 25
D1 0 N002 D_ideal
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model MYSW SW(Ron=30m Roff=1Meg Vt=5 Vh=-.4)
.tran 0 50u 49u
.model D_ideal D(Ron=0.1n Roff=1G Vfwd=0.7)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 192 64 112 64
WIRE 320 64 272 64
WIRE 400 64 320 64
WIRE 560 64 400 64
WIRE 640 64 560 64
WIRE 736 64 640 64
WIRE 848 64 816 64
WIRE 928 64 912 64
WIRE 112 80 112 64
WIRE 640 80 640 64
WIRE 928 128 928 64
WIRE 112 176 112 160
WIRE 320 176 320 64
WIRE 400 176 400 64
WIRE 272 192 208 192
WIRE 560 192 560 64
WIRE 640 192 640 160
WIRE 224 272 208 272
WIRE 272 272 272 240
WIRE 272 272 224 272
WIRE 320 272 320 256
WIRE 400 272 400 240
WIRE 560 272 560 256
WIRE 640 272 640 256
WIRE 928 272 928 208
WIRE 224 288 224 272
FLAG 320 272 0
FLAG 560 272 0
FLAG 640 272 0
FLAG 112 176 0
FLAG 928 272 0
FLAG 224 288 0
FLAG 400 272 0
SYMBOL voltage 208 288 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 10 0 1n 1n 11n 36n)
SYMBOL voltage 112 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 24
SYMBOL sw 320 160 R0
WINDOW 0 -36 4 Left 2
WINDOW 3 -18 142 Left 2
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL ind 176 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 62.7n
SYMBOL ind 624 64 R0
SYMATTR InstName L2
SYMATTR Value 80n
SYMBOL ind 720 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 357n
SYMBOL cap 912 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 96.5p
SYMBOL cap 656 256 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value 95.7p
SYMBOL cap 576 256 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value 290p
SYMBOL res 912 112 R0
SYMATTR InstName R1
SYMATTR Value 25
SYMBOL diode 416 240 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value D_ideal
TEXT 192 352 Left 2 !.model MYSW SW(Ron=30m Roff=1Meg Vt=5 Vh=-.4)
TEXT -188 372 Left 2 !.tran 0 50u 49u
TEXT 200 384 Left 2 !.model D_ideal D(Ron=0.1n Roff=1G Vfwd=0.7)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2138-1.0.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5
L1 N001 OUT 1 Rser=60m
Rload OUT 0 2
C1 OUT 0 10
XU1 IN IN N001 OUT 0 IN ADP2138-x.x Rtop=80K ;pnba Vin)EN)SW)Vout)GND)Mode
.tran .5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2138-1.0.asy)
.lib ADP2138-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2138-1.0 352 224 R0
SYMATTR InstName U1
TEXT 600 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1d3106c62b1d_simulacionDiodo1N4007.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N002 0 1N4007
R1 N002 N001 1K
V1 N001 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -2 10 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 128 96 48 96
WIRE 272 96 208 96
WIRE 48 128 48 96
WIRE 272 128 272 96
WIRE 48 224 48 192
WIRE 272 224 272 192
WIRE 272 224 48 224
WIRE 48 256 48 224
SYMBOL res 224 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL Misc\\cell 48 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL diode 256 128 R0
SYMATTR InstName D1
SYMATTR Value 1N4007
FLAG 48 256 0
TEXT 72 264 Left 2 !.dc V1 -2 10 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG621.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nCharge Injection not included\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG621.asy)
V1 N003 0 PULSE(0 3 25u 1n 1n 20u)
C1 N002 0 36p
R1 N002 0 301
XU1 N003 N002 N001 -V 0 +V ADG621 ;pnba IN)D)S)Vss)GND)Vdd
V4 -V 0 -5
V2 N001 0 3
V3 +V 0 5
.tran 75u
.lib ADG621.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 16 -48 -32
WIRE -144 96 -320 96
WIRE 128 96 48 96
WIRE 256 96 128 96
WIRE -320 128 -320 96
WIRE 128 128 128 96
WIRE 256 128 256 96
WIRE -144 160 -240 160
WIRE -512 176 -512 128
WIRE -432 176 -432 128
WIRE -320 224 -320 208
WIRE 128 240 128 208
WIRE 256 240 256 192
WIRE -512 272 -512 256
WIRE -432 272 -432 256
WIRE -240 272 -240 160
WIRE -112 304 -112 272
WIRE 16 304 16 272
WIRE -240 416 -240 352
SYMBOL voltage -432 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -5
SYMBOL res 112 112 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL cap 240 128 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -240 256 R0
WINDOW 3 24 102 Left 2
SYMATTR Value PULSE(0 3 25u 1n 1n 20u)
SYMATTR InstName V1
SYMBOL ADG621 -48 144 R0
SYMATTR InstName U1
SYMBOL voltage -320 112 R0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL voltage -512 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
FLAG 128 240 0
FLAG 256 240 0
FLAG 16 304 0
FLAG -240 416 0
FLAG -320 224 0
FLAG -48 -32 +V
FLAG -512 272 0
FLAG -512 128 +V
FLAG -432 272 0
FLAG -432 128 -V
FLAG -112 304 -V
TEXT -224 392 Left 2 !.tran 75u
TEXT -520 -152 Left 2 ;Note:\nCharge Injection not included\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\14c6d654d743_R_cMeter.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N002 0 N001 R C capometer current=1m freq=3Meg C=.5 Q=.25 ;pnba DUT+)DUT-)bias)Resistance)Capacitance
V1 N001 0 PWL(0 -25 1m 25)
Dut 0 N002 1N4148
R1 N002 N001 100
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 1m .5m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -432 256 -432 192
WIRE -432 272 -432 256
WIRE -432 384 -432 352
WIRE -352 256 -432 256
WIRE -224 256 -272 256
WIRE -224 288 -224 256
WIRE -224 384 -432 384
WIRE -224 384 -224 352
WIRE -160 384 -224 384
WIRE -160 384 -160 320
WIRE -160 416 -160 384
WIRE -96 192 -432 192
WIRE -96 256 -224 256
WIRE -96 320 -160 320
WIRE 304 224 272 224
WIRE 304 288 272 288
SYMBOL SpecialFunctions\\capmeter -16 224 R0
WINDOW 0 86 -48 Left 0
WINDOW 3 49 112 Left 0
SYMATTR InstName U1
SYMBOL voltage -432 256 M0
WINDOW 3 -182 147 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -15 61 Left 0
SYMATTR Value PWL(0 -25 1m 25)
SYMATTR InstName V1
SYMBOL diode -208 352 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName Dut
SYMATTR Value 1N4148
SYMBOL res -256 240 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 100
FLAG -160 416 0
FLAG 304 224 R
FLAG 304 288 C
TEXT -450 450 Left 0 !.tran 0 1m .5m
* Z:\home\khalils\Downloads\files\data\raw_asc\21b43b6ab311_Delay_sT_Tline_Delay.asc
* Generated by LTspice 26.0.1 for Windows.
* .tran 100u
* .optons plotwinsize=0
* Delay Functions
* Not working in for .AC analysis
B1 OUT 0 V=V(IN) LAPLACE(exp(-s*{TS}))
E1 N001 0 IN 0 1
B2 OUTD 0 V=delay(V(IN), {TS})
R1 N002 0 50
T1 N001 0 N002 0 Td={TS} Z0=50
E2 OUTZ 0 N002 0 1
V1 IN 0 SINE(0 1 100k 0 10k 0) AC 1
.param TS=1u
.ac dec 100 1k 10meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 900
WIRE -16 224 -80 224
WIRE 624 224 256 224
WIRE -80 256 -80 224
WIRE 256 256 256 224
WIRE -80 368 -80 336
WIRE 256 368 256 336
WIRE 368 496 240 496
WIRE 576 496 464 496
WIRE 656 496 576 496
WIRE 768 496 704 496
WIRE 240 512 240 496
WIRE 576 512 576 496
WIRE 704 512 704 496
WIRE 192 528 144 528
WIRE 368 528 352 528
WIRE 480 528 464 528
WIRE 656 528 656 496
WIRE 192 608 192 576
WIRE 240 608 240 592
WIRE 576 608 576 592
WIRE 656 608 656 576
WIRE 704 608 704 592
WIRE 624 736 256 736
WIRE 256 768 256 736
WIRE 256 880 256 848
IOPIN -16 224 In
IOPIN 624 224 Out
IOPIN 624 736 Out
SYMBOL bv 256 240 R0
SYMATTR InstName B1
SYMATTR Value V=V(IN)   LAPLACE(exp(-s*{TS}))
SYMBOL tline 416 512 R0
SYMATTR InstName T1
SYMATTR Value Td={TS} Z0=50
SYMBOL e 240 496 R0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL voltage -80 240 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 100k 0 10k 0)
SYMATTR Value2 AC 1
SYMBOL res 560 496 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL e 704 496 R0
SYMATTR InstName E2
SYMATTR Value 1
SYMBOL bv 256 752 R0
SYMATTR InstName B2
SYMATTR Value V=delay(V(IN), {TS})
FLAG 256 368 0
FLAG -16 224 IN
FLAG 624 224 OUT
FLAG -80 368 0
FLAG 576 608 0
FLAG 352 528 0
FLAG 480 528 0
FLAG 240 608 0
FLAG 192 608 0
FLAG 704 608 0
FLAG 656 608 0
FLAG 768 496 OUTZ
FLAG 144 528 IN
FLAG 256 880 0
FLAG 624 736 OUTD
TEXT -88 40 Left 0 !.param TS=1u
TEXT -88 80 Left 0 !.ac dec 100 1k 10meg
TEXT -88 120 Left 0 ;.tran 100u
TEXT -88 152 Left 0 ;.optons plotwinsize=0
TEXT 280 56 Left 0 ;Delay Functions
TEXT 376 792 Left 0 ;Not working in for .AC analysis
* Z:\home\khalils\Downloads\files\data\raw_asc\229573f8575d_Triangular_WaveForm_Generator.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1001.asy)
R1 N003 N002 13.5k
R3 N002 N005 20k
XU1 0 N003 N001 N006 N004 LT1001 ;pnba In+)In-)V+)V-)OUT
R2 N005 N004 7.5k
R4 Output N004 7.5k
XU2 N005 0 N001 N006 N002 LT1001 ;pnba In+)In-)V+)V-)OUT
V2 0 N006 15
C1 N004 N003 50n
V1 N001 0 15
.tran 0.01
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 948 680
WIRE 592 -272 512 -272
WIRE 512 -256 512 -272
WIRE 512 -256 80 -256
WIRE 512 -160 512 -176
WIRE 592 -128 592 -272
WIRE 592 -128 560 -128
WIRE 784 -48 -208 -48
WIRE 512 0 480 0
WIRE 144 48 0 48
WIRE 256 48 208 48
WIRE 480 64 480 0
WIRE 560 80 560 -128
WIRE 80 96 80 -256
WIRE 512 96 512 0
WIRE 528 96 512 96
WIRE -208 112 -208 -48
WIRE -128 112 -208 112
WIRE 0 112 0 48
WIRE 0 112 -48 112
WIRE 48 112 0 112
WIRE 704 112 592 112
WIRE 784 112 784 -48
WIRE 784 112 704 112
WIRE 256 128 256 48
WIRE 256 128 112 128
WIRE 320 128 256 128
WIRE 400 128 320 128
WIRE 512 128 480 128
WIRE 528 128 512 128
WIRE 48 144 32 144
WIRE 32 208 32 144
WIRE 512 208 512 128
WIRE 576 208 512 208
WIRE 704 208 704 112
WIRE 704 208 656 208
WIRE 80 256 80 160
WIRE 560 256 560 144
WIRE 560 256 80 256
WIRE 80 304 80 256
WIRE 320 368 320 128
WIRE 640 368 320 368
WIRE 784 368 720 368
WIRE 80 416 80 384
SYMBOL OpAmps\\LT1001 80 64 R0
SYMATTR InstName U1
SYMBOL cap 208 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 50n
SYMBOL Misc\\battery 80 400 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 672 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 20k
SYMBOL res 736 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 7.5k
SYMBOL res 496 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 7.5k
SYMBOL OpAmps\\LT1001 560 48 R0
SYMATTR InstName U2
SYMBOL Misc\\battery 512 -272 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res -32 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 13.5k
FLAG 32 208 0
FLAG 512 -160 0
FLAG 480 64 0
FLAG 80 416 0
FLAG 784 368 Output
TEXT -208 440 Left 2 !.tran 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1982.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N002 0 3.3
V2 N004 0 PULSE(0 3 .7m 100n 100n 2.5m 5m)
MQ1 N002 N003 N006 N006 Si4838DY
R1 0 N006 10
XU1 N001 0 N004 N005 N003 N002 LTC1982 ;pnba _SHDN1)GND)_SHDN2)Gate2)Gate1)Vcc
V3 N001 0 PULSE(0 3 0 100n 100n 2.5m 5m)
MQ2 N002 N005 N007 N007 Si4838DY
R2 0 N007 10
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1982.asy)
.lib LTC1982.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -240 112 -256 112
WIRE 32 112 -160 112
WIRE 352 112 256 112
WIRE 480 112 352 112
WIRE 576 112 480 112
WIRE 352 128 352 112
WIRE 576 128 576 112
WIRE 32 208 16 208
WIRE 304 208 256 208
WIRE 480 224 480 112
WIRE 576 224 576 208
WIRE -240 304 -256 304
WIRE 32 304 -160 304
WIRE 432 304 256 304
WIRE 352 368 352 224
WIRE 480 368 480 320
WIRE 352 464 352 448
WIRE 480 464 480 448
FLAG 576 224 0
FLAG 16 208 0
FLAG -256 304 0
FLAG 352 464 0
FLAG -256 112 0
FLAG 480 464 0
SYMBOL voltage 576 112 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage -144 304 R90
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 3 .7m 100n 100n 2.5m 5m)
SYMATTR InstName V2
SYMBOL nmos 304 128 R0
WINDOW 3 53 80 Left 2
WINDOW 0 56 51 Left 2
SYMATTR Value Si4838DY
SYMATTR InstName Q1
SYMBOL res 368 464 R180
WINDOW 0 -35 89 Left 2
WINDOW 3 -33 43 Left 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL LTC1982 144 208 R0
SYMATTR InstName U1
SYMBOL voltage -144 112 R90
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 3 0 100n 100n 2.5m 5m)
SYMATTR InstName V3
SYMBOL nmos 432 224 R0
WINDOW 3 53 80 Left 2
WINDOW 0 56 48 Left 2
SYMATTR Value Si4838DY
SYMATTR InstName Q2
SYMBOL res 496 464 R180
WINDOW 0 -35 89 Left 2
WINDOW 3 -33 43 Left 2
SYMATTR InstName R2
SYMATTR Value 10
TEXT 56 408 Left 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1412.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1412.asy)
R1 vD 0 301
V3 v+ 0 15
C1 vD 0 36p
V1 vS 0 SINE(0 5 20)
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
XU1 vIN vS vD v- v+ 0 ADG1412 ;pnba IN)S)D)Vss)Vdd)GND
V4 v- 0 -15
.tran 1
.lib ADG1412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 112 240 112
WIRE 240 144 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 368 224 336 224
WIRE 416 224 368 224
WIRE 528 224 416 224
WIRE 416 256 416 224
WIRE 528 256 528 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -272 304 -288 304
WIRE -176 304 -192 304
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 416 352 416 336
WIRE 528 352 528 320
WIRE 304 416 304 400
WIRE 176 432 176 400
WIRE 192 432 176 432
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 20)
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL res 400 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL ADG1412 240 272 R0
SYMATTR InstName U1
SYMBOL cap 512 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG -112 224 0
FLAG 48 464 0
FLAG 416 352 0
FLAG 304 416 0
FLAG 368 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 528 352 0
FLAG -272 304 v+
FLAG 256 112 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -176 304 v-
FLAG 192 432 v-
TEXT 80 528 Left 2 !.tran 1
TEXT -360 -40 Left 2 ;Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\26aef9142f85_VoltageStabilizerNpnBJT.asc
* Generated by LTspice 26.0.1 for Windows.
* Voltage regulator with feedback
* .tran 50m
V1 N001 0 12
D1 0 N003 RB876W
R1 N003 N001 1000
R2 0 N002 100
Q1 N001 N003 N002 0 NPN
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc oct R2 10 100000 10000
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 144 16 0 16
WIRE 352 16 144 16
WIRE 624 16 448 16
WIRE 0 64 0 16
WIRE 624 96 624 16
WIRE 144 112 144 16
WIRE 176 112 144 112
WIRE 400 112 400 80
WIRE 400 112 256 112
WIRE 400 128 400 112
WIRE 0 224 0 144
WIRE 400 224 400 192
WIRE 400 224 0 224
WIRE 624 224 624 176
WIRE 624 224 400 224
WIRE 0 256 0 224
SYMBOL voltage 0 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL npn 352 80 R270
SYMATTR InstName Q1
SYMBOL res 640 192 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL res 272 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL diode 416 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value RB876W
SYMATTR Description Diode
SYMATTR Type diode
FLAG 0 256 0
TEXT -504 -104 Left 2 ;Voltage regulator with feedback
TEXT -504 280 Left 2 ;.tran 50m
TEXT -504 312 Left 2 !.dc oct R2 10 100000 10000
* Z:\home\khalils\Downloads\files\data\raw_asc\05c937015e6b_cmos-voltage-dependent-resistor.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N002 100Meg
E1 NC_01 NC_02 NC_03 NC_04 E
M1 N002 N001 0 0 2N7002
M2 N003 N001 N002 N002 2N7002
V1 N001 0 1
R2 N001 N003 10k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc v1 0 3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 -64 -160 -64
WIRE 128 -64 32 -64
WIRE 272 -64 128 -64
WIRE 352 -64 272 -64
WIRE 128 -32 128 -64
WIRE 352 -32 352 -64
WIRE 128 80 128 48
WIRE 240 80 128 80
WIRE 128 112 128 80
WIRE 352 112 352 48
WIRE -160 160 -160 -64
WIRE 32 192 32 -64
WIRE 80 192 32 192
WIRE 272 192 272 -64
WIRE 304 192 272 192
WIRE 240 240 240 80
WIRE 352 240 352 208
WIRE 352 240 240 240
WIRE -160 272 -160 240
WIRE 128 272 128 208
SYMBOL nmos 304 112 R0
SYMATTR InstName M2
SYMATTR Value 2N7002
SYMBOL e 640 64 R0
SYMATTR InstName E1
SYMBOL nmos 80 112 R0
SYMATTR InstName M1
SYMATTR Value 2N7002
SYMBOL res 336 -48 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -160 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMBOL res 112 -48 R0
SYMATTR InstName R1
SYMATTR Value 100Meg
FLAG -160 272 0
FLAG 128 272 0
TEXT 560 -136 Left 2 !.dc v1 0 3