Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\14d1266e5030_fig-02-02-26_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
VS1 VCC 0 15
V2 N009 0 AC 0
V4 N005 0 AC 0
VS2 0 VEE 15
V9 N002 N001 AC 0
R15 N003 N010 1k
V3 N007 0 AC 0
R12 N003 N009 1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -464 -224 -496 -224
WIRE -352 -224 -384 -224
WIRE -224 -224 -272 -224
WIRE 96 -224 -224 -224
WIRE -496 -128 -496 -224
WIRE -464 -128 -496 -128
WIRE -352 -128 -384 -128
WIRE -224 -128 -224 -224
WIRE -224 -128 -272 -128
WIRE -144 -128 -176 -128
WIRE -32 -128 -64 -128
WIRE 96 -128 96 -224
WIRE 96 -128 48 -128
WIRE -496 -32 -496 -128
WIRE -464 -32 -496 -32
WIRE -352 -32 -384 -32
WIRE -224 -32 -224 -128
WIRE -224 -32 -272 -32
WIRE -176 -32 -176 -128
WIRE -144 -32 -176 -32
WIRE -32 -32 -64 -32
WIRE 96 -32 96 -128
WIRE 96 -32 48 -32
WIRE -496 64 -496 -32
WIRE -352 64 -384 64
WIRE -224 64 -224 -32
WIRE -224 64 -272 64
WIRE -176 64 -176 -32
WIRE -144 64 -176 64
WIRE -32 64 -64 64
WIRE 96 64 96 -32
WIRE 96 64 48 64
WIRE 176 64 96 64
WIRE 304 64 256 64
WIRE 160 128 160 112
WIRE -352 160 -384 160
WIRE -224 160 -224 64
WIRE -224 160 -272 160
WIRE -176 160 -176 64
WIRE -144 160 -176 160
WIRE -32 160 -64 160
WIRE 96 160 96 64
WIRE 96 160 48 160
WIRE 160 160 160 128
WIRE 96 176 96 160
WIRE 128 176 96 176
WIRE 304 192 304 64
WIRE 304 192 192 192
WIRE 368 192 304 192
WIRE 128 208 32 208
WIRE -176 240 -176 160
WIRE 160 256 160 224
WIRE 32 272 32 208
WIRE 160 272 160 256
WIRE 304 272 304 256
WIRE 368 272 368 256
WIRE 304 320 304 272
WIRE 368 320 368 272
WIRE 304 416 304 400
WIRE 368 416 368 400
SYMBOL Misc\\battery 368 304 R0
WINDOW 0 9 8 Left 2
WINDOW 3 17 96 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS1
SYMATTR Value 15
SYMBOL voltage -48 64 R90
WINDOW 3 -87 181 Left 2
WINDOW 123 44 46 VLeft 2
WINDOW 39 0 0 Left 2
WINDOW 0 43 105 VLeft 2
SYMATTR Value ""
SYMATTR Value2 AC 0
SYMATTR InstName V2
SYMBOL voltage -48 -128 R90
WINDOW 3 -87 181 Left 2
WINDOW 123 44 46 VLeft 2
WINDOW 39 0 0 Left 2
WINDOW 0 43 105 VLeft 2
SYMATTR Value ""
SYMATTR Value2 AC 0
SYMATTR InstName V4
SYMBOL Misc\\battery 304 416 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS2
SYMATTR Value 15
SYMBOL voltage -368 -224 R90
WINDOW 3 -87 181 Left 2
WINDOW 123 44 46 VLeft 2
WINDOW 39 0 0 Left 2
WINDOW 0 43 105 VLeft 2
SYMATTR Value ""
SYMATTR Value2 AC 0
SYMATTR InstName V9
SYMBOL res -256 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R15
SYMATTR Value 1k
SYMBOL voltage -48 -32 R90
WINDOW 3 -87 181 Left 2
WINDOW 123 44 46 VLeft 2
WINDOW 39 0 0 Left 2
WINDOW 0 43 105 VLeft 2
SYMATTR Value ""
SYMATTR Value2 AC 0
SYMATTR InstName V3
SYMBOL res 64 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 1k
FLAG 368 192 VOUT
FLAG 304 416 0
FLAG 368 416 0
FLAG 304 272 VEE
FLAG 368 272 VCC
FLAG 160 128 VCC
FLAG 160 256 VEE
FLAG -176 240 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8604C.asc
* Generated by LTspice 26.0.1 for Windows.
L1 SW OUT 120 Rser=1
C1 OUT 0 22
R1 FB 0 301k
R2 RT 0 110k
V1 N001 0 12
R3 OUT PG 100k
R4 OUT FB 1.62Meg
XU1 NC_01 SW OUT SYNC RT FB TRSS PG N001 N001 0 LT8604C LT8604=1 DFN=0 VOUT33=0 ;pnba HYST)SW)Bias)SYNC)Rt)FB)TR/SS)PG)EN/UV)Vin)GND
Rload OUT 0 50
.tran 3m steady nodiscard
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8604C.asy)
.lib LT8604C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1748 780
WIRE -32 48 -192 48
WIRE 16 48 -32 48
WIRE 336 48 304 48
WIRE 400 48 336 48
WIRE 528 48 480 48
WIRE 624 48 528 48
WIRE 800 48 624 48
WIRE 912 48 800 48
WIRE 944 48 912 48
WIRE -192 128 -192 48
WIRE -32 144 -32 48
WIRE 16 144 -32 144
WIRE 528 144 528 48
WIRE 528 144 304 144
WIRE 800 160 800 48
WIRE 944 160 944 48
WIRE 624 192 624 48
WIRE 800 256 800 224
WIRE 944 256 944 240
WIRE -192 272 -192 208
WIRE -48 336 -112 336
WIRE 16 336 -48 336
WIRE 336 336 304 336
WIRE 624 336 624 272
WIRE 624 336 336 336
WIRE 624 352 624 336
WIRE -64 432 -112 432
WIRE 16 432 -64 432
WIRE 624 464 624 432
WIRE -48 528 -192 528
WIRE 16 528 -48 528
WIRE 336 528 304 528
WIRE 384 528 336 528
WIRE 528 528 528 144
WIRE 528 528 464 528
WIRE -192 576 -192 528
WIRE 160 624 160 576
WIRE -192 720 -192 656
FLAG 624 464 0
FLAG 800 256 0
FLAG 912 48 OUT
FLAG -192 720 0
FLAG -192 272 0
FLAG 336 528 PG
FLAG 336 336 FB
FLAG 336 48 SW
FLAG -48 528 RT
FLAG -64 432 TRSS
FLAG 160 624 0
FLAG -48 336 SYNC
FLAG 944 256 0
SYMBOL ind 384 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 120
SYMATTR SpiceLine Rser=1
SYMBOL cap 784 160 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 608 336 R0
SYMATTR InstName R1
SYMATTR Value 301k
SYMBOL res -208 560 R0
SYMATTR InstName R2
SYMATTR Value 110k
SYMBOL voltage -192 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 480 512 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL res 608 176 R0
SYMATTR InstName R4
SYMATTR Value 1.62Meg
SYMBOL LT8604C 160 240 R0
SYMATTR InstName U1
SYMBOL res 928 144 R0
SYMATTR InstName Rload
SYMATTR Value 50
TEXT 576 616 Left 2 !.tran 3m steady nodiscard
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2370-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2370-1.2.asy)
R1 OUT N001 10K
C1 OUT 0 10
L1 N002 OUT 10 Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
Rload OUT 0 10
V1 IN 0 12
XU1 NC_01 IN IN IN N002 OUT N001 0 ADP2370-1.2 IPSM=320m Rt=166.6667k Rb=333.33333k C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=0 ;pnba FSEL)SYNC)EN)Vin)SW)FB)PG)PGND
.tran 500u startup
.lib ADP2370-1.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 948 692
WIRE 128 96 16 96
WIRE 160 96 128 96
WIRE 464 96 384 96
WIRE 640 96 544 96
WIRE 16 112 16 96
WIRE 128 176 128 96
WIRE 160 176 128 176
WIRE 416 176 384 176
WIRE 544 176 496 176
WIRE 640 176 640 96
WIRE 640 176 544 176
WIRE 736 176 640 176
WIRE 736 192 736 176
WIRE 16 208 16 192
WIRE 128 336 128 176
WIRE 544 256 544 240
WIRE 544 256 384 256
WIRE 544 272 544 256
WIRE 736 288 736 272
WIRE 160 336 128 336
WIRE 640 336 640 176
WIRE 640 336 384 336
SYMBOL ind 400 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
SYMBOL VOLTAGE 16 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL ADP2370-1.2 272 208 R0
SYMATTR InstName U1
SYMBOL cap 528 176 R0
WINDOW 0 29 15 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 560 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 720 176 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 16 208 0
FLAG 16 96 IN
FLAG 544 272 0
FLAG 736 176 OUT
FLAG 736 288 0
TEXT 488 392 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\05a9ece993ad_BJT_Tran.asc
* Generated by LTspice 26.0.1 for Windows.
Ibb 0 N002 0
Q1 N001 N002 0 0 BC547B
V2 N001 0 {Uce}
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc Ibb 0 500u
.step param Uce list 5 10 20
.meas dc Ib find Ib(Q1) when Ic(Q1)=20mA
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 368 16 208 16
WIRE 208 80 208 16
WIRE 368 96 368 16
WIRE 144 128 32 128
WIRE 32 144 32 128
WIRE 32 256 32 224
WIRE 208 256 208 176
WIRE 368 256 368 176
SYMBOL current 32 224 R180
WINDOW 0 -63 0 Left 2
WINDOW 3 -66 28 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Ibb
SYMATTR Value 0
SYMBOL npn 144 80 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL voltage 368 80 R0
WINDOW 3 35 85 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 35 57 Left 2
SYMATTR Value {Uce}
SYMATTR InstName V2
FLAG 208 256 0
FLAG 32 256 0
FLAG 368 256 0
TEXT 48 304 Left 2 !.dc Ibb 0 500u
TEXT 48 328 Left 2 !.step param Uce list 5 10 20
TEXT 208 304 Left 2 !.meas dc Ib find Ib(Q1) when Ic(Q1)=20mA
* Z:\home\khalils\Downloads\files\data\raw_asc\31772dcbc446_Q1_iii_.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 1
L N003 N002 1
C N003 0 1
R N002 N001 2
.tran 0 30s 0 0.00002s
.ic V(n003) = 0
.ic I(L) = 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1360 680
WIRE 176 -208 48 -208
WIRE 368 -208 256 -208
WIRE 528 -208 448 -208
WIRE 48 -160 48 -208
WIRE 528 -144 528 -208
WIRE 48 0 48 -80
WIRE 304 0 48 0
WIRE 528 0 528 -80
WIRE 528 0 304 0
WIRE 304 32 304 0
SYMBOL voltage 48 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMBOL cap 512 -144 R0
SYMATTR InstName C
SYMATTR Value 1
SYMBOL res 272 -224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R
SYMATTR Value 2
SYMBOL ind 464 -192 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L
SYMATTR Value 1
FLAG 304 32 0
TEXT -72 40 Left 2 !.tran 0 30s 0 0.00002s
TEXT 600 -16 Left 2 !.ic V(n003) = 0
TEXT 600 16 Left 2 !.ic I(L) = 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4265.asc
* Generated by LTspice 26.0.1 for Windows.
* Diode Bridge
* Set for Class 4 Load
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4265.asy)
D2 IN N006 MURS120
R1 N001 N002 100K
Cload N001 OUT 100 Rser=10m
Rload N001 OUT 1.3K
D1 0 N001 MURS120
XU1 IN N002 N004 MP_01 IN IN OUT OUT N005 N003 MP_02 N001 LTC4265 ;pnba SHDN)_T2PSE)Rclass))Vin1)Vin)Vout1)Vout)PWRGD)_PWRGD))GND
R3 N001 N005 100K
R2 N001 N003 100K
VPSE 0 N006 PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 8 555m 8 560m 4 610m 4 611m 17 621m 17 622m 8 627m 8 628m 17 638m 17 639m 8 659m 8 660m 57)
C1 N001 IN .1 Rser=10m
Rclass N004 IN 30.9
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
.lib LTC4265.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1516 692
WIRE -560 80 -1488 80
WIRE -496 80 -560 80
WIRE -384 80 -432 80
WIRE -224 80 -384 80
WIRE 320 80 -224 80
WIRE 400 80 320 80
WIRE 512 80 400 80
WIRE 624 80 512 80
WIRE 768 80 624 80
WIRE -560 112 -560 80
WIRE -224 112 -224 80
WIRE 400 112 400 80
WIRE -64 144 -96 144
WIRE 320 144 320 80
WIRE 320 144 288 144
WIRE 512 192 512 80
WIRE -384 224 -384 80
WIRE -224 224 -224 192
WIRE -64 224 -224 224
WIRE 400 224 400 192
WIRE 400 224 288 224
WIRE 624 224 624 80
WIRE 768 224 768 80
WIRE -1488 256 -1488 80
WIRE -64 304 -224 304
WIRE 512 304 512 272
WIRE 512 304 288 304
WIRE -224 336 -224 304
WIRE -96 384 -96 144
WIRE -64 384 -96 384
WIRE 320 384 288 384
WIRE -1488 464 -1488 336
WIRE -496 464 -1488 464
WIRE -384 464 -384 288
WIRE -384 464 -432 464
WIRE -224 464 -224 416
WIRE -224 464 -384 464
WIRE -96 464 -96 384
WIRE -96 464 -224 464
WIRE -64 464 -96 464
WIRE 320 464 320 384
WIRE 320 464 288 464
WIRE 624 464 624 288
WIRE 624 464 320 464
WIRE 768 464 768 304
WIRE 768 464 624 464
SYMBOL LTC4265 112 304 R0
WINDOW 0 0 -63 Center 2
WINDOW 3 0 78 Center 2
SYMATTR InstName U1
SYMBOL diode -432 480 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value MURS120
SYMBOL voltage -1488 240 R0
WINDOW 3 40 57 Left 2
WINDOW 123 22 102 Left 2
SYMATTR Value PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 8 555m 8 560m 4 610m 4
SYMATTR Value2 611m 17 621m 17 622m 8 627m 8 628m 17 638m 17 639m 8 659m 8 660m 57)
SYMATTR InstName VPSE
SYMBOL res -240 320 R0
SYMATTR InstName Rclass
SYMATTR Value 30.9
SYMBOL diode -496 64 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MURS120
SYMBOL res 496 176 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res -240 96 R0
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL res 752 208 R0
SYMATTR InstName Rload
SYMATTR Value 1.3K
SYMBOL cap -400 224 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 384 96 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap 608 224 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName Cload
SYMATTR Value 100
FLAG 768 464 OUT
FLAG -560 112 0
FLAG -384 464 IN
TEXT 392 576 Left 2 !.tran 1
TEXT -392 400 Right 2 ;Diode Bridge
TEXT -224 480 Top 2 ;Set for Class 4 Load
* Z:\home\khalils\Downloads\files\data\raw_asc\5f09ec375360_Fig23_4.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot VREF
R1 VDD VREF 1Meg TC1=0.002
VDD VDD 0 5
M6B VREF VREF 0 0 N_1u l=2u w=10u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.DC VDD 4 6 1m
.step temp 0 100 25
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1784 680
WIRE 1104 -32 1104 -64
WIRE 1104 -16 1104 -32
WIRE 1312 112 1312 16
WIRE 1328 112 1312 112
WIRE 1376 -96 1376 -160
WIRE 1376 0 1376 -16
WIRE 1376 16 1312 16
WIRE 1376 16 1376 0
WIRE 1376 32 1376 16
WIRE 1376 160 1376 128
WIRE 1488 0 1376 0
SYMBOL res 1360 -112 R0
SYMATTR InstName R1
SYMATTR Value 1MEG TC1=0.002
SYMBOL nmos4 1328 32 R0
WINDOW 123 56 100 Left 0
WINDOW 0 69 31 Left 0
SYMATTR Value2 l=2u w=10u
SYMATTR InstName M6B
SYMATTR Value N_1u
SYMBOL voltage 1104 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 5
FLAG 1104 64 0
FLAG 1104 -32 VDD
FLAG 1376 80 0
FLAG 1376 160 0
FLAG 1376 -160 VDD
FLAG 1488 0 VREF
TEXT 1016 136 Left 0 !.lib cmosedu_models.txt
TEXT 1160 -152 Left 0 ;Plot VREF
TEXT 1016 112 Left 0 !.DC VDD 4 6 1m
TEXT 1016 160 Left 0 !.step temp 0 100 25
* Z:\home\khalils\Downloads\files\data\raw_asc\295e110d07ca_AD8034.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8034.asy)
Rload OUT 0 10K
V1 +V 0 10
R1 N001 0 1K
XU1 IN N001 +V -V OUT AD8033 ;pnba In+)In-)V+)V-)OUT
R2 OUT N001 1K
Vin IN 0 SINE(0 1 100K)
V2 -V 0 -10
.tran 100u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 160 -1152 160 -1168
WIRE 272 -1152 272 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 736 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 736 -1088 736 -1104
WIRE 432 -1072 432 -1088
WIRE 160 -1040 160 -1072
WIRE 272 -1040 272 -1072
WIRE 736 -992 736 -1008
WIRE 432 -976 432 -992
SYMBOL voltage 160 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage 272 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -10
SYMBOL Opamps\\AD8034 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL res 720 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
FLAG 160 -1168 +V
FLAG 432 -976 0
FLAG 736 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 272 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 736 -992 0
FLAG 272 -1040 0
FLAG 160 -1040 0
TEXT 664 -944 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\2eb9a2fc9221_hw7_prob4.asc
* Generated by LTspice 26.0.1 for Windows.
* Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
R1 N001 0 15
C1 vout 0 1.6667m
R2 vout N001 1
I1 0 N001 0 AC 5 30
.options plotwinsize=0 numdgt=15 measdgt=15
.ac list {50/(2*pi)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 692
WIRE -176 -80 -384 -80
WIRE -112 -80 -176 -80
WIRE 0 -80 -32 -80
WIRE 16 -80 0 -80
WIRE -384 -32 -384 -80
WIRE -176 -32 -176 -80
WIRE 16 -16 16 -80
WIRE -384 128 -384 48
WIRE -208 128 -384 128
WIRE -176 128 -176 48
WIRE -176 128 -208 128
WIRE 16 128 16 48
WIRE 16 128 -176 128
WIRE -208 160 -208 128
SYMBOL res -400 -48 R0
SYMATTR InstName R1
SYMATTR Value 15
SYMBOL res -16 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL current -176 48 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 52 Left 2
SYMATTR InstName I1
SYMATTR Value 0
SYMATTR Value2 AC 5 30
SYMBOL cap 0 -16 R0
SYMATTR InstName C1
SYMATTR Value 1.6667m
FLAG -208 160 0
FLAG 0 -80 vout
TEXT -432 304 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ac list {50/(2*pi)}
TEXT -544 -648 Left 2 ;Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
* Z:\home\khalils\Downloads\files\data\raw_asc\edfd2651496d_mos_param_visibility.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc V1 0 5 .01
* How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
M2 out in vdd vdd PMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
M3 out in 0 0 NMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
V1 in 0 2.5
V2 vdd 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.model PMOS1 pmos level=2 nsub=4e15 tox=50n
.model NMOS1 nmos level=2 nsub=4e15 tox=50n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1404 948
WIRE 48 400 48 320
WIRE 48 544 48 480
WIRE 64 32 64 -32
WIRE 64 176 64 112
WIRE 112 320 48 320
WIRE 256 320 112 320
WIRE 256 320 256 160
WIRE 256 464 256 320
WIRE 352 160 256 160
WIRE 352 464 256 464
WIRE 400 -32 64 -32
WIRE 400 80 400 -32
WIRE 400 144 400 80
WIRE 400 320 400 240
WIRE 400 384 400 320
WIRE 400 544 400 480
WIRE 496 192 400 192
WIRE 496 432 400 432
WIRE 560 320 400 320
SYMBOL nmos4 352 384 R0
WINDOW 123 56 100 Left 0
SYMATTR InstName M3
SYMATTR Value NMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
SYMBOL voltage 64 16 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL pmos4 352 240 M180
WINDOW 0 59 69 Left 0
WINDOW 3 57 27 Left 0
WINDOW 123 57 -1 Left 0
SYMATTR InstName M2
SYMATTR Value PMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
SYMBOL voltage 48 384 R0
SYMATTR InstName V1
SYMATTR Value 2.5
FLAG 112 320 in
FLAG 400 544 0
FLAG 496 432 0
FLAG 496 192 vdd
FLAG 400 80 vdd
FLAG 560 320 out
FLAG 64 176 0
FLAG 48 544 0
TEXT 24 -104 Left 0 !.op
TEXT 24 624 Left 0 !.model PMOS1 pmos level=2 nsub=4e15 tox=50n\n.model NMOS1 nmos level=2 nsub=4e15 tox=50n
TEXT 24 -136 Left 0 ;.dc V1 0 5 .01
TEXT 16 -608 Left 0 ;How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
* Z:\home\khalils\Downloads\files\data\raw_asc\4bfdeb663ad2_2N7000_Input_Characteristic_Curve.asc
* Generated by LTspice 26.0.1 for Windows.
* https://www.youtube.com/watch?v=7WWJ2kfJ3oc
Vcc N001 0 12
Rc N001 Vds 0.001
Vg N002 0 0
M1 Vds N002 0 0 2N7000
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vg 1.5 20 .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1232 680
WIRE 448 16 256 16
WIRE 256 32 256 16
WIRE 256 128 256 112
WIRE 320 128 256 128
WIRE 256 144 256 128
WIRE 448 144 448 16
WIRE 208 224 48 224
WIRE 448 240 448 224
WIRE 48 272 48 224
WIRE 256 272 256 240
WIRE 48 368 48 352
SYMBOL voltage 48 256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vg
SYMATTR Value 0
SYMBOL voltage 448 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 12
SYMBOL res 240 16 R0
SYMATTR InstName Rc
SYMATTR Value 0.001
SYMBOL nmos 208 144 R0
SYMATTR InstName M1
SYMATTR Value 2N7000
FLAG 256 272 0
FLAG 448 240 0
FLAG 48 368 0
FLAG 320 128 Vds
TEXT 144 336 Left 2 !.dc Vg 1.5 20 .01
TEXT 584 16 Left 2 ;https://www.youtube.com/watch?v=7WWJ2kfJ3oc
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-2.5.asy)
Rload OUT 0 500
C1 OUT 0 10
XU1 IN 0 IN N001 OUT LT1761-2.5 ;pnba IN)GND)_SHDN)BYP)OUT
V1 IN 0 PWL(0 0 1 10)
C2 OUT N001 .01
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 48 -224 48
WIRE 16 48 -16 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE -16 144 -16 48
WIRE 16 144 -16 144
WIRE 336 144 336 128
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1761-2.5 160 96 R0
SYMATTR InstName U1
SYMBOL cap 320 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -224 48 IN
TEXT 360 224 Left 2 !.tran 1