* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4719.asc
* Generated by LTspice 26.0.1 for Windows.
* Battery Input
* Main Power Input
* 1.8V VOUT
* 2.3V VBUS
* Parameters A_REG and CD_REG can be defined by Ctrl + right click\non the LTM4719 symbol.\n \nA_REG default of 65295 and CD_REG of 65530 will test this circuit\nwith the over counter IRQ pulling low in ~215ms. M is set by bits\nA[4:0] of A_REG and AMAX is set by bits A[15:8] of the A_REG. \nCD_REG set the initial count.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4719.asy)
C5 VBUS 0 47
R4 N004 0 47.5k
R3 N003 0 549k
C2 N001 0 4.7
XU1 VINC 0 NC_01 NC_02 NC_03 NC_04 N001 N001 NC_05 NC_06 N001 NC_07 NC_08 VBUS 0 0 NC_09 N002 N002 N002 N002 N002 N001 N001 vIN vIN vOUT NC_10 NC_11 FB2 PRIORITY 0 N003 NC_12 N004 LTM4719 A_REG = 65295 CD_REG = 65530 ;pnba VINC)GND)BAL)IPK0)IPK1)IPK2)VOC)AVcc)_IRQ)VINCOK)DVcc)A_Reg)B_Reg)VBUS)VSET2)VSET1)EXTVcc)INTVcc)VREF)PWM_SYNC)EN2)EN1)SVIN2)VIN2)SVIN1)VIN1)VOUT)VALID1)VALID2)FB2)PRIORITY)DIODE)FB1)PG)RT
C3 vIN 0 10
V1 VINC 0 4.2
R2 FB2 0 124k
C4 vOUT 0 4.7
R1 vOUT FB2 100k
C1 N002 0 4.7
V2 vIN 0 12
.tran 1m startup
.lib LTM4719.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1952 1144
WIRE 240 -608 192 -608
WIRE 240 -560 240 -608
WIRE 400 -560 400 -592
WIRE -96 -480 -304 -480
WIRE 0 -480 -96 -480
WIRE 48 -480 0 -480
WIRE 720 -480 544 -480
WIRE 880 -480 720 -480
WIRE -96 -448 -96 -480
WIRE 880 -448 880 -480
WIRE -304 -432 -304 -480
WIRE 720 -400 720 -480
WIRE 0 -384 0 -480
WIRE 48 -384 0 -384
WIRE -96 -352 -96 -384
WIRE 880 -352 880 -384
WIRE -304 -336 -304 -352
WIRE 0 -288 -96 -288
WIRE 48 -288 0 -288
WIRE -96 -256 -96 -288
WIRE 0 -192 0 -288
WIRE 48 -192 0 -192
WIRE 624 -192 544 -192
WIRE 720 -192 720 -320
WIRE 720 -192 624 -192
WIRE -96 -160 -96 -192
WIRE 720 -144 720 -192
WIRE 0 -96 0 -192
WIRE 48 -96 0 -96
WIRE 720 -32 720 -64
WIRE 0 0 0 -96
WIRE 48 0 0 0
WIRE 0 96 0 0
WIRE 48 96 0 96
WIRE -64 192 -304 192
WIRE 48 192 -64 192
WIRE -304 224 -304 192
WIRE 48 288 0 288
WIRE 768 288 544 288
WIRE 784 288 768 288
WIRE -304 320 -304 304
WIRE 784 320 784 288
WIRE 0 384 0 288
WIRE 48 384 0 384
WIRE 784 432 784 384
WIRE 0 480 0 384
WIRE 48 480 0 480
WIRE 656 480 544 480
WIRE 656 512 656 480
WIRE 0 576 0 480
WIRE 48 576 0 576
WIRE 656 624 656 592
WIRE 0 672 0 576
WIRE 0 672 -112 672
WIRE 48 672 0 672
WIRE -112 736 -112 672
WIRE 656 768 544 768
WIRE 656 800 656 768
WIRE -112 864 -112 800
WIRE 48 864 0 864
WIRE 656 912 656 880
WIRE 0 960 0 864
WIRE 48 960 0 960
WIRE 0 1008 0 960
WIRE 288 1088 288 1056
SYMBOL res 640 496 R0
SYMATTR InstName R3
SYMATTR Value 549k
SYMBOL res 704 -416 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap -112 -448 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL cap 864 -448 R0
SYMATTR InstName C4
SYMATTR Value 4.7
SYMBOL cap -128 736 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL res 704 -160 R0
SYMATTR InstName R2
SYMATTR Value 124k
SYMBOL cap 768 320 R0
SYMATTR InstName C5
SYMATTR Value 47
SYMBOL voltage -304 -448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL LTM4719 288 624 R0
SYMATTR InstName U1
SYMBOL cap -112 -256 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL voltage -304 208 R0
SYMATTR InstName V1
SYMATTR Value 4.2
SYMBOL res 640 784 R0
SYMATTR InstName R4
SYMATTR Value 47.5k
FLAG 288 1088 0
FLAG 0 1008 0
FLAG -112 864 0
FLAG -304 320 0
FLAG -96 -160 0
FLAG -96 -352 0
FLAG 720 -32 0
FLAG 880 -352 0
FLAG 784 432 0
FLAG 656 624 0
FLAG 656 912 0
FLAG -304 -336 0
FLAG -304 -480 vIN
FLAG 880 -480 vOUT
FLAG 624 -192 FB2
FLAG 768 288 VBUS
FLAG -64 192 VINC
FLAG 192 -608 PRIORITY
FLAG 400 -592 0
TEXT -296 168 Left 2 ;Battery Input
TEXT -176 -496 Left 2 ;Main Power Input
TEXT 584 -496 Left 2 ;1.8V VOUT
TEXT 584 272 Left 2 ;2.3V VBUS
TEXT 800 1000 Left 2 !.tran 1m startup
TEXT 792 712 Left 2 ;Parameters A_REG and CD_REG can be defined by Ctrl + right click\non the LTM4719 symbol.\n \nA_REG default of 65295 and CD_REG of 65530 will test this circuit\nwith the over counter IRQ pulling low in ~215ms. M is set by bits\nA[4:0] of A_REG and AMAX is set by bits A[15:8] of the A_REG. \nCD_REG set the initial count.