* Z:\home\khalils\Downloads\files\data\raw_asc\fc90bb71f00b_rising_edge_dtype_latch_ltspice.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Qbar N001 Vp Vp CD4007-PMOS
M2 Qbar N001 0 0 CD4007-NMOS
M4 N001 W1 Q Vp CD4007-PMOS
M3 W2 W1 N001 0 CD4007-NMOS
M5 Q Qbar Vp Vp CD4007-PMOS
M6 Q Qbar 0 0 CD4007-NMOS
V1 Vp 0 5
V2 W1 0 PULSE(-1 5 0 1p 1p 0.5m 1m)
V3 W2 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL CD4007-NMOS NMOS ( LEVEL = 1 L=5u W=20u
+VTO = 1.77 Kp = 2.169e-4 GAMMA = 4.10
+PHI = 0.65 LAMBDA = 1.5e-2 CBD = 20e-12
+CBS = 0 IS = 1e-15 PB = 0.87
+CBS = 2e-14 CGDO = 88e-8 CGBO = 0
+CJ = 2e-10 MJ = 0.5 CJSW = 1e-9
+MJSW = 0.33 JS = 1e-8 TOX = 1.265e-10)
.MODEL CD4007-PMOS PMOS ( LEVEL = 1 L=5u W=100u
+VTO = -1.40 KP = 3.2e-5 GAMMA = 3.30
+PHI = 0.65 LAMBDA = 9e-2 CBD = 65e-12
+CBS = 2e-14 IS = 1e-15 PB = 0.87
+CGSO = 0 CGDO = 0 CGBO = 1e-5
+CJ = 2e-10 MJ = 0.5 CJSW = 1e-9
+MJSW = 0.33 JS = 1e-8 TOX = 6.89e-10)
.tran 5m
* 6 Transistor Rising Edge D-Type Latch
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2840 1020
WIRE 464 -192 -96 -192
WIRE 464 -128 464 -192
WIRE 272 -112 176 -112
WIRE -96 -80 -96 -192
WIRE -96 -80 -176 -80
WIRE 128 -80 32 -80
WIRE 176 -80 176 -112
WIRE 304 -80 224 -80
WIRE 384 -80 304 -80
WIRE 560 -80 480 -80
WIRE -96 0 -96 -80
WIRE 208 0 208 -32
WIRE 208 0 -96 0
WIRE 432 16 432 -80
WIRE 432 16 352 16
WIRE 304 32 304 -80
WIRE 304 32 32 32
WIRE -688 80 -688 48
WIRE -576 80 -576 48
WIRE -464 80 -464 48
WIRE 352 96 352 16
WIRE 352 96 144 96
WIRE 400 96 352 96
WIRE 416 96 400 96
WIRE 144 112 144 96
WIRE 400 112 400 96
WIRE 416 112 400 112
WIRE 32 128 32 32
WIRE 96 128 32 128
WIRE 352 128 304 128
WIRE 416 160 416 112
WIRE 416 160 400 160
WIRE -688 192 -688 160
WIRE -576 192 -576 160
WIRE -464 192 -464 160
WIRE 144 256 144 208
WIRE 304 256 304 128
WIRE 304 256 144 256
WIRE 400 256 400 208
WIRE 560 256 560 -80
WIRE 560 256 400 256
WIRE 640 256 640 240
WIRE 640 256 560 256
WIRE 656 256 640 256
WIRE 144 320 144 256
WIRE 400 320 400 256
WIRE 416 368 400 368
WIRE 32 400 32 128
WIRE 96 400 32 400
WIRE 304 400 304 256
WIRE 352 400 304 400
WIRE 416 416 416 368
WIRE 416 416 400 416
WIRE 144 432 144 416
WIRE 272 432 272 -112
WIRE 272 432 144 432
WIRE 400 432 400 416
WIRE 400 432 272 432
WIRE 144 464 144 432
WIRE 304 496 304 400
WIRE 544 496 304 496
FLAG 144 464 0
FLAG 32 -80 W2
IOPIN 32 -80 In
FLAG 656 256 Q
IOPIN 656 256 In
FLAG 544 496 Qbar
IOPIN 544 496 In
FLAG 640 240 2+
IOPIN 640 240 In
FLAG -688 192 0
FLAG -576 192 0
FLAG -464 192 0
FLAG -688 48 Vp
IOPIN -688 48 In
FLAG -576 48 W1
IOPIN -576 48 In
FLAG -464 48 W2
IOPIN -464 48 In
FLAG 416 96 Vp
IOPIN 416 96 In
FLAG -176 -80 W1
IOPIN -176 -80 In
SYMBOL pmos 96 208 M180
SYMATTR InstName M1
SYMATTR Value CD4007-PMOS
SYMBOL nmos 96 320 R0
SYMATTR InstName M2
SYMATTR Value CD4007-NMOS
SYMBOL pmos4 384 -128 M90
WINDOW 0 62 43 VLeft 2
WINDOW 3 89 105 VLeft 2
SYMATTR InstName M4
SYMATTR Value CD4007-PMOS
SYMBOL nmos4 128 -32 R270
WINDOW 0 65 6 VRight 2
WINDOW 3 111 -21 VRight 2
SYMATTR InstName M3
SYMATTR Value CD4007-NMOS
SYMBOL pmos4 352 208 M180
SYMATTR InstName M5
SYMATTR Value CD4007-PMOS
SYMBOL nmos4 352 320 R0
SYMATTR InstName M6
SYMATTR Value CD4007-NMOS
SYMBOL voltage -688 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -576 64 R0
WINDOW 3 -30 170 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(-1 5 0 1p 1p 0.5m 1m)
SYMATTR InstName V2
SYMBOL voltage -464 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
TEXT 832 368 Left 1 !.MODEL CD4007-NMOS    NMOS    ( LEVEL   = 1           L=5u    W=20u             \n+VTO    = 1.77          Kp      = 2.169e-4      GAMMA   = 4.10  \n+PHI    = 0.65          LAMBDA  = 1.5e-2        CBD     = 20e-12\n+CBS    = 0             IS      = 1e-15         PB      = 0.87\n+CBS    = 2e-14         CGDO    = 88e-8         CGBO    = 0\n+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9\n+MJSW   = 0.33          JS      = 1e-8          TOX     = 1.265e-10)
TEXT 824 200 Left 1 !.MODEL CD4007-PMOS    PMOS    ( LEVEL   = 1           L=5u    W=100u                \n+VTO    = -1.40         KP      = 3.2e-5        GAMMA   = 3.30  \n+PHI    = 0.65          LAMBDA  = 9e-2          CBD     = 65e-12\n+CBS    = 2e-14         IS      = 1e-15         PB      = 0.87\n+CGSO   = 0             CGDO    = 0             CGBO    = 1e-5\n+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9\n+MJSW   = 0.33          JS      = 1e-8          TOX     = 6.89e-10)
TEXT -512 448 Left 2 !.tran 5m
TEXT -56 -280 Left 2 ;6 Transistor Rising Edge D-Type Latch