* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4231-2.asc
* Generated by LTspice 26.0.1 for Windows.
MQ1 N001 N004 N002 N002 Si7164DP
C1 OUT 0 220
R1 N001 IN 22.5m
C2 N010 0 180n
R2 IN N005 1020K
R3 N005 N007 1.65K
R4 N007 N008 4.22K
R5 N008 N009 32.4K
V1 IN 0 PWL(0 0 1u 24)
S1 0 OUT N003 0 SLD
V2 N003 0 PULSE(0 1 100m 100n 100n 10m 1000m)
R6 OUT N006 20K
MQ2 OUT N004 N002 N002 SI5410DU
XU1 N001 IN IN N005 N007 N008 N009 0 N006 N010 N002 N004 LTC4231-2 ;pnba SENSE)IN)_SHDN)UVL)UVH)OV)GNDSW)GND)STATUS)TIMER)SOURCE)GATE
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 700m
.model SLD SW(Ron=1 Roff=1K Vt=.5 Vh=-.3)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4231-2.asy)
.lib LTC4231-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3644 720
WIRE 720 -128 -160 -128
WIRE -160 -64 -160 -128
WIRE -160 -64 -480 -64
WIRE 32 -64 -160 -64
WIRE 48 -64 32 -64
WIRE 160 -64 128 -64
WIRE 240 -64 160 -64
WIRE 448 -64 336 -64
WIRE 464 -64 448 -64
WIRE 640 -64 560 -64
WIRE 768 -64 640 -64
WIRE 880 -64 768 -64
WIRE -480 -48 -480 -64
WIRE 768 -48 768 -64
WIRE 880 -48 880 -64
WIRE -160 -32 -160 -64
WIRE 1008 -32 928 -32
WIRE 1008 -16 1008 -32
WIRE 320 0 320 -16
WIRE 480 0 480 -16
WIRE 480 0 320 0
WIRE 160 16 160 -64
WIRE 320 16 320 0
WIRE 944 16 928 16
WIRE 640 32 640 -64
WIRE -480 48 -480 32
WIRE -160 64 -160 48
WIRE 0 64 -160 64
WIRE 768 64 768 16
WIRE 880 64 880 32
WIRE -160 80 -160 64
WIRE 1008 80 1008 64
WIRE 32 96 32 -64
WIRE 64 96 32 96
WIRE 448 96 448 -64
WIRE 448 96 416 96
WIRE 0 160 0 64
WIRE 64 160 0 160
WIRE 640 160 640 112
WIRE 640 160 416 160
WIRE -160 176 -160 160
WIRE -32 176 -160 176
WIRE -160 192 -160 176
WIRE -32 224 -32 176
WIRE 64 224 -32 224
WIRE -160 288 -160 272
WIRE 64 288 -160 288
WIRE 720 288 720 -128
WIRE 720 288 416 288
WIRE -160 304 -160 288
WIRE 64 352 -16 352
WIRE 432 352 416 352
WIRE 512 352 496 352
WIRE -160 400 -160 384
WIRE -16 400 -16 352
WIRE -16 400 -160 400
WIRE 240 432 240 416
FLAG 768 64 0
FLAG 880 -64 OUT
FLAG 512 352 0
FLAG 240 432 0
FLAG -480 48 0
FLAG -480 -64 IN
FLAG 880 64 0
FLAG 1008 80 0
FLAG 944 16 0
SYMBOL nmos 240 -16 R270
WINDOW 0 53 47 VTop 2
WINDOW 3 8 91 VRight 2
SYMATTR InstName Q1
SYMATTR Value Si7164DP
SYMBOL cap 752 -48 R0
SYMATTR InstName C1
SYMATTR Value 220
SYMBOL res 144 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 22.5m
SYMBOL cap 432 368 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 180n
SYMBOL res -176 -48 R0
SYMATTR InstName R2
SYMATTR Value 1020K
SYMBOL res -176 64 R0
SYMATTR InstName R3
SYMATTR Value 1.65K
SYMBOL res -176 176 R0
SYMATTR InstName R4
SYMATTR Value 4.22K
SYMBOL res -176 288 R0
SYMATTR InstName R5
SYMATTR Value 32.4K
SYMBOL voltage -480 -64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1u 24)
SYMBOL sw 880 48 R180
WINDOW 0 -14 97 Right 2
WINDOW 3 -12 9 Right 2
SYMATTR InstName S1
SYMATTR Value SLD
SYMBOL voltage 1008 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 100m 100n 100n 10m 1000m)
SYMBOL res 624 16 R0
SYMATTR InstName R6
SYMATTR Value 20K
SYMBOL nmos 560 -16 M270
WINDOW 0 57 34 VTop 2
WINDOW 3 -13 72 VLeft 2
SYMATTR InstName Q2
SYMATTR Value SI5410DU
SYMBOL LTC4231-2 240 224 R0
SYMATTR InstName U1
TEXT 624 360 Left 2 !.tran 700m\n.model SLD SW(Ron=1 Roff=1K Vt=.5 Vh=-.3)