* Z:\home\khalils\Downloads\files\data\raw_asc\LT4220.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT4220.asy)
R8 N010 IN- 36.5K
R12 OUT+ N006 36.5K
C3 N009 0 1
R1 IN+ N004 100K
R2 N001 IN+ 5m
C1 0 N003 10n Rser=1K
R14 N006 0 4.99K
V2 0 IN- PULSE(0 12 0 20u 1u 200m 250m)
I1 OUT+ 0 PWL(0 0 60m 0 120m 10 200m 10 260m 0) load
R11 OUT+ N008 20K
R3 N002 N003 10
C8 OUT+ 0 33 Rser=25m
C2 0 N010 10n
R15 0 N011 4.99K
XU1 N013 IN- N015 N012 N011 N010 N004 N009 0 N008 N007 N005 N006 N003 N001 IN+ LT4220 ;pnba VEE)SENSEK)SENSE-)GATE-)FB-)ON-)TRACK)TIMER)GND)PWRGD)_FAULT)ON+)FB+)GATE+)SENSE+)Vcc
C5 N013 0 0.1
R18 N012 N014 10
I2 0 OUT- PWL(0 0 60m 0 120m 10 200m 10 260m 0) load
R5 IN+ N005 36.5K
R10 N015 IN- 5m
R7 0 N010 4.99K
MQ1 N001 N002 OUT+ OUT+ SUM85N03-06P
C9 0 OUT- 33 Rser=25m
R4 IN+ N007 20K
C6 OUT- N012 10n Rser=1K
R17 0 OUT- 10
R16 OUT+ 0 10
C4 N005 0 10n
MQ2 OUT- N014 N015 N015 SUM85N03-06P
V1 IN+ 0 PULSE(0 12 0 20u 1u 200m 250m)
C7 N012 N015 100n
R13 N011 OUT- 36.5K
R9 N013 IN- 1
R6 N005 0 4.99K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 400m startup
.lib LT4220.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
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WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
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SYMBOL cap -2896 -784 R90
WINDOW 0 0 32 VBottom 2
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TEXT -2040 -512 Left 2 !.tran 400m startup