Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\62bdc00b1dee_ideal_mult.asc
* Generated by LTspice 26.0.1 for Windows.
* input signals
* internally generated signals
* output signals
* Simulation of analog multiplier
* V1 and V2 represent input signals A and B
* B1 is the inverter for the signal A
* V2 is the internal triangle wave generator
* B2 represents the analog switch which is controlled by a comparator
* B3 generates a reference signal which is the real multiplication of A and B
* ----------------------------------------------
B1 Aneg 0 V=-V(A)
V3 ref 0 PULSE(-1 1 0 0.5u 0.5u 0 1u)
B3 out_mult 0 V=V(A)*V(B)
V2 B 0 SINE(0 1 40k)
R1 N001 out 1k
B2 N001 0 V=if(V(B)>V(ref),V(A),V(Aneg))
V1 A 0 SINE(0 1 41k)
C1 out 0 1n
.tran 0 10m 0 10n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1716 680
WIRE 592 32 416 32
WIRE 928 32 720 32
WIRE 1408 32 1120 32
WIRE 1520 32 1488 32
WIRE 1584 32 1520 32
WIRE 416 48 416 32
WIRE 720 48 720 32
WIRE 1120 48 1120 32
WIRE 1520 48 1520 32
WIRE 1520 128 1520 112
WIRE 592 176 416 176
WIRE 928 176 720 176
WIRE 1584 176 1120 176
WIRE 416 192 416 176
WIRE 720 192 720 176
WIRE 1120 192 1120 176
SYMBOL cap 1504 48 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL bv 720 32 R0
SYMATTR InstName B1
SYMATTR Value V=-V(A)
SYMBOL bv 1120 32 R0
SYMATTR InstName B2
SYMATTR Value V=if(V(B)>V(ref),V(A),V(Aneg))
SYMBOL voltage 416 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 1 40k)
SYMBOL voltage 416 32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 41k)
SYMBOL res 1392 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL bv 1120 176 R0
SYMATTR InstName B3
SYMATTR Value V=V(A)*V(B)
SYMBOL voltage 720 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 0.5u 0.5u 0 1u)
FLAG 416 128 0
FLAG 416 272 0
FLAG 592 32 A
FLAG 592 176 B
FLAG 720 128 0
FLAG 720 272 0
FLAG 928 176 ref
FLAG 928 32 Aneg
FLAG 1120 128 0
FLAG 1120 272 0
FLAG 1584 32 out
FLAG 1584 176 out_mult
FLAG 1520 128 0
TEXT 424 -48 Left 2 ;input signals
TEXT 704 -48 Left 2 ;internally generated signals
TEXT 1256 -48 Left 2 ;output signals
TEXT 382 360 Left 2 !.tran 0 10m 0 10n
TEXT 384 -160 Left 3 ;Simulation of analog multiplier
TEXT 384 464 Left 2 ;V1 and V2 represent input signals A and B
TEXT 384 496 Left 2 ;B1 is the inverter for the signal A
TEXT 384 528 Left 2 ;V2 is the internal triangle wave generator
TEXT 384 560 Left 2 ;B2 represents the analog switch which is controlled by a comparator
TEXT 384 592 Left 2 ;B3 generates a reference signal which is the real multiplication of A and B
TEXT 384 -136 Left 3 ;----------------------------------------------
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1844-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1844-2.5.asy)
C1 OUT 0 1
XU1 IN 0 IN OUT LTC1844-2.5 ;pnba IN)GND)_SHDN)OUT
V1 IN 0 PWL(0 0 1 6.5)
R1 OUT 0 17
.tran 1
.lib LTC1844-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1940 1316
WIRE 64 80 -32 80
WIRE 80 80 64 80
WIRE 432 80 368 80
WIRE 528 80 432 80
WIRE -32 96 -32 80
WIRE 528 96 528 80
WIRE 432 112 432 80
WIRE -32 192 -32 176
WIRE 432 192 432 176
WIRE 528 192 528 176
WIRE 64 240 64 80
WIRE 80 240 64 240
WIRE 224 304 224 288
SYMBOL cap 416 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL LTC1844-2.5 224 160 R0
SYMATTR InstName U1
SYMBOL res 512 80 R0
SYMATTR InstName R1
SYMATTR Value 17
SYMBOL voltage -32 80 R0
WINDOW 3 -89 162 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PWL(0 0 1 6.5)
SYMATTR InstName V1
FLAG 224 304 0
FLAG -32 192 0
FLAG 528 192 0
FLAG 528 80 OUT
FLAG -32 80 IN
FLAG 432 192 0
TEXT 184 368 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\2096ddd98fcd_InverseLogarithmicPotentiometer.asc
* Generated by LTspice 26.0.1 for Windows.
Ra 1 2 R=Rp*(1-a*pow(b,1-x)-c)+tol
Rb 2 3 R=Rp*(a*pow(b,1-x)+c)+tol
.param tol=1u Rm=0.1
.param b=pow(1/Rm-1,2)
.param a=1/(b-1)
.param c=-a
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 0 128 0
WIRE 208 48 208 0
WIRE 208 176 208 128
WIRE 288 176 208 176
WIRE 208 224 208 176
WIRE 208 352 208 304
WIRE 208 352 128 352
FLAG 128 0 1
FLAG 128 352 3
FLAG 288 176 2
SYMBOL res 192 32 R0
SYMATTR InstName Ra
SYMATTR Value R=Rp*(1-a*pow(b,1-x)-c)+tol
SYMBOL res 192 208 R0
SYMATTR InstName Rb
SYMATTR Value R=Rp*(a*pow(b,1-x)+c)+tol
TEXT -256 96 Left 2 !.param tol=1u Rm=0.1
TEXT -256 128 Left 2 !.param b=pow(1/Rm-1,2)
TEXT -256 160 Left 2 !.param a=1/(b-1)
TEXT -256 192 Left 2 !.param c=-a
* Z:\home\khalils\Downloads\files\data\raw_asc\ADGM1121.asc
* Generated by LTspice 26.0.1 for Windows.
V1 RF1A 0 2
V2 N001 0 PULSE(3.3 0 0 10u 10u 10m 20m)
V3 +V 0 3.3
R1 RFCA 0 300
XU1 +V N001 RF1A RFCA 0 ADGM1121 ;pnba VDD)IN1)RF1A)RFCA)GND
.tran 100m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADGM1121.asy)
.lib ADGM1121.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2144 2724
WIRE 912 96 912 32
WIRE 656 176 624 176
WIRE 768 176 736 176
WIRE 816 176 768 176
WIRE 1056 176 1008 176
WIRE 1088 176 1056 176
WIRE 1088 192 1088 176
WIRE 816 240 736 240
WIRE 1088 288 1088 272
WIRE 560 304 560 240
WIRE 736 304 736 240
WIRE 912 368 912 352
WIRE 560 416 560 384
WIRE 736 432 736 384
FLAG 624 176 0
FLAG 1088 288 0
FLAG 912 368 0
FLAG 736 432 0
FLAG 912 32 +V
FLAG 560 416 0
FLAG 560 240 +V
FLAG 768 176 RF1A
FLAG 1056 176 RFCA
SYMBOL voltage 752 176 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL voltage 736 288 R0
WINDOW 3 33 134 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(3.3 0 0 10u 10u 10m 20m)
SYMATTR InstName V2
SYMBOL voltage 560 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 3.3
SYMBOL res 1072 176 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL ADGM1121 912 224 R0
SYMATTR InstName U1
TEXT 1240 440 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\4bfdeb663ad2_2N7000_Input_Characteristic_Curve.asc
* Generated by LTspice 26.0.1 for Windows.
* https://www.youtube.com/watch?v=7WWJ2kfJ3oc
Vg N002 0 0
M1 Vds N002 0 0 2N7000
Vcc N001 0 12
Rc N001 Vds 0.001
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vg 1.5 20 .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1232 680
WIRE 448 16 256 16
WIRE 256 32 256 16
WIRE 256 128 256 112
WIRE 320 128 256 128
WIRE 256 144 256 128
WIRE 448 144 448 16
WIRE 208 224 48 224
WIRE 448 240 448 224
WIRE 48 272 48 224
WIRE 256 272 256 240
WIRE 48 368 48 352
SYMBOL voltage 48 256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vg
SYMATTR Value 0
SYMBOL nmos 208 144 R0
SYMATTR InstName M1
SYMATTR Value 2N7000
SYMBOL voltage 448 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 12
SYMBOL res 240 16 R0
SYMATTR InstName Rc
SYMATTR Value 0.001
FLAG 256 272 0
FLAG 448 240 0
FLAG 48 368 0
FLAG 320 128 Vds
TEXT 144 336 Left 2 !.dc Vg 1.5 20 .01
TEXT 584 16 Left 2 ;https://www.youtube.com/watch?v=7WWJ2kfJ3oc
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3129.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3129.asy)
C2 N002 N004 22n
R2 N005 0 1.02Meg
R4 N006 0 100K
R1 OUT N005 3.32Meg
L1 N001 N002 10 Rser=20m
C4 OUT N005 10p
V1 IN 0 12
XU1 0 N003 N001 MP_01 IN N006 N007 N007 N005 N004 0 N002 NC_02 OUT LTC3129 ;pnba GND)BST1)SW1))Vin)RUN)Vcc)MPPC)FB)BST2)PWM)SW2)Pgood)Vout
C5 OUT 0 10 Rser=1m
Rload OUT 0 25
C3 N007 0 2.2
C1 N001 N003 22n
R3 IN N006 680K
.tran 5m startup
.lib LTC3129.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -96 -16 -96
WIRE 160 -96 144 -96
WIRE 400 -96 240 -96
WIRE -16 -64 -16 -96
WIRE 400 -64 400 -96
WIRE 144 -32 144 -96
WIRE 240 -32 240 -96
WIRE -16 32 -16 0
WIRE 48 32 -16 32
WIRE 400 32 400 0
WIRE 400 32 336 32
WIRE -48 128 -160 128
WIRE 48 128 -48 128
WIRE 400 128 336 128
WIRE 480 128 400 128
WIRE 640 128 480 128
WIRE 768 128 640 128
WIRE -160 144 -160 128
WIRE 400 144 400 128
WIRE 768 144 768 128
WIRE 640 160 640 128
WIRE -48 192 -48 128
WIRE 48 224 32 224
WIRE 400 224 400 208
WIRE 400 224 336 224
WIRE 480 224 480 208
WIRE 480 224 400 224
WIRE -160 240 -160 224
WIRE 480 240 480 224
WIRE 640 240 640 224
WIRE 768 240 768 224
WIRE -144 320 -176 320
WIRE -48 320 -48 272
WIRE -48 320 -64 320
WIRE 48 320 -48 320
WIRE 384 320 336 320
WIRE 480 336 480 320
WIRE 384 416 384 320
WIRE 384 416 336 416
WIRE 384 432 384 416
WIRE 192 496 192 480
WIRE 384 512 384 496
SYMBOL res -48 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL cap 624 160 R0
WINDOW 3 23 56 Left 2
SYMATTR Value 10
SYMATTR SpiceLine Rser=1m
SYMATTR InstName C5
SYMBOL res 464 224 R0
WINDOW 3 34 81 Left 2
SYMATTR Value 1.02Meg
SYMATTR InstName R2
SYMBOL cap 384 -64 R0
SYMATTR InstName C2
SYMATTR Value 22n
SYMBOL voltage -160 128 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL LTC3129 192 224 R0
SYMATTR InstName U1
SYMBOL res 752 128 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL cap -32 -64 R0
SYMATTR InstName C1
SYMATTR Value 22n
SYMBOL res -64 176 R0
SYMATTR InstName R3
SYMATTR Value 680K
SYMBOL cap 368 432 R0
SYMATTR InstName C3
SYMATTR Value 2.2
SYMBOL res 464 112 R0
WINDOW 3 31 91 Left 2
SYMATTR Value 3.32Meg
SYMATTR InstName R1
SYMBOL cap 384 144 R0
SYMATTR InstName C4
SYMATTR Value 10p
SYMBOL ind 144 -80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=20m
FLAG 192 496 0
FLAG -160 240 0
FLAG 384 512 0
FLAG 480 336 0
FLAG 640 240 0
FLAG 768 240 0
FLAG 768 128 OUT
FLAG -160 128 IN
FLAG -176 320 0
FLAG 32 224 0
TEXT 520 440 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8691.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8691.asy)
R1 N001 0 1K
V2 -V 0 -2.5
XU1 IN N001 +V -V OUT AD8691 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 2.5
Vin IN 0 SINE(0 1 100K)
Rload OUT 0 2K
R2 OUT N001 1K
.tran 100u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL Opamps\\AD8691 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 2K
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
FLAG 144 -1168 +V
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 768 -992 0
FLAG 256 -1056 0
FLAG 144 -1056 0
TEXT 720 -936 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8552.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 IN N001 +V -V OUT AD8552 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 5
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -5
Rload OUT 0 10K
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8552.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 240 -992 224 -992
WIRE 336 -992 320 -992
WIRE 352 -992 336 -992
WIRE 448 -992 432 -992
WIRE -16 -896 -16 -912
WIRE 80 -896 80 -912
WIRE 336 -880 336 -992
WIRE 352 -880 336 -880
WIRE 448 -864 448 -992
WIRE 448 -864 416 -864
WIRE 560 -864 448 -864
WIRE 352 -848 240 -848
WIRE 560 -848 560 -864
WIRE 240 -832 240 -848
WIRE -16 -800 -16 -816
WIRE 80 -800 80 -816
WIRE 560 -752 560 -768
WIRE 240 -736 240 -752
FLAG -16 -912 +V
FLAG -16 -800 0
FLAG 240 -736 0
FLAG 560 -864 OUT
FLAG 240 -848 IN
FLAG 384 -896 +V
FLAG 80 -912 -V
FLAG 384 -832 -V
FLAG 224 -992 0
FLAG 560 -752 0
FLAG 80 -800 0
SYMBOL Opamps\\AD8552 384 -928 R0
SYMATTR InstName U1
SYMBOL voltage -16 -912 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 240 -848 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 336 -1008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 448 -1008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 80 -912 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 544 -864 R0
SYMATTR InstName Rload
SYMATTR Value 10K
TEXT 496 -712 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ba2c0dca089b_BJT-for-simple-current-regulation.asc
* Generated by LTspice 26.0.1 for Windows.
* Adjusting the potentiometer, the current through R1 is (approximately)\nlinearly regulated.
* Sizing: \n \nAssume BJT works in saturation -> Vce = 0.3. On the load the voltage drop is 4.7V,\nAssume the load draws 100 mA.\n \nBase current for the polarization is Ic/hfe. Assuming a hfe of 100 the required base\ncurrent is 100ma/100 = 1mA\n \nVbe is fixed at 0.8 V (PN junction). I set R2 so as to have exactly 1 mA of base current\ni.e. R2 = 4.2/0.001 = 4.2k
* BJT for simple current regulation
RPot Vin N002 {10k*x}
RPotenziometro N002 0 {10k*(1-x)}
V1 Vin 0 5
R1 Vin N001 47
R2 N003 N002 4.2k
Q1 N001 N003 0 0 2N3904
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.step param x 1n 0.99 0.5
.tran 1s
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1704 680
WIRE -16 16 -16 0
WIRE 272 64 272 32
WIRE 80 80 80 48
WIRE 272 176 272 144
WIRE 80 224 80 160
WIRE 112 224 80 224
WIRE 208 224 192 224
WIRE 272 288 272 272
WIRE 80 304 80 224
SYMBOL voltage -16 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 64 64 R0
SYMATTR InstName Pot
SYMATTR Value {10k*x}
SYMBOL res 256 48 R0
SYMATTR InstName R1
SYMATTR Value 47
SYMBOL res 208 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 4.2k
SYMBOL npn 208 176 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 64 288 R0
SYMATTR InstName Potenziometro
SYMATTR Value {10k*(1-x)}
FLAG 80 384 0
FLAG 272 288 0
FLAG -16 0 Vin
FLAG 272 32 Vin
FLAG -16 96 0
FLAG 80 48 Vin
TEXT 360 128 Left 2 !.step param x 1n 0.99 0.5
TEXT 360 168 Left 2 !.tran 1s
TEXT -120 -144 Left 2 ;Adjusting the potentiometer, the current through R1 is (approximately)\nlinearly regulated.
TEXT 456 240 Left 2 ;Sizing: \n \nAssume BJT works in saturation -> Vce = 0.3. On the load the voltage drop is 4.7V,\nAssume the load draws 100 mA.\n \nBase current for the polarization is Ic/hfe. Assuming a hfe of 100 the required base\ncurrent is 100ma/100 = 1mA\n \nVbe is fixed at 0.8 V (PN junction). I set R2 so as to have exactly 1 mA of base current\ni.e. R2 = 4.2/0.001 = 4.2k
TEXT 368 -264 Left 4 ;BJT for simple current regulation
* Z:\home\khalils\Downloads\files\data\raw_asc\006824e455ed_rectifier_halfwave_filter.asc
* Generated by LTspice 26.0.1 for Windows.
D1 IN OUT 1N4148
V1 IN 0 SINE(0 5 60 0 0 0 3)
R1 OUT 0 100
C1 OUT 0 {Cf}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 50m
.step param Cf list 22u 47u 100u 220u 470u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 956
WIRE 112 464 96 464
WIRE 208 464 112 464
WIRE 352 464 272 464
WIRE 368 464 352 464
WIRE 512 464 368 464
WIRE 96 496 96 464
WIRE 368 496 368 464
WIRE 512 496 512 464
WIRE 96 608 96 576
WIRE 368 608 368 560
WIRE 368 608 96 608
WIRE 512 608 512 576
WIRE 512 608 368 608
WIRE 96 640 96 608
FLAG 96 640 0
FLAG 112 464 IN
FLAG 352 464 OUT
SYMBOL diode 208 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL voltage 96 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 60 0 0 0 3)
SYMBOL res 496 480 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL cap 352 496 R0
SYMATTR InstName C1
SYMATTR Value {Cf}
TEXT 112 696 Left 2 !.tran 50m
TEXT 112 728 Left 2 !.step param Cf list 22u 47u 100u 220u 470u
* Z:\home\khalils\Downloads\files\data\raw_asc\10d4decf18b0_Trans-sw.asc
* Generated by LTspice 26.0.1 for Windows.
V1 VIN 0 PULSE(0 12 0 0.001 0.001 0.004 0.010)
Q1 VOUT VBE 0 0 NPN
R2 VBE VIN 10000
R3 VOUT 0 1000000
V2 N001 0 5
R1 N001 VOUT 10000
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0 0.05 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 16 240 16
WIRE 240 48 240 16
WIRE 384 48 384 16
WIRE 64 112 -16 112
WIRE 240 144 240 128
WIRE 240 160 240 144
WIRE 512 160 240 160
WIRE -16 176 -16 112
WIRE 64 208 64 112
WIRE 160 208 144 208
WIRE 176 208 160 208
WIRE -16 288 -16 256
WIRE 240 288 240 256
WIRE 512 288 512 240
SYMBOL res 160 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10000
SYMBOL res 496 144 R0
SYMATTR InstName R3
SYMATTR Value 1000000
SYMBOL res 224 32 R0
SYMATTR InstName R1
SYMATTR Value 10000
SYMBOL voltage -16 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -255 109 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 12 0 0.001 0.001 0.004 0.010)
SYMBOL npn 176 160 R0
SYMATTR InstName Q1
SYMBOL Misc\\battery 384 32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
FLAG 240 288 0
FLAG -16 288 0
FLAG -16 112 VIN
FLAG 240 144 VOUT
FLAG 512 288 0
FLAG 384 128 0
FLAG 160 208 VBE
TEXT -272 56 Left 2 !.tran 0 0.05 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-3.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-3.5.asy)
C1 OUT 0 10
L1 N001 N002 1.5 Rser=80m
V1 IN 0 3.3
Rload OUT 0 50
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-3.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
.tran 400u startup
.lib ADP2504-3.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 384 224 320 224
WIRE 496 224 384 224
WIRE 384 240 384 224
WIRE 496 240 496 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 384 336 384 304
WIRE 496 336 496 320
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 480 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2504-3.5 176 176 R0
SYMATTR InstName U1
SYMBOL cap 368 240 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 384 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 496 336 0
FLAG 496 224 OUT
FLAG -64 64 IN
TEXT 432 376 Left 2 !.tran 400u startup
TEXT 192 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\18fd5b447ecb_KVL.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N001 470
V1 N003 0 10
R2 N003 N002 330
R3 0 N002 680
V2 0 N001 5
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -272 80 -336 80
WIRE -144 80 -192 80
WIRE -112 80 -144 80
WIRE 48 80 -32 80
WIRE -336 112 -336 80
WIRE -144 112 -144 80
WIRE 48 112 48 80
WIRE -144 192 -336 192
WIRE 48 192 -144 192
WIRE -144 256 -144 192
DATAFLAG 48 80 "$-V(N002)"
DATAFLAG -144 80 ""
DATAFLAG -144 80 ""
DATAFLAG -336 80 "$-V(N002)"
SYMBOL res -176 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 470
SYMBOL res -128 208 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 680
SYMBOL res -16 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 330
SYMBOL Misc\\battery -336 208 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL Misc\\battery 48 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
FLAG -144 256 0
TEXT -64 168 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\Transformer2.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* A transformer with three windings
R1 N001 IN 10
L3 B 0 400
V1 IN 0 PULSE(0 1 0 10n 10n 5u 10u)
K1 L1 L2 L3 1
L2 A 0 400
L1 0 N001 100
.tran 100u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 96 160 96
WIRE 160 112 160 96
WIRE -128 176 -288 176
WIRE 112 176 -48 176
WIRE -288 192 -288 176
WIRE 112 192 112 176
WIRE 160 208 160 192
WIRE 352 240 160 240
WIRE 160 256 160 240
WIRE -288 288 -288 272
WIRE 112 288 112 272
WIRE 160 352 160 336
SYMBOL ind2 176 240 M0
WINDOW 0 -10 36 Right 2
WINDOW 3 -10 73 Right 2
SYMATTR InstName L3
SYMATTR Value 400
SYMATTR Type ind
SYMBOL res -32 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage -288 176 R0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 10n 10n 5u 10u)
SYMBOL ind2 176 96 M0
WINDOW 0 -10 36 Right 2
WINDOW 3 -8 74 Right 2
SYMATTR InstName L2
SYMATTR Value 400
SYMATTR Type ind
SYMBOL ind2 96 288 M180
WINDOW 0 -15 80 Right 2
WINDOW 3 -7 42 Right 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR Type ind
FLAG -288 288 0
FLAG 160 352 0
FLAG 112 288 0
FLAG 160 208 0
FLAG 352 96 A
FLAG 352 240 B
FLAG -288 176 IN
TEXT 136 96 Bottom 2 !K1 L1 L2 L3 1
TEXT 280 352 Left 2 !.tran 100u
TEXT 32 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT 48 24 Bottom 2 ;A transformer with three windings