* Z:\home\khalils\Downloads\files\data\raw_asc\0e2a76aaa803_AD4001_THDD_V01.asc
* Generated by LTspice 26.0.1 for Windows.
* Driver Supply
* ADC Supply
* Simulation Setup
* Simulation Parameters
* Anti Aliasing Filter
* Simulation cycles\nSample size\nADC reference voltage\nADC supply\nDriver VCC\nDriver VEE\nDC offset voltage\nSample frequency\nSample Period\nInput frequency\nInput amplitude\nMax time step\nSimulation end
* Rval1\nCval1\nRval2\nCval2
* AD4001_THDD_V01
* This circuit may be used to obtain THD results for the AD4001 series differential ADC\n using the AD4003 macro-model with an AD4807-2 driver in a non-inverting gain differential configuration.\n Additional driver models may be inserted via the component menu. Schematic redraw may\n be required. Simulation results produced by the .four SPICE command may be accessed by \nview->SPICE error log and are displayed at the end of the file. For all other performance \ncharacteristics and specifications refer to the AD4001 datasheet located at\nhttps://www.analog.com/en/products/ad4001.html#product-overview
* Anti-Aliasing Filter
* ADC Driver
* Input
* Driver Parameters
* U1 Rf\nU1 Rg\nGain\nU2 Rf\nU2 Rg
* Library below included based on ModelFile attribute of instance XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4003.asy)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4807-2.asy)
V6 REF 0 {vref_val}
R3 N002 N001 {Rf1_val}
V4 N003 0 PULSE(0 {vdd_val} 1u 1n 1n 10n {ts})
V2 0 VINN SINE({-vcm} {vmag} {fin} 0 0 0)
XU2 VINN N005 VCC VEE N004 VCC ADA4807 ;pnba 100)101)102)103)104)106
XU1 VINP N001 VCC VEE N002 VCC ADA4807 ;pnba 100)101)102)103)104)106
V8 VEE 0 {vee_val}
V9 VDD 0 {vdd_val}
R5 N001 0 {Rg1_val}
R2 ADCINN N004 {Rval2}
C1 ADCINP 0 {Cval1}
XU3 REF VDD ADCINP MP_01 0 ADCINN VSAMPLED N003 AD4003 EN_Hi_Z=1 ;pnba REF)Vdd)IN+))GND)IN-)Vout)CNV
R1 ADCINP N002 {Rval1}
V7 VCC 0 {vcc_val}
V1 VINP 0 SINE({vcm} {vmag} {fin} 0 0 0)
R4 N004 N005 {Rf2_val}
C2 ADCINN 0 {Cval2}
R6 N005 0 {Rg2_val}
.param M=3
.param N=4096
.param vref_val=5
.param vdd_val=1.8
.param vcc_val=15
.param vee_val=-15
.param vcm=vref_val/{2*Gain}
.param fs=2e6
.param ts=1/fs
.param fin= fs*M/N
.param vmag=.93*vref_val/{2*Gain}
.param tmax=1/(fs)
.param END_SIM=M*(1/fin)
.save v(vsampled)
.option plotwinsize=0 numdgt=15
.four {fin} 5 -1 v(vsampled)
.param Rval1=200
.param Cval1=180p
.param Rval2=Rval1
.param Cval2=Cval1
.tran 0 {END_SIM+1/fin} {1/fin} {tmax}
.param Rf2_val=Rf1_val
.param Rg2_val=Rg1_val
.param Rf1_val=1K
.param Rg1_val=1K
.param Gain = { Rf1_val/Rg1_val + 1}
.lib AD4003.sub
.lib ADA4807.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3184 1252
WIRE 464 -384 352 -384
WIRE 624 -384 464 -384
WIRE 352 -320 352 -384
WIRE -816 -256 -832 -256
WIRE -704 -256 -736 -256
WIRE -640 -256 -704 -256
WIRE -512 -256 -560 -256
WIRE 352 -176 352 -240
WIRE -608 -128 -608 -160
WIRE -704 -112 -704 -256
WIRE -624 -112 -704 -112
WIRE -512 -96 -512 -256
WIRE -512 -96 -560 -96
WIRE -304 -96 -512 -96
WIRE -144 -96 -224 -96
WIRE 64 -96 -144 -96
WIRE -720 -80 -976 -80
WIRE -624 -80 -720 -80
WIRE 624 -80 624 -384
WIRE -976 -48 -976 -80
WIRE -144 -48 -144 -96
WIRE -608 -32 -608 -64
WIRE -576 -32 -576 -64
WIRE 896 -32 896 -176
WIRE 896 -32 752 -32
WIRE 64 16 64 -96
WIRE 224 16 64 16
WIRE 384 16 224 16
WIRE 384 48 384 16
WIRE 400 48 384 48
WIRE -976 64 -976 32
WIRE -976 64 -1040 64
WIRE -144 64 -144 16
WIRE -144 64 -224 64
WIRE 1056 64 752 64
WIRE 400 80 384 80
WIRE -976 96 -976 64
WIRE -144 112 -144 64
WIRE 224 112 64 112
WIRE 384 112 384 80
WIRE 384 112 224 112
WIRE 896 160 752 160
WIRE -608 192 -608 160
WIRE -576 192 -576 160
WIRE -976 208 -976 176
WIRE -720 208 -976 208
WIRE -624 208 -720 208
WIRE -512 224 -560 224
WIRE -304 224 -512 224
WIRE -144 224 -144 176
WIRE -144 224 -224 224
WIRE 64 224 64 112
WIRE 64 224 -144 224
WIRE -624 240 -704 240
WIRE 624 240 624 208
WIRE -608 288 -608 256
WIRE -816 384 -832 384
WIRE -704 384 -704 240
WIRE -704 384 -736 384
WIRE -640 384 -704 384
WIRE -512 384 -512 224
WIRE -512 384 -560 384
WIRE 896 416 896 160
WIRE -2048 592 -2048 496
WIRE -1792 592 -1792 496
WIRE -1520 592 -1520 496
WIRE 896 592 896 496
WIRE -2048 768 -2048 672
WIRE -1792 768 -1792 672
WIRE -1520 768 -1520 672
IOPIN 1056 64 Out
RECTANGLE Normal -1360 800 -2208 384 4
RECTANGLE Normal -2208 -592 -1360 -432
RECTANGLE Normal -1360 368 -2208 -416 4
RECTANGLE Normal 32 464 -352 -304 4
RECTANGLE Normal -368 464 -864 -304 4
RECTANGLE Normal -880 464 -1072 -304 4
SYMBOL voltage -976 80 R0
WINDOW 0 -32 56 VBottom 2
WINDOW 3 -38 292 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE({-vcm} {vmag} {fin} 0 0 0)
SYMBOL Opamps\\ADA4807-2 -592 -96 R0
SYMATTR InstName U1
SYMBOL voltage -2048 576 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V7
SYMATTR Value {vcc_val}
SYMBOL voltage -1792 576 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V8
SYMATTR Value {vee_val}
SYMBOL voltage 896 400 R0
WINDOW 3 58 -156 VRight 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 {vdd_val} 1u 1n 1n 10n {ts})
SYMATTR InstName V4
SYMBOL ADC\\AD4003 656 64 R0
SYMATTR InstName U3
SYMBOL cap -160 -48 R0
SYMATTR InstName C1
SYMATTR Value {Cval1}
SYMBOL res -208 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {Rval1}
SYMBOL res -208 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {Rval2}
SYMBOL res -720 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value {Rg1_val}
SYMBOL res -544 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {Rf2_val}
SYMBOL cap -128 176 R180
WINDOW 0 -22 54 Left 2
WINDOW 3 -59 -2 Left 2
SYMATTR InstName C2
SYMATTR Value {Cval2}
SYMBOL voltage 352 -336 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V6
SYMATTR Value {vref_val}
SYMBOL voltage -1520 576 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V9
SYMATTR Value {vdd_val}
SYMBOL Opamps\\ADA4807-2 -592 224 M180
SYMATTR InstName U2
SYMBOL voltage -976 -64 R0
WINDOW 0 -32 56 VBottom 2
WINDOW 3 -46 -162 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE({vcm} {vmag} {fin} 0 0 0)
SYMBOL res -720 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value {Rg2_val}
SYMBOL res -544 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {Rf1_val}
FLAG 624 240 0
FLAG 896 -176 VDD
FLAG 224 16 ADCINP
FLAG 224 112 ADCINN
FLAG 896 592 0
FLAG 464 -384 REF
FLAG -1792 768 0
FLAG -2048 496 VCC
FLAG -1792 496 VEE
FLAG -1520 496 VDD
FLAG -1520 768 0
FLAG -2048 768 0
FLAG 1056 64 VSAMPLED
FLAG -224 64 0
FLAG -1040 64 0
FLAG -720 -80 VINP
FLAG -720 208 VINN
FLAG -832 -256 0
FLAG -832 384 0
FLAG -608 -160 VCC
FLAG -608 -32 VEE
FLAG -576 -32 VCC
FLAG -608 288 VCC
FLAG -608 160 VEE
FLAG -576 160 VCC
FLAG 352 -176 0
TEXT -2000 416 Left 2 ;Driver Supply
TEXT -1592 416 Left 2 ;ADC Supply
TEXT -2176 -352 Left 2 !.param M=3\n.param N=4096\n.param vref_val=5\n.param vdd_val=1.8\n.param vcc_val=15\n.param vee_val=-15\n.param vcm=vref_val/{2*Gain}\n.param fs=2e6\n.param ts=1/fs\n.param fin= fs*M/N\n.param vmag=.93*vref_val/{2*Gain}\n.param tmax=1/(fs)\n.param END_SIM=M*(1/fin)
TEXT -2176 -456 Left 2 !.save v(vsampled)
TEXT -2176 -480 Left 2 !.option plotwinsize=0 numdgt=15
TEXT -2176 -504 Left 2 !.four {fin} 5 -1 v(vsampled)
TEXT -2176 72 Left 2 !.param Rval1=200\n.param Cval1=180p
TEXT -2176 128 Left 2 !.param Rval2=Rval1\n.param Cval2=Cval1
TEXT -2184 -560 Left 3 ;Simulation Setup
TEXT -2176 -528 Left 2 !.tran 0 {END_SIM+1/fin} {1/fin} {tmax}
TEXT -2176 -384 Left 3 ;Simulation Parameters
TEXT -2176 48 Left 2 ;Anti Aliasing Filter
TEXT -1704 -352 Left 2 ;Simulation cycles\nSample size\nADC reference voltage\nADC supply\nDriver VCC\nDriver VEE\nDC offset voltage\nSample frequency\nSample Period\nInput frequency\nInput amplitude\nMax time step\nSimulation end
TEXT -1704 80 Left 2 ;Rval1\nCval1\nRval2\nCval2
TEXT -2208 -840 Left 4 ;AD4001_THDD_V01
TEXT -2208 -800 Left 2 ;This circuit may be used to obtain THD results for the AD4001 series differential ADC\n using the AD4003 macro-model with an AD4807-2 driver in a non-inverting gain differential configuration.\n Additional driver models may be inserted via the component menu. Schematic redraw may\n be required. Simulation results produced by the .four SPICE command may be accessed by \nview->SPICE error log and are displayed at the end of the file. For all other performance \ncharacteristics and specifications refer to the AD4001 datasheet located at\nhttps://www.analog.com/en/products/ad4001.html#product-overview
TEXT -264 -328 Left 2 ;Anti-Aliasing Filter
TEXT -672 -328 Left 2 ;ADC Driver
TEXT -984 -328 Left 2 ;Input
TEXT -2168 184 Left 2 ;Driver Parameters
TEXT -2176 296 Left 2 !.param Rf2_val=Rf1_val\n.param Rg2_val=Rg1_val
TEXT -2176 208 Left 2 !.param Rf1_val=1K\n.param Rg1_val=1K\n.param Gain = { Rf1_val/Rg1_val + 1}
TEXT -1704 208 Left 2 ;U1 Rf\nU1 Rg\nGain\nU2 Rf\nU2 Rg