* Z:\home\khalils\Downloads\files\data\raw_asc\MAX77659A.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\n \nI2C communication, analog MUX (AMUX), Watchdog timer, die temperature\nmonitoring, factory ship mode, and top-off state are not modeled.\nFor GPIO, only the input function is modeled.\nFor the nEN pin, the model assumes push-button input. \n \nThe following parameters model the corresponding register settings.\nUse decimal numbers for the settings, e.g., use 17 for 0x11. \n \n1. TV0, TV1, TV2, TVLDO: target voltages for SBB0/1/2 and LDO.\n2. IP0, IP1, IP2, IP3: peak currents of SBB0/1/2 and charging channel. \n3. EN0, EN1, EN2, EN_LDO: chanel enable for SBB0/1/2 and LDO. \n4. MD0, MD1, MD2, MD3: operation mode of SBB0/1/2 and charging channel.\n5. ADE0, ADE1, ADE2, ADE_LDO: active discharge enable for SBB0/1/2 and LDO.\n6. CHG_EN: charger enable\n7. THM_EN: thermistor enable\n8. VCHG: fast-charge voltage\n9. VCHG_J: JEITA-modified fast-charge voltage\n10. ICHG: fast-charge current\n11. ICHG_J: JEITA-modified fast-charge current\n12. LDO_MD: LDO operation mode\n13. GPI_RF: GPI edge detection. 0, 1, 2 stand for falling, rising, and\nboth edges, respectively. A valid edge triggers a 10us active low\npulse on the nIRQ pin.\n \nThe following parameters can be customized to reduce simulation time.\nThey may not be programmable on the real part.\n \n1. tDB_i: nEN pin debounce time.\n2. tChDB_i: CHGIN pin debounce time. \n3. tGIDB_i: GPI pin debounce time.\n4. tRST_i: manual reset duration\n5. tOFF_i: WAIT time for off actions \n6. tPQ_i: pre-qualification timer
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX77659A.asy)
C6 SBB0 0 4.7 Rser=1m
Cbatt BATT 0 220 IC=3.6 Rser=10m
C8 SBB2 0 4.7 Rser=1m
R6 N007 nIRQ 100k
C4 nIRQ 0 25p
C9 SYS 0 4.7 Rser=1m
C7 SBB1 0 4.7 Rser=1m
R5 N007 nRST 100k
R4 SBB2 0 18k
V3 GPIO1 0 PULSE(0 3.3 1.2m 1u 1u 1.5m 3m)
L1 N004 N005 1.5 Rser=90m
V2 GPIO0 0 PULSE(0 3.3 1m 1u 1u 1m 3m)
C10 N005 N006 10n
V4 N007 0 3.3
R3 SBB0 0 600
C3 nRST 0 25p
C2 SYS 0 4.7 Rser=1m
R2 N003 0 10k
C5 SYS 0 4.7 Rser=1m
R1 N001 N003 10k
I1 SBB1 0 PULSE(0 25m 5.4m 0.1u 0.1u 1u 0.5m) load
XU1 0 CHGIN N002 N002 SYS N004 N005 N006 GPIO0 GPIO1 nIRQ NC_01 BATT N001 N003 SYS SBB0 SBB1 SBB2 SYS NC_02 NC_03 N007 nRST MAX77659A TV0=28 TV1=80 TV2=50 IP0=3 IP1=3 IP2=3 IP3=3 EN0=0 EN1=2 EN2=1 MD0=1 MD1=0 MD2=1 MD3=0 ADE0=1 ADE1=0 ADE2=0 CHG_EN=1 THM_EN=1 VCHG=0 VCHG_J=0 ICHG=1 ICHG_J=0 EN_LDO=4 TVLDO=0 ADE_LDO=0 LDO_MD=1 GPI_RF=1 tDB_i=500u tChDB_i=0.12m tGIDB_i=30u tRST_i=1m tOFF_i=60u tPQ_i=1.8 ;pnba GND)CHGIN)PVL)AVL)IN_SBB)LXA)LXB)BST)GPIO0)GPIO1)nIRQ)nEN)BATT)TBIAS)THM)SYS)SBB0)SBB1)SBB2)SBB3)IN_LDO)LDO)VIO)nRST
C1 N002 0 1
V1 CHGIN 0 5
.tran 6m startup
.lib MAX77659A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2144 1272
WIRE 160 -624 48 -624
WIRE 208 -624 160 -624
WIRE 544 -624 496 -624
WIRE 672 -624 544 -624
WIRE 48 -608 48 -624
WIRE 672 -608 672 -624
WIRE 208 -528 176 -528
WIRE 576 -528 496 -528
WIRE 576 -512 576 -528
WIRE 672 -512 672 -544
WIRE 176 -432 96 -432
WIRE 208 -432 176 -432
WIRE 96 -416 96 -432
WIRE 576 -416 576 -432
WIRE 576 -416 496 -416
WIRE 656 -416 576 -416
WIRE 768 -416 736 -416
WIRE 96 -336 96 -352
WIRE 176 -336 176 -432
WIRE 208 -336 176 -336
WIRE 544 -320 496 -320
WIRE 592 -320 544 -320
WIRE 672 -320 656 -320
WIRE 64 -240 48 -240
WIRE 160 -240 128 -240
WIRE 208 -240 160 -240
WIRE 544 -224 496 -224
WIRE 592 -224 544 -224
WIRE 896 -224 592 -224
WIRE 992 -224 960 -224
WIRE 208 -144 96 -144
WIRE 544 -128 496 -128
WIRE 832 -128 544 -128
WIRE 896 -128 832 -128
WIRE 992 -128 960 -128
WIRE 96 -112 96 -144
WIRE 544 -32 496 -32
WIRE 704 -32 544 -32
WIRE 896 -32 704 -32
WIRE 992 -32 960 -32
WIRE 96 0 96 -32
WIRE 208 0 96 0
WIRE 96 16 96 0
WIRE 544 80 496 80
WIRE 896 80 544 80
WIRE 992 80 960 80
WIRE 96 112 96 80
WIRE 208 112 96 112
WIRE 592 112 592 -224
WIRE 704 112 704 -32
WIRE 832 112 832 -128
WIRE 160 208 32 208
WIRE 208 208 160 208
WIRE 592 208 592 192
WIRE 704 208 704 192
WIRE 832 208 832 192
WIRE 32 224 32 208
WIRE 160 448 32 448
WIRE 208 448 160 448
WIRE 32 464 32 448
WIRE 816 464 496 464
WIRE 544 560 496 560
WIRE 592 560 544 560
WIRE 672 560 592 560
WIRE 816 560 816 464
WIRE 816 560 752 560
WIRE 592 576 592 560
WIRE 592 656 592 640
WIRE 544 704 496 704
WIRE 672 704 544 704
WIRE 816 704 816 560
WIRE 816 704 752 704
WIRE 544 720 544 704
WIRE 816 720 816 704
WIRE 544 800 544 784
WIRE 816 816 816 800
SYMBOL cap 896 64 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C9
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1m
SYMBOL cap 576 576 R0
SYMATTR InstName C3
SYMATTR Value 25p
SYMBOL cap 896 -48 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C8
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1m
SYMBOL cap 896 -144 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1m
SYMBOL voltage 32 208 R0
WINDOW 3 -157 136 Left 2
SYMATTR Value PULSE(0 3.3 1m 1u 1u 1m 3m)
SYMATTR InstName V2
SYMBOL res 688 96 R0
SYMATTR InstName R4
SYMATTR Value 18k
SYMBOL res 768 688 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 100k
SYMBOL ind 80 -128 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=90m
SYMBOL current 832 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 108 Left 2
SYMATTR SpiceLine load
SYMATTR InstName I1
SYMATTR Value PULSE(0 25m 5.4m 0.1u 0.1u 1u 0.5m)
SYMBOL voltage 816 704 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 3.3
SYMBOL res 640 -432 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 560 -528 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage 32 448 R0
WINDOW 3 -196 138 Left 2
SYMATTR Value PULSE(0 3.3 1.2m 1u 1u 1.5m 3m)
SYMATTR InstName V3
SYMBOL cap 656 -608 R0
WINDOW 123 25 80 Left 2
SYMATTR Value2 IC=3.6
SYMATTR InstName Cbatt
SYMATTR Value 220
SYMATTR SpiceLine Rser=10m
SYMBOL cap 80 -416 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 128 -256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1m
SYMBOL res 768 544 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100k
SYMBOL res 576 96 R0
SYMATTR InstName R3
SYMATTR Value 600
SYMBOL voltage 48 -624 R0
WINDOW 3 34 89 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL cap 80 16 R0
SYMATTR InstName C10
SYMATTR Value 10n
SYMBOL cap 528 720 R0
SYMATTR InstName C4
SYMATTR Value 25p
SYMBOL cap 592 -336 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1m
SYMBOL cap 896 -240 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1m
SYMBOL MAX77659A 352 208 R0
SYMATTR InstName U1
FLAG 48 -528 0
FLAG 176 -528 0
FLAG 96 -336 0
FLAG 32 304 0
FLAG 592 656 0
FLAG 816 816 0
FLAG 544 800 0
FLAG 672 -512 0
FLAG 544 560 nRST
FLAG 160 -624 CHGIN
FLAG 544 -624 BATT
FLAG 768 -416 0
FLAG 544 -320 SYS
FLAG 992 -224 0
FLAG 992 -128 0
FLAG 992 -32 0
FLAG 992 80 0
FLAG 160 -240 SYS
FLAG 544 80 SYS
FLAG 32 544 0
FLAG 592 208 0
FLAG 704 208 0
FLAG 832 208 0
FLAG 544 -224 SBB0
FLAG 544 -128 SBB1
FLAG 544 -32 SBB2
FLAG 48 -240 0
FLAG 672 -320 0
FLAG 160 208 GPIO0
FLAG 160 448 GPIO1
FLAG 544 704 nIRQ
TEXT 944 792 Left 2 !.tran 6m startup
TEXT 1312 -584 Left 2 ;Notes:\n \nI2C communication, analog MUX (AMUX), Watchdog timer, die temperature\nmonitoring, factory ship mode, and top-off state are not modeled.\nFor GPIO, only the input function is modeled.\nFor the nEN pin, the model assumes push-button input. \n \nThe following parameters model the corresponding register settings.\nUse decimal numbers for the settings, e.g., use 17 for 0x11. \n \n1. TV0, TV1, TV2, TVLDO: target voltages for SBB0/1/2 and LDO.\n2. IP0, IP1, IP2, IP3: peak currents of SBB0/1/2 and charging channel. \n3. EN0, EN1, EN2, EN_LDO: chanel enable for SBB0/1/2 and LDO. \n4. MD0, MD1, MD2, MD3: operation mode of SBB0/1/2 and charging channel.\n5. ADE0,  ADE1, ADE2, ADE_LDO: active discharge enable for SBB0/1/2 and LDO.\n6. CHG_EN: charger enable\n7. THM_EN: thermistor enable\n8. VCHG: fast-charge voltage\n9. VCHG_J: JEITA-modified fast-charge voltage\n10. ICHG: fast-charge current\n11. ICHG_J: JEITA-modified fast-charge current\n12. LDO_MD: LDO operation mode\n13. GPI_RF: GPI edge detection. 0, 1, 2 stand for falling, rising, and\nboth edges, respectively. A valid edge triggers a 10us active low\npulse on the nIRQ pin.\n \nThe following parameters can be customized to reduce simulation time.\nThey may not be programmable on the real part.\n \n1. tDB_i: nEN pin debounce time.\n2. tChDB_i: CHGIN pin debounce time. \n3. tGIDB_i: GPI pin debounce time.\n4. tRST_i: manual reset duration\n5. tOFF_i: WAIT time for off actions \n6. tPQ_i: pre-qualification timer