* Z:\home\khalils\Downloads\files\data\raw_asc\AD4130-8.asc
* Generated by LTspice 26.0.1 for Windows.
V4 VDD 0 2.5
V2 N001 0 0
V3 input+ N001 SINE(0 {Amplitude} 10)
V1 N001 input- SINE(0 {Amplitude} 10)
XU1 input+ input- 0 0 0 0 0 VDD Vout CLK AD4130-8 GAIN=1 PGA_BYP=0 I1=0 I2=0 REF_SELECT=2.5 CLK_SEL=0 FS_WORD=2 ;pnba AIN0)AIN1)REFM)REFP)GND)IOUT1)IOUT2)VDD)Vout)CLK
.param Amplitude = 2.7
* Only one channel of the AD4130-8 is modelled and other channels and related functions and pins are not modeled.The following parameters can be \ndefined by right-clicking on the AD4130-8 symbol. \n \nGAIN= 1, 2, 4, 8, 16, 32, 64, 128; sets the gain of PGA.\nPGA_BYP=0,1; 0 for disable PGA bypass, 1 for enable PGA bypass\nI1/2 = 0.1u, 10u, 20u, 50u, 100u, 150u, 200u; control the two excitation sources IOUT1 and IOUT2 respectively with values specified in the Datasheet.\nREF_SELECT=0, 1.25, 2.5; set which reference voltage to use, set 0 to use external voltage set through REF_P and REF_M pins.\nCLK_SEL=0, 1; set to 0 to observe the internal clock at the CLK pin, set to 1 to use an external clock\nFS_WORD=1 to 2047; set to any integer value from 1 to 2047 to change Output Data Rate(ODR) of the ADC between 1.17SPS to 2.4kSPS
.tran 100m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4130-8.asy)
.lib AD4130-8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1752 772
WIRE 288 80 272 80
WIRE 416 80 288 80
WIRE 528 80 496 80
WIRE 112 96 112 80
WIRE 192 96 192 80
WIRE 272 96 272 80
WIRE -112 160 -240 160
WIRE -32 160 -112 160
WIRE 0 176 0 144
WIRE -32 208 -32 160
WIRE -416 240 -464 240
WIRE -240 240 -336 240
WIRE 352 240 304 240
WIRE -240 336 -240 320
WIRE -112 336 -240 336
WIRE -32 336 -32 272
WIRE -32 336 -112 336
WIRE 0 336 0 304
WIRE 144 400 144 384
WIRE 272 400 272 384
FLAG 528 80 0
FLAG 288 80 VDD
FLAG 352 240 Vout
IOPIN 352 240 Out
FLAG -112 160 input-
FLAG -112 336 input+
FLAG -464 240 0
FLAG 272 400 0
FLAG 0 336 0
FLAG 0 144 0
FLAG 112 80 0
FLAG 192 80 0
FLAG 144 400 CLK
SYMBOL voltage 400 80 R270
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V4
SYMATTR Value 2.5
SYMBOL voltage -320 240 R90
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
SYMATTR Value 0
SYMATTR InstName V2
SYMBOL voltage -240 336 R180
WINDOW 3 265 -25 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 31 30 Left 2
SYMATTR Value SINE(0 {Amplitude} 10)
SYMATTR InstName V3
SYMBOL voltage -240 256 R180
WINDOW 3 269 105 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 31 30 Left 2
SYMATTR Value SINE(0 {Amplitude} 10)
SYMATTR InstName V1
SYMBOL AD4130-8 144 240 R0
SYMATTR InstName U1
TEXT -496 96 Left 2 !.param Amplitude = 2.7
TEXT -528 -216 Left 2 ;Only one channel of the AD4130-8 is modelled and other channels and related functions and pins are not modeled.The following parameters can be \ndefined by right-clicking on the AD4130-8 symbol. \n \nGAIN= 1,  2, 4, 8, 16, 32, 64, 128; sets the gain of PGA.\nPGA_BYP=0,1; 0 for disable PGA bypass, 1 for enable PGA bypass\nI1/2 = 0.1u, 10u, 20u, 50u, 100u, 150u, 200u; control the two excitation sources IOUT1 and IOUT2 respectively with values specified in the Datasheet.\nREF_SELECT=0, 1.25, 2.5; set which reference voltage to use, set 0 to use external voltage set through REF_P and REF_M pins.\nCLK_SEL=0, 1;  set to 0 to observe the internal clock at the CLK pin,  set to 1 to use an external clock\nFS_WORD=1 to 2047;  set to any integer value from 1 to 2047 to change Output Data Rate(ODR) of the ADC between 1.17SPS to 2.4kSPS
TEXT 376 376 Left 2 !.tran 100m