* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5054_chan1_2.asc
* Generated by LTspice 26.0.1 for Windows.
* The schematic simulates channels 1 and 2 in parallel.\nNotice how the CFG, COMP, and FB pins are configured\nThis is different then the real world. Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
* Rlim is the resistor generally placed on DL pin to set current limit
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5054_chan1_2.asy)
A1 N013 0 0 0 0 N014 N010 0 SCHMITT Vt=0.5 vh=8m Vhigh=5 Vlow=0
C4 N005 N004 2.2n
V2 N013 0 PULSE(0 5 0 10n 10n 833n 1.666u)
L2 N016 OUT 2.2
R2 N002 0 10K
R1 IN N002 10K
C7 OUT 0 16
Rload OUT 0 2
C2 OUT 0 16
XU2 N022 N014 N018 N002 IN N015 N016 N017 N009 N005 N019 0 N020 N021 ADP5054_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)Rlim)CFG12
R9 N018 N021 600k
C1 N001 N003 0.1
R6 N011 0 22K
C3 N007 0 1
C5 OUT N009 47p
M2 N016 N017 0 0 BSC080N03MS
R4 OUT N009 34.8K
R5 N009 0 23.2K
L1 N003 OUT 2.2
C6 N015 N016 0.1
C8 N018 0 1
R13 N020 0 22K
M1 N003 N006 0 0 BSC080N03MS
XU1 N012 N010 N007 N002 IN N001 N003 N006 N009 N005 N008 0 N011 0 ADP5054_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)Rlim)CFG12
R16 N018 N019 10K
R14 N022 0 31.6K
R10 N021 0 100K
V1 IN 0 12
R7 N012 0 31.6K
R3 N004 0 1.82K
R8 N007 N008 10K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m startup
.lib ADP5054_chan1_2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 1444
WIRE -304 -96 -400 -96
WIRE -160 -96 -304 -96
WIRE 80 -96 -160 -96
WIRE 448 -96 368 -96
WIRE -400 -80 -400 -96
WIRE -304 -80 -304 -96
WIRE 448 -80 448 -96
WIRE -304 16 -304 0
WIRE -192 16 -304 16
WIRE 80 16 -192 16
WIRE 448 16 448 -16
WIRE 448 16 368 16
WIRE 512 16 448 16
WIRE 640 16 592 16
WIRE 720 16 640 16
WIRE 848 16 720 16
WIRE 912 16 848 16
WIRE 976 16 912 16
WIRE -400 32 -400 0
WIRE -304 32 -304 16
WIRE 848 32 848 16
WIRE 976 32 976 16
WIRE 448 48 448 16
WIRE 720 48 720 16
WIRE 640 112 640 16
WIRE 848 112 848 96
WIRE -304 128 -304 112
WIRE -96 128 -112 128
WIRE 0 128 -16 128
WIRE 80 128 64 128
WIRE 400 128 368 128
WIRE 976 128 976 112
WIRE 448 160 448 144
WIRE 64 192 64 128
WIRE 64 192 -128 192
WIRE -32 240 -80 240
WIRE 80 240 48 240
WIRE 640 240 640 176
WIRE 640 240 368 240
WIRE 720 240 720 128
WIRE 720 240 640 240
WIRE 720 256 720 240
WIRE 80 352 -560 352
WIRE 384 352 368 352
WIRE 480 352 464 352
WIRE 720 352 720 336
WIRE 480 416 368 416
WIRE -16 464 -32 464
WIRE 80 464 64 464
WIRE 400 464 368 464
WIRE 448 464 400 464
WIRE 448 480 448 464
WIRE 224 512 224 496
WIRE -80 544 -80 240
WIRE 400 544 400 464
WIRE 400 544 -80 544
WIRE -560 560 -560 352
WIRE -560 560 -720 560
WIRE 448 560 448 544
WIRE -960 576 -1104 576
WIRE -784 576 -880 576
WIRE -560 592 -720 592
WIRE -784 640 -784 608
WIRE -160 688 -160 -96
WIRE 96 688 -160 688
WIRE 464 688 384 688
WIRE 464 704 464 688
WIRE -192 800 -192 16
WIRE 96 800 -192 800
WIRE 464 800 464 768
WIRE 464 800 384 800
WIRE 528 800 464 800
WIRE 864 800 608 800
WIRE 912 800 912 16
WIRE 912 800 864 800
WIRE 864 816 864 800
WIRE 464 832 464 800
WIRE 864 896 864 880
WIRE -128 912 -128 192
WIRE 96 912 -128 912
WIRE 416 912 384 912
WIRE 464 944 464 928
WIRE -16 1024 -48 1024
WIRE 96 1024 64 1024
WIRE 640 1024 640 240
WIRE 640 1024 384 1024
WIRE -560 1136 -560 592
WIRE 96 1136 -560 1136
WIRE 400 1136 384 1136
WIRE 496 1136 480 1136
WIRE 752 1168 624 1168
WIRE 624 1184 624 1168
WIRE 560 1200 384 1200
WIRE 0 1248 -16 1248
WIRE 96 1248 80 1248
WIRE 416 1248 384 1248
WIRE 464 1248 416 1248
WIRE 464 1264 464 1248
WIRE 560 1280 560 1200
WIRE 624 1280 624 1264
WIRE 624 1280 560 1280
WIRE 240 1296 240 1280
WIRE 624 1296 624 1280
WIRE -48 1328 -48 1024
WIRE 416 1328 416 1248
WIRE 416 1328 -48 1328
WIRE 464 1344 464 1328
WIRE 624 1392 624 1376
WIRE 416 1440 416 1328
WIRE 752 1440 752 1168
WIRE 752 1440 416 1440
SYMBOL ind 496 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL ind 512 816 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 2.2
SYMBOL res 608 1280 R0
SYMATTR InstName R10
SYMATTR Value 100K
SYMBOL res 96 1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 31.6K
SYMBOL res 368 368 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 22K
SYMBOL cap 432 480 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 80 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL nmos 416 832 R0
SYMATTR InstName M2
SYMATTR Value BSC080N03MS
SYMBOL ADP5054_chan1_2 224 192 R0
SYMATTR InstName U1
SYMBOL cap 448 704 R0
SYMATTR InstName C6
SYMATTR Value 0.1
SYMBOL cap 848 816 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C7
SYMATTR Value 16
SYMBOL cap 624 112 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL cap 448 1264 R0
SYMATTR InstName C8
SYMATTR Value 1
SYMBOL nmos 400 48 R0
SYMATTR InstName M1
SYMATTR Value BSC080N03MS
SYMBOL res 384 1152 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R13
SYMATTR Value 22K
SYMBOL res 704 32 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL res 960 16 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL voltage -864 576 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 37 140 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10n 10n 833n 1.666u)
SYMBOL res -48 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL Digital\\schmitt -784 512 R0
WINDOW 0 22 24 Left 2
WINDOW 123 26 118 Left 2
WINDOW 39 26 146 Left 2
SYMATTR InstName A1
SYMATTR Value2 Vt=0.5 vh=8m
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR Description Behavioral Schmitt-Triggered inverter
SYMATTR Type schmtinv
SYMBOL VOLTAGE -400 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res -320 16 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res -32 1040 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R16
SYMATTR Value 10K
SYMBOL cap 832 32 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C2
SYMATTR Value 16
SYMBOL cap 64 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL res 704 240 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL cap 432 -80 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL res 608 1168 R0
SYMATTR InstName R9
SYMATTR Value 600k
SYMBOL res 0 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL ADP5054_chan1_2 240 976 R0
SYMATTR InstName U2
SYMBOL res -320 -96 R0
SYMATTR InstName R1
SYMATTR Value 10K
FLAG 224 512 0
FLAG -400 32 0
FLAG -304 128 0
FLAG 448 160 0
FLAG 848 112 0
FLAG 720 352 0
FLAG 480 352 0
FLAG 448 560 0
FLAG -32 464 0
FLAG -112 128 0
FLAG 976 16 OUT
FLAG -400 -96 IN
FLAG 976 128 0
FLAG 480 416 0
FLAG 240 1296 0
FLAG 464 944 0
FLAG 864 896 0
FLAG 496 1136 0
FLAG 464 1344 0
FLAG -16 1248 0
FLAG -784 640 0
FLAG -1104 576 0
FLAG 624 1392 0
TEXT 864 1320 Left 2 !.tran 3m startup
TEXT -1400 280 Left 2 ;The schematic simulates channels 1 and 2 in parallel.\nNotice how the CFG, COMP, and FB pins are configured\nThis is different then the real world.  Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
TEXT 504 392 Left 2 ;Rlim is the resistor generally placed on DL pin to set current limit