Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\086e7208ca70_2909-25_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
C2 0 N001 1000p
V3 N006 0 PWL(0 0 5010m 0 5011m 0.9 10010m 0.9 10011m 5)
V2 N007 0 PULSE(2.5 5 0 1000m 1000m 3000m 5000m)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1152 788
WIRE 304 80 -96 80
WIRE 304 160 304 80
WIRE 304 160 272 160
WIRE 320 160 304 160
WIRE 432 160 384 160
WIRE 496 224 272 224
WIRE 592 224 576 224
WIRE -192 288 -208 288
WIRE -96 288 -112 288
WIRE 16 288 -96 288
WIRE 304 288 272 288
WIRE 400 288 368 288
WIRE -96 304 -96 288
WIRE 352 352 272 352
WIRE 352 368 352 352
WIRE -256 400 -256 80
WIRE -224 400 -256 400
WIRE -96 400 -96 384
WIRE -96 400 -144 400
WIRE 0 400 -96 400
WIRE -256 464 -256 400
WIRE 352 464 352 448
WIRE -256 576 -256 544
SYMBOL cap 384 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1000p
SYMBOL voltage 352 352 R0
WINDOW 3 30 89 Left 2
SYMATTR Value PWL(0 0 5010m 0 5011m 0.9 10010m 0.9 10011m 5)
SYMATTR InstName V3
SYMBOL voltage -256 448 R0
SYMATTR InstName V2
SYMATTR Value PULSE(2.5 5 0 1000m 1000m 3000m 5000m)
FLAG -256 576 0
FLAG -208 288 0
FLAG 400 288 0
FLAG 432 160 0
FLAG 352 464 0
* Z:\home\khalils\Downloads\files\data\raw_asc\2d604922a429_Fig_2-139_CSW.asc
* Generated by LTspice 26.0.1 for Windows.
V1 CONT 0 PULSE(-1 1 1m 4m 2m 1m 10m)
W1 N001 OUT V1 MyCSW
R1 CONT 0 1
V2 N001 0 5
R2 OUT 0 100
.model MyCSW CSW(Ron=1 Roff=1T It=0 Ih={TH})
.step param TH list 0.5 -1
.tran 20m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1024 680
WIRE 112 128 -48 128
WIRE 384 128 352 128
WIRE 480 128 384 128
WIRE -48 160 -48 128
WIRE 112 160 112 128
WIRE 352 160 352 128
WIRE 480 160 480 128
WIRE 112 256 112 240
WIRE 112 256 80 256
WIRE -48 272 -48 240
WIRE 352 272 352 240
WIRE 480 272 480 240
WIRE 112 288 112 256
WIRE 112 400 112 368
SYMBOL res 96 272 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL csw 112 160 R0
SYMATTR InstName W1
SYMATTR Value V1 MyCSW
SYMBOL res 464 144 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage 352 144 R0
WINDOW 0 -21 17 Bottom 2
WINDOW 3 101 163 Top 2
WINDOW 123 0 0 Left 0
WINDOW 39 60 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PULSE(-1 1 1m 4m 2m 1m 10m)
SYMBOL voltage -48 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
FLAG 352 272 0
FLAG 480 272 0
FLAG 384 128 CONT
FLAG 112 400 0
FLAG 80 256 OUT
FLAG -48 272 0
TEXT -48 56 Left 2 !.model MyCSW CSW(Ron=1 Roff=1T It=0 Ih={TH})
TEXT 320 80 Left 2 !.step param TH list 0.5 -1
TEXT -48 16 Left 2 !.tran 20m
* Z:\home\khalils\Downloads\files\data\raw_asc\09d9c2689d19_FWrecFiltt.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N002 0 2m
D1 N001 N002 MUR460
D2 N004 N002 MUR460
L1 N003 0 1
R1 N002 0 100
L3 N001 0 .01
V1 N003 0 SINE(0 170 60) Rser=.01
L2 0 N004 .01
K1 L1 L2 L3 1.
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 33.33e-3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 64 176 64
WIRE 320 64 272 64
WIRE 384 64 320 64
WIRE 320 144 320 64
WIRE 384 144 384 64
WIRE 80 160 -16 160
WIRE 176 160 176 144
WIRE 224 160 176 160
WIRE -16 176 -16 160
WIRE 80 176 80 160
WIRE 176 176 176 160
WIRE 224 192 224 160
WIRE 320 256 320 208
WIRE 384 256 384 224
WIRE 384 256 320 256
WIRE -16 288 -16 256
WIRE 80 288 80 256
WIRE 176 288 176 256
WIRE 208 288 176 288
WIRE 272 288 272 64
WIRE 320 288 320 256
SYMBOL ind2 192 48 M0
SYMATTR InstName L3
SYMATTR Value .01
SYMATTR Type ind
SYMBOL res 368 128 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL ind2 64 160 R0
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR Type ind
SYMBOL voltage -16 160 R0
WINDOW 3 -204 56 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 -204 84 Left 0
SYMATTR Value SINE(0 170 60)
SYMATTR SpiceLine Rser=.01
SYMATTR InstName V1
SYMBOL cap 304 144 R0
SYMATTR InstName C1
SYMATTR Value 2m
SYMBOL diode 208 48 M90
WINDOW 0 68 33 VBottom 0
WINDOW 3 -30 29 VTop 0
SYMATTR InstName D1
SYMATTR Value MUR460
SYMBOL diode 208 304 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D2
SYMATTR Value MUR460
SYMBOL ind2 192 160 M0
SYMATTR InstName L2
SYMATTR Value .01
SYMATTR Type ind
FLAG -16 288 0
FLAG 80 288 0
FLAG 320 288 0
FLAG 224 192 0
TEXT 56 352 Left 0 !.tran 33.33e-3
TEXT -48 112 Left 0 !K1 L1 L2 L3 1.
* Z:\tmp\asc_dec_bjh7r6w2\07132c728f03_MV_DAC_Filter_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N004 N003 6.8k
C3 N003 0 1500pf
XU2 N005 N001 N002 N006 N001 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 400 64 400 -48
WIRE 400 64 192 64
WIRE 272 160 272 -368
WIRE 192 176 192 64
WIRE 240 176 192 176
WIRE 400 192 400 64
WIRE 400 192 304 192
WIRE 656 192 400 192
WIRE -352 208 -512 208
WIRE -256 208 -352 208
WIRE -128 208 -128 -48
WIRE -128 208 -176 208
WIRE -48 208 -128 208
WIRE 96 208 32 208
WIRE 240 208 96 208
WIRE -352 256 -352 208
WIRE 96 288 96 208
WIRE -352 352 -352 320
WIRE 96 384 96 352
WIRE 272 448 272 224
SYMBOL res -160 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 6.8k
SYMBOL cap -368 256 R0
SYMATTR InstName C3
SYMATTR Value 1500pf
SYMBOL Opamps\\UniversalOpamp2 272 192 R0
SYMATTR InstName U2
FLAG 96 384 0
FLAG -352 352 0
* Z:\home\khalils\Downloads\files\data\raw_asc\4f7f7a4bc83a_part3_a_vgs_sweep.asc
* Generated by LTspice 26.0.1 for Windows.
M1 drain gate 0 0 NMOS
VDS drain 0 8
VGS gate 0 7
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model nmos NMOS (kp=100u, vt0=0.5, l={x}, w=.36u)
.dc VGS 0 10 0.01
.step param X list .09u .13u .2u .3u .6u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 48 96 48
WIRE 240 48 160 48
WIRE 96 112 96 48
WIRE 240 144 240 48
WIRE -64 192 -96 192
WIRE 48 192 -64 192
WIRE -96 208 -96 192
WIRE -96 336 -96 288
WIRE 96 336 96 208
WIRE 96 336 -96 336
WIRE 176 336 96 336
WIRE 240 336 240 224
WIRE 240 336 176 336
SYMBOL voltage 240 128 R0
SYMATTR InstName VDS
SYMATTR Value 8
SYMBOL voltage -96 192 R0
SYMATTR InstName VGS
SYMATTR Value 7
SYMBOL nmos 48 112 R0
SYMATTR InstName M1
FLAG 96 336 0
FLAG -64 192 gate
FLAG 160 48 drain
FLAG 176 336 source
TEXT -104 376 Left 2 !.model nmos NMOS (kp=100u, vt0=0.5, l={x}, w=.36u)
TEXT -104 408 Left 2 !.dc VGS 0 10 0.01
TEXT -104 440 Left 2 !.step param X list .09u .13u .2u .3u .6u
* Z:\tmp\asc_dec_bjh7r6w2\19fac28300e4_Fig_26_50_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
M11 N004 phi2 N003 0 N_50n l=50n w=500n
M9 ideal_vcma phi1 N004 0 N_50n l=50n w=500n
M16 N009 phi2b N010 VDD P_50n l=50n w=500n
M10 N004 phi1b ideal_vcma VDD P_50n l=50n w=500n
M1 ideal_vcma phi1 N001 0 N_50n l=50n w=500n
M2 N001 phi1b ideal_vcma VDD P_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1620 680
WIRE 432 -304 432 -368
WIRE 624 -304 624 -368
WIRE 384 -240 384 -384
WIRE 464 -240 464 -256
WIRE 464 -240 384 -240
WIRE 416 -224 416 -256
WIRE 416 -224 352 -224
WIRE 512 -224 512 -256
WIRE 560 -224 512 -224
WIRE 608 -224 608 -256
WIRE 608 -224 560 -224
WIRE 704 -224 704 -256
WIRE 816 -224 704 -224
WIRE 1136 -224 1136 -256
WIRE 1136 -224 1024 -224
WIRE 1232 -224 1232 -256
WIRE 1280 -224 1232 -224
WIRE 1328 -224 1328 -256
WIRE 1328 -224 1280 -224
WIRE 1424 -224 1424 -256
WIRE 1520 -224 1424 -224
WIRE 1616 -224 1520 -224
WIRE 464 -192 384 -192
WIRE 416 -176 416 -224
WIRE 464 -176 464 -192
WIRE 512 -176 512 -224
WIRE 608 -176 608 -224
WIRE 704 -176 704 -224
WIRE 1136 -176 1136 -224
WIRE 1232 -176 1232 -224
WIRE 1328 -176 1328 -224
WIRE 1424 -176 1424 -224
WIRE 560 -96 560 -224
WIRE 1024 -96 1024 -224
WIRE 1280 -96 1280 -224
WIRE 384 -80 384 -192
WIRE 416 112 416 64
WIRE 512 112 512 64
WIRE 560 112 560 -32
WIRE 608 112 608 64
WIRE 1024 112 1024 -32
WIRE 1024 112 928 112
WIRE 1136 112 1136 64
WIRE 1136 112 1024 112
WIRE 1232 112 1232 64
WIRE 1280 112 1280 -32
WIRE 1280 112 1232 112
WIRE 1328 112 1328 64
WIRE 1328 112 1280 112
WIRE 1424 112 1424 64
WIRE 1136 144 1136 112
WIRE 1232 144 1232 112
WIRE 1328 144 1328 112
SYMBOL nmos4 1232 -128 M270
WINDOW 0 119 20 Invisible 0
WINDOW 3 157 46 Invisible 0
SYMATTR InstName M11
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 1424 -128 M270
WINDOW 0 119 20 Invisible 0
WINDOW 3 157 46 Invisible 0
SYMATTR InstName M9
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 1136 16 M90
WINDOW 0 116 21 Invisible 0
WINDOW 3 175 48 Invisible 0
SYMATTR InstName M16
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 1328 -304 M90
WINDOW 0 116 21 Invisible 0
WINDOW 3 175 48 Invisible 0
SYMATTR InstName M10
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 416 -128 R270
WINDOW 0 119 20 Invisible 0
WINDOW 3 157 46 Invisible 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 512 -304 R90
WINDOW 0 116 21 Invisible 0
WINDOW 3 175 48 Invisible 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=500n
FLAG 496 -128 phi1
FLAG 656 -256 VDD
FLAG 656 -176 0
FLAG 688 -128 phi2
FLAG 464 64 VDD
FLAG 432 16 phi1b
FLAG 1376 -256 VDD
FLAG 1376 -176 0
FLAG 1344 -128 phi1
FLAG 1408 -304 phi1b
FLAG 1184 -256 VDD
FLAG 1184 -176 0
FLAG 1152 -128 phi2
FLAG 1216 -304 phi2b
FLAG 1376 64 VDD
FLAG 1408 16 phi1b
FLAG 1184 64 VDD
FLAG 1184 144 0
FLAG 1152 192 phi2
FLAG 1216 16 phi2b
FLAG 1520 -224 ideal_vcma
FLAG 352 -224 ideal_vcma
FLAG 384 -384 VDD
FLAG 384 -80 GND
FLAG 432 -368 phi1b
FLAG 624 -368 phi2b
* Z:\home\khalils\Downloads\files\data\raw_asc\08e96ae65e70_nor2tg.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 PULSE(0 5 0 10us 10us 2ms 4ms)
V3 N002 0 PULSE(0 5 0 10us 10us 1ms 2ms)
M8 Vdd N002 N003 Vdd PMOS
M3 Y N004 N003 0 NMOS
M2 Y N004 0 Vdd PMOS
M5 Vdd N001 N004 Vdd PMOS
M7 N003 N002 0 0 NMOS
M1 Y N001 N003 Vdd PMOS
M6 N004 N001 0 0 NMOS
M4 Y N001 0 0 NMOS
V1 Vdd 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 4ms 10us
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 -288 -224 -288
WIRE -96 -208 -176 -208
WIRE 0 -208 -96 -208
WIRE 0 -192 0 -208
WIRE 176 -192 176 -288
WIRE -48 -112 -64 -112
WIRE 256 -112 256 -144
WIRE 368 -112 256 -112
WIRE 416 -112 368 -112
WIRE -176 -96 -176 -128
WIRE 160 -96 160 -144
WIRE 160 -96 0 -96
WIRE 160 -80 160 -96
WIRE 256 -80 256 -112
WIRE -96 -64 -96 -208
WIRE -96 -64 -192 -64
WIRE -64 -32 -64 -112
WIRE -64 -32 -144 -32
WIRE -64 -16 -64 -32
WIRE -48 -16 -64 -16
WIRE 176 16 176 -32
WIRE 176 16 96 16
WIRE 16 48 -80 48
WIRE 176 64 176 16
WIRE -192 80 -192 -64
WIRE -80 80 -80 48
WIRE -80 80 -192 80
WIRE -32 128 -64 128
WIRE 160 128 160 112
WIRE 160 128 128 128
WIRE 256 128 256 112
WIRE 368 128 368 -112
WIRE 368 128 256 128
WIRE -224 144 -224 -288
WIRE -128 144 -224 144
WIRE 96 144 96 16
WIRE 96 144 16 144
WIRE 16 160 16 144
WIRE -128 176 -128 144
WIRE -64 176 -64 128
WIRE -64 176 -128 176
WIRE 160 176 160 128
WIRE 256 176 256 128
WIRE -64 240 -64 176
WIRE -32 240 -64 240
WIRE -224 288 -224 144
WIRE 176 288 176 224
WIRE 176 288 -224 288
SYMBOL pmos4 256 64 R90
WINDOW 0 131 -48 Left 2
WINDOW 3 -27 -14 Left 2
SYMATTR InstName M2
SYMBOL voltage -176 -224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 28 -1 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL nmos4 -48 -96 R0
SYMATTR InstName M7
SYMBOL voltage -144 -48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 39 1 Left 2
WINDOW 3 -46 -269 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 10us 10us 1ms 2ms)
SYMBOL nmos4 256 -32 M270
WINDOW 0 1 -37 Left 2
WINDOW 3 -25 -14 Left 2
SYMATTR InstName M3
SYMBOL pmos4 256 -192 R90
WINDOW 0 -9 -36 Left 2
WINDOW 3 -28 -13 Left 2
SYMATTR InstName M1
SYMBOL nmos4 -32 160 R0
SYMATTR InstName M6
SYMBOL pmos4 -48 -192 R0
SYMATTR InstName M8
SYMBOL nmos4 256 224 M270
WINDOW 0 134 -43 Left 2
WINDOW 3 -24 -20 Left 2
SYMATTR InstName M4
SYMBOL pmos4 -32 48 R0
SYMATTR InstName M5
SYMBOL voltage -128 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 0 -7 Left 2
WINDOW 3 -55 158 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10us 10us 2ms 4ms)
FLAG 16 256 0
FLAG -128 256 0
FLAG -144 48 0
FLAG 416 -112 Y
FLAG 0 0 0
FLAG 16 208 0
FLAG -176 -208 Vdd
FLAG 0 -144 Vdd
FLAG 208 -144 Vdd
FLAG 208 112 Vdd
FLAG 16 96 Vdd
FLAG 208 -80 0
FLAG 208 176 0
FLAG 0 -48 0
FLAG 128 128 0
FLAG -176 -96 0
TEXT 288 -144 Left 2 !.tran 0 4ms 10us
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3444.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3444.asy)
XU1 IN N001 0 N002 OUT IN 0 N003 LTC3444 ;pnba _SHDN)SW1)GND)SW2)Vout)Vin)Vc)FB
C1 OUT 0 4.7 Rser=10m
V1 IN 0 3.6
Iload OUT 0 100m
R3 N004 N003 205K
R2 N003 0 267K
L1 N001 N002 2.2
V2 N004 0 PULSE(.28 2.36 100u 10u 10u 140u 300u)
R1 OUT N003 340K
.tran 650u startup
.lib LTC3444.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2824 2324
WIRE 1824 1232 1664 1232
WIRE 2048 1232 1904 1232
WIRE 1664 1328 1664 1232
WIRE 1696 1328 1664 1328
WIRE 2048 1328 2048 1232
WIRE 2048 1328 2016 1328
WIRE 2096 1376 2048 1376
WIRE 2384 1376 2096 1376
WIRE 2480 1376 2384 1376
WIRE 2096 1392 2096 1376
WIRE 2480 1392 2480 1376
WIRE 1664 1408 1552 1408
WIRE 1696 1408 1664 1408
WIRE 2048 1408 2048 1376
WIRE 2048 1408 2016 1408
WIRE 2384 1408 2384 1376
WIRE 1552 1424 1552 1408
WIRE 1664 1488 1664 1408
WIRE 1696 1488 1664 1488
WIRE 2096 1488 2096 1472
WIRE 2096 1488 2016 1488
WIRE 2176 1488 2096 1488
WIRE 2288 1488 2256 1488
WIRE 2096 1504 2096 1488
WIRE 2288 1504 2288 1488
WIRE 2384 1504 2384 1472
WIRE 2480 1504 2480 1472
WIRE 1552 1520 1552 1504
WIRE 1696 1568 1664 1568
WIRE 2048 1568 2016 1568
WIRE 2096 1600 2096 1584
WIRE 2288 1600 2288 1584
SYMBOL ind 1808 1248 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL voltage 2288 1488 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(.28 2.36 100u 10u 10u 140u 300u)
SYMBOL cap 2368 1408 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=10m
SYMBOL res 2080 1488 R0
SYMATTR InstName R2
SYMATTR Value 267K
SYMBOL res 2080 1376 R0
SYMATTR InstName R1
SYMATTR Value 340K
SYMBOL PowerProducts\\LTC3444 1856 1456 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1552 1408 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL res 2272 1472 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 205K
SYMBOL current 2480 1392 R0
SYMATTR Value 100m
SYMATTR InstName Iload
FLAG 1552 1520 0
FLAG 2096 1600 0
FLAG 2384 1504 0
FLAG 2480 1504 0
FLAG 2480 1376 OUT
FLAG 1664 1568 0
FLAG 2048 1568 0
FLAG 2288 1600 0
FLAG 1552 1408 IN
TEXT 2072 1680 Left 2 !.tran 650u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\21dd10917d69_PentoCarG1Step.asc
* Generated by LTspice 26.0.1 for Windows.
Vg2 N002 0 360
Vp N001 0 0
Vg1 N003 0 0
XU1 0 N003 N002 0 N001 EL34Pent Pentrode ;pnba Cathode)G1)G2)G3)Anode
.dc Vp 0 2K 100 Vg1 0 -40 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 96 -144 96
WIRE 48 112 48 96
WIRE -144 128 -144 96
WIRE 0 160 -16 160
WIRE 144 176 96 176
WIRE 0 192 -64 192
WIRE 144 192 144 176
WIRE -64 208 -64 192
WIRE -16 256 -16 160
WIRE 16 256 16 240
WIRE 16 256 -16 256
WIRE -16 272 -16 256
WIRE -144 304 -144 208
WIRE -64 304 -64 288
WIRE -64 304 -144 304
WIRE 16 304 16 256
WIRE 16 304 -64 304
WIRE 144 304 144 272
WIRE 144 304 16 304
WIRE 16 320 16 304
SYMBOL voltage -64 192 R0
WINDOW 0 -18 61 Left 0
SYMATTR InstName Vg1
SYMATTR Value 0
SYMBOL voltage 144 176 R0
WINDOW 0 -47 15 Left 0
WINDOW 3 -20 61 Left 0
SYMATTR InstName Vg2
SYMATTR Value 360
SYMBOL Valve\\Pentode 48 176 R0
WINDOW 0 -77 -52 Left 0
WINDOW 38 37 111 Center 0
SYMATTR InstName U1
SYMATTR SpiceModel EL34Pent
SYMBOL voltage -144 112 R0
WINDOW 0 -16 57 Left 0
SYMATTR InstName Vp
SYMATTR Value 0
FLAG -16 272 0
TEXT -152 320 Left 0 !.dc Vp 0 2K 100 Vg1 0 -40 5
* Z:\home\khalils\Downloads\files\data\raw_asc\fa6d8caf90c3_Adder.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 input 1k
V2 N002 0 12
XU1 0 N001 N002 N003 vout LM741/NS ;pnba In+)In-)V+)V-)OUT
V3 input 0 SINE(0 2 1k) AC 1
R2 N001 input 1k
V1 N003 0 -12
R3 vout N001 1k
.include C:\Users\PRANAV ARYA\Documents\GitHub\ECN351-Lab\LM741.MOD
.tran 0 10m 0 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 -208 208 -208
WIRE -112 -128 -160 -128
WIRE 48 -128 -112 -128
WIRE 80 -128 48 -128
WIRE 272 -112 272 -272
WIRE 160 -96 160 -128
WIRE 208 -96 208 -208
WIRE 208 -96 160 -96
WIRE 240 -96 208 -96
WIRE 352 -80 304 -80
WIRE 368 -80 368 -208
WIRE 368 -80 352 -80
WIRE 48 -64 48 -128
WIRE 80 -64 48 -64
WIRE 160 -64 160 -96
WIRE 240 -64 224 -64
WIRE -160 -48 -160 -128
WIRE 272 48 272 -48
WIRE 224 176 224 -64
SYMBOL voltage -160 -64 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value SINE(0 2 1k)
SYMBOL res 176 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -26 18 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL OpAmps\\opamp2 272 -144 R0
WINDOW 3 12 6 Left 2
SYMATTR Value LM741/NS
SYMATTR InstName U1
SYMBOL res 384 -224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -26 18 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 176 -80 R90
WINDOW 0 -2 60 VBottom 2
WINDOW 3 45 55 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 272 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -12
SYMBOL voltage 272 -256 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
FLAG 272 128 0
FLAG 272 -352 0
FLAG -160 32 0
FLAG 224 176 0
FLAG 352 -80 vout
FLAG -112 -128 input
TEXT -192 360 Left 2 !.include C:\\Users\\PRANAV ARYA\\Documents\\GitHub\\ECN351-Lab\\LM741.MOD
TEXT 112 312 Left 2 !.tran 0 10m 0 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1413A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1413A.asy)
R5 N004 0 10Meg
R2 N001 0 1Meg
XU1 N004 N001 +V 0 OUT LT1413 ;pnba In+)In-)V+)V-)OUT
R1 OUT N001 10Meg
V1 +V 0 9
R4 N004 0 1Meg
R6 N004 N003 10Meg
V3 N003 0 SINE(45 40 100)
R3 N001 N002 10Meg
V2 N002 N003 SINE(-2 1 1K)
.tran 10m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE 32 176 -304 176
WIRE 128 176 128 96
WIRE 128 176 112 176
WIRE 192 208 192 192
WIRE 128 224 128 176
WIRE 160 224 128 224
WIRE -432 240 -432 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE -96 256 -304 256
WIRE 0 256 -16 256
WIRE 112 256 0 256
WIRE 160 256 112 256
WIRE 0 272 0 256
WIRE 112 272 112 256
WIRE 192 288 192 272
WIRE -304 320 -304 256
WIRE -432 336 -432 320
WIRE 0 368 0 352
WIRE 112 368 112 352
WIRE -304 416 -304 400
SYMBOL res 96 256 R0
SYMATTR InstName R5
SYMATTR Value 10Meg
SYMBOL voltage -304 304 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(45 40 100)
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10Meg
SYMBOL res 0 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10Meg
SYMBOL voltage -432 224 R0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage -304 160 R0
WINDOW 0 23 -6 Left 2
WINDOW 3 25 119 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(-2 1 1K)
SYMBOL res -16 256 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL res 128 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10Meg
SYMBOL opamps\\LT1413A 192 176 R0
SYMATTR InstName U1
FLAG -432 336 0
FLAG 192 192 +V
FLAG -432 224 +V
FLAG 16 96 0
FLAG 192 288 0
FLAG 112 368 0
FLAG 0 368 0
FLAG -304 416 0
FLAG 288 240 OUT
TEXT 224 424 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2055.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC2055.asy)
R1 N002 N001 10K
R2 N001 0 10K
XU1 N003 N001 N002 +V -V LTC2054 ;pnba IN+)IN-)OUT)VCC)VEE
V1 +V 0 2.5
V3 N003 0 SINE(0 1 1K)
V2 -V 0 -2.5
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -128 16 -144 16
WIRE -32 16 -48 16
WIRE 32 16 -32 16
WIRE 128 16 112 16
WIRE 32 96 32 80
WIRE -400 112 -400 96
WIRE -272 112 -272 96
WIRE -32 112 -32 16
WIRE 0 112 -32 112
WIRE 128 128 128 16
WIRE 128 128 64 128
WIRE 0 144 -96 144
WIRE -96 160 -96 144
WIRE 32 176 32 160
WIRE -400 208 -400 192
WIRE -272 208 -272 192
WIRE -96 256 -96 240
SYMBOL res -32 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 128 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -96 144 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL voltage -400 96 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL opamps\\LTC2055 32 128 R0
SYMATTR InstName U1
SYMBOL voltage -272 96 R0
SYMATTR InstName V1
SYMATTR Value 2.5
FLAG -272 208 0
FLAG 32 80 +V
FLAG -272 96 +V
FLAG 32 176 -V
FLAG -400 208 0
FLAG -400 96 -V
FLAG -96 256 0
FLAG -144 16 0
TEXT 88 288 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-3.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-3.5.asy)
C1 OUT 0 10
L1 N001 N002 1.5 Rser=80m
Rload OUT 0 50
V1 IN 0 3.3
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-3.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
.tran 400u startup
.lib ADP2503-3.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ADP2503-3.5 176 176 R0
SYMATTR InstName U1
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 424 376 Left 2 !.tran 400u startup
TEXT 168 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\tmp\asc_dec_bjh7r6w2\051a8011225e_EDM_Powersupply_V4c_noGD_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
V4 N001 N005 10
R3 N006 N002 10
R4 N001 N003 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1876 680
WIRE 624 -32 544 -32
WIRE 976 -32 624 -32
WIRE 544 0 544 -32
WIRE 624 16 624 -32
WIRE 1264 32 1152 32
WIRE 976 64 976 -32
WIRE 1152 112 1152 32
WIRE 1264 112 1152 112
WIRE 624 128 624 96
WIRE 544 240 544 176
WIRE 976 256 976 144
WIRE 1152 272 1152 112
WIRE 1280 272 1152 272
WIRE 1424 272 1424 112
WIRE 1424 272 1344 272
WIRE 1424 352 1424 272
WIRE 1456 352 1424 352
WIRE 1152 416 1152 272
WIRE 1168 416 1152 416
WIRE 1280 416 1248 416
WIRE 1424 416 1424 352
WIRE 1424 416 1344 416
SYMBOL voltage 976 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL res 1264 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10
SYMBOL res 608 0 R0
SYMATTR InstName R4
SYMATTR Value 10
FLAG 1456 352 0