* Z:\home\khalils\Downloads\files\data\raw_asc\12de45372383_11-15-24.asc
* Generated by LTspice 26.0.1 for Windows.
XM1 N001 VG1 VS1 IPB032N10N5_L0 ;pnba D)G)S
XM2 VS1 VG2 0 IPB032N10N5_L0 ;pnba D)G)S
L1 VS1 Vout 120
C1 Vout 0 470
V4 VG1 VS1 PULSE(0 10 0 1p 1p 22.118u 25u)
C4 N001 0 470
V2 VG2 0 PULSE(10 0 0 1p 1p 22.118u 25u)
V1 N001 0 20.04
R1 Vout 0 {R}
.meas Voavg AVG V(vout)
.meas ILavg AVG I(L1)
.step param R list 5 6 7 8
.tran 20m
.SUBCKT IPB032N10N5_L0 drain gate source
Lg gate g1 6.5n
Ld drain d1 0.1n
Ls source s1 3.6n
Rs s1 s2 411u TC=3m
Rg g1 g2 1.3
M1 d2 g2 s2 s2 DMOS L=1u W=1u
.MODEL DMOS NMOS ( KP=461.4 VTO=4.1 THETA=0 VMAX=1.5e5 ETA=0.0035 LEVEL=3)
Rd d1 d2 2.12m TC=7m
Dbd s2 d2 Dbt
.MODEL Dbt D(BV=107 M=0.75 CJO=1.5n VJ=2.5V)
Rsp s2 s3 0.44
Dbd1 s3 d2 Dbt1
.MODEL Dbt1 D(BV=1000 M=0.75 CJO=5.94n VJ=2.5V)
Dbody s2 21 DBODY
.MODEL DBODY D(IS=53.5p N=1.12 RS=0.04u EG=1.12 TT=20n)
Rdiode d1 21 0.49m TC=1m
.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1)
Maux g2 c a a sw
Maux2 b d g2 g2 sw
Eaux c a d2 g2 1
Eaux2 d g2 d2 g2 -1
Cox b d2 1.37n
.MODEL DGD D(M=0.55 CJO=1.37n VJ=0.5)
Rpar b d2 1Meg
Dgd a d2 DGD
Rpar2 d2 a 10Meg
Cgs g2 s2 5.32n
.ENDS IPB032N10N5_L0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3376 1248
WIRE -448 208 -448 192
WIRE 0 208 0 192
WIRE -448 256 -448 208
WIRE 0 256 0 208
WIRE -448 400 -448 336
WIRE -448 416 -448 400
WIRE 0 416 0 336
WIRE 32 640 -208 640
WIRE 64 640 32 640
WIRE 272 640 160 640
WIRE 304 640 272 640
WIRE 400 640 304 640
WIRE 528 640 480 640
WIRE 576 640 528 640
WIRE 752 640 576 640
WIRE -208 688 -208 640
WIRE 176 688 144 688
WIRE 576 688 576 640
WIRE 752 688 752 640
WIRE 32 720 32 640
WIRE 304 720 304 640
WIRE 240 800 240 768
WIRE 256 800 240 800
WIRE -208 848 -208 768
WIRE 32 848 32 784
WIRE 32 848 -208 848
WIRE 304 848 304 816
WIRE 304 848 32 848
WIRE 576 848 576 752
WIRE 576 848 304 848
WIRE 752 848 752 768
WIRE 752 848 576 848
WIRE 304 896 304 848
FLAG 304 896 0
FLAG 176 688 VG1
FLAG 240 768 VG2
FLAG 528 640 Vout
FLAG 272 640 VS1
FLAG -448 208 VG1
FLAG -448 400 VS1
FLAG 0 208 VG2
FLAG 0 416 0
SYMBOL nmos 64 688 R270
SYMATTR InstName M1
SYMATTR Value IPB032N10N5_L0
SYMATTR Prefix X
SYMBOL nmos 256 720 R0
SYMATTR InstName M2
SYMATTR Value IPB032N10N5_L0
SYMATTR Prefix X
SYMBOL ind 384 656 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 120µ
SYMBOL cap 560 688 R0
SYMATTR InstName C1
SYMATTR Value 470µ
SYMBOL voltage -448 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 10 0 1p 1p 22.118u 25u)
SYMBOL cap 16 720 R0
SYMATTR InstName C4
SYMATTR Value 470µ
SYMBOL voltage 0 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(10 0 0 1p 1p 22.118u 25u)
SYMBOL Voltage -208 672 R0
SYMATTR InstName V1
SYMATTR Value 20.04
SYMBOL Res 736 672 R0
SYMATTR InstName R1
SYMATTR Value {R}
TEXT -448 496 Left 2 !.meas Voavg AVG V(vout)\n.meas ILavg AVG I(L1)\n.step param R list 5 6 7 8\n.tran 20m
TEXT 1504 120 Left 2 !.SUBCKT IPB032N10N5_L0 drain gate source\n \nLg     gate   g1   6.5n\nLd     drain  d1   0.1n\nLs     source s1   3.6n\nRs     s1     s2   411u  TC=3m\n \nRg     g1     g2   1.3\n \nM1     d2     g2    s2    s2    DMOS    L=1u   W=1u\n.MODEL DMOS NMOS ( KP=461.4  VTO=4.1  THETA=0  VMAX=1.5e5  ETA=0.0035  LEVEL=3)\nRd     d1    d2    2.12m  TC=7m\n \nDbd     s2    d2    Dbt\n.MODEL     Dbt    D(BV=107  M=0.75  CJO=1.5n  VJ=2.5V)\nRsp     s2    s3     0.44\nDbd1    s3    d2     Dbt1\n.MODEL     Dbt1    D(BV=1000   M=0.75  CJO=5.94n  VJ=2.5V)\nDbody   s2   21    DBODY\n.MODEL DBODY  D(IS=53.5p  N=1.12  RS=0.04u  EG=1.12  TT=20n)\nRdiode  d1  21    0.49m  TC=1m\n \n.MODEL   sw    NMOS(VTO=0  KP=10   LEVEL=1)\nMaux      g2   c    a    a   sw\nMaux2     b    d    g2    g2   sw\nEaux      c    a    d2    g2   1\nEaux2     d    g2   d2    g2   -1\nCox       b    d2   1.37n\n.MODEL     DGD    D(M=0.55  CJO=1.37n  VJ=0.5)\nRpar      b    d2   1Meg\nDgd       a    d2   DGD\nRpar2     d2   a    10Meg\nCgs     g2    s2    5.32n\n \n.ENDS IPB032N10N5_L0