* Z:\home\khalils\Downloads\files\data\raw_asc\0c61c7b74adb_AD4630-16.asc
* Generated by LTspice 26.0.1 for Windows.
Vin_cm N001 0 {cmval}
VinP input+ N001 SINE(0 2 2000)
Cfilt1 IN+ 0 1n
Rfilt1 input+ IN+ 33
Rfilt2 IN- input- 33
Cfilt2 0 IN- 1n
V3 CNV 0 PULSE(0 1.8 500n .2n .2n 19.8n 500n)
V4 RSTn 0 PWL(0 0 1n 0 2n 1.8)
VinN input- N001 SINE(0 2 2000 0 0 180)
V7 VREF 0 5
V8 VDD 0 5.4
R1 Vout 0 10k
XU1 IN+ VDD 0 Vout VREF CNV IN- RSTn NC_01 NC_02 AD4630-16 ;pnba IN+)VDD)GND)VOrti)REF)CNV)IN-)_RST)VOrto)Busy
.tran 0 2m 0 1n
.op plotwinsize=0 numdgt=15
.param cmval=2.5
* IN+, IN-: Sampling transients from analog inputs are modeled. Input range is +/-Vref.\nREF: For 5V Vref, VDD should be 5.4V +/-100mV\nVDD: For Vref=4.096V Vdd = 4.75V to 5.25V. For Vref=4.5V Vdd= 4.8V to 5.25V\nVout: Analog output +/-Vref\nCNV: 2MHz max 0V-1.8V logic level\nRSTn: Resets ADC. Tie to 1.8V for normal operation
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4630-16.asy)
.lib AD4630-16.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 12540 5124
WIRE 10688 3072 10480 3072
WIRE 10816 3072 10688 3072
WIRE 10816 3088 10816 3072
WIRE 10480 3168 10480 3072
WIRE 9808 3184 9680 3184
WIRE 9904 3184 9808 3184
WIRE 10016 3184 9984 3184
WIRE 10144 3184 10016 3184
WIRE 10816 3184 10816 3168
WIRE 9680 3200 9680 3184
WIRE 10016 3216 10016 3184
WIRE 10688 3216 10608 3216
WIRE 10816 3216 10688 3216
WIRE 10816 3232 10816 3216
WIRE 10144 3296 10144 3184
WIRE 10192 3296 10144 3296
WIRE 10256 3296 10192 3296
WIRE 9680 3312 9680 3280
WIRE 9680 3312 9472 3312
WIRE 10688 3312 10608 3312
WIRE 10720 3312 10688 3312
WIRE 10192 3328 10144 3328
WIRE 10256 3328 10192 3328
WIRE 10720 3328 10720 3312
WIRE 10816 3328 10816 3312
WIRE 9472 3344 9472 3312
WIRE 10016 3344 10016 3280
WIRE 10096 3344 10016 3344
WIRE 10096 3376 10096 3344
WIRE 9680 3408 9680 3312
WIRE 10016 3408 10016 3344
WIRE 10640 3408 10608 3408
WIRE 10672 3408 10640 3408
WIRE 10720 3424 10720 3408
WIRE 9472 3456 9472 3424
WIRE 10304 3456 10304 3376
WIRE 10304 3488 10304 3456
WIRE 10480 3488 10480 3456
WIRE 10672 3488 10672 3408
WIRE 9680 3504 9680 3488
WIRE 9808 3504 9680 3504
WIRE 9904 3504 9808 3504
WIRE 10016 3504 10016 3472
WIRE 10016 3504 9984 3504
WIRE 10144 3504 10144 3328
WIRE 10144 3504 10016 3504
WIRE 10304 3584 10304 3568
WIRE 10672 3584 10672 3568
FLAG 9472 3456 0
FLAG 9808 3184 input+
FLAG 9808 3504 input-
FLAG 10096 3376 0
FLAG 10672 3584 0
FLAG 10304 3584 0
FLAG 10816 3184 0
FLAG 10816 3328 0
FLAG 10480 3488 0
FLAG 10720 3424 0
FLAG 10192 3296 IN+
FLAG 10192 3328 IN-
FLAG 10688 3312 Vout
FLAG 10640 3408 CNV
FLAG 10304 3456 RSTn
FLAG 10688 3216 VDD
FLAG 10688 3072 VREF
SYMBOL voltage 9472 3328 M0
WINDOW 0 -7 8 Right 2
WINDOW 3 -6 98 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin_cm
SYMATTR Value {cmval}
SYMBOL voltage 9680 3184 R0
WINDOW 0 -29 15 Right 2
WINDOW 3 -20 90 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VinP
SYMATTR Value SINE(0 2 2000)
SYMBOL cap 10000 3216 R0
SYMATTR InstName Cfilt1
SYMATTR Value 1n
SYMBOL res 9888 3168 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt1
SYMATTR Value 33
SYMBOL res 10000 3488 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt2
SYMATTR Value 33
SYMBOL cap 10000 3408 R0
SYMATTR InstName Cfilt2
SYMATTR Value 1n
SYMBOL voltage 10672 3472 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -457 96 Left 2
WINDOW 0 -53 21 Left 2
SYMATTR Value PULSE(0 1.8 500n .2n .2n 19.8n 500n)
SYMATTR InstName V3
SYMBOL voltage 10304 3472 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PWL(0 0 1n 0 2n 1.8)
SYMBOL voltage 9680 3504 R180
WINDOW 0 84 95 Right 2
WINDOW 3 291 13 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VinN
SYMATTR Value SINE(0 2 2000 0 0 180)
SYMBOL voltage 10816 3072 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V7
SYMATTR Value 5
SYMBOL voltage 10816 3216 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value 5.4
SYMBOL res 10704 3312 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL AD4630-16 10512 3312 R0
SYMATTR InstName U1
TEXT 9664 3576 Left 2 !.tran 0 2m 0 1n\n.op plotwinsize=0 numdgt=15
TEXT 9664 3632 Left 2 !.param cmval=2.5
TEXT 9576 2944 Left 2 ;IN+, IN-: Sampling transients from analog inputs are modeled. Input range is +/-Vref.\nREF: For 5V Vref, VDD should be 5.4V +/-100mV\nVDD: For Vref=4.096V Vdd = 4.75V to 5.25V. For Vref=4.5V Vdd= 4.8V to 5.25V\nVout: Analog output +/-Vref\nCNV: 2MHz max 0V-1.8V logic level\nRSTn: Resets ADC. Tie to 1.8V for normal operation