* Z:\home\khalils\Downloads\files\data\raw_asc\25051e669ee7_Cd4046Vco.asc
* Generated by LTspice 26.0.1 for Windows.
D1 Cext1 VCC 1N914
D2 Cext2 VCC 1N914
S1c N003 Cext1 PSW 0 SW
S2c N003 Cext2 NSW 0 SW
M1 N003 VCOin R1 R1 BSS123
M2 N003 Th_ref R2 R2 BSS123
S1v Cext1 VCC NSW 0 SW
S2v Cext2 VCC PSW 0 SW
AsrFf N001 N002 0 0 0 NSW PSW 0 SRFLOP Td=10ns Trise=10ns Tfall=10ns
C1 Cext1 Cext2 10n
A2 Th_ref Cext2 0 0 0 0 N001 0 SCHMITT Vt=0 Vh=.1
A3 Th_ref Cext1 0 0 0 0 N002 0 SCHMITT Vt=0 Vh=.1
V+ VCC 0 {Vdd}
Vctl VCOin 0 PULSE(0 {Vdd} 0 2m 2m 1m)
R1 R1 0 10k
R2 R2 0 100k
Vref Th_ref 0 {Vdd*.6}
Eout VCOout 0 PSW 0 {Vdd}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model SW SW(Ron=10 Roff=10G Vt=0.5)
.tran 5ms
* @Title\nSimulation of the CMOS4046 VCO\nwith a behaviour similar to the real device\nconcerning the external pins.
* @Author\nAndreas Czechanowski, 2005-12-27
* external components
* NOTES:\n* The value of the threshold reference voltage Th_ref is probably not correct\n* Current-source transistors M1, M2 and diodes D1, D2 should be modelled correctly\n* The output stage is simplified by using Bout\n* The phase of the output voltage is probably inverted
.param Vdd=10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1192 952
WIRE -1280 656 -1280 592
WIRE -1280 800 -1280 736
WIRE -1136 656 -1136 608
WIRE -1136 800 -1136 736
WIRE -1040 688 -1040 656
WIRE -1040 800 -1040 768
WIRE -928 592 -944 592
WIRE -928 688 -928 656
WIRE -928 800 -928 768
WIRE -832 640 -832 624
WIRE -832 784 -832 768
WIRE -800 608 -800 544
WIRE -800 752 -800 608
WIRE -768 544 -800 544
WIRE -768 608 -800 608
WIRE -768 640 -832 640
WIRE -768 672 -768 656
WIRE -768 752 -800 752
WIRE -768 784 -832 784
WIRE -768 816 -768 800
WIRE -672 624 -704 624
WIRE -672 672 -672 624
WIRE -672 768 -704 768
WIRE -672 768 -672 720
WIRE -640 672 -672 672
WIRE -640 720 -672 720
WIRE -640 768 -640 752
WIRE -512 672 -544 672
WIRE -512 720 -528 720
WIRE -448 528 -464 528
WIRE -448 592 -448 576
WIRE -400 512 -400 480
WIRE -400 624 -400 592
WIRE -400 656 -400 624
WIRE -352 736 -352 720
WIRE -352 800 -352 784
WIRE -304 480 -400 480
WIRE -304 528 -304 480
WIRE -304 624 -400 624
WIRE -304 624 -304 592
WIRE -304 720 -304 624
WIRE -304 832 -304 800
WIRE -176 480 -304 480
WIRE -176 528 -176 480
WIRE -176 624 -176 592
WIRE -176 720 -176 624
WIRE -176 832 -304 832
WIRE -176 832 -176 800
WIRE -128 736 -128 720
WIRE -128 800 -128 784
WIRE -80 480 -176 480
WIRE -80 512 -80 480
WIRE -80 624 -176 624
WIRE -80 624 -80 592
WIRE -80 656 -80 624
WIRE -64 480 -80 480
WIRE -32 592 -32 576
WIRE -16 528 -32 528
WIRE 16 720 16 704
WIRE 32 720 16 720
WIRE 80 704 80 656
WIRE 80 832 -176 832
WIRE 80 832 80 800
WIRE 128 720 128 704
WIRE 144 720 128 720
WIRE 192 704 192 656
WIRE 192 832 80 832
WIRE 192 832 192 800
WIRE 272 720 272 688
WIRE 272 800 272 768
WIRE 320 800 272 800
WIRE 320 800 320 784
WIRE 320 816 320 800
WIRE 448 704 448 672
WIRE 448 816 448 784
FLAG -400 656 Cext1
IOPIN -400 656 BiDir
FLAG -80 656 Cext2
IOPIN -80 656 BiDir
FLAG -64 480 VCC
IOPIN -64 480 In
FLAG -128 800 0
FLAG 80 656 R1
IOPIN 80 656 BiDir
FLAG 192 656 R2
IOPIN 192 656 BiDir
FLAG -512 672 PSW
IOPIN -512 672 Out
FLAG -512 720 NSW
IOPIN -512 720 Out
FLAG -352 800 0
FLAG -352 720 PSW
IOPIN -352 720 In
FLAG -128 720 NSW
IOPIN -128 720 In
FLAG -448 592 0
FLAG -32 592 0
FLAG -16 528 PSW
IOPIN -16 528 In
FLAG -464 528 NSW
IOPIN -464 528 In
FLAG -1008 592 Cext1
FLAG -928 592 Cext2
FLAG -640 768 0
FLAG -832 624 Cext2
IOPIN -832 624 In
FLAG -832 768 Cext1
IOPIN -832 768 In
FLAG 448 816 0
FLAG 448 672 Th_ref
IOPIN 448 672 Out
FLAG -768 544 Th_ref
IOPIN -768 544 In
FLAG -1280 800 0
FLAG -1280 592 VCC
IOPIN -1280 592 Out
FLAG -1136 800 0
FLAG -1136 608 VCOin
IOPIN -1136 608 Out
FLAG 128 704 Th_ref
IOPIN 128 704 In
FLAG 16 704 VCOin
IOPIN 16 704 In
FLAG -768 672 0
FLAG -768 816 0
FLAG -1040 800 0
FLAG -1040 656 R1
FLAG -928 800 0
FLAG -928 656 R2
FLAG 320 704 VCOout
IOPIN 320 704 Out
FLAG 320 816 0
FLAG 272 688 PSW
IOPIN 272 688 In
SYMBOL diode -320 592 M180
WINDOW 0 -18 74 Left 0
WINDOW 3 -53 -18 Left 0
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL diode -160 592 R180
WINDOW 0 -24 72 Left 0
WINDOW 3 -62 -13 Left 0
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL sw -304 816 M180
WINDOW 3 -27 55 Left 0
SYMATTR InstName S1c
SYMBOL sw -176 816 R180
WINDOW 3 -26 55 Left 0
SYMATTR InstName S2c
SYMBOL nmos 32 800 M180
WINDOW 0 7 99 Left 0
WINDOW 3 22 29 Left 0
SYMATTR InstName M1
SYMATTR Value BSS123
SYMBOL nmos 144 800 M180
WINDOW 0 8 105 Left 0
WINDOW 3 -40 -13 Left 0
SYMATTR InstName M2
SYMATTR Value BSS123
SYMBOL sw -400 608 M180
WINDOW 0 -58 102 Left 0
WINDOW 3 -28 56 Left 0
SYMATTR InstName S1v
SYMBOL sw -80 608 R180
WINDOW 0 -58 98 Left 0
WINDOW 3 -26 56 Left 0
SYMATTR InstName S2v
SYMBOL Digital\\srflop -592 624 R0
WINDOW 3 -147 185 Left 0
WINDOW 0 -28 29 Left 0
SYMATTR Value Td=10ns Trise=10ns Tfall=10ns
SYMATTR InstName AsrFf
SYMBOL cap -1008 608 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL Digital\\diffschmtbuf -768 560 R0
WINDOW 3 -19 16 Left 0
WINDOW 0 23 63 Left 0
SYMATTR Value Vt=0 Vh=.1
SYMATTR InstName A2
SYMBOL Digital\\diffschmtbuf -768 704 R0
WINDOW 3 -19 13 Left 0
WINDOW 0 24 63 Left 0
SYMATTR Value Vt=0 Vh=.1
SYMATTR InstName A3
SYMBOL voltage -1280 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -28 54 Left 0
SYMATTR Value {Vdd}
SYMATTR InstName V+
SYMBOL voltage -1136 640 R0
WINDOW 3 -164 191 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -18 58 Left 0
SYMATTR Value PULSE(0 {Vdd} 0 2m 2m 1m)
SYMATTR InstName Vctl
SYMBOL Misc\\EuropeanResistor -1056 672 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL Misc\\EuropeanResistor -944 672 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage 448 688 R0
WINDOW 0 -23 59 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -90 106 Left 0
SYMATTR InstName Vref
SYMATTR Value {Vdd*.6}
SYMBOL e 320 688 R0
WINDOW 0 -25 56 Left 0
WINDOW 3 28 21 Left 0
SYMATTR InstName Eout
SYMATTR Value {Vdd}
TEXT -392 848 Left 0 !.model SW SW(Ron=10 Roff=10G Vt=0.5)
TEXT 344 848 Left 0 !.tran 5ms
TEXT -408 368 Left 0 ;@Title\nSimulation of the CMOS4046 VCO\nwith a behaviour similar to the real device\nconcerning the external pins.
TEXT 56 424 Left 0 ;@Author\nAndreas Czechanowski, 2005-12-27
TEXT -1112 512 Left 0 ;external components
TEXT -1328 360 Left 0 ;NOTES:\n* The value of the threshold reference voltage Th_ref is probably not correct\n* Current-source transistors M1, M2 and diodes D1, D2 should be modelled correctly\n* The output stage is simplified by using Bout\n* The phase of the output voltage is probably inverted
TEXT 80 848 Left 0 !.param Vdd=10
RECTANGLE Normal -864 848 -1328 496