Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\0af14298bf79_voltagesense_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N003 N004 470k
R2 N005 N002 1Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 712
WIRE 96 -48 -416 -48
WIRE 96 0 96 -48
WIRE 48 64 0 64
WIRE 96 112 96 96
WIRE 96 256 96 192
WIRE 192 256 96 256
WIRE 304 256 256 256
WIRE 192 352 128 352
WIRE 304 352 304 256
WIRE 304 352 256 352
WIRE 128 384 128 352
WIRE 304 384 304 352
WIRE 0 480 0 64
WIRE 128 480 128 464
WIRE 128 480 0 480
WIRE 304 480 304 464
WIRE 304 480 128 480
SYMBOL res 80 96 R0
SYMATTR InstName R1
SYMATTR Value 470k
SYMBOL res 288 368 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\35b485c8cce3_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 0 4000
R2 N001 N002 1000
I1 0 N001 I={Isrc}
.dc Isrc 0A 1A 0.1A
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 32 64 32
WIRE 256 64 256 32
WIRE 64 128 64 32
WIRE 256 176 256 144
WIRE 64 304 64 208
WIRE 256 304 256 256
WIRE 256 304 64 304
WIRE 256 336 256 304
FLAG 256 336 0
SYMBOL res 240 160 R0
SYMATTR InstName R1
SYMATTR Value 4000
SYMBOL res 240 48 R0
SYMATTR InstName R2
SYMATTR Value 1000
SYMBOL current 64 208 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value I={Isrc}
TEXT -80 392 Left 2 !.dc Isrc 0A 1A 0.1A
* Z:\home\khalils\Downloads\files\data\raw_asc\16b0bf0f19a4_1734-4.1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1734-4.1.asy)
XU1 N002 0 N001 N004 N005 N003 LTC1734-x.x Ref=4.1 ;pnba Isense)GND)Vcc)Prog)BAT)Drive
R1 N004 0 1K
C1 N005 0 1
V1 N001 0 7
Q1 N005 N003 N002 0 2N2907
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 5 startup
.lib LTC1734-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2284 1688
WIRE 1680 1280 1536 1280
WIRE 2096 1280 1968 1280
WIRE 1536 1296 1536 1280
WIRE 2096 1328 2096 1280
WIRE 1680 1376 1664 1376
WIRE 2032 1376 1968 1376
WIRE 1536 1392 1536 1376
WIRE 1584 1472 1568 1472
WIRE 1680 1472 1664 1472
WIRE 2096 1472 2096 1424
WIRE 2096 1472 1968 1472
WIRE 2096 1488 2096 1472
WIRE 2096 1568 2096 1552
SYMBOL PowerProducts\\LTC1734-4.1 1824 1376 R0
SYMATTR InstName U1
SYMBOL RES 1680 1456 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL VOLTAGE 1536 1280 R0
SYMATTR InstName V1
SYMATTR Value 7
SYMBOL PNP 2032 1424 M180
WINDOW 0 76 72 Left 2
WINDOW 3 76 36 Left 2
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL cap 2080 1488 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 1568 1472 0
FLAG 1664 1376 0
FLAG 1536 1392 0
FLAG 2096 1568 0
TEXT 1840 1592 Left 2 !.tran 5 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\31c08986be65_Prob_4a2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 0 Vgs 1
V2 0 Vds 1.8V
M1 Vds Vgs 0 0 pch_tt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.dc V2 0 1.8 0.01 V1 0 1 0.2
;.dc V1 0 1 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 400 48 368 48
WIRE 368 64 368 48
WIRE 368 64 224 64
WIRE 224 80 224 64
WIRE 368 80 368 64
WIRE 48 160 16 160
WIRE 176 160 48 160
WIRE 48 176 48 160
WIRE 224 192 224 176
WIRE 368 192 368 160
WIRE 48 272 48 256
FLAG 48 272 0
FLAG 224 192 0
FLAG 368 192 0
FLAG 16 160 Vgs
IOPIN 16 160 In
FLAG 400 48 Vds
IOPIN 400 48 Out
SYMBOL voltage 48 272 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMBOL voltage 368 176 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8V
SYMBOL pmos 176 80 R0
SYMATTR InstName M1
SYMATTR Value pch_tt
TEXT -128 32 Left 2 !.include TSMC180.lib
TEXT -128 296 Left 2 !.dc V2 0 1.8 0.01 V1 0 1 0.2
TEXT -136 328 Left 2 !;.dc  V1 0 1 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8609A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8609A.asy)
Rload OUT 0 2.5
C1 N004 0 1n
C3 N002 N003 0.1
C4 OUT 0 22 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
L1 N003 OUT 2.2 Rser=3m
R2 OUT N005 1Meg
C2 N001 0 1
C5 OUT N005 10p
XU1 N002 N003 N001 N006 NC_01 N005 N004 NC_02 IN IN 0 LT8609A ;pnba BST)SW)INTVcc)RT)SYNC)FB)TR/SS)PG)VIN)EN/UV)GND
R3 N005 0 187K
R1 N006 0 18.2K
V1 IN 0 24
.tran 500u startup
.lib LT8609A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1028 680
WIRE 32 -80 0 -80
WIRE 80 -80 32 -80
WIRE 256 -80 80 -80
WIRE 0 -48 0 -80
WIRE 256 -48 256 -80
WIRE 80 0 80 -80
WIRE 112 0 80 0
WIRE 416 0 400 0
WIRE 496 0 480 0
WIRE 0 48 0 32
WIRE 432 96 400 96
WIRE 432 112 432 96
WIRE 432 192 432 176
WIRE 432 192 400 192
WIRE 512 192 432 192
WIRE 624 192 592 192
WIRE 736 192 624 192
WIRE 832 192 736 192
WIRE 880 192 832 192
WIRE 928 192 880 192
WIRE 624 208 624 192
WIRE 736 208 736 192
WIRE 832 208 832 192
WIRE 928 208 928 192
WIRE 32 288 0 288
WIRE 112 288 96 288
WIRE 624 288 400 288
WIRE 736 288 736 272
WIRE 736 288 624 288
WIRE 624 304 624 288
WIRE 832 304 832 272
WIRE 928 304 928 288
WIRE 16 384 0 384
WIRE 112 384 96 384
WIRE 416 384 400 384
WIRE 624 400 624 384
SYMBOL voltage 0 -64 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 112 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 18.2K
SYMBOL cap 416 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL LT8609A 256 192 R0
SYMATTR InstName U1
SYMBOL res 608 192 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL cap 96 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 912 192 R0
SYMATTR InstName Rload
SYMATTR Value 2.5
SYMBOL cap 416 112 R0
SYMATTR InstName C3
SYMATTR Value 0.1
SYMBOL res 608 288 R0
SYMATTR InstName R3
SYMATTR Value 187K
SYMBOL cap 720 208 R0
SYMATTR InstName C5
SYMATTR Value 10p
SYMBOL cap 816 208 R0
SYMATTR InstName C4
SYMATTR Value 22
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL ind 496 208 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=3m
FLAG 0 384 0
FLAG 0 288 0
FLAG 0 48 0
FLAG 496 0 0
FLAG 832 304 0
FLAG 624 400 0
FLAG 928 304 0
FLAG 880 192 OUT
FLAG 32 -80 IN
FLAG 416 384 0
TEXT 616 448 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\138749826563_BUCK-CCM-VM.asc
* Generated by LTspice 26.0.1 for Windows.
* BUCK-CCM-VM
* TR DC model:\nA=Active node, the switch terminal not connected to the diode\nP=Pasive node, the diode terminal not connected to the switch\nC=Common node, the junction between the diode and the power switch terminal\nCheck the right diode polarity
* A node current accepted, hence "-" sign on I=-I(B2)*V(D)
* DC bias
B2 C P V=V(A,P)*V(D)
B1 A P I=-I(B2)*V(D)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 928 680
WIRE 192 -112 -48 -112
WIRE 704 -112 448 -112
WIRE 192 -32 192 -112
WIRE 448 -32 448 -112
WIRE 192 144 192 48
WIRE 192 144 -48 144
WIRE 448 144 448 48
WIRE 448 144 192 144
WIRE 64 256 -48 256
IOPIN -48 -112 In
IOPIN -48 144 In
IOPIN 704 -112 Out
IOPIN -48 256 In
RECTANGLE Normal 704 304 -48 -208
SYMBOL bv 448 -48 R0
SYMATTR InstName B2
SYMATTR Value V=V(A,P)*V(D)
SYMBOL bi 192 -32 R0
SYMATTR InstName B1
SYMATTR Value I=-I(B2)*V(D)
FLAG -48 -112 A
FLAG -48 144 P
FLAG 704 -112 C
FLAG -48 256 D
TEXT 208 -192 Left 0 ;BUCK-CCM-VM
TEXT -48 336 Left 0 ;TR DC model:\nA=Active node, the switch terminal not connected to the diode\nP=Pasive node, the diode terminal not connected to the switch\nC=Common node, the junction between the diode and the power switch terminal\nCheck the right diode polarity
TEXT 32 280 Left 0 ;A node current accepted, hence "-" sign on I=-I(B2)*V(D)
TEXT -32 240 Left 0 ;DC bias
* Z:\home\khalils\Downloads\files\data\raw_asc\LT4320-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LT4320-1.asy)
MQ2 OUT N004 N002 N002 IPD220N06L3
V1 N002 N001 SINE(0 36 400) Rser=.5
MQ1 OUT N003 N001 N001 IPD220N06L3
MQ4 N002 N005 0 0 IPD220N06L3
XU1 N001 N003 N005 N006 0 OUT N004 N002 LT4320-1 ;pnba IN2)TG2)BG2)BG1)Outn)Outp)TG1)IN1
MQ3 N001 N006 0 0 IPD220N06L3
C1 OUT 0 200
Rload OUT 0 32
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 12.5m
.lib LT4320-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1320 1428
WIRE 48 -112 0 -112
WIRE 656 -112 144 -112
WIRE -64 -16 -304 -16
WIRE 416 -16 -64 -16
WIRE 448 -16 416 -16
WIRE 656 -16 656 -112
WIRE 656 -16 544 -16
WIRE 720 -16 656 -16
WIRE 848 -16 720 -16
WIRE 720 0 720 -16
WIRE 848 0 848 -16
WIRE -304 16 -304 -16
WIRE 0 48 0 -112
WIRE 96 48 0 48
WIRE 416 48 416 -16
WIRE 416 48 384 48
WIRE 720 96 720 64
WIRE 848 96 848 80
WIRE 64 112 64 -64
WIRE 96 112 64 112
WIRE 464 112 464 32
WIRE 464 112 384 112
WIRE -304 128 -304 96
WIRE -144 128 -304 128
WIRE 0 128 0 48
WIRE 0 128 -144 128
WIRE 96 176 32 176
WIRE 656 176 656 -16
WIRE 656 176 384 176
WIRE 96 240 64 240
WIRE 416 240 384 240
WIRE 32 288 32 176
WIRE 64 288 64 240
WIRE 304 288 64 288
WIRE -64 336 -64 -16
WIRE -48 336 -64 336
WIRE 416 336 416 240
WIRE 416 336 48 336
WIRE 304 384 304 288
WIRE -144 432 -144 128
WIRE 224 432 -144 432
WIRE 416 432 416 336
WIRE 416 432 320 432
WIRE 448 432 416 432
SYMBOL nmos -48 288 M90
WINDOW 0 4 52 VBottom 2
WINDOW 3 57 43 VTop 2
SYMATTR InstName Q4
SYMATTR Value IPD220N06L3
SYMBOL voltage -304 0 R0
WINDOW 123 24 138 Left 2
WINDOW 39 42 56 Left 2
SYMATTR SpiceLine Rser=.5
SYMATTR InstName V1
SYMATTR Value SINE(0 36 400)
SYMBOL res 832 -16 R0
SYMATTR InstName Rload
SYMATTR Value 32
SYMBOL nmos 224 384 M90
WINDOW 0 5 48 VBottom 2
WINDOW 3 54 48 VTop 2
SYMATTR InstName Q3
SYMATTR Value IPD220N06L3
SYMBOL nmos 544 32 M270
WINDOW 0 56 43 VTop 2
WINDOW 3 -15 73 VLeft 2
SYMATTR InstName Q2
SYMATTR Value IPD220N06L3
SYMBOL LT4320-1 240 144 R0
SYMATTR InstName U1
SYMBOL cap 704 0 R0
SYMATTR InstName C1
SYMATTR Value 200
SYMBOL nmos 144 -64 M270
WINDOW 0 55 44 VTop 2
WINDOW 3 -14 71 VLeft 2
SYMATTR InstName Q1
SYMATTR Value IPD220N06L3
FLAG 848 -16 OUT
FLAG 720 96 0
FLAG 848 96 0
FLAG 448 432 0
TEXT 704 384 Left 2 !.tran 12.5m
* Z:\home\khalils\Downloads\files\data\raw_asc\1ea338c01c33_ADuM4121A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4121A.asy)
V1 N001 0 5
XU1 N001 N003 0 0 0 OUT N004 N002 ADuM4121A ;pnba Vdd1)VI+)VI-)GND1)GND2)Clamp)Vout)Vdd2
V2 N002 0 15
V3 N003 0 PULSE(0 5 0 2n 2n 998n 2u)
C1 OUT 0 2n
R1 OUT N004 5
.tran 100u startup
.lib ADuM4121A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -16 -240 -16
WIRE 640 -16 320 -16
WIRE -240 0 -240 -16
WIRE 640 0 640 -16
WIRE 160 64 160 -16
WIRE 320 64 320 -16
WIRE -240 96 -240 80
WIRE 640 96 640 80
WIRE 112 128 -240 128
WIRE 384 128 368 128
WIRE 480 128 464 128
WIRE 528 128 480 128
WIRE -240 144 -240 128
WIRE 528 144 528 128
WIRE 112 192 96 192
WIRE 480 192 480 128
WIRE 480 192 368 192
WIRE 528 224 528 208
WIRE -240 240 -240 224
WIRE 160 272 160 256
WIRE 320 272 320 256
SYMBOL voltage -240 128 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 2n 2n 998n 2u)
SYMBOL cap 512 144 R0
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL res 480 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5
SYMBOL voltage 640 -16 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL voltage -240 -16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\ADUm4121A 240 160 R0
SYMATTR InstName U1
FLAG 160 272 0
FLAG 320 272 0
FLAG 528 224 0
FLAG 528 128 OUT
FLAG 640 96 0
FLAG -240 96 0
FLAG -240 240 0
FLAG 96 192 0
TEXT 440 288 Left 2 !.tran 100u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\14fc0fa9b89d_linear_inductor.asc
* Generated by LTspice 26.0.1 for Windows.
* G1, C1, E1 models volt-seconds\n applied to inductor
* F1, V1 reflects current resulting\n from applied volt-seconds
* R1 models linear inductance\n with unity gain: L = C1*R1
* V1 senses current drawn by\n applied volt-seconds
* Generalized Impedance Converter Based Linear Inductor Model
* L1: the reference standard\n (compare its current to that\n of the various models)
V1 N001 3 0
R1 3 0 1m
C1 2 0 1
E1 N001 0 2 0 1
F1 1 0 V1 1
Vs 1 0 PULSE(-1 1 1m .1u .1u 2m 4m)
G1 0 2 1 0 1
L1 1 0 1m
.tran 0 10m 1u uic
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1044 680
WIRE -112 -80 -112 -112
WIRE -112 32 -112 0
WIRE -160 -64 -160 -112
WIRE -160 -112 -240 -112
WIRE -304 -112 -304 -80
WIRE -304 0 -304 32
WIRE -160 -16 -160 32
WIRE -240 32 -240 -16
WIRE -240 -80 -240 -112
WIRE -240 -112 -272 -112
WIRE -352 -16 -352 32
WIRE -352 -112 -432 -112
WIRE -352 -112 -352 -64
WIRE -432 -112 -576 -112
WIRE -432 32 -432 0
WIRE -432 -80 -432 -112
WIRE -640 32 -640 0
WIRE -640 -80 -640 -112
WIRE -608 -112 -640 -112
WIRE 48 -112 48 -80
WIRE 48 0 48 32
WIRE 48 -112 16 -112
WIRE -112 -112 -64 -112
WIRE 48 -112 80 -112
WIRE -272 -112 -304 -112
WIRE 80 -112 96 -112
WIRE -576 -112 -576 -80
WIRE -576 0 -576 32
WIRE -576 -112 -608 -112
LINE Normal -96 -160 -288 -160 2
LINE Normal -64 -144 -96 -160 2
LINE Normal -320 -144 -288 -160 2
LINE Normal -384 -80 -320 -144 2
SYMBOL cap -256 -80 R0
WINDOW 0 32 0 Left 0
WINDOW 3 32 80 Left 0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -80 -112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 Invisible 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL voltage -640 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 48 72 Left 0
WINDOW 3 -48 176 Left 0
WINDOW 0 -42 57 Right 0
SYMATTR Value PULSE(-1 1 1m .1u .1u 2m 4m)
SYMATTR InstName Vs
SYMBOL res 32 -96 R0
WINDOW 0 32 16 Left 0
WINDOW 3 32 96 Left 0
SYMATTR InstName R1
SYMATTR Value 1m
SYMBOL e -112 -96 R0
WINDOW 0 16 16 Left 0
WINDOW 3 16 96 Left 0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL g -304 -96 R0
WINDOW 0 16 16 Left 0
WINDOW 3 16 96 Left 0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL f -432 -80 R0
WINDOW 0 16 0 Left 0
WINDOW 3 40 41 Left 0
WINDOW 123 16 80 Left 0
SYMATTR InstName F1
SYMATTR Value V1
SYMATTR Value2 1
SYMBOL ind -560 -96 M0
WINDOW 0 0 16 Right 0
WINDOW 3 0 96 Right 0
SYMATTR InstName L1
SYMATTR Value 1m
FLAG -272 -112 2
FLAG -640 32 0
FLAG -608 -112 1
FLAG -304 32 0
FLAG -240 32 0
FLAG -160 32 0
FLAG -112 32 0
FLAG 48 32 0
FLAG 80 -112 3
FLAG -576 32 0
FLAG -432 32 0
FLAG -352 32 0
TEXT -688 -160 Left 0 !.tran 0 10m 1u uic
TEXT -248 -192 VLeft 0 ;G1, C1, E1 models volt-seconds\n applied to inductor
TEXT -432 -192 VLeft 0 ;F1, V1 reflects current resulting\n from applied volt-seconds
TEXT 56 -192 VLeft 0 ;R1 models linear inductance\n with unity gain: L = C1*R1
TEXT -56 -192 VLeft 0 ;V1 senses current drawn by\n applied volt-seconds
TEXT -296 -624 Bottom 0 ;Generalized Impedance Converter Based Linear Inductor Model
TEXT -592 -192 VLeft 0 ;L1: the reference standard\n (compare its current to that\n of the various models)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM7223C.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM7223C.asy)
C2 VOB 0 2n
V2 inputB 0 PULSE(5 0 0 2n 2n 5u 10u)
V5 VDDA 0 12
C1 VOA 0 2n
V6 VDDB 0 12
V3 VDD1 0 5
XU1 0 inputA inputB 0 VDD1 0 VOB VDDB 0 VOA VDDA ADuM7223C ;pnba GND1)VIA)VIB)DISABLE)VDD1)GNDB)VOB)VDDB)GNDA)VOA)VDDA
V1 inputA 0 PULSE(0 5 0 2n 2n 5u 10u)
.tran 50u
.lib ADuM7223C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1228 692
WIRE 416 16 368 16
WIRE 688 16 416 16
WIRE 64 32 -64 32
WIRE -64 48 -64 32
WIRE 416 80 368 80
WIRE 592 80 416 80
WIRE 592 96 592 80
WIRE 16 112 -448 112
WIRE 64 112 16 112
WIRE 688 128 688 96
WIRE 432 144 368 144
WIRE -448 160 -448 112
WIRE 592 176 592 160
WIRE 16 192 -288 192
WIRE 64 192 16 192
WIRE 416 224 368 224
WIRE 688 224 416 224
WIRE -448 256 -448 240
WIRE 64 272 -80 272
WIRE 416 288 368 288
WIRE 592 288 416 288
WIRE -288 304 -288 272
WIRE -80 304 -80 272
WIRE 592 304 592 288
WIRE 16 352 -80 352
WIRE 64 352 16 352
WIRE 432 352 368 352
WIRE 432 368 432 352
WIRE -80 384 -80 352
WIRE 592 384 592 368
WIRE -80 480 -80 464
SYMBOL voltage 688 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V5
SYMATTR Value 12
SYMBOL voltage -80 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 32 90 Left 2
SYMATTR Value 5
SYMATTR InstName V3
SYMBOL voltage 688 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 12
SYMBOL cap 576 304 R0
SYMATTR InstName C2
SYMATTR Value 2n
SYMBOL ADuM7223C 224 112 R0
SYMATTR InstName U1
SYMBOL voltage -448 144 R0
WINDOW 0 30 80 Left 2
WINDOW 3 18 -5 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 2n 2n 5u 10u)
SYMBOL cap 576 96 R0
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL voltage -288 176 R0
WINDOW 0 20 108 Left 2
WINDOW 3 39 40 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(5 0 0 2n 2n 5u 10u)
FLAG -80 480 0
FLAG -448 256 0
FLAG -288 304 0
FLAG 592 176 0
FLAG 592 384 0
FLAG 416 288 VOB
FLAG 416 80 VOA
FLAG 432 368 0
FLAG 432 144 0
FLAG 16 192 inputB
FLAG 688 304 0
FLAG 688 128 0
FLAG 16 352 VDD1
FLAG -64 48 0
FLAG 416 224 VDDB
FLAG 16 112 inputA
FLAG 416 16 VDDA
FLAG -80 304 0
TEXT 64 440 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX8627.asc
* Generated by LTspice 26.0.1 for Windows.
* Fault delay is parameterized for fast simulation,\nbut it is fixed at 64 ms on the real part.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX8627.asy)
C1 vOUT 0 22 m=2
Rload vOUT 0 50
XU1 0 vIN vIN N003 vOUT N001 N002 vOUT MAX8627 fault_delay=0.8m ;pnba GND)BATT)ON)FB)POUT)LX)ILIM)OUTS
R2 N002 0 294k
L1 vIN N001 1 Rser=17m
R1 vOUT N002 2.21Meg
R4 0 N003 102k
R3 N003 vOUT 402k
V1 vIN 0 3.6
.tran 1.4m startup
.lib MAX8627.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1080 680
WIRE 288 -112 144 -112
WIRE 496 -112 368 -112
WIRE 48 -32 32 -32
WIRE 144 -32 144 -112
WIRE 144 -32 48 -32
WIRE 176 -32 144 -32
WIRE 496 -32 496 -112
WIRE 496 -32 464 -32
WIRE 32 -16 32 -32
WIRE 496 48 464 48
WIRE 544 48 496 48
WIRE 656 48 544 48
WIRE 752 48 656 48
WIRE 800 48 752 48
WIRE 544 64 544 48
WIRE 800 64 800 48
WIRE 32 80 32 64
WIRE 144 96 144 -32
WIRE 176 96 144 96
WIRE 656 112 656 48
WIRE 496 128 496 48
WIRE 496 128 464 128
WIRE 800 160 800 144
WIRE 544 176 544 128
WIRE -48 224 -80 224
WIRE 80 224 32 224
WIRE 176 224 80 224
WIRE 656 224 656 192
WIRE 656 224 464 224
WIRE 80 240 80 224
WIRE 656 240 656 224
WIRE 80 336 80 320
WIRE 656 336 656 320
WIRE 320 384 320 368
WIRE -80 432 -80 224
WIRE 752 432 752 48
WIRE 752 432 -80 432
SYMBOL voltage 32 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL res -64 208 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2.21Meg
SYMBOL cap 528 64 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 m=2
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL MAX8627 320 144 R0
SYMATTR InstName U1
SYMBOL ind 272 -96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=17m
SYMBOL res 640 336 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 102k
SYMBOL res 640 208 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 402k
SYMBOL res 64 224 R0
SYMATTR InstName R2
SYMATTR Value 294k
SYMBOL res 784 48 R0
SYMATTR InstName Rload
SYMATTR Value 50
FLAG 32 80 0
FLAG 320 384 0
FLAG 544 176 0
FLAG 800 160 0
FLAG 48 -32 vIN
FLAG 800 48 vOUT
FLAG 80 336 0
FLAG 656 336 0
TEXT 472 400 Left 2 !.tran 1.4m startup
TEXT 96 456 Left 2 ;Fault delay is parameterized for fast simulation,\nbut it is fixed at 64 ms on the real part.
* Z:\home\khalils\Downloads\files\data\raw_asc\06a54b5845e1_Fig18_5.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N002 Vin 0 0 N_50n l=50n w=500n
Vin Vin 0 PULSE(0 1 0 100n 100n 1n 2u)
M5 VDD Vin N001 VDD P_50n l=50n w=1u
M2 Vout Vin N002 0 N_50n l=50n w=500n
M4 N001 Vin Vout VDD P_50n l=50n w=1u
VDD VDD 0 1
M3 VDD Vout N002 0 N_50n l=50n w=1.125u
M6 N001 Vout 0 VDD P_50n l=50n w=1.3u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 200n
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 160 -496 160 -512
WIRE 160 -480 160 -496
WIRE 160 -368 160 -400
WIRE 160 -192 160 -208
WIRE 160 -96 160 -112
WIRE 320 -208 304 -208
WIRE 368 -272 368 -432
WIRE 368 -208 320 -208
WIRE 368 -208 368 -272
WIRE 368 -96 368 -208
WIRE 368 64 368 -96
WIRE 400 -432 368 -432
WIRE 400 -272 368 -272
WIRE 400 -96 368 -96
WIRE 400 64 368 64
WIRE 448 -512 448 -560
WIRE 448 -384 448 -416
WIRE 448 -352 448 -384
WIRE 448 -208 448 -256
WIRE 448 -176 448 -208
WIRE 448 -48 448 -80
WIRE 448 -16 448 -48
WIRE 448 128 448 80
WIRE 688 -384 448 -384
WIRE 720 -48 448 -48
WIRE 736 -208 448 -208
WIRE 736 -96 736 -208
WIRE 768 -208 736 -208
WIRE 768 -208 768 -336
WIRE 848 -384 784 -384
WIRE 848 -352 848 -384
WIRE 848 -48 816 -48
WIRE 848 -48 848 -112
WIRE 992 -208 768 -208
WIRE 1024 -208 992 -208
SYMBOL nmos4 816 -96 R90
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M3
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=1.125u
SYMBOL pmos4 400 -352 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 400 -16 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 688 -336 R270
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1.3u
SYMBOL voltage 160 -496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL nmos4 400 -176 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M2
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 160 -208 R0
WINDOW 0 -72 21 Left 0
WINDOW 3 -149 149 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value PULSE(0 1 0 100n 100n 1n 2u)
SYMBOL pmos4 400 -512 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
FLAG 160 -96 0
FLAG 160 -208 Vin
FLAG 448 32 0
FLAG 160 -368 0
FLAG 160 -496 VDD
FLAG 448 -464 VDD
FLAG 448 128 0
FLAG 448 -560 VDD
FLAG 320 -208 Vin
FLAG 448 -304 VDD
FLAG 448 -128 0
FLAG 992 -208 Vout
FLAG 736 -384 VDD
FLAG 768 -48 0
FLAG 848 -112 VDD
FLAG 848 -352 0
TEXT 88 -16 Left 0 !.tran 200n
TEXT 24 24 Left 0 !.lib cmosedu_models.txt