* Z:\home\khalils\Downloads\files\data\raw_asc\LT3380.asc
* Generated by LTspice 26.0.1 for Windows.
* Mode of Operation\n \n Mode_x - 0 - Pulse-Skipping Mode\n 1 - Burst Mode Operation\n 2 - Forced Continuous Mode\n \n *The switching converters operate in PSKIP mode during SoftStart (SS)\n and mode transition happens after SS and Time delay, Td:\n For Bucks 1&2:\n > 2.7Vin: Td=500us\n > 5.5Vin: Td=3.2ms\n For Bucks 3&4:\n > 3.3Vin: Td=1.6ms\n > 5.5Vin: Td=3.6ms\n \nSwitching Frequency\n \n FSW_x - 0 Switching Frequency 2.25MHz\n 1 - Switching Frequency 1.125MHz\n \nPhase\n \n PH_x - 0 - Clock Phase 1\n 1 - Clock Phase 2\n \n \nVoltage Feedback Programming \n \n with 12.5mV LSB Step Size (Use Dec Fomart)\n E.g. 11111 (Bin) = 31 (Dec)\n \n Decimal Input = FB Reference\n 0 = 412.5mV\n 25 = 725mV\n 31 = 800mV
* *Bx - Buckx\n*Lx - LDOx\n \nSoftware Enable\n \n sEn_Bx/Lx - 0 - Disabled if EN Pin Is Low\n 1 - Enabled\n \nKeep Alive\n \n KA_Bx/Lx - 0 - Do Not Keep Enabled in Device Standby\n 1 - Keep Enabled in Device Standby\n \nEnable Output Offset\n \n EOO_Bx/Lx - 0 - Enable at Any Output Voltage\n 1 - Enable Only if Output Voltage Is <300mV\n \nTurn Off Delay / Sequence Down Control\n \n tOff_Bx/Lx - 0 - Disable Regulator at Falling PWR_ON\n 1 - Disable Regulator at Falling PWR_ON + 100ms\n 2 - Disable Regulator at Falling PWR_ON + 200ms\n 3 - Disable Regulator at Falling PWR_ON + 300ms
* Configurable Parameters
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3380.asy)
R4 N005 0 1Meg
C3 vBUCK3 0 47 Rser=1m
C8 vBUCK1 N003 10p Rpar=649k
C6 L2_OUT 0 1
RLOAD2 vBUCK2 0 5k
C5 L1_OUT 0 1
R16 PG vIN 100k
L3 N007 vBUCK3 1.5
C10 vBUCK3 N008 10p Rpar=1Meg
R21 L1_OUT N002 649k
XU1 N006 vIN L2_OUT L3_OUT vIN L1_OUT vIN N002 vBUCK4 L2_OUT N001 vIN 0 MP_01 vIN vIN vIN vBUCK1 MP_02 N004 vIN N005 N003 N010 N008 MP_03 vIN MP_04 MP_05 L1_OUT N007 MP_06 MP_07 vBUCK2 vIN vIN vBUCK3 MP_08 PG N009 LT3380 Mode_1=0 Mode_2=0 Mode_3=0 Mode_4=0 FSW_1=0 FSW_2=0 FSW_3=0 FSW_4=0 PH_1=0 PH_2=0 PH_3=0 PH_4=0 VFB_1=25 VFB_2=25 VFB_3=25 VFB_4=25 sEn_B1=0 sEn_B2=0 sEn_B3=0 sEn_B4=0 sEn_L1=0 sEn_L2=0 sEn_L3=0 KA_B1=0 KA_B2=0 KA_B3=0 KA_B4=0 KA_L1=0 KA_L2=0 KA_L3=0 EOO_B1=0 EOO_B2=0 EOO_B3=0 EOO_B4=0 EOO_L1=0 EOO_L2=0 EOO_L3=0 tOFF_B1=0 tOFF_B2=0 tOFF_B3=0 tOFF_B4=0 tOFF_L1=0 tOFF_L2=0 tOFF_L3=0 mskPG_B1=1 mskPG_B2=1 mskPG_B3=1 mskPG_B4=1 mskPG_L1=1 mskPG_L2=1 mskPG_L3=1 ;pnba FB_L2)Vin_L2)LDO2)LDO3)Vin_L3)LDO1)Vin_L1)FB_L1)EN_L1)EN_L3)SW1)DVdd)GND))PVin1)PVin2)EN_B1)EN_B2))SW2)PWR_ON)FB_B2)FB_B1)FB_B4)FB_B3))Vin)))EN_L2)SW3)))EN_B3)PVin3)PVin4)EN_B4))PGOOD)SW4
L2 N004 vBUCK2 0.82
R25 N003 0 1Meg
RLOAD3 vBUCK3 0 5
C1 vBUCK1 0 47 Rser=1m
C9 vBUCK2 N005 10p Rpar=1.07Meg
R13 L3_OUT 0 15
R2 L2_OUT N006 102K
R11 N006 0 1Meg
C11 vBUCK4 N010 10p Rpar=1Meg
R6 N008 0 412k
L4 N009 vBUCK4 1.5
R22 N002 0 1Meg
C2 vBUCK2 0 47 Rser=1m
RLOAD4 vBUCK4 0 5
R15 L1_OUT 0 5
C7 L3_OUT 0 1
L1 N001 vBUCK1 0.82
R12 L2_OUT 0 5
V1 vIN 0 5
R8 N010 0 665k
C4 vBUCK4 0 47 Rser=1m
RLOAD1 vBUCK1 0 5k
.tran 10m startup
.lib LT3380.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5012 2548
WIRE -64 -480 -96 -480
WIRE 128 -480 -64 -480
WIRE 288 -480 128 -480
WIRE 448 -480 288 -480
WIRE -96 -448 -96 -480
WIRE 288 -432 288 -480
WIRE 128 -384 128 -480
WIRE 144 -384 128 -384
WIRE 448 -384 448 -480
WIRE 448 -384 432 -384
WIRE -96 -352 -96 -368
WIRE -352 -288 -400 -288
WIRE -256 -288 -352 -288
WIRE -48 -288 -256 -288
WIRE 144 -288 -48 -288
WIRE 496 -288 432 -288
WIRE 624 -288 576 -288
WIRE 864 -288 624 -288
WIRE 976 -288 864 -288
WIRE 1024 -288 976 -288
WIRE 624 -256 624 -288
WIRE 1024 -256 1024 -288
WIRE -400 -240 -400 -288
WIRE -256 -240 -256 -288
WIRE -48 -240 -48 -288
WIRE 864 -240 864 -288
WIRE 144 -192 48 -192
WIRE 512 -192 432 -192
WIRE -256 -128 -256 -176
WIRE -192 -128 -256 -128
WIRE -48 -128 -48 -160
WIRE -48 -128 -112 -128
WIRE 48 -128 48 -192
WIRE 48 -128 -48 -128
WIRE 512 -128 512 -192
WIRE 624 -128 624 -192
WIRE 624 -128 512 -128
WIRE 704 -128 624 -128
WIRE 864 -128 864 -176
WIRE 864 -128 784 -128
WIRE 864 -112 864 -128
WIRE 1024 -112 1024 -176
WIRE -400 -96 -400 -160
WIRE -256 -96 -256 -128
WIRE 144 -96 128 -96
WIRE 448 -96 432 -96
WIRE -144 0 -192 0
WIRE -32 0 -144 0
WIRE 144 0 -32 0
WIRE 496 0 432 0
WIRE 624 0 576 0
WIRE 864 0 624 0
WIRE 960 0 864 0
WIRE 1024 0 960 0
WIRE 624 32 624 0
WIRE 1024 32 1024 0
WIRE -192 48 -192 0
WIRE -32 48 -32 0
WIRE 864 48 864 0
WIRE 144 96 128 96
WIRE 512 96 432 96
WIRE -192 160 -192 128
WIRE -32 160 -32 112
WIRE 512 160 512 96
WIRE 624 160 624 96
WIRE 624 160 512 160
WIRE 704 160 624 160
WIRE 864 160 864 112
WIRE 864 160 784 160
WIRE 864 176 864 160
WIRE 1024 176 1024 112
WIRE -368 192 -416 192
WIRE -256 192 -368 192
WIRE -48 192 -256 192
WIRE 144 192 -48 192
WIRE 448 192 432 192
WIRE -416 240 -416 192
WIRE -256 240 -256 192
WIRE -48 240 -48 192
WIRE 144 288 48 288
WIRE 480 288 432 288
WIRE 608 288 560 288
WIRE 848 288 608 288
WIRE 960 288 848 288
WIRE 1008 288 960 288
WIRE 608 320 608 288
WIRE 1008 320 1008 288
WIRE -256 336 -256 304
WIRE -192 336 -256 336
WIRE -48 336 -48 320
WIRE -48 336 -112 336
WIRE 48 336 48 288
WIRE 48 336 -48 336
WIRE 848 336 848 288
WIRE -416 384 -416 320
WIRE -256 384 -256 336
WIRE 144 384 128 384
WIRE 496 384 432 384
WIRE 496 448 496 384
WIRE 608 448 608 384
WIRE 608 448 496 448
WIRE 688 448 608 448
WIRE 848 448 848 400
WIRE 848 448 768 448
WIRE 848 464 848 448
WIRE 1008 464 1008 400
WIRE 144 480 128 480
WIRE 448 480 432 480
WIRE 144 576 128 576
WIRE 480 576 432 576
WIRE 608 576 560 576
WIRE 848 576 608 576
WIRE 960 576 848 576
WIRE 1008 576 960 576
WIRE 608 608 608 576
WIRE 1008 608 1008 576
WIRE 848 624 848 576
WIRE 144 672 128 672
WIRE 496 672 432 672
WIRE 496 736 496 672
WIRE 608 736 608 672
WIRE 608 736 496 736
WIRE 688 736 608 736
WIRE 848 736 848 688
WIRE 848 736 768 736
WIRE 848 752 848 736
WIRE 1008 752 1008 688
WIRE 144 768 128 768
WIRE 464 768 432 768
WIRE 464 832 464 768
WIRE 512 832 464 832
WIRE 544 832 512 832
WIRE 656 832 624 832
WIRE 144 864 128 864
WIRE 144 960 128 960
WIRE 144 1056 128 1056
WIRE 144 1152 128 1152
WIRE 288 1232 288 1216
SYMBOL cap -272 240 R0
SYMATTR InstName C6
SYMATTR Value 1
SYMBOL res 688 -144 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R25
SYMATTR Value 1Meg
SYMBOL voltage -96 -464 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 480 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.82
SYMBOL res -208 32 R0
SYMATTR InstName R13
SYMATTR Value 15
SYMBOL cap -48 48 R0
SYMATTR InstName C7
SYMATTR Value 1
SYMBOL res 992 304 R0
SYMATTR InstName RLOAD3
SYMATTR Value 5
SYMBOL res 528 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R16
SYMATTR Value 100k
SYMBOL res -416 -256 R0
SYMATTR InstName R15
SYMATTR Value 5
SYMBOL cap 592 608 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 Rpar=1Meg
SYMATTR InstName C11
SYMATTR Value 10p
SYMBOL cap 608 32 R0
WINDOW 123 24 76 Left 2
SYMATTR Value2 Rpar=1.07Meg
SYMATTR InstName C9
SYMATTR Value 10p
SYMBOL res -96 -112 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R22
SYMATTR Value 1Meg
SYMBOL cap 832 336 R0
SYMATTR InstName C3
SYMATTR Value 47
SYMATTR SpiceLine Rser=1m
SYMBOL res 672 432 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 412k
SYMBOL res -96 352 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R11
SYMATTR Value 1Meg
SYMBOL cap -272 -240 R0
SYMATTR InstName C5
SYMATTR Value 1
SYMBOL ind 464 592 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 1.5
SYMBOL cap 592 320 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 Rpar=1Meg
SYMATTR InstName C10
SYMATTR Value 10p
SYMBOL res 688 144 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL res -432 224 R0
SYMATTR InstName R12
SYMATTR Value 5
SYMBOL ind 464 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 1.5
SYMBOL res -64 -256 R0
SYMATTR InstName R21
SYMATTR Value 649k
SYMBOL res 1008 16 R0
SYMATTR InstName RLOAD2
SYMATTR Value 5k
SYMBOL res -64 224 R0
SYMATTR InstName R2
SYMATTR Value 102K
SYMBOL res 1008 -272 R0
SYMATTR InstName RLOAD1
SYMATTR Value 5k
SYMBOL res 672 720 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 665k
SYMBOL res 992 592 R0
SYMATTR InstName RLOAD4
SYMATTR Value 5
SYMBOL cap 608 -256 R0
WINDOW 123 26 77 Left 2
SYMATTR Value2 Rpar=649k
SYMATTR InstName C8
SYMATTR Value 10p
SYMBOL cap 832 624 R0
SYMATTR InstName C4
SYMATTR Value 47
SYMATTR SpiceLine Rser=1m
SYMBOL cap 848 -240 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMATTR SpiceLine Rser=1m
SYMBOL cap 848 48 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMATTR SpiceLine Rser=1m
SYMBOL LT3380 288 288 R0
WINDOW 39 1632 164 Center 0
WINDOW 40 1526 183 Center 0
WINDOW 123 1489 144 Center 0
SYMATTR InstName U1
SYMBOL ind 480 -272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.82
FLAG -96 -352 0
FLAG -64 -480 vIN
FLAG -400 -96 0
FLAG 864 -112 0
FLAG 128 -96 vIN
FLAG 1024 176 0
FLAG 864 176 0
FLAG 448 -96 vIN
FLAG 1008 464 0
FLAG 848 464 0
FLAG 448 192 vIN
FLAG 1008 752 0
FLAG 848 752 0
FLAG 448 480 vIN
FLAG -256 -96 0
FLAG -416 384 0
FLAG -256 384 0
FLAG 128 96 vIN
FLAG -192 160 0
FLAG -32 160 0
FLAG 960 0 vBUCK2
FLAG 976 -288 vBUCK1
FLAG 656 832 vIN
FLAG -352 -288 L1_OUT
FLAG -144 0 L3_OUT
FLAG -368 192 L2_OUT
FLAG 960 288 vBUCK3
FLAG 960 576 vBUCK4
FLAG 128 672 vBUCK2
FLAG 128 768 vBUCK3
FLAG 128 864 vBUCK4
FLAG 128 960 L1_OUT
FLAG 128 1056 L2_OUT
FLAG 512 832 PG
FLAG 128 480 vIN
FLAG 128 384 vIN
FLAG 1024 -112 0
FLAG 128 576 vBUCK1
FLAG 288 1232 0
FLAG 128 1152 vIN
TEXT 184 1264 Left 2 !.tran 10m startup
TEXT 1400 -584 Left 2 ;Mode of Operation\n \n     Mode_x - 0 - Pulse-Skipping Mode\n                      1 - Burst Mode Operation\n                      2 - Forced Continuous Mode\n \n           *The switching converters operate in PSKIP mode during SoftStart (SS)\n              and mode transition happens after SS and Time delay, Td:\n                     For Bucks 1&2:\n                             > 2.7Vin: Td=500us\n                             > 5.5Vin: Td=3.2ms\n                     For Bucks 3&4:\n                             > 3.3Vin: Td=1.6ms\n                             > 5.5Vin: Td=3.6ms\n \nSwitching Frequency\n \n     FSW_x - 0 Switching Frequency 2.25MHz\n                    1 - Switching Frequency 1.125MHz\n \nPhase\n \n     PH_x - 0 - Clock Phase 1\n                 1 - Clock Phase 2\n \n \nVoltage Feedback Programming \n \n     with 12.5mV LSB Step Size (Use Dec Fomart)\n     E.g. 11111 (Bin) = 31 (Dec)\n \n     Decimal Input = FB Reference\n     0                     = 412.5mV\n     25                   = 725mV\n     31                   = 800mV
TEXT 2440 -560 Left 2 ;*Bx - Buckx\n*Lx - LDOx\n \nSoftware Enable\n \n     sEn_Bx/Lx - 0 - Disabled if EN Pin Is Low\n                          1 - Enabled\n \nKeep Alive\n \n     KA_Bx/Lx - 0 - Do Not Keep Enabled in Device Standby\n                        1 - Keep Enabled in Device Standby\n \nEnable Output Offset\n \n     EOO_Bx/Lx - 0 - Enable at Any Output Voltage\n                                1 - Enable Only if Output Voltage Is <300mV\n \nTurn Off Delay / Sequence Down Control\n \n     tOff_Bx/Lx - 0 - Disable Regulator at Falling PWR_ON\n                           1 - Disable Regulator at Falling PWR_ON + 100ms\n                           2 - Disable Regulator at Falling PWR_ON + 200ms\n                           3 - Disable Regulator at Falling PWR_ON + 300ms
TEXT 1400 -664 Left 4 ;Configurable Parameters