* Z:\home\khalils\Downloads\files\data\raw_asc\1920b4d03234_jfet_tolerance1.asc
* Generated by LTspice 26.0.1 for Windows.
J1 VCC N001 N002 2N5484X
V1 VCC 0 20
RS N002 0 {RS}
V2 N001 0 {VGS}
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.model 2N5484X NJF(Is=.25p Alpha=1e-4 Vk= 80 Vto={-1.8+x} Vtotc=-3m
+ Beta={0.45m*sqrt(4+x)} Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17)
.op
.param RS=1u VGS=0
.step param VGS -3 0 0.05
.step param x -0.6 .8 0.2
* * The original model from standard.jft, the library file in LTspice.\n*\n.model 2N5484X NJF(Is=.25p Alpha=1e-4 Vk= 80 Vto=-1.5 Vtotc=-3m\n+ Beta=3.0m Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17)
* I tried to model the production tolerance of Vto, Idss and g_fs.\nA function for BETA(Vto) is required which also fits for Idss and g_fs.\nThe result is a compromise of course, because it's impossible to fit\ntwo properties(Idss, g_fs) with only one parameter BETA.\nBETA is a parameter in the JFET model.\nReference: http://www.fairchildsemi.com/ds/2N/2N5484.pdf\n \nHint: \n1. Try to use a JFET with a "low" tolerance in Idss.\n2. Use a JFET with high Idss and set the Id with a resistor RS.\n This results in a reduction of the tolerance of Id.\n \nFor this design:\nThe tolerance of the current Id can be reduced from a factor of 5 to a factor \nof 2 if a high value of RS (10k Ohm) is used, but the current will be \nlowered to about 100uA with the 2N5484.\n \n \nPlot: d(Id(J1)) is the forward transconductance g_fs.
* Vto=-2.4 to -1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1336 680
WIRE -304 16 -304 -80
WIRE -304 208 -304 96
WIRE -304 240 -304 208
WIRE -272 -80 -304 -80
WIRE 176 80 176 32
WIRE 176 208 -304 208
WIRE 176 208 176 160
WIRE 272 32 176 32
WIRE 320 -80 -272 -80
WIRE 320 -32 320 -80
WIRE 320 96 320 64
WIRE 320 208 176 208
WIRE 320 208 320 176
FLAG -304 240 0
FLAG -272 -80 VCC
SYMBOL njf 272 -32 R0
SYMATTR InstName J1
SYMATTR Value 2N5484X
SYMBOL voltage -304 0 R0
SYMATTR InstName V1
SYMATTR Value 20
SYMBOL res 304 80 R0
SYMATTR InstName RS
SYMATTR Value {RS}
SYMBOL voltage 176 64 R0
SYMATTR InstName V2
SYMATTR Value {VGS}
TEXT -320 304 Left 0 !.model 2N5484X NJF(Is=.25p Alpha=1e-4 Vk= 80 Vto={-1.8+x} Vtotc=-3m\n+ Beta={0.45m*sqrt(4+x)} Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17)
TEXT -328 -200 Left 0 !.op
TEXT -328 -312 Left 0 !.param RS=1u VGS=0
TEXT -328 -272 Left 0 !.step param VGS -3 0 0.05\n.step param x -0.6 .8 0.2
TEXT -320 384 Left 0 ;* The original model from standard.jft, the library file in LTspice.\n*\n.model 2N5484X NJF(Is=.25p Alpha=1e-4 Vk= 80 Vto=-1.5 Vtotc=-3m\n+ Beta=3.0m Lambda=10m Betatce=-.5 Rd=10 Rs=10 Cgs=4p Cgd=4p Kf=3e-17)
TEXT -336 -912 Left 0 ;I tried to model the production tolerance of Vto, Idss and g_fs.\nA function for BETA(Vto) is required which also fits for Idss and g_fs.\nThe result is a compromise of course, because it's impossible to fit\ntwo properties(Idss, g_fs) with only one parameter BETA.\nBETA is a parameter in the JFET model.\nReference: http://www.fairchildsemi.com/ds/2N/2N5484.pdf\n \nHint: \n1. Try to use a JFET with a "low" tolerance in Idss.\n2. Use a JFET with high Idss and set the Id with a resistor RS.\n    This results in a reduction of the tolerance of Id.\n \nFor this design:\nThe tolerance of the current Id can be reduced from a factor of 5 to a factor \nof 2 if a high value of RS (10k Ohm) is used, but the current will be \nlowered to about 100uA with the 2N5484.\n \n \nPlot: d(Id(J1)) is the forward transconductance g_fs.
TEXT 48 -240 Left 0 ;Vto=-2.4 to -1