Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5681R.asc
* Generated by LTspice 26.0.1 for Windows.
CLOAD NC_01 0 10n
Vdac vDAC 0 PWL(0 0.625 10u 0.625 +1u 1.875)
V1 Vdd 0 5
I1 0 0 1m AC 1
XU1 vDAC Vdd 0 vOUT AD5681R Gain=2 ;pnba Vdac)Vdd)GND)Vout
Vdac1 NC_02 0 1.25 AC 1
.tran 200u
;dc I1 0 40m 1m
;ac oct 100 1u 1G
* Gain parameter can be 1 or 2
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5681R.asy)
.lib AD5681R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -240 -208 -240 -240
WIRE -240 -80 -240 -128
WIRE -240 -32 -240 -80
WIRE -528 112 -800 112
WIRE -368 112 -528 112
WIRE 192 112 0 112
WIRE 464 112 192 112
WIRE -800 144 -800 112
WIRE -944 256 -944 224
WIRE -800 256 -800 224
WIRE 272 256 272 224
WIRE 464 256 464 240
WIRE 464 256 272 256
WIRE 272 272 272 256
WIRE -240 288 -240 256
FLAG 192 112 vOUT
FLAG -800 256 0
FLAG -528 112 vDAC
FLAG -240 -240 0
FLAG -240 288 0
FLAG 272 272 0
FLAG -240 -80 Vdd
FLAG 464 160 0
FLAG -944 256 0
SYMBOL cap 256 160 R0
SYMATTR InstName CLOAD
SYMATTR Value 10n
SYMBOL voltage -800 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac
SYMATTR Value PWL(0 0.625 10u 0.625 +1u 1.875)
SYMBOL voltage -240 -112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL current 464 160 R0
WINDOW 123 24 108 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName I1
SYMATTR Value 1m
SYMBOL AD5681R -208 112 R0
SYMATTR InstName U1
SYMBOL voltage -944 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName Vdac1
SYMATTR Value 1.25
TEXT -160 344 Left 2 !.tran 200u
TEXT -160 392 Left 2 !;dc I1 0 40m 1m
TEXT -160 440 Left 2 !;ac oct 100 1u 1G
TEXT -160 288 Left 2 ;Gain parameter can be 1 or 2
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2386-18.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\LTC2386-18.asy)
V1 N003 0 PWL(0 0 100u 5)
V5 N002 0 5
V4 N001 0 4.096
V2 N007 0 PWL(0 5 100u 0)
C1 0 N005 10p
V3 N008 0 PULSE(0 1.8 100n .2n .2n 9.8n 100n)
XU1 N004 N002 0 N005 N001 N008 N006 LTC2386-18 ;pnba IN+)Vdd)GND)Vout)REFBUF)CNV)IN-
R1 N004 N003 10
R2 N006 N007 10
.tran 110u
.lib LTC2386-18.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 12540 5124
WIRE 10752 3008 10512 3008
WIRE 10752 3040 10752 3008
WIRE 10752 3152 10752 3120
WIRE 10512 3200 10512 3008
WIRE 10880 3248 10640 3248
WIRE 9856 3280 9824 3280
WIRE 9984 3280 9936 3280
WIRE 10144 3280 10064 3280
WIRE 10880 3280 10880 3248
WIRE 10144 3328 10144 3280
WIRE 10288 3328 10144 3328
WIRE 10720 3344 10640 3344
WIRE 10816 3344 10784 3344
WIRE 10288 3360 10144 3360
WIRE 10880 3392 10880 3360
WIRE 9856 3408 9824 3408
WIRE 9984 3408 9936 3408
WIRE 10144 3408 10144 3360
WIRE 10144 3408 10064 3408
WIRE 10768 3440 10640 3440
WIRE 10512 3520 10512 3488
WIRE 10768 3584 10768 3440
WIRE 10768 3744 10768 3664
SYMBOL voltage 10752 3024 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 4.096
SYMBOL voltage 10768 3568 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1.8 100n .2n .2n 9.8n 100n)
SYMBOL res 10080 3392 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL LTC2386-18 10544 3344 R0
SYMATTR InstName U1
SYMBOL res 10080 3264 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage 9952 3408 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 5 100u 0)
SYMBOL voltage 10880 3264 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL voltage 9952 3280 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 100u 5)
SYMBOL cap 10784 3328 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
FLAG 10768 3744 0
FLAG 10752 3152 0
FLAG 10880 3392 0
FLAG 10512 3520 0
FLAG 9824 3280 0
FLAG 9824 3408 0
FLAG 10816 3344 0
TEXT 10896 3656 Left 2 !.tran 110u
* Z:\home\khalils\Downloads\files\data\raw_asc\831f5b29c629_LLCTankOnly.asc
* Generated by LTspice 26.0.1 for Windows.
Lr N002 N001 {Lr}
R1 Vo 0 {R}
Lm Vo 0 {Lm}
V1 N001 0 AC 1
C1 Vo N002 {Cr}
.param Lr =2u
.param Cr=60n
.param Lm=100u
.step param R list 200 100 50
.ac dec 100 10k 1Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 80 -48 80
WIRE 240 80 144 80
WIRE 368 80 368 48
WIRE 368 80 304 80
WIRE 480 80 368 80
WIRE 368 128 368 80
WIRE 480 128 480 80
WIRE -48 144 -48 80
WIRE -48 256 -48 224
WIRE 368 256 368 208
WIRE 368 256 -48 256
WIRE 480 256 480 208
WIRE 480 256 368 256
WIRE 368 272 368 256
SYMBOL ind 352 112 R0
SYMATTR InstName Lm
SYMATTR Value {Lm}
SYMBOL voltage -48 128 R0
SYMATTR InstName V1
SYMATTR Value AC 1
SYMBOL cap 304 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {Cr}
SYMBOL res 464 112 R0
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL ind 160 64 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Lr
SYMATTR Value {Lr}
FLAG 368 48 Vo
FLAG 368 272 0
TEXT 48 -80 Left 2 !.param Lr =2u\n.param Cr=60n\n.param Lm=100u
TEXT 16 8 Left 2 !.step param R list 200 100 50
TEXT -82 296 Left 2 !.ac dec 100 10k 1Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG779.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG779.asy)
C1 D 0 36p
V3 +V 0 5
XU1 IN 0 D S2 +V 0 ADG779 ;pnba IN)S1)D)S2)Vdd)GND
V1 IN 0 PULSE(0 3 25u 1n 1n 20u)
R1 D 0 301
V2 S2 0 3
.tran 75u
.lib ADG779.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 0 -48 -48
WIRE -192 64 -400 64
WIRE -144 64 -192 64
WIRE -512 96 -512 48
WIRE -400 96 -400 64
WIRE 128 96 48 96
WIRE 256 96 128 96
WIRE -144 128 -288 128
WIRE 128 128 128 96
WIRE 256 128 256 96
WIRE -288 160 -288 128
WIRE -512 192 -512 176
WIRE -400 192 -400 176
WIRE -192 192 -288 192
WIRE -144 192 -192 192
WIRE 128 240 128 208
WIRE 256 240 256 192
WIRE -288 304 -288 192
WIRE -48 336 -48 304
WIRE -288 448 -288 384
SYMBOL voltage -512 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage -288 288 R0
WINDOW 3 24 102 Left 2
SYMATTR Value PULSE(0 3 25u 1n 1n 20u)
SYMATTR InstName V1
SYMBOL res 112 112 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG779 -48 144 R0
SYMATTR InstName U1
SYMBOL cap 240 128 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -400 80 R0
SYMATTR InstName V2
SYMATTR Value 3
FLAG 128 240 0
FLAG 256 240 0
FLAG -48 336 0
FLAG -288 448 0
FLAG -288 160 0
FLAG -400 192 0
FLAG -48 -48 +V
FLAG -512 192 0
FLAG -512 48 +V
FLAG -192 64 S2
FLAG -192 192 IN
FLAG 128 96 D
TEXT 144 320 Left 2 !.tran 75u
* Z:\home\khalils\Downloads\files\data\raw_asc\276d15f19544_qztst.asc
* Generated by LTspice 26.0.1 for Windows.
* Crystal model from easily measurable parameters
*serial freq
*difference between serial and // freq
* This example schematic is supplied for informational/educational purposes only.\nContributed by Dominique Szymik.
CY1 N002 OUT {Cs} Rser={Rs} Lser={Ls} Cpar={Cp}
R1 N002 N001 50
V1 N001 0 AC 2
R2 0 OUT 50
.ac lin 1001 3.95e6 4.05e6
.params fs=4e6
.params df=10e3
.params Rs=50
.params Cp=4e-12
.params Cs=2.0*cp*df/fs
.params Ls=1/(4*pi*pi*fs*fs*Cs)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3040 2464
WIRE 1712 2192 1632 2192
WIRE 1824 2192 1792 2192
WIRE 2000 2192 1888 2192
WIRE 2048 2192 2000 2192
WIRE 1632 2208 1632 2192
WIRE 2000 2208 2000 2192
WIRE 1632 2304 1632 2288
WIRE 2000 2320 2000 2288
SYMBOL res 1808 2176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL VOLTAGE 1632 2192 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 2
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL MISC\\XTAL 1824 2208 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName Y1
SYMATTR Value {Cs}
SYMATTR SpiceLine Rser={Rs} Lser={Ls} Cpar={Cp}
SYMBOL res 2016 2304 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 50
FLAG 2000 2320 0
FLAG 1632 2304 0
FLAG 2048 2192 OUT
TEXT 1672 2104 Left 2 !.ac lin 1001 3.95e6 4.05e6
TEXT 1184 2048 Left 2 ;Crystal model from easily measurable parameters
TEXT 1136 2112 Left 2 !*serial freq\n.params fs=4e6  \n*difference between serial and // freq \n.params df=10e3  \n.params Rs=50\n.params Cp=4e-12\n.params Cs=2.0*cp*df/fs\n.params Ls=1/(4*pi*pi*fs*fs*Cs)
TEXT 1592 2392 Top 1 ;This example schematic is supplied for informational/educational purposes only.\nContributed by Dominique Szymik.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1270A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1270A.asy)
Rload OUT 0 10
D1 N001 OUT MBRS360
C3 N004 0 1
XU1 N003 N002 0 N001 IN LT1270A ;pnba Vc)FB)GND)SW)Vin
R1 OUT N002 8.7K
C1 OUT 0 500
R3 N003 N004 1K
L1 IN N001 10
R2 N002 0 1K
V1 IN 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 15m startup
.lib LT1270A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1472
WIRE 1824 880 1616 880
WIRE 1872 880 1824 880
WIRE 1984 880 1952 880
WIRE 2032 880 1984 880
WIRE 2144 880 2096 880
WIRE 2256 880 2144 880
WIRE 2368 880 2256 880
WIRE 1616 896 1616 880
WIRE 2256 896 2256 880
WIRE 2368 896 2368 880
WIRE 1824 944 1824 880
WIRE 2144 960 2144 880
WIRE 1616 992 1616 976
WIRE 2256 992 2256 960
WIRE 2368 992 2368 976
WIRE 1984 1024 1984 880
WIRE 1984 1024 1952 1024
WIRE 2144 1088 2144 1040
WIRE 2144 1088 1952 1088
WIRE 2144 1104 2144 1088
WIRE 1968 1152 1952 1152
WIRE 2064 1152 2048 1152
WIRE 2064 1168 2064 1152
WIRE 2144 1200 2144 1184
WIRE 1824 1248 1824 1232
WIRE 2064 1248 2064 1232
SYMBOL RES 1952 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL RES 2128 1088 R0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL PowerProducts\\LT1270A 1824 1088 R0
SYMATTR InstName U1
SYMBOL schottky 2032 896 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMBOL IND 1856 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL CAP 2048 1168 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL RES 2128 944 R0
SYMATTR InstName R1
SYMATTR Value 8.7K
SYMBOL VOLTAGE 1616 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL polcap 2240 896 R0
SYMATTR InstName C1
SYMATTR Value 500
SYMBOL res 2352 880 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 2368 880 OUT
FLAG 2144 1200 0
FLAG 2256 992 0
FLAG 2368 992 0
FLAG 2064 1248 0
FLAG 1824 1248 0
FLAG 1616 992 0
FLAG 1616 880 IN
TEXT 2208 1248 Left 2 !.tran 15m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\f0c693a40ec9_ID_vs_UGS-7.asc
* Generated by LTspice 26.0.1 for Windows.
* ID_vs_UGS-5
* Enhancement mode P-channel MOSFET
V1 UDS 0 -10V
M1 UDS UGS 0 0 PMOSENH
V2 UGS 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V2 -2V 0V
.lib mosfet.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1292 680
WIRE -624 -176 -720 -176
WIRE -560 -176 -624 -176
WIRE -720 -128 -720 -176
WIRE -560 -80 -560 -176
WIRE -880 -48 -896 -48
WIRE -768 -48 -880 -48
WIRE -896 -32 -896 -48
WIRE -896 64 -896 48
WIRE -720 64 -720 -32
WIRE -560 64 -560 0
SYMBOL pmos -768 -128 R0
SYMATTR InstName M1
SYMATTR Value PMOSENH
SYMBOL voltage -896 -48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 53 Left 2
WINDOW 3 -97 181 Left 2
WINDOW 0 35 44 Left 2
SYMATTR Value ""
SYMATTR InstName V2
SYMBOL voltage -560 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 37 60 Left 2
WINDOW 0 36 55 Left 2
WINDOW 3 36 82 Left 2
SYMATTR InstName V1
SYMATTR Value -10V
FLAG -560 64 0
FLAG -896 64 0
FLAG -720 64 0
FLAG -880 -48 UGS
FLAG -624 -176 UDS
TEXT -904 96 Left 2 !.dc V2 -2V 0V
TEXT -896 -168 Left 2 ;ID_vs_UGS-5
TEXT -904 112 Left 2 !.lib mosfet.lib
TEXT -920 -208 Left 2 ;Enhancement mode P-channel MOSFET
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC694.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1086-5.asy)
* Library below included based on ModelFile attribute of instance XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC694.asy)
R4 OUT 0 100
XU1 0 N001 IN LT1086-5 ;pnba ADJ)OUT)IN
R3 N001 N006 10K
V1 IN 0 PWL(20u 0 25u 7.5) Rser=10m
C1 N001 0 100
R1 IN N005 51K
V3 N003 N004 PULSE(0 2 0 1u 1u 20m 40m 6) Rser=0.1
XU3 OUT N001 0 N005 N006 N003 _Reset N002 LTC694 ;pnba Vout)Vcc)GND)PFI)_PFO)WDI)_Reset)Vbatt
R2 N005 0 10K
V2 N002 0 3 Rser=10m
V4 N004 0 PULSE(0 2 0.4 1u 1u 20m 40m) Rser=0.1
.tran 0.7
.lib LT1083.lib
.lib LTC694.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1212 680
WIRE 1136 -144 -336 -144
WIRE -272 -64 -288 -64
WIRE -160 -64 -192 -64
WIRE -128 -64 -160 -64
WIRE 256 -64 224 -64
WIRE 368 -64 336 -64
WIRE 1136 0 1136 -144
WIRE -720 32 -1056 32
WIRE -640 32 -720 32
WIRE -336 32 -336 -144
WIRE -336 32 -384 32
WIRE -128 32 -336 32
WIRE 272 32 224 32
WIRE -1056 48 -1056 32
WIRE -336 48 -336 32
WIRE -720 128 -720 32
WIRE -336 128 -336 112
WIRE -128 128 -144 128
WIRE 400 128 224 128
WIRE 832 128 480 128
WIRE 944 128 912 128
WIRE -1056 144 -1056 128
WIRE -512 176 -512 128
WIRE -720 224 -720 208
WIRE -128 224 -720 224
WIRE 1136 224 1136 80
WIRE 1136 224 224 224
WIRE -720 240 -720 224
WIRE -720 336 -720 320
SYMBOL VOLTAGE 240 -64 R270
WINDOW 123 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value 3
SYMATTR SpiceLine Rser=10m
SYMBOL res 1120 -16 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res -736 112 R0
SYMATTR InstName R1
SYMATTR Value 51K
SYMBOL VOLTAGE -1056 32 R0
WINDOW 123 24 117 Left 2
SYMATTR Value PWL(20u 0 25u 7.5)
SYMATTR InstName V1
SYMATTR SpiceLine Rser=10m
SYMBOL LTC694 48 96 R0
SYMATTR InstName U3
SYMBOL res -176 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100
SYMBOL VOLTAGE 816 128 R270
WINDOW 123 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V4
SYMATTR Value PULSE(0 2 0.4 1u 1u 20m 40m)
SYMATTR SpiceLine Rser=0.1
SYMBOL res -736 224 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL cap -352 48 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMBOL PowerProducts\\LT1086-5 -512 32 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 384 128 R270
WINDOW 123 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 2 0 1u 1u 20m 40m 6)
SYMATTR SpiceLine Rser=0.1
FLAG -144 128 0
FLAG -160 -64 OUT
FLAG -1056 144 0
FLAG -336 128 0
FLAG -512 176 0
FLAG -1056 32 IN
FLAG 368 -64 0
FLAG -288 -64 0
FLAG -720 336 0
FLAG 272 32 _Reset
FLAG 944 128 0
TEXT 504 288 Left 2 !.tran 0.7
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3307A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3307A.asy)
R2 N003 0 100K
XU1 IN IN N002 N003 0 0 IN N001 0 LTC3307A ;pnba Vin)EN)SW)FB)AGND)PGND)Rt)Pgood)Mode/Sync
L1 N002 OUT 330n
V1 IN 0 5
R1 OUT N003 260K
Rload OUT 0 1
C3 OUT N003 2.2p
R4 OUT N001 500K
C1 OUT 0 22
.tran 1.5m startup
.lib LTC3307A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2652 1736
WIRE 1536 1264 1440 1264
WIRE 1712 1264 1536 1264
WIRE 1440 1280 1440 1264
WIRE 1712 1280 1712 1264
WIRE 1536 1344 1536 1264
WIRE 1552 1344 1536 1344
WIRE 1904 1344 1872 1344
WIRE 2016 1344 1984 1344
WIRE 1440 1376 1440 1360
WIRE 1536 1456 1536 1344
WIRE 1552 1456 1536 1456
WIRE 1904 1456 1872 1456
WIRE 2016 1456 2016 1344
WIRE 2016 1456 1984 1456
WIRE 2112 1456 2016 1456
WIRE 2192 1456 2112 1456
WIRE 2272 1456 2192 1456
WIRE 2016 1472 2016 1456
WIRE 2112 1472 2112 1456
WIRE 2192 1472 2192 1456
WIRE 2272 1472 2272 1456
WIRE 1552 1568 1536 1568
WIRE 2016 1568 2016 1552
WIRE 2016 1568 1872 1568
WIRE 2112 1568 2112 1536
WIRE 2112 1568 2016 1568
WIRE 2192 1568 2192 1536
WIRE 2272 1568 2272 1552
WIRE 2016 1584 2016 1568
WIRE 1648 1664 1648 1648
WIRE 1776 1664 1776 1648
WIRE 2016 1680 2016 1664
SYMBOL res 2000 1568 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL VOLTAGE 1440 1264 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 1888 1472 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 330n
SYMBOL res 2000 1328 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 500K
SYMBOL cap 2096 1472 R0
SYMATTR InstName C3
SYMATTR Value 2.2p
SYMBOL res 2256 1456 R0
SYMATTR InstName Rload
SYMATTR Value 1
SYMBOL LTC3307A 1712 1456 R0
SYMATTR InstName U1
SYMBOL RES 2000 1456 R0
SYMATTR InstName R1
SYMATTR Value 260K
SYMBOL cap 2176 1472 R0
SYMATTR InstName C1
SYMATTR Value 22
FLAG 1776 1664 0
FLAG 1648 1664 0
FLAG 1440 1376 0
FLAG 1536 1568 0
FLAG 2272 1568 0
FLAG 2016 1680 0
FLAG 2192 1568 0
FLAG 1440 1264 IN
FLAG 2272 1456 OUT
TEXT 2152 1680 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1e8d69bf0b40_Fig9_24_pmos.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1) and 1/d(Id(M1)) (to get ro)
VSD 0 N002 0
VSG 0 N001 1.15
M1 0 N001 N002 0 P_1u l=2u w=30u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSD 0 5 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1224 688
WIRE 320 96 320 80
WIRE 320 192 320 176
WIRE 400 192 320 192
WIRE 448 80 320 80
WIRE 448 112 448 80
WIRE 448 304 448 208
WIRE 672 80 448 80
WIRE 672 160 448 160
WIRE 672 160 672 80
WIRE 672 192 672 160
WIRE 672 304 448 304
WIRE 672 304 672 272
WIRE 848 80 672 80
WIRE 848 112 848 80
SYMBOL pmos4 400 112 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=2u w=30u
SYMATTR InstName M1
SYMATTR Value P_1u
SYMBOL voltage 672 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 54 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VSD
SYMATTR Value 0
SYMBOL voltage 320 80 R0
WINDOW 0 -93 54 Left 0
WINDOW 3 -93 82 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSG
SYMATTR Value 1.15
FLAG 848 112 0
TEXT 384 336 Left 0 !.dc VSD 0 5 1m
TEXT 384 360 Left 0 !.lib cmosedu_models.txt
TEXT 368 48 Left 0 ;Plot Id(M1) and 1/d(Id(M1)) (to get ro)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6992-2.asc
* Generated by LTspice 26.0.1 for Windows.
* 400Hz, 95% to 5% Duty Cycle\nSwept Pulse Width Modulated Output\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6992-2.asy)
V1 N002 0 3
R3 N002 N004 392K
R2 N004 0 1000K
R1 N003 0 487K
XU1 N001 0 N003 N004 N002 PWMout LTC6992-2 ;pnba MOD)GND)SET)DIV)V+)OUT
R4 PWMout 0 10K
V2 N001 0 PULSE(0 1 10m 50m 50m 5m 110m)
.tran 120m startup
.lib LTC6992-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 888 680
WIRE -208 96 -224 96
WIRE 96 96 -128 96
WIRE 608 96 320 96
WIRE 608 112 608 96
WIRE 96 176 80 176
WIRE 368 176 320 176
WIRE 496 176 368 176
WIRE 368 192 368 176
WIRE 496 192 496 176
WIRE 608 208 608 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 336 256 320 256
WIRE 336 288 336 256
WIRE 368 288 368 272
WIRE 368 288 336 288
WIRE 496 288 496 272
WIRE 368 304 368 288
WIRE 368 400 368 384
SYMBOL voltage 496 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 592 96 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 487K
SYMBOL SpecialFunctions\\LTC6992-2 208 176 R0
SYMATTR InstName U1
SYMBOL voltage -112 96 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 1 10m 50m 50m 5m 110m)
SYMATTR InstName V2
SYMBOL res 352 288 R0
SYMATTR InstName R2
SYMATTR Value 1000K
SYMBOL res 352 176 R0
SYMATTR InstName R3
SYMATTR Value 392K
FLAG -224 96 0
FLAG 496 288 0
FLAG 80 176 0
FLAG -16 256 0
FLAG 368 400 0
FLAG 608 208 0
FLAG 608 96 PWMout
TEXT 504 400 Left 2 !.tran 120m startup
TEXT 216 56 Bottom 2 ;400Hz, 95% to 5% Duty Cycle\nSwept Pulse Width Modulated Output\nStartup Modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3063.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3063.asy)
V1 IN 0 2.3
C1 N002 0 .01
R2 N001 0 59K
XU1 N002 N001 OUT MP_01 IN MP_02 IN 0 LT3063 ;pnba BYP)ADJ)OUT))IN))_SHDN)GND
C2 OUT 0 10 Rser=10m
R1 OUT N001 118K
Rload OUT 0 9
.tran .1 startup
.lib LT3063.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 96 0 96
WIRE 112 96 96 96
WIRE 512 96 368 96
WIRE 624 96 512 96
WIRE 720 96 624 96
WIRE 0 112 0 96
WIRE 512 112 512 96
WIRE 624 112 624 96
WIRE 720 112 720 96
WIRE 0 208 0 192
WIRE 96 208 96 96
WIRE 112 208 96 208
WIRE 512 208 512 192
WIRE 512 208 368 208
WIRE 624 208 624 176
WIRE 720 208 720 192
WIRE 512 224 512 208
WIRE 112 320 80 320
WIRE 384 320 368 320
WIRE 464 320 448 320
WIRE 512 320 512 304
SYMBOL res 496 208 R0
SYMATTR InstName R2
SYMATTR Value 59K
SYMBOL res 704 96 R0
SYMATTR InstName Rload
SYMATTR Value 9
SYMBOL res 496 96 R0
SYMATTR InstName R1
SYMATTR Value 118K
SYMBOL voltage 0 96 R0
SYMATTR InstName V1
SYMATTR Value 2.3
SYMBOL cap 384 336 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value .01
SYMBOL PowerProducts\\LT3063 240 208 R0
SYMATTR InstName U1
SYMBOL cap 608 112 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMATTR SpiceLine Rser=10m
FLAG 80 320 0
FLAG 0 208 0
FLAG 464 320 0
FLAG 512 320 0
FLAG 624 208 0
FLAG 720 208 0
FLAG 0 96 IN
FLAG 720 96 OUT
TEXT 592 320 Left 2 !.tran .1 startup