Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\0b9886147507_nonlinear_capacitance_poly.asc
* Generated by LTspice 26.0.1 for Windows.
* Simulation of nonlinear capacitors with POLY parameter\n \nPlot I(Cx)/1e6A to get pico as multiplier on the Y-axis.\nChange the X-axis to time*1e6V/1s or to V(vc)\n \nPOLY capacitor as used in some SPICE programs:\nCname +node -node POLY 0 c1 c2 c3 ...\n \nFormula: C(x) = c0 + c1*V + c2*V*V + c3*V*V*V + c4*V*V*V*V + ...\n \nExample: \nCvar 10 cathode poly 23.3836e-12 5.1258e-12 + 0.5214e-12 0.0240e-12 0.0004e-12\n \n \nQ = Integral(C(x)dx) \n \nQ= c0*x + c1/2*x**2 +c2/3*x**3 + c3/4*x**4 + c4/5*x**5\n \nQ = 23.3836e-12*x + 5.1258e-12*x*x/2 + 0.5214e-12*x*x*x/3 + 0.0240e-12*x*x*x*x/4 + 0.0004e-12*x*x*x*x*x/5\n \nIn the netlist:\nCvar +node -node Q = 23.3836e-12*x + 5.1258e-12*x*x/2 + 0.5214e-12*x*x*x/3 + 0.0240e-12*x*x*x*x/4 + 0.0004e-12*x*x*x*x*x/5
* Just for testing
V7 vc 0 PWL(0 -6 56u 50)
Cvar vc 0 Q = 23.3836e-12*x + 5.1258e-12*x*x/2 + 0.5214e-12*x*x*x/3 + 0.0240e-12*x*x*x*x/4 + 0.0004e-12*x*x*x*x*x/5
R1 cf 0 1
B1 0 cf I= 23.3836e-12 + 5.1258e-12*V(vc) + 0.5214e-12*V(vc)*V(vc) + 0.0240e-12*V(vc)*V(vc)*V(vc) + 0.0004e-12*V(vc)*V(vc)*V(vc)*V(vc)
.tran 0 11u 1u 0.01u
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1856 1860
WIRE 352 -176 64 -176
WIRE 64 -128 64 -176
WIRE 352 -112 352 -176
WIRE 64 0 64 -48
WIRE 352 0 352 -48
WIRE 352 96 64 96
WIRE 352 112 352 96
WIRE 64 176 64 96
WIRE 352 208 352 192
WIRE 64 272 64 256
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage 64 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value PWL(0 -6 56u 50)
SYMBOL cap 336 -112 R0
SYMATTR InstName Cvar
SYMATTR Value Q = 23.3836e-12*x + 5.1258e-12*x*x/2 + 0.5214e-12*x*x*x/3 + 0.0240e-12*x*x*x*x/4 + 0.0004e-12*x*x*x*x*x/5
SYMBOL bi 64 256 M180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName B1
SYMATTR Value I= 23.3836e-12 + 5.1258e-12*V(vc) + 0.5214e-12*V(vc)*V(vc) + 0.0240e-12*V(vc)*V(vc)*V(vc) + 0.0004e-12*V(vc)*V(vc)*V(vc)*V(vc)
FLAG 64 0 0
FLAG 352 0 0
FLAG 352 -176 vc
FLAG 352 208 0
FLAG 352 96 cf
FLAG 64 272 0
TEXT 80 -312 Left 0 !.tran 0 11u 1u 0.01u
TEXT 40 -968 Left 0 ;Simulation of nonlinear capacitors with POLY parameter\n \nPlot I(Cx)/1e6A  to get pico as multiplier on the Y-axis.\nChange the  X-axis to  time*1e6V/1s or to V(vc)\n \nPOLY capacitor as used in some SPICE programs:\nCname +node -node POLY 0 c1 c2 c3 ...\n \nFormula: C(x) = c0 + c1*V + c2*V*V + c3*V*V*V + c4*V*V*V*V + ...\n \nExample: \nCvar 10 cathode poly 23.3836e-12 5.1258e-12 + 0.5214e-12 0.0240e-12 0.0004e-12\n \n \nQ = Integral(C(x)dx)   \n \nQ= c0*x + c1/2*x**2 +c2/3*x**3 + c3/4*x**4 + c4/5*x**5\n \nQ = 23.3836e-12*x + 5.1258e-12*x*x/2 + 0.5214e-12*x*x*x/3 + 0.0240e-12*x*x*x*x/4 + 0.0004e-12*x*x*x*x*x/5\n \nIn the netlist:\nCvar +node -node Q = 23.3836e-12*x + 5.1258e-12*x*x/2 + 0.5214e-12*x*x*x/3 + 0.0240e-12*x*x*x*x/4 + 0.0004e-12*x*x*x*x*x/5
TEXT 80 -280 Left 0 !.options plotwinsize=0
TEXT 168 136 Left 0 ;Just for testing
* Z:\home\khalils\Downloads\files\data\raw_asc\ADAQ23875.asc
* Generated by LTspice 26.0.1 for Windows.
V4 N002 N001 SINE(0 1.8189 100k) AC 1
V2 N003 0 PULSE(0 1.8 66.6n .2n .2n 5n 66.6n)
V3 VS_N 0 -2
V1 PDB 0 6.5
V5 VDD 0 5
XU1 N001 N002 PDB PDB VS_N NC_01 NC_02 NC_03 VDD Vout N003 0 ADAQ23875 ;pnba IN-)IN+)VS+)PDB_AMP)VS-)REF_IN)VCMO)REFBUF)VDD)Vout)CNV)ADC_GND
* Simulation Settings:
.noise V(Vout) V1 dec 500 100 10G
;.tran 10u
;.ac dec 100 100 10G
* Power Supplies:
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\ADAQ23875.asy)
.lib ADAQ23875.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1496 700
WIRE -144 -480 -144 -560
WIRE 432 -480 432 -560
WIRE -640 -288 -816 -288
WIRE 656 -240 544 -240
WIRE 704 -240 656 -240
WIRE -816 -208 -816 -288
WIRE -640 -192 -640 -288
WIRE -560 -192 -640 -192
WIRE -1696 -112 -1696 -160
WIRE -1552 -112 -1552 -160
WIRE -1504 -112 -1504 -160
WIRE -1504 -112 -1552 -112
WIRE -1408 -112 -1408 -160
WIRE -560 -112 -640 -112
WIRE -1696 -80 -1696 -112
WIRE -1552 -80 -1552 -112
WIRE -1408 -80 -1408 -112
WIRE 704 -64 544 -64
WIRE -816 -16 -816 -128
WIRE -640 -16 -640 -112
WIRE -640 -16 -816 -16
WIRE 704 -16 704 -64
WIRE -1696 32 -1696 0
WIRE -1552 32 -1552 0
WIRE -1552 32 -1696 32
WIRE -1408 32 -1408 0
WIRE -1408 32 -1552 32
WIRE -1696 64 -1696 32
WIRE 704 144 704 64
WIRE -192 256 -192 176
WIRE -144 256 -144 176
WIRE 128 272 128 176
FLAG 704 144 0
FLAG -1696 64 0
FLAG -1696 -112 VS_N
FLAG -1408 -112 VDD
FLAG 656 -240 Vout
FLAG 432 -560 VDD
FLAG -144 -560 VS_P
FLAG -144 256 VS_N
FLAG 128 272 0
FLAG -192 256 PDB
FLAG -1504 -160 PDB
FLAG -1552 -160 VS_P
SYMBOL voltage -816 -112 R180
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value SINE(0 1.8189 100k)
SYMBOL voltage 704 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1.8 66.6n .2n .2n 5n 66.6n)
SYMBOL voltage -1696 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -2
SYMBOL voltage -1552 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 6.5
SYMBOL voltage -1408 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL ADAQ23875 -192 -176 R0
SYMATTR InstName U1
TEXT -1776 -376 Left 2 ;Simulation Settings:
TEXT -1760 -336 Left 2 !.noise V(Vout) V1 dec 500 100 10G
TEXT -1760 -272 Left 2 !;.tran 10u
TEXT -1760 -304 Left 2 !;.ac dec 100 100 10G
TEXT -1776 -216 Left 2 ;Power Supplies:
RECTANGLE Normal -1200 112 -1808 -400 2
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3011.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3011.asy)
XU1 OUT OUT N002 0 IN N001 MP_01 IN LT3011 ;pnba OUT)ADJ)Ct)GND)_SHDN)PWRGD))Vin
C1 OUT 0 1
C2 0 N002 1000p
V1 IN 0 PWL(0 0 10m 10)
Rload OUT 0 1K
R1 IN N001 1.6Meg
.tran 10m
.lib LT3010.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1172 680
WIRE -80 48 -336 48
WIRE 0 48 -80 48
WIRE 32 48 0 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -336 64 -336 48
WIRE 512 64 512 48
WIRE 416 80 416 48
WIRE -80 128 -80 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -336 160 -336 144
WIRE 416 160 416 144
WIRE 512 160 512 144
WIRE -80 240 -80 208
WIRE 32 240 -80 240
WIRE 336 240 320 240
WIRE 416 240 400 240
WIRE 176 304 176 288
SYMBOL res -96 112 R0
SYMATTR InstName R1
SYMATTR Value 1.6Meg
SYMBOL PowerProducts\\LT3011 176 144 R0
SYMATTR InstName U1
SYMBOL cap 400 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1000p
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL cap 400 80 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -336 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 10m 10)
FLAG -336 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 304 0
FLAG -336 48 IN
FLAG 512 48 OUT
FLAG 416 240 0
TEXT 512 248 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\0495c6f3b833_TP2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
R1 N001 N004 1.8Meg
V4 Vcc 0 10
R3 N003 N002 220k
XU1 0 N001 Vcc N005 N003 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N001 0 1.8Meg
V1 N004 0 Rser=100k
R4 N002 N001 220k
R5 0 N002 903.66
V3 N005 0 -10
.lib F:\Users\Ivan\Documents\LTspiceXVII\lib\LM324.lib
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1072 680
WIRE 496 -64 496 -80
WIRE 400 80 384 80
WIRE 496 80 496 16
WIRE 496 80 480 80
WIRE 512 80 496 80
WIRE 608 80 592 80
WIRE 224 96 224 80
WIRE 512 160 512 144
WIRE 240 176 176 176
WIRE 384 176 384 80
WIRE 384 176 320 176
WIRE 480 176 384 176
WIRE 608 192 608 80
WIRE 608 192 544 192
WIRE 480 208 464 208
WIRE 288 256 272 256
WIRE 368 256 352 256
WIRE 384 256 384 176
WIRE 384 256 368 256
WIRE 464 256 464 208
WIRE 176 272 176 176
WIRE 512 304 512 224
WIRE 176 448 176 352
WIRE 272 448 272 256
WIRE 272 448 176 448
WIRE 512 448 512 384
WIRE 512 448 272 448
WIRE 176 464 176 448
SYMBOL voltage 176 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 -127 97 Left 2
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR SpiceLine Rser=100k
SYMBOL voltage 224 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL res 496 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -53 53 VTop 2
SYMATTR InstName R4
SYMATTR Value 220k
SYMBOL voltage 512 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -10
SYMBOL res 608 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -53 53 VTop 2
SYMATTR InstName R3
SYMATTR Value 220k
SYMBOL res 480 -80 R0
SYMATTR InstName R5
SYMATTR Value 903.66
SYMBOL res 384 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.8Meg
SYMBOL OpAmps\\UniversalOpAmp 512 192 R0
SYMATTR InstName U1
SYMBOL res 336 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1.8Meg
FLAG 224 96 0
FLAG 224 0 Vcc
FLAG 512 144 Vcc
FLAG 176 464 0
FLAG 496 -80 0
FLAG 464 256 0
TEXT 64 536 Left 2 !.lib F:\\Users\\Ivan\\Documents\\LTspiceXVII\\lib\\LM324.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\862af9ffe82f_TS3_butter.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N001 0 N005 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
V1 N007 0 AC 1
XU2 0 N006 N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
XU3 N004 0 N003 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R1 N001 N007 {R1}
R2 N005 N001 {R2}
C1 N005 N001 {C}
R3 N002 N001 {R3}
R4 N002 N004 {R4}
R5 N004 N003 {R4}
C2 N003 N006 {C}
R6 N006 N005 {R3}
.ac dec 100 0.1 1MEG
.lib opamp.sub
.param R1=1 Q=1/sqrt(2) R2=Q*R3 R3=R1 f0=10k w0=2*pi*f0 C=1/(R3*w0) R4=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 -160 -160 -160
WIRE 672 -160 176 -160
WIRE 368 -96 320 -96
WIRE 480 -96 448 -96
WIRE 496 -96 480 -96
WIRE 672 -96 672 -160
WIRE 672 -96 576 -96
WIRE -160 -64 -160 -160
WIRE -128 -64 -160 -64
WIRE -16 -64 -48 -64
WIRE 480 0 480 -96
WIRE 480 0 448 0
WIRE 208 16 176 16
WIRE 320 16 320 -96
WIRE 320 16 272 16
WIRE 384 16 320 16
WIRE 480 32 448 32
WIRE -160 48 -160 -64
WIRE -128 48 -160 48
WIRE -16 48 -16 -64
WIRE -16 48 -64 48
WIRE 480 96 480 32
WIRE -256 144 -320 144
WIRE -160 144 -160 48
WIRE -160 144 -176 144
WIRE -128 144 -160 144
WIRE -16 160 -16 48
WIRE -16 160 -64 160
WIRE 32 160 -16 160
WIRE 176 160 176 16
WIRE 176 160 112 160
WIRE 208 160 176 160
WIRE -128 176 -160 176
WIRE 672 176 672 -96
WIRE 672 176 272 176
WIRE -320 192 -320 144
WIRE 208 192 176 192
WIRE -160 240 -160 176
WIRE 176 256 176 192
WIRE -320 320 -320 272
FLAG -320 320 0
FLAG -160 240 0
FLAG 176 256 0
FLAG 480 96 0
SYMBOL OpAmps\\opamp -96 96 R0
SYMATTR InstName U1
SYMBOL voltage -320 176 R0
WINDOW 123 17 102 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL OpAmps\\opamp 240 240 M180
SYMATTR InstName U2
SYMBOL OpAmps\\opamp 416 -48 M0
SYMATTR InstName U3
SYMBOL res -160 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL res -32 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL cap -64 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {C}
SYMBOL res 192 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {R3}
SYMBOL res 592 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {R4}
SYMBOL res 464 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value {R4}
SYMBOL cap 272 0 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {C}
SYMBOL res 128 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value {R3}
TEXT -352 392 Left 2 !.ac dec 100 0.1 1MEG
TEXT -352 416 Left 2 !.lib opamp.sub
TEXT -352 440 Left 2 !.param R1=1 Q=1/sqrt(2) R2=Q*R3 R3=R1 f0=10k w0=2*pi*f0 C=1/(R3*w0) R4=1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1085.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1085.asy)
C1 OUT 0 10
R1 OUT N001 121
XU1 N001 OUT IN LT1085 ;pnba ADJ)OUT)IN
R2 N001 0 365
V1 IN 0 PWL(0 0 1 10) Rser=0.1
Rload OUT 0 10
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1328 896
WIRE 1856 896 1808 896
WIRE 1952 896 1856 896
WIRE 2064 896 1952 896
WIRE 1328 912 1328 896
WIRE 1856 912 1856 896
WIRE 1952 912 1952 896
WIRE 2064 912 2064 896
WIRE 1328 1008 1328 992
WIRE 1952 1008 1952 976
WIRE 2064 1008 2064 992
WIRE 1680 1024 1680 992
WIRE 1856 1024 1856 992
WIRE 1856 1024 1680 1024
WIRE 1856 1040 1856 1024
WIRE 1856 1136 1856 1120
SYMBOL RES 1840 1024 R0
SYMATTR InstName R2
SYMATTR Value 365
SYMBOL PowerProducts\\LT1085 1680 896 R0
SYMATTR InstName U1
SYMBOL RES 1840 896 R0
SYMATTR InstName R1
SYMATTR Value 121
SYMBOL RES 2048 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL VOLTAGE 1328 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
SYMBOL cap 1936 912 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 2064 896 OUT
FLAG 1856 1136 0
FLAG 2064 1008 0
FLAG 1328 1008 0
FLAG 1952 1008 0
FLAG 1328 896 IN
TEXT 1968 1088 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\030d15d29b17_lab5_task2.asc
* Generated by LTspice 26.0.1 for Windows.
Rc1 P001 0 1k
Vcc1 N001 0 5
Vi1 N002 0 PULSE(5 0 0 50n 50n 500u 1m)
Rb1 N003 N002 4.7k
M1 P001 N003 N001 N001 BSS84
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 5m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 680
WIRE 416 -144 416 -176
WIRE 416 64 416 -64
WIRE 32 80 -16 80
WIRE 240 80 112 80
WIRE 368 80 320 80
WIRE 416 272 416 240
SYMBOL voltage 416 -48 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 24 68 Left 2
SYMATTR InstName Vcc1
SYMATTR Value 5
SYMBOL res 400 144 R0
SYMATTR InstName Rc1
SYMATTR Value 1k
SYMBOL pmos 368 160 M180
SYMATTR InstName M1
SYMATTR Value BSS84
SYMBOL res 336 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rb1
SYMATTR Value 4.7k
SYMBOL voltage 128 80 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vi1
SYMATTR Value PULSE(5 0 0 50n 50n 500u 1m)
FLAG 416 272 0
FLAG -16 80 0
FLAG 416 -176 0
TEXT -72 376 Left 2 !.tran 0 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\100ec9b23e07_Pre-charge_FET.asc
* Generated by LTspice 26.0.1 for Windows.
* Battery simulation\nInternal resistance: ~100mOhm per cell, *10/2 (because 10S2P) = 500mOhm
* Pre-charge FET
* Analysis Setup\n1000ms simulation in 1ms increments
* 15V Linear regulator
* System Load
* Operating point:\nCurrent draw (battery engaged): 15uA\nCurrent draw (battery not engaged): 0
V1 CELL_10_POS 0 30 Rser=500m
R4 PRECHG_FET_EN 0 1Meg
R_SYSTEM CELL_10_POS SYSTEM_GND 10
V2 15VO 0 15
M2 Vd PRECHG_FET_EN 0 0 BSS123
V3 PRECHG_FET_EN 0 PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
R5 SYSTEM_GND Vd 1k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1m 150m uic
.step param R5 list 100 1k 2k 5k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5144 2508
WIRE 352 416 112 416
WIRE 112 560 112 416
WIRE 1216 656 1072 656
WIRE 112 720 112 640
WIRE 224 720 112 720
WIRE 224 736 224 720
WIRE 1072 768 1072 656
WIRE 112 800 112 720
WIRE 352 800 112 800
WIRE 3024 928 2896 928
WIRE 1072 1024 1072 848
WIRE 1216 1024 1072 1024
WIRE 3024 1104 3024 928
WIRE 464 1216 176 1216
WIRE 1488 1232 1296 1232
WIRE 1664 1232 1488 1232
WIRE 1488 1312 1488 1232
WIRE 176 1360 176 1216
WIRE 3024 1376 3024 1184
WIRE 3024 1376 2896 1376
WIRE 1664 1472 1664 1232
WIRE 1488 1520 1488 1392
WIRE 1488 1520 1296 1520
WIRE 1648 1520 1488 1520
WIRE 1792 1520 1744 1520
WIRE 1872 1520 1792 1520
WIRE 2144 1520 1952 1520
WIRE 176 1584 176 1440
WIRE 464 1584 176 1584
DATAFLAG 1488 1232 "$"
RECTANGLE Normal 60 1088 996 1644 2
RECTANGLE Normal 1068 1084 2372 1648 2
RECTANGLE Normal 40 872 564 1064 2
RECTANGLE Normal 32 300 592 832 2
RECTANGLE Normal 2580 824 3200 1448 2
SYMBOL nmos 1744 1472 R90
SYMATTR InstName M2
SYMATTR Value BSS123
SYMBOL res 1968 1504 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL res 3008 1088 R0
SYMATTR InstName R_SYSTEM
SYMATTR Value 10
SYMBOL voltage 112 544 R0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL battery 176 1344 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMATTR SpiceLine Rser=500m
SYMBOL res 1472 1296 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL voltage 1072 752 R0
SYMATTR InstName V3
SYMATTR Value PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
FLAG 1296 1520 BMS_GND
FLAG 1296 1232 PRECHG_FET_EN
FLAG 2144 1520 SYSTEM_GND
FLAG 464 1216 CELL_10_POS
FLAG 464 1584 BMS_GND
FLAG 352 416 15VO
FLAG 352 800 BMS_GND
FLAG 1216 656 PRECHG_FET_EN
FLAG 1216 1024 BMS_GND
FLAG 2896 1376 SYSTEM_GND
FLAG 2896 928 CELL_10_POS
FLAG 224 736 0
FLAG 1792 1520 Vd
TEXT 88 968 Left 2 !.tran 1m 150m uic
TEXT 88 1128 Left 2 ;Battery simulation\nInternal resistance: ~100mOhm per cell, *10/2 (because 10S2P) = 500mOhm
TEXT 1120 1120 Left 2 ;Pre-charge FET
TEXT 80 888 Left 2 ;Analysis Setup\n1000ms simulation in 1ms increments
TEXT 72 336 Left 2 ;15V Linear regulator
TEXT 2616 848 Left 2 ;System Load
TEXT 1864 1392 Left 2 !.step param R5 list 100 1k 2k 5k
TEXT 1800 600 Left 2 ;Operating point:\nCurrent draw (battery engaged): 15uA\nCurrent draw (battery not engaged): 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP198.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP198.asy)
C2 OUT 0 1
Rload OUT 0 100
V1 IN 0 1.65
XU1 IN IN OUT 0 ADP198 ;pnba Vin)En)Vout)GND
.tran 10m startup
.lib ADP198.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 128 96 16 96
WIRE 160 96 128 96
WIRE 448 96 352 96
WIRE 528 96 448 96
WIRE 16 112 16 96
WIRE 448 112 448 96
WIRE 528 112 528 96
WIRE 16 208 16 192
WIRE 448 208 448 176
WIRE 528 208 528 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 368 224 352 224
SYMBOL voltage 16 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.65
SYMBOL cap 432 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL ADP198 256 144 R0
SYMATTR InstName U1
SYMBOL res 512 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
FLAG 16 208 0
FLAG 368 224 0
FLAG 448 208 0
FLAG 528 208 0
FLAG 528 96 OUT
FLAG 16 96 IN
TEXT 376 288 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8552.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8552.asy)
Rload OUT 0 10K
Vin IN 0 SINE(0 1 10K)
V2 -V 0 -5
XU1 IN N001 +V -V OUT AD8552 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 5
R2 OUT N001 10K
R1 N001 0 10K
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 240 -992 224 -992
WIRE 336 -992 320 -992
WIRE 352 -992 336 -992
WIRE 448 -992 432 -992
WIRE -16 -896 -16 -912
WIRE 80 -896 80 -912
WIRE 336 -880 336 -992
WIRE 352 -880 336 -880
WIRE 448 -864 448 -992
WIRE 448 -864 416 -864
WIRE 560 -864 448 -864
WIRE 352 -848 240 -848
WIRE 560 -848 560 -864
WIRE 240 -832 240 -848
WIRE -16 -800 -16 -816
WIRE 80 -800 80 -816
WIRE 560 -752 560 -768
WIRE 240 -736 240 -752
SYMBOL res 336 -1008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -16 -912 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 448 -1008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 544 -864 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 240 -848 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL Opamps\\AD8552 384 -928 R0
SYMATTR InstName U1
SYMBOL voltage 80 -912 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
FLAG -16 -912 +V
FLAG -16 -800 0
FLAG 240 -736 0
FLAG 560 -864 OUT
FLAG 240 -848 IN
FLAG 384 -896 +V
FLAG 80 -912 -V
FLAG 384 -832 -V
FLAG 224 -992 0
FLAG 560 -752 0
FLAG 80 -800 0
TEXT 496 -712 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\4f7f7a4bc83a_part3_a_vgs_sweep.asc
* Generated by LTspice 26.0.1 for Windows.
VGS gate 0 7
VDS drain 0 8
M1 drain gate 0 0 NMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model nmos NMOS (kp=100u, vt0=0.5, l={x}, w=.36u)
.dc VGS 0 10 0.01
.step param X list .09u .13u .2u .3u .6u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 48 96 48
WIRE 240 48 160 48
WIRE 96 112 96 48
WIRE 240 144 240 48
WIRE -64 192 -96 192
WIRE 48 192 -64 192
WIRE -96 208 -96 192
WIRE -96 336 -96 288
WIRE 96 336 96 208
WIRE 96 336 -96 336
WIRE 176 336 96 336
WIRE 240 336 240 224
WIRE 240 336 176 336
FLAG 96 336 0
FLAG -64 192 gate
FLAG 160 48 drain
FLAG 176 336 source
SYMBOL voltage -96 192 R0
SYMATTR InstName VGS
SYMATTR Value 7
SYMBOL voltage 240 128 R0
SYMATTR InstName VDS
SYMATTR Value 8
SYMBOL nmos 48 112 R0
SYMATTR InstName M1
TEXT -104 376 Left 2 !.model nmos NMOS (kp=100u, vt0=0.5, l={x}, w=.36u)
TEXT -104 408 Left 2 !.dc VGS 0 10 0.01
TEXT -104 440 Left 2 !.step param X list .09u .13u .2u .3u .6u
* Z:\home\khalils\Downloads\files\data\raw_asc\0921da894dcd_L2-CarBreak.asc
* Generated by LTspice 26.0.1 for Windows.
A1 0 driver 0 N001 0 0 out 0 OR Vhigh=5 Vlow=0
A2 0 radar 0 camera 0 0 N001 0 AND Vhigh=5 Vlow=0
V2 radar 0 PULSE(0 5 2 0.001 0.001 2 4 2)
V1 driver 0 PULSE(0 5 4 0.001 0.001 4 8 1)
V3 camera 0 PULSE(0 5 1 0.001 0.001 1 2 4)
.tran 0 8 0 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -32 -48 -32
WIRE 160 160 160 -32
WIRE 240 160 160 160
WIRE 304 160 288 160
WIRE 400 160 304 160
WIRE 240 192 144 192
WIRE -32 304 -112 304
WIRE 144 304 144 192
WIRE 144 304 32 304
WIRE -32 336 -112 336
SYMBOL voltage -736 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 2 0.001 0.001 2 4 2)
SYMBOL Digital\\or 272 112 R0
WINDOW 39 -74 130 Left 2
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR InstName A1
SYMBOL voltage -736 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 1 0.001 0.001 1 2 4)
SYMBOL voltage -736 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 4 0.001 0.001 4 8 1)
SYMBOL Digital\\and 0 256 R0
WINDOW 39 -90 149 Left 2
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR InstName A2
FLAG 400 160 out
FLAG -736 -128 driver
FLAG -736 48 radar
FLAG -736 224 camera
FLAG -736 -48 0
FLAG -736 128 0
FLAG -736 304 0
FLAG -48 -32 driver
FLAG -112 304 radar
FLAG -112 336 camera
TEXT -768 400 Left 2 !.tran 0 8 0 0.01
* Z:\tmp\asc_dec_bjh7r6w2\1a61542db3d3_Zener_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N002 N001 1K
R1 N002 0 100k
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 944 680
WIRE 336 144 288 144
WIRE 464 144 416 144
WIRE 544 144 464 144
WIRE 704 144 544 144
WIRE 864 144 704 144
WIRE 464 176 464 144
WIRE 544 176 544 144
WIRE 704 176 704 144
WIRE 864 192 864 144
WIRE 464 272 464 240
WIRE 544 272 544 256
WIRE 544 272 464 272
WIRE 704 272 704 240
WIRE 704 272 544 272
WIRE 704 288 704 272
WIRE 864 336 864 272
SYMBOL res 432 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 848 176 R0
SYMATTR InstName R1
SYMATTR Value 100k
FLAG 704 288 0
FLAG 864 336 0