* Z:\home\khalils\Downloads\files\data\raw_asc\LT7171-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Please read the following notes carefully since all the LT7171-1 features and programmability choices are not modelled\n \n(1) PMBus communication and memory address related functions and pins are not modeled, \nincluding SDA, SCL, WP. The pins shown in the symbol is only for representation \n(2) Changes to parameter values while the simulation is running will not take effect unless the\nsimulation is stopped and restarted. This is different from the way the part operates which will\nrespond to the changes while running. \n(3) Resistor Configuration pins are not modelled (VOUT_CFG,ASEL, PWM_CFG). The pins shown in the symbol is only for representation \n(4) Only default fault responses are modelled. The part offers diffeent fault responses choices\n(5) Initialization time is not modelled.\n \nThe following parameters can be defined by right-clicking on the LT7171-1 symbol.\nThe nomenclature used here may differ from the one in the data sheet. If any value of these parameters is\nset beyond the scope described in the data sheet, the resulting simulation will not be meaningful.:\n \nFrequency_switch -- in Hz, sets switching frequency\n \nVout_range -- sets maximum output range, 0 for 1.375V, 1 for 2.75V, 2 for 5.5V\n \nVout_command -- in volt, sets output voltage\n \nTon_delay & Ton_rise -- in sec, set ON delay and soft-start time\nToff_delay & Toff_fall -- in sec, set OFF delay and soft-off time \n \nIlim_range -- sets current limit options:\n 0 positive valley current limit of 4.5A per phase, negative valley current limit of -3A\n 1 positive valley current limit of 6.5A per phase, negative valley current limit of -3.8A\n 2 positive valley current limit of 7.8A per phase, negative valley current limit of -4.7A\n 3 positive valley current limit of 10.7A per phase, negative valley current limit of -6A \n \n \n \nGMEA_control--Sets Error Amp parameters, N=0 to 31\n GmEA = 0.15mS*(n+1)/(2^VOUT_RANGE) (relative to VSENSE inputs)\n \n \nRITH--in ohm, programmable internal compensation\n \nCITH--in Farad, programmable internal compensation\n \n \nMFR_PWM_PHASE-- in degree, sets the SW0 phase delay in 15-degree increments with respect to the SYNC frequency if present.\n \n \n \nVout_UV_Fault_Limit and Vout_OV_Fault_Limit --- in volt, set the undervoltage and overvoltage fault limit.\nVout_UV_Warn_Limit and Vout_OV_Warn_Limit-- in volt, set the undervoltage and overvoltage warning limit.\n \n \nMFR_DISCHARGE_THRESHOLD--Output voltage threshold to determine that the output has decayed sufficiently to enable the channel\n \nMFR_RETRY_DELAY -- sets the time in milliseconds to retry the LT7171-1 after shuts down due to a fault\n \nEN_SYNC_OUT ---1 Output SYNC Pulses, 0 SYNC works as input.\n \nTON_MAX_FAULT_LIMIT-- Determines how long the LT7171-1 can attempt to soft-start the output without reaching the output undervoltage fault limit.\n \nTo simulate Polyphase load-sharing operation \n \nTie RUN, VIN, SHARE_CLK, _FAULT, _ALERT, PGOOD, ITH pins of all the parts together\nset EN_SYNC_OUT = 1 for only one part and set EN_SYNC_OUT = 0 for all other parts\nThe parameters set in both the part should be identical other than EN_SYNC_OUT
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT7171-1.asy)
XU1 IN SW0 0 SW1 BOOST0 BOOST1 DRVCC INTVCC EXTVCC VDD18 _ALERT 0 OUT 0 RUN PGOOD INTVCC N002 0 0 _FAULT N001 NC_01 0 LT7171-1 FREQUENCY_SWITCH=750k VOUT_RANGE=0 VOUT_COMMAND=0.85 VIN_ON= 1.4 VIN_OFF=1.35 TON_DELAY=.01m TON_RISE=.5m TOFF_DELAY=.2m TOFF_FALL=.3m ILIM_RANGE=0 EN_SYNC_OUT=1 GMEA_CONTROL=10 RITH=7k CITH=320p MFR_PWM_PHASE=180 VOUT_UV_FAULT_LIMIT=0.6 VOUT_OV_FAULT_LIMIT=1.1 VOUT_UV_WARN_LIMIT=0.7 VOUT_OV_WARN_LIMIT=1 MFR_DISCHARGE_THRESHOLD=0.2 MFR_RETRY_DELAY=10m TON_MAX_FAULT_LIMIT=5m ;pnba PVIN)SW0)SGND)SW1)BOOST0)BOOST1)DRVCC)INTVCC)EXTVCC)VDD18)_ALERT)PGND)VSENSEP)VSENSEN)RUN)PGOOD)ITH)SYNC)PWM_CFG)VOUT_CFG)_FAULT)SHARE_CLK)ASEL)WP
R8 OUT 0 0.283
L3 SW1 OUT 330n Rser=2.5m
R5 EXTVCC _ALERT 100k
R1 N001 EXTVCC 11.4k
V2 RUN 0 PWL(500u 0 500.001u 5 2500u 5 2500.001u 0)
C14 0 INTVCC 10
C9 0 DRVCC 10
C10 OUT 0 100 x2 Rser=5m
V1 IN 0 12
C11 OUT 0 100 x2 Rser=2m
L2 SW0 OUT 330n Rser=2.5m
C13 BOOST0 SW0 0.1
C12 BOOST1 SW1 0.1
R7 EXTVCC _FAULT 6.8k
C5 0 VDD18 4.7
R6 EXTVCC PGOOD 100k
V5 EXTVCC 0 5
.tran 2m startup
.lib LT7171-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4588 1188
WIRE 32 -1392 -448 -1392
WIRE 512 -1392 448 -1392
WIRE -448 -1376 -448 -1392
WIRE 512 -1376 512 -1392
WIRE -16 -1296 -272 -1296
WIRE 32 -1296 -16 -1296
WIRE 480 -1296 448 -1296
WIRE 512 -1296 512 -1312
WIRE 512 -1296 480 -1296
WIRE 576 -1296 512 -1296
WIRE 704 -1296 656 -1296
WIRE 752 -1296 704 -1296
WIRE 848 -1296 752 -1296
WIRE 912 -1296 848 -1296
WIRE 1040 -1296 912 -1296
WIRE -448 -1280 -448 -1296
WIRE -272 -1280 -272 -1296
WIRE 752 -1280 752 -1296
WIRE 848 -1280 848 -1296
WIRE -80 -1200 -128 -1200
WIRE 32 -1200 0 -1200
WIRE 512 -1200 448 -1200
WIRE 512 -1184 512 -1200
WIRE 752 -1184 752 -1216
WIRE 848 -1184 848 -1216
WIRE -272 -1168 -272 -1200
WIRE 480 -1104 448 -1104
WIRE 512 -1104 512 -1120
WIRE 512 -1104 480 -1104
WIRE 576 -1104 512 -1104
WIRE 704 -1104 704 -1296
WIRE 704 -1104 656 -1104
WIRE 32 -1008 -32 -1008
WIRE 1040 -1008 1040 -1296
WIRE 1040 -1008 448 -1008
WIRE -256 -912 -288 -912
WIRE -128 -912 -128 -1200
WIRE -128 -912 -176 -912
WIRE -32 -912 -128 -912
WIRE 32 -912 -32 -912
WIRE 1040 -912 1040 -928
WIRE 1040 -912 448 -912
WIRE 1040 -896 1040 -912
WIRE 32 -816 -16 -816
WIRE 528 -816 448 -816
WIRE 608 -816 528 -816
WIRE 784 -816 688 -816
WIRE 32 -720 -16 -720
WIRE 528 -720 448 -720
WIRE 608 -720 528 -720
WIRE 784 -720 784 -816
WIRE 784 -720 688 -720
WIRE -16 -672 -16 -720
WIRE -16 -672 -64 -672
WIRE -16 -624 -16 -672
WIRE 32 -624 -16 -624
WIRE 528 -624 448 -624
WIRE 608 -624 528 -624
WIRE 768 -624 688 -624
WIRE 784 -624 784 -720
WIRE 784 -624 768 -624
WIRE -224 -528 -240 -528
WIRE -112 -528 -160 -528
WIRE -48 -528 -112 -528
WIRE 32 -528 -48 -528
WIRE 528 -528 448 -528
WIRE 640 -528 528 -528
WIRE 720 -528 704 -528
WIRE -48 -432 -48 -528
WIRE 32 -432 -48 -432
WIRE 528 -432 448 -432
WIRE 640 -432 528 -432
WIRE 720 -432 704 -432
WIRE 160 -336 160 -352
WIRE 320 -336 320 -352
SYMBOL cap 704 -512 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C9
SYMATTR Value 10
SYMBOL voltage -448 -1392 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 704 -832 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 6.8k
SYMBOL res 704 -640 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100k
SYMBOL ind 560 -1280 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 330n
SYMATTR SpiceLine Rser=2.5m
SYMBOL cap 704 -416 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C5
SYMATTR Value 4.7
SYMBOL res 1024 -1024 R0
SYMATTR InstName R8
SYMATTR Value 0.283
SYMBOL cap 496 -1376 R0
SYMATTR InstName C13
SYMATTR Value 0.1
SYMBOL voltage -272 -1296 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(500u 0 500.001u 5 2500u 5 2500.001u 0)
SYMBOL voltage -160 -912 M270
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL cap 496 -1184 R0
SYMATTR InstName C12
SYMATTR Value 0.1
SYMBOL res 704 -736 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 100k
SYMBOL cap 736 -1280 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 x2
SYMATTR InstName C11
SYMATTR Value 100
SYMATTR SpiceLine Rser=2m
SYMBOL cap -224 -544 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C14
SYMATTR Value 10
SYMBOL ind 560 -1088 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 330n
SYMATTR SpiceLine Rser=2.5m
SYMBOL LT7171-1 240 -1104 R0
SYMATTR InstName U1
SYMBOL res 16 -1216 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 11.4k
SYMBOL cap 832 -1280 R0
WINDOW 123 24 77 Left 2
SYMATTR Value2 x2
SYMATTR InstName C10
SYMATTR Value 100
SYMATTR SpiceLine Rser=5m
FLAG 320 -336 0
FLAG 160 -336 0
FLAG -448 -1392 IN
FLAG -448 -1280 0
FLAG -16 -1296 RUN
FLAG 720 -432 0
FLAG 528 -432 VDD18
FLAG -272 -1168 0
FLAG 768 -624 EXTVCC
FLAG 528 -624 _ALERT
FLAG 528 -720 PGOOD
FLAG 720 -528 0
FLAG 528 -528 DRVCC
FLAG 528 -816 _FAULT
FLAG 848 -1184 0
FLAG 912 -1296 OUT
FLAG 752 -1184 0
FLAG 512 -1392 BOOST0
FLAG 480 -1296 SW0
FLAG 480 -1104 SW1
FLAG 512 -1200 BOOST1
FLAG 1040 -896 0
FLAG -112 -528 INTVCC
FLAG -240 -528 0
FLAG -32 -912 EXTVCC
FLAG -288 -912 0
FLAG -32 -1008 0
FLAG -64 -672 0
TEXT 856 -304 Left 2 !.tran 2m startup
TEXT 1264 -1488 Left 2 ;Please read the following notes carefully since all the LT7171-1 features and programmability choices are not modelled\n \n(1) PMBus communication and memory address related functions and pins are not modeled, \nincluding SDA, SCL, WP. The pins shown in the symbol is only for representation \n(2) Changes to parameter values while the simulation is running will not take effect unless the\nsimulation is stopped and restarted. This is different from the way the part operates which will\nrespond to the changes while running.  \n(3) Resistor Configuration pins are not modelled (VOUT_CFG,ASEL, PWM_CFG). The pins shown in the symbol is only for representation \n(4) Only default fault responses are modelled. The part offers diffeent fault responses choices\n(5) Initialization time is not modelled.\n \nThe following parameters can be defined by right-clicking on the LT7171-1 symbol.\nThe nomenclature used here may differ from the one in the data sheet. If any value of these parameters is\nset beyond the scope described in the data sheet, the resulting simulation will not be meaningful.:\n \nFrequency_switch -- in Hz, sets switching frequency\n \nVout_range -- sets maximum output range, 0 for 1.375V, 1 for 2.75V, 2 for 5.5V\n \nVout_command -- in volt, sets output voltage\n \nTon_delay & Ton_rise -- in sec, set ON delay and soft-start time\nToff_delay & Toff_fall -- in sec, set OFF delay and soft-off time \n \nIlim_range -- sets current limit options:\n   0 positive valley current limit of 4.5A per phase, negative valley current limit of -3A\n   1 positive valley current limit of 6.5A per phase, negative valley current limit of -3.8A\n   2 positive valley current limit of 7.8A per phase, negative valley current limit of -4.7A\n   3 positive valley current limit of 10.7A per phase, negative valley current limit of -6A         \n \n \n     \nGMEA_control--Sets Error Amp parameters, N=0 to 31\n     GmEA = 0.15mS*(n+1)/(2^VOUT_RANGE)   (relative to VSENSE inputs)\n     \n \nRITH--in ohm, programmable internal compensation\n \nCITH--in Farad, programmable internal compensation\n \n \nMFR_PWM_PHASE-- in degree, sets the SW0 phase delay in 15-degree increments with respect to the SYNC frequency if present.\n \n \n \nVout_UV_Fault_Limit and Vout_OV_Fault_Limit --- in volt, set the undervoltage and overvoltage fault limit.\nVout_UV_Warn_Limit and Vout_OV_Warn_Limit-- in volt, set the undervoltage and overvoltage warning limit.\n \n \nMFR_DISCHARGE_THRESHOLD--Output voltage threshold to determine that the output has decayed sufficiently to enable the channel\n \nMFR_RETRY_DELAY -- sets the time in milliseconds to retry the LT7171-1 after shuts down due to a fault\n \nEN_SYNC_OUT ---1 Output SYNC Pulses, 0 SYNC works as input.\n \nTON_MAX_FAULT_LIMIT--  Determines how long the LT7171-1 can attempt to soft-start the output without reaching the output undervoltage fault limit.\n \nTo simulate Polyphase load-sharing operation \n \nTie RUN, VIN, SHARE_CLK, _FAULT, _ALERT, PGOOD, ITH pins of all the parts together\nset EN_SYNC_OUT = 1 for only one part and set EN_SYNC_OUT = 0 for all other parts\nThe parameters set in both the part should be identical other than EN_SYNC_OUT