Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP166-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP166-1.2.asy)
XU1 IN 0 N001 OUT ADP16xf K=833.3u ;pnba Vin)GND)En)Vout
C1 OUT 0 1
V1 IN 0 5
Rload OUT 0 120
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -32 96
WIRE 416 96 352 96
WIRE 512 96 416 96
WIRE -32 112 -32 96
WIRE 416 112 416 96
WIRE 512 112 512 96
WIRE -32 208 -32 192
WIRE 160 208 16 208
WIRE 416 208 416 176
WIRE 512 208 512 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL ADP166-1.2 256 208 R0
SYMATTR InstName U1
SYMBOL voltage -32 96 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 400 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 120
FLAG -32 208 0
FLAG 256 272 0
FLAG 416 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG -32 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3007-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3007-3.3.asy)
XU1 IN OUT OUT 0 IN LT3008-3.3 ;pnba IN)OUT)Sense)GND)_SHDN
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 330
C1 OUT 0 1
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\LT3007-3.3 176 96 R0
SYMATTR InstName U1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 330
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 336 248 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\23f2b4f3a241_with_nmos.asc
* Generated by LTspice 26.0.1 for Windows.
* The voltage reading at IN must be equal to the voltage reading at OUT\n \nThis works quite well as long as the RLoad is relatively small (<10 Ohms)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
V1 IN 0 SINE(0.1 0.1 1)
C1 N006 0 10n
R5 N007 N006 1K
RL N002 N003 8
XU1 N007 N001 N002 0 N004 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R1 N005 N004 100
M1 N003 N005 OUT OUT NMOS
R4 OUT 0 1
R2 OUT N001 1K
C2 N007 0 10n
Vs N002 0 12
R3 N006 IN 1K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 10 0 0.01
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1176 680
WIRE 240 -272 16 -272
WIRE 528 -272 320 -272
WIRE 400 -176 400 -224
WIRE 400 -64 400 -96
WIRE 400 -64 128 -64
WIRE 400 -48 400 -64
WIRE 400 64 400 32
WIRE 128 112 128 -64
WIRE 16 128 16 -272
WIRE 96 128 16 128
WIRE 224 144 160 144
WIRE 352 144 304 144
WIRE -304 160 -368 160
WIRE -160 160 -224 160
WIRE -96 160 -160 160
WIRE 32 160 -16 160
WIRE 96 160 32 160
WIRE -368 192 -368 160
WIRE -160 192 -160 160
WIRE 32 192 32 160
WIRE 400 192 400 160
WIRE 448 192 400 192
WIRE 528 192 528 -272
WIRE 528 192 448 192
WIRE 128 208 128 176
WIRE 400 224 400 192
WIRE -368 304 -368 272
WIRE -160 304 -160 256
WIRE -160 304 -368 304
WIRE 32 304 32 256
WIRE 32 304 -160 304
WIRE 400 336 400 304
WIRE -368 352 -368 304
SYMBOL nmos 352 64 R0
SYMATTR InstName M1
SYMBOL res 336 -288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 384 -64 R0
SYMATTR InstName RL
SYMATTR Value 8
SYMBOL res 384 208 R0
SYMATTR InstName R4
SYMATTR Value 1
SYMBOL cap -176 192 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage 400 -80 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vs
SYMATTR Value 12
SYMBOL res -208 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL Misc\\signal -368 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -70 80 Left 2
WINDOW 3 -214 45 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0.1 0.1 1)
SYMBOL cap 16 192 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 320 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL res 0 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL OpAmps\\UniversalOpAmp 128 144 R0
SYMATTR InstName U1
FLAG -368 352 0
FLAG 128 208 0
FLAG 400 -224 0
FLAG 400 336 0
FLAG -368 160 IN
FLAG 448 192 OUT
TEXT 32 520 Left 2 !.tran 0 10 0 0.01
TEXT -952 -120 Left 2 ;The voltage reading at IN must be equal to the voltage reading at OUT\n \nThis works quite well as long as the RLoad is relatively small (<10 Ohms)
* Z:\home\khalils\Downloads\files\data\raw_asc\2fce557217ca_fig-01-03-12.asc
* Generated by LTspice 26.0.1 for Windows.
V1 VIN 0 SINE(0 1 1k)
D1 VOP VOUT 1N4148
VS1 VCC 0 15
VS2 0 VEE 15
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 NC_07 NC_08 ADA4077-2 ;pnba +INA)-INA)OUTA)V+)V-)+INB)-INB)OUTB
R1 VOUT 0 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 2m 0 1u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4077-2.asy)
.lib ADA4077-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 400 80 144 80
WIRE 208 112 208 96
WIRE 208 144 208 112
WIRE 144 160 144 80
WIRE 176 160 144 160
WIRE 288 176 240 176
WIRE 304 176 288 176
WIRE 400 176 400 80
WIRE 400 176 368 176
WIRE 432 176 400 176
WIRE 96 192 48 192
WIRE 176 192 96 192
WIRE 48 208 48 192
WIRE 400 208 400 176
WIRE 208 240 208 208
WIRE 208 256 208 240
WIRE 256 288 256 272
WIRE 320 288 320 272
WIRE 400 320 400 288
WIRE 48 336 48 288
WIRE 256 336 256 288
WIRE 320 336 320 288
WIRE 256 432 256 416
WIRE 320 432 320 416
FLAG 48 336 0
FLAG 432 176 VOUT
IOPIN 432 176 Out
FLAG 96 192 VIN
FLAG 288 176 VOP
FLAG 256 432 0
FLAG 320 432 0
FLAG 256 288 VEE
FLAG 320 288 VCC
FLAG 208 112 VCC
FLAG 208 240 VEE
FLAG 400 320 0
SYMBOL voltage 48 192 R0
WINDOW 0 10 99 Left 2
WINDOW 3 -60 179 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
SYMBOL diode 304 192 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL Misc\\battery 320 320 R0
WINDOW 0 12 6 Left 2
WINDOW 3 15 95 Left 2
SYMATTR InstName VS1
SYMATTR Value 15
SYMBOL Misc\\battery 256 432 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName VS2
SYMATTR Value 15
SYMBOL Opamps\\ADA4077-2 208 112 R0
WINDOW 3 14 122 Left 2
SYMATTR InstName U1
SYMBOL res 384 192 R0
SYMATTR InstName R1
SYMATTR Value 1k
TEXT -40 64 Left 2 !.tran 0 2m 0 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1106.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1106.asy)
C1 N010 0 .1
MQ2 N003 N009 N007 N007 Si9803DY
XU1 0 N010 N001 MP_01 N008 0 MP_02 MP_03 N002 MP_04 MP_05 MP_06 0 N006 N009 N005 N007 N004 N003 N011 LT1106 ;pnba SEL 12/5)Soft Start)Vcc))3/5 Detect)PGND)))SW))))SGND)_Vpp Valid)G2)G1)Vpp2)Vpp1)AVpp)ON/OFF
V1 N001 0 3.3
C2 N003 0 1
L1 N001 N002 10
R1 N010 0 1Meg
D1 N002 N003 MBR0530L
MQ1 N003 N005 N004 N004 Si9803DY
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m startup
.lib LT1106.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2260 1624
WIRE 1648 976 1392 976
WIRE 1680 976 1648 976
WIRE 1808 976 1760 976
WIRE 1904 976 1808 976
WIRE 2048 976 1968 976
WIRE 1392 992 1392 976
WIRE 1648 1072 1648 976
WIRE 1808 1072 1808 976
WIRE 1392 1088 1392 1072
WIRE 1520 1136 1248 1136
WIRE 2048 1136 2048 976
WIRE 2048 1136 1936 1136
WIRE 2256 1136 2048 1136
WIRE 2048 1152 2048 1136
WIRE 1248 1184 1248 1136
WIRE 1520 1200 1296 1200
WIRE 1968 1200 1936 1200
WIRE 2048 1232 2048 1216
WIRE 1520 1264 1392 1264
WIRE 1968 1264 1936 1264
WIRE 1392 1312 1392 1264
WIRE 1520 1328 1440 1328
WIRE 2064 1328 1936 1328
WIRE 2144 1328 2064 1328
WIRE 2064 1344 2064 1328
WIRE 2144 1344 2144 1328
WIRE 1520 1392 1488 1392
WIRE 1968 1392 1936 1392
WIRE 2064 1440 2064 1408
WIRE 2144 1440 2144 1424
WIRE 1648 1488 1648 1456
WIRE 1808 1488 1808 1456
WIRE 1248 1552 1248 1280
WIRE 1392 1552 1392 1408
WIRE 1392 1552 1248 1552
WIRE 2256 1552 2256 1136
WIRE 2256 1552 1392 1552
SYMBOL cap 2032 1152 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL schottky 1904 992 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBR0530L
SYMBOL voltage 1392 976 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL PowerProducts\\LT1106 1728 1264 R0
SYMATTR InstName U1
SYMBOL ind 1664 992 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL pmos 1440 1408 R180
WINDOW 0 33 100 Right 2
WINDOW 3 40 -10 Right 2
SYMATTR InstName Q2
SYMATTR Value Si9803DY
SYMBOL cap 2048 1344 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL pmos 1296 1280 R180
WINDOW 0 41 103 Right 2
WINDOW 3 40 -12 Right 2
SYMATTR InstName Q1
SYMATTR Value Si9803DY
SYMBOL res 2128 1328 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
FLAG 2064 1440 0
FLAG 2144 1440 0
FLAG 1968 1392 0
FLAG 1808 1488 0
FLAG 1648 1488 0
FLAG 2048 1232 0
FLAG 1392 1088 0
TEXT 1952 1576 Left 2 !.tran 100m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8397.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8397.asy)
Vee 0 Vee 5
XU1 VOS+ VOS- Vcc Vee VOS- AD8397 ;pnba In+)In-)V+)V-)OUT
Vcm VOS+ 0 SINE(0 1 1k)
R1 VOS- 0 100
Vcc Vcc 0 5
.tran 5m
.lib AD8397.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1704 1132
WIRE 352 160 64 160
WIRE -192 208 -192 192
WIRE 208 272 208 256
WIRE 64 288 64 160
WIRE 128 288 64 288
WIRE 176 288 128 288
WIRE 352 304 352 160
WIRE 352 304 240 304
WIRE -192 320 -192 288
WIRE -192 320 -240 320
WIRE 128 320 64 320
WIRE 176 320 128 320
WIRE -240 336 -240 320
WIRE -192 336 -192 320
WIRE 208 352 208 336
WIRE 64 368 64 320
WIRE 352 368 352 304
WIRE -192 432 -192 416
WIRE 64 464 64 448
WIRE 352 480 352 448
DATAFLAG 352 304 ""
SYMBOL res 336 352 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage -192 192 R0
WINDOW 123 0 0 Left 2
WINDOW 0 34 37 Left 2
WINDOW 3 34 66 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcc
SYMATTR Value 5
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 2
WINDOW 0 37 40 Left 2
WINDOW 3 38 73 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vee
SYMATTR Value 5
SYMBOL AD8397 208 240 R0
SYMATTR InstName U1
SYMBOL voltage 64 352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcm
SYMATTR Value SINE(0 1 1k)
FLAG -240 336 0
FLAG 208 256 Vcc
FLAG 208 352 Vee
FLAG -192 192 Vcc
FLAG -192 432 Vee
FLAG 128 320 VOS+
FLAG 128 288 VOS-
FLAG 64 464 0
FLAG 352 480 0
TEXT -216 32 Left 2 !.tran 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\0019e8de1157_2nd_order_butterworth_lp.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6241.asy)
R2 N002 N001 1k
XU1 N002 OUT V+ V- OUT LTC6241 ;pnba IN+)IN-)VCC)VEE)OUT
C1 0 N002 112nF
V2 V- 0 -5
C2 OUT N001 224nF
V1 V+ 0 5
R1 N001 IN 1k
V3 IN 0 PWL(1m 0 1.001m 1 2m 1 2.001m 0) AC 1V
.ac oct 10 10 100k
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 680
WIRE -640 -48 -640 -64
WIRE -544 -48 -544 -64
WIRE -640 64 -640 32
WIRE -544 64 -544 32
WIRE -256 208 -288 208
WIRE -160 208 -256 208
WIRE -256 256 -256 208
WIRE -240 256 -256 256
WIRE -160 272 -160 208
WIRE -160 272 -176 272
WIRE -112 272 -160 272
WIRE -96 272 -112 272
WIRE -464 288 -480 288
WIRE -448 288 -464 288
WIRE -352 288 -352 208
WIRE -352 288 -368 288
WIRE -336 288 -352 288
WIRE -240 288 -256 288
WIRE -480 304 -480 288
WIRE -256 320 -256 288
WIRE -480 416 -480 384
WIRE -256 416 -256 384
SYMBOL res -352 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL LTC6241 -208 272 R0
WINDOW 3 -50 -91 Left 2
SYMATTR InstName U1
SYMBOL cap -288 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 224nF
SYMBOL voltage -640 -64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -480 288 R0
WINDOW 3 24 160 Left 2
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PWL(1m 0 1.001m 1 2m 1 2.001m 0)
SYMATTR Value2 AC 1V
SYMATTR InstName V3
SYMBOL cap -240 384 R180
WINDOW 0 -26 30 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 112nF
SYMBOL voltage -544 -64 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res -240 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
FLAG -640 64 0
FLAG -544 64 0
FLAG -208 304 V-
FLAG -544 -64 V-
FLAG -640 -64 V+
FLAG -208 240 V+
FLAG -256 416 0
FLAG -480 416 0
FLAG -464 288 IN
FLAG -112 272 OUT
TEXT -136 400 Left 2 !.ac oct 10 10 100k
* Z:\home\khalils\Downloads\files\data\raw_asc\10edf969c578_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD795.asy)
C3 N006 N005 C
R4 N002 N001 R
C1 N001 N003 C
XU2 N007 N006 NC_03 NC_04 N006 AD795 ;pnba In+)In-)V+)V-)OUT
C2 N004 N001 C
R2 N007 N005 R
R1 N004 0 R
R3 N005 N003 R
C4 0 N007 C
XU1 N004 N002 NC_01 NC_02 N002 AD795 ;pnba In+)In-)V+)V-)OUT
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -144 -176 -144
WIRE 256 -144 64 -144
WIRE -320 -16 -384 -16
WIRE -176 -16 -176 -144
WIRE -176 -16 -256 -16
WIRE -112 -16 -176 -16
WIRE 16 -16 -48 -16
WIRE 144 -16 16 -16
WIRE 256 0 256 -144
WIRE 256 0 208 0
WIRE 16 16 16 -16
WIRE 144 16 96 16
WIRE 96 112 96 16
WIRE 256 112 256 0
WIRE 256 112 96 112
WIRE 16 128 16 96
WIRE -16 304 -176 304
WIRE 256 304 48 304
WIRE -384 432 -384 -16
WIRE -320 432 -384 432
WIRE -176 432 -176 304
WIRE -176 432 -240 432
WIRE -128 432 -176 432
WIRE 16 432 -48 432
WIRE 144 432 16 432
WIRE 256 448 256 304
WIRE 256 448 208 448
WIRE 16 464 16 432
WIRE 144 464 96 464
WIRE 16 560 16 528
WIRE 96 576 96 464
WIRE 256 576 256 448
WIRE 256 576 96 576
SYMBOL cap -48 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMBOL res -32 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMBOL OpAmps\\AD795 176 512 M180
SYMATTR InstName U2
SYMBOL res -224 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMBOL res 80 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMBOL OpAmps\\AD795 176 64 M180
SYMATTR InstName U1
SYMBOL res 0 0 R0
SYMATTR InstName R1
SYMBOL cap -256 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMBOL cap 32 528 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C4
SYMBOL cap 48 288 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
FLAG 16 128 0
FLAG 16 560 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG5412.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 15V dual supply\nPin Capacitance not included\nOnly one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG5412.asy)
V2 -V 0 -15
V3 N001 0 10
XU1 +V -V N003 N001 N002 0 ADG5412 ;pnba Vdd)Vss)IN)S)D)GND
V4 N003 0 pulse(0 5 0 20n 20n 10u 20u)
R1 N002 0 300
V1 +V 0 15
.tran 50u
.lib ADG5412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2844 1336
WIRE -112 -128 -112 -144
WIRE -464 -48 -464 -64
WIRE -304 -48 -336 -48
WIRE -208 -48 -224 -48
WIRE 48 -48 -16 -48
WIRE 48 -16 48 -48
WIRE -208 16 -336 16
WIRE -464 48 -464 32
WIRE 48 80 48 64
WIRE -336 96 -336 16
WIRE -464 144 -464 128
WIRE -176 144 -176 128
WIRE -48 144 -48 128
WIRE -464 240 -464 224
WIRE -336 240 -336 176
SYMBOL voltage -208 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -336 80 R0
WINDOW 3 19 116 Left 2
SYMATTR Value pulse(0 5 0 20n 20n 10u 20u)
SYMATTR InstName V4
SYMBOL ADG5412 -112 0 R0
SYMATTR InstName U1
SYMBOL voltage -464 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -464 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 32 -32 R0
SYMATTR InstName R1
SYMATTR Value 300
FLAG -464 240 0
FLAG -464 48 0
FLAG -464 -64 +V
FLAG -464 128 -V
FLAG -336 -48 0
FLAG -176 144 -V
FLAG -112 -144 +V
FLAG -48 144 0
FLAG -336 240 0
FLAG 48 80 0
TEXT 112 256 Left 2 !.tran 50u
TEXT -488 -320 Left 2 ;Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 15V dual supply\nPin Capacitance not included\nOnly one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\b9fab507a88d_mosfet-driver.asc
* Generated by LTspice 26.0.1 for Windows.
* This circuit simulate the driving of the MOSFET\n \nWith this choise of components the slew rate of the signal at the \noutput is of about 1us, which means we are losing 1us of duty-cycle.\n \nR1 is chose in order to limit the current sinked from the microcontroller and \nalso to speed up the bjt commutation.\nIt also saturates the bjt with V2/R2 < Ib*B.\n \nR2 is a pull-up resistor. It soure the gate capacitance during ON-time.\nIt is chosen in order to mantain low current trhought the bjt, but low enought \nto charge C2 (gate capacitance) as fast as possible.
Q1 N002 N004 0 0 2N2222
C2 N002 0 1480p
R1 N004 N003 200R
V1 N003 0 PULSE(0 3.3 0 20n 20n 20u 50u)
V2 N001 0 8
R2 N002 N001 100R
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 8m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1816 680
WIRE 336 -224 -144 -224
WIRE -144 -144 -144 -224
WIRE 336 -64 336 -224
WIRE -144 -16 -144 -64
WIRE 336 80 336 16
WIRE 624 80 336 80
WIRE 624 112 624 80
WIRE 336 128 336 80
WIRE 144 176 -32 176
WIRE 272 176 224 176
WIRE -32 240 -32 176
WIRE 624 272 624 176
WIRE -32 448 -32 320
WIRE 336 448 336 224
SYMBOL voltage -32 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0 20n 20n 20u 50u)
SYMBOL cap 608 112 R0
SYMATTR InstName C2
SYMATTR Value 1480p
SYMBOL res 240 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200R
SYMBOL voltage -144 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 8
SYMBOL npn 272 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL res 352 32 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 100R
FLAG -32 448 0
FLAG 336 448 0
FLAG -144 -16 0
FLAG 624 272 0
TEXT -178 472 Left 2 !.tran 8m
TEXT 904 -368 Left 2 ;This circuit simulate the driving of the MOSFET\n \nWith this choise of components the slew rate of the signal at the \noutput is of about 1us, which means we are losing 1us of duty-cycle.\n \nR1 is chose in order to limit the current sinked from the microcontroller and \nalso to speed up the bjt commutation.\nIt also saturates the bjt with V2/R2 < Ib*B.\n \nR2 is a pull-up resistor. It soure the gate capacitance during ON-time.\nIt is chosen in order to mantain low current trhought the bjt, but low enought \nto charge C2 (gate capacitance) as fast as possible.
* Z:\home\khalils\Downloads\files\data\raw_asc\37405ac0a07f_AnalogVdivider_noise.asc
* Generated by LTspice 26.0.1 for Windows.
* .ac dec 10 1 10k
R1 N001 analog_in 10
C2 analog_out 0 10n V=50
C1 N001 0 100n V=50
R2 N001 N002 100k
V2 3v3 0 3.3
D1 analog_out 3v3 BAT54
R3 N002 0 150k
R4 analog_out N002 1k
V1 analog_in 0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.noise V(analog_out) V1 oct 10 1 16k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE 64 112 -160 112
WIRE 208 112 144 112
WIRE 384 112 208 112
WIRE 720 112 720 0
WIRE 208 224 208 176
WIRE 384 256 384 192
WIRE 528 256 384 256
WIRE 720 256 720 176
WIRE 720 256 608 256
WIRE 912 256 720 256
WIRE 384 320 384 256
WIRE 720 320 720 256
WIRE -432 400 -432 336
WIRE -240 400 -240 304
WIRE 384 448 384 400
WIRE 720 448 720 384
WIRE -432 544 -432 480
WIRE -240 544 -240 480
SYMBOL res 624 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage -240 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL res 368 96 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage -432 384 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL cap 704 320 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMATTR SpiceLine V=50
SYMBOL res 368 304 R0
SYMATTR InstName R3
SYMATTR Value 150k
SYMBOL schottky 736 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 192 112 R0
SYMATTR InstName C1
SYMATTR Value 100n
SYMATTR SpiceLine V=50
SYMBOL res 160 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
FLAG 912 256 analog_out
FLAG -160 112 analog_in
FLAG 384 448 0
FLAG 720 448 0
FLAG 720 0 3v3
FLAG 208 224 0
FLAG -432 336 3v3
FLAG -432 544 0
FLAG -240 544 0
FLAG -240 304 analog_in
TEXT 480 520 Left 2 ;.ac dec 10 1 10k
TEXT 480 552 Left 2 !.noise V(analog_out) V1 oct 10 1 16k