Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX44246.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX44246.asy)
V1 IN 0 SINE(0 50m 100k)
XU1 IN OUT Vcc Vee OUT MAX44246 ;pnba In+)In-)V+)V-)OUT
Vee 0 Vee 15
RL OUT 0 5k
CL OUT 0 15p
Vcc Vcc 0 15
.tran 10u
.lib MAX44246.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 656 256 304 256
WIRE 64 288 64 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 656 384 656 256
WIRE 656 384 464 384
WIRE 752 384 656 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 656 416 656 384
WIRE 752 432 752 384
WIRE 64 448 64 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 656 528 656 496
WIRE 752 528 752 496
WIRE 64 544 64 528
WIRE 304 592 304 576
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 15
SYMBOL cap 736 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 100k)
SYMBOL MAX44246 432 320 R0
SYMATTR InstName U1
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 15
SYMBOL res 640 400 R0
SYMATTR InstName RL
SYMATTR Value 5k
FLAG 752 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 656 528 0
FLAG 304 400 IN
FLAG 752 528 0
TEXT 16 632 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1949-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1949-1.asy)
V1 IN 0 3.3
L1 IN N001 10
D1 N001 OUT MBRS130L
Rload OUT 0 57.5
XU1 N006 N003 N005 0 N001 IN N004 N002 LT1949-1 ;pnba Vc)FB)_SHDN)GND)SW)Vin)LBI)LBO
R1 N006 N007 68K
R3 N003 0 140K
R2 OUT N003 1Meg
R4 IN N002 1Meg
C1 N007 0 330p
C2 OUT 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT1949-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2700 680
WIRE 1728 128 1616 128
WIRE 1888 128 1728 128
WIRE 1936 128 1888 128
WIRE 2048 128 2016 128
WIRE 2112 128 2048 128
WIRE 2272 128 2176 128
WIRE 2384 128 2272 128
WIRE 2496 128 2384 128
WIRE 1616 144 1616 128
WIRE 2384 144 2384 128
WIRE 2496 144 2496 128
WIRE 1728 176 1728 128
WIRE 2272 176 2272 128
WIRE 1888 224 1888 128
WIRE 2048 224 2048 128
WIRE 1616 240 1616 224
WIRE 2384 240 2384 208
WIRE 2496 240 2496 224
WIRE 1728 304 1728 256
WIRE 1824 304 1728 304
WIRE 2272 304 2272 256
WIRE 2272 304 2112 304
WIRE 2272 320 2272 304
WIRE 1824 368 1808 368
WIRE 2272 416 2272 400
WIRE 1824 432 1808 432
WIRE 2128 432 2112 432
WIRE 2224 432 2208 432
WIRE 2224 448 2224 432
WIRE 2224 528 2224 512
WIRE 1968 560 1968 512
SYMBOL res 2256 160 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL RES 2112 448 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 68K
SYMBOL res 1712 160 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL cap 2208 448 R0
SYMATTR InstName C1
SYMATTR Value 330p
SYMBOL ind 1920 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1949-1 1968 368 R0
SYMATTR InstName U1
SYMBOL cap 2368 144 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL schottky 2112 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS130L
SYMBOL res 2256 304 R0
SYMATTR InstName R3
SYMATTR Value 140K
SYMBOL res 2480 128 R0
SYMATTR InstName Rload
SYMATTR Value 57.5
SYMBOL VOLTAGE 1616 128 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 1968 560 0
FLAG 2224 528 0
FLAG 2272 416 0
FLAG 2384 240 0
FLAG 1616 240 0
FLAG 2496 240 0
FLAG 1616 128 IN
FLAG 2496 128 OUT
TEXT 2384 480 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC660.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC660.asy)
XU1 NC_01 N001 0 N004 OUT N003 N002 IN LTC660 ;pnba Boost)Cap+)GND)Cap-)Vout)LV)OSC)Vin
C2 OUT 0 150
C1 N001 N004 150
V1 IN 0 5
Rload OUT 0 43.7
.tran 10m startup
.lib LTC660.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3516 2244
WIRE 3312 1904 3200 1904
WIRE 3312 1920 3312 1904
WIRE 2944 1968 2832 1968
WIRE 3216 1968 3200 1968
WIRE 2832 2000 2832 1968
WIRE 3312 2016 3312 2000
WIRE 2944 2032 2928 2032
WIRE 3216 2032 3200 2032
WIRE 2832 2096 2832 2064
WIRE 2944 2096 2832 2096
WIRE 3248 2096 3200 2096
WIRE 3360 2096 3248 2096
WIRE 3248 2112 3248 2096
WIRE 3360 2112 3360 2096
WIRE 3248 2208 3248 2176
WIRE 3360 2208 3360 2192
SYMBOL cap 3232 2112 R0
SYMATTR InstName C2
SYMATTR Value 150
SYMBOL cap 2816 2000 R0
SYMATTR InstName C1
SYMATTR Value 150
SYMBOL PowerProducts\\LTC660 3072 2000 R0
SYMATTR InstName U1
SYMBOL res 3344 2096 R0
SYMATTR InstName Rload
SYMATTR Value 43.7
SYMBOL voltage 3312 1904 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 2928 2032 0
FLAG 3312 2016 0
FLAG 3248 2208 0
FLAG 3360 2208 0
FLAG 3360 2096 OUT
FLAG 3312 1904 IN
TEXT 2952 2216 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\61d9b327f701_iNMOS.asc
* Generated by LTspice 26.0.1 for Windows.
S1 S N001 G S SW_iNMOS
R1 D N003 {rsnb}
C1 N003 S {csnb}
L1 D N001 {esl}
D1 S N002 myD
L2 D N002 {esl}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)
.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
.param ron=10m
.param esl=1f
.param rsnb=1k
.param csnb=10p
* body diode
* snubber
* binary
* Ideal NMOS
* on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
* Drain
* Source
* Gate
* 2025-7-21
* <Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1384 680
WIRE 288 -288 288 -320
WIRE 608 -288 288 -288
WIRE 928 -288 608 -288
WIRE 288 -240 288 -288
WIRE 608 -240 608 -288
WIRE 928 -192 928 -288
WIRE 288 -112 288 -160
WIRE 240 -96 96 -96
WIRE 608 -96 608 -160
WIRE 928 -80 928 -112
WIRE 240 -48 208 -48
WIRE 208 0 208 -48
WIRE 288 0 288 -32
WIRE 288 0 208 0
WIRE 288 80 288 0
WIRE 608 80 608 -32
WIRE 608 80 288 80
WIRE 928 80 928 -16
WIRE 928 80 608 80
WIRE 288 112 288 80
FLAG 288 -320 D
IOPIN 288 -320 BiDir
FLAG 288 112 S
IOPIN 288 112 BiDir
FLAG 96 -96 G
IOPIN 96 -96 BiDir
SYMBOL sw 288 -16 M180
SYMATTR InstName S1
SYMATTR Value SW_iNMOS
SYMBOL res 912 -208 R0
SYMATTR InstName R1
SYMATTR Value {rsnb}
SYMBOL cap 912 -80 R0
SYMATTR InstName C1
SYMATTR Value {csnb}
SYMBOL ind 272 -256 R0
SYMATTR InstName L1
SYMATTR Value {esl}
SYMBOL diode 624 -32 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value myD
SYMBOL ind 592 -256 R0
SYMATTR InstName L2
SYMATTR Value {esl}
TEXT 56 -440 Left 2 !.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)\n.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
TEXT 56 -568 Left 2 !.param ron=10m\n.param esl=1f\n.param rsnb=1k\n.param csnb=10p
TEXT 552 -320 Left 2 ;body diode
TEXT 888 -320 Left 2 ;snubber
TEXT 56 -120 Left 1 ;binary
TEXT 40 -624 Left 4 ;Ideal NMOS
TEXT 312 -568 Left 2 ;on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
TEXT 312 -344 Left 2 ;Drain
TEXT 312 136 Left 2 ;Source
TEXT 56 -64 Left 2 ;Gate
TEXT 1000 -624 Left 2 ;2025-7-21
TEXT 80 208 Left 2 ;<Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
* Z:\home\khalils\Downloads\files\data\raw_asc\168d23038f34_Draft14.asc
* Generated by LTspice 26.0.1 for Windows.
T6 N005 N012 N006 N006 Td=50n Z0=50
V1 s 0 PULSE(0 5 0 0.1n 0.1n 0.5n 0 1)
T5 N004 N011 N005 N012 Td=50n Z0=50
T1 s 0 N001 N008 Td=50n Z0=50
T2 N001 N008 N002 N009 Td=50n Z0=50
R1 R_end 0 100
T7 N006 N006 N007 N013 Td=50n Z0=50
T8 N007 N013 R_end 0 Td=50n Z0=50
T4 N003 N010 N004 N011 Td=50n Z0=50
T3 N002 N009 N003 N010 Td=50n Z0=50
.tran 0 900n 0 0.6n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1732 680
WIRE -32 32 -48 32
WIRE 80 32 -32 32
WIRE 272 32 176 32
WIRE 464 32 368 32
WIRE 656 32 560 32
WIRE 832 32 752 32
WIRE 1008 32 928 32
WIRE 1152 32 1104 32
WIRE 1184 32 1152 32
WIRE 1360 32 1280 32
WIRE 1648 32 1456 32
WIRE 1664 32 1648 32
WIRE 80 64 16 64
WIRE 272 64 176 64
WIRE 464 64 368 64
WIRE 656 64 560 64
WIRE 832 64 752 64
WIRE 1008 64 928 64
WIRE 1152 64 1152 32
WIRE 1152 64 1104 64
WIRE 1184 64 1152 64
WIRE 1360 64 1280 64
WIRE 1552 64 1456 64
WIRE 1664 112 1664 32
WIRE -48 128 -48 32
WIRE -48 272 -48 208
WIRE 16 272 16 64
WIRE 1552 304 1552 64
WIRE 1664 304 1664 192
SYMBOL tline 1056 48 R0
SYMATTR InstName T6
SYMBOL tline 512 48 R0
SYMATTR InstName T3
SYMBOL tline 880 48 R0
SYMATTR InstName T5
SYMBOL tline 128 48 R0
SYMATTR InstName T1
SYMBOL tline 704 48 R0
SYMATTR InstName T4
SYMBOL tline 1408 48 R0
SYMATTR InstName T8
SYMBOL tline 1232 48 R0
SYMATTR InstName T7
SYMBOL res 1648 96 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL tline 320 48 R0
SYMATTR InstName T2
SYMBOL voltage -48 112 R0
WINDOW 3 -54 -105 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 0.1n 0.1n 0.5n 0 1)
FLAG -48 272 0
FLAG 16 272 0
FLAG 1552 304 0
FLAG 1664 304 0
FLAG 1648 32 R_end
FLAG -32 32 s
TEXT -88 440 Left 2 !.tran 0 900n 0 0.6n
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1176.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1176.asy)
L1 N001 OUT 100
XU1 IN N005 0 N004 N003 N002 N006 N001 LT1176 top=10 bot=1G ;pnba Vin)Ilim)GND)FB)_SHDN)Status)Vc)SW
R1 OUT N004 2.8K
C1 OUT 0 470 Rser=.1
R4 OUT 0 10
R3 N006 N007 2.8K
C2 0 N007 .01
R2 N004 0 2.2K
D1 0 N001 1N5819
V1 IN 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LT1176.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2728 1608
WIRE 1792 1104 1520 1104
WIRE 1520 1120 1520 1104
WIRE 1792 1136 1792 1104
WIRE 2032 1136 1984 1136
WIRE 2096 1136 2032 1136
WIRE 2224 1136 2176 1136
WIRE 2336 1136 2224 1136
WIRE 2432 1136 2336 1136
WIRE 2336 1152 2336 1136
WIRE 2432 1152 2432 1136
WIRE 2032 1168 2032 1136
WIRE 2224 1168 2224 1136
WIRE 1632 1200 1616 1200
WIRE 1984 1200 1984 1136
WIRE 1984 1200 1952 1200
WIRE 1520 1216 1520 1200
WIRE 2032 1248 2032 1232
WIRE 2336 1248 2336 1216
WIRE 2432 1248 2432 1232
WIRE 1632 1280 1616 1280
WIRE 2224 1280 2224 1248
WIRE 2224 1280 1952 1280
WIRE 2224 1296 2224 1280
WIRE 1632 1360 1616 1360
WIRE 1968 1360 1952 1360
WIRE 2064 1360 2048 1360
WIRE 2144 1360 2128 1360
WIRE 2224 1392 2224 1376
WIRE 1792 1440 1792 1424
SYMBOL polcap 2320 1152 R0
SYMATTR SpiceLine Rser=.1
SYMATTR InstName C1
SYMATTR Value 470
SYMBOL res 1952 1376 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 2.8K
SYMBOL cap 2128 1344 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL RES 2416 1136 R0
SYMATTR InstName R4
SYMATTR Value 10
SYMBOL res 2208 1280 R0
SYMATTR InstName R2
SYMATTR Value 2.2K
SYMBOL POWERPRODUCTS\\LT1176 1792 1280 R0
SYMATTR InstName U1
SYMBOL ind 2080 1152 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL RES 2208 1152 R0
SYMATTR InstName R1
SYMATTR Value 2.8K
SYMBOL schottky 2016 1232 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMBOL VOLTAGE 1520 1104 R0
SYMATTR InstName V1
SYMATTR Value 10
FLAG 1792 1440 0
FLAG 1520 1216 0
FLAG 2032 1248 0
FLAG 2224 1392 0
FLAG 2336 1248 0
FLAG 2144 1360 0
FLAG 2432 1248 0
FLAG 2432 1136 OUT
FLAG 1520 1104 IN
TEXT 2064 1440 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2188be8b98c0__Fig1_25_K_is_4_AC_MSD.asc
* Generated by LTspice 26.0.1 for Windows.
E1 Vout 0 Vin N001 1
T1 Vin 0 N001 0 Td=40n Z0=50
R1 N001 0 50
Vin Vin 0 AC 1
.ac lin 1000 1k 100MEG
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1056 688
WIRE 752 256 704 256
WIRE 800 256 752 256
WIRE 704 288 704 256
WIRE 208 304 192 304
WIRE 272 304 208 304
WIRE 656 304 272 304
WIRE 192 320 192 304
WIRE 192 416 192 400
WIRE 272 480 272 304
WIRE 400 480 272 480
WIRE 656 480 656 352
WIRE 656 480 496 480
WIRE 656 496 656 480
WIRE 400 512 384 512
WIRE 528 512 496 512
WIRE 656 608 656 576
SYMBOL res 640 480 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL e 704 272 R0
WINDOW 0 42 39 Left 0
WINDOW 3 44 69 Left 0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL tline 448 496 R0
SYMATTR InstName T1
SYMATTR Value Td=40n Z0=50
SYMBOL voltage 192 304 R0
WINDOW 0 -73 38 Left 0
WINDOW 123 -82 95 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value2 AC 1
SYMATTR Value ""
FLAG 656 608 0
FLAG 528 512 0
FLAG 384 512 0
FLAG 192 416 0
FLAG 208 304 Vin
FLAG 752 256 Vout
FLAG 704 368 0
TEXT 304 392 Left 0 !.ac lin 1000 1k 100MEG
* Z:\tmp\asc_dec_bjh7r6w2\0ac64165dd67_standard_hold_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
M7 N002 WL BL 0 EECMOSN l={l_ax} w={w_ax}
M3 Qneg N001 0 0 EECMOSN l={l_nmos_q_neg} w={w_nmos_q_neg}
M8 BLneg WL Qneg 0 EECMOSN l={l_ax} w={w_ax}
Vwl WL 0 {vwl}
Vbl BL 0 {vbl}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -512 0 -512 -64
WIRE -512 0 -560 0
WIRE -512 48 -512 0
WIRE -512 48 -560 48
WIRE -1360 64 -1360 -80
WIRE -272 64 -272 -80
WIRE -608 80 -640 80
WIRE -1456 112 -1584 112
WIRE -1376 112 -1456 112
WIRE -1040 112 -1280 112
WIRE -640 112 -640 80
WIRE -640 112 -1024 112
WIRE -560 112 -560 96
WIRE -512 112 -560 112
WIRE -288 112 -512 112
WIRE -272 112 -288 112
WIRE -32 112 -192 112
WIRE 80 112 -32 112
WIRE -560 128 -560 112
WIRE -560 128 -944 128
WIRE -512 176 -560 176
WIRE -240 176 -240 112
WIRE -1328 192 -1328 112
WIRE -640 208 -640 112
WIRE -608 208 -640 208
WIRE -512 224 -512 176
WIRE -512 224 -560 224
WIRE -560 256 -560 224
WIRE -768 272 -800 272
WIRE -736 272 -768 272
WIRE -800 304 -800 272
SYMBOL nmos4 -1280 64 R90
WINDOW 123 79 185 Left 2
WINDOW 3 77 149 Left 2
SYMATTR Value2 l={l_ax} w={w_ax}
SYMATTR Value EECMOSN
SYMATTR InstName M7
SYMBOL nmos4 -608 128 R0
WINDOW 123 79 185 Left 2
WINDOW 3 77 149 Left 2
SYMATTR Value2 l={l_nmos_q_neg} w={w_nmos_q_neg}
SYMATTR Value EECMOSN
SYMATTR InstName M3
SYMBOL nmos4 -192 64 R90
WINDOW 123 81 -61 Left 2
WINDOW 3 79 -22 Left 2
SYMATTR Value2 l={l_ax} w={w_ax}
SYMATTR Value EECMOSN
SYMATTR InstName M8
SYMBOL voltage -688 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vwl
SYMATTR Value {vwl}
SYMBOL voltage -1584 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vbl
SYMATTR Value {vbl}
FLAG -560 256 0
FLAG -864 0 0
FLAG -240 176 0
FLAG -1328 192 0
FLAG -1584 192 0
FLAG -1456 112 BL
FLAG -32 112 BLneg
FLAG -512 112 Qneg
FLAG -768 272 Qneg
FLAG -688 0 0
FLAG -864 -80 VDD
FLAG -512 -64 VDD
FLAG -272 -80 WL
FLAG -688 -80 WL
FLAG -1360 -80 WL
* Z:\home\khalils\Downloads\files\data\raw_asc\3d6de1b83fec_Bonus3.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 0 2
C1 out N001 {24/31}
C2 N002 0 {24}
V1 N001 0 AC 1 Rser=1
L2 out N002 {2/3}
.net V(out) V1
.ac dec 1000000 10m 1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 352 80 128 80
WIRE 432 80 352 80
WIRE 592 80 496 80
WIRE 592 96 592 80
WIRE 128 144 128 80
WIRE 352 144 352 80
WIRE 592 192 592 176
WIRE 128 256 128 224
WIRE 352 256 352 224
SYMBOL ind 336 128 R0
SYMATTR InstName L1
SYMATTR Value 2
SYMBOL cap 496 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {24/31}
SYMBOL ind 576 80 R0
SYMATTR InstName L2
SYMATTR Value {2/3}
SYMBOL cap 576 192 R0
SYMATTR InstName C2
SYMATTR Value {24}
SYMBOL voltage 128 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR Value2 AC 1
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value ""
FLAG 352 256 0
FLAG 592 256 0
FLAG 128 256 0
FLAG 592 80 out
TEXT 88 304 Left 2 !.net V(out) V1
TEXT 64 344 Left 2 !.ac dec 1000000 10m 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3620-1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 3.6
L1 N001 OUT 22 Rpar=10K
C1 OUT 0 1
Rload OUT 0 100
XU1 N001 0 0 NC_01 MP_02 OUT IN IN LTC3620-1 ;pnba SW)GND)Fmin/Mode)LoBatB))Vout)Run)Vin
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3620-1.asy)
.lib LTC3620-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 96 16 96
WIRE 256 96 112 96
WIRE 16 112 16 96
WIRE 256 112 256 96
WIRE 112 160 112 96
WIRE 128 160 112 160
WIRE 16 208 16 192
WIRE 128 256 112 256
WIRE 416 256 384 256
WIRE 528 256 496 256
WIRE 560 256 528 256
WIRE 640 256 560 256
WIRE 560 272 560 256
WIRE 640 272 640 256
WIRE 128 352 112 352
WIRE 528 352 528 256
WIRE 528 352 384 352
WIRE 560 368 560 336
WIRE 640 368 640 352
FLAG 16 208 0
FLAG 112 256 0
FLAG 112 352 0
FLAG 560 368 0
FLAG 640 368 0
FLAG 640 256 OUT
FLAG 16 96 IN
SYMBOL voltage 16 96 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL ind 400 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 22
SYMATTR SpiceLine Rpar=10K
SYMBOL cap 544 272 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 624 256 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL LTC3620-1 256 256 R0
SYMATTR InstName U1
TEXT 472 424 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1205ac0c4888_1_3b.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N003 N002 D
R2 0 N002 1k
R1 N002 N001 100
V1 N001 0 SINE(0 5 200)
D2 N003 0 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model D ako: 1N750 Bv=2.7
.tran .05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 80 -64 80
WIRE 272 80 96 80
WIRE 528 80 272 80
WIRE 272 96 272 80
WIRE -64 128 -64 80
WIRE 528 144 528 80
WIRE 272 176 272 160
WIRE -64 256 -64 208
WIRE 272 256 272 240
WIRE 272 256 -64 256
WIRE 528 256 528 224
WIRE 528 256 272 256
WIRE -64 272 -64 256
SYMBOL res 544 240 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL zener 288 160 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL voltage -64 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 200)
SYMBOL zener 256 176 R0
SYMATTR InstName D2
SYMBOL res 112 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100
FLAG -64 272 0
TEXT 480 24 Left 2 !.model D ako: 1N750 Bv=2.7
TEXT -98 296 Left 2 !.tran .05
* Z:\home\khalils\Downloads\files\data\raw_asc\242d6a81905e_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 V2 N001 1k
L1 N002 0 100
R2 N002 V2 1k
V1 V1 0 SINE(0 10 1 0.001 0.001 0)
V2 V2 0 PULSE(0 10 0 0.001 0.001 1 10 0)
C1 N001 0 5e-5
.tran 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -560 16 -560 0
WIRE 64 64 48 64
WIRE 160 64 144 64
WIRE 176 64 160 64
WIRE 48 96 48 64
WIRE 256 96 256 64
WIRE 160 128 160 64
WIRE 192 128 160 128
WIRE -560 144 -560 128
WIRE 48 192 48 160
WIRE 160 192 160 176
WIRE 160 192 48 192
WIRE 256 192 256 176
WIRE 256 192 160 192
WIRE 160 208 160 192
SYMBOL res 272 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL cap 32 96 R0
SYMATTR InstName C1
SYMATTR Value 5e-5
SYMBOL ind 240 80 R0
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL voltage -560 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 1 0.001 0.001 0)
SYMBOL voltage -560 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0 0.001 0.001 1 10 0)
SYMBOL res 160 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 160 208 0
FLAG 128 128 V1
FLAG 192 128 V2
FLAG -560 224 0
FLAG -560 96 0
FLAG -560 0 V1
FLAG -560 128 V2
TEXT 30 232 Left 2 !.tran 5
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG633.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nCharge Injection not included\nOff Isolation is -92.5dB at 1MHz\nOnly one channel included\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG633.asy)
R1 D 0 301
V2 SB 0 0
V5 +V 0 5
V1 SA 0 3
V4 -V 0 -5
C1 D 0 36p
V3 IN 0 PULSE(0 3 0 20n 20n 10u 20u)
XU1 IN SA D SB +V 0 0 -V ADG633 ;pnba IN)SA)D)SB)Vdd)GND)_EN)Vss
.tran 100u
.lib ADG633.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1728 -272 -1920 -272
WIRE -1696 -272 -1728 -272
WIRE -1920 -256 -1920 -272
WIRE -1472 -240 -1504 -240
WIRE -1408 -240 -1472 -240
WIRE -1296 -240 -1408 -240
WIRE -1408 -224 -1408 -240
WIRE -1296 -224 -1296 -240
WIRE -1728 -208 -1840 -208
WIRE -1696 -208 -1728 -208
WIRE -1840 -192 -1840 -208
WIRE -1920 -160 -1920 -176
WIRE -1728 -144 -1760 -144
WIRE -1696 -144 -1728 -144
WIRE -1472 -144 -1504 -144
WIRE -1472 -128 -1472 -144
WIRE -1408 -128 -1408 -144
WIRE -1296 -128 -1296 -160
WIRE -1840 -96 -1840 -112
WIRE -1760 -80 -1760 -144
WIRE -1664 -16 -1664 -32
WIRE -1536 -16 -1536 -32
WIRE -1760 32 -1760 0
SYMBOL voltage -1760 -96 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 20n 20n 10u 20u)
SYMATTR InstName V3
SYMBOL ADG633 -1600 -192 R0
SYMATTR InstName U1
SYMBOL res -1424 -240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -1840 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL cap -1312 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -2144 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL voltage -1920 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL voltage -2048 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -5
FLAG -1920 -160 0
FLAG -1840 -96 0
FLAG -1760 32 0
FLAG -1600 -368 +V
FLAG -1408 -128 0
FLAG -1536 -16 0
FLAG -1296 -128 0
FLAG -2048 -64 0
FLAG -2048 -144 -V
FLAG -1472 -128 0
FLAG -2144 -64 0
FLAG -2144 -144 +V
FLAG -1664 -16 -V
FLAG -1728 -272 SA
FLAG -1728 -208 SB
FLAG -1728 -144 IN
FLAG -1472 -240 D
TEXT -1360 -40 Left 2 !.tran 100u
TEXT -2160 -472 Left 2 ;Note:\nCharge Injection not included\nOff Isolation is -92.5dB at 1MHz\nOnly one channel included\nSwitch shown for a logic 0 input