* Z:\home\khalils\Downloads\files\data\raw_asc\189866f3481a_2932.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N005 N006 53.6K
R2 N006 0 47.5K
V1 N002 0 PWL(500u 5 600u 5 600.001u 4.6161 900u 4.6161 901u 5)
V2 N001 0 5
XU1 NC_01 N001 NC_02 N003 N001 N002 NC_03 _RST 0 N001 0 0 N006 N005 N001 N001 NC_04 N004 N001 NC_05 LTC2932 ;pnba COMP5)V5)COMP3)COMP1)V3)V1)CRT)_RST)T0)_RDIS)T1)GND)VPG)Vref)V4)V2)COMP4)COMP2)V6)COMP6
R3 N001 _RST 1K
R4 N001 N003 1K
R5 N001 N004 1K
.tran 1600u startup uic
* Transient Duration vs Comparator Overdrive (V1, V2) Test Jig\nThis circuit is for injecting variable lenght and duration pulses that are\nbelow the typical 5V comparator threshold on V1. The actual threshold here\nhas been found to be about 4.6557V. \n \nTo measure the transient duration before _RST is asserted a below threshold\npulse is driven into V1 and the time between that falling edge and the falling /RST\nedge is measured.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2932.asy)
.lib LTC2932.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 920 748
WIRE 448 -96 48 -96
WIRE 544 -96 448 -96
WIRE 640 -96 544 -96
WIRE 448 -80 448 -96
WIRE 544 -80 544 -96
WIRE 640 -80 640 -96
WIRE -480 16 -528 16
WIRE 64 16 -400 16
WIRE 448 16 448 0
WIRE 448 16 400 16
WIRE 48 64 48 -96
WIRE 48 64 -64 64
WIRE 64 64 48 64
WIRE 544 64 544 0
WIRE 544 64 400 64
WIRE -64 80 -64 64
WIRE 48 112 48 64
WIRE 64 112 48 112
WIRE 48 160 48 112
WIRE 64 160 48 160
WIRE -64 176 -64 160
WIRE 48 208 48 160
WIRE 64 208 48 208
WIRE 48 256 48 208
WIRE 64 256 48 256
WIRE 48 320 48 256
WIRE 64 320 48 320
WIRE 544 320 400 320
WIRE 640 320 640 0
WIRE 640 320 544 320
WIRE 64 368 48 368
WIRE 416 368 400 368
WIRE 528 368 496 368
WIRE 64 416 48 416
WIRE 528 416 528 368
WIRE 528 416 400 416
WIRE 528 432 528 416
WIRE 176 480 176 464
WIRE 528 528 528 512
FLAG 176 480 0
FLAG 528 528 0
FLAG -64 176 0
FLAG -528 16 0
FLAG 48 416 0
FLAG 48 368 0
FLAG 544 320 _RST
SYMBOL res 400 384 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 53.6K
SYMBOL res 512 416 R0
SYMATTR InstName R2
SYMATTR Value 47.5K
SYMBOL voltage -384 16 R90
WINDOW 3 32 56 VTop 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PWL(500u 5 600u 5 600.001u 4.6161 900u 4.6161 901u 5)
SYMATTR InstName V1
SYMBOL voltage -64 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL LTC2932 224 160 R0
SYMATTR InstName U1
SYMBOL res 624 -96 R0
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL res 432 -96 R0
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL res 528 -96 R0
SYMATTR InstName R5
SYMATTR Value 1K
TEXT 648 496 Left 2 !.tran 1600u startup uic
TEXT -304 -304 Left 2 ;Transient Duration vs Comparator Overdrive (V1, V2) Test Jig\nThis circuit is for injecting variable lenght and duration pulses that are\nbelow the typical 5V comparator threshold on V1.  The actual threshold here\nhas been found to be about 4.6557V.  \n \nTo measure the transient duration before _RST is asserted a below threshold\npulse is driven into V1 and the time between that falling edge and the falling /RST\nedge is measured.