* Z:\home\khalils\Downloads\files\data\raw_asc\8c90125a3474_Project_2.asc
* Generated by LTspice 26.0.1 for Windows.
*------------ Power Supply-----------
* Bias Circuit
*------------ Input Signals ------------
* --- Simulation Commands ---
* ~-For DC sweep-~
*.dc Vin_p -0.02 0.02 0.0001
* -~AC analysis-~
* .ac dec 10 1 100meg
* ~- Transient ~-:
* .tran 0.01u 10u
M2 Y inn N001 N001 NMOS_05 W=1500u L=0.5u
M9 N002 vb1 N003 N003 NMOS_05 W=97u L=0.5u
IREF2 iref2 vss 100u
M5 out vb2 Y Y PMOS_05 W=200u L=0.5u
Mb1 iref1 iref1 vss vss NMOS_05 W=10u L=0.5u
Vb1 vb1 0 DC -2.05
IREF3 vdd iref3 100u
M11 N001 iref1 vss vss NMOS_05 W=130u L=0.5u
M1 X inp N001 N001 NMOS_05 W=1500u L=0.5u
M8 N003 iref3 vss vss NMOS_05 W=100u L=0.5u
VSS vss 0 DC -3.0
R1 out 0 250k tol=0
M4 Y iref2 vdd vdd PMOS_05 W=150u L=0.5u
M7 out vb1 N004 N004 NMOS_05 W=97u L=0.5u
M6 N002 vb2 X X PMOS_05 W=200u L=0.5u
Mb2_src iref2 iref2 vdd vdd PMOS_05 W=15u L=0.5u
IREF1 vdd iref1 100u
Mb3_sink iref3 iref3 vss vss NMOS_05 W=10u L=0.5u
C1 out 0 10pF
M10 N004 iref3 vss vss NMOS_05 W=100u L=0.5u
M3 X iref2 vdd vdd PMOS_05 W=150u L=0.5u
Vin_p inp 0 DC 0 AC 1 PULSE(-1 1 1u 10n 10n 5u 10u)
Vb2 vb2 0 DC 1.7
VDD vdd 0 DC 3.0
Vin_n inn 0 DC 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model NMOS_05 nmos level=1 vto=0.7 kp=134u gamma=0.45 phi=0.9 lambda=0.1
.model PMOS_05 pmos level=1 vto=-0.8 kp=38u gamma=0.45 phi=0.9 lambda=0.2
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2412 680
WIRE 1008 -448 992 -448
WIRE 1024 -448 1008 -448
WIRE 848 -416 816 -416
WIRE 1008 -416 1008 -448
WIRE 1008 -416 848 -416
WIRE 1184 -416 1008 -416
WIRE 1552 -416 1184 -416
WIRE 848 -368 848 -416
WIRE 848 -368 832 -368
WIRE 1184 -368 1184 -416
WIRE 1184 -368 1168 -368
WIRE 1552 -368 1552 -416
WIRE 1568 -368 1552 -368
WIRE 1504 -352 1488 -352
WIRE 896 -336 896 -352
WIRE 1232 -336 1232 -352
WIRE 1232 -336 896 -336
WIRE 1488 -336 1488 -352
WIRE 1488 -336 1232 -336
WIRE 832 -320 832 -368
WIRE 848 -320 832 -320
WIRE 1168 -320 1168 -368
WIRE 1184 -320 1168 -320
WIRE 1568 -320 1568 -368
WIRE 1568 -320 1552 -320
WIRE 848 -240 848 -272
WIRE 848 -240 272 -240
WIRE 1488 -240 1488 -336
WIRE 1552 -240 1552 -272
WIRE 1552 -240 1488 -240
WIRE 1184 -224 1184 -272
WIRE 1184 -224 592 -224
WIRE 1824 -208 1008 -208
WIRE 848 -192 848 -240
WIRE 848 -192 832 -192
WIRE 1184 -192 1184 -224
WIRE 1200 -192 1184 -192
WIRE 896 -160 896 -176
WIRE 1008 -160 1008 -208
WIRE 1008 -160 896 -160
WIRE 1136 -160 1136 -176
WIRE 1136 -160 1008 -160
WIRE 832 -144 832 -192
WIRE 848 -144 832 -144
WIRE 864 -144 848 -144
WIRE 1200 -144 1200 -192
WIRE 1200 -144 1184 -144
WIRE 1024 -32 992 -32
WIRE 1104 -32 1024 -32
WIRE 1184 -32 1184 -96
WIRE 1184 -32 1104 -32
WIRE 1552 -32 1552 -240
WIRE 1024 -16 1024 -32
WIRE 1104 -16 1104 -32
WIRE 1024 96 1024 64
WIRE 1072 96 1024 96
WIRE 1104 96 1104 48
WIRE 1104 96 1072 96
WIRE 1072 112 1072 96
WIRE 272 160 272 -240
WIRE 592 160 592 -224
WIRE 224 208 160 208
WIRE 288 208 272 208
WIRE 592 208 576 208
WIRE 848 224 848 -96
WIRE 1184 224 1184 -32
WIRE 224 240 224 208
WIRE 288 256 288 208
WIRE 288 256 272 256
WIRE 432 256 288 256
WIRE 576 256 576 208
WIRE 576 256 432 256
WIRE 592 256 576 256
WIRE 848 272 832 272
WIRE 1200 272 1184 272
WIRE 1008 288 896 288
WIRE 1136 288 1008 288
WIRE 896 304 896 288
WIRE 1136 304 1136 288
WIRE 832 320 832 272
WIRE 848 320 832 320
WIRE 1200 320 1200 272
WIRE 1200 320 1184 320
WIRE -16 336 -16 288
WIRE 32 336 -16 336
WIRE 640 336 640 240
WIRE 640 336 160 336
WIRE 1008 336 1008 288
WIRE 1824 336 1008 336
WIRE 1552 352 1552 160
WIRE 1552 352 1504 352
WIRE -16 368 -16 336
WIRE 432 368 432 256
WIRE 848 368 848 320
WIRE 1184 368 1184 320
WIRE 1552 368 1552 352
WIRE -16 416 -32 416
WIRE 32 416 32 336
WIRE 384 416 32 416
WIRE 448 416 432 416
WIRE 848 416 832 416
WIRE 1184 416 1168 416
WIRE 1568 416 1552 416
WIRE 1232 432 896 432
WIRE 1504 432 1504 352
WIRE 1504 432 1232 432
WIRE 32 448 32 416
WIRE 384 448 384 416
WIRE 896 448 896 432
WIRE 1232 448 1232 432
WIRE 1504 448 1504 432
WIRE -32 464 -32 416
WIRE -16 464 -32 464
WIRE 448 464 448 416
WIRE 448 464 432 464
WIRE 832 464 832 416
WIRE 848 464 832 464
WIRE 1168 464 1168 416
WIRE 1184 464 1168 464
WIRE 1568 464 1568 416
WIRE 1568 464 1552 464
WIRE -16 544 -16 464
WIRE 432 544 432 464
WIRE 432 544 -16 544
WIRE 848 544 848 464
WIRE 848 544 432 544
WIRE 976 544 848 544
WIRE 1184 544 1184 464
WIRE 1184 544 976 544
WIRE 1552 544 1552 464
WIRE 1552 544 1184 544
WIRE 976 592 976 544
WIRE 976 592 960 592
WIRE 992 592 976 592
SYMBOL nmos4 224 160 R0
SYMATTR InstName M1
SYMATTR Value NMOS_05
SYMATTR Value2 W=1500u L=0.5u
SYMBOL pmos4 1232 -272 R180
SYMATTR InstName M4
SYMATTR Value PMOS_05
SYMATTR Value2 W=150u L=0.5u
SYMBOL nmos4 896 224 M0
SYMATTR InstName M9
SYMATTR Value NMOS_05
SYMATTR Value2 W=97u L=0.5u
SYMBOL nmos4 896 368 M0
SYMATTR InstName M8
SYMATTR Value NMOS_05
SYMATTR Value2 W=100u L=0.5u
SYMBOL pmos4 1504 -272 M180
SYMATTR InstName Mb2_src
SYMATTR Value PMOS_05
SYMATTR Value2 W=15u L=0.5u
SYMBOL nmos4 32 368 M0
SYMATTR InstName Mb1
SYMATTR Value NMOS_05
SYMATTR Value2 W=10u L=0.5u
SYMBOL nmos4 1504 368 R0
SYMATTR InstName Mb3_sink
SYMATTR Value NMOS_05
SYMATTR Value2 W=10u L=0.5u
SYMBOL nmos4 1136 224 R0
SYMATTR InstName M7
SYMATTR Value NMOS_05
SYMATTR Value2 W=97u L=0.5u
SYMBOL pmos4 896 -272 R180
SYMATTR InstName M3
SYMATTR Value PMOS_05
SYMATTR Value2 W=150u L=0.5u
SYMBOL nmos4 1232 368 M0
SYMATTR InstName M10
SYMATTR Value NMOS_05
SYMATTR Value2 W=100u L=0.5u
SYMBOL nmos4 384 368 R0
SYMATTR InstName M11
SYMATTR Value NMOS_05
SYMATTR Value2 W=130u L=0.5u
SYMBOL nmos4 640 160 M0
SYMATTR InstName M2
SYMATTR Value NMOS_05
SYMATTR Value2 W=1500u L=0.5u
SYMBOL pmos4 896 -96 R180
SYMATTR InstName M6
SYMATTR Value PMOS_05
SYMATTR Value2 W=200u L=0.5u
SYMBOL cap 1088 -16 R0
SYMATTR InstName C1
SYMATTR Value 10pF
SYMBOL res 1008 -32 R0
SYMATTR InstName R1
SYMATTR Value 250k
SYMATTR SpiceLine tol=0
SYMBOL pmos4 1136 -96 M180
SYMATTR InstName M5
SYMATTR Value PMOS_05
SYMATTR Value2 W=200u L=0.5u
FLAG -16 288 iref1
FLAG 976 592 vss
FLAG 1008 -448 vdd
FLAG 1552 160 iref3
FLAG 160 208 inp
FLAG 160 336 inn
FLAG 848 -240 X
FLAG 1184 -224 Y
FLAG 1072 112 0
FLAG 992 -32 out
FLAG 1552 -32 iref2
FLAG 1824 336 vb1
FLAG 1824 -208 vb2
TEXT -616 -648 Left 2 !.model NMOS_05 nmos level=1 vto=0.7 kp=134u gamma=0.45 phi=0.9 lambda=0.1\n.model PMOS_05 pmos level=1 vto=-0.8 kp=38u gamma=0.45 phi=0.9 lambda=0.2\n \n*------------ Power Supply----------- \nVDD vdd 0 DC 3.0\nVSS vss 0 DC -3.0\nVb1 vb1 0 DC -2.05\nVb2 vb2 0 DC 1.7\n \n \n* Bias Circuit\nIREF1 vdd iref1 100u\nIREF2 iref2 vss 100u\nIREF3 vdd iref3 100u\n \n*------------ Input Signals ------------\nVin_p inp 0 DC 0 AC 1 PULSE(-1 1 1u 10n 10n 5u 10u)\nVin_n inn 0 DC 0
TEXT -616 -88 Left 2 !* --- Simulation Commands ---\n.op\n \n* ~-For DC sweep-~\n*.dc Vin_p -0.02 0.02 0.0001\n \n* -~AC analysis-~\n* .ac dec 10 1 100meg\n \n* ~- Transient ~-:\n* .tran 0.01u 10u