Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2d660fed7918_6600-10.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\FilterProducts\LT6600-10.asy)
R3 N002 N004 200
R2 N005 N007 200
E2 0 N002 N001 0 .5
V3 0 N009 2.5
E1 N003 0 N001 0 .5
C1 N005 N004 82p
V1 N008 0 2.5
R4 N003 N005 200
XU1 N006 0 N008 N010 N011 N009 0 N007 LT6600-10 ;pnba IM)VOCM)VCC)OP)OM)VEE)VMID)IP
V2 N001 0 PULSE(0 .5 300n 10n 10n 50u 100u)
R1 N004 N006 200
.tran 900n
.lib LT6600-10.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2436 800
WIRE 1056 -16 1024 -16
WIRE 1424 -16 1136 -16
WIRE 1600 -16 1424 -16
WIRE 1376 32 1376 16
WIRE 1424 32 1424 -16
WIRE 1552 32 1552 16
WIRE 1600 32 1600 -16
WIRE 1360 80 1296 80
WIRE 1488 80 1488 48
WIRE 1488 80 1440 80
WIRE 1536 80 1488 80
WIRE 1664 80 1616 80
WIRE 1296 96 1296 80
WIRE 1664 96 1664 80
WIRE 1296 192 1296 176
WIRE 1440 192 1296 192
WIRE 1664 192 1664 176
WIRE 1664 192 1504 192
WIRE 1296 208 1296 192
WIRE 1664 208 1664 192
WIRE 1296 304 1296 288
WIRE 1376 304 1296 304
WIRE 1664 304 1664 288
WIRE 1664 304 1600 304
WIRE 1376 384 1344 384
WIRE 1632 384 1600 384
WIRE 1264 464 1248 464
WIRE 1376 464 1344 464
WIRE 1616 464 1600 464
WIRE 1712 464 1696 464
WIRE 1376 544 1344 544
WIRE 1632 544 1600 544
SYMBOL LT6600-10 1488 432 R0
SYMATTR InstName U1
SYMBOL res 1280 192 R0
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL e 1456 80 R90
WINDOW 0 -23 25 VLeft 2
WINDOW 3 32 26 VLeft 2
SYMATTR InstName E2
SYMATTR Value .5
SYMBOL res 1280 80 R0
SYMATTR InstName R3
SYMATTR Value 200
SYMBOL voltage 1712 464 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
SYMATTR InstName V3
SYMATTR Value 2.5
SYMBOL res 1648 80 R0
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL voltage 1360 464 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL cap 1504 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 82p
SYMBOL res 1648 192 R0
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL voltage 1152 -16 R90
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
SYMATTR Value PULSE(0 .5 300n 10n 10n 50u 100u)
SYMATTR InstName V2
SYMBOL e 1632 80 R90
WINDOW 0 -25 24 VLeft 2
WINDOW 3 20 20 VLeft 2
SYMATTR InstName E1
SYMATTR Value .5
FLAG 1248 464 0
FLAG 1024 -16 0
FLAG 1376 16 0
FLAG 1552 16 0
FLAG 1712 464 0
FLAG 1488 48 0
FLAG 1344 384 0
FLAG 1632 384 0
TEXT 1720 576 Left 2 !.tran 900n
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG5212.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vS 0 SINE(0 10 20)
R1 vD 0 301
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
C1 vD 0 36p
V3 v+ 0 15
V4 v- 0 -15
XU1 vIN vD vS v- 0 v+ ADG5212 ;pnba IN)D)S)Vss)GND)Vdd
.tran 1
* Note:\nSwitch shown for a logic 0 input\nQinj not included\nOn resistance modeled at 15V supplies\nOny one channel is modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG5212.asy)
.lib ADG5212.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 240 144 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE 304 416 304 400
WIRE 176 432 176 400
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 304 416 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -288 304 v+
FLAG 240 112 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -192 304 v-
FLAG 176 432 v-
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 20)
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL ADG5212 240 272 R0
SYMATTR InstName U1
TEXT 80 528 Left 2 !.tran 1
TEXT -320 -8 Left 2 ;Note:\nSwitch shown for a logic 0 input\nQinj not included\nOn resistance modeled at 15V supplies\nOny one channel is modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\LT5400-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Misc\LT5400-1.asy)
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1468.asy)
XU2 N002 N001 +V -V OUT LT1468 ;pnba In+)In-)V+)V-)OUT
V3 IN 0 AC 1
V2 -V 0 -15
V1 +V 0 15
XU1 OUT IN 0 0 N002 N002 N001 N001 NC_01 LT5400-1 ;pnba 1)2)3)4)5)6)7)8)PAD
C1 N001 OUT 4.7p
C2 N002 0 4.7p
.ac oct 10 1K 10Meg
.lib LT5400-1.sub
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1472
WIRE 2304 624 1936 624
WIRE 1936 688 1936 624
WIRE 2016 688 1936 688
WIRE 2192 688 2080 688
WIRE 1936 816 1936 688
WIRE 1952 816 1936 816
WIRE 2192 816 2192 688
WIRE 2192 816 2144 816
WIRE 1952 880 1744 880
WIRE 2192 880 2192 816
WIRE 2192 880 2144 880
WIRE 1392 896 1392 880
WIRE 1520 896 1520 880
WIRE 1744 896 1744 880
WIRE 2192 896 2192 880
WIRE 2208 896 2192 896
WIRE 2304 912 2304 624
WIRE 2304 912 2272 912
WIRE 2336 912 2304 912
WIRE 2208 928 2192 928
WIRE 1952 944 1936 944
WIRE 2192 944 2192 928
WIRE 2192 944 2144 944
WIRE 1392 992 1392 976
WIRE 1520 992 1520 976
WIRE 1744 992 1744 976
WIRE 1920 1008 1872 1008
WIRE 1952 1008 1920 1008
WIRE 2192 1008 2192 944
WIRE 2192 1008 2144 1008
WIRE 1920 1120 1920 1008
WIRE 2016 1120 1920 1120
WIRE 2192 1120 2192 1008
WIRE 2192 1120 2080 1120
SYMBOL voltage 1392 880 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 1520 880 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL cap 2080 1104 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7p
SYMBOL misc\\LT5400-1 2048 912 R0
SYMATTR InstName U1
SYMBOL opamps\\LT1468 2240 848 R0
SYMATTR InstName U2
SYMBOL voltage 1744 880 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL cap 2080 672 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.7p
FLAG 2240 880 +V
FLAG 2240 944 -V
FLAG 2336 912 OUT
FLAG 1520 992 0
FLAG 1520 880 +V
FLAG 1392 992 0
FLAG 1392 880 -V
FLAG 1744 992 0
FLAG 1744 880 IN
FLAG 1872 1008 0
FLAG 1936 944 0
TEXT 2312 1064 Left 2 !.ac oct 10 1K 10Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1773.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1773.asy)
V1 IN 0 5
C1 OUT 0 180 Rser=.1
MQ1 N005 N002 N001 N001 FDC638P
L1 N005 OUT 5
XU1 N004 N003 IN N006 0 N007 N002 IN N001 N005 LTC1773 ;pnba Ith)Run/SS)FCB)FB)GND)BG)TG)Vin)Sense-)SW
R2 0 N006 80.6K
C3 N004 0 220p Rser=30K
R3 IN N001 .025
MQ2 N005 N007 0 0 IRF7201
R1 OUT N006 169K
Rload OUT 0 2
C4 N003 0 .001
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1m startup
.lib LTC1773.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2908 1472
WIRE 1632 896 1504 896
WIRE 1824 896 1632 896
WIRE 2064 896 1824 896
WIRE 1504 912 1504 896
WIRE 2064 912 2064 896
WIRE 1824 944 1824 896
WIRE 1504 1008 1504 992
WIRE 1632 1008 1632 896
WIRE 1664 1008 1632 1008
WIRE 2064 1008 2064 992
WIRE 2064 1008 1984 1008
WIRE 2064 1024 2064 1008
WIRE 2016 1040 2000 1040
WIRE 1584 1072 1568 1072
WIRE 1664 1072 1648 1072
WIRE 2000 1072 2000 1040
WIRE 2000 1072 1984 1072
WIRE 1504 1136 1472 1136
WIRE 1664 1136 1568 1136
WIRE 2064 1136 2064 1120
WIRE 2064 1136 1984 1136
WIRE 2112 1136 2064 1136
WIRE 2240 1136 2192 1136
WIRE 2352 1136 2240 1136
WIRE 2464 1136 2352 1136
WIRE 2064 1152 2064 1136
WIRE 2240 1152 2240 1136
WIRE 2352 1152 2352 1136
WIRE 2464 1152 2464 1136
WIRE 1664 1200 1632 1200
WIRE 2000 1200 1984 1200
WIRE 2000 1232 2000 1200
WIRE 2016 1232 2000 1232
WIRE 2240 1248 2240 1232
WIRE 2240 1248 2160 1248
WIRE 2352 1248 2352 1216
WIRE 2464 1248 2464 1232
WIRE 2064 1264 2064 1248
WIRE 2240 1264 2240 1248
WIRE 1824 1280 1824 1264
WIRE 1632 1312 1632 1200
WIRE 2160 1312 2160 1248
WIRE 2160 1312 1632 1312
WIRE 2240 1360 2240 1344
SYMBOL VOLTAGE 1504 896 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL RES 2048 896 R0
SYMATTR InstName R3
SYMATTR Value .025
SYMBOL cap 1568 1120 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 39 56 34 VTop 2
SYMATTR InstName C3
SYMATTR Value 220p
SYMATTR SpiceLine Rser=30K
SYMBOL RES 2224 1136 R0
SYMATTR InstName R1
SYMATTR Value 169K
SYMBOL POWERPRODUCTS\\LTC1773 1824 1104 R0
WINDOW 3 -45 67 Left 2
SYMATTR InstName U1
SYMBOL res 2224 1360 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 80.6K
SYMBOL cap 1648 1056 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value .001
SYMBOL NMOS 2016 1152 R0
SYMATTR InstName Q2
SYMATTR Value IRF7201
SYMBOL polcap 2336 1152 R0
SYMATTR SpiceLine Rser=.1
SYMATTR InstName C1
SYMATTR Value 180
SYMBOL ind 2096 1152 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5
SYMBOL res 2448 1136 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL PMOS 2016 1120 M180
WINDOW 0 60 79 Left 2
WINDOW 3 58 47 Left 2
SYMATTR InstName Q1
SYMATTR Value FDC638P
FLAG 1824 1280 0
FLAG 2240 1360 0
FLAG 2352 1248 0
FLAG 1504 1008 0
FLAG 2464 1248 0
FLAG 2464 1136 OUT
FLAG 2064 1264 0
FLAG 1472 1136 0
FLAG 1568 1072 0
FLAG 1504 896 IN
TEXT 2360 1328 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\10b4692862b3_AM-FM-signals-sources.asc
* Generated by LTspice 26.0.1 for Windows.
* How to generate AM and FM modulated signal for RF testing
B1 FM_modulated_output 0 V=sin(V(modulating_signal)*3.14158*2*time)
B2 AM_modulated_output 0 V=V(modulating_signal)*sin(50*3.14158*2*time)
V1 modulating_signal 0 SINE(10 10 1)
.tran 0 5 0 0.1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1576 680
WIRE 32 176 32 96
WIRE 352 176 352 96
WIRE 960 192 960 112
WIRE 32 320 32 256
WIRE 352 320 352 256
WIRE 960 336 960 272
SYMBOL bv 352 160 R0
SYMATTR InstName B1
SYMATTR Value V=sin(V(modulating_signal)*3.14158*2*time)
SYMBOL voltage 32 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(10 10 1)
SYMBOL bv 960 176 R0
SYMATTR InstName B2
SYMATTR Value V=V(modulating_signal)*sin(50*3.14158*2*time)
FLAG 32 320 0
FLAG 352 320 0
FLAG 32 96 modulating_signal
FLAG 960 336 0
FLAG 352 96 FM_modulated_output
FLAG 960 112 AM_modulated_output
TEXT 1088 384 Left 2 !.tran 0 5 0 0.1m
TEXT 440 -264 Left 4 ;How to generate AM and FM modulated signal for RF testing
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1083-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1083-12.asy)
Rload OUT 0 20
V1 IN 0 PWL(0 0 1 15) Rser=0.1
XU1 0 OUT IN LT1083-12 ;pnba GND)OUT)IN
C1 OUT 0 10
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1904 896 1808 896
WIRE 2016 896 1904 896
WIRE 1344 912 1344 896
WIRE 2016 912 2016 896
WIRE 1904 928 1904 896
WIRE 1344 1008 1344 992
WIRE 1904 1008 1904 992
WIRE 2016 1008 2016 992
WIRE 1680 1024 1680 992
SYMBOL PowerProducts\\LT1083-12 1680 896 R0
SYMATTR InstName U1
SYMBOL cap 1888 928 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL RES 2000 896 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 15)
SYMATTR SpiceLine Rser=0.1
FLAG 2016 896 OUT
FLAG 2016 1008 0
FLAG 1344 1008 0
FLAG 1904 1008 0
FLAG 1344 896 IN
FLAG 1680 1024 0
TEXT 1920 1064 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1421.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1421.asy)
V3 N001 0 10
C1 N002 0 35p
XU1 N003 N002 N001 -V 0 +V ADG1421 ;pnba IN)D)S)Vss)GND)Vdd
V1 +V 0 15
R1 N002 0 300
V2 -V 0 -15
V4 N003 0 pulse(0 3.3 0 1u 1u 5m 10m)
.tran 30m
.lib ADG1421.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -112 -112 -112 -128
WIRE -448 -80 -448 -96
WIRE -304 -48 -336 -48
WIRE -208 -48 -224 -48
WIRE 16 -48 -16 -48
WIRE 112 -48 16 -48
WIRE 16 -16 16 -48
WIRE 112 0 112 -48
WIRE -448 16 -448 0
WIRE -208 16 -304 16
WIRE 16 80 16 64
WIRE 112 80 112 64
WIRE -304 96 -304 16
WIRE -448 112 -448 96
WIRE -160 144 -160 128
WIRE -64 144 -64 128
WIRE -448 208 -448 192
WIRE -304 240 -304 176
SYMBOL voltage -208 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -448 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL cap 96 0 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL ADG1421 -112 0 R0
SYMATTR InstName U1
SYMBOL voltage -448 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -304 80 R0
WINDOW 3 19 116 Left 2
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMATTR InstName V4
SYMBOL res 0 -32 R0
SYMATTR InstName R1
SYMATTR Value 300
FLAG -448 208 0
FLAG -448 16 0
FLAG -448 -96 +V
FLAG -448 96 -V
FLAG -336 -48 0
FLAG -160 144 -V
FLAG -112 -128 +V
FLAG -64 144 0
FLAG -304 240 0
FLAG 16 80 0
FLAG 112 80 0
TEXT 8 248 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1086.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1086.asy)
XU1 N001 OUT IN LT1086 ;pnba ADJ)OUT)IN
Rload OUT 0 10
R2 N001 0 365
C1 OUT 0 10
R1 OUT N001 121
V1 IN 0 PWL(0 0 1 10) Rser=0.1
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1856 896 1808 896
WIRE 1952 896 1856 896
WIRE 2064 896 1952 896
WIRE 1344 912 1344 896
WIRE 1856 912 1856 896
WIRE 1952 912 1952 896
WIRE 2064 912 2064 896
WIRE 1344 1008 1344 992
WIRE 1952 1008 1952 976
WIRE 2064 1008 2064 992
WIRE 1680 1024 1680 992
WIRE 1856 1024 1856 992
WIRE 1856 1024 1680 1024
WIRE 1856 1040 1856 1024
WIRE 1856 1136 1856 1120
SYMBOL cap 1936 912 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL RES 1840 1024 R0
SYMATTR InstName R2
SYMATTR Value 365
SYMBOL RES 2048 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL RES 1840 896 R0
SYMATTR InstName R1
SYMATTR Value 121
SYMBOL PowerProducts\\LT1086 1680 896 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
FLAG 2064 896 OUT
FLAG 1856 1136 0
FLAG 2064 1008 0
FLAG 1344 1008 0
FLAG 1952 1008 0
FLAG 1344 896 IN
TEXT 1960 1096 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\0f54e9a3181f_Nand2.asc
* Generated by LTspice 26.0.1 for Windows.
M4 VDD N001 NAND VDD PMOS l=1u w=10u
M2 N002 N001 N003 0 NMOS l=1u w=10u
V1 N001 0 PULSE(0 1 1n 10p 10p 20n 40n)
M3 NAND N001 N002 0 NMOS l=1u w=10u
V2 VDD 0 PULSE(0 1 1n 10p 10p 10n 20n)
M6 VDD N001 NAND VDD PMOS l=1u w=10u
M1 N003 N001 0 0 NMOS l=1u w=10u
M5 VDD N001 NAND VDD PMOS l=1u w=10u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.tran 0 100n 0 1p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE 256 -160 96 -160
WIRE 512 -160 480 -160
WIRE 752 -160 720 -160
WIRE 96 -128 96 -160
WIRE 480 -128 480 -160
WIRE 480 -128 96 -128
WIRE 720 -128 720 -160
WIRE 720 -128 480 -128
WIRE 304 -96 304 -144
WIRE 560 -96 560 -144
WIRE 560 -96 304 -96
WIRE 800 -96 800 -144
WIRE 800 -96 560 -96
WIRE 928 -96 800 -96
WIRE 256 -16 208 -16
WIRE 96 48 96 -128
WIRE 96 48 0 48
WIRE 208 48 208 -16
WIRE 208 48 96 48
WIRE 304 64 304 0
WIRE 208 144 208 48
WIRE 256 144 208 144
WIRE 304 224 304 160
WIRE 208 304 208 144
WIRE 256 304 208 304
IOPIN 928 -96 Out
SYMBOL voltage 0 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 1n 10p 10p 20n 40n)
SYMBOL pmos4 256 -240 R0
WINDOW 123 75 -34 Left 2
SYMATTR InstName M4
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 752 -240 R0
WINDOW 123 74 -33 Left 2
SYMATTR InstName M6
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 256 -96 R0
WINDOW 123 57 100 Left 2
SYMATTR InstName M3
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 512 -240 R0
WINDOW 123 76 -34 Left 2
SYMATTR InstName M5
SYMATTR Value2 l=1u w=10u
SYMBOL voltage 640 0 R0
WINDOW 3 35 76 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 1n 10p 10p 10n 20n)
SYMBOL nmos4 256 64 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=1u w=10u
SYMBOL nmos4 256 224 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=1u w=10u
FLAG 304 112 0
FLAG 304 272 0
FLAG 304 -48 0
FLAG 640 96 0
FLAG 0 128 0
FLAG 304 320 0
FLAG 640 16 VDD
FLAG 304 -192 VDD
FLAG 560 -192 VDD
FLAG 800 -192 VDD
FLAG 800 -240 VDD
FLAG 560 -240 VDD
FLAG 304 -240 VDD
FLAG 928 -96 NAND
TEXT 720 120 Left 2 !.include cmosedu_models.txt
TEXT -48 344 Left 2 !.tran 0 100n 0 1p
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3595.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N002 N001 QTLP690C N=5
L1 N001 N004 100
C1 IN N001 .47
V1 IN 0 30
XU1 N003 IN N002 N004 0 N005 N007 N003 N006 LT3595 ;pnba _SHDN)Vin)L1)SW1)GND)Rset)PWM1)Vcc)_OpenLED
V2 N003 0 3.3
R1 0 N005 30.1K
R2 N006 N003 100K
V3 N007 0 PULSE(0 3.3 0 1u 1u 50u 100u)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 300u startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3595.asy)
.lib LT3595.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1000 804
WIRE 208 -32 0 -32
WIRE 240 -32 208 -32
WIRE 336 -32 304 -32
WIRE 496 -32 336 -32
WIRE 0 -16 0 -32
WIRE 336 -16 336 -32
WIRE 496 0 496 -32
WIRE 208 64 208 -32
WIRE 336 64 336 48
WIRE 0 80 0 64
WIRE 0 128 -96 128
WIRE 112 128 0 128
WIRE 496 128 496 80
WIRE 496 128 432 128
WIRE -96 144 -96 128
WIRE 0 208 0 128
WIRE 112 208 0 208
WIRE 448 208 432 208
WIRE 544 208 528 208
WIRE -96 240 -96 224
WIRE 0 288 0 208
WIRE 16 288 0 288
WIRE 112 288 96 288
WIRE 592 288 432 288
WIRE 704 288 672 288
WIRE 272 368 272 352
FLAG 272 368 0
FLAG 0 80 0
FLAG 0 -32 IN
FLAG -96 240 0
FLAG 544 208 0
FLAG 704 288 0
SYMBOL LED 320 48 M180
WINDOW 0 23 62 Left 2
WINDOW 3 25 3 Left 2
WINDOW 123 84 37 Left 2
SYMATTR InstName D1
SYMATTR Value QTLP690C
SYMATTR Value2 N=5
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL ind 480 -16 R0
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL cap 240 -16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value .47
SYMBOL voltage 0 -32 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL PowerProducts\\LT3595 272 208 R0
SYMATTR InstName U1
SYMBOL voltage -96 128 R0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 544 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 30.1K
SYMBOL res 112 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL voltage 576 288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 3.3 0 1u 1u 50u 100u)
TEXT 504 400 Left 2 !.tran 300u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-4.5.asy)
C1 OUT 0 10
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-4.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
V1 IN 0 3.3
Rload OUT 0 50
L1 N001 N002 1.5 Rser=80m
.tran 400u startup
.lib ADP2504-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ADP2504-4.5 176 176 R0
SYMATTR InstName U1
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG 480 224 OUT
FLAG -64 64 IN
TEXT 432 376 Left 2 !.tran 400u startup
TEXT 160 -8 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\tmp\asc_dec_bjh7r6w2\05b4f1c04374_Diodeless_Precision_Rectifier_1_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N002 0 1k
R4 N002 Vout 2k
R5 U1vin 0 1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -96 96 -176 96
WIRE 64 96 -16 96
WIRE 128 96 64 96
WIRE 160 96 128 96
WIRE 272 96 240 96
WIRE 304 96 272 96
WIRE -320 128 -320 96
WIRE 64 128 64 96
WIRE 32 176 -96 176
WIRE -176 192 -176 96
WIRE 64 224 64 208
WIRE 192 240 192 224
WIRE -32 256 -32 240
WIRE 128 256 128 96
WIRE 160 256 128 256
WIRE -96 272 -96 176
WIRE -64 272 -96 272
WIRE 272 272 272 96
WIRE 272 272 224 272
WIRE 32 288 32 176
WIRE 32 288 0 288
WIRE 112 288 32 288
WIRE 160 288 112 288
WIRE -176 304 -176 272
WIRE -64 304 -176 304
WIRE -320 320 -320 304
WIRE 112 320 112 288
WIRE -176 336 -176 304
WIRE -176 432 -176 416
SYMBOL res 48 112 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 144 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 2k
SYMBOL res -192 320 R0
SYMATTR InstName R5
SYMATTR Value 1k
FLAG 64 224 0
FLAG -176 432 0
FLAG -320 208 0
FLAG -320 400 0
FLAG -320 304 Vcc
FLAG 304 96 Vout
FLAG 192 304 0
FLAG -32 320 0
FLAG 192 224 Vcc
FLAG -32 240 Vcc
FLAG -176 304 U1vin