* Z:\home\khalils\Downloads\files\data\raw_asc\18d245cd7ad5_hw6_prob1.asc
* Generated by LTspice 26.0.1 for Windows.
* HW6, Problem 1\nFind V0(t), t > 0
* IMPORTANT!!!\ndo not change anything else in this verification\ntestbench besides A, B, and c (note that c is 1/tau)
* error tolerance for this problem (note that all problems on this \nassignment have their own unique error tolerance):\n \n0.05\n \nafter running the simulation, view the spice error log (ctrl-L) and \nnote the maxerror value; if your maxerror is less than or equal to\n0.05, then your solution is acceptable; else if maxerror is larger than\n0.05, then your solution for A, B, and/or c is incorrect, and you should \nwork to resolve the issues prior to submitting
* verify your part (a) by-hand sketch in 2 ways:\n \n1) plot trace V(voutcheck) and compare to your by-hand sketch in part (a);\n V(voutcheck) is what your sketch should look like given the A, B, c values \n you supplied here in the testbench; if there are discrepencies, then you are\n not sketching your waveform properly with the A, B, c values you entered;\n resolve issues here first, before moving on to the 2nd plot verification below\n \n2) plot traces V(vout) and V(voutcheck) on the same plot and compare them;\n V(vout) is what the correct sketch should look like, so if these two plots do \n not agree very well, then that means your A, B, and/or c values are incorrect,\n and you should work to resolve any issues before submitting
;enter your solution values here:
L1 N003 vout 36m Rser=0
R4 0 N002 30
V1 N002 N003 0
R3 N001 0 8
R2 N002 N001 12
R5 0 vout 6
B1 voutcheck 0 V=A+B*exp(-(time*c))
.options plotwinsize=0 numdgt=15 measdgt=15
.ic I(L1)=2.5
.tran 20m
.meas tran maxerror max abs(V(vout)-V(voutcheck))
.param A=0 B=15 c=500
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1564 1204
WIRE -400 -192 -464 -192
WIRE -256 -192 -320 -192
WIRE -192 -192 -256 -192
WIRE -64 -192 -112 -192
WIRE 80 -192 16 -192
WIRE 96 -192 80 -192
WIRE -464 -80 -464 -192
WIRE -256 -80 -256 -192
WIRE 96 -80 96 -192
WIRE -464 48 -464 0
WIRE -256 48 -256 0
WIRE -256 48 -464 48
WIRE -224 48 -256 48
WIRE 96 48 96 0
WIRE 96 48 -224 48
WIRE -224 80 -224 48
WIRE -576 368 -656 368
WIRE -544 368 -576 368
WIRE -656 400 -656 368
WIRE -656 544 -656 480
SYMBOL res -480 -96 R0
SYMATTR InstName R3
SYMATTR Value 8
SYMBOL res -304 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 12
SYMBOL ind -80 -176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 36m
SYMATTR SpiceLine Rser=0
SYMBOL res 112 16 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R5
SYMATTR Value 6
SYMBOL bv -656 384 R0
SYMATTR InstName B1
SYMATTR Value V=A+B*exp(-(time*c))
SYMBOL voltage -208 -192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL res -240 16 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 30
FLAG -224 80 0
FLAG 80 -192 vout
FLAG -656 544 0
FLAG -576 368 voutcheck
TEXT 944 480 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ic I(L1)=2.5\n.tran 20m\n.meas tran maxerror max abs(V(vout)-V(voutcheck))
TEXT -648 -400 Left 2 ;HW6, Problem 1\nFind V0(t), t > 0
TEXT 944 264 Left 2 !;enter your solution values here:\n.param A=0 B=15 c=500
TEXT 944 136 Left 2 ;IMPORTANT!!!\ndo not change anything else in this verification\ntestbench besides A, B, and c (note that c is 1/tau)
TEXT -88 336 Left 2 ;error tolerance for this problem (note that all problems on this \nassignment have their own unique error tolerance):\n \n0.05\n \nafter running the simulation, view the spice error log (ctrl-L) and \nnote the maxerror value; if your maxerror is less than or equal to\n0.05, then your solution is acceptable; else if maxerror is larger than\n0.05, then your solution for A, B, and/or c is incorrect, and you should \nwork to resolve the issues prior to submitting
TEXT 632 -400 Left 2 ;verify your part (a) by-hand sketch in 2 ways:\n \n1) plot trace V(voutcheck) and compare to your by-hand sketch in part (a);\n     V(voutcheck) is what your sketch should look like given the A, B, c values \n     you supplied here in the testbench; if there are discrepencies, then you are\n     not sketching your waveform properly with the A, B, c values you entered;\n     resolve issues here first, before moving on to the 2nd plot verification below\n \n2) plot traces V(vout) and V(voutcheck) on the same plot and compare them;\n     V(vout) is what the correct sketch should look like, so if these two plots do \n     not agree very well, then that means your A, B, and/or c values are incorrect,\n     and you should work to resolve any issues before submitting