* Z:\home\khalils\Downloads\files\data\raw_asc\1d7b288d6132_Ideal_3_bit_DAC.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Vtrip 0 100Meg
R2 VDD Vtrip 100Meg
S7 B2L Vone B2 Vtrip switmod
S8 0 B2L Vtrip B2 switmod
S13 B1L Vone B1 Vtrip switmod
S14 0 B1L Vtrip B1 switmod
S15 B0L Vone B0 Vtrip switmod
S16 0 B0L Vtrip B0 switmod
B1 Vout 0 V=((v(vrefp)-v(vrefm))/8)*(v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)
R3 Vrefp Vrefm 100Meg
Vone Vone 0 1
.model switmod SW
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2732 1316
WIRE 1408 -208 1408 -256
WIRE 528 -192 528 -256
WIRE 1360 -192 1312 -192
WIRE 320 -176 208 -176
WIRE 320 -144 320 -176
WIRE 1360 -144 1312 -144
WIRE 1408 -96 1408 -128
WIRE 1536 -96 1408 -96
WIRE 1568 -96 1536 -96
WIRE 528 -80 528 -112
WIRE 608 -80 528 -80
WIRE 640 -80 608 -80
WIRE 1408 -80 1408 -96
WIRE 1360 -64 1312 -64
WIRE 528 -48 528 -80
WIRE 320 -16 320 -64
WIRE 320 -16 208 -16
WIRE 1360 -16 1312 -16
WIRE 1776 -16 1616 -16
WIRE 1616 32 1616 -16
WIRE 1408 48 1408 0
WIRE 528 96 528 32
WIRE 1616 176 1616 112
WIRE 944 192 944 144
WIRE 1408 192 1408 144
WIRE 896 208 848 208
WIRE 1360 208 1312 208
WIRE 368 224 192 224
WIRE 896 256 848 256
WIRE 1360 256 1312 256
WIRE 368 272 192 272
WIRE 480 272 480 208
WIRE 944 304 944 272
WIRE 1072 304 944 304
WIRE 1104 304 1072 304
WIRE 1408 304 1408 272
WIRE 1536 304 1408 304
WIRE 1568 304 1536 304
WIRE 368 320 192 320
WIRE 944 320 944 304
WIRE 1408 320 1408 304
WIRE 896 336 848 336
WIRE 1360 336 1312 336
WIRE 896 384 848 384
WIRE 1360 384 1312 384
WIRE 480 416 480 352
WIRE 944 448 944 400
WIRE 1408 448 1408 400
FLAG 608 -80 Vtrip
FLAG 528 -256 VDD
IOPIN 528 -256 In
FLAG 848 208 B2
FLAG 848 256 Vtrip
FLAG 848 336 Vtrip
FLAG 848 384 B2
FLAG 1072 304 B2L
FLAG 944 448 0
FLAG 1312 -192 B1
FLAG 1312 -144 Vtrip
FLAG 1312 -64 Vtrip
FLAG 1312 -16 B1
FLAG 1536 -96 B1L
FLAG 1408 48 0
FLAG 1312 208 B0
FLAG 1312 256 Vtrip
FLAG 1312 336 Vtrip
FLAG 1312 384 B0
FLAG 1536 304 B0L
FLAG 1408 448 0
FLAG 1616 176 0
FLAG 1776 -16 Vout
IOPIN 1776 -16 Out
FLAG 208 -176 Vrefp
IOPIN 208 -176 In
FLAG 208 -16 Vrefm
IOPIN 208 -16 In
FLAG 192 224 B2
IOPIN 192 224 In
FLAG 192 272 B1
IOPIN 192 272 In
FLAG 192 320 B0
IOPIN 192 320 In
FLAG 528 96 0
FLAG 480 416 0
FLAG 480 208 Vone
FLAG 944 144 Vone
FLAG 1408 -256 Vone
FLAG 1408 144 Vone
SYMBOL res 512 -64 R0
SYMATTR InstName R1
SYMATTR Value 100MEG
SYMBOL res 512 -208 R0
SYMATTR InstName R2
SYMATTR Value 100MEG
SYMBOL sw 944 288 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S7
SYMBOL sw 944 416 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S8
SYMBOL sw 1408 -112 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S13
SYMBOL sw 1408 16 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S14
SYMBOL sw 1408 288 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S15
SYMBOL sw 1408 416 M180
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S16
SYMBOL bv 1616 16 R0
WINDOW 123 24 132 Left 0
SYMATTR InstName B1
SYMATTR Value V=((v(vrefp)-v(vrefm))/8)*(v(B2L)*4+v(B1L)*2+v(B0L))+v(vrefm)
SYMBOL res 304 -160 R0
SYMATTR InstName R3
SYMATTR Value 100MEG
SYMBOL voltage 480 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vone
SYMATTR Value 1
TEXT 120 64 Left 0 !.model switmod SW