* Z:\home\khalils\Downloads\files\data\raw_asc\058ed4f42be8_Fig18_20.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 Vinm N003 0 N_50n l=50n w=500n
Vinp Vinp 0 PULSE(100mV 300mV 5n 5n 5n 5n 20n)
VDD VDD 0 1
M3 VDD N001 N001 VDD P_50n l=50n w=1u
M4 VDD N001 N002 VDD P_50n l=50n w=1u
M2 N002 Vinp N003 0 N_50n l=50n w=500n
Vinm Vinm 0 200m
M6 N003 N001 0 0 N_50n l=50n w=500n
M5 VDD N002 Vout VDD P_50n l=50n w=1u
M7 Vout N002 0 0 N_50n l=50n w=500n
Cload Vout 0 50f
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 30n 0 10p
.lib cmosedu_models.txt
* Plot Vout Vinp Vinm
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1496 680
WIRE 224 -544 224 -560
WIRE 224 -528 224 -544
WIRE 224 -416 224 -448
WIRE 240 -272 240 -288
WIRE 240 -176 240 -192
WIRE 304 -400 304 -416
WIRE 304 -304 304 -320
WIRE 576 -544 576 -592
WIRE 576 -432 576 -448
WIRE 576 -416 576 -432
WIRE 576 -288 576 -320
WIRE 688 -464 624 -464
WIRE 688 -432 576 -432
WIRE 688 -432 688 -464
WIRE 688 -192 688 -432
WIRE 704 -192 688 -192
WIRE 752 -288 576 -288
WIRE 752 -272 752 -288
WIRE 752 -144 752 -176
WIRE 880 -464 688 -464
WIRE 928 -544 928 -592
WIRE 928 -432 928 -448
WIRE 928 -416 928 -432
WIRE 928 -288 752 -288
WIRE 928 -288 928 -320
WIRE 1136 -432 928 -432
WIRE 1136 -432 1136 -480
WIRE 1136 -320 1136 -432
WIRE 1184 -560 1184 -608
WIRE 1184 -432 1184 -464
WIRE 1184 -400 1184 -432
WIRE 1184 -256 1184 -304
WIRE 1232 -432 1184 -432
WIRE 1392 -432 1232 -432
WIRE 1392 -336 1392 -368
FLAG 240 -176 0
FLAG 240 -288 Vinp
FLAG 576 -368 0
FLAG 224 -416 0
FLAG 224 -544 VDD
FLAG 576 -496 VDD
FLAG 752 -144 0
FLAG 576 -592 VDD
FLAG 928 -496 VDD
FLAG 928 -368 0
FLAG 928 -592 VDD
FLAG 304 -304 0
FLAG 304 -416 Vinm
FLAG 752 -224 0
FLAG 528 -336 Vinm
FLAG 976 -336 Vinp
FLAG 1184 -512 VDD
FLAG 1184 -608 VDD
FLAG 1184 -352 0
FLAG 1184 -256 0
FLAG 1232 -432 Vout
FLAG 1392 -336 0
SYMBOL nmos4 528 -416 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 240 -288 R0
WINDOW 0 34 41 Left 0
WINDOW 3 26 119 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vinp
SYMATTR Value PULSE(100mV 300mV 5n 5n 5n 5n 20n)
SYMBOL voltage 224 -544 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 624 -544 M0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 880 -544 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 976 -416 M0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M2
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 304 -416 R0
WINDOW 0 25 19 Left 0
WINDOW 3 27 91 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vinm
SYMATTR Value 200m
SYMBOL nmos4 704 -272 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M6
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 1136 -560 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 1136 -400 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M7
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL cap 1376 -432 R0
SYMATTR InstName Cload
SYMATTR Value 50f
TEXT 320 -144 Left 0 !.tran 0 30n 0 10p
TEXT 320 -120 Left 0 !.lib cmosedu_models.txt
TEXT 240 -616 Left 0 ;Plot Vout Vinp Vinm