Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3009-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3009-5.asy)
C1 OUT 0 1
Rload OUT 0 500
XU1 IN OUT MP_01 0 IN LT3009-5 ;pnba IN)OUT))GND)_SHDN
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 416 48 320 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT3009-5 176 96 R0
SYMATTR InstName U1
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 400 224 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3204-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3204-3.3.asy)
C1 N001 N002 2.2
XU1 0 IN OUT N001 N002 IN LTC3204-3.3 ;pnba GND)Vin)Vout)C+)C-)_SHDN
Rload OUT 0 100
C2 OUT 0 2.2
V1 IN 0 2.4
.tran 1m startup
.lib LTC3204-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 160 -96 160
WIRE 16 160 0 160
WIRE 384 160 272 160
WIRE 480 160 384 160
WIRE -96 176 -96 160
WIRE 384 176 384 160
WIRE 480 176 480 160
WIRE 0 240 0 160
WIRE 16 240 0 240
WIRE 304 240 272 240
WIRE 384 272 384 240
WIRE 480 272 480 256
WIRE -96 288 -96 256
WIRE 16 320 0 320
WIRE 304 320 304 304
WIRE 304 320 272 320
SYMBOL PowerProducts\\LTC3204-3.3 144 240 R0
SYMATTR InstName U1
SYMBOL res 464 160 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 288 240 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL cap 368 176 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL voltage -96 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.4
FLAG 384 272 0
FLAG 480 272 0
FLAG 0 320 0
FLAG -96 288 0
FLAG -96 160 IN
FLAG 480 160 OUT
TEXT 384 320 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0dc8747d0803_sim.asc
* Generated by LTspice 26.0.1 for Windows.
L2 N003 N004 0.19217
L1 N002 N003 1.255
C1 N003 0 0.55285
RL N004 0 1
V1 N001 0 AC 1
RG N002 N001 1
.ac dec 1000 0.01 10
.net I(RL) V1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -352 144 -400 144
WIRE -144 144 -272 144
WIRE 16 144 -64 144
WIRE 96 144 16 144
WIRE 320 144 176 144
WIRE -400 192 -400 144
WIRE 16 192 16 144
WIRE 320 224 320 144
WIRE -400 320 -400 272
WIRE 16 320 16 256
WIRE 16 320 -400 320
WIRE 320 320 320 304
WIRE 320 320 16 320
WIRE 320 368 320 320
RECTANGLE Normal 272 352 -192 48 2
SYMBOL cap 0 192 R0
SYMATTR InstName C1
SYMATTR Value 0.55285
SYMBOL ind 80 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.19217
SYMBOL voltage -400 176 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL ind -160 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1.255
SYMBOL res 304 208 R0
SYMATTR InstName RL
SYMATTR Value 1
SYMBOL res -256 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG
SYMATTR Value 1
FLAG 320 368 0
TEXT -382 358 Left 2 !.ac dec 1000 0.01 10
TEXT -384 392 Left 2 !.net I(RL) V1
* Z:\home\khalils\Downloads\files\data\raw_asc\d24df8f1fa09_osc_impedance.asc
* Generated by LTspice 26.0.1 for Windows.
* Run ".ac analysis" and plot "Z", (Vgate/I(I1)), in "cartesion coordinate" mode.\nNote that as {R} is decreased, the real part of Z becomes more and more negative.\nAs {R} is further decreased, the real part of Z becomes more positive. A this point,\nthe oscillator fails to start.\nRun ".transient analysis" to see what effect decreasing {R} has on oscillator startup.
;tran 0 50uS 0S 200pS
C2 N002 0 31.8pF
V1 N001 0 9V
R2 Vgate 0 {R}
I2 N002 0 1mA
J1 N001 Vgate N002 MPF102
L2 Vgate 0 159nH Rser=0
C1 Vgate N002 31.8pF
I1 0 Vgate AC 1uA
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.ac oct 10k 98e6 102e6
.step param R 3k 1.5k 500
.meas ac Re find re(V(vgate)/I(I1)) at 100e6
.meas ac Im find im(V(vgate)/I(I1)) at 100e6
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 884
WIRE -736 416 -736 272
WIRE -736 624 -736 496
WIRE -656 272 -736 272
WIRE -656 272 -656 208
WIRE -576 272 -656 272
WIRE -576 416 -576 272
WIRE -576 624 -736 624
WIRE -576 624 -576 496
WIRE -432 272 -576 272
WIRE -432 416 -432 272
WIRE -432 624 -576 624
WIRE -432 624 -432 496
WIRE -304 272 -432 272
WIRE -304 304 -304 272
WIRE -304 416 -304 368
WIRE -304 480 -304 416
WIRE -304 624 -432 624
WIRE -304 624 -304 544
WIRE -224 272 -304 272
WIRE -176 208 -176 176
WIRE -176 416 -304 416
WIRE -176 416 -176 304
WIRE -176 480 -176 416
WIRE -176 624 -304 624
WIRE -176 624 -176 560
WIRE 0 176 -176 176
WIRE 0 288 0 176
WIRE 0 624 -176 624
WIRE 0 624 0 368
WIRE 0 656 0 624
SYMBOL cap -320 304 R0
SYMATTR InstName C1
SYMATTR Value 31.8pF
SYMBOL njf -224 208 R0
SYMATTR InstName J1
SYMATTR Value MPF102
SYMBOL current -176 480 R0
WINDOW 123 24 116 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 43 47 Left 0
SYMATTR Value 1mA
SYMATTR InstName I2
SYMBOL res -592 400 R0
SYMATTR InstName R2
SYMATTR Value {R}
SYMBOL cap -320 480 R0
SYMATTR InstName C2
SYMATTR Value 31.8pF
SYMBOL ind -448 400 R0
SYMATTR InstName L2
SYMATTR Value 159nH
SYMATTR SpiceLine Rser=0
SYMBOL current -736 496 R180
WINDOW 123 -101 105 Left 0
WINDOW 3 24 88 Invisible 0
SYMATTR Value2 AC 1uA
SYMATTR Value ""
SYMATTR InstName I1
SYMBOL voltage 0 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9V
FLAG 0 656 0
FLAG -656 208 Vgate
TEXT -1000 224 Left 0 !;tran 0 50uS 0S 200pS
TEXT -1000 272 Left 0 !.ac oct 10k 98e6 102e6
TEXT -1024 320 Left 0 !.step param R 3k 1.5k 500
TEXT -816 -80 Left 0 ;Run ".ac analysis" and plot "Z", (Vgate/I(I1)), in "cartesion coordinate" mode.\nNote that as {R} is decreased, the real part of Z becomes more and more negative.\nAs {R} is further decreased, the real part of Z becomes more positive. A this point,\nthe oscillator fails to start.\nRun ".transient analysis" to see what effect decreasing {R} has on oscillator startup.
TEXT -1336 392 Left 0 !.meas ac Re find re(V(vgate)/I(I1)) at 100e6\n.meas ac Im find im(V(vgate)/I(I1)) at 100e6
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7150-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7150-3.3.asy)
V1 IN 0 6.2
C1 N004 0 10 Rser=10m Lser=1n
C2 N002 0 1
R3 IN N001 100K
C3 OUT 0 10
XU1 N004 OUT N002 0 N003 N003 N001 IN ADM7150-3.3 ;pnba Vreg)Vout)Byp)GND)Ref_Sense)Ref)EN)Vin
R5 OUT 0 18
C4 N003 0 1
.tran 5m startup
.lib ADM7150-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 856
WIRE -32 32 -160 32
WIRE 80 32 -32 32
WIRE 464 32 400 32
WIRE 560 32 464 32
WIRE -160 48 -160 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE -160 144 -160 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 0 224 -16 224
WIRE 80 224 64 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL res 544 32 R0
SYMATTR InstName R5
SYMATTR Value 18
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap 448 240 R0
WINDOW 0 36 14 Left 2
WINDOW 3 36 50 Left 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR Value2 Rser=10m
SYMATTR SpiceLine Lser=1n
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL ADM7150-3.3 240 176 R0
SYMATTR InstName U1
SYMBOL voltage -160 32 R0
SYMATTR InstName V1
SYMATTR Value 6.2
SYMBOL cap 448 48 R0
SYMATTR InstName C3
SYMATTR Value 10
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG -16 224 0
FLAG -160 144 0
FLAG 560 144 0
FLAG -160 32 IN
FLAG 560 32 OUT
TEXT 552 448 Left 2 !.tran 5m startup
* Z:\tmp\asc_dec_bjh7r6w2\07ab3c1e79b8_Assignment_4b__i__dec0.asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 N001 1N4148
D3 N002 N001 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 448 64 144 64
WIRE 144 80 144 64
WIRE 144 80 -16 80
WIRE 304 80 144 80
WIRE 304 112 304 80
WIRE -16 128 -16 80
WIRE 448 192 448 64
WIRE -16 240 -16 192
WIRE 64 240 -16 240
WIRE 144 240 64 240
WIRE 304 240 304 176
WIRE 304 240 224 240
WIRE 64 272 64 240
WIRE 304 272 304 240
WIRE -16 288 -16 240
WIRE -16 384 -16 352
WIRE 144 384 -16 384
WIRE 304 384 304 336
WIRE 304 384 144 384
WIRE 144 400 144 384
WIRE 448 400 448 272
SYMBOL diode 0 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL diode 320 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value 1N4148
FLAG 64 272 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3460.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3460.asy)
L1 IN N001 22 Rpar=2K
C2 OUT N003 22p
R1 OUT N003 130K
XU1 N001 0 N003 N002 IN LT3460 ;pnba SW)GND)FB)_SHDN)Vin
D1 N001 OUT MBR0540
R2 N003 0 15K
R3 IN N002 10K
C1 OUT 0 1
V1 IN 0 5
C3 N002 0 .1
Rload OUT 0 171
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 500u startup
.lib LT3460.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2648 1624
WIRE 1536 1200 1440 1200
WIRE 1680 1200 1536 1200
WIRE 1728 1200 1680 1200
WIRE 1840 1200 1808 1200
WIRE 1888 1200 1840 1200
WIRE 2000 1200 1952 1200
WIRE 2096 1200 2000 1200
WIRE 2176 1200 2096 1200
WIRE 2256 1200 2176 1200
WIRE 1440 1216 1440 1200
WIRE 2256 1216 2256 1200
WIRE 2096 1232 2096 1200
WIRE 2176 1232 2176 1200
WIRE 1536 1248 1536 1200
WIRE 2000 1248 2000 1200
WIRE 1680 1280 1680 1200
WIRE 1840 1280 1840 1200
WIRE 1440 1312 1440 1296
WIRE 2176 1312 2176 1296
WIRE 2256 1312 2256 1296
WIRE 1536 1376 1536 1328
WIRE 1616 1376 1536 1376
WIRE 2000 1376 2000 1328
WIRE 2000 1376 1904 1376
WIRE 2096 1376 2096 1296
WIRE 2096 1376 2000 1376
WIRE 1536 1392 1536 1376
WIRE 2000 1392 2000 1376
WIRE 1536 1472 1536 1456
WIRE 1760 1488 1760 1472
WIRE 2000 1488 2000 1472
SYMBOL schottky 1888 1216 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBR0540
SYMBOL PowerProducts\\LT3460 1760 1376 R0
SYMATTR InstName U1
SYMBOL res 1984 1232 R0
SYMATTR InstName R1
SYMATTR Value 130K
SYMBOL cap 2160 1232 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 2240 1200 R0
SYMATTR InstName Rload
SYMATTR Value 171
SYMBOL cap 2080 1232 R0
SYMATTR InstName C2
SYMATTR Value 22p
SYMBOL cap 1520 1392 R0
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL ind 1712 1216 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 22
SYMATTR SpiceLine Rpar=2K
SYMBOL res 1520 1232 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL VOLTAGE 1440 1200 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 1984 1376 R0
SYMATTR InstName R2
SYMATTR Value 15K
FLAG 1760 1488 0
FLAG 1440 1312 0
FLAG 2176 1312 0
FLAG 2000 1488 0
FLAG 2256 1312 0
FLAG 1536 1472 0
FLAG 2256 1200 OUT
FLAG 1440 1200 IN
TEXT 2120 1472 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2139-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2139-1.2.asy)
Rload OUT 0 3
XU1 IN IN N001 OUT 0 IN ADP2139-x.x Rtop=112K ;pnba Vin)EN)SW)Vout)GND)Mode
C1 OUT 0 10
L1 N001 OUT 1 Rser=60m
V1 IN 0 5
.tran .5m startup
.lib ADP2139-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL ADP2139-1.2 352 224 R0
SYMATTR InstName U1
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 3
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 600 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\61d9b327f701_iNMOS.asc
* Generated by LTspice 26.0.1 for Windows.
* body diode
* snubber
* binary
* Ideal NMOS
* on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
* Drain
* Source
* Gate
* 2025-7-21
* <Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
D1 S N002 myD
L1 D N001 {esl}
C1 N003 S {csnb}
L2 D N002 {esl}
S1 S N001 G S SW_iNMOS
R1 D N003 {rsnb}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)
.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
.param ron=10m
.param esl=1f
.param rsnb=1k
.param csnb=10p
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1384 680
WIRE 288 -288 288 -320
WIRE 608 -288 288 -288
WIRE 928 -288 608 -288
WIRE 288 -240 288 -288
WIRE 608 -240 608 -288
WIRE 928 -192 928 -288
WIRE 288 -112 288 -160
WIRE 240 -96 96 -96
WIRE 608 -96 608 -160
WIRE 928 -80 928 -112
WIRE 240 -48 208 -48
WIRE 208 0 208 -48
WIRE 288 0 288 -32
WIRE 288 0 208 0
WIRE 288 80 288 0
WIRE 608 80 608 -32
WIRE 608 80 288 80
WIRE 928 80 928 -16
WIRE 928 80 608 80
WIRE 288 112 288 80
IOPIN 288 -320 BiDir
IOPIN 288 112 BiDir
IOPIN 96 -96 BiDir
SYMBOL sw 288 -16 M180
SYMATTR InstName S1
SYMATTR Value SW_iNMOS
SYMBOL res 912 -208 R0
SYMATTR InstName R1
SYMATTR Value {rsnb}
SYMBOL ind 592 -256 R0
SYMATTR InstName L2
SYMATTR Value {esl}
SYMBOL cap 912 -80 R0
SYMATTR InstName C1
SYMATTR Value {csnb}
SYMBOL diode 624 -32 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value myD
SYMBOL ind 272 -256 R0
SYMATTR InstName L1
SYMATTR Value {esl}
FLAG 288 -320 D
FLAG 288 112 S
FLAG 96 -96 G
TEXT 56 -440 Left 2 !.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)\n.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
TEXT 56 -568 Left 2 !.param ron=10m\n.param esl=1f\n.param rsnb=1k\n.param csnb=10p
TEXT 552 -320 Left 2 ;body diode
TEXT 888 -320 Left 2 ;snubber
TEXT 56 -120 Left 1 ;binary
TEXT 40 -624 Left 4 ;Ideal NMOS
TEXT 312 -568 Left 2 ;on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
TEXT 312 -344 Left 2 ;Drain
TEXT 312 136 Left 2 ;Source
TEXT 56 -64 Left 2 ;Gate
TEXT 1000 -624 Left 2 ;2025-7-21
TEXT 80 208 Left 2 ;<Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3035.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3035.asy)
Rload OUT 0 20
C1 N002 N004 0.1
C3 OUT 0 1
R2 N003 0 40.2K
C2 N001 0 1
V1 IN 0 3.6
R1 OUT N003 294K
XU1 N002 N004 0 IN OUT N003 IN N001 LTC3035 ;pnba CP)CM)GND)IN)OUT)ADJ)_SHDN)BIAS
.tran 5m startup
.lib LTC3035.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 128 -160 128
WIRE 0 128 -48 128
WIRE 272 128 256 128
WIRE 352 128 336 128
WIRE -160 144 -160 128
WIRE -48 208 -48 128
WIRE 0 208 -48 208
WIRE 336 208 256 208
WIRE 448 208 336 208
WIRE 544 208 448 208
WIRE 448 224 448 208
WIRE 544 224 544 208
WIRE -160 240 -160 224
WIRE 0 288 -64 288
WIRE 336 288 256 288
WIRE 336 304 336 288
WIRE 448 320 448 288
WIRE 544 320 544 304
WIRE -64 368 -64 352
WIRE 0 368 -64 368
WIRE 288 368 256 368
WIRE 336 400 336 384
SYMBOL PowerProducts\\LTC3035 128 256 R0
SYMATTR InstName U1
SYMBOL res 320 192 R0
SYMATTR InstName R1
SYMATTR Value 294K
SYMBOL res 528 208 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL cap 432 224 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 320 288 R0
SYMATTR InstName R2
SYMATTR Value 40.2K
SYMBOL voltage -160 128 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL cap 272 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap -80 288 R0
WINDOW 0 26 13 Left 2
SYMATTR InstName C1
SYMATTR Value 0.1
FLAG -160 240 0
FLAG 352 128 0
FLAG 288 368 0
FLAG 336 400 0
FLAG 544 320 0
FLAG 448 320 0
FLAG 544 208 OUT
FLAG -160 128 IN
TEXT 424 392 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\23f2b4f3a241_with_nmos.asc
* Generated by LTspice 26.0.1 for Windows.
* The voltage reading at IN must be equal to the voltage reading at OUT\n \nThis works quite well as long as the RLoad is relatively small (<10 Ohms)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
C1 N006 0 10n
Vs N002 0 12
R5 N007 N006 1K
C2 N007 0 10n
R1 N005 N004 100
RL N002 N003 8
M1 N003 N005 OUT OUT NMOS
R2 OUT N001 1K
V1 IN 0 SINE(0.1 0.1 1)
R4 OUT 0 1
R3 N006 IN 1K
XU1 N007 N001 N002 0 N004 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 10 0 0.01
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1176 680
WIRE 240 -272 16 -272
WIRE 528 -272 320 -272
WIRE 400 -176 400 -224
WIRE 400 -64 400 -96
WIRE 400 -64 128 -64
WIRE 400 -48 400 -64
WIRE 400 64 400 32
WIRE 128 112 128 -64
WIRE 16 128 16 -272
WIRE 96 128 16 128
WIRE 224 144 160 144
WIRE 352 144 304 144
WIRE -304 160 -368 160
WIRE -160 160 -224 160
WIRE -96 160 -160 160
WIRE 32 160 -16 160
WIRE 96 160 32 160
WIRE -368 192 -368 160
WIRE -160 192 -160 160
WIRE 32 192 32 160
WIRE 400 192 400 160
WIRE 448 192 400 192
WIRE 528 192 528 -272
WIRE 528 192 448 192
WIRE 128 208 128 176
WIRE 400 224 400 192
WIRE -368 304 -368 272
WIRE -160 304 -160 256
WIRE -160 304 -368 304
WIRE 32 304 32 256
WIRE 32 304 -160 304
WIRE 400 336 400 304
WIRE -368 352 -368 304
SYMBOL res 384 -64 R0
SYMATTR InstName RL
SYMATTR Value 8
SYMBOL res -208 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL res 384 208 R0
SYMATTR InstName R4
SYMATTR Value 1
SYMBOL voltage 400 -80 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vs
SYMATTR Value 12
SYMBOL res 0 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL cap -176 192 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL nmos 352 64 R0
SYMATTR InstName M1
SYMBOL res 336 -288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL OpAmps\\UniversalOpAmp 128 144 R0
SYMATTR InstName U1
SYMBOL cap 16 192 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL Misc\\signal -368 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -70 80 Left 2
WINDOW 3 -214 45 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0.1 0.1 1)
SYMBOL res 320 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100
FLAG -368 352 0
FLAG 128 208 0
FLAG 400 -224 0
FLAG 400 336 0
FLAG -368 160 IN
FLAG 448 192 OUT
TEXT 32 520 Left 2 !.tran 0 10 0 0.01
TEXT -952 -120 Left 2 ;The voltage reading at IN must be equal to the voltage reading at OUT\n \nThis works quite well as long as the RLoad is relatively small (<10 Ohms)
* Z:\home\khalils\Downloads\files\data\raw_asc\a4d322905325_N2-mos.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 VG 0 0 nch l='Ltab' w='Wtab'
VDS N001 0 1.8
Vgs VG 0 0.5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib modely/cmos018.txt
.PARAM Ltab = table(n, 1,0.18u, 2,0.5u, 3,0.5u, 4,1u, 5,1u, 6,2u, 7,5u, 8,10u, 9,10u)
.PARAM Wtab = table(n, 1,0.22u, 2,1u, 3,2u, 4,2u, 5,5u, 6,5u, 7,10u, 8,10u, 9,40u)
.STEP param n 1 9 1
.MEAS DC VTH FIND V(VG) WHEN Id(m1)=1e-7*{Wtab/Ltab}
.dc VGS 0 1 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 224 64 -192 64
WIRE 224 144 224 64
WIRE 128 160 0 160
WIRE -192 192 -192 64
WIRE 0 192 0 160
WIRE 320 192 224 192
WIRE 128 224 128 160
WIRE 176 224 128 224
WIRE 224 256 224 240
WIRE 320 256 320 192
WIRE 320 256 224 256
WIRE 224 272 224 256
SYMBOL voltage 0 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vgs
SYMATTR Value 0.5
SYMBOL voltage -192 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 1.8
SYMBOL nmos4 176 144 R0
WINDOW 123 55 3 Left 2
SYMATTR Value2 l='Ltab' w='Wtab'
SYMATTR InstName M1
SYMATTR Value nch
FLAG 224 272 0
FLAG -192 272 0
FLAG 0 272 0
FLAG 128 160 VG
TEXT -200 -168 Left 2 !.lib modely/cmos018.txt
TEXT -200 -120 Left 2 !.PARAM Ltab = table(n, 1,0.18u, 2,0.5u, 3,0.5u, 4,1u, 5,1u, 6,2u, 7,5u, 8,10u, 9,10u)
TEXT -200 -96 Left 2 !.PARAM Wtab = table(n, 1,0.22u, 2,1u, 3,2u, 4,2u, 5,5u, 6,5u, 7,10u, 8,10u, 9,40u)
TEXT -200 -72 Left 2 !.STEP param n 1 9 1
TEXT -200 -48 Left 2 !.MEAS DC VTH FIND V(VG) WHEN Id(m1)=1e-7*{Wtab/Ltab}
TEXT -200 -144 Left 2 !.dc VGS 0 1 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\0296d0322a3d_6993-3.asc
* Generated by LTspice 26.0.1 for Windows.
* LTC6993-3 Non-Retriggerable 20ms One Shot\nFalling Edge Triggered, Positive Output Pulse\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6993-3.asy)
R1 N003 0 243K
R2 N002 N004 1000K
V2 N001 0 PULSE(0 3.3 0.25m 1n 1n 2m 15m 3)
XU1 N001 0 N003 N004 N002 OUT LTC6993-3 ;pnba TRIG)GND)SET)DIV)V+)OUT
R3 N004 0 392K
V1 N002 0 5
R4 OUT 0 100K
.tran 60m startup
.lib LTC6993-3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -224 96 -240 96
WIRE 96 96 -144 96
WIRE 656 96 320 96
WIRE 656 112 656 96
WIRE 96 176 64 176
WIRE 400 176 320 176
WIRE 560 176 400 176
WIRE 400 192 400 176
WIRE 560 192 560 176
WIRE 656 208 656 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 352 256 320 256
WIRE 352 288 352 256
WIRE 400 288 400 272
WIRE 400 288 352 288
WIRE 560 288 560 272
WIRE 400 304 400 288
WIRE 400 400 400 384
SYMBOL voltage -128 96 R90
WINDOW 123 74 56 VTop 0
WINDOW 39 53 56 VTop 0
WINDOW 3 32 56 VTop 0
WINDOW 0 -32 56 VBottom 0
SYMATTR Value PULSE(0 3.3 0.25m 1n 1n 2m 15m 3)
SYMATTR InstName V2
SYMBOL voltage 560 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL SpecialFunctions\\LTC6993-3 208 176 R0
SYMATTR InstName U1
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 243K
SYMBOL res 384 176 R0
SYMATTR InstName R2
SYMATTR Value 1000K
SYMBOL res 384 288 R0
SYMATTR InstName R3
SYMATTR Value 392K
SYMBOL res 640 96 R0
SYMATTR InstName R4
SYMATTR Value 100K
FLAG -240 96 0
FLAG 560 288 0
FLAG 656 96 OUT
FLAG 656 208 0
FLAG 400 400 0
FLAG -16 256 0
FLAG 64 176 0
TEXT 520 392 Left 0 !.tran 60m startup
TEXT 216 64 Bottom 0 ;LTC6993-3 Non-Retriggerable 20ms One Shot\nFalling Edge Triggered, Positive Output Pulse\nStartup Modeled