* Z:\home\khalils\Downloads\files\data\raw_asc\71f80225565f_crow_22nm_tech_scaling.asc
* Generated by LTspice 26.0.1 for Windows.
* Bitline to array0
* Bitline to array1
* Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
* Word line in array 0
* Word line in array 1
* .step param X 0.0v 1.5v 0.1v
* Word line in array 1
* DRAM Circuit Parameters
* ohm
* Bitline Resistance
* Cell Array
* Sense Amp.
* Voltage
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Word line in array 1
* Wordline Activation
* 1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
* Technology Scaling
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra1 ra1 0 PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
R2 bitline1 N002 {mc(bitline_R, process_var)}
cell_cap_8 mb8 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell7_charge}
R1 N001 bitline0 {mc(bitline_R, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n) Rser=2048 Cpar=0.6pF
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
CBL_cap_1 N002 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
Vra3 ra2 0 PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
Vra4 ra4 0 PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
Vra6 ra6 0 PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M13 N001 ra2 mb2 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vra8 ra8 0 PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
VDD_source1 PV 0 {plate_voltage}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n) Rser=2048 Cpar=0.6pf
cell_cap_5 mb5 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell4_charge}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M18 N001 ra8 mb8 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_4 mb4 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell3_charge}
cell_cap_3 mb2 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell2_charge}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
VDD_source2 VDDby2 0 {core_voltage/2}
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M8 N002 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
VDD_source VDD 0 {core_voltage}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
cell_cap_6 mb6 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell5_charge}
M7 N001 ra0 mb0 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_7 mb7 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell6_charge}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
M12 N001 ra1 mb1 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act}) Rser=100 Cpar=10fF
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act}) Rser=100 Cpar=10fF
M16 N001 ra6 mb6 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
M15 N001 ra5 mb5 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vra5 ra5 0 PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
Vra7 ra7 0 PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M17 N001 ra7 mb7 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M14 N001 ra4 mb4 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_1 mb1 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell1_charge}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include ../DRAM_models/transistor_model.pm
.tran 120ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=1024
.param core_voltage=0.95V
.param wordline_voltage=2.5V
.param cell0_charge=core_voltage*cells_charge_state
.param cell1_charge=core_voltage*cells_charge_state
.param cell2_charge=core_voltage*cells_charge_state
.param cell3_charge=core_voltage*cells_charge_state
.param cell4_charge=core_voltage*cells_charge_state
.param cell5_charge=core_voltage*cells_charge_state
.param cell6_charge=core_voltage*cells_charge_state
.param cell7_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param wl1_act=1.0
.param wl2_act=1.0
.param wl3_act=1.0
.param wl4_act=1.0
.param wl5_act=1.0
.param wl6_act=1.0
.param wl7_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.93**tech_node}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2320
WIRE 768 -4832 464 -4832
WIRE 464 -4800 464 -4832
WIRE 304 -4720 96 -4720
WIRE 416 -4720 304 -4720
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WIRE 464 -4464 464 -4496
WIRE 768 -4400 768 -4832
WIRE 768 -4400 464 -4400
WIRE 464 -4368 464 -4400
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WIRE 416 -4288 304 -4288
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WIRE 768 -3952 464 -3952
WIRE 464 -3920 464 -3952
WIRE 304 -3840 96 -3840
WIRE 416 -3840 304 -3840
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WIRE 464 -3232 464 -3248
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WIRE -512 -512 -512 -544
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WIRE 832 -512 832 -528
WIRE 832 -512 768 -512
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WIRE 1056 -352 1056 -368
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WIRE 768 -304 768 -320
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WIRE 944 -304 896 -304
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WIRE 1120 -304 1120 -416
WIRE 1120 -304 1072 -304
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WIRE 832 -192 768 -192
WIRE 912 -192 832 -192
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WIRE 1120 -192 1120 -288
WIRE 1120 -192 1040 -192
WIRE 832 -176 832 -192
WIRE 1040 -176 1040 -192
WIRE 1312 -144 1312 -224
WIRE 1360 -144 1312 -144
WIRE 912 -96 976 -192
WIRE 912 -96 880 -96
WIRE 976 -96 912 -192
WIRE 992 -96 976 -96
WIRE 1360 -96 1360 -144
WIRE 832 -48 832 -80
WIRE 832 -48 720 -48
WIRE 960 -48 832 -48
WIRE 1040 -48 1040 -80
WIRE 1040 -48 960 -48
WIRE 672 32 416 32
WIRE 1312 128 1312 -144
WIRE 1312 128 1200 128
WIRE 1200 160 1200 128
WIRE 1088 272 880 272
WIRE 1152 272 1152 240
WIRE 1152 272 1088 272
WIRE 1200 304 1200 256
WIRE 1200 320 1200 304
WIRE 1312 432 1312 128
SYMBOL voltage -1392 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pF
SYMBOL pmos4 992 -528 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL cap 448 -3232 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_5
SYMATTR SpiceLine IC={-plate_voltage + cell4_charge}
SYMBOL nmos4 1152 160 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -1584 -1152 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 416 -1952 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M12
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 576 -1360 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M7
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -800 -2624 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra8
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL pmos4 880 -528 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL nmos4 416 -3920 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M16
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1184 320 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL res 1296 -320 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -832 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL pmos4 640 -656 M180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL nmos4 800 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL voltage -512 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL cap 1344 -96 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL voltage -608 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=10fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act})
SYMATTR InstName Vsp
SYMBOL nmos4 416 -2464 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M13
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 816 -848 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL nmos4 880 -176 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL voltage -1104 -1136 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL nmos4 672 -48 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -240 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=10fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act})
SYMATTR InstName Vsn
SYMBOL nmos4 416 -4800 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M18
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -208 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 1008 -368 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL voltage -1456 -2592 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra7
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL cap 368 -1136 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL voltage -800 -2320 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra6
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL cap 448 -4128 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_7
SYMATTR SpiceLine IC={-plate_voltage + cell6_charge}
SYMBOL voltage -1456 -1952 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra4
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 992 -176 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 416 -4368 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M17
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -1456 -2320 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra5
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL voltage -832 -1952 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra3
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL cap 448 -1712 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_1
SYMATTR SpiceLine IC={-plate_voltage + cell1_charge}
SYMBOL nmos4 416 -3472 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M15
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 416 -2976 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M14
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 976 -352 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL cap 448 -2736 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_4
SYMATTR SpiceLine IC={-plate_voltage + cell3_charge}
SYMBOL res 752 -784 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL cap 448 -3680 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_6
SYMATTR SpiceLine IC={-plate_voltage + cell5_charge}
SYMBOL cap 448 -2224 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_3
SYMATTR SpiceLine IC={-plate_voltage + cell2_charge}
SYMBOL cap 448 -4560 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_8
SYMATTR SpiceLine IC={-plate_voltage + cell7_charge}
FLAG -1104 -1024 0
FLAG -1104 -1136 Eq
FLAG 720 0 0
FLAG -608 -1040 0
FLAG -608 -1184 sense_P
FLAG 1040 -128 0
FLAG 832 -128 0
FLAG 960 -416 0
FLAG 848 -304 0
FLAG 1024 -304 0
FLAG 640 -368 Eq
FLAG 944 -256 VDDby2
FLAG 416 32 sense_N
FLAG 720 48 0
FLAG 768 -320 bitline0
FLAG 1120 -288 bitline1
FLAG 624 -1312 0
FLAG 384 -1152 mb0
FLAG 304 -1280 ra0
FLAG 1200 208 0
FLAG 1200 384 0
FLAG 1200 304 mb3
FLAG 1088 272 ra3
FLAG -1392 -1552 0
FLAG -1392 -1664 ra0
FLAG 688 -704 VDD
FLAG 1040 -576 VDD
FLAG 832 -576 VDD
FLAG 688 -752 VDD
FLAG 432 -736 sense_p
FLAG 912 -656 ACT
FLAG 960 -48 NLAT
FLAG -240 -1040 0
FLAG -240 -1184 sense_N
FLAG -832 -1664 ra1
FLAG -832 -1552 0
FLAG 832 -784 0
FLAG 1360 -32 0
FLAG 464 -1904 0
FLAG 464 -1728 mb1
FLAG 304 -1872 ra1
FLAG -1584 -1152 ra3
FLAG -1584 -1040 0
FLAG -800 -512 0
FLAG -800 -656 VDD
FLAG -512 -512 0
FLAG -512 -656 VDDby2
FLAG -832 -1952 ra2
FLAG -832 -1840 0
FLAG 464 -2416 0
FLAG 464 -2240 mb2
FLAG 304 -2384 ra2
FLAG -1456 -1952 ra4
FLAG -1456 -1840 0
FLAG 464 -2928 0
FLAG 464 -2752 mb4
FLAG 304 -2896 ra4
FLAG -1456 -2320 ra5
FLAG -1456 -2208 0
FLAG 464 -3424 0
FLAG 464 -3248 mb5
FLAG 304 -3392 ra5
FLAG -800 -2320 ra6
FLAG -800 -2208 0
FLAG 464 -3872 0
FLAG 464 -3696 mb6
FLAG 304 -3840 ra6
FLAG -1456 -2592 ra7
FLAG -1456 -2480 0
FLAG 464 -4320 0
FLAG 464 -4144 mb7
FLAG 304 -4288 ra7
FLAG -800 -2624 ra8
FLAG -800 -2512 0
FLAG 464 -4752 0
FLAG 464 -4576 mb8
FLAG 304 -4720 ra8
FLAG 464 -4464 PV
FLAG 464 -4032 PV
FLAG 464 -3584 PV
FLAG 464 -3136 PV
FLAG 464 -2640 PV
FLAG 464 -2128 PV
FLAG 464 -1616 PV
FLAG 384 -976 PV
FLAG -208 -512 0
FLAG -208 -656 PV
TEXT -376 136 Left 2 !.include ../DRAM_models/transistor_model.pm
TEXT 800 -952 VLeft 2 ;Bitline to array0
TEXT 1296 96 VLeft 2 ;Bitline to array1
TEXT -448 104 Left 2 !.tran 120ns uic
TEXT -392 216 Left 2 ;Plot Eq, ra0, ra1, bitline0+1.25, bitline1+1.25, sense_n+2.5, and sense_p+3.75
TEXT 48 -1296 Left 2 ;Word line in array 0
TEXT 832 256 Left 2 ;Word line in array 1
TEXT -368 168 Left 2 ;.step param X 0.0v 1.5v 0.1v
TEXT 48 -1888 Left 2 ;Word line in array 1
TEXT -832 80 Left 2 !.param process_var=0.05
TEXT -832 40 Left 2 !.step param run 1 100 1
TEXT -832 456 Left 2 !.param cell_cap={24.0fF*cell_cap_factor}
TEXT -832 496 Left 2 !.param bitline_cap={85fF*bl_cap_factor}
TEXT -920 168 Left 2 ;DRAM Circuit Parameters
TEXT -832 536 Left 2 !.param access_tran_L={85nm*access_tran_L_factor}
TEXT -832 576 Left 2 !.param access_tran_W={55nm*access_tran_W_factor}
TEXT -816 1504 Left 2 !.param bitline_R=R_per_cell*cells_per_BL
TEXT -576 1440 Left 2 ;ohm
TEXT -816 1440 Left 2 !.param R_per_cell=40
TEXT -816 1408 Left 2 ;Bitline Resistance
TEXT -824 976 Left 2 !.param SA_nmos_L={160nm*SA_nmos_L_factor}
TEXT -824 1000 Left 2 !.param SA_nmos_W={1900nm*SA_nmos_W_factor}
TEXT -824 1032 Left 2 !.param SA_pmos_L={160nm*SA_pmos_L_factor}
TEXT -824 1056 Left 2 !.param SA_pmos_W={1330nm*SA_pmos_W_factor}
TEXT -824 1096 Left 2 !.param SA_eq_L=96.3nm
TEXT -824 1120 Left 2 !.param SA_eq_W=541nm
TEXT -824 1160 Left 2 !.param SA_nset_L={270nm*SA_nset_L_factor}
TEXT -824 1184 Left 2 !.param SA_nset_W={220nm*SA_nset_W_factor}
TEXT -824 1224 Left 2 !.param SA_pset_L={270nm*SA_pset_L_factor}
TEXT -824 1248 Left 2 !.param SA_pset_W={220nm*SA_pset_W_factor}
TEXT -816 1472 Left 2 !.param cells_per_BL=1024
TEXT -832 424 Left 2 ;Cell Array
TEXT -824 944 Left 2 ;Sense Amp.
TEXT -832 224 Left 2 ;Voltage
TEXT -832 248 Left 2 !.param core_voltage=0.95V
TEXT -832 288 Left 2 !.param wordline_voltage=2.5V
TEXT -832 616 Left 2 !.param cell0_charge=core_voltage*cells_charge_state
TEXT -832 656 Left 2 !.param cell1_charge=core_voltage*cells_charge_state
TEXT -832 688 Left 2 !.param cell2_charge=core_voltage*cells_charge_state
TEXT 48 -2400 Left 2 ;Word line in array 1
TEXT -832 720 Left 2 !.param cell3_charge=core_voltage*cells_charge_state
TEXT 48 -2912 Left 2 ;Word line in array 1
TEXT -832 752 Left 2 !.param cell4_charge=core_voltage*cells_charge_state
TEXT 48 -3408 Left 2 ;Word line in array 1
TEXT -832 784 Left 2 !.param cell5_charge=core_voltage*cells_charge_state
TEXT 48 -3856 Left 2 ;Word line in array 1
TEXT -832 816 Left 2 !.param cell6_charge=core_voltage*cells_charge_state
TEXT 48 -4304 Left 2 ;Word line in array 1
TEXT -832 840 Left 2 !.param cell7_charge=core_voltage*cells_charge_state
TEXT 48 -4736 Left 2 ;Word line in array 1
TEXT -832 872 Left 2 !.param cells_charge_state=0.8
TEXT -832 320 Left 2 !.param pv_modifier=0.5
TEXT -832 360 Left 2 !.param plate_voltage={core_voltage*pv_modifier}
TEXT -824 1296 Left 2 !.param psense_act=4ns
TEXT -824 1320 Left 2 !.param nsense_act=4ns
TEXT -816 1568 Left 2 ;Wordline Activation
TEXT -816 1600 Left 2 !.param wl0_act=1.0
TEXT -816 1632 Left 2 !.param wl1_act=1.0
TEXT -816 1664 Left 2 !.param wl2_act=1.0
TEXT -816 1696 Left 2 !.param wl3_act=1.0
TEXT -816 1728 Left 2 !.param wl4_act=1.0
TEXT -816 1760 Left 2 !.param wl5_act=1.0
TEXT -816 1792 Left 2 !.param wl6_act=1.0
TEXT -816 1824 Left 2 !.param wl7_act=1.0
TEXT -816 1920 Left 2 !.param tech_node=7
TEXT -568 1920 Left 2 ;1 -> 45 nm, 4 -> 32nm, 7 -> 22 nm, 9-> 16nm
TEXT -816 1888 Left 2 ;Technology Scaling
TEXT -816 1952 Left 2 !.param cell_cap_factor={0.95**tech_node}
TEXT -816 1984 Left 2 !.param bl_cap_factor={0.95**tech_node}
TEXT -816 2016 Left 2 !.param access_tran_L_factor={0.95**tech_node}
TEXT -816 2048 Left 2 !.param access_tran_W_factor={0.85**tech_node}
TEXT -816 2080 Left 2 !.param SA_nmos_L_factor={0.93**tech_node}
TEXT -816 2104 Left 2 !.param SA_nmos_W_factor={0.93**tech_node}
TEXT -816 2136 Left 2 !.param SA_pmos_L_factor={0.93**tech_node}
TEXT -816 2160 Left 2 !.param SA_pmos_W_factor={0.93**tech_node}
TEXT -816 2192 Left 2 !.param SA_nset_L_factor={0.93**tech_node}
TEXT -816 2216 Left 2 !.param SA_nset_W_factor={0.93**tech_node}
TEXT -816 2248 Left 2 !.param SA_pset_L_factor={0.93**tech_node}
TEXT -816 2272 Left 2 !.param SA_pset_W_factor={0.93**tech_node}