Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1117.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1117.asy)
R3 N003 0 154
V1 N001 0 4.25
C1 N002 0 10 V=33 Irms=0 Rser=0.3 Lser=0 mfg="KEMET" pn="T495D106M035AS" type="Tantalum"
I1 N002 0 pulse(.1 .6 10u 1u 1u 50u 100u)
R2 N002 N003 121
XU1 N003 N002 N001 LT1117 ;pnba ADJ)OUT)IN
.tran 300u
.lib LT1117.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1108 680
WIRE 96 176 -16 176
WIRE 416 176 352 176
WIRE 512 176 416 176
WIRE 624 176 512 176
WIRE -16 192 -16 176
WIRE 416 192 416 176
WIRE 512 192 512 176
WIRE 624 192 624 176
WIRE -16 288 -16 272
WIRE 512 288 512 256
WIRE 624 288 624 272
WIRE 224 304 224 272
WIRE 416 304 416 272
WIRE 416 304 224 304
WIRE 416 320 416 304
WIRE 416 416 416 400
SYMBOL polcap 496 192 R0
WINDOW 3 24 56 Left 2
SYMATTR Value 10
SYMATTR InstName C1
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=33 Irms=0 Rser=0.3 Lser=0 mfg="KEMET" pn="T495D106M035AS" type="Tantalum"
SYMBOL res 400 304 R0
SYMATTR InstName R3
SYMATTR Value 154
SYMBOL voltage -16 176 R0
SYMATTR InstName V1
SYMATTR Value 4.25
SYMBOL current 624 192 R0
SYMATTR InstName I1
SYMATTR Value pulse(.1 .6 10u 1u 1u 50u 100u)
SYMBOL PowerProducts\\LT1117 224 176 R0
SYMATTR InstName U1
SYMBOL res 400 176 R0
SYMATTR InstName R2
SYMATTR Value 121
FLAG -16 288 0
FLAG 512 288 0
FLAG 624 288 0
FLAG 416 416 0
TEXT 584 368 Left 2 !.tran 300u
* Z:\home\khalils\Downloads\files\data\raw_asc\e0ea26ce6fcd_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N001 R
Q1 P002 N002 0 0 BC547C
R2 P001 P002 R
V1 N001 0 V
V2 P001 0 V
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1344 680
WIRE 128 112 80 112
WIRE 240 112 208 112
WIRE 80 160 80 112
WIRE 192 240 80 240
WIRE 304 240 304 160
WIRE 304 240 192 240
SYMBOL voltage 80 144 R0
SYMATTR InstName V1
SYMBOL npn2 240 64 R0
SYMATTR InstName Q1
SYMATTR Value BC547C
SYMBOL res 288 -32 R0
SYMATTR InstName R2
SYMBOL res 224 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMBOL voltage 304 0 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
FLAG 192 240 0
FLAG 304 -96 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6994-1.asc
* Generated by LTspice 26.0.1 for Windows.
* LTC6994-1 10ms Delay Interval Generator\nOutput Low When IN is Low\nRising Edge On IN Starts Delay to Output Rising Edge\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6994-1.asy)
R1 N003 0 121K
XU1 N001 0 N003 N004 N002 OUT LTC6994-1 ;pnba IN)GND)SET)DIV)V+)OUT
R4 OUT 0 100K
R2 N002 N004 1000K
V2 N001 0 PULSE(3.3 0 0.25m 1n 1n 0.5m 25m 3)
V1 N002 0 5
R3 N004 0 392K
.tran 100m startup
.lib LTC6994-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 680
WIRE -224 96 -240 96
WIRE 96 96 -144 96
WIRE 624 96 320 96
WIRE 624 112 624 96
WIRE 96 176 64 176
WIRE 400 176 320 176
WIRE 528 176 400 176
WIRE 400 192 400 176
WIRE 528 192 528 176
WIRE 624 208 624 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 352 256 320 256
WIRE 352 288 352 256
WIRE 400 288 400 272
WIRE 400 288 352 288
WIRE 528 288 528 272
WIRE 400 304 400 288
WIRE 400 400 400 384
SYMBOL res 384 288 R0
SYMATTR InstName R3
SYMATTR Value 392K
SYMBOL res 384 176 R0
SYMATTR InstName R2
SYMATTR Value 1000K
SYMBOL voltage 528 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -128 96 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(3.3 0 0.25m 1n 1n 0.5m 25m 3)
SYMATTR InstName V2
SYMBOL SpecialFunctions\\LTC6994-1 208 176 R0
SYMATTR InstName U1
SYMBOL res 608 96 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 121K
FLAG -240 96 0
FLAG 528 288 0
FLAG 624 96 OUT
FLAG 624 208 0
FLAG 400 400 0
FLAG -16 256 0
FLAG 64 176 0
TEXT 528 368 Left 2 !.tran 100m startup
TEXT 216 56 Bottom 2 ;LTC6994-1 10ms Delay Interval Generator\nOutput Low When IN is Low\nRising Edge On IN Starts Delay to Output Rising Edge\nStartup Modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\ba977df796df_Assignment_3b__iii_.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 SINE(0 311 50) Rser=0.001
R1 N002 0 1000
D1 N002 N001 1N4148
C1 N002 0 0.000001
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
* Negative Half Wave Rectifier Circuit (with 1microF Capacitor) (Ideal)
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 320 64 208 64
WIRE 480 64 384 64
WIRE 608 64 480 64
WIRE 208 112 208 64
WIRE 480 112 480 64
WIRE 608 128 608 64
WIRE 208 240 208 192
WIRE 304 240 208 240
WIRE 480 240 480 192
WIRE 480 240 304 240
WIRE 608 240 608 192
WIRE 608 240 480 240
WIRE 304 272 304 240
FLAG 304 272 0
SYMBOL voltage 208 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
SYMBOL res 464 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL diode 384 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL cap 592 128 R0
SYMATTR InstName C1
SYMATTR Value 0.000001
TEXT 144 272 Left 2 !.tran 0.05
TEXT -8 8 Left 2 ;Negative Half Wave Rectifier Circuit (with 1microF Capacitor) (Ideal)
* Z:\tmp\asc_dec_bjh7r6w2\16c59d2ab122_Draft1_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N003 0 C
XU1 N001 N003 Vcc Vee N002 OP413 ;pnba In+)In-)V+)V-)OUT
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP413.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 900 680
WIRE -112 48 -128 48
WIRE -112 96 -112 48
WIRE -144 112 -320 112
WIRE 32 128 -80 128
WIRE -144 144 -208 144
WIRE 32 160 32 128
WIRE 128 160 32 160
WIRE -112 208 -112 160
WIRE 448 272 288 272
WIRE -96 288 -112 288
WIRE 32 288 32 160
WIRE 32 288 -16 288
WIRE -208 352 -208 144
WIRE -112 352 -112 288
WIRE -112 352 -208 352
WIRE -112 416 -112 352
WIRE 128 416 -112 416
WIRE 176 416 128 416
WIRE 640 416 256 416
WIRE 128 448 128 416
WIRE 128 560 128 512
SYMBOL cap 112 448 R0
SYMATTR InstName C1
SYMBOL OpAmps\\OP413 -112 192 M180
SYMATTR InstName U1
FLAG 288 272 Input
FLAG 128 560 0
FLAG -112 208 Vcc
FLAG -128 48 Vee
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3012B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3012B.asy)
V1 IN 0 PWL(0 0 1 10)
XU1 IN OUT 0 N001 LT3012B ;pnba IN)OUT)GND)ADJ
R1 OUT N001 750K
R2 N001 0 249K
Rload OUT 0 100
C1 OUT 0 3.3
.tran 1
.lib LT3012B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 128 -96 128
WIRE 112 128 -64 128
WIRE 432 128 400 128
WIRE 576 128 432 128
WIRE 624 128 576 128
WIRE 672 128 624 128
WIRE 432 144 432 128
WIRE 672 144 672 128
WIRE -96 160 -96 128
WIRE 576 160 576 128
WIRE 432 224 400 224
WIRE 432 240 432 224
WIRE 576 240 576 224
WIRE 672 240 672 224
WIRE -96 272 -96 240
WIRE 256 304 256 288
WIRE 432 336 432 320
SYMBOL cap 560 160 R0
SYMATTR InstName C1
SYMATTR Value 3.3
SYMBOL res 656 128 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL res 416 128 R0
SYMATTR InstName R1
SYMATTR Value 750K
SYMBOL voltage -96 144 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL LT3012B 256 160 R0
SYMATTR InstName U1
SYMBOL res 416 224 R0
SYMATTR InstName R2
SYMATTR Value 249K
FLAG 256 304 0
FLAG -96 272 0
FLAG 672 240 0
FLAG 576 240 0
FLAG 432 336 0
FLAG 624 128 OUT
FLAG -64 128 IN
TEXT 584 312 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\acc6b51324af_sim.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Vin 0 1k
R4 N001 0 1k
I1 Vin 0 SINE(0 1 1 0 0 0 100) AC 1 0
R2 Vin N002 1k
XU1 N001 Vin N002 opamp Aol=1000K GBW=100Meg ;pnba invin)noninvin)out
R3 N001 N002 1k
.ac dec 100 1 1e5
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 80 -96 80
WIRE 224 80 80 80
WIRE 304 80 224 80
WIRE 400 80 336 80
WIRE 544 80 400 80
WIRE -96 112 -96 80
WIRE 80 112 80 80
WIRE 224 112 224 80
WIRE 400 112 400 80
WIRE 544 112 544 80
WIRE 304 128 304 80
WIRE 336 128 336 80
WIRE 224 224 224 192
WIRE 320 224 320 192
WIRE 320 224 224 224
WIRE 400 224 400 192
WIRE 400 224 320 224
WIRE -96 256 -96 192
WIRE 80 256 80 192
WIRE 80 256 -96 256
WIRE 544 256 544 192
WIRE 544 256 80 256
SYMBOL current -96 112 R0
WINDOW 3 -9 183 Left 2
WINDOW 123 -9 209 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value SINE(0 1 1 0 0 0 100)
SYMATTR Value2 AC 1 0
SYMBOL res 528 96 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 208 96 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 384 96 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 64 96 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL Opamps\\opamp 384 160 R90
SYMATTR InstName U1
SYMATTR SpiceLine Aol=1000K
SYMATTR SpiceLine2 GBW=100Meg
FLAG 80 256 0
FLAG -96 80 Vin
TEXT -106 348 Left 2 !.ac dec 100 1 1e5
TEXT 168 296 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\4649b5ccb3c4_1844-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1844-1.5.asy)
V1 IN 0 5
XU1 IN 0 IN OUT LTC1844-1.5 ;pnba IN)GND)_SHDN)OUT
I1 OUT 0 {iload} load
.dc v1 5 0 10m
.measure DC vdrop WHEN V(out)=1.4
.measure DC dropout param Vdrop-1.4
.param iload=150m
.lib LTC1844-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1940 1316
WIRE 64 80 -48 80
WIRE 80 80 64 80
WIRE 464 80 368 80
WIRE -48 96 -48 80
WIRE 464 96 464 80
WIRE -48 192 -48 176
WIRE 464 192 464 176
WIRE 64 240 64 80
WIRE 80 240 64 240
WIRE 224 304 224 288
SYMBOL LTC1844-1.5 224 160 R0
SYMATTR InstName U1
SYMBOL voltage -48 80 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL current 464 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 25 81 Left 2
WINDOW 3 36 48 Left 2
SYMATTR SpiceLine load
SYMATTR InstName I1
SYMATTR Value {iload}
FLAG 224 304 0
FLAG -48 192 0
FLAG 464 192 0
FLAG 464 80 OUT
FLAG -48 80 IN
TEXT 648 120 Left 2 !.dc v1 5 0 10m
TEXT 648 208 Left 2 !.measure DC vdrop WHEN V(out)=1.4\n.measure DC dropout param Vdrop-1.4
TEXT 648 160 Left 2 !.param iload=150m
* Z:\home\khalils\Downloads\files\data\raw_asc\60f309d3b696_part3_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
R1 0 N002 13.09k
R2 N002 N003 100k
R3 VE N003 3.67k
VEE N003 0 -5
VCC N001 0 -5
Q1 N001 N002 VE 0 My2n3904
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.MODEL My2n3904 npn
+IS=1.26532e-10 BF=206.302 NF=1.5 VAF=1000
+IKF=0.0272221 ISE=2.30771e-09 NE=3.31052 BR=20.6302
+NR=2.89609 VAR=9.39809 IKR=0.272221 ISC=2.30771e-09
+NC=1.9876 RB=5.8376 IRB=50.3624 RBM=0.634251
+RE=0.0001 RC=2.65711 XTB=0.1 XTI=1
+EG=1.05 CJE=4.64214e-12 VJE=0.4 MJE=0.256227
+TF=4.19578e-10 XTF=0.906167 VTF=8.75418 ITF=0.0105823
+CJC=3.76961e-12 VJC=0.4 MJC=0.238109 XCJC=0.8
+FC=0.512134 CJS=0 VJS=0.75 MJS=0.5
+TR=6.82023e-08 PTF=0 KF=0 AF=1
* X2
* X1
* X3
.dc VCC -5 5 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1464 704
WIRE 176 -16 64 -16
WIRE 784 -16 512 -16
WIRE 64 64 64 -16
WIRE 176 64 176 -16
WIRE 784 64 784 -16
WIRE 512 144 512 -16
WIRE 176 192 176 144
WIRE 448 192 176 192
WIRE 784 208 784 144
WIRE 512 272 512 240
WIRE 176 288 176 192
WIRE 512 288 512 272
WIRE 176 432 176 368
WIRE 512 432 512 368
WIRE 512 432 176 432
WIRE 512 512 512 432
WIRE 512 656 512 592
FLAG 64 64 0
FLAG 512 656 0
FLAG 784 208 0
FLAG 512 272 VE
SYMBOL res 160 48 R0
SYMATTR InstName R1
SYMATTR Value 13.09k
SYMBOL res 160 272 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL res 496 272 R0
SYMATTR InstName R3
SYMATTR Value 3.67k
SYMBOL voltage 512 496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VEE
SYMATTR Value -5
SYMBOL voltage 784 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCC
SYMATTR Value -5
SYMBOL npn 448 144 R0
SYMATTR InstName Q1
SYMATTR Value My2n3904
TEXT 720 352 Left 2 !.MODEL My2n3904 npn\n+IS=1.26532e-10 BF=206.302 NF=1.5 VAF=1000\n+IKF=0.0272221 ISE=2.30771e-09 NE=3.31052 BR=20.6302\n+NR=2.89609 VAR=9.39809 IKR=0.272221 ISC=2.30771e-09\n+NC=1.9876 RB=5.8376 IRB=50.3624 RBM=0.634251\n+RE=0.0001 RC=2.65711 XTB=0.1 XTI=1\n+EG=1.05 CJE=4.64214e-12 VJE=0.4 MJE=0.256227\n+TF=4.19578e-10 XTF=0.906167 VTF=8.75418 ITF=0.0105823\n+CJC=3.76961e-12 VJC=0.4 MJC=0.238109 XCJC=0.8\n+FC=0.512134 CJS=0 VJS=0.75 MJS=0.5\n+TR=6.82023e-08 PTF=0 KF=0 AF=1
TEXT 816 216 Left 2 ;X2
TEXT 544 664 Left 2 ;X1
TEXT 8 64 Left 2 ;X3
TEXT 8 688 Left 2 !.dc VCC -5 5 0.05
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4860.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4860.asy)
V1 +V 0 5
Rload OUT 0 10K
XU1 IN N001 +V -V OUT N002 ADA4860 ;pnba 1)2)Vcc)Vee)Vout)PD
V3 N002 0 -5
R2 OUT N001 10K
Vin IN 0 SINE(0 1 1K)
V2 -V 0 -5
R1 N001 0 10K
.tran 10m
.lib ADA4860.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 384 -1088
WIRE 752 -1088 752 -1104
WIRE 384 -1072 384 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 560 -1056 560 -1072
WIRE 592 -1040 592 -1072
WIRE 752 -992 752 -1008
WIRE 384 -976 384 -992
WIRE 592 -944 592 -960
SYMBOL ADA4860 576 -1104 R0
WINDOW 0 17 -21 Left 2
WINDOW 3 25 19 Left 2
SYMATTR InstName U1
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 592 -1056 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName V3
SYMATTR Value -5
SYMBOL voltage 384 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
WINDOW 0 17 18 Left 2
WINDOW 3 17 96 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 384 -976 0
FLAG 752 -1104 OUT
FLAG 384 -1088 IN
FLAG 560 -1136 +V
FLAG 256 -1168 -V
FLAG 560 -1056 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
FLAG 592 -944 0
TEXT 696 -944 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2360.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5
R1 IN N001 100K
R2 IN N003 22Meg
C1 N005 0 1n
L1 N002 OUT 100 Rpar=50k
C2 OUT 0 10 Rser=3m
R3 OUT N004 357K
R4 N004 0 115K
C3 OUT N004 10p
Rload OUT 0 66
XU1 N001 N003 0 N004 N005 0 N002 IN 0 ADP2360 ;pnba EN)PG)Ith)FB)SS)PGND)SW)Vin)AGND
.tran 3m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2360.asy)
.lib ADP2360.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE -144 -48 -256 -48
WIRE 0 -48 -144 -48
WIRE 224 -48 0 -48
WIRE -256 -32 -256 -48
WIRE 0 -32 0 -48
WIRE -144 16 -144 -48
WIRE 224 32 224 -48
WIRE -256 64 -256 48
WIRE 0 64 0 48
WIRE 96 64 0 64
WIRE 384 64 352 64
WIRE 512 64 464 64
WIRE 592 64 512 64
WIRE 704 64 592 64
WIRE 848 64 704 64
WIRE 592 80 592 64
WIRE 704 80 704 64
WIRE 848 80 848 64
WIRE 512 96 512 64
WIRE -144 128 -144 96
WIRE 96 128 -144 128
WIRE 704 176 704 144
WIRE 848 176 848 160
WIRE 96 192 80 192
WIRE 512 192 512 160
WIRE 512 192 352 192
WIRE 592 192 592 160
WIRE 592 192 512 192
WIRE 592 208 592 192
WIRE 16 256 0 256
WIRE 96 256 80 256
WIRE 592 304 592 288
WIRE 176 320 176 304
WIRE 272 320 272 304
FLAG 0 256 0
FLAG -256 64 0
FLAG 176 320 0
FLAG 272 320 0
FLAG 704 176 0
FLAG 848 176 0
FLAG 592 304 0
FLAG 848 64 OUT
FLAG 80 192 0
FLAG -256 -48 IN
SYMBOL voltage -256 -48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res -16 -48 R0
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL res -160 0 R0
SYMATTR InstName R2
SYMATTR Value 22Meg
SYMBOL cap 80 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL ind 368 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rpar=50k
SYMBOL cap 688 80 R0
WINDOW 39 24 61 Left 2
WINDOW 3 45 33 Left 2
SYMATTR SpiceLine Rser=3m
SYMATTR Value 10
SYMATTR InstName C2
SYMBOL res 576 64 R0
SYMATTR InstName R3
SYMATTR Value 357K
SYMBOL res 576 192 R0
SYMATTR InstName R4
SYMATTR Value 115K
SYMBOL cap 496 96 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL res 832 64 R0
SYMATTR InstName Rload
SYMATTR Value 66
SYMBOL PowerProducts\\ADP2360 224 160 R0
SYMATTR InstName U1
TEXT 712 288 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1882.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1882.asy)
V1 +V 0 10
R1 N002 N001 1K
R2 N001 0 1K
XU1 N003 N001 +V -V N002 LT1881 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -10
V3 N003 0 SINE(0 1 1K)
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -224 128 -224 112
WIRE -96 128 -96 112
WIRE 192 208 192 192
WIRE -224 224 -224 208
WIRE -96 224 -96 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -224 112 R0
SYMATTR InstName V2
SYMATTR Value -10
SYMBOL opamps\\LT1882 192 240 R0
SYMATTR InstName U1
SYMBOL voltage -96 112 R0
SYMATTR InstName V1
SYMATTR Value 10
FLAG -96 224 0
FLAG 192 192 +V
FLAG -96 112 +V
FLAG 192 288 -V
FLAG -224 224 0
FLAG -224 112 -V
FLAG 16 96 0
FLAG 0 368 0
TEXT 256 360 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX4163.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX4163.asy)
RL OUT 0 10k
CL OUT 0 15p
V1 IN 0 SINE(0 50m 1k)
Vee 0 Vee 2.5
Vcc Vcc 0 2.5
XU1 IN OUT Vcc Vee OUT MAX4163 ;pnba In+)In-)V+)V-)OUT
.tran 1m
.lib MAX4163.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 144 288 144 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 144 400 144 368
WIRE 144 400 112 400
WIRE 400 400 304 400
WIRE 112 416 112 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 144 448 144 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 144 544 144 528
WIRE 304 592 304 576
SYMBOL voltage 144 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL MAX4163 432 320 R0
SYMATTR InstName U1
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 1k)
SYMBOL voltage 144 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
FLAG 720 384 OUT
FLAG 144 272 Vcc
FLAG 144 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 112 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
TEXT 96 632 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\100ec9b23e07_Pre-charge_FET.asc
* Generated by LTspice 26.0.1 for Windows.
* Battery simulation\nInternal resistance: ~100mOhm per cell, *10/2 (because 10S2P) = 500mOhm
* Pre-charge FET
* Analysis Setup\n1000ms simulation in 1ms increments
* 15V Linear regulator
* System Load
* Operating point:\nCurrent draw (battery engaged): 15uA\nCurrent draw (battery not engaged): 0
M2 Vd PRECHG_FET_EN 0 0 BSS123
V3 PRECHG_FET_EN 0 PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
R4 PRECHG_FET_EN 0 1Meg
V1 CELL_10_POS 0 30 Rser=500m
V2 15VO 0 15
R_SYSTEM CELL_10_POS SYSTEM_GND 10
R5 SYSTEM_GND Vd 1k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1m 150m uic
.step param R5 list 100 1k 2k 5k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5144 2508
WIRE 352 416 112 416
WIRE 112 560 112 416
WIRE 1216 656 1072 656
WIRE 112 720 112 640
WIRE 224 720 112 720
WIRE 224 736 224 720
WIRE 1072 768 1072 656
WIRE 112 800 112 720
WIRE 352 800 112 800
WIRE 3024 928 2896 928
WIRE 1072 1024 1072 848
WIRE 1216 1024 1072 1024
WIRE 3024 1104 3024 928
WIRE 464 1216 176 1216
WIRE 1488 1232 1296 1232
WIRE 1664 1232 1488 1232
WIRE 1488 1312 1488 1232
WIRE 176 1360 176 1216
WIRE 3024 1376 3024 1184
WIRE 3024 1376 2896 1376
WIRE 1664 1472 1664 1232
WIRE 1488 1520 1488 1392
WIRE 1488 1520 1296 1520
WIRE 1648 1520 1488 1520
WIRE 1792 1520 1744 1520
WIRE 1872 1520 1792 1520
WIRE 2144 1520 1952 1520
WIRE 176 1584 176 1440
WIRE 464 1584 176 1584
DATAFLAG 1488 1232 "$"
RECTANGLE Normal 60 1088 996 1644 2
RECTANGLE Normal 1068 1084 2372 1648 2
RECTANGLE Normal 40 872 564 1064 2
RECTANGLE Normal 32 300 592 832 2
RECTANGLE Normal 2580 824 3200 1448 2
SYMBOL res 1968 1504 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL res 3008 1088 R0
SYMATTR InstName R_SYSTEM
SYMATTR Value 10
SYMBOL voltage 112 544 R0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 1472 1296 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL voltage 1072 752 R0
SYMATTR InstName V3
SYMATTR Value PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
SYMBOL nmos 1744 1472 R90
SYMATTR InstName M2
SYMATTR Value BSS123
SYMBOL battery 176 1344 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMATTR SpiceLine Rser=500m
FLAG 1296 1520 BMS_GND
FLAG 1296 1232 PRECHG_FET_EN
FLAG 2144 1520 SYSTEM_GND
FLAG 464 1216 CELL_10_POS
FLAG 464 1584 BMS_GND
FLAG 352 416 15VO
FLAG 352 800 BMS_GND
FLAG 1216 656 PRECHG_FET_EN
FLAG 1216 1024 BMS_GND
FLAG 2896 1376 SYSTEM_GND
FLAG 2896 928 CELL_10_POS
FLAG 224 736 0
FLAG 1792 1520 Vd
TEXT 88 968 Left 2 !.tran 1m 150m uic
TEXT 88 1128 Left 2 ;Battery simulation\nInternal resistance: ~100mOhm per cell, *10/2 (because 10S2P) = 500mOhm
TEXT 1120 1120 Left 2 ;Pre-charge FET
TEXT 80 888 Left 2 ;Analysis Setup\n1000ms simulation in 1ms increments
TEXT 72 336 Left 2 ;15V Linear regulator
TEXT 2616 848 Left 2 ;System Load
TEXT 1864 1392 Left 2 !.step param R5 list 100 1k 2k 5k
TEXT 1800 600 Left 2 ;Operating point:\nCurrent draw (battery engaged): 15uA\nCurrent draw (battery not engaged): 0
* Z:\home\khalils\Downloads\files\data\raw_asc\0343b31d7325_RCHPF.asc
* Generated by LTspice 26.0.1 for Windows.
C1 V_O N001 1n
R1 V_O 0 1k
V1 N001 0 SINE(0 0.707 10)
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 160 -48 64 -48
WIRE 336 -48 224 -48
WIRE 384 -48 336 -48
WIRE 336 32 336 -48
WIRE 64 112 64 -48
WIRE 336 192 336 112
SYMBOL voltage 64 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 0.707 10)
SYMBOL res 320 16 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 224 -64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
FLAG 64 192 0
FLAG 336 192 0
FLAG 384 -48 V_O
TEXT 24 216 Left 2 !.tran 1