Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1762.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1762.asy)
XU1 OUT OUT N001 0 IN MP_01 MP_02 IN LT1762 ;pnba OUT)ADJ)BYP)GND)_SHDN)))IN
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10
Rload OUT 0 500
C2 OUT N001 .01
.tran 1
.lib LT1762.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 32 304 32
WIRE 352 32 320 32
WIRE 432 32 352 32
WIRE 528 32 432 32
WIRE 0 48 -208 48
WIRE 16 48 0 48
WIRE 432 48 432 32
WIRE 528 48 528 32
WIRE -208 64 -208 48
WIRE 352 64 352 32
WIRE 320 96 320 32
WIRE 320 96 304 96
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 432 144 432 112
WIRE 528 144 528 128
WIRE -208 160 -208 144
WIRE 352 160 352 128
WIRE 352 160 304 160
WIRE 160 240 160 208
SYMBOL cap 416 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1762 160 96 R0
SYMATTR InstName U1
SYMBOL cap 336 64 R0
SYMATTR InstName C2
SYMATTR Value .01
FLAG -208 160 0
FLAG 432 144 0
FLAG 528 144 0
FLAG 160 240 0
FLAG 528 32 OUT
FLAG -208 48 IN
TEXT 384 216 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\98d4371d11e7_Draft2N.asc
* Generated by LTspice 26.0.1 for Windows.
VGS2 VG 0 1
VUDS N001 0 0.9
M1 N001 VG 0 0 nch l=lset w=wset
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmos018.txt
.dc VGS2 0 1 1m
.param wset=table(n, 1,0.22u, 2,1u, 3,2u, 4,2u, 5,5u, 6,5u, 7,10u, 8,10u, 9,40u)
.param lset=table(n, 1,0.18u, 2,0.5u, 3,0.5u, 4,1u, 5,1u, 6,2u, 7,5u, 8,10u, 9,10u)
.step param n 1 9 1
.meas DC UTH FIND V(VG) WHEN Id(M1)=100n*wset/lset
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1356 680
WIRE 544 176 224 176
WIRE 224 224 224 176
WIRE 544 224 544 176
WIRE 240 272 224 272
WIRE 80 304 32 304
WIRE 176 304 80 304
WIRE 32 320 32 304
WIRE 240 320 240 272
WIRE 240 320 224 320
WIRE 224 416 224 320
WIRE 544 416 544 304
FLAG 224 416 0
FLAG 544 416 0
FLAG 80 304 VG
FLAG 32 400 0
SYMBOL voltage 32 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS2
SYMATTR Value 1
SYMBOL voltage 544 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName UDS
SYMATTR Value 0.9
SYMBOL nmos4 176 224 R0
WINDOW 0 71 23 Left 2
WINDOW 3 72 48 Left 2
WINDOW 123 71 80 Left 2
SYMATTR InstName M1
SYMATTR Value nch
SYMATTR Value2 l=lset w=wset
TEXT -40 -64 Left 2 !.lib cmos018.txt
TEXT -40 96 Left 2 !.dc VGS2 0 1 1m
TEXT -40 -16 Left 2 !.param wset=table(n, 1,0.22u, 2,1u, 3,2u, 4,2u, 5,5u, 6,5u, 7,10u, 8,10u, 9,40u)\n.param lset=table(n, 1,0.18u, 2,0.5u, 3,0.5u, 4,1u, 5,1u, 6,2u, 7,5u, 8,10u, 9,10u)\n.step param n 1 9 1\n.meas DC UTH FIND V(VG) WHEN Id(M1)=100n*wset/lset
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1302-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1302-5.asy)
C3 N005 0 .01
V1 IN 0 2.5
Rload OUT 0 100
L1 IN N001 10 Rser=0.02 Rpar=5000
D1 N001 OUT MBRS340
R1 N004 N005 20K
C1 OUT 0 100 Rser=0.02
XU1 0 N004 N002 OUT N003 IN N001 0 LT1302 top=315K bot=105K ;pnba GND)Vc)SHDN)Sense)It)Vin)SW)PGND
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT1302.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1604 1024
WIRE 688 448 416 448
WIRE 752 448 688 448
WIRE 880 448 832 448
WIRE 928 448 880 448
WIRE 1040 448 992 448
WIRE 1104 448 1040 448
WIRE 416 464 416 448
WIRE 1104 464 1104 448
WIRE 688 512 688 448
WIRE 416 560 416 544
WIRE 1104 560 1104 544
WIRE 880 592 880 448
WIRE 880 592 832 592
WIRE 544 608 528 608
WIRE 1040 656 1040 448
WIRE 1040 656 832 656
WIRE 1040 672 1040 656
WIRE 544 704 528 704
WIRE 848 720 832 720
WIRE 944 720 928 720
WIRE 944 736 944 720
WIRE 1040 752 1040 736
WIRE 608 816 608 800
WIRE 768 816 768 800
WIRE 944 816 944 800
SYMBOL schottky 928 464 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL res 1088 448 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL CAP 928 736 R0
SYMATTR InstName C3
SYMATTR Value .01
SYMBOL PowerProducts\\LT1302-5 688 656 R0
SYMATTR InstName U1
SYMBOL POLCAP 1024 672 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL IND 736 464 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL VOLTAGE 416 448 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL RES 832 736 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 20K
FLAG 1040 752 0
FLAG 1104 560 0
FLAG 768 816 0
FLAG 608 816 0
FLAG 944 816 0
FLAG 416 560 0
FLAG 1104 448 OUT
FLAG 416 448 IN
TEXT 920 872 Left 2 !.tran 1m startup
* Z:\tmp\asc_dec_bjh7r6w2\11da3431e1e8_adc_2bit_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 Uin N001 Vcc 0 A level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R3 N001 N003 1.2k
XU3 Uin N007 Vcc 0 C level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
A3 0 N006 0 C 0 0 N005 0 AND VHIGH=5V
V1 Vcc 0 5
* Library below included based on ModelFile attribute of instance XU1, XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1312 680
WIRE 464 -208 464 -240
WIRE 592 -128 592 -192
WIRE 640 -128 592 -128
WIRE 768 -112 704 -112
WIRE 464 -96 464 -128
WIRE 640 -96 464 -96
WIRE 464 -64 464 -96
WIRE 768 -64 768 -112
WIRE 1008 -64 768 -64
WIRE 1024 -64 1008 -64
WIRE 1280 -64 1088 -64
WIRE 1024 -32 768 -32
WIRE 592 16 592 -128
WIRE 640 16 592 16
WIRE 768 32 768 -32
WIRE 768 32 704 32
WIRE 464 48 464 16
WIRE 640 48 464 48
WIRE 1008 48 1008 -64
WIRE 1136 48 1008 48
WIRE 1280 48 1200 48
WIRE 464 80 464 48
WIRE 1136 80 1104 80
WIRE 768 96 768 32
WIRE 848 96 768 96
WIRE 1008 96 912 96
WIRE 1104 96 1104 80
WIRE 1104 96 1072 96
WIRE 1008 128 768 128
WIRE 592 176 592 16
WIRE 640 176 592 176
WIRE 768 192 768 128
WIRE 768 192 704 192
WIRE 640 208 464 208
WIRE 768 352 464 352
SYMBOL OpAmps\\UniversalOpAmp2 672 -112 M180
SYMATTR InstName U1
SYMBOL res 448 -80 R0
SYMATTR InstName R3
SYMATTR Value 1.2k
SYMBOL OpAmps\\UniversalOpAmp2 672 192 M180
SYMATTR InstName U3
SYMBOL Digital\\and 1040 48 R0
WINDOW 40 -64 123 Left 2
WINDOW 0 7 24 Left 2
SYMATTR SpiceLine2 VHIGH=5V
SYMATTR InstName A3
SYMBOL voltage 224 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 224 32 0
FLAG 224 -48 Vcc
FLAG 464 -240 Vcc
FLAG 672 -80 Vcc
FLAG 672 64 Vcc
FLAG 672 224 Vcc
FLAG 672 -144 0
FLAG 672 0 0
FLAG 672 160 0
FLAG 768 -112 A
FLAG 768 32 B
FLAG 768 192 C
FLAG 768 352 D
FLAG 592 -192 Uin
* Z:\home\khalils\Downloads\files\data\raw_asc\56e9f3c6ec9c_MiModelo_N_500mua.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 MiModelo
VG N002 0 2.3950
VD N001 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.INCLUDE CD4007.lib
.dc VG 0 5 0.1
;dc VD 0 5 0.1
.MODEL MiModelo NMOS (LEVEL=1 KP=7.5581e-04 VT0=1.1703 LAMBDA=0.0085116)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1296 680
WIRE 416 128 224 128
WIRE 176 208 32 208
WIRE 32 224 32 208
WIRE 32 368 32 304
WIRE 224 368 224 224
WIRE 416 368 416 208
FLAG 32 368 0
FLAG 224 368 0
FLAG 416 368 0
SYMBOL nmos 176 128 R0
SYMATTR InstName M1
SYMATTR Value MiModelo
SYMBOL voltage 32 208 R0
SYMATTR InstName VG
SYMATTR Value 2.3950
SYMBOL voltage 416 112 R0
SYMATTR InstName VD
SYMATTR Value 5
TEXT 72 48 Left 2 !.INCLUDE CD4007.lib
TEXT 80 -24 Left 2 !.dc VG 0 5 0.1
TEXT 88 8 Left 2 !;dc VD 0 5 0.1
TEXT 72 80 Left 2 !.MODEL MiModelo NMOS (LEVEL=1 KP=7.5581e-04 VT0=1.1703 LAMBDA=0.0085116)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7104-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7104-5.0.asy)
XU1 IN OUT IN N001 OUT 0 ADP7104-5.0 ;pnba Vin)Sense)EN)PG)Vout)GND
R1 OUT N001 100k
Rload OUT 0 15
C1 OUT 0 2.2 Rser=1.5m
V1 IN 0 PWL(0 0 20u 6)
.tran 3m startup
.lib ADP7104-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -128 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -128 48 -128 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -128 144 -128 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 20u 6)
SYMBOL ADP7104-5.0 224 128 R0
SYMATTR InstName U1
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
FLAG 224 304 0
FLAG -128 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -128 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\16f44ecd87de_06-invertin_amplifier_bode.asc
* Generated by LTspice 26.0.1 for Windows.
* BW = 600 KHz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
Rf1 out N001 {fb_val}
XU1 0 N001 vcc vee out LT1001 ;pnba In+)In-)V+)V-)OUT
V3 in 0 AC 1
R1 N001 in {r1_val}
V2 0 vee +18
V1 vcc 0 +18
.param fb_val=2k r1_val=1k
.ac dec 100 1 1meg
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 -64 288 -64
WIRE 448 -64 400 -64
WIRE 32 16 32 -16
WIRE 352 48 352 32
WIRE 160 64 144 64
WIRE 176 64 160 64
WIRE 288 64 288 -64
WIRE 288 64 256 64
WIRE 320 64 288 64
WIRE 448 80 448 -64
WIRE 448 80 384 80
WIRE 496 80 448 80
WIRE 512 80 496 80
WIRE 320 96 304 96
WIRE 32 112 32 96
WIRE 32 112 -32 112
WIRE 144 112 144 64
WIRE 32 128 32 112
WIRE 304 128 304 96
WIRE 352 128 352 112
WIRE -32 144 -32 112
WIRE 144 224 144 192
WIRE 32 240 32 208
SYMBOL res 416 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 45 VTop 2
SYMATTR InstName Rf1
SYMATTR Value {fb_val}
SYMBOL voltage 144 96 R0
WINDOW 0 43 66 Left 2
WINDOW 3 20 91 Left 2
WINDOW 123 26 102 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 272 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {r1_val}
SYMBOL voltage 32 112 R0
WINDOW 3 19 88 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value +18
SYMATTR InstName V2
SYMBOL voltage 32 0 R0
WINDOW 3 24 85 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value +18
SYMATTR InstName V1
SYMBOL OpAmps\\OP07 352 16 R0
SYMATTR InstName U1
FLAG -32 144 0
FLAG 32 -16 vcc
FLAG 32 240 vee
FLAG 144 224 0
FLAG 160 64 in
FLAG 352 128 vee
FLAG 352 32 vcc
FLAG 496 80 out
FLAG 304 128 0
TEXT 176 240 Left 2 !.param fb_val=2k r1_val=1k
TEXT 176 272 Left 2 !.ac dec 100 1 1meg
TEXT 560 -48 Left 2 ;BW = 600 KHz
* Z:\home\khalils\Downloads\files\data\raw_asc\57038050a92b_GM1.asc
* Generated by LTspice 26.0.1 for Windows.
vinN N001 0
M1 dm N001 sp sp P_1u l={Lp2} w={Wp2}
vsp sp 0 1.1367383V
vdm dm 0 -1.3427744
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.inc cmosedu_models.txt
.dc vinN -2.5 2.5 0.0001
.meas gm FIND d(Id(M1)) AT 0
.param Wp=49.992332u Lp=49.986531u Wp2=49.998294u Lp2=9.069192u Wn=41.548244u Ln=47.775368u Wn2=49.906981u Ln2=28.964298u C=0.100001p Iref=10892.687537n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2468 680
WIRE 1056 -112 1056 -160
WIRE 1152 -112 1056 -112
WIRE 1008 -96 880 -96
WIRE 1152 -64 1152 -112
WIRE 1152 -64 1056 -64
WIRE 496 -16 496 -48
WIRE 688 -16 688 -48
WIRE 880 -16 880 -96
WIRE 1056 64 1056 -16
WIRE 496 128 496 64
WIRE 688 128 688 64
WIRE 880 128 880 64
SYMBOL voltage 688 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 24 90 Left 2
SYMATTR Value -1.3427744
SYMATTR InstName vdm
SYMBOL pmos4 1008 -16 M180
SYMATTR InstName M1
SYMATTR Value2 l={Lp2} w={Wp2}
SYMATTR Value P_1u
SYMBOL voltage 496 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 24 90 Left 2
SYMATTR Value 1.1367383V
SYMATTR InstName vsp
SYMBOL voltage 880 -32 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value ""
SYMATTR InstName vinN
FLAG 880 128 0
FLAG 496 -48 sp
FLAG 496 128 0
FLAG 1056 -160 sp
FLAG 688 -48 dm
FLAG 688 128 0
FLAG 1056 64 dm
TEXT 472 192 Left 2 !.inc cmosedu_models.txt
TEXT 472 248 Left 2 !.dc vinN -2.5 2.5 0.0001
TEXT 472 168 Left 2 !.meas gm FIND d(Id(M1)) AT 0
TEXT 272 272 Left 2 !.param Wp=49.992332u Lp=49.986531u Wp2=49.998294u Lp2=9.069192u Wn=41.548244u Ln=47.775368u Wn2=49.906981u Ln2=28.964298u C=0.100001p Iref=10892.687537n
* Z:\tmp\asc_dec_bjh7r6w2\151bd6dabebd_1783_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 N005 OUT 0 2N3904
I1 N003 0 SINE(1 1 1K)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 400 32 128 32
WIRE -32 64 -32 32
WIRE -192 112 -192 96
WIRE 192 112 192 96
WIRE 400 144 400 32
WIRE -32 160 -32 144
WIRE 16 160 -32 160
WIRE 160 160 96 160
WIRE 336 192 304 192
WIRE -192 208 -192 192
WIRE 128 224 128 32
WIRE 160 224 128 224
WIRE -32 240 -32 160
WIRE 400 256 400 240
WIRE 448 256 400 256
WIRE 400 272 400 256
WIRE 192 288 192 272
WIRE -32 336 -32 320
SYMBOL npn 336 144 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL current -32 240 R0
SYMATTR InstName I1
SYMATTR Value SINE(1 1 1K)
FLAG -192 208 0
FLAG 192 96 +V
FLAG -192 96 +V
FLAG 192 288 0
FLAG -32 336 0
FLAG 448 256 OUT
* Z:\tmp\asc_dec_bjh7r6w2\170cab4795dd_dff1_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
C1 sample Vss 500p
S6 hold N002 clk tp switch
AX2 0 0 0 0 0 0 0 0 BUF
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 6308 700
WIRE 1472 -736 1456 -736
WIRE 1488 -736 1472 -736
WIRE 1616 -736 1600 -736
WIRE 1632 -736 1616 -736
WIRE 1472 -720 1472 -736
WIRE 1616 -720 1616 -736
WIRE 800 -704 720 -704
WIRE 960 -704 880 -704
WIRE 1056 -704 960 -704
WIRE 1200 -704 1104 -704
WIRE 1344 -704 1280 -704
WIRE 1440 -704 1344 -704
WIRE 1552 -704 1504 -704
WIRE 1584 -704 1552 -704
WIRE 1712 -704 1648 -704
WIRE 1104 -688 1104 -704
WIRE 960 -672 960 -704
WIRE 1056 -672 1056 -704
WIRE 1344 -672 1344 -704
WIRE 1472 -672 1472 -688
WIRE 1472 -672 1456 -672
WIRE 1488 -672 1472 -672
WIRE 1616 -672 1616 -688
WIRE 1616 -672 1600 -672
WIRE 1632 -672 1616 -672
WIRE 1472 -656 1456 -672
WIRE 1472 -656 1488 -672
WIRE 1616 -656 1600 -672
WIRE 1616 -656 1632 -672
WIRE 864 -608 864 -656
WIRE 1056 -592 1056 -624
WIRE 1104 -592 1104 -608
WIRE 1104 -592 1056 -592
WIRE 960 -576 960 -608
WIRE 960 -576 944 -576
WIRE 976 -576 960 -576
WIRE 1104 -576 1104 -592
WIRE 1104 -576 1088 -576
WIRE 1120 -576 1104 -576
WIRE 1344 -576 1344 -608
WIRE 1344 -576 1328 -576
WIRE 1360 -576 1344 -576
WIRE 960 -560 944 -576
WIRE 960 -560 976 -576
WIRE 1104 -560 1088 -576
WIRE 1104 -560 1120 -576
WIRE 1344 -560 1328 -576
WIRE 1344 -560 1360 -576
SYMBOL cap 944 -672 R0
SYMATTR InstName C1
SYMATTR Value 500p
SYMBOL sw 1296 -704 M270
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switch
SYMATTR InstName S6
SYMBOL inv 1584 -672 R0
SYMATTR InstName X2
FLAG 1712 -704 Q
FLAG 864 -608 Clk
FLAG 1344 -704 hold
FLAG 1552 -704 Qi
FLAG 960 -576 Vss
FLAG 1344 -576 Vss
FLAG 816 -656 tp
FLAG 1264 -656 tp
FLAG 1216 -656 clk
FLAG 960 -704 sample
FLAG 1104 -576 Vss
FLAG 1472 -736 Vdd
FLAG 1472 -672 Vss
FLAG 1616 -736 Vdd
FLAG 1616 -672 Vss
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3617.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3617.asy)
V1 IN 0 2.5
Rload OUT 0 .2
XU1 IN 0 N001 IN N002 MP_01 MP_02 MP_03 MP_04 MP_05 MP_06 MP_07 MP_08 MP_09 MP_10 MP_11 MP_12 IN IN MP_13 NC_14 OUT IN IN 0 LTC3617 ;pnba Rt)SGND)VTTR)PVin)SW)))))))))))))SVin)Run))Pgood)FB)Ith)VDDQin)PGND
C1 OUT 0 47 x2 Rser=5m
L1 N002 OUT .15 Rser=1m Rpar=5K
C2 N001 0 .1
.tran 2m startup
.lib LTC3617.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 -64 -80 -64
WIRE 128 -64 16 -64
WIRE 224 -64 128 -64
WIRE 336 -64 224 -64
WIRE -80 -48 -80 -64
WIRE 128 -48 128 -64
WIRE 224 -48 224 -64
WIRE 16 16 16 -64
WIRE 32 16 16 16
WIRE 368 16 320 16
WIRE -80 48 -80 32
WIRE 16 112 16 16
WIRE 32 112 16 112
WIRE 368 112 320 112
WIRE 480 112 448 112
WIRE 544 112 480 112
WIRE 640 112 544 112
WIRE 544 128 544 112
WIRE 640 128 640 112
WIRE 480 208 480 112
WIRE 480 208 320 208
WIRE 544 224 544 192
WIRE 640 224 640 208
WIRE 16 304 16 112
WIRE 32 304 16 304
WIRE 336 304 336 -64
WIRE 336 304 320 304
WIRE 128 384 128 368
WIRE 224 384 224 368
SYMBOL PowerProducts\\LTC3617 176 160 R0
SYMATTR InstName U1
SYMBOL voltage -80 -64 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL ind 352 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value .15
SYMATTR SpiceLine Rser=1m Rpar=5K
SYMBOL cap 368 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL res 624 112 R0
SYMATTR InstName Rload
SYMATTR Value .2
SYMBOL cap 528 128 R0
WINDOW 123 31 69 Left 2
WINDOW 3 37 37 Left 2
SYMATTR Value2 x2
SYMATTR Value 47
SYMATTR InstName C1
SYMATTR SpiceLine Rser=5m
FLAG -80 48 0
FLAG 128 384 0
FLAG 544 224 0
FLAG 640 224 0
FLAG 640 112 OUT
FLAG -80 -64 IN
FLAG 224 384 0
FLAG 432 16 0
TEXT 424 312 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3693.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3693.asy)
R5 OUT N007 100K
R3 N003 N002 15K
D1 0 N004 MBRS340
C4 N001 0 .01
XU1 OUT N006 N004 IN N001 0 N007 N008 N003 N005 0 LT3693 ;pnba BD)BOOST)SW)Vin)RUN/SS)GND)PG)FB)VC)RT)SYNC
R6 IN N001 500K
L1 N004 OUT 4.7 Rpar=2K
V1 IN 0 30
R1 OUT N008 536K
C1 OUT 0 47
C2 N004 N006 .47
Rload OUT 0 1.43
C3 N002 0 680p
R2 N008 0 100K
R4 N005 0 63.4K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT3693.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1236 740
WIRE -352 64 -448 64
WIRE 96 64 -352 64
WIRE -448 80 -448 64
WIRE -352 80 -352 64
WIRE 96 112 96 64
WIRE -64 160 -352 160
WIRE 560 160 256 160
WIRE -448 176 -448 160
WIRE -352 176 -352 160
WIRE -240 240 -256 240
WIRE -160 240 -176 240
WIRE -64 240 -80 240
WIRE 288 240 256 240
WIRE 384 240 288 240
WIRE 448 240 384 240
WIRE 560 240 560 160
WIRE 560 240 528 240
WIRE 656 240 560 240
WIRE 752 240 656 240
WIRE 848 240 752 240
WIRE -352 256 -352 240
WIRE 288 256 288 240
WIRE 384 256 384 240
WIRE 752 256 752 240
WIRE 848 256 848 240
WIRE 560 272 560 240
WIRE -208 320 -256 320
WIRE -64 320 -128 320
WIRE 288 320 256 320
WIRE 384 336 384 320
WIRE 656 336 656 240
WIRE 752 352 752 320
WIRE 848 352 848 336
WIRE -64 400 -96 400
WIRE 560 400 560 352
WIRE 560 400 256 400
WIRE 560 416 560 400
WIRE 32 464 32 448
WIRE 160 464 160 448
WIRE 560 512 560 496
WIRE -96 544 -96 400
WIRE 656 544 656 416
WIRE 656 544 -96 544
SYMBOL voltage -448 64 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL LT3693 96 288 R0
SYMATTR InstName U1
SYMBOL res -368 64 R0
SYMATTR InstName R6
SYMATTR Value 500K
SYMBOL ind 432 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rpar=2K
SYMBOL cap 736 256 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMBOL res -64 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 15K
SYMBOL cap -368 176 R0
SYMATTR InstName C4
SYMATTR Value .01
SYMBOL cap 272 256 R0
WINDOW 3 30 49 Left 2
SYMATTR Value .47
SYMATTR InstName C2
SYMBOL res -112 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 63.4K
SYMBOL res 640 320 R0
SYMATTR InstName R5
SYMATTR Value 100K
SYMBOL cap -176 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 680p
SYMBOL schottky 368 320 M180
WINDOW 0 28 62 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 832 240 R0
SYMATTR InstName Rload
SYMATTR Value 1.43
SYMBOL res 544 400 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 544 256 R0
SYMATTR InstName R1
SYMATTR Value 536K
FLAG 384 336 0
FLAG 752 352 0
FLAG 560 512 0
FLAG -256 240 0
FLAG -448 176 0
FLAG 160 464 0
FLAG 848 352 0
FLAG -256 320 0
FLAG -352 256 0
FLAG 848 240 OUT
FLAG -448 64 IN
FLAG 32 464 0
TEXT 264 496 Left 2 !.tran 1m startup
* Z:\tmp\asc_dec_bjh7r6w2\19aa72b9e44b_pwm-highpass_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N006 N005 301
R3 N005 N002 1100
R1 N003 N002 301
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 980 680
WIRE 400 240 176 240
WIRE 544 240 464 240
WIRE 704 240 544 240
WIRE 848 240 784 240
WIRE 912 240 848 240
WIRE 544 272 544 240
WIRE 848 288 848 240
WIRE 400 384 320 384
WIRE 544 384 544 352
WIRE 544 384 464 384
WIRE 704 384 544 384
WIRE 848 384 848 352
WIRE 848 384 784 384
WIRE 912 384 848 384
SYMBOL res 800 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 301
SYMBOL res 560 368 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 1100
SYMBOL res 800 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 301
* Z:\home\khalils\Downloads\files\data\raw_asc\13fd25a6f385_Diode-Rectifier-9.asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 a RBR2VWM60A
R1 out 0 100
V1 a b SINE(0 50 100) Rser=0.5
D2 a out RBR2VWM60A
D3 b out RBR2VWM60A
D4 0 b RBR2VWM60A
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 50m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 -240 -144 -240
WIRE 112 -240 64 -240
WIRE 176 -240 112 -240
WIRE 304 -240 240 -240
WIRE 400 -240 304 -240
WIRE 448 -240 400 -240
WIRE 176 -128 96 -128
WIRE 304 -128 304 -240
WIRE 304 -128 240 -128
WIRE -144 -112 -144 -240
WIRE 448 -112 448 -240
WIRE 112 -32 112 -240
WIRE 176 -32 112 -32
WIRE 304 -32 240 -32
WIRE -144 96 -144 -32
WIRE 64 96 -144 96
WIRE 96 96 96 -128
WIRE 96 96 64 96
WIRE 176 96 96 96
WIRE 304 96 304 -32
WIRE 304 96 240 96
WIRE 448 96 448 -32
WIRE 448 96 304 96
WIRE 448 128 448 96
FLAG 448 128 0
FLAG 64 -240 a
FLAG 400 -240 out
FLAG 64 96 b
SYMBOL diode 240 -48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value RBR2VWM60A
SYMBOL Misc\\EuropeanResistor 432 -128 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL Misc\\signal -144 -128 R0
WINDOW 123 0 0 Left 2
SYMATTR SpiceLine Rser=0.5
SYMATTR InstName V1
SYMATTR Value SINE(0 50 100)
SYMBOL diode 176 -224 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RBR2VWM60A
SYMBOL diode 176 -112 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D3
SYMATTR Value RBR2VWM60A
SYMBOL diode 240 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D4
SYMATTR Value RBR2VWM60A
TEXT -144 128 Left 2 !.tran 50m