Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\02aa06bafee5_isolated_gate_driver_using_pulse_transformer_LTSPICE.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N006 N003 100
L2 0 N004 900
D1 N006 N003 1N5818
V1 N003 0 5V
M1 N006 N008 0 0 AO6408
R1 N008 0 1K
R2 N008 N007 10
V2 N007 0 PULSE(0 5 0 1n 1n 2.25m 0.5m) Rser=0.001
D2 N004 N005 1N5818
M2 N001 N005 0 0 FDMC8462
V3 N002 0 24
R3 N002 N001 24
R4 N005 0 1K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* ISOLATED GATE DRIVER USING PULSE TRANSFORMER
* to get 1:3 turns ratio you will have to give 1:9 inductance ratio
K L1 L2 1
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 904 744
WIRE 720 32 608 32
WIRE 848 32 800 32
WIRE 608 48 608 32
WIRE 64 64 -128 64
WIRE 160 64 64 64
WIRE 304 64 208 64
WIRE 448 64 368 64
WIRE 528 64 448 64
WIRE -128 96 -128 64
WIRE 160 96 160 64
WIRE 208 96 208 64
WIRE 64 112 64 64
WIRE 528 128 528 64
WIRE 560 128 528 128
WIRE 848 128 848 32
WIRE 448 176 448 144
WIRE 448 176 208 176
WIRE 608 176 608 144
WIRE 608 176 448 176
WIRE 64 192 64 176
WIRE 160 192 160 176
WIRE 160 192 64 192
WIRE 608 192 608 176
WIRE 848 224 848 208
WIRE 160 272 160 192
WIRE -64 352 -224 352
WIRE 64 352 16 352
WIRE 112 352 64 352
WIRE -224 384 -224 352
WIRE -224 400 -224 384
WIRE 64 400 64 352
WIRE -224 512 -224 464
WIRE 64 512 64 480
WIRE 112 512 64 512
WIRE 160 512 160 368
WIRE 160 512 112 512
WIRE 112 528 112 512
FLAG -128 176 0
FLAG -224 512 0
FLAG 112 528 0
FLAG 608 192 0
FLAG 848 224 0
SYMBOL ind2 144 192 M180
WINDOW 0 -37 85 Left 2
WINDOW 3 -21 35 Left 2
SYMATTR InstName L1
SYMATTR Value 100µ
SYMBOL ind2 224 192 R180
WINDOW 0 -36 86 Left 2
WINDOW 3 -25 37 Left 2
SYMATTR InstName L2
SYMATTR Value 900µ
SYMBOL zener 80 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N5818
SYMBOL voltage -128 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL nmos 112 272 R0
SYMATTR InstName M1
SYMATTR Value AO6408
SYMBOL res 48 384 R0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 32 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL voltage -224 368 R0
WINDOW 3 -188 101 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 -188 129 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1n 1n 2.25m 0.5m)
SYMATTR SpiceLine Rser=0.001
SYMBOL zener 304 80 R270
WINDOW 0 36 32 VTop 2
WINDOW 3 -4 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value 1N5818
SYMBOL nmos 560 48 R0
SYMATTR InstName M2
SYMATTR Value FDMC8462
SYMBOL voltage 848 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 24
SYMBOL res 816 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 24
SYMBOL res 432 48 R0
SYMATTR InstName R4
SYMATTR Value 1K
TEXT 96 -120 Left 2 ;ISOLATED GATE DRIVER USING PULSE TRANSFORMER
TEXT -24 704 Left 2 ;to get 1:3 turns ratio you will have to give 1:9 inductance ratio
TEXT 128 24 Left 2 !K L1 L2 1
TEXT -416 728 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\007d18e2d0ed_2b.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 Vref N002 V -V N001 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
M1 Vin N001 Output Output NMOS l=1u w=10u
R1 Output N002 {R}
R2 N002 0 3k
V1 V 0 15
V2 -V 0 -15
V3 Vref 0 3
V4 Vin 0 17.024
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model M1 nmos(vto=0.7 kp=1e-6 lambda=0)
.tran 1m
.step param R 3k 7k 1k
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1228 680
WIRE 384 48 384 -32
WIRE 464 96 384 96
WIRE 144 112 112 112
WIRE 336 128 208 128
WIRE 144 144 96 144
WIRE 464 144 464 96
WIRE 464 144 384 144
WIRE 384 192 384 144
WIRE 464 192 384 192
WIRE 96 304 96 144
WIRE 384 304 384 272
WIRE 384 304 96 304
WIRE 384 336 384 304
FLAG 176 160 V
FLAG 176 96 -V
FLAG 384 416 0
FLAG 112 112 Vref
FLAG 464 192 Output
IOPIN 464 192 Out
FLAG 768 96 0
FLAG 880 96 0
FLAG 992 96 0
FLAG 768 16 V
FLAG 880 16 -V
FLAG 992 16 Vref
FLAG 1120 96 0
FLAG 1120 16 Vin
FLAG 384 -32 Vin
SYMBOL OpAmps\\UniversalOpAmp2 176 128 M180
SYMATTR InstName U1
SYMBOL nmos4 336 48 R0
SYMATTR InstName M1
SYMATTR Value2 l=1u w=10u
SYMBOL res 368 176 R0
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL res 368 320 R0
SYMATTR InstName R2
SYMATTR Value 3k
SYMBOL voltage 768 0 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 880 0 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 992 0 R0
SYMATTR InstName V3
SYMATTR Value 3
SYMBOL voltage 1120 0 R0
SYMATTR InstName V4
SYMATTR Value 17.024
TEXT 72 488 Left 2 !.model M1 nmos(vto=0.7 kp=1e-6 lambda=0)
TEXT 48 512 Left 2 !.tran 1m
TEXT 56 544 Left 2 !.step param R 3k 7k 1k
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3060-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3060-1.2.asy)
V1 IN 0 12
Rload OUT 0 12
C2 OUT N001 10n
XU1 N002 N001 OUT MP_01 IN MP_02 IN 0 LT3060-1.2 ;pnba Ref/Byp)ADJ)OUT))IN))_SHDN)GND
C1 N002 0 10n
C3 OUT 0 10
.tran .1 startup
.lib LT3060-1.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 112 -16 112
WIRE 96 112 0 112
WIRE 112 112 96 112
WIRE 432 112 368 112
WIRE 544 112 432 112
WIRE 624 112 544 112
WIRE -16 128 -16 112
WIRE 544 128 544 112
WIRE 624 128 624 112
WIRE 432 144 432 112
WIRE -16 224 -16 208
WIRE 96 224 96 112
WIRE 112 224 96 224
WIRE 432 224 432 208
WIRE 432 224 368 224
WIRE 544 224 544 192
WIRE 624 224 624 208
WIRE 112 336 80 336
WIRE 400 336 368 336
WIRE 400 352 400 336
WIRE 400 432 400 416
SYMBOL cap 416 144 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 608 112 R0
SYMATTR InstName Rload
SYMATTR Value 12
SYMBOL cap 384 352 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL cap 528 128 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL PowerProducts\\LT3060-1.2 240 224 R0
SYMATTR InstName U1
SYMBOL voltage -16 112 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 80 336 0
FLAG -16 224 0
FLAG 400 432 0
FLAG 544 224 0
FLAG 624 224 0
FLAG 624 112 OUT
FLAG 0 112 IN
TEXT 480 320 Left 2 !.tran .1 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADAQ23876.asc
* Generated by LTspice 26.0.1 for Windows.
* Simulation Settings:
* Power Supplies:
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\ADAQ23876.asy)
;.tran 10u
;.ac dec 100 100 10G
V5 VDD 0 5
V2 N004 0 PULSE(0 1.8 66.6n .2n .2n 5n 66.6n)
XU1 N001 N002 N002 NC_01 NC_02 N003 N003 N005 NC_03 NC_04 VS_P VS_P VS_N NC_05 NC_06 NC_07 VDD Vout N004 0 ADAQ23876 ;pnba OUT+)IN-_2)IN-_1)SJ-)SJ+)IN+_1)IN+_2)OUT-)ADCIN+)ADCIN-)VS+)PDB_AMP)VS-)REF_IN)VCMO)REFBUF)VDD)Vout)CNV)ADC_GND
V1 VS_P 0 6.5
V4 N003 N002 SINE(0 1.8189 100k) AC 1
V3 VS_N 0 -2
.noise V(Vout) V1 dec 500 100 10G
.lib ADAQ23876.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1496 700
WIRE -144 -480 -144 -560
WIRE 432 -480 432 -560
WIRE -560 -336 -640 -336
WIRE -688 -288 -816 -288
WIRE -560 -288 -688 -288
WIRE -688 -240 -688 -288
WIRE -560 -240 -688 -240
WIRE 656 -240 544 -240
WIRE 704 -240 656 -240
WIRE -816 -208 -816 -288
WIRE -1488 -112 -1488 -160
WIRE -1344 -112 -1344 -160
WIRE -1200 -112 -1200 -160
WIRE -1488 -80 -1488 -112
WIRE -1344 -80 -1344 -112
WIRE -1200 -80 -1200 -112
WIRE -560 -64 -688 -64
WIRE 704 -64 544 -64
WIRE -816 -16 -816 -128
WIRE -688 -16 -688 -64
WIRE -688 -16 -816 -16
WIRE -560 -16 -688 -16
WIRE 704 -16 704 -64
WIRE -1488 32 -1488 0
WIRE -1344 32 -1344 0
WIRE -1344 32 -1488 32
WIRE -1200 32 -1200 0
WIRE -1200 32 -1344 32
WIRE -560 32 -640 32
WIRE -1488 64 -1488 32
WIRE 704 144 704 64
WIRE -192 256 -192 176
WIRE -144 256 -144 176
WIRE 128 272 128 176
RECTANGLE Normal -1104 128 -1600 -400 2
SYMBOL voltage -1344 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 6.5
SYMBOL voltage -816 -112 R180
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value SINE(0 1.8189 100k)
SYMBOL voltage -1488 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -2
SYMBOL voltage 704 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1.8 66.6n .2n .2n 5n 66.6n)
SYMBOL voltage -1200 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL ADAQ23876 -192 -176 R0
SYMATTR InstName U1
FLAG 704 144 0
FLAG -1488 64 0
FLAG -1488 -112 VS_N
FLAG -1344 -112 VS_P
FLAG -1200 -112 VDD
FLAG 656 -240 Vout
FLAG 432 -560 VDD
FLAG -192 256 VS_P
FLAG -144 -560 VS_P
FLAG -144 256 VS_N
FLAG 128 272 0
TEXT -1568 -376 Left 2 ;Simulation Settings:
TEXT -1552 -336 Left 2 !.noise V(Vout) V1 dec 500 100 10G
TEXT -1552 -272 Left 2 !;.tran 10u
TEXT -1552 -304 Left 2 !;.ac dec 100 100 10G
TEXT -1568 -216 Left 2 ;Power Supplies:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8606.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8606.asy)
XU1 IN N001 +V -V OUT AD8606 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 2.5
R1 N001 0 10K
Rload OUT 0 10K
R2 OUT N001 10K
V2 -V 0 -2.5
Vin IN 0 SINE(0 1 100K)
.tran 100u
.lib AD8606.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1240 700
WIRE 464 -1184 448 -1184
WIRE 560 -1184 544 -1184
WIRE 576 -1184 560 -1184
WIRE 672 -1184 656 -1184
WIRE 224 -1072 224 -1088
WIRE 336 -1072 336 -1088
WIRE 560 -1072 560 -1184
WIRE 576 -1072 560 -1072
WIRE 672 -1056 672 -1184
WIRE 672 -1056 640 -1056
WIRE 800 -1056 672 -1056
WIRE 576 -1040 464 -1040
WIRE 800 -1040 800 -1056
WIRE 464 -1024 464 -1040
WIRE 224 -976 224 -992
WIRE 336 -976 336 -992
WIRE 800 -944 800 -960
WIRE 464 -928 464 -944
SYMBOL res 672 -1200 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 464 -1040 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL voltage 224 -1088 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 560 -1200 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 784 -1056 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 336 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL AD8606 608 -1120 R0
SYMATTR InstName U1
FLAG 224 -1088 +V
FLAG 224 -976 0
FLAG 464 -928 0
FLAG 800 -1056 OUT
FLAG 464 -1040 IN
FLAG 608 -1088 +V
FLAG 336 -1088 -V
FLAG 608 -1024 -V
FLAG 448 -1184 0
FLAG 800 -944 0
FLAG 336 -976 0
TEXT 752 -880 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\098f27b328b5_Leitungstheorie-RG58.asc
* Generated by LTspice 26.0.1 for Windows.
* RG58 wire with high-impedance closing\nCreated by AblL
O1 N001 0 N002 0 RG58
R1 N002 0 10Meg
V1 N001 0 PULSE(0 20 0 0.01n 0.01n 10n 1m) Rser=50
.tran 0 2us 0 0.1n
.inc lib/RG58.mod
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 112 -144 112
WIRE 512 112 224 112
WIRE -144 144 -144 112
WIRE 128 144 0 144
WIRE 352 144 224 144
WIRE 512 144 512 112
WIRE 0 192 0 144
WIRE 352 192 352 144
WIRE -144 240 -144 224
WIRE 512 240 512 224
SYMBOL voltage -144 128 R0
WINDOW 3 -191 147 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 -191 175 Left 2
SYMATTR Value PULSE(0 20 0 0.01n 0.01n 10n 1m)
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMBOL res 496 128 R0
SYMATTR InstName R1
SYMATTR Value 10Meg
SYMBOL ltline 176 128 R0
SYMATTR InstName O1
SYMATTR Value RG58
FLAG 0 192 0
FLAG 352 192 0
FLAG 512 240 0
FLAG -144 240 0
TEXT 8 40 Left 2 !.tran 0 2us 0 0.1n
TEXT 8 16 Left 2 !.inc lib/RG58.mod
TEXT 0 -40 Left 2 ;RG58 wire with high-impedance closing\nCreated by AblL
* Z:\home\khalils\Downloads\files\data\raw_asc\34f4eb0e8788_Fig_8-12_LowPass_Filter_AC.asc
* Generated by LTspice 26.0.1 for Windows.
* .PARAM C 0.1u
* .STEP PARAM R list 1K 10K 100K
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6231.asy)
R5 IN N002 {R}
XU2 N002 OUT2 OUT2 VP VN LT6231 ;pnba IN+)IN-)OUT)VCC)VEE
C1 N001 OUT1 {C}
R1 IN N001 {RI}
VP VP 0 +5
C2 N002 0 {C}
V1 IN 0 AC 1
XU1 0 N001 OUT1 VP VN LT6231 ;pnba IN+)IN-)OUT)VCC)VEE
R2 N001 OUT1 {R}
VN VN 0 -5
.ac oct 100 0.1 10Meg
.STEP PARAM C list 0.001u 0.01u 0.1u
.PARAM R 10K
.PARAM RI 100
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 680
WIRE 160 -96 112 -96
WIRE 256 -96 224 -96
WIRE 112 0 112 -96
WIRE 144 0 112 0
WIRE 256 0 256 -96
WIRE 256 0 224 0
WIRE 864 0 720 0
WIRE 784 96 784 80
WIRE 176 112 176 96
WIRE 720 112 720 0
WIRE 752 112 720 112
WIRE -96 128 -128 128
WIRE -32 128 -96 128
WIRE 112 128 112 0
WIRE 112 128 48 128
WIRE 144 128 112 128
WIRE 864 128 864 0
WIRE 864 128 816 128
WIRE 896 128 864 128
WIRE 256 144 256 0
WIRE 256 144 208 144
WIRE 288 144 256 144
WIRE 560 144 512 144
WIRE 672 144 640 144
WIRE 752 144 672 144
WIRE 144 160 96 160
WIRE -128 176 -128 128
WIRE 672 176 672 144
WIRE 784 176 784 160
WIRE 176 192 176 176
WIRE 672 272 672 240
WIRE -128 288 -128 256
SYMBOL Opamps\\LT6231 784 128 R0
SYMATTR InstName U2
SYMBOL res -48 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value {RI}
SYMBOL cap 160 -80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value {C}
SYMBOL res 544 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value {R}
SYMBOL voltage -128 160 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL res 128 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value {R}
SYMBOL Opamps\\LT6231 176 144 R0
SYMATTR InstName U1
SYMBOL cap 656 176 R0
SYMATTR InstName C2
SYMATTR Value {C}
FLAG 176 96 VP
FLAG 176 192 VN
FLAG 96 160 0
FLAG 288 144 OUT1
FLAG -128 288 0
FLAG -96 128 IN
FLAG 784 80 VP
FLAG 784 176 VN
FLAG 896 128 OUT2
FLAG 512 144 IN
FLAG 672 272 0
TEXT 72 280 Left 2 !VP VP 0 +5\nVN VN 0 -5
TEXT -48 368 Left 2 !.ac oct 100 0.1 10Meg
TEXT 304 -136 Left 2 !.STEP PARAM C list 0.001u 0.01u 0.1u
TEXT 304 -40 Left 2 !.PARAM R 10K
TEXT 304 -8 Left 2 !.PARAM RI 100
TEXT 304 -104 Left 2 ;.PARAM C 0.1u
TEXT 304 24 Left 2 ;.STEP PARAM R list 1K 10K 100K
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8644S.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5
R1 N005 0 17.8k
C1 N006 0 1n
L1 N001 OUT 150n Rser=6m
R2 N002 0 100k
C2 OUT 0 330 x2 Rser=4m
Rload OUT 0 0.08
R3 OUT N002 100k
C4 OUT N002 47p
C3 N004 0 1n
R4 N004 N003 11k
XU2 0 NC_01 0 IN IN MP_02 NC_03 N001 MP_04 MP_05 MP_06 MP_07 MP_08 MP_09 MP_10 MP_11 IN N005 NC_12 NC_13 N006 N003 NC_14 N002 LT8644S ;pnba PHMODE)INTVcc)GND)SVin)PVin))BST)SW)))))))))EN/UV)Rt)CLKout)SYNC/Mode)SS)Vc)PG)FB
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8644S.asy)
.lib LT8644S.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1044 680
WIRE 96 -64 -32 -64
WIRE 128 -64 96 -64
WIRE -32 -48 -32 -64
WIRE 96 -32 96 -64
WIRE 128 -32 96 -32
WIRE 96 32 96 -32
WIRE 128 32 96 32
WIRE 448 32 416 32
WIRE 576 32 528 32
WIRE 656 32 576 32
WIRE 816 32 656 32
WIRE 944 32 816 32
WIRE -32 48 -32 32
WIRE 576 48 576 32
WIRE 656 48 656 32
WIRE 816 48 816 32
WIRE 944 48 944 32
WIRE 128 128 80 128
WIRE 576 128 576 112
WIRE 576 128 416 128
WIRE 656 128 576 128
WIRE 656 144 656 128
WIRE 816 144 816 112
WIRE 944 144 944 128
WIRE 448 224 416 224
WIRE 560 224 528 224
WIRE 560 240 560 224
WIRE 656 240 656 224
WIRE 32 320 0 320
WIRE 128 320 112 320
WIRE 560 320 560 304
WIRE 32 416 0 416
WIRE 128 416 96 416
WIRE 272 496 272 480
FLAG -32 48 0
FLAG 0 320 0
FLAG 0 416 0
FLAG 272 496 0
FLAG 656 240 0
FLAG 816 144 0
FLAG 944 144 0
FLAG 560 320 0
FLAG 944 32 OUT
FLAG -32 -64 IN
FLAG 80 128 0
SYMBOL voltage -32 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 128 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 17.8k
SYMBOL cap 96 400 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL ind 432 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150n
SYMATTR SpiceLine Rser=6m
SYMBOL res 640 128 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL cap 800 48 R0
WINDOW 123 24 54 Left 2
WINDOW 3 39 31 Left 2
SYMATTR Value2 x2
SYMATTR Value 330
SYMATTR InstName C2
SYMATTR SpiceLine Rser=4m
SYMBOL res 928 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.08
SYMBOL res 640 32 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL cap 560 48 R0
SYMATTR InstName C4
SYMATTR Value 47p
SYMBOL cap 544 240 R0
SYMATTR InstName C3
SYMATTR Value 1n
SYMBOL res 544 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 11k
SYMBOL LT8644S 272 176 R0
SYMATTR InstName U2
TEXT 488 424 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\11b02168e93e_FET03op.asc
* Generated by LTspice 26.0.1 for Windows.
Vdd N001 0 {Vdd}
R2 g 0 {R2}
Rs s 0 {Rs}
Rd N001 d {Rd}
J1 d g s JFET
R1 N001 g {R1}
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.op
.model JFET njf(Beta=3m Vto=-5)
.param Vdd=25 Rs=120 Rd=560 R1=4.7Meg R2=680k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1608 1076
WIRE 192 -128 16 -128
WIRE 384 -128 192 -128
WIRE 16 -80 16 -128
WIRE 192 -80 192 -128
WIRE 192 32 192 0
WIRE 192 48 192 32
WIRE 384 48 384 -128
WIRE 16 112 16 0
WIRE 96 112 16 112
WIRE 144 112 96 112
WIRE 192 160 192 144
WIRE 16 176 16 112
WIRE 192 176 192 160
WIRE 16 272 16 256
WIRE 192 272 192 256
WIRE 192 272 16 272
WIRE 384 272 384 128
WIRE 384 272 192 272
WIRE 192 288 192 272
SYMBOL voltage 384 32 R0
WINDOW 0 55 34 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdd
SYMATTR Value {Vdd}
SYMBOL njf 144 48 R0
SYMATTR InstName J1
SYMATTR Value JFET
SYMBOL res 176 160 R0
SYMATTR InstName Rs
SYMATTR Value {Rs}
SYMBOL res 0 -96 R0
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL res 0 160 R0
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL res 176 -96 R0
SYMATTR InstName Rd
SYMATTR Value {Rd}
FLAG 192 288 0
FLAG 96 112 g
FLAG 192 32 d
FLAG 192 160 s
TEXT 16 312 Left 2 !.op
TEXT 16 352 Left 2 !.model JFET njf(Beta=3m Vto=-5)
TEXT 16 392 Left 2 !.param Vdd=25 Rs=120 Rd=560 R1=4.7Meg R2=680k
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1550L.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1550L.asy)
C1 N002 N006 .1
Rload OUT 0 1K
R2 OUT N007 100K
R3 N007 0 100K
XU1 N001 N002 N003 OUT N006 0 0 N010 N011 N009 N008 N007 N005 N004 IN IN LTC1550L ;pnba NC)C+)NC)Vout)C-)PGND)AGND)NC)NC)NC)CPout)ADJ)NC)REG)_SHDN)Vin
C3 N008 0 .1
R1 IN N004 10K
V1 IN 0 4.5
C2 OUT 0 10
.tran 1m startup
.lib LTC1550L.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1600 908
WIRE 240 128 224 128
WIRE 576 128 528 128
WIRE 624 128 576 128
WIRE 752 128 624 128
WIRE 624 144 624 128
WIRE 752 144 752 128
WIRE 240 192 176 192
WIRE 576 192 576 128
WIRE 576 192 528 192
WIRE 176 208 176 192
WIRE 752 240 752 224
WIRE 240 256 224 256
WIRE 624 256 624 224
WIRE 624 256 528 256
WIRE -16 320 -144 320
WIRE 80 320 -16 320
WIRE 240 320 80 320
WIRE 544 320 528 320
WIRE -144 336 -144 320
WIRE -16 336 -16 320
WIRE 80 336 80 320
WIRE 176 384 176 272
WIRE 240 384 176 384
WIRE 656 384 528 384
WIRE -144 432 -144 416
WIRE -16 432 -16 400
WIRE 80 432 80 416
WIRE 176 432 80 432
WIRE 80 448 80 432
WIRE 240 448 224 448
WIRE 544 448 528 448
WIRE 624 448 608 448
WIRE 240 512 224 512
WIRE 544 512 528 512
WIRE 80 544 80 528
WIRE 240 576 224 576
WIRE 544 576 528 576
WIRE 176 640 176 432
WIRE 656 640 656 384
WIRE 656 640 176 640
SYMBOL PowerProducts\\LTC1550L 384 224 R0
SYMATTR InstName U1
SYMBOL res 64 320 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 608 128 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res -160 320 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL cap 544 464 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL res 64 432 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL VOLTAGE 752 128 R0
SYMATTR InstName V1
SYMATTR Value 4.5
SYMBOL cap -32 336 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL cap 160 208 R0
SYMATTR InstName C1
SYMATTR Value .1
FLAG -144 432 0
FLAG -16 432 0
FLAG 752 240 0
FLAG 224 448 0
FLAG 224 512 0
FLAG 624 448 0
FLAG 80 544 0
FLAG -144 320 OUT
FLAG 752 128 IN
TEXT 728 640 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0fc3fe4d1e6b_Fig13_30.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Vout Vin
M1 N001 Vin 0 0 N_50n l=50n w=500n
Cload Vout 0 50f
M2 VDD Vin N001 VDD P_50n l=50n w=500n
VDD VDD 0 1
V1 Vin 0 PULSE(0 1 500p 1p 1p 1n 6n)
M4 VDD N001 Vout VDD P_50n l=50n w=500n
M3 Vout N001 0 0 N_50n l=50n w=5u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 2n 0 1p
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3172 680
WIRE 192 -368 192 -384
WIRE 192 -352 192 -368
WIRE 192 -240 192 -272
WIRE 192 -160 192 -176
WIRE 192 -32 192 -80
WIRE 272 -176 192 -176
WIRE 368 -176 272 -176
WIRE 368 -176 368 -224
WIRE 368 -96 368 -176
WIRE 400 -224 368 -224
WIRE 400 -96 368 -96
WIRE 448 -304 448 -352
WIRE 448 -176 448 -208
WIRE 448 -32 448 -80
WIRE 624 -176 448 -176
WIRE 624 -176 624 -224
WIRE 624 -96 624 -176
WIRE 656 -224 624 -224
WIRE 656 -96 624 -96
WIRE 704 -304 704 -352
WIRE 704 -192 704 -208
WIRE 704 -176 704 -192
WIRE 704 -32 704 -80
WIRE 896 -192 704 -192
WIRE 960 -192 896 -192
WIRE 960 -48 960 -128
SYMBOL nmos4 400 -176 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 656 -176 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M3
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=5u
SYMBOL pmos4 400 -304 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=500n
SYMBOL cap 944 -192 R0
SYMATTR InstName Cload
SYMATTR Value 50f
SYMBOL voltage 192 -176 R0
WINDOW 3 -102 180 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 1 500p 1p 1p 1n 6n)
SYMATTR InstName V1
SYMBOL voltage 192 -368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 656 -304 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=500n
FLAG 448 -128 0
FLAG 192 -240 0
FLAG 192 -368 VDD
FLAG 448 -256 VDD
FLAG 448 -32 0
FLAG 448 -352 VDD
FLAG 704 -128 0
FLAG 704 -256 VDD
FLAG 704 -32 0
FLAG 704 -352 VDD
FLAG 960 -48 0
FLAG 192 -32 0
FLAG 896 -192 Vout
FLAG 272 -176 Vin
TEXT 88 48 Left 0 !.tran 0 2n 0 1p
TEXT 88 88 Left 0 !.lib cmosedu_models.txt
TEXT 264 -392 Left 0 ;Plot Vout Vin