* Z:\home\khalils\Downloads\files\data\raw_asc\28035ffc5782_spark_gap_model2.asc
* Generated by LTspice 26.0.1 for Windows.
* Simple Spark Gap
* .options plotwinsize=0
* REM2: 2nd if(..) can be ommitted,\nbut then it may 'forget' to switch off\nat very low Isust settings and when\ngoing through zero.\n(this is due to time step resolution)
* REM1: this model could be reduced to\n3 components using ABS(..) statements,\nbut then the effect mentionend in REM2\nwill show up.
* Ron was not included in the switch model due to voltage polarity change\nand convergence problem when operated\nwith a capacitor across the spark gap.
R1 2 1 1k
S2 0 N002 N003 0 SW1
B2 N003 0 V=if( V(2)/Vignit<-1,10, if(I(Bb)/Isus<-1,if(V(2)<-Vbmin,10,0),0) )
V2 1 0 PWL(0 0 1 2k 2 0 3 -2k 4 0)
S1 0 N002 N001 0 SW1
B1 N001 0 V=if( V(2)/Vignit>1,10, if(I(Bb)/Isus>1,if(V(2)>Vbmin,10,0),0) )
Bb 2 N002 V=sgn(V(2))*max((Vb+ABS(I(Bb))*(Ron-1)),0)
.model sw1 sw(Ron=1 Roff=1E18 Vt=1 Vh=1m) ;Vh is dummy
.param Vb=200 ;burning, upper limit
.param Vbmin= 50 ;burning, lower limit
.param Vignit=1000 ;ignition
.param Isus=1u ;sustain
.param Ron=-20 ;on resistance
.tran 0 4 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE -304 32 -304 -64
WIRE -304 432 -304 112
WIRE -224 -64 -304 -64
WIRE -64 224 -64 192
WIRE -64 384 -64 304
WIRE 16 192 -64 192
WIRE 16 240 16 192
WIRE 16 384 -64 384
WIRE 16 384 16 288
WIRE 64 -64 -144 -64
WIRE 64 32 64 -64
WIRE 64 192 64 112
WIRE 64 224 64 192
WIRE 64 384 16 384
WIRE 64 384 64 304
WIRE 64 432 64 384
WIRE 240 192 64 192
WIRE 240 224 240 192
WIRE 240 384 64 384
WIRE 240 384 240 304
WIRE 288 240 288 192
WIRE 288 384 240 384
WIRE 288 384 288 288
WIRE 368 192 288 192
WIRE 368 224 368 192
WIRE 368 384 288 384
WIRE 368 384 368 304
SYMBOL sw 240 320 R180
SYMATTR InstName S2
SYMATTR Value SW1
SYMBOL voltage 64 16 R0
WINDOW 3 56 50 Left 0
SYMATTR Value V=sgn(V(2))*max((Vb+ABS(I(Bb))*(Ron-1)),0)
SYMATTR InstName Bb
SYMATTR Prefix B
SYMBOL bv 368 208 M0
WINDOW 0 34 53 Left 0
WINDOW 3 -372 210 Left 0
SYMATTR InstName B2
SYMATTR Value V=if( V(2)/Vignit<-1,10, if(I(Bb)/Isus<-1,if(V(2)<-Vbmin,10,0),0) )
SYMBOL bv -64 208 R0
WINDOW 0 34 53 Left 0
WINDOW 3 -136 273 Left 0
SYMATTR InstName B1
SYMATTR Value V=if( V(2)/Vignit>1,10, if(I(Bb)/Isus>1,if(V(2)>Vbmin,10,0),0) )
SYMBOL res -128 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -304 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 13 112 Left 0
SYMATTR Value PWL(0 0 1 2k 2 0 3 -2k 4 0)
SYMATTR InstName V2
SYMBOL sw 64 320 M180
SYMATTR InstName S1
SYMATTR Value SW1
FLAG 64 432 0
FLAG -304 432 0
FLAG 64 -64 2
FLAG -304 -64 1
TEXT -224 544 Left 0 !.model sw1 sw(Ron=1 Roff=1E18 Vt=1 Vh=1m) ;Vh is dummy
TEXT 448 240 Left 0 !.param Vb=200       ;burning, upper limit\n.param Vbmin= 50 ;burning, lower limit\n.param Vignit=1000 ;ignition\n.param Isus=1u   ;sustain\n.param Ron=-20 ;on resistance
TEXT -370 506 Left 0 !.tran 0 4 0
TEXT -88 -152 Left 0 ;Simple Spark Gap
TEXT 448 200 Left 0 ;.options plotwinsize=0
TEXT 456 456 Left 0 ;REM2: 2nd if(..) can be ommitted,\nbut then it may 'forget' to switch off\nat very low Isust settings and when\ngoing through zero.\n(this is due to time step resolution)
TEXT 192 -128 Left 0 ;REM1: this model could be reduced to\n3 components using ABS(..) statements,\nbut then the effect mentionend in REM2\nwill show up.
TEXT 120 96 Left 0 ;Ron was not included in the switch model due to voltage polarity change\nand  convergence problem when operated\nwith a capacitor across the spark gap.