* Z:\home\khalils\Downloads\files\data\raw_asc\33edc5ee1d9d_falling_edge_dtype_latch_ltspice.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Qbar N001 Vp Vp CD4007-PMOS
M2 Qbar N001 0 0 CD4007-NMOS
M4 W2 W1 N001 Vp CD4007-PMOS
M3 N001 W1 Q 0 CD4007-NMOS
M5 Q Qbar Vp Vp CD4007-PMOS
M6 Q Qbar 0 0 CD4007-NMOS
V1 Vp 0 5
V2 W1 0 PULSE(-1 5 0 1p 1p 0.5m 1m)
V3 W2 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL CD4007-NMOS NMOS ( LEVEL = 1 L=5u W=20u
+VTO = 1.77 Kp = 2.169e-4 GAMMA = 4.10
+PHI = 0.65 LAMBDA = 1.5e-2 CBD = 20e-12
+CBS = 0 IS = 1e-15 PB = 0.87
+CBS = 2e-14 CGDO = 88e-8 CGBO = 0
+CJ = 2e-10 MJ = 0.5 CJSW = 1e-9
+MJSW = 0.33 JS = 1e-8 TOX = 1.265e-10)
.MODEL CD4007-PMOS PMOS ( LEVEL = 1 L=5u W=100u
+VTO = -1.40 KP = 3.2e-5 GAMMA = 3.30
+PHI = 0.65 LAMBDA = 9e-2 CBD = 65e-12
+CBS = 2e-14 IS = 1e-15 PB = 0.87
+CGSO = 0 CGDO = 0 CGBO = 1e-5
+CJ = 2e-10 MJ = 0.5 CJSW = 1e-9
+MJSW = 0.33 JS = 1e-8 TOX = 6.89e-10)
.tran 10m
* 6 Transistor Falling Edge D-Type Latch
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2840 1020
WIRE -1040 -208 -1040 -240
WIRE -928 -208 -928 -240
WIRE -816 -208 -816 -240
WIRE 176 -192 -96 -192
WIRE 176 -128 176 -192
WIRE 480 -128 416 -128
WIRE -1040 -96 -1040 -128
WIRE -928 -96 -928 -128
WIRE -816 -96 -816 -128
WIRE -96 -80 -96 -192
WIRE -96 -80 -176 -80
WIRE 96 -80 32 -80
WIRE 272 -80 192 -80
WIRE 368 -80 272 -80
WIRE 416 -80 416 -128
WIRE 528 -80 464 -80
WIRE 144 -64 144 -80
WIRE 192 -64 144 -64
WIRE -96 0 -96 -80
WIRE 448 0 448 -32
WIRE 448 0 -96 0
WIRE 272 32 272 -80
WIRE 272 32 32 32
WIRE 192 96 192 -64
WIRE 192 96 144 96
WIRE 400 96 192 96
WIRE 416 96 400 96
WIRE 144 112 144 96
WIRE 400 112 400 96
WIRE 416 112 400 112
WIRE 32 128 32 32
WIRE 96 128 32 128
WIRE 352 128 304 128
WIRE 416 160 416 112
WIRE 416 160 400 160
WIRE 144 256 144 208
WIRE 304 256 304 128
WIRE 304 256 144 256
WIRE 400 256 400 208
WIRE 528 256 528 -80
WIRE 528 256 400 256
WIRE 640 256 640 240
WIRE 640 256 528 256
WIRE 656 256 640 256
WIRE 144 320 144 256
WIRE 400 320 400 256
WIRE 416 368 400 368
WIRE 32 400 32 128
WIRE 96 400 32 400
WIRE 304 400 304 256
WIRE 352 400 304 400
WIRE 416 416 416 368
WIRE 416 416 400 416
WIRE 144 432 144 416
WIRE 400 432 400 416
WIRE 400 432 144 432
WIRE 480 432 480 -128
WIRE 480 432 400 432
WIRE 144 464 144 432
WIRE 304 496 304 400
WIRE 544 496 304 496
FLAG 144 464 0
FLAG 32 -80 W2
IOPIN 32 -80 In
FLAG 656 256 Q
IOPIN 656 256 In
FLAG 544 496 Qbar
IOPIN 544 496 In
FLAG 640 240 2+
IOPIN 640 240 In
FLAG -1040 -96 0
FLAG -928 -96 0
FLAG -816 -96 0
FLAG -1040 -240 Vp
IOPIN -1040 -240 In
FLAG -928 -240 W1
IOPIN -928 -240 In
FLAG -816 -240 W2
IOPIN -816 -240 In
FLAG 416 96 Vp
IOPIN 416 96 In
FLAG -176 -80 W1
IOPIN -176 -80 In
SYMBOL pmos 96 208 M180
SYMATTR InstName M1
SYMATTR Value CD4007-PMOS
SYMBOL nmos 96 320 R0
SYMATTR InstName M2
SYMATTR Value CD4007-NMOS
SYMBOL pmos4 96 -128 M90
WINDOW 0 62 43 VLeft 2
WINDOW 3 89 105 VLeft 2
SYMATTR InstName M4
SYMATTR Value CD4007-PMOS
SYMBOL nmos4 368 -32 R270
WINDOW 0 65 6 VRight 2
WINDOW 3 103 -14 VRight 2
SYMATTR InstName M3
SYMATTR Value CD4007-NMOS
SYMBOL pmos4 352 208 M180
SYMATTR InstName M5
SYMATTR Value CD4007-PMOS
SYMBOL nmos4 352 320 R0
SYMATTR InstName M6
SYMATTR Value CD4007-NMOS
SYMBOL voltage -1040 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -928 -224 R0
WINDOW 3 -30 170 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(-1 5 0 1p 1p 0.5m 1m)
SYMATTR InstName V2
SYMBOL voltage -816 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
TEXT 832 368 Left 1 !.MODEL CD4007-NMOS    NMOS    ( LEVEL   = 1           L=5u    W=20u             \n+VTO    = 1.77          Kp      = 2.169e-4      GAMMA   = 4.10  \n+PHI    = 0.65          LAMBDA  = 1.5e-2        CBD     = 20e-12\n+CBS    = 0             IS      = 1e-15         PB      = 0.87\n+CBS    = 2e-14         CGDO    = 88e-8         CGBO    = 0\n+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9\n+MJSW   = 0.33          JS      = 1e-8          TOX     = 1.265e-10)
TEXT 824 200 Left 1 !.MODEL CD4007-PMOS    PMOS    ( LEVEL   = 1           L=5u    W=100u                \n+VTO    = -1.40         KP      = 3.2e-5        GAMMA   = 3.30  \n+PHI    = 0.65          LAMBDA  = 9e-2          CBD     = 65e-12\n+CBS    = 2e-14         IS      = 1e-15         PB      = 0.87\n+CGSO   = 0             CGDO    = 0             CGBO    = 1e-5\n+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9\n+MJSW   = 0.33          JS      = 1e-8          TOX     = 6.89e-10)
TEXT -512 448 Left 2 !.tran 10m
TEXT -56 -280 Left 2 ;6 Transistor Falling Edge D-Type Latch