* Z:\home\khalils\Downloads\files\data\raw_asc\UniversalOpAmp4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
V3 N001 0 PULSE(-50m 50m 250n 1n 1n 1u 2u)
R1 OUT 0 10k
C1 OUT 0 10p
XU1 N001 OUT +V -V OUT level4 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg Ro=1k Ccm=1p Cdiff=2p ;pnba In+)In-)V+)V-)OUT
.tran 1.5u
* A two pole op amp with virtual ground, input and output impedance, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()\nRo = open-loop output resistance ()\nCcm = common-mode input capacitance (F)\nCdiff = differential input capacitance (F)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp4.asy)
.lib UniversalOpAmp4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2580 1412
WIRE 560 560 400 560
WIRE 496 624 496 608
WIRE 400 640 400 560
WIRE 464 640 400 640
WIRE 560 656 560 560
WIRE 560 656 528 656
WIRE 656 656 560 656
WIRE 464 672 400 672
WIRE 560 672 560 656
WIRE 656 672 656 656
WIRE 496 704 496 688
WIRE 176 752 176 736
WIRE 288 752 288 736
WIRE 400 752 400 672
WIRE 560 768 560 752
WIRE 656 768 656 736
WIRE 176 848 176 832
WIRE 288 848 288 832
WIRE 400 848 400 832
FLAG 288 848 0
FLAG 176 848 0
FLAG 176 736 +V
FLAG 288 736 -V
FLAG 400 848 0
FLAG 496 704 -V
FLAG 496 608 +V
FLAG 656 768 0
FLAG 560 768 0
FLAG 656 656 OUT
SYMBOL voltage 176 736 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 288 736 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 400 736 R0
WINDOW 0 25 13 Left 2
WINDOW 3 27 90 Left 2
WINDOW 123 27 116 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(-50m 50m 250n 1n 1n 1u 2u)
SYMBOL res 544 656 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 640 672 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL UniversalOpAmp4 496 656 R0
WINDOW 123 82 -103 Left 2
WINDOW 39 81 -74 Left 2
WINDOW 40 81 -43 Left 2
SYMATTR InstName U1
TEXT 152 904 Left 2 !.tran 1.5u
TEXT 376 920 Left 2 ;A two pole op amp with virtual ground, input and output impedance, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()\nRo = open-loop output resistance ()\nCcm = common-mode input capacitance (F)\nCdiff = differential input capacitance (F)