Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1306.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1306.asy)
L1 IN N002 10 Rpar=1K
D1 IN N001 MBR0530L
R1 OUT N005 768K
V1 IN 0 3
R2 N005 0 249K
C1 N002 N001 1
R3 N004 N003 118K
C3 N004 0 68p
Rload OUT 0 15
XU1 N004 N005 OUT 0 N002 N001 IN IN LT1306 ;pnba Vc)FB)OUT)GND)SW)CAP)Vin)_SHDN
C4 OUT 0 220
C2 N003 0 680p
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LT1306.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2592 1680
WIRE 1920 1040 1840 1040
WIRE 2064 1040 1984 1040
WIRE 1744 1136 1632 1136
WIRE 1840 1136 1840 1040
WIRE 1840 1136 1744 1136
WIRE 1856 1136 1840 1136
WIRE 1952 1136 1936 1136
WIRE 1984 1136 1952 1136
WIRE 2064 1136 2064 1040
WIRE 2064 1136 2048 1136
WIRE 1632 1152 1632 1136
WIRE 1840 1200 1840 1136
WIRE 1952 1200 1952 1136
WIRE 2064 1200 2064 1136
WIRE 1632 1248 1632 1232
WIRE 1744 1296 1744 1136
WIRE 1792 1296 1744 1296
WIRE 2176 1296 2112 1296
WIRE 2288 1296 2176 1296
WIRE 2400 1296 2288 1296
WIRE 2176 1312 2176 1296
WIRE 2288 1312 2288 1296
WIRE 2400 1312 2400 1296
WIRE 2288 1408 2288 1376
WIRE 2400 1408 2400 1392
WIRE 1616 1424 1584 1424
WIRE 1728 1424 1696 1424
WIRE 1792 1424 1728 1424
WIRE 2176 1424 2176 1392
WIRE 2176 1424 2112 1424
WIRE 1584 1456 1584 1424
WIRE 1728 1456 1728 1424
WIRE 2176 1456 2176 1424
WIRE 1584 1552 1584 1520
WIRE 1728 1552 1728 1520
WIRE 1952 1552 1952 1520
WIRE 2176 1552 2176 1536
SYMBOL polcap 1984 1120 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL polcap 2272 1312 R0
SYMATTR InstName C4
SYMATTR Value 220
SYMBOL ind 1840 1152 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rpar=1K
SYMBOL cap 1568 1456 R0
SYMATTR InstName C2
SYMATTR Value 680p
SYMBOL POWERPRODUCTS\\LT1306 1952 1360 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1632 1136 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL RES 2384 1296 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL RES 2160 1440 R0
SYMATTR InstName R2
SYMATTR Value 249K
SYMBOL RES 1712 1408 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 118K
SYMBOL cap 1712 1456 R0
SYMATTR InstName C3
SYMATTR Value 68p
SYMBOL RES 2160 1296 R0
SYMATTR InstName R1
SYMATTR Value 768K
SYMBOL schottky 1920 1056 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBR0530L
FLAG 2176 1552 0
FLAG 1952 1552 0
FLAG 1584 1552 0
FLAG 1728 1552 0
FLAG 1632 1248 0
FLAG 2288 1408 0
FLAG 2400 1408 0
FLAG 2400 1296 OUT
FLAG 1632 1136 IN
TEXT 2296 1520 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX15103.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX15103.asy)
Rload vOUT 0 0.5
XU1 0 vIN vOUT vIN N002 N003 N001 MAX15103 ;pnba GND)IN)OUT)EN)PG)SS_BYP)FB
R1 vOUT N001 909
R2 N001 0 604
Cout vOUT 0 22
V1 vIN 0 1.8
R3 vIN N002 100k
Css N003 0 33n
.tran 2.5m startup
.lib MAX15103.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 32 32 -64 32
WIRE 112 32 32 32
WIRE 144 32 112 32
WIRE 464 32 336 32
WIRE 592 32 464 32
WIRE 704 32 592 32
WIRE 464 48 464 32
WIRE 704 48 704 32
WIRE -64 64 -64 32
WIRE 32 64 32 32
WIRE 592 64 592 32
WIRE 112 96 112 32
WIRE 144 96 112 96
WIRE 464 144 464 128
WIRE 464 144 336 144
WIRE 592 144 592 128
WIRE 704 144 704 128
WIRE 464 160 464 144
WIRE -64 176 -64 144
WIRE 32 176 32 144
WIRE 144 176 32 176
WIRE 464 256 464 240
WIRE 144 272 128 272
WIRE 368 272 336 272
WIRE 368 288 368 272
WIRE 368 368 368 352
SYMBOL MAX15103 240 160 R0
SYMATTR InstName U1
SYMBOL res 448 32 R0
SYMATTR InstName R1
SYMATTR Value 909
SYMBOL res 448 144 R0
SYMATTR InstName R2
SYMATTR Value 604
SYMBOL voltage -64 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL cap 576 64 R0
SYMATTR InstName Cout
SYMATTR Value 22
SYMBOL res 688 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.5
SYMBOL cap 352 288 R0
SYMATTR InstName Css
SYMATTR Value 33n
SYMBOL res 16 48 R0
SYMATTR InstName R3
SYMATTR Value 100k
FLAG -64 176 0
FLAG 128 272 0
FLAG 464 256 0
FLAG 368 368 0
FLAG 592 144 0
FLAG 704 144 0
FLAG -64 32 vIN
FLAG 704 32 vOUT
TEXT 144 336 Left 2 !.tran 2.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\01f58085b77a_2022023_3.asc
* Generated by LTspice 26.0.1 for Windows.
D2 N003 N004 D
V1 N001 N004 SINE(0 15 50)
D4 N001 N002 D
D1 N001 N003 D
D3 N004 N002 D
R1 N002 N003 1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 80 -32 80
WIRE 112 80 64 80
WIRE 224 80 176 80
WIRE 384 80 224 80
WIRE 64 112 64 80
WIRE 224 112 224 80
WIRE 384 128 384 80
WIRE -32 144 -32 80
WIRE 64 208 64 176
WIRE 96 208 64 208
WIRE 224 208 224 176
WIRE 224 208 160 208
WIRE 64 256 64 208
WIRE 384 256 384 208
WIRE 384 256 64 256
WIRE -32 288 -32 224
WIRE 224 288 224 208
WIRE 224 288 -32 288
SYMBOL diode 112 96 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D4
SYMBOL diode 96 224 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMBOL res 368 112 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -32 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 15 50)
SYMBOL diode 240 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMBOL diode 48 112 R0
SYMATTR InstName D1
* Z:\home\khalils\Downloads\files\data\raw_asc\00d1ce32ceff_TS14_Rev1.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 N001 1
C1 N002 0 2
L2 Vo N002 1
R2 Vo 0 1
V1 N001 0 SINE(0 1 1 0 0 0 1000) AC 1 0 Rser=1
.net I(R2) v1
.param f = w/(2*pi)
.step dec param w 0.01 100 30
.ac list {f}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 112 -16 112
WIRE 320 112 256 112
WIRE 384 112 320 112
WIRE 512 112 464 112
WIRE 560 112 512 112
WIRE 320 160 320 112
WIRE -16 176 -16 112
WIRE 560 176 560 112
WIRE -16 320 -16 256
WIRE 320 320 320 224
WIRE 320 320 -16 320
WIRE 560 320 560 256
WIRE 560 320 320 320
FLAG 320 320 0
FLAG 512 112 Vo
SYMBOL ind 272 96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL cap 304 160 R0
SYMATTR InstName C1
SYMATTR Value 2
SYMBOL ind 480 96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L2
SYMATTR Value 1
SYMBOL res 544 160 R0
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL voltage -16 160 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 24 44 Left 2
SYMATTR Value SINE(0 1 1 0 0 0 1000)
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
TEXT 600 120 Left 2 !.net I(R2) v1
TEXT -40 384 Left 2 !.param f = w/(2*pi)\n.step dec param w 0.01 100 30\n.ac list {f}
* Z:\home\khalils\Downloads\files\data\raw_asc\47d2dffe5211_protection.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 0 1k
D1 0 N001 KDZ20B
V1 N001 0 12
M1 N001 0 N002 N002 IRF7204
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 80 0 80
WIRE 240 80 192 80
WIRE 448 80 336 80
WIRE 0 112 0 80
WIRE 192 112 192 80
WIRE 448 128 448 80
WIRE 0 272 0 192
WIRE 192 272 192 176
WIRE 192 272 0 272
WIRE 320 272 320 128
WIRE 320 272 192 272
WIRE 448 272 448 208
WIRE 448 272 320 272
WIRE 0 288 0 272
SYMBOL voltage 0 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 432 112 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL zener 208 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value KDZ20B
SYMATTR Type tvsdiode
SYMBOL pmos 240 128 R270
WINDOW 3 76 71 VRight 2
SYMATTR InstName M1
SYMATTR Value IRF7204
FLAG 0 288 0
TEXT -32 312 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\801e98c8d774_OR.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N003 N002 0 0 C5NNMOS l=0.6u w=3.6u
M2 N003 N005 0 0 C5NNMOS l=0.6u w=3.6u
M3 N001 N002 N004 N001 C5NPMOS l=0.6u w=7.2u
M4 N004 N005 N003 N001 C5NPMOS l=0.6u w=7.2u
VA N002 0 PULSE(0 5 0 1n 1n 5u 10u)
VB N005 0 PULSE(0 5 0 1n 1n 10u 20u)
V3 N001 0 5
M5 N001 N003 Vout N001 C5NPMOS l=0.6u w=7.2u
M6 Vout N003 0 0 C5NNMOS l=0.6u w=3.6u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include D:\NIELIT\ENGR3426\ENGR3426\engr3426.sub
.tran 100u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1232 680
WIRE 416 -160 288 -160
WIRE 528 -160 416 -160
WIRE 848 -160 528 -160
WIRE 960 -160 848 -160
WIRE 528 -128 528 -160
WIRE 288 -96 288 -160
WIRE 848 -96 848 -160
WIRE 416 -48 416 -160
WIRE 416 -48 288 -48
WIRE 960 -48 960 -160
WIRE 960 -48 848 -48
WIRE -32 -16 -480 -16
WIRE 240 -16 -32 -16
WIRE 528 -16 528 -48
WIRE 800 -16 624 -16
WIRE 288 64 288 0
WIRE 848 64 848 0
WIRE 1120 64 848 64
WIRE 416 112 416 -48
WIRE 416 112 288 112
WIRE 848 128 848 64
WIRE -112 144 -288 144
WIRE 240 144 -112 144
WIRE -288 160 -288 144
WIRE -480 176 -480 -16
WIRE 288 176 288 160
WIRE 624 176 624 -16
WIRE 624 176 288 176
WIRE 976 176 848 176
WIRE 288 208 288 176
WIRE 288 208 128 208
WIRE 400 208 288 208
WIRE 624 208 624 176
WIRE 800 208 624 208
WIRE -288 272 -288 240
WIRE -480 288 -480 256
WIRE 128 288 128 208
WIRE 400 288 400 208
WIRE 256 336 128 336
WIRE 512 336 400 336
WIRE -32 368 -32 -16
WIRE 80 368 -32 368
WIRE -112 400 -112 144
WIRE 352 400 352 368
WIRE 352 400 -112 400
WIRE 128 432 128 384
WIRE 256 432 256 336
WIRE 256 432 128 432
WIRE 400 432 400 384
WIRE 400 432 256 432
WIRE 512 432 512 336
WIRE 512 432 400 432
WIRE 848 432 848 224
WIRE 848 432 512 432
WIRE 976 432 976 176
WIRE 976 432 848 432
WIRE 256 448 256 432
FLAG -480 288 0
FLAG -288 272 0
FLAG 528 -16 0
FLAG 256 448 0
FLAG 1120 64 Vout
IOPIN 1120 64 Out
SYMBOL nmos4 80 288 R0
SYMATTR InstName M1
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL nmos4 352 288 R0
SYMATTR InstName M2
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL pmos4 240 -96 R0
SYMATTR InstName M3
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL pmos4 240 64 R0
SYMATTR InstName M4
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL voltage -480 160 R0
WINDOW 3 -6 167 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VA
SYMATTR Value PULSE(0 5 0 1n 1n 5u 10u)
SYMBOL voltage -288 144 R0
WINDOW 3 -200 222 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VB
SYMATTR Value PULSE(0 5 0 1n 1n 10u 20u)
SYMBOL voltage 528 -144 R0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL pmos4 800 -96 R0
SYMATTR InstName M5
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL nmos4 800 128 R0
SYMATTR InstName M6
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
TEXT -512 448 Left 2 !.include D:\\NIELIT\\ENGR3426\\ENGR3426\\engr3426.sub
TEXT -512 472 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\3d80200d9ffc_4_8a.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Out Triangle 100k
R3 N001 0 100k
VCC Vcc 0 10V
C1 Triangle 0 10n
XU1 N001 Triangle Vcc Vee Out uA741 ;pnba In+)In-)V+)V-)OUT
R2 Out N001 100k
VEE Vee 0 -10V
.inc uA741.lib
.tran .02
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 940 680
WIRE 688 -80 336 -80
WIRE 336 -64 336 -80
WIRE -96 16 -96 -16
WIRE 0 16 0 -16
WIRE 336 64 336 16
WIRE 480 64 336 64
WIRE 688 80 688 -80
WIRE 688 80 544 80
WIRE 880 80 688 80
WIRE 480 96 432 96
WIRE 688 112 688 80
WIRE -96 128 -96 96
WIRE 0 128 0 96
WIRE 432 224 432 96
WIRE 688 224 688 192
WIRE 688 224 432 224
WIRE 336 256 336 64
WIRE 688 256 688 224
WIRE 336 352 336 320
WIRE 480 352 336 352
WIRE 688 352 688 336
WIRE 688 352 480 352
WIRE 480 400 480 352
SYMBOL res 672 96 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage -96 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCC
SYMATTR Value 10V
SYMBOL res 320 -80 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 672 240 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL OpAmps\\opamp2 512 16 R0
SYMATTR InstName U1
SYMATTR Value uA741
SYMBOL voltage 0 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VEE
SYMATTR Value -10V
SYMBOL cap 320 256 R0
SYMATTR InstName C1
SYMATTR Value 10n
FLAG -96 128 0
FLAG 0 128 0
FLAG -96 -16 Vcc
FLAG 0 -16 Vee
FLAG 512 48 Vcc
FLAG 512 112 Vee
FLAG 480 400 0
FLAG 880 80 Out
FLAG 336 64 Triangle
TEXT -104 216 Left 2 !.inc uA741.lib
TEXT -96 272 Left 2 !.tran .02
* Z:\tmp\asc_dec_bjh7r6w2\0a01783c50d9_SE_DE_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N003 N004 {Res}
R3 Vout- OPAMP_- 47
C3 N002 Vout- 0.1n
R2 OPAMP_- N003 {Res}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1524 760
WIRE 1104 144 1008 144
WIRE 1248 144 1248 96
WIRE 1248 144 1184 144
WIRE 1456 144 1248 144
WIRE 1248 240 1248 144
WIRE 720 416 672 416
WIRE 928 416 800 416
WIRE 992 416 928 416
WIRE 1104 416 992 416
WIRE 1248 416 1248 304
WIRE 1248 416 1184 416
WIRE 1424 416 1248 416
WIRE 1520 416 1424 416
WIRE 1248 480 1248 416
WIRE 528 576 528 176
WIRE 576 576 528 576
WIRE 672 576 672 416
WIRE 672 576 656 576
WIRE 704 576 672 576
WIRE 928 608 928 416
WIRE 928 608 848 608
WIRE 1248 608 1248 544
WIRE 704 640 576 640
WIRE 576 688 576 640
SYMBOL res 672 560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {Res}
SYMBOL res 1200 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 47
SYMBOL cap 1232 240 R0
SYMATTR InstName C3
SYMATTR Value 0.1n
SYMBOL res 816 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {Res}
FLAG 1424 416 Vout-
FLAG 576 688 0
FLAG 736 528 +V
FLAG 720 224 -V
FLAG 736 688 -V
FLAG 992 416 OPAMP_-
* Z:\home\khalils\Downloads\files\data\raw_asc\2fce557217ca_fig-01-03-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4077-2.asy)
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 NC_07 NC_08 ADA4077-2 ;pnba +INA)-INA)OUTA)V+)V-)+INB)-INB)OUTB
VS1 VCC 0 15
D1 VOP VOUT 1N4148
R1 VOUT 0 1k
VS2 0 VEE 15
V1 VIN 0 SINE(0 1 1k)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 2m 0 1u
.lib ADA4077-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 400 80 144 80
WIRE 208 112 208 96
WIRE 208 144 208 112
WIRE 144 160 144 80
WIRE 176 160 144 160
WIRE 288 176 240 176
WIRE 304 176 288 176
WIRE 400 176 400 80
WIRE 400 176 368 176
WIRE 432 176 400 176
WIRE 96 192 48 192
WIRE 176 192 96 192
WIRE 48 208 48 192
WIRE 400 208 400 176
WIRE 208 240 208 208
WIRE 208 256 208 240
WIRE 256 288 256 272
WIRE 320 288 320 272
WIRE 400 320 400 288
WIRE 48 336 48 288
WIRE 256 336 256 288
WIRE 320 336 320 288
WIRE 256 432 256 416
WIRE 320 432 320 416
IOPIN 432 176 Out
SYMBOL Opamps\\ADA4077-2 208 112 R0
WINDOW 3 14 122 Left 2
SYMATTR InstName U1
SYMBOL Misc\\battery 256 432 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName VS2
SYMATTR Value 15
SYMBOL res 384 192 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 48 192 R0
WINDOW 0 10 99 Left 2
WINDOW 3 -60 179 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
SYMBOL diode 304 192 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL Misc\\battery 320 320 R0
WINDOW 0 12 6 Left 2
WINDOW 3 15 95 Left 2
SYMATTR InstName VS1
SYMATTR Value 15
FLAG 48 336 0
FLAG 432 176 VOUT
FLAG 96 192 VIN
FLAG 288 176 VOP
FLAG 256 432 0
FLAG 320 432 0
FLAG 256 288 VEE
FLAG 320 288 VCC
FLAG 208 112 VCC
FLAG 208 240 VEE
FLAG 400 320 0
TEXT -40 64 Left 2 !.tran 0 2m 0 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\009751c7ab1c_1818.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
V2 -V 0 -5
R1 N003 N002 432
R2 N002 0 200
V3 IN 0 AC 1
XU1 IN N002 N003 +V -V LT1818 ;pnba IN+)IN-)OUT)VCC)VEE
R3 OUT N001 432
R4 N001 0 200
XU2 N003 N001 OUT +V -V LT1818 ;pnba IN+)IN-)OUT)VCC)VEE
.ac oct 10 100K 500Meg
* 80MHz, 20dB Gain Block
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1818.asy)
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 240 32 224 32
WIRE 336 32 320 32
WIRE 352 32 336 32
WIRE 464 32 432 32
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -160 160 -160 144
WIRE -64 160 -64 144
WIRE 400 192 400 176
WIRE 192 208 192 192
WIRE 336 208 336 32
WIRE 368 208 336 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 464 224 464 32
WIRE 464 224 432 224
WIRE 496 224 464 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 368 240 256 240
WIRE -160 256 -160 240
WIRE -64 256 -64 240
WIRE 160 256 32 256
WIRE 32 272 32 256
WIRE 400 272 400 256
WIRE 192 288 192 272
WIRE 32 368 32 352
FLAG -64 256 0
FLAG 192 192 +V
FLAG -64 144 +V
FLAG 192 288 -V
FLAG -160 256 0
FLAG -160 144 -V
FLAG 16 96 0
FLAG 32 368 0
FLAG 400 176 +V
FLAG 400 272 -V
FLAG 224 32 0
FLAG 496 224 OUT
FLAG 32 256 IN
SYMBOL voltage -64 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -160 144 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 432
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL voltage 32 256 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL opamps\\LT1818 192 240 R0
SYMATTR InstName U1
SYMBOL res 448 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 432
SYMBOL res 336 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL opamps\\LT1818 400 224 R0
SYMATTR InstName U2
TEXT 232 344 Left 2 !.ac oct 10 100K 500Meg
TEXT 264 -32 Bottom 2 ;80MHz, 20dB Gain Block
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1881.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1881.asy)
V2 -V 0 -5
R1 N002 N001 1K
R2 N001 0 1K
XU1 N003 N001 +V -V N002 LT1881 ;pnba In+)In-)V+)V-)OUT
V3 N003 0 SINE(0 1 1K)
V1 +V 0 5
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -208 128 -208 112
WIRE -80 128 -80 112
WIRE 192 208 192 192
WIRE -208 224 -208 208
WIRE -80 224 -80 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -80 112 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT1881 192 176 R0
SYMATTR InstName U1
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -208 112 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
FLAG -80 224 0
FLAG 192 192 +V
FLAG -80 112 +V
FLAG 192 288 -V
FLAG -208 224 0
FLAG -208 112 -V
FLAG 16 96 0
FLAG 0 368 0
TEXT 224 352 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8584.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8584.asy)
L1 N003 N001 10 Rser=10m Rpar=5K
C2 Vpack 0 1
V2 Vpack 0 50
V1 Vbatt 0 4.2
C1 N001 0 100 Rser=10m
V3 N005 0 PWL(.5m 0 .51m 2)
D1 N002 Vpack MMSD4148
XU1 0 N003 N005 N001 N001 0 0 N004 N001 Vbatt LT8584 ;pnba GND)SW)DCHRG)VSNS)MODE)RTMR)DIN)OUT)VIN)VCELL
R1 N001 Vbatt 12m
L2 N002 0 160 Rser=.1 Rpar=2K
C3 N004 0 47n
K1 L1 L2 .99
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LT8584.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 900 680
WIRE 96 -112 -16 -112
WIRE 272 -112 96 -112
WIRE 432 -112 320 -112
WIRE 576 -112 496 -112
WIRE 656 -112 576 -112
WIRE 688 -112 656 -112
WIRE 96 -96 96 -112
WIRE 272 -96 272 -112
WIRE 320 -96 320 -112
WIRE 576 -96 576 -112
WIRE 688 -96 688 -112
WIRE 96 -16 96 -32
WIRE 272 0 272 -16
WIRE 272 0 240 0
WIRE 320 0 320 -16
WIRE 576 0 576 -32
WIRE 688 0 688 -16
WIRE 240 32 240 0
WIRE -16 96 -16 -112
WIRE 64 96 -16 96
WIRE 96 96 64 96
WIRE 464 96 384 96
WIRE 464 112 464 96
WIRE -16 192 -16 96
WIRE 96 192 -16 192
WIRE 400 192 384 192
WIRE 464 192 464 176
WIRE -16 288 -16 272
WIRE -16 288 -96 288
WIRE 96 288 -16 288
WIRE 464 288 384 288
WIRE -96 304 -96 288
WIRE 464 304 464 288
WIRE 64 368 64 96
WIRE 96 368 64 368
WIRE 400 368 384 368
WIRE -96 400 -96 384
WIRE 464 400 464 384
WIRE 240 448 240 432
SYMBOL diode 432 -128 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MMSD4148
SYMBOL res -32 176 R0
SYMATTR InstName R1
SYMATTR Value 12m
SYMBOL ind2 256 0 M180
WINDOW 0 0 75 Right 2
WINDOW 3 0 38 Right 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR Type ind
SYMATTR SpiceLine Rser=10m Rpar=5K
SYMBOL voltage 688 -112 R0
SYMATTR InstName V2
SYMATTR Value 50
SYMBOL LT8584 240 240 R0
SYMATTR InstName U1
SYMBOL voltage -96 288 R0
SYMATTR InstName V1
SYMATTR Value 4.2
SYMBOL cap 80 -96 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMATTR SpiceLine Rser=10m
SYMBOL cap 560 -96 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 448 112 R0
SYMATTR InstName C3
SYMATTR Value 47n
SYMBOL voltage 464 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(.5m 0 .51m 2)
SYMBOL ind2 336 -112 M0
WINDOW 0 1 33 Right 2
WINDOW 3 0 79 Right 2
SYMATTR InstName L2
SYMATTR Value 160
SYMATTR Type ind
SYMATTR SpiceLine Rser=.1 Rpar=2K
FLAG 240 448 0
FLAG -96 400 0
FLAG 96 -16 0
FLAG 320 0 0
FLAG 576 0 0
FLAG 688 0 0
FLAG 400 368 0
FLAG 400 192 0
FLAG 464 192 0
FLAG 464 400 0
FLAG -96 288 Vbatt
FLAG 656 -112 Vpack
TEXT 296 -120 Bottom 2 !K1 L1 L2 .99
TEXT 464 448 Left 2 !.tran 1.5m startup