* Z:\home\khalils\Downloads\files\data\raw_asc\328c3e1ec4d2_High_Voltage_back-to-back_bjt_v3.asc
* Generated by LTspice 26.0.1 for Windows.
*source LM2903B
* PSpice Model Editor - Version 17.4.0
*$
* LM2903B
*****************************************************************************
* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer.
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model
*
*****************************************************************************
*
** Released by: Texas Instruments Inc.
* Part: LM2903B
* Date: 9/30/2021
* Model Type: All In One
* Simulator: PSPICE
* Simulator Version: 17.4.0.p001
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SCLS005AE - November 2020
* Model Version: 1.0
*
*****************************************************************************
*
* Updates:
*
* Version 1.0 : Release to Web
*
*****************************************************************************
* Notes:
* The following parameters are modeled:
* Iq, tpd, Vcm, Vs, Vhys, Ib, Vos,
* If either input goes beyond the recommended maximum range, the output will float to mid supply for the respective output
* If the supply goes beyond the recommended maximum range, both outputs will float to mid supply
*
*****************************************************************************
* source LM2903B
*$
*$
*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }
*C1 2 0 1e-12
*$
*$
*$
*$
*$
*$
*$
*$
*$
*$
*$
*$
*C1 OUT 0 1e-12
*$
*$
*$
*$
*$
*$
*$
*$
*$
*E_EHYST HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }
*$
*
*RIS2 VCC VEE 100000000
*$
*$
+(0.5,0.0636)
+(0.55,0.0636)
+(0.6,0.0636)
+(0.65,0.0636)
+(0.7,0.0635)
+(0.71,0.0636)
+(0.72,0.0635)
+(0.73,0.0636)
+(0.74,0.0634)
+(0.75,0.0635)
+(0.76,0.0638)
+(0.77,0.0637)
+(0.78,0.0637)
+(0.79,0.0637)
+(0.8,0.0636)
+(0.81,0.0636)
+(0.82,0.0636)
+(0.83,0.0636)
+(0.84,0.0425)
+(0.85,0.0411)
+(0.86,0.0398)
+(0.87,0.0386)
+(0.88,0.0371)
+(0.89,0.0359)
+(0.9,0.0347)
+(0.91,0.0334)
+(0.92,0.032)
+(0.93,0.0309)
+(0.94,0.0296)
+(1,0.0223)
+(1.05,0.0164)
+(1.1,0.0108)
+(1.15,0.0056)
+(1.2,0.0007)
+(1.25,0)
D9 0 out MBRS1100
C1 OUT_OUT 0 1e-12
C1 1 0 1e-12
X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ
EOUT OUT 0 VALUE = {V(VMID)}
EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) }
EVH VH 0 VALUE = { ( V(VHYS)/2) }
V_VOS N785573 IN+BUFF 0.37m
X_U15 N780252 N780066 POR 1V 0 VCC_Range
EOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }
R_R1 V-_BUF LATCH_OUT 1k TC=0,0
X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE
EOUT OUT1 0 VALUE = { V(1)- V(2)}
S1 0 N006 N005 0 MYSW
X_U21 N202710 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393
R4 N018 vref 10k
C4 out 0 10n
L_L1 N778484 VOUT 1n
C_COUTH VOUT VCC 0.5p TC=0,0
V2 N005 0 PWL(0 0 22m 0 22.020m 5 24m 0)
C1 OUT 0 1e-12
R11 N017 N016 1k
C1 OUT 0 1e-12
X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393
E1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
X_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393
R15 NC_01 source 100k
V3 cp_out 100v 11
C1 OUT 0 1e-12
M9 out N009 source source FDB2532
D1 N007 N008 RB238T150
M8 N016 N012 3v3_sw 3v3_sw BSS84
X_U16 N780086 POR EN 1V 0 ORGATE
V_VCMNP N20415 V-_BUFFER -110m
C1 OUT 0 1e-12
Q3 N004 P001 source 0 2N5550
X_U9 CONTROL_HIZ N789513 1V 0 INVERTER
Q1 N001 N003 gate 0 2N5550
E1 amp_raw 0 100v N002 200
X_U13 V+_BUFFER V-_BUFFER N780066 1V 0 Difference
C_CINPL GND IN+ 0.5p TC=0,0
R1 OUT2 OUT 1
M10 out N009 source source FDB2532
R22 N015 0 10k
X_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393
R_RS N03175 VIN 50 TC=0,0
M3 N007 N011 N013 N013 BSP89
R1 4 3 1
M4 N002 N009 source source FDB2532
EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) }
V_VCMPN N202710 V+_BUFFER -2
E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }
R14 N009 gate 1
L1 out N006 660n Rser=1m
V_VLOGIC 1V 0 1
R1 OUT 2 1
M5 N013 N014 0 0 BSP89
X_U6 GND V+_BUFFER V-_BUFFER VCC Supply_Buffer
C1 2 0 1e-12
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }
X_U5 N21237 GND N21168 0 V+_BUFFER V-_BUFFER VCC N858872 OUT Output_Stage
R12 3v3_sw N012 10k
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
C_CINNH IN- VCC 0.5p TC=0,0
R16 N011 nFault 100k
EOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
XU2 N018 N016 5v 0 N011 LM2903B ;pnba In+)In-)V+)V-)OUT
X_U3 VIN N774212 V+_BUFFER V-_BUFFER VCC N774290 DIGLEVSHIFT
B1 out 0 V={V(R_Value)}*I(B1)
Q2 source N003 gate 0 2N5401
C_COUTL GND VOUT 0.5p TC=0,0
EOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }
EVDD_NEW VDD_NEW 0 VALUE = {V(1)}
RIS VCC1 VCC 1
X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID
M11 out N009 source source FDB2532
X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLY
C5 N016 0 .1n
GIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }
V_VS_MAX_SET N779976 0 36.01
C1 2 0 1e-12
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
I1 0 out PWL(0 0 25m 0 25.005m 40)
E_EIN VLE V-_BUF LEHYST V- 1
R1 OUT OUT_OUT 1
R13 3v3_sw N011 10k
V11 3v3 0 3.3
R1 OUT1 OUT 1
V8 5v 0 7
C_CINPH IN+ VCC 0.5p TC=0,0
M7 N012 N014 N011 N011 BSP89
T_TPD N03175 0 VOUT 0 Z0=50 TD=1.22u
R_R3 V-_BUF HYST_OUT 1k TC=0,0
R1 OUT2 OUT 1
X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE
R1 5 6 1
X_U7 N21237 0 V+_BUFFER V-_BUFFER Supply_Enable
V_VLATCH N00729 V- 1.25
RS_SMID 1 2 1G
V_V1 VCC N774290 1
D5 out 0 Didl
I_IS N843683 GND DC 550u
C1 3 0 1e-12
E_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }
E_E1 N858872 V-_BUFFER N858868 V-_BUFFER 2
B2 N017 0 V=If(V(amp_raw)<0,0,IF(V(amp_raw)>5,5,V(amp_raw)))
R17 N003 N004 100
R_ROUTL N850209 N778496 60 TC=0,0
E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
C1 OUT 0 1e-12
C1 OUT 0 1e-12
V4 R_Value 0 PWL(10m 100k 10.001m {start_res} 15m {end_res} 16m 100k)
E1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
RS_SVOL 1 2 1G
M6 out N009 source source FDB2532
X_SVOL N774212 N774290 GND N850209 Output_Stage_SVOL
R_RPU N00729 LEHYST 40k TC=0,0
C1 2 0 1e-12
V1 3v3_sw 0 3.3
R1 OUT2 OUT 1
V9 vref 0 1.15
EINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }
R_RIS N843683 VCC 1u TC=0,0
X_U3 N785573 IN-BUFF N21103 V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS
R_R2 V-_BUF VLE 1k TC=0,0
R8 N001 N007 100k
R1 4 3 1
EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }
C1 3 0 1e-12
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1
C1 N011 0 10n
R2 out 0 100k
V5 100v 0 100
R1 OUT OUT2 1
X_U2 IN-BUFF IN+BUFF N21168 V+_BUFFER V-_BUFFER INPUTRANGE
S_SVOL 3 4 1 2 _SVOL
R1 OUT2 OUT 1
R1 OUT2 OUT 1
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
V_VCMNN N20539 V-_BUFFER -110m
R_RT 0 VOUT 50 TC=0,0
V7 N015 0 PULSE(0 3.3 .01 1u 1u 5m 10m 5)
R10 100v N002 .0005
X_U4 N21103 N858868 Prop_Delay
EOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}
X_U1 VCC GND V+_BUFFER V-_BUFFER SUPPLY_BUFFER1
R5 N018 N011 1Meg
M14 N002 N009 source source FDB2532
EOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
C1 OUT 0 1e-12
C_CINNL GND IN- 0.5p TC=0,0
R1 N001 N004 24k
M2 N002 N009 source source FDB2532
C1 OUT 0 1e-12
M1 N002 N009 source source FDB2532
RS_SHIZ 1 2 1G
EOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}
S_SHIZ 3 4 1 2 _SHIZ
C1 OUT 0 1e-12
EOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }
R7 P001 N008 24k
V_VHYST N852568 0 0
X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer
E1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) }
EVSS_NEW VSS_NEW 0 VALUE = {V(2)}
V_VLOGIC 1V 0 1
X_U5 N780066 N779976 N780086 1V 0 VCC_Range
R1 OUT OUT2 1
R23 N016 0 1k
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }
R1 OUT 2 1
R9 N014 N015 10k
EOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }
V_VS_MIN_SET N780252 0 1.99
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
R1 3 2 1
I_IBN IN- GND DC -3.5n
R3 cp_out N001 .001
R6 N009 source 500k
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
S_SMID 3 4 1 2 _SMID
X_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE
V_VCMPP N20155 V+_BUFFER -2
I_IBP IN+ GND DC -3.5n
R1 OUT 2 1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 50m
.SUBCKT LM2903B IN+ IN- Vcc GND OUT
.ENDS
.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF
.ENDS
.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER
.ENDS
.SUBCKT Supply_Buffer GND V+_BUFFER V-_BUFFER Vcc
.ENDS
.SUBCKT Output_Stage EN GND IN_RANGE POR V+_BUFFER V-_BUFFER Vcc VIN VOUT
.ENDS
.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER
.ENDS
.SUBCKT Prop_Delay VIN VOUT
.ENDS
.subckt Output_Stage_SMID 1 2 3 4
.MODEL _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SMID
.subckt Output_Stage_SHIZ 1 2 3 4
.MODEL _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SHIZ
.subckt Output_Stage_SVOL 1 2 3 4
.MODEL _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0
.ends Output_Stage_SVOL
.SUBCKT ANDGATE 1 2 3 VDD VSS
.ENDS
.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS
.ENDS
.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEW
.ENDS
.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS
.ENDS
.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS
.ENDS
.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS
.ENDS
.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS
.ENDS
.SUBCKT VIN_INV 1 2 VDD VSS
.ENDS
.SUBCKT INVERTER 1 2 VDD VSS
.ENDS
.SUBCKT MID_SUPPLY OUT VDD VSS
.ENDS
.SUBCKT ORGATE 1 2 3 VDD VSS
.ENDS
.SUBCKT NOR_GATE 1 2 OUT VDD VSS
.ENDS
.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSS
.ENDS
.SUBCKT PORCHECK 1 2 OUT VDD VSS
.ENDS
.SUBCKT Difference 1 2 OUT VDD VSS
.ENDS
.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW
.ENDS
.SUBCKT VCC_Range 1 2 OUT VDD VSS
.ENDS
.SUBCKT VINRANGE_393 1 2 OUT VDD VSS
.ENDS
.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSS
.ENDS
.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUT
.ENDS
.SUBCKT NORGATE 1 2 OUT VDD VSS
.ENDS
.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n
.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n
.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT
.ENDS
.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBAD
.ENDS
.SUBCKT 4ORGATE 1 2 3 4 5 VDD VSS
.ENDS
.model MYSW SW(Ron=.1m Roff=1Meg Vt = .5 Vh = -.4)
.model Didl D(Ron=.001 Roff=1Meg Vfwd=110 Vrev=200)
.param start_res=100
.param end_res 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 10012 9280
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WIRE -1392 -928 -1728 -928
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WIRE -896 -928 -1152 -928
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WIRE 656 -752 -208 -752
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SYMBOL nmos 384 -64 M180
SYMATTR InstName M11
SYMATTR Value FDB2532
SYMBOL nmos -1616 496 R0
SYMATTR InstName M5
SYMATTR Value BSP89
SYMBOL nmos -208 -352 R0
SYMATTR InstName M1
SYMATTR Value FDB2532
SYMBOL res -1168 -640 R0
SYMATTR InstName R1
SYMATTR Value 24k
SYMBOL res -672 832 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1Meg
SYMBOL ind 1712 -528 R0
SYMATTR InstName L1
SYMATTR Value 660n
SYMATTR SpiceLine Rser=1m
SYMBOL nmos -848 576 R0
SYMATTR InstName M7
SYMATTR Value BSP89
SYMBOL res -816 416 R0
SYMATTR InstName R12
SYMATTR Value 10k
SYMBOL res -432 -720 R0
SYMATTR InstName R10
SYMATTR Value .0005
SYMBOL res -1408 -592 R0
SYMATTR InstName R8
SYMATTR Value 100k
SYMBOL cap -896 736 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL nmos -1616 368 R0
SYMATTR InstName M3
SYMATTR Value BSP89
SYMBOL res -1296 928 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R16
SYMATTR Value 100k
SYMBOL diode 2128 -288 R0
SYMATTR InstName D5
SYMATTR Value Didl
SYMBOL pnp -960 -192 M180
SYMATTR InstName Q2
SYMATTR Value 2N5401
SYMBOL e -208 -720 R0
SYMATTR InstName E1
SYMATTR Value 200
SYMBOL res -1840 640 R0
SYMATTR InstName R22
SYMATTR Value 10k
SYMBOL nmos -464 -64 M180
SYMATTR InstName M6
SYMATTR Value FDB2532
SYMBOL schottky -1392 -352 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RB238T150
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res -1200 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 24k
SYMBOL voltage -2000 704 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value PULSE(0 3.3 .01 1u 1u 5m 10m 5)
SYMBOL Opamps\\opamp2 -672 672 M0
SYMATTR InstName U2
SYMATTR Value LM2903B
SYMBOL cap -256 96 R0
SYMATTR InstName C4
SYMATTR Value 10n
SYMBOL current 2016 -208 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PWL(0 0 25m 0 25.005m 40)
SYMBOL res -256 720 R0
SYMATTR InstName R23
SYMATTR Value 1k
SYMBOL voltage -2320 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V9
SYMATTR Value 1.15
SYMBOL res -624 752 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL nmos -208 -64 M180
SYMATTR InstName M9
SYMATTR Value FDB2532
SYMBOL nmos 80 -352 R0
SYMATTR InstName M2
SYMATTR Value FDB2532
SYMBOL res -96 704 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 1k
SYMBOL cap -336 752 R0
SYMATTR InstName C5
SYMATTR Value .1n
SYMBOL voltage 1344 -400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 0 22m 0 22.020m 5 24m 0)
SYMBOL voltage 2464 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PWL(10m 100k 10.001m {start_res} 15m {end_res} 16m 100k)
SYMBOL nmos 80 -64 M180
SYMATTR InstName M10
SYMATTR Value FDB2532
SYMBOL res -1664 640 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 10k
SYMBOL voltage -1968 -944 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 11
SYMBOL nmos -464 -352 R0
SYMATTR InstName M14
SYMATTR Value FDB2532
SYMBOL res -672 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 1
SYMBOL res -432 160 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL bv 128 736 R0
SYMATTR InstName B2
SYMATTR Value V=If(V(amp_raw)<0,0,IF(V(amp_raw)>5,5,V(amp_raw)))
SYMBOL res -1024 -432 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R17
SYMATTR Value 100
SYMBOL res -656 -288 R0
SYMATTR InstName R6
SYMATTR Value 500k
SYMBOL res -1824 -912 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value .001
SYMBOL sw 1728 -288 M180
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL res -944 416 R0
SYMATTR InstName R13
SYMATTR Value 10k
SYMBOL voltage -2224 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value 7
SYMBOL bv 2464 -240 R0
SYMATTR InstName B1
SYMATTR Value V={V(R_Value)}*I(B1)
SYMBOL voltage -1984 -656 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 100
SYMBOL schottky -464 96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D9
SYMATTR Value MBRS1100
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL npn -1216 -416 R0
SYMATTR InstName Q3
SYMATTR Value 2N5550
SYMBOL res -1328 -304 R0
SYMATTR InstName R15
SYMATTR Value 100k
SYMBOL pmos -592 560 M180
SYMATTR InstName M8
SYMATTR Value BSS84
SYMBOL npn -960 -528 R0
SYMATTR InstName Q1
SYMATTR Value 2N5550
SYMBOL voltage -2448 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V11
SYMATTR Value 3.3
SYMBOL nmos 384 -352 R0
SYMATTR InstName M4
SYMATTR Value FDB2532
SYMBOL voltage -2592 624 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG -416 -784 100v
FLAG -416 256 0
FLAG -1968 -944 cp_out
FLAG -2000 800 0
FLAG -2224 736 0
FLAG -2224 656 5v
FLAG -208 -624 0
FLAG -672 768 0
FLAG -2320 736 0
FLAG -2320 656 vref
FLAG -544 880 vref
FLAG -320 816 0
FLAG -2448 736 0
FLAG -2448 656 3v3
FLAG -672 704 5v
FLAG -208 16 out
FLAG -800 -368 gate
FLAG 1552 -288 0
FLAG -1392 944 nFault
FLAG -480 96 0
FLAG 2016 -208 0
FLAG 2144 -224 0
FLAG 2464 -144 0
FLAG 2464 144 0
FLAG 2464 64 R_Value
FLAG 2464 -224 out
FLAG 2048 -336 out
FLAG 1728 -256 0
FLAG 1744 -544 out
FLAG -800 -192 source
FLAG 448 720 amp_raw
FLAG 128 832 0
FLAG -240 160 0
FLAG -2592 720 0
FLAG -2592 640 3v3_sw
FLAG -752 416 3v3_sw
FLAG -1568 592 0
FLAG -1824 736 0
FLAG -240 816 0
FLAG -880 800 0
FLAG -1984 -736 100v
FLAG -1984 -544 0
TEXT -1064 776 Left 2 !.tran 50m
TEXT 8080 24 Left 2 !*source LM2903B\n* PSpice Model Editor - Version 17.4.0\n*$\n* LM2903B\n*****************************************************************************\n* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.\n*****************************************************************************\n** This model is designed as an aid for customers of Texas Instruments.\n** TI and its licensors and suppliers make no warranties, either expressed\n** or implied, with respect to this model, including the warranties of \n** merchantability or fitness for a particular purpose.  The model is\n** provided solely on an "as is" basis.  The entire risk as to its quality\n** and performance is with the customer.\n*****************************************************************************\n*\n* This model is subject to change without notice. Texas Instruments\n* Incorporated is not responsible for updating this model\n*\n*****************************************************************************\n*\n** Released by: Texas Instruments Inc.\n* Part: LM2903B\n* Date: 9/30/2021\n* Model Type: All In One\n* Simulator: PSPICE \n* Simulator Version: 17.4.0.p001\n* EVM Order Number: N/A \n* EVM Users Guide:  N/A \n* Datasheet: SCLS005AE - November 2020\n* Model Version: 1.0\n*\n*****************************************************************************\n*\n* Updates:\n*\n* Version 1.0 : Release to Web        \n*\n*****************************************************************************\n* Notes:\n* The following parameters are modeled: \n* Iq, tpd, Vcm, Vs, Vhys, Ib, Vos, \n* If either input goes beyond the recommended maximum range, the output will float to mid supply for the respective output\n* If the supply goes beyond the recommended maximum range, both outputs will float to mid supply\n*\n*****************************************************************************\n* source LM2903B\n.SUBCKT LM2903B IN+ IN- Vcc GND OUT   \nX_U4 N21103 N858868 Prop_Delay  \nX_U2 IN-BUFF IN+BUFF N21168 V+_BUFFER V-_BUFFER INPUTRANGE  \nX_U5 N21237 GND N21168 0 V+_BUFFER V-_BUFFER VCC N858872 OUT Output_Stage  \nX_U6 GND V+_BUFFER V-_BUFFER VCC Supply_Buffer  \nX_U3         N785573 IN-BUFF N21103 V+_BUFFER V-_BUFFER N852568 HPA_COMPHYS\nI_IS         N843683 GND DC 550u  \nX_U7 N21237 0 V+_BUFFER V-_BUFFER Supply_Enable  \nX_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer  \nI_IBP         IN+ GND DC -3.5n  \nI_IBN         IN- GND DC -3.5n  \nV_VOS         N785573 IN+BUFF 0.37m\nR_RIS         N843683 VCC  1u TC=0,0 \nC_CINPL         GND IN+  0.5p  TC=0,0 \nC_CINNL         GND IN-  0.5p  TC=0,0 \nC_CINPH         IN+ VCC  0.5p  TC=0,0 \nC_CINNH         IN- VCC  0.5p  TC=0,0 \nV_VHYST         N852568 0 0\nE_E1         N858872 V-_BUFFER N858868 V-_BUFFER 2\n.ENDS\n \n.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF  \nX_U1         IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1 \n.ENDS\n \n.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER  \nX_U15         N780252 N780066 POR 1V 0 VCC_Range\nX_U13         V+_BUFFER V-_BUFFER N780066 1V 0 Difference\nV_VLOGIC         1V 0 1\nV_VS_MIN_SET         N780252 0 1.99\nX_U5         N780066 N779976 N780086 1V 0 VCC_Range\nV_VS_MAX_SET         N779976 0 36.01\nX_U16         N780086 POR EN 1V 0 ORGATE \n.ENDS\n \n.SUBCKT Supply_Buffer GND V+_BUFFER V-_BUFFER Vcc  \nX_U1         VCC GND V+_BUFFER V-_BUFFER SUPPLY_BUFFER1 \n.ENDS\n \n.SUBCKT Output_Stage EN GND IN_RANGE POR V+_BUFFER V-_BUFFER Vcc VIN VOUT  \nX_SMID    CONTROL_MID 0 N778484 MID Output_Stage_SMID \nX_U3         VIN N774212 V+_BUFFER V-_BUFFER VCC N774290 DIGLEVSHIFT\nX_U7         MID V+_BUFFER V-_BUFFER MID_SUPPLY\nV_VLOGIC         1V 0 1\nV_V1         VCC N774290 1\nX_SHIZ    CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ \nX_U8          POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE\nX_U9         CONTROL_HIZ N789513 1V 0 INVERTER\nX_U10         N789513 POR CONTROL_MID 1V 0 ORGATE \nL_L1         N778484 VOUT  1n  \nC_COUTH         VOUT VCC  0.5p  TC=0,0 \nC_COUTL         GND VOUT  0.5p  TC=0,0 \nX_SVOL    N774212 N774290 GND N850209 Output_Stage_SVOL \nR_ROUTL         N850209 N778496  60 TC=0,0 \n.ENDS\n \n.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER  \nV_VCMNP         N20415 V-_BUFFER -110m\nV_VCMPN         N202710 V+_BUFFER -2\nX_U1         N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393\nV_VCMPP         N20155 V+_BUFFER -2\nV_VCMNN         N20539 V-_BUFFER -110m\nX_U21         N202710 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393\nX_U22         INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393\nX_U23         INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393\nX_U24         N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE \n.ENDS\n \n.SUBCKT Prop_Delay VIN VOUT  \nT_TPD         N03175 0 VOUT 0 Z0=50 TD=1.22u  \nR_RT         0 VOUT  50 TC=0,0 \nR_RS         N03175 VIN  50 TC=0,0 \n.ENDS\n \n.subckt Output_Stage_SMID 1 2 3 4  \nS_SMID         3 4 1 2 _SMID\nRS_SMID         1 2 1G\n.MODEL         _SMID VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0\n.ends Output_Stage_SMID\n \n.subckt Output_Stage_SHIZ 1 2 3 4  \nS_SHIZ         3 4 1 2 _SHIZ\nRS_SHIZ         1 2 1G\n.MODEL         _SHIZ VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0\n.ends Output_Stage_SHIZ\n \n.subckt Output_Stage_SVOL 1 2 3 4  \nS_SVOL         3 4 1 2 _SVOL\nRS_SVOL         1 2 1G\n.MODEL         _SVOL VSWITCH Roff=1e12 Ron=1.0 Voff=1 Von=0\n.ends Output_Stage_SVOL\n \n.SUBCKT ANDGATE 1 2 3 VDD VSS\nE1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 4 3 1\nC1 3 0 1e-12\n.ENDS\n*$\n.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS\nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEVH VH 0 VALUE = { ( V(VHYS)/2) }\nEINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }\nEOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }\nR1 OUT OUT_OUT 1\nC1 OUT_OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEW\n*E1 3 0 VALUE = { IF( V(1) < (V(VDD_OLD)+V(VSS_OLD))/2, V(VSS_NEW), V(VDD_NEW) ) }\n \nE1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }\n \nR1 3 2 1\n*C1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) }\nR1 OUT 2 1\nC1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS \nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT VIN_INV 1 2 VDD VSS\nE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }\nC1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT INVERTER 1 2 VDD VSS\nE2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }\nC1 1 0 1e-12\n.ENDS\n*$\n.SUBCKT MID_SUPPLY OUT VDD VSS\nEVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }\nEOUT OUT 0 VALUE = {V(VMID)}\n.ENDS\n*$\n.SUBCKT ORGATE 1 2 3 VDD VSS\nE1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) }\nR1 4 3 1\nC1 3 0 1e-12\n.ENDS\n*$\n.SUBCKT NOR_GATE 1 2 OUT VDD VSS\nEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 OUT 2 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSS\nEOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }\n.ENDS\n*$\n.SUBCKT PORCHECK 1 2 OUT VDD VSS \nEOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) }\nR1 OUT 2 1\nC1 2 0 1e-12\n.ENDS\n*$\n.SUBCKT Difference 1 2 OUT VDD VSS \nEOUT OUT1 0 VALUE = { V(1)- V(2)}\nR1 OUT1 OUT 1\n*C1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW \nEVDD_NEW VDD_NEW 0 VALUE = {V(1)}\nEVSS_NEW VSS_NEW 0 VALUE = {V(2)}\n.ENDS\n*$\n.SUBCKT VCC_Range 1 2 OUT VDD VSS \nEOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }\nR1 OUT OUT2 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT VINRANGE_393 1 2 OUT VDD VSS \nEOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSS\nEOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}\nR1 OUT OUT2 1\nC1 OUT 0 1e-12 \n.ENDS\n*$\n.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN  VSS OUT\nEOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}\nC1 OUT 0 1e-12\n.ENDS\n*$\n.SUBCKT NORGATE 1 2 OUT VDD VSS\nEOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 OUT2 OUT 1\nC1 OUT 0 1e-12\n.ENDS\n*$\n.MODEL NPN1 NPN LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n \n*$\n.MODEL PNP1 PNP LEVEL=1 IS=1E-16 RB=850 RC=1 TF=5n \n*$\n.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT\nV_VLATCH         N00729 V- 1.25\nR_RPU         N00729 LEHYST  40k TC=0,0 \nE_EIN         VLE V-_BUF LEHYST V- 1\nR_R1         V-_BUF LATCH_OUT  1k TC=0,0 \nR_R2         V-_BUF VLE  1k TC=0,0\nR_R3         V-_BUF HYST_OUT  1k TC=0,0  \nE_ELATCH   LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }\n*E_EHYST     HYST_OUT V-_BUF VALUE = { IF( V(VLE)<= 1.25,V(VLE),0 ) }\nE_EHYST     HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)\n+(0.5,0.0636)\n+(0.55,0.0636)\n+(0.6,0.0636)\n+(0.65,0.0636)\n+(0.7,0.0635)\n+(0.71,0.0636)\n+(0.72,0.0635)\n+(0.73,0.0636)\n+(0.74,0.0634)\n+(0.75,0.0635)\n+(0.76,0.0638)\n+(0.77,0.0637)\n+(0.78,0.0637)\n+(0.79,0.0637)\n+(0.8,0.0636)\n+(0.81,0.0636)\n+(0.82,0.0636)\n+(0.83,0.0636)\n+(0.84,0.0425)\n+(0.85,0.0411)\n+(0.86,0.0398)\n+(0.87,0.0386)\n+(0.88,0.0371)\n+(0.89,0.0359)\n+(0.9,0.0347)\n+(0.91,0.0334)\n+(0.92,0.032)\n+(0.93,0.0309)\n+(0.94,0.0296)\n+(1,0.0223)\n+(1.05,0.0164)\n+(1.1,0.0108)\n+(1.15,0.0056)\n+(1.2,0.0007)\n+(1.25,0)\n.ENDS\n*$\n* \n.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBAD\nGIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }\nRIS VCC1 VCC 1\n*RIS2 VCC VEE 100000000\n.ENDS\n*$\n \n.SUBCKT 4ORGATE 1 2 3 4 5 VDD VSS\nE1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }\nR1 5 6 1\n.ENDS\n*$
TEXT 1856 -536 Left 2 !.model MYSW SW(Ron=.1m Roff=1Meg Vt = .5 Vh = -.4)
TEXT 1856 -568 Left 2 !.model Didl D(Ron=.001 Roff=1Meg Vfwd=110 Vrev=200)
TEXT 2440 -408 Left 2 !.param start_res=100
TEXT 2448 -368 Left 2 !.param end_res 1