* Z:\home\khalils\Downloads\files\data\raw_asc\69ab86deaf7d_Exercise6_Cascode_CMRR.asc
* Generated by LTspice 26.0.1 for Windows.
* Differential Amplifier with CASCODE Tail (Exercise 6 - Improved CMRR)\n \nDifferential Pair:\n M1, M2: NMOS (W=20u, L=5u)\n \nActive Load (Current Mirror):\n M3, M4: PMOS (W=5u, L=5u)\n \nCASCODE Tail Current Source (for high CMRR):\n MCAS: Upper cascode transistor (W=20u, L=50u)\n MB: Lower current source (W=20u, L=50u)\n VBIAS: Sets cascode gate voltage\n IBIAS: 20A bias current\n \nOutput Stage:\n M5: NMOS common-source (W=90u, L=20u)\n \nExpected CMRR Improvement:\n +20 to 30 dB vs simple tail (Exercise6_Differential_CMRR.asc)\n \nTrade-off:\n - Better CMRR (higher tail impedance: r_o g_m*r_o^2)\n - Loses one V_DSsat of headroom
M1 NC_01 N004 NC_02 NC_03 N_20_5
VBIAS N006 0 -2.5
M4 NC_10 NC_11 NC_12 NC_13 P_5_5
M3 N001 NC_07 NC_08 NC_09 P_5_5
IBIAS 0 NC_26 20
MB NC_16 NC_17 NC_18 NC_19 N_20_50
V1 N004 0 SINE(0 0.01 1k) AC 0.5 0
CL VOUT NC_25 10p
MCAS 0 NC_14 VSS NC_15 N_20_50
V2 N004 0 SINE(0 -0.01 1k) AC 0.5 180
VSS N007 NC_23 -5
M2 NC_04 N005 NC_05 NC_06 N_20_5
RL VOUT 0 1Meg
M5 NC_20 N005 NC_21 NC_22 N_90_20
VDD VDD N001 5
RBIAS N001 NC_24 250k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model N_20_5 NMOS (Level=1 VTO=0.7 KP=200u Lambda=0.02 Gamma=0.4 Phi=0.7)
.model N_20_50 NMOS (Level=1 VTO=0.7 KP=200u Lambda=0.02 Gamma=0.4 Phi=0.7)
.model N_90_20 NMOS (Level=1 VTO=0.7 KP=200u Lambda=0.02 Gamma=0.4 Phi=0.7)
.model P_5_5 PMOS (Level=1 VTO=-0.7 KP=100u Lambda=0.02 Gamma=0.4 Phi=0.7)
.tran 0 10m 0 1u
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1600 1000
WIRE 464 -384 352 -384
WIRE 672 -384 464 -384
WIRE 352 -368 352 -384
WIRE 464 -368 464 -384
WIRE 672 -368 672 -384
WIRE 352 -272 352 -288
WIRE 464 -272 464 -288
WIRE 464 -272 352 -272
WIRE 672 -272 672 -288
WIRE 464 -256 464 -272
WIRE 352 -176 352 -272
WIRE 416 -176 352 -176
WIRE 672 -176 672 -272
WIRE 704 -176 672 -176
WIRE 464 -80 464 -160
WIRE 624 -80 464 -80
WIRE 896 -80 704 -80
WIRE 992 -80 896 -80
WIRE 464 -64 464 -80
WIRE 992 -64 992 -80
WIRE 896 -48 896 -80
WIRE 224 16 128 16
WIRE 336 16 224 16
WIRE 576 16 416 16
WIRE 656 16 576 16
WIRE 992 32 992 16
WIRE 128 48 128 16
WIRE 224 48 224 16
WIRE 576 48 576 16
WIRE 896 64 896 32
WIRE 128 144 128 128
WIRE 224 144 224 128
WIRE 224 144 128 144
WIRE 464 144 464 32
WIRE 464 144 224 144
WIRE 576 144 576 128
WIRE 576 144 464 144
WIRE 128 160 128 144
WIRE 256 224 192 224
WIRE 416 256 352 256
WIRE 464 256 464 144
WIRE 192 272 192 224
WIRE 352 272 352 256
WIRE 416 368 352 368
WIRE 192 384 192 352
WIRE 192 384 160 384
WIRE 352 384 352 368
WIRE 160 400 160 384
WIRE 352 480 352 464
WIRE 464 480 464 352
WIRE 464 480 352 480
WIRE 352 496 352 480
SYMBOL nmos4 256 272 R0
SYMATTR InstName MB
SYMATTR Value N_20_50
SYMBOL voltage 192 256 R0
SYMATTR InstName VBIAS
SYMATTR Value -2.5
SYMBOL voltage 128 32 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 0.5 0
SYMATTR InstName V1
SYMATTR Value SINE(0 0.01 1k)
SYMBOL pmos4 416 -256 M180
SYMATTR InstName M3
SYMATTR Value P_5_5
SYMBOL nmos4 656 -64 R0
SYMATTR InstName M5
SYMATTR Value N_90_20
SYMBOL voltage 352 256 R0
SYMATTR InstName VSS
SYMATTR Value -5
SYMBOL voltage 224 32 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 0.5 180
SYMATTR InstName V2
SYMATTR Value SINE(0 -0.01 1k)
SYMBOL pmos4 704 -256 R180
SYMATTR InstName M4
SYMATTR Value P_5_5
SYMBOL nmos4 576 -64 M0
SYMATTR InstName M2
SYMATTR Value N_20_5
SYMBOL nmos4 336 -64 R0
SYMATTR InstName M1
SYMATTR Value N_20_5
SYMBOL nmos4 416 256 R0
SYMATTR InstName MCAS
SYMATTR Value N_20_50
SYMBOL res 448 -272 R0
SYMATTR InstName RBIAS
SYMATTR Value 250k
SYMBOL res 880 -64 R0
SYMATTR InstName RL
SYMATTR Value 1Meg
SYMBOL voltage 352 -384 R0
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL cap 976 -64 R0
SYMATTR InstName CL
SYMATTR Value 10p
SYMBOL current 464 32 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName IBIAS
SYMATTR Value 20u
FLAG 128 160 0
FLAG 464 -384 VDD
FLAG 352 496 VSS
FLAG 992 -80 VOUT
FLAG 992 32 0
FLAG 896 64 0
FLAG 160 400 0
TEXT 80 544 Left 2 !.model N_20_5 NMOS (Level=1 VTO=0.7 KP=200u Lambda=0.02 Gamma=0.4 Phi=0.7)
TEXT 80 576 Left 2 !.model N_20_50 NMOS (Level=1 VTO=0.7 KP=200u Lambda=0.02 Gamma=0.4 Phi=0.7)
TEXT 80 608 Left 2 !.model N_90_20 NMOS (Level=1 VTO=0.7 KP=200u Lambda=0.02 Gamma=0.4 Phi=0.7)
TEXT 80 640 Left 2 !.model P_5_5 PMOS (Level=1 VTO=-0.7 KP=100u Lambda=0.02 Gamma=0.4 Phi=0.7)
TEXT 80 688 Left 2 !.tran 0 10m 0 1u
TEXT 80 720 Left 2 !.ac dec 100 1 100Meg
TEXT 80 752 Left 2 !.op
TEXT 528 544 Left 2 ;Differential Amplifier with CASCODE Tail (Exercise 6 - Improved CMRR)\n \nDifferential Pair:\n  M1, M2: NMOS (W=20u, L=5u)\n \nActive Load (Current Mirror):\n  M3, M4: PMOS (W=5u, L=5u)\n \nCASCODE Tail Current Source (for high CMRR):\n  MCAS: Upper cascode transistor (W=20u, L=50u)\n  MB: Lower current source (W=20u, L=50u)\n  VBIAS: Sets cascode gate voltage\n  IBIAS: 20µA bias current\n \nOutput Stage:\n  M5: NMOS common-source (W=90u, L=20u)\n \nExpected CMRR Improvement:\n  +20 to 30 dB vs simple tail (Exercise6_Differential_CMRR.asc)\n \nTrade-off:\n  - Better CMRR (higher tail impedance: r_o → g_m*r_o^2)\n  - Loses one V_DSsat of headroom