* Z:\home\khalils\Downloads\files\data\raw_asc\0a7b7fc07784_VCO_logic_2-3-curr-mirr_6-sw_2-phd__Shmitt_Vt_.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vref 0 5
V2 Test|_VCO_without_PHD 0 PULSE(0 6 0 1500u 1u 1u 1700u)
R2 12 0 200k
XU1 12 Vref A opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
V3 _inh 0 5
R1 11 0 10k
XU16 11 9 B opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R5 A N003 10
M3 11 11 B B QP
M4 N007 11 N006 N006 QP
D1 N004 N005 1N914
D2 N007 N005 1N914
R6 B N006 10
M1 12 12 A A QP
M2 N004 12 N003 N003 QP
R7 N005 N001 1
R8 A 12 100k
R9 11 B 100k
C2 C1B C1A 220p
B1 VCO_out 0 V=V(Gate2)*V(Vref)
B4 _VCO_out 0 V=V(Gate1)*V(Vref)
S1 0 C1A Gate2 0 SW
S2 C1B N001 Gate2 0 SW
S3 0 C1B Gate1 0 SW
S4 C1A N001 Gate1 0 SW
A1 C1B 0 0 0 0 0 N002 0 SCHMITT Vt=0.05 Vh=0
A2 C1A 0 0 0 0 0 N008 0 SCHMITT Vt=0.05 Vh=0
A3 N008 N002 0 0 0 Gate1 Gate2 0 SRFLOP Td=10ns Trise=10ns Tfall=10ns
A4 N009 _VCO_out 0 0 0 0 N010 0 PHASEDET
V4 N009 0 PULSE(0 1 1u 100n 100n 5u 9.8u)
R3 N010 0 100k
R4 9 N010 1k
R10 9 N011 470
C1 9 N011 1n
C3 N011 0 10n
C4 B 9 10p
D3 C1A N001 1N746
D4 0 C1A 1N746
D5 C1B N001 1N746
D6 0 C1B 1N746
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model QN ako:BSS123
.model QP ako:BSS84
.ic V(C1A)=0 V(C1B)=0
.tran 4.08m
.lib opamp.sub
.inc "C:\Program Files\LTC\LTspiceIV\lib\sym\Extra\CD4000\CD4000.lib"
* PULSE(0 5 0 1500u 1u 1u 1700u)
* "The VCO requires one external capacitor C1 (between\nC1A and C1B) and one external resistor R1 (between\nR1 and GND) or two external resistors R1 and R2\n(between R1 and GND, and R2 and GND). Resistor R1\nand capacitor C1 determine the frequency range of the\nVCO. Resistor R2 enables the VCO to have a frequency\noffset if required."\n74HC4046 Philips Semiconductors Product Specification 1997 Nov 25
* VCO_in
* Current Mirror.\nD1,D2,R7 - for control during simulation
* R5 and R6 - current-limiting resistors.\nThey are interdependent with U17-U20\nIf delete U17-U20, then incrase R5 and\nR6 resistance up to 1KOm
.model SW SW(Ron=10 Roff=10G Vt=0.1 Vh=0)
* This part of VCO according Fig.2.18 on p.26 chapter Two of Pase-Locked Loops. Design simulation and aplication by Roland E.,Best\n*********************************************************************************************************\nNMOS, PMOS and output stage repleced by SW and BV with help of LTSpice asc file \nAndreas Czechanowski, 2005-12-27
* External componets and input logic is similar\n74HC4046 Philips Semiconductors\nProduct Specification\n1997 Nov 25
* The basic reference is 74HC4046 Philips Semiconductors Product Specification 1997 Nov 25\nlook datasheet
* This one varying from one reference to other\nand maybe chenged for best result
* This behavioral model is crude - not tested in accordance with datasheet and real 4046 VCO output\nSo, R5 - R7, D1, D2, U17 - U20 - are parameters to adjust VCO OUTPUT according with ReaL\nTo be continued
* Phase Detector
* LPF
* Quick aprox no oscill on startup with VCO_out (not with _VCO_out)\nVt=0.6 Vh=-0.4\nVt=0.5 Vh=-0.5\nVt=0.4 Vh=-0.6\nVt=0.3 Vh=-0.7\n*****************\nVt=0.3 Vh=-0.1\nVt=0.3 Vh=0
* Vt and Vh of schmitt determine Upper voltage of C1A and C1B and therefore determine phase Error.\nSo, the smaller Vt the smaller Error, but on the other hand small enough Vt cause no switching trigger,\nand thereof no pulse on VCO out.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3744 1204
WIRE 608 -480 608 -528
WIRE 736 -480 736 -512
WIRE 1152 -480 1152 -528
WIRE 608 -368 608 -400
WIRE 736 -368 736 -400
WIRE 1152 -368 1152 -400
WIRE 224 -176 176 -176
WIRE 336 -160 288 -160
WIRE 368 -160 336 -160
WIRE 224 -144 192 -144
WIRE 1136 -144 1104 -144
WIRE 1440 -128 1408 -128
WIRE 1104 -112 1104 -144
WIRE 1200 -112 1152 -112
WIRE 1408 -112 1408 -128
WIRE 1488 -112 1456 -112
WIRE 448 -80 448 -144
WIRE 560 -80 448 -80
WIRE 672 -80 656 -80
WIRE 704 -80 672 -80
WIRE 2256 -80 2256 -144
WIRE 192 -64 192 -144
WIRE 192 -64 176 -64
WIRE 224 -64 192 -64
WIRE 336 -64 336 -160
WIRE 336 -64 304 -64
WIRE 1088 -64 1040 -64
WIRE 1280 -64 1168 -64
WIRE 1392 -64 1280 -64
WIRE 1488 -64 1488 -112
WIRE 1488 -64 1472 -64
WIRE 1504 -64 1488 -64
WIRE 1712 -16 1696 -16
WIRE 576 0 576 -32
WIRE 672 0 672 -80
WIRE 672 0 576 0
WIRE 1696 16 1696 -16
WIRE 576 32 576 0
WIRE 1040 32 1040 -64
WIRE 1120 32 1040 32
WIRE 1280 32 1280 -64
WIRE 1280 32 1184 32
WIRE 1360 32 1280 32
WIRE 1456 32 1424 32
WIRE 2256 32 2256 0
WIRE 1696 48 1648 48
WIRE 1824 64 1760 64
WIRE 1872 64 1856 64
WIRE 448 80 448 -80
WIRE 464 80 448 80
WIRE 560 80 544 80
WIRE 720 80 656 80
WIRE 896 80 784 80
WIRE -16 96 -16 64
WIRE 128 96 128 64
WIRE 1856 96 1856 64
WIRE 1280 112 1280 32
WIRE 1280 112 1264 112
WIRE 896 128 896 80
WIRE 928 128 896 128
WIRE 1040 128 1040 32
WIRE 1040 128 1008 128
WIRE 1456 128 1456 32
WIRE 1488 128 1456 128
WIRE 1824 128 1824 64
WIRE 1856 128 1824 128
WIRE 2000 128 1968 128
WIRE 1280 160 1264 160
WIRE 464 176 448 176
WIRE 560 176 544 176
WIRE 720 176 656 176
WIRE 896 176 896 128
WIRE 896 176 784 176
WIRE 1856 176 1824 176
WIRE 2000 176 1952 176
WIRE 1712 192 1696 192
WIRE -16 208 -16 176
WIRE 128 208 128 176
WIRE 1696 208 1696 192
WIRE 1040 240 1040 128
WIRE 1120 240 1040 240
WIRE 1280 240 1280 160
WIRE 1280 240 1184 240
WIRE 1360 240 1280 240
WIRE 1456 240 1456 128
WIRE 1456 240 1424 240
WIRE 1696 240 1648 240
WIRE 576 256 576 224
WIRE 672 256 576 256
WIRE 1824 256 1824 176
WIRE 1824 256 1760 256
WIRE 576 288 576 256
WIRE 2256 288 2256 224
WIRE 16 304 -16 304
WIRE 128 304 80 304
WIRE 1040 320 1040 240
WIRE 1088 320 1040 320
WIRE 1280 320 1280 240
WIRE 1280 320 1168 320
WIRE 1392 320 1280 320
WIRE 1488 320 1472 320
WIRE 1504 320 1488 320
WIRE 448 336 448 176
WIRE 560 336 448 336
WIRE 672 336 672 256
WIRE 672 336 656 336
WIRE 704 336 672 336
WIRE 256 352 224 352
WIRE 352 352 320 352
WIRE 1184 368 1152 368
WIRE 1488 368 1488 320
WIRE 1488 368 1456 368
WIRE 1408 384 1408 368
WIRE 1440 384 1408 384
WIRE 1104 400 1104 368
WIRE 1152 400 1104 400
WIRE 2256 400 2256 368
WIRE 448 432 448 336
WIRE 224 448 224 352
WIRE 224 448 192 448
WIRE 240 448 224 448
WIRE 352 464 352 352
WIRE 352 464 304 464
WIRE 384 464 352 464
WIRE 240 480 208 480
WIRE 208 560 208 480
WIRE 208 560 176 560
WIRE 224 560 208 560
WIRE 352 560 352 464
WIRE 352 560 304 560
WIRE 1216 816 1024 816
WIRE 1504 832 1344 832
WIRE 1520 832 1504 832
WIRE 1616 832 1600 832
WIRE 1696 832 1616 832
WIRE 1792 832 1696 832
WIRE 1184 848 1184 736
WIRE 1216 848 1184 848
WIRE 1696 848 1696 832
WIRE 1024 864 1024 816
WIRE 1504 864 1504 832
WIRE 1216 880 1184 880
WIRE 1184 896 1184 880
WIRE 1616 928 1616 912
WIRE 1696 928 1696 912
WIRE 1696 928 1616 928
WIRE 1696 944 1696 928
WIRE 1024 960 1024 944
WIRE 1504 976 1504 944
WIRE 1696 1024 1696 1008
FLAG 736 -368 0
FLAG 608 -368 0
FLAG 608 -528 Vref
FLAG 176 -176 Vref
FLAG 128 208 0
FLAG 1504 -64 0
FLAG 1504 320 0
FLAG 1136 -144 Gate1
FLAG 1152 400 Gate2
FLAG 1264 112 C1A
IOPIN 1264 112 BiDir
FLAG 1264 160 C1B
IOPIN 1264 160 BiDir
FLAG 2000 128 Gate1
FLAG 1152 -368 0
FLAG 1152 -528 _inh
FLAG -16 208 0
FLAG 1488 128 0
FLAG 368 -160 A
FLAG 384 464 B
FLAG 448 432 B
FLAG 448 -144 A
FLAG -16 64 11
IOPIN -16 64 BiDir
FLAG 128 64 12
IOPIN 128 64 BiDir
FLAG 176 -64 12
IOPIN 176 -64 BiDir
FLAG 176 560 11
IOPIN 176 560 BiDir
FLAG 192 448 9
IOPIN 192 448 BiDir
FLAG 1792 832 9
IOPIN 1792 832 BiDir
FLAG -16 304 C1A
IOPIN -16 304 BiDir
FLAG 128 304 C1B
IOPIN 128 304 BiDir
FLAG 704 -80 12
IOPIN 704 -80 BiDir
FLAG 704 336 11
IOPIN 704 336 BiDir
FLAG 2256 32 0
FLAG 2256 400 0
FLAG 2000 176 Gate2
FLAG 1200 -112 0
FLAG 1184 368 0
FLAG 1440 -128 Gate2
FLAG 1440 384 Gate1
FLAG 1712 -16 0
FLAG 1712 192 0
FLAG 1648 240 C1A
IOPIN 1648 240 BiDir
FLAG 1648 48 C1B
IOPIN 1648 48 BiDir
FLAG 1872 64 0
FLAG 2256 -144 VCO_out
FLAG 2256 224 _VCO_out
FLAG 1024 960 0
FLAG 1504 976 0
FLAG 1696 1024 0
FLAG 1184 736 _VCO_out
FLAG 1184 896 0
FLAG 736 -512 Test|_VCO_without_PHD
SYMBOL voltage 608 -496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 736 -496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 6 0 1500u 1u 1u 1700u)
SYMBOL res 112 80 R0
SYMATTR InstName R2
SYMATTR Value 200k
SYMBOL Opamps\\opamp 256 -96 M180
SYMATTR InstName U1
SYMBOL voltage 1152 -496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res -32 80 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL Opamps\\opamp 272 528 M180
SYMATTR InstName U16
SYMBOL res 448 96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL pmos 656 288 R90
SYMATTR InstName M3
SYMATTR Value QP
SYMBOL pmos 656 224 M270
SYMATTR InstName M4
SYMATTR Value QP
SYMBOL diode 720 64 M90
WINDOW 3 32 32 VTop 0
WINDOW 0 0 32 VBottom 0
SYMATTR Value 1N914
SYMATTR InstName D1
SYMBOL diode 720 192 R270
WINDOW 3 0 32 VBottom 0
WINDOW 0 32 32 VTop 0
SYMATTR Value 1N914
SYMATTR InstName D2
SYMBOL res 448 160 M90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 10
SYMBOL pmos 656 -32 M270
SYMATTR InstName M1
SYMATTR Value QP
SYMBOL pmos 656 32 R90
SYMATTR InstName M2
SYMATTR Value QP
SYMBOL res 912 112 M90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value 1
SYMBOL res 320 -80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R8
SYMATTR Value 100k
SYMBOL res 208 544 M90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R9
SYMATTR Value 100k
SYMBOL cap 80 288 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 220p
SYMBOL bv 2256 -96 R0
WINDOW 3 -90 165 Left 0
SYMATTR Value V=V(Gate2)*V(Vref)
SYMATTR InstName B1
SYMBOL bv 2256 272 R0
WINDOW 3 -99 111 Left 0
SYMATTR Value V=V(Gate1)*V(Vref)
SYMATTR InstName B4
SYMBOL sw 1488 -64 R90
SYMATTR InstName S1
SYMBOL sw 1184 320 M270
SYMATTR InstName S2
SYMBOL sw 1488 320 M270
SYMATTR InstName S3
SYMBOL sw 1184 -64 R90
SYMATTR InstName S4
SYMBOL Digital\\schmitt 1696 112 M180
WINDOW 3 46 100 Left 0
SYMATTR Value Vt=0.05 Vh=0
SYMATTR InstName A1
SYMBOL Digital\\schmitt 1696 304 M180
WINDOW 3 38 -4 Left 0
SYMATTR Value Vt=0.05 Vh=0
SYMATTR InstName A2
SYMBOL Digital\\srflop 1904 224 M180
WINDOW 3 -74 -20 Left 0
SYMATTR Value Td=10ns Trise=10ns Tfall=10ns
SYMATTR InstName A3
SYMBOL Digital\\phidet 1248 832 R0
SYMATTR InstName A4
SYMBOL voltage 1024 848 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 1 1u 100n 100n 5u 9.8u)
SYMBOL res 1488 848 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL res 1616 816 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 1600 816 R0
SYMATTR InstName R10
SYMATTR Value 470
SYMBOL cap 1680 848 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL cap 1680 944 R0
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL cap 320 336 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C4
SYMATTR Value 10p
SYMBOL zener 1184 16 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D3
SYMATTR Value 1N746
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL zener 1424 16 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D4
SYMATTR Value 1N746
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL zener 1184 224 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D5
SYMATTR Value 1N746
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL zener 1424 224 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D6
SYMATTR Value 1N746
SYMATTR Description Diode
SYMATTR Type diode
TEXT -96 -672 Left 0 !.model QN ako:BSS123\n.model QP ako:BSS84\n.ic V(C1A)=0 V(C1B)=0
TEXT -96 -592 Left 0 !.tran 4.08m
TEXT -96 -728 Left 0 !.lib opamp.sub
TEXT -96 -776 Left 0 !.inc "C:\\Program Files\\LTC\\LTspiceIV\\lib\\sym\\Extra\\CD4000\\CD4000.lib"
TEXT 760 -520 Left 0 ;PULSE(0 5 0 1500u 1u 1u 1700u)
TEXT -96 -504 Left 0 ;"The VCO requires one external capacitor C1 (between\nC1A and C1B) and one external resistor R1 (between\nR1 and GND) or two external resistors R1 and R2\n(between R1 and GND, and R2 and GND). Resistor R1\nand capacitor C1 determine the frequency range of the\nVCO. Resistor R2 enables the VCO to have a frequency\noffset if required."\n74HC4046 Philips Semiconductors Product Specification 1997 Nov 25
TEXT 128 400 Left 0 ;VCO_in
TEXT 464 -272 Left 0 ;Current Mirror.\nD1,D2,R7 - for control during simulation
TEXT 472 448 Left 0 ;R5 and R6 - current-limiting resistors.\nThey are interdependent with U17-U20\nIf delete U17-U20, then incrase R5 and\nR6 resistance up to 1KOm
TEXT 2000 384 Right 0 !.model SW SW(Ron=10 Roff=10G Vt=0.1 Vh=0)
TEXT 1024 -272 Left 0 ;This part of VCO according Fig.2.18 on p.26 chapter Two of Pase-Locked Loops. Design simulation and aplication by Roland E.,Best\n*********************************************************************************************************\nNMOS, PMOS and output stage repleced by SW and BV with help of LTSpice asc file \nAndreas Czechanowski, 2005-12-27
TEXT -88 -264 Left 0 ;External componets and input logic is similar\n74HC4046 Philips Semiconductors\nProduct Specification\n1997 Nov 25
TEXT 816 -792 Left 0 ;The basic reference is 74HC4046 Philips Semiconductors Product Specification 1997 Nov 25\nlook datasheet
TEXT 464 -208 Left 0 ;This one varying from one reference to other\nand maybe chenged for best result
TEXT 1016 536 Left 0 ;This behavioral model is crude - not tested in accordance with datasheet and real 4046 VCO output\nSo, R5 - R7, D1, D2, U17 - U20 - are parameters to adjust VCO OUTPUT according with ReaL\nTo be continued
TEXT 1104 1032 Left 0 ;Phase Detector
TEXT 1464 1072 Left 0 ;LPF
TEXT 1240 -608 Left 0 ;Quick aprox no oscill on startup with VCO_out (not with _VCO_out)\nVt=0.6 Vh=-0.4\nVt=0.5 Vh=-0.5\nVt=0.4 Vh=-0.6\nVt=0.3 Vh=-0.7\n*****************\nVt=0.3 Vh=-0.1\nVt=0.3 Vh=0
TEXT 1456 -536 Left 0 ;Vt and Vh of schmitt determine Upper voltage of C1A and C1B and therefore determine phase Error.\nSo, the smaller Vt the smaller Error, but on the other hand small enough Vt cause no switching trigger,\nand thereof no pulse on VCO out.
RECTANGLE Normal 400 624 -96 -288 2
RECTANGLE Normal 976 608 432 -288 2
RECTANGLE Normal 2384 496 1024 -288 2
RECTANGLE Normal 1408 1120 976 624 2
RECTANGLE Normal 1776 1120 1424 768 2