* Z:\home\khalils\Downloads\files\data\raw_asc\UniversalOpAmp.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
V3 N001 0 PULSE(-50m 50m 250n 1n 1n 1u 2u)
Xlevel1 N001 1 +V -V 1 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Xlevel2 N001 2 +V -V 2 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Xlevel3a N001 3a +V -V 3a level3a Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Xlevel3b N001 3b +V -V 3b level3b Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Xlevel4 N001 4 +V -V 4 level4 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg Ro=1k Ccm=1p Cdiff=2p ;pnba In+)In-)V+)V-)OUT
XU1 N001 5 +V -V 5 level5 Avol=1Meg GBW=10Meg Phimargin=45 SlewPos=10Meg SlewNeg=10Meg En=0 Enk=0 In=0 Ink=0 Rcm=500Meg Ccm=1p Rdiff=500k Cdiff=2p Ro=1k Vos=0 Ibp=2n Ibn=1n Iq=1m Rail=0 Ilimit=25m ;pnba In+)In-)V+)V-)OUT
.tran 1.5u
* A linear, single pole op amp with no internal nodes\nor output voltage range limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nVos = input offset voltage (V)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* A single pole op amp with one internal node,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* A two pole op amp with delay, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* A two pole op amp with two internal nodes, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* This example schematic is supplied for informational/educational purposes only.
* This example demonstrates the use of the different levels of UniversalOpamp.\nChoose a higher level model in order to simulate more aspects of op amp behavior. \nLevel1 is merely a transconductance working into an R||C and does not clamp relative to the supplies.\nLevel2 adds slew rate, output voltage and output current limit. \nLevel3a adds a second pole to the dominant pole response.\nLevel3b adds a delay to the dominant pole response. \nLevel4 adds a virtual ground to support high voltage supplies, as well as realistic input and output impedance.\nLevel5 adds independent rising/falling slew rate limit and additional input parameters.\nNoise is modeled at all levels.
* A two pole op amp with virtual ground, input and output impedance, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()\nRo = open-loop output resistance ()\nCcm = common-mode input capacitance (F)\nCdiff = differential input capacitance (F)
* A two pole op amp with virtual ground, input and output impedance, programmable phase margin,\nindependent rising/falling slew rate limit, output voltage and current limit, and\nadditional input and output parameters.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nPhimargin = phase margin (degrees)\nSlewPos = rising slew rate limit (V/s) \nSlewNeg = falling slew rate limit (V/s) \nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRcm = common-mode input resistance ()\nCcm = common-mode input capacitance (F)\nRdiff = differential input resistance ()\nCdiff = differential input capacitance (F)\nRo = open-loop output resistance ()\nVos = input offset voltage (V)\nIbp = positive input bias current (A)\nIbn = negative input bias current (A)\nIq = quiescent current (A)\nRail = output voltage limit relative to the power supply (V)\nIlimit = output current limit (A)
* Library below included based on ModelFile attribute of instance Xlevel1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp1.asy)
.lib UniversalOpAmp1.lib
* Library below included based on ModelFile attribute of instance Xlevel2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
* Library below included based on ModelFile attribute of instance Xlevel3a (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp3a.asy)
.lib UniversalOpAmp3a.lib
* Library below included based on ModelFile attribute of instance Xlevel3b (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp3b.asy)
.lib UniversalOpAmp3b.lib
* Library below included based on ModelFile attribute of instance Xlevel4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp4.asy)
.lib UniversalOpAmp4.lib
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp5.asy)
.lib UniversalOpAmp5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3716 1260
WIRE 240 -288 80 -288
WIRE 1360 -288 1184 -288
WIRE 2496 -288 2336 -288
WIRE 144 -224 144 -240
WIRE 1248 -224 1248 -240
WIRE 2400 -224 2400 -240
WIRE 80 -208 80 -288
WIRE 112 -208 80 -208
WIRE 1184 -208 1184 -288
WIRE 1216 -208 1184 -208
WIRE 2336 -208 2336 -288
WIRE 2368 -208 2336 -208
WIRE 240 -192 240 -288
WIRE 240 -192 176 -192
WIRE 256 -192 240 -192
WIRE 1360 -192 1360 -288
WIRE 1360 -192 1280 -192
WIRE 1376 -192 1360 -192
WIRE 2496 -192 2496 -288
WIRE 2496 -192 2432 -192
WIRE 2512 -192 2496 -192
WIRE 112 -176 48 -176
WIRE 1216 -176 1136 -176
WIRE 2368 -176 2304 -176
WIRE 144 -144 144 -160
WIRE 1248 -144 1248 -160
WIRE 2400 -144 2400 -160
WIRE 240 304 80 304
WIRE 1360 304 1184 304
WIRE 2496 304 2336 304
WIRE 144 368 144 352
WIRE 1248 368 1248 352
WIRE 2400 368 2400 352
WIRE 80 384 80 304
WIRE 112 384 80 384
WIRE 1184 384 1184 304
WIRE 1216 384 1184 384
WIRE 2336 384 2336 304
WIRE 2368 384 2336 384
WIRE 240 400 240 304
WIRE 240 400 176 400
WIRE 256 400 240 400
WIRE 1360 400 1360 304
WIRE 1360 400 1280 400
WIRE 1376 400 1360 400
WIRE 2496 400 2496 304
WIRE 2496 400 2432 400
WIRE 2512 400 2496 400
WIRE 48 416 48 -176
WIRE 112 416 48 416
WIRE 1136 416 1136 -176
WIRE 1216 416 1136 416
WIRE 2304 416 2304 -176
WIRE 2368 416 2304 416
WIRE 144 448 144 432
WIRE 1248 448 1248 432
WIRE 2400 448 2400 432
WIRE 48 736 48 416
WIRE 1136 736 1136 416
WIRE 1136 736 48 736
WIRE 2304 736 2304 416
WIRE 2304 736 1136 736
WIRE -208 832 -208 816
WIRE -80 832 -80 816
WIRE 48 832 48 736
WIRE -208 928 -208 912
WIRE -80 928 -80 912
WIRE 48 928 48 912
FLAG 144 -240 +V
FLAG 144 -144 -V
FLAG -80 928 0
FLAG -208 928 0
FLAG -208 816 +V
FLAG -80 816 -V
FLAG 48 928 0
FLAG 144 352 +V
FLAG 144 448 -V
FLAG 1248 352 +V
FLAG 1248 448 -V
FLAG 1248 -240 +V
FLAG 1248 -144 -V
FLAG 256 -192 1
FLAG 256 400 2
FLAG 1376 400 3b
FLAG 1376 -192 3a
FLAG 2400 -240 +V
FLAG 2400 -144 -V
FLAG 2512 -192 4
FLAG 2400 352 +V
FLAG 2400 448 -V
FLAG 2512 400 5
SYMBOL voltage -208 816 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -80 816 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 48 816 R0
WINDOW 0 22 12 Left 2
WINDOW 3 27 90 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-50m 50m 250n 1n 1n 1u 2u)
SYMBOL OpAmps\\UniversalOpAmp1 144 -192 R0
SYMATTR InstName level1
SYMBOL OpAmps\\UniversalOpAmp2 144 400 R0
SYMATTR InstName level2
SYMBOL OpAmps\\UniversalOpAmp3a 1248 -192 R0
WINDOW 0 11 -38 Left 2
SYMATTR InstName level3a
SYMBOL OpAmps\\UniversalOpAmp3b 1248 400 R0
WINDOW 0 14 -40 Left 2
SYMATTR InstName level3b
SYMBOL OpAmps\\UniversalOpAmp4 2400 -192 R0
SYMATTR InstName level4
SYMBOL UniversalOpAmp5 2400 400 R0
WINDOW 0 16 -32 Invisible 2
WINDOW 38 18 -26 Left 2
SYMATTR InstName U1
TEXT 432 808 Left 2 !.tran 1.5u
TEXT 288 -272 Left 2 ;A linear, single pole op amp with no internal nodes\nor output voltage range limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nVos = input offset voltage (V)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
TEXT 288 320 Left 2 ;A single pole op amp with one internal node,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
TEXT 1416 312 Left 2 ;A two pole op amp with delay, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
TEXT 1416 -272 Left 2 ;A two pole op amp with two internal nodes, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
TEXT 704 776 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT 1096 -568 Left 2 ;This example demonstrates the use of the different levels of UniversalOpamp.\nChoose a higher level model in order to simulate more aspects of op amp behavior.  \nLevel1 is merely a transconductance working into an R||C and does not clamp relative to the supplies.\nLevel2 adds slew rate, output voltage and output current limit.  \nLevel3a adds a second pole to the dominant pole response.\nLevel3b adds a delay to the dominant pole response.  \nLevel4 adds a virtual ground to support high voltage supplies, as well as realistic input and output impedance.\nLevel5 adds independent rising/falling slew rate limit and additional input parameters.\nNoise is modeled at all levels.
TEXT 2568 -256 Left 2 ;A two pole op amp with virtual ground, input and output impedance, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()\nRo = open-loop output resistance ()\nCcm = common-mode input capacitance (F)\nCdiff = differential input capacitance (F)
TEXT 2568 288 Left 2 ;A two pole op amp with virtual ground, input and output impedance, programmable phase margin,\nindependent rising/falling slew rate limit, output voltage and current limit, and\nadditional input and output parameters.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nPhimargin = phase margin (degrees)\nSlewPos = rising slew rate limit  (V/s) \nSlewNeg = falling slew rate limit  (V/s) \nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRcm = common-mode input resistance ()\nCcm = common-mode input capacitance (F)\nRdiff = differential input resistance ()\nCdiff = differential input capacitance (F)\nRo = open-loop output resistance ()\nVos = input offset voltage (V)\nIbp = positive input bias current (A)\nIbn = negative input bias current (A)\nIq = quiescent current (A)\nRail = output voltage limit relative to the power supply (V)\nIlimit = output current limit (A)