* Z:\home\khalils\Downloads\files\data\raw_asc\172591a22b0f_lab6_.asc
* Generated by LTspice 26.0.1 for Windows.
VDD1 VDD 0 1
M5 Q N001 0 0 N_50n l=250n w=250n
VD1 D 0 PULSE(0 1 07n 0.1p 0.1p 100n 200n)
M15 CLK_BAR CLK 0 0 N_50n l=250n w=150n
M6 Q N001 VDD VDD P_50n l=250n w=450n
M2 N002 Q VDD VDD P_50n l=250n w=450n
M8 N002 CLK N001 VDD P_50n l=250n w=450n
M4 N003 D VDD VDD P_50n l=250n w=450n
M16 CLK_BAR CLK VDD VDD P_50n l=250n w=450n
M9 N003 CLK N001 0 N_50n l=250n w=150n
VCLK1 CLK 0 PULSE(0 1 0n 0.1p 0.1p 1000n 2000n)
M1 N002 Q 0 0 N_50n l=250n w=250n
M10 N003 CLK_BAR N001 VDD P_50n l=250n w=450n
M3 N003 D 0 0 N_50n l=250n w=250n
M7 N002 CLK_BAR N001 0 N_50n l=250n w=150n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 8000n
.lib D:\software\pure_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 1052
WIRE 624 -384 -560 -384
WIRE -1168 -352 -1168 -368
WIRE -1168 -336 -1168 -352
WIRE -1168 -224 -1168 -256
WIRE -432 -192 -432 -240
WIRE 16 -192 16 -304
WIRE 432 -192 432 -240
WIRE -480 -176 -512 -176
WIRE 384 -176 352 -176
WIRE -64 -144 -96 -144
WIRE 64 -144 32 -144
WIRE -16 -128 -16 -144
WIRE -1152 -80 -1152 -96
WIRE -432 -80 -432 -96
WIRE -96 -80 -96 -144
WIRE -96 -80 -432 -80
WIRE 64 -80 64 -144
WIRE 192 -80 64 -80
WIRE 352 -80 352 -176
WIRE 352 -80 192 -80
WIRE 432 -80 432 -96
WIRE 624 -80 624 -384
WIRE 624 -80 432 -80
WIRE -560 -64 -560 -384
WIRE -512 -64 -512 -176
WIRE -512 -64 -560 -64
WIRE -432 -64 -432 -80
WIRE 432 -64 432 -80
WIRE -96 0 -96 -80
WIRE -64 0 -96 0
WIRE 64 0 64 -80
WIRE 64 0 32 0
WIRE -1152 16 -1152 0
WIRE -512 16 -512 -64
WIRE -480 16 -512 16
WIRE 352 16 352 -80
WIRE 384 16 352 16
WIRE -432 80 -432 32
WIRE 432 80 432 32
WIRE 16 160 16 48
WIRE 688 160 688 144
WIRE 688 256 688 240
WIRE -432 272 -432 224
WIRE 16 272 16 160
WIRE -480 288 -512 288
WIRE -64 320 -96 320
WIRE 64 320 32 320
WIRE -16 336 -16 320
WIRE -512 368 -512 288
WIRE -512 368 -608 368
WIRE -432 384 -432 368
WIRE -96 384 -96 320
WIRE -96 384 -432 384
WIRE 64 384 64 320
WIRE 192 384 192 -80
WIRE 192 384 64 384
WIRE -432 400 -432 384
WIRE -96 464 -96 384
WIRE -64 464 -96 464
WIRE 64 464 64 384
WIRE 64 464 32 464
WIRE -512 480 -512 368
WIRE -480 480 -512 480
WIRE -432 544 -432 496
WIRE 16 576 16 512
WIRE 624 576 16 576
WIRE -1120 640 -1120 592
WIRE -1168 656 -1200 656
WIRE 240 656 240 640
WIRE -1120 752 -1120 736
WIRE -944 752 -1120 752
WIRE -1232 768 -1248 768
WIRE -1200 768 -1200 656
WIRE -1200 768 -1232 768
WIRE -1120 768 -1120 752
WIRE -1200 848 -1200 768
WIRE -1168 848 -1200 848
WIRE -1120 912 -1120 864
WIRE -944 944 -944 752
WIRE 320 944 -944 944
WIRE -1232 992 -1232 768
WIRE 320 992 -1232 992
SYMBOL pmos4 -480 -96 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=250n w=450n
SYMBOL nmos4 -1168 768 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M15
SYMATTR Value N_50n
SYMATTR Value2 l=250n w=150n
SYMBOL pmos4 -64 -192 M90
WINDOW 0 88 9 Right 2
WINDOW 3 96 69 Right 2
WINDOW 123 134 106 Right 2
SYMATTR InstName M8
SYMATTR Value P_50n
SYMATTR Value2 l=250n w=450n
SYMBOL voltage -1152 -96 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -106 154 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName CLK1
SYMATTR Value PULSE(0 1 0n 0.1p 0.1p 1000n 2000n)
SYMBOL pmos4 -1168 736 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M16
SYMATTR Value P_50n
SYMATTR Value2 l=250n w=450n
SYMBOL nmos4 -480 -64 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=250n w=250n
SYMBOL voltage 688 144 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -106 154 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName D1
SYMATTR Value PULSE(0 1 07n 0.1p 0.1p 100n 200n)
SYMBOL pmos4 -64 272 M90
WINDOW 0 88 9 Right 2
WINDOW 3 96 69 Right 2
WINDOW 123 134 106 Right 2
SYMATTR InstName M10
SYMATTR Value P_50n
SYMATTR Value2 l=250n w=450n
SYMBOL pmos4 384 -96 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=250n w=450n
SYMBOL pmos4 -480 368 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=250n w=450n
SYMBOL nmos4 -480 400 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M3
SYMATTR Value N_50n
SYMATTR Value2 l=250n w=250n
SYMBOL nmos4 -64 48 R270
WINDOW 0 104 24 Right 2
WINDOW 3 123 70 Right 2
WINDOW 123 145 -8 Right 2
SYMATTR InstName M7
SYMATTR Value N_50n
SYMATTR Value2 l=250n w=150n
SYMBOL nmos4 -64 512 R270
WINDOW 0 104 24 Right 2
WINDOW 3 123 70 Right 2
WINDOW 123 145 -8 Right 2
SYMATTR InstName M9
SYMATTR Value N_50n
SYMATTR Value2 l=250n w=150n
SYMBOL voltage -1168 -352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD1
SYMATTR Value 1
SYMBOL nmos4 384 -64 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M5
SYMATTR Value N_50n
SYMATTR Value2 l=250n w=250n
FLAG -432 -16 0
FLAG -432 -144 VDD
FLAG -432 80 0
FLAG -432 -240 VDD
FLAG -432 448 0
FLAG -432 320 VDD
FLAG -432 544 0
FLAG -432 224 VDD
FLAG 432 -16 0
FLAG 432 -144 VDD
FLAG 432 80 0
FLAG 432 -240 VDD
FLAG -16 0 0
FLAG -16 -128 VDD
FLAG -16 464 0
FLAG -16 336 VDD
FLAG 16 -304 CLK
FLAG 16 160 CLK_BAR
FLAG 624 -80 Q
FLAG 624 576 CLK
FLAG -1152 16 0
FLAG -1152 -96 CLK
FLAG -1168 -224 0
FLAG -1168 -352 VDD
FLAG -1120 816 0
FLAG -1120 688 VDD
FLAG -1120 912 0
FLAG -1120 592 VDD
FLAG -1248 768 CLK
FLAG 320 992 CLK
FLAG 320 944 CLK_BAR
FLAG -608 368 D
FLAG 688 256 0
FLAG 688 144 D
TEXT -1224 -184 Left 2 !.tran 8000n
TEXT -1384 160 Left 2 !.lib D:\\software\\pure_models.txt