* Z:\home\khalils\Downloads\files\data\raw_asc\30f96f2f013e_TayloeDetectorAmplifier.asc
* Generated by LTspice 26.0.1 for Windows.
* Signals for voltage-controlled switches \nused to simulate our multiplexer.
* Power Connections
* RF signal in
* Multiplexer
* Simulation Control
* R2 and R3 to emulate PE1NNZ
* Output from inverting alone with R2=0 is: .0.9mV\nOutput from non-inverting input with R2=200 connected to gnd is: 0.9mV\nThe 200 is compensating for there being a signal connected 1/4 of the time,\nThe output with both connected is; 1.8mV, so both contribute equally.\nThe output equation is v_o = (1+(41k/50)/4)v+ - ((41k/50)/4)v- and v- = -v+=5uV\nThis comes out to 2.05mV. This shows our ideal op amp theory isn't quite dead on, about.
* The filtering is not just due to the sampling capacitors. It is also due to the op-amps.\nThis simulation has the roll off at almost 40 dB/decade without C2. \nYou can also see this effect in the peaking at 100 kHz. C2 removes the peaking,\nand makes it drop faster in the first couple of decades, but then the unity gain\nzero of the non-inverting amplifier takes over, so it only drops at 40 db/decade\nthereafter.
* Ideal op amps used as simulation time is long with the ones I am using.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
;.ac dec 10 10 1000Meg;
;.noise V(V_outQ) V3 dec 10 10 100meg
;.op
;step dec param Audio_freq 1000 10000000 1
R7 N005 11 1
C7 0 N009 {C_Sample}
C13 0 N005 {C_Sample}
S2 N003 01 V_90_deg 0 MYSW
XU1 N004 N001 +5V 0 V_Q level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V6 V_180_deg 0 PULSE(0 1 {2*SW_time} 0.001p 0.001p {SW_time} {4*SW_time})
V2 V_90_deg 0 PULSE(0 1 {SW_time} 0.001p 0.001p {SW_time} {4*SW_time})
C1 0 N007 {C_Sample}
R4 V_Q N001 100k
R2 N006 N007 10
R8 N004 N005 10
S6 N003 10 V_270_deg 0 MYSW
V4 +5V 0 5
V5 0 -5V 5
R6 N001 N002 10
R24 N007 01 0.1
V1 V_0_deg 0 PULSE(0 1 0 0.001p 0.001p {SW_time} {4*SW_time})
R1 V_I N006 100k
V3 N003 0 SINE(2.5 1u {RF_Freq}) AC 1 Rser=50
R25 N009 10 0.1
V7 V_270_deg 0 PULSE(0 1 {3*SW_time} 0.001p 0.001p {SW_time} {4*SW_time})
S7 N003 00 V_0_deg 0 MYSW
XU2 N008 N006 +5V 0 V_I level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
C3 0 N002 {C_Sample}
R5 N002 00 1
C2 V_I N006 150pF
R3 N008 N009 10
C4 V_Q N001 150pF
S4 N003 11 V_180_deg 0 MYSW
.model MYSW SW(Vt=0.9 Vh=0 Ron=1 Roff=100G)
.tran 0 .7m .2m
.param RF_freq=15Meg LO_freq={RF_freq - Audio_freq} LO_period={1/LO_freq} SW_time={LO_period/4}
.param C_Sample=4.7n
.param Audio_freq=10000
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3200 1748
WIRE 1056 -208 912 -208
WIRE 1200 -208 1120 -208
WIRE 912 -128 912 -208
WIRE 1008 -128 912 -128
WIRE 1200 -128 1200 -208
WIRE 1200 -128 1088 -128
WIRE 208 -64 160 -64
WIRE 400 -64 288 -64
WIRE 496 -64 400 -64
WIRE -272 -48 -352 -48
WIRE 16 -48 -192 -48
WIRE 400 -32 400 -64
WIRE -96 0 -208 0
WIRE 496 0 496 -64
WIRE 800 0 496 0
WIRE 912 0 912 -128
WIRE 912 0 880 0
WIRE 976 0 912 0
WIRE 976 16 976 0
WIRE 1008 16 976 16
WIRE 1200 32 1200 -128
WIRE 1200 32 1072 32
WIRE 1264 32 1200 32
WIRE 400 48 400 32
WIRE 1008 48 976 48
WIRE -352 64 -352 -48
WIRE -272 64 -352 64
WIRE 16 64 -192 64
WIRE 800 64 496 64
WIRE 976 64 976 48
WIRE 976 64 880 64
WIRE -96 112 -208 112
WIRE 1280 112 1136 112
WIRE 1424 112 1344 112
WIRE -624 128 -704 128
WIRE -352 128 -352 64
WIRE -352 128 -544 128
WIRE 208 128 160 128
WIRE 400 128 288 128
WIRE 496 128 496 64
WIRE 496 128 400 128
WIRE -704 144 -704 128
WIRE 400 160 400 128
WIRE -352 176 -352 128
WIRE -272 176 -352 176
WIRE 16 176 -192 176
WIRE 1136 192 1136 112
WIRE 1232 192 1136 192
WIRE 1424 192 1424 112
WIRE 1424 192 1312 192
WIRE -96 224 -208 224
WIRE 400 240 400 224
WIRE 688 256 544 256
WIRE 880 256 768 256
WIRE 976 256 880 256
WIRE -352 288 -352 176
WIRE -272 288 -352 288
WIRE 16 288 -192 288
WIRE 880 288 880 256
WIRE 976 320 976 256
WIRE 1024 320 976 320
WIRE 1136 320 1136 192
WIRE 1136 320 1104 320
WIRE 1200 320 1136 320
WIRE -96 336 -208 336
WIRE 1200 336 1200 320
WIRE 1232 336 1200 336
WIRE 1424 352 1424 192
WIRE 1424 352 1296 352
WIRE 1488 352 1424 352
WIRE 880 368 880 352
WIRE 1232 368 1200 368
WIRE 1024 384 976 384
WIRE 1200 384 1200 368
WIRE 1200 384 1104 384
WIRE 688 448 544 448
WIRE 880 448 768 448
WIRE 976 448 976 384
WIRE 976 448 880 448
WIRE 880 480 880 448
WIRE 880 560 880 544
WIRE -624 800 -736 800
WIRE 192 800 80 800
WIRE -736 832 -736 800
WIRE 80 832 80 800
WIRE 1280 896 1280 880
WIRE 1280 896 1200 896
WIRE 1280 912 1280 896
WIRE 1200 928 1200 896
WIRE -624 992 -736 992
WIRE 192 992 80 992
WIRE -736 1024 -736 992
WIRE 80 1024 80 992
SYMBOL res 896 48 R90
WINDOW 0 46 3 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 10
SYMBOL cap 416 32 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value {C_Sample}
SYMBOL sw -288 288 R270
SYMATTR InstName S6
SYMATTR Value MYSW
SYMBOL res 304 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL res 1120 368 R90
WINDOW 0 46 3 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10
SYMBOL res 1104 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage 1280 896 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL cap 896 352 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value {C_Sample}
SYMBOL voltage 1280 784 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL voltage 80 816 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value PULSE(0 1 {2*SW_time} 0.001p 0.001p {SW_time} {4*SW_time})
SYMBOL sw -288 -48 R270
SYMATTR InstName S7
SYMATTR Value MYSW
SYMBOL voltage -528 128 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 118 56 VBottom 2
WINDOW 39 90 64 VBottom 2
SYMATTR InstName V3
SYMATTR Value SINE(2.5 1u {RF_Freq})
SYMATTR Value2 AC 1
SYMATTR SpiceLine Rser=50
SYMBOL OpAmps\\UniversalOpAmp 1264 352 R0
SYMATTR InstName U2
SYMBOL voltage -736 1008 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 {SW_time} 0.001p 0.001p {SW_time} {4*SW_time})
SYMBOL voltage -736 816 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0.001p 0.001p {SW_time} {4*SW_time})
SYMBOL sw -288 176 R270
SYMATTR InstName S4
SYMATTR Value MYSW
SYMBOL res 1328 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 896 -16 R90
WINDOW 0 13 112 VBottom 2
WINDOW 3 24 58 VTop 2
SYMATTR InstName R6
SYMATTR Value 10
SYMBOL cap 896 544 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C7
SYMATTR Value {C_Sample}
SYMBOL sw -288 64 R270
SYMATTR InstName S2
SYMATTR Value MYSW
SYMBOL voltage 80 1008 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value PULSE(0 1 {3*SW_time} 0.001p 0.001p {SW_time} {4*SW_time})
SYMBOL cap 1344 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 150pF
SYMBOL res 784 432 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R25
SYMATTR Value 0.1
SYMBOL cap 1120 -224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 150pF
SYMBOL res 1120 304 R90
WINDOW 0 13 112 VBottom 2
WINDOW 3 24 58 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL cap 416 224 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C13
SYMATTR Value {C_Sample}
SYMBOL OpAmps\\UniversalOpAmp 1040 32 R0
SYMATTR InstName U1
SYMBOL res 784 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R24
SYMATTR Value 0.1
SYMBOL res 304 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 1
FLAG -256 0 0
FLAG -256 112 0
FLAG -256 224 0
FLAG -256 336 0
FLAG -704 144 0
FLAG 1280 800 +5V
FLAG 1200 928 0
FLAG 1280 992 -5V
FLAG -96 0 V_0_deg
FLAG -96 112 V_90_deg
FLAG -96 224 V_180_deg
FLAG -96 336 V_270_deg
FLAG -736 912 0
FLAG -624 800 V_0_deg
FLAG -736 1104 0
FLAG -624 992 V_90_deg
FLAG 80 912 0
FLAG 192 800 V_180_deg
FLAG 80 1104 0
FLAG 192 992 V_270_deg
FLAG 16 -48 00
FLAG 16 176 11
FLAG 880 560 0
FLAG 880 368 0
FLAG 16 64 01
FLAG 16 288 10
FLAG 400 240 0
FLAG 400 48 0
FLAG 160 128 11
FLAG 160 -64 00
FLAG 544 448 10
FLAG 544 256 01
FLAG 1264 320 +5V
FLAG 1040 0 +5V
FLAG 1488 352 V_I
FLAG 1264 32 V_Q
FLAG 1040 64 0
FLAG 1264 384 0
TEXT -760 384 Left 2 !.model MYSW SW(Vt=0.9 Vh=0 Ron=1 Roff=100G)
TEXT 232 600 Left 2 !.tran 0 .7m .2m\n;.ac dec 10 10 1000Meg;\n;.noise V(V_outQ) V3 dec 10 10 100meg\n;.op
TEXT -760 424 Left 2 !.param RF_freq=15Meg LO_freq={RF_freq - Audio_freq} LO_period={1/LO_freq} SW_time={LO_period/4}
TEXT 928 536 Left 2 !.param C_Sample=4.7n
TEXT -776 688 Left 4 ;Signals for voltage-controlled switches \nused to simulate our multiplexer.
TEXT 1032 696 Left 4 ;Power Connections
TEXT -576 48 Left 2 ;RF signal in
TEXT -584 -176 Left 4 ;Multiplexer
TEXT 216 544 Left 4 ;Simulation Control
TEXT 232 744 Left 2 !;step dec param Audio_freq 1000 10000000 1
TEXT 232 712 Left 2 !.param Audio_freq=10000
TEXT 1000 448 Left 2 ;R2 and R3 to emulate PE1NNZ
TEXT -96 -312 Left 2 ;Output from inverting alone with R2=0 is: .0.9mV\nOutput from non-inverting input with R2=200 connected to gnd is: 0.9mV\nThe 200 is compensating for there being a signal connected 1/4 of the time,\nThe output with both connected is; 1.8mV, so both contribute equally.\nThe output equation is v_o = (1+(41k/50)/4)v+ - ((41k/50)/4)v-  and v- = -v+=5uV\nThis comes out to 2.05mV.  This shows our ideal op amp theory isn't quite dead on, about.
TEXT -760 464 Left 2 ;The filtering is not just due to the sampling capacitors.  It is also due to the op-amps.\nThis simulation has the roll off at almost 40 dB/decade without C2.  \nYou can also see this effect in the peaking at 100 kHz.  C2 removes the peaking,\nand makes it drop faster in the first couple of decades, but then the unity gain\nzero of the non-inverting amplifier takes over, so it only drops at 40 db/decade\nthereafter.
TEXT 712 608 Left 2 ;Ideal op amps used as simulation time is long with the ones I am using.