Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\995fffebf1b2_Basic_opamp1.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain stage and limiter
* Lowpass
* Output resistance
* Basic Opamp Subcircuit
* Model with infinite power supply rejection (PSRR)
* opamp2
Rout out 0 {ROUT}
V1 V+ 0 -5
XU1 in 0 V+ V- out opatyp1 ;pnba In+)In-)V+)V-)OUT
R1 out0 0 1k
G1 out 0 out0 0 {1/ROUT}
VS in 0 0
V2 V- 0 5
B1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))
C1 out0 0 1p
.subckt opatyp1 ip im vp vm out
.param GAIN=10000
.param ROUT=10
.ends
.dc VS -10m 10m 0.1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1504 680
WIRE 128 128 128 112
WIRE 96 144 64 144
WIRE 256 160 160 160
WIRE -16 176 -32 176
WIRE 96 176 -16 176
WIRE -32 192 -32 176
WIRE 128 208 128 192
WIRE -32 288 -32 272
WIRE -32 400 -32 384
WIRE 112 400 112 384
WIRE -32 496 -32 480
WIRE 112 496 112 480
LINE Normal 160 224 256 288
LINE Normal 176 256 160 224
LINE Normal 160 224 176 256
LINE Normal 192 224 160 224
SYMBOL voltage 112 384 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -32 384 R0
SYMATTR InstName V1
SYMATTR Value -5
SYMBOL voltage -32 176 R0
SYMATTR InstName VS
SYMATTR Value 0
SYMBOL Opamps\\opamp2 128 96 R0
SYMATTR InstName U1
SYMATTR Value opatyp1
FLAG 64 144 0
FLAG 128 112 V+
FLAG 128 208 V-
FLAG -32 288 0
FLAG -32 496 0
FLAG 112 496 0
FLAG -32 384 V+
FLAG 112 384 V-
FLAG 256 160 out
FLAG -16 176 in
TEXT 368 136 Left 0 !.subckt opatyp1 ip im vp vm out\n.param GAIN=10000\n.param ROUT=10\n* Gain stage and limiter\nB1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))\n* Lowpass\nR1 out0 0 1k\nC1 out0 0 1p\n* Output resistance\nG1 out 0 out0 0 {1/ROUT}\nRout out 0 {ROUT}\n.ends
TEXT -88 32 Left 0 !.dc VS -10m 10m 0.1m
TEXT -88 -24 Left 0 ;Basic Opamp Subcircuit
TEXT 280 72 Left 0 ;Model with infinite power supply rejection (PSRR)
TEXT 216 304 Left 0 ;opamp2
* Z:\tmp\asc_dec_bjh7r6w2\0d107d2197ef_Draft3_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R9 Vo3 N012 R
V1 N005 0 V
V2 N006 0 V
R8 N015 N012 R
R6 N009 Vo1 R
R2 N003 N011 R
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 680
WIRE 80 -32 16 -32
WIRE 592 16 592 -48
WIRE 384 32 336 32
WIRE 528 32 528 -80
WIRE 528 32 464 32
WIRE 560 32 528 32
WIRE 672 48 672 -80
WIRE 672 48 624 48
WIRE 768 48 672 48
WIRE 560 64 512 64
WIRE 976 64 976 0
WIRE 1056 64 1056 0
WIRE 80 96 80 32
WIRE 384 96 384 32
WIRE 480 96 384 96
WIRE 512 96 512 64
WIRE 16 112 16 -32
WIRE 16 112 -32 112
WIRE 48 112 16 112
WIRE 352 112 352 64
WIRE 160 128 160 -32
WIRE 160 128 112 128
WIRE 176 128 160 128
WIRE 272 128 272 32
WIRE 272 128 256 128
WIRE 320 128 272 128
WIRE 592 128 592 80
WIRE 48 144 0 144
WIRE 480 144 480 96
WIRE 480 144 384 144
WIRE 320 160 272 160
WIRE 576 176 512 176
WIRE 768 176 768 48
WIRE 768 176 656 176
WIRE 272 192 272 160
WIRE 976 192 976 144
WIRE 1056 192 1056 144
WIRE 80 224 80 160
WIRE 160 240 160 128
WIRE 256 240 160 240
WIRE 352 240 352 176
WIRE 512 256 512 176
WIRE 576 256 512 256
WIRE 736 256 656 256
WIRE 0 272 0 144
WIRE 80 272 0 272
WIRE 192 272 160 272
WIRE 480 272 480 144
WIRE 480 272 192 272
WIRE 0 304 0 272
WIRE 608 336 608 288
WIRE 256 352 256 240
WIRE 304 352 256 352
WIRE 368 352 304 352
WIRE 512 352 512 256
WIRE 512 352 448 352
WIRE 576 352 512 352
WIRE 736 368 736 256
WIRE 736 368 640 368
WIRE 928 368 736 368
WIRE 576 384 512 384
WIRE 0 416 0 384
WIRE 512 416 512 384
WIRE 608 448 608 400
WIRE 192 528 192 272
SYMBOL res 672 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMBOL voltage 976 48 R0
SYMATTR InstName V1
SYMBOL voltage 1056 48 R0
SYMATTR InstName V2
SYMBOL res 672 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMBOL res 272 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMBOL res 176 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
FLAG 0 416 0
FLAG 512 416 0
FLAG 512 96 0
FLAG 272 192 0
FLAG 304 352 Vo1
FLAG 768 48 Vo3
FLAG 976 192 0
FLAG 1056 192 0
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX6037_ADJ.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\MAX6037_ADJ.asy)
V1 IN 0 3
Iload OUT 0 PULSE(5m -5m 2m 1n 1n 5m 10m)
XU1 N001 0 IN IN OUT MAX6037_ADJ ;pnba 1)2)3)4)5
C1 OUT 0 1
R1 OUT N001 1m
.tran 10m
.lib MAX6037_ADJ.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1384 692
WIRE 16 32 -32 32
WIRE 160 32 16 32
WIRE 160 48 160 32
WIRE 16 80 16 32
WIRE 48 80 16 80
WIRE 336 80 272 80
WIRE 432 80 336 80
WIRE 528 80 432 80
WIRE 336 96 336 80
WIRE 432 96 432 80
WIRE 528 112 528 80
WIRE -32 176 -32 32
WIRE 432 192 432 160
WIRE 336 208 336 176
WIRE 336 208 272 208
WIRE 528 208 528 192
WIRE 160 256 160 240
WIRE -32 272 -32 256
SYMBOL voltage -32 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL MAX6037_ADJ 160 144 R0
SYMATTR InstName U1
SYMBOL current 528 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 33 84 Left 2
WINDOW 3 27 127 Left 2
SYMATTR InstName Iload
SYMATTR Value PULSE(5m -5m 2m 1n 1n 5m 10m)
SYMBOL res 320 80 R0
SYMATTR InstName R1
SYMATTR Value 1m
SYMBOL cap 416 96 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 160 256 0
FLAG 432 192 0
FLAG -32 272 0
FLAG 160 32 IN
FLAG 528 80 OUT
FLAG 528 208 0
TEXT -64 328 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\239c7e3098ec_voltage_divider.asc
* Generated by LTspice 26.0.1 for Windows.
* Voltage Divider
R1 N001 OUT 10K
R2 OUT 0 20K
V1 N001 0 10
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 -80 80 -80
WIRE 256 64 256 -80
WIRE 80 112 80 -80
WIRE 256 176 256 144
WIRE 384 176 256 176
WIRE 256 208 256 176
WIRE 80 320 80 192
WIRE 256 320 256 288
SYMBOL res 240 192 R0
SYMATTR InstName R2
SYMATTR Value 20K
SYMBOL res 240 48 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
FLAG 80 320 0
FLAG 256 320 0
FLAG 384 176 OUT
TEXT 46 344 Left 2 !.tran 1
TEXT 88 -144 Left 2 ;Voltage Divider
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7102-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 3.3
Rload OUT 0 10
C1 OUT 0 2.2 Rser=1.5m
R1 OUT N001 100k
XU1 IN OUT IN N001 OUT 0 ADP7102 Vref=1.8 ;pnba Vin)Sense)EN)PG)Vout)GND
.tran 3m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7102-1.8.asy)
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ADP7102-1.8 224 128 R0
SYMATTR InstName U1
TEXT 432 288 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8618.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8618.asy)
R3 OUT PG 100k
C1 OUT 0 22
C2 N002 SW 47n
R2 RT 0 110k
R4 OUT FB 1.62Meg
L1 SW OUT 120 Rser=1
XU1 N003 SW OUT N002 RT FB TRSS PG N001 N001 0 LT8604C LT8604=0 DFN=1 VOUT33=0 ;pnba INTVCC)SW)Bias)BST)Rt)FB)TR/SS)PG)EN/UV)Vin)GND
R1 FB 0 301k
V1 N001 0 12
Rload OUT 0 50
C3 N003 0 1
.tran 3m steady nodiscard
.lib LT8604C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1748 780
WIRE -32 48 -192 48
WIRE 16 48 -32 48
WIRE 368 48 304 48
WIRE 368 64 368 48
WIRE -192 128 -192 48
WIRE -32 144 -32 48
WIRE 16 144 -32 144
WIRE 336 144 304 144
WIRE 368 144 368 128
WIRE 368 144 336 144
WIRE 432 144 368 144
WIRE 528 144 512 144
WIRE 608 144 528 144
WIRE 800 144 608 144
WIRE 912 144 800 144
WIRE 944 144 912 144
WIRE 800 160 800 144
WIRE 944 160 944 144
WIRE 608 192 608 144
WIRE -64 240 -96 240
WIRE 16 240 0 240
WIRE 528 240 528 144
WIRE 528 240 304 240
WIRE 800 256 800 224
WIRE 944 256 944 240
WIRE -192 272 -192 208
WIRE 336 336 304 336
WIRE 608 336 608 272
WIRE 608 336 336 336
WIRE 608 352 608 336
WIRE -64 432 -112 432
WIRE 16 432 -64 432
WIRE 608 464 608 432
WIRE -48 528 -192 528
WIRE 16 528 -48 528
WIRE 336 528 304 528
WIRE 384 528 336 528
WIRE 528 528 528 240
WIRE 528 528 464 528
WIRE -192 576 -192 528
WIRE 160 624 160 576
WIRE -192 720 -192 656
SYMBOL res 928 144 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 64 R0
SYMATTR InstName C2
SYMATTR Value 47n
SYMBOL res -208 560 R0
SYMATTR InstName R2
SYMATTR Value 110k
SYMBOL cap 784 160 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL voltage -192 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 0 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 480 512 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL ind 416 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 120
SYMATTR SpiceLine Rser=1
SYMBOL LT8618 160 240 R0
SYMATTR InstName U1
SYMBOL res 592 336 R0
SYMATTR InstName R1
SYMATTR Value 301k
SYMBOL res 592 176 R0
SYMATTR InstName R4
SYMATTR Value 1.62Meg
FLAG 608 464 0
FLAG 800 256 0
FLAG 912 144 OUT
FLAG -192 720 0
FLAG -192 272 0
FLAG 336 528 PG
FLAG 336 336 FB
FLAG 336 144 SW
FLAG -48 528 RT
FLAG -64 432 TRSS
FLAG 160 624 0
FLAG 944 256 0
FLAG -96 240 0
TEXT 608 616 Left 2 !.tran 3m steady nodiscard
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1366.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
V2 -V 0 -5
R1 OUT N001 10K
XU1 IN N001 +V -V OUT LT1366 ;pnba In+)In-)V+)V-)OUT
XU2 N001 N003 +V -V N002 LT1366 ;pnba In+)In-)V+)V-)OUT
R2 N003 N002 1Meg
C1 N003 N002 22p
R3 IN N002 1Meg
V3 IN 0 SINE(0 1 100)
.tran 30m
* Input Bias Current Cancellation
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1366.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 720
WIRE 208 -32 192 -32
WIRE 320 -32 288 -32
WIRE 256 80 256 64
WIRE 192 96 192 -32
WIRE 224 96 192 96
WIRE 320 112 320 -32
WIRE 320 112 288 112
WIRE 368 112 320 112
WIRE 96 128 -128 128
WIRE 224 128 96 128
WIRE -128 144 -128 128
WIRE 256 160 256 144
WIRE 96 176 96 128
WIRE 192 208 192 96
WIRE 272 208 192 208
WIRE -128 240 -128 224
WIRE 208 288 208 272
WIRE 272 304 272 208
WIRE 272 304 240 304
WIRE 96 320 96 256
WIRE 176 320 96 320
WIRE 272 336 240 336
WIRE 208 368 208 352
WIRE -192 400 -192 384
WIRE -64 400 -64 384
WIRE 96 416 96 320
WIRE 112 416 96 416
WIRE 272 416 272 336
WIRE 272 416 192 416
WIRE 96 480 96 416
WIRE 192 480 96 480
WIRE 272 480 272 416
WIRE 272 480 256 480
WIRE -192 496 -192 480
WIRE -64 496 -64 480
FLAG -64 496 0
FLAG 256 64 +V
FLAG -64 384 +V
FLAG 256 160 -V
FLAG -192 496 0
FLAG -192 384 -V
FLAG 208 368 +V
FLAG 208 272 -V
FLAG 368 112 OUT
FLAG -128 128 IN
FLAG -128 240 0
SYMBOL voltage -64 384 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -192 384 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 304 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL opamps\\LT1366 256 48 R0
SYMATTR InstName U1
SYMBOL opamps\\LT1366 208 384 R180
WINDOW 0 29 91 Left 2
WINDOW 3 21 34 Left 2
SYMATTR InstName U2
SYMBOL res 208 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL cap 256 464 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 22p
SYMBOL res 80 160 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL voltage -128 128 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
TEXT 320 328 Left 2 !.tran 30m
TEXT 144 -80 Bottom 2 ;Input Bias Current Cancellation
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1155.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1155.asy)
R1 N001 N003 .03
Rload2 N007 0 10
V1 N001 0 5
R2 N003 N002 100K
MQ1 N003 N006 N007 N007 Si9936DY
XU1 N002 N006 0 N004 N005 N001 N008 N002 LTC1155 ;pnba DS1)G1)GND)IN1)IN2)Vs)G2)DS2
V2 N004 0 PULSE(0 5 0 100n 100n 2.5m 5m)
Rload1 N009 0 10
V3 N005 0 PULSE(0 5 0 100n 100n 2.5m 5m)
C1 N001 N002 .1
MQ2 N003 N008 N009 N009 Si9936DY
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
.lib LTC1155.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 352 64 16 64
WIRE 656 64 352 64
WIRE 656 80 656 64
WIRE 352 96 352 64
WIRE -80 128 -96 128
WIRE 16 128 16 64
WIRE 16 128 0 128
WIRE 48 128 16 128
WIRE 320 128 304 128
WIRE 320 192 320 128
WIRE 352 192 352 160
WIRE 352 192 320 192
WIRE 400 192 352 192
WIRE 496 192 480 192
WIRE 656 192 656 160
WIRE 656 192 496 192
WIRE -208 224 -224 224
WIRE 48 224 -128 224
WIRE 320 224 320 192
WIRE 320 224 304 224
WIRE 656 240 656 192
WIRE -208 320 -224 320
WIRE 48 320 -128 320
WIRE 608 320 304 320
WIRE 496 336 496 192
WIRE 656 352 656 336
WIRE 48 416 16 416
WIRE 448 416 304 416
WIRE 496 448 496 432
WIRE 656 448 656 432
WIRE 496 544 496 528
SYMBOL cap 336 96 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 640 64 R0
SYMATTR InstName R1
SYMATTR Value .03
SYMBOL res 480 432 R0
SYMATTR InstName Rload1
SYMATTR Value 10
SYMBOL voltage 16 128 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LTC1155 176 272 R0
SYMATTR InstName U1
SYMBOL nmos 448 336 R0
WINDOW 0 56 22 Left 2
WINDOW 3 55 77 Left 2
SYMATTR InstName Q2
SYMATTR Value Si9936DY
SYMBOL nmos 608 240 R0
WINDOW 0 55 5 Left 2
WINDOW 3 54 62 Left 2
SYMATTR InstName Q1
SYMATTR Value Si9936DY
SYMBOL res 640 336 R0
SYMATTR InstName Rload2
SYMATTR Value 10
SYMBOL voltage -112 320 R90
WINDOW 0 -2 6 VBottom 2
WINDOW 3 37 54 VTop 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 100n 100n 2.5m 5m)
SYMBOL voltage -112 224 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 30 53 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 100n 100n 2.5m 5m)
SYMBOL res 496 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
FLAG 16 416 0
FLAG -96 128 0
FLAG -224 224 0
FLAG -224 320 0
FLAG 656 448 0
FLAG 496 544 0
TEXT 80 520 Left 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6360.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6360.asy)
R1 N003 OUT 10
C1 OUT 0 330p
C2 N002 0 1.1
V1 IN 0 SINE(2.5 1 300K)
XU1 N003 N003 N001 N001 N002 N002 NC_01 IN 0 LTC6360 ;pnba -IN)OUT)Vcc)Vdd)CPO)CPI)_SHDN)+IN)GND
V2 N001 0 5
.tran 50u
.lib LTC6360.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2244 1252
WIRE 1328 496 1216 496
WIRE 1504 496 1328 496
WIRE 1056 512 720 512
WIRE 1504 512 1504 496
WIRE 720 528 720 512
WIRE 1056 528 1056 512
WIRE 1216 528 1216 496
WIRE 1328 528 1328 496
WIRE 1456 592 1408 592
WIRE 1504 608 1504 592
WIRE 720 624 720 608
WIRE 1456 688 1456 592
WIRE 1456 688 1408 688
WIRE 1456 704 1456 688
WIRE 1216 768 1216 752
WIRE 1056 784 1056 752
WIRE 1152 784 1152 752
WIRE 1152 784 1056 784
WIRE 1456 784 1456 768
WIRE 1152 800 1152 784
WIRE 1152 896 1152 880
WIRE 1216 896 1152 896
WIRE 1152 912 1152 896
WIRE 1152 992 1152 976
SYMBOL voltage 720 512 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(2.5 1 300K)
SYMBOL voltage 1504 496 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL LTC6360 1216 640 R0
SYMATTR InstName U1
SYMBOL cap 1136 912 R0
SYMATTR InstName C1
SYMATTR Value 330p
SYMBOL cap 1440 704 R0
SYMATTR InstName C2
SYMATTR Value 1.1
SYMBOL res 1136 784 R0
SYMATTR InstName R1
SYMATTR Value 10
FLAG 720 624 0
FLAG 1504 608 0
FLAG 1216 768 0
FLAG 1152 992 0
FLAG 1456 784 0
FLAG 720 512 IN
FLAG 1216 896 OUT
TEXT 1440 896 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\d453d5317a33_ej3_guiaTC2.asc
* Generated by LTspice 26.0.1 for Windows.
* .param norma_W=2*pi*3.2k
L3 Vo N006 {L3}
XU1 N003 N001 N003 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
XU2 N005 N002 N005 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R1 N001 Vi {R}
R2 N004 N003 {R}
C3 Vo 0 {C3}
L2 N002 N004 {L2}
R3 N006 N005 {R}
C2 N002 0 {C2}
C1 N001 0 {C1}
V1 Vi 0 AC 1 0
.lib opamp.sub
.param norma_R= 1 w01={0.621*norma_W} w02={0.7032*norma_W} w03={1.027*norma_W} Q2={1.125} Q3={4.3}
.param R={norma_R} C1={1/norma_R/w01}
.param L2={Q2*norma_R/w02} C2={1/(L2*(w02**2))}
.param L3={Q3*norma_R/w03} C3={1/(L3*(w03**2))}
.ac dec 10000 0.001 10
.param norma_W=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1376 680
WIRE 32 96 -16 96
WIRE 160 96 112 96
WIRE 240 96 160 96
WIRE 624 96 592 96
WIRE 704 96 624 96
WIRE 336 112 304 112
WIRE 368 112 336 112
WIRE 512 112 448 112
WIRE 592 112 592 96
WIRE 800 112 768 112
WIRE 816 112 800 112
WIRE 960 112 896 112
WIRE 1056 112 1040 112
WIRE 1104 112 1056 112
WIRE 240 128 224 128
WIRE 704 128 688 128
WIRE -16 144 -16 96
WIRE 224 160 224 128
WIRE 336 160 336 112
WIRE 336 160 224 160
WIRE 688 160 688 128
WIRE 800 160 800 112
WIRE 800 160 688 160
WIRE 160 176 160 96
WIRE 624 176 624 96
WIRE 1056 176 1056 112
WIRE -16 288 -16 224
WIRE 160 288 160 240
WIRE 160 288 -16 288
WIRE 624 288 624 240
WIRE 624 288 160 288
WIRE 1056 288 1056 240
WIRE 1056 288 624 288
WIRE -16 320 -16 288
IOPIN 1104 112 Out
IOPIN -16 96 In
SYMBOL cap 1040 176 R0
SYMATTR InstName C3
SYMATTR Value {C3}
SYMBOL cap 144 176 R0
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL OpAmps\\opamp 736 176 M180
SYMATTR InstName U2
SYMBOL ind 608 96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L2
SYMATTR Value {L2}
SYMBOL voltage -16 128 R0
WINDOW 0 -60 22 Left 2
WINDOW 123 -87 105 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL OpAmps\\opamp 272 176 M180
SYMATTR InstName U1
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL ind 1056 96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L3
SYMATTR Value {L3}
SYMBOL res 912 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {R}
SYMBOL cap 608 176 R0
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL res 464 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R}
FLAG 1104 112 Vo
FLAG -16 96 Vi
FLAG -16 320 0
TEXT 432 328 Left 2 !.lib opamp.sub
TEXT 56 392 Left 2 !.param norma_R= 1 w01={0.621*norma_W} w02={0.7032*norma_W} w03={1.027*norma_W} Q2={1.125} Q3={4.3}
TEXT 56 432 Left 2 !.param R={norma_R} C1={1/norma_R/w01}
TEXT 56 472 Left 2 !.param L2={Q2*norma_R/w02} C2={1/(L2*(w02**2))}
TEXT 56 512 Left 2 !.param L3={Q3*norma_R/w03} C3={1/(L3*(w03**2))}
TEXT 64 328 Left 2 !.ac dec 10000 0.001 10
TEXT 56 592 Left 2 ;.param norma_W=2*pi*3.2k
TEXT 440 592 Left 2 !.param norma_W=1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP160-2.1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP160-2.1.asy)
C1 OUT 0 1
XU1 IN 0 N001 OUT ADP16xfd K=476.2u ;pnba Vin)GND)En)Vout
V1 IN 0 5
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
Rload OUT 0 210
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -64 96
WIRE 416 96 352 96
WIRE 512 96 416 96
WIRE -64 112 -64 96
WIRE 416 112 416 96
WIRE 512 112 512 96
WIRE -64 208 -64 192
WIRE 160 208 16 208
WIRE 416 208 416 176
WIRE 512 208 512 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 210
SYMBOL voltage -64 96 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADP160-2.1 256 208 R0
SYMATTR InstName U1
SYMBOL cap 400 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
FLAG -64 208 0
FLAG 256 272 0
FLAG 416 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG -64 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4221-1A.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vin 0 PULSE(0 5 0 2n 2n 5u 10u)
V3 N005 0 0
V2 N003 0 5
R1 N006 0 10k
XU1 Vin N003 0 N005 N006 0 N007 N004 0 N001 N002 ADuM4221-1A ;pnba PWM)VDD1)GND1)DISABLE)DT)GNDB)VOB)VDDB)GNDA)VOA)VDDA
C1 Gate_A 0 2.2n
C2 Gate_B 0 2.2n
R2 Gate_A N001 5.11
R3 Gate_B N007 5.11
V4 N004 0 15
V5 N002 0 15
.tran 50u
* GND1 is modeled as common GND
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4221-1A.asy)
.lib ADuM4221-1A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 3080 680
WIRE -1824 -432 -2208 -432
WIRE -1728 -432 -1824 -432
WIRE -1136 -432 -1424 -432
WIRE -1008 -432 -1056 -432
WIRE -880 -432 -1008 -432
WIRE -832 -432 -880 -432
WIRE -1008 -400 -1008 -432
WIRE -2208 -384 -2208 -432
WIRE -1248 -368 -1424 -368
WIRE -1728 -352 -2096 -352
WIRE -1248 -352 -1248 -368
WIRE -1008 -320 -1008 -336
WIRE -1392 -304 -1424 -304
WIRE -2096 -288 -2096 -352
WIRE -1728 -272 -1760 -272
WIRE -1248 -224 -1424 -224
WIRE -1248 -208 -1248 -224
WIRE -1728 -176 -1984 -176
WIRE -1392 -160 -1424 -160
WIRE -1728 -112 -1872 -112
WIRE -1136 -96 -1424 -96
WIRE -1008 -96 -1056 -96
WIRE -880 -96 -1008 -96
WIRE -832 -96 -880 -96
WIRE -1984 -80 -1984 -176
WIRE -1872 -64 -1872 -112
WIRE -1008 -64 -1008 -96
WIRE -1008 32 -1008 0
WIRE -2208 128 -2208 -304
WIRE -2096 128 -2096 -208
WIRE -1984 128 -1984 0
WIRE -1872 128 -1872 16
FLAG -1984 128 0
FLAG -1392 -160 0
FLAG -2208 128 0
FLAG -2096 128 0
FLAG -1824 -432 Vin
FLAG -1392 -304 0
FLAG -1760 -272 0
FLAG -1872 128 0
FLAG -1248 -128 0
FLAG -880 -96 Gate_B
FLAG -880 -432 Gate_A
FLAG -1008 32 0
FLAG -1008 -320 0
FLAG -1248 -272 0
SYMBOL voltage -2208 -400 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 2n 2n 5u 10u)
SYMBOL voltage -1984 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL voltage -2096 -304 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res -1888 -80 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL ADuM4221-1A -1568 -336 R0
SYMATTR InstName U1
SYMBOL cap -1024 -400 R0
SYMATTR InstName C1
SYMATTR Value 2.2n
SYMBOL cap -1024 -64 R0
SYMATTR InstName C2
SYMATTR Value 2.2n
SYMBOL res -1040 -448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 5.11
SYMBOL res -1040 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 5.11
SYMBOL voltage -1248 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 42 34 Left 2
WINDOW 3 45 64 Left 2
SYMATTR InstName V4
SYMATTR Value 15
SYMBOL voltage -1248 -368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 43 29 Left 2
WINDOW 3 46 61 Left 2
SYMATTR InstName V5
SYMATTR Value 15
TEXT -1728 8 Left 2 !.tran 50u
TEXT -1728 -16 Left 1 ;GND1 is modeled as common GND