* Z:\home\khalils\Downloads\files\data\raw_asc\06bc8cabd5c8_Fig12_12_varying_load.asc
* Generated by LTspice 26.0.1 for Windows.
Vin Vin 0 PULSE 0 1 200p 1p 1p 1.5n
VDD VDD 0 1
M4 Vout Vin VDD VDD P_50n l=50n w=1u
M1 P001 Vin 0 0 N_50n l=50n w=500n
M2 P002 Vin P001 0 N_50n l=50n w=500n
M3 Vout Vin P002 0 N_50n l=50n w=500n
M5 Vout Vin VDD VDD P_50n l=50n w=1u
M6 Vout Vin VDD VDD P_50n l=50n w=1u
Cload Vout 0 {C}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 2.5n
.include cmosedu_models.txt
* Plot Vout and Vin
.step param c 0 100f 25f
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 496 -448 496 -496
WIRE 704 -448 704 -496
WIRE 928 -448 928 -496
WIRE 192 -368 192 -384
WIRE 448 -368 448 -432
WIRE 448 -368 384 -368
WIRE 192 -352 192 -368
WIRE 656 -336 656 -432
WIRE 656 -336 400 -336
WIRE 880 -304 880 -432
WIRE 880 -304 416 -304
WIRE 496 -272 496 -352
WIRE 704 -272 704 -352
WIRE 704 -272 496 -272
WIRE 928 -272 928 -352
WIRE 928 -272 704 -272
WIRE 976 -272 928 -272
WIRE 1008 -272 976 -272
WIRE 192 -240 192 -272
WIRE 400 -192 400 -336
WIRE 400 -192 352 -192
WIRE 448 -192 400 -192
WIRE 320 -176 304 -176
WIRE 352 -176 352 -192
WIRE 352 -176 320 -176
WIRE 384 -176 384 -368
WIRE 384 -176 352 -176
WIRE 384 -160 384 -176
WIRE 416 -160 416 -304
WIRE 416 -160 384 -160
WIRE 208 -96 208 -112
WIRE 384 -96 384 -160
WIRE 448 -96 384 -96
WIRE 208 0 208 -16
WIRE 416 0 416 -160
WIRE 448 0 416 0
WIRE 496 32 496 16
FLAG 208 0 0
FLAG 208 -112 Vin
FLAG 496 -128 0
FLAG 192 -240 0
FLAG 192 -368 VDD
FLAG 496 -400 VDD
FLAG 496 32 0
FLAG 496 -496 VDD
FLAG 320 -176 Vin
FLAG 976 -272 Vout
FLAG 704 -400 VDD
FLAG 704 -496 VDD
FLAG 496 -224 0
FLAG 496 -32 0
FLAG 928 -400 VDD
FLAG 928 -496 VDD
FLAG 1008 -208 0
SYMBOL voltage 208 -112 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -121 144 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vin
SYMATTR Value PULSE 0 1 200p 1p 1p 1.5n
SYMBOL voltage 192 -368 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 448 -352 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 448 -80 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 448 -176 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M2
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 448 -272 R0
WINDOW 0 104 24 Right 2
WINDOW 3 179 41 Right 2
WINDOW 123 213 74 Right 2
SYMATTR InstName M3
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 656 -352 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 880 -352 M180
WINDOW 0 88 9 Right 2
WINDOW 3 168 20 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL cap 992 -272 R0
WINDOW 3 45 38 Left 2
SYMATTR Value {C}
SYMATTR InstName Cload
TEXT 752 -120 Left 2 !.tran 2.5n
TEXT 752 -96 Left 2 !.include cmosedu_models.txt
TEXT 184 -432 Left 2 ;Plot Vout and Vin
TEXT 752 -144 Left 2 !.step param c 0 100f 25f