* Z:\home\khalils\Downloads\files\data\raw_asc\070be14aa3cc_Pierce_new1.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N001 0 62p
C2 N002 0 62p
C3 N002 N001 .012p V=20 Irms=200m Rser=100 Lser=529m Cpar=4p
V1 VCC G 5
R1 N002 N001 1Meg
M1 Out N001 0 0 MHCNEN
R2 Out N002 2k2
R3 G 0 1m
M2 Out N001 VCC VCC MHCPEN
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 50m
* .options nomarch
.option reltol 0.001 gshunt 10n
************************************************
* NOMINAL N-Channel Transistor *
* UCB-3 Parameter Set *
* HIGH-SPEED CMOS Logic Family *
* 10-Jan.-1995 *
************************************************
.Model MHCNEN NMOS W=35U L=2.4U AD=260P AS=260P PD=70U PS= 20U
+LEVEL = 3
+KP = 45.3E-6
+VTO = 0.72
+TOX = 51.5E-9
+NSUB = 2.8E15
+GAMMA = 0.94
+PHI = 0.65
+VMAX = 150E3
+RS = 40
+RD = 40
+XJ = 0.11E-6
+LD = 0.52E-6
+DELTA = 0.315
+THETA = 0.054
+ETA = 0.025
+KAPPA = 0.0
+WD = 0.0
***********************************************
* NOMINAL P-Channel transistor *
* UCB-3 Parameter Set *
* HIGH-SPEED CMOS Logic Family *
* 10-Jan.-1995 *
***********************************************
.Model MHCPEN PMOS W=20U L=2.4U AD=100P AS=100P PD=40U PS= 20U
+LEVEL = 3
+KP = 22.1E-6
+VTO = -0.71
+TOX = 51.5E-9
+NSUB = 3.3E16
+GAMMA = 0.92
+PHI = 0.65
+VMAX = 970E3
+RS = 80
+RD = 80
+XJ = 0.63E-6
+LD = 0.23E-6
+DELTA = 2.24
+THETA = 0.108
+ETA = 0.322
+KAPPA = 0.0
+WD = 0.0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1372 904
WIRE 16 -192 -32 -192
WIRE -32 -160 -32 -192
WIRE 208 -64 208 -128
WIRE -32 -48 -32 -80
WIRE 16 -48 -32 -48
WIRE 160 -48 144 -48
WIRE -32 -32 -32 -48
WIRE 208 48 208 32
WIRE 320 48 208 48
WIRE 368 48 320 48
WIRE -32 64 -32 48
WIRE 144 64 144 -48
WIRE 144 64 80 64
WIRE 208 64 208 48
WIRE 320 112 320 48
WIRE 144 144 144 64
WIRE 160 144 144 144
WIRE 208 176 208 160
WIRE 80 240 80 64
WIRE 144 240 80 240
WIRE 160 240 144 240
WIRE 256 240 224 240
WIRE 320 240 320 192
WIRE 320 240 256 240
WIRE 80 256 80 240
WIRE 320 256 320 240
WIRE 144 320 144 240
WIRE 160 320 144 320
WIRE 256 320 256 240
WIRE 256 320 240 320
WIRE 320 352 320 320
WIRE 80 368 80 320
FLAG 320 352 0
FLAG -32 64 0
FLAG 208 -128 VCC
IOPIN 208 -128 In
FLAG 16 -192 VCC
IOPIN 16 -192 Out
FLAG 368 48 Out
IOPIN 368 48 Out
FLAG 80 368 0
FLAG 208 176 0
FLAG 16 -48 G
IOPIN 16 -48 Out
SYMBOL cap 64 256 R0
SYMATTR InstName C1
SYMATTR Value 62p
SYMBOL cap 304 256 R0
SYMATTR InstName C2
SYMATTR Value 62p
SYMBOL Misc\\xtal 224 224 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C3
SYMATTR Value .012p
SYMATTR SpiceLine V=20 Irms=200m Rser=100 Lser=529m Cpar=4p
SYMBOL voltage -32 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 256 304 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL nmos 160 64 R0
SYMATTR InstName M1
SYMATTR Value MHCNEN
SYMBOL res 304 96 R0
SYMATTR InstName R2
SYMATTR Value 2k2
SYMBOL res -48 -48 R0
SYMATTR InstName R3
SYMATTR Value 1m
SYMBOL pmos 160 32 M180
SYMATTR InstName M2
SYMATTR Value MHCPEN
TEXT -88 104 Left 0 !.tran 50m
TEXT -128 136 Left 0 ;.options nomarch
TEXT 0 400 Left 0 !.option reltol 0.001 gshunt 10n
TEXT 512 -240 Left 0 !************************************************\n\n*         NOMINAL N-Channel Transistor         *\n\n*            UCB-3 Parameter Set               *\n\n*         HIGH-SPEED CMOS Logic Family         *\n\n*                10-Jan.-1995                  *\n\n************************************************\n\n.Model MHCNEN NMOS W=35U L=2.4U AD=260P AS=260P PD=70U PS= 20U\n\n+LEVEL = 3\n\n+KP    = 45.3E-6\n\n+VTO   = 0.72\n\n+TOX   = 51.5E-9\n\n+NSUB  = 2.8E15\n\n+GAMMA = 0.94\n\n+PHI   = 0.65\n\n+VMAX  = 150E3\n\n+RS    = 40\n\n+RD    = 40\n\n+XJ    = 0.11E-6\n\n+LD    = 0.52E-6\n\n+DELTA = 0.315\n\n+THETA = 0.054\n\n+ETA   = 0.025\n\n+KAPPA = 0.0\n\n+WD    = 0.0\n\n\n***********************************************\n\n*        NOMINAL P-Channel transistor         *\n\n*           UCB-3 Parameter Set               *\n\n*         HIGH-SPEED CMOS Logic Family        *\n\n*               10-Jan.-1995                  *\n\n***********************************************\n\n.Model MHCPEN PMOS W=20U L=2.4U AD=100P AS=100P PD=40U PS= 20U\n\n+LEVEL = 3\n\n+KP    = 22.1E-6\n\n+VTO   = -0.71\n\n+TOX   = 51.5E-9\n\n+NSUB  = 3.3E16\n\n+GAMMA = 0.92\n\n+PHI   = 0.65\n\n+VMAX  = 970E3\n\n+RS    = 80\n\n+RD    = 80\n\n+XJ    = 0.63E-6\n\n+LD    = 0.23E-6\n\n+DELTA = 2.24\n\n+THETA = 0.108\n\n+ETA   = 0.322\n\n+KAPPA = 0.0\n\n+WD    = 0.0