* Z:\home\khalils\Downloads\files\data\raw_asc\2d09733d67b9_Draft07.asc
* Generated by LTspice 26.0.1 for Windows.
VIN FGND 0 PULSE(25 -25 0 100n 100n 0.2ms 0.4ms 7)
Q1 N004 N003 N002 0 2N3906
Q3 N003 N002 N001 0 2N3906
R6 N001 N002 800R
V1 N001 0 100
V4 0 N020 100
R8 N003 N018 500k
D1 FGND N004 Z17V
D2 N014 FGND Z17V
Q2 N014 N018 N019 0 2N3904
R1 N019 N020 800R
Q4 N018 N019 N020 0 2N3904
Q5 FVCC N010 P001 0 2SC5200
Q6 FVEE N010 P002 0 2SA1943
R3 P001 N012 0.5R
R5 N012 P002 0.5R
R7 N012 N010 300R
M2 N006 N004 FVCC FVCC IRFP240
M4 N015 N014 FVEE FVEE IRFP9240
XU1 FGND N012 VCC4 VEE4 N010 LT1006 ;pnba In+)In-)V+)V-)OUT
C2 N004 FGND 100n
C3 FGND N014 100n
C5 N012 N010 1p
R2 N012 0 100R
R4 N007 FVCC 100R
D3 FGND N009 Z10V
R9 N009 N007 5k
C4 N009 FGND 100n
Q7 N007 N009 VCC4 0 2N3904
R10 N013 FVEE 100R
R11 N013 N011 5k
D4 N011 FGND Z10V
Q8 N013 N011 VEE4 0 2N3906
C6 FGND N011 100n
C7 FVCC FVEE 100n
D5 N012 FVCC D
D6 FVEE N012 D
D7 FVCC N004 D
D8 N014 FVEE D
D9 N008 N006 D
V2 N008 0 36
D10 N015 N016 D
V3 0 N016 36
M1 N001 N005 N006 N006 IRFP240
D11 N006 N005 D
D12 N004 N005 D
M3 N020 N017 N015 N015 IRFP9240
D13 N017 N015 D
D14 N017 N014 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3ms
.include my.lib
.model Z17V ako: BZX84C33VL bv=17
.model Z10V ako: BZX84C33VL bv=10
* discrete, should have better psrr at higher freq than linear reg/ldo.
* EXTR. FVCC, FVEE are set in relation to FGND by zeners and drop on fets. all correct.\n- but fgnd should not be signal source.\n- yes. remember the cascode biasing is itself bootstrapped. \n- instead keep non-invert input of op is tied to fgnd, and negative should be driven\nas error integrator.
.include standard.bjt
* 50R load works. 1.4A at +-70V
* at +-20V all power goes through 36V supplies. (fet Vgs = 20+17-36==1V)\nat +-25V all power goes through the 100V supplies. (fet Vgs = 25+17-36=6V)
* issue - haven't got enough headroom for +-15V. eg. 17-4.5Vgs=12.5V.\ncan have another zener. and then two smaller fets to the HV rail perhaps.\nOr use r2r ops, or just +-5V vfb, and ifb.\n- or just use a HV bjt. off of the 17V zeners. nothing else needed.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1006.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3300 1052
WIRE 704 -544 528 -544
WIRE 1232 -544 704 -544
WIRE 1328 -544 1232 -544
WIRE 528 -512 528 -544
WIRE 704 -464 592 -464
WIRE 640 -416 528 -416
WIRE 1232 -416 1232 -544
WIRE 704 -336 704 -368
WIRE 1008 -336 704 -336
WIRE 1184 -336 1072 -336
WIRE 1232 -272 1232 -320
WIRE 1232 -272 1184 -272
WIRE 1968 -224 1888 -224
WIRE 2224 -224 1968 -224
WIRE 1232 -208 1232 -272
WIRE 1328 -208 1296 -208
WIRE 2224 -192 2224 -224
WIRE 1232 -160 1232 -208
WIRE 2048 -144 1968 -144
WIRE 2160 -144 2048 -144
WIRE 2352 -96 2224 -96
WIRE 704 -80 704 -336
WIRE 1184 -80 704 -80
WIRE 528 -16 528 -416
WIRE 1232 -16 1232 -64
WIRE 1232 -16 1184 -16
WIRE 1968 -16 1968 -80
WIRE 1968 -16 1808 -16
WIRE 1968 0 1968 -16
WIRE 2048 0 2048 -80
WIRE 2048 0 1968 0
WIRE 1232 16 1232 -16
WIRE 1328 16 1232 16
WIRE 1232 48 1232 16
WIRE 1968 64 1968 0
WIRE 2048 64 2048 0
WIRE 2352 80 2224 80
WIRE 1168 96 1088 96
WIRE 2048 128 1968 128
WIRE 2160 128 2048 128
WIRE 1456 160 880 160
WIRE 704 176 704 -80
WIRE 752 176 704 176
WIRE 1088 176 1088 96
WIRE 1104 176 1088 176
WIRE 1200 176 1168 176
WIRE 880 208 880 160
WIRE 896 208 880 208
WIRE 1968 208 1888 208
WIRE 2224 208 2224 176
WIRE 2224 208 1968 208
WIRE 1072 224 960 224
WIRE 1088 224 1088 176
WIRE 1088 224 1072 224
WIRE 1104 224 1088 224
WIRE 1200 224 1200 176
WIRE 1200 224 1184 224
WIRE 1232 224 1200 224
WIRE 1456 224 1456 160
WIRE 1456 224 1232 224
WIRE 1536 224 1456 224
WIRE 1552 224 1536 224
WIRE 1648 224 1552 224
WIRE 352 240 -32 240
WIRE 704 240 352 240
WIRE 752 240 704 240
WIRE 768 240 752 240
WIRE 896 240 768 240
WIRE -32 272 -32 240
WIRE 768 304 704 304
WIRE 1072 352 1072 224
WIRE 1168 352 1072 352
WIRE 1232 432 1232 400
WIRE 1328 432 1232 432
WIRE 1232 448 1232 432
WIRE 1232 448 1184 448
WIRE 1232 496 1232 448
WIRE 704 512 704 304
WIRE 1184 512 704 512
WIRE 1232 640 1232 592
WIRE 1344 640 1296 640
WIRE 1232 704 1232 640
WIRE 1232 704 1184 704
WIRE 1232 752 1232 704
WIRE 704 768 704 512
WIRE 1056 768 704 768
WIRE 1184 768 1120 768
WIRE 704 816 704 768
WIRE 528 864 528 64
WIRE 640 864 528 864
WIRE 704 912 592 912
WIRE 528 992 528 960
WIRE 704 992 528 992
WIRE 1232 992 1232 848
WIRE 1232 992 704 992
WIRE 1344 992 1232 992
FLAG -32 352 0
FLAG 1328 -464 0
FLAG 1648 304 0
FLAG 1328 16 FVCC
FLAG 1328 432 FVEE
FLAG 352 240 FGND
FLAG 2352 -96 VCC4
FLAG 928 192 VCC4
FLAG 2352 80 VEE4
FLAG 928 256 VEE4
FLAG 1808 -16 FGND
FLAG 1536 -144 FVCC
FLAG 1808 -224 FVCC
FLAG 1536 -80 FVEE
FLAG 1808 208 FVEE
FLAG 1536 160 FVCC
FLAG 1552 288 FVEE
FLAG 1328 -128 0
FLAG 1344 560 0
FLAG 1344 912 0
SYMBOL voltage -32 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -143 168 Left 2
SYMATTR Value PULSE(25 -25 0 100n 100n 0.2ms 0.4ms 7)
SYMATTR InstName VIN
SYMBOL pnp 640 -368 M180
SYMATTR InstName Q1
SYMATTR Value 2N3906
SYMBOL pnp 592 -416 R180
SYMATTR InstName Q3
SYMATTR Value 2N3906
SYMBOL res 688 -560 R0
SYMATTR InstName R6
SYMATTR Value 800R
SYMBOL voltage 1328 -560 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 42 41 Left 2
SYMATTR Value 100
SYMATTR InstName V1
SYMBOL voltage 1344 896 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 36 39 Left 2
SYMATTR InstName V4
SYMATTR Value 100
SYMBOL res 512 -32 R0
SYMATTR InstName R8
SYMATTR Value 500k
SYMBOL zener 720 240 R180
WINDOW 0 24 64 Left 2
WINDOW 3 56 35 Left 2
SYMATTR InstName D1
SYMATTR Value Z17V
SYMBOL zener 720 304 R180
WINDOW 0 24 64 Left 2
WINDOW 3 54 30 Left 2
SYMATTR InstName D2
SYMATTR Value Z17V
SYMBOL npn 640 816 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 688 896 R0
SYMATTR InstName R1
SYMATTR Value 800R
SYMBOL npn 592 864 M0
SYMATTR InstName Q4
SYMATTR Value 2N3904
SYMBOL npn 1168 48 R0
SYMATTR InstName Q5
SYMATTR Value 2SC5200
SYMBOL pnp 1168 400 M180
WINDOW 3 85 0 Left 2
SYMATTR Value 2SA1943
SYMATTR InstName Q6
SYMBOL res 1216 128 R0
SYMATTR InstName R3
SYMATTR Value 0.5R
SYMBOL res 1216 208 R0
SYMATTR InstName R5
SYMATTR Value 0.5R
SYMBOL res 1200 208 R90
WINDOW 0 81 66 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 300R
SYMBOL nmos 1184 -160 R0
SYMATTR InstName M2
SYMATTR Value IRFP240
SYMBOL pmos 1184 592 M180
SYMATTR InstName M4
SYMATTR Value IRFP9240
SYMBOL OpAmps\\LT1006 928 160 R0
SYMATTR InstName U1
SYMBOL cap 736 176 R0
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL cap 752 240 R0
SYMATTR InstName C3
SYMATTR Value 100n
SYMBOL cap 1168 160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 -59 31 VTop 2
SYMATTR InstName C5
SYMATTR Value 1p
SYMBOL res 1632 208 R0
SYMATTR InstName R2
SYMATTR Value 100R
SYMBOL res 1904 -240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100R
SYMBOL zener 1984 -80 R180
WINDOW 0 24 64 Left 2
WINDOW 3 56 35 Left 2
SYMATTR InstName D3
SYMATTR Value Z10V
SYMBOL res 1984 -128 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R9
SYMATTR Value 5k
SYMBOL cap 2032 -144 R0
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL npn 2160 -192 R0
SYMATTR InstName Q7
SYMATTR Value 2N3904
SYMBOL res 1904 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 100R
SYMBOL res 1984 224 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R11
SYMATTR Value 5k
SYMBOL zener 1984 128 R180
WINDOW 0 24 64 Left 2
WINDOW 3 56 35 Left 2
SYMATTR InstName D4
SYMATTR Value Z10V
SYMBOL pnp 2160 176 M180
WINDOW 3 85 0 Left 2
SYMATTR Value 2N3906
SYMATTR InstName Q8
SYMBOL cap 2032 64 R0
SYMATTR InstName C6
SYMATTR Value 100n
SYMBOL cap 1520 -144 R0
SYMATTR InstName C7
SYMATTR Value 100n
SYMBOL diode 1552 224 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D5
SYMBOL diode 1568 288 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D6
SYMBOL diode 1200 -16 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D7
SYMBOL diode 1200 512 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D8
SYMBOL diode 1296 -224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D9
SYMBOL voltage 1328 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 42 41 Left 2
SYMATTR Value 36
SYMATTR InstName V2
SYMBOL diode 1232 656 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D10
SYMBOL voltage 1344 544 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 42 41 Left 2
SYMATTR Value 36
SYMATTR InstName V3
SYMBOL nmos 1184 -416 R0
SYMATTR InstName M1
SYMATTR Value IRFP240
SYMBOL diode 1200 -272 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D11
SYMBOL diode 1008 -320 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D12
SYMBOL pmos 1184 848 M180
SYMATTR InstName M3
SYMATTR Value IRFP9240
SYMBOL diode 1200 768 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D13
SYMBOL diode 1120 752 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D14
TEXT -104 -288 Left 2 !.tran 3ms
TEXT -136 -176 Left 2 !.include my.lib
TEXT -192 -88 Left 2 !.model Z17V ako:  BZX84C33VL bv=17
TEXT -192 -48 Left 2 !.model Z10V ako:  BZX84C33VL bv=10
TEXT 1648 -344 Left 2 ;discrete, should have better psrr at higher freq than linear reg/ldo.
TEXT 1544 -600 Left 2 ;EXTR. FVCC, FVEE are set in relation to FGND by zeners and drop on fets. all correct.\n- but fgnd should not be signal source.\n- yes. remember the cascode biasing is itself bootstrapped. \n- instead keep non-invert input of op is tied to fgnd, and negative should be driven\nas error integrator.
TEXT -136 -144 Left 2 !.include standard.bjt
TEXT 1792 352 Left 2 ;50R load works. 1.4A at +-70V
TEXT 1664 512 Left 2 ;at +-20V all power goes through 36V supplies.  (fet Vgs = 20+17-36==1V)\nat +-25V all power goes through the 100V supplies. (fet Vgs = 25+17-36=6V)
TEXT 2456 -216 Left 2 ;issue - haven't got enough headroom for +-15V. eg. 17-4.5Vgs=12.5V.\ncan have another zener. and then two smaller fets to the HV rail perhaps.\nOr use r2r ops, or just +-5V vfb, and ifb.\n- or just use a HV bjt. off of the 17V zeners. nothing else needed.