Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4601AHV.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4601AHV.asy)
R2 N008 0 392K
R3 OUT N002 100K
C3 N011 0 .001
R1 N004 0 19.1K
C1 OUT N004 100p
Rload OUT 0 .2
C2 OUT 0 660
V1 IN 0 12
XU1 IN 0 OUT 0 N006 N006 OUT 0 N002 N004 N007 N012 N010 N009 N008 N005 N003 N011 N001 N007 LTM4601 ;pnba Vin)PGND)Vout)Vosns-)Vout_LCL)DiffVout)Vosns+)SGND)Pgood)FB)DRVcc)MARG1)MARG0)Fset)MPGM)Comp)Run)Track/SS)PLLIN)INTVcc
R4 IN N003 100K
.tran 750u startup
.lib LTM4601.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1032 680
WIRE 432 -32 -144 -32
WIRE -160 -16 -256 -16
WIRE 128 -16 -160 -16
WIRE -256 0 -256 -16
WIRE 128 0 128 -16
WIRE 272 0 272 -16
WIRE -144 48 -144 -32
WIRE -128 48 -144 48
WIRE 16 48 -48 48
WIRE 432 48 432 -32
WIRE 432 48 400 48
WIRE 576 48 432 48
WIRE 656 48 576 48
WIRE 576 64 576 48
WIRE -256 96 -256 80
WIRE -160 112 -160 -16
WIRE -80 112 -160 112
WIRE 16 112 0 112
WIRE 432 112 400 112
WIRE 480 112 432 112
WIRE 480 128 480 112
WIRE 576 144 576 128
WIRE 16 176 0 176
WIRE 432 176 400 176
WIRE 480 224 480 208
WIRE 16 240 0 240
WIRE 432 240 432 176
WIRE 432 240 400 240
WIRE 656 272 656 48
WIRE 656 272 576 272
WIRE 720 272 656 272
WIRE 720 288 720 272
WIRE 0 304 0 240
WIRE 16 304 0 304
WIRE 576 304 576 272
WIRE 576 304 400 304
WIRE -80 368 -96 368
WIRE 16 368 0 368
WIRE 576 368 400 368
WIRE 576 384 576 368
WIRE 720 384 720 368
WIRE 720 384 576 384
WIRE 720 400 720 384
WIRE 16 432 0 432
WIRE 416 432 400 432
WIRE -64 496 -80 496
WIRE 16 496 0 496
WIRE 416 496 400 496
WIRE 128 576 128 560
WIRE 288 576 288 560
SYMBOL cap 416 48 R0
WINDOW 0 34 18 Left 2
WINDOW 3 35 47 Left 2
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL voltage -256 -16 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 0 480 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL res -144 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 464 112 R0
SYMATTR InstName R1
SYMATTR Value 19.1K
SYMBOL cap 560 64 R0
SYMATTR InstName C2
SYMATTR Value 660
SYMBOL res 16 384 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 392K
SYMBOL res -96 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL res 704 272 R0
SYMATTR InstName Rload
SYMATTR Value .2
SYMBOL PowerProducts\\LTM4601AHV 208 256 R0
SYMATTR InstName U1
FLAG 128 576 0
FLAG 288 576 0
FLAG 480 224 0
FLAG -96 368 0
FLAG 720 400 0
FLAG -256 96 0
FLAG -80 496 0
FLAG 720 272 OUT
FLAG -256 -16 IN
FLAG 576 144 0
TEXT 472 496 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0787bf4e2468_Level9Comparison.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 1
R1 N002 0 1Gig
R3 N003 0 1Gig
QGP N002 N001 0 0 BC856_PHI_1
QVBIC N003 N001 0 0 BC856_PHI_3
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.MODEL BC856_PHI_1
.INC GP-BC856_PHI.mod
.dc V1 5 6 100m
.TEMP -55 +25 +150
.PARAM tnom=25
.PARAM Vbbe=5 ibbe=10u
.LIB GP-BC856_PHI.par
.MODEL BC856_PHI_3
.INC GP2VBIC.mod
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5756 2000
WIRE 1840 704 1680 704
WIRE 2064 704 1840 704
WIRE 1936 720 1920 720
WIRE 2160 720 2144 720
WIRE 1936 736 1936 720
WIRE 2160 736 2160 720
WIRE 1840 768 1840 704
WIRE 1856 768 1840 768
WIRE 2064 768 2064 704
WIRE 2080 768 2064 768
WIRE 1680 784 1680 704
WIRE 1920 832 1920 816
WIRE 2144 832 2144 816
WIRE 1680 928 1680 864
WIRE 1920 928 1920 912
WIRE 2144 928 2144 912
SYMBOL pnp 2080 816 M180
SYMATTR InstName QVBIC
SYMATTR Value BC856_PHI_3
SYMBOL res 1904 816 R0
SYMATTR InstName R1
SYMATTR Value 1Gig
SYMBOL voltage 1680 768 R0
WINDOW 3 24 104 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 1
SYMATTR InstName V1
SYMBOL res 2128 816 R0
SYMATTR InstName R3
SYMATTR Value 1Gig
SYMBOL pnp 1856 816 M180
SYMATTR InstName QGP
SYMATTR Value BC856_PHI_1
FLAG 1936 736 0
FLAG 1680 928 0
FLAG 1920 928 0
FLAG 2160 736 0
FLAG 2144 928 0
TEXT 1680 1040 Left 0 !.MODEL BC856_PHI_1\n.INC GP-BC856_PHI.mod
TEXT 1680 1008 Left 0 !.dc V1 5 6 100m
TEXT 1680 976 Left 0 !.TEMP -55 +25 +150
TEXT 2128 960 Left 0 !.PARAM tnom=25\n.PARAM Vbbe=5 ibbe=10u \n.LIB GP-BC856_PHI.par\n.MODEL BC856_PHI_3\n.INC GP2VBIC.mod
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4446.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 10
V2 N008 0 PULSE(0 5 20n 10n 10n .96u 2u)
MQ1 N004 N005 N003 N003 IRF7468
MQ2 N003 N009 0 0 IRF7468
C1 N003 N002 .1
D1 N001 N002 1N5819
V3 N004 0 50
L1 N003 N007 1
C2 N007 0 10
R1 N007 0 .5
V4 N006 0 PULSE(5 0 0 10n 10n .99u 2u)
XU1 N006 N008 N001 N009 MP_01 N002 N005 N003 0 LTC4446 ;pnba Tinp)Binp)Vcc)BG))Boost)TG)TS)GND
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100u startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4446.asy)
.lib LTC4446.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 48 -192 48
WIRE 0 48 -48 48
WIRE 112 48 64 48
WIRE 176 48 112 48
WIRE 272 48 240 48
WIRE -192 64 -192 48
WIRE 496 80 336 80
WIRE 336 96 336 80
WIRE 496 96 496 80
WIRE 112 112 112 48
WIRE -192 160 -192 144
WIRE -48 176 -48 48
WIRE -16 176 -48 176
WIRE 288 176 240 176
WIRE 496 192 496 176
WIRE -16 256 -192 256
WIRE 272 256 272 48
WIRE 272 256 240 256
WIRE 336 256 336 192
WIRE 336 256 272 256
WIRE 384 256 336 256
WIRE 496 256 464 256
WIRE 576 256 496 256
WIRE 496 272 496 256
WIRE 576 272 576 256
WIRE -16 336 -96 336
WIRE 288 336 240 336
WIRE -96 368 -96 336
WIRE 336 368 336 352
WIRE 496 368 496 336
WIRE 576 368 576 352
WIRE 112 416 112 400
WIRE -192 448 -192 256
WIRE -96 464 -96 448
WIRE -192 544 -192 528
FLAG 112 416 0
FLAG -96 464 0
FLAG -192 160 0
FLAG 336 368 0
FLAG 496 192 0
FLAG 496 368 0
FLAG 576 368 0
FLAG -192 544 0
SYMBOL voltage -192 48 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL voltage -96 352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 20n 10n 10n .96u 2u)
SYMBOL nmos 288 96 R0
SYMATTR InstName Q1
SYMATTR Value IRF7468
SYMBOL nmos 288 256 R0
SYMATTR InstName Q2
SYMATTR Value IRF7468
SYMBOL cap 240 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL schottky 0 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage 496 80 R0
SYMATTR InstName V3
SYMATTR Value 50
SYMBOL ind 368 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL cap 480 272 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL res 560 256 R0
SYMATTR InstName R1
SYMATTR Value .5
SYMBOL voltage -192 432 R0
SYMATTR InstName V4
SYMATTR Value PULSE(5 0 0 10n 10n .99u 2u)
SYMBOL PowerProducts\\LTC4446 112 256 R0
SYMATTR InstName U1
TEXT 392 440 Left 2 !.tran 100u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3580.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3580.asy)
C3 N002 0 .001
C1 OUT 0 10
D1 N001 OUT 1N5818
V1 IN 0 5
C2 0 N005 1000p Rser=10K
L1 IN N001 4.2
R2 OUT N003 130K
Rload OUT 0 22
XU1 N003 N005 IN N001 IN N004 N002 MP_01 0 LT3580 ;pnba FB)Vc)Vin)SW)_SHDN)Rt)SS))GND
R1 N004 0 75K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 500u startup
.lib LT3580.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 96 -144 96
WIRE 128 96 -64 96
WIRE 176 96 128 96
WIRE 304 96 256 96
WIRE 336 96 304 96
WIRE 464 96 400 96
WIRE 512 96 464 96
WIRE 592 96 512 96
WIRE -144 112 -144 96
WIRE 512 112 512 96
WIRE 592 112 592 96
WIRE 128 144 128 96
WIRE -144 208 -144 192
WIRE -64 208 -64 96
WIRE -16 208 -64 208
WIRE 304 208 304 96
WIRE 304 208 272 208
WIRE 512 208 512 176
WIRE 592 208 592 192
WIRE -96 288 -128 288
WIRE -16 288 -32 288
WIRE 368 288 272 288
WIRE 464 288 464 96
WIRE 464 288 448 288
WIRE -112 368 -128 368
WIRE -16 368 -32 368
WIRE 320 368 272 368
WIRE 416 368 384 368
WIRE 128 448 128 432
SYMBOL res -16 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 75K
SYMBOL voltage -144 96 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL schottky 336 112 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5818
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap -32 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL res 464 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 130K
SYMBOL cap 496 112 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 576 96 R0
SYMATTR InstName Rload
SYMATTR Value 22
SYMBOL ind 160 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.2
SYMBOL PowerProducts\\LT3580 128 288 R0
SYMATTR InstName U1
SYMBOL cap 384 352 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 39 60 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1000p
SYMATTR SpiceLine Rser=10K
FLAG 128 448 0
FLAG 512 208 0
FLAG 416 368 0
FLAG -128 368 0
FLAG -128 288 0
FLAG -144 208 0
FLAG 592 208 0
FLAG -144 96 IN
FLAG 592 96 OUT
TEXT 264 472 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\faac78401234_LDO.asc
* Generated by LTspice 26.0.1 for Windows.
* 10K gain
* Library below included based on ModelFile attribute of instance XE1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp1.asy)
R1 5V 2.5V 10k
V3 V+ 0 12
R2 2.5V 0 10k
R3 5V 0 100
V1 N001 0 12
XE1 N003 2.5V V+ V- N002 level1 Avol=10k GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Q1 N001 N002 5V 0 2N2222
V4 0 V- 12
V2 N003 0 2.5
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0 1 0 500n uic
.options numdgt = 7
.options plotwinsize = 0
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1176 680
WIRE 192 32 48 32
WIRE 640 32 288 32
WIRE 784 32 784 -16
WIRE 784 32 640 32
WIRE 640 80 640 32
WIRE 384 112 304 112
WIRE 784 128 784 32
WIRE 976 128 976 32
WIRE 1120 128 1120 32
WIRE 48 144 48 32
WIRE 384 160 384 112
WIRE 640 176 640 160
WIRE 640 176 416 176
WIRE 704 176 640 176
WIRE 240 192 240 96
WIRE 352 192 240 192
WIRE 480 208 416 208
WIRE 480 240 480 208
WIRE 640 240 640 176
WIRE 384 272 384 224
WIRE 384 272 304 272
WIRE 976 320 976 208
WIRE 1120 320 1120 208
WIRE 48 368 48 224
WIRE 480 368 480 320
WIRE 480 368 48 368
WIRE 640 368 640 320
WIRE 640 368 480 368
WIRE 784 368 784 208
WIRE 784 368 640 368
WIRE 480 400 480 368
SYMBOL res 624 64 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL OpAmps\\UniversalOpAmp1 384 192 M0
SYMATTR InstName E1
SYMATTR Value2 Avol=10k GBW=10Meg Vos=0
SYMBOL res 624 224 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 976 112 R0
SYMATTR InstName V3
SYMATTR Value 12
SYMBOL npn 192 96 R270
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL voltage 480 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 2.5
SYMBOL voltage 1120 224 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -39 104 Left 2
WINDOW 3 -34 11 Left 2
SYMATTR InstName V4
SYMATTR Value 12
SYMBOL voltage 48 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 768 112 R0
SYMATTR InstName R3
SYMATTR Value 100
FLAG 304 112 V+
FLAG 304 272 V-
FLAG 976 320 0
FLAG 1120 320 0
FLAG 976 32 V+
FLAG 1120 32 V-
FLAG 480 400 0
FLAG 784 -16 5V
FLAG 704 176 2.5V
TEXT 64 384 Left 2 !.tran 0 1 0 500n uic
TEXT 400 144 Left 1 ;10K gain
TEXT 64 416 Left 2 !.options numdgt = 7
TEXT 64 448 Left 2 !.options plotwinsize = 0
* Z:\home\khalils\Downloads\files\data\raw_asc\1c9428612c7f_template1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP727.asy)
V2 VCC 0 5v
V1 N002 0 SINE(2 1 1KHz)
XU1 N002 N001 VCC 0 N001 OP727 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 1k
.tran 1ms
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 48 -48 48
WIRE 48 96 48 -16
WIRE -48 112 -48 48
WIRE 16 112 -48 112
WIRE 176 128 176 48
WIRE 176 128 80 128
WIRE 16 144 -304 144
WIRE 176 160 176 128
WIRE 48 240 48 160
WIRE -304 288 -304 224
WIRE 176 288 176 240
SYMBOL voltage -304 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(2 1 1KHz)
SYMBOL Opamps\\OP727 48 64 R0
SYMATTR InstName U1
SYMBOL voltage -304 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5v
SYMBOL res 160 144 R0
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 176 288 0
FLAG -304 288 0
FLAG 48 240 0
FLAG 48 -16 VCC
FLAG -304 -48 VCC
FLAG -304 32 0
TEXT -338 312 Left 2 !.tran 1ms
* Z:\home\khalils\Downloads\files\data\raw_asc\06fc9646b120_01-j111_voltage_controlled_resistor.asc
* Generated by LTspice 26.0.1 for Windows.
* Semiconductor Devices: JFET Voltage Controlled Resistor\nhttps://youtu.be/T4IESXeRtWo?si=Ukin5aEwjMJSvs0i
J1 out N002 0 J111
R2 N002 N001 1Meg
R1 out in 10k
R3 out N003 22k
VC N001 0 {VC}
V1 in 0 SINE(0 50m 1k)
R4 N003 0 68k
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.tran 2m
.step param VC -5 5 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -208 48 -240 48
WIRE -32 48 -208 48
WIRE 144 48 48 48
WIRE 256 48 144 48
WIRE 272 48 256 48
WIRE 256 96 256 48
WIRE 144 128 144 48
WIRE -240 144 -240 48
WIRE -16 192 -64 192
WIRE 96 192 64 192
WIRE 256 208 256 176
WIRE -64 240 -64 192
WIRE -240 256 -240 224
WIRE 144 256 144 224
WIRE 256 336 256 288
WIRE -64 352 -64 320
IOPIN 272 48 Out
SYMBOL res 64 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL njf 96 128 R0
SYMATTR InstName J1
SYMATTR Value J111
SYMBOL voltage -64 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VC
SYMATTR Value {VC}
SYMBOL res 240 192 R0
SYMATTR InstName R4
SYMATTR Value 68k
SYMBOL voltage -240 128 R0
WINDOW 3 -62 107 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0 50m 1k)
SYMATTR InstName V1
SYMBOL res 240 80 R0
SYMATTR InstName R3
SYMATTR Value 22k
SYMBOL res 80 176 R90
WINDOW 0 13 24 VBottom 2
WINDOW 3 -14 123 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
FLAG -64 352 0
FLAG 144 256 0
FLAG 256 336 0
FLAG -240 256 0
FLAG -208 48 in
FLAG 272 48 out
TEXT -288 -48 Left 2 ;Semiconductor Devices: JFET Voltage Controlled Resistor\nhttps://youtu.be/T4IESXeRtWo?si=Ukin5aEwjMJSvs0i
TEXT 80 400 Left 2 !.tran 2m
TEXT -280 400 Left 2 !.step param VC -5 5 1
* Z:\home\khalils\Downloads\files\data\raw_asc\UniversalOpAmp3a.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
V3 N001 0 PULSE(-50m 50m 250n 1n 1n 1u 2u)
R1 OUT 0 10k
C1 OUT 0 10p
XU1 N001 OUT +V -V OUT level3a Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.tran 1.5u
* A two pole op amp with two internal nodes, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp3a.asy)
.lib UniversalOpAmp3a.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2580 1312
WIRE 560 560 400 560
WIRE 496 624 496 608
WIRE 400 640 400 560
WIRE 464 640 400 640
WIRE 560 656 560 560
WIRE 560 656 528 656
WIRE 656 656 560 656
WIRE 464 672 400 672
WIRE 560 672 560 656
WIRE 656 672 656 656
WIRE 496 704 496 688
WIRE 176 752 176 736
WIRE 288 752 288 736
WIRE 400 752 400 672
WIRE 560 768 560 752
WIRE 656 768 656 736
WIRE 176 848 176 832
WIRE 288 848 288 832
WIRE 400 848 400 832
FLAG 288 848 0
FLAG 176 848 0
FLAG 176 736 +V
FLAG 288 736 -V
FLAG 400 848 0
FLAG 496 704 -V
FLAG 496 608 +V
FLAG 656 768 0
FLAG 560 768 0
FLAG 656 656 OUT
SYMBOL voltage 176 736 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 288 736 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 400 736 R0
WINDOW 0 25 13 Left 2
WINDOW 3 27 90 Left 2
WINDOW 123 27 116 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(-50m 50m 250n 1n 1n 1u 2u)
SYMBOL res 544 656 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 640 672 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL UniversalOpAmp3a 496 656 R0
WINDOW 123 83 -96 Left 2
WINDOW 39 82 -70 Left 2
WINDOW 40 81 -44 Left 2
SYMATTR InstName U1
TEXT 152 904 Left 2 !.tran 1.5u
TEXT 376 904 Left 2 ;A two pole op amp with two internal nodes, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP172-1.26.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP172-1.26.asy)
V1 IN 0 3.6
RLOAD OUT 0 3.79
XU1 OUT IN IN 0 ADP172-1.26 ;pnba Vout)Vin)En)GND
C1 OUT 0 1
.tran 2m startup
.lib ADP172-1.26.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 80 -48 80
WIRE 48 80 -32 80
WIRE 64 80 48 80
WIRE 304 80 256 80
WIRE 336 80 304 80
WIRE 384 80 336 80
WIRE -48 96 -48 80
WIRE 304 96 304 80
WIRE 304 176 304 160
WIRE 384 176 384 160
WIRE -48 192 -48 176
WIRE 48 192 48 80
WIRE 64 192 48 192
WIRE 272 192 256 192
SYMBOL res 368 64 R0
SYMATTR InstName RLOAD
SYMATTR Value 3.79
SYMBOL ADP172-1.26 160 192 R0
SYMATTR InstName U1
SYMBOL cap 288 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -48 80 R0
SYMATTR InstName V1
SYMATTR Value 3.6
FLAG -48 192 0
FLAG 304 176 0
FLAG 272 192 0
FLAG 384 176 0
FLAG -32 80 IN
FLAG 336 80 OUT
TEXT 160 256 Center 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3078.asc
* Generated by LTspice 26.0.1 for Windows.
I3 OUT 0 PULSE(0 4.77 5m 1u 1u 1m 2m)
C1 N002 0 4.7
V1 N001 0 5
V2 IN 0 1.65
R1 OUT N003 499k
R2 OUT 0 4.8
C2 OUT 0 10 Rser=2m
R3 N004 P001 40.2k
C3 P001 0 20p
C4 N005 0 4.7
XU1 IN 0 NC_01 NC_02 N003 N004 OUT N001 TEMP OUT 0 IN N005 NC_03 0 N002 LT3078 TA=25 Rth=42 ;pnba EN)Vo0)Vo1)Vo2)PG)VIOC)OUT)BIAS)TEMP)SENSE)GND)IN)REF)MARG)IMON)BIASF
.tran 10m startup
* TA and Rth are the ambient temperature and thermal resistance used in the simulation.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3078.asy)
.lib LT3078.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1988 1664
WIRE 208 1008 -128 1008
WIRE 480 1008 336 1008
WIRE 592 1008 544 1008
WIRE -128 1040 -128 1008
WIRE 208 1040 208 1008
WIRE 336 1040 336 1008
WIRE 80 1104 -32 1104
WIRE 96 1104 80 1104
WIRE 528 1104 448 1104
WIRE 672 1104 608 1104
WIRE -32 1120 -32 1104
WIRE -128 1136 -128 1120
WIRE 80 1168 80 1104
WIRE 96 1168 80 1168
WIRE 560 1168 448 1168
WIRE -32 1216 -32 1200
WIRE 96 1232 80 1232
WIRE 560 1232 560 1168
WIRE 560 1232 448 1232
WIRE 672 1232 672 1104
WIRE 672 1232 560 1232
WIRE 784 1232 672 1232
WIRE 560 1248 560 1232
WIRE 672 1248 672 1232
WIRE 784 1248 784 1232
WIRE 560 1328 560 1312
WIRE 672 1344 672 1328
WIRE 784 1344 784 1328
WIRE 464 1360 448 1360
WIRE 96 1424 64 1424
WIRE 480 1424 448 1424
WIRE 560 1424 544 1424
WIRE 208 1504 208 1488
WIRE 336 1504 336 1488
WIRE 352 1504 336 1504
FLAG 208 1504 0
FLAG -80 1424 0
FLAG 80 1232 0
FLAG -32 1216 0
FLAG -32 1104 IN
FLAG -128 1136 0
FLAG 560 1328 0
FLAG 672 1344 0
FLAG 784 1232 OUT
FLAG 784 1344 0
FLAG 464 1360 0
FLAG 560 1424 0
FLAG 592 1008 0
FLAG 336 1504 TEMP
SYMBOL current 784 1248 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I3
SYMATTR Value PULSE(0 4.77 5m 1u 1u 1m 2m)
SYMBOL cap 480 1024 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value 4.7
SYMATTR InstName C1
SYMBOL voltage -128 1024 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -32 1104 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.65
SYMBOL res 624 1088 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 499k
SYMBOL res 656 1232 R0
SYMATTR InstName R2
SYMATTR Value 4.8
SYMBOL cap 544 1248 R0
WINDOW 3 26 56 Left 2
SYMATTR Value 10
SYMATTR InstName C2
SYMATTR SpiceLine Rser=2m
SYMBOL res 80 1408 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 40.2k
SYMBOL cap -16 1408 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 39 53 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 20p
SYMBOL cap 480 1440 R270
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 39 53 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 4.7
SYMBOL LT3078 272 1216 R0
SYMATTR InstName U1
TEXT 904 1600 Left 2 !.tran 10m startup
TEXT 96 1560 Left 2 ;TA and Rth are the ambient temperature and thermal resistance used in the simulation.
* Z:\home\khalils\Downloads\files\data\raw_asc\0e3582086da3_Lap.asc
* Generated by LTspice 26.0.1 for Windows.
B1 out 0 V=V(in) Laplace(W(s))
R1 in 0 1G
.func W(p) {1/(1+p*2e-3)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 144 48 144
WIRE 224 144 160 144
SYMBOL bv 160 128 R0
WINDOW 0 39 57 Left 0
WINDOW 3 -70 133 Left 0
SYMATTR InstName B1
SYMATTR Value V=V(in) Laplace(W(s))
SYMBOL res 80 128 R0
WINDOW 0 -35 49 Left 0
WINDOW 3 -37 77 Left 0
SYMATTR InstName R1
SYMATTR Value 1G
FLAG 160 224 0
FLAG 224 144 out
FLAG 48 144 in
FLAG 96 224 0
TEXT 64 112 Left 0 !.func W(p) {1/(1+p*2e-3)}