Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4098-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4098-2.asy)
V1 +V 0 5
XU1 IN N001 +V -V OUT NC_01 ADA4098-1 ;pnba In+)In-)V+)V-)OUT)SD
R2 OUT N001 1k
Vin IN 0 SINE(0 10m 100k)
V2 -V 0 -5
C1 OUT 0 10p
R3 OUT 0 10k
R1 N001 0 1k
.tran 100u
.lib ADA4098-1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 752 -1216 624 -1216
WIRE 160 -1152 160 -1168
WIRE 272 -1152 272 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 704 -1104 608 -1104
WIRE 752 -1104 752 -1216
WIRE 752 -1104 704 -1104
WIRE 848 -1104 752 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 848 -1072 848 -1104
WIRE 560 -1056 560 -1072
WIRE 160 -1040 160 -1072
WIRE 272 -1040 272 -1072
WIRE 432 -976 432 -992
WIRE 752 -976 752 -1008
WIRE 848 -976 848 -1008
SYMBOL cap 832 -1072 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 160 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 272 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL OpAmps\\ADA4098-2 576 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 10m 100k)
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 736 -1104 R0
SYMATTR InstName R3
SYMATTR Value 10k
FLAG 160 -1168 +V
FLAG 432 -976 0
FLAG 704 -1104 OUT
FLAG 432 -1088 IN
FLAG 560 -1136 +V
FLAG 272 -1168 -V
FLAG 560 -1056 -V
FLAG 416 -1216 0
FLAG 272 -1040 0
FLAG 160 -1040 0
FLAG 752 -976 0
FLAG 848 -976 0
TEXT 680 -936 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8068.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 24
C2 OUT1 0 22 Rser=30m
R2 N001 0 162K
XU1 IN 0 IN 0 OUT1 OUT2 N002 N001 MP_01 NC_02 LTM8068 ;pnba RUN)Voutn)Vin)GND)Vout1)Vout2)Rref)FB2))BYP
R1 N002 0 7.32K
C1 OUT2 0 10 Rser=5m
Rload OUT2 0 16.67
.tran 7m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8068.asy)
.lib LTM8068.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 964 680
WIRE 64 48 -16 48
WIRE 80 48 64 48
WIRE 352 48 304 48
WIRE 384 48 352 48
WIRE -16 64 -16 48
WIRE 64 144 64 48
WIRE 80 144 64 144
WIRE 480 144 304 144
WIRE 560 144 480 144
WIRE -16 160 -16 144
WIRE 480 160 480 144
WIRE 560 160 560 144
WIRE 320 240 304 240
WIRE 416 240 400 240
WIRE 480 256 480 224
WIRE 560 256 560 240
WIRE -16 336 -32 336
WIRE 80 336 64 336
WIRE 80 432 64 432
WIRE 320 432 304 432
FLAG 64 432 0
FLAG -16 160 0
FLAG -16 48 IN
FLAG 352 48 OUT1
FLAG -32 336 0
FLAG 560 144 OUT2
FLAG 320 432 0
FLAG 416 240 0
FLAG 448 48 0
FLAG 480 256 0
FLAG 560 256 0
SYMBOL voltage -16 48 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL cap 384 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=30m
SYMBOL res 304 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 162K
SYMBOL PowerProducts\\LTM8068 192 240 R0
SYMATTR InstName U1
SYMBOL res 80 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 7.32K
SYMBOL cap 464 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=5m
SYMBOL res 544 144 R0
SYMATTR InstName Rload
SYMATTR Value 16.67
TEXT 432 424 Left 2 !.tran 7m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2142b964b4c3_ampTest1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6241.asy)
R5 N002 SIG 2.4k
R2 VDD N002 649k
C1 OUT N001 4p
R4 N001 0 2.4k
XU1 N002 N001 VDD 0 OUT LTC6241 ;pnba IN+)IN-)VCC)VEE)OUT
R1 OUT N001 26.7k
V1 VDD 0 3.3
V2 SIG 0 AC 1
R3 N002 0 53.6k
.ac dec 100 1k 10000k
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 576 -160 512 -160
WIRE 688 -160 656 -160
WIRE 400 -64 384 -64
WIRE 512 -64 512 -160
WIRE 512 -64 480 -64
WIRE 576 -64 512 -64
WIRE 688 -64 688 -160
WIRE 688 -64 640 -64
WIRE 384 -32 384 -64
WIRE 224 48 224 16
WIRE 608 96 608 64
WIRE 512 112 512 -64
WIRE 576 112 512 112
WIRE 688 128 688 -64
WIRE 688 128 640 128
WIRE 816 128 688 128
WIRE 224 144 224 128
WIRE 512 144 224 144
WIRE 576 144 512 144
WIRE 224 160 224 144
WIRE 608 192 608 160
WIRE 400 208 368 208
WIRE 512 208 512 144
WIRE 512 208 480 208
WIRE 224 272 224 240
WIRE 48 288 48 256
WIRE -80 304 -80 272
WIRE -80 400 -80 368
WIRE 48 400 48 368
SYMBOL res 496 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 2.4k
SYMBOL res 496 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 2.4k
SYMBOL cap 640 -80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4p
SYMBOL Misc\\signal 48 272 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V2
SYMATTR Value ""
SYMBOL Opamps\\LTC6241 608 128 R0
SYMATTR InstName U1
SYMBOL res 208 144 R0
SYMATTR InstName R3
SYMATTR Value 53.6k
SYMBOL res 208 32 R0
SYMATTR InstName R2
SYMATTR Value 649k
SYMBOL res 672 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 26.7k
SYMBOL Misc\\cell -80 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG -80 400 0
FLAG 608 192 0
FLAG -80 272 VDD
FLAG 608 64 VDD
FLAG 224 272 0
FLAG 224 16 VDD
FLAG 384 -32 0
FLAG 368 208 SIG
FLAG 48 400 0
FLAG 48 256 SIG
FLAG 816 128 OUT
TEXT -112 424 Left 2 !.ac dec 100 1k 10000k
* Z:\home\khalils\Downloads\files\data\raw_asc\2fd9edd809e1_Draft12.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N003 10k
Q1 N002 0 N001 0 PNP
V1 v+ 0 12
V2 N003 0 {V}
R2 v+ N001 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10m
.step param V 0 12 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1032 680
WIRE 112 128 112 80
WIRE 112 256 112 208
WIRE 480 288 480 240
WIRE 48 304 -16 304
WIRE -16 368 -16 304
WIRE 112 400 112 352
WIRE 480 400 480 368
WIRE 624 400 480 400
WIRE 624 448 624 400
WIRE 112 528 112 480
WIRE 112 656 112 608
SYMBOL pnp 48 352 M180
SYMATTR InstName Q1
SYMBOL res 96 112 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 480 272 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage 112 512 R0
SYMATTR InstName V2
SYMATTR Value {V}
SYMBOL res 96 384 R0
SYMATTR InstName R1
SYMATTR Value 10k
FLAG -16 368 0
FLAG 624 448 0
FLAG 480 240 v+
FLAG 112 80 v+
FLAG 112 656 0
TEXT 696 176 Left 2 !.tran 10m\n.step param V 0 12 1
* Z:\home\khalils\Downloads\files\data\raw_asc\79e5494c997e_current2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1001.asy)
XU1 N004 N001 N002 0 OUT LT1001 ;pnba In+)In-)V+)V-)OUT
R6 N006 0 1k
R2 OUT N001 100k
R5 OUT N006 1k
R1 N001 N003 500
R3 N004 N005 500
V1 N003 0 5V
R4 0 N004 100k
V2 N002 0 12V
V3 N005 0 5.035
.tran 0 10 0 .01
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 964 680
WIRE 352 48 304 48
WIRE 480 48 432 48
WIRE 528 96 384 96
WIRE 160 112 112 112
WIRE 304 112 304 48
WIRE 304 112 240 112
WIRE 384 128 384 96
WIRE 304 144 304 112
WIRE 352 144 304 144
WIRE 480 160 480 48
WIRE 480 160 416 160
WIRE 608 160 480 160
WIRE 640 160 608 160
WIRE 352 176 304 176
WIRE 640 192 640 160
WIRE 160 256 112 256
WIRE 304 256 304 176
WIRE 304 256 240 256
WIRE 304 272 304 256
WIRE 528 304 528 96
WIRE 640 304 640 272
WIRE 384 416 384 192
WIRE 416 416 384 416
WIRE 528 416 528 384
WIRE 528 416 416 416
WIRE 304 432 304 352
WIRE 416 432 416 416
WIRE 640 432 640 384
SYMBOL res 256 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -48 59 VTop 2
SYMATTR InstName R1
SYMATTR Value 500
SYMBOL res 624 176 R0
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL res 256 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500
SYMBOL voltage 528 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 12V
SYMBOL Opamps\\LT1001 384 96 R0
SYMATTR InstName U1
SYMBOL res 448 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL res 624 288 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res 320 368 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage 112 240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 5.035
SYMBOL voltage 112 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5V
FLAG 416 432 0
FLAG 608 160 OUT
FLAG 304 432 0
FLAG 640 432 0
FLAG 112 192 0
FLAG 112 336 0
TEXT 80 456 Left 2 !.tran 0 10 0 .01
* Z:\home\khalils\Downloads\files\data\raw_asc\2380337a4bbe_rev_breakdown_voltage.asc
* Generated by LTspice 26.0.1 for Windows.
* Reverse Breakdown Voltage
V2 V- 0 -5
Q1 +1 +1 V- 0 2N3906
V1 +2 0 PULSE(-5 5 0 5m 5m 0 10m)
R1 +2 +1 100
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 -128 -112 -128
WIRE 304 -128 -64 -128
WIRE 384 -128 304 -128
WIRE 304 -80 304 -128
WIRE -64 -64 -64 -128
WIRE 304 32 304 0
WIRE 384 32 304 32
WIRE -64 48 -64 16
WIRE 304 80 304 32
WIRE 384 80 304 80
WIRE 304 128 304 80
WIRE 304 128 176 128
WIRE 304 160 304 128
WIRE 176 208 176 128
WIRE 240 208 176 208
WIRE 304 288 304 256
WIRE 384 288 304 288
WIRE 304 336 304 288
WIRE 384 336 304 336
WIRE 304 352 304 336
WIRE 304 464 304 432
IOPIN -112 -128 In
IOPIN 384 -128 In
IOPIN 384 32 In
IOPIN 384 80 In
IOPIN 384 288 In
IOPIN 384 336 In
SYMBOL res 288 -96 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL pnp 240 160 R0
SYMATTR InstName Q1
SYMATTR Value 2N3906
SYMBOL voltage -64 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(-5 5 0 5m 5m 0 10m)
SYMBOL voltage 304 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -5
FLAG -112 -128 W1
FLAG 384 -128 +2
FLAG 384 32 -2
FLAG 384 80 +1
FLAG 384 288 -1
FLAG -64 48 0
FLAG 384 336 V-
FLAG 304 464 0
TEXT -48 368 Left 2 !.tran 100m
TEXT -32 -184 Left 2 ;Reverse Breakdown Voltage
* Z:\home\khalils\Downloads\files\data\raw_asc\34d729eb1ffb_Modelo.asc
* Generated by LTspice 26.0.1 for Windows.
**********
*SRC=ARF463AB;ARF463AB;MOSFETs N;Enh;500V 9.0A 1.1ohms PPG Microsemi RF MOSFET
*SYM=POWMOSN
*09-14-09 Rev A GJK PPG Microsemi
* TERMINALS: D G S
*****
RG 19 2 .5
RS 29 3 2.25m
DSD 3 1 DSUB
R1 N001 N002 10
LG 20 19 2.8n
LS 30 29 2n
VGG N003 0 PULSE(0 6 0 1e-12 1e-12 1.25e-6 250e-6)
D2 5 2 DGD
M1 1 2 3 3 DMOS L=1U W=1U
VDD N001 0 125
RD 11 1 1.1
CGS 2 3 1200p
LD 10 11 2n
XM1 N002 N003 0 ARF463AB ;pnba D)G)S
D1 5 1 DGD
.tran 10e-6
.SUBCKT ARF463AB 10 20 30
.MODEL DMOS NMOS(LEVEL=3 VMAX=1.04Meg THETA=100.0m ETA=2.00m VTO=3.00 KP=2.60)
.MODEL DSUB D (IS=1.27u N=1.50 RS=5.00m BV=500 CJO=799p VJ=0.800 M=0.420 TT=311n)
.MODEL DGD D (IS=100n N=1.5 RS=10m BV=500 CJO=81.7p M=.5 VJ=.700 TT=1n)
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2376 868
WIRE 1984 160 1840 160
WIRE 1984 208 1984 160
WIRE 1840 224 1840 160
WIRE 1840 320 1840 304
WIRE 1984 384 1984 288
WIRE 1936 464 1840 464
WIRE 1840 512 1840 464
WIRE 1984 544 1984 480
WIRE 1840 624 1840 592
SYMBOL voltage 1840 496 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VGG
SYMATTR Value PULSE(0 6 0 1e-12 1e-12 1.25e-6 250e-6)
SYMBOL res 1968 192 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage 1840 208 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 125
SYMBOL nmos 1936 384 R0
SYMATTR InstName M1
SYMATTR Value ARF463AB
SYMATTR Prefix X
FLAG 1984 544 0
FLAG 1840 320 0
FLAG 1840 624 0
TEXT 318 852 Left 2 !.tran 10e-6
TEXT 312 192 Left 2 !**********\n*SRC=ARF463AB;ARF463AB;MOSFETs N;Enh;500V 9.0A 1.1ohms PPG Microsemi RF MOSFET\n*SYM=POWMOSN\n*09-14-09 Rev A GJK PPG Microsemi\n.SUBCKT ARF463AB   10 20 30\n*     TERMINALS:  D  G  S\nM1   1  2  3  3  DMOS L=1U W=1U\nLD  10  11  2n\nRD  11          1   1.1\nLG  20  19  2.8n\nRG  19  2   .5\nD1   5  1   DGD\nD2   5  2   DGD\nCGS  2  3   1200p\nDSD  3  1   DSUB\nRS  29  3   2.25m\nLS  30  29  2n\n.MODEL DMOS NMOS(LEVEL=3 VMAX=1.04Meg THETA=100.0m ETA=2.00m VTO=3.00 KP=2.60)\n.MODEL DSUB D (IS=1.27u N=1.50 RS=5.00m BV=500 CJO=799p VJ=0.800 M=0.420 TT=311n)\n.MODEL DGD  D (IS=100n N=1.5 RS=10m BV=500 CJO=81.7p M=.5 VJ=.700 TT=1n)\n.ENDS\n*****
* Z:\home\khalils\Downloads\files\data\raw_asc\168d23038f34_Draft14.asc
* Generated by LTspice 26.0.1 for Windows.
R1 R_end 0 100
T3 N002 N009 N003 N010 Td=50n Z0=50
T1 s 0 N001 N008 Td=50n Z0=50
T8 N007 N013 R_end 0 Td=50n Z0=50
T6 N005 N012 N006 N006 Td=50n Z0=50
T7 N006 N006 N007 N013 Td=50n Z0=50
V1 s 0 PULSE(0 5 0 0.1n 0.1n 0.5n 0 1)
T5 N004 N011 N005 N012 Td=50n Z0=50
T2 N001 N008 N002 N009 Td=50n Z0=50
T4 N003 N010 N004 N011 Td=50n Z0=50
.tran 0 900n 0 0.6n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1732 680
WIRE -32 32 -48 32
WIRE 80 32 -32 32
WIRE 272 32 176 32
WIRE 464 32 368 32
WIRE 656 32 560 32
WIRE 832 32 752 32
WIRE 1008 32 928 32
WIRE 1152 32 1104 32
WIRE 1184 32 1152 32
WIRE 1360 32 1280 32
WIRE 1648 32 1456 32
WIRE 1664 32 1648 32
WIRE 80 64 16 64
WIRE 272 64 176 64
WIRE 464 64 368 64
WIRE 656 64 560 64
WIRE 832 64 752 64
WIRE 1008 64 928 64
WIRE 1152 64 1152 32
WIRE 1152 64 1104 64
WIRE 1184 64 1152 64
WIRE 1360 64 1280 64
WIRE 1552 64 1456 64
WIRE 1664 112 1664 32
WIRE -48 128 -48 32
WIRE -48 272 -48 208
WIRE 16 272 16 64
WIRE 1552 304 1552 64
WIRE 1664 304 1664 192
SYMBOL tline 704 48 R0
SYMATTR InstName T4
SYMBOL voltage -48 112 R0
WINDOW 3 -54 -105 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 0.1n 0.1n 0.5n 0 1)
SYMBOL res 1648 96 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL tline 880 48 R0
SYMATTR InstName T5
SYMBOL tline 1232 48 R0
SYMATTR InstName T7
SYMBOL tline 1408 48 R0
SYMATTR InstName T8
SYMBOL tline 512 48 R0
SYMATTR InstName T3
SYMBOL tline 128 48 R0
SYMATTR InstName T1
SYMBOL tline 1056 48 R0
SYMATTR InstName T6
SYMBOL tline 320 48 R0
SYMATTR InstName T2
FLAG -48 272 0
FLAG 16 272 0
FLAG 1552 304 0
FLAG 1664 304 0
FLAG 1648 32 R_end
FLAG -32 32 s
TEXT -88 440 Left 2 !.tran 0 900n 0 0.6n
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5685R.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc I1 0 40m 1m
* .ac oct 100 1u 1G
* Gain parameter can be 1 or 2
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5685R.asy)
CLOAD vOUT 0 10n
Vdac vDAC 0 PWL(0 0.625 10u 0.625 +1u 1.875)
XU2 vDAC Vdd 0 vOUT AD5685R Gain=2 ;pnba Vdac)Vdd)GND)Vout
V1 Vdd 0 5
Vdac1 NC_01 0 1.25
I1 0 0 100 AC 1
.tran 200u
.lib AD5685R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -240 -208 -240 -240
WIRE -240 -80 -240 -128
WIRE -240 -32 -240 -80
WIRE -800 112 -1008 112
WIRE -528 112 -800 112
WIRE -368 112 -528 112
WIRE 192 112 0 112
WIRE 272 112 192 112
WIRE 464 112 272 112
WIRE -800 144 -800 112
WIRE 272 160 272 112
WIRE -1008 256 -1008 224
WIRE -800 256 -800 224
WIRE 272 256 272 224
WIRE 464 256 464 240
WIRE 464 256 272 256
WIRE 272 272 272 256
WIRE -240 288 -240 256
SYMBOL current 464 160 R0
WINDOW 123 24 108 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName I1
SYMATTR Value 100
SYMBOL cap 256 160 R0
SYMATTR InstName CLOAD
SYMATTR Value 10n
SYMBOL voltage -800 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac
SYMATTR Value PWL(0 0.625 10u 0.625 +1u 1.875)
SYMBOL AD5685R -208 112 R0
SYMATTR InstName U2
SYMBOL voltage -240 -112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -1008 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac1
SYMATTR Value 1.25
FLAG 192 112 vOUT
FLAG -800 256 0
FLAG -528 112 vDAC
FLAG -240 -240 0
FLAG -240 288 0
FLAG 272 272 0
FLAG -240 -80 Vdd
FLAG -1008 256 0
FLAG 464 160 0
TEXT -160 312 Left 2 !.tran 200u
TEXT -160 360 Left 2 ;.dc I1 0 40m 1m
TEXT -160 408 Left 2 ;.ac oct 100 1u 1G
TEXT -632 368 Left 2 ;Gain parameter can be 1 or 2
* Z:\tmp\asc_dec_bjh7r6w2\136c11eba467_Measure_Margins_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
Vin N003 0 AC {1-lp*lp}
C2 0 N004 3p
C1 N004 N001 3p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2848 1728
WIRE 1120 256 1120 208
WIRE 1120 368 1120 336
WIRE 1232 208 1120 208
WIRE 1232 288 1232 208
WIRE 1296 384 1296 176
WIRE 1344 176 1296 176
WIRE 1344 288 1232 288
WIRE 1472 384 1296 384
WIRE 1472 384 1472 304
WIRE 1488 176 1344 176
WIRE 1488 208 1456 208
WIRE 1504 384 1472 384
WIRE 1520 160 1520 144
WIRE 1520 240 1520 224
WIRE 1568 304 1472 304
WIRE 1664 304 1632 304
WIRE 1664 384 1584 384
WIRE 1664 384 1664 304
WIRE 1744 384 1664 384
WIRE 1744 416 1744 384
WIRE 1744 496 1744 480
WIRE 1760 192 1552 192
WIRE 1840 384 1744 384
WIRE 2032 384 1920 384
SYMBOL voltage 1120 240 R0
WINDOW 38 60 56 VTop 0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC {1-lp*lp}
SYMATTR InstName Vin
SYMATTR Value ""
SYMBOL cap 1728 480 M180
WINDOW 0 24 64 Left 0
WINDOW 3 24 8 Left 0
SYMATTR InstName C2
SYMATTR Value 3p
SYMBOL cap 1632 320 M270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 3p
FLAG 1520 144 +V
FLAG 1520 240 -V
FLAG 1120 368 0
FLAG 1456 208 0
FLAG 1744 496 0
* Z:\tmp\asc_dec_bjh7r6w2\0a3c4258feab_FiltroAntiAlias_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
C2 Vo 0 10n
R1 N003 N002 3k3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 0 128 0
WIRE 128 48 128 0
WIRE 160 48 128 48
WIRE 256 64 256 0
WIRE 256 64 224 64
WIRE 16 80 -32 80
WIRE 128 80 96 80
WIRE 160 80 128 80
WIRE 256 80 256 64
WIRE 272 80 256 80
WIRE 384 80 352 80
WIRE 416 80 384 80
WIRE -32 112 -32 80
WIRE 128 112 128 80
WIRE 384 112 384 80
WIRE -32 224 -32 192
WIRE 128 224 128 176
WIRE 384 224 384 176
SYMBOL cap 368 112 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res 112 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 3k3
FLAG 128 224 0
FLAG 384 224 0
FLAG 416 80 Vo
FLAG -32 224 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-1.8.asy)
V1 IN 0 5.5
C2 OUT 0 1
Rload OUT 0 100
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=76923 ;pnba Vout))Sense)GND)En)))Vin
C1 IN 0 1
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL ADP124-1.8 256 208 R0
SYMATTR InstName U1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\204563ade8a8_3048-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3048-12.asy)
C2 OUT N003 .1n
Rload OUT 0 413.8
XU1 N002 IN 0 N003 OUT N001 IN N001 LT3048-12 ;pnba SW)Vin)GND)BYP)LDOOUT)LDOIN)EN)BSTOUT
C1 N001 0 4.7
V1 IN 0 3.3
C3 OUT 0 1 Rser=10m
L1 IN N002 10 Rser=.65
.tran 1.5m startup
.lib LT3048-12.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 416 48 256 48
WIRE 464 48 416 48
WIRE 256 64 256 48
WIRE 464 64 464 48
WIRE 112 128 80 128
WIRE 416 128 416 48
WIRE 416 128 400 128
WIRE 464 144 464 128
WIRE 80 224 80 208
WIRE 80 224 -32 224
WIRE 112 224 80 224
WIRE 448 224 400 224
WIRE 528 224 448 224
WIRE 608 224 528 224
WIRE -32 240 -32 224
WIRE 448 240 448 224
WIRE 528 240 528 224
WIRE 608 240 608 224
WIRE 80 320 80 224
WIRE 112 320 80 320
WIRE 448 320 448 304
WIRE 448 320 400 320
WIRE -32 336 -32 320
WIRE 528 336 528 304
WIRE 608 336 608 320
WIRE 256 400 256 384
SYMBOL cap 432 240 R0
SYMATTR InstName C2
SYMATTR Value .1n
SYMBOL res 592 224 R0
SYMATTR InstName Rload
SYMATTR Value 413.8
SYMBOL ind 96 224 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value 10u
SYMATTR SpiceLine Rser=.65
SYMBOL cap 512 240 R0
SYMATTR InstName C3
SYMATTR Value 1u
SYMATTR SpiceLine Rser=10m
SYMBOL voltage -32 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL PowerProducts\\LT3048-12 256 224 R0
SYMATTR InstName U1
SYMBOL cap 448 64 R0
SYMATTR InstName C1
SYMATTR Value 4.7u
FLAG 256 400 0
FLAG -32 336 0
FLAG 464 144 0
FLAG 528 336 0
FLAG 608 336 0
FLAG -32 224 IN
FLAG 608 224 OUT
TEXT 432 384 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\02ea5393bd18_DFF.asc
* Generated by LTspice 26.0.1 for Windows.
* D Flip-Flop
* binary
* binary
* binary
* binary
* 2026-01-02
* <Revision History>\n2025-01-03: Initial version\n2026-01-02: Changed to .machine base state machine instead of Ltspice default DFF to avoid unexpected behaviour.
A1 o 0 0 0 0 xQ 0 0 BUF
A2 o 0 0 0 0 0 Q 0 BUF
R1 o 0 1k
.machine
.state LO 0
.state LATCH 1
.state HI 2
.rule LO LATCH V(clk)>.5
.rule LATCH HI V(clk)>.9
.rule * LO V(clk)<.5
.output (o) IF((state==1),V(D),V(Q))
.endmachine
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1208 680
WIRE -16 -496 -192 -496
WIRE 752 -496 704 -496
WIRE 848 -496 752 -496
WIRE 896 -496 848 -496
WIRE 976 -496 960 -496
WIRE 752 -464 752 -496
WIRE 896 -464 896 -480
WIRE -32 -368 -160 -368
WIRE 848 -368 848 -496
WIRE 896 -368 848 -368
WIRE 976 -368 960 -368
WIRE 752 -352 752 -384
WIRE 896 -336 896 -352
IOPIN -192 -496 In
IOPIN -160 -368 In
IOPIN 976 -496 Out
IOPIN 976 -368 Out
SYMBOL Digital\\buf1 896 -560 R0
SYMATTR InstName A2
SYMBOL res 736 -480 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL Digital\\inv 896 -432 R0
SYMATTR InstName A1
FLAG -192 -496 D
FLAG -160 -368 CLK
FLAG 976 -496 Q
FLAG 976 -368 xQ
FLAG 896 -336 0
FLAG 896 -464 0
FLAG 752 -352 0
FLAG 704 -496 o
TEXT -256 -648 Left 3 ;D Flip-Flop
TEXT -232 -520 Left 1 ;binary
TEXT -200 -392 Left 1 ;binary
TEXT 968 -520 Left 1 ;binary
TEXT 976 -392 Left 1 ;binary
TEXT 976 -656 Left 2 ;2026-01-02
TEXT 144 -528 Left 2 !.machine\n.state LO 0\n.state LATCH 1\n.state HI 2\n.rule LO LATCH V(clk)>.5\n.rule LATCH HI  V(clk)>.9\n.rule * LO V(clk)<.5\n.output (o) IF((state==1),V(D),V(Q))  \n.endmachine
TEXT -264 -200 Left 2 ;<Revision History>\n2025-01-03: Initial version\n2026-01-02: Changed to .machine base state machine instead of Ltspice default DFF to avoid unexpected behaviour.