* Z:\home\khalils\Downloads\files\data\raw_asc\a8fc710bcecc_GainStage_DCanalysis.asc
* Generated by LTspice 26.0.1 for Windows.
* Power rails
* MIC
* PIC analog input impedance model
* Readme:\nThis simulation is for modeling the AC transfer function of the analog gain stage,\nfor debugging and component selection. Currently there are two "groups" of component\nchoices, one for notes below middle C (65 - 262Hz), and one for notes above middle C (262 - 1047Hz).\nTo simulate one group, uncomment the corresponding "Parameter Group" SPICE directive.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
;PARAMETER GROUP 1 (LOW FREQUENCY)
;Amplifier stage
R9 N004 N003 10k
C10 ADC_in 0 5p
XU1 Midscale1 N001 Vdd 0 AmpOut level1 Avol=0.5Meg GBW=0.73Meg Vos={V_inputOffset} En=0 Enk=0 In=0 Ink=0 Rin=1e13 ;pnba In+)In-)V+)V-)OUT
C6 N004 0 5p
R13 N002 N001 {R_fbTop}
R1 ADC_in N004 10k
V2 Midscale1 0 3.3
R16 N003 AmpOut 1k
R14 N002 AmpOut {R_fbTop}
V4 Midscale2 Midscale1 0
C_pin N003 0 50p
R15 Midscale2 N002 {R_fbBot}
V1 Vdd 0 3.3
.param R_fbTop = 10Meg
.param R_fbBot = 270k
.param V_inputOffset = 0.00
.dc v4 -0.1 0.1 0.05
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4120 1800
WIRE -2000 -256 -2000 -352
WIRE -2000 -144 -2000 -176
WIRE -1344 -128 -1344 -160
WIRE -1664 -16 -1664 -48
WIRE -1344 -16 -1344 -48
WIRE -1344 -16 -1664 -16
WIRE -1664 0 -1664 -16
WIRE -1664 112 -1664 80
WIRE -48 208 -128 208
WIRE 256 208 32 208
WIRE 288 208 256 208
WIRE 448 208 368 208
WIRE 256 240 256 208
WIRE -128 352 -128 208
WIRE -80 352 -128 352
WIRE 256 368 256 320
WIRE 256 368 -16 368
WIRE 304 368 256 368
WIRE 672 368 304 368
WIRE 992 368 752 368
WIRE 1072 368 992 368
WIRE 1200 368 1152 368
WIRE 1264 368 1200 368
WIRE 1392 368 1344 368
WIRE 1552 368 1392 368
WIRE -80 384 -240 384
WIRE 1200 400 1200 368
WIRE 1392 400 1392 368
WIRE -48 448 -48 400
WIRE 992 480 992 432
WIRE 1200 480 1200 464
WIRE 1200 480 992 480
WIRE 1200 512 1200 480
WIRE 1392 512 1392 464
SYMBOL cap 976 368 R0
SYMATTR InstName C_pin
SYMATTR Value 50p
SYMBOL voltage -1664 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 33 59 Left 2
WINDOW 3 27 85 Left 2
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 1360 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 1376 400 R0
SYMATTR InstName C10
SYMATTR Value 5p
SYMBOL voltage -1344 -144 R0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL res 384 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R15
SYMATTR Value {R_fbBot}
SYMBOL res 48 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R13
SYMATTR Value {R_fbTop}
SYMBOL cap 1184 400 R0
SYMATTR InstName C6
SYMATTR Value 5p
SYMBOL res 768 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R16
SYMATTR Value 1k
SYMBOL Opamps\\UniversalOpAmp -48 368 R0
SYMATTR InstName U1
SYMATTR Value2 Avol=0.5Meg GBW=0.73Meg Vos={V_inputOffset}
SYMATTR SpiceLine En=0 Enk=0 In=0 Ink=0 Rin=1e13
SYMBOL res 240 224 R0
SYMATTR InstName R14
SYMATTR Value {R_fbTop}
SYMBOL res 1168 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 10k
SYMBOL voltage -2000 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 33 59 Left 2
WINDOW 3 27 85 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG -2000 -144 0
FLAG -2000 -352 Vdd
FLAG 304 368 AmpOut
FLAG -48 336 Vdd
FLAG -48 448 0
FLAG 448 208 Midscale2
FLAG -240 384 Midscale1
FLAG 1200 512 0
FLAG 1392 512 0
FLAG 1552 368 ADC_in
FLAG -1664 112 0
FLAG -1664 -48 Midscale1
FLAG -1344 -160 Midscale2
TEXT -1608 -448 Left 4 ;Power rails
TEXT -808 -456 Left 4 ;MIC
TEXT -40 808 Left 2 !;PARAMETER GROUP 1 (LOW FREQUENCY)\n \n;Amplifier stage\n.param R_fbTop = 10Meg\n.param R_fbBot  = 270k\n.param V_inputOffset = 0.00
TEXT 1144 248 Left 2 ;PIC analog input impedance model
TEXT -680 1416 Left 5 ;Readme:\nThis simulation is for modeling the AC transfer function of the analog gain stage,\nfor debugging and component selection. Currently there are two "groups" of component\nchoices, one for notes below middle C (65 - 262Hz), and one for notes above middle C (262 - 1047Hz).\nTo simulate one group, uncomment the corresponding "Parameter Group" SPICE directive.
TEXT 208 1264 Left 4 !.dc v4 -0.1 0.1 0.05