Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8061-4.1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8061-4.1.asy)
C1 OUT 0 .2m
V1 IN 0 12
XU1 N001 N001 N001 N002 N003 0 N005 N004 OUT IN OUT MP_01 0 LTM8061-4.1 ;pnba Vin)VinC/CLP)RUN)_CHRG)_Fault)TMR)RNG/SS)NTC)BAT)VinA)Bias))GND
C3 N001 0 4.7
.tran 3m startup
.lib LTM8061-4.1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 80 -64 -32 -64
WIRE 384 -64 368 -64
WIRE 496 -64 384 -64
WIRE -32 -48 -32 -64
WIRE 496 -48 496 -64
WIRE 80 32 64 32
WIRE 384 32 384 -64
WIRE 384 32 368 32
WIRE 496 32 496 16
WIRE -32 48 -32 32
WIRE 64 128 64 32
WIRE 80 128 64 128
WIRE 384 128 368 128
WIRE -16 224 -32 224
WIRE 64 224 64 128
WIRE 64 224 48 224
WIRE 80 224 64 224
WIRE 384 224 368 224
WIRE 80 320 64 320
WIRE 384 320 368 320
WIRE 80 416 64 416
WIRE 384 416 368 416
SYMBOL cap 480 -48 R0
SYMATTR InstName C1
SYMATTR Value .2m
SYMBOL voltage -32 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL PowerProducts\\LTM8061-4.1 224 176 R0
SYMATTR InstName U1
SYMBOL cap 48 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7
FLAG 64 416 0
FLAG -32 48 0
FLAG 496 32 0
FLAG -32 -64 IN
FLAG 496 -64 OUT
FLAG -32 224 0
FLAG 64 320 0
TEXT 512 416 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\df9eaff10e15_BJT_output.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 N002 0 0 2N2222
VBE N002 0 0
VCE N001 0 1
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc VCE 0 1 0.01 VBE 0.4 1 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 80 160 80
WIRE 160 112 160 80
WIRE 320 128 320 80
WIRE 96 160 16 160
WIRE 16 176 16 160
WIRE 16 288 16 256
WIRE 160 288 160 208
WIRE 320 288 320 208
SYMBOL npn 96 112 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL voltage 320 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCE
SYMATTR Value 1
SYMBOL voltage 16 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VBE
SYMATTR Value 0
FLAG 16 288 0
FLAG 160 288 0
FLAG 320 288 0
TEXT -16 328 Left 2 !.dc VCE 0 1 0.01 VBE 0.4 1 0.05
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1412.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1412.asy)
V3 v+ 0 15
V1 vS 0 SINE(0 5 20)
C1 vD 0 36p
R1 vD 0 301
V4 v- 0 -15
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
XU1 vIN vS vD v- v+ 0 ADG1412 ;pnba IN)S)D)Vss)Vdd)GND
.tran 1
.lib ADG1412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 112 240 112
WIRE 240 144 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 368 224 336 224
WIRE 416 224 368 224
WIRE 528 224 416 224
WIRE 416 256 416 224
WIRE 528 256 528 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -272 304 -288 304
WIRE -176 304 -192 304
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 416 352 416 336
WIRE 528 352 528 320
WIRE 304 416 304 400
WIRE 176 432 176 400
WIRE 192 432 176 432
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL res 400 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL ADG1412 240 272 R0
SYMATTR InstName U1
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL cap 512 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 20)
FLAG -112 224 0
FLAG 48 464 0
FLAG 416 352 0
FLAG 304 416 0
FLAG 368 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 528 352 0
FLAG -272 304 v+
FLAG 256 112 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -176 304 v-
FLAG 192 432 v-
TEXT 80 528 Left 2 !.tran 1
TEXT -360 -40 Left 2 ;Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8604C.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8604C.asy)
R3 OUT PG 100k
V1 N001 0 12
R4 OUT FB 1.62Meg
Rload OUT 0 50
R2 RT 0 110k
C1 OUT 0 22
XU1 NC_01 SW OUT SYNC RT FB TRSS PG N001 N001 0 LT8604C LT8604=1 DFN=0 VOUT33=0 ;pnba HYST)SW)Bias)SYNC)Rt)FB)TR/SS)PG)EN/UV)Vin)GND
R1 FB 0 301k
L1 SW OUT 120 Rser=1
.tran 3m steady nodiscard
.lib LT8604C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1748 780
WIRE -32 48 -192 48
WIRE 16 48 -32 48
WIRE 336 48 304 48
WIRE 400 48 336 48
WIRE 528 48 480 48
WIRE 624 48 528 48
WIRE 800 48 624 48
WIRE 912 48 800 48
WIRE 944 48 912 48
WIRE -192 128 -192 48
WIRE -32 144 -32 48
WIRE 16 144 -32 144
WIRE 528 144 528 48
WIRE 528 144 304 144
WIRE 800 160 800 48
WIRE 944 160 944 48
WIRE 624 192 624 48
WIRE 800 256 800 224
WIRE 944 256 944 240
WIRE -192 272 -192 208
WIRE -48 336 -112 336
WIRE 16 336 -48 336
WIRE 336 336 304 336
WIRE 624 336 624 272
WIRE 624 336 336 336
WIRE 624 352 624 336
WIRE -64 432 -112 432
WIRE 16 432 -64 432
WIRE 624 464 624 432
WIRE -48 528 -192 528
WIRE 16 528 -48 528
WIRE 336 528 304 528
WIRE 384 528 336 528
WIRE 528 528 528 144
WIRE 528 528 464 528
WIRE -192 576 -192 528
WIRE 160 624 160 576
WIRE -192 720 -192 656
SYMBOL ind 384 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 120
SYMATTR SpiceLine Rser=1
SYMBOL res 608 176 R0
SYMATTR InstName R4
SYMATTR Value 1.62Meg
SYMBOL res 928 144 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL voltage -192 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 480 512 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL LT8604C 160 240 R0
SYMATTR InstName U1
SYMBOL res -208 560 R0
SYMATTR InstName R2
SYMATTR Value 110k
SYMBOL cap 784 160 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 608 336 R0
SYMATTR InstName R1
SYMATTR Value 301k
FLAG 624 464 0
FLAG 800 256 0
FLAG 912 48 OUT
FLAG -192 720 0
FLAG -192 272 0
FLAG 336 528 PG
FLAG 336 336 FB
FLAG 336 48 SW
FLAG -48 528 RT
FLAG -64 432 TRSS
FLAG 160 624 0
FLAG -48 336 SYNC
FLAG 944 256 0
TEXT 576 616 Left 2 !.tran 3m steady nodiscard
* Z:\home\khalils\Downloads\files\data\raw_asc\0c99d03324a8_Transmission_gate_vani.asc
* Generated by LTspice 26.0.1 for Windows.
M4 N001 clock clock_bar N002 PMOS l=2u w=20u
M2 in clock out N005 NMOS
M1 out clock_bar in N004 PMOS
V1 N001 0 1
V3 in 0 PULSE(0 1 0 1p 1p 0.5m 1m)
M3 clock_bar clock 0 N003 NMOS l=2u w=40u
V2 clock 0 PULSE(0 1 0 1p 1p 1m 2m)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 2m 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1052 680
WIRE 768 -272 768 -320
WIRE 768 -224 768 -256
WIRE 720 -192 672 -192
WIRE 608 -144 528 -144
WIRE 672 -144 672 -192
WIRE 672 -144 608 -144
WIRE 768 -144 768 -176
WIRE 880 -144 768 -144
WIRE 528 -128 528 -144
WIRE 768 -96 768 -144
WIRE 672 -16 672 -144
WIRE 720 -16 672 -16
WIRE 768 -16 768 -48
WIRE 176 144 112 144
WIRE 224 144 192 144
WIRE 352 144 272 144
WIRE 16 224 -96 224
WIRE 112 224 112 144
WIRE 112 224 16 224
WIRE 352 224 352 144
WIRE 448 224 352 224
WIRE -96 240 -96 224
WIRE 112 304 112 224
WIRE 176 304 112 304
WIRE 256 304 224 304
WIRE 352 304 352 224
WIRE 352 304 272 304
IOPIN 608 -144 In
IOPIN 256 352 In
IOPIN 880 -144 In
IOPIN 192 96 In
IOPIN 448 224 Out
IOPIN 16 224 In
SYMBOL nmos4 176 352 R270
SYMATTR InstName M2
SYMBOL pmos4 720 -272 R0
SYMATTR InstName M4
SYMATTR Value2 l=2u w=20u
SYMBOL pmos4 272 96 R90
SYMATTR InstName M1
SYMBOL voltage 528 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 1p 1p 1m 2m)
SYMBOL voltage 768 -304 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMBOL voltage -96 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 0 1p 1p 0.5m 1m)
SYMBOL nmos4 720 -96 R0
SYMATTR InstName M3
SYMATTR Value2 l=2u w=40u
FLAG 768 0 0
FLAG 768 -400 0
FLAG 528 -48 0
FLAG 608 -144 clock
FLAG 256 352 clock
FLAG 880 -144 clock_bar
FLAG 192 96 clock_bar
FLAG -96 320 0
FLAG 448 224 out
FLAG 16 224 in
TEXT 688 120 Left 2 !.tran 0 2m 0
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL42005-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL42005-5.0.asy)
R1 OUT N001 100k
XU1 IN OUT IN N001 OUT 0 ADPL42005-5.0 ;pnba Vin)Sense)EN)PG)Vout)GND
Rload OUT 0 10
C1 OUT 0 2.2 Rser=1.5m
V1 IN 0 8
.tran 3m startup
.lib ADPL42005-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL ADPL42005-5.0 224 128 R0
SYMATTR InstName U1
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 25 97 Left 2
SYMATTR Value 8
SYMATTR InstName V1
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup
* Z:\tmp\asc_dec_bjh7r6w2\0ac62ce9603e_fig-03-01-31_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
I1 0 N007 0 AC 1
XU2 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 NC_07 NC_08 ADA4077-2 ;pnba +INA)-INA)OUTA)V+)V-)+INB)-INB)OUTB
R2 N004 N003 1k
R1 N003 0 1k
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4077-2.asy)
.lib ADA4077-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 964 680
WIRE -336 32 -464 32
WIRE -96 32 -256 32
WIRE 256 32 128 32
WIRE 496 32 336 32
WIRE -384 112 -384 80
WIRE 208 112 208 80
WIRE -384 144 -384 112
WIRE 208 144 208 112
WIRE -576 160 -608 160
WIRE -464 160 -464 32
WIRE -464 160 -496 160
WIRE -416 160 -464 160
WIRE 16 160 -16 160
WIRE 128 160 128 32
WIRE 128 160 96 160
WIRE 176 160 128 160
WIRE -304 176 -352 176
WIRE -256 176 -304 176
WIRE 304 176 240 176
WIRE 496 176 496 32
WIRE 496 176 432 176
WIRE -416 192 -464 192
WIRE 176 192 128 192
WIRE -16 208 -16 160
WIRE 496 224 496 176
WIRE -464 256 -464 192
WIRE -384 256 -384 208
WIRE 128 256 128 192
WIRE 208 256 208 208
WIRE -384 272 -384 256
WIRE 208 272 208 256
WIRE 304 304 304 176
WIRE 304 304 144 304
WIRE -16 336 -16 320
WIRE 48 336 48 320
WIRE -16 384 -16 336
WIRE 48 384 48 336
WIRE 144 400 144 304
WIRE 176 400 144 400
WIRE 288 400 256 400
WIRE 320 400 288 400
WIRE 432 400 432 176
WIRE 432 400 400 400
WIRE 288 448 288 400
WIRE 288 544 288 528
SYMBOL current 288 528 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMBOL Opamps\\ADA4077-2 -384 112 R0
WINDOW 3 15 -10 Left 2
SYMATTR InstName U2
SYMBOL res 352 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 112 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 128 256 0
FLAG -16 208 0
FLAG -16 336 VEE
FLAG 48 336 VCC
FLAG 208 112 VCC
FLAG 208 256 VEE
FLAG 288 544 0
FLAG -464 256 0
FLAG -384 112 VCC
FLAG -384 256 VEE
FLAG -304 176 VOUT
* Z:\tmp\asc_dec_bjh7r6w2\008583889490_4_2_1_b_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Ri N004 0 10k
V1 N004 0 AC 15mV
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 32 192 32
WIRE 256 64 144 64
WIRE 256 96 256 64
WIRE 192 112 192 32
WIRE 224 112 192 112
WIRE 384 128 288 128
WIRE 112 144 80 144
WIRE 224 144 112 144
WIRE 112 176 112 144
WIRE 192 176 192 112
WIRE 256 272 256 160
SYMBOL res 96 160 R0
SYMATTR InstName Ri
SYMATTR Value 10k
SYMBOL voltage 96 144 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 60 56 VTop 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 15mV
FLAG 192 256 0
FLAG 112 256 0
FLAG 64 64 0
FLAG 0 144 0
* Z:\tmp\asc_dec_bjh7r6w2\137c63cc823d_LTC6101_AC_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 OUT 0 5K
R1 N002 N001 .1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 96 -64 96
WIRE 256 96 144 96
WIRE 336 96 256 96
WIRE 400 96 336 96
WIRE 256 112 256 96
WIRE -32 208 -64 208
WIRE 256 208 256 192
WIRE 256 208 224 208
WIRE 336 320 336 96
WIRE 336 320 224 320
WIRE 272 480 224 480
WIRE 272 496 272 480
WIRE 272 592 272 576
SYMBOL res 256 480 R0
SYMATTR InstName R3
SYMATTR Value 5K
SYMBOL res 160 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value .1
FLAG 272 592 0
FLAG 272 480 OUT
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2301.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2301.asy)
R1 OUT N003 69.8K
V1 IN 0 12
C2 N001 N002 100n
Rload OUT 0 15
C1 OUT 0 10
L1 N002 OUT 6.8 Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
XU1 IN IN N001 N002 N003 0 ADP2300_1 FREQ=1 CSGain=0.25 ;pnba Vin)EN)BST)SW)FB)GND
D1 0 N002 MBRS340
R2 N003 0 13.3K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib ADP2300_1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1000 692
WIRE 128 48 16 48
WIRE 160 48 128 48
WIRE 448 48 416 48
WIRE 16 64 16 48
WIRE 448 80 448 48
WIRE 16 160 16 144
WIRE 128 176 128 48
WIRE 160 176 128 176
WIRE 448 176 448 144
WIRE 448 176 416 176
WIRE 544 176 448 176
WIRE 672 176 624 176
WIRE 768 176 672 176
WIRE 912 176 768 176
WIRE 448 192 448 176
WIRE 672 192 672 176
WIRE 912 192 912 176
WIRE 768 208 768 176
WIRE 448 272 448 256
WIRE 672 272 672 256
WIRE 912 288 912 272
WIRE 160 304 128 304
WIRE 768 304 768 288
WIRE 768 304 416 304
WIRE 768 320 768 304
WIRE 768 416 768 400
SYMBOL cap 432 80 R0
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL ind 528 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 6.8
SYMATTR SpiceLine Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
SYMBOL ADP2301 288 176 R0
SYMATTR InstName U1
SYMBOL res 752 192 R0
SYMATTR InstName R1
SYMATTR Value 69.8K
SYMBOL res 752 304 R0
SYMATTR InstName R2
SYMATTR Value 13.3K
SYMBOL res 896 176 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL schottky 432 256 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 656 192 R0
WINDOW 0 29 15 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL VOLTAGE 16 48 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 16 160 0
FLAG 16 48 IN
FLAG 672 272 0
FLAG 912 176 OUT
FLAG 128 304 0
FLAG 448 272 0
FLAG 768 416 0
FLAG 912 288 0
TEXT 520 384 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\083b5bdf29c2_Diff_Schmitt.asc
* Generated by LTspice 26.0.1 for Windows.
* Diff. Sch,itt-Trigger\nPlot V(vp,vn) and V(out)\n \nThreshholds Vt+Vh, Vt-Vh\nExample Vt=1, Vh=0.4\nOutput switches to high at (vp-vn) = 1V+0.4V = 1.4V\nOutput switches to low at (vp-vn) = 1V-0.4V = 0.6V\n \nRightClick on the symbol body to see where vt and vh is set\nAny of the attribute lines Value, Value2, SpiceLine, SpiceLine2 is ok.
A1 VP VN 0 0 0 0 out 0 SCHMITT vt=1 vh=0.4
V1 VN 0 SINE(0 1 1kHz 0 0 180) AC 1
V3 VP 0 SINE(0 1 1kHz) AC 1
.tran 0 2m 0 1u
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1208 904
WIRE -272 224 -272 192
WIRE -272 336 -272 304
WIRE -272 416 -272 384
WIRE -272 528 -272 496
WIRE -256 192 -272 192
WIRE -256 384 -272 384
WIRE 32 384 -256 384
WIRE 32 384 32 224
WIRE 112 192 -256 192
WIRE 112 224 32 224
WIRE 240 192 176 192
IOPIN 240 192 Out
SYMBOL voltage -272 208 R0
WINDOW 3 39 57 Left 0
WINDOW 123 39 83 Left 0
WINDOW 39 24 44 Left 0
SYMATTR Value SINE(0 1 1kHz)
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMBOL voltage -272 400 R0
WINDOW 3 39 57 Left 0
WINDOW 123 39 83 Left 0
WINDOW 39 24 44 Left 0
SYMATTR Value SINE(0 1 1kHz 0 0 180)
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL Digital\\diffschmitt 112 144 R0
WINDOW 123 2 118 Left 0
SYMATTR InstName A1
SYMATTR Value2 vt=1 vh=0.4
FLAG -256 192 VP
FLAG -272 336 0
FLAG -256 384 VN
FLAG -272 528 0
FLAG 240 192 out
TEXT -280 56 Left 0 !.tran 0 2m 0 1u
TEXT -280 80 Left 0 !.options plotwinsize=0
TEXT -272 -240 Left 0 ;Diff. Sch,itt-Trigger\nPlot V(vp,vn)  and V(out)\n \nThreshholds Vt+Vh, Vt-Vh\nExample Vt=1, Vh=0.4\nOutput switches to high at (vp-vn) = 1V+0.4V = 1.4V\nOutput switches to low at (vp-vn) = 1V-0.4V = 0.6V\n \nRightClick on the symbol body to see where vt and vh is set\nAny of the attribute lines Value, Value2, SpiceLine, SpiceLine2 is ok.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1085-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1085-5.asy)
Rload OUT 0 10
C1 OUT 0 10
XU1 0 OUT IN LT1085-5 ;pnba GND)OUT)IN
V1 IN 0 PWL(0 0 1 10) Rser=0.1
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1952 896 1808 896
WIRE 2064 896 1952 896
WIRE 1344 912 1344 896
WIRE 1952 912 1952 896
WIRE 2064 912 2064 896
WIRE 1344 1008 1344 992
WIRE 1952 1008 1952 976
WIRE 2064 1008 2064 992
WIRE 1680 1024 1680 992
SYMBOL PowerProducts\\LT1085-5 1680 896 R0
SYMATTR InstName U1
SYMBOL cap 1936 912 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
SYMBOL RES 2048 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 2064 896 OUT
FLAG 2064 1008 0
FLAG 1344 1008 0
FLAG 1952 1008 0
FLAG 1344 896 IN
FLAG 1680 1024 0
TEXT 1968 1088 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADTL084.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADTL084.asy)
V1 +V 0 15
XU1 IN N001 +V -V OUT ADTL084 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -15
Rload OUT 0 10K
R1 N001 0 10K
R2 OUT N001 10K
Vin IN 0 SINE(0 1 10K)
.tran 1m
.lib ADTL084.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 720 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 720 -1088 720 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 720 -992 720 -1008
WIRE 432 -976 432 -992
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL opamps\\ADTL084 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 704 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 720 -992 0
FLAG 256 -1056 0
TEXT 784 -896 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6228.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
V2 -V 0 -5
XU1 N005 N001 N002 +V -V +V LTC6228 ;pnba IN+)IN-)OUT)VCC)VEE)SHDN_L
R2 OUT N002 49.9
C1 N002 N001 18p
R1 N002 N001 200
R3 N001 N004 348
R4 N004 N003 49.9
C2 N004 N007 18p
R5 N007 N006 49.9
R6 N005 N007 150
R7 0 N005 101
V3 N003 N006 AC 1
.ac oct 8 100K 200Meg
* Differential to Single-Ended Converter
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6228.asy)
.lib LTC6228.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4472 1028
WIRE -2592 -624 -2688 -624
WIRE -2464 -624 -2528 -624
WIRE -3136 -528 -3136 -544
WIRE -2976 -528 -2976 -544
WIRE -2688 -512 -2688 -624
WIRE -2608 -512 -2688 -512
WIRE -2464 -512 -2464 -624
WIRE -2464 -512 -2528 -512
WIRE -3136 -432 -3136 -448
WIRE -2976 -432 -2976 -448
WIRE -2592 -400 -2592 -416
WIRE -2960 -352 -3024 -352
WIRE -2848 -352 -2880 -352
WIRE -2816 -352 -2848 -352
WIRE -2688 -352 -2688 -512
WIRE -2688 -352 -2736 -352
WIRE -2624 -352 -2688 -352
WIRE -2464 -320 -2464 -512
WIRE -2464 -320 -2480 -320
WIRE -2448 -320 -2464 -320
WIRE -2352 -320 -2368 -320
WIRE -3024 -304 -3024 -352
WIRE -2848 -304 -2848 -352
WIRE -2624 -288 -2720 -288
WIRE -2592 -224 -2592 -240
WIRE -2544 -224 -2544 -240
WIRE -3024 -160 -3024 -224
WIRE -2960 -160 -3024 -160
WIRE -2848 -160 -2848 -240
WIRE -2848 -160 -2880 -160
WIRE -2816 -160 -2848 -160
WIRE -2720 -160 -2720 -288
WIRE -2720 -160 -2736 -160
WIRE -2688 -160 -2720 -160
WIRE -2576 -160 -2608 -160
WIRE -2576 -128 -2576 -160
FLAG -3136 -432 0
FLAG -2976 -432 0
FLAG -3136 -544 +V
FLAG -2976 -544 -V
FLAG -2352 -320 OUT
FLAG -2576 -128 0
FLAG -2592 -416 +V
FLAG -2544 -224 +V
FLAG -2592 -224 -V
SYMBOL voltage -3136 -544 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -2976 -544 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL LTC6228 -2592 -320 R0
SYMATTR InstName U1
SYMBOL res -2352 -336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 49.9
SYMBOL cap -2528 -640 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 18p
SYMBOL res -2512 -528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL res -2720 -368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 348
SYMBOL res -2864 -368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 49.9
SYMBOL cap -2864 -304 R0
SYMATTR InstName C2
SYMATTR Value 18p
SYMBOL res -2864 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 49.9
SYMBOL res -2720 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 150
SYMBOL res -2592 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 101
SYMBOL voltage -3024 -320 R0
WINDOW 123 19 102 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value ""
TEXT -2424 -136 Left 2 !.ac oct 8 100K 200Meg
TEXT -2944 -624 Bottom 2 ;Differential to Single-Ended Converter