Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\02aa51ef5066_B.asc
* Generated by LTspice 26.0.1 for Windows.
VEE N003 0 -5
RL Vo N003 10k
Q1 Vo Vin N001 0 My2n3906
Q2 Vin Vin N001 0 My2n3906
VCC N001 0 5
IREF Vin N003 0.000091 AC 0
C1 Vo N002 100T
V2 N002 N003 0 AC 0.000001 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
* X3
.MODEL My2n3906 pnp
+IS=7.75521e-12 BF=194.093 NF=1.35509 VAF=156.436
+IKF=0.0660057 ISE=1.88546e-12 NE=1.81673 BR=3.41317
+NR=1.5 VAR=5.86061 IKR=1.70599 ISC=7.64281e-10
+NC=1.92376 RB=6.48961 IRB=0.1 RBM=0.1
+RE=0.0001 RC=2.45044 XTB=0.1 XTI=1
+EG=1.05 CJE=6.11928e-12 VJE=0.4 MJE=0.248812
+TF=5.21843e-10 XTF=0.932702 VTF=9.1046 ITF=0.0106472
+CJC=6.85007e-12 VJC=0.4 MJC=0.279018 XCJC=0.9
+FC=0.478887 CJS=0 VJS=0.75 MJS=0.5
+TR=4.30605e-07 PTF=0 KF=0 AF=1
* X2
;dc IREF 0.000085 0.000095 0.0000001
.ac lin 11 100 200
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1424 680
WIRE -32 -576 -608 -576
WIRE 384 -576 -32 -576
WIRE 384 -464 384 -576
WIRE -608 -320 -608 -576
WIRE -32 -320 -32 -576
WIRE 384 -304 384 -384
WIRE -336 -272 -544 -272
WIRE -96 -272 -336 -272
WIRE -32 -192 -32 -224
WIRE 160 -192 -32 -192
WIRE 160 -128 160 -192
WIRE -608 -112 -608 -224
WIRE -336 -112 -336 -272
WIRE -336 -112 -608 -112
WIRE -32 -112 -32 -192
WIRE -608 -64 -608 -112
WIRE -608 48 -608 -64
WIRE -32 48 -32 -112
WIRE 160 48 160 -64
WIRE -608 208 -608 128
WIRE -32 208 -32 128
WIRE -32 208 -608 208
WIRE -32 240 -32 208
WIRE 160 240 160 128
WIRE 160 240 -32 240
WIRE -32 304 -32 240
WIRE -32 448 -32 384
FLAG -32 448 0
FLAG 384 -304 0
FLAG -32 -112 Vo
FLAG -608 -64 Vin
SYMBOL voltage -32 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VEE
SYMATTR Value -5
SYMBOL res -48 32 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL pnp -96 -224 M180
SYMATTR InstName Q1
SYMATTR Value My2n3906
SYMBOL pnp -544 -224 R180
SYMATTR InstName Q2
SYMATTR Value My2n3906
SYMBOL voltage 384 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCC
SYMATTR Value 5
SYMBOL current -608 48 R0
WINDOW 3 24 28 Left 2
WINDOW 123 24 56 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName IREF
SYMATTR Value 0.000091
SYMATTR Value2 AC 0
SYMBOL cap 144 -128 R0
SYMATTR InstName C1
SYMATTR Value 100T
SYMBOL voltage 160 32 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMATTR Value2 AC 0.000001 0
TEXT 336 -320 Left 2 ;X3
TEXT 696 -536 Left 2 !.MODEL My2n3906 pnp\n+IS=7.75521e-12 BF=194.093 NF=1.35509 VAF=156.436\n+IKF=0.0660057 ISE=1.88546e-12 NE=1.81673 BR=3.41317\n+NR=1.5 VAR=5.86061 IKR=1.70599 ISC=7.64281e-10\n+NC=1.92376 RB=6.48961 IRB=0.1 RBM=0.1\n+RE=0.0001 RC=2.45044 XTB=0.1 XTI=1\n+EG=1.05 CJE=6.11928e-12 VJE=0.4 MJE=0.248812\n+TF=5.21843e-10 XTF=0.932702 VTF=9.1046 ITF=0.0106472\n+CJC=6.85007e-12 VJC=0.4 MJC=0.279018 XCJC=0.9\n+FC=0.478887 CJS=0 VJS=0.75 MJS=0.5\n+TR=4.30605e-07 PTF=0 KF=0 AF=1
TEXT -72 432 Left 2 ;X2
TEXT -752 424 Left 2 !;dc IREF 0.000085 0.000095 0.0000001
TEXT 440 -96 Left 2 !.ac lin 11 100 200
* Z:\home\khalils\Downloads\files\data\raw_asc\00ccec2cdc4e_2641A-16.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N005 0 PULSE(0 3.3 0 0.1n 0.1n 19.8n 40n)
V2 N002 0 5
V3 N003 0 2.5
V4 N004 0 PULSE(0 3.3 0 0.1n 0.1n 9.9n 20n)
V5 N001 0 PWL(0 3.3 0.6u 3.3 +2n 0 +0.31u 0 +2n 3.3)
V6 N006 0 PWL(0 3.3 2u 3.3 +2n 0 +30n 0 +2n 3.3)
C1 OUT 0 10p
XU1 N003 N001 N004 N005 N006 OUT N002 0 LTC2641A-16 ;pnba REF)_CS)SCLK)DIN)_CLR)Vout)Vdd)GND
.tran 3u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC2641A-16.asy)
.lib LTC2641A-16.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 932
WIRE 320 16 320 -16
WIRE 448 16 448 -16
WIRE -32 64 -48 64
WIRE 192 64 48 64
WIRE 320 128 320 96
WIRE 448 128 448 96
WIRE 192 176 192 64
WIRE 240 176 192 176
WIRE -32 192 -48 192
WIRE 160 192 48 192
WIRE 160 240 160 192
WIRE 240 240 160 240
WIRE 608 272 528 272
WIRE 608 288 608 272
WIRE -32 304 -48 304
WIRE 240 304 48 304
WIRE 240 368 176 368
WIRE 608 368 608 352
WIRE 384 416 384 400
WIRE -32 448 -48 448
WIRE 176 448 176 368
WIRE 176 448 48 448
FLAG 384 416 0
FLAG -48 304 0
FLAG 320 -16 0
FLAG 448 -16 0
FLAG -48 192 0
FLAG -48 64 0
FLAG -48 448 0
FLAG 608 272 OUT
FLAG 608 368 0
SYMBOL voltage 64 304 R90
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 -49 44 VRight 2
WINDOW 3 46 -99 VRight 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0 0.1n 0.1n 19.8n 40n)
SYMBOL voltage 320 112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 448 112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 2.5
SYMBOL voltage 64 192 R90
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 -49 44 VRight 2
WINDOW 3 46 -89 VRight 2
SYMATTR InstName V4
SYMATTR Value PULSE(0 3.3 0 0.1n 0.1n 9.9n 20n)
SYMBOL voltage 64 64 R90
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 -49 44 VRight 2
WINDOW 3 46 -122 VRight 2
SYMATTR InstName V5
SYMATTR Value PWL(0 3.3 0.6u 3.3 +2n 0 +0.31u 0 +2n 3.3)
SYMBOL voltage 64 448 R90
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 -49 44 VRight 2
WINDOW 3 46 -99 VRight 2
SYMATTR InstName V6
SYMATTR Value PWL(0 3.3 2u 3.3 +2n 0 +30n 0 +2n 3.3)
SYMBOL cap 592 288 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL LTC2641A-16 384 272 R0
SYMATTR InstName U1
TEXT 632 432 Left 2 !.tran 3u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1402.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vS 0 10
R1 vD 0 301
V2 vIN 0 PULSE(3 0 0 1u 1u 5m 10m)
V4 v- 0 -15
V3 v+ 0 15
XU1 v+ v- vIN vS vD 0 ADG1402 ;pnba Vdd)Vss)IN)S)D)GND
.tran 30m
* Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 15V dual supply\nPin Capacitance not included
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1402.asy)
.lib ADG1402.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 936 832
WIRE 240 160 240 96
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 464 256 464 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -320 336 -320 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 288 448 288 400
WIRE -320 464 -320 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
WIRE 192 464 192 400
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 288 448 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG -192 304 v-
FLAG 240 96 v+
FLAG -192 464 0
FLAG 192 464 v-
FLAG -320 304 v+
FLAG -320 464 0
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -20 198 Left 2
SYMATTR Value PULSE(3 0 0 1u 1u 5m 10m)
SYMATTR InstName V2
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL voltage -320 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL ADG1402 240 272 R0
SYMATTR InstName U1
TEXT 440 512 Left 2 !.tran 30m
TEXT -360 -16 Left 2 ;Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 15V dual supply\nPin Capacitance not included
* Z:\home\khalils\Downloads\files\data\raw_asc\2fdf4fe4a2d7_circuito_extremos.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N003 0 SINE(0 1 1k) Rser=50
V4 0 - 10
R3 0 N002 330
V3 + 0 10
V2 N004 0 SINE(0 1 1k) AC 0 Rser=50
R11 N001 N003 1Meg
XU1 0 N001 + - Out LMX24_LM2902 ;pnba In+)In-)V+)V-)OUT
R2 Out N002 100k
R12 N001 N004 1Meg
R1 N002 N001 100k
.include LM324.lib
.tran 0 4m 0 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1556 1528
WIRE 16 -64 -16 -64
WIRE 128 -64 96 -64
WIRE 160 -64 128 -64
WIRE 256 -64 240 -64
WIRE 928 -64 928 -96
WIRE 1024 -64 928 -64
WIRE 128 -48 128 -64
WIRE 1024 -48 1024 -64
WIRE 928 -32 928 -64
WIRE 128 48 128 32
WIRE -160 96 -304 96
WIRE -16 96 -16 -64
WIRE -16 96 -80 96
WIRE 160 96 -16 96
WIRE -304 112 -304 96
WIRE 256 112 256 -64
WIRE 256 112 224 112
WIRE 288 112 256 112
WIRE 160 128 128 128
WIRE -160 160 -208 160
WIRE -16 160 -16 96
WIRE -16 160 -80 160
WIRE -208 176 -208 160
WIRE -304 224 -304 192
WIRE 128 272 128 128
WIRE -208 304 -208 256
IOPIN 288 112 Out
SYMBOL res -64 80 R90
WINDOW 0 -24 59 VBottom 2
WINDOW 3 -3 54 VBottom 2
SYMATTR InstName R11
SYMATTR Value 1Meg
SYMBOL res 256 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL res -64 144 R90
WINDOW 0 55 37 VBottom 2
WINDOW 3 85 30 VBottom 2
SYMATTR InstName R12
SYMATTR Value 1Meg
SYMBOL res 112 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL voltage 928 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL voltage -304 96 R0
WINDOW 3 -129 143 Left 2
WINDOW 123 -129 143 Left 2
WINDOW 39 -129 115 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
SYMATTR SpiceLine Rser=50
SYMBOL res 144 48 R180
WINDOW 0 43 45 Left 2
WINDOW 3 33 17 Left 2
SYMATTR InstName R3
SYMATTR Value 330
SYMBOL voltage -208 160 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 180 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 1 1k)
SYMATTR Value2 AC 0
SYMATTR SpiceLine Rser=50
SYMBOL OpAmps\\opamp2 192 48 R0
SYMATTR InstName U1
SYMATTR Value LMX24_LM2902
SYMBOL voltage 928 -192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
FLAG 288 112 Out
FLAG 192 80 +
FLAG 192 144 -
FLAG 928 -176 +
FLAG -304 224 0
FLAG -208 304 0
FLAG 1024 -48 0
FLAG 128 48 0
FLAG 128 272 0
FLAG 928 48 -
TEXT 816 -240 Left 2 !.include LM324.lib
TEXT -432 368 Left 2 !.tran 0 4m 0 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG711.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 5V single supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG711.asy)
V2 vIN 0 PULSE(0 3 0 10n 10n 980n 2u)
V1 vS 0 3
XU1 v+ vS vD vIN 0 ADG711 ;pnba Vdd)S)D)IN)GND
C1 vD 0 36p
R1 vD 0 301
V3 v+ 0 5
.tran 10u
.lib ADG711.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 112 240 112
WIRE 240 160 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -176 304 -192 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE 240 432 240 400
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL ADG711 240 272 R0
SYMATTR InstName U1
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 240 432 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -192 304 v+
FLAG 240 112 v+
FLAG -192 464 0
TEXT 336 424 Left 2 !.tran 10u
TEXT -360 -16 Left 2 ;Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 5V single supply\nOny one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\3f9dfa2b91a4_1013.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1013.asy)
R1 N002 N001 50K
XU1 N003 N001 +V -V N002 LT1013 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
V3 N003 0 sine(0 .5 10K)
V2 -V 0 -15
R2 N001 0 5K
.tran 1m
.lib LT1013.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1028 680
WIRE 192 0 176 0
WIRE 288 0 272 0
WIRE 352 0 288 0
WIRE 448 0 432 0
WIRE -80 64 -80 48
WIRE 32 64 32 48
WIRE 336 96 336 80
WIRE 288 112 288 0
WIRE 304 112 288 112
WIRE 448 128 448 0
WIRE 448 128 368 128
WIRE 304 144 160 144
WIRE -80 160 -80 144
WIRE 32 160 32 144
WIRE 160 160 160 144
WIRE 336 176 336 160
WIRE 160 256 160 240
SYMBOL res 448 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50K
SYMBOL opamps\\LT1013 336 64 R0
SYMATTR InstName U1
SYMBOL voltage 160 144 R0
SYMATTR InstName V3
SYMATTR Value sine(0 .5 10K)
SYMBOL res 288 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 5K
SYMBOL voltage 32 48 R0
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -80 48 R0
WINDOW 39 24 125 Left 2
SYMATTR InstName V1
SYMATTR Value 15
FLAG -80 160 0
FLAG 336 80 +V
FLAG -80 48 +V
FLAG 176 0 0
FLAG 160 256 0
FLAG 32 160 0
FLAG 32 48 -V
FLAG 336 176 -V
TEXT 384 240 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\2660db64d82c_ADA4177.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4177.asy)
R2 OUT N001 10K
Vin IN 0 SINE(0 1 10K)
V2 -V 0 -15
R1 N001 0 10K
XU1 IN N001 +V -V OUT ADA4177 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
.tran 1m
.lib ADA4177.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 512 -1232 496 -1232
WIRE 544 -1232 512 -1232
WIRE 656 -1232 624 -1232
WIRE 128 -1136 128 -1152
WIRE 240 -1136 240 -1152
WIRE 512 -1120 512 -1232
WIRE 544 -1120 512 -1120
WIRE 656 -1104 656 -1232
WIRE 656 -1104 608 -1104
WIRE 720 -1104 656 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 128 -1040 128 -1056
WIRE 240 -1040 240 -1056
WIRE 432 -976 432 -992
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL OpAmps\\ADA4177 576 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 128 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 240 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
FLAG 128 -1152 +V
FLAG 128 -1040 0
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 240 -1152 -V
FLAG 576 -1072 -V
FLAG 400 -1232 0
FLAG 240 -1040 0
TEXT 704 -992 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1981.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1981.asy)
XU1 N002 0 N003 N004 N001 LTC1981 ;pnba GDR)GND)_SHDN)Gate)Vcc
V1 N001 0 3.3
MQ1 N001 N004 N005 N005 Si4838DY
R2 N001 N002 100K
V2 N003 0 PULSE(0 3 0 100n 100n 2.5m 5m)
R1 0 N005 10
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
.lib LTC1981.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 336 0 -48 0
WIRE -48 16 -48 0
WIRE -48 112 -48 96
WIRE 32 112 -48 112
WIRE 336 112 336 0
WIRE 336 112 256 112
WIRE 544 112 336 112
WIRE 544 128 544 112
WIRE 32 192 0 192
WIRE 336 192 336 112
WIRE 544 224 544 208
WIRE 32 272 -176 272
WIRE 288 272 256 272
WIRE -176 288 -176 272
WIRE 336 320 336 288
WIRE -176 384 -176 368
WIRE 336 416 336 400
SYMBOL voltage 544 112 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL nmos 288 192 R0
WINDOW 3 53 80 Left 2
SYMATTR Value Si4838DY
SYMATTR InstName Q1
SYMBOL LTC1981 144 192 R0
SYMATTR InstName U1
SYMBOL res -64 0 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 352 416 R180
WINDOW 0 -35 89 Left 2
WINDOW 3 -33 43 Left 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage -176 272 R0
SYMATTR Value PULSE(0 3 0 100n 100n 2.5m 5m)
SYMATTR InstName V2
FLAG 544 224 0
FLAG 0 192 0
FLAG -176 384 0
FLAG 336 416 0
TEXT 440 352 Left 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\6a790f9cfc78_nand.asc
* Generated by LTspice 26.0.1 for Windows.
V1 a 0 PULSE(0 1 0 0.1n 0.1n 10n 20n)
V3 b 0 PULSE(0 1 0 0.1n 0.1n 5n 10n)
V2 N001 0 1
M2 N002 b 0 0 NMOS l=200n w=200n
M3 N001 a out N001 PMOS l=200n w=400n
M4 N001 b out N001 PMOS l=200n w=400n
M1 out a N002 0 NMOS l=200n w=200n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib /Users/young/Documents/LTspice/90nm_bulk.pm
.tran 0 30n 0 0.1n
.meas TRAN tr TRIG v(in)=0.5 FALL=3 TARG v(out)=0.5 RISE=2
.meas TRAN tf TRIG v(in)=0.5 FALL=2 TARG v(out)=0.5 RISE=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1244 680
WIRE 272 -32 128 -32
WIRE 496 -32 272 -32
WIRE 640 -32 496 -32
WIRE 960 -32 640 -32
WIRE 272 16 272 -32
WIRE 272 16 128 16
WIRE 640 16 640 -32
WIRE 640 16 496 16
WIRE 448 96 448 48
WIRE 448 96 224 96
WIRE 960 128 960 -32
WIRE 128 176 128 64
WIRE 304 176 128 176
WIRE 496 176 496 64
WIRE 496 176 304 176
WIRE 704 176 496 176
WIRE 304 224 304 176
WIRE -208 272 -304 272
WIRE 80 272 80 48
WIRE 80 272 -208 272
WIRE 192 272 80 272
WIRE 432 272 304 272
WIRE -208 304 -208 272
WIRE 192 304 192 272
WIRE 256 304 192 304
WIRE -208 384 -416 384
WIRE 304 400 304 320
WIRE -208 448 -304 448
WIRE 224 448 224 96
WIRE 224 448 -208 448
WIRE 256 448 224 448
WIRE 432 448 432 272
WIRE 432 448 304 448
WIRE -208 464 -208 448
WIRE 256 480 256 448
WIRE 304 544 304 496
WIRE 304 544 224 544
WIRE 432 544 432 448
WIRE 432 544 304 544
WIRE 960 544 960 208
WIRE 960 544 432 544
WIRE 304 560 304 544
WIRE -416 608 -416 384
WIRE -208 608 -208 544
WIRE -208 608 -416 608
WIRE 224 608 224 544
WIRE 224 608 -208 608
IOPIN 704 176 Out
IOPIN -304 272 In
IOPIN -304 448 In
SYMBOL pmos4 80 -32 R0
SYMATTR InstName M3
SYMATTR Value2 l=200n w=400n
SYMBOL voltage -208 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0.1n 0.1n 10n 20n)
SYMBOL nmos4 256 224 R0
SYMATTR InstName M1
SYMATTR Value2 l=200n w=200n
SYMBOL voltage 960 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL voltage -208 448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 0 0.1n 0.1n 5n 10n)
SYMBOL nmos4 256 400 R0
SYMATTR InstName M2
SYMATTR Value2 l=200n w=200n
SYMBOL pmos4 448 -32 R0
SYMATTR InstName M4
SYMATTR Value2 l=200n w=400n
FLAG 704 176 out
FLAG -304 272 a
FLAG -304 448 b
FLAG 304 560 0
TEXT 544 312 Left 2 !.lib /Users/young/Documents/LTspice/90nm_bulk.pm
TEXT 552 360 Left 2 !.tran 0 30n 0 0.1n
TEXT 560 416 Left 2 !.meas TRAN tr TRIG v(in)=0.5 FALL=3 TARG v(out)=0.5 RISE=2
TEXT 560 456 Left 2 !.meas TRAN tf TRIG v(in)=0.5 FALL=2 TARG v(out)=0.5 RISE=1
* Z:\home\khalils\Downloads\files\data\raw_asc\8a6fc8eb1f84_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD712.asy)
V2 -V 0 -15
Vin2 IN2 0 1
R3 N002 0 10k
V1 +V 0 15
R4 N002 IN2 10k
Vin1 IN1 0
R2 N001 IN1 10k
XU1 N002 N001 +V -V OUT AD712 ;pnba In+)In-)V+)V-)OUT
R1 N001 OUT 100k
.dc Vin1 -3 3 0.5 Vin2 -1 1 1
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 208 -96 176 -96
WIRE -288 0 -304 0
WIRE -192 0 -208 0
WIRE -128 0 -192 0
WIRE 96 0 96 -96
WIRE 96 0 -48 0
WIRE 112 0 96 0
WIRE 208 16 208 -96
WIRE 208 16 176 16
WIRE 256 16 208 16
WIRE 400 16 400 0
WIRE 512 16 512 0
WIRE 80 32 -32 32
WIRE 112 32 80 32
WIRE 80 64 80 32
WIRE -304 96 -320 96
WIRE -160 96 -224 96
WIRE -112 96 -160 96
WIRE -32 96 -32 32
WIRE 400 112 400 96
WIRE 512 112 512 96
SYMBOL AD712 144 -48 R0
SYMATTR InstName U1
SYMBOL res 64 48 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL voltage -208 96 R90
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
WINDOW 3 24 44 Left 2
SYMATTR InstName Vin2
SYMATTR Value 1
SYMBOL voltage 400 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res -32 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 512 0 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -192 0 R90
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin1
SYMATTR Value ""
SYMBOL res -16 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res 80 -112 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
FLAG -304 0 0
FLAG 256 16 OUT
FLAG -192 0 IN1
FLAG 144 -16 +V
FLAG 144 48 -V
FLAG 80 144 0
FLAG 400 0 +V
FLAG 400 112 0
FLAG 512 0 -V
FLAG 512 112 0
FLAG -320 96 0
FLAG -160 96 IN2
TEXT -40 208 Left 2 !.dc Vin1 -3 3 0.5 Vin2 -1 1 1
* Z:\home\khalils\Downloads\files\data\raw_asc\22f8ec86cddd_Fig16_66.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot -I(VGS)
VGS VGS 0 1
M1 N001 VGS N002 0 N_50n l=50n w=500n
VDD N001 0 1
R1 N002 0 1G
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.dc VGS 0 2 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1748 680
WIRE 384 -128 384 -144
WIRE 384 -96 384 -128
WIRE 384 16 384 -16
WIRE 576 -144 384 -144
WIRE 624 -224 624 -256
WIRE 624 -96 624 -128
WIRE 624 16 624 -16
WIRE 704 -256 624 -256
WIRE 848 -256 784 -256
WIRE 848 -192 848 -256
SYMBOL voltage 688 -256 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL res 608 -112 R0
SYMATTR InstName R1
SYMATTR Value 1G
SYMBOL voltage 384 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Invisible 0
WINDOW 0 39 62 Left 0
SYMATTR Value 1
SYMATTR InstName VGS
SYMBOL nmos4 576 -224 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
WINDOW 123 -114 111 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
FLAG 624 -176 0
FLAG 384 16 0
FLAG 384 -128 VGS
FLAG 848 -192 0
FLAG 624 16 0
TEXT 368 80 Left 0 !.lib cmosedu_models.txt
TEXT 368 56 Left 0 !.dc VGS 0 2 1m
TEXT 416 -264 Left 0 ;Plot -I(VGS)