* Z:\home\khalils\Downloads\files\data\raw_asc\cc759fa430f5_Real_Assignment.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc VIN -0.1 0.1 0.00001
* .tran 5m
* .ac dec 100 1 1g
* DC Source
* Current Mirror Circuit
* Differential Amplifier
* Input Signal
* Common Source Stage
* Common Drain Stage
* Load
C1 V3 N005 3p
M2 V1 0 N003 N003 tsmc018n l=0.18u w=3u
M4 V1 N002 N001 N001 tsmc018p l=0.18u w=50u
M9 V3 N004 N005 N005 tsmc018n l=0.18u w=18u
R2 V2 N005 8k
VIN VIN 0 SINE(0 5m 1k) AC 1
VDD1 N001 0 0.9
M7 V2 V1 N001 N001 tsmc018p l=0.18u w=18u
M3 N002 N002 N001 N001 tsmc018p l=0.18u w=50u
R1 N001 N004 10k
ROUT V3 N005 30
M8 N001 V2 V3 V3 tsmc018n l=0.18u w=1800u
M1 N002 VIN N003 N003 tsmc018n l=0.18u w=3u
M5 N003 N004 N005 N005 tsmc018n l=0.18u w=1800u
VDD2 0 N005 0.9
M6 N004 N004 N005 N005 tsmc018n l=0.18u w=18u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib "C:\Users\User\OneDrive - Asia Pacific University\Documents\Y4 Sem1\Analogue Integrated Circuits and Systems\Topology\TSMC_models.txt"
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2292 1124
WIRE 48 64 -320 64
WIRE 592 64 48 64
WIRE 912 64 592 64
WIRE 1360 64 912 64
WIRE 1744 64 1360 64
WIRE 592 208 592 64
WIRE 592 208 480 208
WIRE 912 208 912 64
WIRE 1024 208 912 208
WIRE -320 240 -320 64
WIRE 592 240 592 208
WIRE 912 240 912 208
WIRE 752 256 640 256
WIRE 864 256 752 256
WIRE 480 288 480 208
WIRE 592 288 480 288
WIRE 1024 288 1024 208
WIRE 1024 288 912 288
WIRE 1360 288 1360 64
WIRE 1424 288 1360 288
WIRE 1360 352 1360 288
WIRE 912 368 912 336
WIRE 1312 368 912 368
WIRE 592 400 592 336
WIRE 752 400 752 256
WIRE 752 400 592 400
WIRE 1424 400 1424 288
WIRE 1424 400 1360 400
WIRE 48 416 48 64
WIRE 912 416 912 368
WIRE 1744 416 1744 64
WIRE 1808 464 1744 464
WIRE -320 480 -320 320
WIRE -320 480 -400 480
WIRE 592 480 592 400
WIRE 912 480 912 416
WIRE 1360 496 1360 448
WIRE 1696 496 1360 496
WIRE -400 528 -400 480
WIRE 672 528 592 528
WIRE 912 528 832 528
WIRE 1744 544 1744 512
WIRE 1808 544 1808 464
WIRE 1808 544 1744 544
WIRE 544 560 464 560
WIRE 976 560 960 560
WIRE 976 592 976 560
WIRE 1744 592 1744 544
WIRE 2064 592 1744 592
WIRE 464 608 464 560
WIRE 592 608 592 576
WIRE 672 608 672 528
WIRE 672 608 592 608
WIRE 832 608 832 528
WIRE 912 608 912 576
WIRE 912 608 832 608
WIRE 592 656 592 608
WIRE 752 656 592 656
WIRE 912 656 912 608
WIRE 912 656 752 656
WIRE 2064 688 2064 592
WIRE 2064 688 2016 688
WIRE 2112 688 2064 688
WIRE -320 704 -320 480
WIRE 464 720 464 688
WIRE 1360 720 1360 496
WIRE 2016 720 2016 688
WIRE 2112 720 2112 688
WIRE 1744 752 1744 592
WIRE 48 784 48 496
WIRE 208 784 48 784
WIRE 1840 800 1744 800
WIRE 1696 832 432 832
WIRE 2016 832 2016 784
WIRE 2064 832 2016 832
WIRE 2112 832 2112 800
WIRE 2112 832 2064 832
WIRE 48 848 48 784
WIRE 752 848 752 656
WIRE 1744 864 1744 848
WIRE 1840 864 1840 800
WIRE 1840 864 1744 864
WIRE 48 896 -32 896
WIRE 832 896 752 896
WIRE 208 928 208 784
WIRE 208 928 96 928
WIRE 432 928 432 832
WIRE 432 928 208 928
WIRE 704 928 432 928
WIRE 832 944 832 896
WIRE 832 944 752 944
WIRE -32 960 -32 896
WIRE 48 960 48 944
WIRE 48 960 -32 960
WIRE -320 992 -320 784
WIRE 48 992 48 960
WIRE 48 992 -320 992
WIRE 752 992 752 944
WIRE 752 992 48 992
WIRE 1360 992 1360 800
WIRE 1360 992 752 992
WIRE 1744 992 1744 864
WIRE 1744 992 1360 992
WIRE 2064 992 2064 832
WIRE 2064 992 1744 992
DATAFLAG 48 224 "I(R1)"
DATAFLAG 592 128 "Is(M3)"
DATAFLAG 912 128 "Is(M4)"
DATAFLAG 1360 192 "Is(M7)"
DATAFLAG 1744 336 "Id(M8)"
DATAFLAG 752 256 ""
DATAFLAG 608 928 ""
DATAFLAG 1136 368 ""
DATAFLAG 1552 496 ""
DATAFLAG 912 368 ""
DATAFLAG 1360 608 ""
DATAFLAG 48 784 ""
DATAFLAG 1744 688 "Id(M9)"
DATAFLAG 752 656 ""
DATAFLAG 752 752 "Id(M5)"
DATAFLAG 1856 592 ""
DATAFLAG 1584 832 ""
LINE Normal -144 1040 -144 16 2
LINE Normal 928 1040 -144 1040 2
LINE Normal 928 752 928 1040 2
LINE Normal 176 752 928 752 2
LINE Normal 176 752 176 752 2
LINE Normal 176 16 176 752 2
LINE Normal -144 16 176 16 2
RECTANGLE Normal -192 1040 -448 16 2
RECTANGLE Normal 1136 736 320 16 2
RECTANGLE Normal 1504 1040 1264 16 2
RECTANGLE Normal 2192 912 1952 624 2
RECTANGLE Normal 1872 16 1632 1040 2
SYMBOL nmos4 1696 416 R0
SYMATTR InstName M8
SYMATTR Value tsmc018n
SYMATTR Value2 l=0.18u w=1800u
SYMBOL nmos4 1696 752 R0
SYMATTR InstName M9
SYMATTR Value tsmc018n
SYMATTR Value2 l=0.18u w=18u
SYMBOL voltage -320 688 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD2
SYMATTR Value 0.9
SYMBOL nmos4 704 848 R0
SYMATTR InstName M5
SYMATTR Value tsmc018n
SYMATTR Value2 l=0.18u w=1800u
SYMBOL voltage -320 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD1
SYMATTR Value 0.9
SYMBOL res 2096 704 R0
SYMATTR InstName ROUT
SYMATTR Value 30
SYMBOL pmos4 640 336 R180
SYMATTR InstName M3
SYMATTR Value tsmc018p
SYMATTR Value2 l=0.18u w=50u
SYMBOL res 32 400 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL nmos4 96 848 M0
SYMATTR InstName M6
SYMATTR Value tsmc018n
SYMATTR Value2 l=0.18u w=18u
SYMBOL pmos4 1312 448 M180
SYMATTR InstName M7
SYMATTR Value tsmc018p
SYMATTR Value2 l=0.18u w=18u
SYMBOL nmos4 960 480 M0
SYMATTR InstName M2
SYMATTR Value tsmc018n
SYMATTR Value2 l=0.18u w=3u
SYMBOL voltage 464 592 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName VIN
SYMATTR Value SINE(0 5m 1k)
SYMBOL pmos4 864 336 M180
SYMATTR InstName M4
SYMATTR Value tsmc018p
SYMATTR Value2 l=0.18u w=50u
SYMBOL cap 2000 720 R0
SYMATTR InstName C1
SYMATTR Value 3p
SYMBOL res 1344 704 R0
SYMATTR InstName R2
SYMATTR Value 8k
SYMBOL nmos4 544 480 R0
SYMATTR InstName M1
SYMATTR Value tsmc018n
SYMATTR Value2 l=0.18u w=3u
FLAG 464 720 0
FLAG 912 416 V1
FLAG 1360 496 V2
FLAG 1744 592 V3
FLAG 464 560 VIN
FLAG 976 592 0
FLAG -400 528 0
TEXT -72 -464 Left 2 !.lib "C:\\Users\\User\\OneDrive - Asia Pacific University\\Documents\\Y4 Sem1\\Analogue Integrated Circuits and Systems\\Topology\\TSMC_models.txt"
TEXT -72 -432 Left 2 !.op
TEXT -64 -392 Left 2 ;.dc VIN -0.1 0.1 0.00001
TEXT -72 -360 Left 2 ;.tran 5m
TEXT -64 -320 Left 2 ;.ac dec 100 1 1g
TEXT -400 1080 Left 3 ;DC Source
TEXT 176 1080 Left 3 ;Current Mirror Circuit
TEXT 560 -32 Left 3 ;Differential Amplifier
TEXT 208 648 Left 3 ;Input Signal
TEXT 1184 1080 Left 3 ;Common Source Stage
TEXT 1592 1080 Left 3 ;Common Drain Stage
TEXT 2024 544 Left 3 ;Load