* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3888-1.asc
* Generated by LTspice 26.0.1 for Windows.
* *************** READ ME **********************************************************************\n \nThis model does not cover the PMBUS and SPI functions of this IC.\nTherefore, many things controlled by the PMBUS are configured by CTRL + right click on the IC.\nShare_CLK is NOT modelled. The SYNC pin can only be used as an input and\nit is grounded when it is not used. CLK_OUT pin is provided to allow clock out function.\nResistor setting pins like Vout_CFG are not modeled.\nVout and PWM_config must be set by CTRL by right-clicking on the IC.\n \nFrequency_Switch sets the frequency in kHz between 250 and 1000.\nPWM_config controls the phasing and master/slave configuration of the 8 channels.\nA decimal number is used for the 3-bit binary number. The description starts on page 72 of the datasheet.\n \n# (PWM0: PWM1)\n7 (7 phase: 1 Phase)\n6 (6 phase: 2 Phase)\n5 (6 phase: 1 phase)\n4 (5 phase: 3 phase)\n3 (4 phase: 4 phase)\n2 (4 phase: 3 phase)\n1 (4 phase: 2 phase)\n0 (3 phase: 3 phase)\n \nVout0 and Vout1 program the output voltage in a range from 0.3 to 3.45V\nVout_trans_rate0 and Vout_trans_rate1 program the rate of movement of VOUT as the part is starting or margining (V/ms).\nGM0 and GM1 program the gain the Error Amplifier in range from 1 to 5.73mS\nIout_Cal_Gain should match the voltage gain of the chosen current sense (V/A)\nRith0 and Rith1 program the compensation resistor in series \n with Cithr on the output of the error amplifier in a range from 1k to 62k ohm\nTon_Min=45n programs the minimum on time of the PWM outputs\n \nOC_Limit0 and OC_Limit1 program the peak current limit of the each phase used for that converter. \n \nTon_Delay0 and Ton_Delay1 set the delay from when the RUN pin goes high until the soft-start begins\nToff_Delay0 and Toff_Delay1 set the delay from when the RUN pin goes low until the turn-off ramp begins\n \nVOUT_UV_Fault_Limit0 and VOUT_UV_Fault_Limit1 program the undervoltage fault limit for the Pgood output\nVOUT_OV_Fault_Limit0 and VOUT_OV_Fault_Limit1 program the overvoltage fault limit for the Pgood output\n \nSlave0 and Slave1 set slave channel. 0 disable,1 enable. If enabled the error amplifier is open circuit
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3888-1.asy)
* Library below included based on ModelFile attribute of instance XU5, XU2, XU3, XU4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC7050.asy)
R4 N017 N003 499
R2 N005 N014 100K
R5 N006 N003 499
R15 N005 N018 10K
XU5 N001 N036 N001 0 N037 N039 N041 N001 N001 IN N033 0 N029 N004 N004 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
Rload1 OUT1 0 25m
C1 N005 0 2.2
L6 N016 OUT1 0.2 Rser=20m
V1 IN 0 12
Rload0 OUT0 0 20.83m
R7 N005 N004 100K
R18 N023 N025 97.6K
C4 N026 0 100p
L4 N034 OUT0 0.2 Rser=20m
R12 N019 N003 499
R8 N028 N003 499
C2 OUT0 0 220 m=7 Rser=2.5m
R14 N039 N003 499
XU2 N001 N012 N001 0 N011 N017 N020 N001 N001 IN N008 0 N006 N002 N002 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
C7 N032 0 3300p
L1 N008 OUT0 0.2 Rser=20m
XU1 N012 N015 N006 N007 N020 0 OUT0 N017 N026 N031 N013 N014 N032 0 N027 N018 OUT1 0 N035 N002 N004 N028 N040 N038 N041 N039 N036 N029 N021 N005 N009 IN N003 N019 0 N022 N023 N024 N025 LTC3888-1 Frequency_Switch=500 Vout0=2.5 Vout1=3 PWM_config=3 GM0=3.02m GM1=3.02m Vout_Trans_Rate0=7.5 Vout_Trans_Rate1=9 Vout_Scale_Loop0=2.507 Vout_Scale_Loop1=4.487 Ton_Delay0=0 Ton_Delay1=0 Toff_Delay0=0 Toff_Delay1=0 Rith0=5K Rith1=5K OC_Limit0=50 OC_Limit1=50 Ton_Min=45n VOUT_UV_Fault_Limit0=2.2 VOUT_UV_Fault_Limit1=2.8 VOUT_OV_Fault_Limit0=2.6 VOUT_OV_Fault_Limit1=3.1 Iout_Cal_Gain=5m Slave0=0 Slave1=0 ;pnba PWM0)PWM1)ISENSE0)ISENSE1)PWM2)VSENSE0-)VSENSE0+)ISENSE2)ITH0)ITHR0)PGOOD0)PGOOD1)ITHR1)SYNC)ITH1)CLKOUT)VSENSE1+)VSENSE1-)PWM3)RUN0)RUN1)ISENSE3)PWM4)ISENSE4)PWM5)ISENSE5)PWM6)ISENSE6)PWM7)VDD33)INTVCC)VIN)IREF)ISENSE7)GND)DAOUT0)DAOUT1)FB0)FB1
R1 N005 N002 100K
R13 N029 N003 499
XU3 N001 N035 N001 0 N034 N038 N040 N001 N001 IN N030 0 N028 N002 N002 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
R17 N024 0 28K
R19 N025 0 28K
L5 N010 OUT1 0.2 Rser=20m
R9 N038 N003 499
V2 N001 0 6
C5 N031 0 3300p
XU4 N001 N015 N001 0 N016 N019 N021 N001 N001 IN N010 0 N007 N004 N004 LTC7050 RTon=5m RBon=1.2m OV=14.8 ;pnba VCC)PWM1)RUN1)SGND)SW2)ISNS2)PWM2)RUN2)PVCC)VIN)SW1)PGND)ISNS1)FLTB1)FLTB2
R11 N007 N003 499
C8 OUT1 0 220 m=7 Rser=2.5m
L7 N033 OUT1 0.2 Rser=20m
R16 N022 N024 42.2K
L3 N030 OUT0 0.2 Rser=20m
L8 N037 OUT1 0.2 Rser=20m
R6 N005 N013 100K
L2 N011 OUT0 0.2 Rser=20m
C6 N027 0 100p
C3 N009 0 4.7
.tran 1m startup
.lib LTC3888-1.sub
.lib LTC7050.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
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SYMBOL LTC3888-1 1264 1472 R0
SYMATTR InstName U1
SYMATTR SpiceLine2 Toff_Delay1=0 Rith0=5K Rith1=5K OC_Limit0=50 OC_Limit1=50 Ton_Min=45n VOUT_UV_Fault_Limit0=2.2 VOUT_UV_Fault_Limit1=2.8 VOUT_OV_Fault_Limit0=2.6 VOUT_OV_Fault_Limit1=3.1 Iout_Cal_Gain=5m Slave0=0 Slave1=0
SYMATTR SpiceLine Frequency_Switch=500 Vout0=2.5 Vout1=3 PWM_config=3 GM0=3.02m GM1=3.02m Vout_Trans_Rate0=7.5 Vout_Trans_Rate1=9 Vout_Scale_Loop0=2.507 Vout_Scale_Loop1=4.487 Ton_Delay0=0 Ton_Delay1=0 Toff_Delay0=0
SYMBOL res 688 1280 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 499
SYMBOL res 1552 912 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 1600 1616 R0
SYMATTR InstName R19
SYMATTR Value 28K
SYMBOL res 1552 816 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 100K
SYMBOL cap 2800 656 R0
WINDOW 3 40 52 Left 2
WINDOW 0 39 8 Left 2
WINDOW 123 40 77 Left 2
SYMATTR Value 220
SYMATTR InstName C8
SYMATTR Value2 m=7
SYMATTR SpiceLine Rser=2.5m
SYMBOL res 1552 1008 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R15
SYMATTR Value 10K
SYMBOL LTC7050 2288 928 R0
SYMATTR InstName U4
SYMBOL ind 0 1824 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL cap 1088 1696 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100p
SYMBOL ind 2592 944 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L6
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL cap -368 656 R0
WINDOW 3 40 52 Left 2
WINDOW 0 39 8 Left 2
WINDOW 123 40 77 Left 2
SYMATTR Value 220
SYMATTR InstName C2
SYMATTR Value2 m=7
SYMATTR SpiceLine Rser=2.5m
SYMBOL res 1888 2032 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 499
SYMBOL cap 1440 1696 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 100p
SYMBOL res -528 640 R0
SYMATTR InstName Rload0
SYMATTR Value 20.83m
SYMBOL cap 1424 624 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL res 2992 640 R0
SYMATTR InstName Rload1
SYMATTR Value 25m
SYMBOL res 864 1520 R0
SYMATTR InstName R16
SYMATTR Value 42.2K
SYMBOL LTC7050 2288 2096 R0
SYMATTR InstName U5
SYMBOL cap 1088 1792 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 3300p
SYMBOL res 960 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL voltage 80 320 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 688 2384 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R9
SYMATTR Value 499
SYMBOL ind 2592 1824 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L7
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL voltage 320 336 R0
SYMATTR InstName V2
SYMATTR Value 6
SYMBOL res 1872 1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 499
SYMBOL res 1888 2224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R13
SYMATTR Value 499
SYMBOL ind 2592 656 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L5
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL res 960 944 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 100K
SYMBOL LTC7050 320 2096 M0
SYMATTR InstName U3
SYMBOL cap 1440 1792 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C7
SYMATTR Value 3300p
SYMBOL ind 0 2112 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL res 1888 2352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 499
SYMBOL res 864 1616 R0
SYMATTR InstName R17
SYMATTR Value 28K
SYMBOL ind 0 656 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL res 688 2064 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 499
SYMBOL cap 1056 720 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL ind 0 944 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL ind 2592 2112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L8
SYMATTR Value 0.2
SYMATTR SpiceLine Rser=20m
SYMBOL res 688 2256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 499
SYMBOL res 1600 1520 R0
SYMATTR InstName R18
SYMATTR Value 97.6K
SYMBOL LTC7050 320 928 M0
SYMATTR InstName U2
FLAG 80 432 0
FLAG 128 272 IN
FLAG 976 736 0
FLAG 1504 640 0
FLAG 1088 1024 0
FLAG 320 1280 0
FLAG 1264 2464 0
FLAG -352 752 0
FLAG -512 752 0
FLAG 160 1216 0
FLAG 1088 1424 0
FLAG 1008 1712 0
FLAG 1008 1808 0
FLAG 1520 1712 0
FLAG 1520 1808 0
FLAG -432 640 OUT0
FLAG 320 2448 0
FLAG 160 2384 0
FLAG 2288 1280 0
FLAG 2816 752 0
FLAG 3008 752 0
FLAG 2448 1216 0
FLAG 2928 640 OUT1
FLAG 2288 2448 0
FLAG 2448 2384 0
FLAG 1440 1424 0
FLAG 320 448 0
FLAG 880 1728 0
FLAG 1616 1728 0
TEXT 2824 1064 Left 2 ;*************** READ ME **********************************************************************\n \nThis model does not cover the PMBUS and SPI functions of this IC.\nTherefore, many things controlled by the PMBUS are configured by CTRL + right click on the IC.\nShare_CLK is NOT modelled. The SYNC pin can only be used as an input and\nit is grounded when it is not used. CLK_OUT pin is provided to allow clock out function.\nResistor setting pins like Vout_CFG are not modeled.\nVout and PWM_config must be set by CTRL by right-clicking on the IC.\n \nFrequency_Switch sets the frequency in kHz between 250 and 1000.\nPWM_config controls the phasing and master/slave configuration of the 8 channels.\nA decimal number is used for the 3-bit binary number. The description starts on page 72 of the datasheet.\n \n# (PWM0: PWM1)\n7 (7 phase: 1 Phase)\n6 (6 phase: 2 Phase)\n5 (6 phase: 1 phase)\n4 (5 phase: 3 phase)\n3 (4 phase: 4 phase)\n2 (4 phase: 3 phase)\n1 (4 phase: 2 phase)\n0 (3 phase: 3 phase)\n \nVout0 and Vout1 program the output voltage in a range from 0.3 to 3.45V\nVout_trans_rate0 and Vout_trans_rate1 program the rate of movement of VOUT as the part is starting or margining (V/ms).\nGM0 and GM1 program the gain the Error Amplifier in range from 1 to 5.73mS\nIout_Cal_Gain should match the voltage gain of the chosen current sense (V/A)\nRith0 and Rith1 program the compensation resistor in series \n                with Cithr on the output of the error amplifier in a range from 1k to 62k ohm\nTon_Min=45n programs the minimum on time of the PWM outputs\n \nOC_Limit0 and OC_Limit1 program the peak current limit of the each phase used for that converter. \n \nTon_Delay0 and Ton_Delay1 set the delay from when the RUN pin goes high until the soft-start begins\nToff_Delay0 and Toff_Delay1 set the delay from when the RUN pin goes low until the turn-off ramp begins\n \nVOUT_UV_Fault_Limit0 and VOUT_UV_Fault_Limit1 program the undervoltage fault limit for the Pgood output\nVOUT_OV_Fault_Limit0 and VOUT_OV_Fault_Limit1 program the overvoltage fault limit for the Pgood output\n \nSlave0 and Slave1 set slave channel. 0 disable,1 enable. If enabled the error amplifier is open circuit
TEXT 2824 896 Left 2 !.tran 1m startup