Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\325c20281a66_Transistor_ckt_for_bat_full_charge.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N002 N004 0 0 NPN
V1 In 0 SINE(11 1.6 1)
R1 N003 0 10K
R2 N004 N003 47K
R3 N001 N002 330
D1 N003 In BZX84C12L
D2 In N001 NSPW500BS
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0 1 0 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -496 -208 -496 -240
WIRE -64 -208 -496 -208
WIRE 192 -208 -64 -208
WIRE 192 -144 192 -208
WIRE 192 -16 192 -80
WIRE -64 32 -64 -208
WIRE -496 48 -496 -208
WIRE 192 112 192 64
WIRE -64 160 -64 96
WIRE -16 160 -64 160
WIRE 128 160 64 160
WIRE -64 224 -64 160
WIRE -496 352 -496 128
WIRE -64 352 -64 304
WIRE -64 352 -496 352
WIRE 192 352 192 208
WIRE 192 352 -64 352
WIRE 192 368 192 352
SYMBOL zener -48 96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C12L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL npn2 128 112 R0
SYMATTR InstName Q1
SYMBOL voltage -496 32 R0
SYMATTR InstName V1
SYMATTR Value SINE(11 1.6 1)
SYMBOL res 176 -32 R0
SYMATTR InstName R3
SYMATTR Value 330
SYMBOL res 80 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 47K
SYMBOL res -80 208 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL LED 176 -144 R0
SYMATTR InstName D2
SYMATTR Value NSPW500BS
SYMATTR Description Diode
SYMATTR Type diode
FLAG 192 368 0
FLAG -496 -240 In
TEXT -720 -56 Left 2 !.tran 0 1 0 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\357c3869d0df_Monte_Carlo.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N003 N001 {mc(18n,tol)}
Vi N001 0 AC 1 0
R3 N003 0 {mc(1.5k,tol)}
C3 N002 0 {mc(39n,tol)}
C2 Vo N003 {mc(18n,tol)}
R2 Vo N002 {mc(3.3k,tol)}
R1 N002 N001 {mc(3.3k,tol)}
.ac dec 100 10 1meg
.param tol=0.05
.step param run 1 1000 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 680
WIRE 32 112 -48 112
WIRE 80 112 32 112
WIRE 224 112 160 112
WIRE 336 112 224 112
WIRE 464 112 416 112
WIRE -48 176 -48 112
WIRE 224 176 224 112
WIRE -48 304 -48 256
WIRE 224 304 224 240
WIRE 288 304 224 304
WIRE 288 320 288 304
WIRE 224 368 224 304
WIRE 32 544 32 112
WIRE 80 544 32 544
WIRE 224 544 224 448
WIRE 224 544 144 544
WIRE 320 544 224 544
WIRE 464 544 464 112
WIRE 464 544 384 544
SYMBOL voltage -48 160 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1 0
SYMATTR InstName Vi
SYMATTR Value ""
SYMBOL res 432 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {mc(3.3k,tol)}
SYMBOL res 176 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {mc(3.3k,tol)}
SYMBOL cap 208 176 R0
SYMATTR InstName C3
SYMATTR Value {mc(39n,tol)}
SYMBOL cap 144 528 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {mc(18n,tol)}
SYMBOL res 240 464 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value {mc(1.5k,tol)}
SYMBOL cap 384 528 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {mc(18n,tol)}
FLAG -48 304 0
FLAG 288 320 0
FLAG 464 112 Vo
TEXT 664 456 Left 2 !.ac dec 100 10 1meg
TEXT 664 384 Left 2 !.param tol=0.05
TEXT 672 424 Left 2 !.step param run 1 1000 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3090.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3090.asy)
V2 N001 0 3.3
C2 OUT 0 4.7 Rser=10m
Rload OUT 0 4.16
R1 N004 0 49.9K
XU1 IN MP_01 N002 N003 N001 IN N004 0 OUT LT3090 ;pnba IN))Ilim)Imonp)Imonn)_SHDN)SET)GND)OUT
V1 IN 0 -3.3
R2 IN N002 10K
C1 N004 0 .1
R3 N003 0 3.32K
.tran .1 startup
.lib LT3090.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 -16 304 -32
WIRE 16 80 -144 80
WIRE 176 80 16 80
WIRE -144 96 -144 80
WIRE 176 96 176 80
WIRE 304 96 304 64
WIRE 16 160 16 80
WIRE 96 160 16 160
WIRE 496 160 384 160
WIRE 592 160 496 160
WIRE 16 176 16 160
WIRE 496 176 496 160
WIRE 592 176 592 160
WIRE -144 192 -144 176
WIRE 496 272 496 240
WIRE 592 272 592 256
WIRE 16 288 16 256
WIRE 96 288 16 288
WIRE 416 288 384 288
WIRE 416 304 416 288
WIRE 176 368 176 352
WIRE 176 368 80 368
WIRE 304 368 304 352
WIRE 80 384 80 368
WIRE 176 384 176 368
WIRE 416 400 416 384
WIRE 80 480 80 448
WIRE 176 480 176 464
SYMBOL res 576 160 R0
SYMATTR InstName Rload
SYMATTR Value 4.16
SYMBOL voltage -144 80 R0
SYMATTR InstName V1
SYMATTR Value -3.3
SYMBOL voltage 304 80 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL cap 480 176 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=10m
SYMBOL res 160 368 R0
SYMATTR InstName R1
SYMATTR Value 49.9K
SYMBOL PowerProducts\\LT3090 240 224 R0
SYMATTR InstName U1
SYMBOL cap 64 384 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 0 160 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 400 288 R0
SYMATTR InstName R3
SYMATTR Value 3.32K
FLAG 80 480 0
FLAG 176 480 0
FLAG 304 368 0
FLAG -144 192 0
FLAG 304 -32 0
FLAG 416 400 0
FLAG 496 272 0
FLAG 592 272 0
FLAG -144 80 IN
FLAG 592 160 OUT
TEXT 384 448 Left 2 !.tran .1 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6658-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6658-3.asy)
C1 N001 0 1
V3 IN 0 PWL(0 0 100u 0 +2u 5.5)
XU1 IN IN IN IN N001 OUT1 OUT1 OUT2 OUT2 0 N002 LT6658-3 ;pnba Vin)Vin1)Vin2)_OD)Bypass)Vout1_F)Vout1_S)Vout2_F)Vout2_S)Gnd)NR
C3 OUT1 0 1
C2 OUT2 0 1
.tran 500u
.lib LT6658.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1448 1048
WIRE 16 -16 -336 -16
WIRE 128 -16 16 -16
WIRE 224 -16 128 -16
WIRE 320 -16 224 -16
WIRE -336 0 -336 -16
WIRE 128 0 128 -16
WIRE 224 0 224 -16
WIRE 320 0 320 -16
WIRE 432 64 416 64
WIRE 512 64 432 64
WIRE 512 80 512 64
WIRE -336 96 -336 80
WIRE 432 144 432 64
WIRE 432 144 416 144
WIRE 512 160 512 144
WIRE 16 192 16 -16
WIRE 48 192 16 192
WIRE 432 224 416 224
WIRE 496 224 432 224
WIRE 496 240 496 224
WIRE 432 304 432 224
WIRE 432 304 416 304
WIRE 496 320 496 304
WIRE 128 400 128 384
WIRE 224 400 224 384
WIRE 320 400 320 384
WIRE 224 480 224 464
SYMBOL LT6658-3 224 192 R0
SYMATTR InstName U1
SYMBOL cap 496 80 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL voltage -336 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 0 100u 0 +2u 5.5)
SYMBOL cap 480 240 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 208 400 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 128 400 0
FLAG 224 480 0
FLAG -336 96 0
FLAG 512 160 0
FLAG 496 320 0
FLAG 496 224 OUT1
FLAG 512 64 OUT2
FLAG -336 -16 IN
TEXT 464 464 Left 2 !.tran 500u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2166-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N008 0 2n
L1 N004 OUT 1.5 Rser=6m
C2 N003 N004 .1
C3 OUT 0 80 Rser=2m
R1 N005 0 100K
C5 N006 0 680p
R2 N007 N006 36K
V1 IN 0 5
R3 OUT N001 100K
C4 N002 0 1
C6 N007 0 1p
Rload OUT 0 .36
XU1 N002 N005 N002 OUT 0 0 N004 IN IN IN N001 N008 N007 N003 N002 ADP2166-x.x Rtop=667K Rbot=333K ;pnba SYNC)Rt)TRK)FB)Gnd)Pgnd)SW)Pvin)Avin)EN)Pgood)SS)Comp)Bst)Vreg
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2166-1.8.asy)
.lib ADP2166-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1076 680
WIRE 48 -96 -144 -96
WIRE 176 -96 48 -96
WIRE 272 -96 176 -96
WIRE -144 -80 -144 -96
WIRE 176 -80 176 -96
WIRE 272 -80 272 -96
WIRE 48 -16 48 -96
WIRE 64 -16 48 -16
WIRE 448 -16 384 -16
WIRE 608 -16 528 -16
WIRE -144 16 -144 0
WIRE -32 64 -48 64
WIRE 48 64 32 64
WIRE 64 64 48 64
WIRE 432 64 384 64
WIRE 48 144 48 64
WIRE 64 144 48 144
WIRE 432 144 432 128
WIRE 432 144 384 144
WIRE 480 144 432 144
WIRE 608 144 608 -16
WIRE 608 144 560 144
WIRE 720 144 608 144
WIRE 832 144 720 144
WIRE 720 160 720 144
WIRE 832 160 832 144
WIRE 48 224 48 144
WIRE 64 224 48 224
WIRE 720 256 720 224
WIRE 832 256 832 240
WIRE -32 304 -48 304
WIRE 64 304 48 304
WIRE 608 304 608 144
WIRE 608 304 384 304
WIRE -160 384 -224 384
WIRE -32 384 -80 384
WIRE 64 384 -32 384
WIRE 400 384 384 384
WIRE 480 384 464 384
WIRE -224 400 -224 384
WIRE -32 400 -32 384
WIRE 176 464 176 448
WIRE 272 464 272 448
WIRE -224 480 -224 464
WIRE -32 480 -32 464
FLAG 480 384 0
FLAG 272 464 0
FLAG -48 304 0
FLAG -224 480 0
FLAG -144 16 0
FLAG 720 256 0
FLAG 832 256 0
FLAG 832 144 OUT
FLAG -144 -96 IN
FLAG -48 64 0
FLAG -32 480 0
FLAG 176 464 0
SYMBOL cap 400 368 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL ind 464 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=6m
SYMBOL cap 416 64 R0
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL cap 704 160 R0
WINDOW 40 24 74 Left 2
SYMATTR Value 80
SYMATTR InstName C3
SYMATTR SpiceLine Rser=2m
SYMBOL res 64 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap -240 400 R0
SYMATTR InstName C5
SYMATTR Value 680p
SYMBOL res -64 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 36K
SYMBOL voltage -144 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 544 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap 32 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap -48 400 R0
SYMATTR InstName C6
SYMATTR Value 1p
SYMBOL res 816 144 R0
SYMATTR InstName Rload
SYMATTR Value .36
SYMBOL ADP2166-1.8 224 176 R0
SYMATTR InstName U1
TEXT 696 424 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\f5c7bf9ca7f6_Draft7.asc
* Generated by LTspice 26.0.1 for Windows.
D4 N001 N003 1N4148
D1 N002 N001 1N4148
D2 N002 0 1N4148
V1 N001 0 SINE(0 1 1k)
R1 N003 N002 1000k
D3 0 N003 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1716 680
WIRE 240 32 16 32
WIRE 240 96 240 32
WIRE 240 96 144 96
WIRE 368 96 240 96
WIRE 16 144 16 32
WIRE 144 176 144 160
WIRE 144 176 96 176
WIRE 368 176 368 160
WIRE 464 176 368 176
WIRE 544 176 464 176
WIRE 144 192 144 176
WIRE 368 192 368 176
WIRE 256 256 144 256
WIRE 368 256 256 256
WIRE 464 256 432 256
WIRE 544 256 464 256
WIRE 96 304 96 176
WIRE 432 304 432 256
WIRE 432 304 96 304
WIRE 16 336 16 224
WIRE 176 336 16 336
WIRE 256 336 256 256
WIRE 256 336 176 336
SYMBOL res 448 160 R0
SYMATTR InstName R1
SYMATTR Value 1000k
SYMBOL diode 128 192 R0
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL diode 352 96 R0
SYMATTR InstName D4
SYMATTR Value 1N4148
SYMBOL voltage 16 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
SYMBOL diode 384 256 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value 1N4148
SYMBOL diode 160 160 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG 176 336 0
TEXT -16 360 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\1a1ad9f5887c_cs_amp_for_differential.asc
* Generated by LTspice 26.0.1 for Windows.
* COMMON SOURCE AMPLIFIER FOR DESIGNING DIFFERENTIAL PAIR USING LUT FROM ADT
* Specification :\nGBW=1GHz\nGian=10 at 100MHz
;.tf V(vout) vgs
;.tran 100n
M1 vout vg vs 0 nch l=0.36u w=16.92u
vgs vg 0 SINE(1.1917 10m 100meg) AC 1
Vb vb 0 0.9257
M2 vout vb vdd vdd pch l=0.36u w=9.9u
vdd vdd 0 1.8
C1 vout 0 0.29p
vs vs 0 0.45
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include CMOS180.txt
.op
.ac dec 10 1MEG 40G
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 732
WIRE 352 64 352 16
WIRE 448 64 352 64
WIRE 352 80 352 64
WIRE 304 96 256 96
WIRE 448 128 448 64
WIRE 448 128 352 128
WIRE 32 256 32 176
WIRE 352 256 352 176
WIRE 608 256 352 256
WIRE 656 256 608 256
WIRE -256 272 -256 224
WIRE -96 272 -96 224
WIRE 352 272 352 256
WIRE -368 288 -368 256
WIRE 464 320 352 320
WIRE 608 336 608 256
WIRE 304 352 240 352
WIRE -368 416 -368 368
WIRE -256 416 -256 352
WIRE -96 416 -96 352
WIRE 32 416 32 336
WIRE 352 416 352 368
WIRE 608 432 608 400
IOPIN 240 352 In
IOPIN 656 256 In
SYMBOL nmos4 304 272 R0
WINDOW 123 55 116 Left 2
SYMATTR Value2 l=0.36u w=16.92u
SYMATTR InstName M1
SYMATTR Value nch
SYMBOL pmos4 304 176 M180
WINDOW 123 120 23 Left 2
SYMATTR Value2 l=0.36u w=9.9u
SYMATTR InstName M2
SYMATTR Value pch
SYMBOL cap 592 336 R0
SYMATTR InstName C1
SYMATTR Value 0.29p
SYMBOL voltage -368 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vs
SYMATTR Value 0.45
SYMBOL voltage -256 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vdd
SYMATTR Value 1.8
SYMBOL voltage 32 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vb
SYMATTR Value 0.9257
SYMBOL voltage -96 256 R0
WINDOW 3 -41 -81 VRight 2
WINDOW 123 28 97 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(1.1917 10m 100meg)
SYMATTR Value2 AC 1
SYMATTR InstName vgs
FLAG -96 416 0
FLAG -256 416 0
FLAG -368 416 0
FLAG -368 256 vs
FLAG -256 224 vdd
FLAG -96 224 vg
FLAG 240 352 vg
FLAG 656 256 vout
FLAG 608 432 0
FLAG 352 16 vdd
FLAG 32 416 0
FLAG 32 176 vb
FLAG 256 96 vb
FLAG 352 416 vs
FLAG 464 320 0
TEXT -376 16 Left 2 !.include CMOS180.txt
TEXT -376 64 Left 2 !.op
TEXT -376 40 Left 2 !;.tf V(vout) vgs
TEXT -376 88 Left 2 !;.tran 100n
TEXT -376 -80 Left 2 ;COMMON SOURCE AMPLIFIER FOR DESIGNING DIFFERENTIAL PAIR USING LUT FROM ADT
TEXT -376 112 Left 2 !.ac dec 10 1MEG 40G
TEXT 560 -16 Left 2 ;Specification :\nGBW=1GHz\nGian=10 at 100MHz
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1306.asc
* Generated by LTspice 26.0.1 for Windows.
L1 IN N002 10 Rpar=1K
C1 N002 N001 1
R1 OUT N005 768K
XU1 N004 N005 OUT 0 N002 N001 IN IN LT1306 ;pnba Vc)FB)OUT)GND)SW)CAP)Vin)_SHDN
R2 N005 0 249K
R3 N004 N003 118K
C2 N003 0 680p
C3 N004 0 68p
V1 IN 0 3
C4 OUT 0 220
D1 IN N001 MBR0530L
Rload OUT 0 15
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1306.asy)
.lib LT1306.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2592 1680
WIRE 1920 1040 1840 1040
WIRE 2064 1040 1984 1040
WIRE 1744 1136 1632 1136
WIRE 1840 1136 1840 1040
WIRE 1840 1136 1744 1136
WIRE 1856 1136 1840 1136
WIRE 1952 1136 1936 1136
WIRE 1984 1136 1952 1136
WIRE 2064 1136 2064 1040
WIRE 2064 1136 2048 1136
WIRE 1632 1152 1632 1136
WIRE 1840 1200 1840 1136
WIRE 1952 1200 1952 1136
WIRE 2064 1200 2064 1136
WIRE 1632 1248 1632 1232
WIRE 1744 1296 1744 1136
WIRE 1792 1296 1744 1296
WIRE 2176 1296 2112 1296
WIRE 2288 1296 2176 1296
WIRE 2400 1296 2288 1296
WIRE 2176 1312 2176 1296
WIRE 2288 1312 2288 1296
WIRE 2400 1312 2400 1296
WIRE 2288 1408 2288 1376
WIRE 2400 1408 2400 1392
WIRE 1616 1424 1584 1424
WIRE 1728 1424 1696 1424
WIRE 1792 1424 1728 1424
WIRE 2176 1424 2176 1392
WIRE 2176 1424 2112 1424
WIRE 1584 1456 1584 1424
WIRE 1728 1456 1728 1424
WIRE 2176 1456 2176 1424
WIRE 1584 1552 1584 1520
WIRE 1728 1552 1728 1520
WIRE 1952 1552 1952 1520
WIRE 2176 1552 2176 1536
FLAG 2176 1552 0
FLAG 1952 1552 0
FLAG 1584 1552 0
FLAG 1728 1552 0
FLAG 1632 1248 0
FLAG 2288 1408 0
FLAG 2400 1408 0
FLAG 2400 1296 OUT
FLAG 1632 1136 IN
SYMBOL ind 1840 1152 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rpar=1K
SYMBOL polcap 1984 1120 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL RES 2160 1296 R0
SYMATTR InstName R1
SYMATTR Value 768K
SYMBOL POWERPRODUCTS\\LT1306 1952 1360 R0
SYMATTR InstName U1
SYMBOL RES 2160 1440 R0
SYMATTR InstName R2
SYMATTR Value 249K
SYMBOL RES 1712 1408 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 118K
SYMBOL cap 1568 1456 R0
SYMATTR InstName C2
SYMATTR Value 680p
SYMBOL cap 1712 1456 R0
SYMATTR InstName C3
SYMATTR Value 68p
SYMBOL VOLTAGE 1632 1136 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL polcap 2272 1312 R0
SYMATTR InstName C4
SYMATTR Value 220
SYMBOL schottky 1920 1056 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBR0530L
SYMBOL RES 2384 1296 R0
SYMATTR InstName Rload
SYMATTR Value 15
TEXT 2296 1520 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\44b1a907ac46_half_wave_rectifier.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 SINE(0 5 100)
R1 N002 0 10k
D1 N001 N002 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 48 -16 48
WIRE 320 48 192 48
WIRE -16 112 -16 48
WIRE 320 112 320 48
WIRE -16 240 -16 192
WIRE 320 240 320 192
WIRE 320 240 -16 240
SYMBOL res 304 96 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL diode 128 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL voltage -16 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 100)
FLAG 320 240 0
TEXT -48 264 Left 2 !.tran 0.05
* Z:\home\khalils\Downloads\files\data\raw_asc\3400814bd16a_parte1.asc
* Generated by LTspice 26.0.1 for Windows.
Vgs1 in N001 AC 1
VDS VDD 0 5V
VGS N001 0 1.5
MN_1u Vout in 0 0 N_1u l=1.5u w=3u
RD VDD Vout 25k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.ac dec 10 1 1000000
.measure AC GAIN FIND V(vout) AT = 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 608 -224 608 -256
WIRE 336 -208 336 -256
WIRE 608 -96 608 -144
WIRE 336 -80 336 -128
WIRE 448 -80 336 -80
WIRE 336 -48 336 -80
WIRE 384 0 336 0
WIRE 64 32 -16 32
WIRE 288 32 64 32
WIRE 64 48 64 32
WIRE 384 48 384 0
WIRE 384 48 336 48
WIRE 336 144 336 48
WIRE 64 176 64 128
WIRE 64 304 64 256
SYMBOL voltage 64 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VGS
SYMATTR Value 1.5
SYMBOL voltage 608 -240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDS
SYMATTR Value 5V
SYMBOL res 320 -224 R0
SYMATTR InstName RD
SYMATTR Value 25k
SYMBOL voltage 64 32 R0
WINDOW 3 24 44 Left 2
WINDOW 123 24 72 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMATTR InstName Vgs1
SYMBOL nmos4 288 -48 R0
SYMATTR InstName N_1u
SYMATTR Value N_1u
SYMATTR Value2 l=1.5u w=3u
FLAG 336 144 0
FLAG 64 304 0
FLAG 448 -80 Vout
FLAG -16 32 in
FLAG 336 -256 VDD
FLAG 608 -96 0
FLAG 608 -256 VDD
TEXT -240 -104 Left 2 !.include cmosedu_models.txt
TEXT -240 -64 Left 2 !.ac dec 10 1 1000000
TEXT -232 -144 Left 2 !.measure AC GAIN FIND V(vout) AT = 1
* Z:\home\khalils\Downloads\files\data\raw_asc\1da71189a8d1_DCLink_Gatedriver.asc
* Generated by LTspice 26.0.1 for Windows.
D2 N002 N001 1N5819
V2 DCLINK 0 PULSE(0 6 100m 1m 1m 100m 200m)
C3 GATE DCLINK 10n
B1 GATEDRIVER 0 V=V(EN)*V(PWM)
V3 EN NC_02 PULSE(0 1 10m 100n 100n 10m 20m)
R2 DCLINK N002 1
D1 N001 GATE 1N5819
V1 PWM NC_01 PULSE(0 8 10m 50n 50n 10u 20u)
C1 GATE DCLINK 100p
R1 GATE DCLINK 1Meg
C2 N001 GATEDRIVER 1n
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 500m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1248 680
WIRE -416 -208 -416 -224
WIRE -416 -32 -416 -48
WIRE 128 16 80 16
WIRE 400 16 192 16
WIRE 704 16 400 16
WIRE 752 16 704 16
WIRE 784 16 752 16
WIRE 400 48 400 16
WIRE 784 48 784 16
WIRE 704 64 704 16
WIRE -400 112 -416 112
WIRE -32 112 -400 112
WIRE 80 112 80 16
WIRE 80 112 32 112
WIRE 80 160 80 112
WIRE 144 160 80 160
WIRE 256 160 208 160
WIRE 400 160 400 112
WIRE 400 160 336 160
WIRE 624 160 400 160
WIRE 704 160 704 128
WIRE 704 160 624 160
WIRE 784 160 784 128
WIRE 784 160 704 160
WIRE -416 176 -416 112
WIRE 784 176 784 160
WIRE -416 288 -416 256
WIRE 784 288 784 256
SYMBOL cap 384 48 R0
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL voltage -416 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 8 10m 50n 50n 10u 20u)
SYMBOL cap 32 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL voltage 784 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 6 100m 1m 1m 100m 200m)
SYMBOL res 768 32 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL voltage -416 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 10m 100n 100n 10m 20m)
SYMBOL cap 688 64 R0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL schottky 128 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 352 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL bv -416 160 R0
SYMATTR InstName B1
SYMATTR Value V=V(EN)*V(PWM)
SYMBOL schottky 208 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N5819
SYMATTR Description Diode
SYMATTR Type diode
FLAG 784 288 0
FLAG -416 288 0
FLAG 624 160 DCLINK
FLAG 752 16 GATE
FLAG -400 112 GATEDRIVER
FLAG -416 -112 0
FLAG -416 64 0
FLAG -416 -224 PWM
FLAG -416 -48 EN
TEXT -450 328 Left 2 !.tran 500m
* Z:\home\khalils\Downloads\files\data\raw_asc\077d2d949229_Power_Transformer.asc
* Generated by LTspice 26.0.1 for Windows.
L1 in 0 5.12
V1 in 0 SINE(0 155.5635 60) Rser=0.01
L2 out1 0 61m
L3 0 out2 61m
K L1 L2 L3 0.99
.tran 50m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 -32 -32 -32
WIRE 464 -32 416 -32
WIRE 416 32 416 -32
WIRE -32 112 -32 -32
WIRE 256 144 256 -32
WIRE 416 176 416 112
WIRE 480 176 416 176
WIRE 480 192 480 176
WIRE 416 256 416 176
WIRE -32 416 -32 192
WIRE 256 416 256 224
WIRE 256 416 -32 416
WIRE 416 416 416 336
WIRE 464 416 416 416
WIRE -32 448 -32 416
IOPIN 256 -32 In
IOPIN 464 -32 Out
IOPIN 464 416 Out
SYMBOL ind2 432 240 M0
SYMATTR InstName L3
SYMATTR Value 61m
SYMATTR Type ind
SYMBOL voltage -32 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 155.5635 60)
SYMATTR SpiceLine Rser=0.01
SYMBOL ind2 432 16 M0
SYMATTR InstName L2
SYMATTR Value 61m
SYMATTR Type ind
SYMBOL ind2 240 128 R0
SYMATTR InstName L1
SYMATTR Value 5.12
SYMATTR Type ind
FLAG -32 448 0
FLAG 480 192 0
FLAG 256 -32 in
FLAG 464 -32 out1
FLAG 464 416 out2
TEXT 272 464 Left 2 !K L1 L2 L3 0.99
TEXT -66 538 Left 2 !.tran 50m
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX4164.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX4164.asy)
CL OUT 0 15p
XU1 IN OUT Vcc Vee OUT MAX4164 ;pnba In+)In-)V+)V-)OUT
V1 IN 0 SINE(0 50m 1k)
Vcc Vcc 0 2.5
RL OUT 0 10k
Vee 0 Vee 2.5
.tran 1m
.lib MAX4164.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 144 288 144 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 144 400 144 368
WIRE 144 400 112 400
WIRE 400 400 304 400
WIRE 112 416 112 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 144 448 144 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 144 544 144 528
WIRE 304 592 304 576
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 1k)
SYMBOL MAX4164 432 320 R0
SYMATTR InstName U1
SYMBOL voltage 144 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL voltage 144 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
FLAG 720 384 OUT
FLAG 144 272 Vcc
FLAG 144 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 112 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
TEXT 96 632 Left 2 !.tran 1m