* Z:\home\khalils\Downloads\files\data\raw_asc\ba1d3e7cb10f_nand_gate.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout A N002 0 n_65 l=65n w=1u
M2 N002 B N003 0 n_65 l=65n w=1u
M3 Vout A N001 VDD p_65 l=65n w=1u
M4 Vout B N001 VDD p_65 l=65n w=1u
M5 N001 clk_b VDD VDD p_65 l=65n w=4u
M6 N003 clk 0 0 n_65 l=65n w=4u
V1 VDD 0 1.2
V2 A 0 PWL(0 0 1u 0 1.001u 1.2 2u 1.2 2.001u 0 3u 0 3.001u 1.2 5u 1.2 5.001u 0 7u 0 7.001u 1.2 8u 1.2)
V3 B 0 PWL(0 0 3u 0 3.001u 1.2 4u 1.2 4.001u 0 5u 0 5.001u 1.2 7u 1.2 7.001u 0)
V4 clk_b 0 PULSE(1.2 0 0 0.01u 0.01u 10u 20u)
V5 clk 0 PULSE(0 1.2 0 0.01u 0.01u 10u 20u)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include 65nm_bulk.txt
.tran 0 20u 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2160 1472
WIRE 1024 240 1024 208
WIRE 432 352 432 288
WIRE 464 352 432 352
WIRE 384 368 336 368
WIRE 464 400 464 352
WIRE 464 400 432 400
WIRE 432 496 432 448
WIRE 432 496 320 496
WIRE 544 496 432 496
WIRE 1024 560 1024 528
WIRE 320 576 320 496
WIRE 544 576 544 496
WIRE 272 592 208 592
WIRE 496 592 400 592
WIRE 352 624 352 576
WIRE 352 624 320 624
WIRE 576 624 576 576
WIRE 576 624 544 624
WIRE 320 720 320 672
WIRE 432 720 320 720
WIRE 544 720 544 672
WIRE 544 720 432 720
WIRE 608 720 544 720
WIRE 208 736 208 592
WIRE 208 736 144 736
WIRE 400 768 400 592
WIRE 400 768 320 768
WIRE 432 800 432 720
WIRE 1024 816 1024 784
WIRE 448 848 432 848
WIRE 208 880 208 736
WIRE 384 880 208 880
WIRE 320 960 320 768
WIRE 320 960 256 960
WIRE 432 960 432 896
WIRE 448 1008 432 1008
WIRE 320 1040 320 960
WIRE 384 1040 320 1040
WIRE 432 1088 432 1056
WIRE 1024 1088 1024 1056
WIRE 448 1136 432 1136
WIRE 384 1168 336 1168
WIRE 1024 1376 1024 1344
FLAG 432 288 VDD
FLAG 448 848 0
FLAG 448 1008 0
FLAG 144 736 A
IOPIN 144 736 In
FLAG 256 960 B
IOPIN 256 960 In
FLAG 352 576 VDD
FLAG 576 576 VDD
FLAG 448 1136 0
FLAG 432 1184 0
FLAG 336 368 clk_b
IOPIN 336 368 In
FLAG 336 1168 clk
IOPIN 336 1168 In
FLAG 608 720 Vout
IOPIN 608 720 Out
FLAG 1024 208 VDD
FLAG 1024 320 0
FLAG 1024 528 A
IOPIN 1024 528 In
FLAG 1024 784 B
IOPIN 1024 784 In
FLAG 1024 896 0
FLAG 1024 640 0
FLAG 1024 1168 0
FLAG 1024 1056 clk_b
IOPIN 1024 1056 In
FLAG 1024 1456 0
FLAG 1024 1344 clk
IOPIN 1024 1344 In
SYMBOL nmos4 384 800 R0
WINDOW 123 56 94 Left 2
SYMATTR Value2 l=65n w=1u
SYMATTR InstName M1
SYMATTR Value n_65
SYMBOL nmos4 384 960 R0
WINDOW 123 56 94 Left 2
SYMATTR Value2 l=65n w=1u
SYMATTR InstName M2
SYMATTR Value n_65
SYMBOL pmos4 272 672 M180
WINDOW 123 56 50 Left 2
SYMATTR Value2 l=65n w=1u
SYMATTR InstName M3
SYMATTR Value p_65
SYMBOL pmos4 496 672 M180
WINDOW 123 56 50 Left 2
SYMATTR Value2 l=65n w=1u
SYMATTR InstName M4
SYMATTR Value p_65
SYMBOL pmos4 384 448 M180
WINDOW 123 56 50 Left 2
SYMATTR Value2 l=65n w=4u
SYMATTR InstName M5
SYMATTR Value p_65
SYMBOL nmos4 384 1088 R0
WINDOW 123 56 94 Left 2
SYMATTR Value2 l=65n w=4u
SYMATTR InstName M6
SYMATTR Value n_65
SYMBOL Voltage 1024 224 R0
SYMATTR InstName V1
SYMATTR Value 1.2
SYMBOL Voltage 1024 544 R0
SYMATTR InstName V2
SYMATTR Value PWL(0 0 1u 0 1.001u 1.2 2u 1.2 2.001u 0 3u 0 3.001u 1.2 5u 1.2 5.001u 0 7u 0 7.001u 1.2 8u 1.2)
SYMBOL Voltage 1024 800 R0
SYMATTR InstName V3
SYMATTR Value PWL(0 0 3u 0 3.001u 1.2 4u 1.2 4.001u 0 5u 0 5.001u 1.2 7u 1.2 7.001u 0)
SYMBOL Voltage 1024 1072 R0
SYMATTR InstName V4
SYMATTR Value PULSE(1.2 0 0 0.01u 0.01u 10u 20u)
SYMBOL Voltage 1024 1360 R0
SYMATTR InstName V5
SYMATTR Value PULSE(0 1.2 0 0.01u 0.01u 10u 20u)
TEXT -56 72 Left 2 !.include 65nm_bulk.txt
TEXT 1176 408 Left 2 !.tran 0 20u 0 1n