Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\143c00045872_laboE1_1.asc
* Generated by LTspice 26.0.1 for Windows.
;.tran .001
;.dc V_ID -.25 .25 .01
Vpolb 0 VEE 15
Q1b Vo1 Vm N002 0 2N3904
R1 VCC N001 1k
Q1a N001 Vp N002 0 2N3904
Q2a N002 N003 VEE 0 2N3904
Iref VCC N003 1m
Vpola VCC 0 15
V_cm Vm 0 SINE({VCMdc} {VCMac} 0 0.5m) AC {VCMac} 0
V_id Vp Vm SINE(0 {VID} 10k 0.5m) AC {VID} 0
Q2b N003 N003 VEE 0 2N3904
R2 VCC Vo1 1k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.op
.ac dec 101 1 10meg
.param VCMdc=0 VCMac=1 VID=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2404 1432
WIRE -400 16 -400 -80
WIRE 288 32 80 32
WIRE 512 32 288 32
WIRE 80 48 80 32
WIRE 512 48 512 32
WIRE -400 144 -400 96
WIRE -400 192 -400 144
WIRE 512 208 512 128
WIRE 80 320 80 128
WIRE 512 320 512 208
WIRE -400 368 -400 272
WIRE -32 368 -48 368
WIRE 16 368 -32 368
WIRE 608 368 576 368
WIRE -48 480 -48 368
WIRE 80 480 80 416
WIRE 288 480 80 480
WIRE 512 480 512 416
WIRE 512 480 288 480
WIRE 800 512 800 464
WIRE -48 608 -48 560
WIRE 32 608 -48 608
WIRE 608 608 608 368
WIRE 608 608 32 608
WIRE 800 656 800 592
WIRE 800 656 672 656
WIRE 32 672 32 608
WIRE 288 704 288 480
WIRE 800 704 800 656
WIRE 672 752 672 656
WIRE 672 752 352 752
WIRE 736 752 672 752
WIRE 32 816 32 752
WIRE 288 912 288 800
WIRE 800 912 800 800
LINE Normal -144 512 -208 512 2
LINE Normal -144 704 -208 704 2
LINE Normal -144 704 -144 704 2
LINE Normal -128 704 -144 688 2
LINE Normal -144 720 -128 704 2
LINE Normal -128 512 -144 496 2
LINE Normal -144 528 -128 512 2
SYMBOL current 800 512 R0
SYMATTR InstName Iref
SYMATTR Value 1m
SYMBOL voltage 32 656 R0
WINDOW 123 -445 62 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 -654 34 Left 2
SYMATTR Value2 AC {VCMac} 0
SYMATTR Value SINE({VCMdc} {VCMac} 0 0.5m)
SYMATTR InstName V_cm
SYMBOL res 496 32 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL npn 576 320 M0
SYMATTR InstName Q1b
SYMATTR Value 2N3904
SYMBOL npn 16 320 R0
SYMATTR InstName Q1a
SYMATTR Value 2N3904
SYMBOL npn 352 704 M0
SYMATTR InstName Q2a
SYMATTR Value 2N3904
SYMBOL res 64 32 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -400 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vpola
SYMATTR Value 15
SYMBOL npn 736 704 R0
SYMATTR InstName Q2b
SYMATTR Value 2N3904
SYMBOL voltage -400 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vpolb
SYMATTR Value 15
SYMBOL voltage -48 464 R0
WINDOW 123 -316 62 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 -466 32 Left 2
SYMATTR Value2 AC {VID} 0
SYMATTR Value SINE(0 {VID} 10k 0.5m)
SYMATTR InstName V_id
FLAG 288 32 VCC
FLAG -400 -80 VCC
FLAG -400 368 VEE
FLAG -400 144 0
FLAG 288 912 VEE
FLAG 512 208 Vo1
FLAG 800 464 VCC
FLAG 608 368 Vm
FLAG -32 368 Vp
FLAG 800 912 VEE
FLAG 32 816 0
TEXT -504 1000 Left 2 !.op
TEXT -504 1032 Left 2 !.ac dec 101 1 10meg
TEXT -504 968 Left 2 !;.tran .001
TEXT -624 928 Left 2 !.param VCMdc=0 VCMac=1 VID=0
TEXT -496 1072 Left 2 !;.dc V_ID -.25 .25 .01
* Z:\home\khalils\Downloads\files\data\raw_asc\1152cc6feb50_DC_analog_to_pulse_wave.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N002 N004 0 0 NPN
R1 N004 N003 10k
R2 N001 N002 1k
V1 N001 0 5
V2 N003 0 SINE(0 5 10)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -128 -64 -128
WIRE -64 -80 -64 -128
WIRE -64 32 -64 0
WIRE 144 64 144 -128
WIRE 144 176 144 144
WIRE -32 224 -144 224
WIRE 80 224 48 224
WIRE -144 240 -144 224
WIRE -144 336 -144 320
WIRE 144 336 144 272
FLAG 144 336 0
FLAG -64 32 0
FLAG -144 336 0
SYMBOL npn 80 176 R0
SYMATTR InstName Q1
SYMBOL res 64 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 128 48 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -64 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -144 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 5 10)
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX40111.asc
* Generated by LTspice 26.0.1 for Windows.
Vee 0 Vee 2.5
Vcc Vcc 0 2.5
RL OUT 0 10k
V1 IN 0 SINE(0 50m 100k)
CL OUT 0 15p
XU1 IN OUT Vcc Vee OUT Vcc MAX40111 ;pnba In+)In-)V+)V-)OUT)SHDN
.tran 10u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX40111.asy)
.lib MAX40111.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 64 288 64 272
WIRE 416 352 416 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 64 448 64 400
WIRE 416 448 416 416
WIRE 448 448 448 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 64 544 64 528
WIRE 304 592 304 576
FLAG 720 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 416 320 Vcc
FLAG 416 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
FLAG 448 448 Vcc
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 100k)
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL MAX40111 432 400 R0
SYMATTR InstName U1
TEXT 16 632 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4251.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4251.asy)
C2 N004 IN 150n
C3 N006 IN 18n
C5 0 OUT 100
R7 N002 IN 32.4K
R6 N005 IN 20m
R1 0 N001 10K
C4 N001 IN 1
Rload 0 OUT 50
XU1 N005 IN N001 N004 N002 N003 LTC4251 ;pnba Sense)Vee)Vin)Timer)UV/OV)Gate
R2 N003 N006 10
R4 0 N002 402K
V1 IN 0 PWL(0 0 1m 0 1.001m -48 220m -48 221m -70)
C1 N002 IN 10n
M1 OUT N003 N005 N005 IRF530
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 400m
.lib LTC4251.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4692 2996
WIRE 2016 1744 2016 1728
WIRE 2640 1744 2640 1728
WIRE 2496 1760 2496 1728
WIRE 1456 1824 1456 1728
WIRE 2016 1856 2016 1824
WIRE 2272 1856 2016 1856
WIRE 2496 1856 2496 1824
WIRE 2640 1856 2640 1824
WIRE 2640 1856 2496 1856
WIRE 2768 1856 2640 1856
WIRE 2496 1872 2496 1856
WIRE 2016 1888 2016 1856
WIRE 864 1936 864 1728
WIRE 1456 1952 1456 1904
WIRE 1600 1952 1456 1952
WIRE 1824 1952 1600 1952
WIRE 2384 1952 2208 1952
WIRE 2448 1952 2384 1952
WIRE 2384 1968 2384 1952
WIRE 2272 2000 2272 1856
WIRE 1456 2032 1456 1952
WIRE 1600 2048 1600 1952
WIRE 1744 2096 1728 2096
WIRE 1824 2096 1808 2096
WIRE 2496 2096 2496 1968
WIRE 2496 2096 2208 2096
WIRE 2384 2112 2384 2048
WIRE 2496 2112 2496 2096
WIRE 864 2208 864 2016
WIRE 1456 2208 1456 2112
WIRE 1456 2208 864 2208
WIRE 1600 2208 1600 2112
WIRE 1600 2208 1456 2208
WIRE 1728 2208 1728 2096
WIRE 1728 2208 1600 2208
WIRE 2016 2208 2016 2160
WIRE 2016 2208 1728 2208
WIRE 2272 2208 2272 2064
WIRE 2272 2208 2016 2208
WIRE 2384 2208 2384 2176
WIRE 2384 2208 2272 2208
WIRE 2496 2208 2496 2192
WIRE 2496 2208 2384 2208
SYMBOL voltage 864 2032 M180
WINDOW 3 24 16 Left 2
WINDOW 0 24 96 Left 2
SYMATTR Value PWL(0 0 1m 0 1.001m -48 220m -48 221m -70)
SYMATTR InstName V1
SYMBOL cap 1808 2080 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 150n
SYMBOL res 2000 1728 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL cap 2256 2000 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 1440 2016 R0
SYMATTR InstName R7
SYMATTR Value 32.4K
SYMBOL nmos 2448 1872 R0
WINDOW 0 101 14 Right 2
WINDOW 3 140 76 Right 2
SYMATTR InstName M1
SYMATTR Value IRF530
SYMBOL res 1440 1808 R0
SYMATTR InstName R4
SYMATTR Value 402K
SYMBOL res 2624 1728 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 1584 2048 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL LTC4251 2016 2016 R0
SYMATTR InstName U1
SYMBOL res 2368 1952 R0
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL cap 2480 1760 R0
SYMATTR InstName C5
SYMATTR Value 100
SYMBOL cap 2368 2112 R0
SYMATTR InstName C3
SYMATTR Value 18n
SYMBOL res 2512 2096 M0
WINDOW 0 -38 37 Left 2
WINDOW 3 -56 78 Left 2
SYMATTR InstName R6
SYMATTR Value 20m
FLAG 864 2208 IN
FLAG 2768 1856 OUT
FLAG 864 1728 0
FLAG 1456 1728 0
FLAG 2016 1728 0
FLAG 2496 1728 0
FLAG 2640 1728 0
TEXT 2632 2176 Left 2 !.tran 400m
* Z:\home\khalils\Downloads\files\data\raw_asc\43174c9cc905_Week1_Ex1C.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 nch l={factor*2u} w={factor*4u}
VGS N002 0 1.8
VDS N001 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib 'C:\Program Files\LTC\LTspiceXVII\lib\cmp\log018.l' TT
.dc VGS 0 1.8 1m
.step param factor list 1 0.5 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 416 240 208 240
WIRE 208 336 208 240
WIRE 304 384 208 384
WIRE 160 416 -48 416
WIRE 416 416 416 240
WIRE -48 432 -48 416
WIRE -48 576 -48 512
WIRE 208 576 208 432
WIRE 208 576 -48 576
WIRE 304 576 304 384
WIRE 304 576 208 576
WIRE 416 576 416 496
WIRE 416 576 304 576
WIRE 208 608 208 576
FLAG 208 608 0
SYMBOL nmos4 160 336 R0
SYMATTR InstName M1
SYMATTR Value nch
SYMATTR Value2 l={factor*2u} w={factor*4u}
SYMBOL voltage -48 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 1.8
SYMBOL voltage 416 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 1.8
TEXT -32 120 Left 2 !.lib 'C:\\Program Files\\LTC\\LTspiceXVII\\lib\\cmp\\log018.l' TT
TEXT -32 168 Left 2 !.dc VGS 0 1.8 1m
TEXT -24 200 Left 2 !.step param factor list 1 0.5 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2965.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC2965.asy)
R4 N001 N004 100K
V2 N001 0 5
XU1 IN N002 N003 N005 0 0 0 N004 LTC2965 ;pnba Vin)Ref)INH)INL)PS)RS)GND)OUT
R1 N003 N005 91K
R3 N005 0 909K
V1 IN 0 PWL(0 0 20u 0 10m 24.5 20m 0)
R2 N002 N003 200K
.tran 25m startup
.lib LTC2965.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 -112 -320 -112
WIRE -320 -96 -320 -112
WIRE 224 -16 224 -112
WIRE 576 -16 448 -16
WIRE -320 0 -320 -16
WIRE 576 0 576 -16
WIRE 32 16 -80 16
WIRE -80 32 -80 16
WIRE 448 32 448 -16
WIRE 32 64 32 16
WIRE 96 64 32 64
WIRE 576 96 576 80
WIRE -80 128 -80 112
WIRE 32 128 -80 128
WIRE -80 144 -80 128
WIRE 32 144 32 128
WIRE 96 144 32 144
WIRE 448 144 448 112
WIRE 448 144 352 144
WIRE 96 224 32 224
WIRE -80 240 -80 224
WIRE 32 240 32 224
WIRE 32 240 -80 240
WIRE -80 256 -80 240
WIRE 144 336 144 320
WIRE 224 336 224 320
WIRE 304 336 304 320
WIRE -80 352 -80 336
SYMBOL voltage -320 -112 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 20u 0 10m 24.5 20m 0)
SYMBOL res 432 16 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL res -96 240 R0
SYMATTR InstName R3
SYMATTR Value 909K
SYMBOL voltage 576 -16 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL LTC2965 224 144 R0
SYMATTR InstName U1
SYMBOL res -96 128 R0
SYMATTR InstName R1
SYMATTR Value 91K
SYMBOL res -96 16 R0
SYMATTR InstName R2
SYMATTR Value 200K
FLAG 304 336 0
FLAG -80 352 0
FLAG -320 0 0
FLAG 576 96 0
FLAG -320 -112 IN
FLAG 144 336 0
FLAG 224 336 0
TEXT 504 248 Left 2 !.tran 25m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7182-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7182-5.0.asy)
V2 N001 0 PULSE(0 2 200u 1n 1n 10m)
R1 OUT 0 50
C1 IN 0 2.2
V1 IN 0 -8
XU1 OUT MP_01 MP_02 N001 MP_03 0 IN ADP7182-x.x Rset=1Meg ;pnba Vout)))EN))GND)Vin
C2 OUT 0 2.2
.tran 1m
.lib ADP7182-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 -80 -48
WIRE 112 -48 32 -48
WIRE 432 -48 368 -48
WIRE 544 -48 432 -48
WIRE -80 -32 -80 -48
WIRE 32 -32 32 -48
WIRE 432 -32 432 -48
WIRE 544 -32 544 -48
WIRE -80 64 -80 48
WIRE 32 64 32 32
WIRE 432 64 432 32
WIRE 544 64 544 48
WIRE 112 144 32 144
WIRE 32 160 32 144
WIRE 32 256 32 240
WIRE 240 256 240 208
SYMBOL cap 16 -32 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL ADP7182-5.0 240 48 R0
SYMATTR InstName U1
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL res 528 -48 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value -8
SYMBOL voltage 32 144 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
FLAG -80 64 0
FLAG 32 64 0
FLAG 432 64 0
FLAG 32 256 0
FLAG 240 256 0
FLAG 544 64 0
FLAG 32 -48 IN
FLAG 432 -48 OUT
TEXT 528 248 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\c6b1ca35c5d5_osc_impedance.asc
* Generated by LTspice 26.0.1 for Windows.
* Run ".ac analysis" and plot "Z", (Vgate/I(I1)), in "cartesion coordinate" mode.\nNote that as {R} is decreased, the real part of Z becomes more and more negative.\nAs {R} is further decreased, the real part of Z becomes more positive. A this point,\nthe oscillator fails to start.\nRun ".transient analysis" to see what effect decreasing {R} has on oscillator startup.
;tran 0 50uS 0S 200pS
C1 Vgate N002 31.8pF
J1 N001 Vgate N002 MPF102
V1 N001 0 9V
R2 Vgate 0 {R}
I2 N002 0 1mA
I1 0 Vgate AC 1uA
L2 Vgate 0 159nH Rser=0
C2 N002 0 31.8pF
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.ac oct 10k 98e6 102e6
.step param R 3k 1.5k 500
.meas ac Re find re(V(vgate)/I(I1)) at 100e6
.meas ac Im find im(V(vgate)/I(I1)) at 100e6
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 884
WIRE -736 416 -736 272
WIRE -736 624 -736 496
WIRE -656 272 -736 272
WIRE -656 272 -656 208
WIRE -576 272 -656 272
WIRE -576 416 -576 272
WIRE -576 624 -736 624
WIRE -576 624 -576 496
WIRE -432 272 -576 272
WIRE -432 416 -432 272
WIRE -432 624 -576 624
WIRE -432 624 -432 496
WIRE -304 272 -432 272
WIRE -304 304 -304 272
WIRE -304 416 -304 368
WIRE -304 480 -304 416
WIRE -304 624 -432 624
WIRE -304 624 -304 544
WIRE -224 272 -304 272
WIRE -176 208 -176 176
WIRE -176 416 -304 416
WIRE -176 416 -176 304
WIRE -176 480 -176 416
WIRE -176 624 -304 624
WIRE -176 624 -176 560
WIRE 0 176 -176 176
WIRE 0 288 0 176
WIRE 0 624 -176 624
WIRE 0 624 0 368
WIRE 0 656 0 624
SYMBOL njf -224 208 R0
SYMATTR InstName J1
SYMATTR Value MPF102
SYMBOL ind -448 400 R0
SYMATTR InstName L2
SYMATTR Value 159nH
SYMATTR SpiceLine Rser=0
SYMBOL cap -320 304 R0
SYMATTR InstName C1
SYMATTR Value 31.8pF
SYMBOL current -176 480 R0
WINDOW 123 24 116 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 43 47 Left 0
SYMATTR Value 1mA
SYMATTR InstName I2
SYMBOL cap -320 480 R0
SYMATTR InstName C2
SYMATTR Value 31.8pF
SYMBOL current -736 496 R180
WINDOW 123 -101 105 Left 0
WINDOW 3 24 88 Invisible 0
SYMATTR Value2 AC 1uA
SYMATTR Value ""
SYMATTR InstName I1
SYMBOL voltage 0 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9V
SYMBOL res -592 400 R0
SYMATTR InstName R2
SYMATTR Value {R}
FLAG 0 656 0
FLAG -656 208 Vgate
TEXT -1000 224 Left 0 !;tran 0 50uS 0S 200pS
TEXT -1000 272 Left 0 !.ac oct 10k 98e6 102e6
TEXT -1024 320 Left 0 !.step param R 3k 1.5k 500
TEXT -816 -80 Left 0 ;Run ".ac analysis" and plot "Z", (Vgate/I(I1)), in "cartesion coordinate" mode.\nNote that as {R} is decreased, the real part of Z becomes more and more negative.\nAs {R} is further decreased, the real part of Z becomes more positive. A this point,\nthe oscillator fails to start.\nRun ".transient analysis" to see what effect decreasing {R} has on oscillator startup.
TEXT -1336 392 Left 0 !.meas ac Re find re(V(vgate)/I(I1)) at 100e6\n.meas ac Im find im(V(vgate)/I(I1)) at 100e6
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1421.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1421.asy)
V4 N003 0 pulse(0 3.3 0 1u 1u 5m 10m)
R1 N002 0 300
V3 N001 0 10
XU1 N003 N002 N001 -V 0 +V ADG1421 ;pnba IN)D)S)Vss)GND)Vdd
V2 -V 0 -15
V1 +V 0 15
C1 N002 0 35p
.tran 30m
.lib ADG1421.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -112 -112 -112 -128
WIRE -448 -80 -448 -96
WIRE -304 -48 -336 -48
WIRE -208 -48 -224 -48
WIRE 16 -48 -16 -48
WIRE 112 -48 16 -48
WIRE 16 -16 16 -48
WIRE 112 0 112 -48
WIRE -448 16 -448 0
WIRE -208 16 -304 16
WIRE 16 80 16 64
WIRE 112 80 112 64
WIRE -304 96 -304 16
WIRE -448 112 -448 96
WIRE -160 144 -160 128
WIRE -64 144 -64 128
WIRE -448 208 -448 192
WIRE -304 240 -304 176
SYMBOL cap 96 0 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL voltage -208 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL ADG1421 -112 0 R0
SYMATTR InstName U1
SYMBOL res 0 -32 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -304 80 R0
WINDOW 3 19 116 Left 2
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMATTR InstName V4
SYMBOL voltage -448 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -448 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
FLAG -448 208 0
FLAG -448 16 0
FLAG -448 -96 +V
FLAG -448 96 -V
FLAG -336 -48 0
FLAG -160 144 -V
FLAG -112 -128 +V
FLAG -64 144 0
FLAG -304 240 0
FLAG 16 80 0
FLAG 112 80 0
TEXT 8 248 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4940.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4940.asy)
RG2 N004 0 1k
G1 0 OUT_DIFF OUT- OUT+ -1m
RG1 N001 IN 1k
VS- N005 0 -2.5
R1 OUT_DIFF 0 1k
Vocm N003 0 0
XU1 NC_01 NC_02 N001 N004 N002 N005 OUT+ OUT- N003 NC_03 ADA4940 ;pnba 1)2)3)4)5)6)7)8)9)10
RF2 OUT+ N004 1k
RF1 OUT- N001 1k
Vin IN 0 PULSE(-50m 50m 20n 1n 1n 100n)
RL2 OUT+ 0 499
RL1 0 OUT- 499
VS+ N002 0 2.5
.tran 150n
.lib ADA4940.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 956 680
WIRE 224 -144 80 -144
WIRE 400 -144 304 -144
WIRE 160 -64 144 -64
WIRE 320 -64 240 -64
WIRE 320 -48 320 -64
WIRE 448 32 448 0
WIRE 224 48 176 48
WIRE 320 48 304 48
WIRE 320 64 320 48
WIRE 144 80 144 -64
WIRE 176 80 176 48
WIRE 720 96 624 96
WIRE -32 128 -320 128
WIRE 80 128 80 -144
WIRE 80 128 48 128
WIRE 112 128 80 128
WIRE 624 128 624 96
WIRE 720 128 720 96
WIRE -320 144 -320 128
WIRE 400 144 400 -144
WIRE 400 144 272 144
WIRE 448 144 448 112
WIRE 448 144 400 144
WIRE 528 144 448 144
WIRE 576 144 528 144
WIRE -32 192 -64 192
WIRE 80 192 48 192
WIRE 112 192 80 192
WIRE 400 208 272 208
WIRE 448 208 400 208
WIRE 528 208 448 208
WIRE 576 208 576 192
WIRE 576 208 528 208
WIRE -64 224 -64 192
WIRE 448 240 448 208
WIRE 624 240 624 208
WIRE 720 240 720 208
WIRE -320 256 -320 224
WIRE 144 352 144 272
WIRE 160 352 144 352
WIRE 304 352 240 352
WIRE 448 352 448 320
WIRE 304 368 304 352
WIRE 80 448 80 192
WIRE 224 448 80 448
WIRE 400 448 400 208
WIRE 400 448 304 448
SYMBOL voltage 208 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName Vocm
SYMATTR Value 0
SYMBOL res 64 112 R90
WINDOW 0 -26 54 VBottom 2
WINDOW 3 -28 55 VTop 2
SYMATTR InstName RG1
SYMATTR Value 1k
SYMBOL ADA4940 144 176 R0
SYMATTR InstName U1
SYMBOL voltage 144 -64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName VS+
SYMATTR Value 2.5
SYMBOL voltage 144 352 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName VS-
SYMATTR Value -2.5
SYMBOL res 320 432 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RF2
SYMATTR Value 1k
SYMBOL res 432 224 R0
SYMATTR InstName RL2
SYMATTR Value 499
SYMBOL voltage -320 128 R0
WINDOW 0 76 31 Right 2
WINDOW 3 -124 -42 Left 2
WINDOW 123 90 88 Right 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value PULSE(-50m 50m 20n 1n 1n 100n)
SYMBOL g 624 112 R0
SYMATTR InstName G1
SYMATTR Value -1m
SYMBOL res 64 176 R90
WINDOW 0 65 57 VBottom 2
WINDOW 3 65 58 VTop 2
SYMATTR InstName RG2
SYMATTR Value 1k
SYMBOL res 704 112 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 432 16 R0
SYMATTR InstName RL1
SYMATTR Value 499
SYMBOL res 320 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 36 57 VTop 2
SYMATTR InstName RF1
SYMATTR Value 1k
FLAG 448 352 0
FLAG 720 96 OUT_DIFF
FLAG 320 64 0
FLAG 320 -48 0
FLAG 304 368 0
FLAG 448 0 0
FLAG -64 224 0
FLAG -320 128 IN
FLAG -320 256 0
FLAG 528 144 OUT-
FLAG 528 208 OUT+
FLAG 624 240 0
FLAG 720 240 0
TEXT 520 416 Left 2 !.tran 150n
* Z:\home\khalils\Downloads\files\data\raw_asc\0787bf4e2468_Level9Comparison.asc
* Generated by LTspice 26.0.1 for Windows.
QVBIC N003 N001 0 0 BC856_PHI_3
QGP N002 N001 0 0 BC856_PHI_1
R3 N003 0 1Gig
V1 N001 0 1
R1 N002 0 1Gig
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.MODEL BC856_PHI_1
.INC GP-BC856_PHI.mod
.dc V1 5 6 100m
.TEMP -55 +25 +150
.PARAM tnom=25
.PARAM Vbbe=5 ibbe=10u
.LIB GP-BC856_PHI.par
.MODEL BC856_PHI_3
.INC GP2VBIC.mod
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5756 2000
WIRE 1840 704 1680 704
WIRE 2064 704 1840 704
WIRE 1936 720 1920 720
WIRE 2160 720 2144 720
WIRE 1936 736 1936 720
WIRE 2160 736 2160 720
WIRE 1840 768 1840 704
WIRE 1856 768 1840 768
WIRE 2064 768 2064 704
WIRE 2080 768 2064 768
WIRE 1680 784 1680 704
WIRE 1920 832 1920 816
WIRE 2144 832 2144 816
WIRE 1680 928 1680 864
WIRE 1920 928 1920 912
WIRE 2144 928 2144 912
SYMBOL res 2128 816 R0
SYMATTR InstName R3
SYMATTR Value 1Gig
SYMBOL pnp 2080 816 M180
SYMATTR InstName QVBIC
SYMATTR Value BC856_PHI_3
SYMBOL voltage 1680 768 R0
WINDOW 3 24 104 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 1
SYMATTR InstName V1
SYMBOL res 1904 816 R0
SYMATTR InstName R1
SYMATTR Value 1Gig
SYMBOL pnp 1856 816 M180
SYMATTR InstName QGP
SYMATTR Value BC856_PHI_1
FLAG 1936 736 0
FLAG 1680 928 0
FLAG 1920 928 0
FLAG 2160 736 0
FLAG 2144 928 0
TEXT 1680 1040 Left 0 !.MODEL BC856_PHI_1\n.INC GP-BC856_PHI.mod
TEXT 1680 1008 Left 0 !.dc V1 5 6 100m
TEXT 1680 976 Left 0 !.TEMP -55 +25 +150
TEXT 2128 960 Left 0 !.PARAM tnom=25\n.PARAM Vbbe=5 ibbe=10u \n.LIB GP-BC856_PHI.par\n.MODEL BC856_PHI_3\n.INC GP2VBIC.mod