* Z:\home\khalils\Downloads\files\data\raw_asc\0773169c8a00_body_diode.asc
* Generated by LTspice 26.0.1 for Windows.
*Lg gate g1 7n
* I had to disable the parasitic inductors of this model.\nThese inductors causes convergence problems.
* The Trr datasheet spec for the body diode reverse recovery\nwas specified with a forward current of 20A to something negative\nwith a slope of 100A/us.
+CJO=11610.43p Vj=0.75 M=0.782 CGS=2350p N=1 IS=1.00E-07 RB=0.0244 tt=750n)
V2 N003 0 480
Maux2 b d g2 g2 sw
Rpar2 d2 a 10Meg
Mr d1 d2a d1a d1a MVDR W=1u L=1u
D1 d N001 clamp
Cgs g2 s2 2.51n
Rx d2a d1a 1m
Eaux c a d2 g2 1
Rs2 s1 s2 1m
I2 dVDmos 0 PWL(0 {is} {1u*is/didt} {is} +{2u*is/didt} {-is} +{2u*is/didt} {-3*is})
Rdiode d1 21 4.9m TC=6m
R1 N002 0 1m
Dbd s2 d2 Dbt
Cox b d2 5.53n
XM1 d N002 0 spa20n60c3_l0 ;pnba D)G)S
Rd d2 d1a 0.136 TC=10m
Rd2 drain d1 3m
M2 dVDmos N004 0 0 20n60c3
Dbody s2 21 DBODY
Cds1 s2 d2 67.3p
Eaux2 d g2 d2 g2 -1
Rg gate g2 0.54
R2 N004 0 1m
Rpar b d2 1Meg
M1 d2 g2 s2 s2 DMOS L=1u W=1u
Rs source s1 1m
Maux g2 c a a sw
V1 N001 0 480
Dgd a d2 DGD
I1 d 0 PWL(0 {is} {1u*is/didt} {is} +{2u*is/didt} {-is} +{2u*is/didt} {-3*is})
D2 dVDmos N003 clamp
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL 20N60C3 VDMOS(KP=17.5 RS=0.017 RD=0.134 RG=0.54 VTO=3.5 CGDMAX=5560p CGDMIN=7p
.tran 0 1u 0 1n
.model clamp d(ron=1m vfwd=0)
.param is=20 didt=100 ;didt in A/us
.option plotwinsize=0
.SUBCKT SPA20N60C3_L0 drain gate source
.MODEL DMOS NMOS ( KP= 34.663 VTO=3.85 THETA=0 VMAX=1.5e5 ETA=0 LEVEL=3)
.MODEL MVDR NMOS (KP=61.17 VTO=-1 LAMBDA=0.1)
.MODEL Dbt D(BV=600 M=0.8 CJO=6.95n VJ=0.5V)
.MODEL DBODY D(IS=14.5p N=1.15 RS=7u EG=1.12 TT=750n)
.MODEL sw NMOS(VTO=0 KP=10 LEVEL=1)
.MODEL DGD D(M=1.2 CJO=5.53n VJ=0.5)
.ENDS SPA20N60C3_L0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2916 916
WIRE 176 176 112 176
WIRE 272 176 176 176
WIRE 320 176 272 176
WIRE 400 176 384 176
WIRE 112 208 112 176
WIRE 272 224 272 176
WIRE 400 224 400 176
WIRE 32 240 -32 240
WIRE -32 256 -32 240
WIRE 32 288 32 240
WIRE 64 288 32 288
WIRE 112 336 112 304
WIRE 112 336 -32 336
WIRE 272 336 272 304
WIRE 272 336 112 336
WIRE 400 336 400 304
WIRE 400 336 272 336
WIRE 112 368 112 336
WIRE 176 560 112 560
WIRE 272 560 176 560
WIRE 320 560 272 560
WIRE 400 560 384 560
WIRE 112 592 112 560
WIRE 272 608 272 560
WIRE 400 608 400 560
WIRE 32 624 -32 624
WIRE -32 640 -32 624
WIRE 32 672 32 624
WIRE 64 672 32 672
WIRE 112 720 112 688
WIRE 112 720 -32 720
WIRE 272 720 272 688
WIRE 272 720 112 720
WIRE 400 720 400 688
WIRE 400 720 272 720
WIRE 112 752 112 720
SYMBOL current 272 224 R0
WINDOW 3 -15 129 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PWL(0 {is} {1u*is/didt} {is} +{2u*is/didt} {-is} +{2u*is/didt} {-3*is})
SYMATTR InstName I1
SYMBOL diode 320 576 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D2
SYMATTR Value clamp
SYMBOL voltage 400 592 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 480
SYMBOL diode 320 192 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value clamp
SYMBOL current 272 608 R0
WINDOW 3 -15 129 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PWL(0 {is} {1u*is/didt} {is} +{2u*is/didt} {-is} +{2u*is/didt} {-3*is})
SYMATTR InstName I2
SYMBOL nmos 64 208 R0
SYMATTR InstName M1
SYMATTR Value spa20n60c3_l0
SYMATTR Prefix x
SYMBOL voltage 400 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 480
SYMBOL res -48 624 R0
SYMATTR InstName R2
SYMATTR Value 1m
SYMBOL res -48 240 R0
SYMATTR InstName R1
SYMATTR Value 1m
SYMBOL nmos 64 592 R0
SYMATTR InstName M2
SYMATTR Value 20n60c3
FLAG 112 368 0
FLAG 176 176 d
FLAG 112 752 0
FLAG 176 560 dVDmos
TEXT -40 448 Left 0 !.MODEL 20N60C3 VDMOS(KP=17.5 RS=0.017 RD=0.134 RG=0.54 VTO=3.5 CGDMAX=5560p CGDMIN=7p \n+CJO=11610.43p Vj=0.75 M=0.782 CGS=2350p N=1 IS=1.00E-07 RB=0.0244 tt=750n)
TEXT 344 32 Left 0 !.tran 0 1u 0 1n
TEXT 344 -40 Left 0 !.model clamp d(ron=1m vfwd=0)
TEXT 344 -16 Left 0 !.param is=20 didt=100 ;didt in A/us
TEXT 344 8 Left 0 !.option plotwinsize=0
TEXT 1056 -24 Left 0 !.SUBCKT SPA20N60C3_L0  drain  gate  source\n \n*Lg     gate  g1    7n\nRd2    drain d1    3m\nRs     source s1   1m\nRs2      s1    s2   1m\n \nRg     gate    g2     0.54\nM1      d2    g2    s2    s2    DMOS    L=1u   W=1u\n.MODEL DMOS NMOS ( KP= 34.663  VTO=3.85  THETA=0  VMAX=1.5e5  ETA=0  LEVEL=3)\nRd     d2    d1a    0.136 TC=10m\n.MODEL MVDR NMOS (KP=61.17 VTO=-1   LAMBDA=0.1)\nMr d1 d2a d1a d1a MVDR W=1u L=1u\nRx d2a d1a 1m\nCds1 s2 d2 67.3p\nDbd     s2    d2    Dbt\n.MODEL     Dbt    D(BV=600   M=0.8  CJO=6.95n  VJ=0.5V)\nDbody   s2   21    DBODY\n.MODEL DBODY  D(IS=14.5p  N=1.15  RS=7u  EG=1.12  TT=750n)\nRdiode  d1  21    4.9m TC=6m\n \n.MODEL   sw    NMOS(VTO=0  KP=10   LEVEL=1)\nMaux      g2   c    a    a   sw\nMaux2     b    d    g2    g2   sw\nEaux      c    a    d2    g2   1\nEaux2     d    g2   d2    g2   -1\nCox       b    d2   5.53n\n.MODEL     DGD    D(M=1.2   CJO=5.53n   VJ=0.5)\nRpar      b    d2   1Meg\nDgd       a    d2   DGD\nRpar2     d2   a    10Meg\nCgs     g2    s2    2.51n\n \n.ENDS  SPA20N60C3_L0
TEXT 1304 56 Left 0 ;I had to disable the parasitic inductors of this model.\nThese inductors causes convergence problems.
TEXT -48 72 Left 0 ;The Trr datasheet spec for the body diode reverse recovery\nwas specified with a forward current of 20A to something negative\nwith a slope of 100A/us.