* Z:\home\khalils\Downloads\files\data\raw_asc\23bd7c30751d_Fig16_8.asc
* Generated by LTspice 26.0.1 for Windows.
* Bitline to array0
* Bitline to array1
* Plot Eq, bitline0, and bitline1
Veq Eq 0 PULSE 0 1 5n 0 0 4n
M3 bitline0 bitline1 N001 0 N_50n l=50n w=500n
M5 bitline0 Eq VDDby2 0 N_50n l=50n w=500n
M2 bitline1 bitline0 N001 0 N_50n l=50n w=500n
Ccol1 bitline1 0 100f
M1 N001 sense_N 0 0 N_50n l=50n w=500n
VDDby2 VDDby2 0 500mV
Vsn sense_N 0 0
Ccol0 bitline0 0 100f
M6 VDDby2 Eq bitline1 0 N_50n l=50n w=500n
VDD VDD 0 1
M4 bitline1 Eq bitline0 0 N_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.ic v(bitline0)=250m v(bitline1)=750m
.tran 10n uic
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1356 680
WIRE 192 -528 192 -560
WIRE 320 -528 320 -560
WIRE 768 -464 768 -752
WIRE 912 -464 768 -464
WIRE 1120 -464 1120 -752
WIRE 1120 -464 1008 -464
WIRE 192 -416 192 -448
WIRE 320 -416 320 -448
WIRE 640 -416 608 -416
WIRE 880 -416 640 -416
WIRE 928 -416 880 -416
WIRE 1056 -416 928 -416
WIRE 1296 -416 1056 -416
WIRE 880 -400 880 -416
WIRE 1056 -400 1056 -416
WIRE 768 -368 768 -464
WIRE 768 -352 768 -368
WIRE 800 -352 768 -352
WIRE 944 -352 896 -352
WIRE 976 -352 944 -352
WIRE 1120 -352 1120 -464
WIRE 1120 -352 1072 -352
WIRE 1120 -336 1120 -352
WIRE 768 -304 768 -352
WIRE 768 -304 688 -304
WIRE 944 -304 944 -352
WIRE 1120 -304 1120 -336
WIRE 1200 -304 1120 -304
WIRE 944 -288 944 -304
WIRE 768 -256 768 -304
WIRE 864 -256 768 -256
WIRE 1120 -256 1120 -304
WIRE 1120 -256 1040 -256
WIRE 304 -240 304 -272
WIRE 768 -240 768 -256
WIRE 1120 -240 1120 -256
WIRE 208 -224 208 -240
WIRE 1008 -176 864 -256
WIRE 848 -160 1040 -256
WIRE 848 -160 816 -160
WIRE 1040 -160 1008 -176
WIRE 1072 -160 1040 -160
WIRE 208 -128 208 -144
WIRE 304 -128 304 -160
WIRE 768 -96 768 -144
WIRE 960 -96 768 -96
WIRE 1120 -96 1120 -144
WIRE 1120 -96 960 -96
WIRE 960 -80 960 -96
WIRE 656 0 608 0
WIRE 912 0 656 0
SYMBOL cap 1184 -304 R0
WINDOW 3 43 46 Left 0
SYMATTR Value 100f
SYMATTR InstName Ccol1
SYMBOL nmos4 800 -400 M90
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M5
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 320 -544 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 41 53 Left 0
SYMATTR Value 500mV
SYMATTR InstName VDDby2
SYMBOL nmos4 1072 -240 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M2
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 192 -544 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL voltage 304 -256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 41 53 Left 0
SYMATTR Value 0
SYMATTR InstName Vsn
SYMBOL nmos4 976 -400 M90
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M6
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 912 -80 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 208 -240 R0
WINDOW 0 -72 21 Left 0
WINDOW 3 -99 147 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Veq
SYMATTR Value PULSE 0 1 5n 0 0 4n
SYMBOL nmos4 1008 -416 M270
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M4
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL cap 704 -304 M0
WINDOW 3 43 46 Left 0
SYMATTR Value 100f
SYMATTR InstName Ccol0
SYMBOL nmos4 816 -240 M0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M3
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
FLAG 208 -128 0
FLAG 208 -240 Eq
FLAG 960 -32 0
FLAG 192 -416 0
FLAG 192 -560 VDD
FLAG 320 -416 0
FLAG 320 -560 VDDby2
FLAG 304 -128 0
FLAG 304 -272 sense_N
FLAG 1120 -192 0
FLAG 768 -192 0
FLAG 960 -464 0
FLAG 848 -352 0
FLAG 1024 -352 0
FLAG 640 -416 Eq
FLAG 944 -304 VDDby2
FLAG 656 0 sense_N
FLAG 960 16 0
FLAG 1200 -240 0
FLAG 688 -240 0
FLAG 768 -368 bitline0
FLAG 1120 -336 bitline1
TEXT 120 -16 Left 0 !.include cmosedu_models.txt
TEXT 752 -576 VLeft 0 ;Bitline to array0
TEXT 1136 -576 VLeft 0 ;Bitline to array1
TEXT 120 8 Left 0 !.ic v(bitline0)=250m v(bitline1)=750m
TEXT 120 -40 Left 0 !.tran 10n uic
TEXT 360 -680 Left 0 ;Plot Eq, bitline0, and bitline1