Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1763-1.25.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1763-1.25.asy)
C2 N003 0 10n
C3 N002 0 1
V1 IN 0 1.6
R1 OUT 0 .6
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1763 Radj=8333.33 m=1.5 ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
R2 N001 IN 50K
C4 OUT 0 10
C1 N004 0 1
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1028 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL ADP1763-1.25 224 176 R0
SYMATTR InstName U1
SYMATTR Value2 ADP1763 Radj=8333.33 m=1.5
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
SYMBOL voltage -128 -32 R0
SYMATTR InstName V1
SYMATTR Value 1.6
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 432 384 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2960-4.asc
* Generated by LTspice 26.0.1 for Windows.
R1 IN N001 118K
R2 N005 0 182K
C1 OUT 0 1
Vbat IN 0 PWL(0 0 10m 14 200 20 220 14 300 14 400 0)
R3 IN N003 10K
R4 N004 N005 68K
R5 N001 N004 7.32Meg
XU1 N003 OUT _FAULT N002 0 N002 N004 N005 LTC2960-4 ;pnba Vin)DVCC)_RST)OUT)GND)_MR)ADJ)IN-
XU2 IN OUT OUT 0 IN LT3008-5 ;pnba IN)OUT)Sense)GND)_SHDN
C2 IN 0 1
* Window Comparator for High Voltage Input
* 6V to 8.4V
* 5V
.tran 400
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3008-5.asy)
.lib LT3009.lib
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC2960-4.asy)
.lib LTC2960-4.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3200 984
WIRE -2832 -3712 -2944 -3712
WIRE -2352 -3712 -2832 -3712
WIRE -2192 -3712 -2352 -3712
WIRE -2064 -3712 -2192 -3712
WIRE -1936 -3712 -2064 -3712
WIRE -1904 -3712 -1936 -3712
WIRE -1568 -3712 -1616 -3712
WIRE -1456 -3712 -1568 -3712
WIRE -2944 -3696 -2944 -3712
WIRE -1456 -3696 -1456 -3712
WIRE -2352 -3680 -2352 -3712
WIRE -2192 -3680 -2192 -3712
WIRE -2064 -3664 -2064 -3712
WIRE -1936 -3616 -1936 -3712
WIRE -1904 -3616 -1936 -3616
WIRE -1568 -3616 -1568 -3712
WIRE -1568 -3616 -1616 -3616
WIRE -1456 -3616 -1456 -3632
WIRE -2944 -3600 -2944 -3616
WIRE -2192 -3600 -2192 -3616
WIRE -2352 -3584 -2352 -3600
WIRE -1936 -3568 -2192 -3568
WIRE -2064 -3536 -2064 -3584
WIRE -1760 -3520 -1760 -3552
WIRE -2352 -3488 -2352 -3504
WIRE -2224 -3488 -2352 -3488
WIRE -2192 -3488 -2192 -3568
WIRE -2176 -3488 -2192 -3488
WIRE -1568 -3488 -1568 -3616
WIRE -1568 -3488 -1952 -3488
WIRE -2352 -3472 -2352 -3488
WIRE -2352 -3376 -2352 -3392
WIRE -2176 -3376 -2352 -3376
WIRE -1936 -3376 -1936 -3568
WIRE -1936 -3376 -1952 -3376
WIRE -2352 -3344 -2352 -3376
WIRE -2224 -3264 -2224 -3488
WIRE -2176 -3264 -2224 -3264
WIRE -1904 -3264 -1952 -3264
WIRE -2352 -3248 -2352 -3264
WIRE -2064 -3200 -2064 -3216
FLAG -2064 -3200 0
FLAG -1456 -3616 0
FLAG -2352 -3248 0
FLAG -1904 -3264 _FAULT
FLAG -1456 -3712 OUT
FLAG -2944 -3600 0
FLAG -1760 -3520 0
FLAG -2832 -3712 IN
FLAG -2192 -3600 0
SYMBOL res -2368 -3696 R0
SYMATTR InstName R1
SYMATTR Value 118K
SYMBOL res -2368 -3360 R0
SYMATTR InstName R2
SYMATTR Value 182K
SYMBOL cap -1472 -3696 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -2944 -3712 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value PWL(0 0 10m 14 200 20 220 14 300 14 400 0)
SYMATTR InstName Vbat
SYMBOL res -2080 -3680 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res -2368 -3488 R0
SYMATTR InstName R4
SYMATTR Value 68K
SYMBOL res -2368 -3600 R0
SYMATTR InstName R5
SYMATTR Value 7.32Meg
SYMBOL LTC2960-4 -2064 -3376 R0
SYMATTR InstName U1
SYMBOL PowerProducts\\LT3008-5 -1760 -3664 R0
SYMATTR InstName U2
SYMBOL cap -2208 -3680 R0
SYMATTR InstName C2
SYMATTR Value 1
TEXT -2088 -3784 Bottom 2 ;Window Comparator for High Voltage Input
TEXT -2832 -3736 Bottom 2 ;6V to 8.4V
TEXT -1456 -3736 Bottom 2 ;5V
TEXT -1632 -3240 Left 2 !.tran 400
* Z:\tmp\asc_dec_bjh7r6w2\0f932bb89804_PMOS_OPEN_CKT_DETECT_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R9 N002 N008 5k
R3 Vsw N007 100
M1 N006 N004 24V 24V BSS84
M3 N005 N008 N010 N010 Si7336ADP
R6 N004 0 10k
Rload N002 N012 100
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1768 680
WIRE 1216 -384 1056 -384
WIRE 1424 -384 1296 -384
WIRE 1680 -384 1424 -384
WIRE -192 -336 -192 -368
WIRE 0 -224 0 -368
WIRE -272 -208 -352 -208
WIRE -128 -208 -192 -208
WIRE -48 -208 -128 -208
WIRE 1424 -176 1424 -384
WIRE -128 -160 -128 -208
WIRE 1280 -128 1056 -128
WIRE 1680 -128 1680 -384
WIRE 1280 -96 1280 -128
WIRE 0 -80 0 -128
WIRE -128 -32 -128 -80
WIRE 240 -32 176 -32
WIRE 400 -32 320 -32
WIRE 1424 -16 1424 -96
WIRE 1424 -16 1328 -16
WIRE 320 16 320 -32
WIRE 1424 16 1424 -16
WIRE 0 32 0 0
WIRE 1280 32 1280 0
WIRE 1280 32 1056 32
WIRE 1424 112 1424 96
WIRE 1680 112 1680 -48
WIRE 320 144 320 96
SYMBOL res 1408 -192 R0
SYMATTR InstName R9
SYMATTR Value 5k
SYMBOL res 224 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100
SYMBOL pmos -48 -128 M180
SYMATTR InstName M1
SYMATTR Value BSS84
SYMBOL nmos 1328 -96 M0
SYMATTR InstName M3
SYMATTR Value Si7336ADP
SYMBOL res -144 -176 R0
SYMATTR InstName R6
SYMATTR Value 10k
SYMBOL res 1664 -144 R0
SYMATTR InstName Rload
SYMATTR Value 100
FLAG 320 144 0
FLAG -128 -32 0
FLAG 176 -32 Vsw
FLAG -192 -336 0
FLAG 0 -368 24V
* Z:\home\khalils\Downloads\files\data\raw_asc\314b8ec9b8df_circuito_4_lab_1.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N001 A D
D3 0 A D
V1 N001 0 SINE(0 10 10)
D2 B 0 D
R1 B A 2.2k
D4 B N001 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 200ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 64 16 64
WIRE 432 64 208 64
WIRE 16 144 16 64
WIRE 208 160 208 128
WIRE 288 160 208 160
WIRE 432 160 432 128
WIRE 432 160 368 160
WIRE 208 176 208 160
WIRE 432 176 432 160
WIRE 16 256 16 224
WIRE 208 256 208 240
WIRE 208 256 16 256
WIRE 432 256 432 240
WIRE 432 256 208 256
WIRE 16 272 16 256
SYMBOL diode 224 240 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMBOL diode 192 64 R0
SYMATTR InstName D1
SYMBOL diode 416 176 R0
SYMATTR InstName D2
SYMBOL voltage 16 128 R0
WINDOW 3 64 -54 VRight 1
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 10)
SYMBOL diode 448 128 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMBOL res 384 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2.2k
FLAG 16 272 0
FLAG 208 160 A
FLAG 432 160 B
TEXT -18 296 Left 2 !.tran 200ms
* Z:\home\khalils\Downloads\files\data\raw_asc\AD3530R.asc
* Generated by LTspice 26.0.1 for Windows.
RLOAD vOUT 0 1k
CLOAD vOUT 0 15n
Vdac vDAC 0 PWL(10u 0 +1u 1.875)
V1 Vdd 0 3.3
XU1 vDAC Vdd 0 vOUT AD3530R Gain=1 ;pnba Vdac)Vdd)GND)Vout
.tran 50u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD3530R.asy)
.lib AD3530R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 952 680
WIRE -528 -96 -832 -96
WIRE -240 -96 -528 -96
WIRE -832 -48 -832 -96
WIRE -240 -32 -240 -96
WIRE -832 64 -832 32
WIRE -528 112 -832 112
WIRE -368 112 -528 112
WIRE 112 112 0 112
WIRE 192 112 112 112
WIRE 272 112 192 112
WIRE -832 144 -832 112
WIRE 112 144 112 112
WIRE 272 160 272 112
WIRE -832 256 -832 224
WIRE 112 272 112 224
WIRE 272 272 272 224
WIRE -240 288 -240 256
FLAG 192 112 vOUT
FLAG -832 256 0
FLAG -528 112 vDAC
FLAG -832 64 0
FLAG -240 288 0
FLAG 112 272 0
FLAG 272 272 0
FLAG -528 -96 Vdd
SYMBOL res 96 128 R0
SYMATTR InstName RLOAD
SYMATTR Value 1k
SYMBOL cap 256 160 R0
SYMATTR InstName CLOAD
SYMATTR Value 15n
SYMBOL voltage -832 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac
SYMATTR Value PWL(10u 0 +1u 1.875)
SYMBOL voltage -832 -64 M0
WINDOW 0 -61 27 Left 2
WINDOW 3 -55 97 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL AD3530R -208 112 R0
SYMATTR InstName U1
SYMATTR SpiceLine Gain=1
TEXT -160 312 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG751.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG751.asy)
V4 N003 0 PULSE(0 3 0 10n 10n 980n 2u)
R1 N002 0 300
XU1 N003 N002 N001 0 +V ADG751 ;pnba IN)D)S)GND)Vdd
VS N001 0 3
C1 N002 0 35p
V1 +V 0 5
.tran 10u
.lib ADG751.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -240 -16 -288 -16
WIRE 0 -16 -48 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -240 48 -368 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V4
SYMBOL ADG751 -144 32 R0
SYMATTR InstName U1
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
TEXT -536 200 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8058.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8058.asy)
XU1 0 OUT1 0 N005 IN N001 IN N003 N002 OUT2 N004 LTM8058 ;pnba GND)Vout1)Vout-)Adj1)Vin)Bias)Run)SS)BYP)Vout2)Adj2
Rload2 OUT2 0 64
C3 OUT2 0 10
Rload1 OUT1 0 64
R2 N004 0 162K
C1 N001 0 4.7
C2 OUT1 0 22
R1 N005 0 6.19K
V1 IN 0 16
.tran 2m startup
.lib LTM8058.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1108 752
WIRE 112 48 0 48
WIRE 128 48 112 48
WIRE 576 48 448 48
WIRE 864 48 576 48
WIRE 0 64 0 48
WIRE 864 112 864 48
WIRE 112 144 112 48
WIRE 128 144 112 144
WIRE 672 144 448 144
WIRE 752 144 672 144
WIRE 0 160 0 144
WIRE 576 192 576 48
WIRE 48 240 32 240
WIRE 128 240 112 240
WIRE 464 240 448 240
WIRE 672 240 672 144
WIRE 752 240 752 144
WIRE 128 336 112 336
WIRE 480 336 448 336
WIRE 32 432 16 432
WIRE 128 432 112 432
WIRE 480 432 480 416
WIRE 480 432 448 432
WIRE 576 432 576 256
WIRE 576 432 480 432
WIRE 672 432 672 304
WIRE 672 432 576 432
WIRE 752 432 752 320
WIRE 752 432 672 432
WIRE 864 432 864 192
WIRE 864 432 752 432
WIRE 864 448 864 432
WIRE 288 496 288 480
SYMBOL cap 560 192 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL res 464 320 R0
SYMATTR InstName R2
SYMATTR Value 162K
SYMBOL res 128 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 6.19K
SYMBOL cap 656 240 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL voltage 0 48 R0
SYMATTR InstName V1
SYMATTR Value 16
SYMBOL cap 112 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL PowerProducts\\LTM8058 288 240 R0
SYMATTR InstName U1
SYMBOL res 736 224 R0
SYMATTR InstName Rload2
SYMATTR Value 64
SYMBOL res 848 96 R0
SYMATTR InstName Rload1
SYMATTR Value 64
FLAG 0 160 0
FLAG 32 240 0
FLAG 16 432 0
FLAG 288 496 0
FLAG 864 448 0
FLAG 864 48 OUT1
FLAG 0 48 IN
FLAG 752 144 OUT2
TEXT 584 472 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG884.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG884.asy)
V2 SB 0 0
R1 D 0 49.9
V4 +V 0 5
V3 IN 0 PULSE(0 5 5u 20n 20n 25u 50u)
V1 SA 0 5
C1 D 0 36p
XU1 IN SA D SB +V 0 ADG884 ;pnba IN)S1)D)S2)Vdd)GND
.tran 75u
.lib ADG884.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1744 -272 -2032 -272
WIRE -1696 -272 -1744 -272
WIRE -2032 -256 -2032 -272
WIRE -1424 -240 -1504 -240
WIRE -1312 -240 -1424 -240
WIRE -1424 -224 -1424 -240
WIRE -1312 -224 -1312 -240
WIRE -1744 -208 -1920 -208
WIRE -1696 -208 -1744 -208
WIRE -1920 -192 -1920 -208
WIRE -2160 -160 -2160 -176
WIRE -2032 -160 -2032 -176
WIRE -1744 -144 -1776 -144
WIRE -1696 -144 -1744 -144
WIRE -1424 -128 -1424 -144
WIRE -1312 -128 -1312 -160
WIRE -1920 -96 -1920 -112
WIRE -1776 -80 -1776 -144
WIRE -2160 -64 -2160 -80
WIRE -1600 -16 -1600 -32
WIRE -1776 32 -1776 0
SYMBOL res -1440 -240 R0
SYMATTR InstName R1
SYMATTR Value 49.9
SYMBOL cap -1328 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL ADG884 -1600 -192 R0
SYMATTR InstName U1
SYMBOL voltage -1920 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage -1776 -96 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 5u 20n 20n 25u 50u)
SYMATTR InstName V3
SYMBOL voltage -2032 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -2160 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
FLAG -2032 -160 0
FLAG -1920 -96 0
FLAG -1776 32 0
FLAG -1600 -368 +V
FLAG -1424 -128 0
FLAG -1600 -16 0
FLAG -1312 -128 0
FLAG -2160 -64 0
FLAG -2160 -176 +V
FLAG -1424 -240 D
FLAG -1744 -272 SA
FLAG -1744 -208 SB
FLAG -1744 -144 IN
TEXT -1360 -40 Left 2 !.tran 75u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7185-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7185-2.5.asy)
C2 OUT 0 4.7 Rser=5m
C3 N001 0 1
C4 N003 0 1
XU1 OUT OUT N001 N002 IN 0 N003 IN ADP7185-2.5 ;pnba Vout)Sense)VA)VAFB)EN)GND)Vreg)Vin
R3 OUT 0 5
V1 IN 0 -3
C1 N001 N002 10n
.tran 200m startup
.lib ADP7185-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 16 -48
WIRE 96 -48 32 -48
WIRE 112 -48 96 -48
WIRE 400 -48 368 -48
WIRE 432 -48 400 -48
WIRE 496 -48 432 -48
WIRE 512 -48 496 -48
WIRE 16 -32 16 -48
WIRE 432 -32 432 -48
WIRE 512 -32 512 -48
WIRE 400 16 400 -48
WIRE 400 16 368 16
WIRE 432 48 432 32
WIRE 16 64 16 48
WIRE 512 64 512 48
WIRE 96 80 96 -48
WIRE 112 80 96 80
WIRE 464 80 368 80
WIRE 384 144 368 144
WIRE 464 144 464 80
WIRE 464 144 448 144
WIRE 464 160 464 144
WIRE 176 224 176 208
WIRE 304 224 304 208
WIRE 464 240 464 224
WIRE 176 320 176 288
SYMBOL res 496 -48 R0
SYMATTR InstName R3
SYMATTR Value 5
SYMBOL cap 448 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL cap 448 160 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL voltage 16 -48 R0
SYMATTR InstName V1
SYMATTR Value -3
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=5m
SYMBOL ADP7185-2.5 240 48 R0
SYMATTR InstName U1
SYMBOL cap 160 224 R0
SYMATTR InstName C4
SYMATTR Value 1
FLAG 16 64 0
FLAG 432 48 0
FLAG 304 224 0
FLAG 512 64 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 464 240 0
FLAG 176 320 0
TEXT 144 360 Left 2 !.tran 200m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\25b414793208_Draft05.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
V3 0 VEE 15
R3 N004 N005 10k
R2 0 N004 1k
R1 N001 0 1k
XU1 N002 N001 VCC VEE VOUT LT1001 ;pnba In+)In-)V+)V-)OUT
R5 N004 P001 10R
V4 N002 0 2.5
R4 N005 N002 10k
Q1 VCC VOUT N003 0 NPN
Q2 VEE N006 P001 0 PNP
XU2 0 N005 VCC VEE N006 LT1001 ;pnba In+)In-)V+)V-)OUT
R6 N003 N001 10
V2 VCC 0 14
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.0001 startup
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 448 -32 416 -32
WIRE 544 -16 512 -16
WIRE 608 -16 544 -16
WIRE 288 0 208 0
WIRE 448 0 288 0
WIRE 672 64 672 32
WIRE -192 80 -272 80
WIRE -272 96 -272 80
WIRE -192 96 -192 80
WIRE 416 144 416 -32
WIRE 672 144 416 144
WIRE 672 384 560 384
WIRE 288 416 288 0
WIRE 560 416 560 384
WIRE 560 416 448 416
WIRE 368 496 368 416
WIRE 400 496 368 496
WIRE 608 512 464 512
WIRE 400 528 304 528
SYMBOL npn 608 -64 R0
SYMATTR InstName Q1
SYMBOL voltage -272 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 46 70 Left 2
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL res 656 48 R0
SYMATTR InstName R6
SYMATTR Value 10
SYMBOL voltage 208 -16 R0
WINDOW 0 -47 117 Left 2
WINDOW 3 -50 145 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 2.5
SYMBOL res 464 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 384 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res 656 368 R0
SYMATTR InstName R5
SYMATTR Value 10R
SYMBOL voltage -272 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 45 Left 2
SYMATTR Value 14
SYMATTR InstName V2
SYMBOL pnp 608 560 M180
SYMATTR InstName Q2
SYMBOL OpAmps\\OP07 432 448 R0
SYMATTR InstName U2
SYMBOL res 656 128 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 656 288 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL OpAmps\\OP07 480 -80 R0
WINDOW 0 40 50 Left 2
SYMATTR InstName U1
FLAG -192 96 0
FLAG 544 -16 VOUT
FLAG 208 80 0
FLAG -272 0 VCC
FLAG -272 176 VEE
FLAG 480 16 VEE
FLAG 672 -64 VCC
FLAG 480 -48 VCC
FLAG 672 224 0
FLAG 432 480 VCC
FLAG 432 544 VEE
FLAG 672 560 VEE
FLAG 672 304 0
FLAG 304 528 0
TEXT -120 280 Left 2 !.tran 0.0001 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2015f5394071_lc_tank_orientation.asc
* Generated by LTspice 26.0.1 for Windows.
* we can see that waveform of v3-v4 is the same as v1-gnd.\nthe point of setting ground in the inductor center tap \nis just for the phase inversion. \n \nIn a hartely oscillator, v4 is used as input to the amp\nand the amp will amplify and invert(common emitter) \nthen supply energy back at node v3.
L2 v2 0 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
C2 v3 v4 0.001 IC=1 Rser=0 Lser=0 Rpar=0 Cpar=0
L4 0 v4 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
C1 v1 0 0.001 IC=1 Rser=0 Lser=0 Rpar=0 Cpar=0
L3 v3 0 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
L1 v1 v2 0.001 IC=0 Rser=0 Rpar=0 Cpar=0
.tran 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1944 680
WIRE 384 -224 256 -224
WIRE 448 -224 384 -224
WIRE 880 -224 784 -224
WIRE 976 -224 880 -224
WIRE 448 -192 448 -224
WIRE 976 -192 976 -224
WIRE 256 -128 256 -224
WIRE 784 -128 784 -224
WIRE 976 -96 976 -112
WIRE 1184 -96 976 -96
WIRE 448 -80 448 -112
WIRE 448 -64 448 -80
WIRE 976 -64 976 -96
WIRE 1184 -48 1184 -96
WIRE 256 48 256 -64
WIRE 384 48 256 48
WIRE 448 48 448 16
WIRE 448 48 384 48
WIRE 784 48 784 -64
WIRE 880 48 784 48
WIRE 976 48 976 16
WIRE 976 48 880 48
WIRE 384 80 384 48
SYMBOL cap 240 -128 R0
SYMATTR InstName C1
SYMATTR Value 0.001 IC=1
SYMATTR SpiceLine Rser=0 Lser=0 Rpar=0 Cpar=0
SYMBOL ind 432 -80 R0
SYMATTR InstName L2
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
SYMBOL ind 960 -80 R0
SYMATTR InstName L4
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
SYMBOL ind 432 -208 R0
SYMATTR InstName L1
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
SYMBOL cap 768 -128 R0
SYMATTR InstName C2
SYMATTR Value 0.001 IC=1
SYMATTR SpiceLine Rser=0 Lser=0 Rpar=0 Cpar=0
SYMBOL ind 960 -208 R0
SYMATTR InstName L3
SYMATTR Value 0.001 IC=0
SYMATTR SpiceLine Rser=0 Rpar=0 Cpar=0
FLAG 384 80 0
FLAG 384 -224 v1
FLAG 448 -80 v2
FLAG 1184 -48 0
FLAG 880 -224 v3
FLAG 880 48 v4
TEXT 592 112 Left 2 !.tran 0.1
TEXT 1264 -208 Left 2 ;we can see that waveform of v3-v4 is the same as v1-gnd.\nthe point of setting ground in the inductor center tap \nis just for the phase inversion. \n \nIn a hartely oscillator, v4 is used as input to the amp\nand the amp will amplify and invert(common emitter) \nthen supply energy back at node v3.
* Z:\home\khalils\Downloads\files\data\raw_asc\5328561c41f0_linear_regulator.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1117.asy)
R4 N003 0 120
R1 Vout N002 460
XU1 N002 Vout N001 LT1117 ;pnba ADJ)OUT)IN
R2 N002 0 270
V1 N001 0 5
R3 N004 0 330
C2 Vout 0 C
.dc V1 0 10 0.1
.lib LT1117.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 112 -112 112
WIRE 400 112 320 112
WIRE 464 112 400 112
WIRE 592 112 464 112
WIRE 608 112 592 112
WIRE -112 160 -112 112
WIRE 400 160 400 112
WIRE 192 272 192 208
WIRE 400 272 400 240
WIRE 400 272 192 272
WIRE -112 320 -112 240
WIRE 304 368 304 320
WIRE 400 368 400 272
WIRE 496 368 496 320
WIRE 592 368 592 112
WIRE 304 480 304 448
WIRE 400 480 400 448
WIRE 496 480 496 448
WIRE 592 480 592 432
WIRE 0 0 0 0
SYMBOL res 384 352 R0
SYMATTR InstName R2
SYMATTR Value 270
SYMBOL voltage -112 144 R0
WINDOW 3 48 68 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 47 34 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 480 352 R0
SYMATTR InstName R3
SYMATTR Value 330
SYMBOL res 384 144 R0
SYMATTR InstName R1
SYMATTR Value 460
SYMBOL PowerProducts\\LT1117 192 112 R0
SYMATTR InstName U1
SYMBOL cap 576 368 R0
SYMATTR InstName C2
SYMBOL res 288 352 R0
SYMATTR InstName R4
SYMATTR Value 120
FLAG -112 320 0
FLAG 400 480 0
FLAG 464 112 Vout
FLAG 496 480 0
FLAG 304 480 0
FLAG 592 480 0
TEXT -56 312 Left 2 !.dc V1 0 10 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\f0c693a40ec9_ID_vs_UGS-7.asc
* Generated by LTspice 26.0.1 for Windows.
V1 UDS 0 -10V
V2 UGS 0
M1 UDS UGS 0 0 PMOSENH
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V2 -2V 0V
* ID_vs_UGS-5
.lib mosfet.lib
* Enhancement mode P-channel MOSFET
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1292 680
WIRE -624 -176 -720 -176
WIRE -560 -176 -624 -176
WIRE -720 -128 -720 -176
WIRE -560 -80 -560 -176
WIRE -880 -48 -896 -48
WIRE -768 -48 -880 -48
WIRE -896 -32 -896 -48
WIRE -896 64 -896 48
WIRE -720 64 -720 -32
WIRE -560 64 -560 0
FLAG -560 64 0
FLAG -896 64 0
FLAG -720 64 0
FLAG -880 -48 UGS
FLAG -624 -176 UDS
SYMBOL voltage -560 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 37 60 Left 2
WINDOW 0 36 55 Left 2
WINDOW 3 36 82 Left 2
SYMATTR InstName V1
SYMATTR Value -10V
SYMBOL voltage -896 -48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 53 Left 2
WINDOW 3 -97 181 Left 2
WINDOW 0 35 44 Left 2
SYMATTR Value ""
SYMATTR InstName V2
SYMBOL pmos -768 -128 R0
SYMATTR InstName M1
SYMATTR Value PMOSENH
TEXT -904 96 Left 2 !.dc V2 -2V 0V
TEXT -896 -168 Left 2 ;ID_vs_UGS-5
TEXT -904 112 Left 2 !.lib mosfet.lib
TEXT -920 -208 Left 2 ;Enhancement mode P-channel MOSFET