* Z:\home\khalils\Downloads\files\data\raw_asc\c42e4c8eec77_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
*---------- DMP4065S Spice Model ----------
* TERMINALS: D G S
*Diodes DMP4065S Spice Model v1.0M Last Revised 2018/2/1
**********************************************************
*
* BC847
*
* Nexperia
*
* General purpose NPN transistor
* IC = 100 mA
* VCEO = 45 V
* hFE = 110 - 450 @ 5V/2mA
*
*
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 23
*
* Package Pin 1: Base
* Package Pin 2: Emitter
* Package Pin 3: Collector
*
*
* Extraction date (week/year): 24/2021
* Spicemodel includes temperature dependency
*
**********************************************************
*#
*
* Diode D1, Transistor Q2 and resistor RQ
* are dedicated to improve modeling of quasi
* saturation area and reverse mode operation
* and do not reflect physical devices.
*
*
+ TOX = 6E-008 NSUB = 1E+016 KP = 8.015 KAPPA = 19.32 VTO = -1.585
+ IS = 1.124E-14
+ NF = 0.9872
+ ISE = 2.566E-15
+ NE = 1.661
+ BF = {WC2(290,200,450,0)}
+ IKF = 0.09455
+ VAF = 36.27
+ NR = 0.9859
+ ISC = 7.015E-18
+ NC = 0.9228
+ BR = 7.047
+ IKR = 0.8167
+ VAR = 16.61
+ RB = 150
+ IRB = 0.0008356
+ RBM = 0.8289
+ RE = 0.804
+ RC = 0.2454
+ XTB = 1.382
+ EG = 1.11
+ XTI = 7.452
+ CJE = 1.264E-11
+ VJE = 0.7056
+ MJE = 0.3401
+ TF = 6.258E-10
+ XTF = 25
+ VTF = 2
+ ITF = 0.277
+ PTF = 0
+ CJC = 3.624E-12
+ VJC = 0.5036
+ MJC = 0.365
+ XCJC = 1
+ TR = 1.55E-07
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.78
+ IS = 1.365E-15
+ N = 0.988
+ BV = 1000
+ IBV = 0.001
+ RS = 2163
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
XQ1 G N002 N003 BC847B ;pnba C)B)E
DDG 14 15 DCGD
RG 20 2 10.24
Q2 11 2 33 MAIN 0.1364
D2 30 15 DLIM
DSD 10 3 DSUB
V1 S 0 12
R1 D 0 50
XM1 D G S DMP4065S ;pnba D)G)S
RQ 11 1 324.8
R2 12 15 1
R3 N003 0 {WC1(1k,0.05,4)}
R4 N001 N002 {WC1(22k,0.01,1)}
RD 10 1 0.04289
CGD 13 14 4.5E-010
EGD 12 30 2 1 1
R5 N002 0 {WC1(10k,0.05,2)}
R1 13 30 1
D1 2 1 DIODE
V3 STEPPING 0 {STEPPING}
M1 1 2 3 3 PMOS L = 1E-006 W = 1E-006
Q1 1 2 3 MAIN 0.8636
RS 30 3 0.001
V2 N001 0 PULSE(0 5 1m 10u 10u 3m)
FFB 2 1 VFB 1
VFB 14 30 0
R2 S G {WC1(10k,0.05,3)}
CGS 2 3 5.75E-010
D1 13 12 DLIM
.tran 5m startup
.SUBCKT DMP4065S 10 20 30
.MODEL PMOS PMOS LEVEL = 3 U0 = 400 VMAX = 1E+006 ETA = 0.001
.MODEL DCGD D CJO = 1.7E-010 VJ = 0.8 M = 0.6
.MODEL DSUB D IS = 2.364E-010 N = 1.26 RS = 0.0254 BV = 46 CJO = 2.226E-010 VJ = 0.8 M = 0.6
.MODEL DLIM D IS = 0.0001
.ENDS
.FUNC MOD(a,b) {a-FLOOR(a/b)*b}
.FUNC BIT(x) {if(MOD(STEPPING,2**(X+1))>=2**x,1,0)}
.FUNC EVA1 (nom, tol, param_num) {if(STEPPING == -1, nom, nom*(1-tol)+2*nom*tol*BIT(param_num))}
.FUNC EVA2 (nom, min, max, param_num) {if(STEPPING == -1, nom, IF(BIT(param_num),max,min))}
.FUNC WC1 (nom, tol, param_num) EVA1(nom, tol, param_num)
.FUNC WC2 (nom, min, max, param_num) EVA2(nom, min, max, param_num)
.step param STEPPING -1 31 1
.SUBCKT BC847B 1 2 3
.MODEL MAIN NPN
.MODEL DIODE D
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4104 3564
WIRE 496 -592 432 -592
WIRE 432 -560 432 -592
WIRE 432 -448 432 -480
WIRE 16 -176 -128 -176
WIRE 304 -176 16 -176
WIRE -128 -144 -128 -176
WIRE 16 -128 16 -176
WIRE -128 -48 -128 -64
WIRE 304 -16 304 -176
WIRE 16 0 16 -48
WIRE 208 0 16 0
WIRE 256 0 208 0
WIRE 16 48 16 0
WIRE -512 96 -656 96
WIRE -272 96 -432 96
WIRE -48 96 -272 96
WIRE 304 96 304 80
WIRE 400 96 304 96
WIRE -272 128 -272 96
WIRE -656 144 -656 96
WIRE 304 160 304 96
WIRE 16 176 16 144
WIRE -656 240 -656 224
WIRE -272 240 -272 208
WIRE 16 288 16 256
WIRE 304 288 304 240
IOPIN 496 -592 Out
SYMBOL voltage -656 128 R0
WINDOW 3 24 92 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 1m 10u 10u 3m)
SYMBOL res 288 144 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL pmos 256 80 M180
SYMATTR InstName M1
SYMATTR Value DMP4065S
SYMATTR Prefix X
SYMBOL res -288 112 R0
SYMATTR InstName R5
SYMATTR Value {WC1(10k,0.05,2)}
SYMBOL npn -48 48 R0
SYMATTR InstName Q1
SYMATTR Value BC847B
SYMATTR Prefix X
SYMBOL res 0 160 R0
SYMATTR InstName R3
SYMATTR Value {WC1(1k,0.05,4)}
SYMBOL res -528 112 R270
WINDOW 0 -29 62 VTop 2
WINDOW 3 63 66 VBottom 2
SYMATTR InstName R4
SYMATTR Value {WC1(22k,0.01,1)}
SYMBOL voltage 432 -576 R0
SYMATTR InstName V3
SYMATTR Value {STEPPING}
SYMBOL res 0 -144 R0
SYMATTR InstName R2
SYMATTR Value {WC1(10k,0.05,3)}
SYMBOL voltage -128 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 304 288 0
FLAG -128 -48 0
FLAG 16 288 0
FLAG -272 240 0
FLAG -656 240 0
FLAG 208 0 G
FLAG 304 -176 S
FLAG 400 96 D
FLAG 432 -448 0
FLAG 496 -592 STEPPING
TEXT -474 368 Left 2 !.tran 5m startup
TEXT 1976 -296 Left 2 !*---------- DMP4065S Spice Model ----------\n.SUBCKT DMP4065S 10 20 30 \n*     TERMINALS:  D  G  S\nM1 1 2 3 3 PMOS L = 1E-006 W = 1E-006 \nRD 10 1 0.04289 \nRS 30 3 0.001 \nRG 20 2 10.24 \nCGS 2 3 5.75E-010 \nEGD 12 30 2 1 1 \nVFB 14 30 0 \nFFB 2 1 VFB 1 \nCGD 13 14 4.5E-010 \nR1 13 30 1 \nD1 13 12 DLIM \nDDG 14 15 DCGD \nR2 12 15 1 \nD2 30 15 DLIM \nDSD 10 3 DSUB \n.MODEL PMOS PMOS LEVEL = 3 U0 = 400 VMAX = 1E+006 ETA = 0.001 \n+ TOX = 6E-008 NSUB = 1E+016 KP = 8.015 KAPPA = 19.32 VTO = -1.585 \n.MODEL DCGD D CJO = 1.7E-010 VJ = 0.8 M = 0.6 \n.MODEL DSUB D IS = 2.364E-010 N = 1.26 RS = 0.0254 BV = 46 CJO = 2.226E-010 VJ = 0.8 M = 0.6 \n.MODEL DLIM D IS = 0.0001 \n.ENDS\n*Diodes DMP4065S Spice Model v1.0M Last Revised 2018/2/1
TEXT -1128 -568 Left 2 !.FUNC MOD(a,b) {a-FLOOR(a/b)*b}\n.FUNC BIT(x) {if(MOD(STEPPING,2**(X+1))>=2**x,1,0)}\n.FUNC EVA1 (nom, tol, param_num) {if(STEPPING == -1, nom, nom*(1-tol)+2*nom*tol*BIT(param_num))}\n.FUNC EVA2 (nom, min, max, param_num) {if(STEPPING == -1, nom, IF(BIT(param_num),max,min))}\n.FUNC WC1 (nom, tol, param_num) EVA1(nom, tol, param_num)\n.FUNC WC2 (nom, min, max, param_num) EVA2(nom, min, max, param_num)
TEXT -1128 -400 Left 2 !.step param STEPPING -1 31 1
TEXT 1064 -296 Left 2 !**********************************************************\n*\n* BC847\n*\n* Nexperia\n*\n* General purpose NPN transistor\n* IC   = 100 mA\n* VCEO = 45 V \n* hFE  = 110 - 450 @ 5V/2mA\n* \n*\n*\n*\n* Package pinning does not match Spice model pinning.\n* Package: SOT 23\n* \n* Package Pin 1: Base\n* Package Pin 2: Emitter\n* Package Pin 3: Collector\n* \n*\n* Extraction date (week/year): 24/2021\n* Spicemodel includes temperature dependency\n*\n**********************************************************\n*#\n*\n* Diode D1, Transistor Q2 and resistor RQ \n* are dedicated to improve modeling of quasi\n* saturation area and reverse mode operation\n* and do not reflect physical devices.\n*\n.SUBCKT BC847B 1 2 3\nQ1 1 2 3 MAIN 0.8636\nQ2 11 2 33 MAIN 0.1364\nRQ 11 1 324.8\nD1 2 1 DIODE\n*\n.MODEL MAIN NPN\n+ IS = 1.124E-14\n+ NF = 0.9872\n+ ISE = 2.566E-15\n+ NE = 1.661\n+ BF = {WC2(290,200,450,0)}\n+ IKF = 0.09455\n+ VAF = 36.27\n+ NR = 0.9859\n+ ISC = 7.015E-18\n+ NC = 0.9228\n+ BR = 7.047\n+ IKR = 0.8167\n+ VAR = 16.61\n+ RB = 150\n+ IRB = 0.0008356\n+ RBM = 0.8289\n+ RE = 0.804\n+ RC = 0.2454\n+ XTB = 1.382\n+ EG = 1.11\n+ XTI = 7.452\n+ CJE = 1.264E-11\n+ VJE = 0.7056\n+ MJE = 0.3401\n+ TF = 6.258E-10\n+ XTF = 25\n+ VTF = 2\n+ ITF = 0.277\n+ PTF = 0\n+ CJC = 3.624E-12\n+ VJC = 0.5036\n+ MJC = 0.365\n+ XCJC = 1\n+ TR = 1.55E-07\n+ CJS = 0\n+ VJS = 0.75\n+ MJS = 0.333\n+ FC = 0.78\n.MODEL DIODE D\n+ IS = 1.365E-15\n+ N = 0.988\n+ BV = 1000\n+ IBV = 0.001\n+ RS = 2163\n+ CJO = 0\n+ VJ = 1\n+ M = 0.5\n+ FC = 0\n+ TT = 0\n+ EG = 1.11\n+ XTI = 3\n.ENDS