Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-2.9.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-2.9.asy)
C2 OUT 0 1
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=41666.67 ;pnba Vout))Sense)GND)En)))Vin
V1 IN 0 5.5
Rload OUT 0 100
C1 IN 0 1
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL ADP124-2.9 256 208 R0
SYMATTR InstName U1
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4210-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4210-2.asy)
C3 N005 0 .22
XU1 N005 0 IN N003 N001 IN LTC4210-2 ;pnba Timer)Gnd)On)Gate)Sense)Vcc
C1 OUT 0 470
R1 N002 N003 100
MQ1 N001 N002 OUT OUT Si4410DY
R2 N003 N004 100
C2 N004 0 .01
R3 N001 IN .01
V1 IN 0 PWL(0 0 15m 0 15.001m 5)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m
.lib LTC4210-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 16 -288 16
WIRE 160 16 80 16
WIRE 208 16 160 16
WIRE 320 16 288 16
WIRE 432 16 320 16
WIRE 640 16 528 16
WIRE -288 32 -288 16
WIRE 640 32 640 16
WIRE 160 80 160 16
WIRE 320 80 320 16
WIRE 512 96 512 64
WIRE 640 112 640 96
WIRE -288 128 -288 112
WIRE 80 192 80 16
WIRE 112 192 80 192
WIRE 512 192 512 176
WIRE 512 192 368 192
WIRE 512 208 512 192
WIRE 512 304 512 288
WIRE 160 320 160 304
WIRE 320 320 320 304
WIRE 512 384 512 368
WIRE 160 400 160 384
SYMBOL res 496 80 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL PowerProducts\\LTC4210-2 240 192 R0
SYMATTR InstName U1
SYMBOL res 496 192 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL nmos 432 64 R270
WINDOW 0 56 41 VTop 2
WINDOW 3 -16 73 VLeft 2
SYMATTR InstName Q1
SYMATTR Value Si4410DY
SYMBOL cap 496 304 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL voltage -288 16 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 15m 0 15.001m 5)
SYMBOL cap 144 320 R0
SYMATTR InstName C3
SYMATTR Value .22
SYMBOL cap 624 32 R0
SYMATTR InstName C1
SYMATTR Value 470
SYMBOL res 304 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value .01
FLAG 320 320 0
FLAG 640 112 0
FLAG 512 384 0
FLAG 160 400 0
FLAG -288 128 0
FLAG 640 16 OUT
FLAG -288 16 IN
TEXT 656 360 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\1bbcc014682e_4440.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4440.asy)
V2 N002 0 PULSE(0 8 0 1n 1n 1u 2u)
V1 N001 0 8
XU1 N001 0 N002 0 N003 N001 LTC4440 ;pnba VCC)GND)INP)TS)TG)BOOST
.tran 50u
.lib LTC4440.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2336 1256
WIRE 1424 -144 1104 -144
WIRE 1008 -80 976 -80
WIRE 1104 -80 1104 -144
WIRE 1104 -80 1088 -80
WIRE 1136 -80 1104 -80
WIRE 1424 -80 1424 -144
WIRE 1424 -80 1392 -80
WIRE 1136 0 944 0
WIRE 1424 0 1392 0
WIRE 944 64 944 0
WIRE 1136 80 1104 80
WIRE 1424 80 1392 80
WIRE 944 160 944 144
SYMBOL voltage 944 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 8 0 1n 1n 1u 2u)
SYMBOL voltage 1104 -80 R90
WINDOW 0 -32 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName V1
SYMATTR Value 8
SYMBOL PowerProducts\\LTC4440 1264 0 R0
SYMATTR InstName U1
FLAG 1104 80 0
FLAG 976 -80 0
FLAG 1424 80 0
FLAG 944 160 0
TEXT 1304 176 Left 0 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\1c9acfbd14a5_4440.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4440.asy)
XU1 N001 0 N002 0 N003 N001 LTC4440 ;pnba VCC)GND)INP)TS)TG)BOOST
V2 N002 0 PULSE(0 8 0 1n 1n 1u 2u)
V1 N001 0 8
.tran 50u
.lib LTC4440.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2336 1256
WIRE 1424 -144 1104 -144
WIRE 1008 -80 992 -80
WIRE 1104 -80 1104 -144
WIRE 1104 -80 1088 -80
WIRE 1136 -80 1104 -80
WIRE 1424 -80 1424 -144
WIRE 1424 -80 1392 -80
WIRE 1136 0 736 0
WIRE 1424 0 1392 0
WIRE 736 16 736 0
WIRE 1136 80 1104 80
WIRE 1424 80 1392 80
WIRE 736 112 736 96
SYMBOL voltage 736 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 8 0 1n 1n 1u 2u)
SYMBOL PowerProducts\\LTC4440 1264 0 R0
SYMATTR InstName U1
SYMBOL voltage 1104 -80 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value 8
FLAG 1104 80 0
FLAG 992 -80 0
FLAG 1424 80 0
FLAG 736 112 0
TEXT 1304 176 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8651.asc
* Generated by LTspice 26.0.1 for Windows.
Vin IN 0 SINE(0 1 100k)
V1 +V 0 2.5
R1 N001 0 10k
R2 OUT N001 10k
V2 -V 0 -2.5
Rload OUT 0 10k
XU1 IN N001 +V -V OUT AD8651 ;pnba In+)In-)V+)V-)OUT
.tran 100u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8651.asy)
.lib AD8651.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 480 -880 464 -880
WIRE 576 -880 560 -880
WIRE 592 -880 576 -880
WIRE 688 -880 672 -880
WIRE 240 -768 240 -784
WIRE 352 -768 352 -784
WIRE 576 -768 576 -880
WIRE 592 -768 576 -768
WIRE 688 -752 688 -880
WIRE 688 -752 656 -752
WIRE 816 -752 688 -752
WIRE 592 -736 480 -736
WIRE 816 -736 816 -752
WIRE 480 -720 480 -736
WIRE 240 -672 240 -688
WIRE 352 -672 352 -688
WIRE 816 -640 816 -656
WIRE 480 -624 480 -640
FLAG 240 -784 +V
FLAG 240 -672 0
FLAG 480 -624 0
FLAG 816 -752 OUT
FLAG 480 -736 IN
FLAG 624 -784 +V
FLAG 352 -784 -V
FLAG 624 -720 -V
FLAG 464 -880 0
FLAG 816 -640 0
FLAG 352 -672 0
SYMBOL voltage 480 -736 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100k)
SYMBOL voltage 240 -784 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 576 -896 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 688 -896 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 352 -784 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 800 -752 R0
SYMATTR InstName Rload
SYMATTR Value 10k
SYMBOL AD8651 624 -816 R0
SYMATTR InstName U1
TEXT 752 -592 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6230-10.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6230-10.asy)
V1 +V 0 5
V3 N003 0 SINE(0 .1 1K)
R1 N002 N001 10K
XU1 N003 N001 N002 +V -V 0 LT6230-10 ;pnba IN+)IN-)OUT)VCC)VEE)EN_L
V2 -V 0 -5
R2 N001 0 1K
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -112 48 -128 48
WIRE 0 48 -32 48
WIRE 96 48 0 48
WIRE 208 48 176 48
WIRE 64 112 64 96
WIRE -416 160 -416 144
WIRE -288 160 -288 144
WIRE 0 160 0 48
WIRE 32 160 0 160
WIRE 208 192 208 48
WIRE 208 192 176 192
WIRE 32 224 -144 224
WIRE -144 240 -144 224
WIRE -416 256 -416 240
WIRE -288 256 -288 240
WIRE 64 288 64 272
WIRE -144 336 -144 320
SYMBOL res 192 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -144 224 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 .1 1K)
SYMBOL res -16 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -416 144 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL opamps\\LT6230-10 64 192 R0
SYMATTR InstName U1
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -288 256 0
FLAG 64 96 +V
FLAG -288 144 +V
FLAG 64 288 -V
FLAG -416 256 0
FLAG -416 144 -V
FLAG -128 48 0
FLAG -144 336 0
FLAG 112 272 0
TEXT 176 344 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\574b9b96c546_ponte_di__Cowan.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 0 1k
L2 0 N005 1
V1 N005 0 SINE(0 10 50) Rser=100
V2 N004 0 SINE(0 100m 10) Rser=0
L1 N003 N002 1
D4 N001 N003 D
D3 N002 0 D
D2 0 N003 D
D1 N002 N001 D
R2 N001 N004 100
K1 L1 L2 1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 4
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1024 680
WIRE 96 16 -144 16
WIRE 384 16 96 16
WIRE 544 16 384 16
WIRE 96 48 96 16
WIRE 384 48 384 16
WIRE -144 64 -144 16
WIRE 96 128 96 112
WIRE 208 128 96 128
WIRE 384 128 384 112
WIRE 384 128 288 128
WIRE 544 128 544 16
WIRE -144 192 -144 144
WIRE 208 224 128 224
WIRE 336 224 288 224
WIRE 96 240 96 128
WIRE 384 240 384 128
WIRE 384 256 384 240
WIRE 128 304 128 224
WIRE 208 304 128 304
WIRE 336 304 336 224
WIRE 336 304 288 304
WIRE -144 352 -144 272
WIRE 32 352 -144 352
WIRE 96 352 96 304
WIRE 96 352 32 352
WIRE 384 352 384 304
WIRE 384 352 96 352
WIRE 544 352 544 208
WIRE 544 352 384 352
WIRE 32 384 32 352
SYMBOL voltage 192 304 R270
WINDOW 0 -35 6 VTop 2
WINDOW 3 -88 56 VBottom 2
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 10 50)
SYMATTR SpiceLine Rser=100
SYMBOL diode 400 304 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL res 528 112 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL ind2 304 240 M270
WINDOW 0 -23 44 VTop 2
WINDOW 3 5 78 VBottom 2
SYMATTR InstName L2
SYMATTR Value 1
SYMATTR Type ind
SYMBOL res -160 48 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL ind2 304 112 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 -24 86 VTop 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR Type ind
SYMBOL voltage -144 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0
SYMATTR InstName V2
SYMATTR Value SINE(0 100m 10)
SYMBOL diode 368 48 R0
SYMATTR InstName D4
SYMBOL diode 112 112 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL diode 80 240 R0
WINDOW 0 -28 -4 Left 2
WINDOW 3 -22 61 Left 2
SYMATTR InstName D3
FLAG 32 384 0
FLAG 336 304 0
TEXT 200 176 Left 2 !K1 L1 L2 1
TEXT -176 424 Left 2 !.tran 4
* Z:\home\khalils\Downloads\files\data\raw_asc\083b5bdf29c2_Diff_Schmitt.asc
* Generated by LTspice 26.0.1 for Windows.
* Diff. Sch,itt-Trigger\nPlot V(vp,vn) and V(out)\n \nThreshholds Vt+Vh, Vt-Vh\nExample Vt=1, Vh=0.4\nOutput switches to high at (vp-vn) = 1V+0.4V = 1.4V\nOutput switches to low at (vp-vn) = 1V-0.4V = 0.6V\n \nRightClick on the symbol body to see where vt and vh is set\nAny of the attribute lines Value, Value2, SpiceLine, SpiceLine2 is ok.
A1 VP VN 0 0 0 0 out 0 SCHMITT vt=1 vh=0.4
V1 VN 0 SINE(0 1 1kHz 0 0 180) AC 1
V3 VP 0 SINE(0 1 1kHz) AC 1
.tran 0 2m 0 1u
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1208 904
WIRE -272 224 -272 192
WIRE -272 336 -272 304
WIRE -272 416 -272 384
WIRE -272 528 -272 496
WIRE -256 192 -272 192
WIRE -256 384 -272 384
WIRE 32 384 -256 384
WIRE 32 384 32 224
WIRE 112 192 -256 192
WIRE 112 224 32 224
WIRE 240 192 176 192
IOPIN 240 192 Out
SYMBOL voltage -272 400 R0
WINDOW 3 39 57 Left 0
WINDOW 123 39 83 Left 0
WINDOW 39 24 44 Left 0
SYMATTR Value SINE(0 1 1kHz 0 0 180)
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL Digital\\diffschmitt 112 144 R0
WINDOW 123 2 118 Left 0
SYMATTR InstName A1
SYMATTR Value2 vt=1 vh=0.4
SYMBOL voltage -272 208 R0
WINDOW 3 39 57 Left 0
WINDOW 123 39 83 Left 0
WINDOW 39 24 44 Left 0
SYMATTR Value SINE(0 1 1kHz)
SYMATTR Value2 AC 1
SYMATTR InstName V3
FLAG -256 192 VP
FLAG -272 336 0
FLAG -256 384 VN
FLAG -272 528 0
FLAG 240 192 out
TEXT -280 56 Left 0 !.tran 0 2m 0 1u
TEXT -280 80 Left 0 !.options plotwinsize=0
TEXT -272 -240 Left 0 ;Diff. Sch,itt-Trigger\nPlot V(vp,vn)  and V(out)\n \nThreshholds Vt+Vh, Vt-Vh\nExample Vt=1, Vh=0.4\nOutput switches to high at (vp-vn) = 1V+0.4V = 1.4V\nOutput switches to low at (vp-vn) = 1V-0.4V = 0.6V\n \nRightClick on the symbol body to see where vt and vh is set\nAny of the attribute lines Value, Value2, SpiceLine, SpiceLine2 is ok.
* Z:\home\khalils\Downloads\files\data\raw_asc\5898df824ddd_OPAMPTBJ01D.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
Vi i 0 {Vi}
V1 Vpp 0 {Vs}
XU1 0 neg Vpp Vnn o level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
D2 neg o D2
V2 0 Vnn {Vs}
RL o 0 {RL}
R1 i neg {R1}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.param Vi=10 Vs=15 R1=1k RL=10k
.op
.model D2 D(IS=10F N=1.2)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1608 1076
WIRE 688 240 640 240
WIRE 800 240 752 240
WIRE 1056 336 1008 336
WIRE 1008 352 1008 336
WIRE 1056 368 1056 336
WIRE 496 400 416 400
WIRE 624 400 576 400
WIRE 640 400 640 240
WIRE 640 400 624 400
WIRE 672 400 640 400
WIRE 800 416 800 240
WIRE 800 416 736 416
WIRE 864 416 800 416
WIRE 672 432 624 432
WIRE 416 448 416 400
WIRE 864 448 864 416
WIRE 624 480 624 432
WIRE 416 560 416 528
WIRE 864 560 864 528
SYMBOL Opamps\\UniversalOpamp2 704 416 R0
SYMATTR InstName U1
SYMBOL res 848 432 R0
SYMATTR InstName RL
SYMATTR Value {RL}
SYMBOL voltage 1056 352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vs}
SYMBOL voltage 1056 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vs}
SYMBOL diode 688 256 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value D2
SYMBOL res 480 416 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL voltage 416 432 R0
WINDOW 3 42 66 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 50 38 Left 2
SYMATTR Value {Vi}
SYMATTR InstName Vi
FLAG 1056 256 Vpp
FLAG 1008 352 0
FLAG 1056 448 Vnn
FLAG 864 560 0
FLAG 416 560 0
FLAG 704 384 Vpp
FLAG 704 448 Vnn
FLAG 624 480 0
FLAG 864 416 o
FLAG 416 400 i
FLAG 624 400 neg
TEXT -152 640 Left 2 !.param Vi=10 Vs=15 R1=1k RL=10k
TEXT -152 696 Left 2 !.op
TEXT -152 672 Left 2 !.model D2 D(IS=10F N=1.2)
* Z:\home\khalils\Downloads\files\data\raw_asc\23d924822e42_inverter.asc
* Generated by LTspice 26.0.1 for Windows.
M2 out in 0 0 TestN l=100u w=100u
Vdd N001 0 2.5V
Vin in 0 0
M1 N001 in out N001 TestP l=100u w=100u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model TestN nmos (kp=90u vt0=0.7 lambda=0.2 u0=460)
.model TestP pmos (kp=40u vt0=-0.7 lambda=0.2 u0=115)
.dc Vin 0V 2.5V 0.01V
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 1316
WIRE -96 800 -496 800
WIRE -96 864 -96 800
WIRE -80 864 -96 864
WIRE -496 880 -496 800
WIRE -80 912 -80 864
WIRE -80 912 -96 912
WIRE -144 944 -208 944
WIRE -96 1024 -96 960
WIRE -272 1040 -336 1040
WIRE -208 1040 -208 944
WIRE -208 1040 -272 1040
WIRE -336 1072 -336 1040
WIRE -96 1072 -96 1024
WIRE -80 1120 -96 1120
WIRE -208 1152 -208 1040
WIRE -144 1152 -208 1152
WIRE -80 1168 -80 1120
WIRE -80 1168 -96 1168
WIRE -336 1280 -336 1152
WIRE -96 1280 -96 1168
WIRE -496 1296 -496 960
SYMBOL voltage -496 864 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vdd
SYMATTR Value 2.5V
SYMBOL nmos4 -144 1072 R0
SYMATTR InstName M2
SYMATTR Value TestN
SYMATTR Value2 l=100u w=100u
SYMBOL voltage -336 1056 R0
WINDOW 3 24 44 Left 2
SYMATTR Value 0
SYMATTR InstName Vin
SYMBOL pmos4 -144 864 R0
SYMATTR InstName M1
SYMATTR Value TestP
SYMATTR Value2 l=100u w=100u
FLAG -496 1296 0
FLAG -96 1280 0
FLAG -336 1280 0
FLAG -96 1024 out
FLAG -272 1040 in
TEXT -688 672 Left 2 !.model TestN nmos (kp=90u vt0=0.7 lambda=0.2 u0=460)\n.model TestP pmos (kp=40u vt0=-0.7 lambda=0.2 u0=115)\n.dc Vin 0V 2.5V 0.01V
* Z:\home\khalils\Downloads\files\data\raw_asc\002a86ca3041_Fig6_13_PMOS.asc
* Generated by LTspice 26.0.1 for Windows.
VSG 0 N001 0
VSD 0 N003 2
VBS N002 0 0
M1 N003 N001 0 N002 P_1u L=1u W=10u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSG 0 2 VBS 0 5 1
.include cmosedu_models.txt
* Plot Is(M1)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 688
WIRE 448 16 320 16
WIRE 672 16 448 16
WIRE 720 16 672 16
WIRE 320 32 320 16
WIRE 720 48 720 16
WIRE 448 112 448 16
WIRE 320 128 320 112
WIRE 400 128 320 128
WIRE 528 160 448 160
WIRE 672 160 672 16
WIRE 672 160 608 160
WIRE 672 208 672 160
WIRE 448 304 448 208
WIRE 672 304 672 288
WIRE 672 304 448 304
FLAG 720 48 0
SYMBOL voltage 320 16 R0
WINDOW 0 -89 56 Left 2
WINDOW 3 -89 84 Left 2
SYMATTR InstName VSG
SYMATTR Value 0
SYMBOL voltage 672 192 R0
WINDOW 0 41 57 Left 2
WINDOW 3 41 85 Left 2
SYMATTR InstName VSD
SYMATTR Value 2
SYMBOL voltage 512 160 M90
WINDOW 0 64 52 VBottom 2
WINDOW 3 62 93 VBottom 2
SYMATTR InstName VBS
SYMATTR Value 0
SYMBOL pmos4 400 208 M180
WINDOW 123 56 100 Left 2
SYMATTR Value2 L=1u W=10u
SYMATTR InstName M1
SYMATTR Value P_1u
TEXT 424 328 Left 2 !.dc VSG 0 2  VBS 0 5 1
TEXT 424 360 Left 2 !.include cmosedu_models.txt
TEXT 488 -8 Left 2 ;Plot Is(M1)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-1.8.asy)
C2 OUT 0 1
C1 IN 0 1
Rload OUT 0 100
V1 IN 0 5.5
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=76923 ;pnba Vout))Sense)GND)En)))Vin
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL ADP124-1.8 256 208 R0
SYMATTR InstName U1
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\247f1eb1a05d_halvwave_current.asc
* Generated by LTspice 26.0.1 for Windows.
* positive values using function "uramp"
* pos. halvwave using function "limit"\nupper_limut is below amplitude for demo
* REF: HELP (F1) / LTspice / Circuit elements / B. Arbitrary
B2 0 N002 I=uramp(v(sin))
V1 sin 0 SINE(0 5 50)
R_Load1 N002 0 1
B1 0 N001 I=limit({lower_limit},v(sin),{upper_limit})
R_Load N001 0 1
.tran 100m
.params lower_limit = 0 upper_limit = 4.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 956 680
WIRE 16 -32 -144 -32
WIRE -144 16 -144 -32
WIRE 16 16 16 -32
WIRE -368 112 -368 64
WIRE -144 144 -144 96
WIRE 16 144 16 96
WIRE -368 224 -368 192
WIRE 16 240 -144 240
WIRE -144 288 -144 240
WIRE 16 288 16 240
WIRE -144 416 -144 368
WIRE 16 416 16 368
SYMBOL bi2 -144 16 R0
WINDOW 3 -9 169 Left 0
SYMATTR InstName B1
SYMATTR Value I=limit({lower_limit},v(sin),{upper_limit})
SYMBOL res 0 272 R0
SYMATTR InstName R_Load1
SYMATTR Value 1
SYMBOL voltage -368 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 50)
SYMBOL res 0 0 R0
SYMATTR InstName R_Load
SYMATTR Value 1
SYMBOL bi2 -144 288 R0
WINDOW 3 -29 163 Left 0
SYMATTR InstName B2
SYMATTR Value I=uramp(v(sin))
FLAG -368 224 0
FLAG -368 64 sin
FLAG -144 144 0
FLAG 16 144 0
FLAG -144 416 0
FLAG 16 416 0
TEXT -350 270 Left 0 !.tran 100m
TEXT 184 368 Left 0 ;positive values using function "uramp"
TEXT 120 -24 Left 0 !.params lower_limit = 0  upper_limit = 4.5
TEXT 200 64 Left 0 ;pos. halvwave using function "limit"\nupper_limut is below amplitude for demo
TEXT 352 224 Left 0 ;REF: HELP (F1) / LTspice / Circuit elements / B. Arbitrary
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4120-1A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4120-1A.asy)
R1 GATE N004 5
V3 N003 0 PULSE(0 5 0 2n 2n 998n 2u)
C1 GATE 0 2n
V2 N002 0 15
XU1 N001 N003 0 0 N004 N002 ADuM4120xx Glitch=0 Vrun2=4.3 ;pnba Vdd1)Vin)GND1)GND2)Vout)Vdd2
V1 N001 0 5
.tran 10u
.lib ADuM4120xx.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 16 0 16
WIRE 512 16 320 16
WIRE 0 32 0 16
WIRE 512 32 512 16
WIRE 160 48 160 16
WIRE 320 48 320 16
WIRE 0 128 0 112
WIRE 512 128 512 112
WIRE 112 160 -64 160
WIRE 400 160 368 160
WIRE 512 160 480 160
WIRE 544 160 512 160
WIRE 512 176 512 160
WIRE 160 288 160 272
WIRE 320 288 320 272
SYMBOL voltage 512 16 R0
WINDOW 0 29 30 Left 2
WINDOW 3 31 84 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL ADuM4120-1A 240 160 R0
SYMATTR InstName U1
SYMBOL voltage 0 16 R0
WINDOW 0 25 25 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 496 176 R0
WINDOW 0 35 16 Left 2
WINDOW 3 36 51 Left 2
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL res 496 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5
SYMBOL voltage -48 160 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 2n 2n 998n 2u)
FLAG 160 288 0
FLAG 320 288 0
FLAG 512 240 0
FLAG 544 160 GATE
FLAG 512 128 0
FLAG 0 128 0
FLAG -144 160 0
TEXT 400 280 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3410B-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3410B-1.2.asy)
V1 IN 0 5
L1 N001 OUT 4.7
C1 OUT 0 4.7
XU1 IN 0 N001 IN MP_01 OUT LTC3410B-x.x top=180K bot=360K ;pnba Run)GND)SW)Vin))FB
Rload OUT 0 20
.tran 250u startup
.lib LTC3410B-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1028 700
WIRE 192 64 96 64
WIRE 352 64 192 64
WIRE 96 80 96 64
WIRE 352 80 352 64
WIRE 192 144 192 64
WIRE 208 144 192 144
WIRE 512 144 496 144
WIRE 608 144 592 144
WIRE 656 144 608 144
WIRE 752 144 656 144
WIRE 656 160 656 144
WIRE 752 160 752 144
WIRE 96 176 96 160
WIRE 656 256 656 224
WIRE 752 256 752 240
WIRE 608 304 608 144
WIRE 608 304 496 304
WIRE 352 384 352 368
SYMBOL VOLTAGE 96 64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LTC3410B-1.2 352 224 R0
SYMATTR InstName U1
SYMBOL RES 736 144 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL cap 640 160 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL ind 496 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
FLAG 96 176 0
FLAG 352 384 0
FLAG 656 256 0
FLAG 752 256 0
FLAG 96 64 IN
FLAG 752 144 OUT
TEXT 560 360 Left 2 !.tran 250u startup