Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP122-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP122-2.8.asy)
XU1 OUT MP_01 0 IN MP_02 IN ADP122 K=1/5600 ;pnba Vout))GND)En))Vin
V1 IN 0 5.5
Rload OUT 0 100
C2 OUT 0 1
C1 IN 0 1
.tran 10m startup
.lib ADP122.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 400 96 352 96
WIRE 480 96 400 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 400 112 400 96
WIRE 480 112 480 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 400 208 400 176
WIRE 480 208 480 192
WIRE 256 272 256 256
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL ADP122-2.8 256 208 R0
SYMATTR InstName U1
SYMBOL cap 384 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 464 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
FLAG 0 208 0
FLAG 256 272 0
FLAG 400 208 0
FLAG 480 208 0
FLAG 480 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6254.asc
* Generated by LTspice 26.0.1 for Windows.
* Single-ended in to differential out
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6254.asy)
XU1 OUT+ 0 IN N001 +V LTC6253 ;pnba 1)2)3)4)5
R5 N003 +V 1K
R3 OUT- N002 1K
R4 N002 IN 1K
R6 0 N003 1K
R2 N001 IN 1K
XU2 OUT- 0 N003 N002 +V LTC6253 ;pnba 1)2)3)4)5
R1 OUT+ N001 1K
V4 IN 0 SINE(2.5 1 250K)
C1 N003 0 0.1
V2 +V 0 5
.tran 25u
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 512 -1232 496 -1232
WIRE 528 -1232 512 -1232
WIRE 624 -1232 608 -1232
WIRE 560 -1136 560 -1152
WIRE 512 -1120 512 -1232
WIRE 528 -1120 512 -1120
WIRE 624 -1104 624 -1232
WIRE 624 -1104 592 -1104
WIRE 656 -1104 624 -1104
WIRE 400 -1088 400 -1232
WIRE 400 -1088 144 -1088
WIRE 528 -1088 400 -1088
WIRE 144 -1072 144 -1088
WIRE 560 -1056 560 -1072
WIRE 144 -976 144 -992
WIRE 400 -976 400 -1088
WIRE 416 -976 400 -976
WIRE 512 -976 496 -976
WIRE 528 -976 512 -976
WIRE 624 -976 608 -976
WIRE 656 -976 624 -976
WIRE 560 -880 560 -896
WIRE 512 -864 512 -976
WIRE 528 -864 512 -864
WIRE 80 -848 80 -864
WIRE 624 -848 624 -976
WIRE 624 -848 592 -848
WIRE 272 -832 240 -832
WIRE 384 -832 352 -832
WIRE 464 -832 384 -832
WIRE 528 -832 464 -832
WIRE 384 -800 384 -832
WIRE 464 -800 464 -832
WIRE 560 -800 560 -816
WIRE 80 -752 80 -768
WIRE 384 -704 384 -720
WIRE 464 -704 464 -736
SYMBOL res 368 -848 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL res 512 -992 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap 448 -800 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL Opamps\\LTC6254 560 -848 R0
SYMATTR InstName U2
SYMBOL res 624 -992 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL voltage 80 -864 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 624 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 368 -704 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R6
SYMATTR Value 1K
SYMBOL Opamps\\LTC6254 560 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 144 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V4
SYMATTR Value SINE(2.5 1 250K)
FLAG 80 -864 +V
FLAG 80 -752 0
FLAG 144 -976 0
FLAG 656 -1104 OUT+
FLAG 560 -1056 0
FLAG 144 -1088 IN
FLAG 560 -800 0
FLAG 656 -976 OUT-
FLAG 240 -832 +V
FLAG 464 -704 0
FLAG 384 -704 0
FLAG 560 -896 +V
FLAG 560 -1152 +V
TEXT 688 -728 Left 2 !.tran 25u
TEXT 384 -1312 Bottom 2 ;Single-ended in to differential out
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4414.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4414.asy)
R1 N002 0 2
MQ1 N001 N003 N002 N002 FDR840P
R2 N004 N005 470K
C1 N002 0 4.7
V2 N005 0 5
V1 N001 0 5
XU1 N001 0 0 N004 N002 N003 LTC4414 ;pnba Vin)CTL)GND)STAT)Sense)Gate
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m startup
.lib LTC4414.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 0 -16 0
WIRE 384 0 352 0
WIRE 448 0 384 0
WIRE 544 0 448 0
WIRE 448 16 448 0
WIRE 544 16 544 0
WIRE -16 112 -16 0
WIRE -16 112 -128 112
WIRE 16 112 -16 112
WIRE 384 112 384 0
WIRE 384 112 272 112
WIRE 448 112 448 80
WIRE 544 112 544 96
WIRE -128 128 -128 112
WIRE 16 192 -16 192
WIRE 336 192 336 48
WIRE 336 192 272 192
WIRE -128 224 -128 208
WIRE 16 272 -16 272
WIRE 288 272 272 272
WIRE 416 272 368 272
WIRE 416 288 416 272
WIRE 416 384 416 368
SYMBOL res 528 0 R0
SYMATTR InstName R1
SYMATTR Value 2
SYMBOL pmos 256 48 R270
WINDOW 0 52 48 VTop 2
WINDOW 3 -14 72 VLeft 2
SYMATTR InstName Q1
SYMATTR Value FDR840P
SYMBOL res 272 288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 470K
SYMBOL voltage -128 112 R0
WINDOW 0 17 15 Left 2
WINDOW 3 21 97 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 416 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL cap 432 16 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL LTC4414 144 192 R0
SYMATTR InstName U1
FLAG -16 192 0
FLAG -128 224 0
FLAG -16 272 0
FLAG 448 112 0
FLAG 544 112 0
FLAG 416 384 0
TEXT 40 336 Left 2 !.tran 100m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\edfd2651496d_mos_param_visibility.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc V1 0 5 .01
* How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
M2 out in vdd vdd PMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
M3 out in 0 0 NMOS1 L=2u W=10u AD=80p PD=25u AS=80p PS=25u
V1 in 0 2.5
V2 vdd 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.model PMOS1 pmos level=2 nsub=4e15 tox=50n
.model NMOS1 nmos level=2 nsub=4e15 tox=50n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1404 948
WIRE 48 400 48 320
WIRE 48 544 48 480
WIRE 64 32 64 -32
WIRE 64 176 64 112
WIRE 112 320 48 320
WIRE 256 320 112 320
WIRE 256 320 256 160
WIRE 256 464 256 320
WIRE 352 160 256 160
WIRE 352 464 256 464
WIRE 400 -32 64 -32
WIRE 400 80 400 -32
WIRE 400 144 400 80
WIRE 400 320 400 240
WIRE 400 384 400 320
WIRE 400 544 400 480
WIRE 496 192 400 192
WIRE 496 432 400 432
WIRE 560 320 400 320
SYMBOL pmos4 352 240 M180
WINDOW 0 59 69 Left 0
WINDOW 3 57 27 Left 0
WINDOW 123 57 -1 Left 0
SYMATTR InstName M2
SYMATTR Value PMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
SYMBOL voltage 48 384 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage 64 16 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL nmos4 352 384 R0
WINDOW 123 56 100 Left 0
SYMATTR InstName M3
SYMATTR Value NMOS1
SYMATTR Value2 L=2u W=10u
SYMATTR SpiceLine AD=80p PD=25u AS=80p PS=25u
FLAG 112 320 in
FLAG 400 544 0
FLAG 496 432 0
FLAG 496 192 vdd
FLAG 400 80 vdd
FLAG 560 320 out
FLAG 64 176 0
FLAG 48 544 0
TEXT 24 -104 Left 0 !.op
TEXT 24 624 Left 0 !.model PMOS1 pmos level=2 nsub=4e15 tox=50n\n.model NMOS1 nmos level=2 nsub=4e15 tox=50n
TEXT 24 -136 Left 0 ;.dc V1 0 5 .01
TEXT 16 -608 Left 0 ;How to make L and W visible, but not the other like AD, PS ...\n \nAdd symbols "nmos4" and "pmos4" to the schematic.\nThe Mosfets become an instance after you you placed it.\nChange NMOS to the model name, e.g. NMOS1.\nChange PMOS to the model name, e.g. PMOS2. \nCtrl-RightMouseClick on the body of a Mosfet.\nAdd L= ... W= ... into the field "Value2". Enable visibility!\nAdd AD= PS= ......... into the field "SpiceLine".\n \nLook in the Spice Error Log file for results after a RUN.\nView->SPICE Error Log\n \nSome parameters are from here:\nhttp://myqu.qu.edu.qa/malani/VLSI/2-Input%20NOR%20Gate.doc
* Z:\home\khalils\Downloads\files\data\raw_asc\LT5400-6.asc
* Generated by LTspice 26.0.1 for Windows.
XU2 N002 N001 +V -V OUT LT1468 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
V2 -V 0 -15
V3 IN 0 AC 1
C1 N001 OUT 4.7p
C2 N002 0 4.7p
XU1 OUT IN 0 0 N002 N002 N001 N001 NC_01 LT5400-6 ;pnba 1)2)3)4)5)6)7)8)PAD
.ac oct 10 1K 10Meg
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Misc\LT5400-6.asy)
.lib LT5400.lib
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1468.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2836 1472
WIRE 2304 624 1936 624
WIRE 1936 688 1936 624
WIRE 2016 688 1936 688
WIRE 2192 688 2080 688
WIRE 1936 816 1936 688
WIRE 1952 816 1936 816
WIRE 2192 816 2192 688
WIRE 2192 816 2144 816
WIRE 1952 880 1744 880
WIRE 2192 880 2192 816
WIRE 2192 880 2144 880
WIRE 1392 896 1392 880
WIRE 1520 896 1520 880
WIRE 1744 896 1744 880
WIRE 2192 896 2192 880
WIRE 2208 896 2192 896
WIRE 2304 912 2304 624
WIRE 2304 912 2272 912
WIRE 2336 912 2304 912
WIRE 2208 928 2192 928
WIRE 1952 944 1936 944
WIRE 2192 944 2192 928
WIRE 2192 944 2144 944
WIRE 1392 992 1392 976
WIRE 1520 992 1520 976
WIRE 1744 992 1744 976
WIRE 1920 1008 1872 1008
WIRE 1952 1008 1920 1008
WIRE 2192 1008 2192 944
WIRE 2192 1008 2144 1008
WIRE 1920 1120 1920 1008
WIRE 2016 1120 1920 1120
WIRE 2192 1120 2192 1008
WIRE 2192 1120 2080 1120
FLAG 2240 880 +V
FLAG 2240 944 -V
FLAG 2336 912 OUT
FLAG 1520 992 0
FLAG 1520 880 +V
FLAG 1392 992 0
FLAG 1392 880 -V
FLAG 1744 992 0
FLAG 1744 880 IN
FLAG 1872 1008 0
FLAG 1936 944 0
SYMBOL opamps\\LT1468 2240 848 R0
SYMATTR InstName U2
SYMBOL voltage 1520 880 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 1392 880 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 1744 880 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL cap 2080 672 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 4.7p
SYMBOL cap 2080 1104 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7p
SYMBOL misc\\LT5400-6 2048 912 R0
SYMATTR InstName U1
TEXT 2312 1064 Left 2 !.ac oct 10 1K 10Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1506-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1506-3.3.asy)
D2 0 N003 MBRS340
C3 N001 N003 .68
V1 IN 0 5
C2 OUT 0 100 Rser=50m
Rload OUT 0 1
C1 N004 0 .0015
XU1 IN N001 OUT 0 N004 N002 MP_01 N003 LT1506 top=1.82K bot=4.99K ;pnba Vin)Boost)Sense)GND)Vc)_SHDN))SW
L1 N003 OUT 5
D1 OUT N001 1N914
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 500u startup
.lib LT1506.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2864 1988
WIRE 1840 1088 1648 1088
WIRE 2128 1088 2000 1088
WIRE 2208 1088 2128 1088
WIRE 2320 1088 2272 1088
WIRE 1648 1104 1648 1088
WIRE 1840 1120 1840 1088
WIRE 2000 1120 2000 1088
WIRE 2128 1120 2128 1088
WIRE 1648 1200 1648 1184
WIRE 1760 1216 1744 1216
WIRE 2128 1216 2128 1184
WIRE 2128 1216 2080 1216
WIRE 2208 1216 2128 1216
WIRE 2320 1216 2320 1088
WIRE 2320 1216 2288 1216
WIRE 2384 1216 2320 1216
WIRE 2128 1232 2128 1216
WIRE 2384 1232 2384 1216
WIRE 2128 1312 2128 1296
WIRE 2384 1328 2384 1312
WIRE 1680 1344 1664 1344
WIRE 1760 1344 1744 1344
WIRE 2320 1344 2320 1216
WIRE 2320 1344 2080 1344
WIRE 2320 1360 2320 1344
WIRE 2320 1440 2320 1424
WIRE 1920 1488 1920 1440
SYMBOL VOLTAGE 1648 1088 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 2368 1216 R0
SYMATTR InstName Rload
SYMATTR Value 1
SYMBOL polcap 2304 1360 R0
SYMATTR SpiceLine Rser=50m
SYMATTR InstName C2
SYMATTR Value 100
SYMBOL cap 1744 1328 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .0015
SYMBOL ind 2192 1232 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5
SYMBOL schottky 2112 1296 M180
WINDOW 0 39 59 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value MBRS340
SYMBOL PowerProducts\\LT1506-3.3 1920 1280 R0
SYMATTR InstName U1
SYMBOL diode 2272 1072 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL cap 2112 1120 R0
SYMATTR InstName C3
SYMATTR Value .68
FLAG 2320 1440 0
FLAG 1920 1488 0
FLAG 1664 1344 0
FLAG 1648 1200 0
FLAG 2384 1328 0
FLAG 2128 1312 0
FLAG 2384 1216 OUT
FLAG 1648 1088 IN
TEXT 2128 1480 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4412.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4412.asy)
V1 N002 0 5
MQ1 N002 N003 OUT OUT FDC638P
R1 OUT N004 470K
XU1 N002 0 0 N004 N003 OUT LTC4412 ;pnba Vin)GND)CTL)STAT)Gate)Sense
D1 N001 OUT 1N5819
Rload OUT 0 100
V2 N001 0 PWL(0 0 1 7)
C1 OUT 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.lib LTC4412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2500 1444
WIRE 1760 1024 1344 1024
WIRE 2064 1024 1824 1024
WIRE 1344 1040 1344 1024
WIRE 1936 1104 1552 1104
WIRE 2064 1104 2064 1024
WIRE 2064 1104 2032 1104
WIRE 2112 1104 2064 1104
WIRE 2240 1104 2112 1104
WIRE 2336 1104 2240 1104
WIRE 2240 1120 2240 1104
WIRE 2336 1120 2336 1104
WIRE 1344 1136 1344 1120
WIRE 2112 1184 2112 1104
WIRE 1552 1216 1552 1104
WIRE 1680 1216 1552 1216
WIRE 2064 1216 2064 1104
WIRE 2064 1216 1936 1216
WIRE 2240 1216 2240 1184
WIRE 2336 1216 2336 1200
WIRE 1552 1232 1552 1216
WIRE 1680 1296 1648 1296
WIRE 2016 1296 2016 1152
WIRE 2016 1296 1936 1296
WIRE 1552 1328 1552 1312
WIRE 1680 1376 1648 1376
WIRE 2112 1376 2112 1264
WIRE 2112 1376 1936 1376
SYMBOL res 2320 1104 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL POWERPRODUCTS\\LTC4412 1808 1296 R0
SYMATTR InstName U1
SYMBOL schottky 1760 1040 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMBOL RES 2096 1168 R0
SYMATTR InstName R1
SYMATTR Value 470K
SYMBOL PMOS 1936 1152 R270
WINDOW 0 90 48 VCenter 2
WINDOW 3 63 45 VCenter 2
SYMATTR InstName Q1
SYMATTR Value FDC638P
SYMBOL cap 2224 1120 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage 1344 1024 R0
SYMATTR InstName V2
SYMATTR Value PWL(0 0 1 7)
SYMBOL VOLTAGE 1552 1216 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 1648 1376 0
FLAG 1648 1296 0
FLAG 2240 1216 0
FLAG 2336 1216 0
FLAG 1552 1328 0
FLAG 1344 1136 0
FLAG 2336 1104 OUT
TEXT 2176 1368 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT7101.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT7101.asy)
C1 OUT 0 47 Rser=15m
L1 N002 OUT 47 Rser=5m
C6 N003 0 1 IC=0 Rser=20m
XU1 MP_01 MP_02 IN MP_03 MP_04 0 0 NC_05 N003 OUT 0 0 NC_06 NC_07 NC_08 NC_09 NC_10 NC_11 0 OUT N003 MP_12 MP_13 N002 MP_14 MP_15 N001 MP_16 MP_17 IN MP_18 MP_19 MP_20 MP_21 0 LT7101 ;pnba ))Run)))SGND)OVLO)Rind)Ith)Vfb)Freq)PLLin/Mode)CLKOut)Pgood)SS)Ictrl)Imon)VPRG1)VPRG2)ExtVcc)IntVcc)))SW)))Boost)))Vin)))))PGND
C2 N001 N002 0.1 Rser=15m
Rload OUT 0 10
V1 IN 0 50
.tran 1.8m startup
.lib LT7101.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 6140 3124
WIRE 592 -256 496 -256
WIRE 624 -256 592 -256
WIRE 1040 -256 1008 -256
WIRE 496 -240 496 -256
WIRE 592 -176 592 -256
WIRE 624 -176 592 -176
WIRE 1040 -176 1040 -192
WIRE 1040 -176 1008 -176
WIRE 1104 -176 1040 -176
WIRE 1216 -176 1184 -176
WIRE 1296 -176 1216 -176
WIRE 1296 -160 1296 -176
WIRE 496 -144 496 -160
WIRE 624 -96 608 -96
WIRE 1040 -96 1008 -96
WIRE 1216 -96 1216 -176
WIRE 1216 -96 1040 -96
WIRE 1216 -80 1216 -96
WIRE 1296 -64 1296 -80
WIRE 624 -16 608 -16
WIRE 1040 -16 1040 -96
WIRE 1040 -16 1008 -16
WIRE 1216 0 1216 -16
WIRE 1072 64 1008 64
WIRE 1072 144 1072 64
WIRE 1072 144 1008 144
WIRE 1072 160 1072 144
WIRE 1072 240 1072 224
WIRE 624 304 608 304
WIRE 1024 304 1008 304
WIRE 752 400 752 384
WIRE 880 400 880 384
SYMBOL cap 1024 -256 R0
SYMATTR Value 0.1
SYMATTR SpiceLine Rser=15m
SYMATTR InstName C2
SYMBOL cap 1056 160 R0
SYMATTR Value 1
SYMATTR SpiceLine Rser=20m
SYMATTR Value2 IC=0
SYMATTR InstName C6
SYMBOL LT7101 816 48 R0
SYMATTR InstName U1
SYMBOL cap 1200 -80 R0
SYMATTR Value 47
SYMATTR SpiceLine Rser=15m
SYMATTR InstName C1
SYMBOL res 1280 -176 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL voltage 496 -256 R0
SYMATTR InstName V1
SYMATTR Value 50
SYMBOL ind 1088 -160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMATTR SpiceLine Rser=5m
FLAG 496 -144 0
FLAG 496 -256 IN
FLAG 1296 -176 OUT
FLAG 608 -96 0
FLAG 608 304 0
FLAG 1296 -64 0
FLAG 1216 0 0
FLAG 752 400 0
FLAG 880 400 0
FLAG 1024 304 0
FLAG 1072 240 0
FLAG 608 -16 0
TEXT 1152 352 Left 2 !.tran 1.8m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8542.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8542.asy)
XU1 IN N001 +V -V OUT AD8542 ;pnba In+)In-)V+)V-)OUT
Rload OUT 0 10K
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
V1 +V 0 2.5
V2 -V 0 -2.5
.tran 1m
.lib AD8542.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 576 -1152 560 -1152
WIRE 672 -1152 656 -1152
WIRE 688 -1152 672 -1152
WIRE 784 -1152 768 -1152
WIRE 336 -1040 336 -1056
WIRE 448 -1040 448 -1056
WIRE 672 -1040 672 -1152
WIRE 688 -1040 672 -1040
WIRE 784 -1024 784 -1152
WIRE 784 -1024 752 -1024
WIRE 912 -1024 784 -1024
WIRE 688 -1008 576 -1008
WIRE 912 -1008 912 -1024
WIRE 576 -992 576 -1008
WIRE 336 -944 336 -960
WIRE 448 -944 448 -960
WIRE 912 -912 912 -928
WIRE 576 -896 576 -912
SYMBOL res 672 -1168 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 896 -1024 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 336 -1056 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage 576 -1008 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 448 -1056 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 784 -1168 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL Opamps\\AD8542 720 -1088 R0
SYMATTR InstName U1
FLAG 336 -1056 +V
FLAG 336 -944 0
FLAG 576 -896 0
FLAG 912 -1024 OUT
FLAG 576 -1008 IN
FLAG 720 -1056 +V
FLAG 448 -1056 -V
FLAG 720 -992 -V
FLAG 560 -1152 0
FLAG 912 -912 0
FLAG 448 -944 0
TEXT 928 -816 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\0a82cbeaf731_PassiveBandpassFilter.asc
* Generated by LTspice 26.0.1 for Windows.
* HPF 450hz
* LPF 550hz
R1 N001 0 10k
C1 N001 in 35n
V1 in 0 SINE(0 1 500) AC 1 0
R2 out N001 10k
C2 out 0 29n
.ac dec 100 1 200000000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 96 96 96
WIRE 320 96 208 96
SYMBOL voltage 96 80 R0
WINDOW 3 -176 84 Left 2
WINDOW 123 -176 112 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0 1 500)
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMBOL res 192 80 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 416 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL cap 384 96 R0
WINDOW 0 57 32 Left 2
SYMATTR InstName C2
SYMATTR Value 29n
SYMBOL cap 208 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 35n
FLAG 208 176 0
FLAG 400 160 0
FLAG 96 176 0
FLAG 400 96 out
FLAG 96 96 in
TEXT 144 232 Left 2 ;HPF 450hz
TEXT 320 224 Left 2 ;LPF 550hz
TEXT -80 256 Left 2 !.ac dec 100 1 200000000
* Z:\home\khalils\Downloads\files\data\raw_asc\25f4e67e9dcb_IRFZ34Mosfet_simulation.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N001 .50
V3 N003 0
M1 N001 N003 0 0 PMOS
V1 N002 0 -14.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model PMOS pmos(kp=32 vt0=-1.4 lambda=0.1)
.dc V3 0 -14.8 .1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 64 144 64
WIRE 288 64 240 64
WIRE 288 96 288 64
WIRE 144 112 144 64
WIRE 0 192 -48 192
WIRE 96 192 80 192
WIRE -48 320 -48 192
WIRE 144 320 144 208
WIRE 144 320 -48 320
WIRE 288 320 288 176
WIRE 288 320 144 320
SYMBOL res 256 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value .50
SYMBOL pmos 96 112 R0
SYMATTR InstName M1
SYMBOL Misc\\battery 288 80 R0
SYMATTR InstName V1
SYMATTR Value -14.8
SYMBOL Misc\\signal 96 192 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
FLAG 144 320 0
TEXT -840 -104 Left 2 !.model PMOS pmos(kp=32 vt0=-1.4 lambda=0.1)
TEXT -840 408 Left 2 !.dc V3 0 -14.8 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1440.asc
* Generated by LTspice 26.0.1 for Windows.
* Power 2.9V Vcc Threshold Detector
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LTC1440.asy)
XU1 N002 N001 Vcc 0 OUT 0 N001 N001 LTC1440 ;pnba In+)In-)V+)V-)OUT)GND)REF)HYST
R2 Vcc N002 1.65Meg
V1 Vcc 0 PWL(0 0 1m 3.3)
R1 N002 0 1.13Meg
.tran 1m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 800
WIRE 128 176 -144 176
WIRE 368 176 128 176
WIRE -144 192 -144 176
WIRE 128 192 128 176
WIRE 368 208 368 176
WIRE 304 256 272 256
WIRE 480 272 432 272
WIRE -144 288 -144 272
WIRE 128 288 128 272
WIRE 304 288 128 288
WIRE 128 304 128 288
WIRE 272 320 272 256
WIRE 304 320 272 320
WIRE 272 352 272 320
WIRE 304 352 272 352
WIRE 128 400 128 384
WIRE 336 432 336 400
WIRE 400 432 400 400
SYMBOL res 112 288 R0
SYMATTR InstName R1
SYMATTR Value 1.13Meg
SYMBOL voltage -144 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m 3.3)
SYMBOL Comparators\\LTC1440 368 208 R0
SYMATTR InstName U1
SYMBOL res 112 176 R0
SYMATTR InstName R2
SYMATTR Value 1.65Meg
FLAG -144 288 0
FLAG 400 432 0
FLAG 336 432 0
FLAG 128 400 0
FLAG 480 272 OUT
FLAG -144 176 Vcc
TEXT 464 456 Left 2 !.tran 1m
TEXT 256 160 Bottom 2 ;Power 2.9V Vcc Threshold Detector