Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1634.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSwitch shown for a logic 0 input\nOnly one channel is modeled\nQinj is not modeled \nModeled at 5V specification\n_EN is not available on the TSSOP package
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1634.asy)
V6 vSB 0 0
XU1 vIN vSA vD vSB +V 0 0 -V ADG1634 ;pnba IN)SA)D)SB)Vdd)GND)_EN)Vss
C1 vD 0 36p
V2 -V 0 -5
V4 vIN 0 PULSE(0 3 0 10n 10n 10u 20u)
V1 +V 0 5
R1 vD 0 301
V5 vSA 0 2
.tran 120u
.lib ADG1634.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -800 -320 -800 -352
WIRE -1040 -256 -1056 -256
WIRE -928 -256 -960 -256
WIRE -896 -256 -928 -256
WIRE -672 -224 -704 -224
WIRE -608 -224 -672 -224
WIRE -528 -224 -608 -224
WIRE -1136 -192 -1152 -192
WIRE -928 -192 -1056 -192
WIRE -896 -192 -928 -192
WIRE -608 -192 -608 -224
WIRE -528 -176 -528 -224
WIRE -1376 -144 -1376 -160
WIRE -1280 -144 -1280 -160
WIRE -928 -128 -1072 -128
WIRE -896 -128 -928 -128
WIRE -672 -128 -704 -128
WIRE -672 -112 -672 -128
WIRE -608 -96 -608 -112
WIRE -528 -96 -528 -112
WIRE -1376 -48 -1376 -64
WIRE -1280 -48 -1280 -64
WIRE -1072 0 -1072 -128
WIRE -864 16 -864 -16
WIRE -736 16 -736 -16
SYMBOL cap -544 -176 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -1280 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage -1072 -16 R0
WINDOW 3 33 91 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 10u 20u)
SYMATTR InstName V4
SYMBOL voltage -1376 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -944 -256 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 2
SYMBOL res -624 -208 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG1634 -800 -176 R0
SYMATTR InstName U1
SYMBOL voltage -1040 -192 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 0
FLAG -1280 -48 0
FLAG -1376 -48 0
FLAG -1376 -160 +V
FLAG -1280 -160 -V
FLAG -1072 80 0
FLAG -1056 -256 0
FLAG -1152 -192 0
FLAG -800 -352 +V
FLAG -736 16 0
FLAG -864 16 -V
FLAG -608 -96 0
FLAG -528 -96 0
FLAG -672 -112 0
FLAG -928 -256 vSA
FLAG -928 -192 vSB
FLAG -928 -128 vIN
FLAG -672 -224 vD
TEXT -688 24 Left 2 !.tran 120u
TEXT -1408 -552 Left 2 ;Notes:\nSwitch shown for a logic 0 input\nOnly one channel is modeled\nQinj is not modeled \nModeled at 5V specification\n_EN is not available on the TSSOP package
* Z:\home\khalils\Downloads\files\data\raw_asc\024ac841a257_Fig9_24_pmos.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1) and 1/d(Id(M1)) (to get ro)
VSG 0 N001 1.15
VSD 0 N002 0
M1 0 N001 N002 0 P_1u l=2u w=30u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSD 0 5 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1224 688
WIRE 320 96 320 80
WIRE 320 192 320 176
WIRE 400 192 320 192
WIRE 448 80 320 80
WIRE 448 112 448 80
WIRE 448 304 448 208
WIRE 672 80 448 80
WIRE 672 160 448 160
WIRE 672 160 672 80
WIRE 672 192 672 160
WIRE 672 304 448 304
WIRE 672 304 672 272
WIRE 848 80 672 80
WIRE 848 112 848 80
SYMBOL pmos4 400 112 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=2u w=30u
SYMATTR InstName M1
SYMATTR Value P_1u
SYMBOL voltage 672 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 54 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VSD
SYMATTR Value 0
SYMBOL voltage 320 80 R0
WINDOW 0 -93 54 Left 0
WINDOW 3 -93 82 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSG
SYMATTR Value 1.15
FLAG 848 112 0
TEXT 384 336 Left 0 !.dc VSD 0 5 1m
TEXT 384 360 Left 0 !.lib cmosedu_models.txt
TEXT 368 48 Left 0 ;Plot Id(M1) and 1/d(Id(M1)) (to get ro)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1368.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Supply Rail Current Sense
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1368.asy)
I1 N003 0 SINE(.2 .1 1K)
XU2 N004 OUT +V 0 OUT LT1368 ;pnba In+)In-)V+)V-)OUT
C1 OUT 0 .1
R1 N001 +V 200
R2 +V N003 .1
R3 N004 0 20K
V1 +V 0 5
XU1 N003 N001 +V 0 N002 LT1368 ;pnba In+)In-)V+)V-)OUT
MQ1 N004 N002 N001 N001 BSS84
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1388 720
WIRE 32 16 -112 16
WIRE 80 16 32 16
WIRE 176 16 160 16
WIRE 384 16 176 16
WIRE -112 32 -112 16
WIRE 32 32 32 16
WIRE 224 80 224 64
WIRE 176 96 176 16
WIRE 192 96 176 96
WIRE 384 96 384 16
WIRE 608 96 496 96
WIRE 336 112 256 112
WIRE -112 128 -112 112
WIRE 32 128 32 112
WIRE 192 128 32 128
WIRE 32 144 32 128
WIRE 224 160 224 144
WIRE 544 160 544 144
WIRE 496 176 496 96
WIRE 512 176 496 176
WIRE 608 192 608 96
WIRE 608 192 576 192
WIRE 672 192 608 192
WIRE 720 192 672 192
WIRE 384 208 384 192
WIRE 512 208 384 208
WIRE 672 208 672 192
WIRE 384 224 384 208
WIRE 32 240 32 224
WIRE 544 240 544 224
WIRE 672 288 672 272
WIRE 384 320 384 304
SYMBOL current 32 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(.2 .1 1K)
SYMBOL pmos 336 192 M180
WINDOW 0 61 66 Left 2
WINDOW 3 59 31 Left 2
SYMATTR InstName Q1
SYMATTR Value BSS84
SYMBOL cap 656 208 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL opamps\\LT1368 544 128 R0
SYMATTR InstName U2
SYMBOL opamps\\LT1368 224 48 R0
SYMATTR InstName U1
SYMBOL res 368 208 R0
SYMATTR InstName R3
SYMATTR Value 20K
SYMBOL res 16 16 R0
SYMATTR InstName R2
SYMATTR Value .1
SYMBOL res 176 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL voltage -112 16 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -112 128 0
FLAG 224 64 +V
FLAG 720 192 OUT
FLAG 32 240 0
FLAG 224 160 0
FLAG 32 16 +V
FLAG 384 320 0
FLAG 544 144 +V
FLAG 544 240 0
FLAG 672 288 0
TEXT 464 312 Left 2 !.tran 3m
TEXT 408 -16 Bottom 2 ;Positive Supply Rail Current Sense
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1429CS8-4.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1429CS8-4.asy)
C4 OUT 0 3.3
R4 IN N003 3.3K
XU1 IN N002 N004 0 N005 OUT N003 N001 LTC1429CS8-4 ;pnba Vcc)C1+)C1-)GND)COMP)OUT)REG)SYNC
Rload OUT 0 100
V1 IN 0 5
C1 N002 N004 .1
V2 N001 0 PULSE(0 5 0 0 0 .25u .5u)
.tran 250u
.lib LTC1429CS8-4.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2680 1852
WIRE 2208 1408 2032 1408
WIRE 1680 1440 1584 1440
WIRE 2080 1440 1680 1440
WIRE 2208 1440 2208 1408
WIRE 1584 1456 1584 1440
WIRE 2080 1472 2080 1440
WIRE 1680 1520 1680 1440
WIRE 1712 1520 1680 1520
WIRE 2032 1520 2032 1408
WIRE 2032 1520 2000 1520
WIRE 1584 1552 1584 1536
WIRE 2208 1552 2208 1520
WIRE 1712 1584 1648 1584
WIRE 2080 1584 2080 1552
WIRE 2080 1584 2000 1584
WIRE 1712 1648 1648 1648
WIRE 2080 1648 2000 1648
WIRE 2176 1648 2080 1648
WIRE 2080 1664 2080 1648
WIRE 2176 1664 2176 1648
WIRE 1712 1712 1696 1712
WIRE 2032 1712 2000 1712
WIRE 2080 1760 2080 1728
WIRE 2176 1760 2176 1744
SYMBOL res 2064 1456 R0
SYMATTR InstName R4
SYMATTR Value 3.3K
SYMBOL VOLTAGE 1584 1440 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 1632 1584 R0
WINDOW 0 39 15 Left 2
WINDOW 3 36 48 Left 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL VOLTAGE 2208 1424 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 0 0 .25u .5u)
SYMBOL cap 2064 1664 R0
SYMATTR InstName C4
SYMATTR Value 3.3
SYMBOL RES 2160 1648 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL PowerProducts\\LTC1429CS8-4 1856 1616 R0
SYMATTR InstName U1
FLAG 1584 1552 0
FLAG 1696 1712 0
FLAG 2080 1760 0
FLAG 2176 1760 0
FLAG 2208 1552 0
FLAG 2176 1648 OUT
FLAG 1584 1440 IN
TEXT 2296 1712 Left 2 !.tran 250u
* Z:\tmp\asc_dec_bjh7r6w2\0fb434f1dcb0_ADA4625-1_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
Rf OUT N001 49.9K
Id N001 0 PULSE(0 200u 1u 1p 1p 2u 3u 2)
XU1 0 N001 +V 0 OUT ADA4625-1 ;pnba In+)In-)V+)V-)OUT
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4625-1.asy)
.lib ADA4625-1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4472 1028
WIRE -2368 -608 -2384 -608
WIRE -2272 -608 -2304 -608
WIRE -2896 -512 -3008 -512
WIRE -2800 -512 -2896 -512
WIRE -2384 -512 -2384 -608
WIRE -2384 -512 -2800 -512
WIRE -2368 -512 -2384 -512
WIRE -2272 -512 -2272 -608
WIRE -2272 -512 -2288 -512
WIRE -2800 -496 -2800 -512
WIRE -2896 -480 -2896 -512
WIRE -2384 -416 -2384 -512
WIRE -2352 -416 -2384 -416
WIRE -2896 -400 -2896 -416
WIRE -2800 -400 -2800 -416
WIRE -2272 -400 -2272 -512
WIRE -2272 -400 -2288 -400
WIRE -2240 -400 -2272 -400
WIRE -2352 -384 -2384 -384
WIRE -2384 -352 -2384 -384
SYMBOL res -2272 -528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf
SYMATTR Value 49.9K
SYMBOL current -2800 -496 R0
WINDOW 123 24 116 Left 2
WINDOW 39 24 98 Left 2
SYMATTR Value PULSE(0 200u 1u 1p 1p 2u 3u 2)
SYMATTR InstName Id
SYMBOL opamps\\ADA4625-1 -2320 -464 R0
SYMATTR InstName U1
FLAG -2240 -400 OUT
FLAG -2320 -432 +V
FLAG -2384 -352 0
FLAG -2320 -368 0
FLAG -2800 -400 0
FLAG -2896 -400 0
* Z:\home\khalils\Downloads\files\data\raw_asc\f4c0412f8e2e_NOR.asc
* Generated by LTspice 26.0.1 for Windows.
M2 N004 N003 Vout N001 C5NPMOS l=0.6u w=7.2u
M4 Vout N003 0 0 C5NNMOS l=0.6u w=3.6u
M1 N001 N002 N004 N001 C5NPMOS l=0.6u w=7.2u
VB N003 0 PULSE(0 5 0 1n 1n 10u 20u)
M3 Vout N002 0 0 C5NNMOS l=0.6u w=3.6u
VDD N001 0 5
VA N002 0 PULSE(0 5 0 1n 1n 5u 10u)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100u
.include D:\NIELIT\ENGR3426\ENGR3426\engr3426.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 -112 208 -112
WIRE 368 -112 320 -112
WIRE 368 -48 368 -112
WIRE 368 64 368 32
WIRE 208 96 208 -112
WIRE 320 144 320 -112
WIRE 320 144 208 144
WIRE -128 176 -432 176
WIRE 160 176 -128 176
WIRE -32 240 -240 240
WIRE 80 240 -32 240
WIRE 208 240 208 192
WIRE 320 288 320 144
WIRE 320 288 208 288
WIRE -432 304 -432 176
WIRE -240 304 -240 240
WIRE 80 320 80 240
WIRE 160 320 80 320
WIRE 624 336 208 336
WIRE 208 352 208 336
WIRE 208 352 96 352
WIRE 448 352 208 352
WIRE -432 416 -432 384
WIRE -240 416 -240 384
WIRE 96 416 96 352
WIRE 448 416 448 352
WIRE 208 464 96 464
WIRE 576 464 448 464
WIRE -128 496 -128 176
WIRE 48 496 -128 496
WIRE -32 528 -32 240
WIRE 400 528 400 496
WIRE 400 528 -32 528
WIRE 96 560 96 512
WIRE 256 560 96 560
WIRE 448 560 448 512
WIRE 448 560 256 560
WIRE 208 592 208 464
WIRE 256 592 256 560
WIRE 256 592 208 592
WIRE 576 592 576 464
WIRE 576 592 256 592
WIRE 256 640 256 592
IOPIN 624 336 Out
SYMBOL pmos4 160 240 R0
SYMATTR InstName M2
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL nmos4 48 416 R0
SYMATTR InstName M3
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL voltage -240 288 R0
WINDOW 3 -128 172 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VB
SYMATTR Value PULSE(0 5 0 1n 1n 10u 20u)
SYMBOL nmos4 400 416 R0
SYMATTR InstName M4
SYMATTR Value C5NNMOS
SYMATTR Value2 l=0.6u w=3.6u
SYMBOL pmos4 160 96 R0
SYMATTR InstName M1
SYMATTR Value C5NPMOS
SYMATTR Value2 l=0.6u w=7.2u
SYMBOL voltage 368 -64 R0
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL voltage -432 288 R0
WINDOW 3 -258 169 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VA
SYMATTR Value PULSE(0 5 0 1n 1n 5u 10u)
FLAG 368 64 0
FLAG -432 416 0
FLAG -240 416 0
FLAG 256 640 0
FLAG 624 336 Vout
TEXT -696 576 Left 2 !.tran 100u
TEXT -696 528 Left 2 !.include D:\\NIELIT\\ENGR3426\\ENGR3426\\engr3426.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1736.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 3
V2 N003 0 0
V3 N004 0 PULSE(0 1.17 0 1n 1n 10u 20u)
R1 N002 0 49.9
C1 N002 0 36p
V4 +V 0 5
XU1 +V N004 NC_01 N005 N002 N001 N003 NC_02 NC_03 NC_04 0 ADG1736 ;pnba VDD)IN1)IN2)EN)D1)S1A)S1B)D2)S2A)S2B)GND
V5 N005 0 1.8
.tran 100u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1736.asy)
.lib ADG1736.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2888 1548
WIRE -976 -480 -976 -512
WIRE -1088 -416 -1376 -416
WIRE -1376 -400 -1376 -416
WIRE -784 -384 -864 -384
WIRE -672 -384 -784 -384
WIRE -784 -368 -784 -384
WIRE -672 -368 -672 -384
WIRE -1088 -352 -1264 -352
WIRE -1264 -336 -1264 -352
WIRE -1376 -304 -1376 -320
WIRE -1088 -288 -1168 -288
WIRE -784 -272 -784 -288
WIRE -672 -272 -672 -304
WIRE -1264 -240 -1264 -256
WIRE -1168 -224 -1168 -288
WIRE -1168 -112 -1168 -144
WIRE -784 -96 -864 -96
WIRE -784 -80 -784 -96
WIRE -784 32 -784 0
WIRE -976 80 -976 64
FLAG -1376 -304 0
FLAG -1264 -240 0
FLAG -1168 -112 0
FLAG -976 -512 +V
FLAG -784 -272 0
FLAG -976 80 0
FLAG -672 -272 0
FLAG -1376 -80 0
FLAG -1376 -160 +V
FLAG -784 32 0
SYMBOL voltage -1376 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL voltage -1264 -352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage -1168 -240 R0
WINDOW 3 -412 256 Left 2
SYMATTR Value PULSE(0 1.17 0 1n 1n 10u 20u)
SYMATTR InstName V3
SYMBOL res -800 -384 R0
SYMATTR InstName R1
SYMATTR Value 49.9
SYMBOL cap -688 -368 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -1376 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL ADG1736 -992 -336 R0
SYMATTR InstName U1
SYMBOL voltage -784 -96 R0
WINDOW 3 32 87 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 1.8
SYMATTR InstName V5
TEXT -728 80 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8071.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8071.asy)
XU2 N001 N001 IN IN N004 N003 NC_01 OUT NC_02 N002 NC_03 0 LTM8071 ;pnba BIAS)AUX)RUN)VIN)FB)TR/SS)SHARE)VOUT)PG)RT)SYNC)GND
R2 0 N004 102K
R1 N002 0 56.2K
R3 OUT 0 1
C2 OUT 0 100
V1 IN 0 22
C1 N003 0 1n
.tran 10m startup
.lib LTM8071.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 -64 -16 -64
WIRE 192 -32 192 -64
WIRE -16 32 -16 -64
WIRE 96 32 -16 32
WIRE 480 32 384 32
WIRE 592 32 480 32
WIRE 480 48 480 32
WIRE 592 48 592 32
WIRE -16 64 -16 32
WIRE 416 128 384 128
WIRE 480 144 480 112
WIRE 592 144 592 128
WIRE -16 160 -16 144
WIRE 0 224 -16 224
WIRE 96 224 80 224
WIRE 416 224 416 128
WIRE 416 224 384 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 400 320 384 320
WIRE 496 320 480 320
WIRE 192 400 192 384
SYMBOL res 576 32 R0
SYMATTR InstName R3
SYMATTR Value 1
SYMBOL res 496 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 102K
SYMBOL res 96 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 56.2K
SYMBOL cap 464 48 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL LTM8071 240 176 R0
SYMATTR InstName U2
SYMBOL voltage -16 48 R0
SYMATTR InstName V1
SYMATTR Value 22
FLAG -16 160 0
FLAG -16 224 0
FLAG -16 320 0
FLAG 192 400 0
FLAG 496 320 0
FLAG 480 144 0
FLAG 592 144 0
FLAG -16 -64 IN
FLAG 592 32 OUT
TEXT 448 424 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4251.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4251.asy)
R1 0 N001 10K
R2 N003 N006 10
C3 N006 IN 18n
R7 N002 IN 32.4K
C4 N001 IN 1
XU1 N005 IN N001 N004 N002 N003 LTC4251 ;pnba Sense)Vee)Vin)Timer)UV/OV)Gate
V1 IN 0 PWL(0 0 1m 0 1.001m -48 220m -48 221m -70)
Rload 0 OUT 50
M1 OUT N003 N005 N005 IRF530
C5 0 OUT 100
R4 0 N002 402K
C2 N004 IN 150n
R6 N005 IN 20m
C1 N002 IN 10n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 400m
.lib LTC4251.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4692 2996
WIRE 2016 1744 2016 1728
WIRE 2640 1744 2640 1728
WIRE 2496 1760 2496 1728
WIRE 1456 1824 1456 1728
WIRE 2016 1856 2016 1824
WIRE 2272 1856 2016 1856
WIRE 2496 1856 2496 1824
WIRE 2640 1856 2640 1824
WIRE 2640 1856 2496 1856
WIRE 2768 1856 2640 1856
WIRE 2496 1872 2496 1856
WIRE 2016 1888 2016 1856
WIRE 864 1936 864 1728
WIRE 1456 1952 1456 1904
WIRE 1600 1952 1456 1952
WIRE 1824 1952 1600 1952
WIRE 2384 1952 2208 1952
WIRE 2448 1952 2384 1952
WIRE 2384 1968 2384 1952
WIRE 2272 2000 2272 1856
WIRE 1456 2032 1456 1952
WIRE 1600 2048 1600 1952
WIRE 1744 2096 1728 2096
WIRE 1824 2096 1808 2096
WIRE 2496 2096 2496 1968
WIRE 2496 2096 2208 2096
WIRE 2384 2112 2384 2048
WIRE 2496 2112 2496 2096
WIRE 864 2208 864 2016
WIRE 1456 2208 1456 2112
WIRE 1456 2208 864 2208
WIRE 1600 2208 1600 2112
WIRE 1600 2208 1456 2208
WIRE 1728 2208 1728 2096
WIRE 1728 2208 1600 2208
WIRE 2016 2208 2016 2160
WIRE 2016 2208 1728 2208
WIRE 2272 2208 2272 2064
WIRE 2272 2208 2016 2208
WIRE 2384 2208 2384 2176
WIRE 2384 2208 2272 2208
WIRE 2496 2208 2496 2192
WIRE 2496 2208 2384 2208
SYMBOL voltage 864 2032 M180
WINDOW 3 24 16 Left 2
WINDOW 0 24 96 Left 2
SYMATTR Value PWL(0 0 1m 0 1.001m -48 220m -48 221m -70)
SYMATTR InstName V1
SYMBOL cap 2256 2000 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 1440 1808 R0
SYMATTR InstName R4
SYMATTR Value 402K
SYMBOL cap 2480 1760 R0
SYMATTR InstName C5
SYMATTR Value 100
SYMBOL cap 1584 2048 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 2624 1728 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL res 2000 1728 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 2368 1952 R0
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL res 1440 2016 R0
SYMATTR InstName R7
SYMATTR Value 32.4K
SYMBOL cap 1808 2080 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 150n
SYMBOL LTC4251 2016 2016 R0
SYMATTR InstName U1
SYMBOL res 2512 2096 M0
WINDOW 0 -38 37 Left 2
WINDOW 3 -56 78 Left 2
SYMATTR InstName R6
SYMATTR Value 20m
SYMBOL cap 2368 2112 R0
SYMATTR InstName C3
SYMATTR Value 18n
SYMBOL nmos 2448 1872 R0
WINDOW 0 101 14 Right 2
WINDOW 3 140 76 Right 2
SYMATTR InstName M1
SYMATTR Value IRF530
FLAG 864 2208 IN
FLAG 2768 1856 OUT
FLAG 864 1728 0
FLAG 1456 1728 0
FLAG 2016 1728 0
FLAG 2496 1728 0
FLAG 2640 1728 0
TEXT 2632 2176 Left 2 !.tran 400m
* Z:\home\khalils\Downloads\files\data\raw_asc\f41f9ae4d06a_HW2_4109061012.asc
* Generated by LTspice 26.0.1 for Windows.
+ LD=0.08e-6 UO=350 LAMBDA=0.1 TOX=9e-9 PB=0.9 CJ=0.56e-3 CJSW=0.35e-11
+ MJ=0.45 MJSW=0.2 CGDO=0.4e-9 JS=1.0e-8)
;.dc VDD 1.62 1.98 0.01
;.ac dec 100 1 1G
;.tran 5ms
M1 N001 Vin 0 0 NMOS l=0.5u w=61u
M2 VDD N001 Vout Vout NMOS l=0.5u w=1949u
Rx VDD N001 9k
Vin Vin 0 SINE(0.76 0.04 6.283e3) AC 1 0
RL Vout 0 50
VDD VDD 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model NMOS NMOS (LEVEL=1 VTO=0.7 GAMMA=0.45 PHI=0.9 NSUB=9e+14
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1840 944
WIRE 368 16 112 16
WIRE 672 16 368 16
WIRE 112 96 112 16
WIRE 368 160 368 16
WIRE 448 208 368 208
WIRE 112 240 112 176
WIRE 320 240 112 240
WIRE 672 256 672 16
WIRE 368 288 368 256
WIRE 448 288 448 208
WIRE 448 288 368 288
WIRE 112 304 112 240
WIRE 176 352 112 352
WIRE 368 368 368 288
WIRE 496 368 368 368
WIRE 64 384 -16 384
WIRE 112 432 112 400
WIRE 176 432 176 352
WIRE 176 432 112 432
WIRE 368 448 368 368
WIRE -16 464 -16 384
WIRE -16 608 -16 544
WIRE 112 608 112 432
WIRE 368 608 368 528
WIRE 672 608 672 336
IOPIN 496 368 Out
IOPIN -16 384 In
DATAFLAG 448 368 ""
DATAFLAG 16 384 ""
SYMBOL voltage 672 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.8
SYMBOL nmos4 64 304 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.5u w=61u
SYMBOL nmos4 320 160 R0
SYMATTR InstName M2
SYMATTR Value2 l=0.5u w=1949u
SYMBOL voltage -16 448 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1 0
SYMATTR InstName Vin
SYMATTR Value SINE(0.76 0.04 6.283e3)
SYMBOL res 352 432 R0
SYMATTR InstName RL
SYMATTR Value 50
SYMBOL res 96 80 R0
SYMATTR InstName Rx
SYMATTR Value 9k
FLAG 496 368 Vout
FLAG 368 608 0
FLAG 112 608 0
FLAG -16 384 Vin
FLAG 672 608 0
FLAG -16 608 0
FLAG 368 16 VDD
TEXT 800 384 Left 2 !.model NMOS NMOS (LEVEL=1 VTO=0.7 GAMMA=0.45 PHI=0.9 NSUB=9e+14 \n+ LD=0.08e-6 UO=350 LAMBDA=0.1 TOX=9e-9 PB=0.9 CJ=0.56e-3 CJSW=0.35e-11 \n+ MJ=0.45 MJSW=0.2 CGDO=0.4e-9 JS=1.0e-8)
TEXT 800 192 Left 2 !;.dc VDD 1.62 1.98 0.01
TEXT 800 240 Left 2 !;.ac dec 100 1 1G
TEXT 800 288 Left 2 !;.tran 5ms
* Z:\home\khalils\Downloads\files\data\raw_asc\05e370202d37_Temperature-Variation-and-Worst-case-LTSpice.asc
* Generated by LTspice 26.0.1 for Windows.
* Temperature Variation Analysis with LTSpice and worst case analysis
* Temperature sweep from -20 degrees to 100 degrees with 120 degrees steps
* Obtained from:\nhttps://k6jca.blogspot.com/2012/07/monte-carlo-and-worst-case-circuit.html
R1 N002 0 {wc(10k, tol)}
D1 N002 N001 BZX84C6V2L
V1 N001 0 12
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.step temp -20 100 120
.tran 1
.param tol=0.2
.step param run 1 50 1
.function wc(nom, tol) if(run==1, nom, if(flat(1) > 0, nom*(1+tol), nom*(1-tol)))
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1320 680
WIRE 224 -32 -96 -32
WIRE 224 0 224 -32
WIRE -96 96 -96 -32
WIRE 224 96 224 64
WIRE -96 208 -96 176
WIRE 224 208 224 176
SYMBOL zener 240 64 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C6V2L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 208 80 R0
SYMATTR InstName R1
SYMATTR Value {wc(10k, tol)}
SYMBOL voltage -96 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 224 208 0
FLAG -96 208 0
TEXT 456 -40 Left 2 !.step temp -20 100 120
TEXT 456 8 Left 2 !.tran 1
TEXT -160 -208 Left 4 ;Temperature Variation Analysis with LTSpice and worst case analysis
TEXT 456 -80 Left 2 ;Temperature sweep from -20 degrees to 100 degrees with 120 degrees steps
TEXT 456 56 Left 2 !.param tol=0.2
TEXT 456 104 Left 2 !.step param run 1 50 1
TEXT 456 160 Left 2 !.function wc(nom, tol) if(run==1, nom, if(flat(1) > 0, nom*(1+tol), nom*(1-tol)))
TEXT 456 224 Left 2 ;Obtained from:\nhttps://k6jca.blogspot.com/2012/07/monte-carlo-and-worst-case-circuit.html