* Z:\home\khalils\Downloads\files\data\raw_asc\6908df4e63d3_OutputStage_1_.asc
* Generated by LTspice 26.0.1 for Windows.
* INSTRUCTIONS--1-dB COMPRESSION POINT OF OUTPUT STAGE:\n-Replace output-stage circuit with your own design.\n-Change RTH resistance to the estimated value of the Thevenin \n equivalent output resistance of your gain stage.\n-Change VTH voltage to the estimated value of the voltage bias\n at the output of your gain stage.\n-Run simluation.\n-Open Error Log (View->SPICE Error Log)\n-Right-mouse-click on Error Log\n-Select "Plot .step'ed .meas data"\n-Right-mouse-click on Plot Window\n-Select "Add Plot Pane"\n-Right-mouse-click on lower plot pane\n-Select "Add Traces"\n-Left-mouse-click "gain"\n-Left-mouse-click OK\n-Right-mouse-click on plot title "gain" and change this statement\n to "20*log10(gain)"\n-Right-mouse-click on upper plot pane\n-Select "Add Traces"\n-Left-mouse-click "vOUTrms"\n-Left-mouse-click OK\n-Right-mouse-click on plot title "vOUTrms" and change this statement\n to "20*log10(vOUTrms/1m)"\n-Right-mouse-click on axes label "vSIG" and change this statement\n to "20*log10(vsig/(1m*sqrt(2)))"\n-To save these plot settings, select "Plot Settings-->Save Plot Settings"\n (you will need to close the plot window and open a new one after running \n another simultation; it does not automatically update)\n-Determine the input 1-dB compression point value of vSIG--where the gain\n deviates by 1-dB\n-Determine the correpsonding output 1-dB compression point value of \n 20*log10(vOUTrms/1m)"\n-Ensure that your output 1-dB compression point meets the specification.\n \nINSTRUCTIONS--TRANSIENT CURRENT CONSUMPTION:\n-Place cursor over output node of VCC.\n-Left-mouse click to plot I(VCC).\n-Left-mouse click on collector or drain node of a transistor to plot \n its transient collector current.\n-Ensure that the value does not exceed the current rating of transistor.\n \nINSTRUCTIONS--QUIESCENT CURRENT CONSUMPTION\n-Comment-out the .tran, .step, and .meas SPICE directives by \n hovering cursor over directive and right-mouse-clicking.\n If ".meas Statement Editor" window appears left-mouse-click "Cancel."\n-Run simulation.\n-A DC operating point window will appear; the value of I(Vcc) is your \n quiescent current consumption.\n \nADDITIONAL NOTE:\nTo place an additional voltage node label, right-mouse-click on a circuit node\nafter running simulation then left-mouse-click on "Place .op Data Labe" (sic).
* DESIGN STRATEGY:\n-Simulate for an small-signal input voltage range that is multiplied by the gain factor of the common emitter stage\n-Set RTH to output resistance of common emitter stage (estimate: RC1)\n-Adjust VTH so that DC voltage at base of Q2 equals DC output voltage of common emitter stage.\n-Adjust RE2 and RE3 for desired DC levels at base and emitter of Q3\n-Circuit will have a voltage gain of less than unity. Important characteristic is dynamic range.
RTH N004 IN 750
VTH N005 0 -.6205
Q2 N006 N004 N002 0 2N3906
RSpeaker OUT 0 32
CDCB_4 OUT N003 10m
VSignal IN N005 SINE(0 {vSIG} 261.626) Rser=50
Q3 N001 N002 N003 0 2N3904
VEE 0 N006 6
VCC N001 0 6
RE2 N001 N002 100
RE3 N003 N006 60
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.step dec param vSIG 2.828m 2.828 10
.tran 0 0.08791175 0.07644500 0.00382225
.meas TRAN vOUTrms RMS V(OUT)
.meas TRAN gain PP 0.5*V(OUT)/vSIG
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2440 1168
WIRE 272 -304 96 -304
WIRE 576 -304 272 -304
WIRE 96 -272 96 -304
WIRE 576 -272 576 -304
WIRE 272 -176 272 -304
WIRE 96 -128 96 -192
WIRE 208 -128 96 -128
WIRE 96 -80 96 -128
WIRE 272 -48 272 -80
WIRE 336 -48 272 -48
WIRE 448 -48 400 -48
WIRE 464 -48 448 -48
WIRE 576 -48 576 -192
WIRE 608 -48 576 -48
WIRE -416 -32 -432 -32
WIRE -256 -32 -416 -32
WIRE 32 -32 -176 -32
WIRE 272 -16 272 -48
WIRE 608 -16 608 -48
WIRE -416 0 -416 -32
WIRE 448 16 448 -48
WIRE 576 128 576 -48
WIRE -416 144 -416 80
WIRE 448 160 448 96
WIRE 96 240 96 16
WIRE 272 240 272 64
WIRE 272 240 96 240
WIRE 576 240 576 208
WIRE 576 240 272 240
WIRE -416 256 -416 224
IOPIN 464 -48 Out
IOPIN -432 -32 In
DATAFLAG -64 -32 ""
DATAFLAG 160 -128 ""
DATAFLAG 304 -48 ""
SYMBOL res -160 -48 R90
WINDOW 0 -28 57 VBottom 2
WINDOW 3 2 56 VBottom 2
SYMATTR InstName RTH
SYMATTR Value 750
SYMBOL voltage -416 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VTH
SYMATTR Value -.6205
SYMBOL res 256 -32 R0
WINDOW 3 36 68 Left 2
SYMATTR Value 60
SYMATTR InstName RE3
SYMBOL cap 400 -64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName DCB_4
SYMATTR Value 10m
SYMBOL pnp 32 16 M180
SYMATTR InstName Q2
SYMATTR Value 2N3906
SYMBOL voltage 576 -288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCC
SYMATTR Value 6
SYMBOL res 432 0 R0
SYMATTR InstName Speaker
SYMATTR Value 32
SYMBOL npn 208 -176 R0
SYMATTR InstName Q3
SYMATTR Value 2N3904
SYMBOL voltage -416 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName Signal
SYMATTR Value SINE(0 {vSIG} 261.626)
SYMBOL res 80 -288 R0
WINDOW 3 36 68 Left 2
SYMATTR Value 100
SYMATTR InstName RE2
SYMBOL voltage 576 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VEE
SYMATTR Value 6
FLAG -416 256 0
FLAG 464 -48 OUT
FLAG -432 -32 IN
FLAG 448 160 0
FLAG 608 -16 0
TEXT -632 -216 Left 2 !.step dec param vSIG 2.828m 2.828 10
TEXT -632 -248 Left 2 !.tran 0 0.08791175 0.07644500 0.00382225
TEXT -632 -184 Left 2 !.meas TRAN vOUTrms RMS V(OUT)\n.meas TRAN gain PP 0.5*V(OUT)/vSIG
TEXT -632 -280 Left 2 !.op
TEXT 712 -304 Left 2 ;INSTRUCTIONS--1-dB COMPRESSION POINT OF OUTPUT STAGE:\n-Replace output-stage circuit with your own design.\n-Change RTH resistance to the estimated value of the Thevenin \n equivalent output resistance of your gain stage.\n-Change VTH voltage to the estimated value of the voltage bias\n at the output of your gain stage.\n-Run simluation.\n-Open Error Log (View->SPICE Error Log)\n-Right-mouse-click on Error Log\n-Select "Plot .step'ed .meas data"\n-Right-mouse-click on Plot Window\n-Select "Add Plot Pane"\n-Right-mouse-click on lower plot pane\n-Select "Add Traces"\n-Left-mouse-click "gain"\n-Left-mouse-click OK\n-Right-mouse-click on plot title "gain" and change this statement\n to "20*log10(gain)"\n-Right-mouse-click on upper plot pane\n-Select "Add Traces"\n-Left-mouse-click "vOUTrms"\n-Left-mouse-click OK\n-Right-mouse-click on plot title "vOUTrms" and change this statement\n to "20*log10(vOUTrms/1m)"\n-Right-mouse-click on axes label "vSIG" and change this statement\n to "20*log10(vsig/(1m*sqrt(2)))"\n-To save these plot settings, select "Plot Settings-->Save Plot Settings"\n (you will need to close the plot window and open a new one after running \n another simultation; it does not automatically update)\n-Determine the input 1-dB compression point value of vSIG--where the gain\n deviates by 1-dB\n-Determine the correpsonding output 1-dB compression point value of \n 20*log10(vOUTrms/1m)"\n-Ensure that your output 1-dB compression point meets the specification.\n \nINSTRUCTIONS--TRANSIENT CURRENT CONSUMPTION:\n-Place cursor over output node of VCC.\n-Left-mouse click to plot I(VCC).\n-Left-mouse click on collector or drain node of a transistor to plot \n its transient collector current.\n-Ensure that the value does not exceed the current rating of transistor.\n \nINSTRUCTIONS--QUIESCENT CURRENT CONSUMPTION\n-Comment-out the .tran, .step, and .meas SPICE directives by \n hovering cursor over directive and right-mouse-clicking.\n If ".meas Statement Editor" window appears left-mouse-click "Cancel."\n-Run simulation.\n-A DC operating point window will appear; the value of I(Vcc) is your \n quiescent current consumption.\n \nADDITIONAL NOTE:\nTo place an additional voltage node label, right-mouse-click on a circuit node\nafter running simulation then left-mouse-click on "Place .op Data Labe" (sic).
TEXT -632 320 Left 2 ;DESIGN STRATEGY:\n-Simulate for an small-signal input voltage range that is multiplied by the gain factor of the common emitter stage\n-Set RTH to output resistance of common emitter stage (estimate: RC1)\n-Adjust VTH so that DC voltage at base of Q2 equals DC output voltage of common emitter stage.\n-Adjust RE2 and RE3 for desired DC levels at base and emitter of Q3\n-Circuit will have a voltage gain of less than unity. Important characteristic is dynamic range.