Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\8cf32c8bc78a_XtalTest_1Mhz_Osc.asc
* Generated by LTspice 26.0.1 for Windows.
* 1MHz Crystal Oscillator
* Unbuffered Gate
* NOTE: for ac loop gain is V(4)/V(1)
I2 2 3 PULSE(0 23 100n 10n 10n 10n 1u 1)
Di 0 i Clamp
R1 2 1 3k3
Bo 0 4 I=limit(30*(2.5-V(i)),0,5) Rpar=1 tripdt=1n
CX1 3 2 .0127pF Lser=2H Rser=200 Cpar=4pF
Ri i 3 100
V1 4 1 AC 1
C3 3 0 10p
C2 2 0 100p
R2 4 3 3.3Meg
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 10m 100u 10n
.model Clamp D(Vfwd=.5 Vrev=5.5)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1656 1100
WIRE 528 304 576 304
WIRE 320 304 384 304
WIRE 608 304 608 336
WIRE 608 400 608 416
WIRE 384 336 384 304
WIRE 384 304 416 304
WIRE 208 304 240 304
WIRE 576 304 608 304
WIRE 176 304 208 304
WIRE 928 416 928 400
WIRE 800 304 832 304
WIRE 848 304 848 336
WIRE 848 400 848 416
WIRE 928 208 928 320
WIRE 832 304 848 304
WIRE 384 208 384 304
WIRE 544 208 608 208
WIRE 608 208 608 304
WIRE 416 304 464 304
WIRE 464 208 384 208
WIRE 672 208 672 304
WIRE 672 304 720 304
WIRE 928 208 848 208
WIRE 768 208 672 208
WIRE 176 304 176 240
WIRE 176 96 208 96
WIRE 928 96 928 208
WIRE 384 416 384 400
WIRE 608 304 672 304
WIRE 176 160 176 96
WIRE 208 96 928 96
SYMBOL res 816 288 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName Ri
SYMATTR Value 100
SYMBOL bi 928 400 M180
WINDOW 0 39 48 Left 0
WINDOW 3 40 24 Left 0
WINDOW 123 40 0 Left 0
SYMATTR InstName Bo
SYMATTR Value I=limit(30*(2.5-V(i)),0,5)
SYMATTR Value2 Rpar=1 tripdt=1n
SYMBOL cap 592 336 R0
WINDOW 0 32 16 Left 0
WINDOW 3 32 48 Left 0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL voltage 176 144 R0
WINDOW 0 40 48 Left 0
WINDOW 3 40 71 Left 0
WINDOW 123 40 72 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 336 288 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 3k3
SYMBOL zener 864 400 R180
WINDOW 0 40 48 Left 0
WINDOW 3 40 16 Left 0
SYMATTR InstName Di
SYMATTR Value Clamp
SYMBOL cap 400 336 M0
WINDOW 0 32 16 Left 0
WINDOW 3 32 48 Left 0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL Misc\\xtal 528 288 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
WINDOW 39 80 32 VTop 0
WINDOW 123 56 32 VTop 0
WINDOW 40 104 32 VTop 0
SYMATTR InstName X1
SYMATTR Value .0127pF
SYMATTR SpiceLine Rser=200
SYMATTR Value2 Lser=2H
SYMATTR SpiceLine2 Cpar=4pF
SYMBOL current 464 208 M90
WINDOW 0 -32 32 VBottom 0
WINDOW 3 -56 32 VBottom 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I2
SYMATTR Value PULSE(0 23 100n 10n 10n 10n 1u 1)
SYMBOL res 864 192 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 3.3Meg
FLAG 384 416 0
FLAG 608 416 0
FLAG 208 304 1
FLAG 416 304 2
FLAG 576 304 3
FLAG 928 416 0
FLAG 848 416 0
FLAG 832 304 i
FLAG 208 96 4
TEXT 128 464 Left 0 !.tran 0 10m 100u 10n
TEXT 128 496 Left 0 !.ac lin 1000 990k 1010k
TEXT 848 464 Center 0 !.model Clamp D(Vfwd=.5 Vrev=5.5)
TEXT 560 16 Center 0 ;1MHz Crystal Oscillator
TEXT 976 288 Left 0 ;Unbuffered Gate
TEXT 560 64 Center 0 ;NOTE: for ac loop gain is V(4)/V(1)
* Z:\home\khalils\Downloads\files\data\raw_asc\0c27a2b21502_final_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .tf V(Vout) V1
* .tran 5m
M1 Vout Vin 0 0 NMOS l=0.72u w=3.57u
V2 Vdd 0 1.8
C1 Vout 0 1p
V1 Vin 0 SINE(0.75 1m 1k) AC 1
M2 Vout Vout Vdd Vdd PMOS l=0.72u w=5.50u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.options plotwinsize=0
.include tsmc180.txt
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -80 240 -144
WIRE 352 -80 240 -80
WIRE 240 -32 240 -80
WIRE 192 -16 160 -16
WIRE 352 16 352 -80
WIRE 352 16 240 16
WIRE 160 80 160 -16
WIRE 240 80 240 64
WIRE 240 80 160 80
WIRE 240 112 240 80
WIRE 512 112 240 112
WIRE 576 112 512 112
WIRE 240 144 240 112
WIRE 512 160 512 112
WIRE 352 192 240 192
WIRE 192 224 80 224
WIRE -256 240 -256 192
WIRE -128 240 -128 192
WIRE 240 288 240 240
WIRE 352 288 352 192
WIRE 352 288 240 288
WIRE 512 288 512 224
WIRE 240 336 240 288
WIRE -256 400 -256 320
WIRE -128 400 -128 320
IOPIN 576 112 Out
SYMBOL voltage -256 224 R0
WINDOW 3 -257 105 Left 2
WINDOW 123 -137 145 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0.75 1m 1k)
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL pmos4 192 64 M180
WINDOW 123 56 4 Left 2
SYMATTR Value2 l=0.72u w=5.50u
SYMATTR InstName M2
SYMBOL voltage -128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL cap 496 160 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL nmos4 192 144 R0
WINDOW 123 66 165 Left 2
SYMATTR Value2 l=0.72u w=3.57u
SYMATTR InstName M1
FLAG -256 400 0
FLAG -128 400 0
FLAG -256 192 Vin
FLAG -128 192 Vdd
FLAG 240 336 0
FLAG 512 288 0
FLAG 80 224 Vin
FLAG 576 112 Vout
FLAG 240 -144 Vdd
TEXT -328 -136 Left 2 !.options plotwinsize=0
TEXT -328 -104 Left 2 !.include tsmc180.txt
TEXT -328 -80 Left 2 ;.op
TEXT -328 -48 Left 2 ;.tf V(Vout) V1
TEXT -328 -16 Left 2 ;.tran 5m
TEXT -328 16 Left 2 !.ac dec 10 10 1gig
* Z:\home\khalils\Downloads\files\data\raw_asc\57038050a92b_GM1.asc
* Generated by LTspice 26.0.1 for Windows.
M1 dm N001 sp sp P_1u l={Lp2} w={Wp2}
vsp sp 0 1.1367383V
vdm dm 0 -1.3427744
vinN N001 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.inc cmosedu_models.txt
.dc vinN -2.5 2.5 0.0001
.meas gm FIND d(Id(M1)) AT 0
.param Wp=49.992332u Lp=49.986531u Wp2=49.998294u Lp2=9.069192u Wn=41.548244u Ln=47.775368u Wn2=49.906981u Ln2=28.964298u C=0.100001p Iref=10892.687537n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2468 680
WIRE 1056 -112 1056 -160
WIRE 1152 -112 1056 -112
WIRE 1008 -96 880 -96
WIRE 1152 -64 1152 -112
WIRE 1152 -64 1056 -64
WIRE 496 -16 496 -48
WIRE 688 -16 688 -48
WIRE 880 -16 880 -96
WIRE 1056 64 1056 -16
WIRE 496 128 496 64
WIRE 688 128 688 64
WIRE 880 128 880 64
SYMBOL voltage 496 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 24 90 Left 2
SYMATTR Value 1.1367383V
SYMATTR InstName vsp
SYMBOL voltage 880 -32 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value ""
SYMATTR InstName vinN
SYMBOL voltage 688 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 24 90 Left 2
SYMATTR Value -1.3427744
SYMATTR InstName vdm
SYMBOL pmos4 1008 -16 M180
SYMATTR InstName M1
SYMATTR Value2 l={Lp2} w={Wp2}
SYMATTR Value P_1u
FLAG 880 128 0
FLAG 496 -48 sp
FLAG 496 128 0
FLAG 1056 -160 sp
FLAG 688 -48 dm
FLAG 688 128 0
FLAG 1056 64 dm
TEXT 472 192 Left 2 !.inc cmosedu_models.txt
TEXT 472 248 Left 2 !.dc vinN -2.5 2.5 0.0001
TEXT 472 168 Left 2 !.meas gm FIND d(Id(M1)) AT 0
TEXT 272 272 Left 2 !.param Wp=49.992332u Lp=49.986531u Wp2=49.998294u Lp2=9.069192u Wn=41.548244u Ln=47.775368u Wn2=49.906981u Ln2=28.964298u C=0.100001p Iref=10892.687537n
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1708.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5.5
R1 OUT N001 187k
R2 N001 0 59k
C2 OUT 0 4.7
Rload OUT 0 100
C1 IN 0 4.7
XU1 OUT OUT N001 0 IN MP_01 MP_02 IN ADP1708 ;pnba Vout)Sense)Adj)GND)En)))Vin
.tran 10m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1708.asy)
.lib ADP1708.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 496 16 256 16
WIRE 256 48 256 16
WIRE 48 96 -32 96
WIRE 128 96 48 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 496 96 496 16
WIRE 496 96 384 96
WIRE 576 96 496 96
WIRE -32 112 -32 96
WIRE 48 112 48 96
WIRE 384 112 384 96
WIRE 496 112 496 96
WIRE 576 112 576 96
WIRE -32 208 -32 192
WIRE 48 208 48 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 192
WIRE 384 208 352 208
WIRE 496 208 496 176
WIRE 576 208 576 192
WIRE 384 224 384 208
WIRE 256 272 256 256
WIRE 384 320 384 304
FLAG -32 208 0
FLAG 256 272 0
FLAG 384 320 0
FLAG 496 208 0
FLAG 576 208 0
FLAG 576 96 OUT
FLAG -32 96 IN
FLAG 48 208 0
SYMBOL voltage -32 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL res 368 96 R0
SYMATTR InstName R1
SYMATTR Value 187k
SYMBOL res 368 208 R0
SYMATTR InstName R2
SYMATTR Value 59k
SYMBOL cap 480 112 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL res 560 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 32 112 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL ADP1708 256 160 R0
SYMATTR InstName U1
TEXT -8 304 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8570-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8570-1.asy)
L1 IN N001 220 Rser=50m
C1 OUT 0 .22 Rser=5m
V1 IN 0 12
C3 N003 0 .001
D1 N001 OUT 1N4148
R1 N005 0 69.8K
Rload OUT 0 960
R2 OUT N004 562K
XU1 N004 N006 IN N001 N002 N005 N003 MP_01 0 LT8570-1 ;pnba FBX)Vc)Vin)SW)_SHDN)Rt)SS))GND
C2 0 N006 3300p Rser=8.87K Cpar=47p
R3 IN N002 576K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 600u startup
.lib LT8570-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -112 96 -208 96
WIRE 128 96 -112 96
WIRE 176 96 128 96
WIRE 304 96 256 96
WIRE 336 96 304 96
WIRE 464 96 400 96
WIRE 512 96 464 96
WIRE 608 96 512 96
WIRE -208 112 -208 96
WIRE -112 112 -112 96
WIRE 512 112 512 96
WIRE 608 112 608 96
WIRE 128 144 128 96
WIRE -208 208 -208 192
WIRE -112 208 -112 192
WIRE -16 208 -112 208
WIRE 304 208 304 96
WIRE 304 208 272 208
WIRE 512 208 512 176
WIRE 608 208 608 192
WIRE -96 288 -128 288
WIRE -16 288 -32 288
WIRE 368 288 272 288
WIRE 464 288 464 96
WIRE 464 288 448 288
WIRE -112 368 -128 368
WIRE -16 368 -32 368
WIRE 320 368 272 368
WIRE 416 368 384 368
WIRE 128 448 128 432
SYMBOL PowerProducts\\LT8570-1 128 288 R0
SYMATTR InstName U1
SYMBOL res -128 96 R0
SYMATTR InstName R3
SYMATTR Value 576K
SYMBOL cap 496 112 R0
SYMATTR InstName C1
SYMATTR Value .22
SYMATTR SpiceLine Rser=5m
SYMBOL voltage -208 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 384 352 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
WINDOW 39 59 -25 VTop 2
SYMATTR InstName C2
SYMATTR Value 3300p
SYMATTR SpiceLine Rser=8.87K Cpar=47p
SYMBOL ind 160 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 220
SYMATTR SpiceLine Rser=50m
SYMBOL diode 336 112 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 464 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 562K
SYMBOL res -16 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 69.8K
SYMBOL cap -32 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL res 592 96 R0
SYMATTR InstName Rload
SYMATTR Value 960
FLAG 128 448 0
FLAG 512 208 0
FLAG 416 368 0
FLAG -128 368 0
FLAG -128 288 0
FLAG -208 208 0
FLAG 608 208 0
FLAG -208 96 IN
FLAG 608 96 OUT
TEXT 264 472 Left 2 !.tran 600u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1376.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1376.asy)
Rload OUT 0 10
D1 OUT N001 1N4148
D2 0 N002 MBRS340
XU1 N001 IN N002 OUT N003 0 N005 N004 LT1376 top=10 bot=1T ;pnba Boost)Vin)SW)BIAS)_SHDN)GND)FB)Vc
C3 N001 N002 .1
C5 OUT 0 1
C2 OUT 0 100 Rser=0.05
R2 N005 0 4.99K
L1 N002 OUT 5 Rser=0.02 Rpar=5000
V1 IN 0 10
R1 OUT N005 5.36K
C4 N004 0 3300p
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.lib LT1376.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2264 1200
WIRE 1456 640 1296 640
WIRE 1536 640 1456 640
WIRE 1632 640 1600 640
WIRE 1136 656 960 656
WIRE 1456 656 1456 640
WIRE 960 672 960 656
WIRE 1136 704 1136 656
WIRE 1296 704 1296 640
WIRE 1456 736 1456 720
WIRE 1456 736 1408 736
WIRE 1520 736 1456 736
WIRE 1632 736 1632 640
WIRE 1632 736 1600 736
WIRE 1456 752 1456 736
WIRE 960 768 960 752
WIRE 1056 784 1040 784
WIRE 1408 784 1408 736
WIRE 1408 784 1376 784
WIRE 1456 832 1456 816
WIRE 1632 864 1632 736
WIRE 1632 864 1376 864
WIRE 1744 864 1632 864
WIRE 1840 864 1744 864
WIRE 1920 864 1840 864
WIRE 1632 880 1632 864
WIRE 1744 880 1744 864
WIRE 1840 880 1840 864
WIRE 1920 880 1920 864
WIRE 976 944 960 944
WIRE 1056 944 1040 944
WIRE 1408 944 1376 944
WIRE 1408 976 1408 944
WIRE 1632 976 1632 960
WIRE 1632 976 1408 976
WIRE 1744 976 1744 944
WIRE 1840 976 1840 944
WIRE 1920 976 1920 960
WIRE 1632 992 1632 976
WIRE 1216 1040 1216 1024
WIRE 1632 1088 1632 1072
SYMBOL IND 1504 752 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL DIODE 1600 624 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL POWERPRODUCTS\\LT1376 1216 864 R0
SYMATTR InstName U1
SYMBOL res 1904 864 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL POLCAP 1440 656 R0
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL VOLTAGE 960 656 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL RES 1616 976 R0
SYMATTR InstName R2
SYMATTR Value 4.99K
SYMBOL polcap 1728 880 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.05
SYMBOL res 1616 864 R0
SYMATTR InstName R1
SYMATTR Value 5.36K
SYMBOL cap 1040 928 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 3300p
SYMBOL POLCAP 1824 880 R0
SYMATTR InstName C5
SYMATTR Value 1
SYMBOL schottky 1440 816 M180
WINDOW 0 33 59 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value MBRS340
FLAG 1632 1088 0
FLAG 1840 976 0
FLAG 1456 832 0
FLAG 1920 976 0
FLAG 1744 976 0
FLAG 1216 1040 0
FLAG 960 768 0
FLAG 960 944 0
FLAG 1920 864 OUT
FLAG 960 656 IN
TEXT 1760 1112 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7185-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7185-1.8.asy)
R3 OUT 0 3.6
V1 IN 0 -2.3
XU1 OUT OUT N001 N002 IN 0 N003 IN ADP7185-1.8 ;pnba Vout)Sense)VA)VAFB)EN)GND)Vreg)Vin
C4 N003 0 1
C1 N001 N002 10n
C3 N001 0 1
C2 OUT 0 4.7 Rser=5m
.tran 200m startup
.lib ADP7185-1.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 16 -48
WIRE 96 -48 32 -48
WIRE 112 -48 96 -48
WIRE 400 -48 368 -48
WIRE 432 -48 400 -48
WIRE 496 -48 432 -48
WIRE 512 -48 496 -48
WIRE 16 -32 16 -48
WIRE 432 -32 432 -48
WIRE 512 -32 512 -48
WIRE 400 16 400 -48
WIRE 400 16 368 16
WIRE 432 48 432 32
WIRE 16 64 16 48
WIRE 512 64 512 48
WIRE 96 80 96 -48
WIRE 112 80 96 80
WIRE 464 80 368 80
WIRE 384 144 368 144
WIRE 464 144 464 80
WIRE 464 144 448 144
WIRE 464 160 464 144
WIRE 176 224 176 208
WIRE 304 224 304 208
WIRE 464 240 464 224
WIRE 176 320 176 288
SYMBOL cap 448 160 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 160 224 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=5m
SYMBOL res 496 -48 R0
SYMATTR InstName R3
SYMATTR Value 3.6
SYMBOL ADP7185-1.8 240 48 R0
SYMATTR InstName U1
SYMBOL cap 448 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage 16 -48 R0
SYMATTR InstName V1
SYMATTR Value -2.3
FLAG 16 64 0
FLAG 432 48 0
FLAG 304 224 0
FLAG 512 64 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 464 240 0
FLAG 176 320 0
TEXT 136 368 Left 2 !.tran 200m startup
* Z:\tmp\asc_dec_bjh7r6w2\0a2292c5498b_Interview01_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
RL N001 N004 33
Q1 N002 N003 N005 0 2N2222
R4 N007 N008 R=if(time>300m,100,500)
R3 N002 N003 750
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1808 1000
WIRE 288 128 80 128
WIRE 784 128 288 128
WIRE 288 160 288 128
WIRE 288 272 288 240
WIRE 496 272 288 272
WIRE 656 272 496 272
WIRE 496 288 496 272
WIRE 784 288 784 128
WIRE 288 400 288 272
WIRE 656 400 656 272
WIRE 496 448 496 368
WIRE 592 448 496 448
WIRE 784 464 784 368
WIRE 496 512 496 448
WIRE 656 512 656 496
WIRE 720 512 656 512
WIRE 288 544 288 464
WIRE 784 576 784 560
WIRE 496 656 496 576
WIRE 784 656 496 656
SYMBOL res 768 272 R0
SYMATTR InstName RL
SYMATTR Value 33
SYMBOL npn 592 400 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL res 768 560 R0
SYMATTR InstName R4
SYMATTR Value R=if(time>300m,100,500)
SYMBOL res 480 272 R0
SYMATTR InstName R3
SYMATTR Value 750
* Z:\home\khalils\Downloads\files\data\raw_asc\6a2fba6b1e07_Draft56.asc
* Generated by LTspice 26.0.1 for Windows.
V2 VCC 0 15
V3 0 VEE 15
Q3 VCC N002 N003 0 2N3904
Q4 VEE N002 N003 0 2N3906
V1 N001 0 5
R1 N003 N001 100k
R2 N002 N001 100G
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 1ms
* bootstrapping the emitters, still leaves voltage offset at the base\nand some leakage.
* there's a voltage offset of 0.57V or so.\n \n10G we get -9pA leakaage\n1G get -9pA.\n100Meg -9pA.
* bootstrap
* signal impedance
* DOES NOT MAKE SENSE.\njust pulling a opto-led again a low-imipedance diode clamp\nwill be just as strong,
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1904 680
WIRE 48 -96 -16 -96
WIRE 464 -96 128 -96
WIRE -192 80 -272 80
WIRE 384 80 352 80
WIRE -272 96 -272 80
WIRE -192 96 -192 80
WIRE -16 128 -16 -96
WIRE 48 128 -16 128
WIRE 288 128 128 128
WIRE 384 128 384 80
WIRE 464 128 464 -96
WIRE 464 128 384 128
WIRE 480 128 464 128
WIRE 384 176 384 128
WIRE 384 176 352 176
WIRE -16 368 -16 128
FLAG -192 96 0
FLAG -272 0 VCC
FLAG -272 176 VEE
FLAG 288 32 VCC
FLAG 288 224 VEE
FLAG -16 448 0
SYMBOL voltage -272 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value 15
SYMATTR InstName V2
SYMBOL voltage -272 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 36 39 Left 2
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL npn 352 32 M0
SYMATTR InstName Q3
SYMATTR Value 2N3904
SYMBOL pnp 352 224 R180
SYMATTR InstName Q4
SYMATTR Value 2N3906
SYMBOL voltage -16 352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 144 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 144 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100G
TEXT -456 304 Left 2 !.tran 1ms
TEXT -1144 -8 Left 2 ;bootstrapping the emitters, still leaves voltage offset at the base\nand some leakage.
TEXT 592 -40 Left 2 ;there's a voltage offset of 0.57V or so.\n \n10G we get -9pA leakaage\n1G get -9pA.\n100Meg -9pA.
TEXT 40 64 Left 2 ;bootstrap
TEXT 40 -160 Left 2 ;signal impedance
TEXT 624 -168 Left 2 ;DOES NOT MAKE SENSE.\njust pulling a opto-led again a low-imipedance diode clamp\nwill be just as strong,
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1261LCS8-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1261LCS8-4.5.asy)
C1 N002 N004 .1
R1 IN N003 3.3K
XU1 IN N002 N004 0 N005 OUT N003 N001 LTC1261LCS8-4.5 ;pnba Vcc)C1+)C1-)GND)COMP)OUT)REG)SHDN
V1 IN 0 5
Rload OUT 0 1K
C2 OUT 0 3.3
.tran 1m
.lib LTC1261LCS8-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2264 2544
WIRE 1680 1824 1504 1824
WIRE 2048 1824 1680 1824
WIRE 1504 1840 1504 1824
WIRE 2048 1856 2048 1824
WIRE 1680 1904 1680 1824
WIRE 1712 1904 1680 1904
WIRE 2016 1904 2000 1904
WIRE 1504 1936 1504 1920
WIRE 1712 1968 1648 1968
WIRE 2048 1968 2048 1936
WIRE 2048 1968 2000 1968
WIRE 1712 2032 1648 2032
WIRE 2048 2032 2000 2032
WIRE 2144 2032 2048 2032
WIRE 2048 2048 2048 2032
WIRE 2144 2048 2144 2032
WIRE 1712 2096 1696 2096
WIRE 2016 2096 2000 2096
WIRE 2048 2144 2048 2112
WIRE 2144 2144 2144 2128
SYMBOL VOLTAGE 1504 1824 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LTC1261LCS8-4.5 1856 2000 R0
SYMATTR InstName U1
SYMBOL cap 1632 1968 R0
WINDOW 0 35 16 Left 2
WINDOW 3 32 49 Left 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL RES 2128 2032 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL cap 2032 2048 R0
SYMATTR InstName C2
SYMATTR Value 3.3
SYMBOL res 2032 1840 R0
SYMATTR InstName R1
SYMATTR Value 3.3K
FLAG 1504 1936 0
FLAG 1696 2096 0
FLAG 2048 2144 0
FLAG 2144 2144 0
FLAG 2144 2032 OUT
FLAG 1504 1824 IN
TEXT 2096 2208 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\11ac91057193_Regulator_UsingZener..asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 N002 1N750
R1 N001 N002 242
V1 N001 0 12
R2 N002 0 470
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
* Raw voltage regulator with zener diode.
* The zener diode regulates the voltage by working in the breakdown region.\nR1 limits the current from the source.\n \nSizing: the load voltage is the nominal zener voltage 4.7V.\nThen IR_2 = 4.7/R2\n \nFrom the datasheet the zener current is found. R1 must be equal to:\n \nR1 = (V1 - Vz)/(Iz + IR_2) = (12 - 4.7)/(20mA + 10mA)
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1392 680
WIRE 112 112 -16 112
WIRE -16 144 -16 112
WIRE 112 144 112 112
WIRE 112 256 112 224
WIRE 224 256 112 256
WIRE 112 272 112 256
WIRE 224 288 224 256
WIRE 112 400 112 336
WIRE 224 400 224 368
FLAG -16 224 0
FLAG 112 400 0
FLAG 224 400 0
SYMBOL zener 128 336 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N750
SYMBOL res 96 128 R0
SYMATTR InstName R1
SYMATTR Value 242
SYMBOL voltage -16 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 208 272 R0
SYMATTR InstName R2
SYMATTR Value 470
TEXT 160 -32 Left 4 ;Raw voltage regulator with zener diode.
TEXT 352 136 Left 2 ;The zener diode regulates the voltage by working in the breakdown region.\nR1 limits the current from the source.\n \nSizing: the load voltage is the nominal zener voltage 4.7V.\nThen IR_2 = 4.7/R2\n \nFrom the datasheet the zener current is found. R1 must be equal to:\n \nR1 = (V1 - Vz)/(Iz + IR_2) = (12 - 4.7)/(20mA + 10mA)
TEXT -48 424 Left 2 !.tran 1