Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2ndOrderBandpass.asc
* Generated by LTspice 26.0.1 for Windows.
* f0 and Q set by parameters
* R1 is arbitary
* This version puts 1/2 the R1 resistance in the capacitor
* Vout
* Vin
* The parameter "H" sets the midband gain
R2 N003 N002 {R1/2}
V1 1 0 AC 1
R3 2 0 .1
R4 2 0 1Meg
R1 N002 0 {R1/2}
G1 0 N002 1 0 {2/R1}
G2 0 2 N003 0 {10*H}
L1 N003 0 {L1} Cpar={C1}
.param f0= 1k Q=0.5
.param R1=1k
.param L1=1/(C1*(2*pi*f0)**2)
.param C1=Q/(R1*2*pi*f0)
.param H=1
.ac dec 101 100 10k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE -384 -128 -448 -128
WIRE -288 -128 -320 -128
WIRE -112 -128 -240 -128
WIRE -64 -128 -112 -128
WIRE 64 -128 16 -128
WIRE 240 -128 64 -128
WIRE 400 -128 288 -128
WIRE 464 -128 400 -128
WIRE 496 -128 464 -128
WIRE 624 -128 560 -128
WIRE -448 -112 -448 -128
WIRE -240 -96 -240 -128
WIRE -288 -80 -288 -128
WIRE -112 -64 -112 -128
WIRE 64 -64 64 -128
WIRE 288 -64 288 -128
WIRE 400 -64 400 -128
WIRE 624 -64 624 -128
WIRE 240 -48 240 -128
WIRE -448 0 -448 -32
WIRE -288 0 -288 -32
WIRE -240 16 -240 -16
WIRE 240 32 240 0
WIRE 288 32 288 16
WIRE 400 32 400 16
WIRE 624 32 624 16
WIRE -112 48 -112 16
WIRE 64 48 64 16
SYMBOL g 288 -80 R0
SYMATTR InstName G2
SYMATTR Value {10*H}
SYMBOL res 384 -80 R0
SYMATTR InstName R3
SYMATTR Value .1
SYMBOL ind 48 -80 R0
WINDOW 0 59 45 Bottom 2
WINDOW 3 61 50 Top 2
WINDOW 123 102 107 Bottom 2
SYMATTR InstName L1
SYMATTR Value {L1}
SYMATTR Value2 Cpar={C1}
SYMBOL res 608 -80 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL Misc\\jumper 528 -192 R0
SYMATTR InstName J2
SYMBOL Misc\\jumper -352 -192 M0
SYMATTR InstName J1
SYMBOL g -240 -112 R0
SYMATTR InstName G1
SYMATTR Value {2/R1}
SYMBOL voltage -448 -128 R0
WINDOW 0 35 41 Left 2
WINDOW 123 33 80 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value2 AC 1
SYMATTR Value ""
SYMBOL res -128 -80 R0
SYMATTR InstName R1
SYMATTR Value {R1/2}
SYMBOL res 32 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R1/2}
FLAG 64 48 0
FLAG -112 48 0
FLAG -240 16 0
FLAG -288 0 0
FLAG 240 32 0
FLAG 288 32 0
FLAG 400 32 0
FLAG 464 -128 2
FLAG -288 -128 1
FLAG -448 0 0
FLAG 624 32 0
TEXT -96 136 Left 2 !.param f0= 1k Q=0.5
TEXT -264 176 Left 2 !.param R1=1k
TEXT -440 296 Left 2 !.param L1=1/(C1*(2*pi*f0)**2)
TEXT -432 136 Left 2 ;f0 and Q set by parameters
TEXT -432 176 Left 2 ;R1 is arbitary
TEXT -328 -200 Left 2 ;This version puts 1/2 the R1 resistance in the capacitor
TEXT -440 256 Left 2 !.param C1=Q/(R1*2*pi*f0)
TEXT 576 -144 Left 2 ;Vout
TEXT -400 -144 Right 2 ;Vin
TEXT -432 216 Left 2 ;The parameter "H" sets the midband gain
TEXT 64 216 Left 2 !.param H=1
TEXT -440 336 Left 2 !.ac dec 101 100 10k
* Z:\tmp\asc_dec_bjh7r6w2\06da7ba760c8_eje2b_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
rg N002 N001 10
C1 N004 N005 4.775e-11
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -496 64 -544 64
WIRE -368 64 -416 64
WIRE -240 64 -288 64
WIRE -96 64 -160 64
WIRE 80 64 -96 64
WIRE -96 80 -96 64
WIRE 80 96 80 64
WIRE -544 112 -544 64
WIRE -96 176 -96 144
WIRE -544 272 -544 192
WIRE -96 272 -96 256
WIRE -96 272 -544 272
WIRE 80 272 80 176
WIRE 80 272 -96 272
SYMBOL res -400 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName rg
SYMATTR Value 10
SYMBOL cap -112 80 R0
SYMATTR InstName C1
SYMATTR Value 4.775e-11
FLAG 80 272 0
* Z:\home\khalils\Downloads\files\data\raw_asc\07ab3c1e79b8_Assignment_4b__i_.asc
* Generated by LTspice 26.0.1 for Windows.
* Full Wave Rectifier (Diode Bridge) (Ideal)
D1 0 N001 1N4148
R1 N001 N003 1000
D4 N003 N002 1N4148
V1 0 N002 SINE(0 311 50) Rser=0.001
D3 N002 N001 1N4148
D2 N003 0 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 448 64 144 64
WIRE 144 80 144 64
WIRE 144 80 -16 80
WIRE 304 80 144 80
WIRE 304 112 304 80
WIRE -16 128 -16 80
WIRE 448 192 448 64
WIRE -16 240 -16 192
WIRE 64 240 -16 240
WIRE 144 240 64 240
WIRE 304 240 304 176
WIRE 304 240 224 240
WIRE 64 272 64 240
WIRE 304 272 304 240
WIRE -16 288 -16 240
WIRE -16 384 -16 352
WIRE 144 384 -16 384
WIRE 304 384 304 336
WIRE 304 384 144 384
WIRE 144 400 144 384
WIRE 448 400 448 272
WIRE 448 400 144 400
SYMBOL diode 0 352 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL voltage 128 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 2
WINDOW 39 -60 56 VBottom 2
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
SYMATTR SpiceLine Rser=0.001
SYMBOL diode 0 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 432 176 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL diode 320 336 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMATTR Value 1N4148
SYMBOL diode 320 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value 1N4148
FLAG 64 272 0
TEXT -16 424 Left 2 !.tran 0.05
TEXT -24 24 Left 2 ;Full Wave Rectifier (Diode Bridge) (Ideal)
* Z:\home\khalils\Downloads\files\data\raw_asc\3cadd4efed06_SiC_recovery1.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N002 0 MUR460
R1 N001 N002 100
V1 N001 0 PULSE(200 -200 0 {Tr} {Tr} 1)
D2 N004 0 CSD06060
R2 N003 N004 100
V2 N003 0 PULSE(200 -200 0 {Tr} {Tr} 1)
D3 N006 0 UPSC600
R3 N005 N006 100
V3 N005 0 PULSE(200 -200 0 {Tr} {Tr} 1)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
* CSD06060 D model
* created using Parts release 8.0 on 01/21/104 at 21:22
* Parts is a MicroSim product.
.MODEL CSD06060 D
+ IS=479.17E-6
+ RS=70.317E-3
+ N=4.9950
+ CJO=537.33E-12
+ M=.40753
+ BV=800.13
+ IKF=1.0000E3
+ VJ=.3905
+ ISR=10.010E-21
+ NR=4.9950
+ IBV=.12937
+ TT=15.628E-12
.tran 0 100n 0 1n
.options plotwinsize=0
* Compare the revoery time of Si and SiC diodes\n \nPlot I(D1), I(D2) and I(D3).
.param Tr=80n
* 50A/us
* Si
* SiC
* SiC
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1800 1012
WIRE -160 240 -160 192
WIRE -160 368 -160 320
WIRE -160 544 -160 496
WIRE -160 672 -160 624
WIRE -16 496 -160 496
WIRE 32 192 -160 192
WIRE 224 192 112 192
WIRE 224 256 224 192
WIRE 224 368 224 320
WIRE 224 496 64 496
WIRE 224 560 224 496
WIRE 224 672 224 624
WIRE 528 240 528 192
WIRE 528 368 528 320
WIRE 672 192 528 192
WIRE 912 192 752 192
WIRE 912 256 912 192
WIRE 912 368 912 320
FLAG -160 368 0
FLAG 224 368 0
FLAG 528 368 0
FLAG 912 368 0
FLAG -160 672 0
FLAG 224 672 0
SYMBOL diode 208 256 R0
SYMATTR InstName D1
SYMATTR Value MUR460
SYMBOL res 16 208 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage -160 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(200 -200 0 {Tr} {Tr} 1)
SYMBOL diode 896 256 R0
SYMATTR InstName D2
SYMATTR Value CSD06060
SYMBOL res 656 208 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL voltage 528 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(200 -200 0 {Tr} {Tr} 1)
SYMBOL diode 208 560 R0
SYMATTR InstName D3
SYMATTR Value UPSC600
SYMBOL res -32 512 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 100
SYMBOL voltage -160 528 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(200 -200 0 {Tr} {Tr} 1)
TEXT 528 -336 Left 0 !* CSD06060 D model\n* created using Parts release 8.0 on 01/21/104 at 21:22\n* Parts is a MicroSim product.\n.MODEL CSD06060 D\n+ IS=479.17E-6\n+ RS=70.317E-3\n+ N=4.9950\n+ CJO=537.33E-12\n+ M=.40753\n+ BV=800.13\n+ IKF=1.0000E3\n+ VJ=.3905\n+ ISR=10.010E-21\n+ NR=4.9950\n+ IBV=.12937\n+ TT=15.628E-12
TEXT -184 -88 Left 0 !.tran 0 100n 0 1n
TEXT -184 -48 Left 0 !.options plotwinsize=0
TEXT -192 -288 Left 0 ;Compare the revoery time of Si and SiC diodes\n \nPlot I(D1),  I(D2) and I(D3).
TEXT -176 16 Left 0 !.param Tr=80n
TEXT -8 16 Left 0 ;50A/us
TEXT 280 288 Left 0 ;Si
TEXT 960 280 Left 0 ;SiC
TEXT 288 584 Left 0 ;SiC
* Z:\home\khalils\Downloads\files\data\raw_asc\62bdc00b1dee_ideal_mult.asc
* Generated by LTspice 26.0.1 for Windows.
* input signals
* internally generated signals
* output signals
* Simulation of analog multiplier
* V1 and V2 represent input signals A and B
* B1 is the inverter for the signal A
* V2 is the internal triangle wave generator
* B2 represents the analog switch which is controlled by a comparator
* B3 generates a reference signal which is the real multiplication of A and B
* ----------------------------------------------
V1 A 0 SINE(0 1 41k)
C1 out 0 1n
B1 Aneg 0 V=-V(A)
V2 B 0 SINE(0 1 40k)
B2 N001 0 V=if(V(B)>V(ref),V(A),V(Aneg))
B3 out_mult 0 V=V(A)*V(B)
R1 N001 out 1k
V3 ref 0 PULSE(-1 1 0 0.5u 0.5u 0 1u)
.tran 0 10m 0 10n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1716 680
WIRE 592 32 416 32
WIRE 928 32 720 32
WIRE 1408 32 1120 32
WIRE 1520 32 1488 32
WIRE 1584 32 1520 32
WIRE 416 48 416 32
WIRE 720 48 720 32
WIRE 1120 48 1120 32
WIRE 1520 48 1520 32
WIRE 1520 128 1520 112
WIRE 592 176 416 176
WIRE 928 176 720 176
WIRE 1584 176 1120 176
WIRE 416 192 416 176
WIRE 720 192 720 176
WIRE 1120 192 1120 176
SYMBOL voltage 416 32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 41k)
SYMBOL bv 720 32 R0
SYMATTR InstName B1
SYMATTR Value V=-V(A)
SYMBOL voltage 416 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 1 40k)
SYMBOL res 1392 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 720 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 0.5u 0.5u 0 1u)
SYMBOL cap 1504 48 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL bv 1120 176 R0
SYMATTR InstName B3
SYMATTR Value V=V(A)*V(B)
SYMBOL bv 1120 32 R0
SYMATTR InstName B2
SYMATTR Value V=if(V(B)>V(ref),V(A),V(Aneg))
FLAG 416 128 0
FLAG 416 272 0
FLAG 592 32 A
FLAG 592 176 B
FLAG 720 128 0
FLAG 720 272 0
FLAG 928 176 ref
FLAG 928 32 Aneg
FLAG 1120 128 0
FLAG 1120 272 0
FLAG 1584 32 out
FLAG 1584 176 out_mult
FLAG 1520 128 0
TEXT 424 -48 Left 2 ;input signals
TEXT 704 -48 Left 2 ;internally generated signals
TEXT 1256 -48 Left 2 ;output signals
TEXT 382 360 Left 2 !.tran 0 10m 0 10n
TEXT 384 -160 Left 3 ;Simulation of analog multiplier
TEXT 384 464 Left 2 ;V1 and V2 represent input signals A and B
TEXT 384 496 Left 2 ;B1 is the inverter for the signal A
TEXT 384 528 Left 2 ;V2 is the internal triangle wave generator
TEXT 384 560 Left 2 ;B2 represents the analog switch which is controlled by a comparator
TEXT 384 592 Left 2 ;B3 generates a reference signal which is the real multiplication of A and B
TEXT 384 -136 Left 3 ;----------------------------------------------
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3310.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 OUT 220n Rser=2m
R1 OUT N004 562K
V1 IN 0 5
R2 N004 0 100K
C5 OUT N004 15p
Rload OUT 0 .5
C2 N003 0 4.7n
C3 N005 0 220p
R4 N006 N005 10K
C1 OUT 0 47
R3 OUT N001 500K
R5 N007 0 274K
XU1 IN IN N002 N004 0 0 N007 N001 IN N006 N003 LTC3310 ;pnba Vin)EN)SW)FB)Agnd)Pgnd)Rt)Pgood)Mode/Sync)Ith)SSTT
.tran .4m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3310.asy)
.lib LTC3310.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2648 1864
WIRE 1536 1248 1376 1248
WIRE 1712 1248 1536 1248
WIRE 1376 1264 1376 1248
WIRE 1712 1280 1712 1248
WIRE 1536 1328 1536 1248
WIRE 1552 1328 1536 1328
WIRE 1904 1328 1872 1328
WIRE 2016 1328 1984 1328
WIRE 1376 1360 1376 1344
WIRE 1536 1424 1536 1328
WIRE 1552 1424 1536 1424
WIRE 1904 1424 1872 1424
WIRE 2016 1424 2016 1328
WIRE 2016 1424 1984 1424
WIRE 2144 1424 2016 1424
WIRE 2224 1424 2144 1424
WIRE 2304 1424 2224 1424
WIRE 2144 1440 2144 1424
WIRE 2224 1440 2224 1424
WIRE 2304 1440 2304 1424
WIRE 1472 1520 1456 1520
WIRE 1552 1520 1536 1520
WIRE 2016 1520 2016 1504
WIRE 2016 1520 1872 1520
WIRE 2144 1520 2144 1504
WIRE 2144 1520 2016 1520
WIRE 2016 1536 2016 1520
WIRE 2224 1536 2224 1504
WIRE 2304 1536 2304 1520
WIRE 1424 1616 1360 1616
WIRE 1552 1616 1504 1616
WIRE 1904 1616 1872 1616
WIRE 1360 1632 1360 1616
WIRE 1904 1632 1904 1616
WIRE 2016 1632 2016 1616
WIRE 1648 1680 1648 1664
WIRE 1776 1680 1776 1664
WIRE 1360 1712 1360 1696
WIRE 1904 1728 1904 1712
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1376 1360 0
FLAG 2304 1536 0
FLAG 2016 1632 0
FLAG 1456 1520 0
FLAG 2304 1424 OUT
FLAG 1376 1248 IN
FLAG 1360 1712 0
FLAG 2224 1536 0
FLAG 1904 1728 0
SYMBOL ind 1888 1440 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 220n
SYMATTR SpiceLine Rser=2m
SYMBOL RES 2000 1408 R0
SYMATTR InstName R1
SYMATTR Value 562K
SYMBOL VOLTAGE 1376 1248 R0
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 2000 1520 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap 2128 1440 R0
SYMATTR InstName C5
SYMATTR Value 15p
SYMBOL res 2288 1424 R0
SYMATTR InstName Rload
SYMATTR Value .5
SYMBOL cap 1536 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL cap 1344 1632 R0
SYMATTR InstName C3
SYMATTR Value 220p
SYMBOL res 1520 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL cap 2208 1440 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMBOL res 2000 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500K
SYMBOL res 1888 1616 R0
SYMATTR InstName R5
SYMATTR Value 274K
SYMBOL LTC3310 1712 1472 R0
SYMATTR InstName U1
TEXT 2152 1640 Left 2 !.tran .4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1790-1.25.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1790-1.25.asy)
XU1 IN 0 OUT LT1790-125 ;pnba IN)GND)OUT
C1 OUT 0 1
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 1K
.tran 1
.lib LT1790.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 320 48 256 48
WIRE 416 48 320 48
WIRE -208 64 -208 48
WIRE 320 64 320 48
WIRE 416 64 416 48
WIRE -208 160 -208 144
WIRE 320 160 320 128
WIRE 416 160 416 144
WIRE 128 176 128 160
SYMBOL PowerProducts\\LT1790-1.25 128 48 R0
SYMATTR InstName U1
SYMBOL res 400 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 304 64 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG -208 160 0
FLAG 320 160 0
FLAG 416 160 0
FLAG 128 176 0
FLAG 416 48 OUT
FLAG -208 48 IN
TEXT 288 208 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1412.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1412.asy)
V3 v+ 0 15
V4 v- 0 -15
V1 vS 0 SINE(0 5 20)
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
XU1 vIN vS vD v- v+ 0 ADG1412 ;pnba IN)S)D)Vss)Vdd)GND
R1 vD 0 301
C1 vD 0 36p
.tran 1
.lib ADG1412.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 112 240 112
WIRE 240 144 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 368 224 336 224
WIRE 416 224 368 224
WIRE 528 224 416 224
WIRE 416 256 416 224
WIRE 528 256 528 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -272 304 -288 304
WIRE -176 304 -192 304
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 416 352 416 336
WIRE 528 352 528 320
WIRE 304 416 304 400
WIRE 176 432 176 400
WIRE 192 432 176 432
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL res 400 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG1412 240 272 R0
SYMATTR InstName U1
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 20)
SYMBOL cap 512 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
FLAG -112 224 0
FLAG 48 464 0
FLAG 416 352 0
FLAG 304 416 0
FLAG 368 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 528 352 0
FLAG -272 304 v+
FLAG 256 112 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -176 304 v-
FLAG 192 432 v-
TEXT 80 528 Left 2 !.tran 1
TEXT -360 -40 Left 2 ;Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3588-2.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N003 0 2
L1 N004 OUT 22
C2 OUT 0 47
I1 N002 N001 SINE(0 200u 100 0 0 0 100)
Rload OUT 0 25K
C3 N003 N005 1
C4 N006 0 1
XU1 N001 N002 N005 N003 N004 OUT N006 0 0 N007 0 LTC3588-2 ;pnba PZ1)PZ2)CAP)Vin)SW)Vout)Vin2)D1)D0)Pgood)GND
.tran 2
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3588-2.asy)
.lib LTC3588-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1028 680
WIRE 208 -112 80 -112
WIRE 432 -112 288 -112
WIRE 80 0 80 -112
WIRE 112 0 80 0
WIRE 432 0 432 -112
WIRE 432 0 400 0
WIRE -16 96 -32 96
WIRE 64 96 48 96
WIRE 112 96 64 96
WIRE 416 96 400 96
WIRE 512 96 496 96
WIRE 560 96 512 96
WIRE 640 96 560 96
WIRE 64 112 64 96
WIRE 560 112 560 96
WIRE 640 112 640 96
WIRE 64 192 64 176
WIRE 112 192 64 192
WIRE 512 192 512 96
WIRE 512 192 400 192
WIRE 560 208 560 176
WIRE 640 208 640 192
WIRE 32 288 16 288
WIRE 112 288 96 288
WIRE 416 288 400 288
WIRE 112 384 96 384
WIRE 416 384 400 384
WIRE 256 448 256 432
FLAG -32 96 0
FLAG 560 208 0
FLAG 416 384 0
FLAG 96 384 0
FLAG 256 448 0
FLAG 640 208 0
FLAG 640 96 OUT
FLAG 16 288 0
SYMBOL cap 48 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2
SYMBOL ind 400 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 22
SYMBOL cap 544 112 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMBOL current 288 -112 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(0 200u 100 0 0 0 100)
SYMBOL res 624 96 R0
SYMATTR InstName Rload
SYMATTR Value 25K
SYMBOL cap 48 112 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 96 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL PowerProducts\\LTC3588-2 256 192 R0
SYMATTR InstName U1
TEXT 536 320 Left 2 !.tran 2
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6910-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6910-1.asy)
V6 N001 0 PULSE(0 5 0 1u 1u 20m 40m)
V4 N003 0 PULSE(0 5 0 1u 1u 5m 10m)
V2 +V 0 +5
C1 0 N005 1
V5 N002 0 PULSE(0 5 0 1u 1u 10m 20m)
XU1 OUT N005 N004 0 N003 N002 N001 +V LTC6910-1 ;pnba OUT)AGND)IN)V-)G0)G1)G2)V+
V3 N004 0 SINE(2.5 10m 1K)
.tran 40m
.lib LTC6910-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1156 680
WIRE 48 -192 48 -208
WIRE -144 -128 -976 -128
WIRE -192 -112 -864 -112
WIRE -240 -96 -752 -96
WIRE 48 -96 48 -112
WIRE -752 -80 -752 -96
WIRE -240 -80 -240 -96
WIRE -192 -80 -192 -112
WIRE -144 -80 -144 -128
WIRE -96 -80 -96 -96
WIRE -864 -16 -864 -112
WIRE -752 16 -752 0
WIRE -272 16 -464 16
WIRE 16 16 -16 16
WIRE -976 48 -976 -128
WIRE -464 64 -464 16
WIRE -864 80 -864 64
WIRE -208 128 -208 112
WIRE -96 128 -96 112
WIRE -976 144 -976 128
WIRE -464 160 -464 144
SYMBOL voltage -464 48 R0
WINDOW 0 28 27 Left 2
WINDOW 3 25 94 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(2.5 10m 1K)
SYMBOL cap -224 192 M180
WINDOW 0 36 51 Left 2
WINDOW 3 34 17 Left 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL LTC6910-1 -160 16 R0
SYMATTR InstName U1
SYMBOL voltage -976 32 R0
WINDOW 0 28 27 Left 2
WINDOW 3 25 94 Left 2
SYMATTR InstName V6
SYMATTR Value PULSE(0 5 0 1u 1u 20m 40m)
SYMBOL voltage 48 -208 R0
WINDOW 3 27 93 Left 2
SYMATTR Value +5
SYMATTR InstName V2
SYMBOL voltage -752 -96 R0
WINDOW 0 28 27 Left 2
WINDOW 3 28 87 Left 2
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1u 1u 5m 10m)
SYMBOL voltage -864 -32 R0
WINDOW 0 28 27 Left 2
WINDOW 3 19 96 Left 2
SYMATTR InstName V5
SYMATTR Value PULSE(0 5 0 1u 1u 10m 20m)
FLAG 48 -96 0
FLAG -464 160 0
FLAG 48 -208 +V
FLAG -96 -96 +V
FLAG -208 192 0
FLAG -96 128 0
FLAG -752 16 0
FLAG -864 80 0
FLAG -976 144 0
FLAG 16 16 OUT
TEXT -72 176 Left 2 !.tran 40m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP151-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP151-3.3.asy)
XU1 IN 0 IN MP_01 OUT ADP151-x.x T=2.3Meg ;pnba Vin)GND)EN))Vout
C1 OUT 0 1
Rload OUT 0 33
V1 IN 0 5
.tran 500u startup
.lib ADP151-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 880 1696 880
WIRE 1984 880 1824 880
WIRE 1696 896 1696 880
WIRE 1984 896 1984 880
WIRE 1696 992 1696 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 33
SYMBOL VOLTAGE 1696 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\ADP151-3.3 1984 1024 R0
SYMATTR InstName U1
FLAG 2256 1024 OUT
FLAG 2256 1136 0
FLAG 1696 992 0
FLAG 1696 880 IN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\137c63cc823d_LTC6101_AC.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N002 0 12
R1 N002 N001 .1
Iload N001 0 PULSE(0.5 1 10n 100n 100n 50u 100u) AC 1
XU1 OUT 0 N003 N001 N002 LTC6101 ;pnba OUT)VEE)IN-)IN+)VCC
R2 N002 N003 100
R3 OUT 0 5K
* .dc Iload 0 1 0.01
.op
.ac dec 100 10 1e6
* AC-response
* DC-Sweep
* Step Response
* .tran 0 .5m 0 .1u
.options plotwinsize=0
* Idc=0.5A for .AC-analysis
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6101.asy)
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 96 -496 96
WIRE 64 96 -64 96
WIRE 256 96 144 96
WIRE 336 96 256 96
WIRE 400 96 336 96
WIRE 256 112 256 96
WIRE 400 112 400 96
WIRE -496 128 -496 96
WIRE -64 208 -64 96
WIRE -32 208 -64 208
WIRE 256 208 256 192
WIRE 256 208 224 208
WIRE 400 224 400 192
WIRE -496 240 -496 208
WIRE -32 320 -64 320
WIRE 336 320 336 96
WIRE 336 320 224 320
WIRE -64 352 -64 320
WIRE 272 480 224 480
WIRE 272 496 272 480
WIRE 272 592 272 576
FLAG 400 224 0
FLAG -496 240 0
FLAG -64 352 0
FLAG 272 592 0
FLAG 272 480 OUT
SYMBOL voltage 400 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 160 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value .1
SYMBOL current -496 128 R0
WINDOW 123 24 116 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName Iload
SYMATTR Value PULSE(0.5 1 10n 100n 100n 50u 100u)
SYMBOL LTC6101 96 336 R0
SYMATTR InstName U1
SYMBOL res 240 96 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL res 256 480 R0
SYMATTR InstName R3
SYMATTR Value 5K
TEXT -488 -32 Left 0 ;.dc Iload 0 1 0.01
TEXT -488 16 Left 0 !.op
TEXT -208 -32 Left 0 !.ac dec 100 10 1e6
TEXT -208 -64 Left 0 ;AC-response
TEXT -488 -64 Left 0 ;DC-Sweep
TEXT 72 -64 Left 0 ;Step Response
TEXT 64 -32 Left 0 ;.tran 0 .5m 0 .1u
TEXT 64 0 Left 0 !.options plotwinsize=0
TEXT -448 176 Left 0 ;Idc=0.5A for .AC-analysis