Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3240-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3240-3.3.asy)
C2 OUT 0 4.7
XU1 0 IN OUT N001 N002 IN LTC3240-3.3 ;pnba GND)Vin)Vout)C+)C-)_SHDN
C1 N001 N002 1
V1 IN 0 3
Rload OUT 0 30
.tran 2m startup
.lib LTC3240-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 176 -112 176
WIRE 32 176 0 176
WIRE 336 176 288 176
WIRE -112 192 -112 176
WIRE 0 256 0 176
WIRE 32 256 0 256
WIRE 336 256 336 240
WIRE 336 256 288 256
WIRE -112 288 -112 272
WIRE 32 336 0 336
WIRE 336 336 288 336
WIRE 432 336 336 336
WIRE 336 352 336 336
WIRE 432 352 432 336
WIRE 336 448 336 416
WIRE 432 448 432 432
SYMBOL cap 320 352 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL LTC3240-3.3 160 256 R0
SYMATTR InstName U1
SYMBOL cap 320 176 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -112 176 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 416 336 R0
SYMATTR InstName Rload
SYMATTR Value 30
FLAG 432 448 0
FLAG 336 448 0
FLAG 0 336 0
FLAG -112 288 0
FLAG -112 176 IN
FLAG 432 336 OUT
TEXT 80 416 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\31b1976d752c_AD8666.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 8
Vin IN 0 SINE(0 1 1K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -8
Rload OUT 0 10K
XU1 IN N001 +V -V OUT AD8666 ;pnba In+)In-)V+)V-)OUT
.tran 10m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8666.asy)
.lib AD8666.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 8
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -8
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL AD8666 576 -1168 R0
SYMATTR InstName U1
TEXT 688 -952 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\276d15f19544_qztst.asc
* Generated by LTspice 26.0.1 for Windows.
* Crystal model from easily measurable parameters
*serial freq
*difference between serial and // freq
* This example schematic is supplied for informational/educational purposes only.\nContributed by Dominique Szymik.
CY1 N002 OUT {Cs} Rser={Rs} Lser={Ls} Cpar={Cp}
R1 N002 N001 50
R2 0 OUT 50
V1 N001 0 AC 2
.ac lin 1001 3.95e6 4.05e6
.params fs=4e6
.params df=10e3
.params Rs=50
.params Cp=4e-12
.params Cs=2.0*cp*df/fs
.params Ls=1/(4*pi*pi*fs*fs*Cs)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3040 2464
WIRE 1712 2192 1632 2192
WIRE 1824 2192 1792 2192
WIRE 2000 2192 1888 2192
WIRE 2048 2192 2000 2192
WIRE 1632 2208 1632 2192
WIRE 2000 2208 2000 2192
WIRE 1632 2304 1632 2288
WIRE 2000 2320 2000 2288
SYMBOL VOLTAGE 1632 2192 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 2
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL res 1808 2176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL res 2016 2304 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL MISC\\XTAL 1824 2208 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName Y1
SYMATTR Value {Cs}
SYMATTR SpiceLine Rser={Rs} Lser={Ls} Cpar={Cp}
FLAG 2000 2320 0
FLAG 1632 2304 0
FLAG 2048 2192 OUT
TEXT 1672 2104 Left 2 !.ac lin 1001 3.95e6 4.05e6
TEXT 1184 2048 Left 2 ;Crystal model from easily measurable parameters
TEXT 1136 2112 Left 2 !*serial freq\n.params fs=4e6  \n*difference between serial and // freq \n.params df=10e3  \n.params Rs=50\n.params Cp=4e-12\n.params Cs=2.0*cp*df/fs\n.params Ls=1/(4*pi*pi*fs*fs*Cs)
TEXT 1592 2392 Top 1 ;This example schematic is supplied for informational/educational purposes only.\nContributed by Dominique Szymik.
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX4488.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX4488.asy)
Vcc Vcc 0 2.5
V1 IN 0 SINE(0 50m 10k)
RL OUT 0 10k
CL OUT 0 15p
Vee 0 Vee 2.5
XU1 IN OUT Vcc Vee OUT Vcc MAX4488 ;pnba In+)In-)V+)V-)OUT)SHDN
.tran 100u
.lib MAX4488.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 64 288 64 272
WIRE 416 352 416 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 64 448 64 400
WIRE 416 448 416 416
WIRE 448 448 448 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 64 544 64 528
WIRE 304 592 304 576
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 10k)
SYMBOL MAX4488 432 400 R0
SYMATTR InstName U1
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
FLAG 720 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 416 320 Vcc
FLAG 416 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
FLAG 448 448 Vcc
TEXT 16 632 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\012944af6fe9_scheme-switch.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N002 N001 PULSE(20 0 10m 10m 10m 60m 120m 0)
R3 N006 N003 2200
V1 N005 0 125
R4 0 N006 2200
R5 N003 N004 2200
L1 N004 0 1.2
R2 N003 N005 2200
S1 N004 N003 N002 N001 MYSW
.tran 0 120m 0 0.1m
.model MYSW SW(Ron=1 Roff=1Meg)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1008 680
WIRE 656 -400 640 -400
WIRE 560 -288 560 -400
WIRE 576 -288 560 -288
WIRE 656 -288 656 -400
WIRE 656 -288 624 -288
WIRE 560 -240 528 -240
WIRE 672 -240 640 -240
WIRE 304 -128 224 -128
WIRE 480 -128 384 -128
WIRE 528 -128 528 -240
WIRE 528 -128 480 -128
WIRE 560 -128 528 -128
WIRE 672 -128 672 -240
WIRE 672 -128 640 -128
WIRE 688 -128 672 -128
WIRE 480 -80 480 -128
WIRE 688 -48 688 -128
WIRE 224 -16 224 -128
WIRE 480 48 480 0
WIRE 224 176 224 64
WIRE 480 176 480 128
WIRE 480 176 224 176
WIRE 688 176 688 32
WIRE 688 176 480 176
WIRE 480 224 480 176
SYMBOL voltage 224 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 484 231 Right 2
SYMATTR Value 125
SYMATTR InstName V1
SYMBOL res 496 16 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 2200
SYMBOL ind 672 -64 R0
SYMATTR InstName L1
SYMATTR Value 1.2
SYMBOL sw 656 -240 R90
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL voltage 544 -400 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(20 0 10m 10m 10m 60m 120m 0)
SYMBOL res 496 144 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 2200
SYMBOL res 544 -112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 2200
SYMBOL res 400 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 2200
FLAG 480 224 0
TEXT 232 160 Left 2 !.tran 0 120m 0 0.1m
TEXT 112 -288 Left 2 !.model MYSW SW(Ron=1 Roff=1Meg)
* Z:\home\khalils\Downloads\files\data\raw_asc\2680dc02d05b_Draft4.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 NMOS l=0.5u w=1u
V2 N002 0 PULSE(0 3.3v 0 1p 1p 1u 2u)
V1 vdd 0 3.3
C1 N001 0 50p
M2 vdd N002 N001 vdd PMOS l=0.5u w=5u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.inc library.mod
.tran 20u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 272 192 256
WIRE 304 272 192 272
WIRE 144 304 144 240
WIRE 144 304 48 304
WIRE 192 304 192 272
WIRE 144 384 144 304
WIRE 48 416 48 304
SYMBOL nmos4 144 304 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.5u w=1u
SYMBOL pmos4 144 160 R0
WINDOW 3 60 73 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=0.5u w=5u
SYMBOL cap 288 272 R0
SYMATTR InstName C1
SYMATTR Value 50p
SYMBOL voltage 480 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage 48 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3v 0 1p 1p 1u 2u)
FLAG 192 352 0
FLAG 192 400 0
FLAG 48 496 0
FLAG 480 272 0
FLAG 480 192 vdd
FLAG 192 160 vdd
FLAG 192 208 vdd
FLAG 304 336 0
TEXT 16 48 Left 2 !.inc library.mod
TEXT 320 104 Left 2 !.tran 20u
* Z:\home\khalils\Downloads\files\data\raw_asc\6e583d2288c1_Assignment_3b__vi_.asc
* Generated by LTspice 26.0.1 for Windows.
* Negative Half Wave Rectifier Circuit (with 10microF Capacitor) (Practical)
V1 N001 0 SINE(0 5 1000) Rser=0.001
R1 N002 0 1000
D1 N002 N001 1N4148
C1 N002 0 0.00001
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5ms
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 320 80 208 80
WIRE 480 80 384 80
WIRE 592 80 480 80
WIRE 208 128 208 80
WIRE 480 128 480 80
WIRE 592 144 592 80
WIRE 208 256 208 208
WIRE 304 256 208 256
WIRE 480 256 480 208
WIRE 480 256 304 256
WIRE 592 256 592 208
WIRE 592 256 480 256
WIRE 304 288 304 256
SYMBOL res 464 112 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL voltage 208 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1000)
SYMBOL diode 384 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL cap 576 144 R0
SYMATTR InstName C1
SYMATTR Value 0.00001
FLAG 304 288 0
TEXT 144 288 Left 2 !.tran 5ms
TEXT -24 8 Left 2 ;Negative Half Wave Rectifier Circuit (with 10microF Capacitor) (Practical)
* Z:\tmp\asc_dec_bjh7r6w2\05ad62ca7a0e_Differential_Amplifier_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 N001 N002 545
R2 N001 N003 545
V3 N004 0 SINE(0 50m 1k) AC -0.5 Rser=1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 -352 -384 -352
WIRE 448 -352 16 -352
WIRE 16 -288 16 -352
WIRE 448 -272 448 -352
WIRE 448 -48 448 -192
WIRE 16 -32 16 -208
WIRE -32 48 -128 48
WIRE 16 112 16 64
WIRE 288 112 16 112
WIRE -128 128 -128 48
WIRE -288 208 -384 208
WIRE -288 320 -288 208
SYMBOL res 432 -288 R0
SYMATTR InstName R3
SYMATTR Value 545
SYMBOL res 0 -304 R0
SYMATTR InstName R2
SYMATTR Value 545
SYMBOL voltage -128 112 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR Value2 AC -0.5
SYMATTR SpiceLine Rser=1k
SYMATTR InstName V3
SYMATTR Value SINE(0 50m 1k)
FLAG -128 208 0
* Z:\home\khalils\Downloads\files\data\raw_asc\37b23b6367e5_lpf_0_2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6220.asy)
V1 N002 0 AC 1
V2 +3V3 0 3V3
R2 N003 0 100k
XU1 N003 N001 +3V3 0 N001 LT6220 ;pnba IN+)IN-)VCC)VEE)OUT
R1 N003 N002 16k
C1 N003 0 10n
.ac dec 50 10 100000
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 512 -48 384 -48
WIRE 432 32 432 16
WIRE 384 48 384 -48
WIRE 400 48 384 48
WIRE 512 64 512 -48
WIRE 512 64 464 64
WIRE 64 80 0 80
WIRE 192 80 144 80
WIRE 288 80 192 80
WIRE 400 80 288 80
WIRE 288 96 288 80
WIRE -112 112 -112 96
WIRE 0 112 0 80
WIRE 192 112 192 80
WIRE 432 112 432 96
WIRE -112 208 -112 192
WIRE 0 208 0 192
WIRE 192 208 192 176
WIRE 288 208 288 176
SYMBOL Opamps\\LT6220 432 64 R0
SYMATTR InstName U1
SYMBOL res 160 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 16k
SYMBOL cap 176 112 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 272 80 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage -112 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 3V3
SYMBOL voltage 0 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value ""
FLAG 192 208 0
FLAG 0 208 0
FLAG 288 208 0
FLAG 432 16 +3V3
FLAG 432 112 0
FLAG -112 208 0
FLAG -112 96 +3V3
TEXT 0 272 Left 2 !.ac dec 50 10 100000
* Z:\home\khalils\Downloads\files\data\raw_asc\0250f72b62db_Fig6_13.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1)
VGS N003 0 0
VSB 0 N002 0
VDS N001 0 5
M1 N001 N003 0 N002 N_1u L=1u W=10u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VGS 0 2 1m VSB 0 5 1
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 352 208 352 192
WIRE 352 304 352 288
WIRE 400 192 352 192
WIRE 448 112 448 80
WIRE 448 272 448 208
WIRE 704 160 448 160
WIRE 704 272 704 240
WIRE 848 80 448 80
WIRE 848 112 848 80
WIRE 848 224 848 192
SYMBOL voltage 352 192 R0
WINDOW 0 -91 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VGS
SYMATTR Value 0
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 L=1u W=10u
SYMBOL voltage 704 256 R180
WINDOW 0 -37 57 Right 0
WINDOW 3 -49 27 Invisible 0
SYMATTR InstName VSB
SYMATTR Value 0
SYMBOL voltage 848 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 57 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VDS
SYMATTR Value 5
FLAG 352 304 0
FLAG 448 272 0
FLAG 848 224 0
FLAG 704 272 0
TEXT 448 320 Left 0 !.dc VGS 0 2 1m VSB 0 5 1
TEXT 448 344 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot Id(M1)
* Z:\tmp\asc_dec_bjh7r6w2\032e61ee16cb_Fig21_19_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
Vi Vin 0 PULSE(1.2 0.8 100n 10n)
M2 VDD Vbias1 Vout VDD P_1u l=2u w=30u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1784 680
WIRE 1072 -304 1072 -336
WIRE 1072 -288 1072 -304
WIRE 1136 32 1136 0
WIRE 1136 160 1136 112
WIRE 1152 0 1136 0
WIRE 1184 -144 1136 -144
WIRE 1264 -144 1184 -144
WIRE 1264 -144 1264 -192
WIRE 1264 0 1152 0
WIRE 1312 -112 1312 -176
WIRE 1312 -80 1312 -112
WIRE 1312 48 1312 16
WIRE 1408 -112 1312 -112
WIRE 1472 -112 1408 -112
SYMBOL voltage 1136 16 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -274 105 Left 0
SYMATTR Value PULSE(1.2 0.8 100n 10n)
SYMATTR InstName Vi
SYMBOL pmos4 1264 -272 R0
WINDOW 123 58 102 Left 0
WINDOW 0 56 16 Left 0
SYMATTR Value2 l=2u w=30u
SYMATTR InstName M2
SYMATTR Value P_1u
FLAG 1072 -208 0
FLAG 1072 -304 VDD
FLAG 1312 -32 0
FLAG 1312 48 0
FLAG 1312 -272 VDD
FLAG 1312 -224 VDD
FLAG 944 -176 Vbias1
FLAG 944 -144 Vhigh
FLAG 944 -112 Vbias2
FLAG 944 -16 Vbias3
FLAG 944 -80 Vpcas
FLAG 944 -48 Vncas
FLAG 944 48 Vbias4
FLAG 944 16 Vlow
FLAG 1408 -112 Vout
FLAG 1136 160 0
FLAG 1152 0 Vin
FLAG 1184 -144 Vbias1
* Z:\home\khalils\Downloads\files\data\raw_asc\04745702c7e1_Filter_Archetype_1.asc
* Generated by LTspice 26.0.1 for Windows.
CLFilt_C1 N003 N002 400n
RSrc N001 N011 1m
CPar N007 0 1.5
LDrive N010 N012 596
CNotch N013 0 1p
CFilt N003 0 400n
LTee2 N008 N007 1p
LCFilt_L N003 0 100 Rser=100m
CSer N009 N008 10
LFilt1 N002 N001 100 Rser=100m
CLFilt_C2 N005 N004 400n
LTee1 N007 N006 1p
LFilt2 N004 N003 100 Rser=100m
RDrive N012 0 .75
LNotch_Tune N006 N005 1p
LNotch N006 N013 10
CDrive N010 N009 66.7n
V1 N011 0 AC 1
.ac oct 1k 1k 500k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1604 680
WIRE -32 64 -128 64
WIRE 112 64 48 64
WIRE 224 64 176 64
WIRE 288 64 224 64
WIRE 432 64 368 64
WIRE 576 64 496 64
WIRE 768 64 656 64
WIRE 928 64 768 64
WIRE 1056 64 1008 64
WIRE 1104 64 1056 64
WIRE 1232 64 1184 64
WIRE 1344 64 1296 64
WIRE 1504 64 1408 64
WIRE 1504 96 1504 64
WIRE -128 128 -128 64
WIRE 224 160 224 64
WIRE 224 160 144 160
WIRE 272 160 224 160
WIRE 768 160 768 64
WIRE 144 192 144 160
WIRE 272 192 272 160
WIRE 1056 208 1056 64
WIRE -128 240 -128 208
WIRE 1504 240 1504 176
WIRE 768 272 768 240
WIRE -128 384 -128 320
WIRE 144 384 144 272
WIRE 144 384 -128 384
WIRE 272 384 272 256
WIRE 272 384 144 384
WIRE 768 384 768 336
WIRE 768 384 272 384
WIRE 1056 384 1056 272
WIRE 1056 384 768 384
WIRE 1504 384 1504 320
WIRE 1504 384 1056 384
WIRE -128 432 -128 384
SYMBOL ind 752 144 R0
SYMATTR InstName LNotch
SYMATTR Value 10
SYMBOL ind 1024 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName LTee1
SYMATTR Value 1p
SYMBOL ind 1200 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName LTee2
SYMATTR Value 1p
SYMBOL cap 176 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName CLFilt_C1
SYMATTR Value 400n
SYMBOL ind 1488 80 R0
SYMATTR InstName LDrive
SYMATTR Value 596u
SYMBOL cap 256 192 R0
SYMATTR InstName CFilt
SYMATTR Value 400n
SYMBOL ind 128 176 R0
SYMATTR InstName LCFilt_L
SYMATTR Value 100u
SYMATTR SpiceLine Rser=100m
SYMBOL cap 752 272 R0
SYMATTR InstName CNotch
SYMATTR Value 1p
SYMBOL cap 1408 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName CDrive
SYMATTR Value 66.7n
SYMBOL ind 672 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName LNotch_Tune
SYMATTR Value 1p
SYMBOL voltage -128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value AC 1
SYMBOL res -144 112 R0
SYMATTR InstName RSrc
SYMATTR Value 1m
SYMBOL ind 64 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName LFilt1
SYMATTR Value 100u
SYMATTR SpiceLine Rser=100m
SYMBOL res 1488 224 R0
SYMATTR InstName RDrive
SYMATTR Value .75
SYMBOL ind 384 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName LFilt2
SYMATTR Value 100u
SYMATTR SpiceLine Rser=100m
SYMBOL cap 1040 208 R0
SYMATTR InstName CPar
SYMATTR Value 1.5u
SYMBOL cap 1296 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName CSer
SYMATTR Value 10
SYMBOL cap 496 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName CLFilt_C2
SYMATTR Value 400n
FLAG -128 432 0
TEXT 264 432 Left 2 !.ac oct 1k 1k 500k
* Z:\home\khalils\Downloads\files\data\raw_asc\d2bf1a526ba9_Clamp1.asc
* Generated by LTspice 26.0.1 for Windows.
B5 Vo 0 V = if(V(V3)>V(Vmin),V(V3),V(Vmin))
B4 V3 0 V = if(V(Vmax)>V(in),V(in),V(Vmax))
B1 out 0 V = V(Vo)
B3 Vmin 0 V = {min}
B2 Vmax 0 V = {max}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 704 -80 624 -80
WIRE -608 16 -608 -48
WIRE -400 16 -400 -48
WIRE -240 16 -240 -48
WIRE 208 16 208 -48
WIRE 624 16 624 -80
WIRE -608 192 -608 96
WIRE -400 192 -400 96
WIRE -240 192 -240 96
WIRE 208 192 208 96
WIRE 624 192 624 96
WIRE -432 320 -576 320
IOPIN 704 -80 Out
IOPIN -576 320 In
SYMBOL bv 208 0 R0
WINDOW 3 -46 228 Left 0
SYMATTR Value V = if(V(V3)>V(Vmin),V(V3),V(Vmin))
SYMATTR InstName B5
SYMBOL bv -400 0 R0
WINDOW 3 -52 229 Left 0
SYMATTR Value V = {min}
SYMATTR InstName B3
SYMBOL bv -608 0 R0
WINDOW 3 -60 232 Left 0
SYMATTR Value V = {max}
SYMATTR InstName B2
SYMBOL bv -240 0 R0
WINDOW 3 -46 228 Left 0
SYMATTR Value V = if(V(Vmax)>V(in),V(in),V(Vmax))
SYMATTR InstName B4
SYMBOL bv 624 0 R0
SYMATTR InstName B1
SYMATTR Value V = V(Vo)
FLAG 624 192 0
FLAG 704 -80 out
FLAG -608 192 0
FLAG -400 192 0
FLAG -576 320 in
FLAG -608 -48 Vmax
FLAG -400 -48 Vmin
FLAG -240 192 0
FLAG -240 -48 V3
FLAG 208 192 0
FLAG 208 -48 Vo
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2138-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5
L1 N001 OUT 1 Rser=60m
Rload OUT 0 5
C1 OUT 0 10
XU1 IN IN N001 OUT 0 IN ADP2138-x.x Rtop=320K ;pnba Vin)EN)SW)Vout)GND)Mode
.tran .5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2138-2.5.asy)
.lib ADP2138-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2138-2.5 352 224 R0
SYMATTR InstName U1
TEXT 600 352 Left 2 !.tran .5m startup