* Z:\home\khalils\Downloads\files\data\raw_asc\42e879c4be1e_XorGate.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N002 B vdd vdd PMOS l=0.18u w=2u
M2 N001 A vdd vdd PMOS l=0.18u w=2u
M3 vout B_bar N001 vdd PMOS l=0.18u w=2u
M4 vout A_bar N002 vdd PMOS l=0.18u w=2u
M5 vout A N003 0 NMOS l=0.18u w=1u
M6 N003 B 0 0 NMOS l=0.18u w=1u
M7 vout B_bar N003 0 NMOS l=0.18u w=1u
M8 N003 A_bar 0 0 NMOS l=0.18u w=1u
vdd vdd 0 1.8
V1 A 0 PULSE(0 1.8 100p 10p 10p 10u 20u)
V2 B 0 PULSE(0 1.8 100p 10p 10p 10u 50u)
M9 A_bar A 0 0 NMOS l=0.18u w=1u
M10 A_bar A vdd vdd PMOS l=0.18u w=2u
M11 B_bar B 0 0 NMOS l=0.18u w=1u
M12 B_bar B vdd vdd PMOS l=0.18u w=2u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include tsmc180.txt
.op
.tran 50u
.meas time_12 find when V(A) = 0.9V rise = 1
.meas time_22 find when V(vout) = 0.9V fall = 1
.meas TPHL time_22 - time_12
.meas time_32 find when V(A) = 0.9V fall = 2
.meas time_42 find when V(vout) = 0.9V rise = 2
.meas TPLH time_42 - time_32
.meas dealy param (TPHL + TPLH)/2
* XOR Gate CMOS Implementation in 180nm Technology
* Delay from Input A to Output
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 680
WIRE 896 -336 896 -368
WIRE 944 -336 896 -336
WIRE 896 -320 896 -336
WIRE 256 -304 256 -320
WIRE 256 -304 160 -304
WIRE 368 -304 256 -304
WIRE 848 -304 784 -304
WIRE 160 -272 160 -304
WIRE 368 -272 368 -304
WIRE 944 -272 944 -336
WIRE 944 -272 896 -272
WIRE 112 -256 32 -256
WIRE 512 -256 416 -256
WIRE 256 -224 256 -304
WIRE 256 -224 160 -224
WIRE 368 -224 256 -224
WIRE 784 -192 784 -304
WIRE 784 -192 720 -192
WIRE 896 -192 896 -224
WIRE 1024 -192 896 -192
WIRE 896 -160 896 -192
WIRE 160 -112 160 -176
WIRE 368 -112 368 -176
WIRE 944 -112 896 -112
WIRE 112 -96 32 -96
WIRE 512 -96 416 -96
WIRE 784 -80 784 -192
WIRE 848 -80 784 -80
WIRE 256 -64 256 -224
WIRE 256 -64 160 -64
WIRE 368 -64 256 -64
WIRE 896 -32 896 -64
WIRE 944 -32 944 -112
WIRE 944 -32 896 -32
WIRE 896 16 896 -32
WIRE 160 48 160 -16
WIRE 256 48 160 48
WIRE 368 48 368 -16
WIRE 368 48 256 48
WIRE 256 96 256 48
WIRE 672 96 256 96
WIRE 256 128 256 96
WIRE 256 128 160 128
WIRE 368 128 256 128
WIRE 160 176 160 128
WIRE 368 176 368 128
WIRE 928 192 928 160
WIRE 976 192 928 192
WIRE 928 208 928 192
WIRE 256 224 160 224
WIRE 368 224 256 224
WIRE 880 224 816 224
WIRE -688 256 -688 192
WIRE -448 256 -448 192
WIRE 112 256 32 256
WIRE 512 256 416 256
WIRE 976 256 976 192
WIRE 976 256 928 256
WIRE -256 272 -256 208
WIRE 256 272 256 224
WIRE 160 320 160 272
WIRE 368 320 368 272
WIRE 368 320 160 320
WIRE 816 336 816 224
WIRE 816 336 752 336
WIRE 928 336 928 304
WIRE 1056 336 928 336
WIRE 160 368 160 320
WIRE 368 368 368 320
WIRE 928 368 928 336
WIRE -688 416 -688 336
WIRE -448 416 -448 336
WIRE -256 416 -256 352
WIRE 256 416 160 416
WIRE 368 416 256 416
WIRE 976 416 928 416
WIRE 112 448 32 448
WIRE 512 448 416 448
WIRE 816 448 816 336
WIRE 880 448 816 448
WIRE 928 496 928 464
WIRE 976 496 976 416
WIRE 976 496 928 496
WIRE 160 512 160 464
WIRE 256 512 256 416
WIRE 256 512 160 512
WIRE 368 512 368 464
WIRE 368 512 256 512
WIRE 256 544 256 512
WIRE 928 544 928 496
FLAG 928 160 vdd
IOPIN 928 160 In
FLAG 32 -256 A
IOPIN 32 -256 In
FLAG 512 -96 A_bar
IOPIN 512 -96 In
FLAG 512 -256 B
IOPIN 512 -256 In
FLAG 32 -96 B_bar
IOPIN 32 -96 In
FLAG 256 544 0
FLAG 672 96 vout
IOPIN 672 96 In
FLAG 32 256 A
IOPIN 32 256 In
FLAG 512 256 B_bar
IOPIN 512 256 In
FLAG 256 272 0
FLAG 32 448 B
IOPIN 32 448 In
FLAG 512 448 A_bar
IOPIN 512 448 In
FLAG -256 416 0
FLAG -256 208 vdd
IOPIN -256 208 In
FLAG -448 416 0
FLAG -688 416 0
FLAG -688 192 A
IOPIN -688 192 In
FLAG -448 192 B
IOPIN -448 192 In
FLAG 928 544 0
FLAG 1056 336 A_bar
IOPIN 1056 336 In
FLAG 752 336 A
IOPIN 752 336 In
FLAG 896 -368 vdd
IOPIN 896 -368 In
FLAG 896 16 0
FLAG 720 -192 B
IOPIN 720 -192 In
FLAG 1024 -192 B_bar
IOPIN 1024 -192 In
FLAG 256 -320 vdd
IOPIN 256 -320 In
SYMBOL pmos4 416 -176 R180
WINDOW 123 -75 -7 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=0.18u w=2u
SYMBOL pmos4 112 -176 M180
WINDOW 123 -61 -6 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=0.18u w=2u
SYMBOL pmos4 112 -16 M180
WINDOW 123 -60 -11 Left 2
SYMATTR InstName M3
SYMATTR Value2 l=0.18u w=2u
SYMBOL pmos4 416 -16 R180
WINDOW 123 -59 -10 Left 2
SYMATTR InstName M4
SYMATTR Value2 l=0.18u w=2u
SYMBOL nmos4 112 176 R0
WINDOW 123 -77 109 Left 2
SYMATTR InstName M5
SYMATTR Value2 l=0.18u w=1u
SYMBOL nmos4 112 368 R0
WINDOW 123 -49 109 Left 2
SYMATTR InstName M6
SYMATTR Value2 l=0.18u w=1u
SYMBOL nmos4 416 176 M0
WINDOW 123 -81 105 Left 2
SYMATTR InstName M7
SYMATTR Value2 l=0.18u w=1u
SYMBOL nmos4 416 368 M0
WINDOW 123 -63 104 Left 2
SYMATTR InstName M8
SYMATTR Value2 l=0.18u w=1u
SYMBOL voltage -256 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vdd
SYMATTR Value 1.8
SYMBOL voltage -688 240 R0
WINDOW 3 -45 -147 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1.8 100p 10p 10p 10u 20u)
SYMBOL voltage -448 240 R0
WINDOW 3 -52 -144 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1.8 100p 10p 10p 10u 50u)
SYMBOL nmos4 880 368 R0
WINDOW 123 -22 108 Left 2
SYMATTR InstName M9
SYMATTR Value2 l=0.18u w=1u
SYMBOL pmos4 880 304 M180
WINDOW 123 -34 -1 Left 2
SYMATTR InstName M10
SYMATTR Value2 l=0.18u w=2u
SYMBOL nmos4 848 -160 R0
WINDOW 123 -22 108 Left 2
SYMATTR InstName M11
SYMATTR Value2 l=0.18u w=1u
SYMBOL pmos4 848 -224 M180
WINDOW 123 -34 -1 Left 2
SYMATTR InstName M12
SYMATTR Value2 l=0.18u w=2u
TEXT -728 -352 Left 2 !.include tsmc180.txt
TEXT -720 -312 Left 2 !.op
TEXT -648 -312 Left 2 !.tran 50u
TEXT -760 -208 Left 2 !.meas time_12 find when V(A) = 0.9V rise = 1\n.meas time_22 find when V(vout) = 0.9V fall = 1\n.meas TPHL time_22 - time_12\n.meas time_32 find when V(A) = 0.9V fall  = 2\n.meas time_42 find when V(vout) = 0.9V rise = 2\n.meas TPLH  time_42 - time_32\n.meas dealy param (TPHL + TPLH)/2
TEXT -112 -440 Left 2 ;XOR Gate CMOS Implementation in 180nm Technology
TEXT -744 -240 Left 2 ;Delay from Input A to Output