* Z:\home\khalils\Downloads\files\data\raw_asc\16327adf4027_nand401.asc
* Generated by LTspice 26.0.1 for Windows.
M1 out in1 N001 N001 nfet l=180n w=720n
M2 VDD in2 out VDD pfet l=180n w=360n
M3 VDD in1 out VDD pfet l=180n w=360n
M4 N001 in2 N002 N002 nfet l=180n w=720n
M5 N002 in3 N003 N003 nfet l=180n w=720n
M6 VDD in3 out VDD pfet l=180n w=360n
M7 N003 in4 0 0 nfet l=180n w=720n
M8 VDD in4 out VDD pfet l=180n w=360n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib "D:\MIT MICRO\vsd internship\osu180_lib\osu018.lib"
* W=720n L=180n
* W=360nm, L=180nm
* W=720n L=180n
* W=360nm, L=180nm
* W=720n L=180n
* W=360n L=180n
* 4 Input NAND\n \nPMOS >>> 2:1\nNMOS >>> 4:1
* W=720n L=180n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 916 1040
WIRE -80 0 -240 0
WIRE 96 0 -80 0
WIRE 272 0 272 -48
WIRE 272 0 96 0
WIRE 96 32 96 0
WIRE 128 32 96 32
WIRE -240 48 -240 0
WIRE -192 48 -240 48
WIRE -80 48 -80 0
WIRE -48 48 -80 48
WIRE 272 48 272 0
WIRE 336 48 272 48
WIRE 96 64 96 32
WIRE 272 64 272 48
WIRE -192 96 -192 48
WIRE -192 96 -240 96
WIRE -48 96 -48 48
WIRE -48 96 -80 96
WIRE 128 112 128 32
WIRE 128 112 96 112
WIRE 336 112 336 48
WIRE 336 112 272 112
WIRE -288 128 -320 128
WIRE -128 128 -144 128
WIRE 48 144 16 144
WIRE 224 144 192 144
WIRE -240 176 -240 144
WIRE -80 176 -80 144
WIRE -80 176 -240 176
WIRE 96 176 96 160
WIRE 96 176 -80 176
WIRE 272 176 272 160
WIRE 272 176 96 176
WIRE 384 176 272 176
WIRE 16 192 16 144
WIRE 16 192 -608 192
WIRE 336 224 272 224
WIRE 16 256 16 192
WIRE 224 256 16 256
WIRE 272 288 272 272
WIRE 336 288 336 224
WIRE 336 288 272 288
WIRE 272 336 272 288
WIRE 192 352 192 144
WIRE 192 352 -608 352
WIRE 320 384 272 384
WIRE 192 416 192 352
WIRE 224 416 192 416
WIRE 272 464 272 432
WIRE 320 464 320 384
WIRE 320 464 272 464
WIRE 272 512 272 464
WIRE 320 560 272 560
WIRE -144 592 -144 128
WIRE -144 592 -608 592
WIRE 224 592 -144 592
WIRE 272 624 272 608
WIRE 320 624 320 560
WIRE 320 624 272 624
WIRE 272 672 272 624
WIRE 320 720 272 720
WIRE -320 752 -320 128
WIRE -320 752 -608 752
WIRE 224 752 -320 752
WIRE 272 800 272 768
WIRE 320 800 320 720
WIRE 320 800 272 800
WIRE 272 928 272 800
FLAG 384 176 out
IOPIN 384 176 Out
FLAG -608 192 in1
IOPIN -608 192 In
FLAG 272 -48 VDD
IOPIN 272 -48 In
FLAG 272 928 GND
IOPIN 272 928 In
FLAG -608 352 in2
IOPIN -608 352 In
FLAG -608 592 in3
IOPIN -608 592 In
FLAG -608 752 in4
IOPIN -608 752 In
SYMBOL nmos4 224 176 R0
SYMATTR InstName M1
SYMATTR Value2 l=180n w=720n
SYMATTR Value nfet
SYMBOL pmos4 224 64 R0
SYMATTR InstName M2
SYMATTR Value2 l=180n w=360n
SYMATTR Value pfet
SYMBOL pmos4 48 64 R0
SYMATTR InstName M3
SYMATTR Value pfet
SYMATTR Value2 l=180n w=360n
SYMBOL nmos4 224 336 R0
SYMATTR InstName M4
SYMATTR Value nfet
SYMATTR Value2 l=180n w=720n
SYMBOL nmos4 224 512 R0
SYMATTR InstName M5
SYMATTR Value nfet
SYMATTR Value2 l=180n w=720n
SYMBOL pmos4 -128 48 R0
SYMATTR InstName M6
SYMATTR Value pfet
SYMATTR Value2 l=180n w=360n
SYMBOL nmos4 224 672 R0
SYMATTR InstName M7
SYMATTR Value nfet
SYMATTR Value2 l=180n w=720n
SYMBOL pmos4 -288 48 R0
SYMATTR InstName M8
SYMATTR Value pfet
SYMATTR Value2 l=180n w=360n
TEXT -448 -112 Left 2 !.lib "D:\\MIT MICRO\\vsd internship\\osu180_lib\\osu018.lib"
TEXT 352 304 Left 2 ;W=720n  L=180n
TEXT 352 88 Left 2 ;W=360nm, L=180nm
TEXT 360 464 Left 2 ;W=720n  L=180n
TEXT -320 -24 Left 2 ;W=360nm, L=180nm
TEXT 360 584 Left 2 ;W=720n  L=180n
TEXT 16 -24 Left 2 ;W=360n  L=180n
TEXT -704 -64 Left 2 ;4 Input NAND\n \nPMOS >>> 2:1\nNMOS >>> 4:1
TEXT 368 752 Left 2 ;W=720n  L=180n
RECTANGLE Normal -512 64 -720 -112 2