* Z:\tmp\asc_dec_bjh7r6w2\0d7394a8060e_SuccessiveApproximationRegister_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
S6 D1 0 VDD/2 N006 SW
A8 N001 0 RST 0 0 0 N007 0 DFLOP
S2 D3 0 VDD/2 N004 SW
A12 P0 CLK 0 0 0 0 Pre0 0 AND
S5 VDD D1 N006 VDD/2 SW
A7 B1 0 RST 0 0 0 N006 0 DFLOP
VDD1 VDD/2 0 .5
S4 D2 0 VDD/2 N008 SW
A5 N003 0 RST 0 0 0 N004 0 DFLOP
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1744 1132
WIRE 1056 32 1024 32
WIRE 1056 48 1056 32
WIRE 1072 48 1056 48
WIRE 1072 64 1024 64
WIRE 1168 64 1136 64
WIRE 1168 128 1168 64
WIRE 960 176 960 32
WIRE 960 176 896 176
WIRE 1088 176 1056 176
WIRE 1312 176 1248 176
WIRE 384 224 368 224
WIRE 1088 224 1072 224
WIRE 464 320 464 272
WIRE 464 320 144 320
WIRE 816 320 464 320
WIRE 1168 320 1168 272
WIRE 1168 320 816 320
WIRE 368 432 224 432
WIRE 560 432 528 432
WIRE 608 432 608 176
WIRE 720 432 608 432
WIRE 960 432 960 176
WIRE 1072 432 960 432
WIRE 1264 432 1232 432
WIRE 1312 432 1312 176
WIRE 1376 432 1312 432
WIRE 1568 432 1536 432
WIRE 368 480 352 480
WIRE 1072 480 1056 480
WIRE 1376 480 1360 480
WIRE 352 560 352 480
WIRE 352 560 320 560
WIRE 704 560 704 480
WIRE 704 560 352 560
WIRE 1056 560 1056 480
WIRE 1056 560 704 560
WIRE 1360 560 1360 480
WIRE 1360 560 1056 560
WIRE 288 624 256 624
WIRE 256 656 256 624
WIRE 560 672 560 432
WIRE 560 672 528 672
WIRE 592 672 560 672
WIRE 912 672 912 432
WIRE 912 672 880 672
WIRE 944 672 912 672
WIRE 1264 672 1264 432
WIRE 1264 672 1232 672
WIRE 1296 672 1264 672
WIRE 1568 672 1568 432
WIRE 1568 672 1536 672
WIRE 1600 672 1568 672
WIRE 480 688 480 672
WIRE 528 688 528 672
WIRE 592 688 592 672
WIRE 640 688 640 672
WIRE 832 688 832 672
WIRE 880 688 880 672
WIRE 944 688 944 672
WIRE 992 688 992 672
WIRE 1184 688 1184 672
WIRE 1232 688 1232 672
WIRE 1296 688 1296 672
WIRE 1344 688 1344 672
WIRE 1488 688 1488 672
WIRE 1536 688 1536 672
WIRE 464 736 448 736
WIRE 560 736 544 736
WIRE 576 736 560 736
WIRE 816 736 800 736
WIRE 912 736 896 736
WIRE 928 736 912 736
WIRE 1168 736 1152 736
WIRE 1264 736 1248 736
WIRE 1280 736 1264 736
WIRE 1472 736 1456 736
WIRE 1568 736 1552 736
WIRE 1584 736 1568 736
WIRE 256 752 256 736
WIRE 448 752 448 736
WIRE 800 752 800 736
WIRE 1152 752 1152 736
WIRE 1456 752 1456 736
WIRE 560 816 560 736
WIRE 912 816 912 736
WIRE 1264 816 1264 736
WIRE 1568 816 1568 736
SYMBOL sw 1264 736 R90
WINDOW 0 45 40 VLeft 2
WINDOW 3 46 84 VLeft 2
SYMATTR InstName S6
SYMBOL Digital\\dflop 1456 384 R0
SYMATTR InstName A8
SYMBOL sw 560 736 R90
WINDOW 0 45 40 VLeft 2
WINDOW 3 46 84 VLeft 2
SYMATTR InstName S2
SYMBOL Digital\\and 1104 16 R0
WINDOW 0 -14 17 Left 2
SYMATTR InstName A12
SYMBOL sw 1376 736 R90
WINDOW 0 45 81 VRight 2
WINDOW 3 52 36 VRight 2
SYMATTR InstName S5
SYMBOL Digital\\dflop 1152 384 R0
SYMATTR InstName A7
SYMBOL voltage 256 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD1
SYMATTR Value .5
SYMBOL sw 912 736 R90
WINDOW 0 45 40 VLeft 2
WINDOW 3 46 84 VLeft 2
SYMATTR InstName S4
SYMBOL Digital\\dflop 448 384 R0
SYMATTR InstName A5
FLAG 1024 32 P0
FLAG 320 560 RST
FLAG 1056 176 Comp
FLAG 1024 64 CLK
FLAG 1072 224 _P0
FLAG 368 224 _P2
FLAG 960 32 B1
FLAG 1568 816 D0
FLAG 1264 816 D1
FLAG 912 816 D2
FLAG 560 816 D3
FLAG 1168 64 Pre0
FLAG 448 752 0
FLAG 656 736 VDD
FLAG 640 672 VDD/2
FLAG 480 672 VDD/2
FLAG 800 752 0
FLAG 1008 736 VDD
FLAG 992 672 VDD/2
FLAG 832 672 VDD/2
FLAG 1152 752 0
FLAG 1360 736 VDD
FLAG 1344 672 VDD/2
FLAG 1184 672 VDD/2
FLAG 1456 752 0
FLAG 1488 672 VDD/2
FLAG 256 752 0
FLAG 288 624 VDD/2