* Z:\home\khalils\Downloads\files\data\raw_asc\1e36fcbeb016_Fig16_29.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 clock 0 0 N_50n l=50n w=500n
VDD VDD 0 1
M11 Outm clock Inm VDD P_50n l=50n w=1u
M2 Outp Outm VDD VDD P_50n l=50n w=1u
M3 Outm Outp VDD VDD P_50n l=50n w=1u
M4 Inp clock Outp VDD P_50n l=50n w=1u
M5 Outm Outp N001 0 N_50n l=50n w=500n
M6 Outp Outm N001 0 N_50n l=50n w=500n
Vinm Inm 0 500m
Vinp Inp 0 PULSE .4 .6 5n 0 0 4n 12n
Vclock clock 0 PULSE 0 1 0 0 0 5n 10n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.tran 0 31n 1n uic
* Plot I(VDD)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1556 680
WIRE 80 -400 80 -432
WIRE 80 -288 80 -320
WIRE 80 -144 80 -176
WIRE 80 -32 80 -64
WIRE 208 -400 208 -432
WIRE 208 -288 208 -320
WIRE 208 -160 208 -192
WIRE 208 -48 208 -80
WIRE 304 -256 288 -256
WIRE 336 -256 304 -256
WIRE 416 0 416 -208
WIRE 480 -256 432 -256
WIRE 480 0 416 0
WIRE 512 -304 512 -320
WIRE 512 -256 480 -256
WIRE 512 -256 512 -304
WIRE 512 -224 512 -256
WIRE 512 -208 512 -224
WIRE 512 -96 512 -112
WIRE 544 0 480 0
WIRE 544 64 544 0
WIRE 592 -400 560 -400
WIRE 592 -304 512 -304
WIRE 592 -224 512 -224
WIRE 592 -128 560 -128
WIRE 592 0 544 0
WIRE 640 -96 512 -96
WIRE 640 -80 640 -96
WIRE 672 -400 592 -304
WIRE 672 -304 592 -400
WIRE 672 -224 592 -128
WIRE 672 -128 592 -224
WIRE 704 -400 672 -400
WIRE 704 -128 672 -128
WIRE 752 -304 672 -304
WIRE 752 -304 752 -320
WIRE 752 -256 752 -304
WIRE 752 -224 672 -224
WIRE 752 -224 752 -256
WIRE 752 -208 752 -224
WIRE 752 -96 640 -96
WIRE 752 -96 752 -112
WIRE 800 -256 752 -256
WIRE 848 -256 800 -256
WIRE 928 64 544 64
WIRE 928 64 928 -208
WIRE 976 -256 944 -256
WIRE 992 -256 976 -256
FLAG 640 -32 0
FLAG 80 -288 0
FLAG 80 -432 VDD
FLAG 896 -256 VDD
FLAG 512 -368 VDD
FLAG 752 -368 VDD
FLAG 512 -416 VDD
FLAG 752 -416 VDD
FLAG 384 -256 VDD
FLAG 640 16 0
FLAG 752 -160 0
FLAG 512 -160 0
FLAG 304 -256 Inp
FLAG 976 -256 Inm
FLAG 480 0 clock
FLAG 800 -256 Outm
FLAG 480 -256 Outp
FLAG 208 -288 0
FLAG 208 -432 Inm
FLAG 80 -32 0
FLAG 80 -176 Inp
FLAG 208 -48 0
FLAG 208 -192 clock
SYMBOL nmos4 592 -80 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 80 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL pmos4 848 -208 R270
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M11
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 560 -320 R180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 704 -320 M180
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL pmos4 336 -208 R270
WINDOW 0 56 32 Invisible 0
WINDOW 3 56 72 Invisible 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 704 -208 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M5
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL nmos4 560 -208 M0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
SYMATTR InstName M6
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 208 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 500m
SYMATTR InstName Vinm
SYMBOL voltage 80 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -40 182 Left 0
SYMATTR Value PULSE .4 .6 5n 0 0 4n 12n
SYMATTR InstName Vinp
SYMBOL voltage 208 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -83 163 Left 0
SYMATTR Value PULSE 0  1 0 0 0 5n 10n
SYMATTR InstName Vclock
TEXT 88 80 Left 0 !.lib cmosedu_models.txt
TEXT 88 56 Left 0 !.tran 0 31n 1n uic
TEXT 320 -472 Left 0 ;Plot I(VDD)