* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2325-16.asc
* Generated by LTspice 26.0.1 for Windows.
* SCLK and _CNV\nare shown in timing\ndiagram on page 14, 15\nof LTC2325-16 data sheet
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\LTC2325-16.asy)
C3 N004 0 10p ic=4.096
Va+ Ain+ 0 PWL(0 0 200u 4.096)
V2 N001 0 PWL(0 0 0.1u 5)
V1 N005 0 PULSE(0 1.8 227n 0.1n 0.1n 40n 199.5n)
C2 N003 0 10 ic=4.096 Rser=10m
V4 N007 0 3
Vsclk2 sclk2 0 PULSE(0 1.81 11.875n 0.1n 0.1n 66.5n 199.5n)
V3 N002 0 1.8
Vsclk1 sclk1 0 PULSE(0 1.8 9.5n 0.1n 0.1n 4.05625n 8.3125n)
C1 OUT 0 10p
XU1 N001 Ain+ Ain- N004 N003 N005 N006 OUT NC_01 N002 0 MP_02 N007 LTC2325-16 ;pnba Vdd)Ain+)Ain-)REF)REFout1)_CNV)SCLK)Vout1)SCLKout)OVdd)GND))RefBufEN
Bsclk N006 0 V=if(V(sclk2)>V(sclk1),V(sclk2),V(sclk1))
Va- Ain- 0 PWL(0 4.096 200u 0)
.tran 250u
.lib LTC2325-16.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 1252
WIRE 208 0 160 0
WIRE 352 0 288 0
WIRE 528 0 480 0
WIRE 656 0 608 0
WIRE -416 64 -464 64
WIRE -224 64 -336 64
WIRE 352 80 352 0
WIRE 480 80 480 0
WIRE 704 80 704 48
WIRE -224 128 -224 64
WIRE 240 128 -224 128
WIRE 704 160 704 144
WIRE 704 160 592 160
WIRE 240 176 -224 176
WIRE -416 240 -464 240
WIRE -224 240 -224 176
WIRE -224 240 -336 240
WIRE 80 240 48 240
WIRE 240 240 144 240
WIRE 704 240 592 240
WIRE 704 256 704 240
WIRE -112 304 -144 304
WIRE 240 304 -32 304
WIRE 704 336 704 320
WIRE 240 368 176 368
WIRE 176 448 176 368
WIRE 352 448 352 416
WIRE 480 464 480 416
WIRE 640 464 480 464
WIRE 752 464 720 464
WIRE 176 560 176 528
WIRE -272 672 -272 656
WIRE 416 672 416 656
WIRE -272 784 -272 752
WIRE 416 784 416 752
SYMBOL voltage -320 240 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName Va-
SYMATTR Value PWL(0 4.096 200u 0)
SYMBOL voltage 304 0 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 -68 56 VBottom 2
WINDOW 39 -50 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 0.1u 5)
SYMBOL voltage 512 0 M90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 68 56 VTop 2
WINDOW 39 50 56 VTop 2
SYMATTR InstName V3
SYMATTR Value 1.8
SYMBOL voltage 624 464 M90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 68 56 VTop 2
WINDOW 39 50 56 VTop 2
SYMATTR InstName V4
SYMATTR Value 3
SYMBOL cap 688 144 M180
WINDOW 0 38 64 Left 2
WINDOW 3 41 41 Left 2
WINDOW 123 41 -7 Left 2
WINDOW 39 41 16 Left 2
SYMATTR InstName C2
SYMATTR Value 10
SYMATTR Value2 ic=4.096
SYMATTR SpiceLine Rser=10m
SYMBOL voltage -16 304 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1.8 227n 0.1n 0.1n 40n 199.5n)
SYMBOL cap 688 256 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL cap 144 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 33 59 VTop 2
WINDOW 123 34 -27 VTop 2
SYMATTR InstName C3
SYMATTR Value 10p
SYMATTR Value2 ic=4.096
SYMBOL bv 176 432 R0
SYMATTR InstName Bsclk
SYMATTR Value V=if(V(sclk2)>V(sclk1),V(sclk2),V(sclk1))
SYMBOL voltage -272 656 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vsclk1
SYMATTR Value PULSE(0 1.8 9.5n 0.1n 0.1n 4.05625n 8.3125n)
SYMBOL voltage -320 64 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Va+
SYMATTR Value PWL(0 0 200u 4.096)
SYMBOL voltage 416 656 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vsclk2
SYMATTR Value PULSE(0 1.81 11.875n 0.1n 0.1n 66.5n 199.5n)
SYMBOL LTC2325-16 416 240 R0
SYMATTR InstName U1
FLAG 352 448 0
FLAG 704 240 OUT
FLAG 704 336 0
FLAG -464 240 0
FLAG -144 304 0
FLAG -272 784 0
FLAG 416 784 0
FLAG 416 656 sclk2
FLAG -272 656 sclk1
FLAG 176 560 0
FLAG -464 64 0
FLAG 160 0 0
FLAG 656 0 0
FLAG 704 48 0
FLAG 48 240 0
FLAG 752 464 0
FLAG -224 64 Ain+
FLAG -224 240 Ain-
TEXT 640 592 Left 2 !.tran 250u
TEXT -176 448 Left 2 ;SCLK and _CNV\nare shown in timing\ndiagram on page 14, 15\nof LTC2325-16 data sheet