* Z:\tmp\asc_dec_bjh7r6w2\0e8f5883c680_wijekoon_neuron_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
M12 N002 post_synaptic_input N006 0 NMOS l=180n w=1.3u
M10 N002 N002 N001 N001 PMOS l=234n w=1.8u
M7 N004 N003 N001 N001 PMOS l=2.52u w=1.3u
V5 Vbias 0 0.3
C2 N004 0 550f
M1 N008 post_synaptic_input N003 N008 NMOS l=180n w=2.3u
M3 post_synaptic_input N003 N001 N001 PMOS l=180n w=1u
V4 Vth 0 0.4
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1880 680
WIRE 320 -112 160 -112
WIRE 368 -112 320 -112
WIRE 464 -112 368 -112
WIRE 512 -112 464 -112
WIRE 688 -112 688 -176
WIRE 688 -112 512 -112
WIRE 816 -112 688 -112
WIRE 1280 -112 816 -112
WIRE 1376 -112 1280 -112
WIRE 1648 -112 1376 -112
WIRE 1504 -96 1424 -96
WIRE 1280 -64 1280 -112
WIRE 1376 -64 1280 -64
WIRE 368 -48 368 -112
WIRE 512 -48 512 -112
WIRE 224 -32 208 -32
WIRE 416 -32 224 -32
WIRE 560 -32 416 -32
WIRE 1504 -32 1504 -96
WIRE 1520 -32 1504 -32
WIRE 1600 -32 1520 -32
WIRE 320 0 320 -112
WIRE 368 0 320 0
WIRE 464 0 464 -112
WIRE 512 0 464 0
WIRE 1376 32 1376 -16
WIRE 1520 32 1520 -32
WIRE 1520 32 1376 32
WIRE 928 48 928 -32
WIRE 1088 48 928 48
WIRE 1200 48 1088 48
WIRE 1376 48 1376 32
WIRE 1376 48 1200 48
WIRE 160 80 160 48
WIRE 224 80 224 -32
WIRE 224 80 160 80
WIRE 512 80 512 48
WIRE 752 80 512 80
WIRE 1280 96 1200 96
WIRE 992 128 528 128
WIRE 1152 128 992 128
WIRE 1040 144 1040 -224
WIRE 1328 144 1200 144
WIRE 1472 144 1328 144
WIRE 1728 144 1472 144
WIRE 160 160 160 80
WIRE 1472 160 1472 144
WIRE 1472 160 1392 160
WIRE 1552 160 1472 160
WIRE 272 176 208 176
WIRE 368 176 368 48
WIRE 368 176 272 176
WIRE 384 176 368 176
WIRE 528 176 528 128
WIRE 528 176 384 176
WIRE 992 176 928 176
WIRE 1728 176 1600 176
WIRE 384 192 384 176
WIRE 720 192 576 192
WIRE 752 192 752 80
WIRE 752 192 720 192
WIRE 768 192 752 192
WIRE 848 192 848 48
WIRE 848 192 768 192
WIRE 160 208 128 208
WIRE 768 208 768 192
WIRE 848 208 848 192
WIRE 528 224 464 224
WIRE 720 240 656 240
WIRE 992 240 992 224
WIRE 1328 240 1328 144
WIRE 1344 240 1328 240
WIRE 128 288 128 208
WIRE 160 288 160 256
WIRE 160 288 128 288
WIRE 384 288 384 256
WIRE 384 288 160 288
WIRE 464 288 464 224
WIRE 464 288 384 288
WIRE 656 288 656 240
WIRE 656 288 528 288
WIRE 720 288 656 288
WIRE 848 288 848 272
WIRE 848 288 720 288
WIRE 928 288 928 176
WIRE 928 288 848 288
WIRE 976 288 928 288
WIRE 1280 288 1280 96
WIRE 1280 288 976 288
WIRE 272 320 272 176
WIRE 272 320 80 320
WIRE 976 352 976 288
WIRE 1088 352 1088 48
SYMBOL nmos4 1152 48 R0
SYMATTR InstName M12
SYMATTR Value2 l=180n w=1.3u
SYMBOL pmos4 1424 -16 R180
SYMATTR InstName M10
SYMATTR Value2 l=234n w=1.8u
SYMBOL pmos4 560 48 R180
SYMATTR InstName M7
SYMATTR Value2 l=2.52u w=1.3u
SYMBOL voltage 672 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 0.3
SYMBOL cap 832 208 R0
SYMATTR InstName C2
SYMATTR Value 550f
SYMBOL nmos4 208 256 R180
SYMATTR InstName M1
SYMATTR Value2 l=180n w=2.3u
SYMBOL pmos4 416 48 R180
SYMATTR InstName M3
SYMATTR Value2 l=180n w=1u
SYMBOL voltage 528 -480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0.4
FLAG 976 352 0
FLAG 992 240 c
FLAG 80 320 post_synaptic_input
FLAG 384 -384 0
FLAG 528 -384 0
FLAG 672 -384 0
FLAG 384 -464 c
FLAG 528 -464 Vth
FLAG 672 -464 Vbias
FLAG 800 -384 0
FLAG 800 -464 d