Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\07ca49e66ec5_logic_level_shifter.asc
* Generated by LTspice 26.0.1 for Windows.
V3 3V3 0 3.3V
M1 Vout 3V3 3V3_IN 3V3_IN NMOS
R2 5V Vout 1k
V1 5V 0 5V
V2 3V3_IN 0 PULSE(0 3.3V)
R1 3V3 3V3_IN 1k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1116 1080
WIRE 496 32 496 -16
WIRE 560 32 496 32
WIRE 496 48 496 32
WIRE 672 64 672 -16
WIRE 560 96 560 32
WIRE 496 144 496 128
WIRE 496 144 448 144
WIRE 544 144 496 144
WIRE 672 144 640 144
WIRE 816 144 672 144
WIRE -128 272 -128 176
WIRE -32 272 -32 176
WIRE 64 272 64 176
WIRE -128 384 -128 352
WIRE -32 384 -32 352
WIRE 64 384 64 352
SYMBOL voltage 64 256 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3V)
SYMBOL Res 656 48 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL Res 480 32 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -32 256 R0
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL voltage -128 256 R0
SYMATTR InstName V3
SYMATTR Value 3.3V
SYMBOL nmos 640 96 R90
SYMATTR InstName M1
FLAG -32 176 5V
FLAG 64 176 3V3_IN
FLAG -32 384 0
FLAG 64 384 0
FLAG 448 144 3V3_IN
FLAG 672 -16 5V
FLAG -128 384 0
FLAG -128 176 3V3
FLAG 496 -16 3V3
FLAG 816 144 Vout
* Z:\home\khalils\Downloads\files\data\raw_asc\0ee497f66acf_Design_A_Transistor.asc
* Generated by LTspice 26.0.1 for Windows.
* Vbe < 0.7v
* Ib = 5.6301mA
* Ic = B*Ic
* Ic = 56.658mA
* B = 110
* From datasheet B = 110 but we will use Bforced = 10 to force transistor to be in saturation region and to be fully on
Rb N003 Vcontrol 750
Vcc Vcc 0 12V
Rc Vcc N001 150
Vcontrol_1 Vcontrol 0 5V
D1 N001 N002 NSPW500BS
Q1 N002 N003 0 0 BC547C
D2 N001 N002 NSPW500BS
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 3268 680
WIRE 400 -160 400 -224
WIRE 400 -32 400 -80
WIRE 400 -32 304 -32
WIRE 496 -32 400 -32
WIRE 304 0 304 -32
WIRE 496 0 496 -32
WIRE 304 96 304 64
WIRE 400 96 304 96
WIRE 496 96 496 64
WIRE 496 96 400 96
WIRE -704 144 -704 80
WIRE 400 144 400 96
WIRE -544 160 -544 96
WIRE 16 192 -160 192
WIRE 336 192 96 192
WIRE -704 256 -704 224
WIRE -544 272 -544 240
WIRE 400 336 400 240
DATAFLAG -64 192 ""
DATAFLAG 256 192 ""
DATAFLAG 400 272 ""
SYMBOL voltage -544 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcontrol_1
SYMATTR Value 5V
SYMBOL res 112 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rb
SYMATTR Value 750
SYMBOL LED 288 0 R0
WINDOW 0 -27 3 Left 2
WINDOW 3 -133 58 Left 2
SYMATTR InstName D2
SYMATTR Value NSPW500BS
SYMBOL LED 480 0 R0
SYMATTR InstName D1
SYMATTR Value NSPW500BS
SYMBOL npn 336 144 R0
SYMATTR InstName Q1
SYMATTR Value BC547C
SYMBOL res 384 -176 R0
SYMATTR InstName Rc
SYMATTR Value 150
SYMBOL voltage -704 128 R0
SYMATTR InstName Vcc
SYMATTR Value 12V
FLAG 400 336 0
FLAG -160 192 Vcontrol
FLAG 400 -224 Vcc
FLAG -704 256 0
FLAG -704 80 Vcc
FLAG -544 272 0
FLAG -544 96 Vcontrol
TEXT -736 360 Left 2 !.tran 0.1
TEXT 208 224 Left 2 ;Vbe < 0.7v
TEXT 0 368 Left 2 ;Ib = 5.6301mA
TEXT 8 400 Left 2 ;Ic = B*Ic
TEXT 8 464 Left 2 ;Ic = 56.658mA
TEXT 128 400 Left 2 ;B = 110
TEXT 8 432 Left 2 ;From datasheet B = 110 but we will use Bforced = 10 to force transistor to be in saturation region and to be fully on
* Z:\home\khalils\Downloads\files\data\raw_asc\07ca49e66ec5_logic_level_shifter.asc
* Generated by LTspice 26.0.1 for Windows.
V2 3V3_IN 0 PULSE(0 3.3V)
M1 Vout 3V3 3V3_IN 3V3_IN NMOS
V3 3V3 0 3.3V
R2 5V Vout 1k
R1 3V3 3V3_IN 1k
V1 5V 0 5V
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1116 1080
WIRE 496 32 496 -16
WIRE 560 32 496 32
WIRE 496 48 496 32
WIRE 672 64 672 -16
WIRE 560 96 560 32
WIRE 496 144 496 128
WIRE 496 144 448 144
WIRE 544 144 496 144
WIRE 672 144 640 144
WIRE 816 144 672 144
WIRE -128 272 -128 176
WIRE -32 272 -32 176
WIRE 64 272 64 176
WIRE -128 384 -128 352
WIRE -32 384 -32 352
WIRE 64 384 64 352
SYMBOL voltage -32 256 R0
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL voltage -128 256 R0
SYMATTR InstName V3
SYMATTR Value 3.3V
SYMBOL Res 656 48 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL Res 480 32 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 64 256 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3V)
SYMBOL nmos 640 96 R90
SYMATTR InstName M1
FLAG -32 176 5V
FLAG 64 176 3V3_IN
FLAG -32 384 0
FLAG 64 384 0
FLAG 448 144 3V3_IN
FLAG 672 -16 5V
FLAG -128 384 0
FLAG -128 176 3V3
FLAG 496 -16 3V3
FLAG 816 144 Vout
* Z:\home\khalils\Downloads\files\data\raw_asc\2ndOrderHighpass.asc
* Generated by LTspice 26.0.1 for Windows.
* f0 and Q set by parameters
* R1 is arbitary
* This version puts 1/2 the R1 resistance in the capacitor
* Vout
* Vin
* High frequency gain is set by the parameter "H"
G1 0 N002 1 0 {2/R1}
R2 2 0 .1
R3 2 0 1Meg
R1 N002 0 {R1/2}
L1 N003 0 {L1}
G2 0 2 N003 0 {10*H}
V1 1 0 AC 1
C1 N002 N003 {C1} Rser={R1/2}
.param f0= 1k Q=.5
.param R1=1k
.param L1=R1*Q/(2*pi*f0)
.param C1=1/(L1*(2*pi*f0)**2)
.param H=1
.ac dec 101 100 10k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE -560 -128 -624 -128
WIRE -464 -128 -496 -128
WIRE -288 -128 -416 -128
WIRE -208 -128 -288 -128
WIRE -32 -128 -144 -128
WIRE 96 -128 -32 -128
WIRE 256 -128 144 -128
WIRE 320 -128 256 -128
WIRE 352 -128 320 -128
WIRE 480 -128 416 -128
WIRE -624 -96 -624 -128
WIRE -416 -96 -416 -128
WIRE -32 -96 -32 -128
WIRE -464 -80 -464 -128
WIRE -288 -64 -288 -128
WIRE 144 -64 144 -128
WIRE 256 -64 256 -128
WIRE 480 -64 480 -128
WIRE 96 -48 96 -128
WIRE -624 0 -624 -16
WIRE -464 0 -464 -32
WIRE -416 0 -416 -16
WIRE -32 32 -32 -16
WIRE 96 32 96 0
WIRE 144 32 144 16
WIRE 256 32 256 16
WIRE 480 32 480 16
WIRE -288 48 -288 16
SYMBOL g 144 -80 R0
SYMATTR InstName G2
SYMATTR Value {10*H}
SYMBOL res 464 -80 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL cap -208 -112 R270
WINDOW 0 52 17 VRight 2
WINDOW 3 -26 17 VRight 2
WINDOW 123 -57 10 VRight 2
SYMATTR InstName C1
SYMATTR Value {C1}
SYMATTR Value2 Rser={R1/2}
SYMBOL res -304 -80 R0
SYMATTR InstName R1
SYMATTR Value {R1/2}
SYMBOL res 240 -80 R0
SYMATTR InstName R2
SYMATTR Value .1
SYMBOL Misc\\jumper 384 -192 R0
SYMATTR InstName J2
SYMBOL Misc\\jumper -528 -192 M0
SYMATTR InstName J1
SYMBOL ind -48 -112 R0
WINDOW 0 59 45 Bottom 2
WINDOW 3 61 51 Top 2
SYMATTR InstName L1
SYMATTR Value {L1}
SYMBOL g -416 -112 R0
SYMATTR InstName G1
SYMATTR Value {2/R1}
SYMBOL voltage -624 -112 R0
WINDOW 0 33 30 Left 2
WINDOW 123 32 79 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value2 AC 1
SYMATTR Value ""
FLAG -32 32 0
FLAG -288 48 0
FLAG -416 0 0
FLAG -464 0 0
FLAG 96 32 0
FLAG 144 32 0
FLAG 256 32 0
FLAG 320 -128 2
FLAG -464 -128 1
FLAG -624 0 0
FLAG 480 32 0
TEXT -304 96 Left 2 !.param f0= 1k Q=.5
TEXT -464 160 Left 2 !.param R1=1k
TEXT -640 224 Left 2 !.param L1=R1*Q/(2*pi*f0)
TEXT -632 96 Left 2 ;f0 and Q set by parameters
TEXT -632 160 Left 2 ;R1 is arbitary
TEXT -632 128 Left 2 ;This version puts 1/2 the R1 resistance in the capacitor
TEXT -640 256 Left 2 !.param C1=1/(L1*(2*pi*f0)**2)
TEXT 432 -144 Left 2 ;Vout
TEXT -576 -144 Right 2 ;Vin
TEXT -632 192 Left 2 ;High frequency gain is set by the parameter "H"
TEXT -80 192 Left 2 !.param H=1
TEXT -640 288 Left 2 !.ac dec 101 100 10k
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2138-1.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2138-1.0.asy)
L1 N001 OUT 1 Rser=60m
C1 OUT 0 10
V1 IN 0 5
XU1 IN IN N001 OUT 0 IN ADP2138-x.x Rtop=80K ;pnba Vin)EN)SW)Vout)GND)Mode
Rload OUT 0 2
.tran .5m startup
.lib ADP2138-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL ADP2138-1.0 352 224 R0
SYMATTR InstName U1
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 600 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\3ca8a9fc3ff6_Parte3.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout N002 0 N003 N_1u l=1.5u w=9.23u
Vgs N002 0 SINE(0 200m 1k)
Vdd N001 0 5
Rd N001 Vout 10k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.dc Vgs 0 5 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 -160 144 -160
WIRE 144 -144 144 -160
WIRE 192 -96 144 -96
WIRE 288 -16 288 -160
WIRE 288 -16 192 -16
WIRE 144 16 144 -96
WIRE 144 128 144 96
WIRE 224 128 144 128
WIRE 64 176 -32 176
WIRE 176 176 144 176
WIRE 64 208 64 176
WIRE 96 208 64 208
WIRE 176 208 176 176
WIRE 176 208 144 208
WIRE 144 272 144 224
WIRE -32 304 -32 256
SYMBOL voltage 192 -112 R0
SYMATTR InstName Vdd
SYMATTR Value 5
SYMBOL nmos4 96 128 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1.5u w=9.23u
SYMBOL res 128 0 R0
SYMATTR InstName Rd
SYMATTR Value 10k
SYMBOL voltage -32 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vgs
SYMATTR Value SINE(0 200m 1k)
FLAG -32 304 0
FLAG 144 272 0
FLAG 144 -144 0
FLAG 224 128 Vout
TEXT -240 -32 Left 2 !.include cmosedu_models.txt
TEXT -242 328 Left 2 !.dc Vgs 0 5 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\19cee9d94910_AD8602.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8602.asy)
Vin IN 0 SINE(0 1 100K)
XU1 IN N001 +V -V OUT AD8602 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10K
R2 OUT N001 10K
V1 +V 0 2.5
Rload OUT 0 10K
V2 -V 0 -2.5
.tran 100u
.lib AD8602.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 272 -944 256 -944
WIRE 368 -944 352 -944
WIRE 384 -944 368 -944
WIRE 480 -944 464 -944
WIRE 32 -832 32 -848
WIRE 144 -832 144 -848
WIRE 368 -832 368 -944
WIRE 384 -832 368 -832
WIRE 480 -816 480 -944
WIRE 480 -816 448 -816
WIRE 608 -816 480 -816
WIRE 384 -800 272 -800
WIRE 608 -800 608 -816
WIRE 272 -784 272 -800
WIRE 32 -736 32 -752
WIRE 144 -736 144 -752
WIRE 608 -704 608 -720
WIRE 272 -688 272 -704
SYMBOL res 592 -816 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL res 480 -960 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 272 -800 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL Opamps\\AD8602 416 -880 R0
SYMATTR InstName U1
SYMBOL voltage 144 -848 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 368 -960 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 32 -848 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
FLAG 32 -848 +V
FLAG 32 -736 0
FLAG 272 -688 0
FLAG 608 -816 OUT
FLAG 272 -800 IN
FLAG 416 -848 +V
FLAG 144 -848 -V
FLAG 416 -784 -V
FLAG 256 -944 0
FLAG 608 -704 0
FLAG 144 -736 0
TEXT 528 -608 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\29bd96a07291_CMOS_Potential_Divider.asc
* Generated by LTspice 26.0.1 for Windows.
V1 VDD 0 5V
M2 Vout Vout VDD VDD PMOS l=5 w=15
M1 Vout Vout 0 N001 NMOS l=5 w=15
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL NMOS NMOS(VT0=0.83 LAMBDA=0.06 KP=50U)
.MODEL PMOS PMOS(VT0=0.91 LAMBDA=0.06 KP=17U)
.tran 600N
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 -48 128 -64
WIRE 144 -48 128 -48
WIRE 144 16 144 -48
WIRE 144 16 128 16
WIRE 80 32 32 32
WIRE 144 64 144 16
WIRE 144 64 128 64
WIRE -176 80 -176 16
WIRE 32 128 32 32
WIRE 128 128 128 112
WIRE 128 128 32 128
WIRE 192 128 128 128
WIRE 128 160 128 128
WIRE 144 208 128 208
WIRE 32 240 32 128
WIRE 80 240 32 240
WIRE 144 240 144 208
WIRE 144 240 128 240
WIRE -176 288 -176 160
WIRE 128 336 128 256
IOPIN 192 128 Out
SYMBOL voltage -176 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL nmos4 80 160 R0
SYMATTR InstName M1
SYMATTR Value2 l=5 w=15
SYMBOL pmos4 80 112 M180
SYMATTR InstName M2
SYMATTR Value2 l=5 w=15
FLAG -176 288 0
FLAG -176 16 VDD
FLAG 128 -64 VDD
FLAG 192 128 Vout
FLAG 128 336 0
TEXT -264 -192 Left 2 !.MODEL NMOS NMOS(VT0=0.83 LAMBDA=0.06 KP=50U)\n.MODEL PMOS PMOS(VT0=0.91 LAMBDA=0.06 KP=17U)
TEXT -224 -112 Left 2 !.tran 600N
* Z:\home\khalils\Downloads\files\data\raw_asc\6091219c02e2_TS7_1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 0 V2 {R}
R2 V2 N001 {R}
C1 V2 V1 {C}
L1 N001 0 {L}
R1 N001 V1 {R}
V1 V1 0 AC 1
.param R=1 L=1 C=L/R**2
.ac dec 10k 1 1MEG
.net I(R3) V1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 160 0 48 0
WIRE 336 0 224 0
WIRE 48 112 48 0
WIRE 48 112 -16 112
WIRE 64 112 48 112
WIRE 192 112 144 112
WIRE 240 112 192 112
WIRE 336 112 336 0
WIRE 336 112 320 112
WIRE 400 112 336 112
WIRE -16 144 -16 112
WIRE 192 144 192 112
WIRE 400 160 400 112
WIRE 192 288 192 224
WIRE 400 288 400 240
WIRE 400 288 192 288
WIRE -16 304 -16 224
WIRE 400 304 400 288
SYMBOL res 160 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL voltage -16 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 416 256 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value {R}
SYMBOL ind 176 128 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMBOL res 336 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R}
SYMBOL cap 224 -16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value {C}
FLAG -16 304 0
FLAG 400 304 0
FLAG 400 112 V2
FLAG -16 112 V1
TEXT -40 336 Left 2 !.param R=1 L=1 C=L/R**2
TEXT -40 368 Left 2 !.ac dec 10k 1 1MEG
TEXT -40 400 Left 2 !.net I(R3) V1
* Z:\home\khalils\Downloads\files\data\raw_asc\1c9428612c7f_template1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP727.asy)
V1 N002 0 SINE(2 1 1KHz)
V2 VCC 0 5v
XU1 N002 N001 VCC 0 N001 OP727 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 1k
.tran 1ms
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 48 -48 48
WIRE 48 96 48 -16
WIRE -48 112 -48 48
WIRE 16 112 -48 112
WIRE 176 128 176 48
WIRE 176 128 80 128
WIRE 16 144 -304 144
WIRE 176 160 176 128
WIRE 48 240 48 160
WIRE -304 288 -304 224
WIRE 176 288 176 240
SYMBOL Opamps\\OP727 48 64 R0
SYMATTR InstName U1
SYMBOL res 160 144 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -304 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(2 1 1KHz)
SYMBOL voltage -304 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5v
FLAG 176 288 0
FLAG -304 288 0
FLAG 48 240 0
FLAG 48 -16 VCC
FLAG -304 -48 VCC
FLAG -304 32 0
TEXT -338 312 Left 2 !.tran 1ms
* Z:\home\khalils\Downloads\files\data\raw_asc\029325a2a4bc_ESP32VoltageSupervisor.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 PULSE(0 3.3 0 0.02 0.01 0.01 2)
R4 N001 N004 68K
R5 N003 N002 220K
Q1 N002 N004 0 0 BC182B
R3 N001 RESETN 15K
Q2 RESETN N003 0 0 BC182B
R1 N001 N002 100K
R2 N004 P001 3.3K
D1 P001 0 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 30m
.TEMP 0 20 40 60
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 992 680
WIRE 64 -64 -128 -64
WIRE 208 -64 64 -64
WIRE 704 -64 208 -64
WIRE 64 -32 64 -64
WIRE 208 -32 208 -64
WIRE 704 -32 704 -64
WIRE 64 -16 64 -32
WIRE -128 48 -128 -64
WIRE 832 48 704 48
WIRE 208 64 208 48
WIRE 416 64 208 64
WIRE 640 64 496 64
WIRE 640 96 640 64
WIRE 64 112 64 48
WIRE 144 112 64 112
WIRE 64 128 64 112
WIRE -128 256 -128 128
WIRE 208 272 208 160
WIRE 704 272 704 144
IOPIN 832 48 Out
SYMBOL res 512 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 220K
SYMBOL voltage -128 32 R0
WINDOW 3 -270 103 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 3.3 0 0.02 0.01 0.01 2)
SYMBOL diode 48 208 R0
WINDOW 0 42 26 Left 2
WINDOW 3 36 53 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 688 -48 R0
SYMATTR InstName R3
SYMATTR Value 15K
SYMBOL npn 144 64 R0
SYMATTR InstName Q1
SYMATTR Value BC182B
SYMBOL npn 640 48 R0
SYMATTR InstName Q2
SYMATTR Value BC182B
SYMBOL res 48 112 R0
SYMATTR InstName R2
SYMATTR Value 3.3K
SYMBOL res 48 -48 R0
SYMATTR InstName R4
SYMATTR Value 68K
SYMBOL res 192 -48 R0
SYMATTR InstName R1
SYMATTR Value 100K
FLAG -128 256 0
FLAG 208 272 0
FLAG 832 48 RESETN
FLAG 704 272 0
FLAG 64 272 0
TEXT -402 200 Left 2 !.tran 30m
TEXT -400 240 Left 2 !.TEMP 0 20 40 60
* Z:\home\khalils\Downloads\files\data\raw_asc\2a89b667dd08_single_edge.asc
* Generated by LTspice 26.0.1 for Windows.
* Free
* Clamp
V1 P001 0 5
V3 P002 0 5
R3 0 N003 1k
R8 IN- N004 10k
V4 N004 0 4.8
R7 N001 0 1.3k
R11 N002 N001 50k
R22 N004 N003 50k
R5 IN+ N003 10k
R6 P001 N001 800
V2 N002 0 4.8
R2 N002 IN+ 10k
R4 N001 IN- 10k
R1 N003 P002 1k
.tran 0.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 720
WIRE 0 80 -112 80
WIRE 176 80 0 80
WIRE 432 80 256 80
WIRE 528 80 528 -16
WIRE 528 80 432 80
WIRE 0 208 0 160
WIRE 256 208 0 208
WIRE 432 240 432 160
WIRE 432 240 0 240
WIRE 544 240 432 240
WIRE 256 304 256 208
WIRE 544 304 256 304
WIRE 256 352 256 304
WIRE 432 352 256 352
WIRE 0 384 0 240
WIRE 432 384 432 352
WIRE 0 464 -144 464
WIRE 176 464 0 464
WIRE 432 464 256 464
WIRE 528 464 432 464
WIRE 528 544 528 464
SYMBOL res -16 368 R0
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL res 416 64 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res -160 448 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -144 528 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res -128 -16 R0
SYMATTR InstName R6
SYMATTR Value 800
SYMBOL voltage 528 0 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 4.8
SYMBOL res -16 64 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res -128 64 R0
SYMATTR InstName R7
SYMATTR Value 1.3k
SYMBOL res -160 368 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 272 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R22
SYMATTR Value 50k
SYMBOL res 272 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 50k
SYMBOL res 416 368 R0
SYMATTR InstName R8
SYMATTR Value 10k
SYMBOL voltage 528 528 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 4.8
SYMBOL voltage -112 16 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 528 -96 0
FLAG 528 624 0
FLAG 544 240 IN+
FLAG 544 304 IN-
FLAG -112 -80 0
FLAG -144 624 0
FLAG -144 384 0
FLAG -112 160 0
TEXT 200 616 Left 2 ;Free
TEXT 184 -48 Left 2 ;Clamp
TEXT -328 272 Left 2 !.tran 0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\163ee040ee6d_Static_Transfer_Using_Triac_with_MOC3081__teste_parcial_.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU5 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Optos\PC817A.asy)
V1 P+ 0 PULSE(0 6 0 1m 1m 80m 120m)
R6 N002 P+ 270R
V2 A+ A- PULSE(0 6 20m 1m 1m 35m 50m)
XU5 N001 A- N002 0 PC817 Igain=1m ;pnba A)K)C)E
R3 N001 A+ 300R
.tran 200m startup
.lib Others\Q4012LH2.sub
.lib PC817.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1152 744
WIRE -160 -128 -160 -144
WIRE -160 -16 -160 -48
WIRE -144 -16 -160 -16
WIRE 96 -16 48 -16
WIRE 192 -16 176 -16
WIRE -144 80 -160 80
WIRE 64 80 48 80
WIRE 64 96 64 80
WIRE 112 96 64 96
WIRE 64 112 64 96
WIRE 112 112 112 96
IOPIN 192 -16 In
IOPIN -160 80 In
IOPIN -160 -144 In
IOPIN 64 112 In
IOPIN -496 64 In
IOPIN -496 144 In
IOPIN -496 240 In
IOPIN -496 320 In
SYMBOL Optos\\PC817A -48 32 R0
WINDOW 0 -79 77 Center 2
WINDOW 3 -1 78 Center 2
SYMATTR InstName U5
SYMBOL res -144 -32 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 300R
SYMBOL Misc\\battery -496 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 6 20m 1m 1m 35m 50m)
SYMBOL Misc\\battery -496 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 6 0 1m 1m 80m 120m)
SYMBOL res 80 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 270R
FLAG 192 -16 P+
FLAG -160 80 A-
FLAG -160 -144 A+
FLAG 64 112 P-
FLAG -496 64 P+
FLAG -496 144 P-
FLAG -496 240 A+
FLAG -496 320 A-
FLAG 112 112 0
TEXT -544 448 Left 2 !.tran 200m startup
TEXT -544 472 Left 2 !.lib Others\\Q4012LH2.sub