* Z:\home\khalils\Downloads\files\data\raw_asc\AD4080.asc
* Generated by LTspice 26.0.1 for Windows.
V4 Refin 0 {VREF}
C9 0 ADC_out 0.1p
C10 0 ADC_out_dsp 0.1p
V1 VOCM 0 1.5
V2 _DIS 0 3.3
R15 ADC_IN+ FDA_OUT_P 25
R16 ADC_IN- FDA_OUT_N 25
R17 AUXIN+ FDA_OUT_P 100
R18 AUXIN- FDA_OUT_N 100
C15 ADC_IN+ ADC_IN- 39p
C16 AUXIN+ AUXIN- 10p
V_FS1 N006 0 {fs}
V_SEL1 N008 0 {sel}
V_DEC1 N007 0 {decimation}
V6 VS+ 0 5
V7 VS- 0 -5
V14 VDD33 0 3.3
V15 CNV 0 PULSE(0 1.1 {ACQ_delay} 0.2n 0.2n {0.9*(1/fs)} {1/fs})
XU2 N002 FDA_IN+ FDA_IN- N004 VS+ VS- FDA_OUT_N FDA_OUT_P _DIS VOCM VREF 0 0 ADA4945-HP ;pnba 1)2)3)4)5)6)7)8)9)10)11)12)13
R5 N001 N002 {RF}
R6 N005 N004 {RF}
C11 FDA_IN+ N002 {CFilt_2}
C12 FDA_IN- N004 {CFilt_2}
R7 N001 Vin_p {RG}
R8 N005 Vin_n {RG}
C13 N001 0 {CFilt_1}
C14 0 N005 {CFilt_1}
R19 N001 FDA_IN+ {RMFB}
R20 N005 FDA_IN- {RMFB}
Vin_n N003 Vin_n SINE(0 {input_Vpp/4} {input_freq}) AC 0.5 0
Vin_cm N003 0 {input_cm} AC 0
Vin_p Vin_p N003 SINE(0 {input_Vpp/4} {input_freq}) AC 0.5 0
XU1 0 VDD33 Refin ADC_IN+ ADC_IN- AUXIN+ AUXIN- CNV ADC_out ADC_out_dsp N007 N008 N006 ADC_out AD4080 ;pnba GND)Vdd)REFIN)IN+)IN-)AUXIN+)AUXIN-)CNV)Vout)DSPOUT)DEC)SEL)FS)DSPIN
.param VREF=3
* External voltage reference
* .tran 5u
* .noise V(ADC_out_dsp) Vin_p dec 100 10 1G
.meas NOISE output_noise_rms INTEG V(onoise) FROM 10 TO {Fmax_noise_integration}
.meas NOISE full_scale_sine_rms PARAM 2*VREF/(2*sqrt(2))
.meas NOISE dynamic_range PARAM 20*log10(full_scale_sine_rms/output_noise_rms)
.param Fmax_noise_integration = 1G
.meas NOISE ENOB PARAM (dynamic_range - 1.76)/6.02
* Fully differential ADC driver
* ADC Kickback Filter
* Set to ~80 MHz BW to allow\ndriver to settle ADC kickback.
* .ac dec 1000 1k 1G
.noise V(ADC_out) Vin_p dec 100 10 1G
* AD4080 Digital Filtering Configuration
* ADC output pre-digital filtering
* ADC output post digital filtering (AC and NOISE simulations only)
* SEL input:\n The voltage applied at this input selects the\n digital filter type.\n 0V = No Filter \n 1V = Sinc1 \n 2V = Sinc5\n 3V = Sinc5 + Comp
* DEC input:\n The voltage applied at this pin sets\n the N value for decimation.\n For Sinc1 and Sinc5 Filters Decimation = N\n For Sinc5 +Comp Decimation = (N * 2)\n 2 = N = 2 \n 4 = N = 4 \n 8 = N = 8\n 16 =........\n ...............\n 256 = N = 256 (Max Setting for Sinc5 and Sinc5 + Comp)\n 512 = N = 512 (Sinc1 Only)\n 1024 = N = 1024 (Sinc1 Only)
* Multi-feedback topology, low-pass, second-order
* --> AD4080 digital filter output (ADC_out_dsp)\n does not support transient simulations
* Other signals
* Simulation commands
* Measurements
* Supplies
* AUX input filter
* FS input:\n A voltage equal to the sampling frequency in Hertz\n must be supplied at this input.
* Results can be found in the "SPICE Output Log" (View->"Spice Output Log" or Ctrl+L").
* 3dB bandwidth (AC analysis)
* Noise parameters: dynamic range and ENOB (NOISE analysis)
* --> Noise simulation with output BEFORE digital filtering (ADC_out)
* --> Noise simulation with output AFTER digital filtering (ADC_out_DSP)
.param decimation 4
* Input signal
.meas AC ADC_out_max MAX MAG(V(ADC_out))
.meas AC bw_3db FIND frequency WHEN mag(V(ADC_out))=(ADC_out_max/sqrt(2))
.param sel 3
* The default configuration (sel=3, decimation=4, fs=40MHz) results in a \nSinc5 + Compensation filter with a 3dB bandwidth of ~2MHz.
* --> SNR
* AD4080 must be used with an external 3V reference.\nThis parameter is used in the Dynamic Range calculations.
.param input_Vpp=2.966
.param input_freq = 500k
.param input_cm = 0
.param fs = 40MEG
.param ACQ_delay = 10n
* --> ADC Sampling rate. For AD4080 min is 1.25 Msps, max 40 Msps
* --> Delay from simulation start to first sampling pulse
* Convert signal
.param AFE_gain = 1 ;--> AFE gain = Rf/Rg
.param RF = 499
.param RMFB = 499
.param RG = {RF/AFE_gain}
.param CFilt_1=150p
.param CFilt_2=56p
* Default settings:\n Gain = 1\n 3dB BW = ~2.5 MHz.
* Datasheet recommended values
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4080.asy)
.lib AD4080.sub
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4945-HP.asy)
.lib ADA4945-HP.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 12976 5604
WIRE 4848 3392 4832 3392
WIRE 5120 3392 5104 3392
WIRE 4064 3408 4048 3408
WIRE 4288 3408 4272 3408
WIRE 4496 3408 4480 3408
WIRE 4832 3440 4832 3392
WIRE 5104 3440 5104 3392
WIRE 4048 3456 4048 3408
WIRE 4272 3456 4272 3408
WIRE 4480 3456 4480 3408
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WIRE 5104 3552 5104 3520
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WIRE 4272 3568 4272 3536
WIRE 4480 3568 4480 3536
WIRE 5664 3904 5584 3904
WIRE 5744 3904 5664 3904
WIRE 5168 3936 5072 3936
WIRE 5744 3936 5744 3904
WIRE 5168 3952 5168 3936
WIRE 3152 4016 2992 4016
WIRE 3392 4016 3232 4016
WIRE 5168 4048 5168 4032
WIRE 5744 4048 5744 4016
WIRE 3280 4112 3152 4112
WIRE 3392 4112 3392 4016
WIRE 3392 4112 3344 4112
WIRE 5072 4192 5072 3936
WIRE 5424 4208 5408 4208
WIRE 2144 4240 2096 4240
WIRE 2752 4240 2144 4240
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WIRE 4816 4368 4816 4352
WIRE 3392 4384 3392 4112
WIRE 3408 4384 3392 4384
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WIRE 4144 4384 4144 4352
WIRE 2096 4400 2096 4352
WIRE 2096 4400 1888 4400
WIRE 2912 4400 2912 4352
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WIRE 3280 4416 3152 4416
WIRE 3408 4416 3280 4416
WIRE 1888 4432 1888 4400
WIRE 2096 4432 2096 4400
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WIRE 5648 4432 5648 4272
WIRE 5648 4432 5408 4432
WIRE 2912 4448 2912 4400
WIRE 3408 4448 3392 4448
WIRE 3408 4480 3360 4480
WIRE 3584 4480 3584 4448
WIRE 3696 4480 3584 4480
WIRE 3824 4480 3872 4352
WIRE 3824 4480 3696 4480
WIRE 3872 4480 3824 4352
WIRE 3904 4480 3872 4480
WIRE 4000 4480 3904 4480
WIRE 4144 4480 4144 4448
WIRE 4144 4480 4080 4480
WIRE 4752 4480 4144 4480
WIRE 4816 4480 4816 4400
WIRE 4816 4480 4752 4480
WIRE 5408 4480 5408 4432
WIRE 5408 4480 5376 4480
WIRE 5744 4512 5376 4512
WIRE 5824 4512 5744 4512
WIRE 3360 4528 3360 4480
WIRE 3520 4528 3520 4512
WIRE 5744 4544 5744 4512
WIRE 1888 4560 1888 4512
WIRE 2096 4560 2096 4512
WIRE 2144 4560 2096 4560
WIRE 2752 4560 2144 4560
WIRE 2912 4560 2912 4512
WIRE 2912 4560 2832 4560
WIRE 2992 4560 2912 4560
WIRE 3040 4560 2992 4560
WIRE 3152 4560 3152 4416
WIRE 3152 4560 3120 4560
WIRE 4976 4560 4976 4528
WIRE 3488 4576 3488 4512
WIRE 3504 4576 3488 4576
WIRE 3904 4576 3904 4480
WIRE 4464 4576 3904 4576
WIRE 4576 4576 4576 4464
WIRE 4576 4576 4544 4576
WIRE 4752 4576 4576 4576
WIRE 4848 4576 4848 4432
WIRE 4848 4576 4752 4576
WIRE 3456 4608 3456 4512
WIRE 3504 4608 3456 4608
WIRE 5744 4640 5744 4608
WIRE 3152 4688 3152 4560
WIRE 3280 4688 3152 4688
WIRE 3392 4688 3392 4448
WIRE 3392 4688 3344 4688
WIRE 2992 4768 2992 4560
WIRE 3168 4768 2992 4768
WIRE 3392 4768 3392 4688
WIRE 3392 4768 3248 4768
WIRE 5072 4800 5072 4528
WIRE 5072 4800 4976 4800
WIRE 5200 4800 5200 4528
WIRE 5296 4800 5200 4800
WIRE 4976 4848 4976 4800
WIRE 5136 4848 5136 4528
WIRE 5296 4848 5296 4800
WIRE 4976 4944 4976 4928
WIRE 5136 4944 5136 4928
WIRE 5296 4944 5296 4928
FLAG 5168 4048 0
FLAG 4976 4560 0
FLAG 5744 4400 0
FLAG 5744 4640 0
FLAG 5840 4272 ADC_out
FLAG 5824 4512 ADC_out_dsp
FLAG 4832 3552 0
FLAG 4848 3392 VOCM
FLAG 5104 3552 0
FLAG 5120 3392 _DIS
FLAG 4752 4256 AUXIN+
FLAG 4752 4352 ADC_IN+
FLAG 4752 4480 ADC_IN-
FLAG 4752 4576 AUXIN-
FLAG 4976 4944 0
FLAG 5136 4944 0
FLAG 5296 4944 0
FLAG 4048 3568 0
FLAG 4272 3568 0
FLAG 4064 3408 VS+
FLAG 4288 3408 VS-
FLAG 4480 3568 0
FLAG 4496 3408 VDD33
FLAG 5744 4048 0
FLAG 5664 3904 CNV
FLAG 5424 4208 VDD33
FLAG 5072 4192 Refin
FLAG 3536 4272 VOCM
FLAG 3536 4240 VS+
FLAG 3504 4608 VS-
FLAG 3360 4528 0
FLAG 3504 4576 _DIS
FLAG 3280 4352 FDA_IN+
FLAG 3280 4416 FDA_IN-
FLAG 3520 4528 0
FLAG 3536 4304 VREF
FLAG 3696 4352 FDA_OUT_N
FLAG 3696 4480 FDA_OUT_P
FLAG 1888 4560 0
FLAG 2144 4240 Vin_p
FLAG 2144 4560 Vin_n
FLAG 2864 4416 0
SYMBOL voltage 5168 3936 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value {VREF}
SYMBOL cap 5728 4368 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C9
SYMATTR Value 0.1p
SYMBOL cap 5728 4608 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C10
SYMATTR Value 0.1p
SYMBOL voltage 4832 3424 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL voltage 5104 3424 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 4096 4336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R15
SYMATTR Value 25
SYMBOL res 4096 4464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R16
SYMATTR Value 25
SYMBOL res 4560 4240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R17
SYMATTR Value 100
SYMBOL res 4560 4560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R18
SYMATTR Value 100
SYMBOL cap 4128 4384 R0
SYMATTR InstName C15
SYMATTR Value 39p
SYMBOL cap 4560 4400 R0
SYMATTR InstName C16
SYMATTR Value 10p
SYMBOL voltage 4976 4832 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -86 14 Left 2
WINDOW 3 -80 45 Left 2
SYMATTR InstName V_FS1
SYMATTR Value {fs}
SYMBOL voltage 5136 4832 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -102 15 Left 2
WINDOW 3 -96 50 Left 2
SYMATTR InstName V_SEL1
SYMATTR Value {sel}
SYMBOL voltage 5296 4832 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -102 20 Left 2
WINDOW 3 -198 51 Left 2
SYMATTR InstName V_DEC1
SYMATTR Value {decimation}
SYMBOL voltage 4048 3440 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 5
SYMBOL voltage 4272 3440 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value -5
SYMBOL voltage 4480 3440 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V14
SYMATTR Value 3.3
SYMBOL voltage 5744 3920 R0
WINDOW 123 0 0 Left 0
WINDOW 39 36 120 Left 2
WINDOW 3 13 96 Left 2
SYMATTR Value PULSE(0 1.1 {ACQ_delay} 0.2n 0.2n {0.9*(1/fs)} {1/fs})
SYMATTR InstName V15
SYMBOL OpAmps\\ADA4945-HP 3456 4416 R0
WINDOW 3 73 92 Left 2
SYMATTR InstName U2
SYMBOL res 3136 4032 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value {RF}
SYMBOL res 3152 4784 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value {RF}
SYMBOL cap 3280 4128 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value {CFilt_2}
SYMATTR InstName C11
SYMBOL cap 3280 4704 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value {CFilt_2}
SYMATTR InstName C12
SYMBOL res 2848 4224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value {RG}
SYMBOL res 2848 4544 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value {RG}
SYMBOL cap 2896 4288 R0
WINDOW 3 18 56 Left 2
WINDOW 0 32 13 Left 2
SYMATTR Value {CFilt_1}
SYMATTR InstName C13
SYMBOL cap 2896 4448 R0
WINDOW 3 17 49 Left 2
WINDOW 0 32 11 Left 2
SYMATTR Value {CFilt_1}
SYMATTR InstName C14
SYMBOL res 3024 4256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R19
SYMATTR Value {RMFB}
SYMBOL res 3024 4576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R20
SYMATTR Value {RMFB}
SYMBOL voltage 2096 4416 R0
WINDOW 123 47 66 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 15 95 Left 2
WINDOW 0 48 37 Left 2
SYMATTR Value2 AC 0.5 0
SYMATTR Value SINE(0 {input_Vpp/4} {input_freq})
SYMATTR InstName Vin_n
SYMBOL voltage 1888 4416 R0
WINDOW 123 41 74 Left 2
WINDOW 39 0 0 Left 0
WINDOW 0 42 49 Left 2
WINDOW 3 30 98 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName Vin_cm
SYMATTR Value {input_cm}
SYMBOL voltage 2096 4256 R0
WINDOW 123 42 70 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 15 95 Left 2
WINDOW 0 43 45 Left 2
SYMATTR Value2 AC 0.5 0
SYMATTR Value SINE(0 {input_Vpp/4} {input_freq})
SYMATTR InstName Vin_p
SYMBOL ADC\\AD4080 5072 4384 R0
SYMATTR InstName U1
TEXT 4800 3912 Left 2 !.param VREF=3
TEXT 4768 3768 Left 4 ;External voltage reference
TEXT 1840 3320 Left 2 ;.tran 5u
TEXT 1840 3440 Left 2 ;.noise V(ADC_out_dsp) Vin_p dec 100 10 1G
TEXT 1864 5208 Left 2 !.meas NOISE output_noise_rms INTEG V(onoise) FROM 10 TO {Fmax_noise_integration}
TEXT 1864 5248 Left 2 !.meas NOISE full_scale_sine_rms PARAM 2*VREF/(2*sqrt(2))
TEXT 1864 5288 Left 2 !.meas NOISE dynamic_range PARAM 20*log10(full_scale_sine_rms/output_noise_rms)
TEXT 1864 5168 Left 2 !.param Fmax_noise_integration = 1G
TEXT 1864 5328 Left 2 !.meas NOISE ENOB PARAM (dynamic_range - 1.76)/6.02
TEXT 2600 3576 Left 4 ;Fully differential ADC driver
TEXT 3920 3944 Left 4 ;ADC Kickback Filter
TEXT 3944 3992 Left 2 ;Set to ~80 MHz BW to allow\ndriver to settle ADC kickback.
TEXT 1840 3360 Left 2 ;.ac dec 1000 1k 1G
TEXT 1840 3400 Left 2 !.noise V(ADC_out) Vin_p dec 100 10 1G
TEXT 4176 4744 Left 4 ;AD4080 Digital Filtering Configuration
TEXT 5664 4232 Left 4 ;ADC output pre-digital filtering
TEXT 5656 4472 Left 4 ;ADC output post digital filtering (AC and NOISE simulations only)
TEXT 4224 4912 Left 2 ;SEL input:\n  The voltage applied at this input selects the\n  digital filter type.\n    0V = No Filter \n    1V = Sinc1 \n    2V = Sinc5\n    3V = Sinc5 + Comp
TEXT 4224 5144 Left 2 ;DEC input:\n  The voltage applied at this pin sets\n  the N value for decimation.\n  For Sinc1 and Sinc5 Filters Decimation = N\n  For Sinc5 +Comp Decimation = (N * 2)\n  2 = N = 2 \n  4 = N = 4 \n  8 = N = 8\n  16 =........\n  ...............\n  256 =   N = 256 (Max Setting for Sinc5 and Sinc5 + Comp)\n  512 =   N = 512 (Sinc1 Only)\n  1024 = N = 1024 (Sinc1 Only)
TEXT 2600 3624 Left 3 ;Multi-feedback topology, low-pass, second-order
TEXT 2408 3320 Left 2 ;--> AD4080 digital filter output (ADC_out_dsp)\n     does not support transient simulations
TEXT 4784 3328 Left 2 ;Other signals
TEXT 1808 3264 Left 2 ;Simulation commands
TEXT 1824 4912 Left 2 ;Measurements
TEXT 3984 3328 Left 2 ;Supplies
TEXT 4392 4112 Left 3 ;AUX input filter
TEXT 4224 4800 Left 2 ;FS input:\n  A voltage equal to the sampling frequency in Hertz\n  must be supplied at this input.
TEXT 1848 4960 Left 2 ;Results can be found in the "SPICE Output Log" (View->"Spice Output Log" or Ctrl+L").
TEXT 1848 5016 Left 2 ;3dB bandwidth (AC analysis)
TEXT 1840 5128 Left 2 ;Noise parameters: dynamic range and ENOB (NOISE analysis)
TEXT 2408 3400 Left 2 ;--> Noise simulation with output BEFORE digital filtering (ADC_out)
TEXT 2408 3440 Left 2 ;--> Noise simulation with output AFTER digital filtering (ADC_out_DSP)
TEXT 4920 5128 Left 2 !.param decimation 4
TEXT 1832 3896 Left 4 ;Input signal
TEXT 1864 5048 Left 2 !.meas AC ADC_out_max MAX MAG(V(ADC_out))
TEXT 1864 5080 Left 2 !.meas AC bw_3db FIND frequency WHEN mag(V(ADC_out))=(ADC_out_max/sqrt(2))
TEXT 4920 5096 Left 2 !.param sel 3
TEXT 4920 5032 Left 2 ;The default configuration (sel=3, decimation=4, fs=40MHz) results in a \nSinc5 + Compensation filter with a 3dB bandwidth of ~2MHz.
TEXT 2976 5288 Left 2 ;--> SNR
TEXT 4792 3848 Left 2 ;AD4080 must be used with an external 3V reference.\nThis parameter is used in the Dynamic Range calculations.
TEXT 1856 3952 Left 2 !.param input_Vpp=2.966\n.param input_freq = 500k\n.param input_cm = 0
TEXT 5760 4080 Left 2 !.param fs = 40MEG\n.param ACQ_delay = 10n
TEXT 6096 4072 Left 2 ;--> ADC Sampling rate. For AD4080 min is 1.25 Msps, max 40 Msps
TEXT 6096 4104 Left 2 ;--> Delay from simulation start to first sampling pulse
TEXT 5544 3768 Left 4 ;Convert signal
TEXT 2648 3784 Left 2 !.param AFE_gain = 1 ;--> AFE gain = Rf/Rg\n.param RF = 499\n.param RMFB = 499\n.param RG = {RF/AFE_gain}\n.param CFilt_1=150p\n.param CFilt_2=56p
TEXT 2648 3664 Left 2 ;Default settings:\n  Gain = 1\n  3dB BW = ~2.5 MHz.
TEXT 4344 4144 Left 2 ;Datasheet recommended values
LINE Normal 5904 4560 5904 4560 2
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RECTANGLE Normal 4688 4640 4320 4128 2
RECTANGLE Normal 6880 4144 5552 3792 2
RECTANGLE Normal 3808 4816 2592 3600 2
RECTANGLE Normal 5792 5504 4176 4768 2
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