* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5014_chan3_4.asc
* Generated by LTspice 26.0.1 for Windows.
* This model simulates two channels of ADP5014\nFeatures configured by the CFG1 and CFG2 pins are controlled\nby features of the IC found by Ctrl right click.\n--CL is current limit and and can be set to 6.9 for 4 A,\n or 3.5 for 2 A. It is also a good to simulate startup using the minimum values\n --Paralllel should be set to 1 if using channels in parallel, else 0\n--Timer should be set to 1 or 8 depending on the length hiccup required\n--PSM should be 0 for forced PWM and 1 for PSM (low power pulse\n skip mode) enabled\n--Outputs of the GPIO pin are pinned out seperately for your convenience\n--Enable mode is always manual mode\n--See the datasheet to configure channels for parallelt operation
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5014_chan3_4.asy)
L2 N006 OUT2 2.2 Rser=20m
V1 IN 0 5
C3 N008 N009 22n
Rload2 OUT2 0 3.3
Rload1 OUT1 0 5
R4 OUT2 N007 16.9K
C5 OUT2 0 22
C1 OUT1 0 22
R6 N010 0 165K
R7 N009 0 255
L1 N001 OUT1 2.2 Rser=47m
XU1 N010 NC_01 N003 IN N001 N002 N004 IN N003 0 0 IN NC_02 NC_03 NC_04 NC_05 N006 N008 N007 IN IN N003 ADP5014 RP=95m RN=73m CS=0.12 CL1=3.5 CL2=3.5 PSM=0 timer=1 parallel=0 ;pnba Rt)SYNC)Vset1)PVin1)SW1)FB1)Comp1)EN1)Vref)PGND1)PGND2)AVin)CLKout)PWRGD)UV)UVO)SW2)Comp2)FB2)EN2)PVin2)Vset2
R3 N005 0 309
R2 N002 0 34K
C6 OUT1 N002 82p
C2 N004 N005 12n
C4 N003 0 100n
R1 OUT1 N002 22.1K
R5 N007 0 64.9K
.tran 500u startup
.softstart .2 ; This option reduces the internal softstart time by 5x.
.lib ADP5014.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1944 952
WIRE -144 -320 -320 -320
WIRE -96 -320 -144 -320
WIRE 272 -320 224 -320
WIRE 432 -320 352 -320
WIRE 528 -320 432 -320
WIRE 656 -320 528 -320
WIRE 784 -320 656 -320
WIRE -320 -304 -320 -320
WIRE 432 -304 432 -320
WIRE 784 -304 784 -320
WIRE 528 -240 528 -320
WIRE 656 -240 656 -320
WIRE -320 -208 -320 -224
WIRE -144 -208 -144 -320
WIRE -96 -208 -144 -208
WIRE 432 -208 432 -240
WIRE 432 -208 224 -208
WIRE 784 -208 784 -224
WIRE 432 -192 432 -208
WIRE -144 -96 -144 -208
WIRE -96 -96 -144 -96
WIRE 528 -96 528 -160
WIRE 528 -96 224 -96
WIRE 656 -96 656 -176
WIRE 656 -96 528 -96
WIRE 528 -80 528 -96
WIRE -96 16 -160 16
WIRE 240 16 224 16
WIRE 320 16 304 16
WIRE 416 16 400 16
WIRE 528 16 528 0
WIRE -144 128 -144 -96
WIRE -96 128 -144 128
WIRE 272 128 224 128
WIRE 432 128 352 128
WIRE 512 128 432 128
WIRE 784 128 512 128
WIRE 432 144 432 128
WIRE 784 144 784 128
WIRE 512 208 512 128
WIRE -144 240 -144 128
WIRE -96 240 -144 240
WIRE 432 240 432 208
WIRE 432 240 224 240
WIRE 784 240 784 224
WIRE 432 256 432 240
WIRE -160 352 -160 16
WIRE -96 352 -160 352
WIRE 512 352 512 288
WIRE 512 352 224 352
WIRE 512 368 512 352
WIRE -256 464 -272 464
WIRE -160 464 -160 352
WIRE -160 464 -192 464
WIRE -96 464 -160 464
WIRE 240 464 224 464
WIRE 320 464 304 464
WIRE 416 464 400 464
WIRE 512 464 512 448
WIRE -208 576 -240 576
WIRE -96 576 -128 576
SYMBOL cap 640 -240 R0
SYMATTR InstName C6
SYMATTR Value 82p
SYMBOL res 496 192 R0
SYMATTR InstName R4
SYMATTR Value 16.9K
SYMBOL res -112 560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 165K
SYMBOL VOLTAGE -320 -320 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 768 -320 R0
SYMATTR InstName Rload1
SYMATTR Value 5
SYMBOL res 304 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 309
SYMBOL res 304 480 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R7
SYMATTR Value 255
SYMBOL cap 416 -304 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL cap 240 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 22n
SYMBOL cap 416 144 R0
SYMATTR InstName C5
SYMATTR Value 22
SYMBOL ind 256 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -23 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=20m
SYMBOL cap -192 480 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL res 768 128 R0
SYMATTR InstName Rload2
SYMATTR Value 3.3
SYMBOL PowerProducts\\ADP5014_chan3_4 64 240 R0
SYMATTR InstName U1
SYMBOL res 512 -256 R0
SYMATTR InstName R1
SYMATTR Value 22.1K
SYMBOL ind 256 -304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -23 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=47m
SYMBOL cap 240 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 12n
SYMBOL res 496 352 R0
SYMATTR InstName R5
SYMATTR Value 64.9K
SYMBOL res 512 -96 R0
SYMATTR InstName R2
SYMATTR Value 34K
FLAG 416 16 0
FLAG -240 576 0
FLAG -272 464 0
FLAG 432 -192 0
FLAG 784 -320 OUT1
FLAG -320 -208 0
FLAG -320 -320 IN
FLAG 784 -208 0
FLAG 416 464 0
FLAG 432 256 0
FLAG 784 128 OUT2
FLAG 784 240 0
FLAG 528 16 0
FLAG 512 464 0
TEXT 480 824 Left 2 !.tran 500u startup\n.softstart .2 ; This option reduces the internal softstart time by 5x.
TEXT -1376 200 Left 2 ;This model simulates two channels of ADP5014\nFeatures configured by the CFG1 and CFG2 pins are controlled\nby features of the IC found by Ctrl right click.\n--CL is current limit and and can be set to 6.9 for 4 A,\n  or 3.5 for  2 A.  It is also a good to simulate startup using the minimum values\n --Paralllel should be set to 1 if using channels in parallel, else 0\n--Timer should be set to 1 or 8 depending on the length hiccup required\n--PSM should be 0 for forced PWM and 1 for PSM (low power pulse\n   skip mode) enabled\n--Outputs of the GPIO pin are pinned out seperately for your convenience\n--Enable mode is always manual mode\n--See the datasheet to configure channels for parallelt operation