Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\5dda1df7eb42_OB_npn_amp.asc
* Generated by LTspice 26.0.1 for Windows.
R5 load 0 10k
R1 N001 out 5k
R4 emiter 0 15k
V2 in 0 SINE(2 2 10k 0.0002 1000 0 30) AC 2 0
R6 emiter in 1k
C3 load out 10n
C1 base 0 100n
V1 N001 0 12
Q1 out base emiter 0 BC847B
R2 N001 base 1Meg
R3 base 0 1.5Meg
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.ac lin 100 100 20k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 -48 -80 -48
WIRE 256 -48 32 -48
WIRE -80 -32 -80 -48
WIRE 256 -32 256 -48
WIRE 32 32 32 -48
WIRE -80 64 -80 48
WIRE 256 80 256 48
WIRE 352 80 256 80
WIRE 384 80 352 80
WIRE 544 80 448 80
WIRE 256 112 256 80
WIRE -128 160 -144 160
WIRE 32 160 32 112
WIRE 32 160 -64 160
WIRE 128 160 32 160
WIRE 192 160 128 160
WIRE 544 160 544 80
WIRE 32 208 32 160
WIRE 256 256 256 208
WIRE 256 256 144 256
WIRE 544 256 544 240
WIRE 32 304 32 288
WIRE 256 304 256 256
WIRE -64 368 -192 368
WIRE 96 368 16 368
WIRE 144 368 144 256
WIRE 144 368 96 368
WIRE -192 400 -192 368
WIRE 256 400 256 384
WIRE -192 496 -192 480
SYMBOL res 240 288 R0
SYMATTR InstName R4
SYMATTR Value 15k
SYMBOL res 16 16 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL npn 192 112 R0
SYMATTR InstName Q1
SYMATTR Value BC847B
SYMBOL cap 448 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL voltage -80 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap -64 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL res 16 192 R0
SYMATTR InstName R3
SYMATTR Value 1.5Meg
SYMBOL res 528 144 R0
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL voltage -192 384 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 124 Left 2
SYMATTR Value2 AC 2 0
SYMATTR InstName V2
SYMATTR Value SINE(2 2 10k 0.0002 1000 0 30)
SYMBOL res 240 -48 R0
SYMATTR InstName R1
SYMATTR Value 5k
SYMBOL res 32 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 1k
FLAG -144 160 0
FLAG 32 304 0
FLAG 256 400 0
FLAG 544 256 0
FLAG -80 64 0
FLAG -192 496 0
FLAG 352 80 out
FLAG -192 368 in
FLAG 128 160 base
FLAG 544 80 load
FLAG 96 368 emiter
TEXT -224 520 Left 2 !.ac lin 100 100 20k
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4075-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4075-2.asy)
XU1 IN N001 V+ V- OUT ADA4075-2 ;pnba In+)In-)V+)V-)OUT
R2 OUT N001 10K
Rload OUT 0 10K
V2 V- 0 -15
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
V1 V+ 0 15
.tran 0.1m
.lib ADA4075-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 592 -1152 576 -1152
WIRE 144 -1136 128 -1136
WIRE 256 -1136 240 -1136
WIRE 576 -1136 576 -1152
WIRE 128 -1120 128 -1136
WIRE 240 -1120 240 -1136
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 576 -1056 576 -1072
WIRE 592 -1056 576 -1056
WIRE 128 -1024 128 -1040
WIRE 240 -1024 240 -1040
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 240 -1136 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL ADA4075-2 576 -1168 R0
WINDOW 0 26 47 Left 2
WINDOW 3 24 86 Left 2
SYMATTR InstName U1
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 128 -1136 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
FLAG 128 -1136 V+
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 592 -1152 V+
FLAG 240 -1136 V-
FLAG 592 -1056 V-
FLAG 416 -1216 0
FLAG 768 -992 0
FLAG 240 -1024 0
FLAG 128 -1024 0
TEXT 784 -896 Left 2 !.tran 0.1m
* Z:\home\khalils\Downloads\files\data\raw_asc\2036df799a04_1634-1.25.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1634-1.25.asy)
V1 N001 0 3
R1 N001 N002 150K
XU1 N002 0 LT1634-1.25 ;pnba VCC)VEE
.dc temp -40 80 .1
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 144 48 144
WIRE 272 144 208 144
WIRE 48 160 48 144
WIRE 272 176 272 144
WIRE 48 256 48 240
WIRE 272 256 272 240
SYMBOL res 112 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 150K
SYMBOL voltage 48 144 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL References\\LT1634-1.25 272 208 R0
SYMATTR InstName U1
FLAG 272 256 0
FLAG 48 256 0
TEXT 72 312 Left 2 !.dc temp -40 80 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\2e19ad06ee12_Flicker1.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 5
V1 N002 0 1.8 AC 1
R3 N001 OUT 6k
R6 N003 N002 6k noiseless
M1 OUT N003 0 0 NMOS1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.NOISE V(out) V1 oct 10 10 100K
* Shows how to make a resistor noiseless.
* Flicker Noise\n---------------------\nHelmut Sennewald\n \nThis example schematic shows how to get the flicker noise.\n \n1. Run the simulation with and without the NMOS noise \nparameter for flicker noise.\n \n2. Plot the difference in V(onoise) to get the flicker noise.\n@1 is the first run. @2 is the second run.\nPlot the following expression: \nsqrt(V(onoise)@2*V(onoise)@2-V(onoise)@1*V(onoise)@1)
.model NMOS1 NMOS(Vto=1 Kp=1m Kf={KF1} Af=1)
.op
.step param KF1 list 0 1e-25
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3088 1688
WIRE 1568 1136 1568 1104
WIRE 1568 1248 1568 1216
WIRE 1664 1104 1568 1104
WIRE 1760 832 1760 816
WIRE 1760 928 1760 912
WIRE 1952 1104 1744 1104
WIRE 2000 816 1760 816
WIRE 2000 832 2000 816
WIRE 2000 1008 2000 912
WIRE 2000 1024 2000 1008
WIRE 2000 1312 2000 1120
WIRE 2240 1008 2000 1008
FLAG 1760 928 0
FLAG 1568 1248 0
FLAG 2240 1008 OUT
FLAG 2000 1312 0
SYMBOL voltage 1760 816 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 1568 1120 R0
WINDOW 3 37 57 Left 0
WINDOW 123 24 104 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 1.8
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL res 1984 816 R0
SYMATTR InstName R3
SYMATTR Value 6k
SYMBOL res 1760 1088 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
WINDOW 123 60 56 VTop 0
SYMATTR InstName R6
SYMATTR Value 6k
SYMATTR Value2 noiseless
SYMBOL nmos 1952 1024 R0
SYMATTR InstName M1
SYMATTR Value NMOS1
TEXT 1464 720 Left 0 !.NOISE V(out) V1 oct 10 10 100K
TEXT 1464 1016 Left 0 ;Shows how to make a resistor noiseless.
TEXT 1472 264 Left 0 ;Flicker Noise\n---------------------\nHelmut Sennewald\n \nThis example schematic shows how to get the flicker noise.\n \n1. Run the simulation with and without the NMOS noise \nparameter for flicker noise.\n \n2. Plot the difference in V(onoise) to get the flicker noise.\n@1 is the first run. @2 is the second run.\nPlot the following expression: \nsqrt(V(onoise)@2*V(onoise)@2-V(onoise)@1*V(onoise)@1)
TEXT 1464 760 Left 0 !.model NMOS1 NMOS(Vto=1 Kp=1m Kf={KF1} Af=1)
TEXT 1464 680 Left 0 !.op
TEXT 1464 640 Left 0 !.step param KF1 list 0 1e-25
LINE Normal 1785 1046 1504 1046
LINE Normal 1785 1316 1785 1046
LINE Normal 1785 1316 1504 1316
LINE Normal 1504 1316 1504 1046
* Z:\home\khalils\Downloads\files\data\raw_asc\28e09038af56_meros_1o__e_.asc
* Generated by LTspice 26.0.1 for Windows.
Q4 vout N001 0 0 2N3904
Q5 N001 N001 0 0 2N3904
I2 vdd N001 1m
V1 vdd 0 10
V2 vout 0 AC 1
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc dec V2 1 9 0.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 992 680
WIRE 96 64 96 32
WIRE 752 144 752 48
WIRE 912 144 912 48
WIRE 96 208 96 144
WIRE 192 208 96 208
WIRE 96 240 96 208
WIRE 320 240 320 32
WIRE 192 288 192 208
WIRE 192 288 160 288
WIRE 256 288 192 288
WIRE 752 384 752 224
WIRE 912 384 912 224
WIRE 96 432 96 336
WIRE 320 432 320 336
FLAG 752 384 0
FLAG 912 384 0
FLAG 320 432 0
FLAG 96 432 0
FLAG 96 32 vdd
FLAG 752 48 vdd
FLAG 320 32 vout
FLAG 912 48 vout
SYMBOL npn 256 240 R0
SYMATTR InstName Q4
SYMATTR Value 2N3904
SYMBOL npn 160 240 M0
SYMATTR InstName Q5
SYMATTR Value 2N3904
SYMBOL current 96 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I2
SYMATTR Value 1m
SYMBOL voltage 752 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL voltage 912 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V2
SYMATTR Value ""
TEXT 12 456 Left 2 !.dc dec V2 1 9 0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6226.asc
* Generated by LTspice 26.0.1 for Windows.
V1 V+ 0 5
V2 V- 0 -5
V3 In 0 PULSE(-75m 75m 100n 1n 1n 400n 800n)
XU1 In N001 Out V+ V- V+ LTC6226 ;pnba IN+)IN-)OUT)VCC)VEE)SHDN_L
R1 Out N001 100
R2 N001 0 11
.tran 1u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6226.asy)
.lib LTC6226.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 4472 1028
WIRE -2800 -528 -2832 -528
WIRE -2688 -528 -2720 -528
WIRE -2544 -528 -2688 -528
WIRE -2384 -528 -2464 -528
WIRE -2576 -416 -2592 -416
WIRE -2592 -400 -2592 -416
WIRE -2688 -352 -2688 -528
WIRE -2624 -352 -2688 -352
WIRE -2384 -320 -2384 -528
WIRE -2384 -320 -2480 -320
WIRE -2352 -320 -2384 -320
WIRE -2624 -288 -2832 -288
WIRE -3184 -256 -3200 -256
WIRE -3008 -256 -3024 -256
WIRE -2544 -224 -2544 -240
WIRE -2528 -224 -2544 -224
WIRE -3200 -208 -3200 -256
WIRE -3024 -208 -3024 -256
WIRE -2832 -208 -2832 -288
WIRE -2592 -208 -2592 -240
WIRE -2576 -208 -2592 -208
WIRE -3200 -80 -3200 -128
WIRE -3024 -80 -3024 -128
WIRE -2832 -80 -2832 -128
FLAG -3200 -80 0
FLAG -3024 -80 0
FLAG -3184 -256 V+
FLAG -3008 -256 V-
FLAG -2576 -416 V+
FLAG -2576 -208 V-
FLAG -2832 -80 0
FLAG -2528 -224 V+
FLAG -2352 -320 Out
FLAG -2832 -288 In
FLAG -2832 -528 0
SYMBOL voltage -3200 -224 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -3024 -224 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage -2832 -224 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-75m 75m 100n 1n 1n 400n 800n)
SYMBOL LTC6226 -2592 -320 R0
SYMATTR InstName U1
SYMBOL res -2448 -544 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL res -2704 -544 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 11
TEXT -2392 -56 Left 2 !.tran 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG5421.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG5421.asy)
V3 N001 0 10
V2 -V 0 -15
V1 +V 0 15
V4 N003 0 pulse(0 3.3 0 1u 1u 5m 10m)
C1 N002 0 35p
XU1 N003 N002 N001 -V 0 +V ADG5421 ;pnba IN)D)S)Vss)GND)Vdd
R1 N002 0 300
.tran 30m
.lib ADG5421.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -112 -112 -112 -128
WIRE -480 -48 -480 -64
WIRE -336 -48 -368 -48
WIRE -208 -48 -256 -48
WIRE 48 -48 -16 -48
WIRE 144 -48 48 -48
WIRE 48 -16 48 -48
WIRE 144 0 144 -48
WIRE -208 16 -336 16
WIRE -480 48 -480 32
WIRE 48 80 48 64
WIRE 144 80 144 64
WIRE -336 96 -336 16
WIRE -480 144 -480 128
WIRE -160 144 -160 128
WIRE -64 144 -64 128
WIRE -480 240 -480 224
WIRE -336 240 -336 176
SYMBOL res 32 -32 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -336 80 R0
WINDOW 3 31 118 Left 2
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMATTR InstName V4
SYMBOL Switches\\ADG5421 -112 0 R0
SYMATTR InstName U1
SYMBOL cap 128 0 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL voltage -480 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -240 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -480 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
FLAG -480 240 0
FLAG -480 48 0
FLAG -480 -64 +V
FLAG -480 128 -V
FLAG -368 -48 0
FLAG -160 144 -V
FLAG -112 -128 +V
FLAG -64 144 0
FLAG -336 240 0
FLAG 48 80 0
FLAG 144 80 0
TEXT -312 224 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\09465577d3d5_EJ1.asc
* Generated by LTspice 26.0.1 for Windows.
L2 N002 N003 1
C1 N002 0 2
L1 N001 N002 1
RL N003 0 1
V1 N001 0 AC 1 Rser=1
.ac dec 1k 0.001 1000
.net I(RL) V1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 96 -48 96
WIRE 176 96 112 96
WIRE 256 96 176 96
WIRE 400 96 336 96
WIRE -48 160 -48 96
WIRE 400 160 400 96
WIRE 176 192 176 96
WIRE -48 304 -48 240
WIRE 176 304 176 256
WIRE 176 304 -48 304
WIRE 400 304 400 240
WIRE 400 304 176 304
WIRE 176 320 176 304
SYMBOL cap 160 192 R0
SYMATTR InstName C1
SYMATTR Value 2
SYMBOL res 384 144 R0
SYMATTR InstName RL
SYMATTR Value 1
SYMBOL ind 16 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL ind 240 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 1
SYMBOL voltage -48 144 R0
WINDOW 123 21 105 Left 2
WINDOW 39 20 131 Left 2
SYMATTR Value2 AC 1
SYMATTR SpiceLine Rser=1
SYMATTR InstName V1
SYMATTR Value ""
FLAG 176 320 0
TEXT -152 352 Left 2 !.ac dec 1k 0.001 1000
TEXT -152 376 Left 2 !.net I(RL) V1
* Z:\home\khalils\Downloads\files\data\raw_asc\871e5305ab5a_LT_QUALIF_2N3904.asc
* Generated by LTspice 26.0.1 for Windows.
I1 0 N002 1m
V1 N001 0 1V
Q1 N001 N002 0 0 2N3904
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 15 0.1 i1 0 10m 100u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1564 2292
WIRE 432 160 128 160
WIRE 432 256 432 160
WIRE 368 304 256 304
WIRE 128 368 128 160
WIRE 256 368 256 304
WIRE 128 512 128 448
WIRE 256 512 256 448
WIRE 256 512 128 512
WIRE 336 512 256 512
WIRE 432 512 432 352
WIRE 432 512 336 512
WIRE 336 528 336 512
SYMBOL /voltage 128 352 R0
SYMATTR InstName V1
SYMATTR Value 1V
SYMBOL /current 256 448 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 1m
SYMBOL /npn 368 256 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
FLAG 336 528 0
TEXT 136 88 Left 2 !.dc V1 0 15 0.1 i1 0 10m 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\c6f172b45764_Assignment_3a__v_.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Half Wave Rectifier Circuit (with 10microF Capacitor) (Ideal)
D1 N001 N002 1N4148
R1 N002 0 1000
C1 N002 0 0.00001
V1 N001 0 SINE(0 311 50) Rser=0.001
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 64 80 64
WIRE 352 64 256 64
WIRE 464 64 352 64
WIRE 80 112 80 64
WIRE 352 112 352 64
WIRE 464 128 464 64
WIRE 80 240 80 192
WIRE 176 240 80 240
WIRE 352 240 352 192
WIRE 352 240 176 240
WIRE 464 240 464 192
WIRE 464 240 352 240
WIRE 176 272 176 240
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 311 50)
SYMBOL cap 448 128 R0
SYMATTR InstName C1
SYMATTR Value 0.00001
SYMBOL diode 192 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
FLAG 176 272 0
TEXT 16 272 Left 2 !.tran 0.05
TEXT 264 8 Center 2 ;Positive Half Wave Rectifier Circuit (with 10microF Capacitor) (Ideal)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3112.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3112.asy)
C3 N001 N003 .1
L1 N001 N002 4.7
V1 IN 0 6
C2 N005 0 1
C4 N002 N004 .1
Rload OUT 0 2.5
C7 OUT 0 47
R2 OUT N006 845K
C1 N008 0 100p
C5 N006 N007 680p Rser=33K Cpar=22p
R3 N006 0 158K
XU1 0 N007 N006 0 IN MP_01 IN N008 OUT MP_02 MP_03 N002 MP_04 N004 N001 MP_05 N003 N005 IN LTC3112 ;pnba GND)COMP)FB)OVP)Vin))RUN)Iout)Vout)))SW2))Bst2)SW1))Bst1)Vcc)PWM/SYNC
C6 OUT N006 47p Rser=10K
R1 N008 0 42.2K
.tran 2.5m startup
.lib LTC3112.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 996 680
WIRE 160 -112 32 -112
WIRE 176 -112 160 -112
WIRE 288 -112 256 -112
WIRE 400 -112 288 -112
WIRE 32 -80 32 -112
WIRE 400 -80 400 -112
WIRE 160 -64 160 -112
WIRE 288 -64 288 -112
WIRE 32 0 32 -16
WIRE 80 0 32 0
WIRE 400 0 400 -16
WIRE 400 0 368 0
WIRE 64 96 -16 96
WIRE 80 96 64 96
WIRE 432 96 368 96
WIRE 720 96 432 96
WIRE 816 96 720 96
WIRE 896 96 816 96
WIRE -16 112 -16 96
WIRE 432 128 432 96
WIRE 720 128 720 96
WIRE 816 128 816 96
WIRE 896 128 896 96
WIRE 64 192 64 96
WIRE 80 192 64 192
WIRE 384 192 368 192
WIRE -16 208 -16 192
WIRE 816 224 816 192
WIRE 896 224 896 208
WIRE 80 288 0 288
WIRE 432 288 432 192
WIRE 432 288 368 288
WIRE 720 288 720 208
WIRE 720 288 432 288
WIRE 0 304 0 288
WIRE 432 304 432 288
WIRE 720 304 720 288
WIRE 0 384 0 368
WIRE 64 384 64 192
WIRE 80 384 64 384
WIRE 432 384 432 368
WIRE 432 384 368 384
WIRE 720 400 720 384
WIRE 160 464 160 448
WIRE 288 464 288 448
WIRE 384 464 288 464
WIRE 288 480 288 464
WIRE 384 480 384 464
WIRE 288 576 288 544
WIRE 384 576 384 560
SYMBOL ind 160 -96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL res 368 464 R0
SYMATTR InstName R1
SYMATTR Value 42.2K
SYMBOL res 880 112 R0
SYMATTR InstName Rload
SYMATTR Value 2.5
SYMBOL cap 416 304 R0
WINDOW 39 24 64 Left 2
WINDOW 3 42 37 Left 2
SYMATTR SpiceLine Rser=33K Cpar=22p
SYMATTR Value 680p
SYMATTR InstName C5
SYMBOL PowerProducts\\LTC3112 224 192 R0
SYMATTR InstName U1
SYMBOL cap 384 -80 R0
SYMATTR InstName C4
SYMATTR Value .1
SYMBOL cap 416 128 R0
WINDOW 39 24 92 Left 2
SYMATTR SpiceLine Rser=10K
SYMATTR InstName C6
SYMATTR Value 47p
SYMBOL cap -16 304 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 16 -80 R0
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL cap 272 480 R0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL res 704 112 R0
SYMATTR InstName R2
SYMATTR Value 845K
SYMBOL voltage -16 96 R0
SYMATTR InstName V1
SYMATTR Value 6
SYMBOL res 704 288 R0
SYMATTR InstName R3
SYMATTR Value 158K
SYMBOL cap 800 128 R0
SYMATTR InstName C7
SYMATTR Value 47
FLAG 160 464 0
FLAG 288 576 0
FLAG 384 576 0
FLAG 0 384 0
FLAG -16 208 0
FLAG -16 96 IN
FLAG 384 192 0
FLAG 720 400 0
FLAG 816 224 0
FLAG 896 224 0
FLAG 896 96 OUT
TEXT 568 496 Left 2 !.tran 2.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3538.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3538.asy)
R1 N004 N005 464K
L1 N001 N002 3.3
Rload N004 0 5
XU1 N005 N006 0 N003 N004 N002 N001 N003 LTC3538 ;pnba FB)Vc)GND)Burst)Vout)SW2)SW1)Vin
C3 N004 0 22 Rser=10m
V1 N003 0 3
C4 N004 N005 33p Rser=10K
C2 N006 N005 330p Rser=15K
R2 N005 0 200K
.tran 2.5m startup
.lib LTC3538.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1096 692
WIRE 432 160 400 160
WIRE 528 160 512 160
WIRE 400 208 400 160
WIRE 528 208 528 160
WIRE 304 256 208 256
WIRE 320 256 304 256
WIRE 640 256 608 256
WIRE 784 256 640 256
WIRE 880 256 784 256
WIRE 960 256 880 256
WIRE 208 272 208 256
WIRE 640 272 640 256
WIRE 784 272 784 256
WIRE 880 272 880 256
WIRE 960 272 960 256
WIRE 304 352 304 256
WIRE 320 352 304 352
WIRE 640 352 640 336
WIRE 640 352 608 352
WIRE 720 352 640 352
WIRE 784 352 720 352
WIRE 208 368 208 352
WIRE 784 368 784 352
WIRE 880 368 880 336
WIRE 960 368 960 352
WIRE 320 448 304 448
WIRE 640 448 608 448
WIRE 720 448 720 352
WIRE 720 448 704 448
WIRE 784 464 784 448
SYMBOL res 944 256 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL cap 864 272 R0
SYMATTR InstName C3
SYMATTR Value 22
SYMATTR SpiceLine Rser=10m
SYMBOL cap 640 464 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
WINDOW 39 -21 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 330p
SYMATTR SpiceLine Rser=15K
SYMBOL voltage 208 256 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 768 352 R0
SYMATTR InstName R2
SYMATTR Value 200K
SYMBOL cap 624 272 R0
WINDOW 3 35 37 Left 2
WINDOW 39 20 59 Left 2
SYMATTR Value 33p
SYMATTR SpiceLine Rser=10K
SYMATTR InstName C4
SYMBOL PowerProducts\\LTC3538 464 352 R0
SYMATTR InstName U1
SYMBOL ind 416 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 3.3
SYMBOL res 768 256 R0
SYMATTR InstName R1
SYMATTR Value 464K
FLAG 208 368 0
FLAG 304 448 0
FLAG 960 368 0
FLAG 784 464 0
FLAG 880 368 0
TEXT 808 528 Left 2 !.tran 2.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\155405efd214_full_adder.asc
* Generated by LTspice 26.0.1 for Windows.
* This EXOR has special function.\nJust only one of all inputs is "H", then output is "H" otherwise "L".
A1 B0 0 0 0 A0 0 N004 0 AND
A2 B0 0 A0 0 0 N008 N006 0 XOR
A3 0 0 N004 0 N005 0 N003 0 AND
A4 N001 0 0 0 C0 0 N002 0 AND
A5 N002 0 0 0 N003 0 Y1 0 OR
A6 N008 0 0 0 C0 0 N009 0 AND
A7 N007 0 0 0 N009 0 Y0 0 OR
A8 N006 0 0 0 N005 0 N007 0 AND
A9 C0 0 0 0 0 N005 0 0 BUF
A10 B0 0 0 0 A0 0 N001 0 OR
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1000 936
WIRE 32 -304 -64 -304
WIRE 304 -288 96 -288
WIRE 400 -272 368 -272
WIRE 32 -240 -16 -240
WIRE 48 -224 48 -240
WIRE 304 -224 160 -224
WIRE 400 -224 400 -272
WIRE 432 -224 400 -224
WIRE 320 -208 320 -224
WIRE 528 -208 496 -208
WIRE 432 -160 400 -160
WIRE 448 -144 448 -160
WIRE -64 -128 -64 -304
WIRE 32 -128 -64 -128
WIRE 400 -128 400 -160
WIRE 400 -128 368 -128
WIRE 304 -112 96 -112
WIRE 304 -80 272 -80
WIRE -16 -64 -16 -240
WIRE 32 -64 -16 -64
WIRE 320 -64 320 -80
WIRE 48 -48 48 -64
WIRE -64 48 -64 -128
WIRE -64 48 -128 48
WIRE 16 48 -64 48
WIRE 304 64 80 64
WIRE -16 80 -16 -64
WIRE -16 80 -128 80
WIRE 16 80 -16 80
WIRE 416 80 368 80
WIRE 112 96 96 96
WIRE 48 128 48 112
WIRE 272 128 272 -80
WIRE 304 128 272 128
WIRE 416 128 416 80
WIRE 448 128 416 128
WIRE 320 144 320 128
WIRE 544 144 512 144
WIRE -16 192 -128 192
WIRE 160 192 160 -224
WIRE 160 192 -16 192
WIRE 192 192 160 192
WIRE 272 192 272 128
WIRE 272 192 256 192
WIRE 448 192 416 192
WIRE 464 208 464 192
WIRE 192 224 192 208
WIRE 112 256 112 96
WIRE 304 256 112 256
WIRE 416 272 416 192
WIRE 416 272 368 272
WIRE -16 320 -16 192
WIRE 304 320 -16 320
WIRE 320 336 320 320
IOPIN -128 80 In
IOPIN -128 48 In
IOPIN 544 144 Out
IOPIN 528 -208 Out
IOPIN -128 192 In
SYMBOL Digital\\or 480 96 R0
SYMATTR InstName A7
SYMBOL Digital\\and 336 224 R0
SYMATTR InstName A6
SYMBOL Digital\\and 336 -320 R0
SYMATTR InstName A4
SYMBOL Digital\\and 336 32 R0
SYMATTR InstName A8
SYMBOL Digital\\and 64 -160 R0
SYMATTR InstName A1
SYMBOL Digital\\or 64 -336 R0
SYMATTR InstName A10
SYMBOL Digital\\and 336 -176 R0
SYMATTR InstName A3
SYMBOL Digital\\xor 64 16 R0
SYMATTR InstName A2
SYMBOL Digital\\inv 192 128 R0
SYMATTR InstName A9
SYMBOL Digital\\or 464 -256 R0
SYMATTR InstName A5
FLAG 48 -48 0
FLAG 48 128 0
FLAG -128 80 A0
FLAG -128 48 B0
FLAG 544 144 Y0
FLAG 528 -208 Y1
FLAG -128 192 C0
FLAG 320 -64 0
FLAG 320 -208 0
FLAG 448 -144 0
FLAG 320 336 0
FLAG 464 208 0
FLAG 320 144 0
FLAG 192 224 0
FLAG 48 -224 0
TEXT -136 376 Left 2 ;This EXOR has special function.\nJust only one of all inputs is "H", then output is "H" otherwise "L".