Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\10dace6d6683_NOR.asc
* Generated by LTspice 26.0.1 for Windows.
V2 A 0 PULSE(5 0 0 30n 30n 2m 4m)
M1 S A 0 0 NMOS
M2 S B 0 0 NMOS
V3 B 0 PULSE(5 0 0 30n 30n 1m 2m)
M4 P001 A N001 N001 PMOS
M3 S B P001 P001 PMOS
V+5V N001 0 5V
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 48 80 48
WIRE 352 80 352 48
WIRE 304 96 256 96
WIRE -224 160 -400 160
WIRE 80 192 80 48
WIRE 304 192 256 192
WIRE -224 208 -304 208
WIRE -400 240 -400 160
WIRE -304 240 -304 208
WIRE 352 288 352 272
WIRE 528 288 352 288
WIRE 352 304 352 288
WIRE 352 304 272 304
WIRE 432 304 352 304
WIRE 272 336 272 304
WIRE 432 336 432 304
WIRE -400 384 -400 320
WIRE -352 384 -400 384
WIRE -304 384 -304 320
WIRE -304 384 -352 384
WIRE -352 416 -352 384
WIRE 224 416 192 416
WIRE 512 416 480 416
WIRE 80 464 80 272
WIRE 224 464 80 464
WIRE 272 464 272 432
WIRE 272 464 224 464
WIRE 432 464 432 432
WIRE 432 464 272 464
WIRE 224 496 224 464
SYMBOL nmos 224 336 R0
SYMATTR InstName M1
SYMBOL pmos 304 272 M180
SYMATTR InstName M3
SYMBOL nmos 480 336 M0
SYMATTR InstName M2
SYMBOL pmos 304 176 M180
SYMATTR InstName M4
SYMBOL voltage -400 224 R0
WINDOW 3 -339 32 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(5 0 0 30n 30n 2m 4m)
SYMATTR InstName V2
SYMBOL voltage -304 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(5 0 0 30n 30n 1m 2m)
SYMBOL voltage 80 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName +5V
SYMATTR Value 5V
FLAG -352 416 0
FLAG -224 160 A
FLAG -224 208 B
FLAG 256 96 A
FLAG 256 192 B
FLAG 224 496 0
FLAG 192 416 A
FLAG 512 416 B
FLAG 528 288 S
TEXT -352 520 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\3524ed4a38ec_VA-F3.asc
* Generated by LTspice 26.0.1 for Windows.
V1 a 0
R1 b 0 1k
D1 a b RF05VAM1S
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0 100
.step temp list 0 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 128 -144 128
WIRE 240 128 80 128
WIRE -144 192 -144 128
WIRE 240 192 240 128
WIRE -144 352 -144 272
WIRE 48 352 -144 352
WIRE 240 352 240 272
WIRE 240 352 48 352
WIRE 48 368 48 352
SYMBOL voltage -144 176 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value ""
SYMATTR InstName V1
SYMBOL Misc\\EuropeanResistor 224 176 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL diode 16 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 -7 36 VBottom 2
SYMATTR InstName D1
SYMATTR Value RF05VAM1S
FLAG -144 128 a
FLAG 240 128 b
FLAG 48 368 0
TEXT -144 392 Left 2 !.dc V1 0 100
TEXT -152 424 Left 2 !.step temp list 0 100
* Z:\home\khalils\Downloads\files\data\raw_asc\0caad4945cde_common_mode_gain_bjt_ltspice.asc
* Generated by LTspice 26.0.1 for Windows.
* Common Mode Gain Configuration
Q1 2- W1 N001 0 2N3904
R3 N001 Vn 15k
V3 W1 0 SINE(-0.8 3.7 100)
V1 Vp 0 5
V2 Vn 0 -5
Q2 2+ W1 N001 0 2N3904
R1 Vp 2- 10k
R2 Vp 2+ 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 50m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 -160 208 -160
WIRE 400 -160 352 -160
WIRE -704 -96 -704 -128
WIRE -544 -96 -544 -128
WIRE -368 -96 -368 -128
WIRE 208 -80 208 -160
WIRE 352 -80 352 -160
WIRE -704 16 -704 -16
WIRE -544 16 -544 -16
WIRE -368 16 -368 -16
WIRE 208 64 208 0
WIRE 256 64 208 64
WIRE 352 64 352 0
WIRE 416 64 352 64
WIRE 208 144 208 64
WIRE 352 144 352 64
WIRE 144 192 48 192
WIRE 512 192 416 192
WIRE -64 256 -64 224
WIRE -64 256 -80 256
WIRE 48 256 48 192
WIRE 48 256 -64 256
WIRE 208 304 208 240
WIRE 272 304 208 304
WIRE 352 304 352 240
WIRE 352 304 272 304
WIRE 48 336 48 256
WIRE 512 336 512 192
WIRE 512 336 48 336
WIRE 272 416 272 304
WIRE 272 560 272 496
WIRE 368 560 272 560
IOPIN -80 256 In
IOPIN 368 560 In
IOPIN 400 -160 In
IOPIN -704 -128 In
IOPIN -544 -128 In
IOPIN -368 -128 In
IOPIN -64 224 In
IOPIN 256 64 In
IOPIN 416 64 In
SYMBOL npn 416 144 M0
WINDOW 3 -83 32 Left 2
SYMATTR Value 2N3904
SYMATTR InstName Q2
SYMBOL res 336 -96 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -368 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(-0.8 3.7 100)
SYMBOL voltage -704 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 256 400 R0
SYMATTR InstName R3
SYMATTR Value 15k
SYMBOL voltage -544 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL npn 144 144 R0
WINDOW 3 -81 30 Left 2
SYMATTR Value 2N3904
SYMATTR InstName Q1
SYMBOL res 192 -96 R0
SYMATTR InstName R1
SYMATTR Value 10k
FLAG -80 256 W1
FLAG 368 560 Vn
FLAG 400 -160 Vp
FLAG -704 16 0
FLAG -544 16 0
FLAG -368 16 0
FLAG -704 -128 Vp
FLAG -544 -128 Vn
FLAG -368 -128 W1
FLAG -64 224 1+
FLAG 256 64 2-
FLAG 416 64 2+
TEXT -104 560 Left 2 !.tran 50m
TEXT -16 -320 Left 2 ;Common Mode Gain Configuration
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1740-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1740-1.5.asy)
R1 IN N001 100k
V1 IN 0 1.8
XU1 IN OUT IN N002 OUT N001 MP_01 0 ADP1740-1.5 ;pnba Vin)Sense)EN)SS)Vout)PG))GND
C1 OUT 0 4.7 Rser=3m
Rload OUT 0 0.75
C2 N002 0 10n
.tran 10m startup
.lib ADP1740-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE -112 32 -128 32
WIRE -16 32 -112 32
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 416 32 368 32
WIRE 496 32 416 32
WIRE 528 32 496 32
WIRE -128 48 -128 32
WIRE -16 48 -16 32
WIRE 416 48 416 32
WIRE 528 48 528 32
WIRE 80 96 80 32
WIRE 96 96 80 96
WIRE -128 144 -128 128
WIRE 416 144 416 112
WIRE 528 144 528 128
WIRE -16 176 -16 128
WIRE 96 176 -16 176
WIRE 16 240 0 240
WIRE 96 240 80 240
WIRE 368 240 368 32
WIRE 368 240 352 240
WIRE 224 304 224 288
SYMBOL ADP1740-1.5 224 128 R0
SYMATTR InstName U1
SYMBOL res -32 32 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.75
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL cap 400 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL cap 80 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
FLAG 224 304 0
FLAG -128 144 0
FLAG 0 240 0
FLAG -112 32 IN
FLAG 528 144 0
FLAG 416 144 0
FLAG 496 32 OUT
TEXT 128 352 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\76820d50ff85_switch.asc
* Generated by LTspice 26.0.1 for Windows.
* switch ON = closed, V>Vt\nswitch OFF = open, V<Vt
C1 N004 0 10e-3
R1 N004 N003 10e+5
R2 N004 0 10e+1
V2 N002 0 5
S1 N003 N002 N001 0 SW_1
V1 N001 0 PULSE(-1 1 1 0 0 0 1)
.Model SW_1 SW(Ron=1 Roff=1000Meg Vt=0)
.tran 5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 680
WIRE 176 -32 -48 -32
WIRE -48 -16 -48 -32
WIRE 176 128 176 -32
WIRE 176 128 128 128
WIRE -48 144 -48 64
WIRE 80 144 -48 144
WIRE 128 144 128 128
WIRE 176 144 176 128
WIRE 64 192 16 192
WIRE 176 192 144 192
WIRE 16 320 16 192
WIRE 16 320 -176 320
WIRE 176 320 176 192
WIRE 208 320 176 320
WIRE 400 320 288 320
WIRE 544 320 400 320
WIRE 400 336 400 320
WIRE 544 336 544 320
WIRE -176 432 -176 400
WIRE 400 432 400 400
WIRE 400 432 -176 432
WIRE 544 432 544 416
WIRE 544 432 400 432
WIRE -176 464 -176 432
SYMBOL res 304 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10e+5
SYMBOL sw 160 192 R90
SYMATTR InstName S1
SYMATTR Value SW_1
SYMBOL res 528 320 R0
SYMATTR InstName R2
SYMATTR Value 10e+1
SYMBOL cap 384 336 R0
SYMATTR InstName C1
SYMATTR Value 10e-3
SYMBOL voltage -176 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -48 80 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(-1 1 1 0 0 0 1)
FLAG 176 144 0
FLAG -176 464 0
TEXT 560 -16 Left 2 !.Model SW_1 SW(Ron=1 Roff=1000Meg Vt=0)
TEXT -336 488 Left 2 !.tran 5
TEXT 408 216 Left 2 ;switch ON = closed, V>Vt\nswitch OFF = open, V<Vt
* Z:\home\khalils\Downloads\files\data\raw_asc\0b386f3d3f5a_bjt_modelo.asc
* Generated by LTspice 26.0.1 for Windows.
;.tran 100e-3
C3 o N004 10e-6
V3 N005 0 SINE(0 1e-3 1e6) AC 0
L1 N002 N006 10e-6
R1 N002 N001 10
L2 N003 N004 10e-6
C2 N006 N005 1e-6
V4 o 0 0 AC 1e-3
C5 o 0 1e-9
C4 NC_01 N007 1e-6
V1 N001 0 0.4
R3 N007 0 50
R4 N004 c 0.1
Q1 c b 0 0 2N3904
R2 N006 b 0.1
C1 N002 0 1e-6
V2 N003 0 6
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.ac dec 100 100e3 20e6
.step param R list 1 10 1e3 10e3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -272 -112 -304 -112
WIRE -160 -112 -192 -112
WIRE -64 -112 -160 -112
WIRE 560 -96 352 -96
WIRE -160 -80 -160 -112
WIRE -304 -48 -304 -112
WIRE -64 -48 -64 -112
WIRE 352 -48 352 -96
WIRE 560 -48 560 -96
WIRE -160 16 -160 -16
WIRE 560 48 560 32
WIRE -304 64 -304 32
WIRE 208 112 192 112
WIRE 240 112 208 112
WIRE 352 112 352 32
WIRE 352 112 320 112
WIRE 416 112 352 112
WIRE 544 112 480 112
WIRE 592 112 544 112
WIRE 656 112 592 112
WIRE -160 160 -304 160
WIRE -64 160 -64 32
WIRE -64 160 -96 160
WIRE -32 160 -64 160
WIRE 80 160 48 160
WIRE 128 160 80 160
WIRE -304 192 -304 160
WIRE 544 192 544 112
WIRE 656 208 656 176
WIRE 80 272 80 256
WIRE -304 288 -304 272
WIRE 192 288 192 208
WIRE 544 288 544 272
WIRE 80 368 80 352
SYMBOL cap 640 112 R0
SYMATTR InstName C5
SYMATTR Value 1e-9
SYMBOL cap -96 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1e-6
SYMBOL cap 480 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10e-6
SYMBOL res 336 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 0.1
SYMBOL res -176 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL res 64 256 R0
SYMATTR InstName R3
SYMATTR Value 50
SYMBOL ind -80 -64 R0
SYMATTR InstName L1
SYMATTR Value 10e-6
SYMBOL voltage -304 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0.4
SYMBOL cap 64 192 R0
SYMATTR InstName C4
SYMATTR Value 1e-6
SYMBOL res -48 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 0.1
SYMBOL cap -176 -80 R0
SYMATTR InstName C1
SYMATTR Value 1e-6
SYMBOL voltage 544 176 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMATTR Value2 AC 1e-3
SYMBOL voltage -304 176 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 1e-3 1e6)
SYMATTR Value2 AC 0
SYMBOL voltage 560 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 6
SYMBOL npn 128 112 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL ind 336 -64 R0
SYMATTR InstName L2
SYMATTR Value 10e-6
FLAG 192 288 0
FLAG -304 64 0
FLAG 560 48 0
FLAG 544 288 0
FLAG -304 288 0
FLAG -160 16 0
FLAG 80 160 b
FLAG 208 112 c
FLAG 80 368 0
FLAG 656 208 0
FLAG 592 112 o
TEXT -258 440 Left 2 !.ac dec 100 100e3 20e6
TEXT -248 488 Left 2 !;.tran 100e-3
TEXT -256 392 Left 2 !.step param R list  1 10 1e3 10e3
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1740-0.75.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1740-0.75.asy)
R1 IN N001 100k
C1 OUT 0 4.7 Rser=3m
Rload OUT 0 0.375
V1 IN 0 1.8
C2 N002 0 10n
XU1 IN OUT IN N002 OUT N001 MP_01 0 ADP1740-0.75 ;pnba Vin)Sense)EN)SS)Vout)PG))GND
.tran 10m startup
.lib ADP1740-0.75.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE -112 32 -128 32
WIRE -16 32 -112 32
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 416 32 368 32
WIRE 496 32 416 32
WIRE 528 32 496 32
WIRE -128 48 -128 32
WIRE -16 48 -16 32
WIRE 416 48 416 32
WIRE 528 48 528 32
WIRE 80 96 80 32
WIRE 96 96 80 96
WIRE -128 144 -128 128
WIRE 416 144 416 112
WIRE 528 144 528 128
WIRE -16 176 -16 128
WIRE 96 176 -16 176
WIRE 16 240 0 240
WIRE 96 240 80 240
WIRE 368 240 368 32
WIRE 368 240 352 240
WIRE 224 304 224 288
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.375
SYMBOL ADP1740-0.75 224 128 R0
SYMATTR InstName U1
SYMBOL cap 80 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL res -32 32 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL cap 400 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
FLAG 224 304 0
FLAG -128 144 0
FLAG 0 240 0
FLAG -112 32 IN
FLAG 528 144 0
FLAG 416 144 0
FLAG 496 32 OUT
TEXT 128 352 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2c60b32c5402_scheme13.asc
* Generated by LTspice 26.0.1 for Windows.
* Vout
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1037.asy)
R2 N005 N004 500
V3 0 N006 {Vcc}
C1 N001 N005 31.8n
V1 N004 0 PULSE(0 10 0.01ms 10p 10p 0.03ms 0.06ms)
C2 N002 N001 3.2n
XU1 0 N001 N003 N006 N002 LT1037 ;pnba In+)In-)V+)V-)OUT
V2 N003 0 {Vcc}
R1 N002 N001 50k
.param Vcc=15
.tran 1ms 1ms
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 144 -48 64 -48
WIRE 288 -48 208 -48
WIRE 64 48 64 -48
WIRE 144 48 64 48
WIRE 288 48 288 -48
WIRE 288 48 224 48
WIRE 480 96 192 96
WIRE 480 128 480 96
WIRE 192 144 192 96
WIRE -160 160 -224 160
WIRE -48 160 -80 160
WIRE 64 160 64 48
WIRE 64 160 16 160
WIRE 160 160 64 160
WIRE -224 176 -224 160
WIRE 288 176 288 48
WIRE 288 176 224 176
WIRE 368 176 288 176
WIRE 160 192 112 192
WIRE 480 240 480 208
WIRE 480 240 416 240
WIRE 112 256 112 192
WIRE 416 256 416 240
WIRE -224 272 -224 256
WIRE 480 288 480 240
WIRE 192 384 192 208
WIRE 480 384 480 368
WIRE 480 384 192 384
SYMBOL OpAmps\\LT1037 192 112 R0
SYMATTR InstName U1
SYMBOL cap 208 -64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 3.2n
SYMBOL res -64 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 500
SYMBOL voltage 480 272 R0
SYMATTR InstName V3
SYMATTR Value {Vcc}
SYMBOL res 240 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50k
SYMBOL voltage 480 112 R0
SYMATTR InstName V2
SYMATTR Value {Vcc}
SYMBOL voltage -224 160 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 10 0.01ms 10p 10p 0.03ms 0.06ms)
SYMBOL cap 16 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 31.8n
FLAG -224 272 0
FLAG 112 256 0
FLAG 416 256 0
TEXT -144 312 Left 2 !.param Vcc=15
TEXT 344 160 Left 2 ;Vout
TEXT -144 344 Left 2 !.tran 1ms 1ms
* Z:\home\khalils\Downloads\files\data\raw_asc\AD4002.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4002.asy)
V4 N006 0 PULSE(0 1.8 227n 0.1n 0.1n 40n 500n)
C1 0 N005 10p
XU1 N001 N002 N004 MP_01 0 N006 MP_02 MP_03 N005 AD4002 EN_Hi_Z=1 ;pnba REF)Vdd)IN))GND)CNV)))Vout
V1 N003 0 PWL(0 0 100u 5)
V2 N001 0 5
V3 N002 0 1.8
R1 N004 N003 10
.tran 110u
.lib AD4002.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 1252
WIRE 704 208 368 208
WIRE 832 208 784 208
WIRE 368 288 368 208
WIRE 704 336 496 336
WIRE 832 336 784 336
WIRE -144 432 -208 432
WIRE -16 432 -64 432
WIRE 128 432 64 432
WIRE 576 432 496 432
WIRE 720 432 640 432
WIRE 704 528 496 528
WIRE 832 528 784 528
WIRE 368 608 368 576
SYMBOL voltage 688 528 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V4
SYMATTR Value PULSE(0 1.8 227n 0.1n 0.1n 40n 500n)
SYMBOL res 80 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage 688 336 R270
WINDOW 0 47 41 VRight 2
WINDOW 3 -44 39 VRight 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 1.8
SYMBOL cap 640 416 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage 688 208 R270
WINDOW 0 45 70 VLeft 2
WINDOW 3 -46 68 VLeft 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -48 432 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 100u 5)
SYMBOL AD4002 400 432 R0
SYMATTR InstName U1
FLAG 368 608 0
FLAG 832 336 0
FLAG -208 432 0
FLAG 720 432 0
FLAG 832 528 0
FLAG 832 208 0
TEXT 176 616 Left 2 !.tran 110u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4440.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4440.asy)
V2 N002 0 PULSE(0 8 0 1n 1n 1u 2u)
XU1 N001 0 N002 0 N003 N001 LTC4440 ;pnba VCC)GND)INP)TS)TG)BOOST
V1 N001 0 8
.tran 50u
.lib LTC4440.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2336 1256
WIRE 1424 -144 1104 -144
WIRE 1008 -80 992 -80
WIRE 1104 -80 1104 -144
WIRE 1104 -80 1088 -80
WIRE 1136 -80 1104 -80
WIRE 1424 -80 1424 -144
WIRE 1424 -80 1392 -80
WIRE 1136 0 736 0
WIRE 1424 0 1392 0
WIRE 736 16 736 0
WIRE 1136 80 1104 80
WIRE 1424 80 1392 80
WIRE 736 112 736 96
SYMBOL voltage 736 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 8 0 1n 1n 1u 2u)
SYMBOL PowerProducts\\LTC4440 1264 0 R0
SYMATTR InstName U1
SYMBOL voltage 1104 -80 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value 8
FLAG 1104 80 0
FLAG 992 -80 0
FLAG 1424 80 0
FLAG 736 112 0
TEXT 1304 176 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\46faddf66dc0_final_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
* DC Sweeping
* .op
* .tran 5m
* .tf V(Vout) V2
* EDIC Winter Internship Assignment\nCommon Source Amplifier with Resistive(Passive) Load\nMohammed Ahmed Majid\nGP5405, 23EEBEA666
;.step param w 0.18u 7.2u 0.18u
Rd Vdd Vout 31.8k
V1 Vdd 0 1.8
CL Vout 0 1p
V2 Vin 0 SINE(0.65 1m 1k) AC 1
M1 Vout Vin 0 0 NMOS l=0.36u w={w}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include tsmc180.txt
.param w 3.97u
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -32 240 -80
WIRE 240 80 240 48
WIRE 464 80 240 80
WIRE 528 80 464 80
WIRE 240 96 240 80
WIRE 464 112 464 80
WIRE -400 144 -400 96
WIRE -256 144 -256 96
WIRE 336 144 240 144
WIRE 192 176 112 176
WIRE 240 224 240 192
WIRE 336 224 336 144
WIRE 336 224 240 224
WIRE 464 224 464 176
WIRE -400 288 -400 224
WIRE -256 288 -256 224
WIRE 240 288 240 224
IOPIN 528 80 Out
SYMBOL nmos4 192 96 R0
WINDOW 123 248 144 Right 2
SYMATTR InstName M1
SYMATTR Value2 l=0.36u w={w}
SYMBOL voltage -400 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL res 224 -48 R0
SYMATTR InstName Rd
SYMATTR Value 31.8k
SYMBOL voltage -256 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0.65 1m 1k)
SYMATTR Value2 AC 1
SYMBOL cap 448 112 R0
SYMATTR InstName CL
SYMATTR Value 1p
FLAG 240 288 0
FLAG 464 224 0
FLAG 528 80 Vout
FLAG 112 176 Vin
FLAG 240 -80 Vdd
FLAG -256 96 Vin
FLAG -400 96 Vdd
FLAG -400 288 0
FLAG -256 288 0
TEXT -376 -144 Left 2 !.include tsmc180.txt
TEXT -376 -120 Left 2 !.param w 3.97u
TEXT -384 -96 Left 2 !;.step param w 0.18u 7.2u 0.18u
TEXT -552 -120 Left 2 ;DC Sweeping
TEXT -376 -72 Left 2 ;.op
TEXT -376 -48 Left 2 ;.tran 5m
TEXT -376 -24 Left 2 ;.tf V(Vout) V2
TEXT -376 0 Left 2 !.ac dec 10 10 1gig
TEXT -552 -304 Left 2 ;EDIC Winter Internship Assignment\nCommon Source Amplifier with Resistive(Passive) Load\nMohammed Ahmed Majid\nGP5405, 23EEBEA666
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7102.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7102.asy)
Rload OUT 0 16.5
R3 OUT N001 100k
R1 OUT N002 17.4k
R2 N002 0 10K
V1 IN 0 4.3
XU1 IN N002 IN N001 OUT 0 ADP7102 Vref=1.22 ;pnba Vin)ADJ)EN)PG)Vout)GND
C1 OUT 0 2.2 Rser=3m
.tran 3m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 400 32 352 32
WIRE 528 32 480 32
WIRE -16 48 -16 32
WIRE 400 128 352 128
WIRE 528 128 528 32
WIRE 528 128 400 128
WIRE 624 128 528 128
WIRE -16 144 -16 128
WIRE 624 144 624 128
WIRE 528 160 528 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 400 224 400 208
WIRE 400 224 352 224
WIRE 400 240 400 224
WIRE 528 240 528 224
WIRE 624 240 624 224
WIRE 224 304 224 288
WIRE 400 336 400 320
SYMBOL res 608 128 R0
SYMATTR InstName Rload
SYMATTR Value 16.5
SYMBOL cap 512 160 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=3m
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 4.3
SYMBOL res 384 224 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 496 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL ADP7102 224 128 R0
SYMATTR InstName U1
SYMBOL res 384 112 R0
SYMATTR InstName R1
SYMATTR Value 17.4k
FLAG 224 304 0
FLAG -16 144 0
FLAG -16 32 IN
FLAG 624 240 0
FLAG 528 240 0
FLAG 624 128 OUT
FLAG 400 336 0
TEXT 512 304 Left 2 !.tran 3m startup
* Z:\tmp\asc_dec_bjh7r6w2\0cd301d69156_Ampli_vertical_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 0 N001 ao NC_01 NC_02 Vs P001 NC_03 LTC6090 ;pnba COM)IN-)IN+)V-)_TF)OUT)V+)_OD
V2 P001 0 32
C1 N001 Vs 40p
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6090.asy)
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 -48 64 -48
WIRE 368 -16 368 -48
WIRE 368 -16 320 -16
WIRE 416 -16 368 -16
WIRE 320 0 320 -16
WIRE 416 0 416 -16
WIRE 64 32 64 -48
WIRE 64 32 48 32
WIRE 320 96 320 64
WIRE 368 96 320 96
WIRE 416 96 416 80
WIRE 416 96 368 96
WIRE 64 128 64 32
WIRE 160 128 64 128
WIRE 368 160 368 96
WIRE 368 160 320 160
WIRE 400 160 368 160
WIRE 96 192 64 192
WIRE 160 192 96 192
WIRE 96 224 96 192
SYMBOL OpAmps\\LTC6090 224 160 R0
WINDOW 0 -31 0 Left 2
SYMATTR InstName U1
SYMBOL voltage 192 96 R180
WINDOW 0 31 88 Left 2
WINDOW 3 31 34 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 32
SYMBOL cap 304 0 R0
SYMATTR InstName C1
SYMATTR Value 40p
FLAG 192 0 0
FLAG 192 320 0
FLAG 224 240 0
FLAG 96 304 0
FLAG 400 160 Vs
FLAG 64 192 ao