* Z:\home\khalils\Downloads\files\data\raw_asc\AD5933.asc
* Generated by LTspice 26.0.1 for Windows.
V1 AVDD 0 3.3
C1 VCM VOUT 47nF ic=0.15
R1 AVDD VCM 49.9k
R2 VCM 0 49.9k
XU1 N001 TIA VIN AVDD 0 VOUT MEAS RE IM VADC AD5933 RANGE=1 RXG=1 NSET=1 FCODE=1006633 fMCLK=16Meg ;pnba MCLK)RFB)VIN)AVDD)AGND)VOUT)MEAS)RE)IM)VADC
R4 TIA VIN 1.1k
V2 N001 0 PULSE(0 3.3 0 2n 2n 29.25n 62.5n)
R3 VIN Tx 1.1k
XU2 VCM Tx AVDD 0 Tx AD8606 ;pnba In+)In-)V+)V-)OUT
.tran 1.06m
* Impedance under test
* IC used to reduce\ntime to reach\nsteady state
* Simulation time > NSET/ft+16*1024/fMCLK
* Formulas to calculate Y/Z/R/C from RE and IM register values:
* .param VDD = 3.3\n.param FREQ = 30k\n.param RFB = 1.1k\n.param RXG = 1\n.param Range = 1\n.param VAC VDD/3.3*table(Range, 1, 1.982, 2, 0.986, 3, 0.383, 4, 0.198)\n.meas TRAN t_end FIND time WHEN V(MEAS)=0.5 FALL=1\n.meas TRAN Real FIND V(RE) AT t_end\n.meas TRAN Imag FIND V(IM) AT t_end\n.meas GF_th PARAM VDD/(VAC*RFB*RXG*2**14)\n.meas Phase_offset PARAM 0.000653*FREQ-0.65\n.meas Mod PARAM sqrt(Real**2+Imag**2)\n.meas Phase PARAM atan(Imag/Real)\n.meas Phase_corr PARAM Phase + Phase_offset\n.meas ModY PARAM Mod*GF_th\n.meas ModZ PARAM 1/ModY\n.meas R PARAM ModZ*cos(Phase_corr)\n.meas C PARAM ModY*sin(Phase_corr)/(2*pi*FREQ)
* # AVDD supply voltage\n# Measurement frequency\n# RFB resistor value\n# Reception gain value (1 or 5)\n# Tx signal range (datasheet Table 1)
* # Tx signal Vpp (datasheet Table 1)
* # Time when MEAS signal falls
* # Real part register value\n# Imaginary part register value\n# Theoretical gain factor (AD5933only)\n# Theoretical phase variation (AD5933 only)\n# Modulus of Real, Imag registers\n# Phase of Real, Imag registers\n# Phase after correcting for AD5933 shift\n# Calculated admittance\n# Calculated impedance\n# Resitance calculated from impedance\n# Capacitance calculated from admittance
* Model parameters:\nRANGE : Tx signal range (1 to 4, datasheet Table 1)\nRXG : PGA gain (1 or 5)\nNSET : number of settling cycles before measurement\nFCODE : frequency register value (datasheet Eq. 1)\n FCODE = int(2^29*ft/fMCLK)\nfMCLK : MCLK clock frequency in Hz (16 MHz in this example)\nft : measurement signal frequency (30 kHz in this example)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5933.asy)
.lib AD5933.sub
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8606.asy)
.lib AD8606.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2480 1176
WIRE 1264 -144 -96 -144
WIRE 1264 -64 1264 -144
WIRE 1104 -48 976 -48
WIRE 896 -32 864 -32
WIRE 912 -32 896 -32
WIRE 160 -16 112 -16
WIRE 288 -16 240 -16
WIRE 864 0 864 -32
WIRE 112 32 112 -16
WIRE 1040 32 1024 32
WIRE 1056 32 1040 32
WIRE -96 48 -96 -144
WIRE 16 48 -96 48
WIRE -96 64 -96 48
WIRE 1024 64 1024 32
WIRE 288 80 288 -16
WIRE 976 80 976 -48
WIRE 992 80 976 80
WIRE 1104 96 1104 -48
WIRE 1104 96 1056 96
WIRE 1232 96 1104 96
WIRE 1264 96 1264 16
WIRE 1264 96 1232 96
WIRE 16 112 16 48
WIRE 48 112 16 112
WIRE 80 112 48 112
WIRE 544 112 496 112
WIRE 704 112 544 112
WIRE 864 112 864 80
WIRE 864 112 768 112
WIRE 928 112 864 112
WIRE 992 112 928 112
WIRE -96 160 -96 144
WIRE 48 160 -96 160
WIRE 80 160 48 160
WIRE 544 160 496 160
WIRE 560 160 544 160
WIRE 864 160 864 112
WIRE 1024 176 1024 128
WIRE 528 208 496 208
WIRE 560 208 528 208
WIRE 80 224 -80 224
WIRE 528 256 496 256
WIRE 560 256 528 256
WIRE -80 272 -80 224
WIRE 864 288 864 240
WIRE 288 320 288 288
WIRE 128 368 96 368
WIRE 192 368 192 288
WIRE 192 368 128 368
WIRE -80 400 -80 352
FLAG 288 320 0
FLAG 112 32 0
FLAG 1024 176 0
FLAG 1040 32 AVDD
FLAG 864 288 0
FLAG 896 -32 AVDD
FLAG 544 112 VOUT
FLAG 928 112 VCM
FLAG 1232 96 Tx
FLAG 528 208 RE
FLAG 528 256 IM
FLAG 544 160 MEAS
FLAG 128 368 VADC
FLAG -80 400 0
FLAG 48 112 VIN
FLAG 48 160 TIA
FLAG 288 -16 AVDD
SYMBOL voltage 256 -16 R90
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -53 47 VRight 2
WINDOW 3 50 36 VRight 2
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 768 96 R90
WINDOW 0 -2 70 VBottom 2
WINDOW 3 -31 13 VTop 2
WINDOW 123 66 30 VBottom 2
SYMATTR InstName C1
SYMATTR Value 47nF
SYMATTR Value2 ic=0.15
SYMBOL res 848 -16 R0
SYMATTR InstName R1
SYMATTR Value 49.9k
SYMBOL res 848 144 R0
SYMATTR InstName R2
SYMATTR Value 49.9k
SYMBOL AD5933 288 192 R0
SYMATTR InstName U1
SYMATTR SpiceLine NSET=1 FCODE=1006633
SYMBOL res -80 160 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 1.1k
SYMBOL voltage -80 256 R0
WINDOW 3 -467 55 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3.3 0 2n 2n 29.25n 62.5n)
SYMATTR InstName V2
SYMBOL res 1248 -80 R0
SYMATTR InstName R3
SYMATTR Value 1.1k
SYMBOL OpAmps\\AD8606 1024 32 R0
SYMATTR InstName U2
TEXT 72 424 Left 2 !.tran 1.06m
TEXT 1376 -24 Left 2 ;Impedance under test
TEXT 624 184 Left 2 ;IC used to reduce\ntime to reach\nsteady state
TEXT -72 472 Left 2 ;Simulation time > NSET/ft+16*1024/fMCLK
TEXT -48 576 Left 2 ;Formulas to calculate Y/Z/R/C from RE and IM register values:
TEXT -56 616 Left 2 ;.param VDD = 3.3\n.param FREQ = 30k\n.param RFB = 1.1k\n.param RXG = 1\n.param Range = 1\n.param VAC VDD/3.3*table(Range, 1, 1.982, 2, 0.986, 3, 0.383, 4, 0.198)\n.meas TRAN t_end FIND time WHEN V(MEAS)=0.5 FALL=1\n.meas TRAN Real FIND V(RE) AT t_end\n.meas TRAN Imag FIND V(IM) AT t_end\n.meas GF_th PARAM VDD/(VAC*RFB*RXG*2**14)\n.meas Phase_offset PARAM 0.000653*FREQ-0.65\n.meas Mod PARAM sqrt(Real**2+Imag**2)\n.meas Phase PARAM atan(Imag/Real)\n.meas Phase_corr PARAM Phase + Phase_offset\n.meas ModY PARAM Mod*GF_th\n.meas ModZ PARAM 1/ModY\n.meas R PARAM ModZ*cos(Phase_corr)\n.meas C PARAM ModY*sin(Phase_corr)/(2*pi*FREQ)
TEXT 208 616 Left 2 ;# AVDD supply voltage\n# Measurement frequency\n# RFB resistor value\n# Reception gain value (1 or 5)\n# Tx signal range (datasheet Table 1)
TEXT 808 752 Left 2 ;# Tx signal Vpp (datasheet Table 1)
TEXT 616 784 Left 2 ;# Time when MEAS signal falls
TEXT 576 816 Left 2 ;# Real part register value\n# Imaginary part register value\n# Theoretical gain factor (AD5933only)\n# Theoretical phase variation (AD5933 only)\n# Modulus of Real, Imag registers\n# Phase of Real, Imag registers\n# Phase after correcting for AD5933 shift\n# Calculated admittance\n# Calculated impedance\n# Resitance calculated from impedance\n# Capacitance calculated from admittance
TEXT 536 312 Left 2 ;Model parameters:\nRANGE : Tx signal range (1 to 4, datasheet Table 1)\nRXG      : PGA gain (1 or 5)\nNSET    : number of settling cycles before measurement\nFCODE  : frequency register value (datasheet Eq. 1)\n                FCODE = int(2^29*ft/fMCLK)\nfMCLK  : MCLK clock frequency in Hz (16 MHz in this example)\nft           : measurement signal frequency (30 kHz in this example)
RECTANGLE Normal 1360 32 1200 -80 2
RECTANGLE Normal 1232 1136 -80 544 2