* Z:\home\khalils\Downloads\files\data\raw_asc\189cf613a6e2_open_loop_4.asc
* Generated by LTspice 26.0.1 for Windows.
* https://www.youtube.com/watch?v=YYWlPFBebfc
* Open loop simulation
* Step 1: For open loop simulation, change the closed loop simulation by\nStep 2: 'Break the loop' at opamp negative input\nStep 3: Give the broken nodes unique names, for example 'fb' and 'inm'\nStep 4: Insert a 0V voltage source to close the loop again
* AC=1 Voltage source sets the\ndifference between 'fb' and 'inm', does \nnot force ratio of 'fb' and 'inm'.\n \nRatio 'fb/inm' is determined by \ncircuit open loop gain.
* Step 5: Give the voltage source an AC=1 stimulus
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6016.asy)
R1 OUT fb 1K
VIN fb inm 0V AC 1
R2 fb 0 1K
VEE vee 0 -15V
C1 OUT 0 {Cload}
VCC vcc 0 15V
XU1 0 inm vcc vee OUT LT6016 ;pnba IN+)IN-)VCC)VEE)OUT
.ac oct 100 1e3 10e6
.step param Cload list 1pF 2200pF
.lib LT6016.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -64 16 -272 16
WIRE 128 16 16 16
WIRE 192 16 128 16
WIRE 384 16 272 16
WIRE 128 80 128 16
WIRE -592 96 -592 48
WIRE -272 96 -272 16
WIRE 128 224 128 160
WIRE 240 240 240 208
WIRE -592 256 -592 176
WIRE -592 256 -656 256
WIRE 128 256 128 224
WIRE 208 256 128 256
WIRE 384 272 384 16
WIRE 384 272 272 272
WIRE 432 272 384 272
WIRE 480 272 432 272
WIRE -656 288 -656 256
WIRE 208 288 128 288
WIRE 432 304 432 272
WIRE -592 352 -592 256
WIRE 128 352 128 288
WIRE 240 384 240 304
WIRE 432 416 432 368
WIRE -592 496 -592 432
SYMBOL res 288 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL Opamps\\LT6016 240 272 R0
SYMATTR InstName U1
SYMBOL voltage -592 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCC
SYMATTR Value 15V
SYMBOL res 32 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -592 448 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VEE
SYMATTR Value -15V
SYMBOL cap 416 304 R0
SYMATTR InstName C1
SYMATTR Value {Cload}
SYMBOL voltage 128 64 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName VIN
SYMATTR Value 0V
SYMATTR Value2 AC 1
FLAG 128 352 0
FLAG 480 272 OUT
FLAG -656 288 0
FLAG -592 496 vee
FLAG 240 384 vee
FLAG -592 48 vcc
FLAG 240 208 vcc
FLAG 128 16 fb
FLAG 128 224 inm
FLAG -272 96 0
FLAG 432 416 0
TEXT -616 -336 Left 2 ;https://www.youtube.com/watch?v=YYWlPFBebfc
TEXT 8 -376 Left 2 ;Open loop simulation
TEXT -676 584 Left 2 !.ac oct 100 1e3 10e6
TEXT 16 -336 Left 2 ;Step 1: For open loop simulation, change the closed loop simulation by\nStep 2: 'Break the loop' at opamp negative input\nStep 3: Give the broken nodes unique names, for example 'fb' and 'inm'\nStep 4: Insert a 0V voltage source to close the loop again
TEXT -392 256 Left 2 ;AC=1 Voltage source sets the\ndifference between 'fb' and 'inm', does \nnot force ratio of 'fb' and 'inm'.\n \nRatio 'fb/inm' is determined by \ncircuit open loop gain.
TEXT 16 -224 Left 2 ;Step 5: Give the voltage source an AC=1 stimulus
TEXT -120 536 Left 2 !.step param Cload list 1pF 2200pF