* Z:\home\khalils\Downloads\files\data\raw_asc\58dc55f06ca9_4Winfluence.asc
* Generated by LTspice 26.0.1 for Windows.
* .ac dec 100 1 1MEG
* AC test: \nV7 = AC 1\nV(A)/V(B)
* Distortion: \nI(V1)+I(R5) or .. R10
* R6/C1/R1/DMN62D0UDW: \n100k / 10p / 220:\n< 40nA diff on 100uA range, >130kHz, < 30us stabilized\n..\n10k / 100p / 220:\n< 30nA diff on 100uA range, >130kHz, < 30us stabilized
* mosfet choice is critical: low gate charge, low Ron, low Vgsth
* TODO: search edge behaviour when adding sampler circuits
* 0.9V max
* Opamp RRio, low noise
V7 B A AC 1
V6 N006 N014 SINE(0.25 0.25 1k 1f)
R3 N009 N013 450
R2 A RefN 50m
XM4 N008 N012 0 DMN62D0UDW ;pnba D)G)S
C1 N004 N003 100p
R10 N008 N009 45
R5 N007 N008 5
XM3 N013 N010 0 DMN62D0UDW ;pnba D)G)S
V2 N014 0 0
R4 N013 0 4500
R12 SenseN 0 100
R1 N005 N004 220
XU1 N006 N003 N001 0 N004 TLV9062 ;pnba In+)In-)V+)V-)OUT
V3_1mA N010 0 3
V1 SenseP SenseN 3 Rser=50m
V5 N001 0 3.3
R6 B N003 10k
XM2 N009 N011 0 DMN62D0UDW ;pnba D)G)S
R11 N002 SenseP 100
V8_100mA N012 0 3
V4_10mA N011 0 3
R7 RefN N007 0.5
R8 SenseN 0 10
XM1 N002 N005 A DMN62D0UDW ;pnba D)G)S
R9 SenseP N002 10
.tran 2ms
.include DMN62D0UDW.lib
.include OPAx388.LIB
.include TLV9062.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2884 9200
WIRE 208 -560 -512 -560
WIRE 1376 -544 960 -544
WIRE 1456 -544 1376 -544
WIRE 1856 -544 1536 -544
WIRE 1376 -512 1376 -544
WIRE 208 -496 208 -560
WIRE 176 -480 128 -480
WIRE 336 -464 240 -464
WIRE 368 -464 336 -464
WIRE 912 -464 448 -464
WIRE 176 -448 -368 -448
WIRE 336 -448 336 -464
WIRE 960 -416 960 -448
WIRE 960 -416 688 -416
WIRE 1376 -416 1376 -432
WIRE 1552 -416 1376 -416
WIRE 1856 -416 1856 -544
WIRE 1856 -416 1552 -416
WIRE 128 -384 128 -480
WIRE 336 -384 128 -384
WIRE 128 -320 128 -384
WIRE 224 -320 128 -320
WIRE 448 -320 304 -320
WIRE 464 -320 448 -320
WIRE 560 -320 544 -320
WIRE 688 -320 688 -416
WIRE 688 -320 560 -320
WIRE 960 -304 960 -416
WIRE 1088 -304 960 -304
WIRE 1200 -304 1088 -304
WIRE 960 -272 960 -304
WIRE 960 -176 960 -192
WIRE 1072 -176 960 -176
WIRE 1200 -176 1072 -176
WIRE 960 -160 960 -176
WIRE 960 -48 960 -80
WIRE 960 48 960 32
WIRE 960 48 880 48
WIRE 960 80 960 48
WIRE 880 144 880 48
WIRE 880 144 336 144
WIRE -368 160 -368 -448
WIRE 960 176 960 160
WIRE 960 176 560 176
WIRE 960 208 960 176
WIRE 736 272 -240 272
WIRE 512 288 -96 288
WIRE 288 304 48 304
WIRE 336 336 336 144
WIRE 560 336 560 176
WIRE 960 336 960 288
WIRE 960 336 784 336
WIRE 1504 336 1392 336
WIRE 1776 336 1504 336
WIRE -512 352 -512 -560
WIRE -368 352 -368 240
WIRE -240 352 -240 272
WIRE -96 352 -96 288
WIRE 48 352 48 304
WIRE 960 352 960 336
WIRE 1392 352 1392 336
WIRE 1856 368 1856 -416
WIRE 288 416 288 304
WIRE 512 416 512 288
WIRE 736 416 736 272
WIRE -512 464 -512 432
WIRE -368 464 -368 432
WIRE -368 464 -512 464
WIRE -240 464 -240 432
WIRE -240 464 -368 464
WIRE -96 464 -96 432
WIRE -96 464 -240 464
WIRE 48 464 48 432
WIRE 48 464 -96 464
WIRE 208 464 208 -432
WIRE 208 464 48 464
WIRE 336 464 336 432
WIRE 336 464 208 464
WIRE 560 464 560 432
WIRE 560 464 336 464
WIRE 784 464 784 432
WIRE 784 464 560 464
WIRE 960 464 960 432
WIRE 960 464 784 464
WIRE 1392 464 1392 432
WIRE 1392 464 960 464
WIRE 1472 464 1392 464
WIRE 1776 464 1776 336
WIRE 1776 464 1552 464
WIRE 1856 464 1856 448
WIRE 1856 464 1776 464
SYMBOL res 944 -64 R0
SYMATTR InstName R5
SYMATTR Value 5
SYMBOL voltage -240 336 R0
WINDOW 3 25 89 Left 2
SYMATTR Value 3
SYMATTR InstName V3_1mA
SYMBOL res 320 -336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10k
SYMBOL voltage 48 336 R0
WINDOW 3 24 90 Left 2
SYMATTR Value 3
SYMATTR InstName V8_100mA
SYMBOL nmos 512 336 R0
SYMATTR InstName M2
SYMATTR Value DMN62D0UDW
SYMATTR Prefix X
SYMBOL voltage 1856 352 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMATTR SpiceLine Rser=50m
SYMBOL voltage -368 336 R0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL res 944 192 R0
SYMATTR InstName R3
SYMATTR Value 450
SYMBOL res 944 336 R0
SYMATTR InstName R4
SYMATTR Value 4500
SYMBOL voltage 448 -320 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V7
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL voltage -368 144 R0
SYMATTR InstName V6
SYMATTR Value SINE(0.25 0.25 1k 1f)
SYMBOL res 1376 336 R0
SYMATTR InstName R12
SYMATTR Value 100
SYMBOL nmos 736 336 R0
SYMATTR InstName M3
SYMATTR Value DMN62D0UDW
SYMATTR Prefix X
SYMBOL res 944 -176 R0
SYMATTR InstName R7
SYMATTR Value 0.5
SYMBOL res 1568 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 10
SYMBOL voltage -96 336 R0
WINDOW 3 23 89 Left 2
SYMATTR Value 3
SYMATTR InstName V4_10mA
SYMBOL voltage -512 336 R0
SYMATTR InstName V5
SYMATTR Value 3.3
SYMBOL res 944 64 R0
SYMATTR InstName R10
SYMATTR Value 45
SYMBOL res 944 -288 R0
SYMATTR InstName R2
SYMATTR Value 50m
SYMBOL cap 320 -448 R0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL res 1360 -528 R0
SYMATTR InstName R11
SYMATTR Value 100
SYMBOL res 464 -480 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 220
SYMBOL nmos 912 -544 R0
SYMATTR InstName M1
SYMATTR Value DMN62D0UDW
SYMATTR Prefix X
SYMBOL nmos 288 336 R0
SYMATTR InstName M4
SYMATTR Value DMN62D0UDW
SYMATTR Prefix X
SYMBOL res 1552 -560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 10
SYMBOL OpAmps/opamp2 208 -528 R0
SYMATTR InstName U1
SYMATTR Value TLV9062
FLAG -368 464 0
FLAG 560 -320 A
FLAG 448 -320 B
FLAG 1088 -304 RefP
FLAG 1072 -176 RefN
FLAG 1552 -416 SenseP
FLAG 1504 336 SenseN
TEXT -496 504 Left 2 !.tran 2ms
TEXT -496 528 Left 2 ;.ac dec 100 1 1MEG
TEXT 776 584 Left 2 ;AC test: \nV7 = AC 1\nV(A)/V(B)
TEXT 776 520 Left 2 ;Distortion: \nI(V1)+I(R5) or .. R10
TEXT -344 704 Left 2 ;R6/C1/R1/DMN62D0UDW: \n100k / 10p / 220:\n< 40nA diff on 100uA range, >130kHz, < 30us stabilized\n..\n10k / 100p / 220:\n< 30nA diff on 100uA range, >130kHz, < 30us stabilized
TEXT -88 504 Left 2 !.include DMN62D0UDW.lib
TEXT -88 560 Left 2 !.include OPAx388.LIB\n.include TLV9062.lib
TEXT -88 528 Left 2 ;mosfet choice is critical: low gate charge, low Ron, low Vgsth
TEXT -352 640 Left 2 ;TODO: search edge behaviour when adding sampler circuits
TEXT -200 -464 Left 2 ;0.9V max
TEXT -88 608 Left 2 ;Opamp RRio, low noise