* Z:\home\khalils\Downloads\files\data\raw_asc\5130c7b342c0_stepping_opamp_models1.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N002 N001 +12 -12 out {M} ;pnba In+)In-)V+)V-)OUT
R1 N001 out 20k
R2 0 N001 10k
V1 +12 0 12
V2 -12 0 -12
V3 in 0 PULSE(-2 2 0 1u 1u 99u 200u)
R3 in N002 5k
.tran 0 500u 0 0.1u
* Stepping Subcircuit Models\n \nThe opamp model names must be reduced to pure numbers!\n \nPlease read the restrictions in the left side txet box!
* National Semiconductor, Inc.
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
* | | | | |
*.SUBCKT LM324/NS 1 2 99 50 28
.SUBCKT 324 1 2 99 50 28
*
*Features:
*Eliminates need for dual supplies
*Large DC voltage gain = 100dB
*High bandwidth = 1MHz
*Low input offset voltage = 2mV
*Wide supply range = +-1.5V to +-16V
*
*NOTE: Model is for single device only and simulated
* supply current is 1/4 of total device current.
* Output crossover distortion with dual supplies
* is not modeled.
*
****************INPUT STAGE**************
*
IOS 2 1 5N
*^Input offset current
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
*Fp2=1.2 MHz
C4 5 6 128.27P
*
***********COMMON MODE EFFECT***********
*
I2 99 50 75U
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 2E-3 1
*Input offset voltage.^
R8 99 49 60K
R9 49 50 60K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
*Fp1=7.86 Hz
R5 98 9 101.2433MEG
C3 98 9 200P
*
***************POLE STAGE***************
*
*Fp=2 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX PNP(BF=1.111E3)
*
.ENDS
*$
* .include opampmodel.txt
* Linear Technology
*
* From ltc.lib
*
*.SUBCKT LT1013D 1 2 3 4 5
.SUBCKT 1013 1 2 3 4 5
*
C1 11 12 8.661E-12
C2 6 7 30.00E-12
DC 8 53 DX
DE 54 8 DX
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY(5) VB VC VE VLP VLN 0 2.475E9 -2E9 2E9 2E9 -2E9
GA 6 0 11 12 113.1E-6
GCM 0 6 10 99 225.7E-12
IEE 3 10 DC 12.03E-6
HLIM 90 0 VLIM 1K
Q1 11 102 13 QM1
Q2 12 101 14 QM2
RB1 2 102 400
RB2 1 101 400
DCM1 105 102 DX
DCM2 105 101 DX
VCMC 105 4 DC 0.4
R2 6 9 100.0E3
RC1 4 11 8.841E3
RC2 4 12 8.841E3
RE1 13 10 4.519E3
RE2 14 10 4.519E3
REE 10 99 16.63E6
RO1 8 5 80
RO2 7 99 25
IP 3 4 328E-6
VB 9 0 DC 0
VC 3 53 DC 1.610
VE 54 4 DC .61
VLIM 7 8 DC 0
VLP 91 0 DC 25
VLN 0 92 DC 25
.MODEL DX D(IS=800.0E-18)
.MODEL QM1 PNP (IS=8.000E-16 BF=3.974E+02)
.MODEL QM2 PNP (IS=8.062E-16 BF=4.027E+02)
.ENDS LT1013D
*
.STEP param M list 324 1013
* We use normally .include for adding models.
* I just realized there's a problem with my\nsuggestion. You have to either make sure\nthat subcircuit nodes and subcircuit device\ncurrents aren't saved(Go to Tools=>Control\nPanel=>Save Default and uncheck all but\nthe top check box) or be sure that each\nsubcircuit has exactly the same internal\ntopology as for each step.\n \n--Mike
* Oh, yes, sorry, now I see the problem.\nI will fix it but it's non-trivial so it might\nnot happen until next year. In the meanwhile,\nthe technique will only work if you specify\nwhat nodes you wish to save and each one\nyou specify exists in each .step run. For\nexample, your circuit will run if you add\nthe SPICE directive\n \n.save V(in) V(out) V(n001) V(n002) V(-12) V(+12)\n \nRegards,\n \n--Mike
.save V(in) V(out) V(n001) V(n002) V(-12) V(+12)
* Read the comments on the left about this necessary workaround!
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 2316
WIRE 208 -368 208 -384
WIRE 208 -304 208 -288
WIRE 240 -336 288 -336
WIRE 176 -352 144 -352
WIRE 176 -320 112 -320
WIRE 144 -352 144 -496
WIRE 144 -496 192 -496
WIRE 144 -496 112 -496
WIRE 288 -336 288 -496
WIRE 288 -336 336 -336
WIRE 288 -496 272 -496
WIRE 32 -496 0 -496
WIRE 480 -368 480 -336
WIRE 624 -368 624 -336
WIRE 624 -448 624 -480
WIRE 480 -448 480 -480
WIRE 32 -320 -16 -320
WIRE -16 -320 -16 -272
WIRE -16 -192 -16 -160
WIRE -16 -352 -16 -320
FLAG 0 -496 0
FLAG 208 -384 +12
FLAG 208 -288 -12
FLAG 480 -336 0
FLAG 624 -336 0
FLAG 480 -480 +12
FLAG 624 -480 -12
FLAG -16 -160 0
FLAG 336 -336 out
IOPIN 336 -336 Out
FLAG -16 -352 in
IOPIN -16 -352 Out
SYMBOL Opamps\\opamp2 208 -400 R0
SYMATTR InstName U1
SYMATTR Value {M}
SYMBOL res 176 -480 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 20k
SYMBOL res 16 -480 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 480 -464 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage 624 -464 R0
SYMATTR InstName V2
SYMATTR Value -12
SYMBOL voltage -16 -288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(-2 2 0 1u 1u 99u 200u)
SYMBOL res 16 -304 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 5k
TEXT -24 -624 Left 0 !.tran 0 500u 0 0.1u
TEXT -8 -1024 Left 0 ;Stepping Subcircuit Models\n \nThe opamp model names must be reduced to pure numbers!\n \nPlease read the restrictions in the left side txet box!
TEXT 776 -872 Left 0 !* National Semiconductor, Inc.  \n*\n* connections:      non-inverting input\n*                   |   inverting input\n*                   |   |   positive power supply\n*                   |   |   |   negative power supply\n*                   |   |   |   |   output\n*                   |   |   |   |   |\n*                   |   |   |   |   |\n*.SUBCKT LM324/NS    1   2  99  50  28\n.SUBCKT  324    1   2  99  50  28\n*\n*Features:\n*Eliminates need for dual supplies\n*Large DC voltage gain =             100dB\n*High bandwidth =                     1MHz\n*Low input offset voltage =            2mV\n*Wide supply range =        +-1.5V to +-16V\n*\n*NOTE: Model is for single device only and simulated\n*      supply current is 1/4 of total device current.\n*      Output crossover distortion with dual supplies\n*      is not modeled.\n*\n****************INPUT STAGE**************\n*\nIOS 2 1 5N\n*^Input offset current\nR1 1 3 500K\nR2 3 2 500K\nI1 99 4 100U\nR3 5 50 517\nR4 6 50 517\nQ1 5 2 4 QX\nQ2 6 7 4 QX\n*Fp2=1.2 MHz\nC4 5 6 128.27P\n*\n***********COMMON MODE EFFECT***********\n*\nI2 99 50 75U\n*^Quiescent supply current\nEOS 7 1 POLY(1) 16 49 2E-3 1\n*Input offset voltage.^\nR8 99 49 60K\nR9 49 50 60K\n*\n*********OUTPUT VOLTAGE LIMITING********\nV2 99 8 1.63\nD1 9 8 DX\nD2 10 9 DX\nV3 10 50 .635\n*\n**************SECOND STAGE**************\n*\nEH 99 98 99 49 1\nG1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459\n*Fp1=7.86 Hz\nR5 98 9 101.2433MEG\nC3 98 9 200P\n*\n***************POLE STAGE***************\n*\n*Fp=2 MHz\nG3 98 15 9 49 1E-6\nR12 98 15 1MEG\nC5 98 15 7.9577E-14\n*\n*********COMMON-MODE ZERO STAGE*********\n*\n*Fpcm=10 KHz\nG4 98 16 3 49 5.6234E-8               \nL2 98 17 15.9M\nR13 17 16 1K\n*\n**************OUTPUT STAGE**************\n*\nF6 50 99 POLY(1) V6 300U 1\nE1 99 23 99 15 1\nR16 24 23 17.5\nD5 26 24 DX\nV6 26 22 .63V\nR17 23 25 17.5\nD6 25 27 DX\nV7 22 27 .63V\nV5 22 21 0.27V\nD4 21 15 DX\nV4 20 22 0.27V\nD3 15 20 DX\nL3 22 28 500P\nRL3 22 28 100K\n*\n***************MODELS USED**************\n*\n.MODEL DX D(IS=1E-15)\n.MODEL QX PNP(BF=1.111E3)\n*\n.ENDS\n*$
TEXT -24 -680 Left 0 ;.include  opampmodel.txt
TEXT -24 88 Left 0 !* Linear Technology\n*\n* From ltc.lib\n*\n*.SUBCKT LT1013D    1 2 3 4 5\n.SUBCKT 1013   1 2 3 4 5\n*\nC1 11 12 8.661E-12\nC2 6 7 30.00E-12\nDC 8 53 DX\nDE 54 8 DX\nDLP 90 91 DX\nDLN 92 90 DX\nDP 4 3 DX\nEGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5\nFB 7 99 POLY(5) VB VC VE VLP VLN 0 2.475E9 -2E9 2E9 2E9 -2E9\nGA 6 0 11 12 113.1E-6\nGCM 0 6 10 99 225.7E-12\nIEE 3 10 DC 12.03E-6\nHLIM 90 0 VLIM 1K\nQ1 11 102 13 QM1\nQ2 12 101 14 QM2\nRB1 2 102 400\nRB2 1 101 400\nDCM1 105 102 DX\nDCM2 105 101 DX\nVCMC 105 4 DC 0.4\nR2 6 9 100.0E3\nRC1 4 11 8.841E3\nRC2 4 12 8.841E3\nRE1 13 10 4.519E3\nRE2 14 10 4.519E3\nREE 10 99 16.63E6\nRO1 8 5 80\nRO2 7 99 25\nIP 3 4 328E-6\nVB 9 0 DC 0\nVC 3 53 DC 1.610\nVE 54 4 DC .61\nVLIM 7 8 DC 0\nVLP 91 0 DC 25\nVLN 0 92 DC 25\n.MODEL DX D(IS=800.0E-18)\n.MODEL QM1 PNP (IS=8.000E-16 BF=3.974E+02)\n.MODEL QM2 PNP (IS=8.062E-16 BF=4.027E+02)\n.ENDS LT1013D\n*
TEXT -24 -752 Left 0 !.STEP param M list 324 1013
TEXT -24 -712 Left 0 ;We use normally  .include   for adding models.
TEXT -576 -896 Left 0 ;I just realized there's a problem with my\nsuggestion. You have to either make sure\nthat subcircuit nodes and subcircuit device\ncurrents aren't saved(Go to Tools=>Control\nPanel=>Save Default and uncheck all but\nthe top check box) or be sure that each\nsubcircuit has exactly the same internal\ntopology as for each step.\n \n--Mike
TEXT -576 -552 Left 0 ;Oh, yes, sorry, now I see the problem.\nI will fix it but it's non-trivial so it might\nnot happen until next year.  In the meanwhile,\nthe technique will only work if you specify\nwhat nodes you wish to save and each one\nyou specify exists in each .step run.  For\nexample, your circuit will run if you add\nthe SPICE directive\n \n.save V(in) V(out) V(n001) V(n002) V(-12) V(+12)\n \nRegards,\n \n--Mike
TEXT -8 -816 Left 0 !.save V(in) V(out) V(n001) V(n002) V(-12) V(+12)
TEXT -8 -856 Left 0 ;Read the comments on the left about this necessary workaround!