* Z:\home\khalils\Downloads\files\data\raw_asc\LTC7132.asc
* Generated by LTspice 26.0.1 for Windows.
* Please read the following notes carefully since the model behaves differently from the user \ninterface for the LTC7132.\n \n(1) PMBus communication and memory address related functions and pins are not modeled.\n \n(2) Changes to parameter values while the simulation is running will not take effect unless the\nsimulation is stopped and restarted. This is different from the way the part operates which will\nrespond to the changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time-related parameters.\n \n(4)The following parameters can be defined by right-clicking on the LTC7132 symbol.\nThe nomenclature used here differs from the one in the data sheet. If any value of these parameters is\nset beyond the scope described in the data sheet, the resulting simulation will not be meaningful.\n \n VIN_ON & VIN_OFF -- in volts, set the unit start/stop input voltages; \n Freq -- in Hz, sets switching frequency as one of values of 250k, 350k, 425k, 500k, 575k, 650k, \n 750k,1000k. Freq_cfg pin needs to float or short to VDD25, to make the value be in effect;\n Sync -- value that sets the switching frequency phase offset with respect to the falling edge of the SYNC signal; \n Certain combinations are restricted as in data sheet. Phase_cfg pin needs to float or \n short to VDD25, to make the value be in effect; \n Sync THETA_SYNC TO THETA_0 THETA_SYNC TO THETA_1\n 0 0 180 \n 1 90 270 \n 2 0 240 \n 3 0 120 \n 4 120 240 \n 5 60 240 \n 6 120 300\n Ton0_delay & Ton0_rise; Ton1_delay & Ton1_rise -- in sec, set delay and soft-start timers for \n channel0 and channel1. Initialization time is not modeled; \n Toff0_delay & Toff0_fall; Toff1_delay & Toff1_fall -- in sec, set delay and soft-off timers for \n channel0 and channel1;\n Vout_0 & Vout_1 -- in volt, set output voltages respectively. Vout_cfgn pin needs to float or \n short to VDD25, to make the value be in effect;\n Vout0_range & Vout1_range -- set maximum output range, with value 0\n for 4.096V (CH0) and 5.5V (CH1), value 1 for 2.75V;\n Ilim0_range & Ilim1_range -- set maximum sensed peak current range, with value 0\n for low (45.14mV), and 1 for high (81.25mV);\n OC_limit0 & OC_limit1 -- set ratio of peak current limit to the maximum value defined by Ilimit_range. \n It must be one of values: 0.5, 0.572, 0.642, 0.714, 0.786, 0.858, 0.928, 1;\n Mode_II -- sets light load operation mode: 0 for discontinuous, 1 for forced continuous;\n Fault_response -- sets the response mode of the LTC7132 to occuring faults:\n 0 for ignore, 1 for latch up, 2 for Hiccup after Retry_delay time;\n Retry_delay -- in sec, sets the timer before the LTC7132 turns on after a fault;\n gm -- transconductance of the error amplifier. It must be between 1m mho and 5.73m mho;\n Rth -- Compensation resistor. It must be set between 0k ohms and 62k ohms;\n LowDCR -- set to 1 if DCR is below 1m ohm and make RC = L/(5*DCR), set to 0 if DCR is above \n 1m ohm and make RC = L/DCR.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC7132.asy)
R12 OUT0 0 0.06
R8 N014 N013 20K
C12 N019 0 1
V1 IN 0 12
C9 OUT0 0 330 m=2 Rser=5m
C8 N007 OUT0 0.22
R3 N007 N005 931
R1 N004 N006 931
L1 N005 OUT0 0.33 Rser=0.32m
C10 N008 0 220p
C1 0 N001 1
C3 N006 OUT1 0.22
R10 N014 N012 24.9K
R2 OUT1 0 0.05
R5 N018 N019 10K
C5 OUT1 0 330 m=2 Rser=5m
C4 N009 0 220p
C13 N014 0 1
D1 N001 N002 CMDSH2-3
C6 N011 0 4700p
C2 N004 N002 0.1
R4 N016 N019 10K
R7 N013 0 17.8K
C11 N010 0 2200p
R6 N017 N019 4.99K
D2 N001 N003 CMDSH2-3
XU1 OUT0 0 N006 OUT1 N011 N009 N007 OUT0 OUT1 0 N017 N003 N005 N002 N004 N001 N018 N016 NC_01 NC_02 N013 N012 NC_03 N014 N014 IN 0 N019 N008 N010 0 0 LTC7132 VIN_ON=5.5 VIN_OFF=5 Vout_0=1.6 Vout_1=2.5 Ilim0_range=0 Ilim1_range=0 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K LowDcr=1 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 Sync=0 ;pnba Vsense0+)Vsense0-)Isense1+)Isense1-)IthR0)Ith0)Isense0+)Isense0-)Vsense1+)Vsense1-)SYNC)Boost0)SW0)Boost1)SW1)IntVcc)Run0)Run1)PGood0)PGood1)Vout_cfg0)Vout_cfg1)Freq_cfg)Phase_cfg)VDD25)Vin)ExtVcc)VDD33)Ith1)IthR1)PGND)SGND
L2 N004 OUT1 0.33 Rser=0.32m
R9 N012 0 7.32K
C7 N005 N003 0.1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.2m startup
.lib LTC7132.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4148 1720
WIRE 288 -352 256 -352
WIRE 720 -352 288 -352
WIRE 256 -336 256 -352
WIRE 512 -304 416 -304
WIRE 816 -304 512 -304
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WIRE 416 -288 416 -304
WIRE 512 -272 512 -304
WIRE 1232 -272 1232 -304
WIRE 256 -240 256 -256
WIRE 720 -240 720 -352
WIRE 816 -240 816 -304
WIRE 912 -240 912 -256
WIRE 1008 -240 1008 -256
WIRE 1104 -240 1104 -256
WIRE 416 -208 416 -224
WIRE 512 -160 512 -208
WIRE 656 -160 512 -160
WIRE 1232 -160 1232 -208
WIRE 1232 -160 1168 -160
WIRE 512 -144 512 -160
WIRE 1232 -144 1232 -160
WIRE 96 -64 48 -64
WIRE 160 -64 96 -64
WIRE 256 -64 160 -64
WIRE 288 -64 256 -64
WIRE 416 -64 368 -64
WIRE 512 -64 512 -80
WIRE 512 -64 416 -64
WIRE 656 -64 512 -64
WIRE 1232 -64 1232 -80
WIRE 1232 -64 1168 -64
WIRE 1408 -64 1232 -64
WIRE 1456 -64 1408 -64
WIRE 1568 -64 1536 -64
WIRE 1616 -64 1568 -64
WIRE 1696 -64 1616 -64
WIRE 1744 -64 1696 -64
WIRE 48 -48 48 -64
WIRE 160 -48 160 -64
WIRE 1616 -48 1616 -64
WIRE 1744 -48 1744 -64
WIRE 416 32 416 -64
WIRE 448 32 416 32
WIRE 560 32 528 32
WIRE 656 32 560 32
WIRE 1232 32 1168 32
WIRE 1296 32 1232 32
WIRE 1408 32 1408 -64
WIRE 1408 32 1376 32
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WIRE 560 48 560 32
WIRE 1232 48 1232 32
WIRE 1616 48 1616 16
WIRE 1744 48 1744 32
WIRE 256 128 256 -64
WIRE 560 128 560 112
WIRE 560 128 256 128
WIRE 656 128 560 128
WIRE 1232 128 1232 112
WIRE 1232 128 1168 128
WIRE 1568 128 1568 -64
WIRE 1568 128 1232 128
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WIRE 656 224 256 224
WIRE 1568 224 1568 128
WIRE 1568 224 1168 224
WIRE 656 320 592 320
WIRE 1200 320 1168 320
WIRE 528 416 496 416
WIRE 656 416 592 416
WIRE 1200 416 1168 416
WIRE 1296 416 1264 416
WIRE 528 512 496 512
WIRE 656 512 592 512
WIRE 1200 512 1168 512
WIRE 1296 512 1264 512
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WIRE 544 608 512 608
WIRE 656 608 544 608
WIRE 1248 608 1168 608
WIRE 1312 608 1248 608
WIRE 1424 608 1392 608
WIRE 1248 688 1248 608
WIRE 656 704 448 704
WIRE 448 752 448 704
WIRE 544 752 544 608
WIRE 448 896 448 832
WIRE 544 896 544 832
WIRE 544 896 448 896
WIRE 816 896 816 864
WIRE 816 896 544 896
WIRE 1248 896 1248 768
WIRE 1248 896 816 896
WIRE 720 912 720 864
WIRE 1008 912 1008 864
WIRE 1104 912 1104 864
WIRE 720 1008 720 992
WIRE 912 1008 912 864
WIRE 912 1008 720 1008
WIRE 1008 1008 1008 992
WIRE 1008 1008 912 1008
WIRE 1104 1008 1104 992
WIRE 1104 1008 1008 1008
WIRE 816 1040 816 896
WIRE 912 1056 912 1008
WIRE 816 1136 816 1104
WIRE 912 1136 912 1120
SYMBOL res 528 848 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R10
SYMATTR Value 24.9K
SYMBOL res 32 -64 R0
SYMATTR InstName R2
SYMATTR Value 0.05
SYMBOL res 992 896 R0
WINDOW 3 30 79 Left 2
SYMATTR Value 4.99K
SYMATTR InstName R6
SYMBOL cap 896 1056 R0
SYMATTR InstName C12
SYMATTR Value 1
SYMBOL cap 1216 -80 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C7
SYMATTR Value 0.1
SYMBOL cap 1600 -48 R0
WINDOW 123 25 59 Left 2
WINDOW 3 35 34 Left 2
SYMATTR Value2 m=2
SYMATTR Value 330
SYMATTR InstName C9
SYMATTR SpiceLine Rser=5m
SYMBOL res 1264 784 R180
WINDOW 0 -9 75 Right 2
WINDOW 3 -9 32 Right 2
SYMATTR InstName R8
SYMATTR Value 20K
SYMBOL schottky 496 -272 R0
WINDOW 3 29 72 Left 2
SYMATTR Value CMDSH2-3
SYMATTR InstName D1
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 1280 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 931
SYMBOL res 1728 -64 R0
SYMATTR InstName R12
SYMATTR Value 0.06
SYMBOL cap 1216 48 R0
SYMATTR InstName C8
SYMATTR Value 0.22
SYMBOL cap 496 -80 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL LTC7132 912 224 R0
SYMATTR InstName U1
SYMBOL cap 800 1040 R0
SYMATTR InstName C13
SYMATTR Value 1
SYMBOL cap 544 48 R0
SYMATTR InstName C3
SYMATTR Value 0.22
SYMBOL res 704 896 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL ind 384 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.33
SYMATTR SpiceLine Rser=0.32m
SYMBOL res 1296 624 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R7
SYMATTR Value 17.8K
SYMBOL cap 1200 400 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 220p
SYMBOL res 528 592 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 7.32K
SYMBOL cap 592 496 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C11
SYMATTR Value 2200p
SYMBOL schottky 1216 -272 R0
SYMATTR Value CMDSH2-3
SYMATTR InstName D2
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 400 -224 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 256 -352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 1088 896 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL res 432 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 931
SYMBOL ind 1440 -48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.33
SYMATTR SpiceLine Rser=0.32m
SYMBOL cap 592 400 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C10
SYMATTR Value 220p
SYMBOL res 432 848 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R13
SYMATTR Value 0
SYMBOL cap 144 -48 R0
WINDOW 123 28 56 Left 2
WINDOW 3 37 32 Left 2
SYMATTR Value2 m=2
SYMATTR Value 330
SYMATTR InstName C5
SYMATTR SpiceLine Rser=5m
SYMBOL cap 1200 496 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 4700p
FLAG 912 -256 0
FLAG 1008 -256 0
FLAG 416 -208 0
FLAG 160 48 0
FLAG 48 48 0
FLAG 96 -64 OUT1
FLAG 288 -352 IN
FLAG 256 -240 0
FLAG 1616 48 0
FLAG 1744 48 0
FLAG 1696 -64 OUT0
FLAG 1104 -256 0
FLAG 1200 320 0
FLAG 592 320 0
FLAG 1296 416 0
FLAG 1296 512 0
FLAG 496 416 0
FLAG 496 512 0
FLAG 912 1136 0
FLAG 1424 608 0
FLAG 400 608 0
FLAG 816 1136 0
TEXT 1448 744 Left 2 !.tran  1.2m startup
TEXT 1824 -336 Left 2 ;Please read the following notes carefully since the model behaves differently from the user \ninterface for the LTC7132.\n \n(1) PMBus communication and memory address related functions and pins are not modeled.\n \n(2) Changes to parameter values while the simulation is running will not take effect unless the\nsimulation is stopped and restarted. This is different from the way the part operates which will\nrespond to the changes while running.  \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time-related parameters.\n \n(4)The following parameters can be defined by right-clicking on the LTC7132 symbol.\nThe nomenclature used here differs from the one in the data sheet. If any value of these parameters is\nset beyond the scope described in the data sheet, the resulting simulation will not be meaningful.\n \n     VIN_ON & VIN_OFF -- in volts, set the unit start/stop input voltages; \n     Freq -- in Hz, sets switching frequency as one of values of 250k, 350k, 425k, 500k, 575k, 650k, \n                 750k,1000k. Freq_cfg pin needs to float or short to VDD25, to make the value be in effect;\n     Sync -- value that sets the switching frequency phase offset with respect to the falling edge of the SYNC signal; \n                Certain combinations are restricted as in data sheet. Phase_cfg pin needs to float or \n                short to VDD25, to make the value be in effect;           \n                   Sync    THETA_SYNC TO THETA_0     THETA_SYNC TO THETA_1\n                  0                           0                                   180 \n                  1                           90                                 270 \n                  2                           0                                   240 \n                  3                           0                                   120 \n                  4                          120                                240 \n                  5                           60                                 240 \n                  6                          120                                300\n      Ton0_delay & Ton0_rise; Ton1_delay & Ton1_rise -- in sec, set delay and soft-start timers for \n                channel0 and channel1. Initialization time is not modeled; \n     Toff0_delay & Toff0_fall; Toff1_delay & Toff1_fall -- in sec, set delay and soft-off timers for \n                channel0 and channel1;\n     Vout_0 & Vout_1 -- in volt, set output voltages respectively. Vout_cfgn pin needs to float or \n                short to VDD25, to make the value be in effect;\n     Vout0_range & Vout1_range -- set maximum output range, with value 0\n                for 4.096V (CH0) and 5.5V (CH1), value 1 for 2.75V;\n     Ilim0_range & Ilim1_range -- set maximum sensed peak current range, with value 0\n               for low (45.14mV), and 1 for high (81.25mV);\n     OC_limit0 & OC_limit1 -- set ratio of peak current limit to the maximum value defined by Ilimit_range. \n               It must be one of values: 0.5, 0.572, 0.642, 0.714, 0.786, 0.858, 0.928, 1;\n     Mode_II -- sets light load operation mode: 0 for discontinuous, 1 for forced continuous;\n     Fault_response -- sets the response mode of the LTC7132 to occuring faults:\n              0 for ignore, 1 for latch up, 2 for Hiccup after Retry_delay time;\n     Retry_delay -- in sec, sets the timer before the LTC7132 turns on after a fault;\n     gm -- transconductance of the error amplifier. It must be between 1m mho and 5.73m mho;\n     Rth -- Compensation resistor. It must be set between 0k ohms and 62k ohms;\n     LowDCR -- set to 1 if DCR is below 1m ohm and make RC = L/(5*DCR), set to 0 if DCR is above \n               1m ohm and make RC = L/DCR.