Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\068bf9d57e20_ADTL084.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADTL084.asy)
Rload OUT 0 10K
V2 -V 0 -15
R1 N001 0 10K
V1 +V 0 15
XU1 IN N001 +V -V OUT ADTL084 ;pnba In+)In-)V+)V-)OUT
R2 OUT N001 10K
Vin IN 0 SINE(0 1 10K)
.tran 1m
.lib ADTL084.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 720 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 720 -1088 720 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 720 -992 720 -1008
WIRE 432 -976 432 -992
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 704 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL opamps\\ADTL084 576 -1168 R0
SYMATTR InstName U1
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 720 -992 0
FLAG 256 -1056 0
TEXT 784 -896 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\2fc95ed4d683_Gates.asc
* Generated by LTspice 26.0.1 for Windows.
A1 0 N001 0 N002 0 V1_NAND_V2 V1_AND_V2 0 AND
A2 0 N001 0 N002 0 V1_NOR_V2 V1_OR_V2 0 OR
A3 N001 0 0 0 0 V1_NOT_V2 0 0 BUF
A4 0 N001 0 N002 0 V1_XNOR_V2 V1_XOR_V2 0 XOR
V1 N001 0 PULSE(0 5 0 5ns 5ns 10ms 20ms)
V2 N002 0 PULSE(0 5 0 5ns 5ns 20ms 40ms)
.tran 240
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 -48 32 -48
WIRE 336 -48 304 -48
WIRE 560 -48 400 -48
WIRE 256 -16 128 -16
WIRE 336 -16 256 -16
WIRE 560 -16 400 -16
WIRE 304 64 304 -48
WIRE 336 64 304 64
WIRE 560 64 400 64
WIRE 256 96 256 -16
WIRE 336 96 256 96
WIRE 560 96 400 96
WIRE 32 192 32 -48
WIRE 304 192 304 64
WIRE 336 192 304 192
WIRE 560 192 400 192
WIRE 128 208 128 -16
WIRE 304 272 304 192
WIRE 336 272 304 272
WIRE 560 272 400 272
WIRE 256 304 256 96
WIRE 336 304 256 304
WIRE 560 304 416 304
IOPIN 560 -48 Out
IOPIN 560 -16 Out
IOPIN 560 64 Out
IOPIN 560 96 Out
IOPIN 560 192 Out
IOPIN 560 272 Out
IOPIN 560 304 Out
SYMBOL Digital\\or 368 16 R0
SYMATTR InstName A2
SYMBOL voltage 128 192 R0
WINDOW 3 -168 113 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 5ns 5ns 20ms 40ms)
SYMBOL Digital\\and 368 -96 R0
SYMATTR InstName A1
SYMBOL voltage 32 176 R0
WINDOW 3 -304 74 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 5ns 5ns 10ms 20ms)
SYMBOL Digital\\xor 384 224 R0
SYMATTR InstName A4
SYMBOL Digital\\inv 336 128 R0
SYMATTR InstName A3
FLAG 32 272 0
FLAG 128 288 0
FLAG 560 -48 V1_AND_V2
FLAG 560 -16 V1_NAND_V2
FLAG 560 64 V1_OR_V2
FLAG 560 96 V1_NOR_V2
FLAG 560 192 V1_NOT_V2
FLAG 560 272 V1_XOR_V2
FLAG 560 304 V1_XNOR_V2
TEXT -308 380 Left 2 !.tran 240
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1185.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1185.asy)
V1 0 IN 7.5
XU1 0 N002 IN OUT N001 LT1185 ;pnba GND)FB)IN)OUT)Ref
C1 0 OUT 2.2 Rser=1
I1 0 OUT pulse(.95 1.05 2u 10n 10n 8u 16u)
R1 0 N001 4.3K
R2 0 N002 2.37K
R3 N002 OUT 2.67K
.tran 16u
.lib LT1185.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1140 680
WIRE 0 64 0 48
WIRE 400 64 400 48
WIRE 224 96 224 48
WIRE -128 112 -128 48
WIRE 640 112 640 48
WIRE 528 128 528 48
WIRE 0 160 0 144
WIRE 96 160 0 160
WIRE 400 160 400 144
WIRE 400 160 352 160
WIRE 400 176 400 160
WIRE -128 272 -128 192
WIRE 96 272 -128 272
WIRE 400 272 400 256
WIRE 400 272 352 272
WIRE 528 272 528 192
WIRE 528 272 400 272
WIRE 640 272 640 192
WIRE 640 272 528 272
SYMBOL res 384 160 R0
SYMATTR InstName R3
SYMATTR Value 2.67K
SYMBOL cap 512 128 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=1
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL res 384 48 R0
SYMATTR InstName R2
SYMATTR Value 2.37K
SYMBOL PowerProducts\\LT1185 224 208 R0
SYMATTR InstName U1
SYMBOL voltage -128 96 R0
SYMATTR InstName V1
SYMATTR Value 7.5
SYMBOL res -16 48 R0
SYMATTR InstName R1
SYMATTR Value 4.3K
SYMBOL current 640 112 R0
SYMATTR InstName I1
SYMATTR Value pulse(.95 1.05 2u 10n 10n 8u 16u)
FLAG 0 48 0
FLAG 400 48 0
FLAG 224 48 0
FLAG -128 48 0
FLAG 640 48 0
FLAG 528 48 0
FLAG -128 272 IN
FLAG 640 272 OUT
TEXT 744 264 Left 2 !.tran 16u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3523.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3523.asy)
Rload1 OUT1 0 16.5
R3 OUT2 N003 511K
R1 OUT1 N004 634K
Rload2 OUT2 0 6
R4 N003 0 511K
L1 IN N001 4.7
V1 IN 0 2
C1 OUT1 0 10
C3 OUT2 N003 10p
R2 N004 0 365K
C2 OUT2 0 10
XU1 N004 IN NC_01 OUT1 N001 0 0 N002 IN NC_02 NC_03 N003 IN 0 IN IN LTC3523 ;pnba FB1)Vin1)Pgood1)Vout)SW1)GND1)GND2)SW2)Vin2)Mode)Pgood2)FB2)_SHDN2)GND3)Vbat)_SHDN1
L2 N002 OUT2 4.7
.tran .6m startup
.lib LTC3523.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 0 -64 -96 -64
WIRE 160 -64 0 -64
WIRE 240 -64 160 -64
WIRE 320 -64 240 -64
WIRE 400 -64 320 -64
WIRE -96 -48 -96 -64
WIRE 160 -48 160 -64
WIRE 240 -48 240 -64
WIRE 320 -48 320 -64
WIRE 0 16 0 -64
WIRE 96 16 0 16
WIRE 400 16 400 -64
WIRE 400 16 384 16
WIRE 0 32 0 16
WIRE -96 48 -96 32
WIRE 0 128 0 112
WIRE 96 128 0 128
WIRE 400 128 384 128
WIRE 512 128 480 128
WIRE 576 128 512 128
WIRE 672 128 576 128
WIRE 752 128 672 128
WIRE 576 144 576 128
WIRE 672 144 672 128
WIRE 752 144 752 128
WIRE 512 160 512 128
WIRE -80 240 -224 240
WIRE 0 240 -80 240
WIRE 96 240 0 240
WIRE 512 240 512 224
WIRE 512 240 384 240
WIRE 576 240 576 224
WIRE 576 240 512 240
WIRE 672 240 672 208
WIRE 752 240 752 224
WIRE -224 256 -224 240
WIRE -80 256 -80 240
WIRE 0 256 0 240
WIRE 576 256 576 240
WIRE -224 352 -224 336
WIRE -80 352 -80 320
WIRE 0 352 0 336
WIRE 96 352 0 352
WIRE 576 352 576 336
WIRE 0 368 0 352
WIRE 0 464 0 448
WIRE 160 544 160 528
WIRE 240 544 240 528
WIRE 320 544 320 528
SYMBOL cap 656 144 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL ind -16 16 R0
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL ind 384 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 4.7
SYMBOL cap -96 256 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res -16 352 R0
SYMATTR InstName R2
SYMATTR Value 365K
SYMBOL PowerProducts\\LTC3523 240 240 R0
SYMATTR InstName U1
SYMBOL res -16 240 R0
SYMATTR InstName R1
SYMATTR Value 634K
SYMBOL res 560 240 R0
SYMATTR InstName R4
SYMATTR Value 511K
SYMBOL res -240 240 R0
SYMATTR InstName Rload1
SYMATTR Value 16.5
SYMBOL cap 496 160 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL res 736 128 R0
SYMATTR InstName Rload2
SYMATTR Value 6
SYMBOL voltage -96 -64 R0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL res 560 128 R0
SYMATTR InstName R3
SYMATTR Value 511K
FLAG 240 544 0
FLAG 160 544 0
FLAG 320 544 0
FLAG -96 48 0
FLAG 0 464 0
FLAG -80 352 0
FLAG -224 352 0
FLAG 576 352 0
FLAG 672 240 0
FLAG 752 240 0
FLAG -96 -64 IN
FLAG -224 240 OUT1
FLAG 752 128 OUT2
TEXT 512 448 Left 2 !.tran .6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3311S.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3311S.asy)
R4 N006 N005 1K
V1 IN 0 5
Rload OUT 0 0.3
C1 OUT 0 22 m=2 Rser=10m
L1 N002 OUT 200n Rser=2m
XU1 IN IN N002 N004 0 0 N007 N001 IN N006 N003 LTC3311S ;pnba VIN)EN)SW)FB)AGND)PGND)RT)PGOOD)MODE/SYNC)ITH)SSTT
C2 N003 0 4.7n
R5 N007 0 274K
R2 N004 0 100K
R3 OUT N001 500K
C3 N005 0 1500p
R1 OUT N004 562K
C5 OUT N004 10p
.tran 1.2m startup
.step temp list 25 100 150
.lib LTC3311S.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2648 1864
WIRE 1408 1248 1376 1248
WIRE 1520 1248 1408 1248
WIRE 1712 1248 1520 1248
WIRE 1376 1280 1376 1248
WIRE 1712 1280 1712 1248
WIRE 1520 1328 1520 1248
WIRE 1552 1328 1520 1328
WIRE 1904 1328 1872 1328
WIRE 2016 1328 1984 1328
WIRE 1376 1376 1376 1360
WIRE 1520 1424 1520 1328
WIRE 1552 1424 1520 1424
WIRE 1904 1424 1872 1424
WIRE 2016 1424 2016 1328
WIRE 2016 1424 1984 1424
WIRE 2144 1424 2016 1424
WIRE 2256 1424 2144 1424
WIRE 2336 1424 2256 1424
WIRE 2384 1424 2336 1424
WIRE 2144 1440 2144 1424
WIRE 2256 1440 2256 1424
WIRE 2384 1440 2384 1424
WIRE 1424 1520 1408 1520
WIRE 1552 1520 1488 1520
WIRE 2016 1520 2016 1504
WIRE 2016 1520 1872 1520
WIRE 2144 1520 2144 1504
WIRE 2144 1520 2016 1520
WIRE 2016 1536 2016 1520
WIRE 2256 1536 2256 1504
WIRE 2384 1536 2384 1520
WIRE 1424 1616 1360 1616
WIRE 1552 1616 1504 1616
WIRE 1904 1616 1872 1616
WIRE 1360 1632 1360 1616
WIRE 1904 1632 1904 1616
WIRE 2016 1632 2016 1616
WIRE 1648 1680 1648 1664
WIRE 1776 1680 1776 1664
WIRE 1360 1712 1360 1696
WIRE 1904 1728 1904 1712
SYMBOL RES 2000 1408 R0
SYMATTR InstName R1
SYMATTR Value 562K
SYMBOL res 2000 1520 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 1888 1616 R0
SYMATTR InstName R5
SYMATTR Value 274K
SYMBOL cap 1488 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL res 2368 1424 R0
SYMATTR InstName Rload
SYMATTR Value 0.3
SYMBOL VOLTAGE 1376 1264 R0
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL ind 1888 1440 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 200n
SYMATTR SpiceLine Rser=2m
SYMBOL res 2000 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500K
SYMBOL cap 2240 1440 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 m=2
SYMATTR InstName C1
SYMATTR Value 22
SYMATTR SpiceLine Rser=10m
SYMBOL cap 2128 1440 R0
SYMATTR InstName C5
SYMATTR Value 10p
SYMBOL LTC3311S 1712 1456 R0
SYMATTR InstName U1
SYMBOL cap 1344 1632 R0
SYMATTR InstName C3
SYMATTR Value 1500p
SYMBOL res 1520 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1K
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1376 1376 0
FLAG 2384 1536 0
FLAG 2016 1632 0
FLAG 1408 1520 0
FLAG 2336 1424 OUT
FLAG 1408 1248 IN
FLAG 1360 1712 0
FLAG 2256 1536 0
FLAG 1904 1728 0
TEXT 2104 1760 Left 2 !.tran 1.2m startup
TEXT 2104 1720 Left 2 !.step temp list 25 100 150
* Z:\home\khalils\Downloads\files\data\raw_asc\02f8fc9ff5c3_1638.asc
* Generated by LTspice 26.0.1 for Windows.
* Positive Supply Rail Current Sense
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1638.asy)
R4 N003 N002 200
R2 +V N002 .2
R3 N001 +V 200
V1 +V 0 5
XU1 N001 N003 +V 0 N004 LT1638 ;pnba In+)In-)V+)V-)OUT
R1 OUT 0 2K
Q1 N001 N004 OUT 0 2N3904
I1 N002 0 SINE(1 1 1K)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -80 80 -80 64
WIRE -32 80 -80 80
WIRE 64 80 48 80
WIRE 288 80 64 80
WIRE -80 112 -80 80
WIRE -288 160 -288 144
WIRE 288 176 288 80
WIRE 128 192 128 176
WIRE -80 208 -80 192
WIRE -32 208 -80 208
WIRE 96 208 48 208
WIRE 224 224 160 224
WIRE -80 240 -80 208
WIRE 64 240 64 80
WIRE 96 240 64 240
WIRE -288 256 -288 240
WIRE 128 272 128 256
WIRE 288 288 288 272
WIRE 368 288 288 288
WIRE 288 304 288 288
WIRE -80 352 -80 320
WIRE 288 400 288 384
SYMBOL res -96 96 R0
SYMATTR InstName R2
SYMATTR Value .2
SYMBOL npn 224 176 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 64 192 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL res 64 64 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 200
SYMBOL current -80 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value SINE(1 1 1K)
SYMBOL opamps\\LT1638 128 160 R0
SYMATTR InstName U1
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 272 288 R0
SYMATTR InstName R1
SYMATTR Value 2K
FLAG -288 256 0
FLAG 128 176 +V
FLAG -288 144 +V
FLAG 128 272 0
FLAG 288 400 0
FLAG -80 64 +V
FLAG -80 352 0
FLAG 368 288 OUT
TEXT 376 368 Left 0 !.tran 3m
TEXT 128 -16 Bottom 0 ;Positive Supply Rail Current Sense
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1963-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 1K
XU1 IN IN 0 OUT OUT LT1963-2.5 ;pnba _SHDN)IN)GND)OUT)SENSE
C1 OUT 0 10 Rser=50m
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1963-2.5.asy)
.lib LT1963.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 352 48 320 48
WIRE 400 48 352 48
WIRE 560 48 400 48
WIRE -208 64 -208 48
WIRE 400 64 400 48
WIRE 560 64 560 48
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 400 160 400 128
WIRE 560 160 560 144
WIRE 176 240 176 208
FLAG -208 160 0
FLAG 400 160 0
FLAG 560 160 0
FLAG 176 240 0
FLAG 560 48 OUT
FLAG -208 48 IN
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 544 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL PowerProducts\\LT1963-2.5 176 96 R0
SYMATTR InstName U1
SYMBOL cap 384 64 R0
WINDOW 3 40 33 Left 2
WINDOW 39 24 59 Left 2
SYMATTR Value 10
SYMATTR SpiceLine Rser=50m
SYMATTR InstName C1
TEXT 368 208 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\3c3562e84cb3_BJT_character.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 IC N003 0 0 BC547B
R1 N001 IC 62k
Vce N001 0 1
Vbe N002 0 0
R2 N003 N002 2k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc Vbe 0 1 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 96 240 96
WIRE 320 96 256 96
WIRE 432 96 400 96
WIRE 432 128 432 96
WIRE 64 144 16 144
WIRE 176 144 144 144
WIRE 16 160 16 144
WIRE 16 288 16 240
WIRE 240 288 240 192
WIRE 432 288 432 208
FLAG 432 288 0
FLAG 240 288 0
FLAG 16 288 0
FLAG 256 96 IC
SYMBOL npn 176 96 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL res 416 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 62k
SYMBOL voltage 432 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vce
SYMATTR Value 1
SYMBOL voltage 16 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vbe
SYMATTR Value 0
SYMBOL res 160 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 2k
TEXT 24 336 Left 2 !.dc Vbe 0 1 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1174HV-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1174HV-3.3.asy)
XU1 OUT N003 N002 0 N001 IN IN IN LTC1174 top=51K bot=31.5K ;pnba FB)LBout)LBin)GND)SW)Vin)Ipgm)_SHDN
L1 N001 OUT 100 Rser=0.02 Rpar=5000
V1 IN 0 9
D1 0 N001 MBRS140
Rload OUT 0 10
C2 OUT 0 100 Rser=0.02
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2.5m startup
.lib LTC1174.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1584 1140
WIRE 464 480 352 480
WIRE 624 480 464 480
WIRE 352 496 352 480
WIRE 624 512 624 480
WIRE 464 560 464 480
WIRE 496 560 464 560
WIRE 816 560 752 560
WIRE 864 560 816 560
WIRE 976 560 944 560
WIRE 1056 560 976 560
WIRE 816 576 816 560
WIRE 1056 576 1056 560
WIRE 352 592 352 576
WIRE 496 624 480 624
WIRE 768 624 752 624
WIRE 816 656 816 640
WIRE 1056 672 1056 656
WIRE 464 688 464 560
WIRE 496 688 464 688
WIRE 976 688 976 560
WIRE 976 688 752 688
WIRE 976 704 976 688
WIRE 624 752 624 736
WIRE 976 784 976 768
SYMBOL IND 848 576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL PowerProducts\\LTC1174HV-3.3 624 624 R0
SYMATTR InstName U1
SYMBOL POLCAP 960 704 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL VOLTAGE 352 480 R0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL SCHOTTKY 800 640 M180
WINDOW 0 33 60 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL res 1040 560 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 1056 560 OUT
FLAG 976 784 0
FLAG 1056 672 0
FLAG 816 656 0
FLAG 624 752 0
FLAG 352 592 0
FLAG 352 480 IN
TEXT 728 760 Left 2 !.tran 2.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG5212.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nQinj not included\nOn resistance modeled at 15V supplies\nOny one channel is modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG5212.asy)
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
C1 vD 0 36p
V1 vS 0 SINE(0 10 20)
V3 v+ 0 15
V4 v- 0 -15
R1 vD 0 301
XU1 vIN vD vS v- 0 v+ ADG5212 ;pnba IN)D)S)Vss)GND)Vdd
.tran 1
.lib ADG5212.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 240 144 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE 304 416 304 400
WIRE 176 432 176 400
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL ADG5212 240 272 R0
SYMATTR InstName U1
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 20)
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 304 416 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -288 304 v+
FLAG 240 112 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -192 304 v-
FLAG 176 432 v-
TEXT 80 528 Left 2 !.tran 1
TEXT -320 -8 Left 2 ;Note:\nSwitch shown for a logic 0 input\nQinj not included\nOn resistance modeled at 15V supplies\nOny one channel is modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\ADGS6414D.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSPI functionality is not included\nCharge Injection and Pin Capacitance are not modeled\nOny one channel is modeled\nSwitch shown for a logic 0 input\nParameter performance modeled at 20V dual supply
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADGS6414D.asy)
V1 vS 0 SINE(0 15 25)
V4 v- 0 -20
V2 vIN 0 PULSE(0 3 0 1n 1n 100m 200m)
R1 vD 0 301
V3 v+ 0 20
XU1 v+ vIN v- vS vD 0 ADGS6414D ;pnba Vdd)IN)Vss)S)D)GND
C1 vD 0 36p
.tran 0.5
.lib ADGS6414D.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 112 240 112
WIRE 240 160 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -352 352 -368 352
WIRE -128 352 -144 352
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE -368 432 -368 352
WIRE -144 432 -144 352
WIRE 48 432 48 288
WIRE 192 432 192 400
WIRE 192 432 176 432
WIRE 288 432 288 400
WIRE -368 560 -368 512
WIRE -144 560 -144 512
WIRE 48 560 48 512
SYMBOL voltage -368 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 20
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 15 25)
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -144 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -20
SYMBOL ADGS6414D 240 272 R0
SYMATTR InstName U1
SYMBOL voltage 48 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 23 115 Left 2
SYMATTR Value PULSE(0 3 0 1n 1n 100m 200m)
SYMATTR InstName V2
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG -112 224 0
FLAG 48 560 0
FLAG 464 352 0
FLAG 288 432 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -368 352 v+
FLAG 240 112 v+
FLAG -368 560 0
FLAG -144 352 v-
FLAG -144 560 0
FLAG 192 432 v-
TEXT 416 456 Left 2 !.tran 0.5
TEXT -368 -80 Left 2 ;Notes:\nSPI functionality is not included\nCharge Injection and Pin Capacitance are not modeled\nOny one channel is modeled\nSwitch shown for a logic 0 input\nParameter performance modeled at 20V dual supply
* Z:\home\khalils\Downloads\files\data\raw_asc\30052fe8f907_CurrentSource_10uA.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N002 N001 VDD VDD PMOS l=5 w=70
M2 N001 N001 VDD VDD PMOS l=5 w=70
V3 0 N002 2.5V
V1 0 VSS 2.5V
V2 VDD 0 2.5V
R1 N001 VSS 380K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL PMOS PMOS(VT0=-0.91 LAMBDA=0.06 KP=17U)
.dc V3 2.5 -2.5 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -96 64 -96 32
WIRE 240 80 240 48
WIRE 240 80 112 80
WIRE 368 80 240 80
WIRE 112 128 112 80
WIRE 128 128 112 128
WIRE 368 128 368 80
WIRE 368 128 352 128
WIRE 208 144 176 144
WIRE 304 144 208 144
WIRE 112 176 112 128
WIRE 128 176 112 176
WIRE 368 176 368 128
WIRE 368 176 352 176
WIRE -96 192 -96 144
WIRE -96 192 -208 192
WIRE -96 240 -96 192
WIRE -208 256 -208 192
WIRE 128 256 128 224
WIRE 208 256 208 144
WIRE 208 256 128 256
WIRE 128 288 128 256
WIRE 352 304 352 224
WIRE -96 368 -96 320
WIRE 128 400 128 368
WIRE 352 432 352 384
SYMBOL pmos4 304 224 M180
SYMATTR InstName M1
SYMATTR Value2 l=5 w=70
SYMBOL pmos4 176 224 R180
SYMATTR InstName M2
SYMATTR Value2 l=5 w=70
SYMBOL voltage -96 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5V
SYMBOL voltage -96 48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 2.5V
SYMBOL voltage 352 400 R180
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 2.5V
SYMBOL res 112 272 R0
SYMATTR InstName R1
SYMATTR Value 380K
FLAG 352 432 0
FLAG -208 256 0
FLAG -96 32 VDD
FLAG -96 368 VSS
FLAG 240 48 VDD
FLAG 128 400 VSS
TEXT -192 -120 Left 2 !.MODEL PMOS PMOS(VT0=-0.91 LAMBDA=0.06 KP=17U)
TEXT -56 -64 Left 2 !.dc V3 2.5 -2.5 0.05