Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\5f20b6ab39f4_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 NC_01 NC_02 NC_03 0 2N2907
R2 N002 0 0.5R
R5 N006 N004 470R
S1 N007 N001 N003 0 SW
V1 N001 0 15
R3 0 N007 10K
R4 N007 N008 1K
M1 N002 N004 N001 N001 Si7137DP
R1 N001 N004 10K
D2 N005 N004 MURS120
V2 N003 0 SINE(0 12 1 0.01)
D1 N005 N001 BZX84C10L
Q2 N006 N008 0 0 BC817-40
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model SW SW(Ron=1 Roff=1Meg Vt=5 Vh=-4)
.tran 2s startup
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 680
WIRE -32 96 -224 96
WIRE 80 96 -32 96
WIRE 128 96 80 96
WIRE 192 96 128 96
WIRE 400 96 288 96
WIRE 128 112 128 96
WIRE -80 144 -144 144
WIRE 80 144 80 96
WIRE -224 176 -224 96
WIRE -144 176 -144 144
WIRE -32 176 -32 96
WIRE 400 176 400 96
WIRE -80 192 -80 144
WIRE 128 208 128 192
WIRE 208 208 208 144
WIRE 208 208 128 208
WIRE 80 240 80 208
WIRE 112 240 80 240
WIRE 208 240 208 208
WIRE 208 240 176 240
WIRE 208 256 208 240
WIRE -224 288 -224 256
WIRE 400 288 400 256
WIRE -144 304 -144 256
WIRE -80 304 -80 240
WIRE -80 304 -144 304
WIRE -144 336 -144 304
WIRE 208 352 208 336
WIRE 208 352 192 352
WIRE -32 400 -32 256
WIRE 0 400 -32 400
WIRE 128 400 80 400
WIRE -32 432 -32 400
WIRE 224 448 192 448
WIRE -32 560 -32 512
WIRE 224 608 224 448
SYMBOL voltage -224 160 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL npn 128 352 R0
SYMATTR InstName Q2
SYMATTR Value BC817-40
SYMBOL res 384 160 R0
SYMATTR InstName R2
SYMATTR Value 0.5R
SYMBOL res -16 528 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL voltage -144 160 R0
SYMATTR InstName V2
SYMATTR Value SINE(0 12 1 0.01)
SYMBOL pnp 848 464 M180
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL zener 96 208 R180
WINDOW 0 24 64 Left 2
WINDOW 3 -37 98 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C10L
SYMBOL res 224 352 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R5
SYMATTR Value 470R
SYMBOL res -16 416 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL sw -32 272 M180
SYMATTR InstName S1
SYMBOL pmos 288 144 M270
SYMATTR InstName M1
SYMATTR Value Si7137DP
SYMBOL diode 112 256 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value MURS120
SYMATTR Description Zener Diode
SYMATTR Type zener
SYMBOL res 112 96 R0
SYMATTR InstName R1
SYMATTR Value 10K
FLAG 224 608 0
FLAG -144 336 0
FLAG -224 288 0
FLAG -32 560 0
FLAG 400 288 0
TEXT -312 16 Left 2 !.model SW SW(Ron=1 Roff=1Meg Vt=5 Vh=-4)
TEXT -304 40 Left 2 !.tran 2s startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8610.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8610.asy)
XU1 0 N003 N005 IN IN N006 N004 NC_01 0 OUT N001 N002 0 LT8610 ;pnba SYNC)TR/SS)RT)EN/UV)VIN)FB)SW)PG)GND)BIAS)INTVcc)BST)PGND
C5 OUT N006 10p
R2 OUT N006 1Meg
L1 N004 OUT 4.7 Rser=3m
V1 IN 0 12
R1 N005 0 60.4K
C4 OUT 0 47 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
R3 N006 0 243K
C1 N003 0 .001
C2 N001 0 1
Rload OUT 0 2
C3 N002 N004 0.1
.tran 750u startup
.lib LT8610.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 680
WIRE 64 -80 -32 -80
WIRE 256 -80 64 -80
WIRE -32 -48 -32 -80
WIRE 256 -48 256 -80
WIRE 64 0 64 -80
WIRE 112 0 64 0
WIRE 416 0 400 0
WIRE 496 0 480 0
WIRE -32 48 -32 32
WIRE 112 96 64 96
WIRE 624 96 400 96
WIRE 432 192 400 192
WIRE 432 208 432 192
WIRE 32 288 16 288
WIRE 112 288 96 288
WIRE 432 288 432 272
WIRE 432 288 400 288
WIRE 512 288 432 288
WIRE 624 288 624 96
WIRE 624 288 592 288
WIRE 736 288 624 288
WIRE 832 288 736 288
WIRE 928 288 832 288
WIRE 624 304 624 288
WIRE 736 304 736 288
WIRE 832 304 832 288
WIRE 928 304 928 288
WIRE 112 384 32 384
WIRE 624 384 400 384
WIRE 736 384 736 368
WIRE 736 384 624 384
WIRE 32 400 32 384
WIRE 624 400 624 384
WIRE 832 400 832 368
WIRE 928 400 928 384
WIRE 192 448 192 432
WIRE 320 448 320 432
WIRE 32 496 32 480
WIRE 624 496 624 480
SYMBOL ind 496 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL cap 416 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 416 208 R0
SYMATTR InstName C3
SYMATTR Value 0.1
SYMBOL res 912 288 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL res 608 384 R0
SYMATTR InstName R3
SYMATTR Value 243K
SYMBOL res 16 384 R0
SYMATTR InstName R1
SYMATTR Value 60.4K
SYMBOL voltage -32 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 608 288 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL cap 720 304 R0
SYMATTR InstName C5
SYMATTR Value 10p
SYMBOL LT8610 256 192 R0
SYMATTR InstName U1
SYMBOL cap 816 304 R0
SYMATTR InstName C4
SYMATTR Value 47
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL cap 96 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .001
FLAG 192 448 0
FLAG 320 448 0
FLAG 32 496 0
FLAG 16 288 0
FLAG -32 48 0
FLAG 496 0 0
FLAG 832 400 0
FLAG 624 496 0
FLAG 928 400 0
FLAG 928 288 OUT
FLAG -32 -80 IN
FLAG 64 96 0
TEXT 848 488 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\36fa21d5f8a7_Example-of-DC-sweep.asc
* Generated by LTspice 26.0.1 for Windows.
* Example of DC sweep in LTSpice
D1 N002 0 1N4148
V1 N001 0
R1 N002 N001 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -10 10 3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 80 80 80
WIRE 272 80 240 80
WIRE 80 112 80 80
WIRE 272 128 272 80
WIRE 80 224 80 192
WIRE 272 224 272 192
SYMBOL res 256 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL diode 256 128 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG 80 224 0
FLAG 272 224 0
TEXT 344 72 Left 2 !.dc V1 -10 10 3
TEXT 128 -8 Left 2 ;Example of DC sweep in LTSpice
* Z:\home\khalils\Downloads\files\data\raw_asc\2ef1d4ffb7c4_B_sources_AC1.asc
* Generated by LTspice 26.0.1 for Windows.
* OK
* Not Working!
* AC-Analysis\n \nIt's always about the linearized circuit.\n \nB-source: V=I(V1)*I(V1)\n-> Gain in .AC-analysis: dV/diV = 2*I(V1)
* OK
* Not Working!
B3 b2 0 V=V(1)*V(1)
B4 b4 0 V=I(L1)*I(L1)
B2 b3 0 V=I(R1)*I(R1)
B1 b1 0 V=I(V1)*I(V1)
L1 N001 0 1n
R1 1 N001 1
V1 1 0 1 AC 1
.ac list 1k
.step V1 1 10 .5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1176 680
WIRE -128 64 -224 64
WIRE -64 64 -128 64
WIRE -64 112 -64 64
WIRE -224 160 -224 64
WIRE 224 160 192 160
WIRE 480 160 448 160
WIRE 816 160 784 160
WIRE 1024 160 992 160
WIRE 192 208 192 160
WIRE 448 208 448 160
WIRE 784 208 784 160
WIRE 992 208 992 160
WIRE -64 224 -64 192
WIRE 192 336 192 288
WIRE 448 336 448 288
WIRE 784 336 784 288
WIRE 992 336 992 288
WIRE -224 352 -224 240
WIRE -64 352 -64 304
RECTANGLE Normal 608 400 96 48
SYMBOL voltage -224 144 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMATTR Value2 AC 1
SYMBOL res -80 96 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL ind -80 208 R0
SYMATTR InstName L1
SYMATTR Value 1n
SYMBOL bv 448 192 R0
SYMATTR InstName B3
SYMATTR Value V=V(1)*V(1)
SYMBOL bv 784 192 R0
SYMATTR InstName B2
SYMATTR Value V=I(R1)*I(R1)
SYMBOL bv 992 192 R0
SYMATTR InstName B4
SYMATTR Value V=I(L1)*I(L1)
SYMBOL bv 192 192 R0
SYMATTR InstName B1
SYMATTR Value V=I(V1)*I(V1)
FLAG -64 352 0
FLAG -224 352 0
FLAG 192 336 0
FLAG -128 64 1
FLAG 224 160 b1
FLAG 784 336 0
FLAG 816 160 b3
FLAG 448 336 0
FLAG 480 160 b2
FLAG 992 336 0
FLAG 1024 160 b4
TEXT -168 -64 Left 0 !.ac list 1k
TEXT -168 -104 Left 0 !.step V1 1 10 .5
TEXT 184 88 Left 0 ;OK
TEXT 752 96 Left 0 ;Not Working!
TEXT 112 -152 Left 0 ;AC-Analysis\n \nIt's always about the linearized circuit.\n \nB-source: V=I(V1)*I(V1)\n-> Gain in .AC-analysis:  dV/diV = 2*I(V1)
TEXT 448 96 Left 0 ;OK
TEXT 960 96 Left 0 ;Not Working!
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1307.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1307.asy)
C1 N002 0 680p
C2 OUT 0 33 Rser=0.02
L1 IN N001 10 Rser=0.02 Rpar=5000
D1 N001 OUT MBRS140
XU1 N003 N004 IN 0 N001 IN N005 N006 LT1307 ;pnba Vc)FB)_SHDN)GND)SW)Vin)LBI)LBO
R4 OUT 0 100
R3 N003 N002 100K
R2 N004 0 324K
V1 IN 0 1.8
R1 OUT N004 1Meg
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LT1307.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1716 968
WIRE 528 464 416 464
WIRE 704 464 528 464
WIRE 752 464 704 464
WIRE 880 464 832 464
WIRE 928 464 880 464
WIRE 1056 464 992 464
WIRE 1200 464 1056 464
WIRE 1328 464 1200 464
WIRE 416 480 416 464
WIRE 1200 480 1200 464
WIRE 1328 480 1328 464
WIRE 704 512 704 464
WIRE 1056 512 1056 464
WIRE 416 576 416 560
WIRE 528 576 528 464
WIRE 560 576 528 576
WIRE 880 576 880 464
WIRE 880 576 848 576
WIRE 1200 576 1200 544
WIRE 1328 576 1328 560
WIRE 464 656 432 656
WIRE 560 656 544 656
WIRE 1056 656 1056 592
WIRE 1056 656 848 656
WIRE 432 672 432 656
WIRE 1056 672 1056 656
WIRE 560 736 544 736
WIRE 864 736 848 736
WIRE 432 752 432 736
WIRE 1056 768 1056 752
WIRE 704 816 704 800
SYMBOL RES 560 640 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL IND 736 480 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL RES 1312 464 R0
SYMATTR InstName R4
SYMATTR Value 100
SYMBOL RES 1040 656 R0
SYMATTR InstName R2
SYMATTR Value 324K
SYMBOL VOLTAGE 416 464 R0
WINDOW 3 26 94 Left 2
SYMATTR Value 1.8
SYMATTR InstName V1
SYMBOL SCHOTTKY 928 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL POWERPRODUCTS\\LT1307 704 656 R0
SYMATTR InstName U1
SYMBOL CAP 416 672 R0
SYMATTR InstName C1
SYMATTR Value 680p
SYMBOL RES 1040 496 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL POLCAP 1184 480 R0
SYMATTR InstName C2
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02
FLAG 1328 464 OUT
FLAG 1056 768 0
FLAG 1200 576 0
FLAG 1328 576 0
FLAG 432 752 0
FLAG 416 576 0
FLAG 704 816 0
FLAG 416 464 IN
TEXT 1096 816 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\7abf06b8813d_CurrentSenseSim.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
R8 N005 N006 33000
R7 0 N002 800
V1 N001 3v3 12
R2 N006 0 3300
V2 3v3 0 3.3
R10 N001 N003 1
XU1 N004 N006 3v3 0 N005 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R9 N003 0 0.05
R5 N002 N004 33000
R6 N002 3v3 800
R1 N004 N003 3300
.dc V1 -12 12 0.1
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 -112 -32 -112
WIRE 192 -112 144 -112
WIRE 144 -96 144 -112
WIRE 192 -96 192 -112
WIRE -32 -48 -32 -112
WIRE 64 -16 64 -112
WIRE 144 -16 64 -16
WIRE 144 0 144 -16
WIRE 48 32 48 -48
WIRE 144 32 144 0
WIRE 240 32 224 32
WIRE 256 32 240 32
WIRE 368 32 336 32
WIRE 368 48 368 32
WIRE 240 64 240 32
WIRE 48 160 48 112
WIRE 128 160 48 160
WIRE 240 160 240 144
WIRE 240 160 208 160
WIRE 352 160 304 160
WIRE 304 176 304 160
WIRE 352 176 352 160
WIRE 240 192 240 160
WIRE 272 192 240 192
WIRE 368 208 336 208
WIRE 272 224 240 224
WIRE 48 256 48 240
WIRE 128 256 48 256
WIRE 240 256 240 224
WIRE 240 256 208 256
WIRE 48 288 48 256
WIRE 240 304 240 256
WIRE 256 304 240 304
WIRE 368 304 368 208
WIRE 368 304 336 304
SYMBOL voltage 64 -48 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 240 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 800
SYMBOL res 32 16 R0
SYMATTR InstName R10
SYMATTR Value 1
SYMBOL res 224 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 3300
SYMBOL res 224 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 3300
SYMBOL Opamps\\UniversalOpamp2 304 208 M180
SYMATTR InstName U1
SYMBOL res 352 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 800
SYMBOL res 32 144 R0
SYMATTR InstName R9
SYMATTR Value 0.05
SYMBOL res 224 48 R0
SYMATTR InstName R5
SYMATTR Value 33000
SYMBOL res 352 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 33000
SYMBOL voltage 144 0 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3.3
FLAG 48 288 0
FLAG 368 48 0
FLAG 192 -96 0
FLAG 352 176 0
FLAG 144 0 3v3
FLAG 304 240 3v3
TEXT -272 248 Left 2 !.dc V1 -12 12 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\097931730ed0_voltage_follower.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 15
R1 N002 vin 270
R2 vout 0 3.3k
Q1 N001 N002 vout 0 NPN
V1 vin 0 SINE(0 5 1k)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 432 32 256 32
WIRE 256 80 256 32
WIRE 432 96 432 32
WIRE 80 128 -16 128
WIRE 192 128 160 128
WIRE -16 160 -16 128
WIRE 256 208 256 176
WIRE 352 208 256 208
WIRE 256 224 256 208
WIRE -16 352 -16 240
WIRE 256 352 256 304
WIRE 256 352 -16 352
WIRE 432 352 432 176
WIRE 432 352 256 352
WIRE 256 384 256 352
SYMBOL voltage 432 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL voltage -16 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1k)
SYMBOL res 176 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 270
SYMBOL res 240 208 R0
SYMATTR InstName R2
SYMATTR Value 3.3k
SYMBOL npn 192 80 R0
SYMATTR InstName Q1
FLAG 256 384 0
FLAG 352 208 vout
FLAG -16 128 vin
TEXT -48 408 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\608ac321afe3_ID_vs_UGS_small_signal.asc
* Generated by LTspice 26.0.1 for Windows.
V2 UGS 0
RD UDS VDD 8
M1 UDS UGS 0 0 BSP89
V1 VDD 0 12
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V2 0 6
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1292 680
WIRE -720 -272 -720 -304
WIRE -720 -160 -720 -192
WIRE -624 -160 -720 -160
WIRE -720 -128 -720 -160
WIRE -928 -48 -944 -48
WIRE -768 -48 -928 -48
WIRE -944 0 -944 -48
WIRE -480 0 -480 -32
WIRE -944 128 -944 80
WIRE -720 128 -720 -32
WIRE -480 128 -480 80
SYMBOL voltage -944 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 53 Left 2
WINDOW 3 -97 181 Left 2
WINDOW 0 35 44 Left 2
SYMATTR Value ""
SYMATTR InstName V2
SYMBOL voltage -480 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 37 60 Left 2
WINDOW 0 36 55 Left 2
WINDOW 3 36 82 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL nmos -768 -128 R0
SYMATTR InstName M1
SYMATTR Value BSP89
SYMBOL Misc\\EuropeanResistor -704 -176 R180
WINDOW 0 -49 65 Left 2
WINDOW 3 -51 33 Left 2
SYMATTR InstName RD
SYMATTR Value 8
FLAG -480 128 0
FLAG -944 128 0
FLAG -720 128 0
FLAG -480 -32 VDD
FLAG -720 -304 VDD
FLAG -624 -160 UDS
FLAG -928 -48 UGS
TEXT -960 168 Left 2 !.dc V2  0 6
* Z:\home\khalils\Downloads\files\data\raw_asc\05fe12980cab_Switch_Option_1.asc
* Generated by LTspice 26.0.1 for Windows.
* Simulation
* Spice Directives
* Switch Model & Control
V2 Vsw 0 PULSE(0 1 0 1u 1u 0.8 3)
S1 N003 N002 Vsw 0 MYSW
V1 N001 0 20
R1 N002 N001 3
R3 Vo N003 1
R2 N003 0 9
C1 Vo 0 20m
.tran 0 3 0 100u
.model MYSW SW(Ron=0.1 Roff=1000Meg Vt=.5 Vh=.4)
.ic V(Vo)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1532 760
WIRE 224 192 224 176
WIRE 272 192 272 160
WIRE 80 240 16 240
WIRE 208 240 160 240
WIRE 352 240 288 240
WIRE 400 240 352 240
WIRE 528 240 480 240
WIRE 16 304 16 240
WIRE 352 304 352 240
WIRE 528 304 528 240
WIRE 688 384 688 368
WIRE 16 432 16 384
WIRE 352 432 352 384
WIRE 352 432 16 432
WIRE 528 432 528 368
WIRE 528 432 352 432
WIRE 16 480 16 432
WIRE 688 496 688 464
RECTANGLE Normal 1024 240 640 160 2
RECTANGLE Normal 880 112 640 64 2
RECTANGLE Normal 1328 576 640 304 2
SYMBOL res 336 288 R0
SYMATTR InstName R2
SYMATTR Value 9
SYMBOL sw 304 240 R90
WINDOW 0 -46 11 Left 2
WINDOW 3 53 17 VRight 2
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL cap 512 304 R0
SYMATTR InstName C1
SYMATTR Value 20m
SYMBOL res 496 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1
SYMBOL voltage 688 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 1u 1u 0.8 3)
SYMBOL res 176 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 3
SYMBOL voltage 16 288 R0
SYMATTR InstName V1
SYMATTR Value 20
FLAG 16 480 0
FLAG 272 160 0
FLAG 224 176 Vsw
FLAG 688 368 Vsw
FLAG 688 496 0
FLAG 528 240 Vo
TEXT 640 48 Left 2 ;Simulation
TEXT 648 88 Left 2 !.tran 0 3 0 100u
TEXT 640 144 Left 2 ;Spice Directives
TEXT 664 536 Left 2 !.model MYSW SW(Ron=0.1 Roff=1000Meg Vt=.5 Vh=.4)
TEXT 648 184 Left 2 !.ic V(Vo)=0
TEXT 640 288 Left 2 ;Switch Model & Control
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8421.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
Vin V+ V- SINE(0 1m 10K)
R1 N001 N002 100
V2 -V 0 0
Rload OUT 0 10K
Vcm V- 0 PWL(0 2.4 2.5m 3.1 5m 2.4)
Vref N003 0 2.5
XU1 V- N001 N002 V+ -V N003 OUT +V AD8421 ;pnba IN-)RG1)RG2)IN+)VEE)REF)OUT)VCC
.tran 5m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8421.asy)
.lib AD8421.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 640 -1264 640 -1280
WIRE 752 -1264 752 -1280
WIRE 304 -1184 96 -1184
WIRE 464 -1184 304 -1184
WIRE 640 -1168 640 -1184
WIRE 752 -1168 752 -1184
WIRE 96 -1152 96 -1184
WIRE 464 -1152 368 -1152
WIRE 752 -1104 640 -1104
WIRE 752 -1088 752 -1104
WIRE 368 -1056 368 -1072
WIRE 464 -1056 368 -1056
WIRE 96 -1024 96 -1072
WIRE 304 -1024 96 -1024
WIRE 464 -1024 304 -1024
WIRE 576 -1024 576 -1040
WIRE 96 -1008 96 -1024
WIRE 752 -992 752 -1008
WIRE 576 -928 576 -944
WIRE 96 -912 96 -928
FLAG 640 -1280 +V
FLAG 640 -1168 0
FLAG 752 -1104 OUT
FLAG 496 -1200 +V
FLAG 752 -1280 -V
FLAG 496 -1008 -V
FLAG 752 -992 0
FLAG 752 -1168 0
FLAG 96 -912 0
FLAG 576 -928 0
FLAG 304 -1024 V-
FLAG 304 -1184 V+
SYMBOL voltage 640 -1280 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 96 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1m 10K)
SYMBOL res 352 -1168 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 752 -1280 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 96 -1024 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName Vcm
SYMATTR Value PWL(0 2.4 2.5m 3.1 5m 2.4)
SYMBOL voltage 576 -1040 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName Vref
SYMATTR Value 2.5
SYMBOL AD8421 496 -1104 R0
SYMATTR InstName U1
TEXT 328 -960 Left 2 !.tran 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\15b6cdfb6b67_1693-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1693-1.asy)
V1 N002 0 5
V2 N001 0 PULSE(0 5 0 1n 1n 5u 10u)
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 NC_07 NC_08 LTC1693-1 ;pnba IN1)GND1)IN2)GND2)OUT2)Vcc2)OUT1)Vcc1
.tran 100u
.lib LTC1693-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2388 1428
WIRE 1440 1072 1072 1072
WIRE 1760 1072 1696 1072
WIRE 1888 1072 1760 1072
WIRE 1888 1088 1888 1072
WIRE 1440 1136 1424 1136
WIRE 1712 1136 1696 1136
WIRE 1888 1184 1888 1168
WIRE 1072 1200 1072 1072
WIRE 1440 1200 1072 1200
WIRE 1760 1200 1760 1072
WIRE 1760 1200 1696 1200
WIRE 1072 1216 1072 1200
WIRE 1440 1264 1424 1264
WIRE 1712 1264 1696 1264
WIRE 1072 1312 1072 1296
SYMBOL voltage 1888 1072 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LTC1693-1 1568 1168 R0
SYMATTR InstName U1
SYMBOL voltage 1072 1200 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1n 1n 5u 10u)
FLAG 1888 1184 0
FLAG 1424 1264 0
FLAG 1424 1136 0
FLAG 1072 1312 0
TEXT 1720 1344 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\11e72c785e4f_FET09op.asc
* Generated by LTspice 26.0.1 for Windows.
Rd N001 N002 {Rd}
M1 N002 g 0 0 MOSFET
Rg g N002 {Rg}
Vdd N001 0 {Vdd}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.model MOSFET pmos(Kp=1m Vto=-4)
.param Vdd=-50 Rd=330 Rg=1Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1608 1076
WIRE 384 -128 192 -128
WIRE 192 -80 192 -128
WIRE 192 16 192 0
WIRE 192 16 -16 16
WIRE 192 32 192 16
WIRE 384 48 384 -128
WIRE -16 112 -16 16
WIRE 16 112 -16 112
WIRE 112 112 96 112
WIRE 144 112 112 112
WIRE 192 176 192 128
WIRE 384 176 384 128
WIRE 384 176 192 176
WIRE 192 208 192 176
SYMBOL res 176 -96 R0
SYMATTR InstName Rd
SYMATTR Value {Rd}
SYMBOL voltage 384 32 R0
WINDOW 0 55 34 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdd
SYMATTR Value {Vdd}
SYMBOL res 112 96 R90
WINDOW 0 -10 57 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rg
SYMATTR Value {Rg}
SYMBOL pmos 144 32 R0
SYMATTR InstName M1
SYMATTR Value MOSFET
FLAG 192 208 0
FLAG 112 112 g
TEXT 240 208 Left 2 !.op
TEXT 72 328 Left 2 !.model MOSFET pmos(Kp=1m Vto=-4)
TEXT 80 376 Left 2 !.param Vdd=-50 Rd=330 Rg=1Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\424d4bec47c8_Parte3.asc
* Generated by LTspice 26.0.1 for Windows.
Vds N001 0 2
Vgs N003 0 1
M1 N001 N003 0 N002 N_1u l=1.5u w=9.6u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.dc Vds 0 5 0.01 Vgs 0 5 0.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 64 144 64
WIRE 144 96 144 64
WIRE 384 112 384 64
WIRE 208 144 144 144
WIRE 96 176 -80 176
WIRE 208 176 208 144
WIRE 208 176 144 176
WIRE -80 208 -80 176
WIRE 144 256 144 192
WIRE 384 272 384 192
WIRE -80 352 -80 288
SYMBOL voltage -80 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vgs
SYMATTR Value 1
SYMBOL nmos4 96 96 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1.5u w=9.6u
SYMBOL voltage 384 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vds
SYMATTR Value 2
FLAG 144 256 0
FLAG 384 272 0
FLAG -80 352 0
TEXT 0 -8 Left 2 !.include cmosedu_models.txt
TEXT -8 408 Left 2 !.dc Vds 0 5 0.01 Vgs 0 5 0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\6fad503e7f57_diodechar_01_02_01_incvs_vd_vr_is.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N001 N002 1N4001
R1 N002 0 1k
V1 N001 0 0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0 2 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 48 -16 48
WIRE 288 48 176 48
WIRE -16 128 -16 48
WIRE 288 128 288 48
WIRE -16 272 -16 208
WIRE 144 272 -16 272
WIRE 288 272 288 208
WIRE 288 272 144 272
WIRE 144 288 144 272
FLAG 144 288 0
SYMBOL diode 112 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4001
SYMBOL res 272 112 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -16 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 0
TEXT -48 312 Left 2 !.dc V1 0 2 0.01