Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\6c6bc7705e3a_ts2.asc
* Generated by LTspice 26.0.1 for Windows.
XU2 0 N004 vo2 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R3 vo2 N001 1
C1 N002 N004 1
R5 vo2 N003 1
V1 Vi 0 AC 1 0
C2 vo1 N001 1
XU3 N003 0 N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R6 N001 Vi 10
R2 vo1 N001 0.2
R4 N003 N002 1
XU1 N001 0 vo1 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R1 N004 vo1 1
.lib opamp.sub
.ac dec 100 1m 10K
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 96 -48 96
WIRE 624 96 256 96
WIRE -48 144 -48 96
WIRE -16 144 -48 144
WIRE 112 144 64 144
WIRE 352 144 320 144
WIRE 496 144 432 144
WIRE 496 208 496 144
WIRE 496 208 400 208
WIRE 512 208 496 208
WIRE 624 208 624 96
WIRE 624 208 592 208
WIRE 688 208 624 208
WIRE -48 224 -48 144
WIRE 0 224 -48 224
WIRE 112 224 112 144
WIRE 112 224 64 224
WIRE 240 224 224 224
WIRE 320 224 320 144
WIRE 320 224 304 224
WIRE 336 224 320 224
WIRE 448 240 400 240
WIRE 448 256 448 240
WIRE -176 304 -240 304
WIRE -48 304 -48 224
WIRE -48 304 -96 304
WIRE 16 304 -48 304
WIRE 112 320 112 224
WIRE 112 320 80 320
WIRE 128 320 112 320
WIRE 224 320 224 224
WIRE 224 320 208 320
WIRE 240 320 224 320
WIRE 16 336 -48 336
WIRE 624 336 624 208
WIRE 624 336 304 336
WIRE -240 352 -240 304
WIRE 240 352 192 352
WIRE -48 384 -48 336
WIRE 192 384 192 352
WIRE 112 400 112 320
WIRE 688 400 688 208
WIRE -240 448 -240 432
SYMBOL OpAmps\\opamp 368 160 M0
SYMATTR InstName U3
SYMBOL res -80 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10
SYMBOL cap 304 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -240 336 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL res 224 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL res 80 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 0.2
SYMBOL res 608 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1
SYMBOL res 448 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 272 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1
SYMBOL OpAmps\\opamp 48 256 R0
SYMATTR InstName U1
SYMBOL OpAmps\\opamp 272 400 M180
SYMATTR InstName U2
FLAG 448 256 0
FLAG -240 448 0
FLAG -48 384 0
FLAG 192 384 0
FLAG -240 304 Vi
FLAG 112 400 vo1
FLAG 688 400 vo2
TEXT 152 488 Left 2 !.lib opamp.sub
TEXT -178 490 Left 2 !.ac dec 100 1m 10K
* Z:\home\khalils\Downloads\files\data\raw_asc\23f2b4f3a241_with_nmos.asc
* Generated by LTspice 26.0.1 for Windows.
* The voltage reading at IN must be equal to the voltage reading at OUT\n \nThis works quite well as long as the RLoad is relatively small (<10 Ohms)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
RL N002 N003 8
C1 N006 0 10n
R4 OUT 0 1
V1 IN 0 SINE(0.1 0.1 1)
C2 N007 0 10n
R3 N006 IN 1K
M1 N003 N005 OUT OUT NMOS
R2 OUT N001 1K
R5 N007 N006 1K
Vs N002 0 12
R1 N005 N004 100
XU1 N007 N001 N002 0 N004 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 10 0 0.01
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1176 680
WIRE 240 -272 16 -272
WIRE 528 -272 320 -272
WIRE 400 -176 400 -224
WIRE 400 -64 400 -96
WIRE 400 -64 128 -64
WIRE 400 -48 400 -64
WIRE 400 64 400 32
WIRE 128 112 128 -64
WIRE 16 128 16 -272
WIRE 96 128 16 128
WIRE 224 144 160 144
WIRE 352 144 304 144
WIRE -304 160 -368 160
WIRE -160 160 -224 160
WIRE -96 160 -160 160
WIRE 32 160 -16 160
WIRE 96 160 32 160
WIRE -368 192 -368 160
WIRE -160 192 -160 160
WIRE 32 192 32 160
WIRE 400 192 400 160
WIRE 448 192 400 192
WIRE 528 192 528 -272
WIRE 528 192 448 192
WIRE 128 208 128 176
WIRE 400 224 400 192
WIRE -368 304 -368 272
WIRE -160 304 -160 256
WIRE -160 304 -368 304
WIRE 32 304 32 256
WIRE 32 304 -160 304
WIRE 400 336 400 304
WIRE -368 352 -368 304
SYMBOL res 384 -64 R0
SYMATTR InstName RL
SYMATTR Value 8
SYMBOL cap 16 192 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap -176 192 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 336 -288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res -208 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL res 384 208 R0
SYMATTR InstName R4
SYMATTR Value 1
SYMBOL Misc\\signal -368 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -70 80 Left 2
WINDOW 3 -214 45 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0.1 0.1 1)
SYMBOL res 320 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL OpAmps\\UniversalOpAmp 128 144 R0
SYMATTR InstName U1
SYMBOL nmos 352 64 R0
SYMATTR InstName M1
SYMBOL res 0 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL voltage 400 -80 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vs
SYMATTR Value 12
FLAG -368 352 0
FLAG 128 208 0
FLAG 400 -224 0
FLAG 400 336 0
FLAG -368 160 IN
FLAG 448 192 OUT
TEXT 32 520 Left 2 !.tran 0 10 0 0.01
TEXT -952 -120 Left 2 ;The voltage reading at IN must be equal to the voltage reading at OUT\n \nThis works quite well as long as the RLoad is relatively small (<10 Ohms)
* Z:\home\khalils\Downloads\files\data\raw_asc\19b34ead5a6f_gm_of_vgs_const_vds_ac.asc
* Generated by LTspice 26.0.1 for Windows.
Vgs Vg 0 {VGS} AC 1
Vds Vd 0 {VDS}
M1 Vd Vg 0 0 BSS83
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.STEP PARAM VGS 0 5 .01
.OP
.AC LIST 1
* Plot transconductance Gm as Id(M1) or I(Vds) to get Gm at 1Hz.
* Forward Conductance "Gm" Versus Gate Source Voltage at 1Hz\n \nPlot Id(M1) to get Gm versus Vgs. \nThe .AC command perfforms a small signal analysis and thus Id(M1)\nis the transconductance Gm.
* Gerneral hint for plots:\nMake the plot window active. \n"PlotSettings->Add Trace" and select an item\nor "right mouse button ->Add Trace" and select an item.
.param VDS=5
* Model from Philips Semiconductor
.MODEL BSS83 NMOS
+ LEVEL=3
+ W=1E-3
+ L=1E-6
+ VTO=2
+ VMAX=1E6
+ RS=3
+ RD=3
+ CJ=0.001396
+ MJ=0.3936
+ THETA=1E-6
+ ETA=0.009307
+ KAPPA=2.226
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1208 724
WIRE -96 320 -96 272
WIRE 96 432 96 608
WIRE 96 608 -96 608
WIRE -96 464 -96 416
WIRE -96 544 -96 608
WIRE -96 640 -96 608
WIRE -96 192 -96 144
WIRE 48 416 -96 416
WIRE -96 144 96 144
WIRE 96 144 96 336
FLAG -96 640 0
FLAG -96 320 0
FLAG -96 144 Vd
FLAG -96 416 Vg
SYMBOL voltage -96 448 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName Vgs
SYMATTR Value {VGS}
SYMBOL voltage -96 176 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vds
SYMATTR Value {VDS}
SYMBOL nmos 48 336 R0
SYMATTR InstName M1
SYMATTR Value BSS83
TEXT -112 -224 Left 0 !.STEP PARAM  VGS 0 5 .01
TEXT -112 -184 Left 0 !.OP
TEXT -112 -136 Left 0 !.AC LIST 1
TEXT 48 -136 Left 0 ;Plot transconductance Gm as Id(M1) or I(Vds) to get Gm at 1Hz.
TEXT -112 -416 Left 0 ;Forward Conductance "Gm" Versus Gate Source Voltage at 1Hz\n \nPlot Id(M1) to get Gm versus Vgs.  \nThe .AC command perfforms a small signal analysis and thus Id(M1)\nis the transconductance Gm.
TEXT -104 -40 Left 0 ;Gerneral hint for plots:\nMake the plot window active. \n"PlotSettings->Add Trace" and select an item\nor "right mouse button  ->Add Trace" and select an item.
TEXT -112 -264 Left 0 !.param VDS=5
TEXT 240 192 Left 0 !* Model from Philips Semiconductor\n.MODEL BSS83 NMOS\n+ LEVEL=3\n+ W=1E-3\n+ L=1E-6\n+ VTO=2\n+ VMAX=1E6\n+ RS=3\n+ RD=3\n+ CJ=0.001396\n+ MJ=0.3936\n+ THETA=1E-6\n+ ETA=0.009307\n+ KAPPA=2.226
* Z:\home\khalils\Downloads\files\data\raw_asc\097057c10774_LT1260.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1260.asy)
V1 +V 0 5
R1 OUT N001 1.6K
R2 N001 0 1.6K
V3 IN 0 SINE(0 1 1K)
V2 -V 0 -5
XU1 IN N001 +V -V OUT LT1259 ;pnba In+)In-)V+)V-)OUT
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -288 144 -288 128
WIRE -160 144 -160 128
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -288 240 -288 224
WIRE -160 240 -160 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL opamps\\LT1260 192 176 R0
SYMATTR InstName U1
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL voltage -160 128 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -288 128 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1.6K
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.6K
FLAG -160 240 0
FLAG 192 192 +V
FLAG -160 128 +V
FLAG 192 288 -V
FLAG -288 240 0
FLAG -288 128 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 288 240 OUT
FLAG 0 256 IN
TEXT 264 336 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\24fae5d7ee28_differential.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 in N004 0 NPN
Q2 N002 N003 N004 0 NPN
V1 vcc 0 30
V2 vcc- 0 -30
R3 0 N003 1k
R4 N002 N003 2.88k
V3 in 0 SINE(0 0.460 1k)
Q3 N001 N001 vcc 0 PNP
Q4 N002 N001 vcc 0 PNP
Q5 N004 N005 vcc- 0 NPN
Q6 N005 N005 vcc- 0 NPN
R1 vcc N005 100k
R2 out 0 450k
C1 out N002 100n
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran {t}
.param f = 1k n=16 t=n/f
.four {f} 10 8 V(out)
.meas TRAN power_Output AVG I(R_load)*V(Out) TRIG time=0 TARG time={t}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -64 160 -64
WIRE 320 -64 240 -64
WIRE 160 -32 160 -64
WIRE 320 -32 320 -64
WIRE 240 16 224 16
WIRE 256 16 240 16
WIRE 320 80 320 64
WIRE 400 80 320 80
WIRE 464 80 400 80
WIRE 544 80 528 80
WIRE 160 96 160 64
WIRE 240 96 240 16
WIRE 240 96 160 96
WIRE 160 112 160 96
WIRE 320 112 320 80
WIRE 96 160 48 160
WIRE 400 160 384 160
WIRE 432 160 400 160
WIRE 528 160 512 160
WIRE 576 160 528 160
WIRE 576 192 576 160
WIRE 160 320 160 208
WIRE 240 320 160 320
WIRE 320 320 320 208
WIRE 320 320 240 320
WIRE 144 336 48 336
WIRE 48 352 48 336
WIRE 240 352 240 320
WIRE 144 400 144 336
WIRE 144 400 112 400
WIRE 176 400 144 400
FLAG 544 80 out
FLAG -640 -16 0
FLAG -528 -16 0
FLAG -640 -96 vcc
FLAG -528 -96 vcc-
FLAG 240 -64 vcc
FLAG 576 192 0
FLAG 48 160 in
FLAG -640 144 0
FLAG -640 64 in
FLAG 48 448 vcc-
FLAG 240 448 vcc-
FLAG 48 256 vcc
SYMBOL npn 96 112 R0
SYMATTR InstName Q1
SYMBOL npn 384 112 M0
SYMATTR InstName Q2
SYMBOL voltage -640 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL voltage -528 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -30
SYMBOL res 528 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 384 64 R0
SYMATTR InstName R4
SYMATTR Value 2.88k
SYMBOL voltage -640 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 0.460 1k)
SYMBOL pnp 224 64 R180
SYMATTR InstName Q3
SYMBOL pnp 256 64 M180
SYMATTR InstName Q4
SYMBOL npn 176 352 R0
SYMATTR InstName Q5
SYMBOL npn 112 352 M0
SYMATTR InstName Q6
SYMBOL res 32 240 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 512 64 R0
SYMATTR InstName R2
SYMATTR Value 450k
SYMBOL cap 528 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
TEXT -672 496 Left 2 !.tran {t}
TEXT -320 -112 Left 2 !.param f = 1k n=16 t=n/f
TEXT -320 -72 Left 2 !.four {f} 10 8 V(out)
TEXT -320 -144 Left 2 !.meas TRAN power_Output AVG I(R_load)*V(Out) TRIG time=0 TARG time={t}
* Z:\home\khalils\Downloads\files\data\raw_asc\25a8f467a146_adaq23875.asc
* Generated by LTspice 26.0.1 for Windows.
* Simulation Settings:
* Power Supplies:
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\ADAQ23875.asy)
;.tran 10u
;.ac dec 100 100 10G
V1 PDB 0 6.5
V2 N003 0 PULSE(0 1.8 66.6n .2n .2n 5n 66.6n)
V5 VDD 0 5
XU1 N001 N002 PDB PDB VS_N NC_01 NC_02 NC_03 VDD Vout N003 0 ADAQ23875 ;pnba IN-)IN+)VS+)PDB_AMP)VS-)REF_IN)VCMO)REFBUF)VDD)Vout)CNV)ADC_GND
V4 N002 N001 SINE(0 1.8189 100k) AC 1
V3 VS_N 0 -2
.noise V(Vout) V1 dec 500 100 10G
.lib ADAQ23875.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1496 700
WIRE -144 -480 -144 -560
WIRE 432 -480 432 -560
WIRE -640 -288 -816 -288
WIRE 656 -240 544 -240
WIRE 704 -240 656 -240
WIRE -816 -208 -816 -288
WIRE -640 -192 -640 -288
WIRE -560 -192 -640 -192
WIRE -1696 -112 -1696 -160
WIRE -1552 -112 -1552 -160
WIRE -1504 -112 -1504 -160
WIRE -1504 -112 -1552 -112
WIRE -1408 -112 -1408 -160
WIRE -560 -112 -640 -112
WIRE -1696 -80 -1696 -112
WIRE -1552 -80 -1552 -112
WIRE -1408 -80 -1408 -112
WIRE 704 -64 544 -64
WIRE -816 -16 -816 -128
WIRE -640 -16 -640 -112
WIRE -640 -16 -816 -16
WIRE 704 -16 704 -64
WIRE -1696 32 -1696 0
WIRE -1552 32 -1552 0
WIRE -1552 32 -1696 32
WIRE -1408 32 -1408 0
WIRE -1408 32 -1552 32
WIRE -1696 64 -1696 32
WIRE 704 144 704 64
WIRE -192 256 -192 176
WIRE -144 256 -144 176
WIRE 128 272 128 176
RECTANGLE Normal -1200 112 -1808 -400 2
SYMBOL voltage -816 -112 R180
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value SINE(0 1.8189 100k)
SYMBOL voltage 704 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1.8 66.6n .2n .2n 5n 66.6n)
SYMBOL voltage -1408 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL ADAQ23875 -192 -176 R0
SYMATTR InstName U1
SYMBOL voltage -1696 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -2
SYMBOL voltage -1552 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 6.5
FLAG 704 144 0
FLAG -1696 64 0
FLAG -1696 -112 VS_N
FLAG -1408 -112 VDD
FLAG 656 -240 Vout
FLAG 432 -560 VDD
FLAG -144 -560 VS_P
FLAG -144 256 VS_N
FLAG 128 272 0
FLAG -192 256 PDB
FLAG -1504 -160 PDB
FLAG -1552 -160 VS_P
TEXT -1776 -376 Left 2 ;Simulation Settings:
TEXT -1760 -336 Left 2 !.noise V(Vout) V1 dec 500 100 10G
TEXT -1760 -272 Left 2 !;.tran 10u
TEXT -1760 -304 Left 2 !;.ac dec 100 100 10G
TEXT -1776 -216 Left 2 ;Power Supplies:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3523-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3523-2.asy)
L1 IN N001 4.7
Rload2 OUT2 0 6
V1 IN 0 2
XU1 N004 IN NC_01 OUT1 N001 0 0 N002 IN NC_02 NC_03 N003 IN 0 IN IN LTC3523-2 ;pnba FB1)Vin1)Pgood1)Vout)SW1)GND1)GND2)SW2)Vin2)Mode)Pgood2)FB2)_SHDN2)GND3)Vbat)_SHDN1
C1 OUT1 0 10
C2 OUT2 0 10
C3 OUT2 N003 10p
R3 OUT2 N003 511K
Rload1 OUT1 0 16.5
R4 N003 0 511K
R2 N004 0 365K
R1 OUT1 N004 634K
L2 N002 OUT2 4.7
.tran .6m startup
.lib LTC3523-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 904 680
WIRE 16 -64 -64 -64
WIRE 160 -64 16 -64
WIRE 240 -64 160 -64
WIRE 320 -64 240 -64
WIRE 400 -64 320 -64
WIRE -64 -48 -64 -64
WIRE 160 -48 160 -64
WIRE 240 -48 240 -64
WIRE 320 -48 320 -64
WIRE 16 16 16 -64
WIRE 96 16 16 16
WIRE 400 16 400 -64
WIRE 400 16 384 16
WIRE 16 32 16 16
WIRE -64 48 -64 32
WIRE 16 128 16 112
WIRE 96 128 16 128
WIRE 400 128 384 128
WIRE 512 128 480 128
WIRE 576 128 512 128
WIRE 672 128 576 128
WIRE 752 128 672 128
WIRE 576 144 576 128
WIRE 672 144 672 128
WIRE 752 144 752 128
WIRE 512 160 512 128
WIRE -96 240 -240 240
WIRE 0 240 -96 240
WIRE 96 240 0 240
WIRE 512 240 512 224
WIRE 512 240 384 240
WIRE 576 240 576 224
WIRE 576 240 512 240
WIRE 672 240 672 208
WIRE 752 240 752 224
WIRE -240 256 -240 240
WIRE -96 256 -96 240
WIRE 0 256 0 240
WIRE 576 256 576 240
WIRE -240 352 -240 336
WIRE -96 352 -96 320
WIRE 0 352 0 336
WIRE 96 352 0 352
WIRE 576 352 576 336
WIRE 0 368 0 352
WIRE 0 464 0 448
WIRE 160 544 160 528
WIRE 240 544 240 528
WIRE 320 544 320 528
SYMBOL res 560 128 R0
SYMATTR InstName R3
SYMATTR Value 511K
SYMBOL ind 384 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 4.7
SYMBOL res 736 128 R0
SYMATTR InstName Rload2
SYMATTR Value 6
SYMBOL cap 496 160 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL res 560 240 R0
SYMATTR InstName R4
SYMATTR Value 511K
SYMBOL res -256 240 R0
SYMATTR InstName Rload1
SYMATTR Value 16.5
SYMBOL PowerProducts\\LTC3523-2 240 240 R0
SYMATTR InstName U1
SYMBOL res -16 352 R0
SYMATTR InstName R2
SYMATTR Value 365K
SYMBOL res -16 240 R0
SYMATTR InstName R1
SYMATTR Value 634K
SYMBOL cap -112 256 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 -64 R0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL cap 656 144 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL ind 0 16 R0
SYMATTR InstName L1
SYMATTR Value 4.7
FLAG 240 544 0
FLAG 160 544 0
FLAG 320 544 0
FLAG -64 48 0
FLAG 0 464 0
FLAG -96 352 0
FLAG -240 352 0
FLAG 576 352 0
FLAG 672 240 0
FLAG 752 240 0
FLAG -64 -64 IN
FLAG -240 240 OUT1
FLAG 752 128 OUT2
TEXT 520 464 Left 2 !.tran .6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-5.0.asy)
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-5.0 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
V1 IN 0 3.3
L1 N001 N002 1.5 Rser=80m
Rload OUT 0 50
C1 OUT 0 10
.tran 400u startup
.lib ADP2504-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ADP2504-5.0 176 176 R0
SYMATTR InstName U1
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 392 384 Left 2 !.tran 400u startup
TEXT 176 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5423.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5423.asy)
V1 0 N007 24
V2 N001 0 24
R1 N006 0 1k
R5 N004 OUT 10
XU1 N001 N001 0 MP_01 MP_02 MP_03 N006 NC_04 N002 N002 MP_05 N007 N005 MP_06 N003 N004 IN AD5423 RANGE = 0, OVRNG_EN = 0, NEG_OFFSET_EN = 0 SR_EN = 0, SR_STEP = 0, SR_CLOCK = 0 VIOUT_PULLDOWN_EN = 0, HART_EN = 0 ;pnba AVDD1)AVDD2)GND))))REFOUT)CHART)VLDO)VLOGIC))AVSS)-VSENSE))+VSENSE)VIOUT)INPUT
R4 OUT N003 1k
R2 N002 0 1k
V4 IN 0 PULSE(1 2 100u 1u 1u 1m)
R6 OUT 0 1k
R3 0 N005 1k
.tran 200u
.lib AD5423.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2016 1328
WIRE -96 -320 -96 -384
WIRE 160 -320 160 -384
WIRE -96 -160 -96 -240
WIRE 32 -160 -96 -160
WIRE 160 -160 160 -240
WIRE 272 -160 160 -160
WIRE -96 -96 -96 -160
WIRE 32 -96 32 -160
WIRE 160 -96 160 -160
WIRE 272 -96 272 -160
WIRE 528 96 464 96
WIRE 816 96 608 96
WIRE -176 224 -512 224
WIRE 576 224 528 224
WIRE 816 224 816 96
WIRE 816 224 656 224
WIRE 864 224 816 224
WIRE 816 240 816 224
WIRE -512 288 -512 224
WIRE 544 352 464 352
WIRE 816 352 816 320
WIRE 816 352 624 352
WIRE -512 432 -512 368
WIRE 816 432 816 352
WIRE 464 464 416 464
WIRE 464 528 464 464
WIRE -16 640 -16 560
WIRE 208 640 208 560
WIRE 464 656 464 608
WIRE -16 800 -16 720
SYMBOL res 640 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 144 -224 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -96 -224 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 24
SYMBOL res 448 512 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL AD5423 80 224 R0
SYMATTR InstName U1
SYMBOL res 560 208 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL res 800 224 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL voltage -512 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(1 2 100u 1u 1u 1m)
SYMBOL res 624 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage -16 736 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
FLAG 208 640 0
FLAG -16 800 0
FLAG -96 -384 0
FLAG 464 656 0
FLAG 160 -384 0
FLAG -512 432 0
FLAG 816 432 0
FLAG -512 224 IN
FLAG 864 224 OUT
TEXT 504 -64 Left 2 !.tran 200u
* Z:\home\khalils\Downloads\files\data\raw_asc\1d9b6b8aa757_inv_20_10.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Out In 0 0 nfet l=180n w=360n
M2 Out In N001 N001 pfet l=180n w=720n
V1 N001 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib osu018.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1196 680
WIRE 448 -432 256 -432
WIRE 256 -400 256 -432
WIRE 448 -304 448 -432
WIRE 464 -304 448 -304
WIRE 400 -288 368 -288
WIRE 464 -256 464 -304
WIRE 464 -256 448 -256
WIRE 368 -176 368 -288
WIRE 368 -176 304 -176
WIRE 448 -176 448 -208
WIRE 624 -176 448 -176
WIRE 464 -128 448 -128
WIRE 368 -96 368 -176
WIRE 400 -96 368 -96
WIRE 464 -80 464 -128
WIRE 464 -80 448 -80
WIRE 448 -32 448 -80
FLAG 304 -176 In
IOPIN 304 -176 In
FLAG 624 -176 Out
IOPIN 624 -176 Out
FLAG 448 -32 0
FLAG 256 -320 0
SYMBOL nmos4 400 -176 R0
WINDOW 0 119 20 Right 2
WINDOW 3 157 46 Right 2
WINDOW 123 238 76 Right 2
SYMATTR InstName M1
SYMATTR Value nfet
SYMATTR Value2 l=180n w=360n
SYMBOL pmos4 400 -208 M180
WINDOW 0 116 21 Right 2
WINDOW 3 151 49 Right 2
WINDOW 123 206 76 Right 2
SYMATTR InstName M2
SYMATTR Value pfet
SYMATTR Value2 l=180n w=720n
SYMBOL voltage 256 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
TEXT 504 8 Left 2 !.lib osu018.lib