Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\06a54b5845e1_Fig18_5.asc
* Generated by LTspice 26.0.1 for Windows.
VDD VDD 0 1
M3 VDD Vout N002 0 N_50n l=50n w=1.125u
M1 N002 Vin 0 0 N_50n l=50n w=500n
M5 VDD Vin N001 VDD P_50n l=50n w=1u
M4 N001 Vin Vout VDD P_50n l=50n w=1u
M6 N001 Vout 0 VDD P_50n l=50n w=1.3u
Vin Vin 0 PULSE(0 1 0 100n 100n 1n 2u)
M2 Vout Vin N002 0 N_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 200n
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 160 -496 160 -512
WIRE 160 -480 160 -496
WIRE 160 -368 160 -400
WIRE 160 -192 160 -208
WIRE 160 -96 160 -112
WIRE 320 -208 304 -208
WIRE 368 -272 368 -432
WIRE 368 -208 320 -208
WIRE 368 -208 368 -272
WIRE 368 -96 368 -208
WIRE 368 64 368 -96
WIRE 400 -432 368 -432
WIRE 400 -272 368 -272
WIRE 400 -96 368 -96
WIRE 400 64 368 64
WIRE 448 -512 448 -560
WIRE 448 -384 448 -416
WIRE 448 -352 448 -384
WIRE 448 -208 448 -256
WIRE 448 -176 448 -208
WIRE 448 -48 448 -80
WIRE 448 -16 448 -48
WIRE 448 128 448 80
WIRE 688 -384 448 -384
WIRE 720 -48 448 -48
WIRE 736 -208 448 -208
WIRE 736 -96 736 -208
WIRE 768 -208 736 -208
WIRE 768 -208 768 -336
WIRE 848 -384 784 -384
WIRE 848 -352 848 -384
WIRE 848 -48 816 -48
WIRE 848 -48 848 -112
WIRE 992 -208 768 -208
WIRE 1024 -208 992 -208
SYMBOL nmos4 816 -96 R90
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M3
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=1.125u
SYMBOL voltage 160 -208 R0
WINDOW 0 -72 21 Left 0
WINDOW 3 -149 149 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value PULSE(0 1 0 100n 100n 1n 2u)
SYMBOL pmos4 400 -352 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 400 -176 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M2
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 160 -496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 688 -336 R270
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1.3u
SYMBOL pmos4 400 -512 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M5
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 400 -16 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
FLAG 160 -96 0
FLAG 160 -208 Vin
FLAG 448 32 0
FLAG 160 -368 0
FLAG 160 -496 VDD
FLAG 448 -464 VDD
FLAG 448 128 0
FLAG 448 -560 VDD
FLAG 320 -208 Vin
FLAG 448 -304 VDD
FLAG 448 -128 0
FLAG 992 -208 Vout
FLAG 736 -384 VDD
FLAG 768 -48 0
FLAG 848 -112 VDD
FLAG 848 -352 0
TEXT 88 -16 Left 0 !.tran 200n
TEXT 24 24 Left 0 !.lib cmosedu_models.txt
* Z:\home\khalils\Downloads\files\data\raw_asc\0046ec7e49c5_question13.asc
* Generated by LTspice 26.0.1 for Windows.
C1 out N001 1n
C2 out 0 2n
V1 N001 0 PULSE(0 1 1u 0.1u 0.1u 0.4u 1u)
.tran 2u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 48 96
WIRE 240 96 224 96
WIRE 304 96 240 96
WIRE 48 128 48 96
WIRE 304 128 304 96
IOPIN 240 96 Out
SYMBOL cap 288 128 R0
SYMATTR InstName C2
SYMATTR Value 2n
SYMBOL voltage 48 112 R0
WINDOW 3 -170 130 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 1 1u 0.1u 0.1u 0.4u 1u)
SYMATTR InstName V1
SYMBOL cap 224 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
FLAG 48 208 0
FLAG 304 192 0
FLAG 240 96 out
TEXT 40 320 Left 2 !.tran 2u
* Z:\home\khalils\Downloads\files\data\raw_asc\05df4343e063_sigma_delta_dual.asc
* Generated by LTspice 26.0.1 for Windows.
V2 Vee 0 -5
V1 Vcc 0 +5
R1 N004 in 10k
R2 N004 N002 10k
R3 N003 Vcc 10k
R4 0 N003 10k
C1 N005 N004 1n
A1 N006 0 N007 0 0 out N001 0 DFLOP Vhigh=5 Td=5n
Vclock1 N007 0 PULSE(0 5 0 0 0 0.5u 1u 1000000)
V3 in 0 SINE(0 4 1000 0 0 0 10)
XU3 N001 N003 Vcc Vee N002 LTC6752 ;pnba +In)-In)VCC)VEE)Q
XU2 N005 0 Vcc Vee N006 LTC6752 ;pnba +In)-In)VCC)VEE)Q
XU1 0 N004 Vcc Vee N005 AD8033 ;pnba In+)In-)V+)V-)OUT
.tran 0 1m 1u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8033.asy)
.lib ADI.lib
* Library below included based on ModelFile attribute of instance XU3, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LTC6752.asy)
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 680
WIRE 960 80 640 80
WIRE 576 96 112 96
WIRE 784 112 640 112
WIRE 784 160 784 112
WIRE 880 160 864 160
WIRE 880 176 880 160
WIRE 112 224 112 96
WIRE 176 224 112 224
WIRE 288 224 256 224
WIRE 320 224 288 224
WIRE 480 224 384 224
WIRE 928 272 816 272
WIRE 816 304 816 272
WIRE 144 320 112 320
WIRE 176 320 144 320
WIRE 288 320 288 224
WIRE 288 320 256 320
WIRE 352 320 288 320
WIRE 480 336 480 224
WIRE 480 336 416 336
WIRE 560 336 480 336
WIRE 352 352 336 352
WIRE 736 352 624 352
WIRE 960 352 960 80
WIRE 960 352 896 352
WIRE 112 368 112 320
WIRE 560 368 528 368
WIRE 336 400 336 352
WIRE 528 400 528 368
WIRE 736 400 672 400
WIRE 960 400 912 400
WIRE 816 464 816 448
WIRE 928 464 928 272
WIRE 928 464 816 464
WIRE 816 480 816 464
WIRE 672 528 672 400
FLAG 384 368 Vee
FLAG 496 528 Vee
FLAG 400 528 Vcc
FLAG 384 304 Vcc
FLAG 608 64 Vee
FLAG 496 608 0
FLAG 400 608 0
FLAG 704 160 Vcc
FLAG 880 176 0
FLAG 528 400 0
FLAG 816 480 0
FLAG 672 608 0
FLAG 112 448 0
FLAG 336 400 0
FLAG 608 128 Vcc
FLAG 592 320 Vee
FLAG 960 400 out
FLAG 144 320 in
FLAG 592 384 Vcc
SYMBOL voltage 496 512 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 400 512 R0
SYMATTR InstName V1
SYMATTR Value +5
SYMBOL res 272 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 272 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 800 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 880 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 384 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL Digital/dflop 816 304 R0
SYMATTR InstName A1
SYMATTR SpiceLine Vhigh=5 Td=5n
SYMBOL voltage 672 512 R0
SYMATTR InstName clock1
SYMATTR Value PULSE(0 5 0 0 0 0.5u 1u 1000000)
SYMBOL voltage 112 352 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 4 1000 0 0 0 10)
SYMBOL Comparators/LTC6752 608 160 R180
SYMATTR InstName U3
SYMBOL Comparators/LTC6752 592 416 M180
SYMATTR InstName U2
SYMBOL OpAmps/AD8033 384 272 R0
SYMATTR InstName U1
TEXT 96 600 Left 2 !.tran 0 1m 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\1f056e9e82d7_COMB07op.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
R2 B E {R2}
V2 0 Vnn {Vs}
Q1 C B E 0 TBJ
V3 N001 0 {Vi}
XU2 C N001 0 Vnn G level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V1 Vpp 0 {Vs}
J1 C G B JFET
R1 0 C {R1}
RL E Vnn {RL}
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.op
.model JFET NJF(Beta=4m Vto=-3)
.param Vi=-1.75 Vs=20 R1=100 R2=3.9k RL=36
.model TBJ NPN(IS=10f BF=75)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 1076
WIRE 1200 -16 1200 -64
WIRE 1088 112 880 112
WIRE 1200 112 1200 64
WIRE 1200 112 1088 112
WIRE 1088 144 1088 112
WIRE 1200 176 1200 112
WIRE 1376 176 1328 176
WIRE 880 192 880 112
WIRE 928 192 880 192
WIRE 1328 192 1328 176
WIRE 1008 208 992 208
WIRE 1040 208 1008 208
WIRE 1376 208 1376 176
WIRE 928 224 848 224
WIRE 1200 224 1200 176
WIRE 1088 272 1088 240
WIRE 1136 272 1088 272
WIRE 848 304 848 224
WIRE 1088 320 1088 272
WIRE 848 416 848 384
WIRE 1088 432 1088 400
WIRE 1200 432 1200 320
WIRE 1200 432 1088 432
WIRE 1088 464 1088 432
WIRE 1088 576 1088 544
SYMBOL njf 1040 144 R0
SYMATTR InstName J1
SYMATTR Value JFET
SYMBOL OpAmps\\UniversalOpAmp2 960 208 M180
WINDOW 0 27 36 Left 2
SYMATTR InstName U2
SYMBOL voltage 1376 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vs}
SYMBOL voltage 1376 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vs}
SYMBOL res 1072 304 R0
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL res 1072 448 R0
SYMATTR InstName RL
SYMATTR Value {RL}
SYMBOL res 1184 -32 R0
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL npn 1136 224 R0
SYMATTR InstName Q1
SYMATTR Value TBJ
SYMBOL voltage 848 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value {Vi}
FLAG 1088 272 B
FLAG 1200 176 C
FLAG 1008 208 G
FLAG 1376 96 Vpp
FLAG 1328 192 0
FLAG 1376 288 Vnn
FLAG 1200 432 E
FLAG 848 416 0
FLAG 1088 576 Vnn
FLAG 1200 -64 0
FLAG 960 176 Vnn
FLAG 960 240 0
TEXT 344 -56 Left 2 !.op
TEXT 344 8 Left 2 !.model JFET NJF(Beta=4m Vto=-3)
TEXT 344 -24 Left 2 !.param Vi=-1.75 Vs=20 R1=100 R2=3.9k RL=36
TEXT 344 40 Left 2 !.model TBJ NPN(IS=10f BF=75)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7112-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7112-1.8.asy)
C2 N001 0 4.7n
C1 OUT 0 2.2 Rser=1.5m
Rload OUT 0 10
V1 IN 0 2.7
XU1 IN OUT IN N001 OUT 0 ADP7118 Vref=1.8 ;pnba Vin)Sense)EN)SS)Vout)GND
.tran 6m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2.7
SYMBOL ADP7112-1.8 224 128 R0
SYMATTR InstName U1
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
TEXT 408 264 Left 2 !.tran 6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD4021.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4021.asy)
R2 N006 N007 10
V3 N001 0 5
R1 N004 N003 10
C1 0 N005 10p
V2 N007 0 PWL(0 5 100u 0)
V4 N008 0 PULSE(0 1.8 227n 0.1n 0.1n 40n 1u)
V1 N003 0 PWL(0 0 100u 5)
XU1 N001 N002 N004 MP_01 0 N006 N005 N008 AD4021 EN_Hi_Z=1 ;pnba REF)Vdd)IN+))GND)IN-)Vout)CNV
V6 N002 0 1.8
.tran 110u
.lib AD4021.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 1252
WIRE 704 224 368 224
WIRE 832 224 784 224
WIRE 368 288 368 224
WIRE 704 336 496 336
WIRE 832 336 784 336
WIRE -208 368 -240 368
WIRE -80 368 -128 368
WIRE 80 368 0 368
WIRE 80 416 80 368
WIRE 144 416 80 416
WIRE 560 432 496 432
WIRE 688 432 624 432
WIRE 144 448 80 448
WIRE -208 496 -240 496
WIRE -80 496 -128 496
WIRE 80 496 80 448
WIRE 80 496 0 496
WIRE 704 528 496 528
WIRE 832 528 784 528
WIRE 368 608 368 576
SYMBOL AD4021 400 432 R0
SYMATTR InstName U1
SYMBOL voltage 688 528 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 1.8 227n 0.1n 0.1n 40n 1u)
SYMBOL voltage -112 496 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 5 100u 0)
SYMBOL voltage 688 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 688 336 M90
WINDOW 0 47 41 VRight 2
WINDOW 3 -44 39 VRight 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V6
SYMATTR Value 1.8
SYMBOL cap 624 416 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL res 16 480 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL voltage -112 368 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 100u 5)
SYMBOL res 16 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
FLAG 368 608 0
FLAG 832 336 0
FLAG -240 368 0
FLAG 688 432 0
FLAG 832 528 0
FLAG 832 224 0
FLAG -240 496 0
TEXT 152 616 Left 2 !.tran 110u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6654-1.25.asc
* Generated by LTspice 26.0.1 for Windows.
* Turn on and off 5mA of sink current\nand then on and off 5mA of source current
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6654-1.25.asy)
C1 OUT 0 1
XU1 0 IN OUT LT6654-1.25 ;pnba GND)IN)OUT
V2 N002 0 PULSE(0 1 600u 10n 10n 200u 10m)
V3 N001 0 PULSE(0 1 100u 10n 10n 200u 10m)
S2 OUT IN N001 0 5mA
S1 0 OUT N002 0 5mA
V1 IN 0 2
.tran 1m
.model 5mA SW(Ron=10 Roff=1Meg Vt=.5 Vh=-.1 Ilimit=5m level=2)
.lib LT6654-1.25.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4212 1120
WIRE 2304 224 1840 224
WIRE 2304 256 2304 224
WIRE 2608 272 2352 272
WIRE 2720 272 2688 272
WIRE 2368 320 2352 320
WIRE 1840 384 1840 224
WIRE 1840 384 1744 384
WIRE 1872 384 1840 384
WIRE 2176 384 2096 384
WIRE 2304 384 2304 336
WIRE 2304 384 2176 384
WIRE 2400 384 2304 384
WIRE 1744 400 1744 384
WIRE 2176 400 2176 384
WIRE 2304 416 2304 384
WIRE 2608 432 2352 432
WIRE 2720 432 2688 432
WIRE 1984 480 1984 448
WIRE 2176 480 2176 464
WIRE 2368 480 2352 480
WIRE 1744 496 1744 480
WIRE 2304 512 2304 496
SYMBOL sw 2304 352 R180
WINDOW 0 -17 112 Right 2
WINDOW 3 -12 4 Right 2
SYMATTR InstName S2
SYMATTR Value 5mA
SYMBOL voltage 1744 384 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL sw 2304 512 R180
WINDOW 0 -15 104 Right 2
WINDOW 3 -11 15 Right 2
SYMATTR InstName S1
SYMATTR Value 5mA
SYMBOL LT6654-1.25 1984 384 R0
SYMATTR InstName U1
SYMBOL voltage 2592 432 R270
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 600u 10n 10n 200u 10m)
SYMBOL cap 2160 400 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 2592 272 M90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 1 100u 10n 10n 200u 10m)
SYMATTR InstName V3
FLAG 1984 480 0
FLAG 2400 384 OUT
FLAG 1744 384 IN
FLAG 1744 496 0
FLAG 2176 480 0
FLAG 2304 512 0
FLAG 2368 480 0
FLAG 2720 432 0
FLAG 2368 320 0
FLAG 2720 272 0
TEXT 2144 600 Left 2 !.tran 1m\n.model 5mA SW(Ron=10 Roff=1Meg Vt=.5 Vh=-.1 Ilimit=5m level=2)
TEXT 1952 208 Bottom 2 ;Turn on and off 5mA of sink current\nand then on and off 5mA of source current
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3528.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3528.asy)
C1 OUT 0 10 Rser=1m
R1 OUT N002 499K
R2 N002 0 287K
L1 IN N001 4.7 Rpar=5K
V1 IN 0 2
Rload OUT 0 8.25
XU1 IN N002 NC_01 OUT N001 0 0 IN LTC3528 ;pnba _SHDN)FB)Pgood)Vout)SW)PGND)SGND)Vin
.tran 500u startup
.lib LTC3528.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 64 -112 64
WIRE 64 64 -32 64
WIRE 96 64 64 64
WIRE 192 64 176 64
WIRE -112 80 -112 64
WIRE 64 112 64 64
WIRE 192 112 192 64
WIRE -112 176 -112 160
WIRE -32 192 -32 64
WIRE -16 192 -32 192
WIRE 320 192 272 192
WIRE 432 192 320 192
WIRE 512 192 432 192
WIRE 320 208 320 192
WIRE 432 208 432 192
WIRE 512 208 512 192
WIRE 320 304 320 288
WIRE 320 304 272 304
WIRE 432 304 432 272
WIRE 512 304 512 288
WIRE 320 320 320 304
WIRE 64 400 64 384
WIRE 192 400 192 384
WIRE 320 416 320 400
SYMBOL res 304 304 R0
SYMATTR InstName R2
SYMATTR Value 287K
SYMBOL voltage -112 64 R0
WINDOW 0 20 15 Left 2
WINDOW 3 25 97 Left 2
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL PowerProducts\\LTC3528 128 256 R0
SYMATTR InstName U1
SYMBOL res 304 192 R0
SYMATTR InstName R1
SYMATTR Value 499K
SYMBOL cap 416 208 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=1m
SYMBOL res 496 192 R0
SYMATTR InstName Rload
SYMATTR Value 8.25
SYMBOL ind 80 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rpar=5K
FLAG -112 176 0
FLAG 64 400 0
FLAG 320 416 0
FLAG 432 304 0
FLAG 512 304 0
FLAG 192 400 0
FLAG 512 192 OUT
FLAG -112 64 IN
TEXT 440 456 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\3c696e2f26dc_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 N003 D
C1 N001 0 C
L1 0 N004 L
R2 N001 N002 R
R1 N003 N004 R
V1 N002 N003 V
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1000 750
WIRE 156 412 156 512
WIRE 156 192 156 332
WIRE 536 156 536 224
WIRE 536 288 536 708
WIRE 156 412 156 512
WIRE 156 592 156 672
WIRE 536 288 536 708
WIRE 156 672 252 672
WIRE 332 672 536 672
WIRE 156 192 292 192
WIRE 372 156 536 156
WIRE 156 440 324 440
WIRE 388 412 536 412
WIRE 372 156 372 192
WIRE 388 412 388 440
SYMBOL voltage 156 316 R0
SYMATTR InstName V1
SYMBOL diode 388 424 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMBOL res 388 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName R2
SYMBOL res 140 496 R0
SYMATTR InstName R1
SYMBOL cap 520 224 R0
SYMATTR InstName C1
SYMBOL ind 348 656 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName L1
FLAG 536 708 0
* Z:\home\khalils\Downloads\files\data\raw_asc\1b0d2bd59ecb_Simple_Switch_series.asc
* Generated by LTspice 26.0.1 for Windows.
* Simulation
* Spice Directives
* Switch Model & Control
S1 Vo N001 Vsw 0 MYSW
R1 Vo 0 200
V2 Vsw 0 PULSE(0 1 0 1u 1u 5m 10m)
V1 N001 0 SINE(0 5 1k)
.tran 0 10m 0 100u
.model MYSW SW(Ron=0.1 Roff=1000Meg Vt=.5 Vh=.4)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1432 696
WIRE 416 192 416 176
WIRE 464 192 464 160
WIRE 400 240 304 240
WIRE 512 240 480 240
WIRE 304 304 304 240
WIRE 512 320 512 240
WIRE 688 352 688 336
WIRE 304 448 304 384
WIRE 512 448 512 400
WIRE 512 448 304 448
WIRE 688 464 688 432
WIRE 304 480 304 448
RECTANGLE Normal 848 224 640 160 2
RECTANGLE Normal 1328 528 640 272 2
RECTANGLE Normal 864 112 640 64 2
SYMBOL sw 496 240 R90
WINDOW 0 -30 91 VRight 2
WINDOW 3 50 18 VRight 2
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL voltage 304 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1k)
SYMBOL voltage 688 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 1u 1u 5m 10m)
SYMBOL res 496 304 R0
SYMATTR InstName R1
SYMATTR Value 200
FLAG 304 480 0
FLAG 464 160 0
FLAG 416 176 Vsw
FLAG 688 336 Vsw
FLAG 688 464 0
FLAG 512 240 Vo
TEXT 640 48 Left 2 ;Simulation
TEXT 648 88 Left 2 !.tran 0 10m 0 100u
TEXT 640 144 Left 2 ;Spice Directives
TEXT 664 504 Left 2 !.model MYSW SW(Ron=0.1 Roff=1000Meg Vt=.5 Vh=.4)
TEXT 640 256 Left 2 ;Switch Model & Control
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1720.asc
* Generated by LTspice 26.0.1 for Windows.
* 2.7 to 6V Crystal Oscillator with TTL/CMOS Output
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT1720.asy)
R2 +V N002 2K
R1 N002 0 620
R4 OUT P001 220
XU1 N002 N001 +V 0 OUT LT1720 ;pnba In+)In-)V+)V-)OUT
R3 OUT N001 2K
V1 +V 0 3.3
C2 N001 0 .1
C1 P001 N002 1.6p Rser=45 Lser=15.6m Cpar=6p
R5 N001 0 1.8K
.tran 250u startup
.lib LT1720.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1236 800
WIRE 144 64 128 64
WIRE 240 64 208 64
WIRE 144 160 128 160
WIRE 240 160 240 64
WIRE 240 160 224 160
WIRE 320 160 240 160
WIRE 416 160 400 160
WIRE 48 256 48 240
WIRE 304 256 304 224
WIRE 240 272 240 160
WIRE 272 272 240 272
WIRE 416 288 416 160
WIRE 416 288 336 288
WIRE 448 288 416 288
WIRE 272 304 240 304
WIRE 160 320 160 304
WIRE 304 336 304 320
WIRE 48 352 48 336
WIRE 160 416 160 400
WIRE 240 416 240 304
WIRE 240 416 160 416
WIRE 256 416 240 416
WIRE 416 416 416 288
WIRE 416 416 400 416
WIRE 160 432 160 416
WIRE 160 528 160 512
SYMBOL res 240 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1.8K
SYMBOL res 144 416 R0
SYMATTR InstName R1
SYMATTR Value 620
SYMBOL res 416 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 2K
SYMBOL res 416 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 220
SYMBOL Comparators\\LT1720 304 224 R0
SYMATTR InstName U1
SYMBOL voltage 48 240 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 208 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL res 144 304 R0
SYMATTR InstName R2
SYMATTR Value 2K
SYMBOL misc\\xtal 320 400 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1.6p
SYMATTR SpiceLine Rser=45 Lser=15.6m Cpar=6p
FLAG 48 352 0
FLAG 48 240 +V
FLAG 304 224 +V
FLAG 160 304 +V
FLAG 160 528 0
FLAG 128 64 0
FLAG 304 336 0
FLAG 128 160 0
FLAG 448 288 OUT
TEXT 336 488 Left 2 !.tran 250u startup
TEXT 392 16 Bottom 2 ;2.7 to 6V Crystal Oscillator with TTL/CMOS Output
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4860.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
Vin IN 0 SINE(0 1 1K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -5
Rload OUT 0 10K
XU1 IN N001 +V -V OUT N002 ADA4860 ;pnba 1)2)Vcc)Vee)Vout)PD
V3 N002 0 -5
.tran 10m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4860.asy)
.lib ADA4860.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 384 -1088
WIRE 752 -1088 752 -1104
WIRE 384 -1072 384 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 560 -1056 560 -1072
WIRE 592 -1040 592 -1072
WIRE 752 -992 752 -1008
WIRE 384 -976 384 -992
WIRE 592 -944 592 -960
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 384 -976 0
FLAG 752 -1104 OUT
FLAG 384 -1088 IN
FLAG 560 -1136 +V
FLAG 256 -1168 -V
FLAG 560 -1056 -V
FLAG 416 -1216 0
FLAG 752 -992 0
FLAG 256 -1056 0
FLAG 592 -944 0
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 384 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
WINDOW 0 17 18 Left 2
WINDOW 3 17 96 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 1K)
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL ADA4860 576 -1104 R0
WINDOW 0 17 -21 Left 2
WINDOW 3 25 19 Left 2
SYMATTR InstName U1
SYMBOL voltage 592 -1056 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName V3
SYMATTR Value -5
TEXT 696 -944 Left 2 !.tran 10m