Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3509.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 IN OUT N006 N005 0 N004 N001 N002 N003 LT3509 ;pnba Vin)BD)FB)Run/SS)GND)DA)Boost)SW)Rt
L1 N002 OUT 10
D1 N004 N002 MBRS140
C1 N001 N002 .1
R1 OUT N006 53.6K
R2 N006 0 10.2K
C2 OUT 0 22
R3 N003 0 60.4K
C3 N005 0 .001
V1 IN 0 10
Rload OUT 0 7
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3509.asy)
.lib LT3509.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 680
WIRE 608 -16 64 -16
WIRE 64 64 64 -16
WIRE 96 64 64 64
WIRE 432 64 384 64
WIRE 432 80 432 64
WIRE 96 160 -144 160
WIRE 432 160 432 144
WIRE 432 160 384 160
WIRE 496 160 432 160
WIRE 608 160 608 -16
WIRE 608 160 576 160
WIRE 704 160 608 160
WIRE 800 160 704 160
WIRE -144 176 -144 160
WIRE 432 176 432 160
WIRE 704 176 704 160
WIRE 800 176 800 160
WIRE 0 256 -32 256
WIRE 96 256 80 256
WIRE 432 256 432 240
WIRE 432 256 384 256
WIRE 608 256 608 160
WIRE -144 272 -144 256
WIRE 704 272 704 240
WIRE 800 272 800 256
WIRE 0 352 -32 352
WIRE 96 352 64 352
WIRE 608 352 608 336
WIRE 608 352 384 352
WIRE 608 368 608 352
WIRE 240 416 240 400
WIRE 608 464 608 448
FLAG 608 464 0
FLAG 704 272 0
FLAG 240 416 0
FLAG -144 272 0
FLAG -32 352 0
FLAG -32 256 0
FLAG -144 160 IN
FLAG 800 272 0
FLAG 800 160 OUT
SYMBOL PowerProducts\\LT3509 240 208 R0
SYMATTR InstName U1
SYMBOL ind 480 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL schottky 416 240 M180
WINDOW 0 35 53 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 416 80 R0
WINDOW 3 25 55 Left 2
SYMATTR Value .1
SYMATTR InstName C1
SYMBOL res 592 240 R0
SYMATTR InstName R1
SYMATTR Value 53.6K
SYMBOL res 592 352 R0
SYMATTR InstName R2
SYMATTR Value 10.2K
SYMBOL cap 688 176 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 60.4K
SYMBOL cap 64 336 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL voltage -144 160 R0
WINDOW 3 26 99 Left 2
SYMATTR Value 10
SYMATTR InstName V1
SYMBOL res 784 160 R0
SYMATTR InstName Rload
SYMATTR Value 7
TEXT 728 368 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2370-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2370-1.8.asy)
C1 OUT 0 10
Rload OUT 0 20
V1 IN 0 12
XU1 NC_01 IN IN IN N002 OUT N001 0 ADP2370-1.8 IPSM=400m Rt=277777.8 Rb=222222.2 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=0 ;pnba FSEL)SYNC)EN)Vin)SW)FB)PG)PGND
R1 OUT N001 10K
L1 N002 OUT 10 Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
.tran 500u startup
.lib ADP2370-1.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 692
WIRE 128 96 16 96
WIRE 176 96 128 96
WIRE 480 96 400 96
WIRE 640 96 560 96
WIRE 16 112 16 96
WIRE 128 176 128 96
WIRE 176 176 128 176
WIRE 432 176 400 176
WIRE 560 176 512 176
WIRE 640 176 640 96
WIRE 640 176 560 176
WIRE 720 176 640 176
WIRE 720 192 720 176
WIRE 16 208 16 192
WIRE 128 336 128 176
WIRE 560 256 560 240
WIRE 560 256 400 256
WIRE 560 272 560 256
WIRE 720 288 720 272
WIRE 176 336 128 336
WIRE 640 336 640 176
WIRE 640 336 400 336
SYMBOL res 704 176 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL cap 544 176 R0
WINDOW 0 29 15 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2370-1.8 288 208 R0
SYMATTR InstName U1
SYMBOL ind 416 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
SYMBOL VOLTAGE 16 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 576 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
FLAG 16 208 0
FLAG 16 96 IN
FLAG 560 272 0
FLAG 720 176 OUT
FLAG 720 288 0
TEXT 552 368 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\604dcace2bb1_Vbe_break.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N003 N001 VBEDIO
Q1 0 N001 N003 0 2N2907
V1 in 0 0
R1 in N001 1k
R2 N003 0 1k
R3 in N002 1k
R4 N004 0 1k
XQ2 0 N002 N004 Q2N2907 ;pnba C)B)E
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 -10 10 0.1
.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
.SUBCKT Q2N2907 C B E
Q1 C B E 2N2907
D1 E B DEB
*Choose Is of diode 10^-10 lower than Is of transistor
.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)
.ENDS
* With external diode
* With subcircuit
* Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal transistor operation.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1480 744
WIRE 304 224 304 288
WIRE 304 480 -128 480
WIRE 208 208 208 176
WIRE 208 176 240 176
WIRE 208 176 48 176
WIRE -128 480 -128 304
WIRE -128 176 -128 224
WIRE -32 176 -128 176
WIRE -128 512 -128 480
WIRE 304 128 304 48
WIRE 304 48 448 48
WIRE 448 48 448 480
WIRE 448 480 304 480
WIRE 304 416 304 480
WIRE 208 272 208 288
WIRE 208 288 304 288
WIRE 304 288 304 336
WIRE 960 224 960 336
WIRE 816 176 896 176
WIRE 960 128 960 48
WIRE 960 48 1104 48
WIRE 1104 48 1104 480
WIRE 1104 480 960 480
WIRE 960 416 960 480
WIRE 736 176 672 176
WIRE 960 512 960 480
FLAG -128 512 0
FLAG -128 176 in
FLAG 672 176 in
FLAG 960 512 0
SYMBOL diode 224 272 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMATTR Value VBEDIO
SYMBOL pnp 240 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL voltage -128 208 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL res -48 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 288 320 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 720 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 944 320 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL pnp 896 128 R0
WINDOW 3 79 79 Left 0
SYMATTR Value Q2N2907
SYMATTR InstName Q2
SYMATTR Prefix X
TEXT -128 -200 Left 0 !.dc V1 -10 10 0.1
TEXT -144 -8 Left 0 !.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
TEXT 640 -136 Left 0 !.SUBCKT Q2N2907  C B E\nQ1 C B E  2N2907\nD1 E B DEB\n*Choose Is of diode 10^-10 lower than Is of transistor\n.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)\n.ENDS
TEXT -136 -56 Left 0 ;With external diode
TEXT 640 -184 Left 0 ;With subcircuit
TEXT -144 -424 Left 0 ;Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal  transistor operation.
RECTANGLE Normal 416 320 96 96
* Z:\home\khalils\Downloads\files\data\raw_asc\1221fc20dfe8_common-gate.asc
* Generated by LTspice 26.0.1 for Windows.
Rl N001 out 10k
Vdd N001 0 3V
Vin in 0 0
M2 out N002 in in TestN l=10u w=100u
VGL N002 0 2V
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model TestN nmos (kp=90u vt0=0.7 lambda=0.01)
.dc Vin 0V 3.0V 0.01V
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 1412
WIRE -96 800 -496 800
WIRE -496 880 -496 800
WIRE -96 880 -96 800
WIRE -96 1024 -96 960
WIRE -96 1072 -96 1024
WIRE -80 1120 -96 1120
WIRE -144 1152 -384 1152
WIRE -80 1168 -80 1120
WIRE -80 1168 -96 1168
WIRE -144 1200 -224 1200
WIRE -96 1200 -96 1168
WIRE -96 1200 -144 1200
WIRE -384 1216 -384 1152
WIRE -224 1216 -224 1200
WIRE -496 1328 -496 960
WIRE -384 1328 -384 1296
WIRE -224 1328 -224 1296
SYMBOL voltage -384 1200 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VGL
SYMATTR Value 2V
SYMBOL voltage -496 864 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vdd
SYMATTR Value 3V
SYMBOL res -112 864 R0
SYMATTR InstName Rl
SYMATTR Value 10k
SYMBOL voltage -224 1200 R0
WINDOW 3 24 44 Left 2
SYMATTR Value 0
SYMATTR InstName Vin
SYMBOL nmos4 -144 1072 R0
SYMATTR InstName M2
SYMATTR Value TestN
SYMATTR Value2 l=10u w=100u
FLAG -496 1328 0
FLAG -224 1328 0
FLAG -96 1024 out
FLAG -144 1200 in
FLAG -384 1328 0
TEXT -680 752 Left 2 !.model TestN nmos (kp=90u vt0=0.7 lambda=0.01)\n.dc Vin 0V 3.0V 0.01V
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-3.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-3.0.asy)
C1 IN 0 1
V1 IN 0 5.5
C2 OUT 0 1
Rload OUT 0 100
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=40000 ;pnba Vout))Sense)GND)En)))Vin
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP124-3.0 256 208 R0
SYMATTR InstName U1
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX44241.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX44241.asy)
V1 IN 0 SINE(0 50m 100k)
Vee 0 Vee 15
Vcc Vcc 0 15
XU1 IN OUT Vcc Vee OUT MAX44241 ;pnba In+)In-)V+)V-)OUT
RL OUT 0 5k
CL OUT 0 15p
.tran 10u
.lib MAX44241.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 656 256 304 256
WIRE 64 288 64 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 656 384 656 256
WIRE 656 384 464 384
WIRE 752 384 656 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 656 416 656 384
WIRE 752 432 752 384
WIRE 64 448 64 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 656 528 656 496
WIRE 752 528 752 496
WIRE 64 544 64 528
WIRE 304 592 304 576
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 100k)
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 15
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 15
SYMBOL cap 736 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL res 640 400 R0
SYMATTR InstName RL
SYMATTR Value 5k
SYMBOL MAX44241 432 320 R0
SYMATTR InstName U1
FLAG 752 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 656 528 0
FLAG 304 400 IN
FLAG 752 528 0
TEXT 16 632 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\4c1d3718d3e5_FDP2532_GateCharge.asc
* Generated by LTspice 26.0.1 for Windows.
* Qgs
* Qgd
* Vgs
* Qg
* VDMOS model
* The Id and Vds value are test conditions specified in the datasheet.
* DUT
+CGDMIN=50p CJO=2648p Vj=0.75 M=0.4812 CGS=5735p N=1 IS=1.00E-14 RB=0.0099 TT=151n)
B1 qg 0 V=idt(-I(V1))
V1 gs 0 PWL(0 0 1m 15)
M1 d gs 0 0 FDP2532
V2 N001 0 {Vds}
B2 0 d I={Id}
D1 d N001 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 1m 0 1u
.options plotwinsize=0
.param Id=16 Vds=75
.model d d ron=1m vfwd=0
.MODEL FDP2532 VDMOS(KP=32.1269 RS=0.0001 RD=0.0094 RG=0.5 VTO=3.0 CGDMAX=1605p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2828 1468
WIRE 16 368 16 352
WIRE 416 416 272 416
WIRE 608 416 416 416
WIRE 640 416 608 416
WIRE 736 416 704 416
WIRE 272 464 272 416
WIRE 16 480 16 448
WIRE 608 512 608 416
WIRE 736 512 736 416
WIRE 80 544 16 544
WIRE 224 544 80 544
WIRE 16 576 16 544
WIRE 16 688 16 656
WIRE 272 688 272 560
WIRE 608 688 608 592
WIRE 736 688 736 592
LINE Normal 936 664 936 408
LINE Normal 1336 664 936 664
LINE Normal 1064 528 936 664
LINE Normal 1192 512 1064 528
LINE Normal 1336 424 1192 512
LINE Normal 936 440 1304 440 2
LINE Normal 1304 656 1304 440 2
LINE Normal 1064 656 1064 528 2
LINE Normal 1192 656 1192 512 2
LINE Normal 1096 632 1064 632
LINE Normal 1192 632 1160 632
LINE Normal 968 632 936 632
LINE Normal 1078 617 1064 632
LINE Normal 1080 648 1064 632
LINE Normal 1174 617 1192 632
LINE Normal 1176 648 1192 632
LINE Normal 952 616 936 632
LINE Normal 952 648 936 632
LINE Normal 1032 632 1064 632
LINE Normal 1048 616 1064 632
LINE Normal 1048 648 1064 632
SYMBOL diode 640 432 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMBOL bv 16 352 R0
SYMATTR InstName B1
SYMATTR Value V=idt(-I(V1))
SYMBOL voltage 16 560 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m 15)
SYMBOL voltage 736 496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vds}
SYMBOL bi 608 592 M180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName B2
SYMATTR Value I={Id}
SYMBOL NMOS 224 464 R0
SYMATTR InstName M1
SYMATTR Value FDP2532
FLAG 608 688 0
FLAG 16 688 0
FLAG 272 688 0
FLAG 16 480 0
FLAG 80 544 gs
FLAG 16 352 qg
FLAG 416 416 d
FLAG 736 688 0
TEXT 8 192 Left 0 !.tran 0 1m 0 1u
TEXT 976 632 Left 0 ;Qgs
TEXT 1104 632 Left 0 ;Qgd
TEXT 888 440 Left 0 ;Vgs
TEXT 1304 688 Left 0 ;Qg
TEXT 8 224 Left 0 !.options plotwinsize=0
TEXT 200 360 Left 0 ;VDMOS model
TEXT 8 136 Left 0 !.param Id=16 Vds=75
TEXT 568 720 Left 0 !.model d d ron=1m vfwd=0
TEXT 8 104 Left 0 ;The Id and Vds value are test conditions specified in the datasheet.
TEXT 280 464 Left 0 ;DUT
TEXT -40 768 Left 0 !.MODEL FDP2532 VDMOS(KP=32.1269 RS=0.0001 RD=0.0094 RG=0.5 VTO=3.0 CGDMAX=1605p \n+CGDMIN=50p CJO=2648p Vj=0.75 M=0.4812 CGS=5735p N=1 IS=1.00E-14 RB=0.0099 TT=151n)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1085-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1085-3.3.asy)
XU1 0 OUT IN LT1085-3.3 ;pnba GND)OUT)IN
Rload OUT 0 10
C1 OUT 0 10
V1 IN 0 PWL(0 0 1 10) Rser=0.1
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1952 896 1808 896
WIRE 2064 896 1952 896
WIRE 1344 912 1344 896
WIRE 1952 912 1952 896
WIRE 2064 912 2064 896
WIRE 1344 1008 1344 992
WIRE 1952 1008 1952 976
WIRE 2064 1008 2064 992
WIRE 1680 1024 1680 992
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
SYMBOL PowerProducts\\LT1085-3.3 1680 896 R0
SYMATTR InstName U1
SYMBOL cap 1936 912 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL RES 2048 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 2064 896 OUT
FLAG 2064 1008 0
FLAG 1344 1008 0
FLAG 1952 1008 0
FLAG 1344 896 IN
FLAG 1680 1024 0
TEXT 1968 1088 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5672R.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5672R.asy)
V1 Vdd 0 5
RLOAD vOUT 0 1k
CLOAD vOUT 0 10n
Vdac vDAC 0 PWL(0 0.625 10u 0.625 +1u 1.875)
XU1 vDAC Vdd 0 vOUT AD5672R Gain=2 ;pnba Vdac)Vdd)GND)Vout
.tran 50u
.lib AD5672R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -240 -208 -240 -240
WIRE -240 -80 -240 -128
WIRE -240 -32 -240 -80
WIRE -528 112 -800 112
WIRE -368 112 -528 112
WIRE 112 112 0 112
WIRE 192 112 112 112
WIRE 272 112 192 112
WIRE -800 144 -800 112
WIRE 112 144 112 112
WIRE 272 160 272 112
WIRE -800 256 -800 224
WIRE 112 272 112 224
WIRE 272 272 272 224
WIRE -240 288 -240 256
SYMBOL voltage -800 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac
SYMATTR Value PWL(0 0.625 10u 0.625 +1u 1.875)
SYMBOL voltage -240 -112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 256 160 R0
SYMATTR InstName CLOAD
SYMATTR Value 10n
SYMBOL AD5672R -208 112 R0
SYMATTR InstName U1
SYMBOL res 96 128 R0
SYMATTR InstName RLOAD
SYMATTR Value 1k
FLAG 192 112 vOUT
FLAG -800 256 0
FLAG -528 112 vDAC
FLAG -240 -240 0
FLAG -240 288 0
FLAG 112 272 0
FLAG 272 272 0
FLAG -240 -80 Vdd
TEXT -160 312 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1097.asc
* Generated by LTspice 26.0.1 for Windows.
* 27V Common Mode Range Difference Amplifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1097.asy)
V3 IN- IN+ SINE(0 1 100)
V1 +V 0 15
V2 -V 0 -15
R3 N001 IN- 50K
V4 IN+ 0 SINE(0 27 1K)
XU1 N002 N001 +V -V OUT LT1097 ;pnba In+)In-)V+)V-)OUT
R2 N002 IN+ 50K
R4 0 N002 50K
R1 OUT N001 50K
.tran 30m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -64 96 -144 96
WIRE -32 96 -64 96
WIRE 128 96 48 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -384 160 -384 144
WIRE -288 160 -288 144
WIRE -144 176 -144 96
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE -384 256 -384 240
WIRE -288 256 -288 240
WIRE 160 256 128 256
WIRE 192 288 192 272
WIRE -144 368 -144 256
WIRE -64 368 -144 368
WIRE 0 368 -64 368
WIRE 128 368 128 256
WIRE 128 368 80 368
WIRE 144 368 128 368
WIRE 256 368 224 368
WIRE -144 384 -144 368
WIRE -144 480 -144 464
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 96 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL opamps\\LT1097 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -144 160 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
SYMBOL res 64 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 50K
SYMBOL res 240 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 50K
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50K
SYMBOL voltage -144 368 R0
SYMATTR InstName V4
SYMATTR Value SINE(0 27 1K)
SYMBOL voltage -384 144 R0
SYMATTR InstName V2
SYMATTR Value -15
FLAG -288 256 0
FLAG 192 192 +V
FLAG -288 144 +V
FLAG 192 288 -V
FLAG -384 256 0
FLAG -384 144 -V
FLAG -144 480 0
FLAG 256 368 0
FLAG 288 240 OUT
FLAG -64 96 IN-
FLAG -64 368 IN+
TEXT 176 448 Left 2 !.tran 30m
TEXT 56 48 Bottom 2 ;27V Common Mode Range Difference Amplifier
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4807-2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
V2 IN 0 SINE(0 0.5 250K)
R1 N001 0 1K
R2 OUT N001 1K
V3 -V 0 -5
XU1 IN N001 +V -V OUT NC_01 ADA4807 ;pnba 100)101)102)103)104)106
.tran 50u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4807-2.asy)
.lib ADA4807.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 512 -1232 496 -1232
WIRE 544 -1232 512 -1232
WIRE 640 -1232 624 -1232
WIRE 176 -1136 176 -1152
WIRE 288 -1136 288 -1152
WIRE 560 -1136 560 -1152
WIRE 512 -1120 512 -1232
WIRE 544 -1120 512 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 704 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 560 -1056 560 -1072
WIRE 176 -1040 176 -1056
WIRE 288 -1040 288 -1056
WIRE 432 -976 432 -992
FLAG 176 -1152 +V
FLAG 176 -1040 0
FLAG 432 -976 0
FLAG 704 -1104 OUT
FLAG 432 -1088 IN
FLAG 560 -1152 +V
FLAG 288 -1152 -V
FLAG 288 -1040 0
FLAG 400 -1232 0
FLAG 560 -1056 -V
SYMBOL voltage 176 -1152 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 0.5 250K)
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 288 -1152 R0
SYMATTR InstName V3
SYMATTR Value -5
SYMBOL opamps\\ADA4807-2 576 -1104 R0
SYMATTR InstName U1
TEXT 728 -976 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\4c5dff18abde_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
R4 N001 N002 1k
V2 N002 0 SINE(0 2 450k)
R1 N001 final 10k
D1 N001 0 1N4148
C1 final 0 4700p
R2 final 0 4.7k
R3 N001 N003 1k
V1 N003 0 SINE(0 3 451k)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 0.01 0 0.00001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 16 -368 16
WIRE 80 32 80 16
WIRE 80 32 -256 32
WIRE -368 48 -368 16
WIRE -256 48 -256 32
WIRE 80 96 80 32
WIRE 80 96 0 96
WIRE 240 96 80 96
WIRE -256 160 -256 128
WIRE 240 208 240 176
WIRE 432 208 240 208
WIRE 448 208 432 208
WIRE -368 240 -368 128
WIRE 240 240 240 208
WIRE 448 240 448 208
WIRE 0 320 0 160
WIRE 240 320 0 320
WIRE 448 320 448 304
WIRE 448 320 240 320
WIRE 240 368 240 320
SYMBOL res -272 32 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL cap 432 240 R0
SYMATTR InstName C1
SYMATTR Value 4700p
SYMBOL res 224 80 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL res 224 224 R0
SYMATTR InstName R2
SYMATTR Value 4.7k
SYMBOL res -384 32 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL diode -16 96 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL Misc\\signal -368 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 3 451k)
SYMBOL Misc\\signal -256 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 2 450k)
FLAG 240 368 0
FLAG 432 208 final
FLAG -368 320 0
FLAG -256 240 0
TEXT -400 392 Left 2 !.tran 0 0.01 0 0.00001
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1259.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1259.asy)
R1 OUT N001 1.6K
XU1 IN N001 +V -V OUT LT1259 ;pnba In+)In-)V+)V-)OUT
R2 N001 0 1.6K
V2 -V 0 -5
V1 +V 0 5
V3 IN 0 SINE(0 1 1K)
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -288 144 -288 128
WIRE -160 144 -160 128
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -288 240 -288 224
WIRE -160 240 -160 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL voltage -160 128 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL opamps\\LT1259 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -288 128 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1.6K
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.6K
FLAG -160 240 0
FLAG 192 192 +V
FLAG -160 128 +V
FLAG 192 288 -V
FLAG -288 240 0
FLAG -288 128 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 288 240 OUT
FLAG 0 256 IN
TEXT 264 336 Left 2 !.tran 3m