* Z:\home\khalils\Downloads\files\data\raw_asc\d2210d36a742_CD4046_VCO.asc
* Generated by LTspice 26.0.1 for Windows.
D1 Cext1 VCC 1N914
D2 Cext2 VCC 1N914
S1c N003 Cext1 PSW 0 SW
S2c N003 Cext2 NSW 0 SW
M1 N003 VCOin R1 R1 BSS123
M2 N003 Th_ref R2 R2 BSS123
S1v Cext1 VCC NSW 0 SW
S2v Cext2 VCC PSW 0 SW
A1 N001 N002 0 0 0 NSW PSW 0 SRFLOP Td=10ns Trise=10ns Tfall=10ns
C1 Cext1 Cext2 10n
A2 Th_ref Cext2 0 0 0 0 N001 0 SCHMITT Vt=0 Vh=0.1
A3 Th_ref Cext1 0 0 0 0 N002 0 SCHMITT Vt=0 Vh=0.1
Bref Th_ref 0 V=V(VCC)*0.6
V1 VCC 0 8.0
V2 VCOin 0 3.0
R3 R1 0 10k
R4 R2 0 100k
B1 VCOout 0 V=V(VCC)*V(PSW)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model SW SW(Ron=10 Roff=10G Vt=0.5)
.tran 5ms
* Simulation of the CMOS4046 VCO\nwith a behaviour similar to the real device\nconcerning the external pins.
* @Author\nAndreas Czechanowski, 2005-12-27
* external components
* NOTES:\n* The value of the threshold reference voltage Th_ref is probably not correct\n* Current-source transistors M1, M2 and diodes D1, D2 should be modelled correctly\n* The output stage is simplified by using Bout\n* The phase of the output voltage is probably inverted
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1140 952
WIRE 48 48 -48 48
WIRE 112 48 112 0
WIRE 112 48 48 48
WIRE 176 48 112 48
WIRE 272 48 176 48
WIRE -48 80 -48 48
WIRE 272 80 272 48
WIRE -96 96 -96 80
WIRE 48 96 48 48
WIRE 176 96 176 48
WIRE 320 96 320 80
WIRE 624 144 624 112
WIRE 752 144 752 112
WIRE -96 160 -96 144
WIRE 320 160 320 144
WIRE -528 192 -528 128
WIRE -496 192 -528 192
WIRE -48 192 -48 160
WIRE 48 192 48 160
WIRE 48 192 -48 192
WIRE 176 192 176 160
WIRE 272 192 272 160
WIRE 272 192 176 192
WIRE -400 208 -432 208
WIRE -496 224 -544 224
WIRE 48 224 48 192
WIRE 48 224 -32 224
WIRE 176 224 176 192
WIRE 256 224 176 224
WIRE -400 240 -400 208
WIRE -368 240 -400 240
WIRE -208 240 -272 240
WIRE -496 256 -496 240
WIRE 624 256 624 224
WIRE 752 256 752 224
WIRE -368 288 -400 288
WIRE -208 288 -256 288
WIRE 48 288 48 224
WIRE 176 288 176 224
WIRE -528 304 -528 192
WIRE -496 304 -528 304
WIRE 0 304 0 288
WIRE 224 304 224 288
WIRE -400 320 -400 288
WIRE -400 320 -432 320
WIRE -496 336 -544 336
WIRE -368 336 -368 320
WIRE 656 336 624 336
WIRE 752 336 720 336
WIRE -496 368 -496 352
WIRE 0 368 0 352
WIRE 224 368 224 352
WIRE 48 400 48 368
WIRE 112 400 48 400
WIRE 176 400 176 368
WIRE 176 400 112 400
WIRE 112 464 112 400
WIRE 112 464 -128 464
WIRE -128 512 -128 464
WIRE 112 512 112 464
WIRE 320 512 272 512
WIRE 272 544 272 512
WIRE -480 576 -480 544
WIRE -176 592 -208 592
WIRE 64 592 32 592
WIRE 608 640 608 576
WIRE 752 640 752 576
WIRE -128 656 -128 608
WIRE 112 656 112 608
WIRE 272 656 272 624
WIRE -480 688 -480 656
WIRE 608 784 608 720
WIRE 752 784 752 720
FLAG -32 224 Cext1
IOPIN -32 224 BiDir
FLAG 256 224 Cext2
IOPIN 256 224 BiDir
FLAG 112 0 VCC
IOPIN 112 0 In
FLAG 224 368 0
FLAG -128 656 R1
IOPIN -128 656 BiDir
FLAG 112 656 R2
IOPIN 112 656 BiDir
FLAG -208 240 PSW
FLAG -208 288 NSW
FLAG 0 368 0
FLAG 0 288 PSW
FLAG 224 288 NSW
FLAG -96 160 0
FLAG 320 160 0
FLAG 320 80 PSW
FLAG -96 80 NSW
FLAG 624 336 Cext1
FLAG 752 336 Cext2
FLAG -368 336 0
FLAG -544 224 Cext2
FLAG -544 336 Cext1
FLAG -480 688 0
FLAG -480 544 Th_ref
FLAG -528 128 Th_ref
FLAG 608 784 0
FLAG 608 576 VCC
FLAG 752 784 0
FLAG 752 576 VCOin
FLAG 32 592 Th_ref
FLAG -208 592 VCOin
IOPIN -208 592 In
FLAG -496 256 0
FLAG -496 368 0
FLAG 624 256 0
FLAG 624 112 R1
FLAG 752 256 0
FLAG 752 112 R2
FLAG 320 512 VCOout
IOPIN 320 512 Out
FLAG 272 656 0
SYMBOL diode 32 160 M180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL diode 192 160 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL sw 48 384 M180
SYMATTR InstName S1c
SYMBOL sw 176 384 R180
SYMATTR InstName S2c
SYMBOL nmos -176 512 R0
SYMATTR InstName M1
SYMATTR Value BSS123
SYMBOL nmos 64 512 R0
SYMATTR InstName M2
SYMATTR Value BSS123
SYMBOL sw -48 176 M180
SYMATTR InstName S1v
SYMBOL sw 272 176 R180
SYMATTR InstName S2v
SYMBOL Digital\\srflop -320 192 R0
WINDOW 3 -58 178 Left 0
SYMATTR Value Td=10ns Trise=10ns Tfall=10ns
SYMATTR InstName A1
SYMBOL cap 656 352 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL Digital\\diffschmtbuf -496 144 R0
WINDOW 3 8 34 Left 0
SYMATTR Value Vt=0 Vh=0.1
SYMATTR InstName A2
SYMBOL Digital\\diffschmtbuf -496 256 R0
WINDOW 3 8 34 Left 0
SYMATTR Value Vt=0 Vh=0.1
SYMATTR InstName A3
SYMBOL bv -480 560 R0
SYMATTR InstName Bref
SYMATTR Value V=V(VCC)*0.6
SYMBOL voltage 608 624 R0
SYMATTR InstName V1
SYMATTR Value 8.0
SYMBOL voltage 752 624 R0
SYMATTR InstName V2
SYMATTR Value 3.0
SYMBOL Misc\\EuropeanResistor 608 128 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL Misc\\EuropeanResistor 736 128 R0
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL bv 272 528 R0
SYMATTR InstName B1
SYMATTR Value V=V(VCC)*V(PSW)
TEXT 136 432 Left 0 !.model SW SW(Ron=10 Roff=10G Vt=0.5)
TEXT 576 464 Left 0 !.tran 5ms
TEXT -536 -56 Left 0 ;Simulation of the CMOS4046 VCO\nwith a behaviour similar to the real device\nconcerning the external pins.
TEXT 136 -48 Left 0 ;@Author\nAndreas Czechanowski, 2005-12-27
TEXT 560 0 Left 0 ;external components
TEXT -584 704 Left 0 ;NOTES:\n* The value of the threshold reference voltage Th_ref is probably not correct\n* Current-source transistors M1, M2 and diodes D1, D2 should be modelled correctly\n* The output stage is simplified by using Bout\n* The phase of the output voltage is probably inverted
RECTANGLE Normal 832 832 544 -16 2