* Z:\home\khalils\Downloads\files\data\raw_asc\1d51fb51c9a6_AD4000_THDS_V02.asc
* Generated by LTspice 26.0.1 for Windows.
* Anti-Aliasing Filter
* Driver Supply
* ADC Supply
* ADC Driver
* Simulation Setup
* Simulation Parameters
* Anti Aliasing Filter
* Simulation cycles\nSample size\nADC reference voltage\nADC supply\nDriver VCC\nDC offset voltage\nSample frequency\nSample Period\nInput frequency\nInput amplitude\nMax time step\nSimulation end
* Rval1\nCval1
* Input
* Driver Parameters
* U2 Rf\nU2 Rg\nGain
* AD4000_THDS_V02
* This circuit may be used to obtain THD results for the AD4000 series pseudo differential ADC\n using the AD4002 macro-model with an AD4807-1 driver in an inverting gain configuration.\n Additional driver models may be inserted via the component menu. Schematic redraw may\n be required. Simulation results produced by the .four SPICE command may be accessed by \nview->SPICE error log and are displayed at the end of the file. For all other performance \ncharacteristics and specifications refer to the AD4000 datasheet located at\nhttps://www.analog.com/en/products/ad4000.html#product-overview
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4002.asy)
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4807-1.asy)
V6 REF 0 {vref_val}
C1 ADCINP 0 {Cval1}
R1 ADCINP N003 {Rval1}
R2 N003 N002 {Rf_val}
V7 VCC 0 {vcc_val}
XU2 VINP N002 VCC 0 N003 VCC ADA4807 ;pnba 100)101)102)103)104)106
XU1 REF VDD ADCINP MP_01 0 N004 MP_02 MP_03 VSAMPLED AD4002 EN_Hi_Z=1 ;pnba REF)Vdd)IN))GND)CNV)))Vout
V4 N004 0 PULSE(0 {vdd_val} 1u 1n 1n 10n {ts})
V2 VINP 0 {Voff}
R3 N002 N001 {Rg_val}
V1 N001 0 SINE({Voff} {vmag} {fin} 0 0 0)
V9 VDD 0 {vdd_val}
.param M=3
.param N=4096
.param vref_val=5
.param vdd_val=1.8
.param vcc_val=7.5
.param voff=vref_val/2
.param fs=2e6
.param ts=1/fs
.param fin= fs*M/N
.param vmag=.93*vref_val/{2*Gain}
.param tmax=1/(fs)
.param END_SIM=M*(1/fin)
.save v(vsampled)
.option plotwinsize=0 numdgt=15
.four {fin} 5 -1 v(vsampled)
.param Rval1=200
.param Cval1=180p
.tran 0 {END_SIM+1/fin} {1/fin}
.param Rf_val=500
.param Rg_val=500
.param Gain={-Rf_val/Rg_val}
.lib AD4002.sub
.lib ADA4807.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3184 1508
WIRE 448 -384 352 -384
WIRE 592 -384 448 -384
WIRE 352 -304 352 -384
WIRE 352 -160 352 -224
WIRE -832 -144 -1088 -144
WIRE -720 -144 -752 -144
WIRE -656 -144 -720 -144
WIRE -512 -144 -576 -144
WIRE 592 -128 592 -384
WIRE 896 -80 896 -176
WIRE 896 -80 720 -80
WIRE -608 -16 -608 -32
WIRE -720 0 -720 -144
WIRE -624 0 -720 0
WIRE -512 16 -512 -144
WIRE -512 16 -560 16
WIRE -304 16 -512 16
WIRE -144 16 -224 16
WIRE 192 16 -144 16
WIRE 352 16 192 16
WIRE 1008 16 720 16
WIRE -624 32 -720 32
WIRE -1088 64 -1088 -144
WIRE -720 64 -720 32
WIRE -144 64 -144 16
WIRE -608 80 -608 48
WIRE -576 80 -576 48
WIRE 896 112 720 112
WIRE -144 176 -144 128
WIRE -1088 192 -1088 144
WIRE -720 192 -720 144
WIRE 592 240 592 160
WIRE 896 336 896 112
WIRE -1968 416 -1968 336
WIRE -1616 416 -1616 336
WIRE 896 512 896 416
WIRE -1968 608 -1968 496
WIRE -1616 608 -1616 496
IOPIN 1008 16 Out
RECTANGLE Normal -32 240 -400 -176 4
RECTANGLE Normal -1360 640 -2208 240 4
RECTANGLE Normal -416 240 -912 -176 4
RECTANGLE Normal -2208 -592 -1360 -432
RECTANGLE Normal -1360 224 -2208 -416 4
RECTANGLE Normal -928 240 -1152 -176 4
SYMBOL voltage -1616 400 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V9
SYMATTR Value {vdd_val}
SYMBOL voltage 352 -320 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V6
SYMATTR Value {vref_val}
SYMBOL res -736 -160 R90
WINDOW 0 10 19 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {Rg_val}
SYMBOL cap -160 64 R0
SYMATTR InstName C1
SYMATTR Value {Cval1}
SYMBOL voltage 896 320 R0
WINDOW 3 73 -155 VRight 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 {vdd_val} 1u 1n 1n 10n {ts})
SYMATTR InstName V4
SYMBOL voltage -720 48 R0
WINDOW 0 -32 56 VBottom 2
WINDOW 3 57 81 Top 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value {Voff}
SYMBOL res -208 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {Rval1}
SYMBOL ADC\\AD4002 624 16 R0
SYMATTR InstName U1
SYMBOL res -560 -160 R90
WINDOW 0 10 19 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {Rf_val}
SYMBOL voltage -1088 48 R0
WINDOW 0 -32 56 VBottom 2
WINDOW 3 173 96 Top 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE({Voff} {vmag} {fin} 0 0 0)
SYMBOL voltage -1968 400 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V7
SYMATTR Value {vcc_val}
SYMBOL Opamps\\ADA4807-1 -592 16 R0
SYMATTR InstName U2
FLAG 896 -176 VDD
FLAG 192 16 ADCINP
FLAG 896 512 0
FLAG 448 -384 REF
FLAG -1968 336 VCC
FLAG -1616 336 VDD
FLAG -1616 608 0
FLAG -1968 608 0
FLAG -1088 192 0
FLAG -720 32 VINP
FLAG 1008 16 VSAMPLED
FLAG -144 176 0
FLAG -608 -32 VCC
FLAG -576 80 VCC
FLAG -608 80 0
FLAG -720 192 0
FLAG 352 -160 0
FLAG 592 240 0
TEXT -336 -200 Left 2 ;Anti-Aliasing Filter
TEXT -2040 256 Left 2 ;Driver Supply
TEXT -1688 256 Left 2 ;ADC Supply
TEXT -728 -200 Left 2 ;ADC Driver
TEXT -2176 -352 Left 2 !.param M=3\n.param N=4096\n.param vref_val=5\n.param vdd_val=1.8\n.param vcc_val=7.5\n.param voff=vref_val/2\n.param fs=2e6\n.param ts=1/fs\n.param fin= fs*M/N\n.param vmag=.93*vref_val/{2*Gain}\n.param tmax=1/(fs)\n.param END_SIM=M*(1/fin)
TEXT -2176 -456 Left 2 !.save v(vsampled)
TEXT -2176 -480 Left 2 !.option plotwinsize=0 numdgt=15
TEXT -2176 -504 Left 2 !.four {fin} 5 -1 v(vsampled)
TEXT -2176 40 Left 2 !.param Rval1=200\n.param Cval1=180p
TEXT -2184 -560 Left 3 ;Simulation Setup
TEXT -2176 -528 Left 2 !.tran 0 {END_SIM+1/fin} {1/fin}
TEXT -2176 -384 Left 3 ;Simulation Parameters
TEXT -2176 16 Left 2 ;Anti Aliasing Filter
TEXT -1704 -352 Left 2 ;Simulation cycles\nSample size\nADC reference voltage\nADC supply\nDriver VCC\nDC offset voltage\nSample frequency\nSample Period\nInput frequency\nInput amplitude\nMax time step\nSimulation end
TEXT -1704 32 Left 2 ;Rval1\nCval1
TEXT -1072 -200 Left 2 ;Input
TEXT -2176 112 Left 2 ;Driver Parameters
TEXT -2176 136 Left 2 !.param Rf_val=500\n.param Rg_val=500\n.param Gain={-Rf_val/Rg_val}
TEXT -1704 128 Left 2 ;U2 Rf\nU2 Rg\nGain
TEXT -2208 -840 Left 4 ;AD4000_THDS_V02
TEXT -2208 -800 Left 2 ;This circuit may be used to obtain THD results for the AD4000 series pseudo differential ADC\n using the AD4002 macro-model with an AD4807-1 driver in an inverting gain configuration.\n Additional driver models may be inserted via the component menu. Schematic redraw may\n be required. Simulation results produced by the .four SPICE command may be accessed by \nview->SPICE error log and are displayed at the end of the file. For all other performance \ncharacteristics and specifications refer to the AD4000 datasheet located at\nhttps://www.analog.com/en/products/ad4000.html#product-overview