Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1875.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1875.asy)
R1 OUT N004 80.6K
L1 N002 OUT 6.2 Rpar=1K
R5 IN N003 1Meg
C1 N005 0 .001
C4 N003 0 .01
R3 N006 N005 150K
R6 IN N001 10K
C3 N008 0 47p
XU1 0 N003 N004 N007 N002 N002 0 IN MP_01 MP_02 MP_03 MP_04 IN N001 0 N006 LTC1875 ;pnba SGND)Run/SS)FB)Ith)SWP)SWN)PGND)PVin)))))SVin)Pgood)Sync/Mode)PLL_LPF
R2 N004 0 28K
C2 OUT 0 47
Rload OUT 0 3
V1 IN 0 5
R4 N007 N008 150K
.tran 5.5m startup
.lib LTC1875.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 700
WIRE 16 0 -80 0
WIRE 112 0 16 0
WIRE 288 0 112 0
WIRE 416 0 288 0
WIRE -80 16 -80 0
WIRE 112 16 112 0
WIRE 16 48 16 0
WIRE 288 48 288 0
WIRE 416 48 416 0
WIRE -80 112 -80 96
WIRE 112 112 112 96
WIRE 192 112 112 112
WIRE 544 112 512 112
WIRE 576 112 544 112
WIRE 688 112 656 112
WIRE 800 112 688 112
WIRE 880 112 800 112
WIRE 688 128 688 112
WIRE 800 128 800 112
WIRE 880 128 880 112
WIRE 16 176 16 128
WIRE 192 176 16 176
WIRE 544 176 544 112
WIRE 544 176 512 176
WIRE 16 192 16 176
WIRE 800 224 800 192
WIRE 880 224 880 208
WIRE 192 240 176 240
WIRE 688 240 688 208
WIRE 688 240 512 240
WIRE 688 256 688 240
WIRE 16 272 16 256
WIRE 96 304 48 304
WIRE 192 304 176 304
WIRE 528 304 512 304
WIRE 624 304 608 304
WIRE 48 320 48 304
WIRE 624 320 624 304
WIRE 688 352 688 336
WIRE 288 384 288 368
WIRE 416 384 416 368
WIRE 48 400 48 384
WIRE 624 400 624 384
SYMBOL res 672 240 R0
SYMATTR InstName R2
SYMATTR Value 28K
SYMBOL RES 672 112 R0
SYMATTR InstName R1
SYMATTR Value 80.6K
SYMBOL res 192 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 150K
SYMBOL cap 608 320 R0
SYMATTR InstName C3
SYMATTR Value 47p
SYMBOL res 864 112 R0
SYMATTR InstName Rload
SYMATTR Value 3
SYMBOL ind 560 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 6.2
SYMATTR SpiceLine Rpar=1K
SYMBOL res 512 288 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 150K
SYMBOL PowerProducts\\LTC1875 352 208 R0
SYMATTR InstName U1
SYMBOL res 96 0 R0
SYMATTR InstName R6
SYMATTR Value 10K
SYMBOL VOLTAGE -80 0 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 0 192 R0
WINDOW 3 25 54 Left 2
SYMATTR Value .01
SYMATTR InstName C4
SYMBOL res 0 32 R0
SYMATTR InstName R5
SYMATTR Value 1Meg
SYMBOL cap 32 320 R0
SYMATTR InstName C1
SYMATTR Value .001
SYMBOL polcap 784 128 R0
SYMATTR InstName C2
SYMATTR Value 47
FLAG -80 112 0
FLAG 288 384 0
FLAG 48 400 0
FLAG 800 224 0
FLAG 688 352 0
FLAG 880 224 0
FLAG 880 112 OUT
FLAG 416 384 0
FLAG 624 400 0
FLAG 176 240 0
FLAG 16 272 0
FLAG -80 0 IN
TEXT 744 400 Left 2 !.tran 5.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\063614342f76_Switch.asc
* Generated by LTspice 26.0.1 for Windows.
V3 N003 0 PULSE(0 5 10 1n 1n 5 10 1)
R3 N001 N002 10k
S2 N004 N002 N003 0 SW
V2 N001 0 14.8
I2 N004 0 3
.model SW SW(Ron=1p Roff=100G Vt=0.5 Vh=0)
.tran 36
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2092 1124
WIRE -944 192 -1616 192
WIRE -1616 240 -1616 192
WIRE -944 272 -944 192
WIRE -944 544 -944 352
WIRE -992 560 -1424 560
WIRE -1424 624 -1424 560
WIRE -944 640 -944 624
WIRE -1616 1008 -1616 320
WIRE -1424 1008 -1424 704
WIRE -1424 1008 -1616 1008
WIRE -1120 1008 -1424 1008
WIRE -992 1008 -992 608
WIRE -992 1008 -1120 1008
WIRE -944 1008 -944 720
WIRE -944 1008 -992 1008
WIRE -1120 1104 -1120 1008
SYMBOL sw -944 640 M180
SYMATTR InstName S2
SYMBOL voltage -1424 608 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 10 1n 1n 5 10 1)
SYMATTR InstName V3
SYMBOL voltage -1616 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 14.8
SYMBOL load2 -944 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I2
SYMATTR Value 3
SYMBOL res -960 256 R0
SYMATTR InstName R3
SYMATTR Value 10k
FLAG -1120 1104 0
TEXT -1624 64 Left 2 !.model SW SW(Ron=1p Roff=100G Vt=0.5 Vh=0)
TEXT -1728 1096 Left 2 !.tran 36
* Z:\home\khalils\Downloads\files\data\raw_asc\0204bdbae06f_TEC_block1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 I_TEC N001 2
C1 TEC 0 1 IC={Ambient}
R3 TEC A {Tcool}
V2 N001 I_Ret 0
B1 A 0 V=((80.2e-6*I(R1)*I(R1)-127*I(R1))+V(Ambient))*V(V1V)
B2 Vmon 0 V=(0.583-2.391e-3*V(TEC)-3.861e-7*V(TEC)*V(TEC)+1.842e-9*V(TEC)*V(TEC)*V(TEC))*V(V1V)
B3 Ambient 0 V=({Ambient})*V(V1V)
.Param Tcool=130 Twarm=130 Ambient=10 initial_temp=10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 1016
WIRE -960 464 -960 400
WIRE -960 688 -960 544
WIRE -864 752 -960 752
WIRE -720 32 -896 32
WIRE -720 80 -720 32
WIRE -720 208 -720 160
WIRE -720 336 -896 336
WIRE -720 336 -720 288
WIRE -720 400 -960 400
WIRE -672 816 -672 736
WIRE -672 992 -672 896
WIRE -624 736 -672 736
WIRE -528 192 -528 112
WIRE -528 352 -528 272
WIRE -528 368 -528 352
WIRE -480 112 -528 112
WIRE -144 112 -480 112
WIRE 64 112 -64 112
WIRE 96 112 64 112
WIRE 96 192 96 112
WIRE 96 352 -528 352
WIRE 96 352 96 256
WIRE 240 112 96 112
FLAG -528 368 0
FLAG 64 112 TEC
FLAG -960 688 0
FLAG -720 400 Vmon
IOPIN -720 400 Out
FLAG 240 112 TEC
IOPIN 240 112 Out
FLAG -896 32 I_TEC
IOPIN -896 32 BiDir
FLAG -896 336 I_Ret
IOPIN -896 336 BiDir
FLAG -480 112 A
FLAG -960 752 V1V
IOPIN -960 752 BiDir
FLAG -672 992 0
FLAG -624 736 Ambient
SYMBOL res -736 64 R0
SYMATTR InstName R1
SYMATTR Value 2
SYMBOL cap 80 192 R0
WINDOW 123 24 92 Left 0
SYMATTR Value2 IC={Ambient}
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res -48 96 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value {Tcool}
SYMBOL voltage -720 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL bv -528 176 R0
WINDOW 3 54 198 Left 0
SYMATTR Value V=((80.2e-6*I(R1)*I(R1)-127*I(R1))+V(Ambient))*V(V1V)
SYMATTR InstName B1
SYMBOL bv -960 448 R0
WINDOW 3 19 174 Left 0
SYMATTR Value V=(0.583-2.391e-3*V(TEC)-3.861e-7*V(TEC)*V(TEC)+1.842e-9*V(TEC)*V(TEC)*V(TEC))*V(V1V)
SYMATTR InstName B2
SYMBOL bv -672 800 R0
WINDOW 3 54 198 Left 0
SYMATTR Value V=({Ambient})*V(V1V)
SYMATTR InstName B3
TEXT -312 448 Left 0 !.Param Tcool=130 Twarm=130 Ambient=10 initial_temp=10
* Z:\home\khalils\Downloads\files\data\raw_asc\112b125786ee_Controlled_Cap_non_phys.asc
* Generated by LTspice 26.0.1 for Windows.
* Non Charge-preserving (non physical) Voltage Controlled Capacitors
* C=Cref*V(ctrl)
* C=Lref*V(ctrl)
* (usable e.g. for simulation of a depot of shares. C=price/share charge=$$)
G1 0 x1 c2 0 1
Bc2 c2 0 I=V(x1)*V(ctrl)
Rdummy c2 0 1G
Bc1 c1 0 I=V(ctrl)*I(Vs)-I(Vs)
I2 0 c2 PULSE(0 1 10n 10n 10n 999)
Lref x1 0 1 Rser=0
Vs P001 0 0
I1 0 c1 PULSE(0 1 10n 10n 10n 999)
Cref c1 P001 1
Vctrl ctrl 0 PULSE(1 2 1 10n 10n)
.tran 2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 -176 -128 -176
WIRE 432 -176 -32 -176
WIRE 560 -176 432 -176
WIRE -32 -144 -32 -176
WIRE 432 -96 432 -176
WIRE -32 -32 -32 -64
WIRE -368 0 -432 0
WIRE -432 32 -432 0
WIRE -160 96 -256 96
WIRE 96 96 -160 96
WIRE 432 96 96 96
WIRE 560 96 432 96
WIRE -32 144 -112 144
WIRE -256 176 -256 96
WIRE -112 176 -112 144
WIRE -32 176 -32 144
WIRE 96 176 96 96
WIRE 432 176 432 96
WIRE -160 192 -160 96
RECTANGLE Normal 208 0 -208 -192
RECTANGLE Normal 224 320 -288 48
SYMBOL res -272 160 R0
WINDOW 0 -8 131 Left 0
SYMATTR InstName Rdummy
SYMATTR Value 1G
SYMBOL current 432 -16 R180
WINDOW 0 24 88 Left 0
WINDOW 3 -135 -37 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(0 1 10n 10n 10n 999)
SYMBOL cap -144 -176 R0
WINDOW 3 23 53 Left 0
WINDOW 0 35 20 Left 0
SYMATTR Value 1
SYMATTR InstName Cref
SYMBOL bi 96 176 R0
WINDOW 3 -58 125 Left 0
SYMATTR InstName Bc2
SYMATTR Value I=V(x1)*V(ctrl)
SYMBOL ind -48 160 R0
WINDOW 39 39 95 Left 0
WINDOW 3 41 66 Left 0
SYMATTR SpiceLine Rser=0
SYMATTR InstName Lref
SYMATTR Value 1
SYMBOL g -112 160 R0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL voltage -432 16 R0
WINDOW 0 29 36 Left 0
WINDOW 3 -99 135 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vctrl
SYMATTR Value PULSE(1 2 1 10n 10n)
SYMBOL bi -32 -144 R0
WINDOW 3 13 86 Left 0
SYMATTR Value I=V(ctrl)*I(Vs)-I(Vs)
SYMATTR InstName Bc1
SYMBOL current 432 256 R180
WINDOW 0 24 88 Left 0
WINDOW 3 -141 -37 Left 0
SYMATTR InstName I2
SYMATTR Value PULSE(0 1 10n 10n 10n 999)
SYMBOL voltage -128 -128 R0
WINDOW 0 -52 17 Left 0
WINDOW 3 -53 52 Left 0
SYMATTR InstName Vs
SYMATTR Value 0
FLAG -112 256 0
FLAG -32 256 0
FLAG 96 256 0
FLAG -160 240 0
FLAG -32 144 x1
FLAG 560 96 c2
FLAG -432 112 0
FLAG -368 0 ctrl
FLAG 432 256 0
FLAG -256 256 0
FLAG -32 -32 0
FLAG -128 -32 0
FLAG 560 -176 c1
FLAG 432 -16 0
TEXT -412 -264 Left 0 !.tran 2
TEXT -248 -272 Left 0 ;Non Charge-preserving (non physical) Voltage Controlled Capacitors
TEXT 32 -112 Left 0 ;C=Cref*V(ctrl)
TEXT -96 72 Left 0 ;C=Lref*V(ctrl)
TEXT -256 -232 Left 0 ;(usable e.g. for simulation of a depot of shares. C=price/share charge=$$)
* Z:\home\khalils\Downloads\files\data\raw_asc\0d3aedf51621_HBrdige.asc
* Generated by LTspice 26.0.1 for Windows.
* Motor +
* Motor -
L1 N004 P001 2.2mH
M3 N005 N003 N001 N001 RRR040P03
M4 N004 N002 N001 N001 RRR040P03
V3 N003 0 PULSE(0 3.3 0.05 1ns 1ns 10ms 0.1 10)
M2 N005 N002 0 0 RTR040N03
V2 N002 0 PULSE(0 3.3 0 1ns 1ns 10ms 0.1 10)
M1 N004 N003 0 0 RTR040N03
V1 N001 0 9
R1 P001 N005 2.1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1s
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1220 680
WIRE 512 -64 112 -64
WIRE 512 0 512 -64
WIRE 512 0 416 0
WIRE 608 0 512 0
WIRE 416 64 416 0
WIRE 608 64 608 0
WIRE 224 80 176 80
WIRE 368 80 336 80
WIRE 784 80 656 80
WIRE 112 96 112 -64
WIRE 224 112 224 80
WIRE 1152 112 912 112
WIRE 1152 144 1152 112
WIRE 608 160 608 144
WIRE 416 192 416 160
WIRE 432 192 416 192
WIRE 608 192 608 160
WIRE 608 192 592 192
WIRE 224 224 224 192
WIRE 416 240 416 192
WIRE 608 240 608 192
WIRE 368 320 352 320
WIRE 688 320 656 320
WIRE 176 368 176 80
WIRE 352 368 352 320
WIRE 352 368 176 368
WIRE 784 368 784 80
WIRE 784 368 352 368
WIRE 416 416 416 336
WIRE 512 416 416 416
WIRE 608 416 608 336
WIRE 608 416 512 416
WIRE 512 448 512 416
WIRE 336 480 336 80
WIRE 688 480 688 320
WIRE 688 480 336 480
WIRE 912 480 912 112
WIRE 912 480 688 480
SYMBOL voltage 112 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL nmos 368 240 R0
WINDOW 3 3 109 Left 2
SYMATTR InstName M2
SYMATTR Value RTR040N03
SYMBOL ind 608 176 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 2.2mH
SYMBOL pmos 656 160 R180
WINDOW 3 -26 108 Left 2
SYMATTR InstName M4
SYMATTR Value RRR040P03
SYMBOL voltage 1152 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -391 341 Left 2
SYMATTR Value PULSE(0 3.3 0.05 1ns 1ns 10ms 0.1 10)
SYMATTR InstName V3
SYMBOL voltage 224 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -391 341 Left 2
SYMATTR Value PULSE(0 3.3 0 1ns 1ns 10ms 0.1 10)
SYMATTR InstName V2
SYMBOL res 528 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2.1
SYMBOL pmos 368 160 M180
WINDOW 3 -18 128 Left 2
SYMATTR InstName M3
SYMATTR Value RRR040P03
SYMBOL nmos 656 240 M0
SYMATTR InstName M1
SYMATTR Value RTR040N03
FLAG 112 176 0
FLAG 512 448 0
FLAG 224 224 0
FLAG 1152 224 0
TEXT 72 504 Left 2 !.tran 1s
TEXT 320 192 Left 2 ;Motor +
TEXT 608 192 Left 2 ;Motor -
* Z:\home\khalils\Downloads\files\data\raw_asc\8462ee253a6e_Simulation4.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
R1 N001 N002 2.6k
M2 N001 N002 N006 N004 NMOS
M3 N009 N005 N005 N007 NMOS
V2 N009 NC_02 -15
M1 N005 N002 N002 N003 NMOS
M4 N006 N005 N009 N008 NMOS
V1 NC_01 N001 15
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc v1 0 8 0.5
.model M1 NMOS(l=100u, w=100u, kp=20, Vto=1v)
.model M2 NMOS(l=100u, w=100u, kp=20, Vto=1v)
.model M3 NMOS(l=100u, w=100u, kp=20, Vto=1v)
.model M4 NMOS(l=100u, w=100u, kp=20, Vto=1v)
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1104 736
WIRE 208 80 16 80
WIRE 432 80 208 80
WIRE 16 144 16 80
WIRE 16 240 16 224
WIRE 160 240 16 240
WIRE 16 304 16 240
WIRE 432 304 432 80
WIRE 432 304 416 304
WIRE 160 320 160 240
WIRE 160 320 64 320
WIRE 208 320 160 320
WIRE 16 384 16 352
WIRE 208 384 208 320
WIRE 368 384 208 384
WIRE 416 384 416 352
WIRE 16 432 16 400
WIRE 192 432 16 432
WIRE 16 464 16 432
WIRE 192 480 192 432
WIRE 192 480 64 480
WIRE 416 496 416 400
WIRE 16 544 16 512
WIRE 192 576 192 480
WIRE 368 576 192 576
WIRE 416 576 416 544
WIRE 16 608 16 560
WIRE 192 608 16 608
WIRE 416 608 416 592
WIRE 416 608 192 608
WIRE 192 640 192 608
SYMBOL nmos4 368 304 R0
SYMATTR InstName M2
SYMBOL voltage 192 624 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL nmos4 64 560 R180
SYMATTR InstName M3
SYMBOL res 0 128 R0
SYMATTR InstName R1
SYMATTR Value 2.6k
SYMBOL nmos4 368 496 R0
SYMATTR InstName M4
SYMBOL nmos4 64 400 R180
SYMATTR InstName M1
SYMBOL voltage 208 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
TEXT -80 672 Left 2 ;.op
TEXT 272 40 Left 2 !.dc v1 0 8 0.5
TEXT -616 352 Left 2 !.model M1 NMOS(l=100u, w=100u, kp=20, Vto=1v)
TEXT 480 352 Left 2 !.model M2 NMOS(l=100u, w=100u, kp=20, Vto=1v)
TEXT -632 520 Left 2 !.model M3 NMOS(l=100u, w=100u, kp=20, Vto=1v)
TEXT 496 536 Left 2 !.model M4 NMOS(l=100u, w=100u, kp=20, Vto=1v)
* Z:\home\khalils\Downloads\files\data\raw_asc\093f8e5acce6_sweep_squarewave.asc
* Generated by LTspice 26.0.1 for Windows.
* freq = V(vc)*10kHz
* LInear sweep from 10kHz to 30kHz.
A1 sc 0 0 0 0 sr N001 0 SCHMITT Vt=0.5 vh=0.5
B1 vc 0 V=1*(1+time*100)
R1 N001 rc 1k
C1 sc 0 50n
E1 out 0 rc 0 20
C2 rc 0 0.1n
B2 0 sc I=IF(V(sr)>0.5, V(vc)*1m, -V(vc)*1m)
.tran 20m
.ic V(sc)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1064 680
WIRE 288 16 288 0
WIRE 0 96 -48 96
WIRE 208 96 0 96
WIRE 960 96 800 96
WIRE 0 128 0 96
WIRE 288 144 288 96
WIRE 800 144 800 96
WIRE 544 160 448 160
WIRE 656 160 624 160
WIRE 704 160 656 160
WIRE 752 160 704 160
WIRE 288 176 288 144
WIRE 384 176 288 176
WIRE 480 192 448 192
WIRE 656 192 656 160
WIRE 288 208 288 176
WIRE 0 224 0 208
WIRE 656 272 656 256
WIRE 752 272 752 208
WIRE 800 272 800 224
WIRE 288 304 288 272
IOPIN -48 96 In
IOPIN 960 96 Out
RECTANGLE Normal 912 352 128 -48
SYMBOL res 528 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 272 208 R0
SYMATTR InstName C1
SYMATTR Value 50n
SYMBOL bi 288 16 R0
SYMATTR InstName B2
SYMATTR Value I=IF(V(sr)>0.5, V(vc)*1m, -V(vc)*1m)
SYMBOL Digital\\schmitt 384 112 R0
SYMATTR InstName A1
SYMATTR SpiceLine Vt=0.5 vh=0.5
SYMBOL e 800 128 R0
SYMATTR InstName E1
SYMATTR Value 20
SYMBOL bv 0 112 R0
WINDOW 3 -78 153 Left 2
SYMATTR InstName B1
SYMATTR Value V=1*(1+time*100)
SYMBOL cap 640 192 R0
SYMATTR InstName C2
SYMATTR Value 0.1n
FLAG 0 224 0
FLAG -48 96 vc
FLAG 288 304 0
FLAG 288 0 0
FLAG 480 192 sr
FLAG 288 144 sc
FLAG 656 272 0
FLAG 752 272 0
FLAG 800 272 0
FLAG 960 96 out
FLAG 704 160 rc
TEXT -90 -120 Left 2 !.tran 20m
TEXT 160 200 Left 2 !.ic V(sc)=0
TEXT 392 -8 Left 2 ;freq = V(vc)*10kHz
TEXT -88 -96 Left 2 ;LInear sweep from 10kHz to 30kHz.
* Z:\home\khalils\Downloads\files\data\raw_asc\4d2948d2b4a0_Fig9_24_pmos.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Is(M1) and 1/d(Is(M1)) (to get ro)
VSG 0 N001 1.15
VSD 0 N002 0
M1 N002 N001 0 0 P_1u l=2u w=30u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSD 0 5
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1224 688
WIRE 448 0 320 0
WIRE 672 0 448 0
WIRE 848 0 672 0
WIRE 320 32 320 0
WIRE 848 32 848 0
WIRE 448 112 448 0
WIRE 320 128 320 112
WIRE 400 128 320 128
WIRE 672 160 672 0
WIRE 672 160 448 160
WIRE 672 192 672 160
WIRE 448 304 448 208
WIRE 672 304 672 272
WIRE 672 304 448 304
SYMBOL pmos4 400 208 M180
WINDOW 123 56 100 Left 2
SYMATTR Value2 l=2u w=30u
SYMATTR InstName M1
SYMATTR Value P_1u
SYMBOL voltage 672 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 0 38 54 Left 2
WINDOW 3 24 104 Invisible 2
SYMATTR InstName VSD
SYMATTR Value 0
SYMBOL voltage 320 16 R0
WINDOW 0 -93 54 Left 2
WINDOW 3 -93 82 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VSG
SYMATTR Value 1.15
FLAG 848 32 0
TEXT 384 336 Left 2 !.dc VSD 0 5
TEXT 384 360 Left 2 !.include cmosedu_models.txt
TEXT 368 -32 Left 2 ;Plot Is(M1) and 1/d(Is(M1)) (to get ro)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADA4930-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4930-1.asy)
RG3 OUTn N001 301
RG2 N004 N005 301
RG4 OUTp N004 301
Vref N005 0 0.9
Vin N002 N005 SINE(0 10m 1Meg)
XU1 N001 N004 NC_01 NC_02 VS 0 N003 OUTp OUTn VS ADA4930-1 ;pnba 1)2)3)4)5)6)7)8)9)10
Vcc VS 0 5
Vocm N003 0 0.9
R1 OUTn OUTp 200
RG1 N001 N002 301
.tran 2u
.lib ADA4930-1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1052 904
WIRE 128 -96 -160 -96
WIRE 240 -96 208 -96
WIRE -16 -16 -32 -16
WIRE 80 -16 64 -16
WIRE -272 64 -384 64
WIRE -160 64 -160 -96
WIRE -160 64 -192 64
WIRE -32 64 -32 -16
WIRE 80 80 0 80
WIRE 176 80 160 80
WIRE -32 96 -32 64
WIRE 0 96 0 80
WIRE -384 112 -384 64
WIRE -160 144 -160 64
WIRE -64 144 -160 144
WIRE 240 160 240 -96
WIRE 240 160 96 160
WIRE 304 160 240 160
WIRE 384 160 304 160
WIRE 384 192 384 160
WIRE -64 208 -160 208
WIRE 240 224 96 224
WIRE -384 272 -384 192
WIRE -272 272 -384 272
WIRE -160 272 -160 208
WIRE -160 272 -192 272
WIRE 64 288 0 288
WIRE -384 304 -384 272
WIRE -32 304 -32 288
WIRE 240 304 240 224
WIRE 304 304 240 304
WIRE 384 304 384 272
WIRE 384 304 304 304
WIRE -384 400 -384 384
WIRE -160 416 -160 272
WIRE 128 416 -160 416
WIRE 240 416 240 304
WIRE 240 416 208 416
SYMBOL voltage -32 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcc
SYMATTR Value 5
SYMBOL res 224 400 R90
WINDOW 0 -4 53 VBottom 2
WINDOW 3 35 56 VTop 2
SYMATTR InstName RG4
SYMATTR Value 301
SYMBOL voltage -384 288 R0
WINDOW 0 86 39 Right 2
WINDOW 3 43 68 Left 2
WINDOW 123 -124 -14 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vref
SYMATTR Value 0.9
SYMBOL res 224 -112 R90
WINDOW 0 -1 53 VBottom 2
WINDOW 3 38 55 VTop 2
SYMATTR InstName RG3
SYMATTR Value 301
SYMBOL voltage -384 96 R0
WINDOW 0 75 36 Right 2
WINDOW 3 43 69 Left 2
WINDOW 123 -124 -14 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value SINE(0 10m 1Meg)
SYMBOL res -176 48 R90
WINDOW 0 -3 55 VBottom 2
WINDOW 3 36 55 VTop 2
SYMATTR InstName RG1
SYMATTR Value 301
SYMBOL res -176 256 R90
WINDOW 0 -2 58 VBottom 2
WINDOW 3 41 57 VTop 2
SYMATTR InstName RG2
SYMATTR Value 301
SYMBOL voltage 64 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vocm
SYMATTR Value 0.9
SYMBOL res 368 176 R0
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL ADA4930-1 -32 192 R0
SYMATTR InstName U1
FLAG 80 -16 0
FLAG 176 80 0
FLAG 304 160 OUTn
FLAG 304 304 OUTp
FLAG -32 64 VS
FLAG -384 400 0
FLAG 64 288 VS
FLAG -32 304 0
TEXT -418 468 Left 2 !.tran 2u
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX44281U.asc
* Generated by LTspice 26.0.1 for Windows.
Vcc Vcc 0 3.3
RL OUT 0 10k
V1 IN 0 SINE(165m 50m 10k)
CL OUT 0 1p
XU1 IN Vcc 0 OUT MAX44281U ;pnba IN)VDD)GND)OUT
.tran 100u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX44281U.asy)
.lib MAX44281U.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 448 192 416 192
WIRE 544 192 528 192
WIRE 544 208 544 192
WIRE 416 240 416 192
WIRE 416 272 416 240
WIRE 384 304 304 304
WIRE 576 304 448 304
WIRE 672 304 576 304
WIRE 576 336 576 304
WIRE 416 352 416 336
WIRE 672 352 672 304
WIRE 304 416 304 304
WIRE 576 448 576 416
WIRE 672 448 672 416
WIRE 304 512 304 496
FLAG 672 304 OUT
FLAG 416 240 Vcc
FLAG 544 208 0
FLAG 304 512 0
FLAG 576 448 0
FLAG 304 304 IN
FLAG 672 448 0
FLAG 416 352 0
SYMBOL voltage 432 192 R270
WINDOW 123 0 0 Left 2
WINDOW 0 47 35 VRight 2
WINDOW 3 -45 40 VRight 2
SYMATTR InstName Vcc
SYMATTR Value 3.3
SYMBOL res 560 320 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 304 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 31 94 Left 2
SYMATTR Value SINE(165m 50m 10k)
SYMATTR InstName V1
SYMBOL cap 656 352 R0
SYMATTR InstName CL
SYMATTR Value 1p
SYMBOL MAX44281U 416 240 R0
SYMATTR InstName U1
TEXT 288 560 Left 2 !.tran 100u
* Z:\tmp\asc_dec_bjh7r6w2\09cd3158f73b_algunos_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R6 N011 N014 {1/6}
I2 0 N001 AC 1 0
C8 N007 N006 {1/10}
R10 N008 N012 1
R8 N007 N006 10
L3 N001 N002 {25/18}
R9 N008 N007 2
C5 N004 N003 {5/4}
V3 N009 N013 AC 1 0
R5 N011 N010 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2516 836
WIRE 2208 -32 2176 -32
WIRE 2352 -32 2288 -32
WIRE 2096 32 1936 32
WIRE 2176 32 2176 -32
WIRE 2176 32 2096 32
WIRE 2352 32 2352 -32
WIRE 2432 32 2352 32
WIRE 1152 64 1088 64
WIRE 1296 64 1232 64
WIRE 1936 80 1936 32
WIRE 2176 80 2176 32
WIRE 2224 80 2176 80
WIRE 2352 80 2352 32
WIRE 2352 80 2288 80
WIRE 2096 96 2096 32
WIRE 1024 112 960 112
WIRE 1088 112 1088 64
WIRE 1088 112 1024 112
WIRE 1296 112 1296 64
WIRE 1376 112 1296 112
WIRE 1088 144 1088 112
WIRE 1152 144 1088 144
WIRE 1296 144 1296 112
WIRE 1296 144 1216 144
WIRE 1024 160 1024 112
WIRE 1376 160 1376 112
WIRE 1936 224 1936 160
WIRE 2096 224 2096 160
WIRE 2096 224 1936 224
WIRE 2432 224 2096 224
WIRE 2096 240 2096 224
WIRE 1024 304 1024 224
WIRE 1024 304 736 304
WIRE 1376 304 1376 240
WIRE 1376 304 1024 304
WIRE 1024 336 1024 304
WIRE 1520 480 1472 480
WIRE 1664 480 1600 480
WIRE 1792 480 1744 480
WIRE 1936 480 1872 480
WIRE 336 496 272 496
WIRE 480 496 416 496
WIRE 272 544 272 496
WIRE 272 544 160 544
WIRE 480 544 480 496
WIRE 512 544 480 544
WIRE 672 544 592 544
WIRE 784 544 672 544
WIRE 1472 544 1472 480
WIRE 1472 544 1376 544
WIRE 1664 544 1664 480
WIRE 1744 544 1744 480
WIRE 1744 544 1664 544
WIRE 1936 544 1936 480
WIRE 2128 544 1936 544
WIRE 272 576 272 544
WIRE 336 576 272 576
WIRE 480 576 480 544
WIRE 480 576 400 576
WIRE 672 592 672 544
WIRE 784 592 784 544
WIRE 1472 608 1472 544
WIRE 1520 608 1472 608
WIRE 1664 608 1664 544
WIRE 1664 608 1584 608
WIRE 1744 608 1744 544
WIRE 1792 608 1744 608
WIRE 1936 608 1936 544
WIRE 1936 608 1856 608
WIRE 2128 608 2128 544
WIRE 160 624 160 544
WIRE 1664 768 1376 768
WIRE 2128 768 2128 688
WIRE 2128 768 1664 768
WIRE 160 784 160 704
WIRE 464 784 160 784
WIRE 672 784 672 672
WIRE 784 784 784 656
WIRE 1664 800 1664 768
SYMBOL res 656 576 R0
SYMATTR InstName R6
SYMATTR Value {1/6}
SYMBOL current 1936 160 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I2
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL cap 1584 592 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C8
SYMATTR Value {1/10}
SYMBOL res 2112 592 R0
SYMATTR InstName R10
SYMATTR Value 1
SYMBOL res 1616 464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 10
SYMBOL ind 2192 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value {25/18}
SYMBOL res 1888 464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 2
SYMBOL cap 1216 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value {5/4}
SYMBOL voltage 160 608 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL res 608 528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1
FLAG 2096 240 0