Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\56a2d4e2fe0b_Draft81.asc
* Generated by LTspice 26.0.1 for Windows.
* Note current spike 1A, for 6ns.
* fdn360p/fdn337n switch time about 1us/3.6A
* DMP/ switch time about 30ns/ 200mA.
* CMOS - compare fets. for cross-conduction
XM3 N004 N002 P002 FDN360P VTEMP=30 ;pnba D)G)S
XM2 N003 N001 P001 DMP31D7L ;pnba D)G)S
R2 VCC P001 0.01R
V2 VCC 0 5
XM4 N004 N002 0 FDN337N ;pnba D)G)S
XM1 N003 N001 0 DMN63D8L ;pnba D)G)S
V1 SW1 0 PULSE(0 5 1us 10ns 10ns 25us 50us 20)
R6 N001 SW1 200R
R1 VCC P002 0.01R
R3 N003 0 50R
R4 N004 0 50R
R5 N002 SW1 200R
.tran 1.2ms
.include my.lib
.param temperature=25
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4244 1268
WIRE 896 -304 848 -304
WIRE 1536 -304 1504 -304
WIRE 512 -224 224 -224
WIRE 1216 -224 944 -224
WIRE 1760 -224 1584 -224
WIRE 848 -144 848 -304
WIRE 896 -144 848 -144
WIRE 1504 -144 1504 -304
WIRE 1536 -144 1504 -144
SYMBOL res 1520 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 200R
SYMBOL nmos 896 -224 R0
SYMATTR InstName M1
SYMATTR Value DMN63D8L
SYMATTR Prefix X
SYMBOL voltage 224 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value PULSE(0 5 1us 10ns 10ns 25us 50us 20)
SYMATTR InstName V1
SYMBOL res 1744 -240 R0
SYMATTR InstName R4
SYMATTR Value 50R
SYMBOL res 864 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 200R
SYMBOL res 1568 -416 R0
SYMATTR InstName R1
SYMATTR Value 0.01R
SYMBOL res 1200 -240 R0
SYMATTR InstName R3
SYMATTR Value 50R
SYMBOL pmos 1536 -224 M180
SYMATTR InstName M3
SYMATTR Value FDN360P
SYMATTR Prefix X
SYMATTR Value2 VTEMP=30
SYMBOL res 928 -416 R0
SYMATTR InstName R2
SYMATTR Value 0.01R
SYMBOL pmos 896 -224 M180
SYMATTR InstName M2
SYMATTR Value DMP31D7L
SYMATTR Prefix X
SYMBOL voltage 384 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 48 40 Left 2
SYMATTR Value 5
SYMATTR InstName V2
SYMBOL nmos 1536 -224 R0
SYMATTR InstName M4
SYMATTR Value FDN337N
SYMATTR Prefix X
FLAG 384 -16 0
FLAG 384 -96 VCC
FLAG 224 -144 0
FLAG 512 -224 SW1
FLAG 944 -400 VCC
FLAG 944 -128 0
FLAG 768 -144 SW1
FLAG 1216 -144 0
FLAG 1584 -400 VCC
FLAG 1424 -144 SW1
FLAG 1584 -128 0
FLAG 1760 -144 0
TEXT 392 -288 Left 2 !.tran 1.2ms
TEXT 512 -520 Left 2 !.include my.lib
TEXT 1024 -576 Left 2 ;Note current spike 1A, for 6ns.
TEXT 432 -456 Left 2 !.param temperature=25
TEXT 1888 -368 Left 2 ;fdn360p/fdn337n switch time about 1us/3.6A
TEXT 744 -8 Left 2 ;DMP/  switch time about 30ns/ 200mA.
TEXT 1168 -720 Left 2 ;CMOS - compare fets. for cross-conduction
* Z:\home\khalils\Downloads\files\data\raw_asc\1e98a8532546_tut2ques20b.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
V2 0 P002 10
V1 P001 0 10
R1 N001 Vi 5k
Vi Vi 0 PULSE({A} {-A} 0 0.5m 0.5m 0 0 100)
R2 V0 N001 15k
XU1 0 N001 P001 P002 V0 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=1 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.tran 0 4ms
.step param A list 1 2 3 4 5
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -80 -32 -176 -32
WIRE -64 -32 -80 -32
WIRE 128 -32 16 -32
WIRE 192 -32 128 -32
WIRE 336 -32 272 -32
WIRE 128 160 128 -32
WIRE 160 160 128 160
WIRE 336 176 336 -32
WIRE 336 176 224 176
WIRE 160 192 128 192
WIRE 128 224 128 192
SYMBOL voltage 192 304 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL res 32 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5k
SYMBOL voltage 192 160 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL OpAmps\\UniversalOpAmp2 192 176 R0
SYMATTR InstName U1
SYMATTR SpiceLine Ilimit=25m Rail=1 Vos=0
SYMBOL voltage -176 -48 R0
WINDOW 3 -152 162 Left 2
SYMATTR Value PULSE({A} {-A} 0 0.5m 0.5m 0 0 100)
SYMATTR InstName Vi
SYMBOL res 288 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 15k
FLAG 128 224 0
FLAG 336 176 V0
FLAG 192 64 0
FLAG 192 288 0
FLAG -176 48 0
FLAG -80 -32 Vi
TEXT -224 224 Left 2 !.tran 0 4ms
TEXT -232 264 Left 2 !.step param A list 1 2 3 4 5
* Z:\home\khalils\Downloads\files\data\raw_asc\3752e431c38c_npn_curve.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 N002 0 0 2N3904
I1 0 N002 {Ib}
V1 N001 0
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.step param Ib 2u 500u 50u
.dc V1 0 10 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 64 240 64
WIRE 416 64 368 64
WIRE 416 96 416 64
WIRE 240 112 240 64
WIRE 64 160 32 160
WIRE 176 160 144 160
WIRE 32 192 32 160
WIRE 240 240 240 208
FLAG 32 192 0
FLAG 416 96 0
FLAG 240 240 0
SYMBOL npn 176 112 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL current 64 160 R270
WINDOW 0 32 40 VTop 2
WINDOW 3 -32 40 VBottom 2
SYMATTR InstName I1
SYMATTR Value {Ib}
SYMBOL voltage 272 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
TEXT -48 24 Left 2 !.step param Ib 2u 500u 50u
TEXT -48 56 Left 2 !.dc V1 0 10 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2109-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2109-1.2.asy)
XU1 IN IN N001 OUT 0 ADP2109-x.x Rtop=112K ;pnba Vin)EN)SW)FB)GND
C1 OUT 0 10 V=4 Irms=8.88 Rser=0.00522854 Lser=0 mfg="KEMET" pn="C0805C106K7PAC" type="X5R"
Rload OUT 0 4
V1 IN 0 5
L1 N001 OUT 1
.tran .5m startup
.lib ADP2109-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 144
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine V=4 Irms=8.88 Rser=0.00522854 Lser=0 mfg="KEMET" pn="C0805C106K7PAC" type="X5R"
SYMBOL ADP2109-1.2 352 224 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 4
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 552 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\05fe12980cab_Switch_Option_1.asc
* Generated by LTspice 26.0.1 for Windows.
* Simulation
* Spice Directives
* Switch Model & Control
V2 Vsw 0 PULSE(0 1 0 1u 1u 0.8 3)
C1 Vo 0 20m
R1 N002 N001 3
R2 N003 0 9
R3 Vo N003 1
V1 N001 0 20
S1 N003 N002 Vsw 0 MYSW
.tran 0 3 0 100u
.model MYSW SW(Ron=0.1 Roff=1000Meg Vt=.5 Vh=.4)
.ic V(Vo)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1532 760
WIRE 224 192 224 176
WIRE 272 192 272 160
WIRE 80 240 16 240
WIRE 208 240 160 240
WIRE 352 240 288 240
WIRE 400 240 352 240
WIRE 528 240 480 240
WIRE 16 304 16 240
WIRE 352 304 352 240
WIRE 528 304 528 240
WIRE 688 384 688 368
WIRE 16 432 16 384
WIRE 352 432 352 384
WIRE 352 432 16 432
WIRE 528 432 528 368
WIRE 528 432 352 432
WIRE 16 480 16 432
WIRE 688 496 688 464
RECTANGLE Normal 1024 240 640 160 2
RECTANGLE Normal 880 112 640 64 2
RECTANGLE Normal 1328 576 640 304 2
SYMBOL res 496 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1
SYMBOL voltage 16 288 R0
SYMATTR InstName V1
SYMATTR Value 20
SYMBOL sw 304 240 R90
WINDOW 0 -46 11 Left 2
WINDOW 3 53 17 VRight 2
SYMATTR InstName S1
SYMATTR Value MYSW
SYMBOL res 176 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 3
SYMBOL cap 512 304 R0
SYMATTR InstName C1
SYMATTR Value 20m
SYMBOL res 336 288 R0
SYMATTR InstName R2
SYMATTR Value 9
SYMBOL voltage 688 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 1u 1u 0.8 3)
FLAG 16 480 0
FLAG 272 160 0
FLAG 224 176 Vsw
FLAG 688 368 Vsw
FLAG 688 496 0
FLAG 528 240 Vo
TEXT 640 48 Left 2 ;Simulation
TEXT 648 88 Left 2 !.tran 0 3 0 100u
TEXT 640 144 Left 2 ;Spice Directives
TEXT 664 536 Left 2 !.model MYSW SW(Ron=0.1 Roff=1000Meg Vt=.5 Vh=.4)
TEXT 648 184 Left 2 !.ic V(Vo)=0
TEXT 640 288 Left 2 ;Switch Model & Control
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2120-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 OUT 2.2
C1 OUT 0 22
R1 OUT N001 100K
V1 IN 0 5
Rload OUT 0 1.5
C2 OUT 0 10
XU1 IN IN N002 0 0 OUT IN N001 IN IN ADP2120-1.5 ;pnba Vin)Pvin)SW)PGND)GND)FB)TRK)Pgood)Sync/Mode)EN
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2120-1.5.asy)
.lib ADP2120-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 0 32 0
WIRE 288 0 128 0
WIRE 32 16 32 0
WIRE 288 16 288 0
WIRE 128 64 128 0
WIRE 160 64 128 64
WIRE 496 64 416 64
WIRE 688 64 576 64
WIRE 32 112 32 96
WIRE 128 144 128 64
WIRE 160 144 128 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 624 144 560 144
WIRE 688 144 688 64
WIRE 688 144 624 144
WIRE 752 144 688 144
WIRE 560 160 560 144
WIRE 624 160 624 144
WIRE 752 160 752 144
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 560 224 416 224
WIRE 624 224 560 224
WIRE 560 256 560 224
WIRE 752 256 752 240
WIRE 128 304 128 224
WIRE 160 304 128 304
WIRE 688 304 688 144
WIRE 688 304 416 304
WIRE 288 368 288 352
FLAG 560 256 0
FLAG 288 368 0
FLAG 32 112 0
FLAG 752 144 OUT
FLAG 752 256 0
FLAG 32 0 IN
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL cap 544 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL voltage 32 0 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 736 144 R0
SYMATTR Value 1.5
SYMATTR InstName Rload
SYMBOL cap 608 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL ADP2120-1.5 288 272 R0
SYMATTR InstName U1
TEXT 504 344 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\Wien.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1001.asy)
C1 N004 N003 .01
XU1 N003 N002 +V -V OUT LT1001 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
R4 0 N003 10K
R3 OUT N004 10K
R1 OUT N002 10K
R2 N002 N001 4.9K
D1 AGC OUT 1N4148
JQ1 N001 AGC 0 U309
V2 -V 0 -15
C2 N003 0 .01
C3 0 AGC .1
R5 AGC 0 1Meg
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.tran 0 .5 0 10u startup
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 1108
WIRE -112 128 -144 128
WIRE 0 128 -16 128
WIRE 112 128 80 128
WIRE 176 128 112 128
WIRE 304 128 256 128
WIRE 112 224 112 128
WIRE 128 224 112 224
WIRE 304 240 304 128
WIRE 304 240 192 240
WIRE 336 240 304 240
WIRE 32 256 -48 256
WIRE 112 256 32 256
WIRE 128 256 112 256
WIRE -48 272 -48 256
WIRE 32 272 32 256
WIRE -288 320 -288 304
WIRE -176 320 -176 304
WIRE -48 368 -48 336
WIRE 32 368 32 352
WIRE 112 368 112 256
WIRE 128 368 112 368
WIRE 208 368 192 368
WIRE 304 368 304 240
WIRE 304 368 288 368
WIRE -288 416 -288 400
WIRE -176 416 -176 400
WIRE -80 464 -80 176
WIRE 32 464 -80 464
WIRE 176 464 32 464
WIRE 304 464 304 368
WIRE 304 464 240 464
WIRE -80 480 -80 464
WIRE 32 496 32 464
WIRE -80 576 -80 560
WIRE 32 576 32 560
SYMBOL diode 176 448 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL njf -16 176 M270
WINDOW 0 49 47 VTop 2
WINDOW 3 -7 52 VLeft 2
SYMATTR InstName Q1
SYMATTR Value U309
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 4.9K
SYMBOL res -96 464 R0
SYMATTR InstName R5
SYMATTR Value 1Meg
SYMBOL res 304 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res 272 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL cap -64 272 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL cap 16 560 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value .1
SYMBOL cap 192 352 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .01
SYMBOL voltage -176 304 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -288 304 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 16 368 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL opamps\\LT1001 160 176 R0
SYMATTR InstName U1
FLAG 160 208 +V
FLAG 160 272 -V
FLAG -288 304 +V
FLAG -176 416 0
FLAG -288 416 0
FLAG -176 304 -V
FLAG 32 368 0
FLAG -48 368 0
FLAG -144 128 0
FLAG 32 576 0
FLAG -80 576 0
FLAG 336 240 OUT
FLAG 32 464 AGC
TEXT 168 560 Left 2 !.tran 0 .5 0 10u startup
TEXT 56 616 Top 1 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1116.asc
* Generated by LTspice 26.0.1 for Windows.
* Single Supply Crystal Oscillator 10MHz to 15MHz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT1116.asy)
XU1 +V N003 N001 0 0 0 N002 OUT LT1116 ;pnba V+)In+)In-)V-)LATCH)GND)OUT+)OUT-
R2 +V N003 1K
R3 N003 0 1K
C1 N001 0 24p
V1 +V 0 5
CY1 N002 N003 .32p Rser=45 Lser=.78m Cpar=18p
R1 N002 N001 2K
.tran 50u startup
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -240 80 -256 80
WIRE -160 80 -176 80
WIRE -112 80 -160 80
WIRE 32 80 -32 80
WIRE -304 160 -304 144
WIRE -432 192 -432 176
WIRE -96 192 -96 160
WIRE -160 224 -160 80
WIRE -128 224 -160 224
WIRE 32 224 32 80
WIRE 32 224 -48 224
WIRE -304 256 -304 240
WIRE -192 256 -304 256
WIRE -128 256 -192 256
WIRE 64 256 -48 256
WIRE -304 272 -304 256
WIRE -432 288 -432 272
WIRE -112 304 -112 288
WIRE -96 304 -96 288
WIRE -96 304 -112 304
WIRE -80 304 -80 288
WIRE -80 304 -96 304
WIRE -96 320 -96 304
WIRE -192 352 -192 256
WIRE -64 352 -192 352
WIRE 32 352 32 224
WIRE 32 352 0 352
WIRE -304 368 -304 352
SYMBOL misc\\xtal 0 336 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 Invisible 2
SYMATTR InstName Y1
SYMATTR Value .32p
SYMATTR SpiceLine Rser=45 Lser=.78m Cpar=18p
SYMBOL res -320 256 R0
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL res -320 144 R0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap -176 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 24p
SYMBOL res -16 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2K
SYMBOL Comparators\\LT1116 -96 176 R0
SYMATTR InstName U1
SYMBOL voltage -432 176 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -432 288 0
FLAG -432 176 +V
FLAG -96 160 +V
FLAG -96 320 0
FLAG -256 80 0
FLAG -304 368 0
FLAG -304 144 +V
FLAG 64 256 OUT
TEXT 64 376 Left 2 !.tran 50u startup
TEXT -120 24 Bottom 2 ;Single Supply Crystal Oscillator 10MHz to 15MHz
* Z:\home\khalils\Downloads\files\data\raw_asc\07fdeeea09fe_Half_Bridge.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 13
R2 out_A N005 {Ron}
C1 N004 0 65n
R3 N003 N004 10
V2 N003 0 PULSE(0 13 1u 1n 1n 10u 20u)
R1 N002 out_A {Ron}
S1 N001 N002 N004 N002 SW1
S2 N005 0 N005 N004 SW1
.param Ron=24m Roff=1MEG
.model sw1 sw(Ron=1n {Roff} Vt=0 Vh=-0.1m)
.tran 50u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -368 160 -368 144
WIRE -288 144 -368 144
WIRE -176 144 -208 144
WIRE -176 176 -176 144
WIRE -96 144 -176 144
WIRE -96 464 -96 144
WIRE -48 192 -48 96
WIRE -48 512 -48 432
WIRE -16 96 -48 96
WIRE -16 144 -96 144
WIRE -16 464 -96 464
WIRE -16 512 -48 512
WIRE 32 80 32 32
WIRE 32 192 -48 192
WIRE 32 192 32 160
WIRE 32 208 32 192
WIRE 32 304 32 288
WIRE 32 336 32 304
WIRE 32 432 -48 432
WIRE 32 432 32 416
WIRE 32 448 32 432
WIRE 336 32 32 32
WIRE 336 64 336 32
WIRE 416 304 32 304
SYMBOL cap -192 176 R0
SYMATTR InstName C1
SYMATTR Value 65n
SYMBOL res -304 160 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 10
SYMBOL voltage -368 144 R0
WINDOW 3 -81 147 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 13 1u 1n 1n 10u 20u)
SYMATTR InstName V2
SYMBOL res 16 192 R0
SYMATTR InstName R1
SYMATTR Value {Ron}
SYMBOL res 16 320 R0
SYMATTR InstName R2
SYMATTR Value {Ron}
SYMBOL sw 32 64 R0
SYMATTR InstName S1
SYMATTR Value SW1
SYMBOL voltage 336 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 13
SYMBOL sw 32 432 R0
SYMATTR InstName S2
SYMATTR Value SW1
FLAG 336 144 0
FLAG 32 528 0
FLAG 416 304 out_A
FLAG -176 240 0
FLAG -368 240 0
TEXT -368 48 Left 0 !.param Ron=24m Roff=1MEG
TEXT -216 8 Left 0 !.model sw1 sw(Ron=1n {Roff} Vt=0 Vh=-0.1m)
TEXT -450 556 Left 0 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\4c9f7df0b0fe_Fig1_17.asc
* Generated by LTspice 26.0.1 for Windows.
D1 Vd 0 mydiode
Vin Vin 0 1
R1 Vin Vd 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc Vin 0 1
.model mydiode D
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 48 224 0 224
WIRE 112 224 48 224
WIRE 256 224 192 224
WIRE 288 224 256 224
WIRE 0 240 0 224
WIRE 288 240 288 224
WIRE 0 336 0 320
WIRE 288 336 288 304
SYMBOL diode 272 240 R0
SYMATTR InstName D1
SYMATTR Value mydiode
SYMBOL voltage 0 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value 1
SYMBOL res 96 240 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 0 336 0
FLAG 288 336 0
FLAG 256 224 Vd
FLAG 48 224 Vin
TEXT 40 400 Left 0 !.dc Vin 0 1
TEXT 40 376 Left 0 !.model mydiode D
* Z:\home\khalils\Downloads\files\data\raw_asc\19cadbe77e1d_currect_regulator.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 10
R1 N002 0 100
J1 N001 N002 N002 2N4119
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.dc V1 0 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 48 32 48
WIRE 208 80 208 48
WIRE 160 144 144 144
WIRE 32 160 32 48
WIRE 144 192 144 144
WIRE 208 192 208 176
WIRE 208 192 144 192
WIRE 208 208 208 192
WIRE 32 304 32 240
WIRE 208 304 208 288
WIRE 208 304 32 304
WIRE 208 320 208 304
SYMBOL voltage 32 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL njf 160 80 R0
SYMATTR InstName J1
SYMATTR Value 2N4119
SYMBOL Misc\\EuropeanResistor 192 192 R0
SYMATTR InstName R1
SYMATTR Value 100
FLAG 208 320 0
TEXT 280 48 Left 2 !.dc V1 0 10
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4626.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4626.asy)
C3 OUT 0 100
R5 0 N005 90.9K
R6 OUT 0 0.085
R4 OUT N003 100K
XU2 NC_01 NC_02 0 N005 N004 N006 N002 N003 N006 0 NC_03 OUT OUT 0 0 MP_04 IN MP_05 MP_06 MP_07 N001 MP_08 NC_09 N001 LTM4626 ;pnba Freq)PhMode)Vosns-)FB)Track/SS)COMPa)Run)Pgood)COMPb)PGND)SW)Vout)Vosns+)Tsense+)Tsense-))Vin))))INTVcc))CLKout)Mode/CLKin
C1 N004 0 2n
R2 IN N002 150K
C2 0 N001 2.2
V1 IN 0 12
R3 N002 0 100K
.tran 1m startup
.lib LTM4626.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 708
WIRE 0 -256 0 -272
WIRE 0 -176 0 -192
WIRE 160 -176 0 -176
WIRE 0 -160 0 -176
WIRE 160 -160 160 -176
WIRE -304 -96 -400 -96
WIRE -96 -96 -304 -96
WIRE 688 -96 576 -96
WIRE 768 -96 688 -96
WIRE 880 -96 768 -96
WIRE -400 -80 -400 -96
WIRE 768 -80 768 -96
WIRE 880 -80 880 -96
WIRE -304 -32 -304 -96
WIRE 768 0 768 -16
WIRE 768 0 720 0
WIRE -400 16 -400 0
WIRE 768 16 768 0
WIRE 880 16 880 0
WIRE -304 96 -304 48
WIRE -96 96 -304 96
WIRE 592 96 576 96
WIRE 688 96 688 -96
WIRE 688 96 672 96
WIRE -304 112 -304 96
WIRE -176 192 -192 192
WIRE -96 192 -112 192
WIRE 688 192 688 96
WIRE 688 192 576 192
WIRE -304 208 -304 192
WIRE 624 288 576 288
WIRE 720 288 720 0
WIRE 720 288 704 288
WIRE -96 384 -112 384
WIRE 720 384 720 288
WIRE 720 384 576 384
WIRE -112 480 -112 384
WIRE -96 480 -112 480
WIRE 592 480 576 480
WIRE 240 560 240 544
WIRE 432 560 432 544
SYMBOL cap -16 -256 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL res -320 96 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL LTM4626 240 192 R0
SYMATTR InstName U2
SYMBOL res 688 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL res 720 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 90.9K
SYMBOL cap -112 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL cap 752 -80 R0
SYMATTR InstName C3
SYMATTR Value 100
SYMBOL res 864 -96 R0
SYMATTR InstName R6
SYMATTR Value 0.085
SYMBOL res -320 -48 R0
SYMATTR InstName R2
SYMATTR Value 150K
SYMBOL voltage -400 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 240 560 0
FLAG 432 560 0
FLAG 592 480 0
FLAG -400 16 0
FLAG -304 208 0
FLAG -192 192 0
FLAG 0 -272 0
FLAG 768 16 0
FLAG 880 16 0
FLAG -400 -96 IN
FLAG 880 -96 OUT
TEXT 680 512 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-4.2.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-4.2.asy)
V1 IN 0 3.3
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-4.2 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
Rload OUT 0 50
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
.tran 400u startup
.lib ADP2503-4.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2503-4.2 176 176 R0
SYMATTR InstName U1
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 432 392 Left 2 !.tran 400u startup
TEXT 192 8 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled