* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5054.asc
* Generated by LTspice 26.0.1 for Windows.
R1 IN N002 10K
R2 N002 0 10K
C1 N001 N003 0.1
C2 OUT 0 16
L1 N003 OUT 2.2
R4 OUT N009 34.8K
R5 N009 0 23.2K
R6 N010 0 22K
C3 N007 0 1
R7 N011 0 31.6K
C4 N005 N004 2.2n
R3 N004 0 1.82K
R8 N007 N008 10K
C5 OUT N009 47p
M1 N003 N006 0 0 BSC080N03MS
Rload OUT 0 2
XU1 N011 N007 N007 N002 IN N001 N003 N006 N009 N005 N008 0 N010 0 ADP5054_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)Rlim)CFG12
V2 IN 0 12
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m startup
* CFG configuration pin is correct for Channel 1\nwhen NOT paralleled with Channel 2
* Rlim is the resistor generally placed on DL pin to set current limit
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5054_chan1_2.asy)
.lib ADP5054_chan1_2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 1240
WIRE -192 -96 -288 -96
WIRE 80 -96 -192 -96
WIRE 448 -96 368 -96
WIRE -288 -80 -288 -96
WIRE -192 -80 -192 -96
WIRE 448 -80 448 -96
WIRE -288 16 -288 0
WIRE -192 16 -192 0
WIRE 80 16 -192 16
WIRE 448 16 448 -16
WIRE 448 16 368 16
WIRE 512 16 448 16
WIRE 640 16 592 16
WIRE 720 16 640 16
WIRE 848 16 720 16
WIRE 976 16 848 16
WIRE -192 32 -192 16
WIRE 848 32 848 16
WIRE 976 32 976 16
WIRE 448 48 448 16
WIRE 720 48 720 16
WIRE 640 112 640 16
WIRE 848 112 848 96
WIRE -192 128 -192 112
WIRE -96 128 -112 128
WIRE 0 128 -16 128
WIRE 80 128 64 128
WIRE 400 128 368 128
WIRE 976 128 976 112
WIRE 448 160 448 144
WIRE -32 240 -64 240
WIRE 80 240 48 240
WIRE 640 240 640 176
WIRE 640 240 368 240
WIRE 720 240 720 128
WIRE 720 240 640 240
WIRE 720 256 720 240
WIRE -64 352 -64 240
WIRE 80 352 -64 352
WIRE 384 352 368 352
WIRE 480 352 464 352
WIRE 720 352 720 336
WIRE 480 416 368 416
WIRE -16 464 -32 464
WIRE 80 464 64 464
WIRE 400 464 368 464
WIRE 448 464 400 464
WIRE 448 480 448 464
WIRE 224 512 224 496
WIRE -64 544 -64 352
WIRE 400 544 400 464
WIRE 400 544 -64 544
WIRE 448 560 448 544
FLAG 224 512 0
FLAG -288 16 0
FLAG -192 128 0
FLAG 448 160 0
FLAG 848 112 0
FLAG 720 352 0
FLAG 480 352 0
FLAG 448 560 0
FLAG -32 464 0
FLAG -112 128 0
FLAG 976 16 OUT
FLAG -288 -96 IN
FLAG 976 128 0
FLAG 480 416 0
SYMBOL res -208 -96 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res -208 16 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL cap 432 -80 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL cap 832 32 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C2
SYMATTR Value 16
SYMBOL ind 496 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res 704 32 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL res 704 240 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL res 368 368 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 22K
SYMBOL cap 432 480 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 80 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL cap 64 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL res 0 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL res -48 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL cap 624 112 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL nmos 400 48 R0
SYMATTR InstName M1
SYMATTR Value BSC080N03MS
SYMBOL res 960 16 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL ADP5054_chan1_2 224 192 R0
SYMATTR InstName U1
SYMBOL VOLTAGE -288 -96 R0
SYMATTR InstName V2
SYMATTR Value 12
TEXT 648 512 Left 2 !.tran 3m startup
TEXT 512 448 Left 2 ;CFG configuration pin is correct for Channel 1\nwhen NOT paralleled with Channel 2
TEXT 512 384 Left 2 ;Rlim is the resistor generally placed on DL pin to set current limit