* Z:\home\khalils\Downloads\files\data\raw_asc\21c7134f63f9_Nth_Root.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 0 N010 NC_01 NC_02 N011 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R1 N010 N012 1K
Vref N012 0 1V
Q1 N010 0 N011 0 NPN
XU2 0 N005 NC_03 NC_04 N006 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N005 Input 1K
Vin Input 0 5V
Q2 N005 0 N006 0 NPN
XU3 N009 N007 NC_05 NC_06 LogOut level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R3 N009 0 1K
R4 N009 N011 1K
R5 N007 N006 1K
R6 LogOut N007 1K
XU5 0 N008 NC_07 NC_08 Antilog_Input level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R8 Antilog_Input N008 1K
R9 N008 LogOut 2K
V1 N004 0 1V
R7 N003 N004 1K
XU4 0 N003 NC_09 NC_10 N002 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Q3 N003 Antilog_Input N002 0 NPN
XU6 0 N001 NC_11 NC_12 Final level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Q4 N001 0 N002 0 NPN
R10 N001 Final 1K
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10ms
* Change resistance
* based on required root
* Library below included based on ModelFile attribute of instance XU1, XU2, XU3, XU5, XU4, XU6 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp1.asy)
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1908 680
WIRE 1808 -1088 1312 -1088
WIRE 1536 -1008 1472 -1008
WIRE 1712 -1008 1632 -1008
WIRE 1584 -944 1584 -960
WIRE 1584 -896 1584 -944
WIRE 1312 -816 1312 -1088
WIRE 1344 -816 1312 -816
WIRE 1472 -816 1472 -1008
WIRE 1472 -816 1424 -816
WIRE 1552 -816 1472 -816
WIRE 1808 -800 1808 -1088
WIRE 1808 -800 1616 -800
WIRE 1904 -800 1808 -800
WIRE 1552 -784 1488 -784
WIRE 1808 -736 1808 -800
WIRE 1488 -704 1488 -784
WIRE 1520 -560 1456 -560
WIRE 1712 -560 1712 -1008
WIRE 1712 -560 1616 -560
WIRE 1568 -496 1568 -512
WIRE 1568 -416 1568 -496
WIRE 1664 -416 1568 -416
WIRE 1312 -368 1264 -368
WIRE 1456 -368 1456 -560
WIRE 1456 -368 1392 -368
WIRE 1536 -368 1456 -368
WIRE 1712 -352 1712 -560
WIRE 1712 -352 1600 -352
WIRE 1536 -336 1472 -336
WIRE 96 -320 64 -320
WIRE 240 -320 192 -320
WIRE 1264 -320 1264 -368
WIRE 1472 -256 1472 -336
WIRE 144 -240 144 -256
WIRE 480 -240 432 -240
WIRE 608 -240 560 -240
WIRE 1024 -208 1008 -208
WIRE 1152 -208 1104 -208
WIRE -112 -192 -208 -192
WIRE -64 -192 -112 -192
WIRE 64 -192 64 -320
WIRE 64 -192 16 -192
WIRE 112 -192 64 -192
WIRE 240 -176 240 -320
WIRE 240 -176 176 -176
WIRE 304 -176 240 -176
WIRE 432 -176 432 -240
WIRE 432 -176 384 -176
WIRE -112 -160 -112 -192
WIRE 112 -160 96 -160
WIRE 432 -128 432 -176
WIRE 480 -128 432 -128
WIRE 608 -112 608 -240
WIRE 608 -112 544 -112
WIRE 624 -112 608 -112
WIRE 912 -112 624 -112
WIRE 1008 -112 1008 -208
WIRE 1008 -112 992 -112
WIRE 1024 -112 1008 -112
WIRE 96 -96 96 -160
WIRE 480 -96 432 -96
WIRE 1152 -96 1152 -208
WIRE 1152 -96 1088 -96
WIRE 1360 -96 1152 -96
WIRE 1664 -96 1664 -416
WIRE 1664 -96 1360 -96
WIRE 1024 -80 976 -80
WIRE -112 -48 -112 -80
WIRE 624 -48 624 -112
WIRE 80 -16 48 -16
WIRE 224 -16 176 -16
WIRE 304 -16 224 -16
WIRE 432 -16 432 -96
WIRE 432 -16 384 -16
WIRE 1360 -16 1360 -96
WIRE 432 0 432 -16
WIRE 976 0 976 -80
WIRE 128 64 128 48
WIRE -64 112 -112 112
WIRE 48 112 48 -16
WIRE 48 112 16 112
WIRE 96 112 48 112
WIRE 432 112 432 80
WIRE 224 128 224 -16
WIRE 224 128 160 128
WIRE -112 144 -112 112
WIRE 96 144 80 144
WIRE 80 208 80 144
WIRE -112 256 -112 224
FLAG -112 256 0
FLAG 80 208 0
FLAG 128 64 0
FLAG -112 -48 0
FLAG 96 -96 0
FLAG 144 -240 0
FLAG 432 112 0
FLAG -208 -192 Input
FLAG 624 -48 LogOut
FLAG 976 0 0
FLAG 1264 -240 0
FLAG 1472 -256 0
FLAG 1488 -704 0
FLAG 1584 -896 0
FLAG 1808 -736 Final
FLAG 1360 -16 Antilog_Input
SYMBOL OpAmps\\UniversalOpAmp1 128 128 R0
SYMATTR InstName U1
SYMBOL res 32 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -112 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vref
SYMATTR Value 1V
SYMBOL npn 80 48 R270
SYMATTR InstName Q1
SYMBOL OpAmps\\UniversalOpAmp1 144 -176 R0
SYMATTR InstName U2
SYMBOL res 32 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -112 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value 5V
SYMBOL npn 96 -256 R270
SYMATTR InstName Q2
SYMBOL OpAmps\\UniversalOpAmp1 512 -112 R0
SYMATTR InstName U3
SYMBOL res 416 -16 R0
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL res 400 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL res 400 -192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1K
SYMBOL res 576 -256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 1K
SYMBOL OpAmps\\UniversalOpAmp1 1056 -96 R0
SYMATTR InstName U5
SYMBOL res 1120 -224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 1K
SYMBOL res 1008 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 2K
SYMBOL voltage 1264 -336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1V
SYMBOL res 1408 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 1K
SYMBOL OpAmps\\UniversalOpAmp1 1568 -352 R0
SYMATTR InstName U4
SYMBOL npn 1520 -496 R270
SYMATTR InstName Q3
SYMBOL OpAmps\\UniversalOpAmp1 1584 -800 R0
SYMATTR InstName U6
SYMBOL npn 1536 -944 R270
SYMATTR InstName Q4
SYMBOL res 1440 -832 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 1K
TEXT -288 280 Left 2 !.tran 10ms
TEXT 736 -208 Left 2 ;Change resistance
TEXT 728 -176 Left 2 ;based on required root