* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5054_chan3_4.asc
* Generated by LTspice 26.0.1 for Windows.
* The schematic simulates channels 3 and 4 in parallel.\nNotice how the CFG, COMP, and FB pins are configured\nThis is different than the real world. Channels are synced\nto out of phase clocks in order to simulate their phase relationship.
* Library below included based on ModelFile attribute of instance XU2, XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5054_chan3_4.asy)
A1 N011 0 0 0 0 N012 N007 0 SCHMITT Vt=0.5 vh=8m Vhigh=5 Vlow=0
R1 IN N002 10K
C2 N013 N014 100n
R3 N004 0 1.82K
R2 N002 0 10K
Cout1 OUT 0 8.12
R7 N009 0 31.6K
R15 N015 N016 10K
C5 OUT N006 47p
Cout OUT 0 8.12
V2 N011 0 PULSE(0 5 0 10n 10n 833n 1.666u)
R13 N018 0 31.6K
R5 N006 0 23.2K
C3 N010 0 1
Rload OUT 0 1
R10 N017 0 300k
XU1 N018 N012 N016 N002 IN N013 N014 N017 N006 N005 N015 0 ADP5054_chan3_4 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)CFG34)FB)Comp)PWRGD)PGND
L2 N014 OUT 3.3 Rser=100m
R4 OUT N006 34.8K
V1 IN 0 12
R9 N016 N017 400k
C6 N016 0 1
C4 N005 N004 2.2n
L1 N003 OUT 3.3 Rser=100m
R8 N008 N010 10K
XU2 N009 N007 N010 N002 IN N001 N003 0 N006 N005 N008 0 ADP5054_chan3_4 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)CFG34)FB)Comp)PWRGD)PGND
C1 N001 N003 100n
.tran 2.5m startup
.lib ADP5054_chan3_4.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2052 1204
WIRE -304 -48 -416 -48
WIRE -240 -48 -304 -48
WIRE 80 -48 -240 -48
WIRE 416 -48 368 -48
WIRE -416 -32 -416 -48
WIRE -240 -32 -240 -48
WIRE 416 -32 416 -48
WIRE -240 64 -240 48
WIRE -144 64 -240 64
WIRE 80 64 -144 64
WIRE 416 64 416 32
WIRE 416 64 368 64
WIRE 464 64 416 64
WIRE 640 64 544 64
WIRE 720 64 640 64
WIRE 848 64 720 64
WIRE 928 64 848 64
WIRE 976 64 928 64
WIRE -416 80 -416 48
WIRE -240 80 -240 64
WIRE 640 80 640 64
WIRE 720 80 720 64
WIRE 848 80 848 64
WIRE 976 80 976 64
WIRE -240 176 -240 160
WIRE -96 176 -112 176
WIRE 0 176 -16 176
WIRE 80 176 64 176
WIRE 640 176 640 144
WIRE 640 176 368 176
WIRE 720 176 720 160
WIRE 720 176 640 176
WIRE 848 176 848 144
WIRE 976 176 976 160
WIRE 720 192 720 176
WIRE 64 240 64 176
WIRE 64 240 -32 240
WIRE 80 288 -464 288
WIRE 448 288 368 288
WIRE 720 288 720 272
WIRE 448 304 448 288
WIRE 80 352 64 352
WIRE -464 400 -464 288
WIRE -464 400 -512 400
WIRE 80 400 16 400
WIRE 448 400 448 384
WIRE 448 400 368 400
WIRE -752 416 -800 416
WIRE -576 416 -672 416
WIRE 16 416 16 400
WIRE 448 416 448 400
WIRE -464 432 -512 432
WIRE 224 448 224 432
WIRE -576 480 -576 448
WIRE 448 496 448 480
WIRE 16 512 16 496
WIRE -304 624 -304 -48
WIRE 80 624 -304 624
WIRE 416 624 368 624
WIRE 416 640 416 624
WIRE -144 736 -144 64
WIRE 80 736 -144 736
WIRE 416 736 416 704
WIRE 416 736 368 736
WIRE 464 736 416 736
WIRE 848 736 544 736
WIRE 928 736 928 64
WIRE 928 736 848 736
WIRE 848 752 848 736
WIRE -32 848 -32 240
WIRE 80 848 -32 848
WIRE 640 848 640 176
WIRE 640 848 368 848
WIRE 848 848 848 816
WIRE -464 960 -464 432
WIRE 80 960 -464 960
WIRE 448 960 368 960
WIRE 448 976 448 960
WIRE -416 1024 -464 1024
WIRE -320 1024 -336 1024
WIRE 80 1024 -320 1024
WIRE -320 1040 -320 1024
WIRE -48 1072 -64 1072
WIRE 80 1072 32 1072
WIRE 384 1072 368 1072
WIRE 448 1072 448 1056
WIRE 448 1072 384 1072
WIRE 448 1088 448 1072
WIRE 224 1120 224 1104
WIRE -320 1136 -320 1120
WIRE 448 1168 448 1152
WIRE -464 1200 -464 1024
WIRE 384 1200 384 1072
WIRE 384 1200 -464 1200
SYMBOL res 960 64 R0
SYMATTR InstName Rload
SYMATTR Value 1
SYMBOL ADP5054_chan3_4 224 176 R0
SYMATTR InstName U2
SYMBOL cap 64 160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL cap 400 640 R0
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL res 432 960 R0
SYMATTR InstName R15
SYMATTR Value 10K
SYMBOL res 0 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL cap 624 80 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL cap 832 752 R0
SYMATTR InstName Cout1
SYMATTR Value 8.12
SYMBOL ind 448 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -23 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 3.3
SYMATTR SpiceLine Rser=100m
SYMBOL cap 432 1088 R0
SYMATTR InstName C6
SYMATTR Value 1
SYMBOL res -256 -48 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL ind 448 752 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -23 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 3.3
SYMATTR SpiceLine Rser=100m
SYMBOL res -256 64 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 432 288 R0
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL res 704 176 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL Digital\\schmitt -576 352 R0
WINDOW 0 20 23 Left 2
WINDOW 123 26 118 Left 2
WINDOW 39 26 146 Left 2
SYMATTR InstName A1
SYMATTR Value2 Vt=0.5 vh=8m
SYMATTR SpiceLine Vhigh=5 Vlow=0
SYMATTR Description Behavioral Schmitt-Triggered inverter
SYMATTR Type schmtinv
SYMBOL cap 400 -32 R0
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL voltage -656 416 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 33 131 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10n 10n 833n 1.666u)
SYMBOL res 0 400 R0
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL res -336 1024 R0
SYMATTR InstName R10
SYMATTR Value 300k
SYMBOL ADP5054_chan3_4 224 848 R0
SYMATTR InstName U1
SYMBOL res -432 1040 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R9
SYMATTR Value 400k
SYMBOL res 48 1056 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R13
SYMATTR Value 31.6K
SYMBOL VOLTAGE -416 -48 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 704 64 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL cap 832 80 R0
SYMATTR InstName Cout
SYMATTR Value 8.12
SYMBOL cap 432 416 R0
SYMATTR InstName C3
SYMATTR Value 1
FLAG 224 448 0
FLAG -240 176 0
FLAG 848 176 0
FLAG 720 288 0
FLAG 448 496 0
FLAG 16 512 0
FLAG -112 176 0
FLAG 976 176 0
FLAG 976 64 OUT
FLAG -416 80 0
FLAG -416 -48 IN
FLAG 64 352 0
FLAG 224 1120 0
FLAG 848 848 0
FLAG 448 1168 0
FLAG -64 1072 0
FLAG -320 1136 0
FLAG -576 480 0
FLAG -800 416 0
TEXT 656 1144 Left 2 !.tran 2.5m startup
TEXT -1040 152 Left 2 ;The schematic simulates channels 3 and 4 in parallel.\nNotice how the CFG, COMP, and FB pins are configured\nThis is different than the real world.  Channels are synced\nto out of phase clocks in order to simulate their phase relationship.