Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\379cf5e30080_CR_OpAmp_Oscillator.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
R1 N002 N003 10k
R4 output N003 10k
R3 output N001 75k
C1 N001 0 1500p
XU2 N003 N001 N002 0 output LT1001 ;pnba In+)In-)V+)V-)OUT
R2 N003 0 10k
V1 N002 0 5
.tran 0 3 0 0.00001
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -96 80 -96
WIRE 352 -96 224 -96
WIRE -64 -32 -368 -32
WIRE 208 -32 -64 -32
WIRE -64 32 -64 -32
WIRE -368 48 -368 -32
WIRE 208 80 208 -32
WIRE 80 96 80 -96
WIRE 176 96 80 96
WIRE 352 112 352 -96
WIRE 352 112 240 112
WIRE 512 112 352 112
WIRE -64 128 -64 112
WIRE 144 128 -64 128
WIRE 176 128 144 128
WIRE -64 176 -64 128
WIRE 80 176 80 96
WIRE 208 176 208 144
WIRE -368 192 -368 128
WIRE 144 256 144 128
WIRE 256 256 144 256
WIRE 352 256 352 112
WIRE 352 256 336 256
WIRE -64 288 -64 256
WIRE 80 288 80 240
SYMBOL OpAmps\\OP07 208 48 R0
SYMATTR InstName U2
SYMBOL cap 64 176 R0
SYMATTR InstName C1
SYMATTR Value 1500p
SYMBOL res 240 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 75k
SYMBOL res -80 160 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res -80 16 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -368 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 352 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
FLAG -368 192 0
FLAG 208 176 0
FLAG 80 288 0
FLAG -64 288 0
FLAG 512 112 output
TEXT -400 312 Left 2 !.tran 0 3 0 0.00001
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-3.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10
Rload OUT 0 500
C2 OUT N001 .01
XU1 IN 0 IN N001 OUT LT1761-3 ;pnba IN)GND)_SHDN)BYP)OUT
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-3.asy)
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 48 -224 48
WIRE 16 48 -16 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE -16 144 -16 48
WIRE 16 144 -16 144
WIRE 336 144 336 128
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG -224 48 IN
FLAG 512 48 OUT
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL cap 320 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL PowerProducts\\LT1761-3 160 96 R0
SYMATTR InstName U1
TEXT 328 240 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\logamp.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 IN 1K
XU1 N001 0 N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
XU2 N003 N004 OUT opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
C1 N002 N001 30p
D1 N002 N001 1N4148
Q1 N001 0 N002 0 2N3904
Q2 N004 N004 N002 0 2N3904
I1 0 N004 100
R2 N003 0 1K
R3 OUT N003 15K
B1 IN 0 V=exp(time-7)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10
.include opamp.sub
.options maxstep=2m
* Log amp
* This example schematic is supplied for informational/educational purposes only.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5945676 13421556
WIRE 1472 -304 1440 -304
WIRE 1568 -304 1536 -304
WIRE 1440 -192 1440 -304
WIRE 1472 -192 1440 -192
WIRE 1568 -192 1568 -304
WIRE 1568 -192 1536 -192
WIRE 1440 -112 1440 -192
WIRE 1456 -112 1440 -112
WIRE 1568 -112 1568 -192
WIRE 1568 -112 1552 -112
WIRE 1712 -48 1696 -48
WIRE 1808 -48 1792 -48
WIRE 1840 -48 1808 -48
WIRE 1936 -48 1920 -48
WIRE 1808 48 1808 -48
WIRE 1824 48 1808 48
WIRE 1328 64 1216 64
WIRE 1440 64 1440 -112
WIRE 1440 64 1408 64
WIRE 1472 64 1440 64
WIRE 1936 64 1936 -48
WIRE 1936 64 1888 64
WIRE 1952 64 1936 64
WIRE 1216 80 1216 64
WIRE 1568 80 1568 -112
WIRE 1568 80 1536 80
WIRE 1600 80 1568 80
WIRE 1712 80 1696 80
WIRE 1760 80 1712 80
WIRE 1824 80 1760 80
WIRE 1472 96 1456 96
WIRE 1760 128 1760 80
WIRE 1712 144 1712 80
WIRE 1712 144 1648 144
WIRE 1216 176 1216 160
WIRE 1760 240 1760 208
FLAG 1216 176 0
FLAG 1504 -48 0
FLAG 1456 96 0
FLAG 1760 240 0
FLAG 1696 -48 0
FLAG 1952 64 OUT
FLAG 1216 64 IN
SYMBOL RES 1424 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL OPAMPS\\OPAMP 1504 16 R0
SYMATTR InstName U1
SYMBOL OPAMPS\\OPAMP 1856 0 R0
SYMATTR InstName U2
SYMBOL cap 1536 -320 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 30p
SYMBOL diode 1536 -208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL NPN 1456 -48 R270
WINDOW 0 52 48 VCenter 2
WINDOW 3 -34 49 VCenter 2
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL npn 1696 144 M270
WINDOW 0 62 46 VCenter 2
WINDOW 3 -22 49 VCenter 2
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL CURRENT 1760 208 M180
WINDOW 0 24 88 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName I1
SYMATTR Value 100
SYMBOL res 1808 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 1936 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 15K
SYMBOL BV 1216 64 R0
SYMATTR InstName B1
SYMATTR Value V=exp(time-7)
TEXT 1872 136 Left 2 !.tran 10
TEXT 1416 256 Left 2 !.include opamp.sub
TEXT 1408 224 Left 2 !.options maxstep=2m
TEXT 1656 -256 Left 2 ;Log amp
TEXT 1552 280 Top 1 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\076e083f7095_Q4.asc
* Generated by LTspice 26.0.1 for Windows.
Vgs N002 0 {Vgs}
Vds N001 0 1.8
M1 N001 N002 0 0 nch_tt l=10u w=15u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
.dc Vds 0 1.8 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 624 -64 352 -64
WIRE 352 16 352 -64
WIRE 624 32 624 -64
WIRE 304 96 96 96
WIRE 96 144 96 96
WIRE 96 352 96 224
WIRE 352 352 352 112
WIRE 352 352 96 352
WIRE 624 352 624 112
WIRE 624 352 352 352
WIRE 352 384 352 352
SYMBOL voltage 624 16 R0
SYMATTR InstName Vds
SYMATTR Value 1.8
SYMBOL nmos 304 16 R0
SYMATTR InstName M1
SYMATTR Value nch_tt
SYMATTR Value2 l=10u w=15u
SYMBOL voltage 96 128 R0
SYMATTR InstName Vgs
SYMATTR Value {Vgs}
FLAG 352 384 0
TEXT -200 80 Left 2 !.include TSMC180.lib
TEXT -416 128 Left 2 !.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
TEXT -184 168 Left 2 !.dc Vds 0 1.8 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\0759cf5372ab_Nested.asc
* Generated by LTspice 26.0.1 for Windows.
I1 0 N001 AC 1
L1 N001 0 {L}
R1 N001 0 10K
C1 N001 0 {C}
.step param L 90u 200u .5u
.step param C 40p 60p 10p
.ac list 2Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 320 80 272
WIRE 80 208 80 144
WIRE 80 144 224 144
WIRE 224 144 224 192
WIRE 224 272 224 320
WIRE -32 320 -32 272
WIRE -32 192 -32 144
WIRE -32 144 80 144
WIRE 224 144 336 144
WIRE 336 144 336 192
WIRE 336 272 336 320
SYMBOL cap 64 208 R0
SYMATTR InstName C1
SYMATTR Value {C}
SYMBOL ind 208 176 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMBOL current -32 272 M180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName I1
SYMATTR Value AC 1
SYMBOL res 320 176 R0
SYMATTR InstName R1
SYMATTR Value 10K
FLAG 224 320 0
FLAG 80 320 0
FLAG -32 320 0
FLAG 336 320 0
TEXT 16 376 Left 0 !.step param L 90u 200u .5u\n.step param C 40p 60p 10p
TEXT 16 448 Left 0 !.ac list 2Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\c2f8261abecf_Draft14.asc
* Generated by LTspice 26.0.1 for Windows.
* 1e-16 * exp((V(vb) - V(ve)) / 26mV)
V3 N002 0 SINE(2 0 500)
R3 VB N002 1k
R1 VE 0 1k
R2 N001 VC 1k
Q1 VC VB VE 0 Test
V1 N001 0 15
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 1
.model Test NPN(is=1e-16)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 704 64 496 64
WIRE 496 144 496 64
WIRE 496 256 496 224
WIRE 496 272 496 256
WIRE 704 272 704 64
WIRE 304 320 256 320
WIRE 416 320 384 320
WIRE 432 320 416 320
WIRE 448 320 432 320
WIRE 256 368 256 320
WIRE 496 384 496 368
WIRE 496 400 496 384
WIRE 256 512 256 448
WIRE 496 512 496 480
WIRE 496 512 256 512
WIRE 704 512 704 352
WIRE 704 512 496 512
WIRE 704 560 704 512
SYMBOL res 400 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL voltage 704 256 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL npn 432 272 R0
SYMATTR InstName Q1
SYMATTR Value Test
SYMBOL voltage 256 352 R0
SYMATTR InstName V3
SYMATTR Value SINE(2 0 500)
SYMBOL res 480 384 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 480 128 R0
SYMATTR InstName R2
SYMATTR Value 1k
FLAG 704 560 0
FLAG 416 320 VB
FLAG 496 384 VE
FLAG 496 256 VC
TEXT -16 128 Left 2 !.tran 1\n.model Test NPN(is=1e-16)
TEXT 0 184 Left 2 ;1e-16 * exp((V(vb) - V(ve)) / 26mV)
* Z:\home\khalils\Downloads\files\data\raw_asc\24ea091a128a_1389-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1389-2.5.asy)
XU1 N002 0 LT1389-2.5 ;pnba VCC)VEE
R1 N001 N002 2.8Meg
V1 N001 0 PULSE(0 5 1.5m 10n 10n 4m 2)
.tran 10m
.lib LT1389-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3476 836
WIRE 720 -272 544 -272
WIRE 960 -272 800 -272
WIRE 544 -240 544 -272
WIRE 960 -224 960 -272
WIRE 544 -128 544 -160
WIRE 960 -128 960 -160
SYMBOL LT1389-2.5 960 -192 R0
SYMATTR InstName U1
SYMBOL res 704 -256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 2.8Meg
SYMBOL voltage 544 -256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1.5m 10n 10n 4m 2)
FLAG 960 -128 0
FLAG 544 -128 0
TEXT 1064 -88 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\03681de3b32d_limiter2.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 Vg 1m
V1 N001 0 10
R2 Vl 0 0.5
R3 Vl Vg R=1/-I(R3)
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -144 96 -208 96
WIRE 0 96 -64 96
WIRE 112 96 0 96
WIRE 464 96 192 96
WIRE 464 144 464 96
WIRE -208 160 -208 96
SYMBOL res -160 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1m
SYMBOL res 448 128 R0
SYMATTR InstName R2
SYMATTR Value 0.5
SYMBOL res 208 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 70 51 VTop 2
SYMATTR InstName R3
SYMATTR Value R=1/-I(R3)
SYMBOL voltage -208 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
FLAG -208 240 0
FLAG 464 224 0
FLAG 464 96 Vl
FLAG 0 96 Vg
TEXT -152 200 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\01146a30637d_m_Nand.asc
* Generated by LTspice 26.0.1 for Windows.
M4 N001 NAND_B VSS VSS BSB012N03LX3
M2 VDD NAND_B NAND_O NAND_O FDC5614P
M1 VDD NAND_A NAND_O NAND_O FDC5614P
M3 NAND_O NAND_A N001 N001 BSB012N03LX3
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 -336 192 -432
WIRE 192 -336 48 -336
WIRE 336 -336 192 -336
WIRE 48 -288 48 -336
WIRE 336 -288 336 -336
WIRE 0 -208 -48 -208
WIRE 288 -208 240 -208
WIRE 48 -112 48 -192
WIRE 192 -112 48 -112
WIRE 336 -112 336 -192
WIRE 336 -112 192 -112
WIRE 448 -112 336 -112
WIRE 192 -16 192 -112
WIRE 144 64 80 64
WIRE 192 144 192 80
WIRE 144 224 80 224
WIRE 192 368 192 240
IOPIN 192 -432 In
IOPIN 192 368 In
IOPIN -48 -208 In
IOPIN 448 -112 Out
IOPIN 240 -208 In
IOPIN 80 64 In
IOPIN 80 224 In
SYMBOL pmos 288 -288 R0
SYMATTR InstName M2
SYMATTR Value FDC5614P
SYMBOL nmos 144 144 R0
SYMATTR InstName M4
SYMATTR Value BSB012N03LX3
SYMBOL pmos 0 -288 R0
SYMATTR InstName M1
SYMATTR Value FDC5614P
SYMBOL nmos 144 -16 R0
SYMATTR InstName M3
SYMATTR Value BSB012N03LX3
FLAG 192 -432 VDD
FLAG 192 368 VSS
FLAG -48 -208 NAND_A
FLAG 448 -112 NAND_O
FLAG 240 -208 NAND_B
FLAG 80 64 NAND_A
FLAG 80 224 NAND_B
* Z:\home\khalils\Downloads\files\data\raw_asc\66618429e336_mos_cs_vgs.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .dc Vin 1.9 2.1 1m
VDD N001 0 10
RL VD 0 2k
RD N001 VD 2k
Vin VG 0 SINE(2.01 1m 30)
M1 VD VG 0 0 SQJ910AEP_Q2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 0.5 1m 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 288 -16 176 -16
WIRE 400 -16 368 -16
WIRE 176 16 176 -16
WIRE 400 16 400 -16
WIRE 176 128 176 96
WIRE 416 128 176 128
WIRE 176 144 176 128
WIRE 416 144 416 128
WIRE 112 208 32 208
WIRE 128 208 112 208
WIRE 32 240 32 208
WIRE 176 240 176 224
WIRE 416 240 416 224
WIRE 32 336 32 320
SYMBOL nmos 128 128 R0
SYMATTR InstName M1
SYMATTR Value SQJ910AEP_Q2
SYMBOL res 400 128 R0
SYMATTR InstName RL
SYMATTR Value 2k
SYMBOL voltage 272 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 10
SYMBOL res 160 0 R0
SYMATTR InstName RD
SYMATTR Value 2k
SYMBOL voltage 32 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 10 101 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(2.01 1m 30)
FLAG 176 240 0
FLAG 176 128 VD
FLAG 400 16 0
FLAG 32 336 0
FLAG 416 240 0
FLAG 112 208 VG
TEXT 224 280 Left 2 ;.op
TEXT 224 304 Left 2 ;.dc Vin 1.9 2.1 1m
TEXT 232 352 Left 2 !.tran 0 0.5 1m 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\23ed7a2935b1_Fig9_27_PMOS.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1) and d(Id(M1)) (to get gm)
VSG 0 N001 0
M1 0 N001 N002 0 P_50n l=100n w=1u
VSD 0 N002 100m
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VSG 0 1 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1224 688
WIRE 320 96 320 80
WIRE 320 192 320 176
WIRE 400 192 320 192
WIRE 448 80 320 80
WIRE 448 112 448 80
WIRE 448 304 448 208
WIRE 672 80 448 80
WIRE 672 160 448 160
WIRE 672 160 672 80
WIRE 672 192 672 160
WIRE 672 304 448 304
WIRE 672 304 672 272
WIRE 848 80 672 80
WIRE 848 112 848 80
SYMBOL pmos4 400 112 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=100n w=1u
SYMATTR InstName M1
SYMATTR Value P_50n
SYMBOL voltage 320 80 R0
WINDOW 0 -93 54 Left 0
WINDOW 3 -93 82 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSG
SYMATTR Value 0
SYMBOL voltage 672 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 54 Left 0
WINDOW 3 38 82 Left 0
SYMATTR InstName VSD
SYMATTR Value 100m
FLAG 848 112 0
TEXT 384 336 Left 0 !.dc VSG 0 1 1m
TEXT 384 360 Left 0 !.lib cmosedu_models.txt
TEXT 360 40 Left 0 ;Plot Id(M1) and d(Id(M1)) (to get gm)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8610.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8610.asy)
C1 N003 0 .001
R2 OUT N006 1Meg
R1 N005 0 60.4K
XU1 0 N003 N005 IN IN N006 N004 NC_01 0 OUT N001 N002 0 LT8610 ;pnba SYNC)TR/SS)RT)EN/UV)VIN)FB)SW)PG)GND)BIAS)INTVcc)BST)PGND
C5 OUT N006 10p
C4 OUT 0 47 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
Rload OUT 0 2
C2 N001 0 1
L1 N004 OUT 4.7 Rser=3m
C3 N002 N004 0.1
V1 IN 0 12
R3 N006 0 243K
.tran 750u startup
.lib LT8610.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 680
WIRE 64 -80 -32 -80
WIRE 256 -80 64 -80
WIRE -32 -48 -32 -80
WIRE 256 -48 256 -80
WIRE 64 0 64 -80
WIRE 112 0 64 0
WIRE 416 0 400 0
WIRE 496 0 480 0
WIRE -32 48 -32 32
WIRE 112 96 64 96
WIRE 624 96 400 96
WIRE 432 192 400 192
WIRE 432 208 432 192
WIRE 32 288 16 288
WIRE 112 288 96 288
WIRE 432 288 432 272
WIRE 432 288 400 288
WIRE 512 288 432 288
WIRE 624 288 624 96
WIRE 624 288 592 288
WIRE 736 288 624 288
WIRE 832 288 736 288
WIRE 928 288 832 288
WIRE 624 304 624 288
WIRE 736 304 736 288
WIRE 832 304 832 288
WIRE 928 304 928 288
WIRE 112 384 32 384
WIRE 624 384 400 384
WIRE 736 384 736 368
WIRE 736 384 624 384
WIRE 32 400 32 384
WIRE 624 400 624 384
WIRE 832 400 832 368
WIRE 928 400 928 384
WIRE 192 448 192 432
WIRE 320 448 320 432
WIRE 32 496 32 480
WIRE 624 496 624 480
SYMBOL voltage -32 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 608 384 R0
SYMATTR InstName R3
SYMATTR Value 243K
SYMBOL cap 96 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .001
SYMBOL LT8610 256 192 R0
SYMATTR InstName U1
SYMBOL cap 416 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 416 208 R0
SYMATTR InstName C3
SYMATTR Value 0.1
SYMBOL res 912 288 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL cap 720 304 R0
SYMATTR InstName C5
SYMATTR Value 10p
SYMBOL ind 496 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL res 16 384 R0
SYMATTR InstName R1
SYMATTR Value 60.4K
SYMBOL cap 816 304 R0
SYMATTR InstName C4
SYMATTR Value 47
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL res 608 288 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
FLAG 192 448 0
FLAG 320 448 0
FLAG 32 496 0
FLAG 16 288 0
FLAG -32 48 0
FLAG 496 0 0
FLAG 832 400 0
FLAG 624 496 0
FLAG 928 400 0
FLAG 928 288 OUT
FLAG -32 -80 IN
FLAG 64 96 0
TEXT 848 488 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8672.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8672.asy)
XU1 OUT 0 NC_01 MP_02 MP_03 N004 N003 OUT IN N002 LT8672 ;pnba EN/UVLO)GND)PG)))AUXSW)AUX)DRAIN)SOURCE)GATE
MQ1 OUT N002 IN IN BSC028N06LS3
D2 N001 IN EDZV33B
C3 OUT 0 1000 Rser=20m
D1 N001 0 EDZV15B
L1 OUT N004 100 Rser=5
C2 OUT 0 10 Rser=10m
V1 IN 0 SINE(12 3 50K 0.2)
C1 OUT N003 1
Rload OUT 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 210m
.lib LT8672.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -272 -64 -576 -64
WIRE -32 -64 -272 -64
WIRE 80 -64 -32 -64
WIRE 224 -64 176 -64
WIRE 352 -64 224 -64
WIRE 480 -64 352 -64
WIRE 624 -64 480 -64
WIRE 704 -64 624 -64
WIRE 864 -64 704 -64
WIRE -576 -48 -576 -64
WIRE -272 -48 -272 -64
WIRE 480 -48 480 -64
WIRE 624 -48 624 -64
WIRE 704 -48 704 -64
WIRE 864 -48 864 -64
WIRE 352 -32 352 -64
WIRE -272 32 -272 16
WIRE 224 32 224 -64
WIRE 224 32 -128 32
WIRE -576 48 -576 32
WIRE -32 48 -32 -64
WIRE 96 48 96 -16
WIRE 224 48 224 32
WIRE 352 48 352 32
WIRE 480 48 480 32
WIRE 624 48 624 16
WIRE 704 48 704 16
WIRE 864 48 864 32
WIRE -272 112 -272 96
WIRE -128 176 -128 32
WIRE -96 176 -128 176
WIRE 224 320 224 304
SYMBOL voltage -576 -64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(12 3 50K 0.2)
SYMBOL zener -288 32 R0
WINDOW 0 28 8 Left 2
WINDOW 3 21 62 Left 2
SYMATTR InstName D1
SYMATTR Value EDZV15B
SYMBOL ind 464 -64 R0
WINDOW 123 38 94 Left 2
WINDOW 0 38 28 Left 2
WINDOW 3 38 61 Left 2
SYMATTR Value2 Rser=5
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL zener -288 16 M180
WINDOW 0 24 57 Left 2
WINDOW 3 21 10 Left 2
SYMATTR InstName D2
SYMATTR Value EDZV33B
SYMBOL LT8672 224 176 R0
WINDOW 3 1 47 Center 2
SYMATTR InstName U1
SYMBOL cap 688 -48 R0
WINDOW 123 23 57 Left 2
WINDOW 3 39 35 Left 2
SYMATTR Value2 Rser=20m
SYMATTR Value 1000
SYMATTR InstName C3
SYMBOL cap 336 -32 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 848 -64 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL nmos 176 -16 M270
WINDOW 0 83 47 VTop 2
WINDOW 3 56 47 VTop 2
SYMATTR InstName Q1
SYMATTR Value BSC028N06LS3
SYMBOL cap 608 -48 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMATTR Value2 Rser=10m
FLAG 624 48 0
FLAG 704 48 0
FLAG 864 48 0
FLAG 224 320 0
FLAG -272 112 0
FLAG -576 -64 IN
FLAG 864 -64 OUT
FLAG -576 48 0
TEXT 528 344 Left 2 !.tran 210m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4257-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Diode Bridge
* Set for Class 4 Load
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4257-1.asy)
R2 N001 N004 100K
D2 N002 IN MURS120
XU1 NC_01 N003 NC_02 N002 OUT N004 N002 N001 LTC4257-1 ;pnba NC)Rclass)NC)Vin)Vout)_PWRGD)SigDisA)GND
Cload N001 OUT 100 Rser=10m
VPSE 0 IN PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 17.5 515m 17.5 516m 57)
Rclass N003 N002 30.9
D1 0 N001 MURS120
Rload N001 OUT 1.3K
C1 N001 N002 .1 Rser=10m
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.7
.lib LTC4257-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1308 744
WIRE -704 128 -1296 128
WIRE -480 128 -704 128
WIRE -352 128 -416 128
WIRE 336 128 -352 128
WIRE 480 128 336 128
WIRE 592 128 480 128
WIRE 752 128 592 128
WIRE 368 176 -80 176
WIRE -704 192 -704 128
WIRE 336 272 336 128
WIRE 336 272 320 272
WIRE 480 272 480 128
WIRE 592 272 592 128
WIRE 752 272 752 128
WIRE -1296 288 -1296 128
WIRE -352 288 -352 128
WIRE -32 352 -192 352
WIRE 368 352 368 176
WIRE 368 352 320 352
WIRE -192 400 -192 352
WIRE 480 432 480 352
WIRE 480 432 320 432
WIRE -1296 512 -1296 368
WIRE -480 512 -1296 512
WIRE -352 512 -352 352
WIRE -352 512 -416 512
WIRE -192 512 -192 480
WIRE -192 512 -352 512
WIRE -80 512 -80 176
WIRE -80 512 -192 512
WIRE -32 512 -80 512
WIRE 592 512 592 336
WIRE 592 512 320 512
WIRE 752 512 752 352
WIRE 752 512 592 512
SYMBOL diode -480 112 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MURS120
SYMBOL res 736 256 R0
SYMATTR InstName Rload
SYMATTR Value 1.3K
SYMBOL cap 576 272 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName Cload
SYMATTR Value 100
SYMBOL cap -368 288 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL diode -416 528 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value MURS120
SYMBOL res 464 256 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res -208 384 R0
SYMATTR InstName Rclass
SYMATTR Value 30.9
SYMBOL LTC4257-1 144 368 R0
SYMATTR InstName U1
SYMBOL voltage -1296 272 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 17.5 515m 17.5 516m 57)
SYMATTR InstName VPSE
FLAG 752 512 OUT
FLAG -704 192 0
FLAG -1296 512 IN
TEXT 392 576 Left 2 !.tran 0.7
TEXT -360 64 Right 2 ;Diode Bridge
TEXT -280 544 Left 2 ;Set for Class 4 Load
* Z:\tmp\asc_dec_bjh7r6w2\15917460908c_Draft_pnp-Transistor_als_Diode_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 IN1 IN2 1k
Q1 IN2 IN2 0 0 2n3906
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 512 48 336 48
WIRE 288 128 208 128
WIRE 336 128 336 48
WIRE 336 128 288 128
WIRE 336 144 336 128
WIRE 512 144 512 128
WIRE 512 144 448 144
WIRE 592 144 512 144
WIRE 512 160 512 144
WIRE 448 208 448 144
WIRE 288 256 288 128
WIRE 512 288 512 256
WIRE 512 288 80 288
WIRE 592 288 512 288
WIRE 592 304 592 288
SYMBOL res 496 32 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL pnp 448 160 R0
SYMATTR InstName Q1
SYMATTR Value 2n3906
FLAG 592 304 0
FLAG 336 144 IN1
FLAG 592 144 IN2