Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8608.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8608.asy)
Vin IN 0 SINE(0 1 100K)
R2 OUT N001 10K
R1 N001 0 10K
V2 -V 0 -2.5
XU1 IN N001 +V -V OUT AD8608 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 2.5
Rload OUT 0 10K
.tran 100u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 320 -1104 304 -1104
WIRE 416 -1104 400 -1104
WIRE 432 -1104 416 -1104
WIRE 528 -1104 512 -1104
WIRE 80 -992 80 -1008
WIRE 192 -992 192 -1008
WIRE 416 -992 416 -1104
WIRE 432 -992 416 -992
WIRE 528 -976 528 -1104
WIRE 528 -976 496 -976
WIRE 656 -976 528 -976
WIRE 432 -960 320 -960
WIRE 656 -960 656 -976
WIRE 320 -944 320 -960
WIRE 80 -896 80 -912
WIRE 192 -896 192 -912
WIRE 656 -864 656 -880
WIRE 320 -848 320 -864
SYMBOL Opamps\\AD8608 464 -1040 R0
SYMATTR InstName U1
SYMBOL voltage 80 -1008 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 640 -976 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL res 528 -1120 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 320 -960 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL res 416 -1120 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 192 -1008 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
FLAG 80 -1008 +V
FLAG 80 -896 0
FLAG 320 -848 0
FLAG 656 -976 OUT
FLAG 320 -960 IN
FLAG 464 -1008 +V
FLAG 192 -1008 -V
FLAG 464 -944 -V
FLAG 304 -1104 0
FLAG 656 -864 0
FLAG 192 -896 0
TEXT 544 -808 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX34406F.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX34406F.asy)
Rsense IN+ IN- 5m
Ccdly CDLY 0 10n
Vcm IN+ 0 12
Iload IN- 0 PWL(0 1 1m 1 +1n 5 8m 5 +1n 1)
VENA ENA 0 PWL(0 5 9m 5 +1n 0 +250u 0 +1n 5)
C1 OUT 0 100p
VDD VDD 0 5
Rpu2 VDD SHTDN 10k
XU1 IN+ IN- VDD 0 OUT OC ENA SHTDN CDLY MAX34406F ;pnba IN+)IN-)VDD)GND)OUT)OC)ENA)SHTDN)CDLY
Rpu1 VDD OC 10k
R1 OUT 0 1Meg
.tran 10m
.lib MAX34406F.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 -64 112 -64
WIRE 240 -64 208 -64
WIRE 416 -64 240 -64
WIRE 528 -64 416 -64
WIRE 112 -48 112 -64
WIRE 416 -32 416 -64
WIRE 528 -32 528 -64
WIRE 240 0 240 -64
WIRE 240 32 240 0
WIRE -336 64 -448 64
WIRE 112 64 -336 64
WIRE 144 64 112 64
WIRE -336 80 -336 64
WIRE 368 80 336 80
WIRE 416 80 416 48
WIRE 416 80 368 80
WIRE 384 128 336 128
WIRE 528 128 528 48
WIRE 528 128 384 128
WIRE -336 176 -336 160
WIRE 112 176 -336 176
WIRE 144 176 112 176
WIRE 368 176 336 176
WIRE 528 176 368 176
WIRE 640 176 528 176
WIRE -448 208 -448 64
WIRE -336 208 -336 176
WIRE 528 208 528 176
WIRE 112 224 -48 224
WIRE 144 224 112 224
WIRE 640 224 640 176
WIRE 112 272 64 272
WIRE 144 272 112 272
WIRE 528 304 528 288
WIRE 640 304 640 288
WIRE 240 320 240 304
WIRE -448 352 -448 288
WIRE -336 352 -336 288
WIRE -336 352 -448 352
WIRE 64 352 64 272
WIRE -448 368 -448 352
WIRE -48 368 -48 224
WIRE -48 448 -48 432
WIRE 64 448 64 432
SYMBOL current -336 208 R0
WINDOW 123 24 106 Left 2
SYMATTR Value2 8m 5 +1n 1)
SYMATTR InstName Iload
SYMATTR Value PWL(0 1 1m 1 +1n 5
SYMBOL res -352 64 R0
SYMATTR InstName Rsense
SYMATTR Value 5m
SYMBOL res 512 -48 R0
SYMATTR InstName Rpu2
SYMATTR Value 10k
SYMBOL voltage 224 -64 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL cap 624 224 R0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL MAX34406F 240 176 R0
WINDOW 0 76 -155 Bottom 2
WINDOW 3 115 135 Top 2
SYMATTR InstName U1
SYMBOL res 512 192 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL voltage -448 192 R0
SYMATTR InstName Vcm
SYMATTR Value 12
SYMBOL res 400 -48 R0
SYMATTR InstName Rpu1
SYMATTR Value 10k
SYMBOL voltage 64 336 R0
SYMATTR InstName VENA
SYMATTR Value PWL(0 5 9m 5 +1n 0 +250u 0 +1n 5)
SYMBOL cap -64 368 R0
SYMATTR InstName Ccdly
SYMATTR Value 10n
FLAG 240 320 0
FLAG -48 448 0
FLAG 528 304 0
FLAG 640 304 0
FLAG 368 176 OUT
FLAG 384 128 SHTDN
FLAG 368 80 OC
FLAG 112 -48 0
FLAG 240 0 VDD
FLAG -448 368 0
FLAG 112 224 CDLY
FLAG 64 448 0
FLAG 112 64 IN+
FLAG 112 176 IN-
FLAG 112 272 ENA
TEXT -496 472 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3008.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3008.asy)
C1 OUT 0 1
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 60
XU1 IN OUT OUT 0 IN LT3008 ;pnba IN)OUT)ADJ)GND)_SHDN
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 60
SYMBOL PowerProducts\\LT3008 176 96 R0
SYMATTR InstName U1
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 336 248 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\0747d30f2b24_lab3Scheme.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1097.asy)
;ac dec 100 1 1meg
V1 N003 0 12
C2 N004 N001 101n
R5 N006 0 23.8k
XU2 N006 N004 N003 N007 N002 LT1097 ;pnba In+)In-)V+)V-)OUT
R3 N002 N004 24k
R6 N001 0 98.5
R1 N001 N005 4.3k
V3 N005 0 PULSE(-2 2 0 1u 1u .02 .04) AC 25m
V2 0 N007 12
C4 N002 N001 100.5n
.tran 100ms
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 696
WIRE 352 -160 48 -160
WIRE 480 -160 416 -160
WIRE 624 -48 432 -48
WIRE 336 0 304 0
WIRE 480 0 480 -160
WIRE 480 0 416 0
WIRE 800 32 624 32
WIRE -80 144 -160 144
WIRE 48 144 48 -160
WIRE 48 144 0 144
WIRE 96 144 48 144
WIRE 304 144 304 0
WIRE 304 144 160 144
WIRE 432 160 432 -48
WIRE 432 160 368 160
WIRE 48 176 48 144
WIRE 368 176 368 160
WIRE 304 192 304 144
WIRE 336 192 304 192
WIRE 480 208 480 0
WIRE 480 208 400 208
WIRE -160 224 -160 144
WIRE 336 224 304 224
WIRE 304 240 304 224
WIRE 304 240 160 240
WIRE 160 272 160 240
WIRE 368 288 368 240
WIRE 624 288 624 112
WIRE 624 288 368 288
WIRE -160 384 -160 304
WIRE 48 384 48 256
WIRE 48 384 -160 384
WIRE 160 384 160 352
WIRE 160 384 48 384
WIRE 800 384 800 32
WIRE 800 384 160 384
WIRE 160 512 160 384
SYMBOL res 32 160 R0
SYMATTR InstName R6
SYMATTR Value 98.5
SYMBOL voltage -160 208 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 25m
SYMATTR InstName V3
SYMATTR Value PULSE(-2 2 0 1u 1u .02 .04)
SYMBOL cap 416 -176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 100.5n
SYMBOL res 432 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 24k
SYMBOL OpAmps\\LT1097 368 144 R0
SYMATTR InstName U2
SYMBOL cap 160 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 101n
SYMBOL Misc\\battery 624 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL res 16 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 4.3k
SYMBOL res 144 256 R0
SYMATTR InstName 5
SYMATTR Value 23.8k
SYMBOL Misc\\battery 624 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 160 512 0
TEXT -176 608 Left 2 !;ac dec 100 1 1meg
TEXT -192 632 Left 2 !.tran 100ms
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7185-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
C2 OUT 0 4.7 Rser=5m
V1 IN 0 -2
R3 OUT 0 2.4
C1 N001 N002 10n
C3 N001 0 1
C4 N003 0 1
XU1 OUT OUT N001 N002 IN 0 N003 IN ADP7185-1.2 ;pnba Vout)Sense)VA)VAFB)EN)GND)Vreg)Vin
.tran 200m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7185-1.2.asy)
.lib ADP7185-1.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 16 -48
WIRE 96 -48 32 -48
WIRE 112 -48 96 -48
WIRE 400 -48 368 -48
WIRE 432 -48 400 -48
WIRE 496 -48 432 -48
WIRE 512 -48 496 -48
WIRE 16 -32 16 -48
WIRE 432 -32 432 -48
WIRE 400 16 400 -48
WIRE 400 16 368 16
WIRE 432 48 432 32
WIRE 512 48 512 32
WIRE 16 64 16 48
WIRE 96 80 96 -48
WIRE 112 80 96 80
WIRE 464 80 368 80
WIRE 384 144 368 144
WIRE 464 144 464 80
WIRE 464 144 448 144
WIRE 464 160 464 144
WIRE 176 224 176 208
WIRE 304 224 304 208
WIRE 464 240 464 224
WIRE 176 304 176 288
FLAG 16 64 0
FLAG 432 48 0
FLAG 304 224 0
FLAG 512 48 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 464 240 0
FLAG 176 304 0
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=5m
SYMBOL voltage 16 -48 R0
SYMATTR InstName V1
SYMATTR Value -2
SYMBOL res 496 -64 R0
SYMATTR InstName R3
SYMATTR Value 2.4
SYMBOL cap 448 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL cap 448 160 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 160 224 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL ADP7185-1.2 240 48 R0
SYMATTR InstName U1
TEXT 240 360 Center 2 !.tran 200m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0a2292c5498b_Interview01.asc
* Generated by LTspice 26.0.1 for Windows.
* 5.92
* 4.5
* 6.8
* Q1. Explain the principle of this circuit.\nQ2. What's the reason for having Q1 and Q2 in that topology?\nQ3. Can we replace D3 with something else?\nQ4. What would have happened if the diodes were reversed?
* R1=1 65mV drop instead of 650mV
R3 N002 N003 750
RL c N004 33
D2 0 N006 MMBZ6V8ALY
R2 c N002 390
D3 0 N003 PTZ6_8B
D1 N006 N002 STZ5_6N
R1 c N001 1
Q1 N002 N003 N005 0 2N2222
V1 N001 0 10
Q2 N004 N005 N007 0 BCW60A
R4 N007 0 R=if(time>300m,100,500)
C1 c 0 4.7m
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 500m
.ic V(c)=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1808 1000
WIRE -48 128 -96 128
WIRE 80 128 80 96
WIRE 80 128 32 128
WIRE 288 128 80 128
WIRE 784 128 288 128
WIRE 288 160 288 128
WIRE -96 192 -96 128
WIRE 288 272 288 240
WIRE 496 272 288 272
WIRE 656 272 496 272
WIRE 496 288 496 272
WIRE 784 288 784 128
WIRE 288 400 288 272
WIRE 656 400 656 272
WIRE 80 416 80 128
WIRE 496 448 496 368
WIRE 592 448 496 448
WIRE 784 464 784 368
WIRE 496 512 496 448
WIRE 656 512 656 496
WIRE 720 512 656 512
WIRE 288 544 288 464
WIRE 784 576 784 560
WIRE -96 656 -96 272
WIRE 80 656 80 480
WIRE 80 656 -96 656
WIRE 288 656 288 608
WIRE 288 656 80 656
WIRE 496 656 496 576
WIRE 496 656 288 656
WIRE 784 656 496 656
WIRE 80 688 80 656
SYMBOL res 272 144 R0
SYMATTR InstName R2
SYMATTR Value 390
SYMBOL npn 592 400 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL zener 304 464 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value STZ5_6N
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 480 272 R0
SYMATTR InstName R3
SYMATTR Value 750
SYMBOL res 768 272 R0
SYMATTR InstName RL
SYMATTR Value 33
SYMBOL res 48 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -96 176 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 768 560 R0
SYMATTR InstName R4
SYMATTR Value R=if(time>300m,100,500)
SYMBOL zener 304 608 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value MMBZ6V8ALY
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL zener 512 576 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value PTZ6_8B
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL npn 720 464 R0
SYMATTR InstName Q2
SYMATTR Value BCW60A
SYMBOL cap 64 416 R0
SYMATTR InstName C1
SYMATTR Value 4.7m
FLAG 80 688 0
FLAG 80 96 c
TEXT 312 432 Left 2 ;5.92
TEXT 320 576 Left 2 ;4.5
TEXT -130 714 Left 2 !.tran 500m
TEXT 552 576 Left 2 ;6.8
TEXT -456 752 Left 5 ;Q1. Explain the principle of this circuit.\nQ2. What's the reason for having Q1 and Q2 in that topology?\nQ3. Can we replace D3 with something else?\nQ4. What would have happened if the diodes were reversed?
TEXT 32 48 Left 2 !.ic V(c)=0
TEXT 32 -8 Left 2 ;R1=1 65mV drop instead of 650mV
* Z:\home\khalils\Downloads\files\data\raw_asc\20ebfeee7bf4_B_function.asc
* Generated by LTspice 26.0.1 for Windows.
B2 tanh1 0 V=5*tanh(V(x))
B1 sinc 0 V=10*if(abs(V(x))<1e-9, 1, sin(2*pi*V(x))/(2*pi*V(x)))
B3 tanh2 0 V=5*tanh(time-9)
V1 x 0 PWL(0 -10 20 10)
B4 out 0 V=0.1*V(x)*V(x)
.tran 0 20 0 1m
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 64 -176 64
WIRE 336 64 144 64
WIRE -176 96 -176 64
WIRE 144 96 144 64
WIRE -176 208 -176 176
WIRE 144 208 144 176
WIRE 16 272 -176 272
WIRE -176 304 -176 272
WIRE -176 416 -176 384
WIRE 16 480 -176 480
WIRE 352 480 160 480
WIRE -176 512 -176 480
WIRE 160 512 160 480
WIRE -176 624 -176 592
WIRE 160 624 160 592
SYMBOL bv -176 496 R0
SYMATTR InstName B2
SYMATTR Value V=5*tanh(V(x))
SYMBOL bv 144 80 R0
SYMATTR InstName B4
SYMATTR Value V=0.1*V(x)*V(x)
SYMBOL voltage -176 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 -10 20 10)
SYMBOL bv -176 288 R0
SYMATTR InstName B1
SYMATTR Value V=10*if(abs(V(x))<1e-9, 1, sin(2*pi*V(x))/(2*pi*V(x)))
SYMBOL bv 160 496 R0
SYMATTR InstName B3
SYMATTR Value V=5*tanh(time-9)
FLAG -176 208 0
FLAG 16 64 x
FLAG -176 416 0
FLAG 16 272 sinc
FLAG -176 624 0
FLAG 16 480 tanh1
FLAG 160 624 0
FLAG 352 480 tanh2
FLAG 144 208 0
FLAG 336 64 out
TEXT -168 -40 Left 0 !.tran 0 20 0 1m
TEXT -168 -8 Left 0 !.options plotwinsize=0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3485-0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3485-0.asy)
L1 N002 N005 10 Rpar=2K Rser=.1
V1 N001 0 5
R3 N004 N001 10K
XU1 N001 N002 N001 N005 MP_01 N008 N007 N001 N004 N006 0 LT3485-0 ;pnba Charge)Vbat)Vin)SW))IBGTout)IBGTin)IBGTpwr)_Done)Vmont)GND
L2 0 N003 {10u*10.2*10.2} Rpar=1Meg
K1 L1 L2 1
V3 N007 0 PWL(30m 0 30.01m 3 30.1m 3 30.11m 0)
C1 OUT 0 .1
D1 N003 OUT D
V2 N002 0 3
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 50m startup
.lib LT3485-0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3528 1804
WIRE 1936 1152 1936 1136
WIRE 1712 1248 1520 1248
WIRE 1824 1248 1712 1248
WIRE 1936 1248 1936 1232
WIRE 2064 1248 1936 1248
WIRE 2224 1248 2112 1248
WIRE 2368 1248 2288 1248
WIRE 2064 1264 2064 1248
WIRE 2112 1264 2112 1248
WIRE 2368 1264 2368 1248
WIRE 1712 1296 1712 1248
WIRE 1824 1296 1824 1248
WIRE 1936 1296 1936 1248
WIRE 1520 1360 1520 1248
WIRE 1568 1360 1520 1360
WIRE 1664 1360 1648 1360
WIRE 2064 1360 2064 1344
WIRE 2064 1360 1984 1360
WIRE 2112 1360 2112 1344
WIRE 2368 1360 2368 1328
WIRE 1520 1440 1520 1360
WIRE 1664 1440 1520 1440
WIRE 2016 1440 1984 1440
WIRE 1520 1456 1520 1440
WIRE 1664 1520 1600 1520
WIRE 2016 1520 1984 1520
WIRE 1520 1552 1520 1536
WIRE 1600 1552 1600 1520
WIRE 1824 1600 1824 1584
WIRE 1600 1664 1600 1632
SYMBOL ind2 2128 1360 R180
WINDOW 0 -3 72 Right 2
WINDOW 3 0 43 Right 2
SYMATTR InstName L2
SYMATTR Value {10u*10.2*10.2}
SYMATTR SpiceLine Rpar=1Meg
SYMBOL ind2 2048 1248 R0
WINDOW 0 -6 35 Right 2
WINDOW 3 -4 73 Right 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rpar=2K Rser=.1
SYMBOL misc\\battery 1936 1248 M180
WINDOW 0 25 87 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL cap 2352 1264 R0
WINDOW 3 27 55 Left 2
SYMATTR Value .1
SYMATTR InstName C1
SYMBOL voltage 1600 1536 R0
WINDOW 3 12 110 Left 2
SYMATTR Value PWL(30m 0 30.01m 3 30.1m 3 30.11m 0)
SYMATTR InstName V3
SYMBOL diode 2224 1264 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL VOLTAGE 1520 1440 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LT3485-0 1824 1440 R0
SYMATTR InstName U1
SYMBOL res 1664 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
FLAG 2368 1360 0
FLAG 1824 1600 0
FLAG 1520 1552 0
FLAG 2112 1360 0
FLAG 1936 1136 0
FLAG 1600 1664 0
FLAG 2368 1248 OUT
TEXT 2048 1560 Left 2 !.tran 50m startup
TEXT 2088 1248 Bottom 2 !K1 L1 L2 1
* Z:\home\khalils\Downloads\files\data\raw_asc\2eb9a2fc9221_hw7_prob4.asc
* Generated by LTspice 26.0.1 for Windows.
* Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
C1 vout 0 1.6667m
I1 0 N001 0 AC 5 30
R1 N001 0 15
R2 vout N001 1
.options plotwinsize=0 numdgt=15 measdgt=15
.ac list {50/(2*pi)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 692
WIRE -176 -80 -384 -80
WIRE -112 -80 -176 -80
WIRE 0 -80 -32 -80
WIRE 16 -80 0 -80
WIRE -384 -32 -384 -80
WIRE -176 -32 -176 -80
WIRE 16 -16 16 -80
WIRE -384 128 -384 48
WIRE -208 128 -384 128
WIRE -176 128 -176 48
WIRE -176 128 -208 128
WIRE 16 128 16 48
WIRE 16 128 -176 128
WIRE -208 160 -208 128
SYMBOL res -16 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL current -176 48 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 52 Left 2
SYMATTR InstName I1
SYMATTR Value 0
SYMATTR Value2 AC 5 30
SYMBOL cap 0 -16 R0
SYMATTR InstName C1
SYMATTR Value 1.6667m
SYMBOL res -400 -48 R0
SYMATTR InstName R1
SYMATTR Value 15
FLAG -208 160 0
FLAG 0 -80 vout
TEXT -432 304 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ac list {50/(2*pi)}
TEXT -544 -648 Left 2 ;Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
* Z:\home\khalils\Downloads\files\data\raw_asc\496ddbd4a125__11_Clipper_using_opamp.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
V3 0 N001 SINE(0 10 50)
R1 P004 output 10k
V1 0 P001 15
V2 P002 0 15
V4 0 P004 3.3
XU1 output N001 P001 P002 P003 LT1001 ;pnba In+)In-)V+)V-)OUT
D1 output P003 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 0 240 -32
WIRE 0 144 0 112
WIRE 80 144 0 144
WIRE 240 160 208 160
WIRE 320 160 240 160
WIRE 80 176 -32 176
WIRE -32 320 -32 176
WIRE 240 320 240 160
WIRE 240 320 -32 320
IOPIN 320 160 Out
SYMBOL diode 208 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 29 -11 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL OpAmps\\OP07 112 96 R0
WINDOW 0 -69 61 Left 2
WINDOW 3 -165 64 Left 2
SYMATTR InstName U1
SYMBOL voltage 112 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL voltage 112 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 224 64 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage 240 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 3.3
SYMBOL voltage 0 16 R0
WINDOW 3 -204 55 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 10 50)
FLAG 112 48 0
FLAG 112 272 0
FLAG 0 32 0
FLAG 240 -32 0
FLAG 320 160 output
TEXT -206 326 Left 2 !.tran 0.05
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5300-1.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 OUT 2.2 Rser=80m
C1 OUT 0 10
R2 N003 0 19.6K
R1 OUT N001 1Meg
V1 IN 0 5
Rload OUT 0 36
XU1 IN IN 0 N003 OUT N001 0 0 N002 0 ADP5300-1 OVO=0 OD=0 ;pnba EN)PVin)Sync/Mode)VID)FB)VoutOK)Pgnd)Agnd)SW)Stop
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5300-1.asy)
.lib ADP5300-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 64 64 64
WIRE 160 64 144 64
WIRE 496 64 416 64
WIRE 608 64 576 64
WIRE 64 80 64 64
WIRE 144 144 144 64
WIRE 160 144 144 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 608 144 608 64
WIRE 608 144 560 144
WIRE 688 144 608 144
WIRE 608 160 608 144
WIRE 688 160 688 144
WIRE 64 176 64 160
WIRE 160 224 144 224
WIRE 560 224 560 144
WIRE 560 224 416 224
WIRE 608 256 608 224
WIRE 688 256 688 240
WIRE 160 304 144 304
WIRE 448 304 416 304
WIRE 544 304 528 304
WIRE 240 384 240 368
WIRE 336 384 336 368
FLAG 544 304 0
FLAG 608 256 0
FLAG 240 384 0
FLAG 64 176 0
FLAG 688 144 OUT
FLAG 688 256 0
FLAG 64 64 IN
FLAG 336 384 0
FLAG 144 304 0
FLAG 144 224 0
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=80m
SYMBOL cap 592 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 432 320 R270
WINDOW 3 0 56 VBottom 2
WINDOW 0 32 56 VTop 2
SYMATTR Value 19.6K
SYMATTR InstName R2
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL voltage 64 64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 672 144 R0
SYMATTR Value 36
SYMATTR InstName Rload
SYMBOL ADP5300-1 288 192 R0
SYMATTR InstName U1
TEXT 440 384 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\14b322586600_vas_stage_pa.asc
* Generated by LTspice 26.0.1 for Windows.
I1 Output_stage V- I
C1 Output_stage Input_Stage Cdom
Q1 Output_stage N001 V+ 0 PNP
R1 V+ N001 R
Q2 0 Input_Stage N001 0 PNP
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 -48 -96 -48
WIRE 256 -48 128 -48
WIRE 416 -48 256 -48
WIRE 256 16 256 -48
WIRE 128 64 128 32
WIRE 192 64 128 64
WIRE 16 112 -96 112
WIRE 64 112 16 112
WIRE 160 160 128 160
WIRE 160 176 160 160
WIRE 16 272 16 112
WIRE 96 272 16 272
WIRE 256 272 256 112
WIRE 256 272 160 272
WIRE 416 272 256 272
WIRE 256 336 256 272
WIRE 256 448 256 416
WIRE 256 448 -96 448
WIRE 416 448 256 448
SYMBOL current 256 336 R0
SYMATTR InstName I1
SYMBOL pnp 64 160 M180
SYMATTR InstName Q2
SYMBOL res 112 -64 R0
SYMATTR InstName R1
SYMBOL cap 160 256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value Cdom
SYMBOL pnp 192 112 M180
SYMATTR InstName Q1
FLAG 160 176 0
FLAG -96 112 Input_Stage
FLAG -96 -48 V+
FLAG 416 272 Output_stage
FLAG -96 448 V-