* Z:\home\khalils\Downloads\files\data\raw_asc\ADAQ4380-4.asc
* Generated by LTspice 26.0.1 for Windows.
* .tran 100u
* .ac dec 201 10k 1g
* Simulation Settings:
* Power Supplies
* Notes
* When used with multiple active components, transient analysis may have a longer\nsimulation time. For faster run time, do the following:\n1. Use .option noopiter\n2. Use the ADAQ4380 model to simulate the performance of the two channels.\n \nEach ADAQ4380-4 channel is set to different gain configurations just for simulation.\nRefer to ADAQ4380-4 datasheet on how to correctly set the gain per channel.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\ADAQ4380-4.asy)
* Library below included based on ModelFile attribute of instance XU6 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1208.asy)
* Library below included based on ModelFile attribute of instance XU1, XU3, XU4, XU5 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1359.asy)
C4 OUTA 0 10p
V8 V+ 0 15
V7 V- 0 -15
XU3 IN_B N007 V+ V- N007 LT1357 ;pnba In+)In-)V+)V-)OUT
V5 CNV 0 PULSE(3.3 0 50n 0.1n 0.1n 190n {1/fs})
C1 OUTD 0 10p
V9 IN_C 0 SINE(0 3.3 20k) AC 1
V6 VS+ 0 5
V4 IN_D 0 SINE(0 2.06 20k) AC 1
XU5 IN_D N009 V+ V- N009 LT1357 ;pnba In+)In-)V+)V-)OUT
C3 OUTB 0 10p
V3 N001 0 10
C2 OUTC 0 10p
XU6 mux_ctrl1 V+ V- N001 N003 NC_19 NC_20 IN_A NC_21 NC_22 NC_23 NC_24 V+ 0 0 0 ADG1208 ;pnba A0)EN)Vss)S1)S2)S3)S4)D)S8)S7)S6)S5)Vdd)GND)A2)A1
V10 mux_ctrl1 0 PULSE(0 3 0 1n 1n 0.5u 1u)
XU2 N005 N004 N005 NC_01 NC_02 N006 0 N006 VS+ 0 VS+ 0 VS+ VS+ N002 N002 CNV OUTA OUTB NC_03 N007 NC_04 NC_05 NC_06 NC_07 0 NC_08 NC_09 NC_10 N008 NC_11 NC_12 0 NC_13 NC_14 NC_15 N009 N009 NC_16 NC_17 0 0 NC_18 OUTC OUTD ADAQ4380-4 ;pnba OUTA-)INA2+)INA1+)SJA+)SJA-)INA1-)INA2-)OUTA+)VS+)VS-)REFIN)GND)IN_LDO)EN_LDO)OUT_LDO)VCC)CNV)SDOA)SDOB)OUTB-)INB2+)INB1+)SJB+)SJB-)INB1-)INB2-)OUTB+)OUTC-)INC2+)INC1+)SJC+)SJC-)INC1-)INC2-)OUTC+)OUTD-)IND2+)IND1+)SJD+)SJD-)IND1-)IND2-)OUTD+)SDOC)SDOD
V1 N003 0 -10
V2 IN_B 0 SINE(0 5.5 20k) AC 1
XU4 IN_C N008 V+ V- N008 LT1357 ;pnba In+)In-)V+)V-)OUT
XU1 IN_A N004 V+ V- N004 LT1357 ;pnba In+)In-)V+)V-)OUT
.param fs 4e6
.noise V(OUTA) V1 dec 201 1 1g
.lib ADAQ4380-4.sub
.lib ADG1208.sub
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2288 1108
WIRE -1168 -1040 -1168 -1072
WIRE -976 -1040 -976 -1072
WIRE -768 -1040 -768 -1072
WIRE -1168 -928 -1168 -960
WIRE -976 -928 -976 -960
WIRE -768 -928 -768 -960
WIRE 160 -688 112 -688
WIRE 480 -688 160 -688
WIRE 1120 -688 480 -688
WIRE 1344 -688 1120 -688
WIRE 160 -560 160 -688
WIRE 480 -560 480 -688
WIRE 1120 -560 1120 -688
WIRE 1344 -560 1344 -688
WIRE -1056 -512 -1056 -560
WIRE -1184 -448 -1440 -448
WIRE 1552 -416 1472 -416
WIRE -1440 -400 -1440 -448
WIRE -1184 -384 -1328 -384
WIRE -1328 -336 -1328 -384
WIRE -272 -336 -432 -336
WIRE -64 -304 -96 -304
WIRE -1440 -288 -1440 -320
WIRE -352 -272 -352 -288
WIRE -96 -272 -96 -304
WIRE -64 -272 -96 -272
WIRE 1552 -272 1552 -416
WIRE 1552 -272 1472 -272
WIRE -432 -256 -432 -336
WIRE -384 -256 -432 -256
WIRE -272 -240 -272 -336
WIRE -272 -240 -320 -240
WIRE -64 -240 -272 -240
WIRE -1328 -224 -1328 -256
WIRE -496 -224 -928 -224
WIRE -384 -224 -496 -224
WIRE -352 -192 -352 -208
WIRE -64 -112 -144 -112
WIRE -64 -80 -96 -80
WIRE -96 -48 -96 -80
WIRE -64 -48 -96 -48
WIRE -272 -32 -432 -32
WIRE -352 32 -352 16
WIRE -432 48 -432 -32
WIRE -384 48 -432 48
WIRE -1264 64 -1328 64
WIRE -1184 64 -1264 64
WIRE -880 64 -928 64
WIRE -272 64 -272 -32
WIRE -272 64 -320 64
WIRE -64 64 -272 64
WIRE -496 80 -576 80
WIRE -384 80 -496 80
WIRE -1328 112 -1328 64
WIRE -576 112 -576 80
WIRE -352 112 -352 96
WIRE -1184 128 -1248 128
WIRE -1248 192 -1248 128
WIRE -1184 192 -1248 192
WIRE -64 192 -144 192
WIRE 1808 192 1472 192
WIRE 1856 192 1808 192
WIRE -576 208 -576 192
WIRE -1328 240 -1328 192
WIRE -1248 240 -1248 192
WIRE -272 240 -432 240
WIRE 1728 240 1472 240
WIRE 1776 240 1728 240
WIRE 1856 240 1856 192
WIRE -1120 272 -1120 240
WIRE -992 288 -992 240
WIRE 1648 288 1472 288
WIRE 1696 288 1648 288
WIRE 1776 288 1776 240
WIRE -352 304 -352 288
WIRE -432 320 -432 240
WIRE -384 320 -432 320
WIRE -272 336 -272 240
WIRE -272 336 -320 336
WIRE -64 336 -272 336
WIRE 1568 336 1472 336
WIRE 1616 336 1568 336
WIRE 1696 336 1696 288
WIRE 1856 336 1856 304
WIRE -496 352 -576 352
WIRE -384 352 -496 352
WIRE -576 384 -576 352
WIRE -352 384 -352 368
WIRE 1504 384 1472 384
WIRE 1536 384 1504 384
WIRE 1616 384 1616 336
WIRE 1776 384 1776 352
WIRE 1696 432 1696 400
WIRE 1536 464 1536 384
WIRE -576 480 -576 464
WIRE 1616 480 1616 448
WIRE -64 528 -144 528
WIRE -272 576 -432 576
WIRE 1536 592 1536 544
WIRE -352 640 -352 624
WIRE -64 640 -96 640
WIRE -432 656 -432 576
WIRE -384 656 -432 656
WIRE -272 672 -272 576
WIRE -272 672 -320 672
WIRE -96 672 -96 640
WIRE -96 672 -272 672
WIRE -64 672 -96 672
WIRE -496 688 -576 688
WIRE -384 688 -496 688
WIRE -576 720 -576 688
WIRE -352 720 -352 704
WIRE -96 800 -144 800
WIRE -64 800 -96 800
WIRE -576 816 -576 800
WIRE -96 832 -96 800
WIRE -64 832 -96 832
WIRE 160 1056 160 1008
WIRE 400 1056 400 1008
WIRE 400 1056 160 1056
WIRE 160 1088 160 1056
RECTANGLE Normal 176 -848 -560 -1232 2
RECTANGLE Normal -592 -848 -1328 -1232 2
RECTANGLE Normal 1648 -848 208 -1232 2
SYMBOL voltage 1536 448 R0
WINDOW 3 24 96 Invisible 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(3.3 0 50n 0.1n 0.1n 190n {1/fs})
SYMATTR InstName V5
SYMBOL voltage -768 -1056 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 5
SYMBOL OpAmps\\LT1359 -352 0 R0
SYMATTR InstName U3
SYMBOL voltage -1328 -352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -10
SYMBOL voltage -576 368 M0
WINDOW 0 46 17 Left 2
WINDOW 123 45 47 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 43 79 Left 2
SYMATTR InstName V9
SYMATTR Value2 AC 1
SYMATTR Value SINE(0 3.3 20k)
SYMBOL voltage -1440 -416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -576 704 M0
WINDOW 0 46 17 Left 2
WINDOW 123 45 47 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 43 79 Left 2
SYMATTR InstName V4
SYMATTR Value2 AC 1
SYMATTR Value SINE(0 2.06 20k)
SYMBOL cap 1680 336 R0
SYMATTR InstName C2
SYMATTR Value 10p
SYMBOL voltage -576 96 M0
WINDOW 0 46 17 Left 2
WINDOW 123 45 47 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 43 79 Left 2
SYMATTR InstName V2
SYMATTR Value2 AC 1
SYMATTR Value SINE(0 5.5 20k)
SYMBOL ADC\\ADAQ4380-4 720 256 R0
SYMATTR InstName U2
SYMBOL OpAmps\\LT1359 -352 -304 R0
SYMATTR InstName U1
SYMBOL OpAmps\\LT1359 -352 272 R0
SYMATTR InstName U4
SYMBOL voltage -1168 -1056 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value 15
SYMBOL cap 1760 288 R0
SYMATTR InstName C3
SYMATTR Value 10p
SYMBOL cap 1600 384 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage -976 -1056 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value -15
SYMBOL OpAmps\\LT1359 -352 608 R0
SYMATTR InstName U5
SYMBOL cap 1840 240 R0
SYMATTR InstName C4
SYMATTR Value 10p
SYMBOL voltage -1328 96 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V10
SYMATTR Value PULSE(0 3 0 1n 1n 0.5u 1u)
SYMBOL Switches\\ADG1208 -1056 -192 R0
SYMATTR InstName U6
FLAG 160 1088 0
FLAG 1536 592 0
FLAG 1616 480 0
FLAG 1568 336 OUTD
FLAG 1696 432 0
FLAG 1648 288 OUTC
FLAG 1776 384 0
FLAG 1856 336 0
FLAG 1808 192 OUTA
FLAG 1728 240 OUTB
FLAG 112 -688 VS+
FLAG 1504 384 CNV
FLAG -768 -928 0
FLAG -496 -224 IN_A
FLAG -496 80 IN_B
FLAG -144 -112 0
FLAG -976 -928 0
FLAG -976 -1072 V-
FLAG -1168 -928 0
FLAG -1168 -1072 V+
FLAG -352 -288 V+
FLAG -352 -192 V-
FLAG -352 16 V+
FLAG -352 112 V-
FLAG -576 208 0
FLAG -144 192 0
FLAG -144 528 0
FLAG -496 352 IN_C
FLAG -352 288 V+
FLAG -352 384 V-
FLAG -576 480 0
FLAG -144 800 0
FLAG -496 688 IN_D
FLAG -352 624 V+
FLAG -352 720 V-
FLAG -576 816 0
FLAG -992 288 0
FLAG -1120 272 V-
FLAG -880 64 V+
FLAG -1056 -560 V+
FLAG -1328 -224 0
FLAG -1440 -288 0
FLAG -1248 240 0
FLAG -1328 240 0
FLAG -1264 64 mux_ctrl1
FLAG -768 -1072 VS+
TEXT -528 -1096 Left 4 ;.tran 100u
TEXT -528 -1024 Left 4 ;.ac dec 201 10k 1g
TEXT 1576 560 Left 3 !.param fs 4e6
TEXT -528 -952 Left 4 !.noise V(OUTA) V1 dec 201 1 1g
TEXT -456 -1184 Left 5 ;Simulation Settings:
TEXT -1168 -1184 Left 5 ;Power Supplies
TEXT 240 -1184 Left 5 ;Notes
TEXT 240 -1120 Left 3 ;When used with multiple active components, transient analysis may have a longer\nsimulation time. For faster run time, do the following:\n1. Use .option noopiter\n2. Use the ADAQ4380 model to simulate the performance of the two channels.\n \nEach ADAQ4380-4 channel is set to different gain configurations just for simulation.\nRefer to ADAQ4380-4 datasheet on how to correctly set the gain per channel.