Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\stepmodelparam.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
I1 0 N002 0
V1 N001 0 0
Q1 N001 N002 0 0 2N2222
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 10 10m I1 10u 50u 10u
.step NPN 2N2222(Vaf) 100 50 25
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2252 1608
WIRE 1872 1232 1728 1232
WIRE 1728 1248 1728 1232
WIRE 1872 1248 1872 1232
WIRE 1664 1296 1520 1296
WIRE 1520 1312 1520 1296
WIRE 1872 1344 1872 1328
WIRE 1728 1360 1728 1344
WIRE 1520 1408 1520 1392
SYMBOL npn 1664 1248 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL voltage 1872 1232 R0
WINDOW 39 0 0 Left 2
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL current 1520 1392 M180
WINDOW 0 23 76 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName I1
SYMATTR Value 0
FLAG 1520 1408 0
FLAG 1728 1360 0
FLAG 1872 1344 0
TEXT 1560 1448 Left 2 !.dc V1 0 10 10m I1 10u 50u 10u
TEXT 1552 1480 Left 2 !.step NPN 2N2222(Vaf) 100 50 25
TEXT 1736 1512 Top 1 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2935-4.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2935-4.asy)
V2 N005 0 PWL(0 0 9.599 0 9.6 3.6 9.999 3.6 10 0)
MQ1 N004 N005 0 0 BSS123
V1 N001 0 PWL(0 0 3.6 3.6 16 3.6 19.6 0 20.1 0 23.7 3.6)
XU1 0 0 0 0 N003 N002 N004 N001 LTC2935-4 ;pnba S2)S1)S0)GND)_PFO)_RST)MR)VCC
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20
.lib LTC2935-4.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1052 680
WIRE 240 32 -208 32
WIRE 240 48 240 32
WIRE 144 96 128 96
WIRE 352 96 336 96
WIRE 144 176 128 176
WIRE 352 176 336 176
WIRE 144 256 128 256
WIRE 352 256 336 256
WIRE 352 272 352 256
WIRE -208 288 -208 32
WIRE 240 320 240 304
WIRE 512 352 400 352
WIRE 512 368 512 352
WIRE -208 384 -208 368
WIRE 352 400 352 368
WIRE 512 464 512 448
SYMBOL nmos 400 272 M0
WINDOW 0 31 -5 Right 2
WINDOW 3 33 104 Right 2
SYMATTR InstName Q1
SYMATTR Value BSS123
SYMBOL LTC2935-4 240 176 R0
SYMATTR InstName U1
SYMBOL voltage -208 272 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 3.6 3.6 16 3.6 19.6 0 20.1 0 23.7 3.6)
SYMBOL voltage 512 352 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 9.599 0 9.6 3.6 9.999 3.6 10 0)
FLAG 240 320 0
FLAG 512 464 0
FLAG -208 384 0
FLAG 352 400 0
FLAG 128 256 0
FLAG 128 176 0
FLAG 128 96 0
TEXT 688 328 Left 2 !.tran 20
* Z:\home\khalils\Downloads\files\data\raw_asc\0495c6f3b833_TP2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
V3 N005 0 -10
R2 N001 0 1.8Meg
R5 0 N002 903.66
R4 N002 N001 220k
V1 N004 0 Rser=100k
R1 N001 N004 1.8Meg
V4 Vcc 0 10
R3 N003 N002 220k
XU1 0 N001 Vcc N005 N003 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.lib F:\Users\Ivan\Documents\LTspiceXVII\lib\LM324.lib
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1072 680
WIRE 496 -64 496 -80
WIRE 400 80 384 80
WIRE 496 80 496 16
WIRE 496 80 480 80
WIRE 512 80 496 80
WIRE 608 80 592 80
WIRE 224 96 224 80
WIRE 512 160 512 144
WIRE 240 176 176 176
WIRE 384 176 384 80
WIRE 384 176 320 176
WIRE 480 176 384 176
WIRE 608 192 608 80
WIRE 608 192 544 192
WIRE 480 208 464 208
WIRE 288 256 272 256
WIRE 368 256 352 256
WIRE 384 256 384 176
WIRE 384 256 368 256
WIRE 464 256 464 208
WIRE 176 272 176 176
WIRE 512 304 512 224
WIRE 176 448 176 352
WIRE 272 448 272 256
WIRE 272 448 176 448
WIRE 512 448 512 384
WIRE 512 448 272 448
WIRE 176 464 176 448
SYMBOL res 336 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1.8Meg
SYMBOL res 496 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -53 53 VTop 2
SYMATTR InstName R4
SYMATTR Value 220k
SYMBOL res 384 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.8Meg
SYMBOL res 480 -80 R0
SYMATTR InstName R5
SYMATTR Value 903.66
SYMBOL voltage 224 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL OpAmps\\UniversalOpAmp 512 192 R0
SYMATTR InstName U1
SYMBOL voltage 512 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -10
SYMBOL voltage 176 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 -127 97 Left 2
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR SpiceLine Rser=100k
SYMBOL res 608 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 -53 53 VTop 2
SYMATTR InstName R3
SYMATTR Value 220k
FLAG 224 96 0
FLAG 224 0 Vcc
FLAG 512 144 Vcc
FLAG 176 464 0
FLAG 496 -80 0
FLAG 464 256 0
TEXT 64 536 Left 2 !.lib F:\\Users\\Ivan\\Documents\\LTspiceXVII\\lib\\LM324.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX4489.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX4489.asy)
V1 IN 0 SINE(0 50m 100k)
Vee 0 Vee 2.5
RL OUT 0 10k
XU1 IN OUT Vcc Vee OUT MAX4489 ;pnba In+)In-)V+)V-)OUT
CL OUT 0 15p
Vcc Vcc 0 2.5
.tran 10u
.lib MAX4489.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 144 288 144 272
WIRE 432 352 432 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 144 400 144 368
WIRE 144 400 112 400
WIRE 400 400 304 400
WIRE 112 416 112 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 144 448 144 400
WIRE 432 448 432 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 144 544 144 528
WIRE 304 592 304 576
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 100k)
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 144 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 2.5
SYMBOL voltage 144 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 2.5
SYMBOL MAX4489 432 320 R0
SYMATTR InstName U1
FLAG 720 384 OUT
FLAG 144 272 Vcc
FLAG 144 544 Vee
FLAG 432 320 Vcc
FLAG 432 448 Vee
FLAG 112 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
TEXT 96 632 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG841.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input.\nCharge injection not included.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG841.asy)
C1 D 0 33p
VS S 0 3
R1 D 0 47
XU1 +V IN S D 0 ADG841 ;pnba Vdd)IN)S)D)GND
V2 IN 0 PULSE(0 2.4 0 10n 10n 980n 2u)
V1 +V 0 3.3
.tran 10u
.lib ADG841.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2844 1336
WIRE -144 -96 -144 -112
WIRE -368 -16 -400 -16
WIRE -272 -16 -288 -16
WIRE -240 -16 -272 -16
WIRE -32 -16 -48 -16
WIRE 0 -16 -32 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -272 48 -368 48
WIRE -240 48 -272 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL ADG841 -144 32 R0
SYMATTR InstName U1
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 2.4 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 33p
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 47
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
FLAG -272 -16 S
FLAG -272 48 IN
FLAG -32 -16 D
TEXT -16 176 Left 2 !.tran 10u
TEXT -592 -232 Left 2 ;Note:\nSwitch shown for a logic 0 input.\nCharge injection not included.
* Z:\tmp\asc_dec_bjh7r6w2\0ee497f66acf_Design_A_Transistor_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Rb N004 N003 750
Vcc Vcc 0 12V
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 3268 680
WIRE 304 0 304 -32
WIRE 304 96 304 64
WIRE 400 96 304 96
WIRE -704 144 -704 80
WIRE -544 160 -544 96
WIRE 16 192 -160 192
WIRE 336 192 96 192
WIRE -704 256 -704 224
WIRE -544 272 -544 240
SYMBOL res 112 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rb
SYMATTR Value 750
SYMBOL voltage -704 128 R0
SYMATTR InstName Vcc
SYMATTR Value 12V
FLAG -704 256 0
FLAG -704 80 Vcc
FLAG -544 272 0
FLAG -544 96 Vcontrol
* Z:\home\khalils\Downloads\files\data\raw_asc\15b3bfcd6e37_Lab2_NonIdeal.asc
* Generated by LTspice 26.0.1 for Windows.
* Ac 325
R2 N001 0 1G
G4 N005 0 N001 0 {1/N}
Vs N002 0 Sin(0 325 50)
G3 N004 0 N001 0 1
G2 0 N001 N005 0 {1/N}
Rload N006 0 100
Rsec N006 N005 5
Riron N004 0 30k
Rprimary N004 N003 70
G1 0 N001 N004 0 1
Rs N003 N002 50
.tran 50m
.param N=15 ; turns ratio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 160 0 112 0
WIRE 544 0 448 0
WIRE 160 16 160 0
WIRE 448 16 448 0
WIRE 304 32 208 32
WIRE 400 32 304 32
WIRE 304 128 304 32
WIRE 304 128 208 128
WIRE 400 128 304 128
WIRE 208 160 208 128
WIRE 304 160 304 128
WIRE 400 160 400 128
WIRE -176 176 -336 176
WIRE -48 176 -96 176
WIRE 160 176 160 96
WIRE 160 176 32 176
WIRE 448 176 448 96
WIRE 592 176 448 176
WIRE 720 176 672 176
WIRE -336 192 -336 176
WIRE 720 192 720 176
WIRE -32 224 -288 224
WIRE 112 224 112 0
WIRE 160 224 112 224
WIRE 544 224 544 0
WIRE 544 224 448 224
WIRE 656 224 544 224
WIRE -32 256 -32 224
WIRE 32 256 -32 256
WIRE 112 256 112 224
WIRE 112 256 32 256
WIRE 208 256 208 240
WIRE 304 256 304 240
WIRE 400 256 400 240
WIRE 656 272 656 224
WIRE 720 272 656 272
WIRE -336 288 -336 272
WIRE -288 288 -288 224
WIRE -288 288 -336 288
WIRE 720 288 720 272
RECTANGLE Normal 576 312 48 -96 2
SYMBOL res 288 144 R0
SYMATTR InstName R2
SYMATTR Value 1G
SYMBOL voltage -336 176 R0
SYMATTR InstName Vs
SYMATTR Value Sin(0 325 50)
SYMBOL g 160 0 M0
WINDOW 0 -10 10 Right 2
WINDOW 3 -16 104 Right 2
SYMATTR InstName G3
SYMATTR Value 1
SYMBOL res 16 160 R0
SYMATTR InstName Riron
SYMATTR Value 30k
SYMBOL g 448 0 R0
WINDOW 0 13 18 Left 2
WINDOW 3 12 101 Left 2
SYMATTR InstName G4
SYMATTR Value {1/N}
SYMBOL res 688 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rsec
SYMATTR Value 5
SYMBOL g 400 144 M0
WINDOW 0 -10 9 Right 2
WINDOW 3 -15 96 Right 2
SYMATTR InstName G2
SYMATTR Value {1/N}
SYMBOL res 48 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rprimary
SYMATTR Value 70
SYMBOL g 208 144 R0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL res -80 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rs
SYMATTR Value 50
SYMBOL res 704 176 R0
SYMATTR InstName Rload
SYMATTR Value 100
FLAG -336 288 0
FLAG 400 256 0
FLAG 208 256 0
FLAG 208 80 0
FLAG 400 80 0
FLAG 304 256 0
FLAG 720 288 0
TEXT 528 336 Left 2 !.tran 50m
TEXT 192 296 Left 2 !.param N=15 ; turns ratio
TEXT -288 296 Left 2 ;Ac 325
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2919-50.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2919-50.asy)
V1 N004 0 PWL(0 0 10m 12)
C2 0 N010 1000p
R3 N005 N003 1.1K
R4 N001 N008 10K
R2 N003 N001 57.6K
I1 N009 0 PWL(0 0 1 0 1.001 1m 2 1m 2.001 -1m 3 -1m 4 -5m 4.001 -5m 5 5m)
XU1 N002 N004 N006 N008 N010 0 N009 N007 N005 N003 LTC2919-50 ;pnba SEL)Vcc)OUT1)OUT2)_RST)GND)REF)TMR)ADJ2)ADJ1
R5 N001 N010 10K
V3 N002 0 PWL(0 0 5010m 0 5011m 0.9 10010m 0.9 10011m 5)
V2 N001 0 PULSE(2.5 5 0 1000m 1000m 3000m 5000m)
R6 N001 N006 10K
R1 N005 0 10K
C1 0 N007 22n
.tran 15
.lib LTC2919-50.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1500 884
WIRE -416 -64 -672 -64
WIRE -320 -64 -336 -64
WIRE -672 16 -672 -64
WIRE -576 16 -672 16
WIRE -480 16 -576 16
WIRE 336 16 -480 16
WIRE 336 48 336 16
WIRE -48 80 -304 80
WIRE 48 80 32 80
WIRE -672 192 -672 16
WIRE -576 192 -576 16
WIRE -480 192 -480 16
WIRE 336 192 336 128
WIRE 336 192 224 192
WIRE -304 208 -304 80
WIRE -224 208 -304 208
WIRE 224 208 224 192
WIRE 224 208 96 208
WIRE 336 208 336 192
WIRE -352 272 -384 272
WIRE -224 272 -272 272
WIRE 224 272 96 272
WIRE 224 304 224 272
WIRE 336 304 336 288
WIRE 336 304 224 304
WIRE 336 320 336 304
WIRE -480 336 -480 272
WIRE -224 336 -480 336
WIRE 112 336 96 336
WIRE -576 400 -576 272
WIRE -224 400 -576 400
WIRE 208 400 96 400
WIRE 208 416 208 400
WIRE 336 416 336 400
WIRE -672 464 -672 272
WIRE -224 464 -672 464
WIRE 128 464 96 464
WIRE -672 480 -672 464
WIRE 208 512 208 496
WIRE -672 560 -672 544
SYMBOL res -688 176 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL voltage -256 272 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 34 73 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 10m 12)
SYMBOL cap -656 544 R180
WINDOW 0 -34 53 Left 2
WINDOW 3 -66 14 Left 2
SYMATTR InstName C2
SYMATTR Value 1000p
SYMBOL res 320 304 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -64 80 R270
WINDOW 3 -32 56 VBottom 2
WINDOW 0 32 56 VTop 2
SYMATTR Value PWL(0 0 5010m 0 5011m 0.9 10010m 0.9 10011m 5)
SYMATTR InstName V3
SYMBOL current 208 416 R0
SYMATTR InstName I1
SYMATTR Value PWL(0 0 1 0 1.001 1m 2 1m 2.001 -1m 3 -1m 4 -5m 4.001 -5m 5 5m)
SYMBOL LTC2919-50 -64 336 R0
SYMATTR InstName U1
SYMBOL res -592 176 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 320 304 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 1.1K
SYMBOL voltage -432 -64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PULSE(2.5 5 0 1000m 1000m 3000m 5000m)
SYMBOL cap 176 320 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 29 VTop 2
SYMATTR InstName C1
SYMATTR Value 22n
SYMBOL res 320 144 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 57.6K
SYMBOL res -496 176 R0
SYMATTR InstName R6
SYMATTR Value 10K
FLAG 128 464 0
FLAG -384 272 0
FLAG 176 336 0
FLAG 336 416 0
FLAG -320 -64 0
FLAG -672 560 0
FLAG 208 512 0
FLAG 48 80 0
TEXT -96 552 Left 2 !.tran 15
* Z:\home\khalils\Downloads\files\data\raw_asc\2d604922a429_Fig_2-139_CSW.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 5
R1 CONT 0 1
W1 N001 OUT V1 MyCSW
V1 CONT 0 PULSE(-1 1 1m 4m 2m 1m 10m)
R2 OUT 0 100
.model MyCSW CSW(Ron=1 Roff=1T It=0 Ih={TH})
.step param TH list 0.5 -1
.tran 20m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1024 680
WIRE 112 128 -48 128
WIRE 384 128 352 128
WIRE 480 128 384 128
WIRE -48 160 -48 128
WIRE 112 160 112 128
WIRE 352 160 352 128
WIRE 480 160 480 128
WIRE 112 256 112 240
WIRE 112 256 80 256
WIRE -48 272 -48 240
WIRE 352 272 352 240
WIRE 480 272 480 240
WIRE 112 288 112 256
WIRE 112 400 112 368
SYMBOL res 96 272 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL csw 112 160 R0
SYMATTR InstName W1
SYMATTR Value V1 MyCSW
SYMBOL voltage -48 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 464 144 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage 352 144 R0
WINDOW 0 -21 17 Bottom 2
WINDOW 3 101 163 Top 2
WINDOW 123 0 0 Left 0
WINDOW 39 60 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PULSE(-1 1 1m 4m 2m 1m 10m)
FLAG 352 272 0
FLAG 480 272 0
FLAG 384 128 CONT
FLAG 112 400 0
FLAG 80 256 OUT
FLAG -48 272 0
TEXT -48 56 Left 2 !.model MyCSW CSW(Ron=1 Roff=1T It=0 Ih={TH})
TEXT 320 80 Left 2 !.step param TH list 0.5 -1
TEXT -48 16 Left 2 !.tran 20m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3642.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3642.asy)
XU1 N001 IN NC_01 NC_02 IN N002 NC_03 0 LTC3642 ;pnba SW)Vin)Iset)SS)Run)FB)Hyst)GND
V1 IN 0 45
C1 OUT 0 10
R2 N002 0 800K
L1 N001 OUT 150
R1 OUT N002 4.2Meg
Rload OUT 0 100
.tran 2.5m startup
.lib LTC3642.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 80 0 80
WIRE 112 80 96 80
WIRE 352 80 336 80
WIRE 448 80 432 80
WIRE 576 80 448 80
WIRE 656 80 576 80
WIRE 0 96 0 80
WIRE 576 96 576 80
WIRE 656 96 656 80
WIRE 96 176 96 80
WIRE 112 176 96 176
WIRE 448 176 448 160
WIRE 448 176 336 176
WIRE 0 192 0 176
WIRE 448 192 448 176
WIRE 576 192 576 160
WIRE 656 192 656 176
WIRE 448 288 448 272
WIRE 352 368 336 368
SYMBOL res 640 80 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 560 96 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LTC3642 224 224 R0
SYMATTR InstName U1
SYMBOL res 432 176 R0
SYMATTR InstName R2
SYMATTR Value 800K
SYMBOL voltage 0 80 R0
SYMATTR InstName V1
SYMATTR Value 45
SYMBOL ind 336 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150
SYMBOL res 432 64 R0
SYMATTR InstName R1
SYMATTR Value 4.2Meg
FLAG 0 192 0
FLAG 352 368 0
FLAG 448 288 0
FLAG 576 192 0
FLAG 656 192 0
FLAG 0 80 IN
FLAG 656 80 OUT
TEXT 448 360 Left 2 !.tran 2.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-4.2.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-4.2.asy)
V1 IN 0 3.3
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-4.2 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
Rload OUT 0 50
.tran 400u startup
.lib ADP2504-4.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2504-4.2 176 176 R0
SYMATTR InstName U1
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 344 392 Left 2 !.tran 400u startup
TEXT 168 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8031.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8031.asy)
C1 OUT 0 10
V1 IN 0 24
XU1 0 IN N003 NC_01 IN NC_02 N001 N002 OUT N002 NC_03 LTM8031 ;pnba GND)Vin)Adj)Share)Run/SS)Pgood)Rt)BIAS)Out)AUX)Fin
Rload OUT 0 5
R2 N003 0 47.5K
R1 N001 0 44.2K
.tran 1m startup
.lib LTM8031.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 64 -96 64
WIRE 160 64 64 64
WIRE -96 80 -96 64
WIRE 160 80 160 64
WIRE 64 144 64 64
WIRE 80 144 64 144
WIRE 448 144 368 144
WIRE 544 144 448 144
WIRE 448 160 448 144
WIRE 544 160 544 144
WIRE -96 176 -96 160
WIRE -16 208 -32 208
WIRE 80 208 64 208
WIRE 384 208 368 208
WIRE 448 256 448 224
WIRE 544 256 544 240
WIRE 384 272 384 208
WIRE 384 272 368 272
WIRE -16 336 -32 336
WIRE 80 336 64 336
WIRE 224 400 224 384
SYMBOL res 80 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 44.2K
SYMBOL res 528 144 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL cap 432 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LTM8031 224 240 R0
SYMATTR InstName U1
SYMBOL res 80 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 47.5K
SYMBOL voltage -96 64 R0
SYMATTR InstName V1
SYMATTR Value 24
FLAG -96 176 0
FLAG -32 208 0
FLAG -32 336 0
FLAG 224 400 0
FLAG 448 256 0
FLAG 544 256 0
FLAG -96 64 IN
FLAG 544 144 OUT
TEXT 448 352 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2371-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 12
L1 N002 OUT 10 Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
C1 OUT 0 10
R1 OUT N001 10K
XU1 NC_01 IN IN IN N002 OUT N001 0 ADP2371-1.2 IPSM=320m Rt=166666 Rb=333333 C1=9.6p Rc1=100k R3=5.92k Rshort=100MEG PD=1 ;pnba FSEL)SYNC)EN)Vin)SW)FB)PG)PGND
Rload OUT 0 20
.tran 500u startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2371-1.2.asy)
.lib ADP2371-1.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 936 692
WIRE 144 96 16 96
WIRE 176 96 144 96
WIRE 480 96 400 96
WIRE 688 96 560 96
WIRE 16 112 16 96
WIRE 144 176 144 96
WIRE 176 176 144 176
WIRE 432 176 400 176
WIRE 560 176 512 176
WIRE 688 176 688 96
WIRE 688 176 560 176
WIRE 752 176 688 176
WIRE 752 192 752 176
WIRE 16 208 16 192
WIRE 144 336 144 176
WIRE 560 256 560 240
WIRE 560 256 400 256
WIRE 560 272 560 256
WIRE 752 288 752 272
WIRE 176 336 144 336
WIRE 688 336 688 176
WIRE 688 336 400 336
FLAG 16 208 0
FLAG 16 96 IN
FLAG 560 272 0
FLAG 752 176 OUT
FLAG 752 288 0
SYMBOL VOLTAGE 16 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL ind 416 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Ipk=1.84 Rser=0.056 Rpar=942 Cpar=0 mfg="Coilcraft" pn="MSS6132-103"
SYMBOL cap 544 176 R0
WINDOW 0 29 15 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 576 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL ADP2371-1.2 288 208 R0
SYMATTR InstName U1
SYMBOL res 736 176 R0
SYMATTR InstName Rload
SYMATTR Value 20
TEXT 504 384 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1b35d7da1a56_VA-R-DEMO.asc
* Generated by LTspice 26.0.1 for Windows.
R1 b a 500
V1 a 0
D1 0 b EDZV33B
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0 40
.step temp list 25 100
.lib edzv33b.lib
.meas dc Iz_4mA find V(b)*1000 when I(D1)=-4mA
.meas dc Iz_5mA find V(b)*1000 when I(D1)=-5mA
.meas dc Iz_6mA find V(b)*1000 when I(D1)=-6mA
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 -336 -112 -336
WIRE 208 -336 96 -336
WIRE 208 -288 208 -336
WIRE -112 -272 -112 -336
WIRE -112 -144 -112 -192
WIRE 64 -144 -112 -144
WIRE 208 -144 208 -224
WIRE 208 -144 64 -144
WIRE 64 -128 64 -144
SYMBOL zener 224 -224 R180
WINDOW 0 -40 70 Left 2
WINDOW 3 23 -18 Left 2
SYMATTR InstName D1
SYMATTR Value EDZV33B
SYMBOL Misc\\EuropeanResistor 112 -352 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 500
SYMBOL voltage -112 -288 R0
WINDOW 3 24 96 Invisible 2
SYMATTR Value ""
SYMATTR InstName V1
FLAG 64 -128 0
FLAG 208 -336 b
FLAG -112 -336 a
TEXT -224 -72 Left 2 !.dc V1 0 40
TEXT -224 -48 Left 2 !.step temp list  25  100
TEXT 72 -72 Left 2 !.lib edzv33b.lib
TEXT -224 -8 Left 2 !.meas dc Iz_4mA find V(b)*1000 when I(D1)=-4mA\n.meas dc Iz_5mA find V(b)*1000 when I(D1)=-5mA\n.meas dc Iz_6mA find V(b)*1000 when I(D1)=-6mA