* Z:\home\khalils\Downloads\files\data\raw_asc\AD4060.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N002 0 PWL(30n 0 40n 1.8)
V3 CNV 0 PULSE(0 1.8 1u 10n 10n 20n 1u)
V1 N001 0 2.5
VinP1 input+ 0 SINE(1.25 1.25 2k)
Cfilt1 vIN+ 0 1n
Rfilt1 input+ vIN+ 75
Rfilt2 vIN- input- 75
Cfilt2 0 vIN- 1n
VinN1 input- 0 SINE(1.25 1.25 2k 0 0 180)
XU1 vIN+ vIN- 0 N001 CNV N002 VOrti VOrto AD4050 ;pnba IN+)IN-)GND)REF)CNV)_RST)VOrti)VOrto
.tran 0.5m
* Notes:\n \nVOrti: Analog output \nVOrto: "Digital" representation of the input\n \nThe Analog input CNV signal does not actually exist on the AD4060.\nIt is included in this model for simulating convert-start instances.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4060.asy)
.lib AD4050.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1128 680
WIRE 256 -80 256 -112
WIRE -384 48 -560 48
WIRE -288 48 -384 48
WIRE -176 48 -208 48
WIRE -48 48 -176 48
WIRE 256 48 256 0
WIRE -560 80 -560 48
WIRE -176 96 -176 48
WIRE 448 96 384 96
WIRE 640 96 448 96
WIRE 640 128 640 96
WIRE -48 144 -48 48
WIRE 0 144 -48 144
WIRE 64 144 0 144
WIRE 432 144 384 144
WIRE -560 192 -560 160
WIRE -560 192 -608 192
WIRE 432 192 384 192
WIRE -608 208 -608 192
WIRE -560 224 -560 192
WIRE -176 224 -176 160
WIRE -128 224 -176 224
WIRE -128 240 -128 224
WIRE 0 240 -48 240
WIRE 64 240 0 240
WIRE 640 240 640 208
WIRE -176 288 -176 224
WIRE 448 288 384 288
WIRE 448 336 448 288
WIRE 256 368 256 336
WIRE -560 384 -560 304
WIRE -384 384 -560 384
WIRE -288 384 -384 384
WIRE -176 384 -176 352
WIRE -176 384 -208 384
WIRE -48 384 -48 240
WIRE -48 384 -176 384
WIRE 448 448 448 416
FLAG 256 368 0
FLAG 448 448 0
FLAG 640 240 0
FLAG 256 -112 0
FLAG 0 144 vIN+
FLAG 0 240 vIN-
FLAG 432 192 VOrti
FLAG -384 48 input+
FLAG -384 384 input-
FLAG -128 240 0
FLAG -608 208 0
FLAG 432 144 VOrto
FLAG 448 96 CNV
SYMBOL voltage 448 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 16 105 Left 2
SYMATTR Value PWL(30n 0 40n 1.8)
SYMATTR InstName V2
SYMBOL voltage 640 112 R0
WINDOW 0 28 -5 Top 2
WINDOW 3 23 97 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1.8 1u 10n 10n 20n 1u)
SYMBOL voltage 256 16 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL voltage -560 64 M0
WINDOW 0 -29 15 Right 2
WINDOW 3 -20 90 Right 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VinP1
SYMATTR Value SINE(1.25 1.25 2k)
SYMBOL cap -192 96 R0
SYMATTR InstName Cfilt1
SYMATTR Value 1n
SYMBOL res -304 32 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt1
SYMATTR Value 75
SYMBOL res -192 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfilt2
SYMATTR Value 75
SYMBOL cap -192 288 R0
SYMATTR InstName Cfilt2
SYMATTR Value 1n
SYMBOL voltage -560 320 M180
WINDOW 0 84 95 Right 2
WINDOW 3 15 11 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VinN1
SYMATTR Value SINE(1.25 1.25 2k 0 0 180)
SYMBOL AD4060 288 192 R0
SYMATTR InstName U1
TEXT 144 456 Left 2 !.tran 0.5m
TEXT -560 -200 Left 2 ;Notes:\n \nVOrti: Analog output \nVOrto: "Digital" representation of the input\n \nThe Analog input CNV signal does not actually exist on the AD4060.\nIt is included in this model for simulating convert-start instances.