* Z:\home\khalils\Downloads\files\data\raw_asc\08a6291ddf3c_Standard_A-devices.asc
* Generated by LTspice 26.0.1 for Windows.
A1 1 8 8 8 8 8 7 8 BUF
A2 1 8 8 8 8 6 8 8 BUF
A3 1 8 8 8 8 6 7 8 BUF
A4 1 8 8 8 8 8 7 8 SCHMITT
A5 1 8 8 8 8 6 8 8 SCHMITT
A6 1 8 8 8 8 6 7 8 SCHMITT
A7 1 2 8 8 8 8 7 8 SCHMITT
A8 1 2 8 8 8 6 8 8 SCHMITT
A9 1 2 8 8 8 6 7 8 SCHMITT
A10 1 2 3 4 5 6 7 8 AND
A11 1 2 3 4 5 6 7 8 OR
A12 1 2 3 4 5 6 7 8 XOR
A13 1 2 8 8 8 6 7 8 SRFLOP
A14 1 8 3 4 5 6 7 8 DFLOP
A15 1 2 8 8 8 8 7 8 PHASEDET
A16 1 2 8 8 8 8 7 8 MODULATOR
A17 1 2 8 8 8 8 7 8 VARISTOR
* BUF
* BUF
* BUF
* SCHMITT
* SCHMITT
* SCHMITT
* SCHMITT
* SCHMITT
* SCHMITT
* AND
* OR
* XOR
* SRFLOP
* DFLOP
* PHASEDET
* MODULATOR
* VARISTOR
* A-SOURCE NETLISTS:\nA1 1 8 8 8 8 8 7 8 BUF\nA2 1 8 8 8 8 6 8 8 BUF\nA3 1 8 8 8 8 6 7 8 BUF\nA4 1 8 8 8 8 8 7 8 SCHMITT\nA5 1 8 8 8 8 6 8 8 SCHMITT\nA6 1 8 8 8 8 6 7 8 SCHMITT\nA7 1 2 8 8 8 8 7 8 SCHMITT\nA8 1 2 8 8 8 6 8 8 SCHMITT\nA9 1 2 8 8 8 6 7 8 SCHMITT\nA10 1 2 3 4 5 6 7 8 AND\nA11 1 2 3 4 5 6 7 8 OR\nA12 1 2 3 4 5 6 7 8 XOR\nA13 1 2 8 8 8 6 7 8 SRFLOP\nA14 1 8 3 4 5 6 7 8 DFLOP\nA15 1 2 8 8 8 8 7 8 PHASEDET\nA16 1 2 8 8 8 8 7 8 MODULATOR\nA17 1 2 8 8 8 8 7 8 VARISTOR
* LTspice Standard A-Sources (Special Functions)
* NODE ASSIGNMENTS:\nThe first node up through to the fifth are reserved for inputs. For differential inputs the first node is used \nas the noninverting one and the second as the inverting half of the pair. The seventh node is the main \noutput with the sixth node serving as a complementary inverting output if needed. Node 8 serves as the \ngate's common. Unconnected nodes are connected by the netlister to the gate's common (that unlabeled \npin in the corner). This is a flag to the compiler to remove them and is different than tying the node to \ncommon with a wire.
* GENERAL GATE PARAMETERS (defaults shown):\nVhigh=1 Vlow=0 (logic levels); Ref=50% (logic threshold - if set becomes an absolute voltage); \nTd=0 (delay time: should be set to 10ns for shift registers and counters and the like);\nTrise=0 Tfall=Trise OR Tau=0 (transistion time constant) OR Rout=0 and Cout=0;\ntripdt=not specified (sets the maximum step size during logic transistions while between 10% and 90%)
* SCHMITT PARAMETERS:\nVt (threshold) Vh (hysteresis: band = 2*Vh) Note: if not specified Vt defaults to 50% and Vh to 5%
* VARISTOR PARAMETERS:\nRclamp=0 (clamping impedance)
* MODULATOR PARAMETERS:\nmark=? space=? (either specify mark and space frequencies or use a look-up table, not both)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1632 1672
WIRE -320 144 -336 144
WIRE -320 160 -320 176
WIRE -256 144 -240 144
WIRE -320 352 -320 368
WIRE -256 336 -240 336
WIRE -320 336 -336 336
WIRE -320 560 -320 576
WIRE -320 528 -336 528
WIRE -256 512 -240 512
WIRE -256 544 -240 544
WIRE -48 144 -32 144
WIRE -112 160 -112 176
WIRE -112 144 -128 144
WIRE -112 352 -112 368
WIRE -48 336 -32 336
WIRE -112 336 -128 336
WIRE -112 560 -112 576
WIRE -48 512 -32 512
WIRE -48 544 -32 544
WIRE -112 528 -128 528
WIRE 96 176 96 192
WIRE 160 144 176 144
WIRE 96 128 80 128
WIRE 96 160 80 160
WIRE 160 336 176 336
WIRE 96 320 80 320
WIRE 96 352 80 352
WIRE 96 368 96 384
WIRE 96 560 96 576
WIRE 96 512 80 512
WIRE 96 544 80 544
WIRE 160 512 176 512
WIRE 160 544 176 544
WIRE 336 112 288 112
WIRE 336 128 320 128
WIRE 336 144 288 144
WIRE 336 160 320 160
WIRE 336 176 288 176
WIRE 400 128 416 128
WIRE 400 160 416 160
WIRE 352 176 352 192
WIRE 336 304 288 304
WIRE 336 320 320 320
WIRE 336 336 288 336
WIRE 336 352 320 352
WIRE 336 368 288 368
WIRE 352 368 352 384
WIRE 400 320 416 320
WIRE 400 352 416 352
WIRE 336 512 288 512
WIRE 336 528 320 528
WIRE 336 544 288 544
WIRE 336 560 320 560
WIRE 336 576 288 576
WIRE 400 528 432 528
WIRE 416 560 432 560
WIRE 368 576 368 592
WIRE 544 144 528 144
WIRE 544 192 528 192
WIRE 640 144 672 144
WIRE 656 192 672 192
WIRE 544 224 544 240
WIRE 704 416 736 416
WIRE 720 464 736 464
WIRE 544 416 528 416
WIRE 544 464 528 464
WIRE 624 512 624 544
WIRE 624 368 624 336
WIRE 624 544 608 544
WIRE 624 336 608 336
WIRE 544 512 544 528
WIRE 976 160 992 160
WIRE 848 144 832 144
WIRE 848 176 832 176
WIRE 848 208 848 224
WIRE 848 384 832 384
WIRE 848 448 832 448
WIRE 992 416 1008 416
WIRE 848 480 848 496
WIRE 1120 144 1104 144
WIRE 1120 176 1104 176
WIRE 1136 128 1136 112
WIRE 1136 192 1136 208
FLAG -336 144 1
IOPIN -336 144 In
FLAG -240 144 7
IOPIN -240 144 Out
FLAG -320 176 8
FLAG -320 368 8
FLAG -240 336 6
IOPIN -240 336 Out
FLAG -336 336 1
IOPIN -336 336 In
FLAG -320 576 8
FLAG -336 528 1
IOPIN -336 528 In
FLAG -240 512 7
IOPIN -240 512 Out
FLAG -240 544 6
IOPIN -240 544 Out
FLAG -32 144 7
IOPIN -32 144 Out
FLAG -112 176 8
FLAG -128 144 1
IOPIN -128 144 In
FLAG -112 368 8
FLAG -32 336 6
IOPIN -32 336 Out
FLAG -128 336 1
IOPIN -128 336 In
FLAG -112 576 8
FLAG -128 528 1
IOPIN -128 528 In
FLAG -32 512 7
IOPIN -32 512 Out
FLAG -32 544 6
IOPIN -32 544 Out
FLAG 96 192 8
FLAG 176 144 7
IOPIN 176 144 Out
FLAG 80 128 1
IOPIN 80 128 In
FLAG 80 160 2
IOPIN 80 160 In
FLAG 176 336 6
IOPIN 176 336 Out
FLAG 80 320 1
IOPIN 80 320 In
FLAG 80 352 2
IOPIN 80 352 In
FLAG 96 384 8
FLAG 96 576 8
FLAG 80 512 1
IOPIN 80 512 In
FLAG 80 544 2
IOPIN 80 544 In
FLAG 176 512 7
IOPIN 176 512 Out
FLAG 176 544 6
IOPIN 176 544 Out
FLAG 288 112 1
IOPIN 288 112 In
FLAG 320 128 2
IOPIN 320 128 In
FLAG 288 144 3
IOPIN 288 144 In
FLAG 320 160 4
IOPIN 320 160 In
FLAG 288 176 5
IOPIN 288 176 In
FLAG 416 128 7
IOPIN 416 128 Out
FLAG 416 160 6
IOPIN 416 160 Out
FLAG 352 192 8
FLAG 288 304 1
IOPIN 288 304 In
FLAG 320 320 2
IOPIN 320 320 In
FLAG 288 336 3
IOPIN 288 336 In
FLAG 320 352 4
IOPIN 320 352 In
FLAG 288 368 5
IOPIN 288 368 In
FLAG 352 384 8
FLAG 416 320 7
IOPIN 416 320 Out
FLAG 416 352 6
IOPIN 416 352 Out
FLAG 288 512 1
IOPIN 288 512 In
FLAG 320 528 2
IOPIN 320 528 In
FLAG 288 544 3
IOPIN 288 544 In
FLAG 320 560 4
IOPIN 320 560 In
FLAG 288 576 5
IOPIN 288 576 In
FLAG 432 528 7
IOPIN 432 528 Out
FLAG 432 560 6
IOPIN 432 560 Out
FLAG 368 592 8
FLAG 528 144 1
IOPIN 528 144 In
FLAG 528 192 2
IOPIN 528 192 In
FLAG 672 144 7
IOPIN 672 144 Out
FLAG 672 192 6
IOPIN 672 192 Out
FLAG 544 240 8
FLAG 736 416 7
IOPIN 736 416 Out
FLAG 736 464 6
IOPIN 736 464 Out
FLAG 528 416 1
IOPIN 528 416 In
FLAG 528 464 3
IOPIN 528 464 In
FLAG 608 336 4
IOPIN 608 336 In
FLAG 608 544 5
IOPIN 608 544 In
FLAG 544 528 8
FLAG 992 160 7
IOPIN 992 160 Out
FLAG 832 144 1
IOPIN 832 144 In
FLAG 832 176 2
IOPIN 832 176 In
FLAG 848 224 8
FLAG 832 384 1
IOPIN 832 384 In
FLAG 832 448 2
IOPIN 832 448 In
FLAG 1008 416 7
IOPIN 1008 416 Out
FLAG 848 496 8
FLAG 1104 144 1
IOPIN 1104 144 In
FLAG 1104 176 2
IOPIN 1104 176 In
FLAG 1136 112 7
FLAG 1136 208 8
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\buf1 -320 80 R0
SYMATTR InstName A1
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\inv -320 272 R0
SYMATTR InstName A2
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\buf -320 464 R0
SYMATTR InstName A3
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\schmtbuf -112 80 R0
SYMATTR InstName A4
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\schmtinv -112 272 R0
SYMATTR InstName A5
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\schmitt -112 464 R0
SYMATTR InstName A6
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\diffschmtbuf 96 80 R0
SYMATTR InstName A7
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\diffschmtinv 96 272 R0
SYMATTR InstName A8
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\diffschmitt 96 464 R0
SYMATTR InstName A9
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\and 368 80 R0
SYMATTR InstName A10
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\or 368 272 R0
SYMATTR InstName A11
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\xor 384 480 R0
SYMATTR InstName A12
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\srflop 592 96 R0
SYMATTR InstName A13
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\dflop 624 368 R0
SYMATTR InstName A14
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\phidet 880 160 R0
SYMATTR InstName A15
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\SpecialFunctions\modulate 848 384 R0
SYMATTR InstName A16
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\SpecialFunctions\varistor 1152 96 R0
SYMATTR InstName A17
TEXT -320 56 Left 0 ;BUF
TEXT -320 240 Left 0 ;BUF
TEXT -320 440 Left 0 ;BUF
TEXT -112 56 Left 0 ;SCHMITT
TEXT -112 248 Left 0 ;SCHMITT
TEXT -112 440 Left 0 ;SCHMITT
TEXT 96 56 Left 0 ;SCHMITT
TEXT 96 248 Left 0 ;SCHMITT
TEXT 96 440 Left 0 ;SCHMITT
TEXT 336 56 Left 0 ;AND
TEXT 336 248 Left 0 ;OR
TEXT 336 440 Left 0 ;XOR
TEXT 544 56 Left 0 ;SRFLOP
TEXT 544 296 Left 0 ;DFLOP
TEXT 848 56 Left 0 ;PHASEDET
TEXT 848 296 Left 0 ;MODULATOR
TEXT 1064 56 Left 0 ;VARISTOR
TEXT -368 656 Left 0 ;A-SOURCE NETLISTS:\nA1   1 8 8 8 8 8 7 8 BUF\nA2   1 8 8 8 8 6 8 8 BUF\nA3   1 8 8 8 8 6 7 8 BUF\nA4   1 8 8 8 8 8 7 8 SCHMITT\nA5   1 8 8 8 8 6 8 8 SCHMITT\nA6   1 8 8 8 8 6 7 8 SCHMITT\nA7   1 2 8 8 8 8 7 8 SCHMITT\nA8   1 2 8 8 8 6 8 8 SCHMITT\nA9   1 2 8 8 8 6 7 8 SCHMITT\nA10 1 2 3 4 5 6 7 8 AND\nA11 1 2 3 4 5 6 7 8 OR\nA12 1 2 3 4 5 6 7 8 XOR\nA13 1 2 8 8 8 6 7 8 SRFLOP\nA14 1 8 3 4 5 6 7 8 DFLOP\nA15 1 2 8 8 8 8 7 8 PHASEDET\nA16 1 2 8 8 8 8 7 8 MODULATOR\nA17 1 2 8 8 8 8 7 8 VARISTOR
TEXT 408 -16 Center 0 ;LTspice Standard A-Sources (Special Functions)
TEXT 48 648 Left 0 ;NODE ASSIGNMENTS:\nThe first node up through to the fifth are reserved for inputs.  For differential inputs the first node is used \nas the noninverting one and the second as the inverting half of the pair.  The seventh node is the main \noutput with the sixth node serving as a complementary inverting output if needed.  Node 8 serves as the \ngate's common.  Unconnected nodes are connected by the netlister to the gate's common (that unlabeled \npin in the corner).  This is a flag to the compiler to remove them and is different than tying the node to \ncommon with a wire.
TEXT 48 848 Left 0 ;GENERAL GATE PARAMETERS (defaults shown):\nVhigh=1 Vlow=0 (logic levels); Ref=50% (logic threshold - if set becomes an absolute voltage); \nTd=0 (delay time: should be set to 10ns for shift registers and counters and the like);\nTrise=0 Tfall=Trise OR Tau=0 (transistion time constant) OR Rout=0 and Cout=0;\ntripdt=not specified (sets the maximum step size during logic transistions while between 10% and 90%)
TEXT 48 992 Left 0 ;SCHMITT PARAMETERS:\nVt (threshold) Vh (hysteresis: band = 2*Vh)  Note: if not specified Vt defaults to 50% and Vh to 5%
TEXT 48 1120 Left 0 ;VARISTOR PARAMETERS:\nRclamp=0 (clamping impedance)
TEXT 48 1056 Left 0 ;MODULATOR PARAMETERS:\nmark=? space=? (either specify mark and space frequencies or use a look-up table, not both)