* Z:\home\khalils\Downloads\files\data\raw_asc\8f2692214d1f_PHAReduced.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU5 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT1715.asy)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6248.asy)
V4 N002 0 3.3
C1 input 0 90p
R1 N005 input 51
R14 N006 0 10.2k
XU1 outp N004 N006 N005 N001 LTC6247 ;pnba 1)4)3)2)7
R16 input 0 100k
C2 outp N005 220pF
V5 N003 0 -.013
I1 input 0 PWL file=/Users/liambranch/Desktop/Monte-Python/monte_carlo_input1ch1_07_12_2023.txt
V1 N001 0 2.5
V2 0 N004 2.5
XU5 N003 input N001 N004 N002 0 compOut LT1715 ;pnba In+)In-)Vcc)Vee)VS+)GND)OUT
R2 outp N005 10.2k
.tran 0 10u 0 0.001u
.lib LT1715.sub
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2500 680
WIRE 272 -512 -368 -512
WIRE 1056 -512 304 -512
WIRE 272 -400 272 -512
WIRE 304 -400 304 -512
WIRE -80 -368 -160 -368
WIRE 256 -368 -80 -368
WIRE 560 -352 336 -352
WIRE 256 -336 64 -336
WIRE 272 -288 272 -304
WIRE 272 -288 -256 -288
WIRE -80 -272 -80 -368
WIRE 64 -272 64 -336
WIRE 512 -256 448 -256
WIRE 640 -256 592 -256
WIRE -80 -144 -80 -192
WIRE 64 -144 64 -192
WIRE 64 -144 -80 -144
WIRE 304 -144 304 -304
WIRE 304 -144 64 -144
WIRE 448 -128 448 -256
WIRE 512 -128 448 -128
WIRE 640 -128 640 -256
WIRE 640 -128 576 -128
WIRE 304 -112 304 -144
WIRE 1056 -96 1056 -512
WIRE -368 -80 -368 -512
WIRE 528 -80 -368 -80
WIRE 528 -16 528 -80
WIRE -368 0 -368 -80
WIRE -160 0 -160 -368
WIRE 0 0 -160 0
WIRE 48 0 0 0
WIRE 80 0 48 0
WIRE 448 0 448 -128
WIRE 448 0 160 0
WIRE 496 0 448 0
WIRE 640 16 640 -128
WIRE 640 16 560 16
WIRE 720 16 640 16
WIRE 496 32 400 32
WIRE 48 96 48 0
WIRE 400 96 400 32
WIRE -368 128 -368 80
WIRE -368 128 -464 128
WIRE -464 160 -464 128
WIRE -160 160 -160 0
WIRE -368 192 -368 128
WIRE -160 304 -160 240
WIRE 48 304 48 160
WIRE 48 304 -160 304
WIRE 400 304 400 176
WIRE 400 304 48 304
WIRE 1056 304 1056 -16
WIRE 1056 304 400 304
WIRE 400 336 400 304
WIRE -368 400 -368 272
WIRE -256 400 -256 -288
WIRE -256 400 -368 400
WIRE 528 400 528 48
WIRE 528 400 -256 400
SYMBOL cap 576 -144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 220pF
SYMBOL LTC6248 528 16 R0
SYMATTR InstName U1
SYMBOL res -96 -288 R0
SYMATTR InstName R16
SYMATTR Value 100k
SYMBOL res 176 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 51
SYMBOL voltage 64 -288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value -.013
SYMBOL voltage -368 176 R0
SYMATTR InstName V2
SYMATTR Value 2.5
SYMBOL res 608 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10.2k
SYMBOL LT1715 288 -352 R0
SYMATTR InstName U5
SYMBOL voltage -368 -16 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 384 80 R0
SYMATTR InstName R14
SYMATTR Value 10.2k
SYMBOL cap 32 96 R0
SYMATTR InstName C1
SYMATTR Value 90p
SYMBOL current -160 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PWL file=/Users/liambranch/Desktop/Monte-Python/monte_carlo_input1ch1_07_12_2023.txt
SYMBOL voltage 1056 -112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value 3.3
FLAG 400 336 0
FLAG -464 160 0
FLAG 0 0 input
FLAG 304 -112 0
FLAG 560 -352 compOut
FLAG 720 16 outp
TEXT 1104 -376 Left 2 !.tran 0 10u 0 0.001u