Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\1c5525808c1c_6104.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N005 MP_01 MP_02 0 N002 N003 N004 N001 LTC6104 ;pnba OUT)))V-)INB+)INB-)INA-)INA+
R1 N002 N001 50m
R2 N003 N001 100
R3 N004 N002 100
V1 N002 0 12
I1 0 N001 sine(0 2 100)
V2 N006 0 2
R4 N005 N006 1K
.tran 30m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6104.asy)
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 -96 -64 -96
WIRE 80 -96 32 -96
WIRE 176 -96 80 -96
WIRE 192 -96 176 -96
WIRE 368 -96 272 -96
WIRE 448 -96 368 -96
WIRE 448 -80 448 -96
WIRE 176 -48 176 -96
WIRE 272 -48 272 -96
WIRE 448 16 448 0
WIRE 176 48 176 32
WIRE 272 48 272 32
WIRE 176 64 272 48
WIRE 272 64 176 48
WIRE 80 80 80 -96
WIRE 176 80 176 64
WIRE 272 80 272 64
WIRE 368 80 368 -96
WIRE 496 208 416 208
WIRE 496 224 496 208
WIRE 496 320 496 304
WIRE 224 352 224 336
WIRE 496 416 496 400
FLAG 224 352 0
FLAG 448 16 0
FLAG -64 -96 0
FLAG 496 416 0
SYMBOL opamps\\LTC6104 224 208 R0
SYMATTR InstName U1
SYMBOL res 288 -112 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 50m
SYMBOL res 160 48 M180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL res 256 48 M180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R3
SYMATTR Value 100
SYMBOL voltage 448 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL current -48 -96 M90
WINDOW 0 -32 40 VBottom 0
WINDOW 3 32 40 VTop 0
SYMATTR InstName I1
SYMATTR Value sine(0 2 100)
SYMBOL voltage 496 304 R0
SYMATTR InstName V2
SYMATTR Value 2
SYMBOL res 480 208 R0
SYMATTR InstName R4
SYMATTR Value 1K
TEXT 616 384 Left 0 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\2eaa6026e19b_1328.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
XU1 N001 N003 N004 0 N005 +V 0 N002 LT1328 ;pnba IN)FILT)FILT_SW)GND)DATA)VCC)MODE)Vbias
C1 N003 N004 10n Rser=.1
C2 N003 0 330p Rser=.1
C3 0 N002 1000p
I1 N001 0 PULSE(7u 100u 0 10n 10n .5u 1u)
.tran 10u
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1328.asy)
.lib LT1328.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -528 -144 -624 -144
WIRE -208 -144 -448 -144
WIRE 64 -144 48 -144
WIRE 144 -144 128 -144
WIRE -272 -80 -352 -80
WIRE -208 -80 -272 -80
WIRE 80 -80 48 -80
WIRE -352 -64 -352 -80
WIRE -208 -16 -272 -16
WIRE 80 -16 48 -16
WIRE -528 0 -528 -16
WIRE -352 16 -352 0
WIRE -208 48 -240 48
WIRE 80 48 48 48
WIRE -528 96 -528 80
FLAG -528 96 0
FLAG -528 -16 +V
FLAG -240 48 0
FLAG 80 -16 +V
FLAG -624 -144 0
FLAG -352 16 0
FLAG 144 -144 0
FLAG 80 -80 0
SYMBOL voltage -528 -16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT1328 -80 -48 R0
SYMATTR InstName U1
SYMBOL cap -288 -80 R0
WINDOW 0 27 13 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMATTR SpiceLine Rser=.1
SYMBOL cap -368 -64 R0
WINDOW 0 27 13 Left 2
WINDOW 3 29 51 Left 2
SYMATTR InstName C2
SYMATTR Value 330p
SYMATTR SpiceLine Rser=.1
SYMBOL cap 128 -160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1000p
SYMBOL current -448 -144 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2
WINDOW 123 32 40 VTop 2
WINDOW 39 32 40 VTop 2
SYMATTR InstName I1
SYMATTR Value PULSE(7u 100u 0 10n 10n .5u 1u)
TEXT 80 88 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\0c27a2b21502_final_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout Vin 0 0 NMOS l=0.72u w=3.57u
M2 Vout Vout Vdd Vdd PMOS l=0.72u w=5.50u
V1 Vin 0 SINE(0.75 1m 1k) AC 1
V2 Vdd 0 1.8
C1 Vout 0 1p
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.options plotwinsize=0
.include tsmc180.txt
* .op
* .tf V(Vout) V1
* .tran 5m
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -80 240 -144
WIRE 352 -80 240 -80
WIRE 240 -32 240 -80
WIRE 192 -16 160 -16
WIRE 352 16 352 -80
WIRE 352 16 240 16
WIRE 160 80 160 -16
WIRE 240 80 240 64
WIRE 240 80 160 80
WIRE 240 112 240 80
WIRE 512 112 240 112
WIRE 576 112 512 112
WIRE 240 144 240 112
WIRE 512 160 512 112
WIRE 352 192 240 192
WIRE 192 224 80 224
WIRE -256 240 -256 192
WIRE -128 240 -128 192
WIRE 240 288 240 240
WIRE 352 288 352 192
WIRE 352 288 240 288
WIRE 512 288 512 224
WIRE 240 336 240 288
WIRE -256 400 -256 320
WIRE -128 400 -128 320
FLAG -256 400 0
FLAG -128 400 0
FLAG -256 192 Vin
FLAG -128 192 Vdd
FLAG 240 336 0
FLAG 512 288 0
FLAG 80 224 Vin
FLAG 576 112 Vout
IOPIN 576 112 Out
FLAG 240 -144 Vdd
SYMBOL nmos4 192 144 R0
WINDOW 123 66 165 Left 2
SYMATTR Value2 l=0.72u w=3.57u
SYMATTR InstName M1
SYMBOL pmos4 192 64 M180
WINDOW 123 56 4 Left 2
SYMATTR Value2 l=0.72u w=5.50u
SYMATTR InstName M2
SYMBOL voltage -256 224 R0
WINDOW 3 -257 105 Left 2
WINDOW 123 -137 145 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0.75 1m 1k)
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL voltage -128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL cap 496 160 R0
SYMATTR InstName C1
SYMATTR Value 1p
TEXT -328 -136 Left 2 !.options plotwinsize=0
TEXT -328 -104 Left 2 !.include tsmc180.txt
TEXT -328 -80 Left 2 ;.op
TEXT -328 -48 Left 2 ;.tf V(Vout) V1
TEXT -328 -16 Left 2 ;.tran 5m
TEXT -328 16 Left 2 !.ac dec 10 10 1gig
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1740-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1740-1.8.asy)
XU1 IN OUT IN N002 OUT N001 MP_01 0 ADP1740-1.8 ;pnba Vin)Sense)EN)SS)Vout)PG))GND
V1 IN 0 2.1
C2 N002 0 10n
C1 OUT 0 4.7 Rser=3m
R1 IN N001 100k
Rload OUT 0 0.9
.tran 10m startup
.lib ADP1740-1.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE -112 32 -128 32
WIRE -16 32 -112 32
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 416 32 368 32
WIRE 496 32 416 32
WIRE 528 32 496 32
WIRE -128 48 -128 32
WIRE -16 48 -16 32
WIRE 416 48 416 32
WIRE 528 48 528 32
WIRE 80 96 80 32
WIRE 96 96 80 96
WIRE -128 144 -128 128
WIRE 416 144 416 112
WIRE 528 144 528 128
WIRE -16 176 -16 128
WIRE 96 176 -16 176
WIRE 16 240 0 240
WIRE 96 240 80 240
WIRE 368 240 368 32
WIRE 368 240 352 240
WIRE 224 304 224 288
SYMBOL ADP1740-1.8 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2.1
SYMBOL res -32 32 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.9
SYMBOL cap 400 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL cap 80 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
FLAG 224 304 0
FLAG -128 144 0
FLAG 0 240 0
FLAG -112 32 IN
FLAG 528 144 0
FLAG 416 144 0
FLAG 496 32 OUT
TEXT 128 352 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1765.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1765.asy)
C3 N002 0 1
R1 OUT 0 .6
R2 N001 IN 50K
C4 OUT 0 22
C2 N003 0 10n
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1765 ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
R3 0 N005 10K
V1 IN 0 1.8
C1 N004 0 1
.tran 2m startup
.lib ADP1765.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 464 320 448 320
WIRE 224 384 224 368
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL voltage -128 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL res 464 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL ADP1765 224 176 R0
SYMATTR InstName U1
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 22
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 320 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 504 392 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2bf6d43efa56_diode_with_table.asc
* Generated by LTspice 26.0.1 for Windows.
* Diode With Table
R1 N002 0 10
G1 N001 N002 N001 N002 table(-100,10m,0,0, 1,1, 2, 50)
V1 N001 0 SINE(0 50 50)
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 96 -240 96
WIRE 32 128 32 96
WIRE 32 128 -16 128
WIRE 32 144 32 128
WIRE -16 160 -16 128
WIRE -16 240 -16 208
WIRE 32 240 32 224
WIRE 32 240 -16 240
WIRE -240 256 -240 96
WIRE 32 288 32 240
WIRE -240 416 -240 336
WIRE 32 416 32 368
WIRE 32 416 -240 416
WIRE -240 432 -240 416
SYMBOL res 16 272 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL g2 32 240 M180
SYMATTR InstName G1
SYMATTR Value table(-100,10m,0,0, 1,1, 2, 50)
SYMBOL voltage -240 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50 50)
FLAG -240 432 0
TEXT -232 32 Left 0 !.tran 100m
TEXT -232 -8 Left 0 ;Diode With Table
* Z:\home\khalils\Downloads\files\data\raw_asc\ed1d7c0920a6_TRR-6.asc
* Generated by LTspice 26.0.1 for Windows.
V1 a 0 PULSE(30 -30 1u 5n 5n 9u 20u) Rser=10
R1 b 0 300
D1 a b RB060M-60
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 6u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 128 -208 128
WIRE -112 128 -176 128
WIRE 16 128 -48 128
WIRE 32 128 16 128
WIRE -208 176 -208 128
WIRE 32 176 32 128
WIRE -208 304 -208 256
WIRE -80 304 -208 304
WIRE 32 304 32 256
WIRE 32 304 -80 304
WIRE -80 320 -80 304
SYMBOL Misc\\EuropeanResistor 16 160 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -208 160 R0
WINDOW 3 10 105 Invisible 2
WINDOW 123 0 0 Left 2
SYMATTR Value PULSE(30 -30 1u 5n 5n 9u 20u)
SYMATTR SpiceLine Rser=10
SYMATTR InstName V1
SYMBOL schottky -112 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RB060M-60
SYMATTR Description Diode
SYMATTR Type diode
FLAG -80 320 0
FLAG -176 128 a
FLAG 16 128 b
TEXT -208 320 Left 2 !.tran 6u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1764-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1764-1.2.asy)
R1 OUT 0 .6
C2 N003 0 10n
C4 OUT 0 10
V1 IN 0 1.5
C3 N002 0 1
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1764 Radj=8026.76 ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
C1 N004 0 1
R2 N001 IN 50K
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL ADP1764-1.2 224 176 R0
SYMATTR InstName U1
SYMBOL voltage -128 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.5
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 504 280 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG721.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG721.asy)
VS N001 0 3
XU2 N003 N002 N001 0 +V ADG721 ;pnba IN)D)S)GND)Vdd
V1 +V 0 5
C1 N002 0 35p
V4 N003 0 PULSE(0 3 0 10n 10n 980n 2u)
R1 N002 0 300
.tran 10u
.lib ADG721.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -240 -16 -288 -16
WIRE 0 -16 -48 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -240 48 -368 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 35p
SYMBOL ADG721 -144 32 R0
SYMATTR InstName U2
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V4
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
TEXT -536 200 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\1e7122ded42d_circnand.asc
* Generated by LTspice 26.0.1 for Windows.
MNMODA Out A N001 Vss NMOD1 l=1u w=50u
CL Out 0 1p
MPMODB Vdd B Out Vdd PMOD1 l=1u w=50u
MPMODA Vdd A Out Vdd PMOD1 l=1u w=50u
MNMODB N001 B Vss Vss NMOD1 l=1u w=100u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model NMOD1 nmos (KP=200U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=0.7)
.model PMOD1 pmos (KP=100U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=-0.7)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 336 -112 336 -176
WIRE 512 -112 336 -112
WIRE 288 -96 224 -96
WIRE 336 -96 336 -112
WIRE 336 -96 288 -96
WIRE 448 -96 336 -96
WIRE 288 -48 288 -96
WIRE 288 -48 224 -48
WIRE 512 -48 512 -112
WIRE 512 -48 448 -48
WIRE 176 -16 112 -16
WIRE 400 -16 368 -16
WIRE 224 64 224 0
WIRE 320 64 224 64
WIRE 448 64 448 0
WIRE 448 64 320 64
WIRE 560 64 448 64
WIRE 320 112 320 64
WIRE 352 160 320 160
WIRE 272 192 224 192
WIRE 320 240 320 208
WIRE 352 288 352 160
WIRE 352 288 320 288
WIRE 272 320 240 320
WIRE 320 352 320 336
WIRE 352 352 352 288
WIRE 352 352 320 352
WIRE 320 400 320 352
IOPIN 112 -16 In
IOPIN 224 192 In
IOPIN 368 -16 In
IOPIN 240 320 In
IOPIN 560 64 Out
SYMBOL pmos4 400 -96 R0
WINDOW 0 5 -61 Left 2
WINDOW 3 10 -34 Left 2
SYMATTR InstName PMODB
SYMATTR Value PMOD1
SYMATTR Value2 l=1u w=50u
SYMBOL nmos4 272 112 R0
WINDOW 0 -191 18 Left 2
WINDOW 3 -193 48 Left 2
SYMATTR InstName NMODA
SYMATTR Value NMOD1
SYMATTR Value2 l=1u w=50u
SYMBOL pmos4 176 -96 R0
WINDOW 0 -60 -47 Left 2
WINDOW 3 -59 -13 Left 2
SYMATTR InstName PMODA
SYMATTR Value PMOD1
SYMATTR Value2 l=1u w=50u
SYMBOL nmos4 272 240 R0
WINDOW 0 -178 22 Left 2
WINDOW 3 -172 51 Left 2
SYMATTR InstName NMODB
SYMATTR Value NMOD1
SYMATTR Value2 l=1u w=100u
FLAG 112 -16 A
FLAG 224 192 A
FLAG 368 -16 B
FLAG 240 320 B
FLAG 560 64 Out
FLAG 320 400 Vss
FLAG 336 -176 Vdd
TEXT -200 464 Left 2 !.model NMOD1 nmos (KP=200U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=0.7)
TEXT -200 496 Left 2 !.model PMOD1 pmos (KP=100U GAMMA=0.9 phi=0.6 lambda=0.02 VTO=-0.7)
TEXT 448 360 Left 2 !CL Out 0 1p
* Z:\home\khalils\Downloads\files\data\raw_asc\5bba5cf74393_1006A.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain 100 Amplifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1006A.asy)
R2 N001 0 1K
R3 OUT 0 660
R1 OUT N001 99K
V1 +V 0 5
V3 IN 0 SINE(5m 1m 1K)
XU1 IN N001 +V 0 OUT LT1006 ;pnba In+)In-)V+)V-)OUT
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 112 16 112
WIRE 128 112 112 112
WIRE 160 112 128 112
WIRE 272 112 240 112
WIRE 192 208 192 192
WIRE 128 224 128 112
WIRE 160 224 128 224
WIRE -80 240 -80 224
WIRE 272 240 272 112
WIRE 272 240 224 240
WIRE 336 240 272 240
WIRE 160 256 48 256
WIRE 336 256 336 240
WIRE 48 272 48 256
WIRE 192 288 192 272
WIRE -80 336 -80 320
WIRE 336 352 336 336
WIRE 48 368 48 352
SYMBOL res 256 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 99K
SYMBOL opamps\\LT1006A 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -80 224 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 48 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(5m 1m 1K)
SYMBOL res 128 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 320 240 R0
SYMATTR InstName R3
SYMATTR Value 660
FLAG -80 336 0
FLAG 192 192 +V
FLAG -80 224 +V
FLAG 16 112 0
FLAG 48 368 0
FLAG 192 288 0
FLAG 336 352 0
FLAG 336 240 OUT
FLAG 48 256 IN
TEXT 288 400 Left 2 !.tran 3m
TEXT 152 56 Bottom 2 ;Gain 100 Amplifier
* Z:\tmp\asc_dec_bjh7r6w2\1468a5443eb8_dff1_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
E1 buf Vss D Vss 1
C2 hold Vss 500p
S6 hold N002 clk tp switch
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 6308 700
WIRE 1472 -736 1456 -736
WIRE 1488 -736 1472 -736
WIRE 1472 -720 1472 -736
WIRE 720 -704 688 -704
WIRE 800 -704 720 -704
WIRE 960 -704 880 -704
WIRE 1200 -704 1104 -704
WIRE 1344 -704 1280 -704
WIRE 1440 -704 1344 -704
WIRE 1552 -704 1504 -704
WIRE 1104 -688 1104 -704
WIRE 1344 -672 1344 -704
WIRE 1472 -672 1472 -688
WIRE 1472 -672 1456 -672
WIRE 1488 -672 1472 -672
WIRE 688 -656 688 -704
WIRE 1472 -656 1456 -672
WIRE 1472 -656 1488 -672
WIRE 640 -640 624 -640
WIRE 864 -608 864 -656
WIRE 1104 -592 1104 -608
WIRE 1104 -592 1056 -592
WIRE 1104 -576 1104 -592
WIRE 1104 -576 1088 -576
WIRE 1120 -576 1104 -576
WIRE 1344 -576 1344 -608
WIRE 1344 -576 1328 -576
WIRE 1360 -576 1344 -576
WIRE 640 -560 640 -592
WIRE 688 -560 688 -576
WIRE 688 -560 640 -560
WIRE 1104 -560 1088 -576
WIRE 1104 -560 1120 -576
WIRE 1344 -560 1328 -576
WIRE 1344 -560 1360 -576
WIRE 688 -544 688 -560
WIRE 688 -544 672 -544
WIRE 704 -544 688 -544
WIRE 688 -528 672 -544
WIRE 688 -528 704 -544
SYMBOL e 688 -672 R0
WINDOW 0 39 41 Left 0
WINDOW 3 38 68 Left 0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL cap 1328 -672 R0
SYMATTR InstName C2
SYMATTR Value 500p
SYMBOL sw 1296 -704 M270
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switch
SYMATTR InstName S6
FLAG 624 -640 D
FLAG 864 -608 Clk
FLAG 1344 -704 hold
FLAG 688 -544 Vss
FLAG 1344 -576 Vss
FLAG 816 -656 tp
FLAG 1264 -656 tp
FLAG 1216 -656 clk
FLAG 720 -704 buf
FLAG 1104 -576 Vss
FLAG 1472 -736 Vdd
FLAG 1472 -672 Vss
* Z:\home\khalils\Downloads\files\data\raw_asc\2eb450a2315e_Fig_8-5_LTC6244_AC.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6244.asy)
V1 +V 0 5
V3 IN 0 AC 1
R1 N001 0 1k
V2 -V 0 -5
XU1 IN N001 +V -V OUT LTC6244 ;pnba IN+)IN-)VCC)VEE)OUT
R2 N001 OUT 100K
.ac dec 100 0.1 1000Meg
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 240 256 240
WIRE 432 240 384 240
WIRE 256 336 256 240
WIRE 304 336 256 336
WIRE 432 352 432 240
WIRE 432 352 368 352
WIRE 464 352 432 352
WIRE 304 368 144 368
WIRE -32 400 -32 368
WIRE 64 400 64 368
WIRE 144 400 144 368
WIRE 256 400 256 336
WIRE 336 400 336 384
WIRE -32 512 -32 480
WIRE 64 512 64 480
WIRE 144 512 144 480
WIRE 256 512 256 480
SYMBOL voltage -32 384 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 288 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 240 384 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 64 384 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL LTC6244 336 352 R0
SYMATTR InstName U1
SYMBOL voltage 144 384 R0
WINDOW 0 15 11 Left 2
WINDOW 3 11 105 Left 2
WINDOW 123 17 108 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value ""
SYMATTR Value2 AC 1
FLAG -32 512 0
FLAG 64 512 0
FLAG -32 368 +V
FLAG 144 512 0
FLAG 144 368 IN
FLAG 464 352 OUT
FLAG 336 320 +V
FLAG 64 368 -V
FLAG 336 400 -V
FLAG 256 512 0
TEXT -72 272 Left 2 !.ac dec 100 0.1 1000Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\5c6e9c62f096_pull_out_stage.asc
* Generated by LTspice 26.0.1 for Windows.
* Amplifier output Stages
V2 N002 0 SINE(0 6 1k)
V1 V+ 0 5
Q1 N003 N002 2+ 0 PNP
V3 V- 0 -5
R1 2+ 0 2.2k
R3 V+ N001 100
Q2 N001 N002 2+ 0 NPN
R2 N003 V- 100
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 -384 192 -416
WIRE -352 -288 -352 -304
WIRE -352 -288 -384 -288
WIRE -208 -288 -208 -304
WIRE -208 -288 -240 -288
WIRE 192 -272 192 -304
WIRE -352 -256 -352 -288
WIRE -208 -256 -208 -288
WIRE 128 -224 96 -224
WIRE -352 -160 -352 -176
WIRE -208 -160 -208 -176
WIRE 96 -144 96 -224
WIRE 96 -144 -48 -144
WIRE 192 -144 192 -176
WIRE 320 -144 192 -144
WIRE 352 -144 320 -144
WIRE -48 -112 -48 -144
WIRE 192 -112 192 -144
WIRE 320 -112 320 -144
WIRE 96 -64 96 -144
WIRE 128 -64 96 -64
WIRE -48 0 -48 -32
WIRE 320 0 320 -32
WIRE 192 16 192 -16
WIRE 192 144 192 96
IOPIN -384 -288 In
IOPIN 352 -144 In
IOPIN -240 -288 In
SYMBOL res 176 0 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL voltage -48 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 6 1k)
SYMBOL voltage -352 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL npn 128 -272 R0
SYMATTR InstName Q2
SYMBOL pnp 128 -16 M180
SYMATTR InstName Q1
SYMBOL voltage -208 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -5
SYMBOL res 304 -128 R0
SYMATTR InstName R1
SYMATTR Value 2.2k
SYMBOL res 176 -400 R0
SYMATTR InstName R3
SYMATTR Value 100
FLAG 320 0 0
FLAG -352 -160 0
FLAG -352 -304 Vp
FLAG 192 -416 Vp
FLAG -48 0 0
FLAG -384 -288 V+
FLAG 352 -144 2+
FLAG -208 -160 0
FLAG -208 -304 Vn
FLAG -240 -288 V-
FLAG 192 144 Vn
TEXT -232 152 Left 2 !.tran 10m
TEXT 56 -504 Left 2 ;Amplifier output Stages