Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2d613338685e_1224.asc
* Generated by LTspice 26.0.1 for Windows.
* 1MHz, 2nd Order Butterworth Filter
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1224.asy)
C3 0 N001 500p
V2 -V 0 -15
R3 N001 IN 619
C2 OUT N002 100p
V3 IN 0 ac 1
R2 N002 N001 825
XU1 0 N002 +V -V OUT LT1224 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
R1 OUT N001 619
.ac oct 10 1K 100Meg
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -208 48 -208 32
WIRE -112 48 -112 32
WIRE 128 64 96 64
WIRE 352 64 208 64
WIRE 256 112 224 112
WIRE 352 112 352 64
WIRE 352 112 320 112
WIRE -208 144 -208 128
WIRE -112 144 -112 128
WIRE 288 208 288 192
WIRE 0 224 -128 224
WIRE 96 224 96 64
WIRE 96 224 80 224
WIRE 128 224 96 224
WIRE 224 224 224 112
WIRE 224 224 208 224
WIRE 256 224 224 224
WIRE -128 240 -128 224
WIRE 352 240 352 112
WIRE 352 240 320 240
WIRE 384 240 352 240
WIRE 96 256 96 224
WIRE 256 256 224 256
WIRE 288 288 288 272
WIRE 96 336 96 320
WIRE -128 352 -128 320
SYMBOL voltage -128 224 R0
SYMATTR InstName V3
SYMATTR Value ac 1
SYMBOL cap 320 96 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL voltage -112 32 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 96 208 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R3
SYMATTR Value 619
SYMBOL res 224 48 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 619
SYMBOL opamps\\LT1224 288 176 R0
SYMATTR InstName U1
SYMBOL cap 80 320 M180
WINDOW 0 24 64 Left 0
WINDOW 3 24 8 Left 0
SYMATTR InstName C3
SYMATTR Value 500p
SYMBOL res 224 208 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 825
SYMBOL voltage -208 32 R0
SYMATTR InstName V2
SYMATTR Value -15
FLAG -112 144 0
FLAG 288 192 +V
FLAG -112 32 +V
FLAG 288 288 -V
FLAG -208 144 0
FLAG -208 32 -V
FLAG 96 336 0
FLAG 224 256 0
FLAG -128 352 0
FLAG 384 240 OUT
FLAG -128 224 IN
TEXT 310 378 Left 0 !.ac oct 10 1K 100Meg
TEXT 224 -8 Bottom 0 ;1MHz, 2nd Order Butterworth Filter
* Z:\home\khalils\Downloads\files\data\raw_asc\SoftDiodeRecovery.asc
* Generated by LTspice 26.0.1 for Windows.
* This example shows the use of dQ/dt damping parameter Vp to control diode soft recovery.\n \nSee K.J. Teng and S. Pan: 'Modified charge-control equation for simulation of diode reverse recovery',\nElectronics Letters, 15th February 1996 Vol. 32 No. 4
V3 N001 0 PULSE(10 -10 .5u 10n 10n 20u 40u)
R1 N001 N002 1
D3 N002 0 x
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 60u
.model X D(Rs=0 Is=1e-10 tt=3u Vp={Vp} Cjo=10n)
.step param Vp list 0 .2 .4 .6 .8 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1796 1732
WIRE -496 832 -736 832
WIRE -208 832 -416 832
WIRE -736 848 -736 832
WIRE -208 848 -208 832
WIRE -208 928 -208 912
WIRE -736 944 -736 928
SYMBOL diode -224 848 R0
SYMATTR InstName D3
SYMATTR Value x
SYMBOL voltage -736 832 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(10 -10 .5u 10n 10n 20u 40u)
SYMBOL res -512 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1
FLAG -736 944 0
FLAG -208 928 0
TEXT -800 1000 Left 2 !.tran 0 60u\n.model X D(Rs=0 Is=1e-10 tt=3u  Vp={Vp} Cjo=10n)\n.step param Vp list 0 .2 .4 .6 .8 1
TEXT -456 776 Bottom 2 ;This example shows the use of dQ/dt damping parameter Vp to control diode soft recovery.\n \nSee K.J. Teng and S. Pan: 'Modified charge-control equation for simulation of diode reverse recovery',\nElectronics Letters, 15th February 1996 Vol. 32 No. 4
* Z:\home\khalils\Downloads\files\data\raw_asc\1c304f39244c_transistorPolarisation2.asc
* Generated by LTspice 26.0.1 for Windows.
; .step param RC list 20 50 100 150 200 250 500
;.step param RC list 250 500 750 1000 1300 1600
R1 Vb 0 7k
Rb N001 Vb 3k
Rc N001 Vc {RC}
Q1 Vc Vb Ve 0 2N2222
V1 N001 0 12
Re Ve 0 6.3k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran .1
.param RC 1k
.meas TRAN IRC FIND I(Rc) AT=.1
.meas TRAN IRB FIND I(Rb) AT=.1
.meas TRAN IRE FIND I(Re) AT=.1
.meas TRAN VE FIND V(Ve) AT=.1
.meas TRAN VBE FIND V(Vb) - V(Ve) AT=.1
.meas TRAN R_RC FIND RC AT=.1
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1108 680
WIRE 240 -96 32 -96
WIRE 400 -96 240 -96
WIRE 400 -80 400 -96
WIRE 240 -32 240 -96
WIRE 400 16 400 0
WIRE 32 32 32 -96
WIRE 400 32 400 16
WIRE 240 80 240 48
WIRE 288 80 240 80
WIRE 336 80 288 80
WIRE 240 112 240 80
WIRE 32 144 32 112
WIRE 400 176 400 128
WIRE 400 192 400 176
WIRE 240 224 240 192
WIRE 400 304 400 272
SYMBOL res 384 -96 R0
SYMATTR InstName Rc
SYMATTR Value {RC}
SYMBOL voltage 32 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 384 176 R0
SYMATTR InstName Re
SYMATTR Value 6.3k
SYMBOL res 224 -48 R0
SYMATTR InstName Rb
SYMATTR Value 3k
SYMBOL npn 336 32 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL res 224 96 R0
SYMATTR InstName R1
SYMATTR Value 7k
FLAG 400 304 0
FLAG 32 144 0
FLAG 400 176 Ve
FLAG 400 16 Vc
FLAG 288 80 Vb
FLAG 240 224 0
TEXT 128 304 Left 2 !.tran .1
TEXT 128 344 Left 2 !; .step param RC list 20 50 100 150 200 250 500\n;.step param RC list 250 500 750 1000 1300 1600\n.param RC 1k
TEXT 552 -56 Left 2 !.meas TRAN IRC FIND I(Rc) AT=.1\n.meas TRAN IRB FIND I(Rb) AT=.1\n.meas TRAN IRE FIND I(Re) AT=.1\n.meas TRAN VE FIND V(Ve) AT=.1\n.meas TRAN VBE FIND V(Vb) - V(Ve) AT=.1\n.meas TRAN R_RC FIND RC AT=.1
* Z:\home\khalils\Downloads\files\data\raw_asc\8595ae3532ad_45n_IDVG.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 NMOS l=45n w=90n
VG N002 0 1
VD N001 0 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VG 0 1 0.0001 VD 0.05 1 0.95
.inc "45nm_HP.pm"
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1144 680
WIRE 464 16 240 16
WIRE 464 32 464 16
WIRE 240 96 240 16
WIRE 336 144 240 144
WIRE 192 176 0 176
WIRE 336 192 336 144
WIRE 336 192 240 192
WIRE 0 272 0 256
WIRE 240 272 240 192
WIRE 240 272 0 272
WIRE 464 272 464 112
WIRE 464 272 240 272
WIRE 240 304 240 272
SYMBOL voltage 464 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VD
SYMATTR Value 1
SYMBOL nmos4 192 96 R0
SYMATTR InstName M1
SYMATTR Value2 l=45n w=90n
SYMBOL voltage 0 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VG
SYMATTR Value 1
FLAG 240 304 0
TEXT 760 136 Left 2 !.dc VG 0 1 0.0001 VD 0.05 1 0.95
TEXT 768 176 Left 2 !.inc "45nm_HP.pm"
* Z:\home\khalils\Downloads\files\data\raw_asc\510fad32ea85_1077.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 3
R1 OUT N001 2Meg
R2 N001 IN 1Meg
V3 IN 0 SINE(0 1 100)
XU1 N002 N001 +V 0 OUT LT1078 ;pnba In+)In-)V+)V-)OUT
R3 N002 0 1Meg
.tran .1
* Half-Wave Rectifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1077.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -96 96 -128 96
WIRE 16 96 -16 96
WIRE 48 96 16 96
WIRE 144 96 128 96
WIRE 160 96 144 96
WIRE 256 96 240 96
WIRE 192 208 192 192
WIRE 144 224 144 96
WIRE 160 224 144 224
WIRE -96 240 -96 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE 64 256 48 256
WIRE 160 256 144 256
WIRE 192 288 192 272
WIRE -96 336 -96 320
FLAG -96 336 0
FLAG 192 192 +V
FLAG -96 224 +V
FLAG -128 96 0
FLAG 48 256 0
FLAG 192 288 0
FLAG 16 96 IN
FLAG 288 240 OUT
SYMBOL voltage -96 224 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2Meg
SYMBOL res 144 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage 0 96 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
SYMBOL opamps\\LT1077 192 176 R0
SYMATTR InstName U1
SYMBOL res 160 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1Meg
TEXT 296 320 Left 2 !.tran .1
TEXT 152 32 Bottom 2 ;Half-Wave Rectifier
* Z:\home\khalils\Downloads\files\data\raw_asc\09097b0d58dc_Fig28_5a.asc
* Generated by LTspice 26.0.1 for Windows.
* Sample-and-Hold, S/H
A1 Vin 0 clock 0 0 0 Vout 0 SAMPLEHOLD REF=0.5
Vin Vin 0 SINE(0.5 0.5 4MEG)
Vclock clock 0 PULSE(0 1 0 0 0 4.9n 10n)
.tran 0 500n 0 .1n uic
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1344 696
WIRE 384 208 320 208
WIRE 736 208 384 208
WIRE 736 240 672 240
WIRE 992 256 912 256
WIRE 320 272 320 208
WIRE 736 272 608 272
WIRE 608 336 608 272
WIRE 320 416 320 352
WIRE 608 480 608 416
SYMBOL SpecialFunctions\\sample 816 240 R0
WINDOW 3 -28 112 Left 0
SYMATTR Value REF=0.5
SYMATTR InstName A1
SYMBOL voltage 608 320 R0
WINDOW 0 36 42 Left 0
WINDOW 3 35 69 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vclock
SYMATTR Value PULSE(0 1 0 0 0 4.9n 10n)
SYMBOL voltage 320 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value SINE(0.5 0.5 4MEG)
FLAG 320 416 0
FLAG 384 208 Vin
FLAG 608 480 0
FLAG 608 272 clock
FLAG 992 256 Vout
FLAG 672 240 0
TEXT 920 144 Left 0 !.tran 0 500n 0 .1n uic
TEXT 920 176 Left 0 !.options plotwinsize=0
TEXT 848 432 Left 0 ;Sample-and-Hold, S/H
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8374-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8374-1.asy)
+ IS=2.256906516939e-020
+ N=2.423363452597
+ RS=0.1351156839844
+ XTI=23.3518044905306
+ EG=2.5000
D1 N005 0 XP-G3 n=5
C1 N003 0 2.2
XU1 N003 N001 N002 NC_01 N004 OUT N005 IN 0 0 NC_02 NC_03 IN LT8374-1 ;pnba INTVcc)BST)SW)CAP)FB)ISP)ISN)VIN)SYNC/SPRD)GND)CTRL)VC)AVIN
V1 IN 0 24
R2 OUT N005 100m
L1 N002 OUT 10 Rser=10m Rser=72m
C2 N001 N002 22n
C3 OUT 0 2.2 Rser=5m
R1 N004 OUT 287k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
.MODEL XP-G3 D
.lib LT8374-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1540 804
WIRE -48 -96 -208 -96
WIRE -16 -96 -48 -96
WIRE 448 -96 400 -96
WIRE -208 -80 -208 -96
WIRE -48 0 -48 -96
WIRE -16 0 -48 0
WIRE 448 0 448 -32
WIRE 448 0 400 0
WIRE 512 0 448 0
WIRE 656 0 592 0
WIRE 720 0 656 0
WIRE 800 0 720 0
WIRE -208 16 -208 0
WIRE 720 16 720 0
WIRE -128 96 -144 96
WIRE -16 96 -64 96
WIRE 512 96 400 96
WIRE 656 96 656 0
WIRE 656 96 592 96
WIRE 720 96 720 80
WIRE 800 192 800 0
WIRE 800 192 400 192
WIRE 800 208 800 192
WIRE 800 288 400 288
WIRE 800 336 800 288
WIRE -16 384 -32 384
WIRE 800 416 800 400
WIRE 192 480 192 464
SYMBOL voltage -208 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 784 192 R0
SYMATTR InstName R2
SYMATTR Value 100m
SYMBOL cap 704 16 R0
SYMATTR InstName C3
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=5m
SYMBOL cap -64 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL LT8374-1 192 96 R0
SYMATTR InstName U1
SYMBOL cap 432 -96 R0
SYMATTR InstName C2
SYMATTR Value 22n
SYMBOL res 496 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 287k
SYMBOL LED 784 336 R0
WINDOW 123 43 68 Left 2
WINDOW 3 79 37 Left 2
SYMATTR Value2 n=5
SYMATTR Value XP-G3
SYMATTR InstName D1
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL ind 496 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR Value2 Rser=10m
SYMATTR SpiceLine Rser=72m
FLAG -208 16 0
FLAG -32 384 0
FLAG 192 480 0
FLAG 720 96 0
FLAG 800 416 0
FLAG -208 -96 IN
FLAG 800 0 OUT
FLAG -144 96 0
TEXT 472 496 Left 2 !.tran 1m startup
TEXT 960 304 Left 2 !.MODEL XP-G3 D\n+ IS=2.256906516939e-020\n+ N=2.423363452597\n+ RS=0.1351156839844\n+ XTI=23.3518044905306\n+ EG=2.5000
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8330.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8330.asy)
R2 N002 0 34.8K
R1 OUT N002 1Meg
L1 IN N001 6.8 Rser=.1
C2 OUT N002 4.7p
D1 N001 OUT BAT46WJ
Rload OUT 0 352
V1 IN 0 12
C1 N003 0 1
C3 OUT 0 4.7 Rser=10m
XU1 N002 MP_01 N001 MP_02 0 IN N003 IN LT8330 ;pnba FBX))SW))GND)Vin)INTVcc)EN/UVLO
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT8330.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 48 -48 48
WIRE 128 48 32 48
WIRE 176 48 128 48
WIRE 288 48 256 48
WIRE 336 48 288 48
WIRE 448 48 400 48
WIRE 560 48 448 48
WIRE 672 48 560 48
WIRE 768 48 672 48
WIRE -48 64 -48 48
WIRE 672 64 672 48
WIRE 768 64 768 48
WIRE 448 80 448 48
WIRE 128 96 128 48
WIRE 288 96 288 48
WIRE 560 96 560 48
WIRE -48 160 -48 144
WIRE 672 160 672 128
WIRE 768 160 768 144
WIRE 32 208 32 48
WIRE 48 208 32 208
WIRE 448 208 448 160
WIRE 448 208 368 208
WIRE 560 208 560 160
WIRE 560 208 448 208
WIRE 448 224 448 208
WIRE 448 320 448 304
WIRE 128 336 128 320
WIRE 288 336 288 320
WIRE 128 416 128 400
SYMBOL voltage -48 48 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL ind 160 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 6.8
SYMATTR SpiceLine Rser=.1
SYMBOL schottky 336 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value BAT46WJ
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 752 48 R0
SYMATTR InstName Rload
SYMATTR Value 352
SYMBOL res 432 208 R0
SYMATTR InstName R2
SYMATTR Value 34.8K
SYMBOL cap 112 336 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 432 64 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL cap 544 96 R0
SYMATTR InstName C2
SYMATTR Value 4.7p
SYMBOL cap 656 64 R0
SYMATTR InstName C3
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=10m
SYMBOL PowerProducts\\LT8330 208 208 R0
SYMATTR InstName U1
FLAG 128 416 0
FLAG 288 336 0
FLAG -48 160 0
FLAG 448 320 0
FLAG 768 160 0
FLAG 672 160 0
FLAG -48 48 IN
FLAG 768 48 OUT
TEXT 464 392 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\5a989c92049f_90nm_PMOS.asc
* Generated by LTspice 26.0.1 for Windows.
vsd N001 0 -1.2
M1 N001 N003 0 N002 PMOS l=90nm w=405nm
vsg N003 0 -1.2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc vsg 0 -1.2 .1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 64 224 64
WIRE 224 96 224 64
WIRE 368 96 368 64
WIRE 224 144 224 112
WIRE 176 176 80 176
WIRE 80 192 80 176
WIRE 208 272 80 272
WIRE 224 272 224 192
WIRE 224 272 208 272
WIRE 368 272 368 176
WIRE 368 272 224 272
WIRE 208 288 208 272
SYMBOL voltage 80 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vsg
SYMATTR Value -1.2
SYMBOL pmos4 176 96 R0
SYMATTR InstName M1
SYMATTR Value2 l=90nm w=405nm
SYMBOL voltage 368 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vsd
SYMATTR Value -1.2
FLAG 208 288 0
TEXT 48 312 Left 2 !.dc vsg 0 -1.2 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\681cffe3d9a1_not_gate.asc
* Generated by LTspice 26.0.1 for Windows.
* out
V2 N001 0 5
V1 N002 0 PULSE(0 5 0 0.01m 0.01m 1m 2m)
M2 N003 N002 N004 N004 NMOS
M1 N001 N002 N003 N001 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 32 320 32
WIRE 320 128 320 32
WIRE 320 128 224 128
WIRE 320 176 320 128
WIRE 320 176 224 176
WIRE 112 208 32 208
WIRE 176 208 112 208
WIRE 256 224 224 224
WIRE 256 240 256 224
WIRE 320 240 256 240
WIRE 400 288 256 288
WIRE 112 320 112 208
WIRE 208 320 112 320
WIRE 400 336 400 288
WIRE 400 336 256 336
SYMBOL pmos4 176 128 R0
SYMATTR InstName M1
SYMBOL voltage 384 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 32 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 0.01m 0.01m 1m 2m)
SYMBOL nmos4 208 240 R0
SYMATTR InstName M2
FLAG 384 112 0
FLAG 32 288 0
TEXT 0 352 Left 2 !.tran 10m
TEXT 320 240 Left 2 ;out
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL42002.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL42002.asy)
V1 IN 0 7
R1 OUT N002 17.4k
C2 N001 0 4.7n
XU1 IN N002 IN N001 OUT 0 ADPL42002 ;pnba Vin)ADJ)EN)SS)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
R2 N002 0 10k
Rload OUT 0 16.5
.tran 6m startup
.lib ADPL42002.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 400 32 352 32
WIRE 528 32 400 32
WIRE 624 32 528 32
WIRE -32 48 -32 32
WIRE 528 48 528 32
WIRE 624 48 624 32
WIRE 400 80 400 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 528 144 528 112
WIRE 624 144 624 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 400 224 400 160
WIRE 400 224 352 224
WIRE 400 240 400 224
WIRE 224 304 224 288
WIRE 400 336 400 320
SYMBOL cap 512 48 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL res 384 64 R0
SYMATTR InstName R1
SYMATTR Value 17.4k
SYMBOL ADPL42002 224 128 R0
SYMATTR InstName U1
SYMBOL res 384 224 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 608 32 R0
SYMATTR InstName Rload
SYMATTR Value 16.5
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 7
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG -32 32 IN
FLAG 624 144 0
FLAG 528 144 0
FLAG 624 32 OUT
FLAG 400 336 0
TEXT 520 272 Left 2 !.tran 6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4219-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4219-5.asy)
R1 N003 0 20K
C1 N004 0 .1
C2 OUT 0 330
V1 IN 0 5
XU1 NC_01 IN 0 0 N004 N004 0 OUT MP_02 MP_03 MP_04 MP_05 NC_06 N002 NC_07 NC_08 N003 NC_09 LTC4219-5 ;pnba Sense)Vdd)_EN1)_EN2)Timer)IntVcc)GND)Out)))))Gate)_PG)_FLT)FB)Imon)Iset
R2 OUT N002 20K
S1 0 OUT N001 0 SHORT
V2 N001 0 PULSE(0 1 240m 1m 1m 10m)
.tran 600m startup
.model SHORT SW(Ron=10m Roff=1K Vt=.5 Vh=-.4)
.lib LTC4219-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1592 680
WIRE 80 16 -48 16
WIRE 416 16 368 16
WIRE 512 16 416 16
WIRE 624 16 512 16
WIRE -48 32 -48 16
WIRE 416 32 416 16
WIRE 512 32 512 16
WIRE 624 32 624 16
WIRE 848 48 672 48
WIRE 944 48 928 48
WIRE 80 80 48 80
WIRE -48 128 -48 112
WIRE 512 128 512 96
WIRE 624 128 624 112
WIRE 80 144 48 144
WIRE 416 144 416 112
WIRE 416 144 368 144
WIRE 384 208 368 208
WIRE 480 208 464 208
WIRE 432 272 368 272
WIRE 432 336 432 272
WIRE 432 336 368 336
WIRE 432 352 432 336
WIRE 224 416 224 384
WIRE 432 432 432 416
SYMBOL cap 416 352 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL LTC4219-5 224 176 R0
SYMATTR InstName U1
SYMBOL res 368 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 20K
SYMBOL voltage 832 48 R270
WINDOW 123 -74 56 VBottom 2
WINDOW 39 -53 56 VBottom 2
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 240m 1m 1m 10m)
SYMBOL sw 624 128 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SHORT
SYMBOL voltage -48 16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 400 16 R0
SYMATTR InstName R2
SYMATTR Value 20K
SYMBOL cap 496 32 R0
SYMATTR InstName C2
SYMATTR Value 330
FLAG 432 432 0
FLAG 224 416 0
FLAG 480 208 0
FLAG -48 128 0
FLAG 512 128 0
FLAG 624 128 0
FLAG 672 96 0
FLAG 944 48 0
FLAG -48 16 IN
FLAG 624 16 OUT
FLAG 48 80 0
FLAG 48 144 0
TEXT 496 304 Left 2 !.tran 600m startup\n.model SHORT SW(Ron=10m Roff=1K Vt=.5 Vh=-.4)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4122C.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4122C.asy)
R1 GATE N004 10
V3 N003 0 PULSE(0 5 0 2n 2n 998n 2u)
V2 N002 0 15
V1 N001 0 5
XU1 N001 N003 0 0 N004 N002 0 N005 ADuM4122x Vrun2=11.2 ;pnba Vdd1)Vin)GND1)GND2)Vout)Vdd2)_SRC)Vout_SRC
C1 GATE 0 2n
R2 GATE N005 10
.tran 10u
.lib ADuM4122x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -16 0 -16
WIRE 448 -16 320 -16
WIRE 0 0 0 -16
WIRE 448 0 448 -16
WIRE 160 48 160 -16
WIRE 320 48 320 -16
WIRE 0 96 0 80
WIRE 448 96 448 80
WIRE 112 160 -288 160
WIRE 400 160 368 160
WIRE 496 160 480 160
WIRE 544 160 496 160
WIRE 576 160 544 160
WIRE -288 176 -288 160
WIRE 544 176 544 160
WIRE 112 240 96 240
WIRE 400 240 368 240
WIRE 496 240 496 160
WIRE 496 240 480 240
WIRE 544 256 544 240
WIRE -288 272 -288 256
WIRE 160 352 160 336
WIRE 320 352 320 336
SYMBOL voltage -288 160 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 2n 2n 998n 2u)
SYMBOL res 496 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL ADuM4122C 240 160 R0
SYMATTR InstName U1
SYMBOL res 496 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL voltage 0 -16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 528 176 R0
WINDOW 0 35 16 Left 2
WINDOW 3 36 51 Left 2
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL voltage 448 -16 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value 15
FLAG 544 256 0
FLAG 576 160 GATE
FLAG 448 96 0
FLAG 0 96 0
FLAG -288 272 0
FLAG 320 352 0
FLAG 160 352 0
FLAG 96 240 0
TEXT 416 336 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3225-1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 2.7
C1 N001 N002 1
C2 OUT N004 .1m ic=1.5
C3 N004 0 .3m ic=1.2
R1 N003 0 12K
XU1 N001 N002 N004 IN NC_01 0 N003 0 IN OUT LTC3225-1 ;pnba C+)C-)Cx)_SHDN)Pgood)Vsel)Prog)GND)Vin)Cout
.tran 2m startup
* Note: \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capacitance is scaled down from its real value;\n2. Load capacitor initial condion can be given to represent the specific \nresidual voltage at the beginning of the charging.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3225-1.asy)
.lib LTC3225-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 680
WIRE 112 0 16 0
WIRE 240 0 112 0
WIRE 240 16 240 0
WIRE 16 32 16 0
WIRE 112 80 112 0
WIRE 128 80 112 80
WIRE 400 80 352 80
WIRE 400 96 400 80
WIRE 16 144 16 112
WIRE 400 176 400 160
WIRE 400 176 352 176
WIRE 128 272 112 272
WIRE 400 272 352 272
WIRE 400 288 400 272
WIRE 32 368 16 368
WIRE 128 368 112 368
WIRE 400 368 400 352
WIRE 400 368 352 368
WIRE 400 384 400 368
WIRE 240 448 240 432
WIRE 400 464 400 448
FLAG 240 448 0
FLAG 16 144 0
FLAG 400 464 0
FLAG 16 368 0
FLAG 112 272 0
FLAG 16 0 IN
FLAG 400 272 OUT
SYMBOL voltage 16 16 R0
SYMATTR InstName V1
SYMATTR Value 2.7
SYMBOL cap 384 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 384 288 R0
SYMATTR InstName C2
SYMATTR Value .1m ic=1.5
SYMBOL cap 384 384 R0
SYMATTR InstName C3
SYMATTR Value .3m ic=1.2
SYMBOL res 128 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 12K
SYMBOL PowerProducts\\LTC3225-1 240 224 R0
SYMATTR InstName U1
TEXT 552 456 Left 2 !.tran 2m startup
TEXT -72 472 Left 2 ;Note: \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capacitance is scaled down from its real value;\n2. Load capacitor initial condion can be given to represent the specific \nresidual voltage at the beginning of the charging.