Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1011.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT1011.asy)
V3 N001 0 PULSE(-100m 100m 0 .5m .5m 0 1m)
R2 N005 0 3K
V2 -V 0 -15
V4 N004 0 PULSE(0 2.7 0 1u 1u 5m 10m)
XU1 0 0 N001 -V NC_01 N003 N002 +V LT1011 ;pnba GND)In+)In-)V-)BAL)STROBE)OUT)V+
Q1 N003 N004 N005 0 2N3904
V1 +V 0 15
R1 +V N002 2K
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 30m
.lib LT1011.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -384 96 -384 80
WIRE -288 96 -288 80
WIRE -96 128 -96 112
WIRE 0 128 -96 128
WIRE 0 144 0 128
WIRE -384 192 -384 176
WIRE -288 192 -288 176
WIRE -96 192 -96 128
WIRE -128 224 -656 224
WIRE -656 240 -656 224
WIRE 0 240 0 224
WIRE 0 240 -48 240
WIRE -128 256 -144 256
WIRE -112 304 -112 288
WIRE -112 304 -144 304
WIRE -144 320 -144 304
WIRE -656 336 -656 320
WIRE -80 336 -80 288
WIRE -144 384 -496 384
WIRE -496 400 -496 384
WIRE -80 448 -80 432
WIRE -496 496 -496 480
WIRE -80 544 -80 528
SYMBOL npn -144 336 R0
WINDOW 0 58 22 Left 2
WINDOW 3 54 66 Left 2
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL voltage -288 80 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -496 384 R0
SYMATTR InstName V4
SYMATTR Value PULSE(0 2.7 0 1u 1u 5m 10m)
SYMBOL res -16 128 R0
SYMATTR InstName R1
SYMATTR Value 2K
SYMBOL voltage -384 80 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res -96 432 R0
SYMATTR InstName R2
SYMATTR Value 3K
SYMBOL voltage -656 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-100m 100m 0 .5m .5m 0 1m)
SYMBOL LT1011 -96 240 R0
SYMATTR InstName U1
FLAG -288 192 0
FLAG -384 192 0
FLAG -384 80 +V
FLAG -96 288 -V
FLAG -288 80 -V
FLAG -96 112 +V
FLAG -656 336 0
FLAG -144 256 0
FLAG -80 544 0
FLAG -496 496 0
FLAG -144 320 0
TEXT 48 488 Left 2 !.tran 30m
* Z:\home\khalils\Downloads\files\data\raw_asc\10edf969c578_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD795.asy)
R2 N007 N005 R
XU1 N004 N002 NC_01 NC_02 N002 AD795 ;pnba In+)In-)V+)V-)OUT
C2 N004 N001 C
R3 N005 N003 R
C4 0 N007 C
R1 N004 0 R
XU2 N007 N006 NC_03 NC_04 N006 AD795 ;pnba In+)In-)V+)V-)OUT
C1 N001 N003 C
R4 N002 N001 R
C3 N006 N005 C
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -144 -176 -144
WIRE 256 -144 64 -144
WIRE -320 -16 -384 -16
WIRE -176 -16 -176 -144
WIRE -176 -16 -256 -16
WIRE -112 -16 -176 -16
WIRE 16 -16 -48 -16
WIRE 144 -16 16 -16
WIRE 256 0 256 -144
WIRE 256 0 208 0
WIRE 16 16 16 -16
WIRE 144 16 96 16
WIRE 96 112 96 16
WIRE 256 112 256 0
WIRE 256 112 96 112
WIRE 16 128 16 96
WIRE -16 304 -176 304
WIRE 256 304 48 304
WIRE -384 432 -384 -16
WIRE -320 432 -384 432
WIRE -176 432 -176 304
WIRE -176 432 -240 432
WIRE -128 432 -176 432
WIRE 16 432 -48 432
WIRE 144 432 16 432
WIRE 256 448 256 304
WIRE 256 448 208 448
WIRE 16 464 16 432
WIRE 144 464 96 464
WIRE 16 560 16 528
WIRE 96 576 96 464
WIRE 256 576 256 448
WIRE 256 576 96 576
SYMBOL cap -48 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMBOL OpAmps\\AD795 176 64 M180
SYMATTR InstName U1
SYMBOL cap 32 528 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C4
SYMBOL cap -256 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMBOL res 80 -160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMBOL res -224 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMBOL res -32 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMBOL res 0 0 R0
SYMATTR InstName R1
SYMBOL cap 48 288 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMBOL OpAmps\\AD795 176 512 M180
SYMATTR InstName U2
FLAG 16 128 0
FLAG 16 560 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4449.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4449.asy)
C1 N003 N002 .1
V1 N001 0 6
L1 N003 N006 1
V2 N007 0 PULSE(0 6 0 10n 10n 1u 2u)
V3 N004 0 32
MQ2 N003 N008 0 0 IRF7468
D1 N001 N002 1N5819
MQ1 N004 N005 N003 N003 IRF7468
C2 N006 0 10
R1 N006 0 1
XU1 MP_01 MP_02 N005 N003 N008 0 N007 N001 N001 N002 LTC4449 ;pnba ))TG)TS)BG)GND)IN)Vlogic)Vcc)Boost
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 250u startup
.lib LTC4449.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 64 -32 64
WIRE 112 64 64 64
WIRE 160 64 112 64
WIRE 256 64 224 64
WIRE 496 80 336 80
WIRE 336 96 336 80
WIRE 496 96 496 80
WIRE 112 112 112 64
WIRE -32 176 -32 64
WIRE -32 176 -112 176
WIRE -16 176 -32 176
WIRE 288 176 240 176
WIRE -112 192 -112 176
WIRE 496 192 496 176
WIRE -32 256 -32 176
WIRE -16 256 -32 256
WIRE 256 256 256 64
WIRE 256 256 240 256
WIRE 336 256 336 192
WIRE 336 256 256 256
WIRE 384 256 336 256
WIRE 496 256 464 256
WIRE 576 256 496 256
WIRE 496 272 496 256
WIRE 576 272 576 256
WIRE -112 288 -112 272
WIRE -16 336 -96 336
WIRE 288 336 240 336
WIRE -96 368 -96 336
WIRE 336 368 336 352
WIRE 496 368 496 336
WIRE 576 368 576 352
WIRE 112 416 112 400
WIRE -96 464 -96 448
SYMBOL voltage -96 352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 6 0 10n 10n 1u 2u)
SYMBOL voltage 496 80 R0
SYMATTR InstName V3
SYMATTR Value 32
SYMBOL nmos 288 96 R0
SYMATTR InstName Q1
SYMATTR Value IRF7468
SYMBOL cap 224 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL voltage -112 176 R0
WINDOW 3 20 97 Left 2
SYMATTR Value 6
SYMATTR InstName V1
SYMBOL PowerProducts\\LTC4449 112 256 R0
SYMATTR InstName U1
SYMBOL cap 480 272 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL ind 368 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL schottky 0 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 560 256 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL nmos 288 256 R0
SYMATTR InstName Q2
SYMATTR Value IRF7468
FLAG 112 416 0
FLAG -96 464 0
FLAG -112 288 0
FLAG 336 368 0
FLAG 496 192 0
FLAG 496 368 0
FLAG 576 368 0
TEXT 392 440 Left 2 !.tran 250u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T2 0 0 OUT 0 Td=30n Z0=150
T1 IN 0 0 OUT Td=50n Z0=50
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC5532.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC5532.asy)
V2 N002 0 SINE(0 {V} 1G) Rser=50
V1 N001 0 3.6
C1 N003 N002 39p
R3 N004 0 10K
XU1 N003 0 0 N004 OUT N001 LTC5532 ;pnba RFin)GND)Vos)Vm)Vout)Vcc
R2 OUT N004 10K
.tran 2u
.step param V list 1m 10m 100m 1
.lib LTC5532.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 192 80 -272 80
WIRE -272 96 -272 80
WIRE 192 112 192 80
WIRE -48 176 -160 176
WIRE 64 176 16 176
WIRE 368 176 320 176
WIRE 400 176 368 176
WIRE -272 192 -272 176
WIRE -160 192 -160 176
WIRE 368 208 368 176
WIRE -160 288 -160 272
WIRE 64 336 32 336
WIRE 368 336 368 288
WIRE 368 336 320 336
WIRE 368 368 368 336
WIRE 192 416 192 400
WIRE 368 464 368 448
SYMBOL SpecialFunctions\\LTC5532 192 256 R0
SYMATTR InstName U1
SYMBOL voltage -160 176 R0
WINDOW 3 16 96 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 41 62 Left 2
SYMATTR Value SINE(0 {V} 1G)
SYMATTR InstName V2
SYMATTR SpiceLine Rser=50
SYMBOL cap 16 160 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 39p
SYMBOL voltage -272 80 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL res 352 192 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 352 352 R0
SYMATTR InstName R3
SYMATTR Value 10K
FLAG -272 192 0
FLAG -160 288 0
FLAG 192 416 0
FLAG 400 176 OUT
FLAG 32 336 0
FLAG 368 464 0
TEXT 232 488 Left 2 !.tran 2u\n.step param V list 1m 10m 100m 1
* Z:\home\khalils\Downloads\files\data\raw_asc\614e972e4358_DivMod.asc
* Generated by LTspice 26.0.1 for Windows.
B1 INT_IN 0 V=ROUND(V(IN))
B2 DIV 0 V=INT(V(INT_IN)/{BASE})
B3 MOD 0 V=ROUND(V(INT_IN)-{BASE}*V(DIV))
.param BASE=2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2360 1444
WIRE 944 -80 848 -80
WIRE 848 -16 848 -80
WIRE 848 96 848 64
WIRE 464 160 272 160
WIRE 608 208 544 208
WIRE 656 208 608 208
WIRE 960 208 848 208
WIRE 544 240 544 208
WIRE 848 272 848 208
WIRE 544 368 544 320
WIRE 848 384 848 352
FLAG 960 208 DIV
IOPIN 960 208 Out
FLAG 272 160 IN
IOPIN 272 160 In
FLAG 944 -80 MOD
IOPIN 944 -80 Out
FLAG 544 368 0
FLAG 608 208 INT_IN
FLAG 848 384 0
FLAG 848 96 0
SYMBOL bv 544 224 R0
SYMATTR InstName B1
SYMATTR Value V=ROUND(V(IN))
SYMBOL bv 848 256 R0
SYMATTR InstName B2
SYMATTR Value V=INT(V(INT_IN)/{BASE})
SYMBOL bv 848 -32 R0
SYMATTR InstName B3
SYMATTR Value V=ROUND(V(INT_IN)-{BASE}*V(DIV))
TEXT 248 320 Left 2 !.param BASE=2
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8030.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8030.asy)
V1 +V 0 5
Vin1 IN 0 SINE(0 1 100K)
R2 OUT N001 10K
V2 -V 0 -5
XU1 IN N001 +V -V OUT AD8040 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10K
.tran 100u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 960 680
WIRE 272 128 256 128
WIRE 368 128 352 128
WIRE 384 128 368 128
WIRE 480 128 464 128
WIRE 32 208 32 192
WIRE 160 208 160 192
WIRE 368 224 368 128
WIRE 384 224 368 224
WIRE 480 240 480 128
WIRE 480 240 448 240
WIRE 544 240 480 240
WIRE 384 256 304 256
WIRE 304 272 304 256
WIRE 32 304 32 288
WIRE 160 304 160 288
WIRE 304 368 304 352
SYMBOL voltage 160 192 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 32 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 480 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 304 256 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin1
SYMATTR Value SINE(0 1 100K)
SYMBOL res 368 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL opamps\\AD8030 416 176 R0
SYMATTR InstName U1
FLAG 32 192 +V
FLAG 304 368 0
FLAG 544 240 OUT
FLAG 304 256 IN
FLAG 416 208 +V
FLAG 160 192 -V
FLAG 416 272 -V
FLAG 256 128 0
FLAG 160 304 0
FLAG 32 304 0
TEXT 560 360 Left 2 !.tran 100u
* Z:\tmp\asc_dec_bjh7r6w2\04a3a49d6e19_rhpz_small_signal_verification_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
B2 Ioo 0 V=(adg+bdg+cdg)*V(iv0)*V(iv0) + (ddg+edg)*V(iv0) + fdg
B7 <idgbasso> 0 V=V(Ioo) Laplace=(1 - s/wrhpz)
B13 idg_izoh 0 V=V(idg_irm_ss) Laplace=s*Tsw/(1 - exp(-s*Tsw))
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2200 4212
WIRE -768 768 -896 768
WIRE -768 880 -768 768
WIRE -768 1024 -768 960
WIRE -736 1792 -928 1792
WIRE 1056 1792 976 1792
WIRE -928 1904 -928 1792
WIRE 976 1904 976 1792
WIRE -928 2048 -928 1984
WIRE 976 2048 976 1984
SYMBOL bv -768 864 R0
SYMATTR InstName B2
SYMATTR Value V=(adg+bdg+cdg)*V(iv0)*V(iv0) + (ddg+edg)*V(iv0) + fdg
SYMBOL bv -928 1888 R0
SYMATTR InstName B7
SYMATTR Value V=V(Ioo) Laplace=(1 - s/wrhpz)
SYMBOL bv 976 1888 R0
SYMATTR InstName B13
SYMATTR Value V=V(idg_irm_ss) Laplace=s*Tsw/(1 - exp(-s*Tsw))
FLAG -896 768 Ioo
FLAG -768 1024 0
FLAG -736 1792 <idgbasso>
FLAG -928 2048 0
FLAG 976 2048 0
FLAG 1056 1792 idg_izoh
* Z:\home\khalils\Downloads\files\data\raw_asc\028aec6c5597_Diode1.asc
* Generated by LTspice 26.0.1 for Windows.
;dc V1 -1 1 0.001
V1 N001 0 SINE(0 15 1000)
R1 V2 0 500
D1 N001 V2 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 3ms 0 0.03ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 -80 48 -80
WIRE 304 -80 240 -80
WIRE 336 -80 304 -80
WIRE 192 0 48 0
WIRE 336 0 192 0
WIRE 192 32 192 0
SYMBOL voltage 48 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 15 1000)
SYMBOL diode 176 -64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 320 -96 R0
SYMATTR InstName R1
SYMATTR Value 500
FLAG 192 32 0
FLAG 304 -80 V2
TEXT 104 -16 Left 2 !;dc V1 -1 1 0.001
TEXT 104 72 Left 2 !.tran 0 3ms 0 0.03ms
* Z:\home\khalils\Downloads\files\data\raw_asc\453467b897ef_DelayOff.asc
* Generated by LTspice 26.0.1 for Windows.
* Inverter with delay to off
A1 N001 0 0 0 0 0 OUT 0 SCHMITT VT=1 Vh=0.1
C1 N001 0 100n Rpar=100Meg
I1 0 N001 {100n/Td}
S1 0 N001 IN 0 SW
.model SW SW(Roff=1G Vt=0.5)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 80 16 80
WIRE 272 80 160 80
WIRE 368 80 272 80
WIRE 480 80 432 80
WIRE 16 96 16 80
WIRE 272 96 272 80
WIRE -32 112 -144 112
WIRE 160 112 160 80
WIRE -32 160 -48 160
WIRE -48 192 -48 160
WIRE 16 192 16 176
WIRE 160 192 160 176
WIRE 272 192 272 176
IOPIN -144 112 In
IOPIN 480 80 Out
SYMBOL cap 176 112 M0
SYMATTR InstName C1
SYMATTR Value 100n
SYMATTR SpiceLine Rpar=100Meg
SYMBOL current 272 176 M180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value {100n/Td}
SYMBOL Digital\\schmtbuf 368 144 M180
WINDOW 3 8 60 Invisible 2
SYMATTR Value VT=1 Vh=0.1
SYMATTR InstName A1
SYMBOL sw 16 192 M180
SYMATTR InstName S1
FLAG 272 192 0
FLAG 160 192 0
FLAG 16 192 0
FLAG -48 192 0
FLAG -144 112 IN
FLAG 480 80 OUT
TEXT 0 32 Left 2 !.model SW SW(Roff=1G Vt=0.5)
TEXT 72 -40 Left 2 ;Inverter with delay to off
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6211.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6211.asy)
V3 N003 0 pulse(-25m 25m 30n 1n 1n 35n 70n)
V1 +V 0 5
XU1 N003 N001 +V -V N002 P001 LT6210 ;pnba In+)In-)V+)V-)OUT)V-1
R2 N002 N001 1.1K
V2 -V 0 -5
R3 N001 0 1.1K
R4 N002 0 150
R1 P001 0 56K
.tran 100n
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 48 48 48
WIRE 176 48 144 48
WIRE 208 48 176 48
WIRE 304 48 288 48
WIRE -272 96 -272 80
WIRE -160 96 -160 80
WIRE 176 176 176 48
WIRE 192 176 176 176
WIRE -272 192 -272 176
WIRE -160 192 -160 176
WIRE 304 208 304 48
WIRE 304 208 288 208
WIRE 400 208 304 208
WIRE 400 224 400 208
WIRE -80 240 -112 240
WIRE 192 240 0 240
WIRE 400 320 400 304
WIRE 240 368 240 352
SYMBOL voltage 16 240 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value pulse(-25m 25m 30n 1n 1n 35n 70n)
SYMBOL res 384 208 R0
SYMATTR InstName R4
SYMATTR Value 150
SYMBOL opamps\\LT6211 224 208 R0
SYMATTR InstName U1
SYMBOL voltage -160 80 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage -272 80 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 224 256 R0
SYMATTR InstName R1
SYMATTR Value 56K
SYMBOL res 160 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.1K
SYMBOL res 304 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.1K
FLAG -160 192 0
FLAG -272 192 0
FLAG -272 80 +V
FLAG 208 144 +V
FLAG -160 80 -V
FLAG 208 272 -V
FLAG 240 368 0
FLAG 48 48 0
FLAG -112 240 0
FLAG 400 320 0
TEXT 352 400 Left 2 !.tran 100n
* Z:\tmp\asc_dec_bjh7r6w2\195e47c9fe61_Thermo_measure_sim_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V2 V_therm 0 -10m
R1 N002 N004 845
V1 3V3 0 3.3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -816 -16 -816 -48
WIRE 96 32 96 0
WIRE -1232 48 -1232 16
WIRE -1008 48 -1008 16
WIRE -192 48 -400 48
WIRE 64 48 -192 48
WIRE 64 80 0 80
WIRE -816 96 -816 64
WIRE -768 96 -816 96
WIRE -192 96 -192 48
WIRE -816 112 -816 96
WIRE -1232 160 -1232 128
WIRE -1008 160 -1008 128
WIRE 0 176 0 160
WIRE 64 176 0 176
WIRE -192 208 -192 160
WIRE -192 208 -400 208
WIRE 0 208 -192 208
WIRE 64 208 0 208
WIRE -816 224 -816 192
WIRE 0 224 0 208
WIRE 96 272 96 224
SYMBOL voltage -1232 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -10m
SYMBOL res -16 64 R0
SYMATTR InstName R1
SYMATTR Value 845
SYMBOL voltage -1008 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG -1008 160 0
FLAG -1008 16 3V3
FLAG 96 0 3V3
FLAG -1232 160 0
FLAG -1232 16 V_therm
FLAG 0 224 0
FLAG -816 224 0
FLAG -816 -48 3V3
FLAG 176 192 V_ref
* Z:\home\khalils\Downloads\files\data\raw_asc\092ec90a9e4e_Gate2a.asc
* Generated by LTspice 26.0.1 for Windows.
A1 0 N001 0 N003 0 0 N002 0 AND
V1 N001 0 pulse(0 1 0 10n 10n .5u 1u)
R1 N003 0 1K
.tran 20u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1220 680
WIRE 704 128 544 128
WIRE 832 128 768 128
WIRE 704 160 640 160
WIRE 640 176 640 160
WIRE 720 192 720 176
WIRE 544 224 544 128
WIRE 640 272 640 256
WIRE 544 320 544 304
SYMBOL digital\\and 736 80 R0
SYMATTR InstName A1
SYMBOL res 624 160 R0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage 544 208 R0
SYMATTR InstName V1
SYMATTR Value pulse(0 1 0 10n 10n .5u 1u)
FLAG 544 320 0
FLAG 640 272 0
FLAG 720 192 0
TEXT 816 208 Left 0 !.tran 20u
* Z:\home\khalils\Downloads\files\data\raw_asc\01573538438c_Draft10.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 0 N002 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 NE555 ;pnba GND)TRIG)OUT)RST)CV)THRS)DIS)Vcc
C1 N002 N001 C
V1 N001 0 V
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Misc\NE555.asy)
.lib NE555.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 32 -48 32
WIRE -464 96 -640 96
WIRE 64 96 -400 96
WIRE -640 144 -640 96
WIRE -640 352 -640 224
WIRE -48 352 -48 32
FLAG -48 352 0
FLAG -640 352 0
SYMBOL Misc\\NE555 176 128 R0
SYMATTR InstName U1
SYMBOL cap -400 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMBOL voltage -640 128 R0
SYMATTR InstName V1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3103.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3103.asy)
L1 N003 OUT1 10
R2 OUT1 N004 1.78Meg
V1 IN 0 12
C3 OUT1 N004 12p
R3 N004 0 665K
C1 N001 0 1
Rload1 OUT1 0 7.3
XU1 IN N003 N002 0 N005 N001 IN N004 MP_01 IN LTC3103 ;pnba Vin)SW)BST)GND)Pgood)Vcc)Run)FB))Mode
C4 OUT1 0 47 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
C2 N002 N003 22n
R1 N001 N005 100K
.tran 2m startup
.lib LTC3103.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 96 -48 -128 -48
WIRE 256 -48 96 -48
WIRE -128 -32 -128 -48
WIRE 256 -32 256 -48
WIRE -32 16 -48 16
WIRE 112 16 32 16
WIRE 432 16 400 16
WIRE 432 32 432 16
WIRE -128 64 -128 48
WIRE 96 112 96 -48
WIRE 112 112 96 112
WIRE 432 112 432 96
WIRE 432 112 400 112
WIRE 496 112 432 112
WIRE 608 112 576 112
WIRE 688 112 608 112
WIRE 848 112 688 112
WIRE 944 112 848 112
WIRE 608 128 608 112
WIRE 848 128 848 112
WIRE 944 128 944 112
WIRE 32 208 32 16
WIRE 96 208 96 112
WIRE 112 208 96 208
WIRE 608 208 608 192
WIRE 608 208 400 208
WIRE 688 208 688 192
WIRE 688 208 608 208
WIRE 688 224 688 208
WIRE 848 224 848 192
WIRE 944 224 944 208
WIRE 32 304 32 288
WIRE 112 304 32 304
WIRE 416 304 400 304
WIRE 688 320 688 304
SYMBOL cap 592 128 R0
SYMATTR InstName C3
SYMATTR Value 12p
SYMBOL res 928 112 R0
SYMATTR InstName Rload1
SYMATTR Value 7.3
SYMBOL ind 480 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL voltage -128 -48 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL PowerProducts\\LTC3103 256 160 R0
SYMATTR InstName U1
SYMBOL cap 416 32 R0
SYMATTR InstName C2
SYMATTR Value 22n
SYMBOL res 672 96 R0
SYMATTR InstName R2
SYMATTR Value 1.78Meg
SYMBOL cap 32 0 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 672 208 R0
SYMATTR InstName R3
SYMATTR Value 665K
SYMBOL cap 832 128 R0
SYMATTR InstName C4
SYMATTR Value 47
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL res 16 192 R0
WINDOW 3 23 93 Left 2
SYMATTR Value 100K
SYMATTR InstName R1
FLAG 416 304 0
FLAG -128 64 0
FLAG -48 16 0
FLAG 688 320 0
FLAG 848 224 0
FLAG 944 224 0
FLAG -128 -48 IN
FLAG 944 112 OUT1
TEXT 824 344 Left 2 !.tran 2m startup