Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\3fd9289a96c6_vca_cont_driver.asc
* Generated by LTspice 26.0.1 for Windows.
R4 N007 -15 5k
R1 N001 N002 10K
XU1 N001 N006 N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R2 N005 0 100
R3 0 N007 23k
Q1 N005 0 N004 0 2N2907
R12 N001 0 10k
R7 N003 N004 22k
V3 0 -15 15
V2 +15 0 15
C1 N003 0 100n
V1 N006 0 PULSE(0 5 0 100m 100u 0u 100.1m)
R6 N002 N003 10k
R5 N001 N007 470k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 5 0.1
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1920 700
WIRE 512 -16 464 -16
WIRE 640 -16 592 -16
WIRE 464 64 464 -16
WIRE 528 64 464 64
WIRE 640 80 640 -16
WIRE 640 80 592 80
WIRE 1024 80 640 80
WIRE 1184 80 1104 80
WIRE 1328 80 1184 80
WIRE 1488 80 1408 80
WIRE 1808 80 1584 80
WIRE 528 96 32 96
WIRE 1808 96 1808 80
WIRE 1184 112 1184 80
WIRE 32 144 32 96
WIRE 464 192 464 64
WIRE 480 192 464 192
WIRE 592 192 560 192
WIRE 1184 208 1184 176
WIRE 1536 208 1536 144
WIRE 1808 208 1808 176
WIRE 464 272 464 192
WIRE 32 288 32 224
WIRE 368 400 368 384
WIRE 208 432 208 384
WIRE 368 512 368 480
WIRE 464 512 464 352
WIRE 464 512 368 512
WIRE 208 528 208 512
WIRE 208 528 192 528
WIRE 192 544 192 528
WIRE 208 560 208 528
WIRE 368 560 368 512
WIRE 208 656 208 640
WIRE 368 656 368 640
WIRE 368 656 208 656
SYMBOL cap 1168 112 R0
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL voltage 32 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 100m 100u 0u 100.1m)
SYMBOL voltage 208 544 R0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL res 496 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 1792 80 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL pnp 1584 144 M270
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL res 464 208 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R12
SYMATTR Value 10k
SYMBOL res 352 384 R0
SYMATTR InstName R3
SYMATTR Value 23k
SYMBOL OpAmps\\opamp 560 16 R0
SYMATTR InstName U1
SYMBOL res 1312 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R7
SYMATTR Value 22k
SYMBOL res 1008 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 10k
SYMBOL res 448 256 R0
SYMATTR InstName R5
SYMATTR Value 470k
SYMBOL voltage 208 416 R0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 352 544 R0
SYMATTR InstName R4
SYMATTR Value 5k
FLAG 32 288 0
FLAG 192 544 0
FLAG 208 384 +15
FLAG 208 656 -15
FLAG 1184 208 0
FLAG 368 384 0
FLAG 592 192 0
FLAG 1536 208 0
FLAG 1808 208 0
TEXT -2 312 Left 2 !.dc V1 0 5 0.1
TEXT -600 496 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\0746cf1e61ce_Fig14_4.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout 0 0 0 N_50n l=50n w=500n
C1 Vout 0 50f
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 40u
.lib cmosedu_models.txt
* Plot Vout
.ic v(vout)=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3172 680
WIRE 272 -128 272 -176
WIRE 400 -176 272 -176
WIRE 448 -256 448 -304
WIRE 448 -112 448 -160
WIRE 592 -304 448 -304
WIRE 720 -304 592 -304
WIRE 720 -288 720 -304
WIRE 720 -192 720 -224
FLAG 448 -208 0
FLAG 448 -112 0
FLAG 272 -128 0
FLAG 720 -192 0
FLAG 592 -304 Vout
SYMBOL nmos4 400 -256 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL cap 704 -288 R0
SYMATTR InstName C1
SYMATTR Value 50f
TEXT 352 -72 Left 0 !.tran 40u
TEXT 352 -48 Left 0 !.lib cmosedu_models.txt
TEXT 288 -272 Left 0 ;Plot Vout
TEXT 496 -72 Left 0 !.ic v(vout)=1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2109-1.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2109-1.3.asy)
V1 IN 0 5
C1 OUT 0 10
Rload OUT 0 4
L1 N001 OUT 1
XU1 IN IN N001 OUT 0 ADP2109-x.x Rtop=128K ;pnba Vin)EN)SW)FB)GND
.tran .5m startup
.lib ADP2109-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 144
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL ADP2109-1.3 352 224 R0
SYMATTR InstName U1
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 4
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 576 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7185.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7185.asy)
V1 IN 0 -3.8
R2 N003 0 24.9k
R1 N002 N003 100k
C3 N002 0 1
C4 N004 0 1
C1 N002 N003 10n
XU1 OUT OUT N002 N003 N001 0 N004 IN ADP7185 ;pnba Vout)Sense)VA)VAFB)EN)GND)Vreg)Vin
V2 N001 0 1.5
RLOAD OUT 0 5
C2 OUT 0 4.7
.tran 20m startup
.lib ADP7185.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 680
WIRE 16 -48 0 -48
WIRE 112 -48 16 -48
WIRE 384 -48 368 -48
WIRE 416 -48 384 -48
WIRE 512 -48 416 -48
WIRE 528 -48 512 -48
WIRE 0 -32 0 -48
WIRE 416 -32 416 -48
WIRE 384 16 384 -48
WIRE 384 16 368 16
WIRE 416 48 416 32
WIRE 528 48 528 32
WIRE 0 64 0 48
WIRE 112 80 48 80
WIRE 416 80 368 80
WIRE 512 80 416 80
WIRE 576 80 512 80
WIRE 416 96 416 80
WIRE 512 96 512 80
WIRE 576 96 576 80
WIRE 48 112 48 80
WIRE 384 144 368 144
WIRE 384 192 384 144
WIRE 416 192 416 176
WIRE 416 192 384 192
WIRE 512 192 512 160
WIRE 512 192 416 192
WIRE 576 192 576 160
WIRE 48 208 48 192
WIRE 416 208 416 192
WIRE 176 224 176 208
WIRE 304 224 304 208
WIRE 176 304 176 288
WIRE 416 304 416 288
SYMBOL voltage 0 -48 R0
SYMATTR InstName V1
SYMATTR Value -3.8
SYMBOL cap 400 -32 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL cap 560 96 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 400 192 R0
SYMATTR InstName R2
SYMATTR Value 24.9k
SYMBOL cap 496 96 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage 48 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.5
SYMBOL ADP7185 240 48 R0
SYMATTR InstName U1
SYMBOL res 512 -64 R0
SYMATTR InstName RLOAD
SYMATTR Value 5
SYMBOL cap 160 224 R0
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 400 80 R0
SYMATTR InstName R1
SYMATTR Value 100k
FLAG 0 64 0
FLAG 416 48 0
FLAG 48 208 0
FLAG 304 224 0
FLAG 528 48 0
FLAG 16 -48 IN
FLAG 512 -48 OUT
FLAG 576 192 0
FLAG 176 304 0
FLAG 416 304 0
TEXT 240 352 Center 2 !.tran 20m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7182-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7182-2.5.asy)
XU1 OUT MP_01 MP_02 N001 MP_03 0 IN ADP7182-x.x Rset=500k ;pnba Vout)))EN))GND)Vin
C1 IN 0 2.2
R1 OUT 0 50
V2 N001 0 PULSE(0 2 200u 1n 1n 10m)
V1 IN 0 -8
C2 OUT 0 2.2
.tran 1m
.lib ADP7182-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 -80 -48
WIRE 112 -48 32 -48
WIRE 432 -48 368 -48
WIRE 544 -48 432 -48
WIRE -80 -32 -80 -48
WIRE 32 -32 32 -48
WIRE 432 -32 432 -48
WIRE 544 -32 544 -48
WIRE -80 64 -80 48
WIRE 32 64 32 32
WIRE 432 64 432 32
WIRE 544 64 544 48
WIRE 112 144 32 144
WIRE 32 160 32 144
WIRE 32 256 32 240
WIRE 240 256 240 208
SYMBOL cap 416 -32 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL voltage 32 144 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
SYMBOL ADP7182-2.5 240 48 R0
SYMATTR InstName U1
SYMBOL res 528 -48 R0
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value -8
SYMBOL cap 16 -32 R0
SYMATTR InstName C1
SYMATTR Value 2.2
FLAG -80 64 0
FLAG 32 64 0
FLAG 432 64 0
FLAG 32 256 0
FLAG 240 256 0
FLAG 544 64 0
FLAG 32 -48 IN
FLAG 432 -48 OUT
TEXT 528 248 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\1a614b5f408e_Ej1.asc
* Generated by LTspice 26.0.1 for Windows.
L1 0 N001 {31/14/Ww}
L3 Vo 0 {31/48/Ww} Rser=0
V1 Vg 0 AC 1
R1 N001 Vg 1
L4 Vo N001 {961/48/Ww} Rser=0
C2 Vo N001 {768/961/Ww}
R2 Vo 0 100000Meg
.ac dec 1000 0.001 100000
.param Ww = 2*pi
.net I(R2) V1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 32 224 32
WIRE -96 96 -144 96
WIRE 112 96 -16 96
WIRE 224 96 224 32
WIRE 224 96 112 96
WIRE 304 96 304 32
WIRE 368 96 304 96
WIRE 608 96 368 96
WIRE -144 144 -144 96
WIRE 112 144 112 96
WIRE 368 144 368 96
WIRE 608 144 608 96
WIRE 224 160 224 96
WIRE 304 160 304 96
WIRE -144 288 -144 224
WIRE 112 288 112 224
WIRE 112 288 -144 288
WIRE 256 288 112 288
WIRE 368 288 368 224
WIRE 368 288 256 288
WIRE 608 288 608 224
WIRE 608 288 368 288
WIRE 256 304 256 288
FLAG 256 304 0
FLAG 368 96 Vo
FLAG -144 96 Vg
SYMBOL ind 128 240 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value {31/14/Ww}
SYMBOL ind 352 128 R0
SYMATTR InstName L3
SYMATTR Value {31/48/Ww}
SYMATTR SpiceLine Rser=0
SYMBOL voltage -144 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 0 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL ind 320 144 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L4
SYMATTR Value {961/48/Ww}
SYMATTR SpiceLine Rser=0
SYMBOL cap 304 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {768/961/Ww}
SYMBOL res 592 128 R0
SYMATTR InstName R2
SYMATTR Value 100000Meg
TEXT -176 360 Left 2 !.ac dec 1000 0.001 100000
TEXT -168 408 Left 2 !.param Ww = 2*pi
TEXT -160 456 Left 2 !.net I(R2) V1
* Z:\tmp\asc_dec_bjh7r6w2\02f8fc9ff5c3_1638_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R1 OUT 0 2K
R2 +V N002 .2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -80 80 -80 64
WIRE -32 80 -80 80
WIRE 64 80 48 80
WIRE 288 80 64 80
WIRE -80 112 -80 80
WIRE -288 160 -288 144
WIRE 288 176 288 80
WIRE 128 192 128 176
WIRE -80 208 -80 192
WIRE -32 208 -80 208
WIRE 96 208 48 208
WIRE 224 224 160 224
WIRE -80 240 -80 208
WIRE 64 240 64 80
WIRE 96 240 64 240
WIRE -288 256 -288 240
WIRE 128 272 128 256
WIRE 288 288 288 272
WIRE 368 288 288 288
WIRE 288 304 288 288
WIRE 288 400 288 384
SYMBOL res 272 288 R0
SYMATTR InstName R1
SYMATTR Value 2K
SYMBOL res -96 96 R0
SYMATTR InstName R2
SYMATTR Value .2
FLAG -288 256 0
FLAG 128 176 +V
FLAG -288 144 +V
FLAG 128 272 0
FLAG 288 400 0
FLAG -80 64 +V
FLAG 368 288 OUT
* Z:\home\khalils\Downloads\files\data\raw_asc\0de55b386468_Tab9_1_ftn.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1)/I(vgs)
VGS N003 0 1.05V AC 1
VDS N001 0 250m
M1 N001 N003 0 N002 N_1u l=2u w=10u
VSB 0 N002 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.ac dec 100 1MEG 1G
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1128 680
WIRE 352 208 352 192
WIRE 352 304 352 288
WIRE 400 192 352 192
WIRE 448 112 448 80
WIRE 448 272 448 208
WIRE 704 160 448 160
WIRE 704 272 704 240
WIRE 848 80 448 80
WIRE 848 112 848 80
WIRE 848 224 848 192
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=2u w=10u
SYMBOL voltage 704 256 R180
WINDOW 0 -37 57 Right 0
WINDOW 3 -37 29 Right 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSB
SYMATTR Value 0
SYMBOL voltage 352 192 R0
WINDOW 0 -91 57 Left 0
WINDOW 3 -91 113 Left 0
WINDOW 123 -91 85 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 1.05V
SYMATTR Value2 AC 1
SYMBOL voltage 848 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 57 Left 0
WINDOW 3 40 85 Left 0
SYMATTR InstName VDS
SYMATTR Value 250m
FLAG 352 304 0
FLAG 448 272 0
FLAG 848 224 0
FLAG 704 272 0
TEXT 448 320 Left 0 !.ac dec 100 1MEG 1G
TEXT 448 344 Left 0 !.lib cmosedu_models.txt
TEXT 488 56 Left 0 ;Plot Id(M1)/I(vgs)
* Z:\tmp\asc_dec_bjh7r6w2\100ec9b23e07_Pre-charge_FET_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
V3 PRECHG_FET_EN N001 PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
M2 Vd N003 N004 N004 BSS123
R_SYSTEM CELL_10_POS N002 10
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5144 2508
WIRE 1216 656 1072 656
WIRE 1072 768 1072 656
WIRE 3024 928 2896 928
WIRE 1072 1024 1072 848
WIRE 3024 1104 3024 928
WIRE 3024 1376 3024 1184
WIRE 1664 1472 1664 1232
WIRE 1648 1520 1488 1520
WIRE 1792 1520 1744 1520
WIRE 1872 1520 1792 1520
SYMBOL voltage 1072 752 R0
SYMATTR InstName V3
SYMATTR Value PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
SYMBOL nmos 1744 1472 R90
SYMATTR InstName M2
SYMATTR Value BSS123
SYMBOL res 3008 1088 R0
SYMATTR InstName R_SYSTEM
SYMATTR Value 10
FLAG 1216 656 PRECHG_FET_EN
FLAG 2896 928 CELL_10_POS
FLAG 1792 1520 Vd
* Z:\tmp\asc_dec_bjh7r6w2\1065192f14ed_AND_SYM_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
M4 N002 Vin2 Vneg Vneg NMOS
M1 N001 Vin1 Vpos Vpos PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 -16 272 -48
WIRE 272 -16 176 -16
WIRE 416 -16 272 -16
WIRE 176 32 176 -16
WIRE 256 32 176 32
WIRE 256 80 256 32
WIRE 256 80 176 80
WIRE 176 144 176 128
WIRE 272 144 176 144
WIRE 416 144 272 144
WIRE 272 192 272 144
WIRE 544 192 272 192
WIRE 272 224 272 192
WIRE 352 272 272 272
WIRE 352 320 352 272
WIRE 352 320 272 320
WIRE 272 352 272 320
WIRE 352 400 272 400
WIRE 352 448 352 400
WIRE 352 448 272 448
WIRE 272 480 272 448
SYMBOL nmos4 224 352 R0
SYMATTR InstName M4
SYMBOL pmos4 128 128 M180
SYMATTR InstName M1
FLAG 272 -48 Vpos
FLAG 128 48 Vin1
FLAG 224 304 Vin1
FLAG 224 432 Vin2
FLAG 272 480 Vneg
* Z:\home\khalils\Downloads\files\data\raw_asc\15a4034c7b68_VoltageClamp.asc
* Generated by LTspice 26.0.1 for Windows.
D2 0 N001 CDZV15B
D1 N001 VB CDZV15B
V1 Vin 0 PULSE(12 60 0.1 0.1 0.2 0 1)
R1 Vin VB 1000R
R2 VOUT 0 R=if(abs(v(VOUT)), 10, (V(VOUT)**2)/0.4)
Q1 Vin VB VOUT 0 2SCR375P
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran .5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1000 680
WIRE 208 0 208 -48
WIRE 208 0 64 0
WIRE 336 0 208 0
WIRE 528 0 432 0
WIRE 560 0 528 0
WIRE 64 32 64 0
WIRE 528 48 528 0
WIRE 208 112 208 80
WIRE 384 112 384 64
WIRE 384 112 208 112
WIRE 432 112 384 112
WIRE 64 160 64 112
WIRE 352 176 256 176
WIRE 208 192 208 112
WIRE 352 192 352 176
WIRE 528 192 528 128
WIRE 208 272 208 256
WIRE 256 272 256 176
WIRE 256 272 208 272
WIRE 352 304 352 256
WIRE 352 304 208 304
SYMBOL npn 336 64 R270
SYMATTR InstName Q1
SYMATTR Value 2SCR375P
SYMBOL res 192 -16 R0
SYMATTR InstName R1
SYMATTR Value 1000R
SYMBOL voltage 64 16 R0
WINDOW 3 -201 -40 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(12 60 0.1 0.1 0.2 0 1)
SYMBOL zener 224 256 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value CDZV15B
SYMBOL zener 368 256 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value CDZV15B
SYMBOL res 512 32 R0
SYMATTR InstName R2
SYMATTR Value R=if(abs(v(VOUT)), 10, (V(VOUT)**2)/0.4)
FLAG 208 304 0
FLAG 528 192 0
FLAG 64 160 0
FLAG 560 0 VOUT
FLAG 432 112 VB
FLAG 208 -48 Vin
FLAG 688 192 0
TEXT -138 264 Left 2 !.tran .5
* Z:\home\khalils\Downloads\files\data\raw_asc\45499092219c_Draft9.asc
* Generated by LTspice 26.0.1 for Windows.
M1 vout vin 0 0 NMOS l=90nm w=Wn
M2 N001 vin vout N001 PMOS l=90nm w=Wp
C1 vout 0 50f
V2 N001 0 1.2
V1 vin 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.step param Wn 135nm 225nm 45nm
.step param Wp 405nm 495nm 45nm
.dc V1 0 1.2 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 32 192 32
WIRE 368 32 240 32
WIRE 192 48 192 32
WIRE 368 80 368 32
WIRE 240 96 240 32
WIRE 240 96 192 96
WIRE 144 128 128 128
WIRE 128 144 128 128
WIRE 128 144 16 144
WIRE 16 160 16 144
WIRE 368 176 368 160
WIRE 464 176 368 176
WIRE 192 192 192 144
WIRE 352 192 192 192
WIRE 400 192 352 192
WIRE 464 192 464 176
WIRE 352 208 352 192
WIRE 224 240 192 240
WIRE 400 256 400 192
WIRE 432 256 400 256
WIRE 128 272 128 144
WIRE 144 272 128 272
WIRE 16 288 16 240
WIRE 224 288 224 240
WIRE 224 288 192 288
WIRE 352 304 352 272
WIRE 384 304 352 304
WIRE 192 320 192 288
WIRE 384 320 384 304
IOPIN 432 256 Out
IOPIN 16 144 In
SYMBOL cap 336 208 R0
SYMATTR InstName C1
SYMATTR Value 50f
SYMBOL voltage 368 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.2
SYMBOL nmos4 144 192 R0
SYMATTR InstName M1
SYMATTR Value2 l=90nm w=Wn
SYMBOL pmos4 144 48 R0
SYMATTR InstName M2
SYMATTR Value2 l=90nm w=Wp
SYMBOL voltage 16 144 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
FLAG 192 320 0
FLAG 464 192 0
FLAG 384 320 0
FLAG 432 256 vout
FLAG 16 144 vin
FLAG 16 288 0
TEXT 328 16 Left 2 !.step param Wn 135nm 225nm 45nm
TEXT 416 112 Left 2 !.step param Wp 405nm 495nm 45nm
TEXT -24 24 Left 2 !.dc V1 0 1.2 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1764-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1764-1.2.asy)
C4 OUT 0 10
C2 N003 0 10n
V1 IN 0 1.5
C1 N004 0 1
R1 OUT 0 .6
R2 N001 IN 50K
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1764 Radj=8026.76 ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
C3 N002 0 1
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1016 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL voltage -128 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP1764-1.2 224 176 R0
SYMATTR InstName U1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 504 280 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7172-4.2.asc
* Generated by LTspice 26.0.1 for Windows.
C2 0 N001 1n
V1 IN 0 4.5
Rload OUT 0 3.5
C1 OUT 0 4.7 Rser=1.5m
XU1 IN OUT IN N001 OUT 0 ADM7172-4.2 ;pnba Vin)Sense)EN)SS)Vout)GND
.tran 5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7172-4.2.asy)
.lib ADM7172-4.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
SYMBOL cap 16 208 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 4.5
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 3.5
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1.5m
SYMBOL ADM7172-4.2 224 128 R0
SYMATTR InstName U1
TEXT 408 264 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\16189616f927_BatCutoff.asc
* Generated by LTspice 26.0.1 for Windows.
* Cutoff je na 9.2V
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1431.asy)
R5 N004 0 100
R4 N002 N001 {R1}
M1 N004 gate N002 N002 IRF7204
XU1 N003 NC_01 N003 NC_02 0 0 NC_03 N001 LT1431 ;pnba Coll)Comp)V+)Rtop)GND-S)GND-F)Rmid)Ref
R2 gate N003 1k
R3 N001 0 {R2}
R1 N002 N003 1k
V1 N002 0 12
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.param R1=73k
.param R2=100k-R1
.lib LT1431.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1364 680
WIRE 352 -464 -336 -464
WIRE -336 -384 -336 -464
WIRE -192 -384 -336 -384
WIRE -32 -384 -112 -384
WIRE 32 -384 -32 -384
WIRE 352 -384 112 -384
WIRE 480 -384 352 -384
WIRE 1152 -384 480 -384
WIRE -336 -256 -336 -384
WIRE 480 -208 480 -384
WIRE 1360 -192 1008 -192
WIRE 448 -128 16 -128
WIRE 480 -128 448 -128
WIRE 1152 -80 1152 -384
WIRE 1360 -64 1360 -192
WIRE 1360 -64 1200 -64
WIRE -32 -48 -32 -384
WIRE 368 -48 -32 -48
WIRE 448 0 448 -128
WIRE 736 0 448 0
WIRE 944 0 816 0
WIRE 1008 0 1008 -192
WIRE 1008 0 944 0
WIRE 16 64 16 -128
WIRE 16 64 -96 64
WIRE 48 64 16 64
WIRE 368 64 368 -48
WIRE 368 64 304 64
WIRE 1152 112 1152 16
WIRE -96 192 -96 64
WIRE 48 192 -96 192
WIRE 368 192 304 192
WIRE 368 256 368 192
WIRE 368 256 304 256
WIRE 1152 272 1152 192
WIRE 368 336 368 256
SYMBOL res 128 -400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {R1}
SYMBOL res 1136 96 R0
SYMATTR InstName R5
SYMATTR Value 100
SYMBOL pmos 1200 16 R180
SYMATTR InstName M1
SYMATTR Value IRF7204
SYMBOL voltage 352 -368 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL References\\LT1431 176 160 R0
SYMATTR InstName U1
SYMBOL res -96 -400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {R2}
SYMBOL res 832 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 464 -224 R0
SYMATTR InstName R1
SYMATTR Value 1k
FLAG 368 336 0
FLAG -336 -256 0
FLAG 944 0 gate
FLAG 1152 272 0
TEXT -448 -96 Left 2 !.tran 1
TEXT -344 -168 Left 2 !.param R1=73k\n.param R2=100k-R1
TEXT 400 -432 Left 2 ;Cutoff je na 9.2V