Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7182.asc
* Generated by LTspice 26.0.1 for Windows.
C1 IN 0 2.2
C2 OUT 0 2.2
V1 IN 0 -8
V2 N001 0 PULSE(0 2 200u 1n 1n 10m)
R3 OUT 0 50
R1 OUT N002 120k
R2 N002 0 120k
XU1 OUT MP_01 N002 N001 MP_02 0 IN ADP7182 ;pnba Vout))ADJ)EN))GND)Vin
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7182.asy)
.lib ADP7182.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 -80 -48
WIRE 112 -48 32 -48
WIRE 416 -48 368 -48
WIRE 496 -48 416 -48
WIRE 608 -48 496 -48
WIRE -80 -32 -80 -48
WIRE 32 -32 32 -48
WIRE 496 -32 496 -48
WIRE 608 -32 608 -48
WIRE 416 48 416 -48
WIRE -80 64 -80 48
WIRE 32 64 32 32
WIRE 496 64 496 32
WIRE 608 64 608 48
WIRE 112 144 32 144
WIRE 416 144 416 128
WIRE 416 144 368 144
WIRE 32 160 32 144
WIRE 416 160 416 144
WIRE 32 256 32 240
WIRE 240 256 240 208
WIRE 416 256 416 240
FLAG -80 64 0
FLAG 32 64 0
FLAG 496 64 0
FLAG 32 256 0
FLAG 240 256 0
FLAG 608 64 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 416 256 0
SYMBOL cap 16 -32 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL cap 480 -32 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value -8
SYMBOL voltage 32 144 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
SYMBOL res 592 -48 R0
SYMATTR InstName R3
SYMATTR Value 50
SYMBOL res 400 32 R0
SYMATTR InstName R1
SYMATTR Value 120k
SYMBOL res 400 144 R0
SYMATTR InstName R2
SYMATTR Value 120k
SYMBOL ADP7182 240 48 R0
SYMATTR InstName U1
TEXT 528 248 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4607.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N009 OUT 0 N001 IN N002 N003 N003 0 N006 N004 N010 N005 N011 IN N007 N008 0 0 NC_01 LTM4607 ;pnba FB)Vout)SGND)SW2)Vin)SW1)Rsense)Sense+)Sense-)Pgood)INTVcc)PLLFLTR)STBYMD)SS)Run)Comp)PLLIN)FCB)PGND)EXTVcc
L1 N001 N002 4.7
C1 OUT 0 330
R1 N003 0 7m
R2 0 N009 4.12K
V1 IN 0 15
C2 N011 0 .002
R3 N006 N004 100K
Rload OUT 0 8
.tran 100m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4607.asy)
.lib LTM4607.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 992 680
WIRE 208 -96 176 -96
WIRE 320 -96 288 -96
WIRE 176 -48 176 -96
WIRE 320 -48 320 -96
WIRE 32 16 -80 16
WIRE 64 16 32 16
WIRE 560 16 448 16
WIRE 656 16 560 16
WIRE -80 32 -80 16
WIRE 560 32 560 16
WIRE 656 32 656 16
WIRE 32 80 32 16
WIRE 64 80 32 80
WIRE 464 80 448 80
WIRE -80 128 -80 112
WIRE 560 128 560 96
WIRE 656 128 656 112
WIRE 480 144 448 144
WIRE 512 144 480 144
WIRE 512 160 512 144
WIRE 64 208 -48 208
WIRE 480 208 480 144
WIRE 480 208 448 208
WIRE -48 240 -48 208
WIRE 64 272 48 272
WIRE 512 272 512 240
WIRE 512 272 448 272
WIRE 512 288 512 272
WIRE -48 336 -48 320
WIRE 64 336 -48 336
WIRE 464 336 448 336
WIRE 64 400 48 400
WIRE 464 400 448 400
WIRE 560 400 544 400
WIRE 64 464 48 464
WIRE 496 464 448 464
WIRE 496 480 496 464
WIRE 176 544 176 528
WIRE 320 544 320 528
WIRE 496 560 496 544
FLAG 464 80 0
FLAG 560 128 0
FLAG 656 128 0
FLAG 560 400 0
FLAG 512 288 0
FLAG 320 544 0
FLAG 176 544 0
FLAG -80 128 0
FLAG 496 560 0
FLAG -80 16 IN
FLAG 656 16 OUT
SYMBOL PowerProducts\\LTM4607 256 240 R0
SYMATTR InstName U1
SYMBOL ind 192 -80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL cap 544 32 R0
SYMATTR InstName C1
SYMATTR Value 330
SYMBOL res 496 144 R0
SYMATTR InstName R1
SYMATTR Value 7m
SYMBOL res 560 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 4.12K
SYMBOL voltage -80 16 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL cap 480 480 R0
SYMATTR InstName C2
SYMATTR Value .002
SYMBOL res -64 336 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 640 16 R0
SYMATTR InstName Rload
SYMATTR Value 8
TEXT 584 480 Left 2 !.tran 100m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6231.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6231.asy)
XU1 N003 N001 N002 +V -V LT6231 ;pnba IN+)IN-)OUT)VCC)VEE
R2 N001 0 1K
V1 +V 0 5
V3 N003 0 SINE(0 1 1K)
R1 N002 N001 1K
V2 -V 0 -5
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -80 80 -96 80
WIRE 16 80 0 80
WIRE 32 80 16 80
WIRE 144 80 112 80
WIRE -368 160 -368 144
WIRE -240 160 -240 144
WIRE 80 192 80 176
WIRE 16 208 16 80
WIRE 48 208 16 208
WIRE 144 224 144 80
WIRE 144 224 112 224
WIRE 48 240 -64 240
WIRE -368 256 -368 240
WIRE -240 256 -240 240
WIRE -64 256 -64 240
WIRE 80 272 80 256
WIRE -64 352 -64 336
SYMBOL voltage -64 240 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL voltage -240 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -368 144 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 16 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 128 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL opamps\\LT6231 80 224 R0
SYMATTR InstName U1
FLAG -240 256 0
FLAG 80 176 +V
FLAG -240 144 +V
FLAG 80 272 -V
FLAG -368 256 0
FLAG -368 144 -V
FLAG -96 80 0
FLAG -64 352 0
TEXT 216 352 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3547B-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3547B-1.asy)
Rload1 OUT1 0 6
V1 IN 0 5
L2 N001 OUT2 4.7
L1 N002 OUT1 4.7
C2 OUT2 0 4.7
Rload2 OUT2 0 4
XU1 OUT1 IN IN N002 0 N001 IN OUT2 LTC3547B-1 ;pnba FB1)Run1)Vin)SW1)GND)SW2)Run2)FB2
C1 OUT1 0 4.7
.tran 800u startup
.lib LTC3547B-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 700
WIRE 272 48 -224 48
WIRE 352 48 272 48
WIRE 432 48 352 48
WIRE -224 64 -224 48
WIRE 272 80 272 48
WIRE 352 80 352 48
WIRE 432 80 432 48
WIRE 16 144 -112 144
WIRE 96 144 16 144
WIRE 112 144 96 144
WIRE 208 144 192 144
WIRE 512 144 496 144
WIRE 608 144 592 144
WIRE 672 144 608 144
WIRE 768 144 672 144
WIRE -224 160 -224 144
WIRE -112 160 -112 144
WIRE 16 160 16 144
WIRE 672 160 672 144
WIRE 768 160 768 144
WIRE -112 256 -112 240
WIRE 16 256 16 224
WIRE 672 256 672 224
WIRE 768 256 768 240
WIRE 96 288 96 144
WIRE 208 288 96 288
WIRE 608 288 608 144
WIRE 608 288 496 288
WIRE 352 368 352 336
SYMBOL res 752 144 R0
SYMATTR InstName Rload1
SYMATTR Value 6
SYMBOL PowerProducts\\LTC3547B-1 352 208 R0
SYMATTR InstName U1
SYMBOL res -128 144 R0
SYMATTR InstName Rload2
SYMATTR Value 4
SYMBOL VOLTAGE -224 48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 496 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL cap 656 160 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL ind 208 160 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 4.7
SYMBOL cap 0 160 R0
SYMATTR InstName C2
SYMATTR Value 4.7
FLAG -224 160 0
FLAG 352 368 0
FLAG -224 48 IN
FLAG 16 256 0
FLAG -112 256 0
FLAG 672 256 0
FLAG 768 256 0
FLAG 768 144 OUT1
FLAG -112 144 OUT2
TEXT 560 360 Left 2 !.tran 800u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\9bc83b8a31ff_buck_converter_hackathon.asc
* Generated by LTspice 26.0.1 for Windows.
* Buck Converter - Based on Zerowings_step1.slx
* Generated for Hackathon Submission
C1 N001 NC_05 2.2e-05
M1 N001 NC_01 Vout Vout MOSFET_SW
D1 NC_02 NC_03 DIODE_FWD
V_GATE Vout 0 PULSE(0 5 0 1n 1n 2.77778e-07 6.66667e-07)
V_IN N001 Vout 12
R_LOAD NC_06 NC_07 5
L1 N001 NC_04 1e-05
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL MOSFET_SW NMOS (Ron=0.15 Roff=1G Vto=2)
.MODEL DIODE_FWD D (Vfwd=0.6 Ron=1m Roff=1G)
.TRAN 6.66667e-09 3.33333e-05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 80 144 80
WIRE 272 80 176 80
WIRE 400 80 272 80
WIRE 144 96 144 80
WIRE 272 96 272 80
WIRE 176 128 176 80
WIRE 400 128 400 80
WIRE 144 192 144 176
WIRE 176 192 176 176
WIRE 176 192 144 192
WIRE 272 192 272 176
WIRE 272 192 176 192
WIRE 400 192 400 176
WIRE 400 192 272 192
WIRE 144 208 144 192
WIRE 144 304 144 288
SYMBOL cap 256 96 R0
SYMATTR InstName C1
SYMATTR Value 2.2e-05
SYMBOL diode 160 176 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value DIODE_FWD
SYMBOL nmos 224 96 R0
SYMATTR InstName M1
SYMATTR Value MOSFET_SW
SYMBOL ind 384 96 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value 1e-05
SYMBOL voltage 144 192 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V_GATE
SYMATTR Value PULSE(0 5 0 1n 1n 2.77778e-07 6.66667e-07)
SYMBOL res 384 192 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R_LOAD
SYMATTR Value 5
SYMBOL voltage 144 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V_IN
SYMATTR Value 12
FLAG 144 304 0
FLAG 400 192 Vout
TEXT 144 328 Left 2 !.MODEL MOSFET_SW NMOS (Ron=0.15 Roff=1G Vto=2)
TEXT 144 352 Left 2 !.MODEL DIODE_FWD D (Vfwd=0.6 Ron=1m Roff=1G)
TEXT 144 376 Left 2 !.TRAN 6.66667e-09 3.33333e-05
TEXT 144 32 Left 2 ;Buck Converter - Based on Zerowings_step1.slx
TEXT 144 48 Left 2 ;Generated for Hackathon Submission
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1037.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain 1000 Amplifier with .01% Accuracy
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1037.asy)
R2 N001 0 365
XU1 IN N001 +V -V OUT LT1037 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 15
R1 OUT N001 355K
V3 IN 0 SINE(0 1m 1)
V2 -V 0 -15
.tran 3
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 160 96 128 96
WIRE 272 96 240 96
WIRE -272 176 -272 160
WIRE -144 176 -144 160
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 272 240 272 96
WIRE 272 240 224 240
WIRE 304 240 272 240
WIRE 160 256 0 256
WIRE -272 272 -272 256
WIRE -144 272 -144 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 355K
SYMBOL voltage -272 160 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 365
SYMBOL opamps\\LT1037 192 176 R0
SYMATTR InstName U1
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1m 1)
SYMBOL voltage -144 160 R0
SYMATTR InstName V1
SYMATTR Value 15
FLAG -144 272 0
FLAG 192 192 +V
FLAG -144 160 +V
FLAG 192 288 -V
FLAG -272 272 0
FLAG -272 160 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 0 256 IN
FLAG 304 240 OUT
TEXT 232 352 Left 2 !.tran 3
TEXT 136 48 Bottom 2 ;Gain 1000 Amplifier with .01% Accuracy
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2139-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5
L1 N001 OUT 1 Rser=60m
Rload OUT 0 3
C1 OUT 0 10
XU1 IN IN N001 OUT 0 IN ADP2139-x.x Rtop=112K ;pnba Vin)EN)SW)Vout)GND)Mode
.tran .5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2139-1.2.asy)
.lib ADP2139-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 192 224 192 144
WIRE 208 224 192 224
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 224
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=60m
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 3
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADP2139-1.2 352 224 R0
SYMATTR InstName U1
TEXT 600 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\39a8af222f2a_Final_simulation_to_understand_the_V_A.asc
* Generated by LTspice 26.0.1 for Windows.
V1 NC_01 NC_02 12
V3 NC_03 NC_04 5
V2 NC_05 NC_06 5
V4 NC_07 NC_08 PULSE(0 5 0 1u 1u 5ms 10ms)
V5 NC_09 NC_10 PULSE(0 5 0 1u 1u 5ms 10ms)
V6 NC_11 NC_12 5
V7 NC_13 NC_14 0
V8 NC_15 NC_16 0
R1 NC_17 NC_18 10
R2 NC_19 NC_20 10
R3 NC_21 NC_22 1000
R4 NC_23 NC_24 1000
R5 NC_25 NC_26 1000
R6 NC_27 NC_28 1000
R8 NC_29 NC_30 10
R9 NC_31 NC_32 10
L1 NC_33 NC_34 100H
L2 NC_35 NC_36 100H
Q4 NC_37 NC_38 NC_39 0 NPN
Q1 NC_40 NC_41 NC_42 0 NPN
Q2 NC_43 NC_44 NC_45 0 NPN
Q3 NC_46 NC_47 NC_48 0 NPN
Q5 NC_49 NC_50 NC_51 0 NPN
D4 NC_52 NC_53 D
D1 NC_54 NC_55 D
D2 NC_56 NC_57 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 100ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1320 880

* Power Sources
SYMBOL voltage -112 144 R0
SYMATTR InstName V1
SYMATTR Value 12

SYMBOL voltage 16 384 R0
SYMATTR InstName V3
SYMATTR Value 5

SYMBOL voltage 272 -208 R90
SYMATTR InstName V2
SYMATTR Value 5

SYMBOL voltage 512 560 R90
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1u 1u 5ms 10ms)

SYMBOL voltage 352 -352 R90
SYMATTR InstName V5
SYMATTR Value PULSE(0 5 0 1u 1u 5ms 10ms)

SYMBOL voltage 848 -384 R0
SYMATTR InstName V6
SYMATTR Value 5

SYMBOL voltage 960 336 R0
SYMATTR InstName V7
SYMATTR Value 0

SYMBOL voltage 448 304 R0
SYMATTR InstName V8
SYMATTR Value 0

* Resistors
SYMBOL res 128 -128 R0
SYMATTR InstName R1
SYMATTR Value 10

SYMBOL res 128 48 R0
SYMATTR InstName R2
SYMATTR Value 10

SYMBOL res 400 -224 R90
SYMATTR InstName R3
SYMATTR Value 1000

SYMBOL res 608 304 R90
SYMATTR InstName R4
SYMATTR Value 1000

SYMBOL res 832 -240 R0
SYMATTR InstName R5
SYMATTR Value 1000

SYMBOL res 944 208 R0
SYMATTR InstName R6
SYMATTR Value 1000

SYMBOL res 736 208 R90
SYMATTR InstName R8
SYMATTR Value 10

SYMBOL res 1280 192 R90
SYMATTR InstName R9
SYMATTR Value 10

* Inductors
SYMBOL ind 752 128 R0
SYMATTR InstName L1
SYMATTR Value 100µH

SYMBOL ind 1056 -80 R0
SYMATTR InstName L2
SYMATTR Value 100µH

* Transistors
SYMBOL npn 224 352 R0
SYMATTR InstName Q4

SYMBOL npn 448 -256 R0
SYMATTR InstName Q1

SYMBOL npn 640 272 R0
SYMATTR InstName Q2

SYMBOL npn 864 -128 R0
SYMATTR InstName Q3

SYMBOL npn 976 112 R0
SYMATTR InstName Q5

* Diodes
SYMBOL diode 352 432 R180
SYMATTR InstName D4

SYMBOL diode 896 208 R180
SYMATTR InstName D1

SYMBOL diode 1184 0 R180
SYMATTR InstName D2

* Connections
FLAG -240 240 0
FLAG 160 528 0
FLAG 528 -80 0
FLAG 96 -192 0
FLAG 704 432 0
FLAG 928 48 0
FLAG 1040 272 0
FLAG 960 464 0
FLAG 752 -400 0

* Wires — skipped in this refined view for brevity, include in actual file if needed for full schematic

* Simulation Command
TEXT -256 552 Left 2 !.tran 100ms
* Z:\home\khalils\Downloads\files\data\raw_asc\2b6cc9ab6460_Circuit1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 0 1000
D1 N001 N002 D1N457A
V1 N001 0 SINE(0 5 60)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model D1N457A D(Is=1.3e-11 N=1.7 Rs=2 Cjo=8p Vj=0.7 M=0.33 Tt=4n Bv=70 Ibv=1e-4 Tnom=27)
.tran .1
.meas TRAN maxvout MAX v(n002)
.meas TRAN rmsvout RMS v(n002)
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1144 680
WIRE 192 112 96 112
WIRE 352 112 256 112
WIRE 96 144 96 112
WIRE 352 160 352 112
WIRE 96 288 96 224
WIRE 208 288 96 288
WIRE 352 288 352 240
WIRE 352 288 208 288
SYMBOL res 336 144 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL voltage 96 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 60)
SYMBOL diode 192 128 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value D1N457A
FLAG 208 288 0
TEXT -112 32 Left 2 !.model D1N457A D(Is=1.3e-11 N=1.7 Rs=2 Cjo=8p Vj=0.7 M=0.33 Tt=4n Bv=70 Ibv=1e-4 Tnom=27)
TEXT -112 296 Left 2 !.tran .1
TEXT 24 344 Left 2 !.meas TRAN maxvout MAX v(n002)
TEXT 48 440 Left 2 !.meas TRAN rmsvout RMS v(n002)
* Z:\home\khalils\Downloads\files\data\raw_asc\045f8464f180_OpAmpAmplifier.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1057.asy)
V1 0 N004 10V
R1 N001 0 11K tol=1 pwr=0.1
R2 N002 N001 100K tol=1 pwr=0.1
V3 IN 0 SINE(0 0.5 50)
V2 N003 0 10V
XU1 IN N001 N003 N004 N002 LT1057 ;pnba In+)In-)V+)V-)OUT
.tran 0 2 0
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -128 80 -128
WIRE 272 -128 224 -128
WIRE 352 -48 160 -48
WIRE 160 -16 160 -48
WIRE 80 0 80 -128
WIRE 128 0 80 0
WIRE 272 16 272 -128
WIRE 272 16 192 16
WIRE 480 16 272 16
WIRE -160 32 -192 32
WIRE 128 32 -160 32
WIRE -192 80 -192 32
WIRE 80 80 80 0
WIRE -192 176 -192 160
WIRE 80 192 80 160
WIRE 160 352 160 48
WIRE 256 352 240 352
WIRE 272 352 256 352
WIRE 352 352 352 -48
WIRE 256 432 256 352
SYMBOL Opamps\\LT1057 160 -48 R0
SYMATTR InstName U1
SYMBOL voltage 368 352 R90
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 10V
SYMBOL voltage -192 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 0.5 50)
SYMBOL res 64 64 R0
SYMATTR InstName R1
SYMATTR Value 11K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL voltage 256 352 R90
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 10V
SYMBOL res 240 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMATTR SpiceLine tol=1 pwr=0.1
FLAG 80 192 0
FLAG 256 432 0
FLAG 512 32 OUT
FLAG -160 32 IN
FLAG -192 176 0
TEXT -216 392 Left 2 !.tran 0 2 0
* Z:\home\khalils\Downloads\files\data\raw_asc\1af8a85453be_Flash_cells_parasitic_R.asc
* Generated by LTspice 26.0.1 for Windows.
VDD VDD 0 1
M1 VDD 0 0 0 N750 l=50n w=150n
R1 P001 0 100k
M2 VDD 0 P001 0 N750 l=50n w=150n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include flash_models.txt
.dc VDD 0 1 100u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2620 680
WIRE 432 -1520 432 -1552
WIRE 704 -1472 704 -1552
WIRE 960 -1472 960 -1552
WIRE 752 -1424 704 -1424
WIRE 1056 -1424 960 -1424
WIRE 432 -1408 432 -1440
WIRE 656 -1392 640 -1392
WIRE 912 -1392 896 -1392
WIRE 640 -1344 640 -1392
WIRE 704 -1344 704 -1376
WIRE 752 -1344 752 -1424
WIRE 896 -1344 896 -1392
WIRE 1056 -1344 1056 -1424
WIRE 960 -1280 960 -1296
SYMBOL voltage 432 -1536 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 40 53 Left 0
SYMATTR Value 1
SYMATTR InstName VDD
SYMBOL nmos4 656 -1472 R0
WINDOW 0 64 -33 Left 0
WINDOW 3 65 -6 Left 0
WINDOW 123 65 19 Left 0
SYMATTR InstName M1
SYMATTR Value N750
SYMATTR Value2 l=50n w=150n
SYMBOL res 944 -1392 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL nmos4 912 -1472 R0
WINDOW 0 64 -33 Left 0
WINDOW 3 65 -6 Left 0
WINDOW 123 65 19 Left 0
SYMATTR InstName M2
SYMATTR Value N750
SYMATTR Value2 l=50n w=150n
FLAG 432 -1408 0
FLAG 432 -1552 VDD
FLAG 704 -1344 0
FLAG 640 -1344 0
FLAG 752 -1344 0
FLAG 704 -1552 VDD
FLAG 960 -1280 0
FLAG 896 -1344 0
FLAG 1056 -1344 0
FLAG 960 -1552 VDD
TEXT 344 -1304 Left 0 !.include flash_models.txt
TEXT 344 -1368 Left 0 !.dc VDD 0 1 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3071.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3071.asy)
C1 0 N006 .01
R2 N001 N002 50K
XU1 0 N001 0 0 N001 N006 N004 N003 IN OUT OUT N001 N005 N002 LT3071 ;pnba GND)VO0)VO1)VO2)Bias)REF/BYP)MargA)Imon)IN)Sense)OUT)EN)VIOC)PWRGD
R1 OUT 0 .18
V2 IN 0 1.2
C2 0 N005 .01
C3 OUT 0 20
V1 N001 0 3
R3 0 N003 1K
.tran 2m startup
.lib LT3071.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1156 680
WIRE 432 -48 96 -48
WIRE 576 -48 432 -48
WIRE 432 -32 432 -48
WIRE 576 -32 576 -48
WIRE 256 0 -112 0
WIRE -112 16 -112 0
WIRE 256 16 256 0
WIRE 96 64 96 -48
WIRE 112 64 96 64
WIRE 432 64 432 48
WIRE 432 64 400 64
WIRE 576 64 576 48
WIRE -112 112 -112 96
WIRE 96 128 96 64
WIRE 112 128 96 128
WIRE 928 128 400 128
WIRE 928 144 928 128
WIRE 96 192 96 128
WIRE 112 192 96 192
WIRE 832 192 928 128
WIRE 832 192 400 192
WIRE 832 208 832 192
WIRE 928 240 928 224
WIRE 112 256 96 256
WIRE 416 256 400 256
WIRE 528 256 496 256
WIRE 832 288 832 272
WIRE 112 320 96 320
WIRE 416 320 400 320
WIRE 32 384 16 384
WIRE 112 384 96 384
WIRE 416 384 400 384
WIRE 496 384 480 384
WIRE 256 432 256 416
SYMBOL cap 32 400 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL PowerProducts\\LT3071 256 224 R0
SYMATTR InstName U1
SYMBOL res 416 -48 R0
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL res 912 128 R0
SYMATTR InstName R1
SYMATTR Value .18
SYMBOL res 512 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL cap 816 208 R0
WINDOW 3 26 56 Left 2
SYMATTR Value 20
SYMATTR InstName C3
SYMBOL cap 480 368 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .01
SYMBOL voltage -112 0 R0
SYMATTR InstName V2
SYMATTR Value 1.2
SYMBOL voltage 576 -48 R0
SYMATTR InstName V1
SYMATTR Value 3
FLAG 496 384 0
FLAG 256 432 0
FLAG 96 320 0
FLAG 96 256 0
FLAG -112 112 0
FLAG 576 64 0
FLAG 16 384 0
FLAG 832 288 0
FLAG 928 240 0
FLAG -112 0 IN
FLAG 928 128 OUT
FLAG 528 256 0
TEXT 512 336 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD797.asc
* Generated by LTspice 26.0.1 for Windows.
RF OUT N001 10k
RG N001 IN 10k
V1 V+ 0 15
V2 V- 0 -15
V3 IN 0 SINE(0 10 1k)
R1 OUT 0 600
XU1 0 N001 V+ V- OUT AD797 ;pnba In+)In-)V+)V-)OUT
.tran 5m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD797.asy)
.lib AD797.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1668 868
WIRE -128 16 -144 16
WIRE -48 16 -128 16
WIRE 64 16 32 16
WIRE 112 16 64 16
WIRE 240 16 192 16
WIRE -144 32 -144 16
WIRE -352 48 -368 48
WIRE -240 48 -256 48
WIRE -368 80 -368 48
WIRE -256 80 -256 48
WIRE -144 128 -144 112
WIRE 144 128 144 112
WIRE 64 144 64 16
WIRE 112 144 64 144
WIRE 240 160 240 16
WIRE 240 160 176 160
WIRE 256 160 240 160
WIRE -368 176 -368 160
WIRE -256 176 -256 160
WIRE 112 176 64 176
WIRE 240 192 240 160
WIRE 144 208 144 192
WIRE 240 304 240 272
WIRE 64 352 64 176
FLAG -368 176 0
FLAG -256 176 0
FLAG -256 48 V-
FLAG -368 48 V+
FLAG 144 112 V+
FLAG 144 208 V-
FLAG 64 352 0
FLAG -144 128 0
FLAG 240 304 0
FLAG 256 160 OUT
FLAG -128 16 IN
SYMBOL res 208 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RF
SYMATTR Value 10k
SYMBOL res 48 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG
SYMATTR Value 10k
SYMBOL voltage -368 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -256 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -144 16 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 10 1k)
SYMBOL res 224 176 R0
SYMATTR InstName R1
SYMATTR Value 600
SYMBOL AD797 144 96 R0
SYMATTR InstName U1
TEXT -344 -72 Left 2 !.tran 5m