Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2b3f64cdfea6_mux.asc
* Generated by LTspice 26.0.1 for Windows.
M4 N001 Vs Vs_bar N001 PMOS l=180nm w=810nm
M1 Vout Vs Va 0 NMOS l=180nm w=270nm
Vb Vb 0 PULSE(0 1.8 0 0.1n 0.1n 10n 20n)
Vs Vs 0 PULSE(0 1.8 0 0.1n 0.1n 20n 40n)
M2 Vs_bar Vs 0 0 NMOS l=180nm w=270nm
V1 N001 0 1.8
C1 Vout 0 50f
Va Va 0 PULSE(1.8 0 0 0.1n 0.1n 10n 20n)
M3 Vout Vs_bar Vb 0 NMOS l=180nm w=270nm
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 100n 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 756
WIRE 384 16 208 16
WIRE 416 16 384 16
WIRE 208 64 208 16
WIRE 208 64 112 64
WIRE 304 64 208 64
WIRE 112 80 112 64
WIRE 304 80 304 64
WIRE 0 112 -64 112
WIRE 16 112 0 112
WIRE 16 160 16 112
WIRE 64 160 16 160
WIRE 496 160 352 160
WIRE 112 192 112 176
WIRE 304 192 304 176
WIRE 112 208 112 192
WIRE 304 208 304 192
WIRE 160 416 128 416
WIRE 224 416 160 416
WIRE 128 496 128 416
WIRE 160 544 160 416
WIRE 160 544 128 544
WIRE 80 576 48 576
WIRE 496 592 496 160
WIRE 496 592 128 592
WIRE 16 624 16 160
WIRE 48 624 48 576
WIRE 48 624 16 624
WIRE 160 640 128 640
WIRE 48 672 48 624
WIRE 80 672 48 672
WIRE 128 720 128 688
WIRE 144 720 128 720
WIRE 160 720 160 640
WIRE 160 720 144 720
WIRE 144 736 144 720
IOPIN 416 16 Out
IOPIN 112 192 In
IOPIN 304 192 In
IOPIN 0 112 In
IOPIN 496 160 In
SYMBOL voltage 224 400 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL nmos4 64 80 R0
SYMATTR InstName M1
SYMATTR Value2 l=180nm w=270nm
SYMBOL pmos4 80 496 R0
SYMATTR InstName M4
SYMATTR Value2 l=180nm w=810nm
SYMBOL voltage -64 96 R0
WINDOW 0 -11 56 Left 2
WINDOW 3 -290 126 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vs
SYMATTR Value PULSE(0 1.8 0 0.1n 0.1n 20n 40n)
SYMBOL voltage 112 192 R0
WINDOW 0 -11 55 Left 2
WINDOW 3 -271 141 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Va
SYMATTR Value PULSE(1.8 0 0 0.1n 0.1n 10n 20n)
SYMBOL voltage 304 192 R0
WINDOW 0 -12 57 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vb
SYMATTR Value PULSE(0 1.8 0 0.1n 0.1n 10n 20n)
SYMBOL nmos4 80 592 R0
SYMATTR InstName M2
SYMATTR Value2 l=180nm w=270nm
SYMBOL nmos4 352 80 M0
SYMATTR InstName M3
SYMATTR Value2 l=180nm w=270nm
SYMBOL cap 368 16 R0
WINDOW 0 -18 14 Left 2
SYMATTR InstName C1
SYMATTR Value 50f
FLAG 416 16 Vout
FLAG 112 128 0
FLAG 304 128 0
FLAG -64 192 0
FLAG 304 288 0
FLAG 112 288 0
FLAG 384 80 0
FLAG 112 192 Va
FLAG 304 192 Vb
FLAG 0 112 Vs
FLAG 144 736 0
FLAG 224 496 0
FLAG 496 160 Vs_bar
TEXT -144 272 Left 2 !.tran 0 100n 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-SD.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10
Rload OUT 0 500
XU1 IN 0 IN OUT OUT LT1761-SD ;pnba IN)GND)_SHDN)ADJ)OUT
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-SD.asy)
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 16 48 0 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 336 144 336 48
WIRE 336 144 304 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -208 48 IN
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT1761-SD 160 96 R0
SYMATTR InstName U1
TEXT 368 232 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1175-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1175-5.asy)
XU1 IN IN OUT OUT 0 N001 IN LT1175-5 ;pnba Vin)Ilim2)Output)Sense)GND)_SHDN)Ilim4
C1 0 OUT 1 Rser=1
Rload 0 OUT 100
V1 IN 0 -5
.tran 1m startup
.lib LT1175-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1236 680
WIRE 144 80 144 64
WIRE 304 80 304 64
WIRE 48 144 -80 144
WIRE 80 144 48 144
WIRE 400 144 368 144
WIRE 464 144 400 144
WIRE 576 144 464 144
WIRE -80 160 -80 144
WIRE 576 160 576 144
WIRE 464 176 464 144
WIRE 48 240 48 144
WIRE 80 240 48 240
WIRE -80 256 -80 240
WIRE 464 256 464 240
WIRE 576 256 576 240
WIRE 48 336 48 240
WIRE 80 336 48 336
WIRE 400 336 400 144
WIRE 400 336 368 336
SYMBOL PowerProducts\\LT1175-5 224 240 R0
SYMATTR InstName U1
SYMBOL res 560 256 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 448 240 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 1
SYMATTR SpiceLine Rser=1
SYMBOL voltage -80 144 R0
SYMATTR InstName V1
SYMATTR Value -5
FLAG 304 64 0
FLAG -80 256 0
FLAG 576 256 0
FLAG 464 256 0
FLAG 576 144 OUT
FLAG -80 144 IN
TEXT 424 384 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\364a78e875d1_6554.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6554.asy)
V1 +V 0 5
R1 0 OUTR 1K
V3 IN 0 SIN(0 1 10Meg) AC 1
XU1 0 0 +V -V IN 0 0 OUTR OUTG OUTB LT6554 ;pnba _EN)DGND)V+)V-)INR)ING)INB)OUTR)OUTG)OUTB
V2 -V 0 -5
C1 0 OUTR .1p
.ac dec 50 10Meg 1G
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1076 884
WIRE 336 432 336 384
WIRE 240 480 -80 480
WIRE 640 496 432 496
WIRE 736 496 640 496
WIRE 848 496 736 496
WIRE -80 512 -80 480
WIRE 640 512 640 496
WIRE 736 512 736 496
WIRE 240 544 192 544
WIRE 512 592 432 592
WIRE 240 608 128 608
WIRE 640 608 640 592
WIRE 736 608 736 576
WIRE -80 624 -80 592
WIRE 192 640 192 544
WIRE 240 640 192 640
WIRE 192 672 192 640
WIRE 512 688 432 688
WIRE 128 704 128 608
WIRE 240 704 128 704
WIRE 128 736 128 704
WIRE -176 752 -176 720
WIRE -64 752 -64 720
WIRE 272 784 272 752
WIRE 336 784 336 752
WIRE 400 784 400 752
WIRE -176 864 -176 832
WIRE -64 864 -64 832
SYMBOL voltage -64 736 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL cap 720 576 M180
WINDOW 0 24 64 Left 0
WINDOW 3 24 8 Left 0
SYMATTR InstName C1
SYMATTR Value .1p
SYMBOL LT6554 336 512 R0
SYMATTR InstName U1
SYMBOL voltage -80 496 R0
WINDOW 123 38 64 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR Value SIN(0 1 10Meg)
SYMATTR InstName V3
SYMBOL voltage -176 736 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 624 608 M180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R1
SYMATTR Value 1K
FLAG -176 864 0
FLAG -64 864 0
FLAG 336 384 +V
FLAG 192 672 0
FLAG -80 624 0
FLAG -80 480 IN
FLAG 848 496 OUTR
FLAG 512 592 OUTG
FLAG 512 688 OUTB
FLAG 128 736 0
FLAG -176 720 +V
FLAG -64 720 -V
FLAG 400 784 -V
FLAG 272 784 0
FLAG 336 784 0
FLAG 640 608 0
FLAG 736 608 0
TEXT 544 776 Left 0 !.ac dec 50 10Meg 1G
* Z:\home\khalils\Downloads\files\data\raw_asc\2c75be78e3d9_Fig_2-63_BI_BI2.asc
* Generated by LTspice 26.0.1 for Windows.
B1 0 V-B1 I=V(Cont)/1K
R1 V-B1 0 10K
B2 V-B2 0 I=V(Cont)/10K
R2 V-B2 0 100K
V1 Cont 0 SINE(0 1 1K)
.tran 5m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 96 256 64
WIRE 256 96 160 96
WIRE 352 96 256 96
WIRE 160 128 160 96
WIRE 352 128 352 96
WIRE -112 208 -112 176
WIRE 160 256 160 208
WIRE 352 256 352 208
WIRE 160 272 160 256
WIRE 352 272 352 256
WIRE -112 320 -112 288
WIRE 160 384 160 352
WIRE 256 384 160 384
WIRE 352 384 352 352
WIRE 352 384 256 384
WIRE 256 400 256 384
SYMBOL bi 160 128 R0
SYMATTR InstName B1
SYMATTR Value I=V(Cont)/1K
SYMBOL bi2 352 128 R0
SYMATTR InstName B2
SYMATTR Value I=V(Cont)/10K
SYMBOL res 336 256 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 144 256 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -112 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1K)
FLAG 256 400 0
FLAG -112 320 0
FLAG -112 176 Cont
FLAG 256 64 0
FLAG 160 256 V-B1
FLAG 352 256 V-B2
TEXT -136 368 Left 2 !.tran 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\3526a6f947c7_part2_a_2.asc
* Generated by LTspice 26.0.1 for Windows.
VDS drain 0 {X}
VGS gate 0 10
M1 drain gate 0 0 NMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model nmos NMOS (kp=100u, vt0=0.5, l=0.18, w=.36u)
.dc VGS 0 10 0.01
.step param X list 1 2 3 5 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 48 96 48
WIRE 240 48 160 48
WIRE 96 112 96 48
WIRE 240 144 240 48
WIRE -64 192 -96 192
WIRE 48 192 -64 192
WIRE -96 208 -96 192
WIRE -96 336 -96 288
WIRE 96 336 96 208
WIRE 96 336 -96 336
WIRE 176 336 96 336
WIRE 240 336 240 224
WIRE 240 336 176 336
SYMBOL voltage -96 192 R0
SYMATTR InstName VGS
SYMATTR Value 10
SYMBOL nmos 48 112 R0
SYMATTR InstName M1
SYMBOL voltage 240 128 R0
SYMATTR InstName VDS
SYMATTR Value {X}
FLAG 96 336 0
FLAG -64 192 gate
FLAG 160 48 drain
FLAG 176 336 source
TEXT -104 376 Left 2 !.model nmos NMOS (kp=100u, vt0=0.5, l=0.18, w=.36u)
TEXT -104 408 Left 2 !.dc VGS 0 10 0.01
TEXT -104 440 Left 2 !.step param X list 1 2 3 5 10
* Z:\home\khalils\Downloads\files\data\raw_asc\529d58fe383c_parte1.asc
* Generated by LTspice 26.0.1 for Windows.
Vgs N002 0 1
M1 N001 N002 0 0 N_1u l=1u w=3u
Vds N001 0 2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vds 0 5 0.01 Vgs 0 5 0.5
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 80 256 80
WIRE 304 128 256 128
WIRE 208 160 32 160
WIRE 32 176 32 160
WIRE 304 176 304 128
WIRE 304 176 256 176
WIRE 448 192 448 80
WIRE 256 224 256 176
WIRE 32 288 32 256
WIRE 448 320 448 272
SYMBOL nmos4 208 80 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=3u
SYMBOL voltage 448 176 R0
SYMATTR InstName Vds
SYMATTR Value 2
SYMBOL voltage 32 160 R0
SYMATTR InstName Vgs
SYMATTR Value 1
FLAG 32 288 0
FLAG 256 224 0
FLAG 448 320 0
TEXT 104 296 Left 2 !.dc Vds 0 5 0.01 Vgs 0 5 0.5
TEXT 72 48 Left 2 !.include cmosedu_models.txt
* Z:\home\khalils\Downloads\files\data\raw_asc\3d387dd337e7_column_vias.asc
* Generated by LTspice 26.0.1 for Windows.
M5 N005 N001 0 0 NMOS l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
V1 N001 0 1.5
M10 vd N001 N002 0 NMOS l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
M7 N003 N001 N004 0 NMOS l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
M8 N002 N001 N003 0 NMOS l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
V2 vd 0 1.5
M6 N004 N001 N005 0 NMOS l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include C5_models.txt
.param Lbias = 3.9u, Wbias = 5.4u
.dc V2 0 5 1m
.param Ld = 1.2u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 964 680
WIRE 240 -368 240 -400
WIRE 416 -368 240 -368
WIRE 416 -352 416 -368
WIRE 368 -272 288 -272
WIRE 416 -224 416 -256
WIRE 288 -144 288 -272
WIRE 288 -144 64 -144
WIRE 368 -144 288 -144
WIRE 416 -112 416 -128
WIRE 288 -32 288 -144
WIRE 368 -32 288 -32
WIRE 64 0 64 -144
WIRE 416 16 416 -16
WIRE 288 96 288 -32
WIRE 368 96 288 96
WIRE 416 160 416 112
WIRE 288 240 288 96
WIRE 368 240 288 240
SYMBOL voltage -128 -16 R0
SYMATTR InstName V2
SYMATTR Value 1.5
SYMBOL nmos4 368 16 R0
SYMATTR InstName M6
SYMATTR Value2 l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
SYMBOL voltage 64 -16 R0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL nmos4 368 -224 R0
SYMATTR InstName M8
SYMATTR Value2 l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
SYMBOL nmos4 368 -352 R0
SYMATTR InstName M10
SYMATTR Value2 l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
SYMBOL nmos4 368 -112 R0
SYMATTR InstName M7
SYMATTR Value2 l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
SYMBOL nmos4 368 160 R0
SYMATTR InstName M5
SYMATTR Value2 l='Lbias' w='Wbias' ad='Wbias*Ld' as='Wbias*Ld' pd='2*Wbias+2*Ld' ps='2*Wbias+2*Ld' m=1
FLAG 64 80 0
FLAG 240 -400 vd
FLAG 416 256 0
FLAG 416 208 0
FLAG 416 64 0
FLAG 416 -64 0
FLAG 416 -176 0
FLAG -128 80 0
FLAG -128 0 vd
FLAG 416 -304 0
TEXT 552 -192 Left 2 !.include C5_models.txt
TEXT 552 -160 Left 2 !.param Lbias = 3.9u, Wbias = 5.4u
TEXT 552 -128 Left 2 !.dc V2 0 5 1m
TEXT 664 -104 Left 2 !.param Ld = 1.2u
* Z:\tmp\asc_dec_bjh7r6w2\023c31ee5f48_CMOS-Inveneter_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Vin G1 0 0.69 AC 1
Iref N002 0 1.6m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1744 680
WIRE 352 32 352 -240
WIRE 352 32 304 32
WIRE 352 64 352 32
WIRE 512 80 400 80
WIRE 592 80 512 80
WIRE 304 112 304 32
WIRE 352 112 304 112
WIRE 672 144 672 96
WIRE 864 144 672 144
WIRE 512 160 512 80
WIRE 512 160 352 160
WIRE 672 160 672 144
WIRE 352 176 352 160
WIRE 352 192 352 176
WIRE 672 192 672 160
WIRE 576 256 512 256
WIRE 592 256 576 256
WIRE 592 272 592 256
WIRE 624 272 592 272
WIRE 352 288 352 256
WIRE 512 320 512 256
WIRE 672 336 672 288
WIRE 512 448 512 400
WIRE 672 448 672 336
SYMBOL voltage 512 304 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 2
SYMATTR Value2 AC 1
SYMATTR Value 0.69
SYMATTR InstName Vin
SYMBOL current 352 176 R0
WINDOW 123 24 108 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName Iref
SYMATTR Value 1.6m
FLAG 672 336 S1
FLAG 672 160 D
FLAG 512 448 0
FLAG 672 448 0
FLAG 352 288 0
FLAG 576 256 G1
* Z:\home\khalils\Downloads\files\data\raw_asc\19109452a74e_1991.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1991.asy)
V2 +V 0 +5
V4 N001 0 SINE(0 .1 100)
V1 -V 0 -5
XU1 N001 NC_01 NC_02 -V 0 OUT +V NC_03 NC_04 0 LT1991 ;pnba P1)P3)P9)Vee)Ref)OUT)VCC)M9)M3)M1
.tran .1
.lib LT1991.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1156 980
WIRE 496 400 400 400
WIRE 144 432 144 400
WIRE 320 432 320 416
WIRE 400 432 400 400
WIRE -144 528 -144 512
WIRE -16 528 -16 512
WIRE -144 624 -144 608
WIRE -16 624 -16 608
WIRE 320 704 320 688
WIRE 400 720 400 688
WIRE 144 752 144 688
WIRE 144 848 144 832
SYMBOL voltage -144 512 R0
SYMATTR InstName V1
SYMATTR Value -5
SYMBOL opamps\\LT1991 320 560 R0
SYMATTR InstName U1
SYMBOL voltage -16 512 R0
SYMATTR InstName V2
SYMATTR Value +5
SYMBOL voltage 144 736 R0
SYMATTR InstName V4
SYMATTR Value SINE(0 .1 100)
FLAG -16 624 0
FLAG -144 624 0
FLAG -144 512 -V
FLAG -16 512 +V
FLAG 320 416 +V
FLAG 320 704 -V
FLAG 400 720 0
FLAG 144 400 0
FLAG 144 848 0
FLAG 496 400 OUT
TEXT 328 784 Left 0 !.tran .1
* Z:\home\khalils\Downloads\files\data\raw_asc\78987b9b5bfc_transient_ideal.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
V1 N003 0 1.25
XU1 N002 Vc N001 0 Vc level2 Avol=1500 GBW=40Meg Slew=10Meg Ilimit=35m Rail=0.2 Vos=200m En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R1 N002 N003 10k
C1 Vc 0 2.3p
V2 N001 0 1.8
.tran 70n
.ic V(n002)=1
.ic V(vc)=1
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1008 680
WIRE 160 -48 -80 -48
WIRE 272 64 80 64
WIRE -80 112 -80 -48
WIRE 160 128 160 -48
WIRE 80 144 80 64
WIRE 128 144 80 144
WIRE 272 160 272 64
WIRE 272 160 192 160
WIRE 448 160 272 160
WIRE 128 176 80 176
WIRE 80 208 80 176
WIRE 160 208 160 192
WIRE 448 208 448 160
WIRE -80 224 -80 192
WIRE 448 304 448 272
WIRE 80 320 80 288
WIRE 80 432 80 400
SYMBOL voltage 80 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.25
SYMBOL OpAmps\\UniversalOpAmp2 160 160 R0
SYMATTR InstName U1
SYMATTR Value2 Avol=1500 GBW=40Meg Slew=10Meg
SYMATTR SpiceLine Ilimit=35m Rail=0.2 Vos=200m
SYMBOL cap 432 208 R0
SYMATTR InstName C1
SYMATTR Value 2.3p
SYMBOL voltage -80 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL res 64 192 R0
SYMATTR InstName R1
SYMATTR Value 10k
FLAG 80 432 0
FLAG 160 208 0
FLAG -80 224 0
FLAG 448 304 0
FLAG 448 160 Vc
TEXT -112 456 Left 2 !.tran 70n
TEXT 360 104 Left 2 !.ic V(n002)=1
TEXT 368 64 Left 2 !.ic V(vc)=1
* Z:\home\khalils\Downloads\files\data\raw_asc\19c18b4abba1_mod_anello_dopp_basic.asc
* Generated by LTspice 26.0.1 for Windows.
* utile per FFT
D4 N006 N005 D
R1 N002 0 1k
D1 N005 N001 D
D2 N001 N002 D
V3 N004 N006 200m
D3 N002 N006 D
R3 0 N005 1k
V2 N007 0 SINE(0 3 10 0 0 90)
V1 N001 N004 200m
E1 N003 0 N002 N005 1
R2 N007 N004 100
R4 N003 0 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.8
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1172 680
WIRE 208 -48 -32 -48
WIRE 336 -48 208 -48
WIRE 512 -48 384 -48
WIRE 592 -48 512 -48
WIRE 1104 -48 688 -48
WIRE 512 -16 512 -48
WIRE -32 0 -32 -48
WIRE 208 0 208 -48
WIRE 336 0 336 -48
WIRE 208 16 208 0
WIRE 336 16 336 0
WIRE 688 80 688 -48
WIRE 1104 80 1104 -48
WIRE -32 96 -32 80
WIRE 48 96 -32 96
WIRE 208 96 208 64
WIRE 208 96 144 96
WIRE 336 96 336 64
WIRE 384 96 384 -48
WIRE 384 96 336 96
WIRE 512 96 512 64
WIRE 512 96 448 96
WIRE 592 96 592 -48
WIRE 640 96 592 96
WIRE -32 128 -32 96
WIRE 208 128 208 96
WIRE 336 128 336 96
WIRE 512 144 512 96
WIRE -32 240 -32 208
WIRE 208 240 208 192
WIRE 208 240 -32 240
WIRE 336 240 336 192
WIRE 336 240 208 240
WIRE 144 272 144 96
WIRE 512 272 512 224
WIRE 512 272 144 272
WIRE 640 272 640 144
WIRE 640 272 512 272
WIRE 688 272 688 160
WIRE 928 272 688 272
WIRE 1104 272 1104 160
WIRE 1104 272 928 272
WIRE 928 304 928 272
WIRE 48 368 48 96
WIRE 112 368 48 368
WIRE 256 368 192 368
WIRE 448 368 448 96
WIRE 448 368 336 368
WIRE 448 416 448 368
SYMBOL res 496 128 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL diode 320 128 R0
SYMATTR InstName D3
SYMBOL diode 224 64 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL res 1088 64 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL e 688 64 R0
SYMATTR InstName E1
SYMATTR Value ""
SYMATTR SpiceLine2 1
SYMBOL Misc\\signal 240 368 R270
WINDOW 0 -32 56 VBottom 2
WINDOW 3 -93 52 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 3 10 0 0 90)
SYMBOL diode 224 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMBOL diode 320 0 R0
SYMATTR InstName D2
SYMBOL res 208 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL res 496 -32 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -32 112 R0
WINDOW 3 -73 93 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -73 121 Left 2
SYMATTR Value 200m
SYMATTR InstName V3
SYMBOL voltage -32 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -70 113 Left 2
WINDOW 3 -70 85 Left 2
SYMATTR Value 200m
SYMATTR InstName V1
FLAG 448 416 0
FLAG 928 304 0
TEXT -176 336 Left 2 !.tran 0.8
TEXT 688 -80 Left 2 ;utile per FFT
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL40502-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL40502-2.5.asy)
Rload vOUT 0 12.5
C1 vOUT 0 1 Rser=1m
XU1 vIN 0 vIN vOUT ADPL40502-2.5 ;pnba Vin)GND)EN)Vout
V1 vIN 0 3.3
.tran 1m startup
.lib ADPL40502-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2808 1464
WIRE 1824 880 1728 880
WIRE 1984 880 1824 880
WIRE 1728 896 1728 880
WIRE 1984 896 1984 880
WIRE 1728 992 1728 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL ADPL40502-2.5 1984 1024 R0
SYMATTR InstName U1
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 12.5
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1u
SYMATTR SpiceLine Rser=1m
SYMBOL VOLTAGE 1728 880 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 2256 1024 vOUT
FLAG 2256 1136 0
FLAG 1728 992 0
FLAG 1728 880 vIN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\1ba5050a935a_Differential_measure.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N004 N002 N003 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R1 N001 N002 47k
R2 N002 0 22k
R3 N004 N005 47k
R4 N003 N004 22k
V1 N001 N005 SINE(2.1 2.1 10)
V2 N005 0 SINE(5 4 3)
.lib opamp.sub
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 -112 -304 -112
WIRE 192 -112 80 -112
WIRE 240 -112 192 -112
WIRE 336 -112 320 -112
WIRE 336 -80 336 -112
WIRE -304 -48 -304 -112
WIRE 192 -48 192 -112
WIRE 224 -48 192 -48
WIRE 368 -32 288 -32
WIRE 224 -16 192 -16
WIRE 0 32 -304 32
WIRE 112 32 80 32
WIRE 112 80 112 32
WIRE 192 80 192 -16
WIRE 192 80 112 80
WIRE 256 80 192 80
WIRE 368 80 368 -32
WIRE 368 80 336 80
WIRE -304 160 -304 32
WIRE -304 320 -304 240
WIRE -48 320 -304 320
WIRE -48 336 -48 320
FLAG -48 336 0
FLAG 336 -80 0
SYMBOL Opamps\\opamp 256 32 M180
SYMATTR InstName U1
SYMBOL res -16 -96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 47k
SYMBOL res 224 -96 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 22k
SYMBOL res 96 48 M270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 47k
SYMBOL res 352 96 M270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 22k
SYMBOL voltage -304 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(2.1 2.1 10)
SYMBOL voltage -304 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(5 4 3)
TEXT 288 328 Left 0 !.lib opamp.sub
TEXT -336 360 Left 0 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4451.asc
* Generated by LTspice 26.0.1 for Windows.
C1 IN 0 0.1
V1 IN 0 24
C2 OUT 0 22
R1 OUT 0 3.48
XU1 0 IN OUT NC_01 IN 0 LTC4451 ;pnba Vcc)IN)OUT)STATUS)SHDN#)GND
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4451.asy)
.lib LTC4451.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -192 96 -208 96
WIRE -96 96 -192 96
WIRE -32 96 -96 96
WIRE 16 96 -32 96
WIRE 608 96 480 96
WIRE 688 96 608 96
WIRE 720 96 688 96
WIRE -208 144 -208 96
WIRE 608 144 608 96
WIRE 720 144 720 96
WIRE -96 160 -96 96
WIRE -32 176 -32 96
WIRE 16 176 -32 176
WIRE 608 256 608 208
WIRE 720 256 720 224
WIRE -208 272 -208 224
WIRE -96 272 -96 224
WIRE 144 304 144 272
WIRE 352 304 352 272
WIRE 352 304 144 304
WIRE 352 336 352 304
FLAG 352 336 0
FLAG -96 272 0
FLAG 608 256 0
FLAG -208 272 0
FLAG -192 96 IN
FLAG 688 96 OUT
FLAG 720 256 0
SYMBOL cap -112 160 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL voltage -208 128 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL cap 592 144 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL res 704 128 R0
SYMATTR InstName R1
SYMATTR Value 3.48
SYMBOL LTC4451 240 160 R0
SYMATTR InstName U1
TEXT -216 360 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\8ede20ffc9c2_Draft15.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N002 15k
J1 0 0 N001 LS844
V1 N002 0 -15
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 80 64 80
WIRE 304 80 240 80
WIRE 432 80 384 80
WIRE 432 96 432 80
WIRE 64 208 64 80
WIRE 208 208 208 128
WIRE 208 208 64 208
WIRE 432 208 432 176
WIRE 432 208 208 208
DATAFLAG 432 80 ""
SYMBOL njf 144 128 R270
SYMATTR InstName J1
SYMATTR Value LS844
SYMBOL voltage 432 80 R0
SYMATTR InstName V1
SYMATTR Value -15
SYMBOL res 288 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 15k
FLAG 208 208 0
TEXT -80 224 Left 2 !.op