* Z:\home\khalils\Downloads\files\data\raw_asc\081160c7176d_tpN1.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 Vin1 N001 vcc vss Vo1 LM324 ;pnba In+)In-)V+)V-)OUT
R1 Vo1 N001 {R}
R2 N001 0 {R}
R3 N002 Vo1 {R}
R4 N002 N001 {R}
R5 Vo2 N002 {R}
XU2 Vin2 N002 vcc vss Vo2 LM324 ;pnba In+)In-)V+)V-)OUT
V1 Vin1 0 SINE(0 {V_1} 1k) AC {V_1}
V2 Vin2 0 SINE(0 {V_2} 1k) AC {V_2}
V3 vcc 0 10
V4 0 vss 10
V5 N003 Vc SINE(0 1 1k) AC .5
V6 Vc N004 SINE(0 1 1k) AC .5
V7 Vc 0 SINE(0 1 1k) AC 5
.lib "D:\dario\cuarto\sintesis de redes\Laboratorios\LM324.lib.txt"
.param R = 1k
.param V_1 = 1
.param V_2=1
.ac dec 100 .1 10Meg
* .STEP PARAM V_1 0 1 1
* .STEP PARAM V_2 1 0 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1084 820
WIRE 240 -80 48 -80
WIRE 464 -80 320 -80
WIRE 48 16 48 -80
WIRE 80 16 48 16
WIRE 240 16 160 16
WIRE 464 48 464 -80
WIRE 544 48 464 48
WIRE 688 48 624 48
WIRE -800 112 -800 32
WIRE -688 112 -688 32
WIRE -544 112 -544 32
WIRE -336 112 -336 32
WIRE 176 112 176 64
WIRE -64 128 -128 128
WIRE 48 128 48 16
WIRE 48 128 16 128
WIRE 144 128 48 128
WIRE 544 128 544 96
WIRE 240 144 240 16
WIRE 240 144 208 144
WIRE 272 144 240 144
WIRE 304 144 272 144
WIRE 464 144 464 48
WIRE 464 144 384 144
WIRE 512 144 464 144
WIRE -128 160 -128 128
WIRE 144 160 96 160
WIRE 688 160 688 48
WIRE 688 160 576 160
WIRE 752 160 688 160
WIRE 768 160 752 160
WIRE 512 176 464 176
WIRE 176 224 176 176
WIRE 544 240 544 192
WIRE -800 272 -800 192
WIRE -688 272 -688 192
WIRE -544 272 -544 192
WIRE -336 272 -336 192
WIRE -544 432 -544 368
WIRE -240 432 -240 384
WIRE -544 624 -544 512
WIRE -432 624 -544 624
WIRE -384 624 -432 624
WIRE -240 624 -240 512
WIRE -240 624 -384 624
WIRE -432 656 -432 624
WIRE -432 800 -432 736
FLAG -128 160 0
FLAG -544 272 0
FLAG -336 272 0
FLAG -336 32 Vin2
FLAG -544 32 Vin1
FLAG 96 160 Vin1
FLAG 272 144 Vo1
FLAG 752 160 Vo2
FLAG -688 272 0
FLAG -800 272 0
FLAG -688 32 vcc
FLAG -800 32 vss
FLAG 176 64 vcc
FLAG 176 224 vss
FLAG 544 240 vss
FLAG 544 96 vcc
FLAG 464 176 Vin2
FLAG -432 800 0
FLAG -384 624 Vc
SYMBOL Opamps\\opamp2 176 80 R0
SYMATTR InstName U1
SYMATTR Value LM324
SYMBOL res 176 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL res 32 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R}
SYMBOL res 400 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {R}
SYMBOL res 336 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {R}
SYMBOL res 640 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value {R}
SYMBOL Opamps\\opamp2 544 96 R0
SYMATTR InstName U2
SYMATTR Value LM324
SYMBOL voltage -544 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC {V_1}
SYMATTR InstName V1
SYMATTR Value SINE(0 {V_1} 1k)
SYMBOL voltage -336 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC {V_2}
SYMATTR InstName V2
SYMATTR Value SINE(0 {V_2} 1k)
SYMBOL voltage -688 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -800 208 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL voltage -544 416 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC .5
SYMATTR InstName V5
SYMATTR Value SINE(0 1 1k)
SYMBOL voltage -240 528 R180
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC .5
SYMATTR InstName V6
SYMATTR Value SINE(0 1 1k)
SYMBOL voltage -432 640 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 5
SYMATTR InstName V7
SYMATTR Value SINE(0 1 1k)
TEXT -56 688 Left 2 !.lib "D:\\dario\\cuarto\\sintesis de redes\\Laboratorios\\LM324.lib.txt"
TEXT 400 344 Left 2 !.param R = 1k\n.param V_1 = 1\n.param V_2=1
TEXT -56 728 Left 2 !.ac dec 100 .1 10Meg
TEXT -56 344 Left 2 ;.STEP PARAM V_1 0 1 1
TEXT -56 376 Left 2 ;.STEP PARAM V_2 1 0 1