Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8538.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8538.asy)
XU1 IN N001 +V -V OUT AD8538 ;pnba In+)In-)V+)V-)OUT
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -2.5
V1 +V 0 2.5
Rload OUT 0 10K
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 384 -1104 368 -1104
WIRE 480 -1104 464 -1104
WIRE 496 -1104 480 -1104
WIRE 592 -1104 576 -1104
WIRE 144 -992 144 -1008
WIRE 256 -992 256 -1008
WIRE 480 -992 480 -1104
WIRE 496 -992 480 -992
WIRE 592 -976 592 -1104
WIRE 592 -976 560 -976
WIRE 704 -976 592 -976
WIRE 496 -960 384 -960
WIRE 704 -960 704 -976
WIRE 384 -944 384 -960
WIRE 144 -896 144 -912
WIRE 256 -896 256 -912
WIRE 704 -864 704 -880
WIRE 384 -848 384 -864
SYMBOL res 688 -976 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 384 -960 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL Opamps\\AD8538 528 -1040 R0
SYMATTR InstName U1
SYMBOL res 480 -1120 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 144 -1008 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 592 -1120 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 256 -1008 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
FLAG 144 -1008 +V
FLAG 144 -896 0
FLAG 384 -848 0
FLAG 704 -976 OUT
FLAG 384 -960 IN
FLAG 528 -1008 +V
FLAG 256 -1008 -V
FLAG 528 -944 -V
FLAG 368 -1104 0
FLAG 704 -864 0
FLAG 256 -896 0
TEXT 736 -768 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\032a4a3e5e89_6012.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6012.asy)
XU1 N003 N001 N002 +V -V LT6011 ;pnba IN+)IN-)OUT)VCC)VEE
V1 +V 0 10
V3 N003 0 SINE(0 1 1K)
R2 N001 0 1K
R1 N002 N001 1K
V2 -V 0 -10
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -112 48 -128 48
WIRE 0 48 -32 48
WIRE 96 48 0 48
WIRE 208 48 176 48
WIRE 64 112 64 96
WIRE -416 160 -416 128
WIRE -288 160 -288 128
WIRE 0 160 0 48
WIRE 32 160 0 160
WIRE 208 192 208 48
WIRE 208 192 176 192
WIRE 32 224 -112 224
WIRE -112 240 -112 224
WIRE -416 288 -416 240
WIRE -288 288 -288 240
WIRE 64 288 64 272
WIRE -112 336 -112 320
SYMBOL opamps\\LT6012 64 192 R0
SYMATTR InstName U1
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL voltage -112 224 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL res -16 32 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 192 32 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -416 144 R0
SYMATTR InstName V2
SYMATTR Value -10
FLAG -288 288 0
FLAG 64 96 +V
FLAG -288 128 +V
FLAG 64 288 -V
FLAG -416 288 0
FLAG -416 128 -V
FLAG -128 48 0
FLAG -112 336 0
TEXT -264 344 Left 0 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX17553C.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX17553C.asy)
R4 vOUT N003 100k
XU1 0 vIN N002 N004 N005 N001 N003 N006 MAX17553C ;pnba GND)IN)EN/UV)HYST)FB/VO)LX)_RESET)RT
R6 N005 0 49.9k
C2 vOUT 0 4.7
R2 N002 0 287k
Rload vOUT 0 240
R3 N002 N004 953k
V1 vIN 0 24
L1 N001 vOUT 220 Rser=3.7
R1 vIN N002 3.32Meg
R5 vOUT N005 698k
R7 N006 0 118k
.tran 4m startup
.lib MAX17553C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 992 680
WIRE -176 -32 -192 -32
WIRE 48 -32 -176 -32
WIRE 176 -32 48 -32
WIRE 512 -32 464 -32
WIRE 624 -32 592 -32
WIRE 704 -32 624 -32
WIRE 768 -32 704 -32
WIRE 864 -32 768 -32
WIRE 896 -32 864 -32
WIRE 48 -16 48 -32
WIRE 624 -16 624 -32
WIRE 768 -16 768 -32
WIRE 896 -16 896 -32
WIRE -192 16 -192 -32
WIRE 624 64 624 48
WIRE 896 80 896 64
WIRE 48 96 48 64
WIRE 48 96 -64 96
WIRE 176 96 48 96
WIRE -64 112 -64 96
WIRE 48 112 48 96
WIRE -192 128 -192 96
WIRE 512 128 464 128
WIRE 704 128 704 -32
WIRE 704 128 592 128
WIRE -64 224 -64 192
WIRE 48 224 48 192
WIRE 176 224 48 224
WIRE 768 224 768 64
WIRE 768 224 464 224
WIRE 768 256 768 224
WIRE 176 320 48 320
WIRE 48 336 48 320
WIRE 768 352 768 336
WIRE 320 384 320 368
WIRE 48 432 48 416
SYMBOL cap 608 -16 R0
SYMATTR InstName C2
SYMATTR Value 4.7
SYMBOL res 32 -32 R0
SYMATTR InstName R1
SYMATTR Value 3.32Meg
SYMBOL res 32 320 R0
SYMATTR InstName R7
SYMATTR Value 118k
SYMBOL voltage -192 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 752 -32 R0
SYMATTR InstName R5
SYMATTR Value 698k
SYMBOL res -80 96 R0
SYMATTR InstName R2
SYMATTR Value 287k
SYMBOL res 752 240 R0
SYMATTR InstName R6
SYMATTR Value 49.9k
SYMBOL MAX17553C 320 144 R0
SYMATTR InstName U1
SYMBOL ind 496 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 220
SYMATTR SpiceLine Rser=3.7
SYMBOL res 880 -32 R0
SYMATTR InstName Rload
SYMATTR Value 240
SYMBOL res 32 96 R0
SYMATTR InstName R3
SYMATTR Value 953k
SYMBOL res 608 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
FLAG -192 128 0
FLAG 320 384 0
FLAG 624 64 0
FLAG 896 80 0
FLAG 768 352 0
FLAG -176 -32 vIN
FLAG 864 -32 vOUT
FLAG -64 224 0
FLAG 48 432 0
TEXT 480 392 Left 2 !.tran 4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2eb9a2fc9221_hw7_prob4.asc
* Generated by LTspice 26.0.1 for Windows.
* Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
I1 0 N001 0 AC 5 30
R2 vout N001 1
R1 N001 0 15
C1 vout 0 1.6667m
.options plotwinsize=0 numdgt=15 measdgt=15
.ac list {50/(2*pi)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 692
WIRE -176 -80 -384 -80
WIRE -112 -80 -176 -80
WIRE 0 -80 -32 -80
WIRE 16 -80 0 -80
WIRE -384 -32 -384 -80
WIRE -176 -32 -176 -80
WIRE 16 -16 16 -80
WIRE -384 128 -384 48
WIRE -208 128 -384 128
WIRE -176 128 -176 48
WIRE -176 128 -208 128
WIRE 16 128 16 48
WIRE 16 128 -176 128
WIRE -208 160 -208 128
SYMBOL cap 0 -16 R0
SYMATTR InstName C1
SYMATTR Value 1.6667m
SYMBOL res -400 -48 R0
SYMATTR InstName R1
SYMATTR Value 15
SYMBOL current -176 48 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 52 Left 2
SYMATTR InstName I1
SYMATTR Value 0
SYMATTR Value2 AC 5 30
SYMBOL res -16 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
FLAG -208 160 0
FLAG 0 -80 vout
TEXT -432 304 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ac list {50/(2*pi)}
TEXT -544 -648 Left 2 ;Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2118-1.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2118-1.0.asy)
XU1 IN IN IN OUT 0 0 N002 IN IN IN N001 ADP2118-x.x Rtop=400k Rbot=600k Ctop=4p ;pnba Sync/Mode)FREQ)TRK)FB)GND)PGND)SW)Pvin)Vin)EN)Pgood
V1 IN 0 5
L1 N002 OUT 1
R1 OUT N001 100K
C1 OUT 0 147
Rload OUT 0 .33
.tran 2m startup
.lib ADP2118-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1104 680
WIRE 128 0 48 0
WIRE 288 0 128 0
WIRE 48 16 48 0
WIRE 288 32 288 0
WIRE 128 64 128 0
WIRE 160 64 128 64
WIRE 496 64 416 64
WIRE 640 64 576 64
WIRE 48 112 48 96
WIRE 128 144 128 64
WIRE 160 144 128 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 640 144 640 64
WIRE 640 144 560 144
WIRE 704 144 640 144
WIRE 560 160 560 144
WIRE 704 160 704 144
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 560 224 416 224
WIRE 560 256 560 224
WIRE 704 256 704 240
WIRE 128 304 128 224
WIRE 160 304 128 304
WIRE 640 304 640 144
WIRE 640 304 416 304
WIRE 128 384 128 304
WIRE 160 384 128 384
WIRE 288 432 288 416
SYMBOL res 688 144 R0
SYMATTR InstName Rload
SYMATTR Value .33
SYMBOL voltage 48 0 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 544 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C1
SYMATTR Value 147
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL ADP2118-1.0 288 272 R0
SYMATTR InstName U1
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
FLAG 560 256 0
FLAG 288 432 0
FLAG 48 112 0
FLAG 704 144 OUT
FLAG 704 256 0
FLAG 48 0 IN
TEXT 504 392 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\39486572ebd2_Referencia.asc
* Generated by LTspice 26.0.1 for Windows.
R7 voltage_ref 30% 1809
R4 70% 0 1k
R5 voltage_ref 50% 1404
R6 50% 0 1k
R1 voltage_ref 90% 859
R8 30% 0 1k
R2 90% 0 1k
R3 voltage_ref 70% 1092
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 64 80 64
WIRE 256 64 112 64
WIRE 384 64 256 64
WIRE 496 64 384 64
WIRE 112 160 112 144
WIRE 176 160 112 160
WIRE 256 160 256 144
WIRE 336 160 256 160
WIRE 384 160 384 144
WIRE 464 160 384 160
WIRE 496 160 496 144
WIRE 576 160 496 160
WIRE 112 192 112 160
WIRE 256 192 256 160
WIRE 384 192 384 160
WIRE 496 192 496 160
WIRE 112 272 80 272
WIRE 256 272 112 272
WIRE 384 272 256 272
WIRE 496 272 384 272
WIRE 176 304 176 160
WIRE 336 304 336 160
WIRE 464 304 464 160
WIRE 576 304 576 160
IOPIN 80 64 In
IOPIN 80 272 In
IOPIN 576 304 Out
IOPIN 464 304 Out
IOPIN 336 304 Out
IOPIN 176 304 Out
SYMBOL res 240 48 R0
SYMATTR InstName R3
SYMATTR Value 1092
SYMBOL res 480 176 R0
SYMATTR InstName R8
SYMATTR Value 1k
SYMBOL res 96 48 R0
SYMATTR InstName R1
SYMATTR Value 859
SYMBOL res 240 176 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 96 176 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 368 48 R0
SYMATTR InstName R5
SYMATTR Value 1404
SYMBOL res 480 48 R0
SYMATTR InstName R7
SYMATTR Value 1809
SYMBOL res 368 176 R0
SYMATTR InstName R6
SYMATTR Value 1k
FLAG 80 64 voltage_ref
FLAG 80 272 GND
FLAG 576 304 30%
FLAG 464 304 50%
FLAG 336 304 70%
FLAG 176 304 90%
* Z:\home\khalils\Downloads\files\data\raw_asc\30de2612192e_3PhaseRect.asc
* Generated by LTspice 26.0.1 for Windows.
* This is a 3-Phase rectifier circuit.\nReference: Schuler, 7th edition, page 71.\nRun the simulation and probe the waveform across R1.\nLeft-click the vertical axis and change the bottom axis limit to 0 V.\nThe low ripple content of three-phase rectification is apparent.
V3 N002 N005 SINE(0 170 60 0 0 -120)
D3 N003 N001 D
V1 N003 N005 SINE(0 170 60)
V2 N004 N005 SINE(0 170 60 0 0 120)
D1 N002 N001 D
D5 N004 N001 D
D4 0 N003 D
D6 0 N004 D
D2 0 N002 D
R1 N001 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 33.3333e-3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 416 48 336 48
WIRE 496 48 416 48
WIRE 544 48 496 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 496 64 496 48
WIRE 272 80 -80 80
WIRE 224 128 80 128
WIRE 544 144 544 48
WIRE 272 160 272 80
WIRE 336 160 336 128
WIRE 336 160 272 160
WIRE 224 176 224 128
WIRE 416 176 416 128
WIRE 416 176 224 176
WIRE -80 192 -80 80
WIRE 80 192 80 128
WIRE 496 192 496 128
WIRE 496 192 288 192
WIRE 336 224 336 160
WIRE 416 224 416 176
WIRE 496 224 496 192
WIRE 496 240 496 224
WIRE -80 288 -80 272
WIRE 80 288 80 272
WIRE 80 288 -80 288
WIRE 336 304 336 288
WIRE 416 304 416 288
WIRE 416 304 336 304
WIRE 496 304 496 288
WIRE 496 304 416 304
WIRE 544 304 544 224
WIRE 544 304 496 304
WIRE 544 336 544 304
WIRE 80 352 80 288
WIRE 80 464 80 432
WIRE 288 464 288 192
WIRE 288 464 80 464
SYMBOL res 528 128 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL diode 432 128 R180
WINDOW 0 28 64 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D3
SYMBOL diode 432 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D4
SYMBOL diode 512 128 R180
WINDOW 0 24 64 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D5
SYMBOL diode 352 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D2
SYMBOL diode 512 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D6
SYMBOL voltage 80 176 R0
WINDOW 3 -76 -69 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 56 Left 0
SYMATTR Value SINE(0 170 60)
SYMATTR InstName V1
SYMBOL voltage 80 448 R180
WINDOW 0 36 54 Left 0
WINDOW 3 -122 -39 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 170 60 0 0 120)
SYMBOL voltage -80 176 R0
WINDOW 3 -105 139 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 57 Left 0
SYMATTR Value SINE(0 170 60 0 0 -120)
SYMATTR InstName V3
SYMBOL diode 352 128 R180
WINDOW 0 27 63 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
FLAG 544 336 0
TEXT 344 408 Left 0 !.tran 33.3333e-3
TEXT -128 -104 Left 0 ;This is a 3-Phase rectifier circuit.\nReference: Schuler, 7th edition, page 71.\nRun the simulation and probe the waveform across R1.\nLeft-click the vertical axis and change the bottom axis limit to 0 V.\nThe low ripple content of three-phase rectification is apparent.
* Z:\home\khalils\Downloads\files\data\raw_asc\58676ea43df8_lab5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 NC_01 N003 15
R1 N002 N001 1000
D1 N002 N003 1N750
R2 N002 N003 100
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model 1N750 D(Is=1.004f Rs=.5875 Ikf=0 N=1 Xti=3
Eg=1.11 Cjo=160p M=.5484 Vj=.75 Fc=.5 Isr=1.8n
Nr=2 Bv=5.1 Ibv=27.721m Nbv=1.1779
Ibvl=1.1646m Nbvl=21.894 Tbv1=176.47u Vpk=5.1
mfg=Motorola type=zener)
.tran 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -96 -192 -272 -192
WIRE -96 -176 -96 -192
WIRE 160 -176 -16 -176
WIRE 272 -176 160 -176
WIRE -272 -144 -272 -192
WIRE 160 -112 160 -176
WIRE 272 -96 272 -176
WIRE -272 32 -272 -48
WIRE 160 32 160 -48
WIRE 160 32 -272 32
WIRE 272 32 272 -16
WIRE 272 32 160 32
WIRE 0 0 0 0
SYMBOL voltage -272 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 0 -192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL zener 144 -112 R0
SYMATTR InstName D1
SYMATTR Value 1N750
SYMBOL res 256 -112 R0
SYMATTR InstName R2
SYMATTR Value 100
TEXT 200 184 Left 2 !.model 1N750 D(Is=1.004f Rs=.5875 Ikf=0 N=1 Xti=3\nEg=1.11 Cjo=160p M=.5484 Vj=.75 Fc=.5 Isr=1.8n\nNr=2 Bv=5.1 Ibv=27.721m Nbv=1.1779\nIbvl=1.1646m Nbvl=21.894 Tbv1=176.47u Vpk=5.1\nmfg=Motorola type=zener)
TEXT -176 88 Left 2 !.tran 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3466.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3466.asy)
XU1 N002 N001 IN MP_01 MP_02 MP_03 MP_04 N005 N004 N003 0 LT3466 ;pnba Vout)SW)Vin)))))Rt)CTRL)FB)GND
R2 N005 0 63.4K
C1 N002 0 2.2
L1 IN N001 47
V1 IN 0 3
V2 N004 0 2
D1 N002 N003 NSPW500BS N=8
R1 N003 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT3466.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1280 680
WIRE -16 80 -96 80
WIRE 16 80 -16 80
WIRE 128 80 96 80
WIRE 384 80 288 80
WIRE 512 80 384 80
WIRE 384 96 384 80
WIRE -96 112 -96 80
WIRE 512 112 512 80
WIRE 128 160 128 80
WIRE 288 160 288 80
WIRE 384 176 384 160
WIRE -96 224 -96 192
WIRE -16 240 -16 80
WIRE 64 240 -16 240
WIRE 512 240 512 176
WIRE 512 240 352 240
WIRE 512 256 512 240
WIRE 512 352 512 336
WIRE 64 368 -48 368
WIRE 400 368 352 368
WIRE -48 384 -48 368
WIRE 400 384 400 368
WIRE 208 464 208 448
WIRE -48 480 -48 464
WIRE 400 480 400 464
SYMBOL PowerProducts\\LT3466 208 304 R0
SYMATTR InstName U1
SYMBOL voltage -96 96 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL voltage -48 368 R0
WINDOW 0 29 23 Left 2
WINDOW 3 30 92 Left 2
SYMATTR InstName V2
SYMATTR Value 2
SYMBOL cap 368 96 R0
WINDOW 3 29 52 Left 2
SYMATTR Value 2.2
SYMATTR InstName C1
SYMBOL res 384 368 R0
SYMATTR InstName R2
SYMATTR Value 63.4K
SYMBOL res 496 240 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL ind 0 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMBOL LED 496 112 R0
WINDOW 123 24 85 Left 2
SYMATTR InstName D1
SYMATTR Value NSPW500BS
SYMATTR Description Diode
SYMATTR Type diode
SYMATTR Value2 N=8
FLAG 512 352 0
FLAG 400 480 0
FLAG 208 464 0
FLAG -96 224 0
FLAG -48 480 0
FLAG 384 176 0
FLAG -96 80 IN
TEXT 592 360 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL42005-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL42005-5.0.asy)
XU1 IN OUT IN N001 OUT 0 ADPL42005-5.0 ;pnba Vin)Sense)EN)PG)Vout)GND
R1 OUT N001 100k
Rload OUT 0 10
V1 IN 0 8
C1 OUT 0 2.2 Rser=1.5m
.tran 3m startup
.lib ADPL42005-5.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ADPL42005-5.0 224 128 R0
SYMATTR InstName U1
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 25 97 Left 2
SYMATTR Value 8
SYMATTR InstName V1
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup
* Z:\tmp\asc_dec_bjh7r6w2\081160c7176d_tpN1_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vin1 0 SINE(0 {V_1} 1k) AC {V_1}
V6 Vc N004 SINE(0 1 1k) AC .5
R4 N002 N001 {R}
R2 N001 0 {R}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1084 820
WIRE 240 -80 48 -80
WIRE 464 -80 320 -80
WIRE 48 16 48 -80
WIRE 80 16 48 16
WIRE 240 16 160 16
WIRE 464 48 464 -80
WIRE 544 48 464 48
WIRE -688 112 -688 32
WIRE -544 112 -544 32
WIRE 176 112 176 64
WIRE -64 128 -128 128
WIRE 48 128 48 16
WIRE 48 128 16 128
WIRE 144 128 48 128
WIRE 240 144 240 16
WIRE 240 144 208 144
WIRE 464 144 464 48
WIRE -128 160 -128 128
WIRE 144 160 96 160
WIRE 176 224 176 176
WIRE -688 272 -688 192
WIRE -544 272 -544 192
WIRE -240 432 -240 384
WIRE -432 624 -544 624
WIRE -384 624 -432 624
WIRE -240 624 -240 512
WIRE -240 624 -384 624
WIRE -432 656 -432 624
SYMBOL voltage -544 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC {V_1}
SYMATTR InstName V1
SYMATTR Value SINE(0 {V_1} 1k)
SYMBOL voltage -240 528 R180
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC .5
SYMATTR InstName V6
SYMATTR Value SINE(0 1 1k)
SYMBOL res 336 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value {R}
SYMBOL res 32 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R}
FLAG -128 160 0
FLAG -544 272 0
FLAG -544 32 Vin1
FLAG 96 160 Vin1
FLAG -688 272 0
FLAG -688 32 vcc
FLAG 176 64 vcc
FLAG 176 224 vss
FLAG -384 624 Vc
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1414.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1414.asy)
R1 D 0 1K
V1 +V 0 15
V2 -V 0 -15
V4 IN 0 pulse(0 3.3 0 1u 1u 5m 10m)
V3 S 0 SINE(0 15 1k)
XU1 IN D S -V 0 +V ADG1414 ;pnba IN)D)S)Vss)GND)Vdd
.tran 30m
.lib ADG1414.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -96
WIRE -576 -32 -576 -48
WIRE -432 0 -464 0
WIRE -256 0 -352 0
WIRE -240 0 -256 0
WIRE -32 0 -48 0
WIRE 0 0 -32 0
WIRE 0 16 0 0
WIRE -576 64 -576 48
WIRE -272 64 -336 64
WIRE -240 64 -272 64
WIRE 0 112 0 96
WIRE -576 160 -576 144
WIRE -336 160 -336 64
WIRE -208 192 -208 176
WIRE -80 192 -80 176
WIRE -576 256 -576 240
WIRE -336 256 -336 240
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -336 0 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 15 1k)
SYMBOL ADG1414 -144 48 R0
SYMATTR InstName U1
SYMBOL voltage -336 144 R0
SYMATTR InstName V4
SYMATTR Value pulse(0 3.3 0 1u 1u 5m 10m)
SYMBOL voltage -576 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -576 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
FLAG -576 256 0
FLAG -576 64 0
FLAG -576 -48 +V
FLAG -576 144 -V
FLAG -464 0 0
FLAG -208 192 -V
FLAG -144 -96 +V
FLAG -80 192 0
FLAG -336 256 0
FLAG 0 112 0
FLAG -256 0 S
FLAG -32 0 D
FLAG -272 64 IN
TEXT -456 -104 Left 2 !.tran 30m