* Z:\home\khalils\Downloads\files\data\raw_asc\f5e4ed190436_hw7_prob6.asc
* Generated by LTspice 26.0.1 for Windows.
* Phasor-domain testbench schematic for checking your work on Problem 6:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe inductor and capacitor values are chosen to give the impedances listed\nin Problem 6 at an angular frequency of 50 rps; note that there is nothing \nparticularly special about 50 rps, but I needed to choose something for ac \nsimulation purposes; 50 rps angular frequency of operation in hertz is\n50/(2*pi) ~ 7.9578 Hz\n \nthe inductor series resistance (Rser) has been set to zero; do not change \nthis!
I1 N002 N001 0 AC 6 0
R3 N003 vout 1
C1 vout N002 10m
I2 N003 N001 0 AC 4 0
L1 N001 vout 20m Rser=0
R1 N002 0 2
I3 N003 0 0 AC 2 0
R2 vout 0 2
.options plotwinsize=0 numdgt=15 measdgt=15
.ac list {50/(2*pi)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 964
WIRE -272 -64 -464 -64
WIRE 32 -64 -272 -64
WIRE -464 -16 -464 -64
WIRE -272 -16 -272 -64
WIRE 32 -16 32 -64
WIRE -464 144 -464 64
WIRE -416 144 -464 144
WIRE -272 144 -272 64
WIRE -272 144 -352 144
WIRE -224 144 -272 144
WIRE -144 144 -224 144
WIRE 32 144 32 64
WIRE 32 144 -64 144
WIRE -464 240 -464 144
WIRE -272 240 -272 144
WIRE 32 240 32 144
WIRE -464 400 -464 320
WIRE -368 400 -464 400
WIRE -272 400 -272 320
WIRE -272 400 -368 400
WIRE 32 400 32 320
WIRE 32 400 -272 400
WIRE -368 432 -368 400
SYMBOL current -464 64 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 52 Left 2
SYMATTR InstName I1
SYMATTR Value 0
SYMATTR Value2 AC 6 0
SYMBOL current 32 64 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 52 Left 2
SYMATTR InstName I2
SYMATTR Value 0
SYMATTR Value2 AC 4 0
SYMBOL ind -288 -32 R0
SYMATTR InstName L1
SYMATTR Value 20m
SYMATTR SpiceLine Rser=0
SYMBOL res -48 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1
SYMBOL res -480 224 R0
SYMATTR InstName R1
SYMATTR Value 2
SYMBOL res -288 224 R0
SYMATTR InstName R2
SYMATTR Value 2
SYMBOL cap -352 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10m
SYMBOL current 32 240 R0
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
SYMATTR InstName I3
SYMATTR Value 0
SYMATTR Value2 AC 2 0
FLAG -368 432 0
FLAG -224 144 vout
TEXT -472 568 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ac list {50/(2*pi)}
TEXT -592 -632 Left 2 ;Phasor-domain testbench schematic for checking your work on Problem 6:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe inductor and capacitor values are chosen to give the impedances listed\nin Problem 6 at an angular frequency of 50 rps; note that there is nothing \nparticularly special about 50 rps, but I needed to choose something for ac \nsimulation purposes; 50 rps angular frequency of operation in hertz is\n50/(2*pi) ~ 7.9578 Hz\n \nthe inductor series resistance (Rser) has been set to zero; do not change \nthis!