* Z:\home\khalils\Downloads\files\data\raw_asc\08625cae2929_gr_del.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 N003 {La}
C1 N003 0 {Ca}
R1 N002 N001 {Zo}
R2 0 gd1 {Zo}
V1 N001 0 0 AC 2
L2 N003 gd1 {La}
L3 N004 N005 {Lb1}
L4 N005 gd2 {Lb1}
L5 N006 N005 {Lb2}
C2 gd2 N004 {Cb1}
C3 N006 0 {Cb2}
R3 N001 N004 {Zo}
R4 gd2 0 {Zo}
L6 N007 gd3 {Lc1}
L7 N008 N009 {Lc2}
C4 N008 N007 {Cc1}
C5 gd3 N008 {Cc1}
C6 N009 0 {Cc2}
R5 N007 N001 {Zo}
R6 gd3 0 {Zo}
.param Zo=50
.param F1=1e6
.param La=Zo/4/pi/F1
.param Ca=1/pi/Zo/F1
K1 L1 L2 1.
.AC lin 401 1e-6 10e6
.param F2=5e6
.param A2=0.2
.param Lob=Zo/2/pi/F2
.param Cob=1/Zo/2/pi/F2
.param Lb1=A2*Lob
.param Lb2=Lob/4/A2
.param Cb1=Cob/4/A2
K2 L3 L4 1.
.param Cb2=Cob*4*A2
.param Loc=Zo/2/pi/F3
.param Coc=1/Zo/2/pi/F3
.param Lc1=Loc*4*A3
.param Lc2=Loc/4/A3
.param Cc1=Coc/2/A3
.param Cc2=Coc/(0.25/A3-A3)
.param F3=3e6
.param A3=0.2
* All pass cells for group delay correction
* This example schematic is supplied for informational/educational purposes only.\nContributed by Dominique Szymik.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2200 1924
WIRE 1024 768 864 768
WIRE 1088 768 1024 768
WIRE 1232 768 1168 768
WIRE 1360 768 1312 768
WIRE 1456 768 1360 768
WIRE 1648 768 1536 768
WIRE 1680 768 1648 768
WIRE 864 800 864 768
WIRE 1360 800 1360 768
WIRE 1648 800 1648 768
WIRE 864 912 864 880
WIRE 1360 912 1360 864
WIRE 1648 912 1648 880
WIRE 1024 992 1024 768
WIRE 1088 992 1024 992
WIRE 1200 992 1168 992
WIRE 1360 992 1200 992
WIRE 1568 992 1424 992
WIRE 1648 992 1568 992
WIRE 1680 992 1648 992
WIRE 1648 1040 1648 992
WIRE 1200 1072 1200 992
WIRE 1248 1072 1200 1072
WIRE 1392 1072 1328 1072
WIRE 1440 1072 1392 1072
WIRE 1568 1072 1568 992
WIRE 1568 1072 1520 1072
WIRE 1392 1088 1392 1072
WIRE 1648 1168 1648 1120
WIRE 1392 1184 1392 1168
WIRE 1392 1264 1392 1248
WIRE 1024 1344 1024 992
WIRE 1072 1344 1024 1344
WIRE 1200 1344 1152 1344
WIRE 1344 1344 1200 1344
WIRE 1552 1344 1424 1344
WIRE 1632 1344 1552 1344
WIRE 1680 1344 1632 1344
WIRE 1632 1408 1632 1344
WIRE 1200 1440 1200 1344
WIRE 1248 1440 1200 1440
WIRE 1376 1440 1312 1440
WIRE 1472 1440 1376 1440
WIRE 1552 1440 1552 1344
WIRE 1552 1440 1536 1440
WIRE 1376 1472 1376 1440
WIRE 1632 1536 1632 1488
WIRE 1376 1584 1376 1552
WIRE 1376 1664 1376 1648
FLAG 864 912 0
FLAG 1360 912 0
FLAG 1648 912 0
FLAG 1392 1264 0
FLAG 1648 1168 0
FLAG 1632 1536 0
FLAG 1376 1664 0
FLAG 1680 768 gd1
FLAG 1680 992 gd2
FLAG 1680 1344 gd3
SYMBOL ind2 1216 784 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value {La}
SYMBOL cap 1344 800 R0
SYMATTR InstName C1
SYMATTR Value {Ca}
SYMBOL RES 1184 752 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {Zo}
SYMBOL res 1632 896 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value {Zo}
SYMBOL VOLTAGE 864 784 R0
WINDOW 39 0 0 Left 2
WINDOW 123 24 136 Left 2
SYMATTR Value2 AC 2
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL ind2 1440 784 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value {La}
SYMBOL ind2 1232 1088 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value {Lb1}
SYMBOL ind2 1424 1088 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value {Lb1}
SYMBOL ind 1408 1184 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L5
SYMATTR Value {Lb2}
SYMBOL cap 1424 976 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {Cb1}
SYMBOL cap 1376 1184 R0
WINDOW 3 25 55 Left 2
SYMATTR Value {Cb2}
SYMATTR InstName C3
SYMBOL res 1072 1008 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value {Zo}
SYMBOL res 1632 1024 R0
SYMATTR InstName R4
SYMATTR Value {Zo}
SYMBOL ind 1328 1360 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L6
SYMATTR Value {Lc1}
SYMBOL ind 1360 1456 R0
SYMATTR InstName L7
SYMATTR Value {Lc2}
SYMBOL cap 1312 1424 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value {Cc1}
SYMBOL cap 1536 1424 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value {Cc1}
SYMBOL cap 1360 1584 R0
WINDOW 3 24 54 Left 2
SYMATTR Value {Cc2}
SYMATTR InstName C6
SYMBOL res 1168 1328 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value {Zo}
SYMBOL res 1616 1392 R0
SYMATTR InstName R6
SYMATTR Value {Zo}
TEXT 1784 800 Left 2 !.param  Zo=50\n.param  F1=1e6 \n.param  La=Zo/4/pi/F1\n.param  Ca=1/pi/Zo/F1\nK1 L1 L2 1.
TEXT 1784 736 Left 2 !.AC lin 401 1e-6 10e6
TEXT 1784 968 Left 2 !.param F2=5e6\n.param A2=0.2
TEXT 1784 1104 Left 2 !.param Lob=Zo/2/pi/F2\n.param Cob=1/Zo/2/pi/F2\n.param Lb1=A2*Lob\n.param Lb2=Lob/4/A2\n.param Cb1=Cob/4/A2\nK2 L3 L4 1.\n.param Cb2=Cob*4*A2
TEXT 1776 1504 Left 2 !.param Loc=Zo/2/pi/F3\n.param Coc=1/Zo/2/pi/F3\n.param Lc1=Loc*4*A3\n.param Lc2=Loc/4/A3\n.param Cc1=Coc/2/A3\n.param Cc2=Coc/(0.25/A3-A3)
TEXT 1776 1384 Left 2 !.param F3=3e6\n.param A3=0.2
TEXT 1160 712 Left 2 ;All pass cells for group delay correction
TEXT 1360 1704 Top 1 ;This example schematic is supplied for informational/educational purposes only.\nContributed by Dominique Szymik.