* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5014_chan1_2.asc
* Generated by LTspice 26.0.1 for Windows.
* This model simulates two channels of ADP5014\nFeatures configured by the CFG1 and CFG2 pins are controlled\nby features of the IC found by Ctrl right click.\n--CL is current limit and and can be set to 6.9 for 4 A,\n or 3.5 for 2 A. It is also a good to simulate startup using the minimum values\n --Paralllel should be set to 1 if using channels in parallel, else 0\n--Timer should be set to 1 or 8 depending on the length hiccup required\n--PSM should be 0 for forced PWM and 1 for PSM (low power pulse\n skip mode) enabled\n--Outputs of the GPIO pin are pinned out seperately for your convenience\n--Enable mode is always manual mode\n--See the datasheet to configure channels for parallelt operation
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5014_chan1_2.asy)
R7 N008 0 2.43K
C1 OUT1 0 200
C3 N007 N008 5.6n
C4 N002 0 100n
V1 IN 0 5
L1 N001 OUT1 1 Rser=33m
R2 N003 0 48.7K
R3 N005 0 2.43K
Rload1 OUT1 0 250m
L2 N006 OUT2 1 Rser=33m
R1 N002 N003 48.7K
C5 OUT2 0 200
R6 N009 0 165K
Rload2 OUT2 0 250m
C2 N004 N005 5.6n
XU1 N009 NC_01 N003 IN N001 OUT1 N004 IN N002 0 0 IN NC_02 NC_03 NC_04 NC_05 N006 N007 OUT2 IN IN N003 ADP5014 RP=49m RN=37m CS=0.06 CL1=6.9 CL2=6.9 PSM=0 timer=1 parallel=0 ;pnba Rt)SYNC)Vset1)PVin1)SW1)FB1)Comp1)EN1)Vref)PGND1)PGND2)AVin)CLKout)PWRGD)UV)UVO)SW2)Comp2)FB2)EN2)PVin2)Vset2
.tran 500u startup
.softstart .2 ; This option reduces the internal softstart time by 5x.
.lib ADP5014.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1976 952
WIRE -144 -320 -320 -320
WIRE -96 -320 -144 -320
WIRE 272 -320 224 -320
WIRE 432 -320 352 -320
WIRE 544 -320 432 -320
WIRE 592 -320 544 -320
WIRE -320 -304 -320 -320
WIRE 432 -304 432 -320
WIRE 592 -304 592 -320
WIRE -320 -208 -320 -224
WIRE -144 -208 -144 -320
WIRE -96 -208 -144 -208
WIRE 432 -208 432 -240
WIRE 432 -208 224 -208
WIRE 592 -208 592 -224
WIRE 432 -192 432 -208
WIRE -272 -96 -336 -96
WIRE -144 -96 -144 -208
WIRE -96 -96 -144 -96
WIRE 544 -96 544 -320
WIRE 544 -96 224 -96
WIRE -272 -80 -272 -96
WIRE -272 16 -272 0
WIRE -176 16 -272 16
WIRE -96 16 -176 16
WIRE 240 16 224 16
WIRE 320 16 304 16
WIRE 416 16 400 16
WIRE -272 32 -272 16
WIRE -272 128 -272 112
WIRE -144 128 -144 -96
WIRE -96 128 -144 128
WIRE 272 128 224 128
WIRE 432 128 352 128
WIRE 528 128 432 128
WIRE 576 128 528 128
WIRE 432 144 432 128
WIRE 576 144 576 128
WIRE -144 240 -144 128
WIRE -96 240 -144 240
WIRE 432 240 432 208
WIRE 432 240 224 240
WIRE 576 240 576 224
WIRE 432 256 432 240
WIRE -176 352 -176 16
WIRE -96 352 -176 352
WIRE 528 352 528 128
WIRE 528 352 224 352
WIRE -336 464 -336 -96
WIRE -96 464 -336 464
WIRE 240 464 224 464
WIRE 320 464 304 464
WIRE 416 464 400 464
WIRE -336 480 -336 464
WIRE -336 560 -336 544
WIRE -192 576 -224 576
WIRE -96 576 -112 576
SYMBOL res 560 128 R0
SYMATTR InstName Rload2
SYMATTR Value 250m
SYMBOL VOLTAGE -320 -320 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap -352 480 R0
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL PowerProducts\\ADP5014_chan1_2 64 240 R0
SYMATTR InstName U1
SYMBOL res 304 480 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R7
SYMATTR Value 2.43K
SYMBOL cap 240 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 5.6n
SYMBOL ind 256 -304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -23 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=33m
SYMBOL res 576 -320 R0
SYMATTR InstName Rload1
SYMATTR Value 250m
SYMBOL cap 240 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 5.6n
SYMBOL cap 416 144 R0
SYMATTR InstName C5
SYMATTR Value 200
SYMBOL res -288 16 R0
SYMATTR InstName R2
SYMATTR Value 48.7K
SYMBOL res -288 -96 R0
SYMATTR InstName R1
SYMATTR Value 48.7K
SYMBOL ind 256 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -23 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 1
SYMATTR SpiceLine Rser=33m
SYMBOL res -96 560 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 165K
SYMBOL cap 416 -304 R0
SYMATTR InstName C1
SYMATTR Value 200
SYMBOL res 304 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 2.43K
FLAG 416 16 0
FLAG -224 576 0
FLAG -336 560 0
FLAG 432 -192 0
FLAG 592 -320 OUT1
FLAG -320 -208 0
FLAG -320 -320 IN
FLAG 592 -208 0
FLAG 416 464 0
FLAG 432 256 0
FLAG 576 128 OUT2
FLAG 576 240 0
FLAG -272 128 0
TEXT 352 664 Left 2 !.tran 500u startup\n.softstart .2 ; This option reduces the internal softstart time by 5x.
TEXT -1488 120 Left 2 ;This model simulates two channels of ADP5014\nFeatures configured by the CFG1 and CFG2 pins are controlled\nby features of the IC found by Ctrl right click.\n--CL is current limit and and can be set to 6.9 for 4 A,\n  or 3.5 for  2 A.  It is also a good to simulate startup using the minimum values\n --Paralllel should be set to 1 if using channels in parallel, else 0\n--Timer should be set to 1 or 8 depending on the length hiccup required\n--PSM should be 0 for forced PWM and 1 for PSM (low power pulse\n   skip mode) enabled\n--Outputs of the GPIO pin are pinned out seperately for your convenience\n--Enable mode is always manual mode\n--See the datasheet to configure channels for parallelt operation