Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\1742a78157db_e1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 SINE(0 1 1k 0 0 0) AC 1 0
R1 IN RL 100
L1 RL OUT 159mH
C1 OUT 0 159nF
.ac dec 100 10 100k
.step param Rv list 100 316 1k 1.41k 2k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1108 680
WIRE 272 272 256 272
WIRE 416 272 272 272
WIRE 576 272 496 272
WIRE 656 272 576 272
WIRE 880 272 736 272
WIRE 1008 272 880 272
WIRE 1104 272 1008 272
WIRE 256 384 256 272
WIRE 880 384 880 272
WIRE 256 512 256 464
WIRE 880 512 880 448
FLAG 256 512 0
FLAG 880 512 0
FLAG 1008 272 OUT
FLAG 272 272 IN
FLAG 576 272 RL
SYMBOL voltage 256 368 R0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k 0 0 0) AC 1 0
SYMBOL res 400 288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL ind 640 288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 159mH
SYMBOL cap 864 384 R0
SYMATTR InstName C1
SYMATTR Value 159nF
TEXT 592 640 Left 2 !.ac dec 100 10 100k\n.step param Rv list 100 316 1k 1.41k 2k
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1084-12.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 20) Rser=0.1
Rload OUT 0 20
C1 OUT 0 10
XU1 0 OUT IN LT1084-12 ;pnba GND)OUT)IN
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1084-12.asy)
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1872 896 1808 896
WIRE 2000 896 1872 896
WIRE 1344 912 1344 896
WIRE 1872 912 1872 896
WIRE 2000 912 2000 896
WIRE 1344 1008 1344 992
WIRE 1872 1008 1872 976
WIRE 2000 1008 2000 992
WIRE 1680 1024 1680 992
FLAG 2000 896 OUT
FLAG 2000 1008 0
FLAG 1344 1008 0
FLAG 1872 1008 0
FLAG 1344 896 IN
FLAG 1680 1024 0
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 20)
SYMATTR SpiceLine Rser=0.1
SYMBOL RES 1984 896 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL cap 1856 912 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1084-12 1680 896 R0
SYMATTR InstName U1
TEXT 1960 1064 Left 2 !.tran 1
* Z:\tmp\asc_dec_bjh7r6w2\1813c96015ff_AD8336_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R3 PRAO INPN 301
V3 PWRA 0 0
R1 OUT 0 500
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -192 -160 -208 -160
WIRE -32 -160 -112 -160
WIRE 16 -160 0 -160
WIRE 112 -160 96 -160
WIRE -208 -144 -208 -160
WIRE 112 -144 112 -160
WIRE -32 -112 -32 -160
WIRE 0 -112 0 -160
WIRE -32 -64 -32 -112
WIRE 0 -64 0 -112
WIRE -112 -16 -336 -16
WIRE -64 -16 -112 -16
WIRE 208 0 160 0
WIRE 352 0 208 0
WIRE -112 16 -304 16
WIRE -64 16 -112 16
WIRE -304 64 -304 16
WIRE -272 64 -304 64
WIRE -176 64 -192 64
WIRE -112 64 -176 64
WIRE -64 64 -112 64
WIRE 352 64 352 0
WIRE -176 96 -176 64
WIRE 32 96 -176 96
WIRE -304 112 -304 64
WIRE -16 128 -16 64
WIRE 144 128 144 64
WIRE 352 160 352 144
WIRE -304 224 -304 192
WIRE -16 224 -16 208
WIRE 144 224 144 208
SYMBOL res -176 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 301
SYMBOL voltage 0 -160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res 336 48 R0
SYMATTR InstName R1
SYMATTR Value 500
FLAG 352 160 0
FLAG 208 0 OUT
FLAG 144 224 0
FLAG 112 -144 0
FLAG -208 -144 0
FLAG -32 -112 VPOS
FLAG -16 224 0
FLAG -112 16 INPN
FLAG -112 64 PRAO
FLAG -304 224 0
FLAG -112 -16 INPP
FLAG 0 -112 PWRA
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2119-1.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2119-1.0.asy)
V1 IN 0 5
Rload OUT 0 1
C1 OUT 0 22
C2 OUT 0 22
L1 N002 OUT 1
R1 OUT N001 100K
XU1 IN IN N002 0 0 OUT IN N001 IN IN ADP2119-1.0 ;pnba Vin)Pvin)SW)PGND)GND)FB)TRK)Pgood)Sync/Mode)EN
.tran 1m
.lib ADP2119-1.0.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 0 64 0
WIRE 288 0 128 0
WIRE 64 16 64 0
WIRE 288 32 288 0
WIRE 128 64 128 0
WIRE 160 64 128 64
WIRE 496 64 416 64
WIRE 624 64 576 64
WIRE 64 112 64 96
WIRE 128 144 128 64
WIRE 160 144 128 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 624 144 624 64
WIRE 624 144 560 144
WIRE 688 144 624 144
WIRE 736 144 688 144
WIRE 560 160 560 144
WIRE 624 160 624 144
WIRE 736 160 736 144
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 560 224 416 224
WIRE 624 224 560 224
WIRE 560 256 560 224
WIRE 736 256 736 240
WIRE 128 304 128 224
WIRE 160 304 128 304
WIRE 688 304 688 144
WIRE 688 304 416 304
WIRE 288 368 288 352
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL ADP2119-1.0 288 272 R0
SYMATTR InstName U1
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL res 720 144 R0
WINDOW 3 34 68 Left 2
SYMATTR Value 1
SYMATTR InstName Rload
SYMBOL cap 608 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL voltage 64 0 R0
WINDOW 0 27 27 Left 2
WINDOW 3 29 88 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 544 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C1
SYMATTR Value 22
FLAG 560 256 0
FLAG 288 368 0
FLAG 64 112 0
FLAG 736 144 OUT
FLAG 736 256 0
FLAG 64 0 IN
TEXT 504 344 Left 2 !.tran 1m
* Z:\tmp\asc_dec_bjh7r6w2\14f9c003e5b2_Q1b_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V3 N001 0 SINE(0 10 500)
V4 0 N003 2
D_ideal1 N001 NC_01 D_ideal D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1184 680
WIRE 736 80 688 80
WIRE 976 80 880 80
WIRE 688 208 688 80
WIRE 976 208 976 176
WIRE 688 352 688 288
WIRE 976 352 976 288
SYMBOL voltage 688 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 10 500)
SYMBOL voltage 976 304 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 2
SYMBOL diode 736 96 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D_ideal1
SYMATTR SpiceModel D_ideal
FLAG 688 352 0
FLAG 976 352 0
* Z:\home\khalils\Downloads\files\data\raw_asc\6dfb044d4233_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
* EDIC Winter Internship (31-12-2024)\nBonus Design\nCommon Source Amplifier with Passive Load and NMOS as a driver
* .op
* .tf V(Vout) V2
* .tran 5m
;.param w 1u
;.step param w 0.13u 7.8u 0.13u
M1 Vout Vin 0 0 NMOS l=0.26u w=7.67u
CL Vout 0 1.5p
V1 Vdd 0 1.8
Rd Vdd Vout 11k
V2 Vin 0 SINE(0.457 1m 1k) AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include IBM130nm.txt
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 16 240 -64
WIRE 240 128 240 96
WIRE 480 128 240 128
WIRE 592 128 480 128
WIRE 240 144 240 128
WIRE 480 160 480 128
WIRE 336 192 240 192
WIRE 32 224 16 224
WIRE 192 224 32 224
WIRE 240 256 240 240
WIRE 336 256 336 192
WIRE 336 256 240 256
WIRE -400 304 -400 240
WIRE -256 304 -256 240
WIRE 480 304 480 224
WIRE 240 448 240 256
WIRE -400 480 -400 384
WIRE -256 480 -256 384
SYMBOL voltage -400 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL res 224 0 R0
SYMATTR InstName Rd
SYMATTR Value 11k
SYMBOL voltage -256 288 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0.457 1m 1k)
SYMATTR Value2 AC 1
SYMBOL nmos4 192 144 R0
WINDOW 123 56 100 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=0.26u w=7.67u
SYMBOL cap 464 160 R0
SYMATTR InstName CL
SYMATTR Value 1.5p
FLAG 32 224 Vin
FLAG 240 -64 Vdd
FLAG 592 128 Vout
FLAG 240 448 0
FLAG 480 304 0
FLAG -400 480 0
FLAG -256 480 0
FLAG -400 240 Vdd
FLAG -256 240 Vin
TEXT -608 -128 Left 2 ;EDIC Winter Internship (31-12-2024)\nBonus Design\nCommon Source Amplifier with Passive Load and NMOS as a driver
TEXT -440 -32 Left 2 !.include IBM130nm.txt
TEXT -440 -8 Left 2 !;.param w 1u
TEXT -440 24 Left 2 !;.step param w 0.13u 7.8u 0.13u
TEXT -440 56 Left 2 ;.op
TEXT -440 80 Left 2 ;.tf V(Vout) V2
TEXT -440 104 Left 2 ;.tran 5m
TEXT -440 128 Left 2 !.ac dec 10 10 1gig
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP151-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP151-2.5.asy)
Rload OUT 0 25
XU1 IN 0 IN MP_01 OUT ADP151-x.x T=1.5Meg ;pnba Vin)GND)EN))Vout
C1 OUT 0 1
V1 IN 0 5
.tran 500u startup
.lib ADP151-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 880 1696 880
WIRE 1984 880 1824 880
WIRE 1696 896 1696 880
WIRE 1984 896 1984 880
WIRE 1696 992 1696 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL PowerProducts\\ADP151-2.5 1984 1024 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1696 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 2256 1024 OUT
FLAG 2256 1136 0
FLAG 1696 992 0
FLAG 1696 880 IN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP122-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP122-3.3.asy)
C2 OUT 0 1
XU1 OUT MP_01 0 IN MP_02 IN ADP122 K=1/6600 ;pnba Vout))GND)En))Vin
V1 IN 0 5.5
Rload OUT 0 100
C1 IN 0 1
.tran 10m startup
.lib ADP122.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 400 96 352 96
WIRE 480 96 400 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 400 112 400 96
WIRE 480 112 480 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 400 208 400 176
WIRE 480 208 480 192
WIRE 256 272 256 256
SYMBOL res 464 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL cap 384 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL ADP122-3.3 256 208 R0
SYMATTR InstName U1
FLAG 0 208 0
FLAG 256 272 0
FLAG 400 208 0
FLAG 480 208 0
FLAG 480 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\6bf76d29762e_LTSpice_StorageTank1.asc
* Generated by LTspice 26.0.1 for Windows.
* "Water Storage Tank is Ful" Indicator Simulation
* This Voltage \nwill come from\nthe water storage\ntank when it's filled.
*.tran 0.1m 10m 6m
*.step param R2 10 10000 100
*.step param R3 10 10000 100
V1 N001 0 5
R4 N002 0 10k
R1 VB Vs 100k
D1 VE N002 D
R2 N001 VC 567.47
Q1 VC VB VE 0 2N3904
VS Vs 0 5V
R3 VE 0 2.1823k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 5 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -304 -336 -320 -336
WIRE -304 -304 -304 -336
WIRE 64 -304 48 -304
WIRE 128 -304 64 -304
WIRE 304 -304 208 -304
WIRE 304 -272 304 -304
WIRE -128 -256 -144 -256
WIRE -32 -256 -48 -256
WIRE -16 -256 -32 -256
WIRE -304 -208 -304 -224
WIRE -304 -208 -416 -208
WIRE 48 -176 48 -208
WIRE 48 -176 32 -176
WIRE 176 -176 112 -176
WIRE -416 -160 -416 -208
WIRE 304 -160 304 -192
WIRE 48 -128 48 -176
WIRE 176 -80 176 -96
WIRE 48 -32 48 -48
IOPIN 32 -176 Out
SYMBOL voltage 304 -288 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -304 -320 R0
WINDOW 0 39 71 Left 2
WINDOW 3 34 51 Left 2
SYMATTR InstName VS
SYMATTR Value 5V
SYMBOL res 32 -144 R0
WINDOW 3 36 76 Left 1
SYMATTR InstName R3
SYMATTR Value 2.1823k
SYMBOL res 160 -192 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL npn -16 -304 R0
WINDOW 0 56 32 Left 1
WINDOW 3 56 68 Left 1
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res -32 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 224 -320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 567.47
SYMBOL diode 48 -160 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
FLAG -416 -160 0
FLAG -320 -336 Vs
FLAG -144 -256 Vs
FLAG -32 -256 VB
FLAG 64 -304 VC
FLAG 304 -160 0
FLAG 176 -80 0
FLAG 32 -176 VE
FLAG 48 -32 0
TEXT -336 -392 Left 2 ;"Water Storage Tank is Ful" Indicator Simulation
TEXT -472 -288 Left 1 ;This Voltage \nwill come from\nthe water storage\ntank when it's filled.
TEXT -248 -144 Left 1 !.dc V1 0 5 0.1
TEXT -248 -128 Left 1 !*.tran 0.1m 10m 6m
TEXT -248 -112 Left 1 !*.step param R2 10 10000 100
TEXT -248 -96 Left 1 !*.step param R3 10 10000 100
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7105-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7105-3.3.asy)
XU2 IN OUT IN N002 OUT 0 N001 ADP7105 Vref=3.3 ;pnba Vin)Sense)EN)SS)Vout)GND)PG
C2 N002 0 2.7n
R1 OUT N001 100k
C1 OUT 0 2.2 Rser=1.5m
Rload OUT 0 11
V1 IN 0 4.3
.tran 6m startup
.lib ADP7105.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -32 48 -32 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -32 144 -32 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 11
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 4.3
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 2.7n
SYMBOL ADP7105-3.3 224 128 R0
SYMATTR InstName U2
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -32 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0358d1323f9b_Circuito_RLC_en_serie_corregido_.asc
* Generated by LTspice 26.0.1 for Windows.
C N003 0 {X}
R N002 N001 {R}
L N002 N003 {X}
V1 N001 0 AC 1
.param R = {1/q}
.param X = {1/w}
.param w = {2*pi*f}
.param f=10
.param q=1
.ac dec 1000 1m 1Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 96 64 96
WIRE 320 96 224 96
WIRE 320 112 320 96
WIRE 64 144 64 96
WIRE 64 272 64 224
WIRE 192 272 64 272
WIRE 224 272 192 272
WIRE 320 272 320 192
WIRE 320 272 288 272
SYMBOL voltage 64 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL cap 288 256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 11 -1 VTop 2
SYMATTR InstName C
SYMATTR Value {X}
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R
SYMATTR Value {R}
SYMBOL ind 304 96 R0
SYMATTR InstName L
SYMATTR Value {X}
FLAG 192 272 0
TEXT -96 384 Left 2 !.param R = {1/q}
TEXT -96 352 Left 2 !.param X = {1/w}
TEXT -96 320 Left 2 !.param w = {2*pi*f}
TEXT -96 224 Left 2 !.param f=10
TEXT -96 256 Left 2 !.param q=1
TEXT -96 288 Left 2 !.ac dec 1000 1m 1Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8023.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8023.asy)
C1 OUT 0 22
V1 IN 0 20
R3 OUT N004 100K
Rload OUT 0 1.65
R2 N003 0 154K
R1 N002 0 49.9K
XU1 IN IN N002 N003 0 N004 N001 N001 OUT LTM8023 ;pnba Vin)Run/SS)Rt)ADJ)GND)Pgood)BIAS)AUX)Vout
.tran 250u startup
.lib LTM8023.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 80 96 -160 96
WIRE 96 96 80 96
WIRE 448 96 384 96
WIRE 544 96 448 96
WIRE 640 96 544 96
WIRE -160 112 -160 96
WIRE 544 112 544 96
WIRE 640 112 640 96
WIRE 80 160 80 96
WIRE 96 160 80 160
WIRE 400 160 384 160
WIRE 448 176 448 96
WIRE -160 208 -160 192
WIRE 544 208 544 176
WIRE 640 208 640 192
WIRE -64 224 -80 224
WIRE 96 224 16 224
WIRE 400 224 400 160
WIRE 400 224 384 224
WIRE 0 288 -80 288
WIRE 96 288 80 288
WIRE 448 288 448 256
WIRE 448 288 384 288
WIRE 240 336 240 320
SYMBOL res 32 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 49.9K
SYMBOL res 96 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 154K
SYMBOL PowerProducts\\LTM8023 240 192 R0
SYMATTR InstName U1
SYMBOL res 432 160 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 624 96 R0
SYMATTR InstName Rload
SYMATTR Value 1.65
SYMBOL voltage -160 96 R0
SYMATTR InstName V1
SYMATTR Value 20
SYMBOL cap 528 112 R0
SYMATTR InstName C1
SYMATTR Value 22
FLAG 240 336 0
FLAG -160 208 0
FLAG -80 224 0
FLAG -80 288 0
FLAG 640 208 0
FLAG 544 208 0
FLAG -160 96 IN
FLAG 640 96 OUT
TEXT 424 320 Left 2 !.tran 250u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1607.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1607.asy)
R2 N002 0 60K
L1 IN N001 2.2 Rser=22m
XU1 OUT N002 IN MP_01 N001 MP_02 IN MP_03 MP_04 MP_05 0 ADP1607 ;pnba Vout)FB)Vin))SW))EN))))GND
Cout OUT 0 6 Rser=10m
Rload OUT 0 22K
R1 OUT N002 100K
V1 IN 0 0.9
.tran 1.6m startup
.lib ADP1607.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 980 680
WIRE 128 -16 32 -16
WIRE 320 -16 208 -16
WIRE 32 80 32 -16
WIRE 32 80 -48 80
WIRE 48 80 32 80
WIRE 320 80 320 -16
WIRE 320 80 304 80
WIRE -48 96 -48 80
WIRE 32 176 32 80
WIRE 48 176 32 176
WIRE 368 176 304 176
WIRE 480 176 368 176
WIRE 640 176 480 176
WIRE -48 192 -48 176
WIRE 368 192 368 176
WIRE 480 192 480 176
WIRE 640 192 640 176
WIRE 48 272 32 272
WIRE 368 272 304 272
WIRE 368 288 368 272
WIRE 480 288 480 256
WIRE 640 288 640 272
WIRE 368 384 368 368
SYMBOL res 624 176 R0
SYMATTR InstName Rload
SYMATTR Value 22K
SYMBOL ADP1607 176 176 R0
SYMATTR InstName U1
SYMBOL voltage -48 80 R0
SYMATTR InstName V1
SYMATTR Value 0.9
SYMBOL res 352 272 R0
SYMATTR InstName R2
SYMATTR Value 60K
SYMBOL ind 112 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 7 58 VBottom 2
WINDOW 39 -45 59 VTop 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=22m
SYMBOL cap 464 192 R0
WINDOW 3 40 38 Left 2
WINDOW 39 25 61 Left 2
SYMATTR Value 6
SYMATTR SpiceLine Rser=10m
SYMATTR InstName Cout
SYMBOL res 352 176 R0
SYMATTR InstName R1
SYMATTR Value 100K
FLAG -48 80 IN
FLAG 640 176 OUT
FLAG 32 272 0
FLAG -48 192 0
FLAG 640 288 0
FLAG 368 384 0
FLAG 480 288 0
TEXT 456 392 Left 2 !.tran 1.6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\13201ff6b543_pad_buffer.asc
* Generated by LTspice 26.0.1 for Windows.
AX1 N008 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac * fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac * fac* fac * fac* fac * fac }
AX2 N009 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac* fac * fac* fac * fac }
AX3 N010 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac* fac * fac* fac }
AX4 N011 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac * fac * fac } wp={wpad * mp * fac* fac * fac* fac }
AX5 N012 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac * fac } wp={wpad * mp * fac * fac* fac }
AX6 N013 vss vss vss vss vss vss vss BUF wn={wpad* fac * fac } wp={wpad * mp * fac* fac }
AX7 N014 vss vss vss vss vss vss vss BUF wn={wpad * fac } wp={wpad * mp * fac }
AX8 N015 vss vss vss vss vss vss vss BUF wn={wpad } wp={wpad * mp }
.param wpad=360u mp=2.16 fac=0.401
.lib BU_180nm.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1168 680
WIRE 48 224 -16 224
WIRE 144 224 48 224
WIRE 240 224 144 224
WIRE 336 224 240 224
WIRE 432 224 336 224
WIRE 528 224 432 224
WIRE 624 224 528 224
WIRE 720 224 624 224
WIRE 48 304 48 224
WIRE 144 304 144 224
WIRE 240 304 240 224
WIRE 336 304 336 224
WIRE 432 304 432 224
WIRE 528 304 528 224
WIRE 624 304 624 224
WIRE 720 304 720 224
WIRE 32 320 -16 320
WIRE 128 320 80 320
WIRE 224 320 176 320
WIRE 320 320 272 320
WIRE 416 320 368 320
WIRE 512 320 464 320
WIRE 608 320 560 320
WIRE 704 320 656 320
WIRE 800 320 752 320
WIRE 48 432 48 336
WIRE 48 432 -16 432
WIRE 144 432 144 336
WIRE 144 432 48 432
WIRE 240 432 240 336
WIRE 240 432 144 432
WIRE 336 432 336 336
WIRE 336 432 240 432
WIRE 432 432 432 336
WIRE 432 432 336 432
WIRE 528 432 528 336
WIRE 528 432 432 432
WIRE 624 432 624 336
WIRE 624 432 528 432
WIRE 720 432 720 336
WIRE 720 432 624 432
SYMBOL inv 240 320 R0
SYMATTR InstName X3
SYMATTR SpiceLine wn={wpad* fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac* fac * fac* fac }
SYMBOL inv 336 320 R0
SYMATTR InstName X4
SYMATTR SpiceLine wn={wpad* fac * fac * fac * fac } wp={wpad * mp * fac* fac * fac* fac }
SYMBOL inv 528 320 R0
SYMATTR InstName X6
SYMATTR SpiceLine wn={wpad* fac * fac } wp={wpad * mp * fac* fac }
SYMBOL inv 720 320 R0
SYMATTR InstName X8
SYMATTR SpiceLine wn={wpad } wp={wpad * mp }
SYMBOL inv 144 320 R0
SYMATTR InstName X2
SYMATTR SpiceLine wn={wpad* fac * fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac* fac * fac* fac * fac }
SYMBOL inv 432 320 R0
SYMATTR InstName X5
SYMATTR SpiceLine wn={wpad* fac * fac * fac } wp={wpad * mp * fac * fac* fac }
SYMBOL inv 624 320 R0
SYMATTR InstName X7
SYMATTR SpiceLine wn={wpad * fac } wp={wpad * mp * fac }
SYMBOL inv 48 320 R0
SYMATTR InstName X1
SYMATTR SpiceLine wn={wpad* fac * fac * fac * fac * fac * fac * fac } wp={wpad * mp * fac * fac * fac* fac * fac* fac * fac }
FLAG -16 224 vdd
FLAG -16 320 in
FLAG 800 320 out
FLAG -16 432 vss
TEXT -40 128 Left 2 !.param wpad=360u mp=2.16 fac=0.401\n.lib BU_180nm.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8422.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8422.asy)
R1 N002 N003 2.21K
Rload OUT 0 10K
V1 +V 0 15
V2 -V 0 -15
Vref N005 0 0.5
Vin N001 N004 SINE(0 100m 10K)
Vcm N004 0 1
XU1 N004 N002 N003 N001 -V N005 OUT +V AD8422 ;pnba IN-)RG1)RG2)IN+)VEE)REF)OUT)VCC
.tran 1m
.lib AD8422.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 640 -1264 640 -1280
WIRE 752 -1264 752 -1280
WIRE 464 -1184 80 -1184
WIRE 640 -1168 640 -1184
WIRE 752 -1168 752 -1184
WIRE 80 -1152 80 -1184
WIRE 464 -1152 368 -1152
WIRE 752 -1104 640 -1104
WIRE 752 -1088 752 -1104
WIRE 368 -1056 368 -1072
WIRE 464 -1056 368 -1056
WIRE 80 -1024 80 -1072
WIRE 464 -1024 80 -1024
WIRE 576 -1024 576 -1040
WIRE 80 -1008 80 -1024
WIRE 752 -992 752 -1008
WIRE 576 -928 576 -944
WIRE 80 -912 80 -928
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL res 352 -1168 R0
SYMATTR InstName R1
SYMATTR Value 2.21K
SYMBOL AD8422 496 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 640 -1280 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 80 -1024 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName Vcm
SYMATTR Value 1
SYMBOL voltage 80 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 100m 10K)
SYMBOL voltage 752 -1280 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 576 -1040 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName Vref
SYMATTR Value 0.5
FLAG 640 -1280 +V
FLAG 640 -1168 0
FLAG 752 -1104 OUT
FLAG 496 -1200 +V
FLAG 752 -1280 -V
FLAG 496 -1008 -V
FLAG 752 -992 0
FLAG 752 -1168 0
FLAG 80 -912 0
FLAG 576 -928 0
TEXT 744 -920 Left 2 !.tran 1m