* Z:\home\khalils\Downloads\files\data\raw_asc\c33b75c3d16d_5.asc
* Generated by LTspice 26.0.1 for Windows.
*SRC=74148;74148;TTL;74xx;Priority encoder
*SYM=T74148
*74148 PRIORITY ENCODER 8-3 LINE
***
*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin TTLin
* TTLout TTLout TTLout TTLout TTLout
*pinout N 5 10 11 12 13 1 2 3 4 9 7 6 14 15:VCC=16 GND=8
*pinout J 5 10 11 12 13 1 2 3 4 9 7 6 14 15:VCC=16 GND=8
*pinout W 5 10 11 12 13 1 2 3 4 9 7 6 14 15:VCC=16 GND=8
* Library below included based on ModelFile attribute of instance XU2, XU3, XU4 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
Xaand6 2b [i3 in4 in5 iei] and
Xainv6 in5 i5 inv
XU4 N004 N006 N002 0 NC_03 LT1001 ;pnba In+)In-)V+)V-)OUT
Xanor3 a2 [3a 3b 3c 3d] ls_nor
Xaand9 3a [i4 iei] and
R2 N003 N005 1R
Xaand8 2d [i7 iei] and
XU3 N004 N005 N002 0 NC_02 LT1001 ;pnba In+)In-)V+)V-)OUT
XU2 N004 N003 N002 0 NC_01 LT1001 ;pnba In+)In-)V+)V-)OUT
Xanor2 a1 [2a 2b 2c 2d] ls_nor
Xanand1 eo [in0 in1 in2 in3 in4 in5 in6 in7] ls_nand1
Xanand2 gs [eo iei] ls_nand2
V2 N001 0 Vref
Xainv7 in6 i6 inv
Xanor1 a0 [1a 1b 1c 1d] ls_nor
R4 N006 0 0.5R
Xaanda 3b [i5 iei] and
Xainv3 in2 i2 inv
Xainv5 in4 i4 inv
Xainv2 in1 i1 inv
V3 N004 0 analog
V1 N002 0 Vcc
R3 N005 N006 1R
Xaand4 1d [i7 iei] and
Xainv4 in3 i3 inv
Xaand7 2c [i6 iei] and
Xaand1 1a [i1 in2 in4 in6 iei] and
Xainv8 in7 i7 inv
Xaandb 3c [i6 iei] and
Xainv9 ei iei inv
R1 N001 N003 1.5R
Xainv1 in0 i0 inv
Xaand5 2a [i2 in4 in5 iei] and
Xaand3 1c [i5 in6 iei] and
Xaand2 1b [i3 in4 in6 iei] and
Xaandc 3d [i7 iei] and
.include opamp.sub
.tran 10
.subckt 74148 ei in0 in1 in2 in3 in4 in5 in6 in7 a0 a1 a2 gs eo
.model ls_nor d_nor(rise_delay=12n fall_delay=12n)
.model ls_nand1 d_nand(rise_delay=15n fall_delay=15n)
.model ls_nand2 d_nand
.model and d_and
.model inv d_inverter
.ends 74148
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1080 1580
WIRE 160 -96 160 -128
WIRE 464 -80 464 -128
WIRE 272 0 272 -128
WIRE 160 32 160 -16
WIRE 464 32 464 0
WIRE 464 32 384 32
WIRE 384 128 384 32
WIRE 160 144 160 112
WIRE 352 144 160 144
WIRE 160 160 160 144
WIRE 272 176 272 80
WIRE 352 176 272 176
WIRE 384 208 384 192
WIRE 384 208 320 208
WIRE 464 224 464 32
WIRE 464 224 384 224
WIRE 384 240 384 224
WIRE 160 256 160 240
WIRE 352 256 160 256
WIRE 160 288 160 256
WIRE 272 288 272 176
WIRE 352 288 272 288
WIRE 320 320 320 208
WIRE 384 320 384 304
WIRE 384 320 320 320
WIRE 464 336 464 224
WIRE 464 336 384 336
WIRE 384 368 384 336
WIRE 160 384 160 368
WIRE 352 384 160 384
WIRE 160 416 160 384
WIRE 272 416 272 288
WIRE 352 416 272 416
WIRE 320 448 320 320
WIRE 384 448 384 432
WIRE 384 448 320 448
WIRE 320 496 320 448
WIRE 160 528 160 496
SYMBOL OpAmps/OP07 384 208 R0
SYMATTR InstName U3
SYMBOL res 144 400 R0
SYMATTR InstName R4
SYMATTR Value 0.5R
SYMBOL res 144 144 R0
SYMATTR InstName R2
SYMATTR Value 1R
SYMBOL voltage 160 0 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value Vref
SYMBOL voltage 464 16 R180
WINDOW 0 24 96 Left 2
WINDOW 3 41 35 Left 2
SYMATTR InstName V1
SYMATTR Value Vcc
SYMBOL voltage 272 96 R180
WINDOW 0 24 96 Left 2
WINDOW 3 -54 8 Left 2
SYMATTR InstName V3
SYMATTR Value analog
SYMBOL res 144 272 R0
SYMATTR InstName R3
SYMATTR Value 1R
SYMBOL OpAmps/OP07 384 336 R0
SYMATTR InstName U4
SYMBOL res 144 16 R0
SYMATTR InstName R1
SYMATTR Value 1.5R
SYMBOL OpAmps/OP07 384 96 R0
SYMATTR InstName U2
FLAG 320 496 0
FLAG 464 -128 0
FLAG 160 528 0
FLAG 160 -128 0
FLAG 272 -128 0
TEXT 872 664 Left 2 !.include opamp.sub\n.tran 10
TEXT 128 664 Left 2 !*SRC=74148;74148;TTL;74xx;Priority encoder\n*SYM=T74148\n*74148 PRIORITY ENCODER 8-3 LINE\n***\n.subckt 74148 ei in0 in1 in2 in3 in4 in5 in6 in7 a0 a1 a2 gs eo\n*FAMILY TTLin TTLin TTLin TTLin TTLin TTLin TTLin TTLin\n*        TTLout TTLout TTLout TTLout TTLout\n*pinout N 5 10 11 12 13 1 2 3 4 9 7 6 14 15:VCC=16 GND=8\n*pinout J 5 10 11 12 13 1 2 3 4 9 7 6 14 15:VCC=16 GND=8\n*pinout W 5 10 11 12 13 1 2 3 4 9 7 6 14 15:VCC=16 GND=8\nXainv1 in0 i0 inv\nXainv2 in1 i1 inv\nXainv3 in2 i2 inv\nXainv4 in3 i3 inv\nXainv5 in4 i4 inv\nXainv6 in5 i5 inv\nXainv7 in6 i6 inv\nXainv8 in7 i7 inv\nXainv9 ei iei inv\nXanand1 eo [in0 in1 in2 in3 in4 in5 in6 in7] ls_nand1\nXanand2 gs [eo iei] ls_nand2\nXaand1 1a [i1 in2 in4 in6 iei] and\nXaand2 1b [i3 in4 in6 iei] and\nXaand3 1c [i5 in6 iei] and\nXaand4 1d [i7 iei] and\nXaand5 2a [i2 in4 in5 iei] and\nXaand6 2b [i3 in4 in5 iei] and\nXaand7 2c [i6 iei] and\nXaand8 2d [i7 iei] and\nXaand9 3a [i4 iei] and\nXaanda 3b [i5 iei] and\nXaandb 3c [i6 iei] and\nXaandc 3d [i7 iei] and\nXanor1 a0 [1a 1b 1c 1d] ls_nor\nXanor2 a1 [2a 2b 2c 2d] ls_nor\nXanor3 a2 [3a 3b 3c 3d] ls_nor\n.model ls_nor d_nor(rise_delay=12n fall_delay=12n)\n.model ls_nand1 d_nand(rise_delay=15n fall_delay=15n)\n.model ls_nand2 d_nand\n.model and d_and\n.model inv d_inverter\n.ends 74148