* Z:\home\khalils\Downloads\files\data\raw_asc\09dce248f467_SLOPE.asc
* Generated by LTspice 26.0.1 for Windows.
I1 0 a {ibias}
C3 a 0 {cacc}
B1 out 0 V=IF(V(in)>0.5, se*(V(a)-V(b)), 0)
R1 o 0 1k
B2 b 0 V=V(o)
B3 N001 0 V=IF(V(in)>0.5,1, 0)
R2 N001 0 1k
.param se=1
* Slope
* binary
* dv/dt of the slope(V/sec)
* in
* out
* dv/dt=se
* 2026-01-02
* <Revision History>\n2024-12-29: Initial Versoin\n2025-02-23: Made following edit to remove negative spike at slope reset and improve simulation time.\n - scale of I1 & C2 by 1/1000, and reduced resistance of diode Ron and buffer Rout\n - changed C1 snubber parameter, \n - added D2 to clamp negative voltage at node a \n - added new parameter vsat to be able to specify saturating voltage\n2025-04-12: Bug fix \n - Fixed a bug where the model would not work when vsat was set to a high voltage \n - Changed default vsat to 1000V (originally 1V).\n2025-05-31: Solved convergence issue at high "se" \n - Replaced current source with state machine.\n2026-01-02: Changed to .machine base for higher accuracy and convergence.\n - removed .param vsat
* .param vsat=1000 (removed)
.param cacc=1u
.param ibias=1u
.ic V(a)=0
.machine
.state LO 0
.state HI 1
.rule LO HI V(in)>.5
.rule HI LO V(in)<.5
.output (o) IF((state==HI),V(b), V(a))
.endmachine
* dummy circuit to ensure stiff falling edge
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2080 1228
WIRE -64 288 -64 256
WIRE 1200 288 1120 288
WIRE 768 336 768 288
WIRE 928 336 928 288
WIRE 1120 336 1120 288
WIRE -64 400 -64 368
WIRE -64 400 -96 400
WIRE 128 400 -64 400
WIRE -64 432 -64 400
WIRE 768 448 768 416
WIRE 928 448 928 416
WIRE 1120 448 1120 416
WIRE -64 528 -64 496
WIRE 1200 592 848 592
WIRE 848 608 848 592
WIRE 1200 608 1200 592
WIRE 128 656 -304 656
WIRE 848 704 848 688
WIRE 1200 704 1200 688
FLAG -304 656 in
IOPIN -304 656 In
FLAG -64 256 0
FLAG -64 528 0
FLAG 1200 288 out
IOPIN 1200 288 Out
FLAG -96 400 a
FLAG 1120 448 0
FLAG 768 448 0
FLAG 768 288 o
FLAG 928 448 0
FLAG 928 288 b
FLAG 1200 704 0
FLAG 848 704 0
SYMBOL current -64 288 R0
SYMATTR InstName I1
SYMATTR Value {ibias}
SYMBOL cap -80 432 R0
SYMATTR InstName C3
SYMATTR Value {cacc}
SYMBOL bv 1120 320 R0
SYMATTR InstName B1
SYMATTR Value V=IF(V(in)>0.5, se*(V(a)-V(b)), 0)
SYMBOL res 752 320 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL bv 928 320 R0
SYMATTR InstName B2
SYMATTR Value V=V(o)
SYMBOL bv 848 592 R0
SYMATTR InstName B3
SYMATTR Value V=IF(V(in)>0.5,1, 0)
SYMBOL res 1184 592 R0
SYMATTR InstName R2
SYMATTR Value 1k
TEXT -304 112 Left 2 !.param se=1
TEXT -304 24 Left 4 ;Slope
TEXT -352 632 Left 1 ;binary
TEXT -136 112 Left 2 ;dv/dt of the slope(V/sec)
TEXT 248 136 Left 1 ;in
TEXT 240 72 Left 1 ;out
TEXT 376 80 Right 1 ;dv/dt=se
TEXT 1192 48 Left 2 ;2026-01-02
TEXT -304 768 Left 2 ;<Revision History>\n2024-12-29: Initial Versoin\n2025-02-23: Made following edit to remove negative spike at slope reset and improve simulation time.\n                    - scale of I1 & C2 by 1/1000, and reduced resistance of diode Ron and buffer Rout\n                    - changed C1 snubber parameter, \n                    - added D2 to clamp negative voltage at node a \n                    - added new parameter vsat to be able to specify saturating voltage\n2025-04-12: Bug fix \n                    - Fixed a bug where the model would not work when vsat was set to a high voltage \n                    - Changed default vsat to 1000V (originally 1V).\n2025-05-31: Solved convergence issue at high "se" \n                    - Replaced current source with state machine.\n2026-01-02: Changed to .machine base for higher accuracy and convergence.\n                    - removed .param vsat
TEXT -304 144 Left 2 ;.param vsat=1000 (removed)
TEXT -312 472 Left 2 !.param cacc=1u\n.param ibias=1u
TEXT -312 440 Left 2 !.ic V(a)=0
TEXT 232 368 Left 2 !.machine\n.state LO 0\n.state HI 1\n.rule LO HI V(in)>.5\n.rule HI LO V(in)<.5\n.output (o) IF((state==HI),V(b), V(a))\n.endmachine
TEXT 768 560 Left 2 ;dummy circuit to ensure stiff falling edge
LINE Normal 288 144 240 144
LINE Normal 288 144 288 112
LINE Normal 384 112 288 112
LINE Normal 384 144 384 112
LINE Normal 432 144 384 144
LINE Normal 288 80 240 80
LINE Normal 288 80 384 32
LINE Normal 384 80 384 32
LINE Normal 432 80 384 80
LINE Normal 288 112 288 80 1
LINE Normal 384 112 384 80 1
RECTANGLE Normal 448 160 225 18 2
RECTANGLE Normal 1296 736 736 576 2