Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\089413953cd8_Cohn.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
L6 N006 0 {Lm}
L5 N003 N006 {L}
R2 OUT 0 {R}
R1 IN N004 {R}
C1 N001 IN {C1}
L1 N001 N005 {L}
L4 N002 N006 {2*L}
C5 N002 0 {C3}
C4 OUT 0 {C2}
C2 IN 0 {C2}
L2 N005 0 {Lm}
C3 N003 OUT {C1}
L3 N002 N005 {2*L}
V1 N004 0 AC 2
.ac oct 1000 10Meg 22Meg
.param x=.54 ; trimer postion
.param R=50
.param L=2.95u Lm=.27u C1=22p+x*25p C2=240p C3=34p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2300 1728
WIRE 1360 1168 1232 1168
WIRE 1664 1168 1536 1168
WIRE 1760 1168 1664 1168
WIRE 2080 1168 1952 1168
WIRE 1232 1184 1232 1168
WIRE 2080 1184 2080 1168
WIRE 1360 1200 1360 1168
WIRE 1536 1200 1536 1168
WIRE 1760 1200 1760 1168
WIRE 1952 1200 1952 1168
WIRE 1664 1280 1664 1168
WIRE 1072 1296 1024 1296
WIRE 1184 1296 1152 1296
WIRE 1232 1296 1232 1248
WIRE 1232 1296 1184 1296
WIRE 1360 1296 1360 1280
WIRE 1456 1296 1360 1296
WIRE 1536 1296 1536 1280
WIRE 1536 1296 1456 1296
WIRE 1760 1296 1760 1280
WIRE 1872 1296 1760 1296
WIRE 1952 1296 1952 1280
WIRE 1952 1296 1872 1296
WIRE 2080 1296 2080 1248
WIRE 2240 1296 2080 1296
WIRE 2240 1312 2240 1296
WIRE 1024 1328 1024 1296
WIRE 1232 1328 1232 1296
WIRE 1456 1328 1456 1296
WIRE 1872 1328 1872 1296
WIRE 2080 1328 2080 1296
WIRE 1024 1424 1024 1408
WIRE 1232 1424 1232 1392
WIRE 1456 1424 1456 1408
WIRE 1664 1424 1664 1344
WIRE 1872 1424 1872 1408
WIRE 2080 1424 2080 1392
WIRE 2240 1424 2240 1392
SYMBOL ind 1440 1312 R0
SYMATTR InstName L2
SYMATTR Value {Lm}
SYMBOL cap 1648 1280 R0
SYMATTR InstName C5
SYMATTR Value {C3}
SYMBOL cap 1216 1328 R0
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL cap 1216 1184 R0
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL ind 1856 1312 R0
SYMATTR InstName L6
SYMATTR Value {Lm}
SYMBOL RES 1168 1280 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value {R}
SYMBOL ind 1936 1184 R0
SYMATTR InstName L5
SYMATTR Value {L}
SYMBOL VOLTAGE 1024 1312 R0
WINDOW 3 25 97 Left 0
SYMATTR Value AC 2
SYMATTR InstName V1
SYMBOL res 2224 1296 R0
SYMATTR InstName R2
SYMATTR Value {R}
SYMBOL ind 1520 1184 R0
SYMATTR InstName L3
SYMATTR Value {2*L}
SYMBOL ind 1344 1184 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMBOL cap 2064 1328 R0
SYMATTR InstName C4
SYMATTR Value {C2}
SYMBOL ind 1744 1184 R0
SYMATTR InstName L4
SYMATTR Value {2*L}
SYMBOL cap 2064 1184 R0
SYMATTR InstName C3
SYMATTR Value {C1}
FLAG 2080 1424 0
FLAG 1872 1424 0
FLAG 1456 1424 0
FLAG 1232 1424 0
FLAG 1664 1424 0
FLAG 1024 1424 0
FLAG 2240 1424 0
FLAG 2240 1296 OUT
FLAG 1184 1296 IN
TEXT 1368 1480 Left 0 !.ac oct 1000 10Meg 22Meg
TEXT 1240 1544 Left 0 !.param x=.54 ; trimer postion\n.param R=50\n.param L=2.95u Lm=.27u C1=22p+x*25p C2=240p C3=34p
TEXT 1160 1656 Left 0 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3484-1.asc
* Generated by LTspice 26.0.1 for Windows.
L1 IN N003 10 Rpar=2K Rser=.1
L2 0 N001 {10u*10.2*10.2} Rpar=1Meg
C1 OUT 0 .01
D1 N001 OUT D
R1 N002 IN 10K
V1 IN 0 5
XU1 N002 IN IN N003 MP_01 IN 0 LT3484-1 ;pnba _Done)Charge)Vin)SW))Vbat)GND
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
K1 L1 L2 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3484-1.asy)
.lib LT3484-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2772 1752
WIRE 1808 1264 1648 1264
WIRE 1936 1264 1808 1264
WIRE 2064 1264 1936 1264
WIRE 2224 1264 2112 1264
WIRE 2352 1264 2288 1264
WIRE 2352 1280 2352 1264
WIRE 1808 1296 1808 1264
WIRE 1936 1296 1936 1264
WIRE 2064 1296 2064 1264
WIRE 2112 1296 2112 1264
WIRE 1648 1360 1648 1264
WIRE 1664 1360 1648 1360
WIRE 1760 1360 1744 1360
WIRE 2352 1376 2352 1344
WIRE 2112 1392 2112 1376
WIRE 2064 1408 2064 1376
WIRE 2064 1408 1984 1408
WIRE 1648 1456 1648 1360
WIRE 1760 1456 1648 1456
WIRE 1648 1472 1648 1456
WIRE 1872 1536 1872 1520
WIRE 1648 1568 1648 1552
FLAG 2352 1376 0
FLAG 1872 1536 0
FLAG 1648 1568 0
FLAG 2112 1392 0
FLAG 2352 1264 OUT
FLAG 1648 1264 IN
SYMBOL ind2 2048 1280 R0
WINDOW 0 -6 35 Right 2
WINDOW 3 -4 73 Right 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rpar=2K Rser=.1
SYMBOL ind2 2128 1392 R180
WINDOW 0 -3 72 Right 2
WINDOW 3 0 43 Right 2
SYMATTR InstName L2
SYMATTR Value {10u*10.2*10.2}
SYMATTR SpiceLine Rpar=1Meg
SYMBOL cap 2336 1280 R0
WINDOW 3 27 55 Left 2
SYMATTR Value .01
SYMATTR InstName C1
SYMBOL diode 2224 1280 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL res 1760 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL VOLTAGE 1648 1456 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LT3484-1 1872 1408 R0
SYMATTR InstName U1
TEXT 2048 1480 Left 2 !.tran 5m startup
TEXT 2088 1264 Bottom 2 !K1 L1 L2 1
* Z:\home\khalils\Downloads\files\data\raw_asc\AD4020.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4020.asy)
C1 0 N005 10p
V2 N007 0 PWL(0 5 100u 0)
R2 N006 N007 10
V3 N001 0 5
XU1 N001 N002 N004 MP_01 0 N006 N005 N008 AD4020 EN_Hi_Z=1 ;pnba REF)Vdd)IN+))GND)IN-)Vout)CNV
R1 N004 N003 10
V6 N002 0 1.8
V1 N003 0 PWL(0 0 100u 5)
V4 N008 0 PULSE(0 1.8 227n 0.1n 0.1n 40n 555n)
.tran 110u
.lib AD4020.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 1252
WIRE 704 224 368 224
WIRE 832 224 784 224
WIRE 368 288 368 224
WIRE 704 336 496 336
WIRE 832 336 784 336
WIRE -208 368 -240 368
WIRE -80 368 -128 368
WIRE 80 368 0 368
WIRE 80 416 80 368
WIRE 144 416 80 416
WIRE 560 432 496 432
WIRE 688 432 624 432
WIRE 144 448 80 448
WIRE -208 496 -240 496
WIRE -80 496 -128 496
WIRE 80 496 80 448
WIRE 80 496 0 496
WIRE 704 528 496 528
WIRE 832 528 784 528
WIRE 368 608 368 576
SYMBOL voltage -112 368 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 100u 5)
SYMBOL AD4020 400 432 R0
SYMATTR InstName U1
SYMBOL voltage 688 336 M90
WINDOW 0 47 41 VRight 2
WINDOW 3 -44 39 VRight 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V6
SYMATTR Value 1.8
SYMBOL voltage 688 528 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 1.8 227n 0.1n 0.1n 40n 555n)
SYMBOL voltage -112 496 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 5 100u 0)
SYMBOL res 16 480 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10
SYMBOL cap 624 416 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage 688 224 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res 16 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
FLAG 368 608 0
FLAG 832 336 0
FLAG -240 368 0
FLAG 688 432 0
FLAG 832 528 0
FLAG 832 224 0
FLAG -240 496 0
TEXT 664 672 Left 2 !.tran 110u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADGM3121.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADGM3121.asy)
R1 vRFCA 0 300
V2 vRF1A 0 3
XU1 0 VDD vIN1 NC_01 NC_02 NC_03 vRFCA vRF1A NC_04 NC_05 NC_06 NC_07 ADGM3121 ;pnba GND)VDD)IN1)IN2)IN3)IN4)RFCA)RF1A)RF2A)RFCB)RF1B)RF2B
V1 VDD 0 {Vdd}
V3 vIN1 0 PULSE(3.3 0 0 10u 10u 10m 20m)
.tran 100m
.param Vdd = 3.3
.lib ADGM3121.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2244 1360
WIRE 1072 -240 1040 -240
WIRE 1072 -208 1072 -240
WIRE 768 -128 736 -128
WIRE 896 -128 848 -128
WIRE 944 -128 896 -128
WIRE 1264 -128 1200 -128
WIRE 1328 -128 1264 -128
WIRE 896 -48 672 -48
WIRE 944 -48 896 -48
WIRE 1328 -48 1328 -128
WIRE 672 -16 672 -48
WIRE 672 96 672 64
WIRE 1328 112 1328 32
WIRE 720 192 672 192
WIRE 672 256 672 192
WIRE 672 384 672 336
WIRE 1072 528 1072 480
RECTANGLE Normal 768 -432 16 -720 2
SYMBOL voltage 672 -32 R0
WINDOW 0 18 8 Left 2
WINDOW 3 -218 178 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(3.3 0 0 10u 10u 10m 20m)
SYMBOL voltage 864 -128 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL ADGM3121 1072 -80 R0
SYMATTR InstName U1
SYMBOL res 1312 -64 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage 672 240 R0
WINDOW 0 55 43 Bottom 2
WINDOW 3 65 85 Top 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vdd}
FLAG 672 384 0
FLAG 1328 112 0
FLAG 1072 528 0
FLAG 672 96 0
FLAG 736 -128 0
FLAG 1264 -128 vRFCA
FLAG 896 -128 vRF1A
FLAG 896 -48 vIN1
FLAG 1040 -240 VDD
FLAG 720 192 VDD
TEXT 1272 536 Left 2 !.tran 100m
TEXT 32 -696 Left 2 ;Notes:
TEXT 32 -392 Left 2 !.param Vdd = 3.3
* Z:\home\khalils\Downloads\files\data\raw_asc\223046dae6f3_tb.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Dip N001 50
R2 Dop Dom 50
V1 N001 0 PULSE(0 5 0 1n 1n 10n) AC 1
X1 Dip Dim Dop Dom DLINE
.include out.cir
.param Ap=0
.param tp=0
.param Cf=10f
.AC LIN 10000 1165000.0 233000000.0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1368 680
WIRE 1312 192 1232 192
WIRE 464 224 368 224
WIRE 720 224 544 224
WIRE 768 224 720 224
WIRE 1184 224 1120 224
WIRE 1232 224 1232 192
WIRE 1232 224 1184 224
WIRE 1312 224 1312 192
WIRE 368 304 368 224
WIRE 768 320 720 320
WIRE 1184 320 1120 320
WIRE 1248 320 1184 320
WIRE 1248 352 1248 320
WIRE 1312 352 1312 304
WIRE 1312 352 1248 352
WIRE 368 464 368 384
WIRE 720 464 720 320
RECTANGLE Normal 1120 352 768 192 2
SYMBOL res 1296 208 R0
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL res 560 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL voltage 368 288 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 1n 1n 10n)
SYMATTR Value2 AC 1
FLAG 368 464 0
FLAG 720 224 Dip
FLAG 720 464 0
FLAG 720 320 Dim
FLAG 1184 224 Dop
FLAG 1184 320 Dom
TEXT 200 -56 Left 2 !.include out.cir
TEXT 200 -32 Left 2 !.param Ap=0
TEXT 200 -8 Left 2 !.param tp=0
TEXT 200 16 Left 2 !.param Cf=10f
TEXT 784 264 Left 2 !X1 Dip Dim Dop Dom DLINE
TEXT 168 552 Left 2 !.AC LIN 10000 1165000.0 233000000.0
* Z:\home\khalils\Downloads\files\data\raw_asc\35b24eac579f_PMOS_CHART_SETUP.asc
* Generated by LTspice 26.0.1 for Windows.
;.dc vg 0 1.8 10m
vd vd 0 0.9
R2 N001 vg 1Meg
vs vs 0 1.8
R1 N002 vd 1.5k
vg vg 0 1.125
M1 N002 N001 vs vs PMOS l=0.36u w={wp}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include tsmc180.txt
.step param wp 0.18u 70u 0.18u
.param wp=1u
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 680
WIRE 192 112 192 48
WIRE 368 112 368 32
WIRE 720 208 720 128
WIRE 800 208 720 208
WIRE 720 240 720 208
WIRE 560 256 528 256
WIRE 672 256 640 256
WIRE 192 272 192 192
WIRE 368 288 368 192
WIRE 800 288 800 208
WIRE 800 288 720 288
WIRE 720 400 720 336
WIRE 720 560 720 480
IOPIN 528 256 In
SYMBOL voltage -112 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vd
SYMATTR Value 0.9
SYMBOL res 704 384 R0
SYMATTR InstName R1
SYMATTR Value 1.5k
SYMBOL voltage 192 96 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 1.125
SYMATTR InstName vg
SYMBOL pmos4 672 336 M180
WINDOW 123 79 3 Left 2
SYMATTR Value2 l=0.36u w={wp}
SYMATTR InstName M1
SYMBOL res 656 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage 368 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vs
SYMATTR Value 1.8
FLAG 192 272 0
FLAG 368 288 0
FLAG 192 48 vg
FLAG 368 32 vs
FLAG 528 256 vg
FLAG 720 128 vs
FLAG -112 192 0
FLAG -112 112 vd
FLAG 720 560 vd
TEXT 56 400 Left 2 !.include tsmc180.txt
TEXT 64 424 Left 2 !;.dc vg 0  1.8  10m
TEXT 16 464 Left 2 !.step param wp 0.18u 70u 0.18u
TEXT 80 512 Left 2 !.param wp=1u
TEXT -16 384 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\3ec71baa452f_Assignment_6b__ii_.asc
* Generated by LTspice 26.0.1 for Windows.
* Inverting Op-Amp (Vout = Vb)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
V2 Vcc 0 15
Vin N002 0 SINE(0 5 1000)
XU1 0 N001 Vcc Vee Vout LT1001 ;pnba In+)In-)V+)V-)OUT
V3 0 Vee 15
Rf Vout N001 300000
Ri N001 N002 100000
.tran 5ms
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 64 -32 64
WIRE 112 64 96 64
WIRE 272 64 272 32
WIRE -144 112 -176 112
WIRE -48 112 -64 112
WIRE -176 160 -176 112
WIRE -48 176 -48 112
WIRE -32 176 -32 64
WIRE -32 176 -48 176
WIRE -16 176 -32 176
WIRE 112 192 112 64
WIRE 112 192 48 192
WIRE 160 192 112 192
WIRE 272 192 272 144
WIRE 400 192 272 192
WIRE -16 208 -48 208
WIRE 400 224 400 192
WIRE 272 240 272 192
WIRE -176 336 -176 240
WIRE -48 336 -48 208
WIRE 272 368 272 320
IOPIN 160 192 Out
SYMBOL res -48 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Ri
SYMATTR Value 100000
SYMBOL voltage -176 144 R0
WINDOW 3 107 96 Center 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 5 1000)
SYMBOL voltage 272 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL Opamps\\OP07 16 128 R0
SYMATTR InstName U1
SYMBOL voltage 272 48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 112 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf
SYMATTR Value 300000
FLAG -176 336 0
FLAG -48 336 0
FLAG 400 224 0
FLAG 272 32 Vcc
FLAG 16 160 Vcc
FLAG 16 224 Vee
FLAG 272 368 Vee
FLAG 160 192 Vout
TEXT -176 392 Left 2 !.tran 5ms
TEXT -88 -48 Left 2 ;Inverting Op-Amp (Vout = Vb)
* Z:\home\khalils\Downloads\files\data\raw_asc\0f04539171c0_completed_alternating_offset_mirror_device.asc
* Generated by LTspice 26.0.1 for Windows.
R8 P006 N001 R
R4 N001 N003 R
R1 P002 N001 R
Q2 P003 P004 0 0 NPN
R5 N003 N001 R
R3 P001 N001 R
V1 N001 N001 V
Q3 N001 N001 P005 0 NPN
R7 P009 N001 R
Q6 P008 P009 0 0 NPN
Q8 P010 N004 N001 0 NPN
R2 P004 N001 R
Q4 P005 N003 N001 0 NPN
Q7 N002 N002 P010 0 NPN
R9 N002 N004 R
R6 P007 N001 R
R10 N004 N001 R
Q5 P006 P007 P008 0 NPN
Q1 P001 P002 P003 0 NPN
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 288 -432 -96 -432
WIRE 448 -432 288 -432
WIRE 656 -432 448 -432
WIRE 288 -320 288 -432
WIRE 448 -320 448 -432
WIRE -96 -192 -96 -432
WIRE 144 -192 -96 -192
WIRE 656 -192 656 -432
WIRE 656 -192 592 -192
WIRE -96 -96 -96 -192
WIRE 144 -96 -96 -96
WIRE 656 -96 656 -192
WIRE 656 -96 592 -96
WIRE -96 0 -96 -96
WIRE 144 0 -96 0
WIRE 288 0 144 0
WIRE 592 0 448 0
WIRE 288 32 288 0
WIRE 448 32 448 0
WIRE 144 80 144 0
WIRE 224 80 144 80
WIRE 592 80 592 0
WIRE 592 80 512 80
WIRE 144 96 144 80
WIRE 592 96 592 80
WIRE 224 176 144 176
WIRE 592 176 512 176
WIRE -96 256 -96 0
WIRE -96 432 -96 336
WIRE 144 432 144 256
WIRE 144 432 -96 432
WIRE 288 432 288 224
WIRE 288 432 144 432
WIRE 448 432 448 224
WIRE 448 432 288 432
WIRE 592 432 592 256
WIRE 592 432 448 432
WIRE 656 432 656 -96
WIRE 656 432 592 432
SYMBOL res 608 80 M0
SYMATTR InstName R9
SYMBOL npn 512 32 M0
SYMATTR InstName Q7
SYMBOL res 496 -208 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMBOL npn 224 -240 R0
SYMATTR InstName Q1
SYMBOL npn 512 -240 M0
SYMATTR InstName Q5
SYMBOL npn 512 128 M0
SYMATTR InstName Q8
SYMBOL res 240 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMBOL res 432 -224 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R8
SYMBOL npn 224 128 R0
SYMATTR InstName Q4
SYMBOL npn 224 -144 R0
SYMATTR InstName Q2
SYMBOL npn 224 32 R0
SYMATTR InstName Q3
SYMBOL res 496 -112 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMBOL res 128 80 R0
SYMATTR InstName R4
SYMBOL res 240 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMBOL npn 512 -144 M0
SYMATTR InstName Q6
SYMBOL res 304 -224 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMBOL res 608 160 M0
SYMATTR InstName R10
SYMBOL voltage -96 240 R0
SYMATTR InstName V1
SYMBOL res 128 160 R0
SYMATTR InstName R5
FLAG 288 -48 0
FLAG 448 -48 0
* Z:\home\khalils\Downloads\files\data\raw_asc\e8dc6e4c905d_mosfet.asc
* Generated by LTspice 26.0.1 for Windows.
**********
*SRC=ARF463AB;ARF463AB;MOSFETs N;Enh;500V 9.0A 1.1ohms PPG Microsemi RF MOSFET
*SYM=POWMOSN
*09-14-09 Rev A GJK PPG Microsemi
* TERMINALS: D G S
*****
M1 1 2 3 3 DMOS L=1U W=1U
RD 11 1 1.1
RG 19 2 .5
R1 VDD N001 4
XM1 N001 G 0 ARF463AB ;pnba D)G)S
D2 5 2 DGD
RS 29 3 2.25m
LS 30 29 2n
V2 r 0 PWL(0 0 10e-3 8)
V3 p 0 PULSE(0 1 0 1p 1p 1.25e-05 250e-6)
LD 10 11 2n
B1 G 0 V=V(p)*V(r)
DSD 3 1 DSUB
D1 5 1 DGD
VDD VDD 0 125
CGS 2 3 1200p
LG 20 19 2.8n
R2 G 0 50
.tran 0 10e-3 0
.SUBCKT ARF463AB 10 20 30
.MODEL DMOS NMOS(LEVEL=3 VMAX=1.04Meg THETA=100.0m ETA=2.00m VTO=3.00 KP=2.60)
.MODEL DSUB D (IS=1.27u N=1.50 RS=5.00m BV=500 CJO=799p VJ=0.800 M=0.420 TT=311n)
.MODEL DGD D (IS=100n N=1.5 RS=10m BV=500 CJO=81.7p M=.5 VJ=.700 TT=1n)
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -480 -784 -624 -784
WIRE -432 -784 -480 -784
WIRE -384 -784 -432 -784
WIRE -480 -736 -480 -784
WIRE -624 -720 -624 -784
WIRE -624 -624 -624 -640
WIRE -1408 -576 -1408 -592
WIRE -1152 -560 -1152 -592
WIRE -480 -560 -480 -656
WIRE -1408 -544 -1408 -576
WIRE -1152 -544 -1152 -560
WIRE -752 -480 -960 -480
WIRE -576 -480 -752 -480
WIRE -528 -480 -576 -480
WIRE -1408 -448 -1408 -464
WIRE -1152 -448 -1152 -464
WIRE -752 -432 -752 -480
WIRE -480 -400 -480 -464
WIRE -960 -384 -960 -480
WIRE -752 -320 -752 -352
WIRE -960 -272 -960 -304
SYMBOL voltage -1408 -560 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 10e-3 8)
SYMBOL bv -960 -400 R0
SYMATTR InstName B1
SYMATTR Value V=V(p)*V(r)
SYMBOL res -768 -448 R0
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL voltage -1152 -560 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 0 1p 1p 1.25e-05 250e-6)
SYMBOL res -496 -752 R0
SYMATTR InstName R1
SYMATTR Value 4
SYMBOL nmos -528 -560 R0
SYMATTR InstName M1
SYMATTR Value ARF463AB
SYMATTR Prefix X
SYMBOL voltage -624 -736 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 125
FLAG -480 -400 0
FLAG -624 -624 0
FLAG -432 -784 VDD
FLAG -576 -480 G
FLAG -752 -320 0
FLAG -960 -272 0
FLAG -1408 -448 0
FLAG -1152 -448 0
FLAG -1152 -560 p
FLAG -1408 -576 r
TEXT -2144 -96 Left 2 !.tran 0 10e-3 0
TEXT -2152 -752 Left 2 !**********\n*SRC=ARF463AB;ARF463AB;MOSFETs N;Enh;500V 9.0A 1.1ohms PPG Microsemi RF MOSFET\n*SYM=POWMOSN\n*09-14-09 Rev A GJK PPG Microsemi\n.SUBCKT ARF463AB   10 20 30\n*     TERMINALS:  D  G  S\nM1   1  2  3  3  DMOS L=1U W=1U\nLD  10  11  2n\nRD  11          1   1.1\nLG  20  19  2.8n\nRG  19  2   .5\nD1   5  1   DGD\nD2   5  2   DGD\nCGS  2  3   1200p\nDSD  3  1   DSUB\nRS  29  3   2.25m\nLS  30  29  2n\n.MODEL DMOS NMOS(LEVEL=3 VMAX=1.04Meg THETA=100.0m ETA=2.00m VTO=3.00 KP=2.60)\n.MODEL DSUB D (IS=1.27u N=1.50 RS=5.00m BV=500 CJO=799p VJ=0.800 M=0.420 TT=311n)\n.MODEL DGD  D (IS=100n N=1.5 RS=10m BV=500 CJO=81.7p M=.5 VJ=.700 TT=1n)\n.ENDS\n*****
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1880.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1880.asy)
V3 N001 0 SINE(0 13.5 1K)
XU1 0 N002 +V -V N003 LT1880 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 1.5
V2 -V 0 -1.5
R1 N003 N002 100K
R2 N002 N001 1Meg
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 0 96 -112 96
WIRE 128 96 80 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -112 112 -112 96
WIRE -368 128 -368 112
WIRE -240 128 -240 112
WIRE -112 208 -112 192
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -368 240 -368 208
WIRE -240 240 -240 208
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 160 256 128 256
WIRE 192 288 192 272
SYMBOL voltage -240 112 R0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL res 96 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage -112 96 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 13.5 1K)
SYMBOL voltage -368 112 R0
SYMATTR InstName V2
SYMATTR Value -1.5
SYMBOL opamps\\LT1880 192 240 R0
SYMATTR InstName U1
FLAG -240 240 0
FLAG 192 192 +V
FLAG -240 112 +V
FLAG 192 288 -V
FLAG -368 240 0
FLAG -368 112 -V
FLAG -112 208 0
FLAG 128 256 0
TEXT -72 304 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\4057b12e4314_Qgate.asc
* Generated by LTspice 26.0.1 for Windows.
+ Cgdmax=1.9n Cgdmin=50p Cgs=3.1n Cjo=1n Is=5.5p
+ Rb=5.7m mfg=Siliconix Vds=30 Ron=15m Qg=60n)
D1 N001 N002 D
I1 0 N001 10.
M2 N001 gate 0 0 Si4410DY
B1 0 gate I=100u*(time > 0) Rpar=1G
V1 N002 0 15
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran .6m
.model D D(Ron=1u Roff=1T)
.options maxstep=.1u
.model Si4410DY VDMOS(Rd=3m Rs=3m Vto=2.6 Kp=60
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5945688 13421568
WIRE 1248 -512 1248 -528
WIRE 1248 -416 1248 -432
WIRE 1376 -528 1248 -528
WIRE 1440 -528 1376 -528
WIRE 1488 -608 1488 -640
WIRE 1488 -416 1488 -512
WIRE 1648 -640 1488 -640
WIRE 1648 -560 1648 -640
WIRE 1648 -416 1648 -480
WIRE 1696 -640 1648 -640
WIRE 1808 -640 1760 -640
WIRE 1808 -560 1808 -640
WIRE 1808 -416 1808 -480
SYMBOL bi2 1248 -512 R0
WINDOW 3 40 42 Left 0
WINDOW 39 23 80 Left 0
SYMATTR Value I=100u*(time > 0)
SYMATTR SpiceLine Rpar=1G
SYMATTR InstName B1
SYMBOL voltage 1808 -576 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL current 1648 -480 M180
WINDOW 0 24 88 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName I1
SYMATTR Value 10.
SYMBOL nmos 1440 -608 R0
WINDOW 0 52 12 Left 0
WINDOW 3 52 80 Left 0
SYMATTR InstName M2
SYMATTR Value Si4410DY
SYMBOL diode 1696 -624 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
FLAG 1248 -416 0
FLAG 1488 -416 0
FLAG 1808 -416 0
FLAG 1648 -416 0
FLAG 1376 -528 gate
TEXT 1064 -392 Left 0 !.tran .6m
TEXT 1064 -344 Left 0 !.model D D(Ron=1u Roff=1T)
TEXT 1064 -368 Left 0 !.options maxstep=.1u
TEXT 1064 -320 Left 0 !.model Si4410DY VDMOS(Rd=3m Rs=3m Vto=2.6 Kp=60\n+ Cgdmax=1.9n Cgdmin=50p Cgs=3.1n Cjo=1n Is=5.5p\n+ Rb=5.7m mfg=Siliconix Vds=30 Ron=15m Qg=60n)