* Z:\home\khalils\Downloads\files\data\raw_asc\17b6a739896a_the_circuit_finale.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .tran 0 100m 95m
* PULSE(-0.5 0.5 0 .5m .5m 1e-10 1m 1000)
* poner capacitancia grande en la salida y probar ciclo de histeresis
Vbias2 N005 N004 0
Vgs N004 0 PULSE(0 0.1 0 0.5m 0.5m 0 1m)
Vss Vss 0 -9
XMmirror3 N009 N010 Vss 2n7000 ;pnba D)G)S
Rd Vdd output 2k
R2 N008 N009 {r}
Rd2 Vdd N010 15.5k
R3 N007 N009 {r}
XM1 N002 N006 N008 2n7000 ;pnba D)G)S
R1 Vdd N003 1k
XMcasc output N001 N002 2n7000 ;pnba D)G)S
XM2 N003 N005 N007 2n7000 ;pnba D)G)S
Vbias N001 0 3
Vbias1 N006 0 0
Vdd Vdd 0 9
XMmirror4 N010 N010 Vss 2n7000 ;pnba D)G)S
.dc Vgs -2 2.2 0.001
.include 2N7000.REV0.SP
.step param r list 100 500 1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1940 1232
WIRE 400 -176 400 -208
WIRE 496 -176 496 -208
WIRE 1392 -112 1392 -144
WIRE 400 -64 400 -96
WIRE 496 -64 496 -96
WIRE 1392 0 1392 -32
WIRE 1392 32 1392 0
WIRE 1344 112 1248 112
WIRE 1248 208 1248 192
WIRE 704 224 704 144
WIRE 1392 352 1392 128
WIRE 1392 352 928 352
WIRE 704 416 704 304
WIRE 928 416 928 352
WIRE 528 496 256 496
WIRE 656 496 608 496
WIRE 1088 496 976 496
WIRE 1184 496 1168 496
WIRE 704 560 704 512
WIRE 1184 560 1184 496
WIRE 928 576 928 512
WIRE 528 624 528 592
WIRE 704 704 704 640
WIRE 928 704 928 656
WIRE 928 704 704 704
WIRE 528 736 528 704
WIRE 592 736 528 736
WIRE 528 752 528 736
WIRE 704 752 704 704
WIRE 592 832 592 736
WIRE 592 832 576 832
WIRE 656 832 592 832
WIRE 528 896 528 848
WIRE 704 896 704 848
WIRE 256 1104 256 496
WIRE 256 1216 256 1184
SYMBOL voltage 400 -192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vdd
SYMATTR Value 9
SYMBOL res 688 544 R0
SYMATTR InstName R3
SYMATTR Value {r}
SYMBOL nmos 576 752 M0
SYMATTR InstName Mmirror4
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL nmos 656 752 R0
SYMATTR InstName Mmirror3
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL res 912 560 R0
SYMATTR InstName R2
SYMATTR Value {r}
SYMBOL voltage 256 1088 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vgs
SYMATTR Value PULSE(0 0.1 0 0.5m 0.5m 0 1m)
SYMBOL battery 624 496 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Vbias2
SYMATTR Value 0
SYMBOL voltage 1248 96 R0
WINDOW 0 -82 18 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vbias
SYMATTR Value 3
SYMBOL voltage 496 -192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vss
SYMATTR Value -9
SYMBOL nmos 656 416 R0
SYMATTR InstName M2
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL nmos 1344 32 R0
SYMATTR InstName Mcasc
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL res 688 208 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 1376 -128 R0
SYMATTR InstName Rd
SYMATTR Value 2k
SYMBOL nmos 976 416 M0
SYMATTR InstName M1
SYMATTR Value 2n7000
SYMATTR Prefix X
SYMBOL res 512 608 R0
SYMATTR InstName Rd2
SYMATTR Value 15.5k
SYMBOL battery 1072 496 M90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Vbias1
SYMATTR Value 0
FLAG 256 1216 0
FLAG 400 -64 0
FLAG 400 -208 Vdd
FLAG 1392 -144 Vdd
FLAG 1248 208 0
FLAG 496 -64 0
FLAG 496 -208 Vss
FLAG 528 592 Vdd
FLAG 528 896 Vss
FLAG 704 896 Vss
FLAG 704 144 Vdd
FLAG 1184 560 0
FLAG 1392 0 output
TEXT 648 -264 Left 2 !.dc Vgs -2 2.2 0.001
TEXT 640 -216 Left 2 !.include 2N7000.REV0.SP
TEXT 920 920 Left 2 !.step param r list 100 500 1k
TEXT 664 -72 Left 2 ;.op
TEXT 656 -40 Left 2 ;.tran 0 100m 95m
TEXT 296 1216 Left 2 ;PULSE(-0.5 0.5 0 .5m .5m 1e-10 1m 1000)
TEXT 360 48 Left 2 ;poner capacitancia grande en la salida y probar ciclo de histeresis