Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\3d80200d9ffc_4_8a.asc
* Generated by LTspice 26.0.1 for Windows.
VCC Vcc 0 10V
R1 Out Triangle 100k
C1 Triangle 0 10n
VEE Vee 0 -10V
R2 Out N001 100k
XU1 N001 Triangle Vcc Vee Out uA741 ;pnba In+)In-)V+)V-)OUT
R3 N001 0 100k
.inc uA741.lib
.tran .02
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 940 680
WIRE 688 -80 336 -80
WIRE 336 -64 336 -80
WIRE -96 16 -96 -16
WIRE 0 16 0 -16
WIRE 336 64 336 16
WIRE 480 64 336 64
WIRE 688 80 688 -80
WIRE 688 80 544 80
WIRE 880 80 688 80
WIRE 480 96 432 96
WIRE 688 112 688 80
WIRE -96 128 -96 96
WIRE 0 128 0 96
WIRE 432 224 432 96
WIRE 688 224 688 192
WIRE 688 224 432 224
WIRE 336 256 336 64
WIRE 688 256 688 224
WIRE 336 352 336 320
WIRE 480 352 336 352
WIRE 688 352 688 336
WIRE 688 352 480 352
WIRE 480 400 480 352
SYMBOL res 672 240 R0
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL res 672 96 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL OpAmps\\opamp2 512 16 R0
SYMATTR InstName U1
SYMATTR Value uA741
SYMBOL voltage 0 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VEE
SYMATTR Value -10V
SYMBOL cap 320 256 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL voltage -96 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VCC
SYMATTR Value 10V
SYMBOL res 320 -80 R0
SYMATTR InstName R1
SYMATTR Value 100k
FLAG -96 128 0
FLAG 0 128 0
FLAG -96 -16 Vcc
FLAG 0 -16 Vee
FLAG 512 48 Vcc
FLAG 512 112 Vee
FLAG 480 400 0
FLAG 880 80 Out
FLAG 336 64 Triangle
TEXT -104 216 Left 2 !.inc uA741.lib
TEXT -96 272 Left 2 !.tran .02
* Z:\home\khalils\Downloads\files\data\raw_asc\00eb9b1b5654_25._.asc
* Generated by LTspice 26.0.1 for Windows.
V1 NC_01 NC_02 V
V2 NC_03 NC_04 V
V3 NC_05 NC_06 V
R1 NC_07 NC_08 R
C1 NC_09 NC_10 C
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
SYMBOL voltage -64 144 R0
SYMATTR InstName V1
SYMBOL voltage 144 416 R0
SYMATTR InstName V2
SYMBOL voltage 336 416 R0
SYMATTR InstName V3
SYMBOL res 224 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMBOL cap 256 96 R0
SYMATTR InstName C1
* Z:\home\khalils\Downloads\files\data\raw_asc\4e4e656bd5c0_Assignment_3b__i_.asc
* Generated by LTspice 26.0.1 for Windows.
* Negative Half Wave Rectifier Circuit (Practical)
D1 N002 N001 1N4148
V1 N001 0 SINE(0 5 1000) Rser=0.001
R1 N002 0 1000
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5ms
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 192 64 80 64
WIRE 352 64 256 64
WIRE 80 112 80 64
WIRE 352 112 352 64
WIRE 80 240 80 192
WIRE 176 240 80 240
WIRE 352 240 352 192
WIRE 352 240 176 240
WIRE 176 272 176 240
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1000)
SYMBOL diode 256 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 336 96 R0
SYMATTR InstName R1
SYMATTR Value 1000
FLAG 176 272 0
TEXT 16 272 Left 2 !.tran 5ms
TEXT -24 8 Left 2 ;Negative Half Wave Rectifier Circuit (Practical)
* Z:\home\khalils\Downloads\files\data\raw_asc\658b92d6440d_Non_Inverting_Amplifier.asc
* Generated by LTspice 26.0.1 for Windows.
* NON INVERTING AMPLIFIER
Rg N002 0 1k
R1 vout N002 9k
E1 vout 0 N001 N002 1e9
V1 N001 0 1
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 80 304 80
WIRE 400 80 384 80
WIRE 256 112 16 112
WIRE 304 112 304 80
WIRE 256 128 256 112
WIRE 16 160 16 112
WIRE 256 176 144 176
WIRE 144 240 144 176
WIRE 192 240 144 240
WIRE 384 240 384 80
WIRE 384 240 272 240
WIRE 144 256 144 240
WIRE 16 288 16 240
WIRE 144 432 144 336
IOPIN 400 80 Out
SYMBOL res 288 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 9k
SYMBOL e 304 96 R0
SYMATTR InstName E1
SYMATTR Value 1e9
SYMBOL res 128 240 R0
SYMATTR InstName Rg
SYMATTR Value 1k
SYMBOL voltage 16 144 R0
SYMATTR InstName V1
SYMATTR Value 1
FLAG 304 192 0
FLAG 16 288 0
FLAG 400 80 vout
FLAG 144 432 0
TEXT -104 32 Left 2 !.op
TEXT 32 -24 Left 2 ;NON INVERTING AMPLIFIER
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4636.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4636.asy)
R1 N002 0 34.8K
R4 N003 N006 15K
C1 N007 0 100p
R3 OUT 0 25m
C2 OUT 0 470 x3 Rser=5m
C4 N006 0 .1
R2 N008 0 7.5K
C3 OUT 0 100 x4 Rser=1m
XU1 IN N004 0 N008 N007 N001 N001 N004 N006 0 OUT N005 N005 NC_01 N003 IN NC_02 NC_03 OUT NC_04 0 0 N002 NC_05 LTM4636 ;pnba Vin)COMPA)VoutS1-)VFB)TK/SS)HiZReg)IntVcc)COMPB)RunC)SGND)VOUT)SNSP2)SNSP1)PGood)PVCC)RunP)SW)PWM2)VoutS1+)Clkout)PGND)Mode/PLLIN)Freq)PhaseMD
V1 IN 0 12
.tran 1.2m startup
.lib LTM4636.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1268 728
WIRE 64 -208 -272 -208
WIRE 192 -208 64 -208
WIRE 448 -208 320 -208
WIRE -272 -192 -272 -208
WIRE 64 -176 64 -208
WIRE 192 -176 192 -208
WIRE 320 -176 320 -208
WIRE 448 -176 448 -208
WIRE -144 -112 -160 -112
WIRE -32 -112 -64 -112
WIRE -272 -96 -272 -112
WIRE -32 -16 -48 -16
WIRE 640 80 544 80
WIRE 752 80 640 80
WIRE 928 80 752 80
WIRE 640 96 640 80
WIRE 752 96 752 80
WIRE 928 160 928 80
WIRE 928 160 880 160
WIRE -32 176 -224 176
WIRE 576 176 544 176
WIRE 640 176 640 160
WIRE 752 176 752 160
WIRE 928 192 928 160
WIRE 592 208 576 176
WIRE 848 208 880 160
WIRE 848 208 592 208
WIRE 848 240 592 240
WIRE -32 272 -64 272
WIRE 576 272 592 240
WIRE 576 272 544 272
WIRE 880 288 848 240
WIRE 928 288 928 272
WIRE 928 288 880 288
WIRE 928 304 928 288
WIRE -224 352 -224 176
WIRE -64 368 -64 272
WIRE -32 368 -64 368
WIRE 576 368 544 368
WIRE -224 464 -224 432
WIRE -32 464 -224 464
WIRE 576 464 576 368
WIRE 576 464 544 464
WIRE -224 480 -224 464
WIRE -224 560 -224 544
WIRE -112 560 -128 560
WIRE -32 560 -48 560
WIRE 576 560 544 560
WIRE 672 560 656 560
WIRE 192 640 192 624
WIRE 320 640 320 624
SYMBOL res 560 576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 7.5K
SYMBOL voltage -272 -208 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res -240 336 R0
SYMATTR InstName R4
SYMATTR Value 15K
SYMBOL cap -240 480 R0
SYMATTR InstName C4
SYMATTR Value .1
SYMBOL PowerProducts\\LTM4636 272 224 R0
SYMATTR InstName U1
SYMBOL res 912 176 R0
SYMATTR InstName R3
SYMATTR Value 25m
SYMBOL cap -48 544 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL cap 736 96 R0
WINDOW 3 37 30 Left 2
WINDOW 123 26 57 Left 2
SYMATTR Value 100
SYMATTR Value2 x4
SYMATTR InstName C3
SYMATTR SpiceLine Rser=1m
SYMBOL res -48 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 34.8K
SYMBOL cap 624 96 R0
WINDOW 3 35 32 Left 2
WINDOW 123 25 59 Left 2
SYMATTR Value 470
SYMATTR Value2 x3
SYMATTR InstName C2
SYMATTR SpiceLine Rser=5m
FLAG -272 -96 0
FLAG 672 560 0
FLAG 192 640 0
FLAG 320 640 0
FLAG -160 -112 0
FLAG -224 560 0
FLAG -128 560 0
FLAG 640 176 0
FLAG 928 304 0
FLAG -48 -16 0
FLAG 928 80 OUT
FLAG 752 176 0
FLAG -272 -208 IN
TEXT 680 640 Left 2 !.tran 1.2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\6d53312ee55e_VCO.asc
* Generated by LTspice 26.0.1 for Windows.
* Voltage Controlled Oscillator
* frequency(Hz)
* clock
* duty 50%
* 2025-02-15
* <Revision History>\n2024-12-29: Initial version\n2025-02-15: Removed 1Mohm pull down resistor at freq pin to avoid large sink current.
* removed
A1 b 0 0 0 0 0 clk 0 BUF
B1 N001 a I=IF(V(b),0,V(freq))
B2 a 0 I=IF(V(b),V(freq),0)
R1 b 0 1k
C1 a 0 1
V2 N001 0 1
.machine
.state LO 0
.state HI 1
.rule LO HI V(a)>0.75
.rule HI LO V(a)<0.25
.output (b) state
.endmachine
.ic V(a)=0.25
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1132 680
WIRE 176 -176 80 -176
WIRE 80 -144 80 -176
WIRE 176 -112 176 -176
WIRE 80 -32 80 -64
WIRE -64 48 -112 48
WIRE 176 48 176 -32
WIRE 320 48 176 48
WIRE 400 48 320 48
WIRE 560 48 560 32
WIRE 704 48 560 48
WIRE 816 48 768 48
WIRE -64 64 -64 48
WIRE 320 64 320 48
WIRE 560 64 560 48
WIRE 704 80 704 64
WIRE 176 112 176 48
WIRE 320 144 320 128
WIRE -64 176 -64 144
WIRE 560 176 560 144
WIRE 176 224 176 192
IOPIN 816 48 Out
IOPIN -112 48 In
SYMBOL cap 304 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL bi 176 112 R0
SYMATTR InstName B2
SYMATTR Value I=IF(V(b),V(freq),0)
SYMBOL voltage 80 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL res 544 48 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL bi 176 -112 R0
SYMATTR InstName B1
SYMATTR Value I=IF(V(b),0,V(freq))
SYMBOL Digital\\buf1 704 -16 R0
SYMATTR InstName A1
FLAG 320 144 0
FLAG 560 176 0
FLAG 176 224 0
FLAG 80 -32 0
FLAG 400 48 a
FLAG 560 32 b
FLAG 704 80 0
FLAG 816 48 clk
FLAG -112 48 freq
FLAG -64 176 0
TEXT 544 -176 Left 2 !.machine\n.state LO 0\n.state HI 1\n.rule LO HI V(a)>0.75\n.rule HI LO V(a)<0.25\n.output (b) state\n.endmachine
TEXT 200 24 Left 2 !.ic V(a)=0.25
TEXT -208 -264 Left 4 ;Voltage Controlled Oscillator
TEXT -176 16 Left 2 ;frequency(Hz)
TEXT 808 16 Left 2 ;clock
TEXT 800 80 Left 2 ;duty 50%
TEXT 592 -240 Left 2 ;2025-02-15
TEXT -168 264 Left 2 ;<Revision History>\n2024-12-29: Initial version\n2025-02-15: Removed 1Mohm pull down resistor at freq pin to avoid large sink current.
TEXT -96 112 Left 2 ;removed
* Z:\home\khalils\Downloads\files\data\raw_asc\31bc697b7e9f_Mod_Generator.asc
* Generated by LTspice 26.0.1 for Windows.
V1 low_freq 0 PULSE(0.7 1.3 0 50u 50u 0 100u)
V2 high_freq 0 SINE(0 1 1Meg 0 0 90)
B1 mod 0 V=V(low_freq)*V(high_freq)
D2 mod N001 D
C2 N001 0 2n
R2 N001 0 10k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.5e-3
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1668 680
WIRE 1168 -16 1088 -16
WIRE 1296 -16 1168 -16
WIRE 1168 16 1168 -16
WIRE 1296 16 1296 -16
WIRE -208 112 -208 16
WIRE 256 128 256 32
WIRE 640 144 640 32
WIRE 1168 160 1168 80
WIRE 1248 160 1168 160
WIRE 1296 160 1296 96
WIRE 1296 160 1248 160
WIRE 1248 208 1248 160
WIRE -208 288 -208 192
WIRE 256 304 256 208
WIRE 640 304 640 224
FLAG -208 288 0
FLAG 256 304 0
FLAG -208 16 low_freq
FLAG 256 32 high_freq
FLAG 640 304 0
FLAG 640 32 mod
FLAG 1024 -16 mod
FLAG 1248 208 0
SYMBOL voltage -208 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0.7 1.3 0 50u 50u 0 100u)
SYMBOL voltage 256 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 1Meg 0 0 90)
SYMBOL bv 640 128 R0
SYMATTR InstName B1
SYMATTR Value V=V(low_freq)*V(high_freq)
SYMBOL diode 1024 0 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMBOL cap 1152 16 R0
SYMATTR InstName C2
SYMATTR Value 2n
SYMBOL res 1280 0 R0
SYMATTR InstName R2
SYMATTR Value 10k
TEXT -240 312 Left 2 !.tran 0.5e-3
* Z:\home\khalils\Downloads\files\data\raw_asc\5623ffba39af_scheme7.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1014.asy)
XU1 N005 N003 N001 N007 N004 LT1013 ;pnba In+)In-)V+)V-)OUT
Vin N002 0 DC 0
R2 N005 N006 10k
V2 N006 0 1
R1 N003 N002 10k
V4 0 N007 {Vcc}
V3 N001 0 {Vcc}
.dc Vin {-1.1*Vcc} {1.1*Vcc} 0.01
.param Vcc=22
.lib LT1013.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 416 48 240 48
WIRE 416 64 416 48
WIRE 64 96 -80 96
WIRE 176 96 144 96
WIRE -80 112 -80 96
WIRE 240 128 240 48
WIRE 176 144 176 96
WIRE 208 144 176 144
WIRE 368 160 272 160
WIRE 416 160 416 144
WIRE 496 160 416 160
WIRE 208 176 176 176
WIRE 416 176 416 160
WIRE 496 176 496 160
WIRE 64 208 -16 208
WIRE 176 208 176 176
WIRE 176 208 144 208
WIRE -16 240 -16 208
WIRE 240 272 240 192
WIRE 416 272 416 256
WIRE 416 272 240 272
SYMBOL voltage 416 160 R0
SYMATTR InstName V4
SYMATTR Value {Vcc}
SYMBOL voltage -80 96 R0
SYMATTR InstName Vin
SYMATTR Value DC 0
SYMBOL voltage 416 48 R0
SYMATTR InstName V3
SYMATTR Value {Vcc}
SYMBOL OpAmps\\LT1014 240 96 R0
SYMATTR InstName U1
SYMBOL res 160 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 160 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -16 224 R0
SYMATTR InstName V2
SYMATTR Value 1
FLAG 496 176 0
FLAG -16 320 0
FLAG -80 192 0
TEXT 80 320 Left 2 !.dc Vin {-1.1*Vcc} {1.1*Vcc} 0.01
TEXT -104 64 Left 2 !.param Vcc=22
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG858.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N004 0 PULSE(0 3 25u 1n 1n 20u)
R1 N002 0 49.9
C1 N002 0 36p
V2 N001 0 3
V3 +V 0 5
XU1 N004 N001 N002 N003 +V 0 ADG858 ;pnba IN)SA)D)SB)Vdd)GND
V4 N003 0 0
.tran 75u
* Note:\nCharge Injection not included\nOnly One channel included\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG858.asy)
.lib ADG858.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 0 -48 -48
WIRE -144 64 -512 64
WIRE -512 96 -512 64
WIRE 128 96 48 96
WIRE 256 96 128 96
WIRE -144 128 -400 128
WIRE 128 128 128 96
WIRE 256 128 256 96
WIRE -512 192 -512 176
WIRE -400 192 -400 128
WIRE -144 192 -288 192
WIRE 128 240 128 208
WIRE 256 240 256 192
WIRE -400 304 -400 272
WIRE -288 304 -288 192
WIRE -512 320 -512 304
WIRE -48 336 -48 304
WIRE -512 416 -512 400
WIRE -288 448 -288 384
FLAG 128 240 0
FLAG 256 240 0
FLAG -48 336 0
FLAG -288 448 0
FLAG -512 192 0
FLAG -48 -48 +V
FLAG -512 416 0
FLAG -512 304 +V
FLAG -400 304 0
SYMBOL voltage -288 288 R0
WINDOW 3 24 102 Left 2
SYMATTR Value PULSE(0 3 25u 1n 1n 20u)
SYMATTR InstName V1
SYMBOL res 112 112 R0
SYMATTR InstName R1
SYMATTR Value 49.9
SYMBOL cap 240 128 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -512 80 R0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL voltage -512 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL ADG858 -48 144 R0
SYMATTR InstName U1
SYMBOL voltage -400 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
TEXT -264 416 Left 2 !.tran 75u
TEXT -536 -112 Left 2 ;Note:\nCharge Injection not included\nOnly One channel included\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6210.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6210.asy)
V3 N003 0 pulse(-25m 25m 30n 1n 1n 35n 70n)
R2 N002 N001 1.1K
XU1 N003 N001 +V -V N002 P001 LT6210 ;pnba In+)In-)V+)V-)OUT)V-1
R4 N002 0 150
R3 N001 0 1.1K
V2 -V 0 -5
R1 P001 0 56K
V1 +V 0 5
.tran 100n
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 48 48 48
WIRE 176 48 144 48
WIRE 208 48 176 48
WIRE 304 48 288 48
WIRE -288 96 -288 80
WIRE -176 96 -176 80
WIRE 176 176 176 48
WIRE 192 176 176 176
WIRE -288 192 -288 176
WIRE -176 192 -176 176
WIRE 304 208 304 48
WIRE 304 208 288 208
WIRE 400 208 304 208
WIRE 400 224 400 208
WIRE -80 240 -112 240
WIRE 192 240 0 240
WIRE 400 320 400 304
WIRE 240 368 240 352
SYMBOL voltage -176 80 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL opamps\\LT6210 224 208 R0
SYMATTR InstName U1
SYMBOL voltage 16 240 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value pulse(-25m 25m 30n 1n 1n 35n 70n)
SYMBOL res 160 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.1K
SYMBOL res 384 208 R0
SYMATTR InstName R4
SYMATTR Value 150
SYMBOL res 304 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.1K
SYMBOL res 224 256 R0
SYMATTR InstName R1
SYMATTR Value 56K
SYMBOL voltage -288 80 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -176 192 0
FLAG -288 192 0
FLAG -288 80 +V
FLAG 208 144 +V
FLAG -176 80 -V
FLAG 208 272 -V
FLAG 240 368 0
FLAG 48 48 0
FLAG -112 240 0
FLAG 400 320 0
TEXT 352 400 Left 2 !.tran 100n
* Z:\home\khalils\Downloads\files\data\raw_asc\097057c10774_1260.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1260.asy)
V3 IN 0 SINE(0 1 1K)
R2 N001 0 1.6K
R1 OUT N001 1.6K
V2 -V 0 -5
XU1 IN N001 +V -V OUT LT1259 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 5
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -288 144 -288 128
WIRE -160 144 -160 128
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -288 240 -288 224
WIRE -160 240 -160 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL voltage -288 128 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.6K
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL voltage -160 128 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1.6K
SYMBOL opamps\\LT1260 192 176 R0
SYMATTR InstName U1
FLAG -160 240 0
FLAG 192 192 +V
FLAG -160 128 +V
FLAG 192 288 -V
FLAG -288 240 0
FLAG -288 128 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 288 240 OUT
FLAG 0 256 IN
TEXT 264 336 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\da66c1bce54b_Ej1.asc
* Generated by LTspice 26.0.1 for Windows.
C3 N004 N003 {C}
C2 N003 N002 {C1}
R1 N004 0 0.00000001m
C1 0 N005 {C2}
L2 N003 N005 {L2} Rser=1m
L1 N002 N001 {L1} Rser=1m
V1 N001 0 AC 1 0 Rser=0.0000001
.param Ww=(2*pi)
.param L1=1/(3*Ww)
.param L2=1/(6*Ww)
.param C1=(3)/(4*Ww)
.param C2=6/Ww
.param C=(9)/(2*Ww)
.net I(R1) V1
.ac dec 1000 0.01 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 96 -80 96
WIRE 128 96 96 96
WIRE 288 96 192 96
WIRE 368 96 288 96
WIRE 528 96 432 96
WIRE 288 128 288 96
WIRE -80 176 -80 96
WIRE 528 176 528 96
WIRE 288 240 288 208
WIRE -80 336 -80 256
WIRE 288 336 288 304
WIRE 288 336 -80 336
WIRE 528 336 528 256
WIRE 528 336 288 336
WIRE 288 384 288 336
SYMBOL cap 192 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value {C1}
SYMBOL voltage -80 160 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMATTR SpiceLine Rser=0.0000001
SYMBOL cap 304 304 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value {C2}
SYMBOL ind 112 80 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value {L1}
SYMATTR SpiceLine Rser=1m
SYMBOL res 512 160 R0
SYMATTR InstName R1
SYMATTR Value 0.00000001m
SYMBOL ind 272 112 R0
SYMATTR InstName L2
SYMATTR Value {L2}
SYMATTR SpiceLine Rser=1m
SYMBOL cap 432 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value {C}
FLAG 288 384 0
TEXT -128 368 Left 2 !.param Ww=(2*pi)\n.param L1=1/(3*Ww)\n.param L2=1/(6*Ww)\n.param C1=(3)/(4*Ww) \n.param C2=6/Ww\n.param C=(9)/(2*Ww)
TEXT -128 536 Left 2 !.net I(R1) V1
TEXT -128 560 Left 2 !.ac dec 1000 0.01 100
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
V1 IN 0 3.3
Rload OUT 0 50
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-4.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
.tran 400u startup
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-4.5.asy)
.lib ADP2503-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2503-4.5 176 176 R0
SYMATTR InstName U1
TEXT 424 392 Left 2 !.tran 400u startup
TEXT 184 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX20337.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nCharge Injection not included
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\MAX20337.asy)
C1 vCOM 0 15p
R1 vCOM 0 300
V3 vNC 0 SINE(0 5 100)
V6 vCB 0 PULSE(0 1.8 20n 20n 20n 150m 300m)
XU1 vCOM vCB 0 +V 0 vNC MAX20337 ;pnba COM)CB)GND)VccEN)NO)NC
V1 +V 0 5
.tran 1
.lib MAX20337.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 224 96 224 64
WIRE -272 144 -272 128
WIRE -80 160 -112 160
WIRE 96 160 0 160
WIRE 128 160 96 160
WIRE 368 192 320 192
WIRE 448 192 368 192
WIRE 544 192 448 192
WIRE 96 224 48 224
WIRE 128 224 96 224
WIRE 448 224 448 192
WIRE -272 240 -272 224
WIRE 544 240 544 192
WIRE 96 288 32 288
WIRE 128 288 96 288
WIRE 448 320 448 304
WIRE 544 320 544 304
WIRE 32 336 32 288
WIRE 224 416 224 400
WIRE 32 464 32 416
SYMBOL cap 528 240 R0
SYMATTR InstName C1
SYMATTR Value 15p
SYMBOL voltage 16 160 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 5 100)
SYMBOL voltage -272 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 32 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 1.8 20n 20n 20n 150m 300m)
SYMATTR InstName V6
SYMBOL MAX20337 224 240 R0
SYMATTR InstName U1
SYMBOL res 432 208 R0
SYMATTR InstName R1
SYMATTR Value 300
FLAG -272 240 0
FLAG -272 128 +V
FLAG -112 160 0
FLAG 32 464 0
FLAG 448 320 0
FLAG 544 320 0
FLAG 224 64 +V
FLAG 224 416 0
FLAG 96 160 vNC
FLAG 368 192 vCOM
FLAG 48 224 0
FLAG 96 224 vNO
FLAG 96 288 vCB
TEXT -280 504 Left 2 !.tran 1
TEXT -296 -80 Left 2 ;Note:\nSwitch shown for a logic 0 input\nCharge Injection not included