* Z:\home\khalils\Downloads\files\data\raw_asc\3917d43a2efe_data_slicer.asc
* Generated by LTspice 26.0.1 for Windows.
* Standard Leaky Comparator
*$
* TLV354
*************************************************************************************************
* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.
*************************************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensor's and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose. The model is
** provided solely on an "as is" basis. The entire risk as to its quality
** and performance is with the customer
*************************************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*************************************************************************************************
*
** Released by: Online Design Tools, Texas Instruments Inc.
* Part: TLV354
* Date: 13FEB2019
* Model Type: Generic (suitable for all analysis types)
* EVM Order Number: N/A
* EVM Users Guide: N/A
* Datasheet: SBOS756 -OCTOBER 2016
* Created with Green-Williams-Lis Op Amp Macro-model Architecture
*
* Model Version: Final 1.2
*
*****************************************************************************
*
* Updates:
*
* Final 1.2
* Updated with unique subckt name,Current Noise, Vos drift and edits in claw block
*
*
* Final 1.1
* Release to Web.
*
****************************************************************************
* Model Usage Notes:
* 1. The following parameters are modeled:
* OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol)
* UNITY GAIN BANDWIDTH (GBW)
* INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)
* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)
* DIFFERENTIAL INPUT IMPEDANCE (Zid)
* COMMON-MODE INPUT IMPEDANCE (Zic)
* OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)
* OUTPUT CURRENT THROUGH THE SUPPLY (Iout)
* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)
* INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)
* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)
* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
* QUIESCENT CURRENT (Iq)
* SETTLING TIME VS. CAPACITIVE LOAD (ts)
* SLEW RATE (SR)
* SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD
* LARGE SIGNAL RESPONSE
* OVERLOAD RECOVERY TIME (tor)
* INPUT BIAS CURRENT (Ib)
* INPUT OFFSET CURRENT (Ios)
* INPUT OFFSET VOLTAGE (Vos)
* INPUT OFFSET VOLTAGE VS. TEMPERATURE (VOS DRIFT)
* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
* INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)
* INPUT/OUTPUT ESD CELLS (ESDin, ESDout)
******************************************************
******************************************************
* MODEL DEFINITIONS:
******************************************************
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* Library below included based on ModelFile attribute of instance XU2, XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
+(0, 1.0064e-4)
+(10, 1.28e-4)
+(20, 2.16e-4)
+(50, 5.31e-4)
+(90.6, 9.91e-4)
+(120, 1.39e-3)
+(140, 1.7e-3)
+(163.7, 2.16e-3)
+(0, 1.0064e-4)
+(9.82, 1.1e-4)
+(20, 2.31e-4)
+(40.51, 4.34e-4)
+(70, 7.51e-4)
+(100, 1.17e-3)
+(120, 1.52e-3)
+(150, 2.11e-3)
S6 VCC OUT OUT VCC ESD_SW
VCM_MIN N040 VEE_B -0.1
C22 N002 N001 4.547e-15
R4 5 0 {RNV}
R7 N040 MID R_NOISELESS 1e12
Xi_nn VOS- MID FEMT_TLV354
XVCCS_LIM_1_TLV354 VCM_CLAMP FB- MID GAIN_1 VCCS_LIM_1_TLV354
R28 N023 N022 R_NOISELESS 1e-3
C14 N041 MID 7.23e-16
D2 N001 N006 RB886CM
C9 MID N018 1e-15
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )}
C1 N054 0 1
C29 MID N056 4.823e-14
C25 N004 N003 6.366e-14
R52 MID N011 R_NOISELESS 1T
R47 N050 VCLP R_NOISELESS 100
R79 MID N049 R_NOISELESS 3.311e1
C5 MID N014 1e-15
E1 MID 0 N054 0 1
R36 N032 MID R_NOISELESS 1
R15 MID VCC_CLP R_NOISELESS 1e3
R18 VOUT_S N045 R_NOISELESS 100
R_PSR PSR N036 R_NOISELESS 1e3
R62 N005 N006 R_NOISELESS 1e8
G_CMR VOS CMR N007 MID 1e-3
D1 7 0 DVN
C2 N053 0 1e-15
C19 MID N019 1e-15
G_Zo MID N042 CL_CLAMP N052 89
R6 MID N039 R_NOISELESS 1e12
I_Q VCC VEE 5.2e-3
R7 4 0 1E9
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
R3 3 6 1E9
E1 VOUT+ VOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Vneg,Vpos)}
Rdummy1 N052 MID R_NOISELESS 6.67e3
H1 N044 MID V4 1e3
XIQp VIMON MID VCC MID VCCS_LIM_IQ_TLV354
XGR_AMP N012 N035 N019 MID N020 N032 CLAMP_AMP_HI_TLV354
R5 5 0 {RNV}
S9 CLAMP N029 N029 CLAMP OR_SW
S8 N030 CLAMP CLAMP N030 OR_SW
R38 MID N020 R_NOISELESS 1
C_DIFF N011 VOS- 2e-12
R11 MID N045 R_NOISELESS 1e12
R43 MID VSENSE R_NOISELESS 1e3
R16 N014 N013 R_NOISELESS 1e-3
R19 N034 MID R_NOISELESS 1e9
R59 N053 N054 R_NOISELESS 1e6
V12 N030 VD2 0
E2 6 4 5 0 10
C6 N027 MID 1e-15
C11 MID N016 1e-15
R27 N015 N016 R_NOISELESS 1e-3
S7 OUT VEE VEE OUT ESD_SW
XCLAWp VIMON MID N013 VCC_B VCCS_LIM_CLAWp_TLV354
R8 N006 NC_01 100
C13 VIMON MID 1e-12
R8 N038 MID R_NOISELESS 1
I1 0 7 10E-3
D2 8 0 DVN
R21 MID N017 R_NOISELESS 1
XIQn MID VIMON VEE MID VCCS_LIM_IQ_TLV354
GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
XCLAW_SRC N016 N023 CLAW_CLAMP MID VCCS_LIM_3_TLV354
R14 VEE_CLP MID R_NOISELESS 1e3
XOL_SENSE_TLV354 MID N057 OLN OLP OL_SENSE_TLV354
R17 N027 N026 R_NOISELESS 1e-3
XVCM_CLAMP PSR MID N038 MID N039 N040 VCCS_EXT_LIM_TLV354
C18 N033 MID 1e-15
R63 N004 MID R_NOISELESS 2.501e4
C4 N002 0 1n
C7 VOUT_S MID 1e-12
G16 0 VCC_B VCC 0 1
E1 3 6 7 8 {GLF}
R3 N054 0 R_NOISELESS 1e12
G_PSR N036 PSR N010 N009 1e-3
XGR_SRC N021 N033 CLAMP MID VCCS_LIM_GR_TLV354
C8 N025 MID 1e-15
E6 VD2 MID N031 MID 1
R32 N057 SW_OL R_NOISELESS 100
XCL_SRC N018 N025 CL_CLAMP MID VCCS_LIM_4_TLV354
XVCCS_LIM_2_TLV354 GAIN_1 MID MID CLAMP VCCS_LIM_2_TLV354
V_ISCp N008 MID 150
D1 N008 N010 1N5819
XU1 N004 N002 3v3 0 out level2 Avol=10Meg GBW=10G Slew=10G Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Xi_np N037 MID FEMT_TLV354
R_CMR CMR VOS R_NOISELESS 1e3
R77 N048 MID R_NOISELESS 1
R37 N035 MID R_NOISELESS 1e9
G17 0 VEE_B VEE 0 1
R76 N056 N047 R_NOISELESS 10e3
XU2 N012 N009 3v3 0 N011 level2 Avol=10Meg GBW=10G Slew=10G Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
Rsrc3 N006 MID R_NOISELESS 1
S2 VCC IN- IN- VCC ESD_SW
R24 N022 MID R_NOISELESS 1
E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
G_adjust2 MID N006 VCC_B MID 8.834e-1
R9 N038 VCM_CLAMP R_NOISELESS 1e-3
V1 N001 N013 PULSE(0.6 0.7 10u 10n 200n 0.2u 1u)
H3 OLP MID V12 1
R10 3v3 N002 1Meg
GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
R45 MID CLAW_CLAMP R_NOISELESS 1e3
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
R60 N054 N055 R_NOISELESS 1e6
C30 N049 N048 4.823e-14
E7 VD1 MID N028 MID 1
R26 MID VCC_CLP R_NOISELESS 1e9
R61 N005 MID R_NOISELESS 4.256e4
R34 N011 IN+ R_NOISELESS 1e-3
R2 N009 N008 100k
R30 N025 N024 R_NOISELESS 1e-3
R88 VCC_B 0 R_NOISELESS 1
G1 1 2 3 0 1e-6
C3 N003 0 3p
R31 N057 MID R_NOISELESS 1
R39 MID N012 R_NOISELESS 1e9
S3 VCC IN+ IN+ VCC ESD_SW
R4 N008 N001 10k
Rdc N042 MID R_NOISELESS 1
R70 MID N043 R_NOISELESS 4.65e2
G12 MID N046 N043 MID 22.5
C28 N043 N042 6e-8
R10 MID N044 R_NOISELESS 1e12
R2 5 0 {RNVF}
V11 N029 VD1 0
V4 N013 N014 PULSE(0 0.02 0.5u 10n 200n 0.2u 0.4u)
Rsrc6 N009 MID R_NOISELESS 1
R42 VSENSE N019 R_NOISELESS 1e-3
GVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
R75 N047 N046 R_NOISELESS 2.3e4
R6 N002 N001 10k
XU1 N049 MID N051 MID VCVS_LIM_1_TLV354
R41 N033 N032 R_NOISELESS 1e-3
R3 N012 N008 10k
G_adjust1 MID N001 N011 MID 3.985e-2
G1 MID N041 VSENSE MID 1e-6
C24 MID VCLP 1e-12
VCM_MAX N039 VCC_B +0.1
C23 N005 N006 1.36e-14
R4 VCC_B N053 R_NOISELESS 1e-3
R65 N003 MID R_NOISELESS 1
R20 N024 MID R_NOISELESS 1
C1 N009 0 100p
V3 N014 0 SINE(0 0.05 0.01Meg 100u)
R2 3 0 1E9
E1 3 0 5 0 10
R29 N017 N018 R_NOISELESS 1e-3
XCL_AMP N008 N034 VIMON MID N017 N024 CLAMP_AMP_LO_TLV354
H2 OLN MID V11 -1
Rsrc1 N001 MID R_NOISELESS 1
C5 N007 0 3p
G3 MID VEE_CLP N027 MID 1e-3
S1 N043 N042 SW_OL MID OL_SW
R9 N007 N001 10k
V_ISCn N034 MID -165
V2 3v3 0 3.3
R57 N002 N001 R_NOISELESS 1e8
G2 MID VCC_CLP N014 MID 1e-3
R22 MID N008 R_NOISELESS 1e9
V_ORn N028 VCLP -0.65
G8 MID CLAW_CLAMP N041 MID 1e-3
E4 N050 MID CL_CLAMP MID 1
R13 N026 VEE_B R_NOISELESS 1e3
R35 VOS- IN- R_NOISELESS 1e-3
R2 FB- VOS- R_NOISELESS 1e-3
Rx1 N052 N051 R_NOISELESS 6.67e4
R44 GAIN_1 MID R_NOISELESS 1e6
R1 3 0 1E9
GSW+ 1 2 Value = {IF((V(3,1)>1e-3 | V(4,1)>1e-3),1,0)}
S4 IN- VEE VEE IN- ESD_SW
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
G15 MID VSENSE CLAMP MID 1e-3
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
S5 IN+ VEE VEE IN+ ESD_SW
R40 N020 N021 R_NOISELESS 1e-3
R71 N046 MID R_NOISELESS 1
I_OS FB- MID 2e-12
C2 N012 0 3p
Xe_n N037 N011 VNSE_TLV354
XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N015 N022 CLAMP_AMP_LO_TLV354
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
R23 VEE_CLP MID R_NOISELESS 1e9
XV_OS VOS N037 VOS_DRIFT_TLV354
R1 N036 CMR R_NOISELESS 1e-3
R5 N055 VEE_B R_NOISELESS 1e-3
R1 5 0 {RNVF}
R5 N003 N001 10k
R78 N049 N048 R_NOISELESS 10e3
XCLAWn MID VIMON VEE_B N026 VCCS_LIM_CLAWn_TLV354
C_CMn VOS- MID 2e-12
R89 VEE_B 0 R_NOISELESS 1
C20 CLAMP MID 6.5e-10
R33 VIMON N044 R_NOISELESS 100
C_CMp MID N011 2e-12
G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}
R1 N009 N010 10k
R69 N043 N042 R_NOISELESS 10e3
G10 MID N003 VEE_B MID 6.64e-1
G14 MID N048 N047 MID 1
C12 SW_OL MID 1e-12
E5 N045 MID OUT MID 1
G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3
R25 MID N015 R_NOISELESS 1
C3 N055 0 1e-15
R48 MID N041 R_NOISELESS 1e6
I_B PSR MID 3e-12
G7 MID N009 N004 MID 1
R46 MID CL_CLAMP R_NOISELESS 1e3
G6 MID N010 N005 MID 1
V4 N052 OUT 0
Rsrc2 N007 MID R_NOISELESS 1
I2 0 8 10E-3
R6 3 4 1E9
C17 MID N021 1e-15
Rsrc4 N010 MID R_NOISELESS 1
GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
V_GRn N035 MID -120
G5 MID N007 N002 MID 1
R7 N004 N003 1k
E3 1 2 3 4 1
R64 N004 N003 R_NOISELESS 1e8
C10 N023 MID 1e-15
C6 out 0 1p IC=0V
R53 VOS- MID R_NOISELESS 1T
V_ORp N031 VCLP 0.65
R58 CLAMP MID R_NOISELESS 1e6
V_GRp N012 MID 110
R12 VCC_B N013 R_NOISELESS 1e3
C4 VCM_CLAMP MID 1e-15
R56 N002 MID R_NOISELESS 2.063e5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 200u 0 10n
.model SN74LVC1G3157 SW(Ron=6 Roff=1G Vt=1.65 Vh=0.66)
.subckt TLV354 IN+ IN- VCC VEE OUT
.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=100e-3 Voff=0)
.model R_NOISELESS RES(T_ABS=-273.15)
.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)
.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)
.ends TLV354
.SUBCKT VOS_DRIFT_TLV354 VOS+ VOS-
.PARAM DC = 645e-6
.PARAM POL = 1
.PARAM DRIFT = 4.5E-06
.ENDS
.subckt CLAMP_AMP_HI_TLV354 VC+ VC- VIN COM VO+ VO-
.param G=10
.ends CLAMP_AMP_HI_TLV354
.subckt OL_SENSE_TLV354 1 2 3 4
.ends OL_SENSE_TLV354
.subckt FEMT_TLV354 1 2
.param NVRF=50
.param RNVF={1.184*PWR(NVRF,2)}
.ends FEMT_TLV354
.subckt VCCS_EXT_LIM_TLV354 VIN+ VIN- IOUT- IOUT+ VP+ VP-
.param Gain = 1
.ends VCCS_EXT_LIM_TLV354
.subckt VCCS_LIM_1_TLV354 VC+ VC- IOUT+ IOUT-
.param Gain = 1e-4
.param Ipos = .5
.param Ineg = -.5
.ends VCCS_LIM_1_TLV354
.subckt VCCS_LIM_2_TLV354 VC+ VC- IOUT+ IOUT-
.param Gain = 4.71e-3
.param Ipos = 99.6e-3
.param Ineg = -99.6e-3
.ends VCCS_LIM_2_TLV354
.subckt VCCS_LIM_3_TLV354 VC+ VC- IOUT+ IOUT-
.param Gain = 1
.param Ipos = 220e-3
.param Ineg = -240e-3
.ends VCCS_LIM_3_TLV354
.subckt VCCS_LIM_4_TLV354 VC+ VC- IOUT+ IOUT-
.param Gain = 1
.param Ipos = 230e-3
.param Ineg = -250e-3
.ends VCCS_LIM_4_TLV354
.subckt VCCS_LIM_CLAWn_TLV354 VC+ VC- IOUT+ IOUT-
.ends VCCS_LIM_CLAWn_TLV354
.subckt VCCS_LIM_IQ_TLV354 VC+ VC- IOUT+ IOUT-
.param Gain = 1e-3
.ends VCCS_LIM_IQ_TLV354
.subckt VCVS_LIM_1_TLV354 VC+ VC- VOUT+ VOUT-
.param Gain = 3.03e2
.param Vpos = 20.5e3
.param Vneg = -22.5e3
.ends VCVS_LIM_1_TLV354
.subckt VNSE_TLV354 1 2
.param FLW=10
.param NLF=605
.param NVR=7.3
.param GLF={PWR(FLW,0.25)*NLF/1164}
.param RNV={1.184*PWR(NVR,2)}
.model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
.ends VNSE_TLV354
.subckt CLAMP_AMP_LO_TLV354 VC+ VC- VIN COM VO+ VO-
.param G=1
.ends CLAMP_AMP_LO_TLV354
.subckt VCCS_LIM_GR_TLV354 VC+ VC- IOUT+ IOUT-
.param Gain = 1
.param Ipos = 0.25
.param Ineg = -0.25
.ends VCCS_LIM_GR_TLV354
.subckt VCCS_LIM_CLAWp_TLV354 VC+ VC- IOUT+ IOUT-
.ends VCCS_LIM_CLAWp_TLV354
.model SN74LVC1G3157 SW(Ron=6 Roff=1G Vt=1.65 Vh=0.66)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2976 10920
WIRE -256 -368 -352 -368
WIRE -144 -368 -176 -368
WIRE -16 -368 -16 -400
WIRE -16 -368 -144 -368
WIRE 224 -368 -16 -368
WIRE -144 -352 -144 -368
WIRE 464 -352 288 -352
WIRE 624 -352 464 -352
WIRE 800 -352 624 -352
WIRE 96 -336 80 -336
WIRE 192 -336 176 -336
WIRE 224 -336 192 -336
WIRE 624 -320 624 -352
WIRE -144 -272 -144 -288
WIRE 192 -224 192 -336
WIRE 224 -224 192 -224
WIRE 336 -224 288 -224
WIRE 464 -224 464 -352
WIRE 464 -224 416 -224
WIRE -352 -176 -352 -368
WIRE -192 -176 -352 -176
WIRE 0 -176 0 -224
WIRE 0 -176 -128 -176
WIRE -352 -48 -352 -176
WIRE -192 -48 -352 -48
WIRE -80 -48 -112 -48
WIRE 0 -48 0 -112
WIRE 0 -48 -80 -48
WIRE 80 -48 80 -336
WIRE 80 -48 0 -48
WIRE -80 -32 -80 -48
WIRE -80 48 -80 32
WIRE -352 432 -352 -48
WIRE 400 432 -352 432
WIRE 512 432 480 432
WIRE 656 432 512 432
WIRE 512 480 512 432
WIRE -912 512 -912 464
WIRE 80 512 -112 512
WIRE 240 512 160 512
WIRE 512 576 512 544
WIRE -912 608 -912 592
WIRE -352 608 -352 432
WIRE -224 608 -352 608
WIRE -112 608 -112 512
WIRE -112 608 -144 608
WIRE 16 608 -112 608
WIRE 112 608 80 608
WIRE 240 608 240 512
WIRE 240 608 192 608
WIRE 416 608 240 608
WIRE 240 656 240 608
WIRE -352 672 -352 608
WIRE 240 736 240 720
WIRE 496 736 496 704
WIRE 416 752 416 608
WIRE 464 752 416 752
WIRE 672 768 528 768
WIRE 464 784 416 784
WIRE -352 816 -352 752
WIRE 496 832 496 800
WIRE -112 864 -112 608
WIRE 48 864 -112 864
WIRE 240 864 128 864
WIRE 416 864 416 784
WIRE 416 864 240 864
WIRE 240 880 240 864
WIRE -352 960 -352 896
WIRE 240 976 240 944
WIRE -352 1104 -352 1040
SYMBOL res -160 -384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10k
SYMBOL res -96 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL res -128 592 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res 192 -352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL voltage -912 496 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL schottky -192 -160 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RB886CM
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage -352 800 R0
WINDOW 3 -447 99 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 0.02 0.5u 10n 200n 0.2u 0.4u)
SYMATTR InstName V4
SYMBOL cap 224 656 R0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL cap -96 -32 R0
SYMATTR InstName C3
SYMATTR Value 3p
SYMBOL OpAmps\\UniversalOpAmp2 496 768 R0
SYMATTR InstName U2
SYMATTR Value2 Avol=10Meg GBW=10G Slew=10G
SYMBOL res 208 592 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap -160 -352 R0
SYMATTR InstName C4
SYMATTR Value 1n
SYMBOL cap 496 480 R0
SYMATTR InstName C5
SYMATTR Value 3p
SYMBOL voltage -352 656 R0
WINDOW 3 -447 99 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0.6 0.7 10u 10n 200n 0.2u 1u)
SYMATTR InstName V1
SYMBOL voltage -352 944 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 0.05 0.01Meg 100u)
SYMBOL res 16 -208 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R8
SYMATTR Value 100
SYMBOL res 144 848 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL schottky 16 624 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 176 496 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL res 496 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 10k
SYMBOL OpAmps\\UniversalOpAmp2 256 -352 R0
SYMATTR InstName U1
SYMATTR Value2 Avol=10Meg GBW=10G Slew=10G
SYMBOL res -32 -496 R0
SYMATTR InstName R10
SYMATTR Value 1Meg
SYMBOL cap 608 -320 R0
WINDOW 39 24 36 Left 2
SYMATTR InstName C6
SYMATTR Value 1p
SYMATTR SpiceLine IC=0V
SYMBOL cap 224 880 R0
SYMATTR InstName C2
SYMATTR Value 3p
FLAG 240 736 0
FLAG -352 1104 0
FLAG 240 976 0
FLAG 496 832 0
FLAG 496 704 3v3
FLAG -912 608 0
FLAG -912 464 3v3
FLAG 512 576 0
FLAG -80 48 0
FLAG 256 -384 3v3
FLAG 256 -320 0
FLAG 800 -352 out
FLAG -144 -272 0
FLAG -16 -480 3v3
FLAG 624 -256 0
TEXT -776 1128 Left 2 !.tran 0 200u 0 10n
TEXT -32 1272 Left 2 !.model SN74LVC1G3157 SW(Ron=6 Roff=1G Vt=1.65 Vh=0.66)
TEXT 616 664 Left 2 ;Standard Leaky Comparator
TEXT 1552 96 Left 2 !*$\n* TLV354\n*************************************************************************************************\n* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.                                            \n*************************************************************************************************\n** This model is designed as an aid for customers of Texas Instruments.\n** TI and its licensor's and suppliers make no warranties, either expressed\n** or implied, with respect to this model, including the warranties of \n** merchantability or fitness for a particular purpose.  The model is\n** provided solely on an "as is" basis.  The entire risk as to its quality\n** and performance is with the customer\n*************************************************************************************************\n*\n* This model is subject to change without notice. Texas Instruments\n* Incorporated is not responsible for updating this model.\n*\n*************************************************************************************************\n*\n** Released by: Online Design Tools, Texas Instruments Inc.\n* Part: TLV354\n* Date: 13FEB2019\n* Model Type: Generic (suitable for all analysis types)\n* EVM Order Number: N/A \n* EVM Users Guide:  N/A \n* Datasheet: SBOS756 -OCTOBER 2016\n* Created with Green-Williams-Lis Op Amp Macro-model Architecture\n*\n* Model Version: Final 1.2\n*\n*****************************************************************************\n*\n* Updates:\n*\n* Final 1.2\n* Updated with unique subckt name,Current Noise, Vos drift and edits in claw block\n*\n*\n* Final 1.1\n* Release to Web.\n*\n****************************************************************************\n* Model Usage Notes:\n* 1. The following parameters are modeled: \n*                               OPEN-LOOP GAIN AND PHASE VS. FREQUENCY  WITH RL, CL EFFECTS (Aol)\n*                               UNITY GAIN BANDWIDTH (GBW)\n*                               INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR)\n*                               POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR)\n*                               DIFFERENTIAL INPUT IMPEDANCE (Zid)\n*                               COMMON-MODE INPUT IMPEDANCE (Zic)\n*                               OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo)\n*                               OUTPUT CURRENT THROUGH THE SUPPLY (Iout)\n*                               INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en)\n*                               INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in)\n*                               OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo)\n*                               SHORT-CIRCUIT OUTPUT CURRENT (Isc)\n*                               QUIESCENT CURRENT (Iq)\n*                               SETTLING TIME VS. CAPACITIVE LOAD (ts)\n*                               SLEW RATE (SR)\n*                               SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD\n*                               LARGE SIGNAL RESPONSE\n*                               OVERLOAD RECOVERY TIME (tor)\n*                               INPUT BIAS CURRENT (Ib)\n*                               INPUT OFFSET CURRENT (Ios)\n*                               INPUT OFFSET VOLTAGE (Vos)\n*                               INPUT OFFSET VOLTAGE VS. TEMPERATURE (VOS DRIFT)\n*                               INPUT COMMON-MODE VOLTAGE RANGE (Vcm)\n*                               INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm)\n*                               INPUT/OUTPUT ESD CELLS (ESDin, ESDout)\n******************************************************\n.subckt TLV354 IN+ IN- VCC VEE OUT\n******************************************************\n* MODEL DEFINITIONS:\n.model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=100e-3 Voff=0)\n.model R_NOISELESS RES(T_ABS=-273.15)\n.model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=250e-3 Voff=0)\n.model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=1e-3 Voff=0)\n******************************************************\nXV_OS VOS N037 VOS_DRIFT_TLV354\nR1 N036 CMR R_NOISELESS 1e-3 \nR2 FB- VOS- R_NOISELESS 1e-3 \nR3 N054 0 R_NOISELESS 1e12 \nC1 N054 0 1\nR4 VCC_B N053 R_NOISELESS 1e-3 \nC2 N053 0 1e-15\nC3 N055 0 1e-15\nR5 N055 VEE_B R_NOISELESS 1e-3 \nG_PSR N036 PSR N010 N009 1e-3\nR6 MID N039 R_NOISELESS 1e12 \nVCM_MIN N040 VEE_B -0.1\nR7 N040 MID R_NOISELESS 1e12 \nVCM_MAX N039 VCC_B +0.1\nXVCM_CLAMP PSR MID N038 MID N039 N040 VCCS_EXT_LIM_TLV354\nR8 N038 MID R_NOISELESS 1 \nC4 VCM_CLAMP MID 1e-15\nR9 N038 VCM_CLAMP R_NOISELESS 1e-3 \nV4 N052 OUT 0\nR10 MID N044 R_NOISELESS 1e12 \nR11 MID N045 R_NOISELESS 1e12 \nXIQp VIMON MID VCC MID VCCS_LIM_IQ_TLV354\nXIQn MID VIMON VEE MID VCCS_LIM_IQ_TLV354\nR12 VCC_B N013 R_NOISELESS 1e3 \nR13 N026 VEE_B R_NOISELESS 1e3 \nXCLAWp VIMON MID N013 VCC_B VCCS_LIM_CLAWp_TLV354\nXCLAWn MID VIMON VEE_B N026 VCCS_LIM_CLAWn_TLV354\nR14 VEE_CLP MID R_NOISELESS 1e3 \nR15 MID VCC_CLP R_NOISELESS 1e3 \nR16 N014 N013 R_NOISELESS 1e-3 \nR17 N027 N026 R_NOISELESS 1e-3 \nC5 MID N014 1e-15\nC6 N027 MID 1e-15\nR18 VOUT_S N045 R_NOISELESS 100 \nC7 VOUT_S MID 1e-12\nG2 MID VCC_CLP N014 MID 1e-3\nG3 MID VEE_CLP N027 MID 1e-3\nXCL_AMP N008 N034 VIMON MID N017 N024 CLAMP_AMP_LO_TLV354\nV_ISCp N008 MID 150\nV_ISCn N034 MID -165\nXOL_SENSE_TLV354 MID N057 OLN OLP OL_SENSE_TLV354\nR19 N034 MID R_NOISELESS 1e9 \nR20 N024 MID R_NOISELESS 1 \nC8 N025 MID 1e-15\nR21 MID N017 R_NOISELESS 1 \nR22 MID N008 R_NOISELESS 1e9 \nC9 MID N018 1e-15\nXCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N015 N022 CLAMP_AMP_LO_TLV354\nR23 VEE_CLP MID R_NOISELESS 1e9 \nR24 N022 MID R_NOISELESS 1 \nC10 N023 MID 1e-15\nR25 MID N015 R_NOISELESS 1 \nR26 MID VCC_CLP R_NOISELESS 1e9 \nC11 MID N016 1e-15\nXCL_SRC N018 N025 CL_CLAMP MID VCCS_LIM_4_TLV354\nXCLAW_SRC N016 N023 CLAW_CLAMP MID VCCS_LIM_3_TLV354\nR27 N015 N016 R_NOISELESS 1e-3 \nR28 N023 N022 R_NOISELESS 1e-3 \nR29 N017 N018 R_NOISELESS 1e-3 \nR30 N025 N024 R_NOISELESS 1e-3 \nR31 N057 MID R_NOISELESS 1 \nR32 N057 SW_OL R_NOISELESS 100 \nC12 SW_OL MID 1e-12\nR33 VIMON N044 R_NOISELESS 100 \nC13 VIMON MID 1e-12\nC_DIFF N011 VOS- 2e-12\nC_CMn VOS- MID 2e-12\nC_CMp MID N011 2e-12\nI_Q VCC VEE 5.2e-3\nI_B PSR MID 3e-12\nI_OS FB- MID 2e-12\nR36 N032 MID R_NOISELESS 1 \nR37 N035 MID R_NOISELESS 1e9 \nR38 MID N020 R_NOISELESS 1 \nR39 MID N012 R_NOISELESS 1e9 \nXGR_AMP N012 N035 N019 MID N020 N032 CLAMP_AMP_HI_TLV354\nXGR_SRC N021 N033 CLAMP MID VCCS_LIM_GR_TLV354\nC17 MID N021 1e-15\nC18 N033 MID 1e-15\nV_GRn N035 MID -120\nV_GRp N012 MID 110\nR40 N020 N021 R_NOISELESS 1e-3 \nR41 N033 N032 R_NOISELESS 1e-3 \nR42 VSENSE N019 R_NOISELESS 1e-3 \nC19 MID N019 1e-15\nR43 MID VSENSE R_NOISELESS 1e3 \nG_CMR VOS CMR N007 MID 1e-3\nG8 MID CLAW_CLAMP N041 MID 1e-3\nR45 MID CLAW_CLAMP R_NOISELESS 1e3 \nG9 MID CL_CLAMP CLAW_CLAMP MID 1e-3\nR46 MID CL_CLAMP R_NOISELESS 1e3 \nR47 N050 VCLP R_NOISELESS 100 \nC24 MID VCLP 1e-12\nE4 N050 MID CL_CLAMP MID 1\nE5 N045 MID OUT MID 1\nH1 N044 MID V4 1e3\nS1 N043 N042 SW_OL MID OL_SW\nR52 MID N011 R_NOISELESS 1T\nR53 VOS- MID R_NOISELESS 1T\nR_CMR CMR VOS R_NOISELESS 1e3 \nR59 N053 N054 R_NOISELESS 1e6 \nR60 N054 N055 R_NOISELESS 1e6 \nR_PSR PSR N036 R_NOISELESS 1e3 \nG15 MID VSENSE CLAMP MID 1e-3\nE6 VD2 MID N031 MID 1\nV_ORp N031 VCLP 0.65\nV_ORn N028 VCLP -0.65\nE7 VD1 MID N028 MID 1\nV11 N029 VD1 0\nV12 N030 VD2 0\nH2 OLN MID V11 -1\nH3 OLP MID V12 1\nS2 VCC IN- IN- VCC ESD_SW\nS3 VCC IN+ IN+ VCC ESD_SW\nS4 IN- VEE VEE IN- ESD_SW\nS5 IN+ VEE VEE IN+ ESD_SW\nS6 VCC OUT OUT VCC ESD_SW\nS7 OUT VEE VEE OUT ESD_SW\nE1 MID 0 N054 0 1\nG16 0 VCC_B VCC 0 1\nG17 0 VEE_B VEE 0 1\nR88 VCC_B 0 R_NOISELESS 1 \nR89 VEE_B 0 R_NOISELESS 1 \nS8 N030 CLAMP CLAMP N030 OR_SW\nS9 CLAMP N029 N029 CLAMP OR_SW\nXVCCS_LIM_1_TLV354 VCM_CLAMP FB- MID GAIN_1 VCCS_LIM_1_TLV354\nXVCCS_LIM_2_TLV354 GAIN_1 MID MID CLAMP VCCS_LIM_2_TLV354\nR44 GAIN_1 MID R_NOISELESS 1e6 \nR58 CLAMP MID R_NOISELESS 1e6 \nC20 CLAMP MID 6.5e-10\nR34 N011 IN+ R_NOISELESS 1e-3 \nR35 VOS- IN- R_NOISELESS 1e-3 \nR48 MID N041 R_NOISELESS 1e6 \nG1 MID N041 VSENSE MID 1e-6\nC14 N041 MID 7.23e-16\nXe_n N037 N011 VNSE_TLV354\nC22 N002 N001 4.547e-15\nG_adjust1 MID N001 N011 MID 3.985e-2\nRsrc1 N001 MID R_NOISELESS 1 \nR56 N002 MID R_NOISELESS 2.063e5 \nR57 N002 N001 R_NOISELESS 1e8 \nRsrc2 N007 MID R_NOISELESS 1 \nG5 MID N007 N002 MID 1\nC23 N005 N006 1.36e-14\nG_adjust2 MID N006 VCC_B MID 8.834e-1\nRsrc3 N006 MID R_NOISELESS 1 \nR61 N005 MID R_NOISELESS 4.256e4 \nR62 N005 N006 R_NOISELESS 1e8 \nG6 MID N010 N005 MID 1\nRsrc4 N010 MID R_NOISELESS 1 \nC25 N004 N003 6.366e-14\nR63 N004 MID R_NOISELESS 2.501e4 \nR64 N004 N003 R_NOISELESS 1e8 \nG7 MID N009 N004 MID 1\nRsrc6 N009 MID R_NOISELESS 1 \nG10 MID N003 VEE_B MID 6.64e-1\nR65 N003 MID R_NOISELESS 1 \nRx1 N052 N051 R_NOISELESS 6.67e4\nRdummy1 N052 MID R_NOISELESS 6.67e3\nG_Zo MID N042 CL_CLAMP N052 89\nRdc N042 MID R_NOISELESS 1\nR69 N043 N042 R_NOISELESS 10e3\nR70 MID N043 R_NOISELESS 4.65e2\nG12 MID N046 N043 MID 22.5\nR71 N046 MID R_NOISELESS 1\nC28 N043 N042 6e-8\nR75 N047 N046 R_NOISELESS 2.3e4\nR76 N056 N047 R_NOISELESS 10e3\nC29 MID N056 4.823e-14\nG14 MID N048 N047 MID 1\nR77 N048 MID R_NOISELESS 1\nR78 N049 N048 R_NOISELESS 10e3\nR79 MID N049 R_NOISELESS 3.311e1\nC30 N049 N048 4.823e-14\nXU1 N049 MID N051 MID VCVS_LIM_1_TLV354\nXi_np N037 MID FEMT_TLV354\nXi_nn VOS- MID FEMT_TLV354\n.ends TLV354\n*\n.SUBCKT VOS_DRIFT_TLV354 VOS+ VOS-\n.PARAM DC = 645e-6\n.PARAM POL = 1\n.PARAM DRIFT = 4.5E-06\nE1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}\n.ENDS\n*\n.subckt CLAMP_AMP_HI_TLV354 VC+ VC- VIN COM VO+ VO-\n.param G=10\nGVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}\nGVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}\n.ends CLAMP_AMP_HI_TLV354\n*\n.subckt OL_SENSE_TLV354 1   2  3  4\nGSW+ 1 2 Value = {IF((V(3,1)>1e-3 | V(4,1)>1e-3),1,0)}\n.ends OL_SENSE_TLV354\n*\n.subckt FEMT_TLV354 1 2\n.param NVRF=50\n.param RNVF={1.184*PWR(NVRF,2)}\nE1 3 0 5 0 10\nR1 5 0 {RNVF}\nR2 5 0 {RNVF}\nG1 1 2 3 0 1e-6\n.ends FEMT_TLV354\n*\n.subckt VCCS_EXT_LIM_TLV354 VIN+ VIN- IOUT- IOUT+ VP+ VP-\n.param Gain = 1\nG1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}\n.ends VCCS_EXT_LIM_TLV354\n*\n.subckt VCCS_LIM_1_TLV354 VC+ VC- IOUT+ IOUT-\n.param Gain = 1e-4\n.param Ipos = .5\n.param Ineg = -.5\nG1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}\n.ends VCCS_LIM_1_TLV354\n*\n.subckt VCCS_LIM_2_TLV354 VC+ VC- IOUT+ IOUT-\n.param Gain = 4.71e-3\n.param Ipos = 99.6e-3\n.param Ineg = -99.6e-3\nG1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}\n.ends VCCS_LIM_2_TLV354\n*\n.subckt VCCS_LIM_3_TLV354 VC+ VC- IOUT+ IOUT-\n.param Gain = 1\n.param Ipos = 220e-3\n.param Ineg = -240e-3\nG1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}\n.ends VCCS_LIM_3_TLV354\n*\n.subckt VCCS_LIM_4_TLV354 VC+ VC- IOUT+ IOUT-\n.param Gain = 1\n.param Ipos = 230e-3\n.param Ineg = -250e-3\nG1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}\n.ends VCCS_LIM_4_TLV354\n*\n.subckt VCCS_LIM_CLAWn_TLV354 VC+ VC- IOUT+ IOUT-\nG1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =\n+(0, 1.0064e-4)\n+(10, 1.28e-4)\n+(20, 2.16e-4)\n+(50, 5.31e-4)\n+(90.6, 9.91e-4)\n+(120, 1.39e-3)\n+(140, 1.7e-3)\n+(163.7, 2.16e-3)\n.ends VCCS_LIM_CLAWn_TLV354\n*\n.subckt VCCS_LIM_IQ_TLV354 VC+ VC- IOUT+ IOUT-\n.param Gain = 1e-3\nG1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )}\n.ends VCCS_LIM_IQ_TLV354\n*\n.subckt VCVS_LIM_1_TLV354 VC+ VC- VOUT+ VOUT-\n.param Gain = 3.03e2\n.param Vpos = 20.5e3\n.param Vneg = -22.5e3\nE1 VOUT+ VOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Vneg,Vpos)}\n.ends VCVS_LIM_1_TLV354\n*\n.subckt VNSE_TLV354 1 2\n.param FLW=10\n.param NLF=605\n.param NVR=7.3\n.param GLF={PWR(FLW,0.25)*NLF/1164}\n.param RNV={1.184*PWR(NVR,2)}\n.model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16\nI1 0 7 10E-3\nI2 0 8 10E-3\nD1 7 0 DVN\nD2 8 0 DVN\nE1 3 6 7 8 {GLF}\nR1 3 0 1E9\nR2 3 0 1E9\nR3 3 6 1E9\nE2 6 4 5 0 10\nR4 5 0 {RNV}\nR5 5 0 {RNV}\nR6 3 4 1E9\nR7 4 0 1E9\nE3 1 2 3 4 1\n.ends VNSE_TLV354\n*\n.subckt CLAMP_AMP_LO_TLV354 VC+ VC- VIN COM VO+ VO-\n.param G=1\nGVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}\nGVo- COM Vo- Value = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}\n.ends CLAMP_AMP_LO_TLV354\n*\n.subckt VCCS_LIM_GR_TLV354 VC+ VC- IOUT+ IOUT-\n.param Gain = 1\n.param Ipos = 0.25\n.param Ineg = -0.25\nG1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)}\n.ends VCCS_LIM_GR_TLV354\n*\n.subckt VCCS_LIM_CLAWp_TLV354 VC+ VC- IOUT+ IOUT-\nG1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =\n+(0, 1.0064e-4)\n+(9.82, 1.1e-4)\n+(20, 2.31e-4)\n+(40.51, 4.34e-4)\n+(70, 7.51e-4)\n+(100, 1.17e-3)\n+(120, 1.52e-3)\n+(150, 2.11e-3)\n.ends VCCS_LIM_CLAWp_TLV354\n*
TEXT 1544 40 Left 2 !.model SN74LVC1G3157 SW(Ron=6 Roff=1G Vt=1.65 Vh=0.66)