Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\326e6e66796c_4-NAND-111.asc
* Generated by LTspice 26.0.1 for Windows.
M7 OUT N003 0 0 NMOS
M6 N003 SEL1 V+ V+ PMOS
M14 N005 SEL0 0 0 NMOS
M13 N005 SEL0 V+ V+ PMOS
M12 OUT N001 0 0 NMOS
M11 OUT N005 0 0 NMOS
M8 N003 SEL1 0 0 NMOS
M9 OUT IN N006 N006 PMOS
M5 N002 N001 V+ V+ PMOS
M2 N001 SEL2 V+ V+ PMOS
M10 OUT IN 0 0 NMOS
M4 N001 SEL2 0 0 NMOS
M3 N004 N003 N002 N002 PMOS
M1 N006 N005 N004 N004 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1660 728
WIRE 464 -608 192 -608
WIRE 608 -608 464 -608
WIRE 464 -576 464 -608
WIRE 464 -576 384 -576
WIRE 336 -560 320 -560
WIRE 608 -528 608 -608
WIRE 560 -512 544 -512
WIRE 320 -480 320 -560
WIRE 320 -480 192 -480
WIRE 544 -480 544 -512
WIRE 544 -480 384 -480
WIRE 320 -400 320 -480
WIRE 336 -400 320 -400
WIRE 480 -384 384 -384
WIRE 608 -368 608 -432
WIRE 752 -368 608 -368
WIRE 464 -352 464 -576
WIRE 464 -352 384 -352
WIRE 336 -336 320 -336
WIRE 752 -304 752 -368
WIRE 704 -288 688 -288
WIRE 320 -256 320 -336
WIRE 320 -256 192 -256
WIRE 688 -256 688 -288
WIRE 688 -256 384 -256
WIRE 320 -176 320 -256
WIRE 336 -176 320 -176
WIRE 480 -160 480 -384
WIRE 480 -160 384 -160
WIRE 752 -144 752 -208
WIRE 896 -144 752 -144
WIRE 464 -128 464 -352
WIRE 464 -128 384 -128
WIRE 336 -112 320 -112
WIRE 896 -80 896 -144
WIRE 848 -64 832 -64
WIRE 320 -32 320 -112
WIRE 320 -32 192 -32
WIRE 832 -32 832 -64
WIRE 832 -32 384 -32
WIRE 320 48 320 -32
WIRE 336 48 320 48
WIRE 896 48 896 16
WIRE 1040 48 896 48
WIRE 480 64 480 -160
WIRE 480 64 384 64
WIRE 1040 80 1040 48
WIRE 992 96 976 96
WIRE 976 128 976 96
WIRE 976 128 192 128
WIRE 752 192 608 192
WIRE 896 192 752 192
WIRE 1040 192 1040 176
WIRE 1040 192 896 192
WIRE 1184 192 1040 192
WIRE 608 208 608 192
WIRE 752 208 752 192
WIRE 896 208 896 192
WIRE 1040 208 1040 192
WIRE 544 288 544 -480
WIRE 560 288 544 288
WIRE 688 288 688 -256
WIRE 704 288 688 288
WIRE 832 288 832 -32
WIRE 848 288 832 288
WIRE 976 288 976 128
WIRE 992 288 976 288
WIRE 480 320 480 64
WIRE 608 320 608 304
WIRE 608 320 480 320
WIRE 752 320 752 304
WIRE 752 320 608 320
WIRE 896 320 896 304
WIRE 896 320 752 320
WIRE 1040 320 1040 304
WIRE 1040 320 896 320
WIRE 896 352 896 320
IOPIN 192 128 In
IOPIN 1184 192 Out
IOPIN 192 -32 In
IOPIN 192 -256 In
IOPIN 192 -480 In
IOPIN 192 -608 In
SYMBOL nmos 336 -32 R0
SYMATTR InstName M14
SYMBOL pmos 704 -208 M180
SYMATTR InstName M3
SYMBOL pmos 336 -480 M180
SYMATTR InstName M2
SYMBOL nmos 704 208 R0
SYMATTR InstName M7
SYMBOL pmos 848 16 M180
SYMATTR InstName M1
SYMBOL pmos 336 -256 M180
SYMATTR InstName M6
SYMBOL nmos 560 208 R0
SYMATTR InstName M12
SYMBOL pmos 560 -432 M180
SYMATTR InstName M5
SYMBOL nmos 848 208 R0
SYMATTR InstName M11
SYMBOL pmos 992 176 M180
SYMATTR InstName M9
SYMBOL nmos 992 208 R0
SYMATTR InstName M10
SYMBOL nmos 336 -480 R0
SYMATTR InstName M4
SYMBOL nmos 336 -256 R0
SYMATTR InstName M8
SYMBOL pmos 336 -32 M180
SYMATTR InstName M13
FLAG 896 352 0
FLAG 192 128 IN
FLAG 1184 192 OUT
FLAG 192 -32 SEL0
FLAG 192 -256 SEL1
FLAG 192 -480 SEL2
FLAG 192 -608 V+
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5075.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N004 N005 15.8K
R2 OUT N004 115K
L1 N001 0 4.7
D1 OUT N001 MBRS140
C2 OUT 0 12
Rload OUT 0 200
C3 0 N006 1
C4 0 N005 1
V1 IN 0 5
R3 N003 N002 50K
C1 N002 0 2n
C5 N003 0 15p
XU1 IN N001 N003 0 N006 IN 0 N004 N005 NC_01 NC_02 IN ADP5075 CL=880m CS=153.85m Ron=330m IQ=1.8m ;pnba PVin)SW)Comp)GND)Vreg)EN)Sync/Freq)FB)Vref)Slew)SS)AVin
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 4.5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5075.asy)
.lib ADP5075.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1432 816
WIRE 96 -48 -48 -48
WIRE 416 -48 96 -48
WIRE -48 -32 -48 -48
WIRE 96 16 96 -48
WIRE 112 16 96 16
WIRE 416 16 416 -48
WIRE 416 16 400 16
WIRE -48 64 -48 48
WIRE 96 128 96 16
WIRE 112 128 96 128
WIRE 448 128 400 128
WIRE 544 128 448 128
WIRE 656 128 608 128
WIRE 720 128 656 128
WIRE 816 128 720 128
WIRE 448 144 448 128
WIRE 720 144 720 128
WIRE 816 144 816 128
WIRE -80 240 -128 240
WIRE 48 240 0 240
WIRE 112 240 48 240
WIRE 448 240 448 224
WIRE 448 240 400 240
WIRE 720 240 720 208
WIRE 816 240 816 224
WIRE -128 256 -128 240
WIRE 48 256 48 240
WIRE 448 256 448 240
WIRE -128 336 -128 320
WIRE 48 336 48 320
WIRE 448 352 400 352
WIRE 528 352 448 352
WIRE 656 352 656 128
WIRE 656 352 608 352
WIRE 448 368 448 352
WIRE 448 464 448 448
WIRE 448 464 400 464
WIRE 528 464 448 464
WIRE 608 464 592 464
WIRE 112 576 96 576
WIRE 432 576 400 576
WIRE 512 576 496 576
FLAG 448 256 0
FLAG 720 240 0
FLAG 816 240 0
FLAG 608 464 0
FLAG 96 576 0
FLAG 512 576 0
FLAG -48 64 0
FLAG -48 -48 IN
FLAG 816 128 OUT
FLAG -128 336 0
FLAG 48 336 0
SYMBOL res 432 352 R0
SYMATTR InstName R1
SYMATTR Value 15.8K
SYMBOL res 624 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 115K
SYMBOL ind 432 128 R0
WINDOW 0 42 41 Left 2
WINDOW 3 39 68 Left 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL schottky 608 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 704 144 R0
SYMATTR InstName C2
SYMATTR Value 12
SYMBOL res 800 128 R0
SYMATTR InstName Rload
SYMATTR Value 200
SYMBOL cap 496 560 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 592 448 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL VOLTAGE -48 -48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 16 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 50K
SYMBOL cap -144 256 R0
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL cap 32 256 R0
SYMATTR InstName C5
SYMATTR Value 15p
SYMBOL PowerProducts\\ADP5075 256 288 R0
SYMATTR InstName U1
TEXT 696 616 Left 2 !.tran 4.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1086-2.85.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10) Rser=0.1
Rload OUT 0 10
C1 OUT 0 10
XU1 0 OUT IN LT1086-2.85 ;pnba ADJ)OUT)IN
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1086-2.85.asy)
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1328 896
WIRE 1888 896 1808 896
WIRE 2000 896 1888 896
WIRE 1328 912 1328 896
WIRE 1888 912 1888 896
WIRE 2000 912 2000 896
WIRE 1328 1008 1328 992
WIRE 1888 1008 1888 976
WIRE 2000 1008 2000 992
WIRE 1680 1040 1680 992
FLAG 2000 896 OUT
FLAG 2000 1008 0
FLAG 1328 1008 0
FLAG 1888 1008 0
FLAG 1680 1040 0
FLAG 1328 896 IN
SYMBOL VOLTAGE 1328 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
SYMBOL RES 1984 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 1872 912 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1086-2.85 1680 896 R0
SYMATTR InstName U1
TEXT 1896 1112 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX17761.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX17761.asy)
C2 OUT 0 22 Rser=4.6m
V1 IN 0 24
Rload OUT 0 {5/0.6}
C1 Vcc 0 1
R5 OUT N002 22
R3 Vcc N006 10k
R2 N005 0 18.2k
C4 N002 0 100n
R4 N004 0 105k
C3 N003 0 10n
XU1 0 IN EN/UVLO N002 N005 NC_01 N006 N001 N003 N004 Vcc 0 MAX17761 ;pnba GND)VIN)EN/UVLO)EXTVCC)FB)MODE/ILIM)_RESET)LX)SS)RT/SYNC)VCC)PGND
L1 N001 OUT 33 Rser=10m
R1 OUT N005 95.3k
.tran 4m startup
.lib MAX17761.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1252 680
WIRE -96 -128 -112 -128
WIRE 336 -128 -96 -128
WIRE 336 -112 336 -128
WIRE -112 -48 -112 -128
WIRE 176 -48 144 -48
WIRE 560 -48 496 -48
WIRE 704 -48 640 -48
WIRE 832 -48 704 -48
WIRE 928 -48 832 -48
WIRE 992 -48 928 -48
WIRE 1008 -48 992 -48
WIRE 704 -32 704 -48
WIRE 832 -32 832 -48
WIRE 1008 -32 1008 -48
WIRE 832 48 832 32
WIRE -112 64 -112 32
WIRE 48 64 16 64
WIRE 144 64 112 64
WIRE 176 64 144 64
WIRE 704 64 704 48
WIRE 704 64 496 64
WIRE 1008 64 1008 48
WIRE 704 96 704 64
WIRE 928 112 928 -48
WIRE 48 176 0 176
WIRE 176 176 112 176
WIRE 512 176 496 176
WIRE 704 176 704 160
WIRE 32 288 0 288
WIRE 176 288 112 288
WIRE 928 288 928 192
WIRE 928 288 496 288
WIRE 928 304 928 288
WIRE 560 400 496 400
WIRE 672 400 640 400
WIRE 928 400 928 384
WIRE 336 464 336 448
SYMBOL voltage -112 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 128 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 105k
SYMBOL cap 112 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 816 -32 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=4.6m
SYMBOL res 912 288 R0
SYMATTR InstName R2
SYMATTR Value 18.2k
SYMBOL res 912 96 R0
SYMATTR InstName R1
SYMATTR Value 95.3k
SYMBOL res 688 -48 R0
SYMATTR InstName R5
SYMATTR Value 22
SYMBOL res 656 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL ind 544 -32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=10m
SYMBOL MAX17761 336 160 R0
SYMATTR InstName U1
SYMBOL cap 688 96 R0
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL cap 112 192 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL res 992 -48 R0
SYMATTR InstName Rload
SYMATTR Value {5/0.6}
FLAG -112 64 0
FLAG 0 288 0
FLAG 336 464 0
FLAG 832 48 0
FLAG 1008 64 0
FLAG -96 -128 IN
FLAG 992 -48 OUT
FLAG 0 176 0
FLAG 928 400 0
FLAG 512 176 0
FLAG 16 64 0
FLAG 672 400 Vcc
FLAG 704 176 0
FLAG 144 64 Vcc
FLAG 144 -48 EN/UVLO
TEXT 808 472 Left 2 !.tran 4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2ndOrderBandpass.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N003 0 {L1} Cpar={C1}
G1 0 N002 1 0 {2/R1}
R1 N002 0 {R1/2}
R2 N003 N002 {R1/2}
G2 0 2 N003 0 {10*H}
R3 2 0 .1
V1 1 0 AC 1
R4 2 0 1Meg
.param f0= 1k Q=0.5
.param R1=1k
.param L1=1/(C1*(2*pi*f0)**2)
* f0 and Q set by parameters
* R1 is arbitary
* This version puts 1/2 the R1 resistance in the capacitor
.param C1=Q/(R1*2*pi*f0)
* Vout
* Vin
* The parameter "H" sets the midband gain
.param H=1
.ac dec 101 100 10k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE -384 -128 -448 -128
WIRE -288 -128 -320 -128
WIRE -112 -128 -240 -128
WIRE -64 -128 -112 -128
WIRE 64 -128 16 -128
WIRE 240 -128 64 -128
WIRE 400 -128 288 -128
WIRE 464 -128 400 -128
WIRE 496 -128 464 -128
WIRE 624 -128 560 -128
WIRE -448 -112 -448 -128
WIRE -240 -96 -240 -128
WIRE -288 -80 -288 -128
WIRE -112 -64 -112 -128
WIRE 64 -64 64 -128
WIRE 288 -64 288 -128
WIRE 400 -64 400 -128
WIRE 624 -64 624 -128
WIRE 240 -48 240 -128
WIRE -448 0 -448 -32
WIRE -288 0 -288 -32
WIRE -240 16 -240 -16
WIRE 240 32 240 0
WIRE 288 32 288 16
WIRE 400 32 400 16
WIRE 624 32 624 16
WIRE -112 48 -112 16
WIRE 64 48 64 16
FLAG 64 48 0
FLAG -112 48 0
FLAG -240 16 0
FLAG -288 0 0
FLAG 240 32 0
FLAG 288 32 0
FLAG 400 32 0
FLAG 464 -128 2
FLAG -288 -128 1
FLAG -448 0 0
FLAG 624 32 0
SYMBOL ind 48 -80 R0
WINDOW 0 59 45 Bottom 2
WINDOW 3 61 50 Top 2
WINDOW 123 102 107 Bottom 2
SYMATTR InstName L1
SYMATTR Value {L1}
SYMATTR Value2 Cpar={C1}
SYMBOL g -240 -112 R0
SYMATTR InstName G1
SYMATTR Value {2/R1}
SYMBOL res -128 -80 R0
SYMATTR InstName R1
SYMATTR Value {R1/2}
SYMBOL res 32 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R1/2}
SYMBOL g 288 -80 R0
SYMATTR InstName G2
SYMATTR Value {10*H}
SYMBOL res 384 -80 R0
SYMATTR InstName R3
SYMATTR Value .1
SYMBOL Misc\\jumper 528 -192 R0
SYMATTR InstName J2
SYMBOL Misc\\jumper -352 -192 M0
SYMATTR InstName J1
SYMBOL voltage -448 -128 R0
WINDOW 0 35 41 Left 2
WINDOW 123 33 80 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value2 AC 1
SYMATTR Value ""
SYMBOL res 608 -80 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
TEXT -96 136 Left 2 !.param f0= 1k Q=0.5
TEXT -264 176 Left 2 !.param R1=1k
TEXT -440 296 Left 2 !.param L1=1/(C1*(2*pi*f0)**2)
TEXT -432 136 Left 2 ;f0 and Q set by parameters
TEXT -432 176 Left 2 ;R1 is arbitary
TEXT -328 -200 Left 2 ;This version puts 1/2 the R1 resistance in the capacitor
TEXT -440 256 Left 2 !.param C1=Q/(R1*2*pi*f0)
TEXT 576 -144 Left 2 ;Vout
TEXT -400 -144 Right 2 ;Vin
TEXT -432 216 Left 2 ;The parameter "H" sets the midband gain
TEXT 64 216 Left 2 !.param H=1
TEXT -440 336 Left 2 !.ac dec 101 100 10k
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1574HV.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1574HV.asy)
L1 N001 OUT 100 Rser=0.02 Rpar=5000
C2 OUT 0 100 Rser=0.02
Rload OUT 0 25
XU1 N002 MP_01 MP_02 0 N001 IN IN IN LTC1574 top=1K bot=1T ;pnba FB)))GND)SW)Vin)Ipgm)_SHDN
R1 OUT N002 93.5K
V1 IN 0 9
R2 N002 0 31.5K
.tran 3m startup
.lib LTC1574.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1492 1120
WIRE 480 528 368 528
WIRE 624 528 480 528
WIRE 368 544 368 528
WIRE 624 544 624 528
WIRE 832 560 800 560
WIRE 944 560 912 560
WIRE 1056 560 944 560
WIRE 1152 560 1056 560
WIRE 944 576 944 560
WIRE 1056 576 1056 560
WIRE 1152 576 1152 560
WIRE 480 608 480 528
WIRE 496 608 480 608
WIRE 800 608 800 560
WIRE 800 608 752 608
WIRE 368 640 368 624
WIRE 480 672 480 608
WIRE 496 672 480 672
WIRE 944 672 944 656
WIRE 944 672 752 672
WIRE 1056 672 1056 640
WIRE 1152 672 1152 656
WIRE 944 688 944 672
WIRE 624 768 624 736
WIRE 944 784 944 768
SYMBOL IND 816 576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL RES 928 672 R0
SYMATTR InstName R2
SYMATTR Value 31.5K
SYMBOL res 1136 560 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL PowerProducts\\LTC1574HV 624 624 R0
SYMATTR InstName U1
SYMBOL POLCAP 1040 576 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL VOLTAGE 368 528 R0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL RES 928 560 R0
SYMATTR InstName R1
SYMATTR Value 93.5K
FLAG 1152 560 OUT
FLAG 368 528 IN
FLAG 1056 672 0
FLAG 1152 672 0
FLAG 624 768 0
FLAG 944 784 0
FLAG 368 640 0
TEXT 1000 848 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\c3b05e182cef_Circuito1.asc
* Generated by LTspice 26.0.1 for Windows.
* Out
C3 N003 N002 0.00001
R1 N005 0 10000
V2 N001 0 10
Q1 N002 N005 N006 0 2N2222
C2 N006 0 0.0001
C1 N005 N004 0.00001
V1 N004 0 SINE(0 0.01 1000)
R2 N001 N005 47000
R4 N001 N002 1000
R3 N006 0 470
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 96 -496 -32 -496
WIRE 432 -496 96 -496
WIRE 544 -496 512 -496
WIRE 544 -464 544 -496
WIRE 96 -416 96 -496
WIRE -32 -272 -32 -496
WIRE 96 -240 96 -336
WIRE 208 -240 96 -240
WIRE 432 -240 272 -240
WIRE 96 -144 96 -240
WIRE -160 -96 -288 -96
WIRE -32 -96 -32 -192
WIRE -32 -96 -96 -96
WIRE 32 -96 -32 -96
WIRE -288 -32 -288 -96
WIRE -32 -16 -32 -96
WIRE 96 16 96 -48
WIRE 240 16 96 16
WIRE 96 96 96 16
WIRE 240 96 240 16
WIRE -288 112 -288 48
WIRE -32 208 -32 64
WIRE 96 208 96 176
WIRE 240 208 240 160
SYMBOL cap -96 -112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.00001
SYMBOL cap 224 96 R0
SYMATTR InstName C2
SYMATTR Value 0.0001
SYMBOL res 80 -432 R0
SYMATTR InstName R4
SYMATTR Value 1000
SYMBOL cap 272 -256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 0.00001
SYMBOL res -48 -32 R0
SYMATTR InstName R1
SYMATTR Value 10000
SYMBOL voltage 416 -496 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL Misc\\signal -288 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 0.01 1000)
SYMBOL res 80 80 R0
SYMATTR InstName R3
SYMATTR Value 470
SYMBOL res -48 -288 R0
SYMATTR InstName R2
SYMATTR Value 47000
SYMBOL npn 32 -144 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
FLAG -288 112 0
FLAG -32 208 0
FLAG 96 208 0
FLAG 240 208 0
FLAG 544 -464 0
TEXT 416 -216 Left 2 ;Out
TEXT 432 -248 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\210ba7ef6f62_Basic_opamp1.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain stage and limiter
* Lowpass
* Output resistance
* Basic Opamp Subcircuit
* Model with infinite power supply rejection (PSRR)
* opamp2
Rout out 0 {ROUT}
G1 out 0 out0 0 {1/ROUT}
V2 V- 0 5
V1 V+ 0 -5
C1 out0 0 1p
XU1 in 0 V+ V- out opatyp1 ;pnba In+)In-)V+)V-)OUT
B1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))
VS in 0 0
R1 out0 0 1k
.subckt opatyp1 ip im vp vm out
.param GAIN=10000
.param ROUT=10
.ends
.dc VS -10m 10m 0.1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1504 680
WIRE 128 128 128 112
WIRE 96 144 64 144
WIRE 256 160 160 160
WIRE -16 176 -32 176
WIRE 96 176 -16 176
WIRE -32 192 -32 176
WIRE 128 208 128 192
WIRE -32 288 -32 272
WIRE -32 400 -32 384
WIRE 112 400 112 384
WIRE -32 496 -32 480
WIRE 112 496 112 480
LINE Normal 160 224 256 288
LINE Normal 176 256 160 224
LINE Normal 160 224 176 256
LINE Normal 192 224 160 224
SYMBOL Opamps\\opamp2 128 96 R0
SYMATTR InstName U1
SYMATTR Value opatyp1
SYMBOL voltage 112 384 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -32 176 R0
SYMATTR InstName VS
SYMATTR Value 0
SYMBOL voltage -32 384 R0
SYMATTR InstName V1
SYMATTR Value -5
FLAG 64 144 0
FLAG 128 112 V+
FLAG 128 208 V-
FLAG -32 288 0
FLAG -32 496 0
FLAG 112 496 0
FLAG -32 384 V+
FLAG 112 384 V-
FLAG 256 160 out
FLAG -16 176 in
TEXT 368 136 Left 0 !.subckt opatyp1 ip im vp vm out\n.param GAIN=10000\n.param ROUT=10\n* Gain stage and limiter\nB1 out0 0 I=1m*limit(V(vm), GAIN*V(ip,im), V(vp))\n* Lowpass\nR1 out0 0 1k\nC1 out0 0 1p\n* Output resistance\nG1 out 0 out0 0 {1/ROUT}\nRout out 0 {ROUT}\n.ends
TEXT -88 32 Left 0 !.dc VS -10m 10m 0.1m
TEXT -88 -24 Left 0 ;Basic Opamp Subcircuit
TEXT 280 72 Left 0 ;Model with infinite power supply rejection (PSRR)
TEXT 216 304 Left 0 ;opamp2
* Z:\home\khalils\Downloads\files\data\raw_asc\0c48f419f88f_Rbot_bias_sim.asc
* Generated by LTspice 26.0.1 for Windows.
V1 VDC 0 PWL(0 0 100m 100)
I1 Vgate 0 {Ileak}
D1 0 Vgate BZX84C8V2L
R2 0 Vgate {Rbot}
R1 Vgate VDC {6*470000}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
.step param Rbot 100k 1Meg 10k
.param Ileak=100n Rbot=330k
.meas TRAN Vth FIND V(VDC) WHEN V(Vgate)=3.2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 112 -64 112
WIRE 16 112 -48 112
WIRE 192 112 96 112
WIRE 240 112 192 112
WIRE 272 112 240 112
WIRE 352 112 272 112
WIRE -64 128 -64 112
WIRE 192 128 192 112
WIRE 272 144 272 112
WIRE 64 208 -64 208
WIRE 192 208 64 208
WIRE 272 208 192 208
WIRE 352 208 352 192
WIRE 352 208 272 208
WIRE 64 224 64 208
SYMBOL zener 288 208 R180
WINDOW 0 24 64 Left 2
WINDOW 3 -114 -31 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84C8V2L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 112 96 R90
WINDOW 0 -31 53 VBottom 2
WINDOW 3 -31 53 VTop 2
SYMATTR InstName R1
SYMATTR Value {6*470000}
SYMBOL current 352 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value {Ileak}
SYMBOL voltage -64 112 R0
WINDOW 0 -69 30 Left 2
WINDOW 3 -147 68 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 100m 100)
SYMBOL res 208 224 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value {Rbot}
FLAG 64 224 0
FLAG 240 112 Vgate
FLAG -48 112 VDC
TEXT -98 284 Left 2 !.tran 1
TEXT 24 296 Left 2 !.step param Rbot 100k 1Meg 10k
TEXT 40 352 Left 2 !.param Ileak=100n Rbot=330k
TEXT 48 392 Left 2 !.meas TRAN Vth FIND V(VDC) WHEN V(Vgate)=3.2
* Z:\home\khalils\Downloads\files\data\raw_asc\ADPL42005-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADPL42005-1.8.asy)
Rload OUT 0 3.6
C1 OUT 0 2.2 Rser=1.5m
R1 OUT N001 100k
V1 IN 0 3.3
XU1 IN OUT IN N001 OUT 0 ADPL42005-1.8 ;pnba Vin)Sense)EN)PG)Vout)GND
.tran 3m startup
.lib ADPL42005-1.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 3.6
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ADPL42005-1.8 224 128 R0
SYMATTR InstName U1
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 288 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1772B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1772B.asy)
L1 N006 OUT 4.7
R4 N002 0 10K
V1 IN 0 5
MQ1 N006 N004 N001 N001 FDC638P
C2 N003 N002 220p
D1 0 N006 MBRS340
XU1 N003 0 N005 N001 IN N004 LTC1772B ;pnba Ith/Run)GND)FB)Sense-)Vin)Pgate
R3 OUT N005 169K
R2 N005 0 78.7K
R1 N001 IN 0.03
C1 OUT 0 47 Rser=.1
Rload OUT 0 2
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 250u startup
.lib LTC1772B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2248 1200
WIRE 1600 544 1312 544
WIRE 1760 544 1600 544
WIRE 1600 560 1600 544
WIRE 1760 560 1760 544
WIRE 1312 576 1312 544
WIRE 1600 656 1600 640
WIRE 1600 656 1488 656
WIRE 1760 656 1760 640
WIRE 1600 720 1600 656
WIRE 944 736 928 736
WIRE 1056 736 1024 736
WIRE 1136 736 1120 736
WIRE 1552 736 1488 736
WIRE 1520 816 1488 816
WIRE 1600 832 1600 816
WIRE 1680 832 1600 832
WIRE 1840 832 1760 832
WIRE 1968 832 1840 832
WIRE 2080 832 1968 832
WIRE 1840 848 1840 832
WIRE 2080 848 2080 832
WIRE 1600 864 1600 832
WIRE 1968 864 1968 832
WIRE 1312 928 1312 896
WIRE 1600 928 1600 912
WIRE 1968 944 1968 928
WIRE 2080 944 2080 928
WIRE 1520 960 1520 816
WIRE 1840 960 1840 928
WIRE 1840 960 1520 960
WIRE 1840 976 1840 960
WIRE 1840 1072 1840 1056
SYMBOL schottky 1584 928 M180
WINDOW 0 37 58 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL polcap 1952 864 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMATTR SpiceLine Rser=.1
SYMBOL res 1824 832 R0
SYMATTR InstName R3
SYMATTR Value 169K
SYMBOL res 1040 720 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL PowerProducts\\LTC1772B 1312 736 R0
SYMATTR InstName U1
SYMBOL PMOS 1552 816 M180
WINDOW 0 56 80 Left 2
WINDOW 3 56 44 Left 2
SYMATTR InstName Q1
SYMATTR Value FDC638P
SYMBOL RES 1584 656 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R1
SYMATTR Value 0.03
SYMBOL ind 1664 848 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL res 2064 832 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL res 1824 960 R0
SYMATTR InstName R2
SYMATTR Value 78.7K
SYMBOL cap 1120 720 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 220p
SYMBOL VOLTAGE 1760 544 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 2080 832 OUT
FLAG 1760 656 0
FLAG 1968 944 0
FLAG 2080 944 0
FLAG 1840 1072 0
FLAG 928 736 0
FLAG 1600 928 0
FLAG 1312 928 0
FLAG 1760 544 IN
TEXT 1968 1032 Left 2 !.tran 250u startup