Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM705.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM705.asy)
R4 0 _PFO 1Meg
V4 WDI 0 PULSE(0 3.5 1m 10n 10n 100m 2)
V1 VCC 0 5
R2 0 _RESET 1Meg
XU1 WDI WDO VCC NC_01 _PFO _MR _RESET 0 ADM705 ;pnba WDI)WDO)VCC)PFI)_PFO)_MR)_RESET)GND
V2 _MR 0 PULSE(3.5 0 1 10n 10n 500m 2 1)
R1 0 WDO 1Meg
.tran 4 startup
.lib ADM705.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 -16 -48 -16
WIRE 176 -16 128 -16
WIRE 464 -16 400 -16
WIRE 512 -16 464 -16
WIRE 608 -16 592 -16
WIRE -48 0 -48 -16
WIRE -48 96 -48 80
WIRE 128 96 32 96
WIRE 176 96 128 96
WIRE 464 96 400 96
WIRE 512 96 464 96
WIRE 608 96 592 96
WIRE 32 112 32 96
WIRE 32 208 32 192
WIRE 128 208 96 208
WIRE 176 208 128 208
WIRE 96 224 96 208
WIRE 96 320 96 304
WIRE 464 320 400 320
WIRE 512 320 464 320
WIRE 608 320 592 320
WIRE 288 400 288 384
SYMBOL voltage 32 96 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 3.5 1m 10n 10n 100m 2)
SYMBOL ADM705 288 144 R0
SYMATTR InstName U1
SYMBOL voltage 96 208 M0
SYMATTR InstName V2
SYMATTR Value PULSE(3.5 0 1 10n 10n 500m 2 1)
SYMBOL res 608 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL res 608 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL voltage -48 -16 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 608 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
FLAG -48 96 0
FLAG 288 400 0
FLAG 608 -16 0
FLAG 608 96 0
FLAG 608 320 0
FLAG 96 320 0
FLAG 128 -16 VCC
FLAG 128 208 _MR
FLAG 464 -16 WDO
FLAG 464 96 _RESET
FLAG 464 320 _PFO
FLAG 32 208 0
FLAG 128 96 WDI
TEXT 216 456 Left 2 !.tran 4 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2dac5c3cd1d2_cs_amp.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .tf V(Vout) V1
* .tran 5m
M2 Vout Vout Vdd Vdd PMOS l=0.36u w=6.1u
M1 Vout Vin 0 0 NMOS l=0.36u w=10.13u
V1 Vin 0 SINE(0.65 1m 1k) AC 1
V2 Vdd 0 1.8
C1 Vout 0 1p
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.options plotwinsize=0
.include tsmc180.txt
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 16 272 -48
WIRE 352 16 272 16
WIRE 272 32 272 16
WIRE 224 48 176 48
WIRE 352 80 352 16
WIRE 352 80 272 80
WIRE 176 144 176 48
WIRE 272 144 272 128
WIRE 272 144 176 144
WIRE 272 192 272 144
WIRE 512 192 272 192
WIRE 560 192 512 192
WIRE 272 208 272 192
WIRE 512 224 512 192
WIRE 368 256 272 256
WIRE 224 288 144 288
WIRE -288 320 -288 256
WIRE -144 320 -144 256
WIRE 272 320 272 304
WIRE 368 320 368 256
WIRE 368 320 272 320
WIRE 512 320 512 288
WIRE 272 400 272 320
WIRE -288 480 -288 400
WIRE -144 480 -144 400
IOPIN 560 192 Out
SYMBOL pmos4 224 128 M180
WINDOW 123 65 4 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=0.36u w=6.1u
SYMBOL cap 496 224 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL nmos4 224 208 R0
WINDOW 123 62 141 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=0.36u w=10.13u
SYMBOL voltage -288 304 R0
WINDOW 3 -268 103 Left 2
WINDOW 123 -125 139 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0.65 1m 1k)
SYMATTR Value2 AC 1
SYMBOL voltage -144 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
FLAG 272 -48 Vdd
FLAG 560 192 Vout
FLAG 144 288 Vin
FLAG 272 400 0
FLAG 512 320 0
FLAG -288 256 Vin
FLAG -144 256 Vdd
FLAG -288 480 0
FLAG -144 480 0
TEXT -360 -80 Left 2 !.options plotwinsize=0
TEXT -360 -48 Left 2 !.include tsmc180.txt
TEXT -360 -24 Left 2 ;.op
TEXT -360 0 Left 2 ;.tf V(Vout) V1
TEXT -360 24 Left 2 ;.tran 5m
TEXT -360 48 Left 2 !.ac dec 10 10 1gig
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX312.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\n \nBandwidth = 139MHz.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\MAX312.asy)
C1 vCOM1 0 36p
V3 v+ 0 15
V5 vVL 0 5
V4 v- 0 -15
V2 vNC1 0 15
R1 vCOM1 0 301
V1 vIN1 0 PULSE(0 2.4 0 10n 10n 5u 10u)
XU2 0 v+ vIN1 NC_01 NC_02 NC_03 vNC1 vCOM1 NC_04 NC_05 NC_06 NC_07 NC_08 NC_09 v- vVL MAX312 ;pnba GND)V+)IN1)IN2)IN3)IN4)NC1)COM1)NC2)COM2)NC3)COM3)NC4)COM4)V-)VL
.tran 100u
.param Vdd = 15
.lib MAX312.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2244 1360
WIRE 1072 -256 1056 -256
WIRE 1072 -208 1072 -256
WIRE 912 -128 544 -128
WIRE 960 -128 912 -128
WIRE 1232 -128 1184 -128
WIRE 1280 -128 1232 -128
WIRE 1376 -128 1280 -128
WIRE 1280 -96 1280 -128
WIRE 1376 -80 1376 -128
WIRE 912 -64 704 -64
WIRE 960 -64 912 -64
WIRE 544 -16 544 -128
WIRE 704 -16 704 -64
WIRE 1280 16 1280 -16
WIRE 1376 16 1376 -16
WIRE 544 96 544 64
WIRE 704 96 704 64
WIRE 672 224 608 224
WIRE 848 224 784 224
WIRE 608 288 608 224
WIRE 784 288 784 224
WIRE 1232 320 1184 320
WIRE 1280 320 1232 320
WIRE 1280 368 1280 320
WIRE 608 416 608 368
WIRE 784 416 784 368
WIRE 1280 480 1280 448
WIRE 1120 496 1120 464
WIRE 1024 512 1024 464
WIRE 1024 512 1008 512
RECTANGLE Normal 768 -432 16 -720 2
SYMBOL MAX312 1072 -80 R0
SYMATTR InstName U2
SYMBOL voltage 544 -32 R0
WINDOW 0 33 8 Left 2
WINDOW 3 41 71 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL voltage 608 272 R0
WINDOW 0 58 35 Bottom 2
WINDOW 3 54 69 Top 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL voltage 704 -32 R0
WINDOW 0 18 8 Left 2
WINDOW 3 -191 178 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 2.4 0 10n 10n 5u 10u)
SYMBOL voltage 1280 352 R0
WINDOW 0 18 8 Left 2
WINDOW 3 15 104 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 5
SYMBOL cap 1360 -80 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage 784 272 R0
WINDOW 0 58 35 Bottom 2
WINDOW 3 54 69 Top 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL res 1264 -112 R0
SYMATTR InstName R1
SYMATTR Value 301
FLAG 1280 480 0
FLAG 1280 16 0
FLAG 1376 16 0
FLAG 1120 496 0
FLAG 608 416 0
FLAG 704 96 0
FLAG 1056 -256 v+
FLAG 1008 512 v-
FLAG 672 224 v+
FLAG 784 416 0
FLAG 848 224 v-
FLAG 544 96 0
FLAG 1232 -128 vCOM1
FLAG 1232 320 vVL
FLAG 912 -128 vNC1
FLAG 912 -64 vIN1
TEXT 1408 528 Left 2 !.tran 100u
TEXT 32 -696 Left 2 ;Notes:\n \nBandwidth = 139MHz.
TEXT 32 -392 Left 2 !.param Vdd = 15
* Z:\home\khalils\Downloads\files\data\raw_asc\24d45bbf3f75_reto2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
XU1 0 N001 NC_01 NC_02 N003 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
XU2 NC_03 NC_04 NC_05 NC_06 N002 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N004 N003 R
R1 N001 N002 R
C1 N005 0 C
L1 N004 N005 L
R3 N003 N001 R
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 464 -48 448 -48
WIRE 336 112 304 112
WIRE 448 112 448 -48
WIRE 448 112 416 112
WIRE 464 112 448 112
WIRE 544 128 544 -48
WIRE 544 128 528 128
WIRE 560 128 544 128
WIRE 656 128 640 128
WIRE 768 128 736 128
WIRE 464 144 448 144
WIRE 448 176 448 144
WIRE 768 224 768 192
SYMBOL cap 752 128 R0
SYMATTR InstName C1
SYMBOL OpAmps\\UniversalOpAmp2 496 128 R0
SYMATTR InstName U1
SYMBOL res 560 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMBOL OpAmps\\UniversalOpAmp2 272 112 R0
SYMATTR InstName U2
SYMBOL res 656 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMBOL res 432 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMBOL ind 640 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
FLAG 768 224 0
FLAG 448 176 0
* Z:\home\khalils\Downloads\files\data\raw_asc\15b3bfcd6e37_Lab2_NonIdeal.asc
* Generated by LTspice 26.0.1 for Windows.
* Ac 325
Riron N004 0 30k
Rload N006 0 100
G1 0 N001 N004 0 1
Rsec N006 N005 5
Rs N003 N002 50
G4 N005 0 N001 0 {1/N}
G2 0 N001 N005 0 {1/N}
R2 N001 0 1G
Vs N002 0 Sin(0 325 50)
G3 N004 0 N001 0 1
Rprimary N004 N003 70
.tran 50m
.param N=15 ; turns ratio
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 160 0 112 0
WIRE 544 0 448 0
WIRE 160 16 160 0
WIRE 448 16 448 0
WIRE 304 32 208 32
WIRE 400 32 304 32
WIRE 304 128 304 32
WIRE 304 128 208 128
WIRE 400 128 304 128
WIRE 208 160 208 128
WIRE 304 160 304 128
WIRE 400 160 400 128
WIRE -176 176 -336 176
WIRE -48 176 -96 176
WIRE 160 176 160 96
WIRE 160 176 32 176
WIRE 448 176 448 96
WIRE 592 176 448 176
WIRE 720 176 672 176
WIRE -336 192 -336 176
WIRE 720 192 720 176
WIRE -32 224 -288 224
WIRE 112 224 112 0
WIRE 160 224 112 224
WIRE 544 224 544 0
WIRE 544 224 448 224
WIRE 656 224 544 224
WIRE -32 256 -32 224
WIRE 32 256 -32 256
WIRE 112 256 112 224
WIRE 112 256 32 256
WIRE 208 256 208 240
WIRE 304 256 304 240
WIRE 400 256 400 240
WIRE 656 272 656 224
WIRE 720 272 656 272
WIRE -336 288 -336 272
WIRE -288 288 -288 224
WIRE -288 288 -336 288
WIRE 720 288 720 272
RECTANGLE Normal 576 312 48 -96 2
SYMBOL res 704 176 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL res 48 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rprimary
SYMATTR Value 70
SYMBOL res 16 160 R0
SYMATTR InstName Riron
SYMATTR Value 30k
SYMBOL g 160 0 M0
WINDOW 0 -10 10 Right 2
WINDOW 3 -16 104 Right 2
SYMATTR InstName G3
SYMATTR Value 1
SYMBOL res 688 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rsec
SYMATTR Value 5
SYMBOL g 400 144 M0
WINDOW 0 -10 9 Right 2
WINDOW 3 -15 96 Right 2
SYMATTR InstName G2
SYMATTR Value {1/N}
SYMBOL res 288 144 R0
SYMATTR InstName R2
SYMATTR Value 1G
SYMBOL res -80 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rs
SYMATTR Value 50
SYMBOL g 208 144 R0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL voltage -336 176 R0
SYMATTR InstName Vs
SYMATTR Value Sin(0 325 50)
SYMBOL g 448 0 R0
WINDOW 0 13 18 Left 2
WINDOW 3 12 101 Left 2
SYMATTR InstName G4
SYMATTR Value {1/N}
FLAG -336 288 0
FLAG 400 256 0
FLAG 208 256 0
FLAG 208 80 0
FLAG 400 80 0
FLAG 304 256 0
FLAG 720 288 0
TEXT 528 336 Left 2 !.tran 50m
TEXT 192 296 Left 2 !.param N=15 ; turns ratio
TEXT -288 296 Left 2 ;Ac 325
* Z:\home\khalils\Downloads\files\data\raw_asc\0b23676cab27_LightDetector.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 5
I1 N001 out PULSE(20u 200u 0 4 1 0 5)
R1 out 0 24k
R4 out 0 1Meg
C2 out 0 14p
.tran 0 10 0 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 48 32 48
WIRE 32 80 32 48
WIRE 224 80 224 48
WIRE 224 208 224 160
WIRE 592 208 224 208
WIRE 672 208 592 208
WIRE 704 208 672 208
WIRE 224 240 224 208
FLAG 32 160 0
FLAG 224 320 0
FLAG 224 208 phototransistor
IOPIN 224 208 In
FLAG 592 272 0
FLAG 704 208 out
IOPIN 704 208 Out
FLAG 672 288 0
SYMBOL voltage 32 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL current 224 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE(20u 200u 0 4 1 0 5)
SYMBOL res 208 224 R0
SYMATTR InstName R1
SYMATTR Value 24k
SYMBOL res 656 192 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL cap 576 208 R0
SYMATTR InstName C2
SYMATTR Value 14p
TEXT 0 344 Left 2 !.tran 0 10 0 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG602.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input.\nPin capacitance and charge injection not included.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG602.asy)
V3 N003 0 PULSE(0 3 0 10n 10n 5m 10m)
V1 +V 0 5
V2 -V 0 -5
Vs N001 0 SINE(0 5 1k)
R1 N002 0 301
XU1 +V -V N003 N001 N002 0 ADG602 ;pnba Vdd)Vss)IN)S)D)GND
C1 N002 0 36p
.tran 20m
.lib ADG602.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 304 80 304 48
WIRE -128 160 -160 160
WIRE 208 160 -48 160
WIRE 464 160 400 160
WIRE 608 160 464 160
WIRE 464 192 464 160
WIRE 608 192 608 160
WIRE 208 224 80 224
WIRE 464 304 464 272
WIRE 608 304 608 256
WIRE -240 320 -240 272
WIRE -128 320 -128 272
WIRE 80 368 80 224
WIRE 240 384 240 336
WIRE 368 384 368 336
WIRE -240 448 -240 400
WIRE -128 448 -128 400
WIRE 80 496 80 448
SYMBOL voltage -128 304 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 448 176 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG602 304 208 R0
SYMATTR InstName U1
SYMBOL voltage -240 304 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 80 352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 3 0 10n 10n 5m 10m)
SYMBOL voltage -32 160 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Vs
SYMATTR Value SINE(0 5 1k)
SYMBOL cap 592 192 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG 464 304 0
FLAG 608 304 0
FLAG -240 448 0
FLAG -160 160 0
FLAG 80 496 0
FLAG 368 384 0
FLAG 304 48 +V
FLAG -240 272 +V
FLAG 240 384 -V
FLAG -128 448 0
FLAG -128 272 -V
TEXT 536 448 Left 2 !.tran 20m
TEXT -376 -48 Left 2 ;Note:\nSwitch shown for a logic 0 input.\nPin capacitance and charge injection not included.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4257-1.asc
* Generated by LTspice 26.0.1 for Windows.
VPSE 0 IN PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 17.5 515m 17.5 516m 57)
Rclass N003 N002 30.9
R2 N001 N004 100K
Cload N001 OUT 100 Rser=10m
C1 N001 N002 .1 Rser=10m
D1 0 N001 MURS120
D2 N002 IN MURS120
Rload N001 OUT 1.3K
XU1 NC_01 N003 NC_02 N002 OUT N004 N002 N001 LTC4257-1 ;pnba NC)Rclass)NC)Vin)Vout)_PWRGD)SigDisA)GND
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.7
* Diode Bridge
* Set for Class 4 Load
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4257-1.asy)
.lib LTC4257-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1308 744
WIRE -704 128 -1296 128
WIRE -480 128 -704 128
WIRE -352 128 -416 128
WIRE 336 128 -352 128
WIRE 480 128 336 128
WIRE 592 128 480 128
WIRE 752 128 592 128
WIRE 368 176 -80 176
WIRE -704 192 -704 128
WIRE 336 272 336 128
WIRE 336 272 320 272
WIRE 480 272 480 128
WIRE 592 272 592 128
WIRE 752 272 752 128
WIRE -1296 288 -1296 128
WIRE -352 288 -352 128
WIRE -32 352 -192 352
WIRE 368 352 368 176
WIRE 368 352 320 352
WIRE -192 400 -192 352
WIRE 480 432 480 352
WIRE 480 432 320 432
WIRE -1296 512 -1296 368
WIRE -480 512 -1296 512
WIRE -352 512 -352 352
WIRE -352 512 -416 512
WIRE -192 512 -192 480
WIRE -192 512 -352 512
WIRE -80 512 -80 176
WIRE -80 512 -192 512
WIRE -32 512 -80 512
WIRE 592 512 592 336
WIRE 592 512 320 512
WIRE 752 512 752 352
WIRE 752 512 592 512
FLAG 752 512 OUT
FLAG -704 192 0
FLAG -1296 512 IN
SYMBOL voltage -1296 272 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value PWL(0 0 10m 6 250m 6 260m 5 500m 5 505m 17.5 515m 17.5 516m 57)
SYMATTR InstName VPSE
SYMBOL res -208 384 R0
SYMATTR InstName Rclass
SYMATTR Value 30.9
SYMBOL res 464 256 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap 576 272 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName Cload
SYMATTR Value 100
SYMBOL cap -368 288 R0
WINDOW 39 24 84 Left 2
SYMATTR SpiceLine Rser=10m
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL diode -480 112 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MURS120
SYMBOL diode -416 528 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value MURS120
SYMBOL res 736 256 R0
SYMATTR InstName Rload
SYMATTR Value 1.3K
SYMBOL LTC4257-1 144 368 R0
SYMATTR InstName U1
TEXT 392 576 Left 2 !.tran 0.7
TEXT -360 64 Right 2 ;Diode Bridge
TEXT -280 544 Left 2 ;Set for Class 4 Load
* Z:\tmp\asc_dec_bjh7r6w2\033745688a27_TriangWave_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
Rc +V Sqr 1k
V2 -V 0 -12V Rser=0
XU2 0 N001 +V -V triang LTC1050 ;pnba In+)In-)V+)V-)OUT
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1050A.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -208 112 -208 96
WIRE -144 224 -192 224
WIRE -144 224 -144 128
WIRE -128 96 -208 96
WIRE -128 128 -144 128
WIRE -112 224 -144 224
WIRE -96 80 -96 64
WIRE -96 176 -96 160
WIRE -32 112 -48 112
WIRE 0 112 -32 112
WIRE 0 112 0 80
WIRE 0 224 -32 224
WIRE 0 224 0 112
WIRE 16 112 0 112
WIRE 128 112 96 112
WIRE 128 112 128 0
WIRE 128 160 128 144
WIRE 160 0 128 0
WIRE 160 112 128 112
WIRE 160 144 128 144
WIRE 272 -48 -320 -48
WIRE 272 0 224 0
WIRE 272 0 272 -48
WIRE 272 128 224 128
WIRE 272 128 272 0
SYMBOL res -16 -16 R0
SYMATTR InstName Rc
SYMATTR Value 1k
SYMBOL voltage -16 352 R0
WINDOW 123 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -12V
SYMATTR SpiceLine Rser=0
SYMBOL Opamps\\LTC1050A 192 64 R0
WINDOW 3 -63 148 Left 0
SYMATTR InstName U2
FLAG -16 368 -V
FLAG -160 448 0
FLAG -16 448 0
FLAG -96 176 -V
FLAG 192 160 -V
FLAG 128 160 0
FLAG -208 112 0
FLAG 272 128 triang
FLAG -96 64 +V
FLAG -160 368 +V
FLAG 192 96 +V
FLAG -32 112 Sqr
FLAG 0 0 +V
* Z:\home\khalils\Downloads\files\data\raw_asc\2329e7bf256a_IXFK27N80Q_test.asc
* Generated by LTspice 26.0.1 for Windows.
* 1. Add a "nmos" component to the schematic.\n \n2. Replace the value NMOS with IXFK27N80Q\n on your nmos-transistor in the schematic.\n \n6. Put the model either on the schematic or into a file.\n \nAdd the line \n .include IXFK27N80Q.lib\nif you use a model file. \nI recommend to keep the model file in the same \nfolder as the schematic. This makes a complete\nbackup of a circuit easy.
* Plot Id(M1) to get the current Idrain depending on Vgs and Vds.
M1 N001 N002 0 0 IXFK27N80Q
V1 N002 0 0
V2 N001 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V2 -0 5 0.01 V1 3.9 4.5 0.2
.include IXFK27N80Q.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1512 988
WIRE -448 272 -448 240
WIRE -448 400 -448 352
WIRE -448 432 -448 400
WIRE -304 240 -448 240
WIRE -256 160 -256 128
WIRE -256 400 -448 400
WIRE -256 400 -256 256
WIRE -32 128 -256 128
WIRE -32 176 -32 128
WIRE -32 400 -256 400
WIRE -32 400 -32 256
SYMBOL voltage -448 256 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL nmos -304 160 R0
SYMATTR InstName M1
SYMATTR Value IXFK27N80Q
SYMBOL voltage -32 160 R0
SYMATTR InstName V2
SYMATTR Value 5
FLAG -448 432 0
TEXT -448 16 Left 0 !.dc V2 -0 5 0.01 V1 3.9 4.5 0.2
TEXT -472 488 Left 0 ;1. Add a "nmos" component to the schematic.\n \n2. Replace the value NMOS with IXFK27N80Q\n    on your nmos-transistor in the schematic.\n \n6. Put the model either  on the schematic or into a file.\n \nAdd the line  \n    .include IXFK27N80Q.lib\nif you use a model file. \nI recommend to keep the model file in the same \nfolder as the schematic. This makes a complete\nbackup of a circuit easy.
TEXT -448 64 Left 0 !.include IXFK27N80Q.lib
TEXT -456 -48 Left 0 ;Plot Id(M1) to get the current Idrain depending on Vgs and Vds.
* Z:\home\khalils\Downloads\files\data\raw_asc\0736ab00e592_6275.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6275.asy)
V3 N001 0 SINE(0 10 3Meg)
R1 N003 N002 1K
XU1 0 N002 +V -V N003 LT6275 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -15
R2 N002 N001 1K
V1 +V 0 15
.tran 10u
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 -112 0 -112
WIRE 256 -112 224 -112
WIRE 288 -112 256 -112
WIRE 416 -112 368 -112
WIRE 0 -96 0 -112
WIRE -336 -80 -336 -96
WIRE -176 -80 -176 -96
WIRE 0 0 0 -16
WIRE 336 0 336 -16
WIRE -336 16 -336 0
WIRE -176 16 -176 0
WIRE 256 16 256 -112
WIRE 304 16 256 16
WIRE 416 32 416 -112
WIRE 416 32 368 32
WIRE 304 48 288 48
WIRE 336 80 336 64
SYMBOL voltage -176 -96 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 0 -112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 10 3Meg)
SYMBOL res 384 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL LT6275 336 32 R0
SYMATTR InstName U1
SYMBOL res 240 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -336 -96 R0
SYMATTR InstName V1
SYMATTR Value 15
FLAG -336 16 0
FLAG -176 16 0
FLAG -336 -96 +V
FLAG -176 -96 -V
FLAG 336 -16 +V
FLAG 336 80 -V
FLAG 0 0 0
FLAG 288 48 0
TEXT 432 136 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\4e1394e9955e_bss83.asc
* Generated by LTspice 26.0.1 for Windows.
* GAMMA added
* Enhanced model of the BSS83 from Philips\n \nSweep of Vgs from 0 to 5V at Vsb=-8, -4, 0V\n.dc V1 0 5 .1 V2 -8 0 4\nPlot Id(M1) to see how Vsb changes the behaviour.\n \nI added GAMMA=0.2 to the model to get the correct Ids(Vgs, Vsb).\nThe simulated drain current is independent of Vsb if GAMMA is \nomitted. This was clearly a missing parameter in the original model.\n \nThe complete ".model"-statement can be also put into a file \nlike BSS83.mod and added with a SPICEdirective.\n.include BSS83.mod
* * Philips model\n.MODEL BSS83 NMOS\n+ LEVEL=3\n+ W=1E-3\n+ L=1E-6\n+ VTO=2\n+ VMAX=1E6\n+ RS=3\n+ RD=3\n+ CJ=0.001396\n+ MJ=0.3936\n+ THETA=1E-6\n+ ETA=0.009307\n+ KAPPA=2.226
+ LEVEL=3
+ W=1E-3
+ L=1E-6
+ VTO=2
+ VMAX=1E6
+ RS=3
+ RD=3
+ CJ=0.001396
+ MJ=0.3936
+ THETA=1E-6
+ ETA=0.009307
+ KAPPA=2.226
+ GAMMA=0.2
V2 N002 0 0
V1 N003 0 2
M1 N001 N003 0 N002 BSS83
V3 N001 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL BSS83 NMOS
.dc V1 0 5 .1 V2 -8 0 4
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1088 680
WIRE 32 256 32 224
WIRE 32 384 32 336
WIRE 128 224 32 224
WIRE 176 144 176 -32
WIRE 176 384 176 240
WIRE 288 -32 176 -32
WIRE 288 0 288 -32
WIRE 288 112 288 80
WIRE 288 192 176 192
WIRE 288 224 288 192
WIRE 288 384 288 304
SYMBOL nmos4 128 144 R0
SYMATTR InstName M1
SYMATTR Value BSS83
SYMBOL voltage 288 -16 R0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 288 208 R0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage 32 240 R0
SYMATTR InstName V1
SYMATTR Value 2
FLAG 288 112 0
FLAG 288 384 0
FLAG 32 384 0
FLAG 176 384 0
TEXT 448 0 Left 0 !* GAMMA added\n.MODEL BSS83 NMOS\n+ LEVEL=3\n+ W=1E-3\n+ L=1E-6\n+ VTO=2\n+ VMAX=1E6\n+ RS=3\n+ RD=3\n+ CJ=0.001396\n+ MJ=0.3936\n+ THETA=1E-6\n+ ETA=0.009307\n+ KAPPA=2.226\n+ GAMMA=0.2
TEXT 32 -112 Left 0 !.dc V1 0 5  .1 V2 -8 0 4
TEXT 32 -72 Left 0 !.op
TEXT 32 -496 Left 0 ;Enhanced model of the BSS83 from Philips\n \nSweep of Vgs from 0 to 5V at Vsb=-8, -4, 0V\n.dc V1 0 5  .1 V2 -8 0 4\nPlot Id(M1) to see how Vsb changes the behaviour.\n \nI added GAMMA=0.2 to the model to get the correct Ids(Vgs, Vsb).\nThe simulated drain current is independent of Vsb if GAMMA is \nomitted. This was clearly a missing parameter in the original model.\n \nThe complete ".model"-statement can be also put into a file \nlike BSS83.mod and added with a SPICEdirective.\n.include BSS83.mod
TEXT 720 0 Left 0 ;* Philips model\n.MODEL BSS83 NMOS\n+ LEVEL=3\n+ W=1E-3\n+ L=1E-6\n+ VTO=2\n+ VMAX=1E6\n+ RS=3\n+ RD=3\n+ CJ=0.001396\n+ MJ=0.3936\n+ THETA=1E-6\n+ ETA=0.009307\n+ KAPPA=2.226