* Z:\tmp\asc_dec_bjh7r6w2\013807eeb9de_pluto-a_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
M12 NC_01 bl_en NC_02 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M6 VDDby2 N002 bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Veq0 Eq0 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
M8 N003 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
VDD_source VDD 0 {core_voltage}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 0 0) Rser=100 Cpar=1fF
Veq2 Eq2 0 PULSE(0 0 0 0 0 0)
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 0 0) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2520
WIRE -1392 -1792 -1392 -1808
WIRE -1392 -1648 -1392 -1664
WIRE -1392 -1552 -1392 -1568
WIRE -608 -1152 -608 -1184
WIRE -240 -1152 -240 -1184
WIRE -4256 -1104 -4256 -1120
WIRE -2576 -1104 -2576 -1120
WIRE -608 -1040 -608 -1072
WIRE -240 -1040 -240 -1072
WIRE -4256 -1008 -4256 -1024
WIRE -2576 -1008 -2576 -1024
WIRE -800 -624 -800 -656
WIRE 1456 -560 1408 -560
WIRE 1584 -560 1456 -560
WIRE -800 -512 -800 -544
WIRE 1312 -256 1120 -256
WIRE 832 -240 832 -256
WIRE 832 -240 768 -240
WIRE 912 -240 960 -336
WIRE 912 -240 832 -240
WIRE 960 -240 912 -336
WIRE 1040 -240 1040 -256
WIRE 1040 -240 960 -240
WIRE 1120 -240 1120 -256
WIRE 1120 -240 1040 -240
WIRE 912 -144 768 -144
WIRE 1120 -144 1120 -240
WIRE 1120 -144 1008 -144
WIRE 880 -96 640 -96
WIRE 928 -96 880 -96
WIRE 1056 -96 928 -96
WIRE 1296 -96 1056 -96
WIRE 880 -80 880 -96
WIRE 1056 -80 1056 -96
WIRE 768 -48 768 -144
WIRE 768 -32 768 -48
WIRE 800 -32 768 -32
WIRE 944 -32 896 -32
WIRE 976 -32 944 -32
WIRE 1120 -32 1120 -144
WIRE 1120 -32 1072 -32
WIRE 1120 -16 1120 -32
WIRE 944 16 944 -32
WIRE 944 32 944 16
WIRE 768 80 768 -32
WIRE 832 80 768 80
WIRE 912 80 832 80
WIRE 1040 80 976 80
WIRE 1120 80 1120 -16
WIRE 1120 80 1040 80
WIRE 832 96 832 80
WIRE 1040 96 1040 80
WIRE 912 176 976 80
WIRE 912 176 880 176
WIRE 976 176 912 80
WIRE 992 176 976 176
WIRE 832 224 832 192
WIRE 832 224 720 224
WIRE 960 224 832 224
WIRE 1040 224 1040 192
WIRE 1040 224 960 224
WIRE 1312 400 1312 128
WIRE 1312 400 1200 400
WIRE 1200 432 1200 400
WIRE 1088 544 880 544
WIRE 1152 544 1152 512
WIRE 1152 544 1088 544
WIRE 1200 576 1200 528
WIRE 1200 592 1200 576
WIRE 1312 704 1312 400
SYMBOL nmos4 1584 -640 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 976 -80 M90
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL voltage -1392 -1664 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -2576 -1120 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq0
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL nmos4 1152 432 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -800 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -240 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 0 0)
SYMATTR InstName Vsn
SYMBOL voltage -4256 -1120 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Veq2
SYMATTR Value PULSE(0 0 0 0 0 0)
SYMBOL nmos4 880 96 M0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL voltage -608 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0 0)
SYMATTR InstName Vsp
SYMBOL nmos4 992 96 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
FLAG 720 272 0
FLAG -608 -1040 0
FLAG -608 -1184 sense_P
FLAG 1040 144 0
FLAG 832 144 0
FLAG 960 -144 0
FLAG 848 -32 0
FLAG 1024 -32 0
FLAG 944 16 VDDby2
FLAG 768 -48 bitline0
FLAG 1120 -16 bitline1
FLAG 1200 480 0
FLAG 1200 576 mb3
FLAG 1088 544 ra3
FLAG -1392 -1552 0
FLAG -1392 -1664 ra0
FLAG 960 224 NLAT
FLAG -240 -1040 0
FLAG -240 -1184 sense_N
FLAG -800 -512 0
FLAG -800 -656 VDD
FLAG 1632 -592 0
FLAG -1392 -1792 0
FLAG 1456 -560 bl_en
FLAG -2576 -1008 0
FLAG -2576 -1120 Eq0
FLAG -4256 -1008 0
FLAG -4256 -1120 Eq2