* Z:\home\khalils\Downloads\files\data\raw_asc\AD4112.asc
* Generated by LTspice 26.0.1 for Windows.
V4 N005 0 5
V2 N003 0 3.3
R1 0 Vout 10Meg
V1 N002 0 PULSE(0 2.5 97u 1n 1n 10m) AC 1
C1 0 N001 0.1
V5 N006 0 0
V3 N004 0 0
E1 VIN0 0 N002 0 1
E2 VIN1 0 N002 0 -1
XU1 VIN0 VIN1 0 0 0 N006 MP_01 N005 Vout 0 MP_02 N001 N003 NC_03 NC_04 N004 NC_05 AD4112 ODR=31.25k fsrSEL=0 inputSEL=0 sincSEL=0 clkSEL=0 refSEL=1 sing_cyc=0 ;pnba VIN0)VIN1)REF-)REF+)GND)AVSS))AVDD)Vout)CLK))REFOUT)IOVDD)IIN0+)IIN0-)VBIAS-)VINCOM
.tran 5m startup
* Only one channel of the AD4112 is modelled and other channels and related functions and pins are not modeled\n \nThe following parameters can be defined by right-clicking on the AD4112 symbol: \nODR: Sets the output data rate\nfsrSEL: Sets full-scale range. 0 for +/- 10*Vref, 1 for +/- 10V, 2 for +/- 5V, 3 for 0V to 10V, 4 for 0V to 5V\ninputSEL: 0 for VIN1-VIN0 voltage input, 1 for VIN1 input, 2 for VIN0 input, 3 for IIN1 IIN0 input\nsincSEL: 0 for SINC3 filter, 1 for SINC5+SINC1 filter\nrefSEL: 0 for REFP-REFM, 1 for internal 2.5V reference, 2 for AVDD-AVSS\nclkSEL: 0 for internal 2 MHz clock\nsing_cyc: 0 for normal ODR, 1 for single cycle settling
* This model emulates the actual part, including startup behavior.\nWhen the part is first powered on, there is a delay of Tsettle/2 of the set ODR is required for the input voltage.\n \nTo simulate startup behavior, please consider the simulation startup command. For example ".tran 0 5m startup". \nIf startup is present, then DC sources will start at 0V and reach their final value 20 us later. For other ramp rates, please use piecewise linear (PWL) or pulse sources.\n \nIf one wishes to simulate steady-state behavior, then one must run the simulation for at least Tsettle of the set ODR before applying the input signal.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4112.asy)
.lib AD4112.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1756 680
WIRE 304 -48 304 -64
WIRE 48 32 48 -64
WIRE 176 32 176 -64
WIRE 304 32 304 16
WIRE 448 32 448 -64
WIRE 752 112 560 112
WIRE 800 112 752 112
WIRE -224 128 -464 128
WIRE -128 128 -224 128
WIRE -464 144 -464 128
WIRE 752 144 752 112
WIRE -512 160 -784 160
WIRE -784 208 -784 160
WIRE -672 208 -784 208
WIRE -224 224 -304 224
WIRE -128 224 -224 224
WIRE 608 224 560 224
WIRE -784 240 -784 208
WIRE -304 240 -304 224
WIRE 752 240 752 224
WIRE -672 256 -672 208
WIRE -352 256 -672 256
WIRE 48 336 48 320
WIRE 176 336 176 320
WIRE 304 336 304 320
WIRE 448 336 448 320
WIRE -784 352 -784 320
WIRE 48 432 48 416
WIRE 176 432 176 416
WIRE 304 432 304 416
WIRE 448 432 448 416
FLAG 304 432 0
FLAG 448 432 0
FLAG 48 432 0
FLAG 608 224 0
FLAG 752 240 0
FLAG -784 352 0
FLAG -224 128 VIN1
FLAG -224 224 VIN0
FLAG 304 -64 0
FLAG 176 -64 0
FLAG 48 -64 0
FLAG 176 432 0
FLAG 448 -64 0
FLAG -304 320 0
FLAG -352 304 0
FLAG -464 224 0
FLAG -512 208 0
FLAG 800 112 Vout
SYMBOL voltage 304 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 736 240 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R1
SYMATTR Value 10Meg
SYMBOL voltage -784 224 R0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value PULSE(0 2.5 97u 1n 1n 10m)
SYMBOL cap 288 -48 R0
SYMATTR InstName C1
SYMATTR Value 0.1u
SYMBOL voltage 448 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 0
SYMBOL voltage 176 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL e -304 224 R0
SYMATTR InstName E1
SYMATTR Value 1
SYMBOL e -464 128 R0
SYMATTR InstName E2
SYMATTR Value -1
SYMBOL AD4112 32 176 R0
SYMATTR InstName U1
TEXT 648 472 Left 2 !.tran 5m startup
TEXT -776 -696 Left 2 ;Only one channel of the AD4112 is modelled and other channels and related functions and pins are not modeled\n \nThe following parameters can be defined by right-clicking on the AD4112 symbol: \nODR: Sets the output data rate\nfsrSEL:  Sets full-scale range.  0 for +/- 10*Vref, 1 for +/- 10V, 2 for +/- 5V, 3 for 0V to 10V, 4 for 0V to 5V\ninputSEL: 0 for VIN1-VIN0 voltage input, 1 for VIN1 input, 2 for VIN0 input, 3 for IIN1 IIN0 input\nsincSEL:  0 for SINC3 filter, 1 for SINC5+SINC1 filter\nrefSEL: 0 for REFP-REFM, 1 for internal 2.5V reference, 2 for AVDD-AVSS\nclkSEL: 0 for internal 2 MHz clock\nsing_cyc: 0 for normal ODR, 1 for single cycle settling
TEXT -768 -360 Left 2 ;This model emulates the actual part, including startup behavior.\nWhen the part is first powered on, there is a delay of Tsettle/2 of the set ODR is required for the input voltage.\n \nTo simulate startup behavior, please consider the simulation startup command.  For example ".tran 0 5m startup".  \nIf startup is present, then DC sources will start at 0V and reach their final value 20 us later.  For other ramp rates, please use piecewise linear (PWL) or pulse sources.\n \nIf one wishes to simulate steady-state behavior, then one must run the simulation for at least Tsettle of the set ODR before applying the input signal.