* Z:\home\khalils\Downloads\files\data\raw_asc\LTC7000-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC7000-1.asy)
V4 N002 0 PWL(0 0 60m 0 +1u 1 +10m 1 +1u 0)
R1 OUT 0 13.5
M1 N001 N004 OUT OUT AOTL66518
V2 N009 0 PULSE(0 3.3 50m 10n 10n 50m 100m 1)
R3 N006 N007 100K
V1 IN 0 135
D1 0 OUT ES1D
R6 IN N001 5m
C4 N006 0 1
S1 0 OUT N002 0 SW
XU1 MP_01 IN N006 NC_02 N007 N008 N009 MP_03 MP_04 MP_05 N004 N004 OUT N005 N003 IN 0 LTC7000-1 ;pnba )Vin)Vcc)Vccuv)_Fault)Timer)INP))))TGdn)TGup)TS)BST)SNS-)SNS+)GND
C3 N008 0 1n
C2 OUT N005 0.1
R2 N001 N003 100
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m startup
.model SW SW(Ron=100m Roff=1G Vt=0.5 Vh=-0.3)
.lib LTC7000-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2608 1256
WIRE 816 -496 720 -496
WIRE 912 -496 816 -496
WIRE 928 -496 912 -496
WIRE 1040 -496 1008 -496
WIRE 1152 -496 1040 -496
WIRE 1264 -496 1248 -496
WIRE 1344 -496 1264 -496
WIRE 1440 -496 1344 -496
WIRE 1664 -496 1440 -496
WIRE 1792 -496 1664 -496
WIRE 720 -480 720 -496
WIRE 1040 -480 1040 -496
WIRE 1664 -480 1664 -496
WIRE 1792 -480 1792 -496
WIRE 2064 -464 1840 -464
WIRE 2176 -464 2144 -464
WIRE 1264 -448 1264 -496
WIRE 1440 -448 1440 -496
WIRE 1856 -416 1840 -416
WIRE 720 -384 720 -400
WIRE 1664 -384 1664 -400
WIRE 1792 -384 1792 -400
WIRE 912 -368 912 -496
WIRE 1040 -368 1040 -400
WIRE 1264 -368 1264 -384
WIRE 928 -352 912 -368
WIRE 1024 -352 1040 -368
WIRE 1232 -352 1232 -448
WIRE 1232 -352 1136 -352
WIRE 928 -336 928 -352
WIRE 1024 -336 1024 -352
WIRE 1136 -336 1136 -352
WIRE 1232 -336 1232 -352
WIRE 1344 -336 1344 -496
WIRE 816 -256 816 -496
WIRE 864 -256 816 -256
WIRE 1440 -240 1440 -384
WIRE 1440 -240 1376 -240
WIRE 1440 -144 1376 -144
WIRE 1488 -144 1440 -144
WIRE 1568 -144 1552 -144
WIRE 1440 -128 1440 -144
WIRE 1440 -32 1440 -48
WIRE 1440 -32 1376 -32
WIRE 784 48 768 48
WIRE 864 48 848 48
WIRE 976 128 976 112
WIRE 1120 128 1120 112
WIRE 976 224 976 208
SYMBOL voltage 976 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 13 100 Left 2
SYMATTR Value PULSE(0 3.3 50m 10n 10n 50m 100m 1)
SYMATTR InstName V2
SYMBOL sw 1792 -384 R180
WINDOW 0 -17 96 Right 2
WINDOW 3 -16 15 Right 2
SYMATTR InstName S1
SYMBOL nmos 1152 -448 R270
WINDOW 0 87 24 VTop 2
WINDOW 3 68 140 VLeft 2
SYMATTR InstName M1
SYMATTR Value AOTL66518
SYMBOL cap 1424 -448 R0
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL res 1024 -496 R0
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL voltage 720 -496 R0
SYMATTR InstName V1
SYMATTR Value 135
SYMBOL res 1648 -496 R0
SYMATTR InstName R1
SYMATTR Value 13.5
SYMBOL cap 1488 -128 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 912 -480 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 5m
SYMBOL diode 1248 -384 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value ES1D
SYMBOL cap 848 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1n
SYMBOL voltage 2048 -464 R270
WINDOW 3 -32 56 VBottom 2
WINDOW 0 32 56 VTop 2
SYMATTR Value PWL(0 0 60m 0 +1u 1 +10m 1 +1u 0)
SYMATTR InstName V4
SYMBOL res 1424 -144 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL LTC7000-1 1120 -112 R0
SYMATTR InstName U1
FLAG 720 -384 0
FLAG 976 224 0
FLAG 1664 -384 0
FLAG 720 -496 IN
FLAG 1792 -496 OUT
FLAG 1120 128 0
FLAG 768 48 0
FLAG 1568 -144 0
FLAG 1792 -384 0
FLAG 1856 -416 0
FLAG 2176 -464 0
FLAG 1264 -368 0
TEXT 1512 128 Left 2 !.tran 100m startup\n.model SW SW(Ron=100m Roff=1G Vt=0.5 Vh=-0.3)