Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\604dcace2bb1_Vbe_break.asc
* Generated by LTspice 26.0.1 for Windows.
*Choose Is of diode 10^-10 lower than Is of transistor
* With external diode
* With subcircuit
* Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal transistor operation.
Q1 0 N001 N003 0 2N2907
D1 E B DEB
R4 N004 0 1k
Q1 C B E 2N2907
XQ2 0 N002 N004 Q2N2907 ;pnba C)B)E
D1 N003 N001 VBEDIO
R1 in N001 1k
R2 N003 0 1k
V1 in 0 0
R3 in N002 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 -10 10 0.1
.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
.SUBCKT Q2N2907 C B E
.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1480 744
WIRE 304 224 304 288
WIRE 304 480 -128 480
WIRE 208 208 208 176
WIRE 208 176 240 176
WIRE 208 176 48 176
WIRE -128 480 -128 304
WIRE -128 176 -128 224
WIRE -32 176 -128 176
WIRE -128 512 -128 480
WIRE 304 128 304 48
WIRE 304 48 448 48
WIRE 448 48 448 480
WIRE 448 480 304 480
WIRE 304 416 304 480
WIRE 208 272 208 288
WIRE 208 288 304 288
WIRE 304 288 304 336
WIRE 960 224 960 336
WIRE 816 176 896 176
WIRE 960 128 960 48
WIRE 960 48 1104 48
WIRE 1104 48 1104 480
WIRE 1104 480 960 480
WIRE 960 416 960 480
WIRE 736 176 672 176
WIRE 960 512 960 480
RECTANGLE Normal 416 320 96 96
SYMBOL voltage -128 208 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL res -48 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL diode 224 272 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMATTR Value VBEDIO
SYMBOL pnp 896 128 R0
WINDOW 3 79 79 Left 0
SYMATTR Value Q2N2907
SYMATTR InstName Q2
SYMATTR Prefix X
SYMBOL res 720 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL pnp 240 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL res 944 320 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 288 320 R0
SYMATTR InstName R2
SYMATTR Value 1k
FLAG -128 512 0
FLAG -128 176 in
FLAG 672 176 in
FLAG 960 512 0
TEXT -128 -200 Left 0 !.dc V1 -10 10 0.1
TEXT -144 -8 Left 0 !.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
TEXT 640 -136 Left 0 !.SUBCKT Q2N2907  C B E\nQ1 C B E  2N2907\nD1 E B DEB\n*Choose Is of diode 10^-10 lower than Is of transistor\n.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)\n.ENDS
TEXT -136 -56 Left 0 ;With external diode
TEXT 640 -184 Left 0 ;With subcircuit
TEXT -144 -424 Left 0 ;Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal  transistor operation.
* Z:\home\khalils\Downloads\files\data\raw_asc\0074b1740816_op_amp.asc
* Generated by LTspice 26.0.1 for Windows.
* Drive should be between 0 and 1000k.\nChange the value to see the difference in the frequency response.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
V1 N005 0 AC 1 0
R6 N002 N001 33k
C5 N001 N004 47n
RDrive N003 N002 1000k
V2 Vcc 0 9
V3 0 -Vcc 9
XU1 N005 N001 Vcc -Vcc N003 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R5 0 N004 4.7k
.ac dec 1k 10 20k
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3044 724
WIRE 528 -400 496 -400
WIRE 656 -400 608 -400
WIRE 768 -400 736 -400
WIRE 496 -208 496 -400
WIRE 416 -208 400 -208
WIRE 480 -208 464 -208
WIRE 496 -208 480 -208
WIRE 528 -208 496 -208
WIRE 768 -192 768 -400
WIRE 768 -192 592 -192
WIRE 896 -192 768 -192
WIRE 528 -176 16 -176
WIRE 560 -144 560 -160
WIRE 16 -128 16 -176
SYMBOL OpAmps/UniversalOpAmp 560 -192 R0
SYMATTR InstName U1
SYMBOL cap 480 -224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 47n
SYMBOL res 624 -416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 33k
SYMBOL res 304 -192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 4.7k
SYMBOL voltage 640 208 R0
SYMATTR InstName V2
SYMATTR Value 9
SYMBOL res 752 -416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Drive
SYMATTR Value 1000k
SYMBOL voltage 784 208 R0
SYMATTR InstName V3
SYMATTR Value 9
SYMBOL voltage 16 -144 R0
WINDOW 123 24 118 Left 2
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMATTR Value ""
FLAG 640 304 0
FLAG 784 224 0
FLAG 640 224 Vcc
FLAG 784 304 -Vcc
FLAG 560 -144 -Vcc
FLAG 560 -224 Vcc
FLAG 16 -48 0
FLAG 320 -208 0
TEXT 336 208 Left 2 !.ac dec 1k 10 20k
TEXT 64 -632 Left 2 ;Drive should be between 0 and 1000k.\nChange the value to see the difference in the frequency response.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8608S.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8608S.asy)
L1 N003 OUT 2.2 Rser=3m
R4 N001 N002 100K
C4 OUT 0 22 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
V1 IN 0 12
Rload OUT 0 2.2
R1 N006 0 18.2K
R2 OUT N005 1Meg
R3 N005 0 309K
XU2 N004 N001 NC_01 IN N005 N002 IN N003 N006 0 LT8608S ;pnba TR/SS)INTVcc)SYNC)VIN)FB)PG)EN/UV)SW)RT)GND
C1 N004 0 1n
C2 N001 0 1
C5 OUT N005 10p
.tran 750u startup
.lib LT8608S.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1044 680
WIRE 80 0 0 0
WIRE 112 0 80 0
WIRE 432 0 400 0
WIRE 496 0 432 0
WIRE 576 0 560 0
WIRE 0 16 0 0
WIRE 432 16 432 0
WIRE 80 96 80 0
WIRE 112 96 80 96
WIRE 432 96 400 96
WIRE 0 112 0 96
WIRE 432 192 400 192
WIRE 544 192 512 192
WIRE 656 192 544 192
WIRE 752 192 656 192
WIRE 848 192 752 192
WIRE 544 208 544 192
WIRE 656 208 656 192
WIRE 752 208 752 192
WIRE 848 208 848 192
WIRE 32 288 0 288
WIRE 112 288 96 288
WIRE 544 288 400 288
WIRE 656 288 656 272
WIRE 656 288 544 288
WIRE 544 304 544 288
WIRE 752 304 752 272
WIRE 848 304 848 288
WIRE 16 384 0 384
WIRE 112 384 96 384
WIRE 416 384 400 384
WIRE 544 400 544 384
SYMBOL LT8608S 256 192 R0
SYMATTR InstName U2
SYMBOL cap 96 272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res 112 368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 18.2K
SYMBOL res 416 0 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL cap 496 16 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 528 288 R0
SYMATTR InstName R3
SYMATTR Value 309K
SYMBOL cap 736 208 R0
SYMATTR InstName C4
SYMATTR Value 22
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL ind 416 208 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=3m
SYMBOL voltage 0 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 528 192 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL res 832 192 R0
SYMATTR InstName Rload
SYMATTR Value 2.2
SYMBOL cap 640 208 R0
SYMATTR InstName C5
SYMATTR Value 10p
FLAG 0 384 0
FLAG 0 288 0
FLAG 0 112 0
FLAG 576 0 0
FLAG 752 304 0
FLAG 544 400 0
FLAG 848 304 0
FLAG 848 192 OUT
FLAG 0 0 IN
FLAG 416 384 0
TEXT 672 384 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP122-2.85.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP122-2.85.asy)
C1 IN 0 1
V1 IN 0 5.5
XU1 OUT MP_01 0 IN MP_02 IN ADP122 K=1/5700 ;pnba Vout))GND)En))Vin
Rload OUT 0 100
C2 OUT 0 1
.tran 10m startup
.lib ADP122.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 400 96 352 96
WIRE 480 96 400 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 400 112 400 96
WIRE 480 112 480 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 400 208 400 176
WIRE 480 208 480 192
WIRE 256 272 256 256
SYMBOL res 464 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL ADP122-2.85 256 208 R0
SYMATTR InstName U1
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 384 112 R0
SYMATTR InstName C2
SYMATTR Value 1
FLAG 0 208 0
FLAG 256 272 0
FLAG 400 208 0
FLAG 480 208 0
FLAG 480 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3528B-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3528B-2.asy)
XU1 IN N002 NC_01 OUT N001 0 0 IN LTC3528B-2 ;pnba _SHDN)FB)Pgood)Vout)SW)PGND)SGND)Vin
C2 OUT N002 33p
R2 N002 0 287K
V1 IN 0 2
C1 OUT 0 10 Rser=1m
L1 IN N001 2.2 Rpar=5K
R1 OUT N002 499K
R3 OUT 0 8.25
.tran .5m startup
.lib LTC3528B-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 64 -112 64
WIRE 64 64 -32 64
WIRE 96 64 64 64
WIRE 192 64 176 64
WIRE -112 80 -112 64
WIRE 64 112 64 64
WIRE 192 112 192 64
WIRE -112 176 -112 160
WIRE -32 192 -32 64
WIRE -16 192 -32 192
WIRE 320 192 272 192
WIRE 432 192 320 192
WIRE 512 192 432 192
WIRE 608 192 512 192
WIRE 320 208 320 192
WIRE 432 208 432 192
WIRE 512 208 512 192
WIRE 608 208 608 192
WIRE 320 304 320 288
WIRE 320 304 272 304
WIRE 432 304 432 272
WIRE 432 304 320 304
WIRE 512 304 512 272
WIRE 608 304 608 288
WIRE 320 320 320 304
WIRE 64 400 64 384
WIRE 192 400 192 384
WIRE 320 416 320 400
SYMBOL cap 496 208 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=1m
SYMBOL res 304 304 R0
SYMATTR InstName R2
SYMATTR Value 287K
SYMBOL res 304 192 R0
SYMATTR InstName R1
SYMATTR Value 499K
SYMBOL res 592 192 R0
SYMATTR InstName R3
SYMATTR Value 8.25
SYMBOL ind 80 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rpar=5K
SYMBOL voltage -112 64 R0
WINDOW 0 20 15 Left 2
WINDOW 3 25 97 Left 2
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL cap 416 208 R0
SYMATTR InstName C2
SYMATTR Value 33p
SYMBOL PowerProducts\\LTC3528B-2 128 256 R0
SYMATTR InstName U1
FLAG -112 176 0
FLAG 64 400 0
FLAG 320 416 0
FLAG 512 304 0
FLAG 608 304 0
FLAG 192 400 0
FLAG 608 192 OUT
FLAG -112 64 IN
TEXT 464 392 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD712.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD712.asy)
V1 +V 0 15
Vin IN 0 SINE(0 1 10K)
XU1 IN N001 +V -V OUT AD712 ;pnba In+)In-)V+)V-)OUT
R2 OUT N001 10K
V2 -V 0 -15
R1 N001 0 10K
.tran 1m
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 688 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 432 -976 432 -992
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL AD712 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 688 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 256 -1056 0
TEXT 776 -952 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\65c7db396f49_OR3.asc
* Generated by LTspice 26.0.1 for Windows.
A1 N003 0 0 0 0 Y 0 0 BUF
M3 N002 C N003 Vdd PMOS l=180n
M1 Vdd A N001 Vdd PMOS
M4 N003 A 0 0 NMOS l=180n
M6 N003 C 0 0 NMOS l=180n
V1 Vdd 0 1.8
M5 N003 B 0 0 NMOS l=180n
M2 N001 B N002 Vdd PMOS l=180n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 692
WIRE 112 -48 112 -80
WIRE 192 -48 112 -48
WIRE 112 0 112 -48
WIRE 192 48 192 -48
WIRE 192 48 112 48
WIRE 112 144 112 96
WIRE -208 160 -208 96
WIRE 192 192 192 48
WIRE 192 192 112 192
WIRE -208 272 -208 240
WIRE 112 288 112 240
WIRE 192 336 192 192
WIRE 192 336 112 336
WIRE 112 384 -16 384
WIRE 144 384 112 384
WIRE 320 384 144 384
WIRE 416 384 320 384
WIRE 512 384 480 384
WIRE -16 432 -16 384
WIRE 144 432 144 384
WIRE 320 432 320 384
WIRE 64 480 -16 480
WIRE 224 480 144 480
WIRE 400 480 320 480
WIRE -16 608 -16 528
WIRE 64 608 64 480
WIRE 64 608 -16 608
WIRE 144 608 144 528
WIRE 144 608 64 608
WIRE 224 608 224 480
WIRE 224 608 144 608
WIRE 320 608 320 528
WIRE 320 608 224 608
WIRE 400 608 400 480
WIRE 400 608 320 608
WIRE 416 608 416 400
WIRE 416 608 400 608
WIRE 224 672 224 608
IOPIN 64 80 In
IOPIN -64 512 In
IOPIN 64 224 In
IOPIN 96 512 In
IOPIN 64 368 In
IOPIN 272 512 In
IOPIN 512 384 Out
IOPIN -208 96 Out
IOPIN 112 -80 In
SYMBOL nmos4 272 432 R0
SYMATTR InstName M6
SYMATTR Value2 l=180n
SYMBOL nmos4 -64 432 R0
SYMATTR InstName M4
SYMATTR Value2 l=180n
SYMBOL pmos4 64 0 R0
SYMATTR InstName M1
SYMBOL pmos4 64 144 R0
SYMATTR InstName M2
SYMATTR Value2 l=180n
SYMBOL Digital\\inv 416 320 R0
SYMATTR InstName A1
SYMBOL pmos4 64 288 R0
SYMATTR InstName M3
SYMATTR Value2 l=180n
SYMBOL voltage -208 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL nmos4 96 432 R0
SYMATTR InstName M5
SYMATTR Value2 l=180n
FLAG 64 80 A
FLAG -64 512 A
FLAG 64 224 B
FLAG 96 512 B
FLAG 64 368 C
FLAG 272 512 C
FLAG 224 672 0
FLAG 512 384 Y
FLAG -208 272 0
FLAG -208 96 Vdd
FLAG 112 -80 Vdd
* Z:\home\khalils\Downloads\files\data\raw_asc\562848f8c2b9_cmos_inv_ltspice.asc
* Generated by LTspice 26.0.1 for Windows.
* CMOS Inverter
+VTO = -1.40 KP = 3.2e-5 GAMMA = 3.30
+PHI = 0.65 LAMBDA = 9e-2 CBD = 65e-12
+CBS = 2e-14 IS = 1e-15 PB = 0.87
+CGSO = 0 CGDO = 0 CGBO = 1e-5
+CJ = 2e-10 MJ = 0.5 CJSW = 1e-9
+MJSW = 0.33 JS = 1e-8 TOX = 6.89e-10)
+VTO = 1.77 Kp = 2.169e-4 GAMMA = 4.10
+PHI = 0.65 LAMBDA = 1.5e-2 CBD = 20e-12
+CBS = 0 IS = 1e-15 PB = 0.87
+CBS = 2e-14 CGDO = 88e-8 CGBO = 0
+CJ = 2e-10 MJ = 0.5 CJSW = 1e-9
+MJSW = 0.33 JS = 1e-8 TOX = 1.265e-10)
M1 2+ W1 0 0 CD4007-NMOS
V2 W1 0 PULSE(0 5 0 1n 1n 1u 2u)
M2 2+ W1 Vp Vp CD4007-PMOS
V1 Vp 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL CD4007-PMOS PMOS ( LEVEL = 1 L=5u W=100u
.MODEL CD4007-NMOS NMOS ( LEVEL = 1 L=5u W=20u
.tran 10u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1416 680
WIRE -544 -224 -544 -256
WIRE -416 -224 -416 -256
WIRE -544 -112 -544 -144
WIRE -416 -112 -416 -144
WIRE 160 -96 160 -288
WIRE 112 -80 -16 -80
WIRE -192 48 -192 16
WIRE -192 48 -240 48
WIRE -16 48 -16 -80
WIRE -16 48 -192 48
WIRE 160 48 160 0
WIRE 224 48 160 48
WIRE 160 112 160 48
WIRE -16 192 -16 48
WIRE 112 192 -16 192
WIRE 160 288 160 208
IOPIN -240 48 In
IOPIN 224 48 In
IOPIN 160 -288 In
IOPIN -544 -256 In
IOPIN -416 -256 In
IOPIN -192 16 In
SYMBOL voltage -416 -240 R0
WINDOW 3 -79 179 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 0 1n 1n 1u 2u)
SYMATTR InstName V2
SYMBOL pmos 112 0 M180
SYMATTR InstName M2
SYMATTR Value CD4007-PMOS
SYMBOL nmos 112 112 R0
SYMATTR InstName M1
SYMATTR Value CD4007-NMOS
SYMBOL voltage -544 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -240 48 W1
FLAG 224 48 2+
FLAG 160 -288 Vp
FLAG 160 288 0
FLAG -544 -112 0
FLAG -416 -112 0
FLAG -544 -256 Vp
FLAG -416 -256 W1
FLAG -192 16 1+
TEXT 504 -112 Left 1 !.MODEL CD4007-PMOS    PMOS    ( LEVEL   = 1           L=5u    W=100u                \n+VTO    = -1.40         KP      = 3.2e-5        GAMMA   = 3.30  \n+PHI    = 0.65          LAMBDA  = 9e-2          CBD     = 65e-12\n+CBS    = 2e-14         IS      = 1e-15         PB      = 0.87\n+CGSO   = 0             CGDO    = 0             CGBO    = 1e-5\n+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9\n+MJSW   = 0.33          JS      = 1e-8          TOX     = 6.89e-10)
TEXT 504 56 Left 1 !.MODEL CD4007-NMOS    NMOS    ( LEVEL   = 1           L=5u    W=20u             \n+VTO    = 1.77          Kp      = 2.169e-4      GAMMA   = 4.10  \n+PHI    = 0.65          LAMBDA  = 1.5e-2        CBD     = 20e-12\n+CBS    = 0             IS      = 1e-15         PB      = 0.87\n+CBS    = 2e-14         CGDO    = 88e-8         CGBO    = 0\n+CJ     = 2e-10         MJ      = 0.5           CJSW    = 1e-9\n+MJSW   = 0.33          JS      = 1e-8          TOX     = 1.265e-10)
TEXT -336 248 Left 2 !.tran 10u
TEXT -128 -480 Left 2 ;CMOS Inverter
* Z:\home\khalils\Downloads\files\data\raw_asc\6aea2f9bc203_inv_amp.asc
* Generated by LTspice 26.0.1 for Windows.
V1 W1 0 SINE(0 1 1k)
R1 N001 W1 1k
R2 +2 N001 2.2k
R3 +2 0 10k
XU1 0 N001 V+ V- +2 OP27 ;pnba In+)In-)V+)V-)OUT
Vp1 V+ 0 5
Vn1 V- 0 -5
* Inverting Amplifier
.tran 10m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP27.asy)
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 32 256 32
WIRE 400 32 352 32
WIRE 304 160 304 112
WIRE 96 176 96 160
WIRE 96 176 80 176
WIRE 128 176 96 176
WIRE 256 176 256 32
WIRE 256 176 208 176
WIRE 272 176 256 176
WIRE -256 192 -256 176
WIRE -256 192 -272 192
WIRE -128 192 -128 176
WIRE -128 192 -144 192
WIRE 400 192 400 32
WIRE 400 192 336 192
WIRE 416 192 400 192
WIRE 432 192 416 192
WIRE -256 208 -256 192
WIRE -128 208 -128 192
WIRE 272 208 240 208
WIRE 416 240 416 192
WIRE 96 256 96 176
WIRE 240 272 240 208
WIRE 304 272 304 224
WIRE -256 320 -256 288
WIRE -128 320 -128 288
WIRE -128 320 -256 320
WIRE -128 336 -128 320
WIRE 96 368 96 336
WIRE 416 384 416 320
FLAG 96 368 0
FLAG 304 272 Vn
FLAG 304 112 Vp
FLAG 416 384 0
FLAG 240 272 0
FLAG 80 176 W1
IOPIN 80 176 In
FLAG 96 160 +1
IOPIN 96 160 In
FLAG 432 192 +2
IOPIN 432 192 In
FLAG -128 336 0
FLAG -256 176 Vp
FLAG -128 176 Vn
FLAG -272 192 V+
IOPIN -272 192 In
FLAG -144 192 V-
IOPIN -144 192 In
SYMBOL voltage 96 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
SYMBOL res 224 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 368 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 2.2k
SYMBOL res 400 224 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL Opamps\\OP27 304 128 R0
SYMATTR InstName U1
SYMBOL voltage -256 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vp1
SYMATTR Value 5
SYMBOL voltage -128 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vn1
SYMATTR Value -5
TEXT 96 -48 Left 2 ;Inverting Amplifier
TEXT -288 424 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\UniversalOpAmp3b.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
V3 N001 0 PULSE(-50m 50m 250n 1n 1n 1u 2u)
R1 OUT 0 10k
C1 OUT 0 10p
XU1 N001 OUT +V -V OUT level3b Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 Phimargin=45 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.tran 1.5u
* A two pole op amp with delay, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp3b.asy)
.lib UniversalOpAmp3b.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2580 1312
WIRE 560 560 400 560
WIRE 496 624 496 608
WIRE 400 640 400 560
WIRE 464 640 400 640
WIRE 560 656 560 560
WIRE 560 656 528 656
WIRE 656 656 560 656
WIRE 464 672 400 672
WIRE 560 672 560 656
WIRE 656 672 656 656
WIRE 496 704 496 688
WIRE 176 752 176 736
WIRE 288 752 288 736
WIRE 400 752 400 672
WIRE 560 768 560 752
WIRE 656 768 656 736
WIRE 176 848 176 832
WIRE 288 848 288 832
WIRE 400 848 400 832
FLAG 288 848 0
FLAG 176 848 0
FLAG 176 736 +V
FLAG 288 736 -V
FLAG 400 848 0
FLAG 496 704 -V
FLAG 496 608 +V
FLAG 656 768 0
FLAG 560 768 0
FLAG 656 656 OUT
SYMBOL voltage 176 736 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 288 736 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 400 736 R0
WINDOW 0 25 13 Left 2
WINDOW 3 27 90 Left 2
WINDOW 123 27 116 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(-50m 50m 250n 1n 1n 1u 2u)
SYMBOL res 544 656 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 640 672 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL UniversalOpAmp3b 496 656 R0
WINDOW 123 82 -97 Left 2
WINDOW 39 82 -69 Left 2
WINDOW 40 81 -42 Left 2
SYMATTR InstName U1
TEXT 152 904 Left 2 !.tran 1.5u
TEXT 384 904 Left 2 ;A two pole op amp with delay, programmable phase margin,\nslew rate limit, and output voltage and current limit.\n---------------------------------------------------------------------------------\nAvol = open-loop gain at DC (dB)\nGBW = gain-bandwidth product (Hz)\nSlew = slew rate limit  (V/s) \nIlimit = output current limit (A)\nRail = output voltage limit relative to the power supply (V)\nVos = input offset voltage (V)\nPhimargin = phase margin (degrees)\nEn = input voltage noise density (V/"Hz)\nEnk = input voltage noise density corner frequency (Hz)\nIn = input current noise density (A/"Hz)\nInk = input current noise density corner frequency (Hz)\nRin = input resistance ()