Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2457b9765153_2.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 efremov
V1 N002 0 V
V2 N001 0 0.9
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model efremov nmos VTO=0.34 LAMBDA=0.05 TOX=3.6n UO=353 l=0.18u w=9u
.dc V1 0 2.34 0.01 V2 0 2 0.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 96 144 96
WIRE 384 144 384 96
WIRE 96 176 -48 176
WIRE -48 208 -48 176
WIRE -48 320 -48 288
WIRE -16 320 -48 320
WIRE 144 320 144 192
WIRE 144 320 -16 320
WIRE 384 320 384 224
WIRE 384 320 144 320
FLAG -16 320 0
SYMBOL nmos 96 96 R0
SYMATTR InstName M1
SYMATTR Value efremov
SYMBOL voltage -48 192 R0
SYMATTR InstName V1
SYMBOL voltage 384 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0.9
TEXT -72 360 Left 2 !.model efremov nmos VTO=0.34 LAMBDA=0.05 TOX=3.6n UO=353 l=0.18u w=9u
TEXT -72 392 Left 2 !.dc V1 0 2.34 0.01 V2 0 2 0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\8df0b109ad81_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 NC_01 0 47k
V1 N001 0 12
R2 N004 N003 47
R5 N004 0 1k
XM2 N002 n1 N001 irfr9024n ;pnba D)G)S
XM1 n1 N004 0 irlml2502 ;pnba D)G)S
R4 N002 0 2
V2 N003 0 PULSE(0 5 0 0 0 0.0002 0.0004)
R1 N001 n1 4.7k
.tran 0 0.001 0 0.000001
.inc C:\Programme\LTC\LTspiceIV\lib\sub\irlml2502.sub
.inc C:\Programme\LTC\LTspiceIV\lib\sub\irfr9024n.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1480 680
WIRE 240 -48 -128 -48
WIRE 688 -48 240 -48
WIRE 240 0 240 -48
WIRE 688 48 688 -48
WIRE 640 64 464 64
WIRE -128 96 -128 -48
WIRE 240 112 240 80
WIRE 400 112 240 112
WIRE 464 112 464 64
WIRE 464 112 400 112
WIRE 480 112 464 112
WIRE 240 128 240 112
WIRE 688 160 688 144
WIRE 80 208 0 208
WIRE 176 208 160 208
WIRE 192 208 176 208
WIRE 0 240 0 208
WIRE 176 240 176 208
WIRE -128 256 -128 176
WIRE 240 256 240 224
WIRE 480 256 480 240
WIRE 688 272 688 240
WIRE 0 336 0 320
WIRE 176 336 176 320
SYMBOL voltage -128 80 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res 464 144 R0
SYMATTR InstName R3
SYMATTR Value 47k
SYMBOL res 672 144 R0
SYMATTR InstName R4
SYMATTR Value 2
SYMBOL res 176 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 47
SYMBOL nmos 192 128 R0
SYMATTR InstName M1
SYMATTR Value irlml2502
SYMATTR Prefix X
SYMBOL pmos 640 144 M180
SYMATTR InstName M2
SYMATTR Value irfr9024n
SYMATTR Prefix X
SYMBOL voltage 0 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 0 0 0.0002 0.0004)
SYMBOL res 224 -16 R0
SYMATTR InstName R1
SYMATTR Value 4.7k
SYMBOL res 160 224 R0
SYMATTR InstName R5
SYMATTR Value 1k
FLAG 240 256 0
FLAG -128 256 0
FLAG 400 112 n1
FLAG 0 336 0
FLAG 480 256 0
FLAG 688 272 0
FLAG 176 336 0
TEXT -160 360 Left 2 !.tran 0 0.001 0 0.000001
TEXT 104 400 Left 2 !.inc C:\\Programme\\LTC\\LTspiceIV\\lib\\sub\\irlml2502.sub
TEXT 104 432 Left 2 !.inc C:\\Programme\\LTC\\LTspiceIV\\lib\\sub\\irfr9024n.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\2363046028a2_74hc08.asc
* Generated by LTspice 26.0.1 for Windows.
A1 A1 B1 VSS VSS VSS VSS Y1 VSS AND Vhigh=5
A2 A2 B2 VSS VSS VSS VSS Y2 VSS AND Vhigh=5
A3 A3 B3 VSS VSS VSS VSS Y3 VSS AND Vhigh=5
A4 A4 B4 VSS VSS VSS VSS Y4 VSS AND Vhigh=5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1612 680
WIRE 256 0 192 0
WIRE 528 0 464 0
WIRE 256 16 192 16
WIRE 368 16 320 16
WIRE 528 16 464 16
WIRE 656 16 592 16
WIRE 160 80 128 80
WIRE 272 96 272 64
WIRE 544 96 544 64
WIRE 256 160 192 160
WIRE 528 160 464 160
WIRE 256 176 192 176
WIRE 368 176 320 176
WIRE 528 176 464 176
WIRE 656 176 592 176
WIRE 272 256 272 224
WIRE 544 256 544 224
SYMBOL Digital\\and 288 128 R0
WINDOW 3 17 5 Left 2
SYMATTR Value Vhigh=5
SYMATTR InstName A2
SYMBOL Digital\\and 560 -32 R0
WINDOW 3 12 5 Left 2
SYMATTR Value Vhigh=5
SYMATTR InstName A3
SYMBOL Digital\\and 560 128 R0
WINDOW 3 2 2 Left 2
SYMATTR Value Vhigh=5
SYMATTR InstName A4
SYMBOL Digital\\and 288 -32 R0
WINDOW 3 -24 2 Left 2
SYMATTR Value Vhigh=5
SYMATTR InstName A1
FLAG 368 16 Y1
FLAG 368 176 Y2
FLAG 656 16 Y3
FLAG 656 176 Y4
FLAG 192 0 A1
FLAG 192 160 A2
FLAG 464 0 A3
FLAG 464 160 A4
FLAG 192 16 B1
FLAG 192 176 B2
FLAG 464 16 B3
FLAG 464 176 B4
FLAG 272 96 VSS
FLAG 544 96 VSS
FLAG 544 256 VSS
FLAG 272 256 VSS
FLAG 128 80 VDD
* Z:\home\khalils\Downloads\files\data\raw_asc\5e4dc1f59a50_250p_IDVD.asc
* Generated by LTspice 26.0.1 for Windows.
VG N002 0
M1 N001 N002 0 N001 PMOS l=240n w=360n
VD N001 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib tsmc025.lib
.dc VD -2.5 0 0.01 VG -0.05 -2.5 -0.5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 64 208 64
WIRE 368 80 368 64
WIRE 208 112 208 64
WIRE 272 112 208 112
WIRE 208 128 208 112
WIRE 272 176 272 112
WIRE 272 176 208 176
WIRE 160 208 -48 208
WIRE -48 304 -48 288
WIRE 208 304 208 224
WIRE 208 304 -48 304
WIRE 368 304 368 160
WIRE 368 304 208 304
WIRE 208 336 208 304
SYMBOL pmos4 160 128 R0
SYMATTR InstName M1
SYMATTR Value2 l=240n w=360n
SYMBOL voltage 368 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VD
SYMATTR Value ""
SYMBOL voltage -48 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VG
SYMATTR Value ""
FLAG 208 336 0
TEXT -440 144 Left 2 !.lib tsmc025.lib
TEXT -584 192 Left 2 !.dc VD -2.5 0 0.01 VG -0.05 -2.5 -0.5
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2360-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2360-3.3.asy)
L1 N002 OUT 100 Rpar=50k
R1 IN N001 100K
C2 OUT 0 10 Rser=3m
C1 N004 0 1n
Rload OUT 0 66
XU1 N001 N003 0 OUT N004 0 N002 IN 0 ADP2360-3.3 ;pnba EN)PG)Ith)FB)SS)PGND)SW)Vin)AGND
V1 IN 0 5
R2 IN N003 22Meg
.tran 3m startup
.lib ADP2360-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 680
WIRE -144 -48 -256 -48
WIRE 0 -48 -144 -48
WIRE 224 -48 0 -48
WIRE -256 -32 -256 -48
WIRE 0 -32 0 -48
WIRE -144 16 -144 -48
WIRE 224 32 224 -48
WIRE -256 64 -256 48
WIRE 0 64 0 48
WIRE 96 64 0 64
WIRE 384 64 352 64
WIRE 512 64 464 64
WIRE 560 64 512 64
WIRE 704 64 560 64
WIRE 560 80 560 64
WIRE 704 80 704 64
WIRE -144 128 -144 96
WIRE 96 128 -144 128
WIRE 560 176 560 144
WIRE 704 176 704 160
WIRE 96 192 80 192
WIRE 512 192 512 64
WIRE 512 192 352 192
WIRE 16 256 0 256
WIRE 96 256 80 256
WIRE 176 320 176 304
WIRE 272 320 272 304
SYMBOL cap 544 80 R0
WINDOW 39 24 61 Left 2
WINDOW 3 45 33 Left 2
SYMATTR SpiceLine Rser=3m
SYMATTR Value 10
SYMATTR InstName C2
SYMBOL voltage -256 -48 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADP2360-3.3 224 160 R0
SYMATTR InstName U1
SYMBOL res 688 64 R0
SYMATTR InstName Rload
SYMATTR Value 66
SYMBOL res -16 -48 R0
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL ind 368 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rpar=50k
SYMBOL cap 80 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL res -160 0 R0
SYMATTR InstName R2
SYMATTR Value 22Meg
FLAG 0 256 0
FLAG -256 64 0
FLAG 176 320 0
FLAG 272 320 0
FLAG 560 176 0
FLAG 704 176 0
FLAG 704 64 OUT
FLAG 80 192 0
FLAG -256 -48 IN
TEXT 400 280 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\89245e335ab4_P-_E_Mosfet.asc
* Generated by LTspice 26.0.1 for Windows.
* D
* S
* G
* Enhancement Mode P Channel MOSFET
V2 N001 0 -1.8
V1 N002 0 -1.8
M2 N001 N002 0 0 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V1 0 -1.8 0.1 V2 0 -1.8 0.2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 528 128 336 128
WIRE 288 208 128 208
WIRE 128 240 128 208
WIRE 128 336 128 320
WIRE 336 336 336 224
WIRE 336 336 128 336
WIRE 528 336 528 208
WIRE 528 336 336 336
WIRE 336 368 336 336
SYMBOL voltage 128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value -1.8
SYMBOL pmos 288 128 R0
SYMATTR InstName M2
SYMBOL voltage 528 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -1.8
FLAG 336 368 0
TEXT 96 392 Left 2 !.dc V1 0 -1.8 0.1 V2 0 -1.8 0.2
TEXT 416 128 Bottom 2 ;D
TEXT 424 336 Top 2 ;S
TEXT 200 208 Bottom 2 ;G
TEXT 88 80 Left 2 ;Enhancement Mode P Channel MOSFET
* Z:\home\khalils\Downloads\files\data\raw_asc\4f6013a0a31d_PN_diode_Reversebias.asc
* Generated by LTspice 26.0.1 for Windows.
* PN Junction Reverse Bias
D1 X Y 1N4007
V1 X 0 5V
R1 Y 0 1K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -5 0 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 144 32 144
WIRE 192 144 160 144
WIRE 288 144 256 144
WIRE 400 144 288 144
WIRE 400 160 400 144
WIRE 32 176 32 144
WIRE 32 320 32 256
WIRE 224 320 32 320
WIRE 400 320 400 240
WIRE 400 320 224 320
WIRE 224 336 224 320
SYMBOL diode 192 160 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4007
SYMBOL voltage 32 160 R0
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL res 384 144 R0
SYMATTR InstName R1
SYMATTR Value 1K
FLAG 224 336 0
FLAG 160 144 X
FLAG 288 144 Y
TEXT -8 96 Left 2 !.dc V1 -5 0 0.01
TEXT -48 24 Left 4 ;PN Junction Reverse Bias
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2907.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2907.asy)
V1 N002 0 PWL(0 0 1m 2.5)
V2 N001 0 PWL(0 0 1m .8)
R3 N003 0 100K
V3 N006 0 5
R1 N006 N005 100K
R2 N001 N003 49.9K
C1 N004 0 .022
XU1 0 N005 N004 N002 N002 N003 0 0 LTC2907 ;pnba GND)_RST)TMR)Vcc)V1)Vadj)S1)TOL
C2 N003 0 .1
.tran 400m
.lib LTC2907.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 940 680
WIRE 512 64 -368 64
WIRE -368 80 -368 64
WIRE 512 80 512 64
WIRE -368 176 -368 160
WIRE 16 176 -224 176
WIRE 32 176 16 176
WIRE 432 176 288 176
WIRE 512 176 512 160
WIRE 512 176 432 176
WIRE -224 192 -224 176
WIRE 432 192 432 176
WIRE 512 192 512 176
WIRE 16 240 16 176
WIRE 32 240 16 240
WIRE 352 240 288 240
WIRE 432 272 432 256
WIRE -224 288 -224 272
WIRE 512 288 512 272
WIRE 32 304 16 304
WIRE 352 304 288 304
WIRE 352 320 352 304
WIRE 32 368 16 368
WIRE 384 368 288 368
WIRE 544 368 464 368
WIRE 544 384 544 368
WIRE 544 480 544 464
SYMBOL cap 416 192 R0
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL voltage -224 176 R0
WINDOW 0 23 24 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m 2.5)
SYMBOL voltage -368 64 R0
WINDOW 3 27 89 Left 2
SYMATTR Value PWL(0 0 1m .8)
SYMATTR InstName V2
SYMBOL cap 336 240 R0
SYMATTR InstName C1
SYMATTR Value .022
SYMBOL res 480 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL LTC2907 160 272 R0
SYMATTR InstName U1
SYMBOL res 496 176 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL voltage 544 368 R0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL res 496 64 R0
SYMATTR InstName R2
SYMATTR Value 49.9K
FLAG -224 288 0
FLAG -368 176 0
FLAG 352 320 0
FLAG 544 480 0
FLAG 16 368 0
FLAG 16 304 0
FLAG 512 288 0
FLAG 432 272 0
TEXT 352 448 Left 2 !.tran 400m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1109A-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1109A-5.asy)
Rload OUT 0 25
C1 OUT 0 22 Rser=0.02
XU1 IN MP_01 N001 0 MP_02 MP_03 N002 OUT LT1109A top=250K bot=83K ;pnba Vin))SW)GND)))_SDN)Sense
V1 IN 0 3 Rser=0.1
L1 IN N001 33 Rser=0.02 Rpar=5000
D1 N001 OUT MBRS140
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LT1109A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2376 1416
WIRE 1520 944 1296 944
WIRE 1584 944 1520 944
WIRE 1696 944 1664 944
WIRE 1744 944 1696 944
WIRE 1856 944 1808 944
WIRE 1920 944 1856 944
WIRE 1296 960 1296 944
WIRE 1920 960 1920 944
WIRE 1520 1008 1520 944
WIRE 1296 1056 1296 1040
WIRE 1920 1056 1920 1040
WIRE 1696 1072 1696 944
WIRE 1696 1072 1648 1072
WIRE 1392 1104 1376 1104
WIRE 1856 1136 1856 944
WIRE 1856 1136 1648 1136
WIRE 1856 1152 1856 1136
WIRE 1856 1232 1856 1216
WIRE 1520 1248 1520 1200
SYMBOL POLCAP 1840 1152 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMATTR SpiceLine Rser=0.02
SYMBOL PowerProducts\\LT1109A-5 1520 1088 R0
SYMATTR InstName U1
SYMBOL res 1904 944 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL IND 1568 960 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL schottky 1744 960 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL VOLTAGE 1296 944 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMATTR SpiceLine Rser=0.1
FLAG 1920 944 OUT
FLAG 1856 1232 0
FLAG 1920 1056 0
FLAG 1296 1056 0
FLAG 1520 1248 0
FLAG 1296 944 IN
TEXT 1624 1264 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\9287eb02b211_diode2.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N002 0 1N4148
V1 N001 0 3
R1 N002 N001 1000
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -0.5 0.7 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 144 -16 64 -16
WIRE 288 -16 224 -16
WIRE 64 16 64 -16
WIRE 288 32 288 -16
WIRE 64 128 64 96
WIRE 288 128 288 96
WIRE 288 128 64 128
WIRE 288 176 288 128
SYMBOL voltage 64 0 R0
WINDOW 123 15 127 Left 2
WINDOW 39 24 124 Left 2
WINDOW 3 15 99 Left 2
SYMATTR Value 3
SYMATTR InstName V1
SYMBOL diode 272 32 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 240 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
FLAG 288 176 0
TEXT 64 152 Left 2 !.dc V1 -0.5 0.7 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\2eb9a2fc9221_hw7_prob4.asc
* Generated by LTspice 26.0.1 for Windows.
* Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
R1 N001 0 15
C1 vout 0 1.6667m
R2 vout N001 1
I1 0 N001 0 AC 5 30
.options plotwinsize=0 numdgt=15 measdgt=15
.ac list {50/(2*pi)}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 692
WIRE -176 -80 -384 -80
WIRE -112 -80 -176 -80
WIRE 0 -80 -32 -80
WIRE 16 -80 0 -80
WIRE -384 -32 -384 -80
WIRE -176 -32 -176 -80
WIRE 16 -16 16 -80
WIRE -384 128 -384 48
WIRE -208 128 -384 128
WIRE -176 128 -176 48
WIRE -176 128 -208 128
WIRE 16 128 16 48
WIRE 16 128 -176 128
WIRE -208 160 -208 128
SYMBOL current -176 48 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 52 Left 2
SYMATTR InstName I1
SYMATTR Value 0
SYMATTR Value2 AC 5 30
SYMBOL cap 0 -16 R0
SYMATTR InstName C1
SYMATTR Value 1.6667m
SYMBOL res -16 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL res -400 -48 R0
SYMATTR InstName R1
SYMATTR Value 15
FLAG -208 160 0
FLAG 0 -80 vout
TEXT -432 304 Left 2 !.options plotwinsize=0 numdgt=15 measdgt=15\n.ac list {50/(2*pi)}
TEXT -544 -648 Left 2 ;Phasor-domain testbench schematic for checking your work on Problem 4:\n \nuse the .ac results report to verify your phasor-domain work; the results\nlisted in the report are given in polar format, i.e., magnitude and phase\n \nV(vout) in the report is the phasor voltage Vout (Vo in the assignment)\n \nthere is nothing to plot for this verification testbench\n \nthe capacitor value is chosen to give the impedance listed in Problem 4\nat an angular frequency of 50 rps; note that there is nothing particularly\nspecial about 50 rps, but I needed to choose something for ac simulation\npurposes; 50 rps angular frequency of operation for this testbench is \n50/(2*pi) ~ 7.9578 Hz
* Z:\home\khalils\Downloads\files\data\raw_asc\12697a5f4c18_Schematic.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N004 0 PULSE(0 10 0 0 0 5.8u 10u)
V1 N001 0 12
R1 N003 0 5
L1 N002 0 68
M1 N001 N004 N002 N002 IRF510
C1 N003 0 100
D1 N003 N002 MBRS340
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 112 80 48 80
WIRE 256 80 208 80
WIRE 272 80 256 80
WIRE 400 80 336 80
WIRE 528 80 400 80
WIRE 400 96 400 80
WIRE 528 96 528 80
WIRE 48 128 48 80
WIRE 256 128 256 80
WIRE 192 160 192 128
WIRE 48 272 48 208
WIRE 192 272 192 240
WIRE 192 272 48 272
WIRE 256 272 256 208
WIRE 256 272 192 272
WIRE 320 272 256 272
WIRE 400 272 400 160
WIRE 400 272 320 272
WIRE 528 272 528 176
WIRE 528 272 400 272
WIRE 320 304 320 272
SYMBOL nmos 112 128 R270
WINDOW 0 17 36 Left 2
SYMATTR InstName M1
SYMATTR Value IRF510
SYMBOL voltage 48 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 384 96 R0
SYMATTR InstName C1
SYMATTR Value 100µ
SYMBOL res 512 80 R0
SYMATTR InstName R1
SYMATTR Value 5
SYMBOL voltage 192 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0 0 0 5.8u 10u)
SYMBOL ind 240 112 R0
SYMATTR InstName L1
SYMATTR Value 68µ
SYMBOL diode 336 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
FLAG 320 304 0
TEXT 208 -208 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1587-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 22
Rload OUT 0 500
XU1 0 OUT IN LT1587-3.3 ;pnba GND)OUT)IN
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1587-3.3.asy)
.lib LT1584.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 176 -176 176
WIRE 368 176 288 176
WIRE 464 176 368 176
WIRE -176 192 -176 176
WIRE 368 192 368 176
WIRE 464 192 464 176
WIRE -176 288 -176 272
WIRE 368 288 368 256
WIRE 464 288 464 272
WIRE 160 304 160 272
FLAG -176 288 0
FLAG 368 288 0
FLAG 464 288 0
FLAG 160 304 0
FLAG 464 176 OUT
FLAG -176 176 IN
SYMBOL voltage -176 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 352 192 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 448 176 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL PowerProducts\\LT1587-3.3 160 176 R0
SYMATTR InstName U1
TEXT 280 336 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\1f8c71cb2d74_Zener_diode_voltage_regulator_-emitter_follower-.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N003 10k
Q1 N002 N003 N004 0 BC547B
R3 N004 0 1k
V1 N001 0 30
R2 N001 N002 10k
D1 0 N003 UMZ5_1N
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 100
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 128 112 96
WIRE 320 128 112 128
WIRE 112 144 112 128
WIRE 320 224 320 208
WIRE 112 272 112 224
WIRE 256 272 112 272
WIRE 112 336 112 272
WIRE 320 368 320 320
WIRE 112 448 112 400
WIRE 320 480 320 448
SYMBOL npn 256 224 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL voltage 112 112 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL res 96 128 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL zener 128 400 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value UMZ5_1N
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 304 352 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 304 112 R0
SYMATTR InstName R2
SYMATTR Value 10k
FLAG 112 448 0
FLAG 320 480 0
FLAG 112 16 0
TEXT 24 504 Left 2 !.tran 100
* Z:\home\khalils\Downloads\files\data\raw_asc\0903ed257978_7805Jerarq.asc
* Generated by LTspice 26.0.1 for Windows.
Rcon In 0 1e6
Vc 4 Out 0
F2 In Aj Vc 4m
B1 4 Aj V= Table (V(In,Aj), 0,0, 1,0, 7,5, 35,5, 36,0)
F1 In 0 Vc 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -144 240 -144 208
WIRE -144 352 -144 320
WIRE -16 208 -144 208
WIRE -16 208 -16 176
WIRE -16 256 -16 208
WIRE -16 352 -144 352
WIRE -16 352 -16 336
WIRE -16 368 -16 352
WIRE 80 208 -16 208
WIRE 80 256 80 208
WIRE 80 352 80 336
WIRE 192 240 192 224
WIRE 192 256 192 240
WIRE 192 352 80 352
WIRE 192 352 192 336
WIRE 224 352 192 352
WIRE 256 224 192 224
WIRE 352 224 336 224
SYMBOL voltage 240 224 R270
WINDOW 0 -15 57 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName Vc
SYMATTR Value 0
SYMBOL f 80 256 R0
WINDOW 3 15 85 Left 0
SYMATTR Value Vc 4m
SYMATTR InstName F2
SYMBOL res -160 224 R0
SYMATTR InstName Rcon
SYMATTR Value 1e6
SYMBOL f -16 256 R0
SYMATTR InstName F1
SYMATTR Value Vc 1
SYMBOL bv 192 240 R0
WINDOW 3 -332 162 Left 0
SYMATTR Value V= Table (V(In,Aj), 0,0, 1,0, 7,5, 35,5, 36,0)
SYMATTR InstName B1
FLAG -16 368 0
FLAG -16 176 In
FLAG 192 240 4
FLAG 224 352 Aj
FLAG 352 224 Out
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1411.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1411.asy)
V3 v+ 0 15
R1 vD 0 301
C1 vD 0 36p
V4 v- 0 -15
XU1 vIN vS vD v- v+ 0 ADG1411 ;pnba IN)S)D)Vss)Vdd)GND
V1 vS 0 SINE(0 5 20)
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
.tran 1
.lib ADG1411.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 112 240 112
WIRE 240 144 240 112
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 368 224 336 224
WIRE 416 224 368 224
WIRE 528 224 416 224
WIRE 416 256 416 224
WIRE 528 256 528 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -272 304 -288 304
WIRE -176 304 -192 304
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 416 352 416 336
WIRE 528 352 528 320
WIRE 304 416 304 400
WIRE 176 432 176 400
WIRE 192 432 176 432
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 20)
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL ADG1411 240 272 R0
SYMATTR InstName U1
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL cap 512 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL res 400 240 R0
SYMATTR InstName R1
SYMATTR Value 301
FLAG -112 224 0
FLAG 48 464 0
FLAG 416 352 0
FLAG 304 416 0
FLAG 368 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 528 352 0
FLAG -272 304 v+
FLAG 256 112 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -176 304 v-
FLAG 192 432 v-
TEXT 80 528 Left 2 !.tran 1
TEXT -360 -40 Left 2 ;Note:\nSwitch shown for a logic 0 input\nPin capacitance and Qinj not included\nParameter performance modeled at 15V supply\nOny one channel is modeled