* Z:\home\khalils\Downloads\files\data\raw_asc\LT4322.asc
* Generated by LTspice 26.0.1 for Windows.
C1 IN N005 22
V1 IN 0 SINE(0 85 60) Rser=10m
C2 OUT 0 220 Rser=10m
S1 0 OUT N001 0 SCSW
V2 N001 0 PWL(0 0 35m 0 +1m 1)
C3 N002 IN 10n
M1 OUT N003 N004 N004 DN2530
MQ1 OUT N002 IN IN BSC320N20NS3
R1 N003 N005 100
XU1 N002 IN IN N005 N004 N004 LT4322 ;pnba GATE)VSSA)ANODE)VDDA)CATHODE)VDDC
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m startup
.model SCSW SW(Ron=160 Roff=70k Vt=.5 Vh=-.4)
.model DN2530 VDMOS (Rg=1 Vto=-1.5 Kp=0.82 Lambda=8m Rs=0.3
+Ksubthres=0.11 Mtriode=0.8 Rd=5 Bex=-1.9 Vtotc=-0.8m Tksubthres1=4m
+Trs1=3m Trd1=3m Cgdmax=170p Cgdmin=15p a=0.7 Cgs=100p Cjo=130p
+m=0.75 VJ=0.75 IS=1n N=1.6 Eg=1.2 Rb=5 Vds=300 Ron=12)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT4322.asy)
.lib LT4322.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2192 680
WIRE -208 -192 -224 -192
WIRE 0 -192 -208 -192
WIRE 112 -192 0 -192
WIRE 272 -192 112 -192
WIRE 752 -192 368 -192
WIRE 880 -192 752 -192
WIRE 896 -192 880 -192
WIRE 896 -176 896 -192
WIRE 1056 -160 944 -160
WIRE -224 -144 -224 -192
WIRE 416 -144 368 -192
WIRE 560 -144 416 -144
WIRE 752 -144 752 -192
WIRE 1056 -144 1056 -160
WIRE 192 -128 272 -192
WIRE 560 -128 560 -144
WIRE 0 -112 0 -192
WIRE 208 -112 272 -192
WIRE 896 -80 896 -96
WIRE 208 -48 208 -112
WIRE 288 -48 288 -144
WIRE 288 -48 272 -48
WIRE 624 -48 608 -48
WIRE 1056 -48 1056 -64
WIRE 752 -32 752 -80
WIRE -224 -16 -224 -64
WIRE 560 -16 560 -32
WIRE 560 -16 432 -16
WIRE 624 -16 624 -48
WIRE 112 32 112 -192
WIRE 192 32 192 -128
WIRE 288 32 288 -48
WIRE 432 32 432 -16
WIRE 0 144 0 -48
WIRE 64 144 0 144
WIRE 560 144 560 -16
WIRE 560 144 512 144
WIRE 0 288 0 144
WIRE 624 288 624 64
WIRE 624 288 0 288
FLAG 752 -32 0
FLAG -224 -16 0
FLAG -208 -192 IN
FLAG 880 -192 OUT
FLAG 896 -80 0
FLAG 944 -112 0
FLAG 1056 -48 0
SYMBOL cap -16 -112 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL voltage -224 -160 R0
WINDOW 123 28 120 Left 2
SYMATTR Value2 Rser=10m
SYMATTR InstName V1
SYMATTR Value SINE(0 85 60)
SYMBOL cap 736 -144 R0
WINDOW 123 24 80 Left 2
SYMATTR Value2 Rser=10m
SYMATTR InstName C2
SYMATTR Value 220
SYMBOL sw 896 -80 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SCSW
SYMBOL voltage 1056 -160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 35m 0 +1m 1)
SYMBOL cap 272 -64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL nmos 608 -128 M0
WINDOW 0 92 34 Right 2
WINDOW 3 -5 36 Right 2
SYMATTR InstName M1
SYMATTR Value DN2530
SYMBOL nmos 368 -144 M270
WINDOW 0 82 58 VLeft 2
WINDOW 3 -16 78 VLeft 2
SYMATTR InstName Q1
SYMATTR Value BSC320N20NS3
SYMBOL res 608 -32 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL LT4322 288 144 R0
SYMATTR InstName U1
TEXT 688 256 Left 2 !.tran 100m startup
TEXT 688 88 Left 2 !.model SCSW SW(Ron=160 Roff=70k Vt=.5 Vh=-.4)\n.model DN2530 VDMOS (Rg=1 Vto=-1.5 Kp=0.82 Lambda=8m Rs=0.3 \n+Ksubthres=0.11 Mtriode=0.8 Rd=5 Bex=-1.9 Vtotc=-0.8m Tksubthres1=4m \n+Trs1=3m Trd1=3m Cgdmax=170p Cgdmin=15p a=0.7 Cgs=100p Cjo=130p \n+m=0.75 VJ=0.75 IS=1n N=1.6 Eg=1.2 Rb=5 Vds=300 Ron=12)