* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2956-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Processor
* Logic representing Processor\nterminates EN early at times\nbefore 2.5 secs.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC2956-2.asy)
A1 N002 0 0 0 0 0 N010 0 SCHMITT Vt=3 Vh=3m Trise=10m Tfall=50n Vhigh=3
A2 0 N010 0 N011 0 0 N009 0 XOR Trise=100n Vhigh=3
A3 0 N010 0 StopEarly 0 0 N011 0 AND Trise=5m Tfall=50n Vhigh=3
R5 N001 N004 10K
XU1 N005 N014 N015 N013 N001 0 N008 N003 N004 N007 N009 N006 LTC2956-2 ;pnba OnMax)Long)Range)Period)Vin)Gnd)_PB)_EN)_PBout)_OffAlert)_Sleep)_OnAlert
R1 N013 0 100K
R3 N015 0 9.76K
C1 N005 0 10n
R4 N014 0 35.7K
R2 N014 N015 100K
MQ1 N002 N003 N001 N001 AO6407
R7 N001 N007 10K
V3 StopEarly 0 PWL(0 3 2.5 3 +100n 0)
V1 N001 0 PWL(0 0 10u 3.3)
S1 N008 0 N012 0 SPB
V2 N012 0 PWL(0 0 1 0 +100n 1 +100m 1 +100n 0 4 0 +100n 1 5.5 1 +100n 0)
R6 N001 N006 10K
R8 N002 0 1K
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 7
.model SPB SW(Ron=100 Roff=1G Vt=.5 Vh=-.3)
.lib LTC2956-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1892 948
WIRE 80 -96 -288 -96
WIRE 544 -96 80 -96
WIRE 560 -96 544 -96
WIRE 1536 -96 656 -96
WIRE 1664 -96 1536 -96
WIRE -288 -80 -288 -96
WIRE 1664 -80 1664 -96
WIRE 576 -16 576 -48
WIRE 576 -16 304 -16
WIRE 80 0 80 -96
WIRE 304 0 304 -16
WIRE -288 16 -288 0
WIRE 1664 16 1664 0
WIRE 432 64 416 64
WIRE 544 64 544 -96
WIRE 544 64 512 64
WIRE -112 128 -128 128
WIRE -32 128 -48 128
WIRE 432 144 416 144
WIRE 544 144 544 64
WIRE 544 144 512 144
WIRE 432 224 416 224
WIRE 544 224 544 144
WIRE 544 224 512 224
WIRE -32 272 -128 272
WIRE -128 288 -128 272
WIRE -176 304 -192 304
WIRE 928 304 416 304
WIRE 1136 304 992 304
WIRE 1408 304 1136 304
WIRE 1536 304 1536 -96
WIRE 1536 304 1472 304
WIRE 1008 336 992 336
WIRE 1472 336 1472 320
WIRE -176 352 -224 352
WIRE -128 384 -128 368
WIRE 960 384 960 352
WIRE 48 400 48 384
WIRE 336 400 336 384
WIRE 128 448 128 384
WIRE 144 448 128 448
WIRE 240 448 240 384
WIRE 240 448 224 448
WIRE 1008 464 1008 336
WIRE 1056 464 1008 464
WIRE 1136 464 1136 304
WIRE 1136 464 1120 464
WIRE 128 480 128 448
WIRE 240 480 240 448
WIRE 336 496 336 480
WIRE 1264 496 1120 496
WIRE 1264 512 1264 496
WIRE -224 560 -224 352
WIRE 1104 560 1104 512
WIRE 128 576 128 560
WIRE 240 576 240 560
WIRE -224 672 -224 640
RECTANGLE Normal 1760 688 720 240 2
SYMBOL res 112 464 R0
SYMATTR InstName R4
SYMATTR Value 35.7K
SYMBOL res 128 464 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL sw -128 272 R0
SYMATTR InstName S1
SYMATTR Value SPB
SYMBOL res 224 464 R0
SYMATTR InstName R3
SYMATTR Value 9.76K
SYMBOL res 528 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL Digital\\schmtbuf 1472 240 M0
WINDOW 3 29 95 Left 2
WINDOW 123 29 128 Left 2
WINDOW 40 18 153 Left 2
SYMATTR Value Vt=3 Vh=3m
SYMATTR Value2 Trise=10m Tfall=50n
SYMATTR SpiceLine2 Vhigh=3
SYMATTR InstName A1
SYMBOL voltage 1264 496 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 3 2.5 3 +100n 0)
SYMBOL Digital\\xor 944 256 M0
WINDOW 3 48 108 Left 2
WINDOW 40 30 141 Left 2
WINDOW 123 11 107 Left 2
SYMATTR SpiceLine2 Vhigh=3
SYMATTR Value2 Trise=100n
SYMATTR InstName A2
SYMBOL voltage -288 -96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 10u 3.3)
SYMBOL voltage -224 544 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 1 0 +100n 1 +100m 1 +100n 0 4 0 +100n 1 5.5 1 +100n 0)
SYMBOL pmos 656 -48 M270
WINDOW 0 27 -6 VLeft 2
WINDOW 3 -13 0 VLeft 2
SYMATTR InstName Q1
SYMATTR Value AO6407
SYMBOL res 320 384 R0
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL LTC2956-2 192 192 R0
SYMATTR InstName U1
SYMBOL res 528 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10K
SYMBOL cap -48 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 1648 -96 R0
SYMATTR InstName R8
SYMATTR Value 1K
SYMBOL res 528 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 10K
SYMBOL Digital\\and 1088 416 M0
WINDOW 3 80 91 Left 2
WINDOW 40 15 134 Left 2
WINDOW 123 9 109 Left 2
SYMATTR SpiceLine2 Vhigh=3
SYMATTR Value2 Trise=5m Tfall=50n
SYMATTR InstName A3
FLAG -128 128 0
FLAG 48 400 0
FLAG 336 496 0
FLAG 128 576 0
FLAG 240 576 0
FLAG -288 16 0
FLAG -224 672 0
FLAG 1472 336 0
FLAG 1104 560 0
FLAG 1264 592 0
FLAG 1264 496 StopEarly
FLAG 960 384 0
FLAG -128 384 0
FLAG -192 304 0
FLAG 1664 16 0
TEXT 1160 704 Left 2 !.tran 7\n.model SPB SW(Ron=100 Roff=1G Vt=.5 Vh=-.3)
TEXT 1080 224 Left 2 ;Processor
TEXT 1352 432 Left 2 ;Logic representing Processor\nterminates EN early at times\nbefore 2.5 secs.