Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6991.asc
* Generated by LTspice 26.0.1 for Windows.
* One Hour Clock Period\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6991.asy)
R1 N001 N003 887K
V1 N001 0 5
R2 N003 0 1Meg
XU1 N001 0 N002 N003 N001 OUT LTC6991 ;pnba RST)GND)SET)DIV)V+)OUT
R3 N002 0 84.5K
.tran 15000 startup
.lib LTC6991.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 512 48 64 48
WIRE 64 96 64 48
WIRE 112 96 64 96
WIRE 352 96 336 96
WIRE 112 176 96 176
WIRE 384 176 336 176
WIRE 512 176 512 48
WIRE 512 176 384 176
WIRE 384 192 384 176
WIRE 512 192 512 176
WIRE 16 256 0 256
WIRE 112 256 96 256
WIRE 352 256 336 256
WIRE 352 288 352 256
WIRE 384 288 384 272
WIRE 384 288 352 288
WIRE 512 288 512 272
WIRE 384 304 384 288
WIRE 384 400 384 384
SYMBOL SpecialFunctions\\LTC6991 224 176 R0
SYMATTR InstName U1
SYMBOL res 112 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 84.5K
SYMBOL res 368 288 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL res 368 176 R0
SYMATTR InstName R1
SYMATTR Value 887K
SYMBOL voltage 512 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
FLAG 96 176 0
FLAG 352 96 OUT
FLAG 512 288 0
FLAG 384 400 0
FLAG 0 256 0
TEXT 232 40 Bottom 2 ;One Hour Clock Period\nStartup Modeled
TEXT 520 376 Left 2 !.tran 15000 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-4.5.asy)
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-4.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
V1 IN 0 3.3
L1 N001 N002 1.5 Rser=80m
Rload OUT 0 50
C1 OUT 0 10
.tran 400u startup
.lib ADP2504-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ADP2504-4.5 176 176 R0
SYMATTR InstName U1
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG 480 224 OUT
FLAG -64 64 IN
TEXT 432 376 Left 2 !.tran 400u startup
TEXT 160 -8 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\068bf9d57e20_ADTL084.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
R2 OUT N001 10K
V2 -V 0 -15
Rload OUT 0 10K
XU1 IN N001 +V -V OUT ADTL084 ;pnba In+)In-)V+)V-)OUT
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADTL084.asy)
.lib ADTL084.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 720 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 720 -1088 720 -1104
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 720 -992 720 -1008
WIRE 432 -976 432 -992
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 720 -992 0
FLAG 256 -1056 0
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 704 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL opamps\\ADTL084 576 -1168 R0
SYMATTR InstName U1
TEXT 784 -896 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM7223B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM7223B.asy)
V6 VDDB 0 12
C2 VOB 0 2n
V1 inputA 0 PULSE(0 5 0 2n 2n 5u 10u)
V2 inputB 0 PULSE(5 0 0 2n 2n 5u 10u)
V5 VDDA 0 12
V3 VDD1 0 5
XU1 0 inputA inputB 0 VDD1 0 VOB VDDB 0 VOA VDDA ADuM7223B ;pnba GND1)VIA)VIB)DISABLE)VDD1)GNDB)VOB)VDDB)GNDA)VOA)VDDA
C1 VOA 0 2n
.tran 50u
.lib ADuM7223B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1228 692
WIRE 416 16 368 16
WIRE 688 16 416 16
WIRE 64 32 -64 32
WIRE -64 48 -64 32
WIRE 416 80 368 80
WIRE 592 80 416 80
WIRE 592 96 592 80
WIRE 16 112 -448 112
WIRE 64 112 16 112
WIRE 688 128 688 96
WIRE 432 144 368 144
WIRE -448 160 -448 112
WIRE 592 176 592 160
WIRE 16 192 -288 192
WIRE 64 192 16 192
WIRE 416 224 368 224
WIRE 688 224 416 224
WIRE -448 256 -448 240
WIRE 64 272 -80 272
WIRE 416 288 368 288
WIRE 592 288 416 288
WIRE -288 304 -288 272
WIRE -80 304 -80 272
WIRE 592 304 592 288
WIRE 16 352 -80 352
WIRE 64 352 16 352
WIRE 432 352 368 352
WIRE 432 368 432 352
WIRE -80 384 -80 352
WIRE 592 384 592 368
WIRE -80 480 -80 464
SYMBOL voltage 688 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 12
SYMBOL ADuM7223B 224 112 R0
SYMATTR InstName U1
SYMBOL voltage -288 176 R0
WINDOW 0 20 108 Left 2
WINDOW 3 39 40 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(5 0 0 2n 2n 5u 10u)
SYMBOL cap 576 304 R0
SYMATTR InstName C2
SYMATTR Value 2n
SYMBOL voltage -448 144 R0
WINDOW 0 30 80 Left 2
WINDOW 3 18 -5 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 2n 2n 5u 10u)
SYMBOL voltage 688 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V5
SYMATTR Value 12
SYMBOL voltage -80 368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 32 90 Left 2
SYMATTR Value 5
SYMATTR InstName V3
SYMBOL cap 576 96 R0
SYMATTR InstName C1
SYMATTR Value 2n
FLAG -80 480 0
FLAG -448 256 0
FLAG -288 304 0
FLAG 592 176 0
FLAG 592 384 0
FLAG 416 288 VOB
FLAG 416 80 VOA
FLAG 432 368 0
FLAG 432 144 0
FLAG 16 192 inputB
FLAG 688 304 0
FLAG 688 128 0
FLAG 16 352 VDD1
FLAG -64 48 0
FLAG 416 224 VDDB
FLAG 16 112 inputA
FLAG 416 16 VDDA
FLAG -80 304 0
TEXT 64 440 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6404-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6404-2.asy)
V1 N004 0 SINE(0 10m 10Meg)
R4 N008 0 100
XU1 N008 N006 N003 N009 N002 0 N003 N001 N005 N007 LTC6404-2 ;pnba IN-)Vocm)V+)OUT+)OUT-)V-)_SHDN)IN+)OUTF-)OUTF+
R1 N002 N001 200
V2 N003 0 3.3
R2 N009 N008 200
R3 N001 N004 100
C1 N006 0 .1
.tran 1u
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 732
WIRE 208 -48 32 -48
WIRE 416 -48 288 -48
WIRE 192 32 128 32
WIRE 528 32 192 32
WIRE 128 48 128 32
WIRE 192 48 192 32
WIRE 528 48 528 32
WIRE 416 96 416 -48
WIRE 416 96 384 96
WIRE -320 144 -368 144
WIRE -144 144 -240 144
WIRE 32 144 32 -48
WIRE 32 144 -64 144
WIRE 80 144 32 144
WIRE 528 144 528 128
WIRE 416 160 384 160
WIRE -16 192 -32 192
WIRE 80 192 48 192
WIRE 416 224 384 224
WIRE -144 240 -192 240
WIRE 32 240 -64 240
WIRE 80 240 32 240
WIRE 416 288 384 288
WIRE 192 368 192 336
WIRE 32 432 32 240
WIRE 208 432 32 432
WIRE 416 432 416 288
WIRE 416 432 288 432
SYMBOL voltage -224 144 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 32 56 VTop 2
WINDOW 39 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value SINE(0 10m 10Meg)
SYMBOL res 304 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200
SYMBOL voltage 528 32 R0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL opamps\\LTC6404-2 208 192 R0
SYMATTR InstName U1
SYMBOL cap 48 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL res 304 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL res -48 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 100
SYMBOL res -48 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100
FLAG -32 192 0
FLAG -368 144 0
FLAG 528 144 0
FLAG -192 240 0
FLAG 192 368 0
TEXT 472 344 Left 2 !.tran 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1964-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1964-5.asy)
C1 OUT 0 1
XU1 0 IN N001 IN OUT LT1964-5 ;pnba GND)IN)BYP)_SHDN)OUT
Rload OUT 0 1K
V1 IN 0 PWL(0 0 1 -10)
.tran 1
.lib LT1964.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 400 48 320 48
WIRE 496 48 400 48
WIRE -208 64 -208 48
WIRE 400 64 400 48
WIRE 496 64 496 48
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 336 144 320 144
WIRE -208 160 -208 144
WIRE 400 160 400 128
WIRE 496 160 496 144
WIRE 176 240 176 208
SYMBOL cap 384 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 -10)
SYMBOL PowerProducts\\LT1964-5 176 96 R0
SYMATTR InstName U1
SYMBOL res 480 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
FLAG -208 160 0
FLAG 400 160 0
FLAG 496 160 0
FLAG 176 240 0
FLAG 496 48 OUT
FLAG -208 48 IN
TEXT 384 216 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\05b522f62527_TP1_3.asc
* Generated by LTspice 26.0.1 for Windows.
* .tran 0.004
XU1 Vin N001 Vcc Vss Vo1 LM324 ;pnba In+)In-)V+)V-)OUT
Vcc Vcc 0 10
R4 Vo2 N003 10k tol=1
R2 N003 N002 5k tol=1
R1 N001 N002 10k tol=1
Vin Vin 0 SINE(0 4 1k)
D1 N002 Vo1 1N4148
D2 Vo1 N001 1N4148
Vss 0 Vss 10
XU2 Vin N003 Vcc Vss Vo2 LM324 ;pnba In+)In-)V+)V-)OUT
R3 N001 0 10k tol=1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.include LM324.txt
.dc Vin -10 10 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 -128 -32 -128
WIRE 160 -128 96 -128
WIRE 240 -128 160 -128
WIRE 384 -128 320 -128
WIRE 448 -128 384 -128
WIRE 592 -128 528 -128
WIRE 160 -80 160 -128
WIRE -432 -64 -432 -128
WIRE -288 -64 -288 -128
WIRE 480 16 480 -32
WIRE -160 32 -192 32
WIRE -32 32 -32 -128
WIRE -32 32 -80 32
WIRE 32 32 -32 32
WIRE 160 32 160 -16
WIRE 160 32 96 32
WIRE 384 32 384 -128
WIRE 448 32 384 32
WIRE 592 48 592 -128
WIRE 592 48 512 48
WIRE 640 48 592 48
WIRE -432 64 -432 16
WIRE -432 64 -528 64
WIRE -192 64 -192 32
WIRE 448 64 384 64
WIRE -528 80 -528 64
WIRE -288 80 -288 16
WIRE -432 112 -432 64
WIRE 480 128 480 80
WIRE 64 176 64 128
WIRE -32 192 -32 32
WIRE 32 192 -32 192
WIRE 160 208 160 32
WIRE 160 208 96 208
WIRE -48 224 -80 224
WIRE 32 224 -48 224
WIRE -432 288 -432 192
WIRE 64 288 64 240
WIRE -48 368 -48 224
WIRE 384 368 384 64
WIRE 384 368 -48 368
IOPIN 160 208 Out
IOPIN 640 48 Out
SYMBOL OpAmps\\opamp2 64 144 R0
SYMATTR InstName U1
SYMATTR Value LM324
SYMBOL res 544 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMATTR SpiceLine tol=1
SYMBOL diode 144 -80 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 336 -144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 5k
SYMATTR SpiceLine tol=1
SYMBOL voltage -432 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vss
SYMATTR Value 10
SYMBOL res -64 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMATTR SpiceLine tol=1
SYMBOL diode 96 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL res 0 -112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMATTR SpiceLine tol=1
SYMBOL OpAmps\\opamp2 480 -16 R0
SYMATTR InstName U2
SYMATTR Value LM324
SYMBOL voltage -432 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcc
SYMATTR Value 10
SYMBOL voltage -288 -80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value SINE(0 4 1k)
FLAG -528 80 0
FLAG -432 -128 Vcc
FLAG -432 288 Vss
FLAG -288 -128 Vin
FLAG -288 80 0
FLAG 64 128 Vcc
FLAG 480 -32 Vcc
FLAG 64 288 Vss
FLAG 480 128 Vss
FLAG -80 224 Vin
FLAG -192 64 0
FLAG 160 208 Vo1
FLAG 640 48 Vo2
TEXT -536 408 Left 2 !.include LM324.txt
TEXT -528 376 Left 2 !.dc Vin -10 10 0.01
TEXT -528 344 Left 2 ;.tran 0.004
* Z:\home\khalils\Downloads\files\data\raw_asc\16bb4a8f70f2_3.asc
* Generated by LTspice 26.0.1 for Windows.
R_D N001 V_out 5K
V_in V_in 0 1.237
VDD N001 0 1.8
M1 V_out V_in 0 N002 NMOS l=0.18 w=20
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model nmos nmos(kp=100u lambda=0)
.dc V_in 0 1 0.0001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 988 680
WIRE 464 -128 160 -128
WIRE 160 -64 160 -128
WIRE 464 48 464 -128
WIRE 160 64 160 16
WIRE 288 64 160 64
WIRE 112 80 -48 80
WIRE 112 144 112 80
WIRE 160 144 160 112
WIRE -48 192 -48 80
WIRE -48 352 -48 272
WIRE 160 352 160 160
WIRE 160 352 -48 352
WIRE 464 352 464 128
WIRE 464 352 160 352
WIRE 160 384 160 352
FLAG 160 384 0
FLAG -48 80 V_in
IOPIN -48 80 In
FLAG 288 64 V_out
IOPIN 288 64 Out
SYMBOL res 144 -80 R0
SYMATTR InstName R_D
SYMATTR Value 5K
SYMBOL voltage -48 176 R0
WINDOW 0 46 16 Center 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V_in
SYMATTR Value 1.237
SYMBOL voltage 464 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.8
SYMBOL nmos4 112 64 R0
SYMATTR InstName M1
SYMATTR Value2 l=0.18 w=20
TEXT 416 448 Left 2 !.model nmos nmos(kp=100u lambda=0)
TEXT -160 472 Left 2 !.dc V_in 0 1 0.0001
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1317.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1317.asy)
C3 N003 0 3300p
Rload OUT 0 50
R2 N005 0 324K
V1 IN 0 1.5
D1 N001 OUT MBRS140
XU1 N004 N005 N002 0 N001 IN N006 N007 LT1317 ;pnba Vc)FB)_SHDN)GND)SW)Vin)LBI)LBO
R1 OUT N005 1Meg
C2 OUT 0 33 Rser=0.02
L1 IN N001 10 Rser=0.02 Rpar=5000
R3 N004 N003 33K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT1317.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1652 960
WIRE 704 448 432 448
WIRE 768 448 704 448
WIRE 896 448 848 448
WIRE 944 448 896 448
WIRE 1072 448 1008 448
WIRE 1184 448 1072 448
WIRE 1280 448 1184 448
WIRE 432 464 432 448
WIRE 1280 464 1280 448
WIRE 1184 480 1184 448
WIRE 704 512 704 448
WIRE 1072 512 1072 448
WIRE 432 560 432 544
WIRE 1184 560 1184 544
WIRE 1280 560 1280 544
WIRE 560 576 544 576
WIRE 896 576 896 448
WIRE 896 576 848 576
WIRE 464 656 416 656
WIRE 560 656 544 656
WIRE 1072 656 1072 592
WIRE 1072 656 848 656
WIRE 416 672 416 656
WIRE 1072 672 1072 656
WIRE 560 736 544 736
WIRE 864 736 848 736
WIRE 416 752 416 736
WIRE 1072 768 1072 752
WIRE 704 816 704 800
SYMBOL res 1264 448 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL RES 1056 496 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL POLCAP 1168 480 R0
SYMATTR InstName C2
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02
SYMBOL CAP 400 672 R0
SYMATTR InstName C3
SYMATTR Value 3300p
SYMBOL POWERPRODUCTS\\LT1317 704 656 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 432 448 R0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL RES 560 640 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 33K
SYMBOL SCHOTTKY 944 464 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL RES 1056 656 R0
SYMATTR InstName R2
SYMATTR Value 324K
SYMBOL IND 752 464 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 1184 560 0
FLAG 1072 768 0
FLAG 704 816 0
FLAG 432 560 0
FLAG 416 752 0
FLAG 1280 560 0
FLAG 1280 448 OUT
FLAG 432 448 IN
TEXT 1104 816 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\04a7602332df_pwm-tuning.asc
* Generated by LTspice 26.0.1 for Windows.
XM1 N001 N002 N006 BS250 ;pnba D)G)S
R4 N005 N004 10k
R1 N002 N006 1k
XM2 N001 N002 0 2N7000 ;pnba D)G)S
R3 out N003 10k
V1 N006 0 9V
V2 N004 0 PULSE(0 5 0 1n 1n {DutyCycle} 100u)
Q1 N002 N005 0 0 2N2222
C2 N003 0 470nF
C1 out 0 470nF
R2 N003 N001 10k
C3 0 N006 100n
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.4
.inc 2N7000.onsemi.lib
.inc BS250.philips.lib
.meas TRAN rippel PP V(out) FROM 180ms TO 230ms
.meas TRAN medel AVG V(out) FROM 180ms TO 230ms
.param ideal=4.5
.meas TRAN diff PARAM medel-ideal
.param DutyCycle=50u
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1088 680
WIRE 288 -128 192 -128
WIRE 144 -48 0 -48
WIRE 192 -32 192 -48
WIRE 192 -16 192 -32
WIRE 288 80 288 -128
WIRE 288 80 176 80
WIRE 304 80 288 80
WIRE 480 80 384 80
WIRE 544 80 480 80
WIRE 672 80 672 -32
WIRE 672 80 624 80
WIRE 480 96 480 80
WIRE 672 112 672 80
WIRE 0 160 0 -48
WIRE 0 160 -192 160
WIRE 128 160 0 160
WIRE 480 192 480 160
WIRE 672 192 672 176
WIRE -368 208 -416 208
WIRE -256 208 -288 208
WIRE 176 208 176 176
WIRE 208 208 176 208
WIRE 304 208 272 208
WIRE 304 240 304 208
WIRE -192 304 -192 256
WIRE 0 304 0 240
WIRE 80 304 0 304
WIRE 176 304 176 208
WIRE 176 304 80 304
WIRE 80 400 80 384
IOPIN 672 -32 Out
SYMBOL voltage 80 288 R0
WINDOW 0 44 55 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9V
SYMBOL res 640 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL cap 656 112 R0
SYMATTR InstName C1
SYMATTR Value 470nF
SYMBOL pmos 128 80 R0
SYMATTR InstName M1
SYMATTR Value BS250
SYMATTR Prefix X
SYMBOL res -16 144 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res -272 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL res 400 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL nmos 144 -128 R0
SYMATTR InstName M2
SYMATTR Value 2N7000
SYMATTR Prefix X
SYMBOL cap 464 96 R0
SYMATTR InstName C2
SYMATTR Value 470nF
SYMBOL voltage -416 192 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1n 1n {DutyCycle} 100u)
SYMBOL npn -256 160 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL cap 272 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 100n
FLAG -416 288 0
FLAG 672 192 0
FLAG -192 304 0
FLAG 80 400 0
FLAG 192 -16 0
FLAG 480 192 0
FLAG 672 -32 out
FLAG 304 240 0
TEXT -864 432 Left 2 !.tran 0.4
TEXT -512 -104 Left 2 !.inc 2N7000.onsemi.lib
TEXT -512 -64 Left 2 !.inc BS250.philips.lib
TEXT -464 -432 Left 2 !.meas TRAN rippel PP V(out) FROM 180ms TO 230ms\n.meas TRAN medel AVG V(out) FROM 180ms TO 230ms
TEXT -464 -376 Left 2 !.param ideal=4.5\n.meas TRAN diff PARAM medel-ideal
TEXT -464 -320 Left 2 !.param DutyCycle=50u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3630.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3630.asy)
R2 N002 0 15K
XU1 N001 MP_01 IN MP_02 N002 N003 0 0 OUT N003 NC_03 NC_04 LTC3630 ;pnba SW))Vin))Run)Vprg2)Vprg1)GND)FB)SS)Iset)FBO
L1 N001 OUT 47 Rser=50m
V1 IN 0 24
C1 OUT 0 100 x2 V=4 Irms=1.5 Rser=0.04 Lser=0 mfg="KEMET" pn="T520B107M004ASE040" type="Tantalum"
Rload OUT 0 6.6
R1 IN N002 200K
.tran 5m startup
.lib LTC3630.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 32 -112 32
WIRE 96 32 -16 32
WIRE 416 32 384 32
WIRE 528 32 496 32
WIRE 576 32 528 32
WIRE 688 32 576 32
WIRE -112 48 -112 32
WIRE 576 48 576 32
WIRE 688 48 688 32
WIRE -16 128 -16 112
WIRE 96 128 -16 128
WIRE 528 128 528 32
WIRE 528 128 384 128
WIRE -112 144 -112 128
WIRE -16 144 -16 128
WIRE 576 144 576 112
WIRE 688 144 688 128
WIRE 96 224 80 224
WIRE 432 224 384 224
WIRE -16 240 -16 224
WIRE 96 320 80 320
WIRE 400 416 384 416
WIRE 80 480 80 320
WIRE 432 480 432 224
WIRE 432 480 80 480
SYMBOL voltage -112 32 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL ind 400 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMATTR SpiceLine Rser=50m
SYMBOL res 672 32 R0
SYMATTR InstName Rload
SYMATTR Value 6.6
SYMBOL res -32 16 R0
SYMATTR InstName R1
SYMATTR Value 200K
SYMBOL res -32 128 R0
SYMATTR InstName R2
SYMATTR Value 15K
SYMBOL polcap 560 48 R0
WINDOW 3 38 37 Left 2
WINDOW 123 23 64 Left 2
SYMATTR Value 100
SYMATTR Value2 x2
SYMATTR InstName C1
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=4 Irms=1.5 Rser=0.04 Lser=0 mfg="KEMET" pn="T520B107M004ASE040" type="Tantalum"
SYMBOL PowerProducts\\LTC3630 240 224 R0
SYMATTR InstName U1
FLAG 400 416 0
FLAG 80 224 0
FLAG -112 144 0
FLAG 576 144 0
FLAG 688 144 0
FLAG -112 32 IN
FLAG 688 32 OUT
FLAG -16 240 0
TEXT 512 304 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG712.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 5V single supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG712.asy)
V1 vS 0 3
V2 vIN 0 PULSE(0 3 0 10n 10n 980n 2u)
R1 vD 0 301
V3 v+ 0 5
XU1 v+ vS vD vIN 0 ADG712 ;pnba Vdd)S)D)IN)GND
C1 vD 0 36p
.tran 10u
.lib ADG712.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 96 240 96
WIRE 240 160 240 96
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -176 304 -192 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE 240 432 240 400
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG712 240 272 R0
SYMATTR InstName U1
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 240 432 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -192 304 v+
FLAG 240 96 v+
FLAG -192 464 0
TEXT 336 424 Left 2 !.tran 10u
TEXT -360 -16 Left 2 ;Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 5V single supply\nOny one channel is modeled