* Z:\home\khalils\Downloads\files\data\raw_asc\AD4084.asc
* Generated by LTspice 26.0.1 for Windows.
* .noise V(ADC_out_dsp) Vin_p dec 100 10 1G
* ADC driver
* ADC Kickback Filter
* Set to ~80 MHz BW to allow\ndriver to settle ADC kickback.
* .ac dec 1000 1k 1G
* .noise V(ADC_out) Vin_p dec 100 10 1G
* AD4084 Digital Filtering Configuration
* ADC output pre-digital filtering
* ADC output post digital filtering (AC and NOISE simulations only)
* SEL input:\n The voltage applied at this input selects the\n digital filter type.\n 0V = No Filter \n 1V = Sinc1 \n 2V = Sinc5\n 3V = Sinc5 + Comp
* DEC input:\n The voltage applied at this pin sets\n the N value for decimation.\n For Sinc1 and Sinc5 Filters Decimation = N\n For Sinc5 +Comp Decimation = (N * 2)\n 2 = N = 2 \n 4 = N = 4 \n 8 = N = 8\n 16 =........\n ...............\n 256 = N = 256 (Max Setting for Sinc5 and Sinc5 + Comp)\n 512 = N = 512 (Sinc1 Only)\n 1024 = N = 1024 (Sinc1 Only)
* Multi-feedback topology, low-pass, second-order
* --> AD4084 digital filter output (ADC_out_dsp)\n does not support transient simulations
* Other signals
* Simulation commands
* Parameters
* Measurements
* Supplies
* Analog front-end
* ADC sampling
* --> ADC Sampling rate. For AD4084 the minimum is 1.25 Msps, maximum 20 Msps
* --> Delay from simulation start to first sampling pulse
* Power supplies
* --> Supply span range for ADA4945-1 is 3V to 10V
* --> Input signal amplitude (peak-to-peak). 2.966 Vpp corresponds to ~-0.1 dBFS\n--> Frequency for the sinusoidal differential input signal\n--> Input signal DC common mode voltage
* Input signal
* The CNV or convert signal is a periodic train of pulses\nwhose rising edges trigger ADC conversion. The frequency\nof these pulses (fs) sets the sampling rate.
* --> VDD33 supply rail for AD4084
* Simulation convergence/speed aid commands
* AUX input filter
* FS input:\n A voltage equal to the sampling frequency in Hertz\n must be supplied at this input.
* Results can be found in the "SPICE Output Log" (View->"Spice Output Log" or Ctrl+L").
* 3dB bandwidth (AC analysis)
* Noise parameters: dynamic range and ENOB (NOISE analysis)
* --> Noise simulation with output BEFORE digital filtering (ADC_out)
* --> Noise simulation with output AFTER digital filtering (ADC_out_DSP)
* .step param decimation list 4 128 256
* Reference
* --> AD4084 can only be used with a 3V reference. This parameter is only used in the Dynamic Range calculations.
* ADC digital filtering
* See the "AD4084 Digital Filtering Configuration" section under the ADC in the schematic below.
* Input signal
* This command speeds up finding the operating point of the circuit
* ; Run a stepped simulation comparing 4 different\n; configurations of the digital filter:\n; Config 1: No digital filtering\n; Config 2: Sinc1 filter, decimation by 64\n; Config 3: Sinc5 filter, decimation by 64\n; Config 4: Sinc5 filter, decimation by 32\n;\n.step param dsp_config list 1 2 3 4\n.param sel = table(dsp_config, 1,0, 2,1, 3,2, 4,2)\n.param decimation = table(dsp_config, 1,2, 2,64, 3,64, 4,32)
* The default configuration (sel=3, decimation=4, fs=20MHz) results in a \nCompensation filter with a bandwidth of ~1MHz.
* --> SNR
* 3V external reference
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\AD4084.asy)
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4945-HP.asy)
V2 VS- 0 {FDA_Vsn}
V_FS N006 0 {fs}
V3 Refin 0 3
C10 0 N005 {CFilt_1}
Vin_n N003 Vin_n SINE(0 {input_Vpp/4} {input_freq}) AC 0.5 0
XU2 N002 FDA_IN+ FDA_IN- N004 VS+ VS- FDA_OUT_N FDA_OUT_P _DIS VOCM Refin 0 0 ADA4945-HP ;pnba 1)2)3)4)5)6)7)8)9)10)11)12)13
V6 VDD33 0 {ADC_VDD33}
V11 VOCM 0 1.5
R14 N005 Vin_n {RG}
V12 _DIS 0 3.3
R13 N001 Vin_p {RG}
R6 N005 FDA_IN- {RMFB}
Vin_cm N003 0 {input_cm} AC 0
C2 0 ADC_out_dsp 0.1p
C7 ADC_IN+ ADC_IN- 78p
C3 FDA_IN+ N002 {CFilt_2}
C1 0 ADC_out 0.1p
V_DEC N007 0 {decimation}
Vin_p Vin_p N003 SINE(0 {input_Vpp/4} {input_freq}) AC 0.5 0
XU1 0 VDD33 Refin ADC_IN+ ADC_IN- AUXIN+ AUXIN- CNV ADC_out ADC_out_dsp N007 N008 N006 ADC_out AD4084 ;pnba GND)Vdd)REFIN)IN+)IN-)AUXIN+)AUXIN-)CNV)Vout)DSPOUT)DEC)SEL)FS)DSPIN
R12 AUXIN- FDA_OUT_N 100
C8 AUXIN+ AUXIN- 10p
R10 ADC_IN- FDA_OUT_N 25
R11 AUXIN+ FDA_OUT_P 100
V1 VS+ 0 {FDA_Vsp}
V14 CNV 0 PULSE(0 1.1 {ACQ_delay} 0.2n 0.2n {0.9*(1/fs)} {1/fs})
C4 FDA_IN- N004 {CFilt_2}
R5 N001 FDA_IN+ {RMFB}
R9 ADC_IN+ FDA_OUT_P 25
C9 N001 0 {CFilt_1}
V_SEL N008 0 {sel}
R3 N005 N004 {RF}
R1 N001 N002 {RF}
.tran 5u
.meas NOISE output_noise_rms INTEG V(onoise) FROM 10 TO {Fmax_noise_integration}
.meas NOISE full_scale_sine_rms PARAM 2*VREF/(2*sqrt(2))
.param VREF=3
.meas NOISE dynamic_range PARAM 20*log10(full_scale_sine_rms/output_noise_rms)
.param Fmax_noise_integration = 1G
.meas NOISE ENOB PARAM (dynamic_range - 1.76)/6.02
.param FDA_VSp = 5V
.param FDA_VSn = -5V
.param fs = 20MEG
.param ACQ_delay = 10n
.param input_Vpp=2.966
.param input_freq = 500k
.param input_cm = 0
.param ADC_VDD33 = 3.3V
.param decimation 4
.ic V(Refin) = 2.999999
.param AFE_gain = 1 ;--> AFE gain = Rf/Rg
.param RF = 499
.param RMFB = 499
.param RG = {RF/AFE_gain}
.param CFilt_1=150p
.param CFilt_2=56p
.meas AC ADC_out_max MAX MAG(V(ADC_out))
.meas AC bw_3db FIND frequency WHEN mag(V(ADC_out))=(ADC_out_max/sqrt(2))
.param sel 3
.lib AD4084.sub
.lib ADA4945-HP.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 12976 5444
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LINE Normal 5216 1696 5216 1696 2
LINE Normal 4272 2736 4272 1904 2
RECTANGLE Normal 5200 2736 3504 1904 2
RECTANGLE Normal 3440 1952 2160 1056 2
RECTANGLE Normal 3888 1776 3488 1088 2
RECTANGLE Normal 3728 912 2496 528 2
RECTANGLE Normal 5168 384 3072 -512 2
RECTANGLE Normal 3056 -288 1664 -512 2
RECTANGLE Normal 3056 384 1664 -48 2
RECTANGLE Normal 2400 912 1600 528 2
RECTANGLE Normal 2112 1952 1424 1056 2
RECTANGLE Normal 3056 -96 1664 -240 2
RECTANGLE Normal 4128 1776 3920 1248 2
RECTANGLE Normal 4704 1168 3952 832 2
SYMBOL voltage 4528 1968 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -102 15 Left 2
WINDOW 3 -96 50 Left 2
SYMATTR InstName V_SEL
SYMATTR Value {sel}
SYMBOL res 4048 1696 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 100
SYMBOL res 3680 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 25
SYMBOL res 2832 1920 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value {RF}
SYMBOL res 2816 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value {RF}
SYMBOL voltage 1696 1392 R0
WINDOW 123 42 70 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 15 95 Left 2
WINDOW 0 43 45 Left 2
SYMATTR Value2 AC 0.5 0
SYMATTR Value SINE(0 {input_Vpp/4} {input_freq})
SYMATTR InstName Vin_p
SYMBOL voltage 1664 720 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {FDA_Vsp}
SYMBOL voltage 1696 1552 R0
WINDOW 123 47 66 Left 2
WINDOW 39 0 0 Left 0
WINDOW 3 15 95 Left 2
WINDOW 0 48 37 Left 2
SYMATTR Value2 AC 0.5 0
SYMATTR Value SINE(0 {input_Vpp/4} {input_freq})
SYMATTR InstName Vin_n
SYMBOL voltage 4688 1968 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -102 20 Left 2
WINDOW 3 -198 51 Left 2
SYMATTR InstName V_DEC
SYMATTR Value {decimation}
SYMBOL cap 5040 1504 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 0.1p
SYMBOL OpAmps\\ADA4945-HP 3184 1552 R0
WINDOW 3 73 92 Left 2
SYMATTR InstName U2
SYMBOL voltage 1888 720 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {FDA_Vsn}
SYMBOL cap 2352 1424 R0
WINDOW 3 18 56 Left 2
WINDOW 0 32 13 Left 2
SYMATTR Value {CFilt_1}
SYMATTR InstName C9
SYMBOL cap 4048 1536 R0
SYMATTR InstName C8
SYMATTR Value 10p
SYMBOL voltage 1488 1552 R0
WINDOW 123 41 74 Left 2
WINDOW 39 0 0 Left 0
WINDOW 0 42 49 Left 2
WINDOW 3 30 98 Left 2
SYMATTR Value2 AC 0
SYMATTR InstName Vin_cm
SYMATTR Value {input_cm}
SYMBOL res 3680 1472 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 25
SYMBOL cap 2960 1824 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value {CFilt_2}
SYMATTR InstName C4
SYMBOL res 2304 1680 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value {RG}
SYMBOL res 2592 1392 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value {RMFB}
SYMBOL voltage 2576 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 36 120 Left 2
WINDOW 3 13 96 Left 2
SYMATTR Value PULSE(0 1.1 {ACQ_delay} 0.2n 0.2n {0.9*(1/fs)} {1/fs})
SYMATTR InstName V14
SYMBOL cap 2352 1584 R0
WINDOW 3 17 49 Left 2
WINDOW 0 32 11 Left 2
SYMATTR Value {CFilt_1}
SYMATTR InstName C10
SYMBOL cap 3696 1520 R0
SYMATTR InstName C7
SYMATTR Value 78p
SYMBOL AD4084 4464 1520 R0
SYMATTR InstName U1
SYMBOL res 2304 1360 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R13
SYMATTR Value {RG}
SYMBOL voltage 3296 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V11
SYMATTR Value 1.5
SYMBOL res 4048 1376 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 100
SYMBOL voltage 4256 976 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 3
SYMBOL voltage 3568 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V12
SYMATTR Value 3.3
SYMBOL res 2592 1712 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value {RMFB}
SYMBOL cap 2960 1280 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value {CFilt_2}
SYMATTR InstName C3
SYMBOL cap 5040 1744 M180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value 0.1p
SYMBOL voltage 2096 720 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value {ADC_VDD33}
SYMBOL voltage 4368 1968 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -86 14 Left 2
WINDOW 3 -80 45 Left 2
SYMATTR InstName V_FS
SYMATTR Value {fs}
FLAG 4368 1696 0
FLAG 5056 1536 0
FLAG 5056 1776 0
FLAG 5152 1408 ADC_out
FLAG 5136 1648 ADC_out_dsp
FLAG 3264 1408 VOCM
FLAG 3264 1376 VS+
FLAG 3232 1744 VS-
FLAG 3088 1664 0
FLAG 3296 768 0
FLAG 3312 608 VOCM
FLAG 3568 768 0
FLAG 3584 608 _DIS
FLAG 3232 1712 _DIS
FLAG 2880 1488 FDA_IN+
FLAG 2880 1552 FDA_IN-
FLAG 3248 1664 0
FLAG 4192 1392 AUXIN+
FLAG 3904 1488 ADC_IN+
FLAG 3904 1616 ADC_IN-
FLAG 4192 1712 AUXIN-
FLAG 3392 1488 FDA_OUT_N
FLAG 3392 1616 FDA_OUT_P
FLAG 4368 2080 0
FLAG 4528 2080 0
FLAG 4688 2080 0
FLAG 1664 848 0
FLAG 1888 848 0
FLAG 1680 688 VS+
FLAG 1904 688 VS-
FLAG 2096 848 0
FLAG 2112 688 VDD33
FLAG 2576 768 0
FLAG 2592 608 CNV
FLAG 1488 1696 0
FLAG 1744 1376 Vin_p
FLAG 1744 1696 Vin_n
FLAG 4816 1344 VDD33
FLAG 4816 1472 CNV
FLAG 4256 1120 0
FLAG 4432 960 Refin
FLAG 2320 1552 0
FLAG 3264 1440 Refin
TEXT 1696 -472 Left 2 !.tran 5u
TEXT 1696 -352 Left 2 ;.noise V(ADC_out_dsp) Vin_p dec 100 10 1G
TEXT 1704 232 Left 2 !.meas NOISE output_noise_rms INTEG V(onoise) FROM 10 TO {Fmax_noise_integration}
TEXT 1704 272 Left 2 !.meas NOISE full_scale_sine_rms PARAM 2*VREF/(2*sqrt(2))
TEXT 3128 -280 Left 2 !.param VREF=3
TEXT 1704 312 Left 2 !.meas NOISE dynamic_range PARAM 20*log10(full_scale_sine_rms/output_noise_rms)
TEXT 1704 192 Left 2 !.param Fmax_noise_integration = 1G
TEXT 1704 352 Left 2 !.meas NOISE ENOB PARAM (dynamic_range - 1.76)/6.02
TEXT 2160 1032 Left 4 ;ADC driver
TEXT 3480 1064 Left 4 ;ADC Kickback Filter
TEXT 3512 1128 Left 2 ;Set to ~80 MHz BW to allow\ndriver to settle ADC kickback.
TEXT 1696 -432 Left 2 ;.ac dec 1000 1k 1G
TEXT 1696 -392 Left 2 ;.noise V(ADC_out) Vin_p dec 100 10 1G
TEXT 3496 1872 Left 4 ;AD4084 Digital Filtering Configuration
TEXT 5072 1352 Left 4 ;ADC output pre-digital filtering
TEXT 5040 1600 Left 4 ;ADC output post digital filtering (AC and NOISE simulations only)
TEXT 3552 2048 Left 2 ;SEL input:\n  The voltage applied at this input selects the\n  digital filter type.\n    0V = No Filter \n    1V = Sinc1 \n    2V = Sinc5\n    3V = Sinc5 + Comp
TEXT 3552 2280 Left 2 ;DEC input:\n  The voltage applied at this pin sets\n  the N value for decimation.\n  For Sinc1 and Sinc5 Filters Decimation = N\n  For Sinc5 +Comp Decimation = (N * 2)\n  2 = N = 2 \n  4 = N = 4 \n  8 = N = 8\n  16 =........\n  ...............\n  256 =   N = 256 (Max Setting for Sinc5 and Sinc5 + Comp)\n  512 =   N = 512 (Sinc1 Only)\n  1024 = N = 1024 (Sinc1 Only)
TEXT 2432 1080 Left 3 ;Multi-feedback topology, low-pass, second-order
TEXT 2264 -472 Left 2 ;--> AD4084 digital filter output (ADC_out_dsp)\n     does not support transient simulations
TEXT 2496 512 Left 2 ;Other signals
TEXT 1664 -528 Left 2 ;Simulation commands
TEXT 3096 -528 Left 2 ;Parameters
TEXT 1664 -64 Left 2 ;Measurements
TEXT 1600 512 Left 2 ;Supplies
TEXT 3120 -424 Left 2 !.param FDA_VSp = 5V\n.param FDA_VSn = -5V
TEXT 3104 16 Left 2 ;Analog front-end
TEXT 3104 -96 Left 2 ;ADC sampling
TEXT 3128 -64 Left 2 !.param fs = 20MEG\n.param ACQ_delay = 10n
TEXT 3488 -64 Left 2 ;--> ADC Sampling rate. For AD4084 the minimum is 1.25 Msps, maximum 20 Msps
TEXT 3488 -32 Left 2 ;--> Delay from simulation start to first sampling pulse
TEXT 3104 -456 Left 2 ;Power supplies
TEXT 3488 -416 Left 2 ;--> Supply span range for ADA4945-1 is 3V to 10V
TEXT 3488 -192 Left 2 ;--> Input signal amplitude (peak-to-peak). 2.966 Vpp corresponds to ~-0.1 dBFS\n--> Frequency for the sinusoidal differential input signal\n--> Input signal DC common mode voltage
TEXT 3128 -192 Left 2 !.param input_Vpp=2.966\n.param input_freq = 500k\n.param input_cm = 0
TEXT 3104 -224 Left 2 ;Input signal
TEXT 2544 808 Left 2 ;The CNV or convert signal is a periodic train of pulses\nwhose rising edges trigger ADC conversion. The frequency\nof these pulses (fs) sets the sampling rate.
TEXT 3488 -352 Left 2 ;--> VDD33 supply rail for AD4084
TEXT 1664 -256 Left 2 ;Simulation convergence/speed aid commands
TEXT 3120 -352 Left 2 !.param ADC_VDD33 = 3.3V
TEXT 3920 1224 Left 3 ;AUX input filter
TEXT 3552 1936 Left 2 ;FS input:\n  A voltage equal to the sampling frequency in Hertz\n  must be supplied at this input.
TEXT 1688 -16 Left 2 ;Results can be found in the "SPICE Output Log" (View->"Spice Output Log" or Ctrl+L").
TEXT 1688 40 Left 2 ;3dB bandwidth (AC analysis)
TEXT 1680 160 Left 2 ;Noise parameters: dynamic range and ENOB (NOISE analysis)
TEXT 2264 -392 Left 2 ;--> Noise simulation with output BEFORE digital filtering (ADC_out)
TEXT 2264 -352 Left 2 ;--> Noise simulation with output AFTER digital filtering (ADC_out_DSP)
TEXT 4312 2296 Left 2 ;.step param decimation list 4 128 256
TEXT 3104 -312 Left 2 ;Reference
TEXT 3488 -288 Left 2 ;--> AD4084 can only be used with a 3V reference. This parameter is only used in the Dynamic Range calculations.
TEXT 3104 288 Left 2 ;ADC digital filtering
TEXT 3128 328 Left 2 ;See the "AD4084 Digital Filtering Configuration" section under the ADC in the schematic below.
TEXT 4312 2264 Left 2 !.param decimation 4
TEXT 1424 1032 Left 4 ;Input signal
TEXT 1688 -200 Left 2 !.ic V(Refin) = 2.999999
TEXT 3128 48 Left 2 !.param AFE_gain = 1 ;--> AFE gain = Rf/Rg\n.param RF = 499\n.param RMFB = 499\n.param RG = {RF/AFE_gain}\n.param CFilt_1=150p\n.param CFilt_2=56p
TEXT 1976 -200 Left 2 ;This command speeds up finding the operating point of the circuit
TEXT 1704 72 Left 2 !.meas AC ADC_out_max MAX MAG(V(ADC_out))
TEXT 1704 104 Left 2 !.meas AC bw_3db FIND frequency WHEN mag(V(ADC_out))=(ADC_out_max/sqrt(2))
TEXT 4312 2408 Left 2 ;; Run a stepped simulation comparing 4 different\n; configurations of the digital filter:\n; Config 1: No digital filtering\n; Config 2: Sinc1 filter, decimation by 64\n; Config 3: Sinc5 filter, decimation by 64\n; Config 4: Sinc5 filter, decimation by 32\n;\n.step param dsp_config list 1 2 3 4\n.param sel = table(dsp_config, 1,0, 2,1, 3,2, 4,2)\n.param decimation = table(dsp_config, 1,2, 2,64, 3,64, 4,32)
TEXT 4312 2232 Left 2 !.param sel 3
TEXT 4312 2168 Left 2 ;The default configuration (sel=3, decimation=4, fs=20MHz) results in a \nCompensation filter with a bandwidth of ~1MHz.
TEXT 2736 312 Left 2 ;--> SNR
TEXT 3952 800 Left 4 ;3V external reference