* Z:\home\khalils\Downloads\files\data\raw_asc\1ac00f53ddc5_ADC_SAR_V2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 in 0 PWL(0 0 1 0 21 20)
*--------------------------------------------------------------------------------------------------------------
*Parameters
*--------------------------------------------------------------------------------------------------------------
.param vhigh 1
.param vlow 0
.param bits 4
.param vref 2**bits
.param nr_quantization_level = 15
.param fullScale=15
.param qInter {fullScale/vref} ; Quantization interval = 15/2^4 = 0.9375
*--------------------------------------------------------------------------------------------------------------
*Circuit
*--------------------------------------------------------------------------------------------------------------
XADC_4B In OUT[3] OUT[2] OUT[1] OUT[0] ADC_4bits
+ vref = {vref}
+ fullScale = fullScale
;B_test step 0 V=(qInter*vref * (V(out[3])/2 + V(out[2])/4 + V(out[1])/8 + V(out[0])/16))+qInter
XADC_3B In OUT1[2] OUT1[1] OUT1[0] ADC_3bits
+ vref = {vref}
+ fullScale = fullScale
;B_test step 0 V=(qInter*vref * (V(out[3])/2 + V(out[2])/4 + V(out[1])/8 + V(out[0])/16))+qInter
*--------------------------------------------------------------------------------------------------------------
*Subcircuit: ADC 4 BITS
*--------------------------------------------------------------------------------------------------------------
.SUBCKT ADC_4bits In OUT[3] OUT[2] OUT[1] OUT[0]
.param bits 4
.param vref 2**bits
.param fullScale=5
.param qInter {fullScale/vref} ; Quantization interval = 15/2^4 = 0.9375
B3_vdac vdac[3] 0 V=qInter * vref * (vhigh/2 + vlow/4 + vlow/8 + vlow/16)
B3_out out[3] 0 V= V(in)>=V(vdac[3]) ? vhigh : vlow
B2_vdac vdac[2] 0 V=qInter * vref * (V(out[3])/2 + vhigh/4 + vlow/8 + vlow/16)
B2_out out[2] 0 V= V(in)>=V(vdac[2]) ? vhigh : vlow
B1_vdac vdac[1] 0 V=qInter * vref * (V(out[3])/2 + V(out[2])/4 + vhigh/8 + vlow/16)
B1_out out[1] 0 V= V(in)>=V(vdac[1]) ? vhigh : vlow
B0_vdac vdac[0] 0 V=qInter * vref * (V(out[3])/2 + V(out[2])/4 + V(out[1])/8 + vhigh/16)
B0_out out[0] 0 V= V(in)>=V(vdac[0]) ? vhigh : vlow
.END
*--------------------------------------------------------------------------------------------------------------
*Subcircuit: ADC 3 BITS
*--------------------------------------------------------------------------------------------------------------
.SUBCKT ADC_3bits In OUT[2] OUT[1] OUT[0]
.param bits 3
.param vref 2**bits
.param fullScale=5
.param qInter {fullScale/vref} ; Quantization interval = 15/2^4 = 0.9375
B2_vdac vdac[2] 0 V=qInter * vref * (vhigh/2 + vlow/4 + vlow/8)
B2_out out[2] 0 V= V(in)>=V(vdac[2]) ? vhigh : vlow
B1_vdac vdac[1] 0 V=qInter * vref * (V(out[2])/2 + vhigh/4 + vlow/8)
B1_out out[1] 0 V= V(in)>=V(vdac[1]) ? vhigh : vlow
B0_vdac vdac[0] 0 V=qInter * vref * (V(out[2])/2 + V(out[1])/4 + vhigh/8)
B0_out out[0] 0 V= V(in)>=V(vdac[0]) ? vhigh : vlow
.END
*--------------------------------------------------------------------------------------------------------------
*Subcircuit: Measurment
*--------------------------------------------------------------------------------------------------------------
.INCLUDE ADC_MEASURMENT.meas
*--------------------------------------------------------------------------------------------------------------
.STEP PARAM fullScale list 5 15
.ends
.tran 18s
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1588 2168
WIRE 48 -48 48 -80
WIRE 48 0 48 -48
WIRE 48 144 48 80
FLAG 48 144 0
FLAG 48 -48 in
SYMBOL voltage 48 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 0  21 20)
TEXT 376 -88 Left 2 !*--------------------------------------------------------------------------------------------------------------\n*Parameters\n*--------------------------------------------------------------------------------------------------------------\n.param vhigh 1\n.param vlow 0\n \n.param bits 4\n.param vref 2**bits\n.param nr_quantization_level = 15\n.param fullScale=15\n.param qInter {fullScale/vref} ; Quantization interval = 15/2^4 = 0.9375\n \n*--------------------------------------------------------------------------------------------------------------\n*Circuit\n*--------------------------------------------------------------------------------------------------------------\nXADC_4B In OUT[3] OUT[2] OUT[1] OUT[0] ADC_4bits\n+ vref = {vref}\n+ fullScale = fullScale\n;B_test step 0 V=(qInter*vref * (V(out[3])/2 + V(out[2])/4 + V(out[1])/8 + V(out[0])/16))+qInter\n \n \nXADC_3B In OUT1[2] OUT1[1] OUT1[0] ADC_3bits\n+ vref = {vref}\n+ fullScale = fullScale\n;B_test step 0 V=(qInter*vref * (V(out[3])/2 + V(out[2])/4 + V(out[1])/8 + V(out[0])/16))+qInter\n \n*--------------------------------------------------------------------------------------------------------------\n*Subcircuit: ADC 4 BITS\n*--------------------------------------------------------------------------------------------------------------\n.SUBCKT ADC_4bits In OUT[3] OUT[2] OUT[1] OUT[0]\n.param bits 4   \n.param vref 2**bits\n.param fullScale=5\n.param qInter {fullScale/vref} ; Quantization interval = 15/2^4 = 0.9375\n \nB3_vdac vdac[3] 0 V=qInter * vref * (vhigh/2 + vlow/4 + vlow/8 + vlow/16)\nB3_out  out[3]  0 V= V(in)>=V(vdac[3]) ? vhigh : vlow\n \n \nB2_vdac vdac[2] 0 V=qInter * vref * (V(out[3])/2 + vhigh/4 + vlow/8 + vlow/16)\nB2_out  out[2]  0 V= V(in)>=V(vdac[2]) ? vhigh : vlow\n \nB1_vdac vdac[1] 0 V=qInter * vref * (V(out[3])/2 + V(out[2])/4 + vhigh/8 + vlow/16)\nB1_out  out[1]  0 V= V(in)>=V(vdac[1]) ? vhigh : vlow\n \n \nB0_vdac vdac[0] 0 V=qInter * vref * (V(out[3])/2 + V(out[2])/4 + V(out[1])/8 + vhigh/16)\nB0_out  out[0]  0 V= V(in)>=V(vdac[0]) ? vhigh : vlow\n \n.END\n \n*--------------------------------------------------------------------------------------------------------------\n*Subcircuit: ADC 3 BITS\n*--------------------------------------------------------------------------------------------------------------\n.SUBCKT ADC_3bits In OUT[2] OUT[1] OUT[0]\n.param bits 3\n.param vref 2**bits\n.param fullScale=5\n.param qInter {fullScale/vref} ; Quantization interval = 15/2^4 = 0.9375\n \nB2_vdac vdac[2] 0 V=qInter * vref * (vhigh/2 + vlow/4 + vlow/8)\nB2_out  out[2]  0 V= V(in)>=V(vdac[2]) ? vhigh : vlow\n \nB1_vdac vdac[1] 0 V=qInter * vref * (V(out[2])/2 + vhigh/4 + vlow/8)\nB1_out  out[1]  0 V= V(in)>=V(vdac[1]) ? vhigh : vlow\n \nB0_vdac vdac[0] 0 V=qInter * vref * (V(out[2])/2 + V(out[1])/4 + vhigh/8)\nB0_out  out[0]  0 V= V(in)>=V(vdac[0]) ? vhigh : vlow\n \n.END\n \n*--------------------------------------------------------------------------------------------------------------\n*Subcircuit: Measurment\n*--------------------------------------------------------------------------------------------------------------\n.INCLUDE ADC_MEASURMENT.meas\n \n*--------------------------------------------------------------------------------------------------------------\n \n.STEP PARAM fullScale list 5 15\n.ends \n.tran 18s