Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1368.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
R1 N001 +V 200
MQ1 N004 N002 N001 N001 BSS84
I1 N003 0 SINE(.2 .1 1K)
R2 +V N003 .1
R3 N004 0 20K
C1 OUT 0 .1
XU1 N003 N001 +V 0 N002 LT1368 ;pnba In+)In-)V+)V-)OUT
XU2 N004 OUT +V 0 OUT LT1368 ;pnba In+)In-)V+)V-)OUT
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m
* Positive Supply Rail Current Sense
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1368.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1388 720
WIRE 32 16 -112 16
WIRE 80 16 32 16
WIRE 176 16 160 16
WIRE 384 16 176 16
WIRE -112 32 -112 16
WIRE 32 32 32 16
WIRE 224 80 224 64
WIRE 176 96 176 16
WIRE 192 96 176 96
WIRE 384 96 384 16
WIRE 608 96 496 96
WIRE 336 112 256 112
WIRE -112 128 -112 112
WIRE 32 128 32 112
WIRE 192 128 32 128
WIRE 32 144 32 128
WIRE 224 160 224 144
WIRE 544 160 544 144
WIRE 496 176 496 96
WIRE 512 176 496 176
WIRE 608 192 608 96
WIRE 608 192 576 192
WIRE 672 192 608 192
WIRE 720 192 672 192
WIRE 384 208 384 192
WIRE 512 208 384 208
WIRE 672 208 672 192
WIRE 384 224 384 208
WIRE 32 240 32 224
WIRE 544 240 544 224
WIRE 672 288 672 272
WIRE 384 320 384 304
FLAG -112 128 0
FLAG 224 64 +V
FLAG 720 192 OUT
FLAG 32 240 0
FLAG 224 160 0
FLAG 32 16 +V
FLAG 384 320 0
FLAG 544 144 +V
FLAG 544 240 0
FLAG 672 288 0
SYMBOL voltage -112 16 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 176 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL pmos 336 192 M180
WINDOW 0 61 66 Left 2
WINDOW 3 59 31 Left 2
SYMATTR InstName Q1
SYMATTR Value BSS84
SYMBOL current 32 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName I1
SYMATTR Value SINE(.2 .1 1K)
SYMBOL res 16 16 R0
SYMATTR InstName R2
SYMATTR Value .1
SYMBOL res 368 208 R0
SYMATTR InstName R3
SYMATTR Value 20K
SYMBOL cap 656 208 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL opamps\\LT1368 224 48 R0
SYMATTR InstName U1
SYMBOL opamps\\LT1368 544 128 R0
SYMATTR InstName U2
TEXT 464 312 Left 2 !.tran 3m
TEXT 408 -16 Bottom 2 ;Positive Supply Rail Current Sense
* Z:\home\khalils\Downloads\files\data\raw_asc\00d48f9df189_CS_pMOS_4x_B.asc
* Generated by LTspice 26.0.1 for Windows.
M1 drain gate VDD VDD PMOS_mobius m=4
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 176 208 176
WIRE 304 176 256 176
WIRE 208 256 208 176
WIRE 160 272 64 272
WIRE 304 304 304 176
WIRE 304 304 208 304
WIRE 208 416 208 352
FLAG 208 416 drain
IOPIN 208 416 BiDir
FLAG 64 272 gate
IOPIN 64 272 BiDir
FLAG 256 176 VDD
SYMBOL pmos4 160 352 M180
WINDOW 123 56 50 Left 2
SYMATTR InstName M1
SYMATTR Value PMOS_mobius
SYMATTR Value2 m=4
* Z:\home\khalils\Downloads\files\data\raw_asc\7cdfce5840d1_1078.asc
* Generated by LTspice 26.0.1 for Windows.
* Absolute Value Circuit(Full-Wave Rectifier)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1078.asy)
XU2 N002 OUT +V 0 OUT LT1078 ;pnba In+)In-)V+)V-)OUT
R2 N001 IN 200K
V3 IN 0 SINE(0 1 100)
XU1 0 N001 +V 0 N003 LT1078 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 5
R1 N002 N001 200K
D1 N003 N002 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 30m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 -80 96
WIRE 128 96 112 96
WIRE 224 96 128 96
WIRE 384 96 304 96
WIRE -80 112 -80 96
WIRE 528 128 432 128
WIRE -192 160 -192 144
WIRE 480 192 480 176
WIRE -80 208 -80 192
WIRE 192 208 192 192
WIRE 432 208 432 128
WIRE 448 208 432 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 528 224 528 128
WIRE 528 224 512 224
WIRE 576 224 528 224
WIRE 304 240 224 240
WIRE 384 240 384 96
WIRE 384 240 368 240
WIRE 448 240 384 240
WIRE 160 256 128 256
WIRE -192 272 -192 240
WIRE 480 272 480 256
WIRE 192 288 192 272
SYMBOL diode 304 256 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 320 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 200K
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 200K
SYMBOL voltage -192 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT1078 480 160 R0
SYMATTR InstName U2
SYMBOL opamps\\LT1078 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -80 96 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
FLAG -192 272 0
FLAG 192 192 +V
FLAG -192 144 +V
FLAG -80 208 0
FLAG 192 288 0
FLAG 480 176 +V
FLAG 480 272 0
FLAG -80 96 IN
FLAG 576 224 OUT
FLAG 128 256 0
TEXT 400 344 Left 0 !.tran 30m
TEXT 272 40 Bottom 0 ;Absolute Value Circuit(Full-Wave Rectifier)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1517-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1517-3.3.asy)
XU1 IN 0 OUT N002 N001 LTC1517-3.3 ;pnba Vin)GND)Vout)Cap+)Cap-
C2 N002 N001 .1
V1 IN 0 3
Rload OUT 0 500
C1 OUT 0 6.8
.tran 2m startup
.lib LTC1517-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3300 2376
WIRE 2832 1872 2784 1872
WIRE 2944 1872 2896 1872
WIRE 2784 1936 2784 1872
WIRE 2944 1936 2944 1872
WIRE 2736 2048 2624 2048
WIRE 3056 2048 2992 2048
WIRE 3152 2048 3056 2048
WIRE 2624 2064 2624 2048
WIRE 3056 2064 3056 2048
WIRE 3152 2064 3152 2048
WIRE 2624 2160 2624 2144
WIRE 3056 2160 3056 2128
WIRE 3152 2160 3152 2144
WIRE 2864 2192 2864 2160
SYMBOL PowerProducts\\LTC1517-3.3 2864 2048 R0
SYMATTR InstName U1
SYMBOL cap 2896 1856 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL VOLTAGE 2624 2048 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL RES 3136 2048 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL cap 3040 2064 R0
SYMATTR InstName C1
SYMATTR Value 6.8
FLAG 3056 2160 0
FLAG 2864 2192 0
FLAG 2624 2160 0
FLAG 3152 2160 0
FLAG 3152 2048 OUT
FLAG 2624 2048 IN
TEXT 3000 2232 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\4c154b27be62_Photodiode.asc
* Generated by LTspice 26.0.1 for Windows.
B1 + N001 I=V($G_POWER)*Responsivity
C1 N001 + 50p
R3 $G_POWER 0 1G
R1 N001 + 1G
R2 N001 - 25
D1 N001 + D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.param Responsivity=0.14
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -128 112 -128
WIRE 160 -96 160 -128
WIRE 160 16 160 -16
WIRE 224 96 160 96
WIRE 288 96 224 96
WIRE 352 96 288 96
WIRE 400 96 352 96
WIRE 528 96 480 96
WIRE 160 128 160 96
WIRE 224 144 224 96
WIRE 288 144 288 96
WIRE 352 144 352 96
WIRE 160 240 160 208
WIRE 224 240 224 208
WIRE 224 240 160 240
WIRE 288 240 288 208
WIRE 288 240 224 240
WIRE 352 240 352 224
WIRE 352 240 288 240
WIRE 528 240 352 240
IOPIN 528 240 BiDir
IOPIN 528 96 BiDir
SYMBOL bi 160 208 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName B1
SYMATTR Value I=V($G_POWER)*Responsivity
SYMBOL cap 272 144 R0
SYMATTR InstName C1
SYMATTR Value 50p
SYMBOL res 384 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 25
SYMBOL res 144 -112 R0
SYMATTR InstName R3
SYMATTR Value 1G
SYMBOL res 336 128 R0
SYMATTR InstName R1
SYMATTR Value 1G
SYMBOL diode 208 144 R0
SYMATTR InstName D1
FLAG 528 240 +
FLAG 528 96 -
FLAG 160 16 0
FLAG 112 -128 $G_POWER
TEXT 72 328 Left 2 !.param Responsivity=0.14
* Z:\home\khalils\Downloads\files\data\raw_asc\AD824.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD824.asy)
V2 -V 0 -15
XU1 IN N001 +V -V OUT AD820 ;pnba In+)In-)V+)V-)OUT
Vin IN 0 SINE(0 1 10K)
R2 OUT N001 10K
R1 N001 0 10K
V1 +V 0 15
.tran 1m
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 144 -1152 144 -1168
WIRE 256 -1152 256 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 688 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 144 -1056 144 -1072
WIRE 256 -1056 256 -1072
WIRE 432 -976 432 -992
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 144 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL AD824 576 -1168 R0
SYMATTR InstName U1
SYMBOL voltage 256 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
FLAG 144 -1168 +V
FLAG 144 -1056 0
FLAG 432 -976 0
FLAG 688 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 256 -1168 -V
FLAG 576 -1072 -V
FLAG 416 -1216 0
FLAG 256 -1056 0
TEXT 704 -1016 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\1008ca164cd9_1.3.1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N002 1K
M2 N002 N003 N004 N004 MC14007_P
Vi N003 0
M1 N004 N003 0 0 MC14007_N
VDD N001 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model MC14007_N NMOS (Vto=1.6 Kp=1.1m
.model MC14007_P PMOS (Vto=-1.3 Kp=1.4m)
.dc Vi 0 5 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -128 -432 -432 -432
WIRE -432 -400 -432 -432
WIRE -432 -256 -432 -320
WIRE -352 -256 -432 -256
WIRE -432 -240 -432 -256
WIRE -480 -160 -624 -160
WIRE -432 -80 -432 -144
WIRE -352 -80 -432 -80
WIRE -128 -64 -128 -432
WIRE -432 -32 -432 -80
WIRE -624 48 -624 -160
WIRE -480 48 -624 48
WIRE -624 176 -624 48
WIRE -624 320 -624 256
WIRE -432 320 -432 64
WIRE -432 320 -624 320
WIRE -128 320 -128 16
WIRE -128 320 -432 320
WIRE -432 368 -432 320
SYMBOL voltage -128 -80 R0
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL nmos -480 -32 R0
SYMATTR InstName M1
SYMATTR Value MC14007_N
SYMBOL pmos -480 -240 R0
SYMATTR InstName M2
SYMATTR Value MC14007_P
SYMBOL res -448 -416 R0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -624 160 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value ""
SYMATTR InstName Vi
FLAG -432 368 0
TEXT 144 -16 Left 1 !.model MC14007_N NMOS (Vto=1.6 Kp=1.1m
TEXT 144 40 Left 1 !.model MC14007_P PMOS (Vto=-1.3 Kp=1.4m)
TEXT -656 392 Left 2 !.dc Vi 0 5 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\5328561c41f0_linear_regulator.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1117.asy)
V1 N001 0 5
C2 Vout 0 C
R1 Vout N002 460
R4 N003 0 120
XU1 N002 Vout N001 LT1117 ;pnba ADJ)OUT)IN
R2 N002 0 270
R3 N004 0 330
.dc V1 0 10 0.1
.lib LT1117.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 112 -112 112
WIRE 400 112 320 112
WIRE 464 112 400 112
WIRE 592 112 464 112
WIRE 608 112 592 112
WIRE -112 160 -112 112
WIRE 400 160 400 112
WIRE 192 272 192 208
WIRE 400 272 400 240
WIRE 400 272 192 272
WIRE -112 320 -112 240
WIRE 304 368 304 320
WIRE 400 368 400 272
WIRE 496 368 496 320
WIRE 592 368 592 112
WIRE 304 480 304 448
WIRE 400 480 400 448
WIRE 496 480 496 448
WIRE 592 480 592 432
WIRE 0 0 0 0
SYMBOL voltage -112 144 R0
WINDOW 3 48 68 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 47 34 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 384 352 R0
SYMATTR InstName R2
SYMATTR Value 270
SYMBOL cap 576 368 R0
SYMATTR InstName C2
SYMBOL res 384 144 R0
SYMATTR InstName R1
SYMATTR Value 460
SYMBOL PowerProducts\\LT1117 192 112 R0
SYMATTR InstName U1
SYMBOL res 480 352 R0
SYMATTR InstName R3
SYMATTR Value 330
SYMBOL res 288 352 R0
SYMATTR InstName R4
SYMATTR Value 120
FLAG -112 320 0
FLAG 400 480 0
FLAG 464 112 Vout
FLAG 496 480 0
FLAG 304 480 0
FLAG 592 480 0
TEXT -56 312 Left 2 !.dc V1 0 10 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\37b6072acc9b_flyback_diode.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N002 VC1 100m Rser=400
Q1 VC1 N006 0 0 BC547B
R1 N006 N005 1k
V2 N005 0 PULSE(0 5 0 1m 1m 20m 100m 1)
V3 N002 0 12
L2 N001 VC2 100m Rser=400
Q2 VC2 N004 0 0 BC547B
R2 N004 N003 1k
V1 N003 0 PULSE(0 5 0 1m 1m 20m 100m 1)
V4 N001 0 12
D1 VC2 N001 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 40m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1004 680
WIRE 864 128 672 128
WIRE 352 144 160 144
WIRE 864 160 864 128
WIRE 864 160 816 160
WIRE 672 192 672 128
WIRE 816 192 816 160
WIRE 864 192 864 160
WIRE 160 208 160 144
WIRE 352 208 352 144
WIRE 672 320 672 272
WIRE 816 320 816 256
WIRE 864 320 864 272
WIRE 864 320 816 320
WIRE 160 336 160 288
WIRE 352 368 352 288
WIRE 416 368 352 368
WIRE 864 368 864 320
WIRE 944 368 864 368
WIRE 864 384 864 368
WIRE 352 400 352 368
WIRE 640 432 496 432
WIRE 800 432 720 432
WIRE 128 448 -16 448
WIRE 288 448 208 448
WIRE 496 464 496 432
WIRE -16 480 -16 448
WIRE 496 576 496 544
WIRE 864 576 864 480
WIRE -16 592 -16 560
WIRE 352 592 352 496
FLAG 352 592 0
FLAG 160 336 0
FLAG -16 592 0
FLAG 864 576 0
FLAG 672 320 0
FLAG 496 576 0
FLAG 944 368 VC2
FLAG 416 368 VC1
SYMBOL ind 336 192 R0
SYMATTR InstName L1
SYMATTR Value 100m
SYMATTR SpiceLine Rser=400
SYMBOL npn 288 400 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL Res 224 432 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL Voltage -16 464 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1m 1m 20m 100m 1)
SYMBOL Voltage 160 192 R0
SYMATTR InstName V3
SYMATTR Value 12
SYMBOL ind 848 176 R0
SYMATTR InstName L2
SYMATTR Value 100m
SYMATTR SpiceLine Rser=400
SYMBOL npn 800 384 R0
SYMATTR InstName Q2
SYMATTR Value BC547B
SYMBOL Res 736 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL Voltage 496 448 R0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 1m 1m 20m 100m 1)
SYMBOL Voltage 672 176 R0
SYMATTR InstName V4
SYMATTR Value 12
SYMBOL diode 832 256 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
TEXT -32 56 Left 2 !.tran 40m
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1728-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N002 0 N004 N005 N003 LTC1728-2.5 ;pnba _RST)GND)VccA)Vcc2.5)Vcc3
R1 N002 N001 10K
V1 N001 0 5
V2 N004 0 PWL(0 1.05 7 1.05 8 0.95 9 1.05)
V3 N005 0 PWL(0 2.5 4 2.5 5 2.25 6 2.5)
V4 N003 0 PWL(0 3.3 1 3.3 2 3 3 3.3)
.tran 10
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC1728-2.5.asy)
.lib LTC1728-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1100 756
WIRE -144 144 -208 144
WIRE 48 144 -64 144
WIRE 464 144 272 144
WIRE 464 160 464 144
WIRE -208 176 -208 144
WIRE 48 208 16 208
WIRE 464 256 464 240
WIRE 48 272 -80 272
WIRE 384 272 272 272
WIRE -208 288 -208 256
WIRE 384 288 384 272
WIRE -80 304 -80 272
WIRE 384 384 384 368
WIRE -80 416 -80 384
FLAG 16 208 0
FLAG -208 288 0
FLAG -80 416 0
FLAG 384 384 0
FLAG 464 256 0
SYMBOL LTC1728-2.5 160 240 R0
SYMATTR InstName U1
SYMBOL res -48 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -208 160 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -80 288 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PWL(0 1.05 7 1.05 8 0.95 9 1.05)
SYMBOL voltage 384 272 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 2.5 4 2.5 5 2.25 6 2.5)
SYMBOL voltage 464 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value PWL(0 3.3 1 3.3 2 3 3 3.3)
TEXT 504 464 Left 2 !.tran 10
* Z:\home\khalils\Downloads\files\data\raw_asc\6566005e0ad9_Assignment_7b.asc
* Generated by LTspice 26.0.1 for Windows.
* Inverting Summing Amplifier (Common Gain)
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
Vee 0 Vee 15
R2 N002 N003 200000
V3 N004 0 SINE(0 3 1000)
Rf Vout N002 400000
XU1 0 N002 Vcc Vee Vout LT1001 ;pnba In+)In-)V+)V-)OUT
V1 N001 0 SINE(0 1 1000)
Vcc Vcc 0 15
V2 N003 0 SINE(0 2 1000)
R1 N002 N001 200000
R3 N002 N004 200000
.tran 5ms
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -208 16 -288 16
WIRE -64 16 -128 16
WIRE 80 16 16 16
WIRE 192 16 112 16
WIRE 336 16 272 16
WIRE 480 48 480 16
WIRE -288 64 -288 16
WIRE 224 144 224 112
WIRE -208 160 -288 160
WIRE -64 160 -128 160
WIRE 80 160 80 16
WIRE 80 160 16 160
WIRE 112 160 112 16
WIRE 112 160 80 160
WIRE 192 160 112 160
WIRE 336 176 336 16
WIRE 336 176 256 176
WIRE 368 176 336 176
WIRE 480 176 480 128
WIRE 608 176 480 176
WIRE 192 192 128 192
WIRE -288 208 -288 160
WIRE 608 208 608 176
WIRE 480 224 480 176
WIRE 224 256 224 208
WIRE -208 304 -288 304
WIRE -64 304 -128 304
WIRE 80 304 80 160
WIRE 80 304 16 304
WIRE 480 336 480 304
WIRE -288 352 -288 304
WIRE 128 352 128 192
IOPIN 368 176 Out
SYMBOL res 32 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 200000
SYMBOL res 32 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200000
SYMBOL res 288 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf
SYMATTR Value 400000
SYMBOL voltage 480 208 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 15
SYMBOL Opamps\\OP07 224 112 R0
SYMATTR InstName U1
SYMBOL voltage -112 16 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1000)
SYMBOL voltage 480 32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 15
SYMBOL res 32 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200000
SYMBOL voltage -112 160 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 2 1000)
SYMBOL voltage -112 304 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 3 1000)
FLAG 128 352 0
FLAG 608 208 0
FLAG 480 16 Vcc
FLAG 224 112 Vcc
FLAG 480 336 Vee
FLAG 224 256 Vee
FLAG 368 176 Vout
FLAG -288 64 0
FLAG -288 208 0
FLAG -288 352 0
TEXT -152 -88 Left 2 ;Inverting Summing Amplifier (Common Gain)
TEXT -360 424 Left 2 !.tran 5ms
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1956.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1956.asy)
R2 N005 0 4.99K
C1 N004 0 1000p
Rload OUT 0 10
XU1 0 N002 MP_01 IN MP_02 N001 MP_03 MP_04 MP_05 OUT N004 N005 MP_06 MP_07 N003 LT1956 ;pnba GND)SW))Vin))Boost))))BIAS)Vc)FB)))_SHDN
D1 0 N002 1N5819
R1 OUT N005 15.4K
C3 OUT 0 100 Rser=.1
C2 N002 N001 .33
D2 OUT N001 1N914
L1 N002 OUT 5
V1 IN 0 20
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT1956.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2712 1832
WIRE 2096 1296 1984 1296
WIRE 2192 1296 2096 1296
WIRE 2384 1296 2256 1296
WIRE 1824 1328 1600 1328
WIRE 2096 1328 2096 1296
WIRE 1600 1344 1600 1328
WIRE 1824 1360 1824 1328
WIRE 1984 1360 1984 1296
WIRE 2208 1376 2176 1376
WIRE 2272 1376 2208 1376
WIRE 2384 1376 2384 1296
WIRE 2384 1376 2352 1376
WIRE 2448 1376 2384 1376
WIRE 2560 1376 2448 1376
WIRE 2208 1392 2208 1376
WIRE 2448 1392 2448 1376
WIRE 2560 1392 2560 1376
WIRE 1600 1440 1600 1424
WIRE 1744 1440 1728 1440
WIRE 2096 1440 2096 1392
WIRE 2096 1440 2064 1440
WIRE 2176 1440 2176 1376
WIRE 2176 1440 2096 1440
WIRE 2208 1488 2208 1456
WIRE 2448 1488 2448 1456
WIRE 2560 1488 2560 1472
WIRE 2384 1520 2384 1376
WIRE 2384 1520 2064 1520
WIRE 1648 1600 1616 1600
WIRE 1744 1600 1712 1600
WIRE 2384 1600 2064 1600
WIRE 2384 1616 2384 1600
WIRE 1904 1712 1904 1680
WIRE 2384 1712 2384 1696
SYMBOL cap 2080 1392 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value .33
SYMBOL VOLTAGE 1600 1328 R0
SYMATTR InstName V1
SYMATTR Value 20
SYMBOL diode 2256 1280 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N914
SYMBOL res 2544 1376 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL schottky 2192 1456 M180
WINDOW 0 34 63 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMBOL cap 1712 1584 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1000p
SYMBOL ind 2256 1392 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 5
SYMBOL RES 2368 1504 R0
SYMATTR InstName R1
SYMATTR Value 15.4K
SYMBOL polcap 2432 1392 R0
SYMATTR InstName C3
SYMATTR Value 100
SYMATTR SpiceLine Rser=.1
SYMBOL POWERPRODUCTS\\LT1956 1904 1520 R0
SYMATTR InstName U1
SYMBOL res 2368 1600 R0
SYMATTR InstName R2
SYMATTR Value 4.99K
FLAG 2208 1488 0
FLAG 2384 1712 0
FLAG 2448 1488 0
FLAG 2560 1488 0
FLAG 1904 1712 0
FLAG 1616 1600 0
FLAG 1600 1440 0
FLAG 2560 1376 OUT
FLAG 1600 1328 IN
TEXT 2088 1664 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\11e72c785e4f_FET09op.asc
* Generated by LTspice 26.0.1 for Windows.
Rg g N002 {Rg}
Vdd N001 0 {Vdd}
Rd N001 N002 {Rd}
M1 N002 g 0 0 MOSFET
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
.model MOSFET pmos(Kp=1m Vto=-4)
.param Vdd=-50 Rd=330 Rg=1Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1608 1076
WIRE 384 -128 192 -128
WIRE 192 -80 192 -128
WIRE 192 16 192 0
WIRE 192 16 -16 16
WIRE 192 32 192 16
WIRE 384 48 384 -128
WIRE -16 112 -16 16
WIRE 16 112 -16 112
WIRE 112 112 96 112
WIRE 144 112 112 112
WIRE 192 176 192 128
WIRE 384 176 384 128
WIRE 384 176 192 176
WIRE 192 208 192 176
FLAG 192 208 0
FLAG 112 112 g
SYMBOL res 112 96 R90
WINDOW 0 -10 57 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rg
SYMATTR Value {Rg}
SYMBOL voltage 384 32 R0
WINDOW 0 55 34 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdd
SYMATTR Value {Vdd}
SYMBOL res 176 -96 R0
SYMATTR InstName Rd
SYMATTR Value {Rd}
SYMBOL pmos 144 32 R0
SYMATTR InstName M1
SYMATTR Value MOSFET
TEXT 240 208 Left 2 !.op
TEXT 72 328 Left 2 !.model MOSFET pmos(Kp=1m Vto=-4)
TEXT 80 376 Left 2 !.param Vdd=-50 Rd=330 Rg=1Meg
* Z:\home\khalils\Downloads\files\data\raw_asc\529d58fe383c_parte1.asc
* Generated by LTspice 26.0.1 for Windows.
Vgs N002 0 1
M1 N001 N002 0 0 N_1u l=1u w=3u
Vds N001 0 2
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vds 0 5 0.01 Vgs 0 5 0.5
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 80 256 80
WIRE 304 128 256 128
WIRE 208 160 32 160
WIRE 32 176 32 160
WIRE 304 176 304 128
WIRE 304 176 256 176
WIRE 448 192 448 80
WIRE 256 224 256 176
WIRE 32 288 32 256
WIRE 448 320 448 272
SYMBOL voltage 448 176 R0
SYMATTR InstName Vds
SYMATTR Value 2
SYMBOL nmos4 208 80 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=3u
SYMBOL voltage 32 160 R0
SYMATTR InstName Vgs
SYMATTR Value 1
FLAG 32 288 0
FLAG 256 224 0
FLAG 448 320 0
TEXT 104 296 Left 2 !.dc Vds 0 5 0.01 Vgs 0 5 0.5
TEXT 72 48 Left 2 !.include cmosedu_models.txt