* Z:\tmp\asc_dec_bjh7r6w2\013807eeb9de_pluto-a_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M1 N006 N007 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
CBL_cap_0 bitline 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
M11 N002 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
CBL_cap_1 N005 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
M4 bitline1 N003 N002 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
R1 bitline N002 {mc(bitline_R, process_var)}
Vbl_en bl_en 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source2 VDDby2 0 {core_voltage/2}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4232 2520
WIRE -1392 -1888 -1392 -1904
WIRE -1392 -1792 -1392 -1808
WIRE 304 -1280 96 -1280
WIRE 576 -1280 304 -1280
WIRE 624 -1232 384 -1232
WIRE 384 -1152 384 -1232
WIRE -1584 -1136 -1584 -1152
WIRE 384 -1136 384 -1152
WIRE -1584 -1040 -1584 -1056
WIRE 384 -976 384 -1072
WIRE 768 -848 768 -1392
WIRE 832 -848 768 -848
WIRE 768 -656 768 -848
WIRE -512 -624 -512 -656
WIRE -512 -512 -512 -544
WIRE 768 -496 768 -656
WIRE 640 -464 432 -464
WIRE 832 -384 688 -384
WIRE 912 -384 832 -384
WIRE 1040 -384 912 -384
WIRE 832 -352 832 -384
WIRE 1040 -352 1040 -384
WIRE 912 -336 880 -336
WIRE 992 -336 960 -336
WIRE 1312 -256 1120 -256
WIRE 768 -240 768 -416
WIRE 832 -240 832 -256
WIRE 832 -240 768 -240
WIRE 912 -240 960 -336
WIRE 912 -240 832 -240
WIRE 960 -240 912 -336
WIRE 1040 -240 1040 -256
WIRE 1040 -240 960 -240
WIRE 1120 -240 1120 -256
WIRE 1120 -240 1040 -240
WIRE 768 -144 768 -240
WIRE 912 -144 768 -144
WIRE 1120 -144 1120 -240
WIRE 1120 -144 1008 -144
WIRE 880 -96 640 -96
WIRE 928 -96 880 -96
WIRE 1056 -96 928 -96
WIRE 1296 -96 1056 -96
WIRE 880 -80 880 -96
WIRE 1056 -80 1056 -96
WIRE 768 -48 768 -144
WIRE 944 -32 896 -32
WIRE 976 -32 944 -32
WIRE 1120 -32 1120 -144
WIRE 1120 -32 1072 -32
WIRE 1120 -16 1120 -32
WIRE 944 16 944 -32
WIRE 944 32 944 16
WIRE 768 80 768 -32
WIRE 832 80 768 80
WIRE 912 80 832 80
WIRE 1040 80 976 80
WIRE 1120 80 1120 -16
WIRE 1120 80 1040 80
WIRE 832 96 832 80
WIRE 1040 96 1040 80
WIRE 1312 128 1312 48
WIRE 1360 128 1312 128
WIRE 912 176 976 80
WIRE 976 176 912 80
WIRE 1360 176 1360 128
WIRE 832 224 832 192
WIRE 832 224 720 224
WIRE 960 224 832 224
WIRE 672 304 416 304
WIRE 1312 400 1312 128
SYMBOL voltage -1584 -1152 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 672 224 R0
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL cap 816 -848 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL pmos4 880 -256 R180
WINDOW 0 56 32 Invisible 2
WINDOW 3 56 72 Invisible 2
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL cap 368 -1136 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL cap 1344 176 R0
WINDOW 3 41 47 Left 2
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL nmos4 1008 -96 M270
WINDOW 0 104 24 Invisible 2
WINDOW 3 179 41 Invisible 2
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL res 752 -512 R0
WINDOW 3 36 68 Left 2
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL voltage -1392 -1904 R0
WINDOW 0 -72 21 Left 2
WINDOW 3 -99 147 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 -72 49 Left 2
SYMATTR InstName Vbl_en
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -512 -640 R0
WINDOW 123 0 0 Left 2
WINDOW 39 -71 197 Left 2
WINDOW 3 -71 169 Left 2
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
FLAG 720 272 0
FLAG 832 144 0
FLAG 960 -144 0
FLAG 848 -32 0
FLAG 1024 -32 0
FLAG 944 16 VDDby2
FLAG 720 320 0
FLAG 1120 -16 bitline1
FLAG 384 -1152 mb0
FLAG 304 -1280 ra0
FLAG 688 -432 VDD
FLAG 1040 -304 VDD
FLAG 832 -304 VDD
FLAG 688 -480 VDD
FLAG 912 -384 ACT
FLAG 832 -784 0
FLAG 1360 240 0
FLAG -1584 -1152 ra3
FLAG -1584 -1040 0
FLAG -512 -512 0
FLAG -512 -656 VDDby2
FLAG 384 -976 PV
FLAG -1392 -1792 0
FLAG -1392 -1904 bl_en
FLAG 768 -656 bitline