* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5052.asc
* Generated by LTspice 26.0.1 for Windows.
R1 IN N002 10K
R2 N002 0 10K
C1 N001 N003 0.1
C2 OUT 0 8.12
L1 N003 OUT 2.2
R4 OUT N009 34.8K
R5 N009 0 23.2K
R6 N010 0 22K
C3 N007 0 1
R7 N011 0 31.6K
C4 N005 N004 2.2n
R3 N004 0 1.82K
R8 N007 N008 10K
C5 OUT N009 47p
M1 N003 N006 0 0 BSC080N03MS
XU1 N011 N007 N007 N002 IN N001 N003 N006 N009 N005 N008 0 N010 MP_01 N007 ADP505x_chan1_2 ;pnba Rt)Sync_Mode)Vreg)EN)Vin)BST)SW)DL)FB)COMP)PWRGD)PGND)Rlim))SS12
Rload OUT 0 2
V1 IN 0 12
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3m startup
* SS12 Configuration is correct for channel 1 \nwhen NOT paralleled with channel 2
* Rlim is the resistor generally placed on DL pin to set current limit
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5052_chan1_2.asy)
.lib ADP505x_chan1_2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 1240
WIRE -192 -96 -288 -96
WIRE 80 -96 -192 -96
WIRE 448 -96 368 -96
WIRE -288 -80 -288 -96
WIRE -192 -80 -192 -96
WIRE 448 -80 448 -96
WIRE -288 16 -288 0
WIRE -192 16 -192 0
WIRE 80 16 -192 16
WIRE 448 16 448 -16
WIRE 448 16 368 16
WIRE 512 16 448 16
WIRE 656 16 592 16
WIRE 736 16 656 16
WIRE 864 16 736 16
WIRE 992 16 864 16
WIRE -192 32 -192 16
WIRE 864 32 864 16
WIRE 992 32 992 16
WIRE 448 48 448 16
WIRE 736 48 736 16
WIRE 656 96 656 16
WIRE -192 128 -192 112
WIRE -96 128 -112 128
WIRE 0 128 -16 128
WIRE 80 128 64 128
WIRE 400 128 368 128
WIRE 864 128 864 96
WIRE 992 128 992 112
WIRE 448 160 448 144
WIRE -32 240 -64 240
WIRE 80 240 48 240
WIRE 656 240 656 160
WIRE 656 240 368 240
WIRE 736 240 736 128
WIRE 736 240 656 240
WIRE 736 256 736 240
WIRE -64 352 -64 240
WIRE 80 352 -64 352
WIRE 384 352 368 352
WIRE 480 352 464 352
WIRE 736 352 736 336
WIRE -64 416 -64 352
WIRE 80 416 -64 416
WIRE -16 464 -32 464
WIRE 80 464 64 464
WIRE 400 464 368 464
WIRE 448 464 400 464
WIRE 448 480 448 464
WIRE 224 512 224 496
WIRE -64 544 -64 416
WIRE 400 544 400 464
WIRE 400 544 -64 544
WIRE 448 560 448 544
FLAG 224 512 0
FLAG -192 128 0
FLAG 448 160 0
FLAG 864 128 0
FLAG 736 352 0
FLAG 480 352 0
FLAG 448 560 0
FLAG -32 464 0
FLAG -112 128 0
FLAG 992 16 OUT
FLAG 992 128 0
FLAG -288 16 0
FLAG -288 -96 IN
SYMBOL res -208 -96 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res -208 16 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL cap 432 -80 R0
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL cap 848 32 R0
WINDOW 123 24 74 Left 2
SYMATTR InstName C2
SYMATTR Value 8.12
SYMBOL ind 496 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res 720 32 R0
SYMATTR InstName R4
SYMATTR Value 34.8K
SYMBOL res 720 240 R0
SYMATTR InstName R5
SYMATTR Value 23.2K
SYMBOL res 368 368 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 22K
SYMBOL cap 432 480 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 80 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 31.6K
SYMBOL cap 64 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL res 0 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1.82K
SYMBOL res -48 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 10K
SYMBOL cap 640 96 R0
SYMATTR InstName C5
SYMATTR Value 47p
SYMBOL nmos 400 48 R0
SYMATTR InstName M1
SYMATTR Value BSC080N03MS
SYMBOL ADP5052_chan1_2 224 192 R0
SYMATTR InstName U1
SYMBOL res 976 16 R0
SYMATTR InstName Rload
SYMATTR Value 2
SYMBOL VOLTAGE -288 -96 R0
SYMATTR InstName V1
SYMATTR Value 12
TEXT 648 512 Left 2 !.tran 3m startup
TEXT -584 384 Left 2 ;SS12 Configuration is correct for channel 1 \nwhen NOT paralleled with channel 2
TEXT 432 424 Left 2 ;Rlim is the resistor generally placed on DL pin to set current limit