Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3407A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3407A.asy)
R2 OUT1 N004 887K
V1 IN 0 5
C5 OUT1 N004 22p
C1 OUT1 0 10
L2 N001 OUT2 2.2
C3 OUT2 0 10
Rload1 OUT1 0 100
C2 IN 0 22
C4 OUT2 N003 22p
R1 N004 0 443.5K
XU1 N004 IN IN N002 0 IN N001 MP_01 IN N003 LTC3407A ;pnba FB1)Run1)Vin)SW1)GND)Mode)SW2))Run2)FB2
Rload2 OUT2 0 100
L1 N002 OUT1 2.2
R4 OUT2 N003 887K
R3 N003 0 280K
.tran 250u startup
.lib LTC3407A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1060 708
WIRE 80 32 -32 32
WIRE 176 32 80 32
WIRE 272 32 176 32
WIRE 352 32 272 32
WIRE 432 32 352 32
WIRE -32 48 -32 32
WIRE 80 64 80 32
WIRE 272 64 272 32
WIRE 352 64 352 32
WIRE 432 64 432 32
WIRE 176 128 176 32
WIRE 208 128 176 128
WIRE -32 144 -32 128
WIRE 80 144 80 128
WIRE -96 224 -208 224
WIRE -32 224 -96 224
WIRE 48 224 -32 224
WIRE 96 224 48 224
WIRE 208 224 176 224
WIRE 512 224 496 224
WIRE 624 224 592 224
WIRE 736 224 624 224
WIRE 816 224 736 224
WIRE 912 224 816 224
WIRE -208 240 -208 224
WIRE -32 240 -32 224
WIRE 48 240 48 224
WIRE 624 240 624 224
WIRE 736 240 736 224
WIRE 912 240 912 224
WIRE -96 256 -96 224
WIRE 816 256 816 224
WIRE -208 336 -208 320
WIRE -96 336 -96 320
WIRE -32 336 -32 304
WIRE 48 336 48 320
WIRE 48 336 -32 336
WIRE 208 336 48 336
WIRE 624 336 624 320
WIRE 624 336 496 336
WIRE 736 336 736 304
WIRE 736 336 624 336
WIRE 816 336 816 320
WIRE 912 336 912 320
WIRE 48 352 48 336
WIRE 624 352 624 336
WIRE 352 400 352 384
WIRE 48 448 48 432
WIRE 624 448 624 432
SYMBOL polcap 64 64 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMBOL ind 496 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res -224 224 R0
SYMATTR InstName Rload2
SYMATTR Value 100
SYMBOL res 608 336 R0
SYMATTR InstName R1
SYMATTR Value 443.5K
SYMBOL PowerProducts\\LTC3407A 352 224 R0
SYMATTR InstName U1
SYMBOL polcap -112 256 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL res 608 224 R0
SYMATTR InstName R2
SYMATTR Value 887K
SYMBOL VOLTAGE -32 32 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 720 240 R0
SYMATTR InstName C5
SYMATTR Value 22p
SYMBOL res 32 336 R0
SYMATTR InstName R3
SYMATTR Value 280K
SYMBOL ind 192 240 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 2.2
SYMBOL res 896 224 R0
SYMATTR InstName Rload1
SYMATTR Value 100
SYMBOL polcap 800 256 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL cap -48 240 R0
SYMATTR InstName C4
SYMATTR Value 22p
SYMBOL res 32 224 R0
SYMATTR InstName R4
SYMATTR Value 887K
FLAG -32 144 0
FLAG 352 400 0
FLAG 816 336 0
FLAG 912 336 0
FLAG 80 144 0
FLAG 912 224 OUT1
FLAG 624 448 0
FLAG -96 336 0
FLAG -208 336 0
FLAG -208 224 OUT2
FLAG 48 448 0
FLAG -32 32 IN
TEXT 256 456 Left 2 !.tran 250u startup
* Z:\tmp\asc_dec_bjh7r6w2\0eefa3fed958_2_stage_opamp_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vdd 0 5
V3 N001 0 SINE(0 1m 1k 0 0 0 1k) AC 1 0
M5 N003 N002 N004 N004 BSP89
R1 Vdd N002 1k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1424 740
WIRE -272 -240 -352 -240
WIRE 128 -240 -272 -240
WIRE -272 -208 -272 -240
WIRE -848 -160 -848 -192
WIRE -736 -160 -736 -192
WIRE 80 48 -80 48
WIRE 512 48 448 48
WIRE -272 80 -272 -128
WIRE -272 80 -416 80
WIRE -160 80 -272 80
WIRE -80 80 -80 48
WIRE 128 128 128 64
WIRE 160 128 128 128
WIRE 368 128 160 128
WIRE 400 128 400 64
WIRE 400 128 368 128
WIRE -272 176 -272 80
WIRE 160 176 160 128
WIRE 368 176 368 128
WIRE 512 176 512 48
WIRE -224 256 -368 256
WIRE -160 256 -160 80
WIRE -160 256 -224 256
WIRE 112 256 -160 256
WIRE 320 256 112 256
WIRE 736 256 320 256
WIRE 160 336 160 272
WIRE 160 336 -272 336
WIRE 368 336 368 272
WIRE 368 336 160 336
WIRE 784 336 368 336
SYMBOL voltage -848 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -80 64 R0
WINDOW 3 24 96 Invisible 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0 1m 1k 0 0 0 1k)
SYMATTR InstName V3
SYMATTR Value2 AC 1 0
SYMBOL nmos 320 176 R0
SYMATTR InstName M5
SYMATTR Value BSP89
SYMBOL res -288 -224 R0
SYMATTR InstName R1
SYMATTR Value 1k
FLAG -80 160 0
FLAG -848 -80 0
FLAG -736 -80 0
FLAG -848 -192 Vdd
FLAG -736 -192 Vss
FLAG -352 -240 Vdd
FLAG 512 176 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-BYP.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-BYP.asy)
XU1 IN 0 N001 OUT OUT LT1761-BYP ;pnba IN)GND)BYP)ADJ)OUT
Rload OUT 0 500
C1 OUT 0 10
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -224 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 16 144 -16 144
WIRE 336 144 336 48
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1761-BYP 160 96 R0
SYMATTR InstName U1
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -224 48 IN
TEXT 376 224 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\31c03f1b9d43_emulator-pen-lift-ct-sim.asc
* Generated by LTspice 26.0.1 for Windows.
* XR2206 SYNCO Output
* +12V DC Supply
* Switch Mode NPN BJT Transistor
V1 +12VDC 0 12V
Q1 Vpen P001 0 0 2N2222
R2 +12VDC Vpen 10k
R1 P001 Vpulse 1k
V2 Vpulse 0 PULSE(0 3 0 0 0 0.054 0.098 4)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0 0.360 0 0.020
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 -32 384 -80
WIRE 384 64 384 48
WIRE 512 64 384 64
WIRE 384 96 384 64
WIRE -160 128 -160 32
WIRE 48 128 48 32
WIRE 240 144 224 144
WIRE -160 304 -160 208
WIRE 48 304 48 208
WIRE 384 304 384 192
IOPIN 48 32 Out
IOPIN -160 32 Out
IOPIN 224 144 In
IOPIN 384 -80 In
IOPIN 512 64 Out
SYMBOL res 368 -48 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 48 112 R0
SYMATTR InstName V1
SYMATTR Value 12V
SYMBOL voltage -160 112 R0
WINDOW 3 -18 245 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 3 0 0 0 0.054 0.098 4)
SYMBOL res 336 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL npn 320 96 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
FLAG 48 32 +12VDC
FLAG 48 304 0
FLAG -160 32 Vpulse
FLAG -160 304 0
FLAG 224 144 Vpulse
FLAG 384 304 0
FLAG 384 -80 +12VDC
FLAG 512 64 Vpen
TEXT -176 378 Left 2 !.tran 0 0.360 0 0.020
TEXT -296 -120 Left 2 ;XR2206 SYNCO Output
TEXT -24 -120 Left 2 ;+12V DC Supply
TEXT 416 224 Left 2 ;Switch Mode NPN BJT Transistor
* Z:\home\khalils\Downloads\files\data\raw_asc\42e039bf86ad_fig-01-03-19.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4077-2.asy)
V2 VTH 0 3
B1 N002 0 V=2*random(time*1e4)
R2 VOUT N001 100k
R1 N001 VIN 10k
R3 0 N001 100k
VS1 VCC 0 15
XU1 NC_01 N001 NC_02 NC_03 NC_04 NC_05 NC_06 NC_07 ADA4077-2 ;pnba +INA)-INA)OUTA)V+)V-)+INB)-INB)OUTB
VS2 0 VEE 15
V1 VIN N002 PULSE(0 5 0 5m 5m 5m 20m)
.tran 0 20m 0 1u
.lib ADA4077-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 16 32 16
WIRE 304 16 240 16
WIRE 208 96 208 80
WIRE 208 144 208 96
WIRE 128 160 112 160
WIRE 176 160 128 160
WIRE 304 176 304 16
WIRE 304 176 240 176
WIRE 352 176 304 176
WIRE -128 192 -144 192
WIRE -80 192 -128 192
WIRE 32 192 32 16
WIRE 32 192 0 192
WIRE 176 192 32 192
WIRE -144 208 -144 192
WIRE 208 240 208 208
WIRE 208 256 208 240
WIRE 32 320 32 192
WIRE -144 336 -144 288
WIRE 112 352 112 160
WIRE 320 352 320 336
WIRE 384 352 384 336
WIRE 320 400 320 352
WIRE 384 400 384 352
WIRE -144 464 -144 416
WIRE 32 464 32 400
WIRE 112 464 112 432
WIRE 320 496 320 480
WIRE 384 496 384 480
IOPIN 352 176 Out
SYMBOL res 48 416 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 100k
SYMBOL voltage -144 192 R0
WINDOW 0 10 99 Left 2
WINDOW 3 58 104 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 5m 5m 5m 20m)
SYMBOL Misc\\battery 112 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL Misc\\battery 384 384 R0
WINDOW 0 12 9 Left 2
WINDOW 3 14 95 Left 2
SYMATTR InstName VS1
SYMATTR Value 15
SYMBOL Opamps\\ADA4077-2 208 112 R0
SYMATTR InstName U1
SYMBOL res 16 176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL Misc\\battery 320 496 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName VS2
SYMATTR Value 15
SYMBOL res 256 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL bv -144 320 R0
WINDOW 3 -12 184 Left 2
SYMATTR Value V=2*random(time*1e4)
SYMATTR InstName B1
FLAG -144 464 0
FLAG -128 192 VIN
FLAG 320 496 0
FLAG 384 496 0
FLAG 320 352 VEE
FLAG 384 352 VCC
FLAG 208 96 VCC
FLAG 208 240 VEE
FLAG 112 464 0
FLAG 352 176 VOUT
FLAG 128 160 VTH
FLAG 32 464 0
TEXT -112 -32 Left 2 !.tran 0 20m 0 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\19b22da50da2_Fig26_18_ID_VDS.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 0 0 N_50n l=50n w=500n
VGS N002 0 400m
VDS N001 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VDS 0 1 1m
.lib cmosedu_models.txt
* Plot Id(M1) and 1/d(Id(M1)) for output resistance
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 288 208 288 192
WIRE 288 304 288 288
WIRE 400 192 288 192
WIRE 448 112 448 80
WIRE 448 224 448 208
WIRE 496 160 448 160
WIRE 640 80 448 80
WIRE 640 112 640 80
WIRE 640 224 640 192
FLAG 288 304 0
FLAG 448 224 0
FLAG 640 224 0
FLAG 496 160 0
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 288 192 R0
WINDOW 0 -90 57 Left 0
WINDOW 3 -90 85 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 400m
SYMBOL voltage 640 96 R0
WINDOW 0 41 55 Left 0
WINDOW 3 41 83 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 0
TEXT 384 272 Left 0 !.dc VDS 0 1 1m
TEXT 384 296 Left 0 !.lib cmosedu_models.txt
TEXT 224 56 Left 0 ;Plot Id(M1) and 1/d(Id(M1)) for output resistance
* Z:\home\khalils\Downloads\files\data\raw_asc\24abba9b8c63_R1D1C1.asc
* Generated by LTspice 26.0.1 for Windows.
V1 VIN 0 SINE(0 5 1k)
C1 VOUT 0 100n
D1 N001 VOUT D
R1 N001 VIN 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 0.01 0 0.001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 -288 16 -288
WIRE 176 -288 128 -288
WIRE 288 -288 240 -288
WIRE 368 -288 288 -288
WIRE 16 -224 16 -288
WIRE 288 -208 288 -288
WIRE 16 -64 16 -144
WIRE 288 -64 288 -144
WIRE 288 -64 16 -64
WIRE 288 -32 288 -64
SYMBOL diode 176 -272 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL res 144 -304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 272 -208 R0
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL voltage 16 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1k)
FLAG 368 -288 VOUT
FLAG 288 -32 0
FLAG 288 -64 GROUND
FLAG 16 -288 VIN
TEXT 24 -48 Left 2 !.tran 0 0.01 0 0.001
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1764A-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1764A-2.5.asy)
XU1 IN IN 0 OUT OUT LT1764-2.5 ;pnba _SHDN)IN)GND)OUT)Sense
C1 OUT 0 10 Rser=.1
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 500
.tran 1
.lib LT1764.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -224 48
WIRE 16 48 0 48
WIRE 320 48 304 48
WIRE 384 48 320 48
WIRE 512 48 384 48
WIRE -224 64 -224 48
WIRE 384 64 384 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 16 144 0 144
WIRE 320 144 320 48
WIRE 320 144 304 144
WIRE -224 160 -224 144
WIRE 384 160 384 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1764A-2.5 160 96 R0
SYMATTR InstName U1
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL cap 368 64 R0
WINDOW 39 24 84 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=.1
FLAG -224 160 0
FLAG 384 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -224 48 IN
TEXT 360 248 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\26cf5cfadc66_HW05P04.asc
* Generated by LTspice 26.0.1 for Windows.
VI0 N001 N002 0
R4 N005 N002 1k
V1 N003 0 10
R1 N004 0 1k
E1 N001 0 N003 N004 100Meg
R2 N005 N004 1k
R3 0 N005 1k
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1368 680
WIRE 496 -144 432 -144
WIRE 640 -144 576 -144
WIRE 432 -112 432 -144
WIRE 384 -96 64 -96
WIRE 384 -48 224 -48
WIRE 224 48 224 -48
WIRE 288 48 224 48
WIRE 432 48 368 48
WIRE 496 48 432 48
WIRE 640 48 640 -144
WIRE 640 48 576 48
WIRE 64 112 64 -96
WIRE 224 112 224 48
WIRE 432 112 432 48
DATAFLAG 640 -144 ""
SYMBOL res 208 96 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 384 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL res 448 208 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL e 432 -128 R0
SYMATTR InstName E1
SYMATTR Value 100Meg
SYMBOL voltage 64 96 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 480 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage 480 -144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName I0
SYMATTR Value 0
FLAG 432 -32 0
FLAG 432 192 0
FLAG 224 192 0
FLAG 64 192 0
TEXT 1328 272 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3991.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N005 0 118K
R2 N007 0 562K
L1 N006 OUT 4.7
R3 OUT N007 1Meg
C1 OUT 0 22
Rout OUT 0 2.75
V1 IN 0 12
D1 0 N006 DFLS220L
C2 N004 N006 .47
R5 N001 0 1Meg
R6 IN N001 5Meg
C3 N003 0 .001
XU1 OUT N004 N006 IN N001 N007 N003 N005 N002 MP_01 0 LT3991 ;pnba BD)Boost)SW)Vin)EN)FB)SS)Rt)PG))GND
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3991.asy)
.lib LT3991.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 680
WIRE -48 -64 -208 -64
WIRE 400 -64 -48 -64
WIRE -208 -48 -208 -64
WIRE -48 -48 -48 -64
WIRE -208 48 -208 32
WIRE -48 48 -48 32
WIRE 80 48 -48 48
WIRE 400 48 400 -64
WIRE 400 48 368 48
WIRE -48 64 -48 48
WIRE 80 144 64 144
WIRE 592 144 368 144
WIRE -48 160 -48 144
WIRE 0 240 -32 240
WIRE 80 240 64 240
WIRE 400 240 368 240
WIRE 400 256 400 240
WIRE -16 336 -32 336
WIRE 80 336 64 336
WIRE 400 336 400 320
WIRE 400 336 368 336
WIRE 480 336 400 336
WIRE 592 336 592 144
WIRE 592 336 560 336
WIRE 704 336 592 336
WIRE 800 336 704 336
WIRE 400 352 400 336
WIRE 592 352 592 336
WIRE 800 352 800 336
WIRE 704 368 704 336
WIRE 80 432 64 432
WIRE 592 432 368 432
WIRE 400 448 400 416
WIRE 592 448 592 432
WIRE 704 448 704 432
WIRE 800 448 800 432
WIRE 592 544 592 528
FLAG 64 432 0
FLAG -32 336 0
FLAG 800 448 0
FLAG 704 448 0
FLAG 592 544 0
FLAG -208 48 0
FLAG 400 448 0
FLAG -48 160 0
FLAG -32 240 0
FLAG -208 -64 IN
FLAG 800 336 OUT
SYMBOL res 80 320 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 118K
SYMBOL res 576 432 R0
SYMATTR InstName R2
SYMATTR Value 562K
SYMBOL ind 464 352 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMBOL res 576 336 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL cap 688 368 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 784 336 R0
SYMATTR InstName Rout
SYMATTR Value 2.75
SYMBOL voltage -208 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL schottky 384 416 M180
WINDOW 0 26 68 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value DFLS220L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 384 256 R0
WINDOW 3 24 54 Left 2
SYMATTR Value .47
SYMATTR InstName C2
SYMBOL res -64 48 R0
SYMATTR InstName R5
SYMATTR Value 1Meg
SYMBOL res -64 -64 R0
SYMATTR InstName R6
SYMATTR Value 5Meg
SYMBOL cap 64 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL PowerProducts\\LT3991 224 240 R0
SYMATTR InstName U1
TEXT 720 536 Left 2 !.tran 1.5m startup
* Z:\tmp\asc_dec_bjh7r6w2\0cb971c3bd41_Pseudonor_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
M6 Vout B 0 0 CMOSN l=180n w=4u
V1 Vdd 0 1.8
M10 Vdd 0 Vout Vdd CMOSP l=180n w=2u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 4196 2548
WIRE 1136 464 1088 464
WIRE 1088 480 1088 464
WIRE 1184 512 1184 480
WIRE 1296 512 1184 512
WIRE 1344 512 1296 512
WIRE 1120 544 976 544
WIRE 1184 544 1184 512
WIRE 1184 544 1120 544
WIRE 1264 544 1184 544
WIRE 1408 544 1264 544
WIRE 976 576 976 544
WIRE 1120 576 1120 544
WIRE 1264 576 1264 544
WIRE 1024 624 976 624
WIRE 1168 624 1120 624
WIRE 1296 624 1264 624
WIRE 1264 656 1264 624
WIRE 976 688 976 672
WIRE 1024 688 1024 624
WIRE 1024 688 976 688
WIRE 1120 688 1120 672
WIRE 1120 688 1024 688
WIRE 1168 688 1168 624
WIRE 1168 688 1120 688
WIRE 1184 688 1168 688
WIRE 1264 688 1264 672
WIRE 1264 688 1184 688
WIRE 1296 688 1264 688
WIRE 1184 720 1184 688
SYMBOL nmos4 1072 576 R0
SYMATTR InstName M6
SYMATTR Value CMOSN
SYMATTR Value2 l=180n w=4u
SYMBOL voltage 800 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL pmos4 1136 384 R0
WINDOW 0 68 19 Left 2
WINDOW 3 57 81 Left 2
SYMATTR InstName M10
SYMATTR Value CMOSP
SYMATTR Value2 l=180n w=2u
FLAG 800 272 A
FLAG 800 96 Vdd
FLAG 1184 720 0
FLAG 1184 384 Vdd
FLAG 1088 480 0
FLAG 928 656 A
FLAG 1072 656 B
FLAG 1216 656 C
FLAG 1184 432 Vdd
FLAG 656 272 B
FLAG 800 176 0
FLAG 1296 512 Vout
* Z:\home\khalils\Downloads\files\data\raw_asc\604dcace2bb1_Vbe_break.asc
* Generated by LTspice 26.0.1 for Windows.
*Choose Is of diode 10^-10 lower than Is of transistor
* With external diode
* With subcircuit
* Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal transistor operation.
D1 E B DEB
XQ2 0 N002 N004 Q2N2907 ;pnba C)B)E
D1 N003 N001 VBEDIO
Q1 C B E 2N2907
R1 in N001 1k
Q1 0 N001 N003 0 2N2907
R4 N004 0 1k
R2 N003 0 1k
R3 in N002 1k
V1 in 0 0
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 -10 10 0.1
.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
.SUBCKT Q2N2907 C B E
.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1480 744
WIRE 304 224 304 288
WIRE 304 480 -128 480
WIRE 208 208 208 176
WIRE 208 176 240 176
WIRE 208 176 48 176
WIRE -128 480 -128 304
WIRE -128 176 -128 224
WIRE -32 176 -128 176
WIRE -128 512 -128 480
WIRE 304 128 304 48
WIRE 304 48 448 48
WIRE 448 48 448 480
WIRE 448 480 304 480
WIRE 304 416 304 480
WIRE 208 272 208 288
WIRE 208 288 304 288
WIRE 304 288 304 336
WIRE 960 224 960 336
WIRE 816 176 896 176
WIRE 960 128 960 48
WIRE 960 48 1104 48
WIRE 1104 48 1104 480
WIRE 1104 480 960 480
WIRE 960 416 960 480
WIRE 736 176 672 176
WIRE 960 512 960 480
RECTANGLE Normal 416 320 96 96
SYMBOL pnp 896 128 R0
WINDOW 3 79 79 Left 0
SYMATTR Value Q2N2907
SYMATTR InstName Q2
SYMATTR Prefix X
SYMBOL res 720 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res -48 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 944 320 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL res 288 320 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL diode 224 272 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMATTR Value VBEDIO
SYMBOL voltage -128 208 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL pnp 240 128 R0
SYMATTR InstName Q1
SYMATTR Value 2N2907
FLAG -128 512 0
FLAG -128 176 in
FLAG 672 176 in
FLAG 960 512 0
TEXT -128 -200 Left 0 !.dc V1 -10 10 0.1
TEXT -144 -8 Left 0 !.MODEL VBEDIO D(Is=1e-24 BV=5 IBV=1m RS=20)
TEXT 640 -136 Left 0 !.SUBCKT Q2N2907  C B E\nQ1 C B E  2N2907\nD1 E B DEB\n*Choose Is of diode 10^-10 lower than Is of transistor\n.MODEL DEB D(Is=1e-24 BV=5 IBV=1m RS=20)\n.ENDS
TEXT -136 -56 Left 0 ;With external diode
TEXT 640 -184 Left 0 ;With subcircuit
TEXT -144 -424 Left 0 ;Including Vbe Breakdown in Transistor Models\n \nThis requires an additional diode in parallel to the base and the emitter.\nChoose IS of the diode a factor of 10^-10 lower than IS of the transistor. \nThis avoids any impact on the normal  transistor operation.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADR4520.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\ADR4520.asy)
XU1 IN 0 OUT ADR4520 ;pnba IN)GND)OUT
C2 IN 0 0.1
V2 N002 0 PULSE(0 1 600u 10n 10n 200u 10m)
C1 OUT 0 1
S1 0 OUT N002 0 10mA
S2 OUT IN N001 0 10mA
V1 IN 0 5
V3 N001 0 PULSE(0 1 100u 10n 10n 200u 10m)
.tran 1m
.model 10mA SW(Ron=10 Roff=1Meg Vt=.5 Vh=-.2 Ilimit=10m level=2)
.lib ADR4520.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1196 680
WIRE 576 -96 80 -96
WIRE 576 -80 576 -96
WIRE 880 -64 624 -64
WIRE 992 -64 960 -64
WIRE 640 -16 624 -16
WIRE 80 32 80 -96
WIRE 80 32 -16 32
WIRE 160 32 80 32
WIRE 480 32 416 32
WIRE 576 32 576 0
WIRE 576 32 480 32
WIRE 672 32 576 32
WIRE -16 48 -16 32
WIRE 480 48 480 32
WIRE 80 64 80 32
WIRE 576 64 576 32
WIRE 880 80 624 80
WIRE 992 80 960 80
WIRE 640 128 624 128
WIRE -16 144 -16 128
WIRE 80 144 80 128
WIRE 480 144 480 112
WIRE 288 160 288 128
WIRE 576 160 576 144
SYMBOL ADR4520 288 32 R0
SYMATTR InstName U1
SYMBOL sw 576 16 R180
WINDOW 0 -11 104 Right 2
WINDOW 3 -15 14 Right 2
SYMATTR InstName S2
SYMATTR Value 10mA
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 26 86 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL cap 464 48 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 64 64 R0
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL voltage 864 80 M90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 600u 10n 10n 200u 10m)
SYMBOL sw 576 160 R180
WINDOW 0 -7 103 Right 2
WINDOW 3 -10 16 Right 2
SYMATTR InstName S1
SYMATTR Value 10mA
SYMBOL voltage 864 -64 M90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 1 100u 10n 10n 200u 10m)
SYMATTR InstName V3
FLAG -16 144 0
FLAG 288 160 0
FLAG 480 144 0
FLAG -16 32 IN
FLAG 80 144 0
FLAG 672 32 OUT
FLAG 576 160 0
FLAG 640 128 0
FLAG 992 80 0
FLAG 640 -16 0
FLAG 992 -64 0
TEXT 112 208 Left 2 !.tran 1m\n.model 10mA SW(Ron=10 Roff=1Meg Vt=.5 Vh=-.2 Ilimit=10m level=2)