* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2323-14.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 PWL(0 0 .1u 5)
C1 OUT1 0 10p
Va+ N003 0 PWL(0 0 400u 4.096)
Va- N005 0 PWL(0 4.096 400u 0)
V1 N006 0 PULSE(0 1.8 227n .1n .1n 40n 199.5n)
Vsclk1 sclk1 0 PULSE(0 1.8 9.5n .1n .1n 4.05625n 8.3125n)
Bsclk N007 0 V=if(V(sclk2)>V(sclk1),V(sclk2),V(sclk1))
Vsclk2 sclk2 0 PULSE(0 1.81 11.875n .1n .1n 66.5n 199.5n)
V3 N002 0 1.8
XU1 N001 N003 N005 NC_01 N004 N006 N007 OUT1 NC_02 N002 0 LTC2323-14 ;pnba Vdd)Ain+)Ain-)REFint)REFout1)_CNV)SCLK)Vout1)SCLKout)OVdd)GND
C2 N004 0 10 ic=4.096 Rser=10m
.tran 400u
* SCLK and _CNV\nare shown in timing\ndiagram on page 11\nof LTC2323-14 data sheet
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\LTC2323-14.asy)
.lib LTC2323-14.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2580 1252
WIRE 176 0 128 0
WIRE 352 0 256 0
WIRE 528 0 480 0
WIRE 656 0 608 0
WIRE -416 64 -464 64
WIRE -192 64 -336 64
WIRE 352 80 352 0
WIRE 480 80 480 0
WIRE 704 80 704 64
WIRE -192 128 -192 64
WIRE 240 128 -192 128
WIRE 704 160 704 144
WIRE 704 160 592 160
WIRE 240 176 -192 176
WIRE -416 240 -464 240
WIRE -192 240 -192 176
WIRE -192 240 -336 240
WIRE 704 240 592 240
WIRE 704 256 704 240
WIRE -64 304 -96 304
WIRE 240 304 16 304
WIRE 704 336 704 320
WIRE 240 368 176 368
WIRE 176 448 176 368
WIRE 416 448 416 416
WIRE 176 560 176 528
WIRE -144 672 -144 656
WIRE 416 672 416 656
WIRE -144 768 -144 752
WIRE 416 768 416 752
FLAG 416 448 0
FLAG 704 336 0
FLAG -464 240 0
FLAG -96 304 0
FLAG -144 768 0
FLAG 416 768 0
FLAG 416 656 sclk2
FLAG -144 656 sclk1
FLAG 176 560 0
FLAG -464 64 0
FLAG 128 0 0
FLAG 656 0 0
FLAG 704 240 OUT1
FLAG 704 64 0
SYMBOL voltage 272 0 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 -68 56 VBottom 2
WINDOW 39 -50 56 VBottom 2
SYMATTR InstName V2
SYMATTR Value PWL(0 0 .1u 5)
SYMBOL cap 688 256 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage -320 64 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Va+
SYMATTR Value PWL(0 0 400u 4.096)
SYMBOL voltage -320 240 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName Va-
SYMATTR Value PWL(0 4.096 400u 0)
SYMBOL voltage 32 304 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1.8 227n .1n .1n 40n 199.5n)
SYMBOL voltage -144 656 R0
SYMATTR InstName Vsclk1
SYMATTR Value PULSE(0 1.8 9.5n .1n .1n 4.05625n 8.3125n)
SYMBOL bv 176 432 R0
SYMATTR InstName Bsclk
SYMATTR Value V=if(V(sclk2)>V(sclk1),V(sclk2),V(sclk1))
SYMBOL voltage 416 656 R0
SYMATTR InstName Vsclk2
SYMATTR Value PULSE(0 1.81 11.875n .1n .1n 66.5n 199.5n)
SYMBOL voltage 512 0 M90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 68 56 VTop 2
WINDOW 39 50 56 VTop 2
SYMATTR InstName V3
SYMATTR Value 1.8
SYMBOL LTC2323-14 416 240 R0
SYMATTR InstName U1
SYMBOL cap 688 144 M180
WINDOW 0 24 56 Left 2
WINDOW 3 44 33 Left 2
WINDOW 123 30 -7 Left 2
WINDOW 39 24 12 Left 2
SYMATTR InstName C2
SYMATTR Value 10
SYMATTR Value2 ic=4.096
SYMATTR SpiceLine Rser=10m
TEXT 600 464 Left 2 !.tran 400u
TEXT -176 448 Left 2 ;SCLK and _CNV\nare shown in timing\ndiagram on page 11\nof LTC2323-14 data sheet