Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4221-2B.asc
* Generated by LTspice 26.0.1 for Windows.
C4 Gate_A 0 2.2n
C5 Gate_B 0 2.2n
R2 Gate_A N001 5.11
R3 Gate_B N006 5.11
V1 VIA 0 PULSE(0 5 0 2n 2n 5u 10u)
V4 N005 0 0
V3 N003 0 5
V6 N004 0 15
V5 N002 0 15
V2 VIB 0 PULSE(5 0 0 2n 2n 5u 10u)
XU2 VIA VIB N003 0 N005 0 N006 N004 0 N001 N002 ADuM4221-2B ;pnba VIA)VIB)VDD1)GND1)DISABLE)GNDB)VOB)VDDB)GNDA)VOA)VDDA
.tran 50u
* GND1 is modeled as common GND
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4221-2B.asy)
.lib ADuM4221-2B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 3080 680
WIRE -1808 -448 -2288 -448
WIRE -1728 -448 -1808 -448
WIRE -1120 -448 -1424 -448
WIRE -992 -448 -1040 -448
WIRE -864 -448 -992 -448
WIRE -816 -448 -864 -448
WIRE -2288 -416 -2288 -448
WIRE -992 -416 -992 -448
WIRE -1808 -384 -2192 -384
WIRE -1728 -384 -1808 -384
WIRE -1232 -384 -1424 -384
WIRE -1232 -368 -1232 -384
WIRE -2192 -352 -2192 -384
WIRE -992 -336 -992 -352
WIRE -1728 -320 -2064 -320
WIRE -1392 -320 -1424 -320
WIRE -1728 -240 -1760 -240
WIRE -1232 -240 -1424 -240
WIRE -2064 -224 -2064 -320
WIRE -1232 -224 -1232 -240
WIRE -1728 -176 -1984 -176
WIRE -1392 -176 -1424 -176
WIRE -1984 -128 -1984 -176
WIRE -1120 -112 -1424 -112
WIRE -992 -112 -1040 -112
WIRE -864 -112 -992 -112
WIRE -816 -112 -864 -112
WIRE -992 -80 -992 -112
WIRE -2288 16 -2288 -336
WIRE -2192 16 -2192 -272
WIRE -2064 16 -2064 -144
WIRE -1984 16 -1984 -48
WIRE -992 16 -992 -16
FLAG -1984 16 0
FLAG -1392 -176 0
FLAG -1232 -144 0
FLAG -864 -112 Gate_B
FLAG -864 -448 Gate_A
FLAG -992 16 0
FLAG -2288 16 0
FLAG -2064 16 0
FLAG -992 -336 0
FLAG -1808 -448 VIA
FLAG -1392 -320 0
FLAG -1760 -240 0
FLAG -1232 -288 0
FLAG -2192 16 0
FLAG -1808 -384 VIB
SYMBOL cap -1008 -416 R0
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL cap -1008 -80 R0
SYMATTR InstName C5
SYMATTR Value 2.2n
SYMBOL res -1024 -464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 5.11
SYMBOL res -1024 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 5.11
SYMBOL voltage -2288 -432 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 2n 2n 5u 10u)
SYMBOL voltage -1984 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL voltage -2064 -240 R0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage -1232 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 42 34 Left 2
WINDOW 3 45 64 Left 2
SYMATTR InstName V6
SYMATTR Value 15
SYMBOL voltage -1232 -384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 43 29 Left 2
WINDOW 3 46 61 Left 2
SYMATTR InstName V5
SYMATTR Value 15
SYMBOL voltage -2192 -368 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(5 0 0 2n 2n 5u 10u)
SYMBOL ADuM4221-2B -1568 -352 R0
SYMATTR InstName U2
TEXT -1728 -8 Left 2 !.tran 50u
TEXT -1728 -32 Left 1 ;GND1 is modeled as common GND
* Z:\home\khalils\Downloads\files\data\raw_asc\0050549bc95a_2_Rev1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 0 1
L4 N002 N001 {34/27}
I1 0 N001 AC 1 0
C1 N002 0 {1/2}
C3 N001 N003 {3/2}
L3 N003 0 {2/27}
.param f = w/(2*pi)
.step dec param w 0.001 10000 100
.ac list {f}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE -32 64 -144 64
WIRE 48 64 -32 64
WIRE 192 64 128 64
WIRE 304 64 192 64
WIRE -32 80 -32 64
WIRE -144 144 -144 64
WIRE 192 144 192 64
WIRE 304 144 304 64
WIRE -32 192 -32 144
WIRE -144 336 -144 224
WIRE -32 336 -32 272
WIRE -32 336 -144 336
WIRE 192 336 192 208
WIRE 192 336 -32 336
WIRE 304 336 304 224
WIRE 304 336 192 336
SYMBOL ind 144 48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L4
SYMATTR Value {34/27}
SYMBOL cap 176 144 R0
SYMATTR InstName C1
SYMATTR Value {1/2}
SYMBOL current -144 224 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 24 -28 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value ""
SYMATTR Value2 AC 1 0
SYMBOL cap -48 80 R0
SYMATTR InstName C3
SYMATTR Value {3/2}
SYMBOL res 288 128 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL ind -48 176 R0
SYMATTR InstName L3
SYMATTR Value {2/27}
FLAG 192 336 0
TEXT -136 368 Left 2 !.param f = w/(2*pi)\n.step dec param w 0.001 10000 100\n.ac list {f}
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8410.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8410.asy)
R1 N003 N004 604K
L1 IN N001 100
C3 N003 0 .01 Rser=10m
C2 OUT 0 .1
R2 N004 0 412K
C1 N002 0 .1
V1 IN 0 3.6 Rser=0.1
XU1 IN IN 0 N001 OUT N002 N003 N004 LT8410 ;pnba _SHDN)Vcc)GND)SW)Vout)CAP)Vref)FBP
Rload OUT 0 20K
.tran 2m startup
.lib LT8410.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1572
WIRE 1648 880 1552 880
WIRE 1664 880 1648 880
WIRE 1760 880 1744 880
WIRE 2016 880 1888 880
WIRE 1552 896 1552 880
WIRE 2016 896 2016 880
WIRE 1760 944 1760 880
WIRE 1888 944 1888 880
WIRE 2016 976 2016 960
WIRE 1552 992 1552 976
WIRE 1648 1008 1648 880
WIRE 1680 1008 1648 1008
WIRE 2208 1008 1968 1008
WIRE 2304 1008 2208 1008
WIRE 2208 1024 2208 1008
WIRE 2304 1024 2304 1008
WIRE 2000 1088 1968 1088
WIRE 2112 1088 2000 1088
WIRE 2112 1104 2112 1088
WIRE 2208 1120 2208 1088
WIRE 2304 1120 2304 1104
WIRE 1648 1168 1648 1008
WIRE 1680 1168 1648 1168
WIRE 2000 1168 1968 1168
WIRE 2000 1184 2000 1168
WIRE 2112 1184 2112 1168
WIRE 1824 1248 1824 1232
WIRE 2000 1280 2000 1264
SYMBOL VOLTAGE 1552 880 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMATTR SpiceLine Rser=0.1
SYMBOL cap 2192 1024 R0
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL RES 1984 1072 R0
SYMATTR InstName R1
SYMATTR Value 604K
SYMBOL ind 1648 896 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL res 2288 1008 R0
SYMATTR InstName Rload
SYMATTR Value 20K
SYMBOL PowerProducts\\LT8410 1824 1088 R0
SYMATTR InstName U1
SYMBOL cap 2000 896 R0
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL cap 2096 1104 R0
SYMATTR InstName C3
SYMATTR Value .01
SYMATTR SpiceLine Rser=10m
SYMBOL RES 1984 1168 R0
SYMATTR InstName R2
SYMATTR Value 412K
FLAG 2304 1008 OUT
FLAG 1824 1248 0
FLAG 1552 992 0
FLAG 1552 880 IN
FLAG 2016 976 0
FLAG 2208 1120 0
FLAG 2304 1120 0
FLAG 2000 1280 0
FLAG 2112 1184 0
TEXT 2144 1248 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4416.asc
* Generated by LTspice 26.0.1 for Windows.
* Automatic PowerPath Switchover
* Primary Supply
* Backup Supply
* LOAD
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4416.asy)
MQ2 N003 N004 N002 N002 IRF7210
V2 N008 0 10.8
Rload N003 0 100
R1 0 N005 24.9K
R3 N005 N001 221K
C1 N003 0 10
R2 N006 N005 187K
MQ1 N001 N004 N002 N002 IRF7210
V1 N001 0 PWL(0 9 1 14 2 14 3 9)
MQ3 N008 N007 N003 N003 IRF7210
XU1 N006 N005 0 0 NC_01 N007 N008 N003 N001 N004 LTC4416 ;pnba H1)E1)GND)_E2)_H2)G2)V2)Vs)V1)G1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 3.2 startup
.lib LTC4416.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 948 756
WIRE -208 0 -576 0
WIRE 304 0 -208 0
WIRE 320 0 304 0
WIRE 480 0 416 0
WIRE 608 0 576 0
WIRE 656 0 608 0
WIRE 752 0 656 0
WIRE -576 16 -576 0
WIRE -208 16 -208 0
WIRE 656 16 656 0
WIRE 752 16 752 0
WIRE 400 64 400 48
WIRE 448 64 400 64
WIRE 496 64 496 48
WIRE 496 64 448 64
WIRE -576 112 -576 96
WIRE -208 112 -208 96
WIRE -96 112 -208 112
WIRE 16 112 -96 112
WIRE 304 112 304 0
WIRE 304 112 272 112
WIRE 656 112 656 80
WIRE 752 112 752 96
WIRE -208 144 -208 112
WIRE 16 192 0 192
WIRE 448 192 448 64
WIRE 448 192 272 192
WIRE -208 240 -208 224
WIRE 16 272 0 272
WIRE 608 272 608 0
WIRE 608 272 272 272
WIRE -96 352 -96 112
WIRE -80 352 -96 352
WIRE 16 352 0 352
WIRE 432 352 272 352
WIRE 304 432 272 432
WIRE 432 448 432 352
WIRE 304 496 304 432
WIRE 304 496 -256 496
WIRE 352 496 304 496
WIRE 608 496 608 272
WIRE 608 496 448 496
WIRE -256 512 -256 496
WIRE -256 608 -256 592
SYMBOL res 736 0 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL SpecialFunctions\\LTC4416 144 272 R0
SYMATTR InstName U1
SYMBOL pmos 320 48 R270
WINDOW 0 56 53 VTop 2
WINDOW 3 -16 51 VBottom 2
SYMATTR InstName Q1
SYMATTR Value IRF7210
SYMBOL cap 640 16 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -576 0 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PWL(0 9 1 14 2 14 3 9)
SYMATTR InstName V1
SYMBOL voltage -256 496 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 10.8
SYMBOL pmos 352 448 M90
WINDOW 0 3 50 VBottom 2
WINDOW 3 53 47 VTop 2
SYMATTR InstName Q3
SYMATTR Value IRF7210
SYMBOL res -224 112 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 221K
SYMBOL res 16 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 187K
SYMBOL res -224 240 M180
WINDOW 0 43 59 Left 2
WINDOW 3 38 30 Left 2
SYMATTR InstName R1
SYMATTR Value 24.9K
SYMBOL pmos 576 48 M270
WINDOW 0 55 35 VTop 2
WINDOW 3 -18 38 VBottom 2
SYMATTR InstName Q2
SYMATTR Value IRF7210
FLAG -576 112 0
FLAG -256 608 0
FLAG 752 112 0
FLAG 656 112 0
FLAG -208 240 0
FLAG 0 192 0
FLAG 0 272 0
TEXT 32 536 Left 2 !.tran 3.2 startup
TEXT 136 -48 Bottom 2 ;Automatic PowerPath Switchover
TEXT -576 -8 Bottom 2 ;Primary Supply
TEXT -256 488 Bottom 2 ;Backup Supply
TEXT 752 0 Bottom 2 ;LOAD
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2118-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2118-1.5.asy)
Rload OUT 0 .5
XU1 IN IN IN OUT 0 0 N002 IN IN IN N001 ADP2118-x.x Rtop=600k Rbot=400k Ctop=4p ;pnba Sync/Mode)FREQ)TRK)FB)GND)PGND)SW)Pvin)Vin)EN)Pgood
R1 OUT N001 100K
L1 N002 OUT 1
V1 IN 0 5
C1 OUT 0 100
.tran 2m startup
.lib ADP2118-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1104 680
WIRE 128 0 48 0
WIRE 288 0 128 0
WIRE 48 16 48 0
WIRE 288 32 288 0
WIRE 128 64 128 0
WIRE 160 64 128 64
WIRE 496 64 416 64
WIRE 640 64 576 64
WIRE 48 112 48 96
WIRE 128 144 128 64
WIRE 160 144 128 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 640 144 640 64
WIRE 640 144 560 144
WIRE 704 144 640 144
WIRE 560 160 560 144
WIRE 704 160 704 144
WIRE 128 224 128 144
WIRE 160 224 128 224
WIRE 560 224 416 224
WIRE 560 256 560 224
WIRE 704 256 704 240
WIRE 128 304 128 224
WIRE 160 304 128 304
WIRE 640 304 640 144
WIRE 640 304 416 304
WIRE 128 384 128 304
WIRE 160 384 128 384
WIRE 288 432 288 416
SYMBOL cap 544 160 R0
WINDOW 0 21 15 Left 2
WINDOW 3 22 48 Left 2
SYMATTR InstName C1
SYMATTR Value 100
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL res 592 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL ADP2118-1.5 288 272 R0
SYMATTR InstName U1
SYMBOL res 688 144 R0
SYMATTR InstName Rload
SYMATTR Value .5
SYMBOL voltage 48 0 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 560 256 0
FLAG 288 432 0
FLAG 48 112 0
FLAG 704 144 OUT
FLAG 704 256 0
FLAG 48 0 IN
TEXT 512 384 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4608A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4608A.asy)
XU1 OUT 0 NC_01 IN MP_02 NC_03 MP_04 MP_05 MP_06 NC_07 NC_08 NC_09 0 MP_10 MP_11 MP_12 MP_13 MP_14 MP_15 NC_16 NC_17 NC_18 MP_19 MP_20 MP_21 MP_22 MP_23 MP_24 N001 IN MP_25 NC_26 0 IN MP_27 MP_28 IN NC_29 LTM4608 ;pnba Vout)SGND)PLLLPF)Vin))SW))))Mode)CLKin)PHmode)GND)))))))MGN)Bsel)Pgood)))))))FB)Track))Ith)IthM)SVin)))Run)CLKout
Rload OUT 0 .225
V1 IN 0 3.6
C1 OUT 0 100
R2 N001 0 4.87K
.tran 200u startup
.lib LTM4608.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1260 708
WIRE -48 16 -192 16
WIRE 80 16 -48 16
WIRE 272 16 80 16
WIRE -192 32 -192 16
WIRE 80 48 80 16
WIRE 272 48 272 16
WIRE 432 112 368 112
WIRE 528 112 432 112
WIRE -192 128 -192 112
WIRE 432 128 432 112
WIRE 528 128 528 112
WIRE -48 192 -48 16
WIRE -16 192 -48 192
WIRE 432 224 432 192
WIRE 528 224 528 208
WIRE -48 272 -48 192
WIRE -16 272 -48 272
WIRE 432 272 368 272
WIRE 432 288 432 272
WIRE 432 384 432 368
WIRE 384 432 368 432
WIRE 80 672 80 656
WIRE 272 672 272 656
SYMBOL res 512 112 R0
SYMATTR InstName Rload
SYMATTR Value .225
SYMBOL voltage -192 16 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL PowerProducts\\LTM4608A 176 352 R0
SYMATTR InstName U1
SYMBOL cap 416 128 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMBOL res 416 272 R0
SYMATTR InstName R2
SYMATTR Value 4.87K
FLAG 80 672 0
FLAG 272 672 0
FLAG -192 128 0
FLAG 432 224 0
FLAG 528 224 0
FLAG 432 384 0
FLAG 384 432 0
FLAG 528 112 OUT
FLAG -192 16 IN
TEXT 432 600 Left 2 !.tran 200u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1529-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1529-5.asy)
Rload OUT 0 500
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 47
XU1 OUT OUT 0 IN IN LT1529-5 ;pnba OUT)Sense)GND)_SHDN)Vin
.tran 1
.lib LT1529.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 176 -192 176
WIRE 32 176 16 176
WIRE 368 176 320 176
WIRE 416 176 368 176
WIRE 512 176 416 176
WIRE -192 192 -192 176
WIRE 416 192 416 176
WIRE 512 192 512 176
WIRE 16 272 16 176
WIRE 32 272 16 272
WIRE 368 272 368 176
WIRE 368 272 320 272
WIRE -192 288 -192 272
WIRE 416 288 416 256
WIRE 512 288 512 272
WIRE 176 368 176 336
SYMBOL res 496 176 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL cap 400 192 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMBOL voltage -192 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1529-5 176 224 R0
SYMATTR InstName U1
FLAG -192 288 0
FLAG 176 368 0
FLAG 416 288 0
FLAG 512 288 0
FLAG -192 176 IN
FLAG 512 176 OUT
TEXT 376 352 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\1ac268ca4ced_LS_ADC_Analog_Frontend.asc
* Generated by LTspice 26.0.1 for Windows.
* .tran 0 10u
C4 V_ADCin+ V_ADCin- 100n
R1 V_ADCin- V_ADCin+ 20k
R8 Vin+ V_ADCin+ 5k15
V3 Vin+ 0 SINE(2.5 2.5 500) AC 1
R2 0 V_ADCin- 5k15
.ac dec 1000 1 1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3168 1620
WIRE -640 64 -640 32
WIRE -432 304 -464 304
WIRE -224 304 -352 304
WIRE -144 304 -224 304
WIRE -64 304 -144 304
WIRE -224 320 -224 304
WIRE -144 320 -144 304
WIRE -432 400 -496 400
WIRE -224 400 -352 400
WIRE -144 400 -144 384
WIRE -144 400 -224 400
WIRE -64 400 -144 400
WIRE -496 432 -496 400
SYMBOL res -448 416 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 5k15
SYMBOL voltage -640 -64 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMATTR Value SINE(2.5 2.5 500)
SYMBOL cap -160 320 R0
SYMATTR InstName C4
SYMATTR Value 100n
SYMBOL res -208 416 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R1
SYMATTR Value 20k
SYMBOL res -448 320 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 5k15
FLAG -464 304 Vin+
FLAG -640 64 0
FLAG -640 -48 Vin+
FLAG -64 304 V_ADCin+
FLAG -496 432 0
FLAG -64 400 V_ADCin-
TEXT -256 608 Left 2 ;.tran 0 10u
TEXT -256 576 Left 2 !.ac dec 1000 1 1k
* Z:\home\khalils\Downloads\files\data\raw_asc\19b22da50da2_Fig26_18_ID_VDS.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1) and 1/d(Id(M1)) for output resistance
M1 N001 N002 0 0 N_50n l=50n w=500n
VDS N001 0 0
VGS N002 0 400m
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VDS 0 1 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 288 208 288 192
WIRE 288 304 288 288
WIRE 400 192 288 192
WIRE 448 112 448 80
WIRE 448 224 448 208
WIRE 496 160 448 160
WIRE 640 80 448 80
WIRE 640 112 640 80
WIRE 640 224 640 192
SYMBOL voltage 640 96 R0
WINDOW 0 41 55 Left 0
WINDOW 3 41 83 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 0
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 288 192 R0
WINDOW 0 -90 57 Left 0
WINDOW 3 -90 85 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 400m
FLAG 288 304 0
FLAG 448 224 0
FLAG 640 224 0
FLAG 496 160 0
TEXT 384 272 Left 0 !.dc VDS 0 1 1m
TEXT 384 296 Left 0 !.lib cmosedu_models.txt
TEXT 224 56 Left 0 ;Plot Id(M1) and 1/d(Id(M1)) for output resistance
* Z:\home\khalils\Downloads\files\data\raw_asc\6df6d302ac2a_EDM_Powersupply_kicad_test.asc
* Generated by LTspice 26.0.1 for Windows.
* Bipolar gate driver and high-side switching
R3 N001 N002 10
R1 gate N003 10
V4 N001 0 100
XM1 drain gate 0 IPW65R037C6_L0 ;pnba D)G)S
R2 gate 0 10k
V1 N003 0 PULSE(0 5 0 2n 2n 2u 20u)
L1 N002 drain 6.4
.include C:\Users\joey2\Documents\3e jaar\BAP\Github\EDM_Powersupply\Library\IPW65R037C6_mosfet\SimulationModel_CoolMOS_C6_MOSFET_650V_Spice.lib
.tran 0 100u 0 10n
.model NMOS NMOS(vto=2.5 kp=150)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1356 732
WIRE 144 32 48 32
WIRE 144 128 144 112
WIRE 144 272 144 208
WIRE 144 288 144 272
WIRE -224 368 -256 368
WIRE -96 368 -144 368
WIRE 64 368 -96 368
WIRE 96 368 64 368
WIRE 144 400 144 384
WIRE -256 432 -256 368
WIRE 144 496 144 400
WIRE -256 560 -256 512
SYMBOL res -112 352 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL ind 128 112 R0
SYMATTR InstName L1
SYMATTR Value 6.4u
SYMBOL res 128 16 R0
SYMATTR InstName R3
SYMATTR Value 10
SYMBOL nmos 96 288 R0
SYMATTR InstName M1
SYMATTR Value IPW65R037C6_L0
SYMATTR Prefix X
SYMBOL res -128 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage -256 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -51 153 VLeft 2
SYMATTR Value PULSE(0 5 0 2n 2n 2u 20u)
SYMATTR InstName V1
SYMBOL voltage 64 32 R90
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 100
FLAG -256 560 0
FLAG 144 272 drain
FLAG 144 400 source
FLAG -96 448 0
FLAG -32 32 0
FLAG 144 496 0
FLAG 64 368 gate
TEXT -736 664 Left 2 !.include C:\\Users\\joey2\\Documents\\3e jaar\\BAP\\Github\\EDM_Powersupply\\Library\\IPW65R037C6_mosfet\\SimulationModel_CoolMOS_C6_MOSFET_650V_Spice.lib
TEXT -736 632 Left 2 !.tran 0 100u 0 10n
TEXT -728 720 Left 2 !.model NMOS NMOS(vto=2.5 kp=150)
TEXT -88 -144 Left 2 ;Bipolar gate driver and high-side switching
* Z:\home\khalils\Downloads\files\data\raw_asc\136dca42c4fa_Fig1_16.asc
* Generated by LTspice 26.0.1 for Windows.
Vin Vin 0 1
R1 Vin Vout 1k
R2 Vout 0 2k
.dc Vin 0 1 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 48 224 0 224
WIRE 112 224 48 224
WIRE 256 224 192 224
WIRE 288 224 256 224
WIRE 0 240 0 224
WIRE 288 240 288 224
WIRE 0 336 0 320
WIRE 288 336 288 320
FLAG 0 336 0
FLAG 288 336 0
FLAG 256 224 Vout
FLAG 48 224 Vin
SYMBOL voltage 0 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value 1
SYMBOL res 96 240 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 272 224 R0
SYMATTR InstName R2
SYMATTR Value 2k
TEXT 40 400 Left 0 !.dc Vin 0 1 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5685R.asc
* Generated by LTspice 26.0.1 for Windows.
* .dc I1 0 40m 1m
* .ac oct 100 1u 1G
* Gain parameter can be 1 or 2
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5685R.asy)
Vdac1 NC_01 0 1.25
I1 0 0 100 AC 1
XU2 vDAC Vdd 0 vOUT AD5685R Gain=2 ;pnba Vdac)Vdd)GND)Vout
V1 Vdd 0 5
CLOAD vOUT 0 10n
Vdac vDAC 0 PWL(0 0.625 10u 0.625 +1u 1.875)
.tran 200u
.lib AD5685R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE -240 -208 -240 -240
WIRE -240 -80 -240 -128
WIRE -240 -32 -240 -80
WIRE -800 112 -1008 112
WIRE -528 112 -800 112
WIRE -368 112 -528 112
WIRE 192 112 0 112
WIRE 272 112 192 112
WIRE 464 112 272 112
WIRE -800 144 -800 112
WIRE 272 160 272 112
WIRE -1008 256 -1008 224
WIRE -800 256 -800 224
WIRE 272 256 272 224
WIRE 464 256 464 240
WIRE 464 256 272 256
WIRE 272 272 272 256
WIRE -240 288 -240 256
SYMBOL voltage -800 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac
SYMATTR Value PWL(0 0.625 10u 0.625 +1u 1.875)
SYMBOL AD5685R -208 112 R0
SYMATTR InstName U2
SYMBOL voltage -1008 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdac1
SYMATTR Value 1.25
SYMBOL voltage -240 -112 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL current 464 160 R0
WINDOW 123 24 108 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName I1
SYMATTR Value 100
SYMBOL cap 256 160 R0
SYMATTR InstName CLOAD
SYMATTR Value 10n
FLAG 192 112 vOUT
FLAG -800 256 0
FLAG -528 112 vDAC
FLAG -240 -240 0
FLAG -240 288 0
FLAG 272 272 0
FLAG -240 -80 Vdd
FLAG -1008 256 0
FLAG 464 160 0
TEXT -160 312 Left 2 !.tran 200u
TEXT -160 360 Left 2 ;.dc I1 0 40m 1m
TEXT -160 408 Left 2 ;.ac oct 100 1u 1G
TEXT -632 368 Left 2 ;Gain parameter can be 1 or 2
* Z:\tmp\asc_dec_bjh7r6w2\040d94d41d7a_fa1_top2bit_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
C1[1] N002 0 20p
R1[0] N001 0 200k
C1[0] N001 0 20p
R1[1] N002 0 200k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2652 1172
WIRE 784 480 784 448
WIRE 1008 480 1008 448
WIRE 784 592 784 560
WIRE 784 592 736 592
WIRE 832 592 784 592
WIRE 1008 592 1008 560
WIRE 1008 592 960 592
WIRE 1056 592 1008 592
WIRE 832 624 832 592
WIRE 1056 624 1056 592
WIRE 736 640 736 592
WIRE 960 640 960 592
WIRE 736 736 736 704
WIRE 784 736 736 736
WIRE 832 736 832 704
WIRE 832 736 784 736
WIRE 960 736 960 704
WIRE 1008 736 960 736
WIRE 1056 736 1056 704
WIRE 1056 736 1008 736
WIRE 784 784 784 736
WIRE 1008 784 1008 736
SYMBOL cap 944 640 R0
SYMATTR InstName C1[1]
SYMATTR Value 20p
SYMBOL res 816 608 R0
SYMATTR InstName R1[0]
SYMATTR Value 200k
SYMBOL cap 720 640 R0
SYMATTR InstName C1[0]
SYMATTR Value 20p
SYMBOL res 1040 608 R0
SYMATTR InstName R1[1]
SYMATTR Value 200k
FLAG 784 448 S[0]
FLAG 784 784 0
FLAG 1008 448 S[1]
FLAG 1008 784 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-5.asy)
V1 IN 0 PWL(0 0 1 10)
C1 OUT 0 10
XU1 IN 0 IN N001 OUT LT1761-5 ;pnba IN)GND)_SHDN)BYP)OUT
Rload OUT 0 500
C2 OUT N001 .01
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 48 -224 48
WIRE 16 48 -16 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE -16 144 -16 48
WIRE 16 144 -16 144
WIRE 336 144 336 128
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL PowerProducts\\LT1761-5 160 96 R0
SYMATTR InstName U1
SYMBOL cap 320 64 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG -224 48 IN
FLAG 512 48 OUT
TEXT 376 216 Left 2 !.tran 1