Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD3542R.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N002 0 5
V2 N001 0 5
V3 N004 0 -5
R1 Vout 0 1k noiseless
V4 vDAC 0 SINE(1.25 1.25 1MEG)
V5 NC_01 0 2.5
V6 NC_02 0 PWL(0 0 2u 0 +1n 2.5)
C1 Vout N003 10p
XU2 Vout NC_03 Vout Vout vDAC N001 0 N002 N004 N003 AD3542R RANGE_SEL=0 ;pnba RFBx4)RFBx2)RFBx1)Vout)VDAC)AVDD)AGND)PVDD)PVSS)CAP
.tran 0 5u 0 1n
* .noise V(Vout) V5 dec 10 0.1 1g
* VDAC input should be within the range 0 to 2.5V\nRANGE_SEL should be an integer within 0 to 4
* Range RFB RANGE_SEL \n0 to 2.5V 1x 0 \n0 to 5V 1x 1\n0 to 10V 2x 2\n-5 to 5V 2x 3\n-2.5 to 7.5V 2x 4
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD3542R.asy)
.lib AD3542R.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 728
WIRE 224 -96 -240 -96
WIRE 128 -48 -64 -48
WIRE -240 -32 -240 -96
WIRE -64 -32 -64 -48
WIRE 128 0 128 -48
WIRE 224 0 224 -96
WIRE 640 48 352 48
WIRE -240 64 -240 48
WIRE -64 64 -64 48
WIRE 640 144 640 48
WIRE 640 144 416 144
WIRE -16 176 -704 176
WIRE 64 176 -16 176
WIRE 592 176 432 176
WIRE 640 176 640 144
WIRE 640 176 592 176
WIRE -704 224 -704 176
WIRE 480 256 384 256
WIRE 640 256 640 176
WIRE 640 256 544 256
WIRE -704 336 -704 304
WIRE -384 336 -384 304
WIRE -240 336 -240 304
WIRE 640 336 640 256
WIRE 128 400 128 352
WIRE 640 464 640 416
WIRE 224 480 224 352
WIRE 224 480 128 480
WIRE 128 512 128 480
FLAG -64 64 0
FLAG -240 64 0
FLAG 128 512 0
FLAG 640 464 0
FLAG -704 336 0
FLAG -384 336 0
FLAG 592 176 Vout
FLAG -240 336 0
FLAG -16 176 vDAC
SYMBOL voltage -64 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -240 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage 128 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value -5
SYMBOL res 624 320 R0
SYMATTR InstName R1
SYMATTR Value 1k noiseless
SYMBOL voltage -704 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value SINE(1.25 1.25 1MEG)
SYMBOL voltage -384 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 2.5
SYMBOL voltage -240 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value PWL(0 0 2u 0 +1n 2.5)
SYMBOL cap 544 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL AD3542R 224 176 R0
SYMATTR InstName U2
SYMATTR Value AD3542R
TEXT -272 536 Left 2 !.tran 0 5u 0 1n
TEXT -272 592 Left 2 ;.noise V(Vout) V5 dec 10 0.1 1g
TEXT -840 432 Left 2 ;VDAC input should be within the range 0 to 2.5V\nRANGE_SEL should be an integer within 0 to 4
TEXT -840 -104 Left 2 ;Range              RFB            RANGE_SEL \n0 to 2.5V            1x                       0           \n0 to 5V               1x                       1\n0 to 10V             2x                       2\n-5 to 5V              2x                       3\n-2.5 to 7.5V        2x                       4
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3591.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3591.asy)
L1 IN N001 22 Rpar=2K
D1 N002 0 NSPW500BS N=7
V1 IN 0 5
XU1 IN 0 N001 N004 N002 N003 LT3591 ;pnba Vin)GND)SW)Cap)LED)CTRL
V2 N003 0 PULSE(.5 1.25 .2m .2m .2m 1m 2.4m)
C1 N004 0 2.2
R1 N004 N002 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT3591.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2532 1864
WIRE 1616 1248 1536 1248
WIRE 1664 1248 1616 1248
WIRE 1760 1248 1744 1248
WIRE 1536 1264 1536 1248
WIRE 1760 1296 1760 1248
WIRE 1536 1360 1536 1344
WIRE 1616 1360 1616 1248
WIRE 1632 1360 1616 1360
WIRE 1920 1360 1888 1360
WIRE 2064 1360 1920 1360
WIRE 1920 1376 1920 1360
WIRE 2064 1392 2064 1360
WIRE 1632 1472 1552 1472
WIRE 1920 1472 1920 1456
WIRE 1920 1472 1888 1472
WIRE 1920 1488 1920 1472
WIRE 2064 1504 2064 1456
WIRE 1552 1520 1552 1472
WIRE 1760 1552 1760 1536
WIRE 1920 1568 1920 1552
WIRE 1552 1632 1552 1600
SYMBOL VOLTAGE 1536 1248 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 1904 1488 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL ind 1648 1264 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 22
SYMATTR SpiceLine Rpar=2K
SYMBOL res 1904 1472 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL PowerProducts\\LT3591 1760 1408 R0
SYMATTR InstName U1
SYMBOL LED 2048 1392 R0
WINDOW 123 24 85 Left 2
SYMATTR InstName D1
SYMATTR Value NSPW500BS
SYMATTR Description Diode
SYMATTR Type diode
SYMATTR Value2 N=7
SYMBOL voltage 1552 1504 R0
WINDOW 123 32 56 VTop 2
WINDOW 39 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(.5 1.25 .2m .2m .2m 1m 2.4m)
FLAG 1760 1552 0
FLAG 1536 1360 0
FLAG 1920 1568 0
FLAG 1552 1632 0
FLAG 1536 1248 IN
FLAG 2064 1504 0
TEXT 2120 1616 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\13c820cefbe1_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
* Tau=69.12n/1m=69.12uS
L1 N001 N002 {L} Rpar=1e37
V1 N001 0 SINE(0 1 {Fre})
C1 N002 0 {C} Rpar=1e37
.param Fre=1/(2*pi*sqrt(L*C))
.param L=69.12n C=19p
.tran 0 70u 0 1n
.opt reltol=1p vntol=1n abstol=1f
.opt itl4=500 chgtol=0.01f
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 48 112 48
WIRE 112 64 112 48
WIRE 304 144 304 128
WIRE 112 176 112 144
SYMBOL voltage 112 48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 {Fre})
SYMBOL cap 288 144 R0
SYMATTR InstName C1
SYMATTR Value {C}
SYMATTR SpiceLine Rpar=1e37
SYMBOL ind 288 32 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMATTR SpiceLine Rpar=1e37
FLAG 304 208 0
FLAG 112 176 0
TEXT 88 -8 Left 2 !.param Fre=1/(2*pi*sqrt(L*C))
TEXT 88 -48 Left 2 !.param L=69.12n C=19p
TEXT 78 232 Left 2 !.tran 0 70u 0 1n
TEXT 128 -88 Left 2 !.opt reltol=1p vntol=1n abstol=1f
TEXT 208 24 Left 2 ;Tau=69.12n/1m=69.12uS
TEXT 128 -120 Left 2 !.opt itl4=500 chgtol=0.01f
* Z:\home\khalils\Downloads\files\data\raw_asc\44b1a907ac46_half_wave_rectifier.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 0 10k
D1 N001 N002 D
V1 N001 0 SINE(0 5 100)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 48 -16 48
WIRE 320 48 192 48
WIRE -16 112 -16 48
WIRE 320 112 320 48
WIRE -16 240 -16 192
WIRE 320 240 320 192
WIRE 320 240 -16 240
SYMBOL diode 128 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL voltage -16 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 5 100)
SYMBOL res 304 96 R0
SYMATTR InstName R1
SYMATTR Value 10k
FLAG 320 240 0
TEXT -48 264 Left 2 !.tran 0.05
* Z:\home\khalils\Downloads\files\data\raw_asc\076e083f7095_Q4.asc
* Generated by LTspice 26.0.1 for Windows.
Vds N001 0 1.8
Vgs N002 0 {Vgs}
M1 N001 N002 0 0 nch_tt l=10u w=15u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
.dc Vds 0 1.8 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 624 -64 352 -64
WIRE 352 16 352 -64
WIRE 624 32 624 -64
WIRE 304 96 96 96
WIRE 96 144 96 96
WIRE 96 352 96 224
WIRE 352 352 352 112
WIRE 352 352 96 352
WIRE 624 352 624 112
WIRE 624 352 352 352
WIRE 352 384 352 352
SYMBOL nmos 304 16 R0
SYMATTR InstName M1
SYMATTR Value nch_tt
SYMATTR Value2 l=10u w=15u
SYMBOL voltage 624 16 R0
SYMATTR InstName Vds
SYMATTR Value 1.8
SYMBOL voltage 96 128 R0
SYMATTR InstName Vgs
SYMATTR Value {Vgs}
FLAG 352 384 0
TEXT -200 80 Left 2 !.include TSMC180.lib
TEXT -416 128 Left 2 !.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
TEXT -184 168 Left 2 !.dc Vds 0 1.8 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\2387f5be90c0_curvetrace.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
V1 N001 0 0.
Q1 N001 N002 0 0 2N2222
I1 0 N002 0.
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 10 10m I1 0 100u 10u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2472 1528
WIRE 2128 1152 1984 1152
WIRE 1984 1200 1984 1152
WIRE 2128 1216 2128 1152
WIRE 1920 1248 1840 1248
WIRE 1840 1264 1840 1248
WIRE 1840 1360 1840 1344
WIRE 1984 1360 1984 1296
WIRE 2128 1360 2128 1296
SYMBOL current 1840 1344 M180
WINDOW 0 23 79 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName I1
SYMATTR Value 0.
SYMBOL voltage 2128 1200 R0
SYMATTR InstName V1
SYMATTR Value 0.
SYMBOL npn 1920 1200 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
FLAG 2128 1360 0
FLAG 1984 1360 0
FLAG 1840 1360 0
TEXT 1824 1416 Left 0 !.dc V1 0 10 10m I1 0 100u 10u
TEXT 1512 1480 Left 0 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\3b9164f95d34_Noninverting_Summer.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
V1 vcc 0 15
XU1 N002 N001 vcc vee out level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R3 N001 0 10k
R2 N002 N004 10k
R1 N002 N003 10k
V2 vee 0 -15
V3 N003 0 1
R4 out N001 10k
V4 N004 0 2
.tran 5m
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -80 0 -112 0
WIRE 32 0 0 0
WIRE 112 0 32 0
WIRE 256 0 192 0
WIRE 160 80 144 80
WIRE -112 112 -112 0
WIRE 160 112 160 80
WIRE 32 128 32 0
WIRE 128 128 32 128
WIRE 256 144 256 0
WIRE 256 144 192 144
WIRE 320 144 256 144
WIRE 128 160 32 160
WIRE -96 224 -336 224
WIRE 32 224 32 160
WIRE 32 224 -16 224
WIRE 160 224 160 176
WIRE 160 224 144 224
WIRE -336 240 -336 224
WIRE 416 288 384 288
WIRE 544 288 512 288
WIRE -96 320 -224 320
WIRE 32 320 32 224
WIRE 32 320 -16 320
WIRE 416 336 416 288
WIRE 544 336 544 288
WIRE -336 352 -336 320
WIRE -224 352 -224 320
WIRE 416 448 416 416
WIRE 544 448 544 416
WIRE -224 464 -224 432
SYMBOL res 16 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 0 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage 544 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -224 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 2
SYMBOL voltage 416 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL OpAmps\\UniversalOpAmp2 160 144 R0
SYMATTR InstName U1
SYMBOL res 0 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -336 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL res 208 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
FLAG 416 448 0
FLAG 544 448 0
FLAG 384 288 vcc
FLAG 512 288 vee
FLAG 144 80 vcc
FLAG 144 224 vee
FLAG 320 144 out
FLAG -336 352 0
FLAG -224 464 0
FLAG -112 112 0
TEXT 224 456 Left 2 !.tran 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6658-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6658-1.2.asy)
C1 N001 0 1
C2 OUT2 0 1
C3 OUT1 0 1
XU1 IN IN IN IN N001 OUT1 OUT1 OUT2 OUT2 0 N002 LT6658-1.2 ;pnba Vin)Vin1)Vin2)_OD)Bypass)Vout1_F)Vout1_S)Vout2_F)Vout2_S)Gnd)NR
V3 IN 0 PWL(0 0 100u 0 +2u 4.5)
.tran 500u
.lib LT6658.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1448 1048
WIRE 16 -32 -336 -32
WIRE 128 -32 16 -32
WIRE 224 -32 128 -32
WIRE 320 -32 224 -32
WIRE -336 0 -336 -32
WIRE 128 0 128 -32
WIRE 224 0 224 -32
WIRE 320 0 320 -32
WIRE 432 64 416 64
WIRE 496 64 432 64
WIRE 496 80 496 64
WIRE -336 96 -336 80
WIRE 432 144 432 64
WIRE 432 144 416 144
WIRE 496 160 496 144
WIRE 16 192 16 -32
WIRE 48 192 16 192
WIRE 432 224 416 224
WIRE 480 224 432 224
WIRE 480 240 480 224
WIRE 432 304 432 224
WIRE 432 304 416 304
WIRE 480 320 480 304
WIRE 128 400 128 384
WIRE 224 400 224 384
WIRE 320 400 320 384
WIRE 224 480 224 464
SYMBOL voltage -336 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 0 100u 0 +2u 4.5)
SYMBOL cap 208 400 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 464 240 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 480 80 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL LT6658-1.2 224 192 R0
SYMATTR InstName U1
FLAG 128 400 0
FLAG 224 480 0
FLAG -336 96 0
FLAG 496 160 0
FLAG 480 320 0
FLAG -336 -32 IN
FLAG 496 64 OUT2
FLAG 480 224 OUT1
TEXT 464 464 Left 2 !.tran 500u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3225.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\n \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capcitance is scaled down from its real value.\n \n2. Load capcitor initial condion can be given to mimic the specific \nresidual voltage at the beginning of the charging.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3225.asy)
R1 N003 0 12K
C1 N001 N002 1
XU1 N001 N002 Cx IN NC_01 0 N003 0 IN OUT LTC3225 ;pnba C+)C-)Cx)_SHDN)Pgood)Vsel)Prog)GND)Vin)Cout
C2 OUT Cx .1m
V1 IN 0 3.2
C3 Cx 0 .1m
.tran 1m startup
.ic V(cx)=2 V(out)=3.5
.lib LTC3225.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 704
WIRE 112 0 -16 0
WIRE 240 0 112 0
WIRE -16 16 -16 0
WIRE 240 16 240 0
WIRE 112 80 112 0
WIRE 128 80 112 80
WIRE 400 80 352 80
WIRE 400 96 400 80
WIRE -16 112 -16 96
WIRE 400 176 400 160
WIRE 400 176 352 176
WIRE 128 272 112 272
WIRE 400 272 352 272
WIRE 400 288 400 272
WIRE 32 368 16 368
WIRE 128 368 112 368
WIRE 400 368 400 352
WIRE 400 368 352 368
WIRE 400 384 400 368
WIRE 240 448 240 432
WIRE 400 464 400 448
SYMBOL res 128 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 12K
SYMBOL voltage -16 0 R0
SYMATTR InstName V1
SYMATTR Value 3.2
SYMBOL cap 384 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\LTC3225 240 224 R0
SYMATTR InstName U1
SYMBOL cap 384 288 R0
WINDOW 3 28 51 Left 2
SYMATTR Value .1m
SYMATTR InstName C2
SYMBOL cap 384 384 R0
WINDOW 0 27 13 Left 2
WINDOW 3 25 55 Left 2
SYMATTR InstName C3
SYMATTR Value .1m
FLAG 240 448 0
FLAG -16 112 0
FLAG 400 464 0
FLAG 16 368 0
FLAG 112 272 0
FLAG -16 0 IN
FLAG 400 272 OUT
FLAG 400 368 Cx
TEXT 544 384 Left 2 !.tran 1m startup\n.ic V(cx)=2 V(out)=3.5
TEXT -112 464 Left 2 ;Notes:\n \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capcitance is scaled down from its real value.\n \n2. Load capcitor initial condion can be given to mimic the specific \nresidual voltage at the beginning of the charging.
* Z:\home\khalils\Downloads\files\data\raw_asc\24fae5d7ee28_differential.asc
* Generated by LTspice 26.0.1 for Windows.
V2 vcc- 0 -30
Q4 N002 N001 vcc 0 PNP
C1 out N002 100n
Q1 N001 in N004 0 NPN
V3 in 0 SINE(0 0.460 1k)
Q6 N005 N005 vcc- 0 NPN
R4 N002 N003 2.88k
Q5 N004 N005 vcc- 0 NPN
Q2 N002 N003 N004 0 NPN
R1 vcc N005 100k
R2 out 0 450k
R3 0 N003 1k
Q3 N001 N001 vcc 0 PNP
V1 vcc 0 30
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran {t}
.param f = 1k n=16 t=n/f
.four {f} 10 8 V(out)
.meas TRAN power_Output AVG I(R_load)*V(Out) TRIG time=0 TARG time={t}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -64 160 -64
WIRE 320 -64 240 -64
WIRE 160 -32 160 -64
WIRE 320 -32 320 -64
WIRE 240 16 224 16
WIRE 256 16 240 16
WIRE 320 80 320 64
WIRE 400 80 320 80
WIRE 464 80 400 80
WIRE 544 80 528 80
WIRE 160 96 160 64
WIRE 240 96 240 16
WIRE 240 96 160 96
WIRE 160 112 160 96
WIRE 320 112 320 80
WIRE 96 160 48 160
WIRE 400 160 384 160
WIRE 432 160 400 160
WIRE 528 160 512 160
WIRE 576 160 528 160
WIRE 576 192 576 160
WIRE 160 320 160 208
WIRE 240 320 160 320
WIRE 320 320 320 208
WIRE 320 320 240 320
WIRE 144 336 48 336
WIRE 48 352 48 336
WIRE 240 352 240 320
WIRE 144 400 144 336
WIRE 144 400 112 400
WIRE 176 400 144 400
SYMBOL npn 176 352 R0
SYMATTR InstName Q5
SYMBOL pnp 224 64 R180
SYMATTR InstName Q3
SYMBOL res 32 240 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 528 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL npn 96 112 R0
SYMATTR InstName Q1
SYMBOL voltage -640 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 0.460 1k)
SYMBOL pnp 256 64 M180
SYMATTR InstName Q4
SYMBOL cap 528 64 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL npn 384 112 M0
SYMATTR InstName Q2
SYMBOL voltage -528 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -30
SYMBOL voltage -640 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL npn 112 352 M0
SYMATTR InstName Q6
SYMBOL res 384 64 R0
SYMATTR InstName R4
SYMATTR Value 2.88k
SYMBOL res 512 64 R0
SYMATTR InstName R2
SYMATTR Value 450k
FLAG 544 80 out
FLAG -640 -16 0
FLAG -528 -16 0
FLAG -640 -96 vcc
FLAG -528 -96 vcc-
FLAG 240 -64 vcc
FLAG 576 192 0
FLAG 48 160 in
FLAG -640 144 0
FLAG -640 64 in
FLAG 48 448 vcc-
FLAG 240 448 vcc-
FLAG 48 256 vcc
TEXT -672 496 Left 2 !.tran {t}
TEXT -320 -112 Left 2 !.param f = 1k n=16 t=n/f
TEXT -320 -72 Left 2 !.four {f} 10 8 V(out)
TEXT -320 -144 Left 2 !.meas TRAN power_Output AVG I(R_load)*V(Out) TRIG time=0 TARG time={t}
* Z:\home\khalils\Downloads\files\data\raw_asc\1700c48e6529_photodiode.asc
* Generated by LTspice 26.0.1 for Windows.
GIph Cathode N001 +Vl -Vl .5
Rsh Cathode N001 {Rsh}
D1 N001 Cathode PDBC156
Rs N001 Anode {Rs}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.MODEL PDBC156 D(IS=3.1e-12 N=1.03 RS=0 KF=0.01 Cjo={Cjo} M=0.13 + Vj={Vj} BV={BV})
.param Rs=3 Rsh=150MEG Cjo=10p BV=50 Vj=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2040 680
WIRE 496 64 448 64
WIRE 592 64 496 64
WIRE 656 64 592 64
WIRE 448 112 448 64
WIRE 448 112 272 112
WIRE 272 128 272 112
WIRE 448 128 448 112
WIRE 496 128 496 64
WIRE 224 144 160 144
WIRE 224 192 160 192
WIRE 272 224 272 208
WIRE 448 224 448 192
WIRE 448 224 272 224
WIRE 448 240 448 224
WIRE 496 240 496 208
WIRE 496 240 448 240
WIRE 576 240 496 240
WIRE 688 240 656 240
SYMBOL g 272 224 M180
SYMATTR InstName Iph
SYMATTR Value .5
SYMBOL res 560 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -6 55 VBottom 2
SYMATTR InstName Rs
SYMATTR Value {Rs}
SYMBOL res 480 112 R0
SYMATTR InstName Rsh
SYMATTR Value {Rsh}
SYMBOL diode 464 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value PDBC156
FLAG 592 64 Cathode
FLAG 688 240 Anode
FLAG 160 144 -Vl
FLAG 160 192 +Vl
TEXT 64 400 Left 1 !.MODEL PDBC156 D(IS=3.1e-12 N=1.03 RS=0 KF=0.01 Cjo={Cjo} M=0.13 + Vj={Vj} BV={BV})
TEXT 64 376 Left 2 !.param Rs=3 Rsh=150MEG Cjo=10p BV=50 Vj=1
* Z:\home\khalils\Downloads\files\data\raw_asc\cab8a9ba309f_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
T1 IN 0 0 OUT Td=50n Z0=50
T2 0 0 OUT 0 Td=30n Z0=150
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\c0d159906937_Draft6.asc
* Generated by LTspice 26.0.1 for Windows.
VE a 0 SINE(0 10 10)
D1 b a D
R b 0 220 tol=1 pwr=0.1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 64 80 64
WIRE 208 64 144 64
WIRE 320 64 272 64
WIRE 368 64 320 64
WIRE 80 144 80 64
WIRE 368 144 368 64
WIRE 80 256 80 224
WIRE 320 256 80 256
WIRE 368 256 368 224
WIRE 368 256 320 256
WIRE 80 272 80 256
FLAG 80 272 0
FLAG 144 64 a
FLAG 320 64 b
FLAG 320 256 c
SYMBOL voltage 80 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName E
SYMATTR Value SINE(0 10 10)
SYMBOL diode 272 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMBOL res 352 128 R0
SYMATTR InstName R
SYMATTR Value 220
SYMATTR SpiceLine tol=1 pwr=0.1
TEXT 46 296 Left 2 !.tran 1