Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4601A-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4601A-1.asy)
C1 OUT N004 100p
C2 OUT 0 100
R3 OUT N001 100K
Rload OUT 0 .625
C3 N009 0 .001
R1 N004 0 8.25K
V1 IN 0 15
R2 N008 0 392K
XU1 IN 0 OUT MP_01 OUT MP_02 MP_03 0 N001 N004 N005 N007 N006 N011 N008 N003 N002 N009 N010 N005 LTM4601-1 ;pnba Vin)PGND)Vout))Vout_LCL)))SGND)Pgood)FB)DRVcc)MARG1)MARG0)Fset)MPGM)Comp)Run)Track/SS)PLLIN)INTVcc
R5 N011 0 100K
R4 IN N002 100K
.tran 750u startup
.lib LTM4601-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1084 680
WIRE 432 -32 -144 -32
WIRE -160 -16 -256 -16
WIRE 208 -16 -160 -16
WIRE -256 0 -256 -16
WIRE 208 0 208 -16
WIRE -144 48 -144 -32
WIRE -128 48 -144 48
WIRE 16 48 -48 48
WIRE 432 48 432 -32
WIRE 432 48 400 48
WIRE -256 96 -256 80
WIRE -160 112 -160 -16
WIRE -80 112 -160 112
WIRE 16 112 0 112
WIRE 432 112 432 48
WIRE 432 112 400 112
WIRE 640 112 432 112
WIRE 736 112 640 112
WIRE 640 128 640 112
WIRE 736 128 736 112
WIRE 16 176 0 176
WIRE 432 176 400 176
WIRE 480 176 432 176
WIRE 480 192 480 176
WIRE 640 224 640 192
WIRE 736 224 736 208
WIRE 16 240 0 240
WIRE 416 240 400 240
WIRE 480 288 480 272
WIRE 0 304 0 240
WIRE 16 304 0 304
WIRE 416 304 400 304
WIRE -80 368 -96 368
WIRE 16 368 0 368
WIRE 416 368 400 368
WIRE 496 368 480 368
WIRE 16 432 0 432
WIRE 480 432 400 432
WIRE 576 432 560 432
WIRE 128 512 128 496
WIRE 288 512 288 496
SYMBOL res 720 112 R0
SYMATTR InstName Rload
SYMATTR Value .625
SYMBOL cap 416 112 R0
WINDOW 0 34 18 Left 2
WINDOW 3 35 47 Left 2
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL res 464 448 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 100K
SYMBOL PowerProducts\\LTM4601A-1 208 256 R0
SYMATTR InstName U1
SYMBOL res -96 128 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL cap 624 128 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMBOL voltage -256 -16 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 16 384 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 392K
SYMBOL res 464 176 R0
SYMATTR InstName R1
SYMATTR Value 8.25K
SYMBOL cap 416 352 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value .001
SYMBOL res -144 64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 100K
FLAG 128 512 0
FLAG 288 512 0
FLAG 480 288 0
FLAG -96 368 0
FLAG 640 224 0
FLAG 736 224 0
FLAG -256 96 0
FLAG 496 368 0
FLAG 736 112 OUT
FLAG -256 -16 IN
FLAG 576 432 0
TEXT 600 336 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG772.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSwitch shown for a logic 0 input\nOnly one channel is modeled\nBandwidth is 424 MHz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG772.asy)
V3 vIN 0 PULSE(0 3 0 1n 1n 20u 40u)
V2 vSB 0 0
V1 vSA 0 2
R1 vD 0 301
XU1 vIN vSA vD vSB +V 0 ADG772 ;pnba IN)SA)D)SB)Vdd)GND
V4 +V 0 3.3
C1 vD 0 36p
.tran 100u
.lib ADG772.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1728 -272 -2032 -272
WIRE -1696 -272 -1728 -272
WIRE -2032 -256 -2032 -272
WIRE -1472 -240 -1504 -240
WIRE -1424 -240 -1472 -240
WIRE -1312 -240 -1424 -240
WIRE -1424 -224 -1424 -240
WIRE -1312 -224 -1312 -240
WIRE -1728 -208 -1920 -208
WIRE -1696 -208 -1728 -208
WIRE -1920 -192 -1920 -208
WIRE -2032 -160 -2032 -176
WIRE -1728 -144 -1776 -144
WIRE -1696 -144 -1728 -144
WIRE -1424 -128 -1424 -144
WIRE -1312 -128 -1312 -160
WIRE -1920 -96 -1920 -112
WIRE -1776 -80 -1776 -144
WIRE -1600 -16 -1600 -32
WIRE -1776 32 -1776 0
SYMBOL voltage -1920 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL voltage -2208 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 3.3
SYMBOL voltage -1776 -96 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 1n 1n 20u 40u)
SYMATTR InstName V3
SYMBOL voltage -2032 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL res -1440 -240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL ADG772 -1600 -192 R0
SYMATTR InstName U1
SYMBOL cap -1328 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG -2032 -160 0
FLAG -1920 -96 0
FLAG -1776 32 0
FLAG -1600 -368 +V
FLAG -1424 -128 0
FLAG -1600 -16 0
FLAG -1312 -128 0
FLAG -2208 -176 0
FLAG -2208 -256 +V
FLAG -1728 -272 vSA
FLAG -1728 -208 vSB
FLAG -1728 -144 vIN
FLAG -1472 -240 vD
TEXT -1480 -24 Left 2 !.tran 100u
TEXT -2056 -584 Left 2 ;Notes:\nSwitch shown for a logic 0 input\nOnly one channel is modeled\nBandwidth is 424 MHz
* Z:\home\khalils\Downloads\files\data\raw_asc\edbaa1b488e2_Q2.asc
* Generated by LTspice 26.0.1 for Windows.
C1 Vout N001 .01
D1 0 Vout D
R1 Vout 0 1
V1 N001 0 SINE(0 10 1000)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 16 32 16
WIRE 336 16 192 16
WIRE 544 16 336 16
WIRE 624 16 544 16
WIRE 624 32 624 16
WIRE 32 112 32 16
WIRE 544 112 544 16
WIRE 336 128 336 16
WIRE 32 272 32 192
WIRE 336 272 336 192
WIRE 544 272 544 192
FLAG 624 32 Vout
IOPIN 624 32 Out
FLAG 32 272 0
FLAG 336 272 0
FLAG 544 272 0
SYMBOL cap 192 0 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .01
SYMBOL diode 352 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL res 528 96 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL Misc\\signal 32 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 1000)
TEXT 0 296 Left 2 !.tran .01
* Z:\home\khalils\Downloads\files\data\raw_asc\cb83a294a607_Draft7.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N004 0 100k
C1 N003 N002 0.0015
D1 N004 N003 D
R1 N003 0 47k
V1 N001 0 PULSE(0 6 0 5u 5u 1m 2m 100)
R3 N002 N001 4.7k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 -256 48 -256
WIRE 224 -256 192 -256
WIRE 448 -256 288 -256
WIRE 448 -192 448 -256
WIRE 448 -192 368 -192
WIRE 368 -160 368 -192
WIRE 448 -160 448 -192
WIRE 368 -48 368 -96
SYMBOL Diode 384 -96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL Res 352 -64 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL Res 432 -176 R0
SYMATTR InstName R1
SYMATTR Value 47k
SYMBOL Voltage 48 -272 R0
WINDOW 3 -231 153 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 6 0 5u 5u 1m 2m 100)
SYMBOL Res 208 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 4.7k
SYMBOL Cap 288 -272 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.0015u
FLAG 368 32 0
FLAG 448 -80 0
FLAG 48 -176 0
TEXT 664 -248 Left 2 !.tran 0.01
* Z:\tmp\asc_dec_bjh7r6w2\0a824ef51f4f_Vin_mon_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
R6 N004 0 1k1
BV2 PSU_en 0 V={if(V(Vin)>7,5,0)}
R1 N002 N003 33k
R5 N001 N002 100k
Q1 N003 N005 0 0 BC847B
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3136 1344
WIRE 128 96 -80 96
WIRE 192 96 128 96
WIRE 320 96 192 96
WIRE 192 128 192 96
WIRE 128 144 128 96
WIRE 320 208 320 96
WIRE 128 224 128 208
WIRE 192 224 192 208
WIRE 192 224 128 224
WIRE 272 224 192 224
WIRE 192 256 192 224
WIRE 192 368 192 336
WIRE 320 400 320 384
WIRE 448 400 320 400
WIRE 624 400 448 400
WIRE -192 416 -304 416
WIRE 32 416 -112 416
WIRE 128 416 32 416
WIRE 320 416 320 400
WIRE 448 416 448 400
WIRE -304 448 -304 416
WIRE 32 448 32 416
WIRE 320 512 320 496
WIRE 448 512 448 480
WIRE -304 544 -304 528
WIRE 32 544 32 528
WIRE 192 544 192 464
SYMBOL res 304 400 R0
SYMATTR InstName R6
SYMATTR Value 1k1
SYMBOL voltage -304 432 R0
SYMATTR InstName V2
SYMATTR Value V={if(V(Vin)>7,5,0)}
SYMATTR Prefix B
SYMBOL res 176 240 R0
SYMATTR InstName R1
SYMATTR Value 33k
SYMBOL res 176 112 R0
SYMATTR InstName R5
SYMATTR Value 100k
SYMBOL npn 128 368 R0
SYMATTR InstName Q1
SYMATTR Value BC847B
FLAG 32 544 0
FLAG 192 544 0
FLAG -304 544 0
FLAG 448 512 0
FLAG 320 512 0
FLAG -304 416 PSU_en
* Z:\tmp\asc_dec_bjh7r6w2\0114d40776ca_audioamp-output-cap_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V4 N001 0 3.3
C2 NC_01 N002 100n
Rf1 N003 N004 1k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2344 2032
WIRE 1152 1168 1024 1168
WIRE 864 1200 864 1184
WIRE 1008 1200 928 1200
WIRE 864 1312 864 1200
WIRE 880 1312 864 1312
WIRE 928 1312 880 1312
WIRE 1008 1312 1008 1200
WIRE 1040 1312 1008 1312
WIRE 752 1360 688 1360
WIRE 1024 1360 1024 1168
WIRE 1024 1360 1008 1360
WIRE 1008 1392 1008 1360
WIRE 752 1408 752 1360
WIRE 768 1408 752 1408
WIRE 880 1408 880 1312
WIRE 880 1408 848 1408
WIRE 976 1408 880 1408
WIRE 1040 1408 1040 1312
WIRE 1088 1408 1040 1408
WIRE 1104 1408 1088 1408
WIRE 944 1424 880 1424
WIRE 1040 1424 1040 1408
WIRE 912 1440 800 1440
WIRE 944 1440 944 1424
WIRE 976 1440 944 1440
WIRE 912 1520 912 1440
WIRE 976 1520 912 1520
WIRE 800 1536 800 1520
WIRE 880 1536 880 1424
WIRE 880 1536 800 1536
WIRE 800 1552 800 1536
SYMBOL VOLTAGE 1152 1152 R0
WINDOW 0 -77 69 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 3.3
SYMBOL cap 1152 1392 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100n
SYMBOL res 864 1392 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf1
SYMATTR Value 1k
FLAG 1008 1456 0
FLAG 1152 1248 0
* Z:\home\khalils\Downloads\files\data\raw_asc\172dba210062_Suiveur.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp.asy)
V-6V P001 0 -6
V3 V_audio 0 AC 1
V6V N002 0 6
XU1 V_audio N001 N002 P001 N001 level1 Avol=1Meg GBW=10Meg Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
.ac oct 500 1 20k
.lib UniversalOpAmp1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 432 112 416 112
WIRE 432 128 432 112
WIRE 400 160 288 160
WIRE 336 176 336 112
WIRE 288 192 288 160
WIRE 304 192 288 192
WIRE 400 208 400 160
WIRE 400 208 368 208
WIRE 304 224 224 224
SYMBOL voltage 336 224 R0
WINDOW 0 36 55 Left 2
WINDOW 3 9 17 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName -6V
SYMATTR Value -6
SYMBOL OpAmps\\UniversalOpAmp 336 208 R0
SYMATTR InstName U1
SYMBOL voltage -16 144 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL voltage 320 112 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 25 14 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName 6V
SYMATTR Value 6
FLAG 336 320 0
FLAG 432 128 0
FLAG -16 240 0
FLAG -16 160 V_audio
FLAG 224 224 V_audio
TEXT 48 344 Left 2 !.ac oct 500 1 20k
* Z:\home\khalils\Downloads\files\data\raw_asc\1fdc55414e1e_EDM_Powersupply_V4_freq.asc
* Generated by LTspice 26.0.1 for Windows.
* High-side switching
* Dumped some components here: easy for copying
* V4a: Gate driver included
+ CJO=26.5p M=0.333 N=1.45 TT=4.32u )
+IS=1.18724e-05 RS=0.0227191 N=1.22913 EG=0.645632
+XTI=0.5 BV=45 IBV=0.0001 CJO=1e-11
+VJ=0.7 M=0.5 FC=0.5 TT=0
+KF=0 AF=1
V1 N004 0 PULSE(0 5 0 20000n 20000n 2u 20u)
L1 N003 N001 6.4 IC=0A
R4 N002 N003 10
V4 N002 0 10
XM1 N001 N004 0 IPW65R070C6_L0 ;pnba D)G)S
.include C:\Users\joey2\Documents\3e jaar\BAP\Github\EDM_Powersupply\Library\IPW65R037C6_mosfet\SimulationModel_CoolMOS_C6_MOSFET_650V_Spice.lib
.tran 0 30u 0 1u
.model BZX84C6V2L D(Is=1.5n Rs=.5 Cjo=185p nbv=3 bv=6.2 Ibv=1m Vpk=6.2 mfg=OnSemi type=Zener)
.model MyIdealDiode D(Ron=0 Roff=1Meg Vfwd=0.7)
.MODEL 1N4007 D ( IS=76.9p RS=42.0m BV=1.00k IBV=5.00u
.MODEL Dmbr745 d
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1876 680
WIRE 752 -112 656 -112
WIRE 928 -112 816 -112
WIRE 656 -32 656 -112
WIRE 656 -32 624 -32
WIRE 800 -32 736 -32
WIRE 928 -32 928 -112
WIRE 928 -32 880 -32
WIRE 976 -32 928 -32
WIRE 624 48 624 -32
WIRE 624 64 624 48
WIRE 976 64 976 -32
WIRE 544 80 480 80
WIRE 544 128 544 80
WIRE 576 128 544 128
WIRE 480 144 480 80
WIRE 480 240 480 224
WIRE 624 240 624 144
WIRE 624 240 480 240
WIRE 624 256 624 240
WIRE 976 256 976 144
WIRE 976 256 624 256
WIRE 480 272 480 240
WIRE 976 272 976 256
RECTANGLE Normal 560 -256 368 -320 2
SYMBOL ind 752 -48 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 6.4u
SYMATTR SpiceLine IC=0A
SYMBOL voltage 480 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -51 153 VLeft 2
SYMATTR Value PULSE(0 5 0 20000n 20000n 2u 20u)
SYMATTR InstName V1
SYMBOL nmos 576 48 R0
SYMATTR InstName M1
SYMATTR Value IPW65R070C6_L0
SYMATTR Prefix X
SYMBOL voltage 976 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 10
SYMBOL res 896 -48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10
FLAG 480 272 0
FLAG 976 272 0
TEXT -720 520 Left 2 !.include C:\\Users\\joey2\\Documents\\3e jaar\\BAP\\Github\\EDM_Powersupply\\Library\\IPW65R037C6_mosfet\\SimulationModel_CoolMOS_C6_MOSFET_650V_Spice.lib
TEXT -720 480 Left 2 !.tran 0 30u 0 1u
TEXT 752 -224 Left 2 ;High-side switching
TEXT 1200 -72 Left 2 ;Dumped some components here: easy for copying
TEXT 1032 -160 Left 2 !.model BZX84C6V2L D(Is=1.5n Rs=.5 Cjo=185p nbv=3 bv=6.2 Ibv=1m Vpk=6.2 mfg=OnSemi type=Zener)
TEXT 1040 -128 Left 2 !.model MyIdealDiode D(Ron=0 Roff=1Meg Vfwd=0.7)
TEXT 400 -288 Left 2 ;V4a: Gate driver included
TEXT 1040 -104 Left 2 !.MODEL 1N4007 D  ( IS=76.9p RS=42.0m BV=1.00k IBV=5.00u\n+ CJO=26.5p  M=0.333 N=1.45 TT=4.32u )
TEXT 1040 -48 Left 2 !.MODEL Dmbr745 d\n+IS=1.18724e-05 RS=0.0227191 N=1.22913 EG=0.645632\n+XTI=0.5 BV=45 IBV=0.0001 CJO=1e-11\n+VJ=0.7 M=0.5 FC=0.5 TT=0\n+KF=0 AF=1
* Z:\home\khalils\Downloads\files\data\raw_asc\8b1c5cec84d7_Draft12.asc
* Generated by LTspice 26.0.1 for Windows.
R1 P001 0 100
M1 N001 N002 P001 P001 NMOS
V2 N001 0 5
V1 N002 0 3
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc V1 0 5 0.1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 -80 256 -80
WIRE 384 -48 384 -80
WIRE 384 96 384 32
WIRE 256 144 256 -80
WIRE 208 224 112 224
WIRE 256 336 256 320
WIRE 112 352 112 304
SYMBOL voltage 384 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 240 224 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 112 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL nmos 208 144 R0
SYMATTR InstName M1
FLAG 112 352 0
FLAG 384 96 0
FLAG 256 336 0
TEXT 576 192 Left 2 !.dc V1 0 5 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2108-1.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2108-1.3.asy)
V1 IN 0 5
L1 N001 OUT 1
Rload OUT 0 4
XU1 IN IN N001 OUT 0 ADP2108-x.x Rtop=128K ;pnba Vin)EN)SW)FB)GND
C1 OUT 0 10
.tran .5m startup
.lib ADP2108-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1112 700
WIRE 192 144 96 144
WIRE 208 144 192 144
WIRE 528 144 496 144
WIRE 640 144 608 144
WIRE 720 144 640 144
WIRE 800 144 720 144
WIRE 96 160 96 144
WIRE 720 160 720 144
WIRE 800 160 800 144
WIRE 96 256 96 240
WIRE 720 256 720 224
WIRE 800 256 800 240
WIRE 192 304 192 144
WIRE 208 304 192 304
WIRE 640 304 640 144
WIRE 640 304 496 304
WIRE 352 384 352 368
SYMBOL VOLTAGE 96 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADP2108-1.3 352 224 R0
SYMATTR InstName U1
SYMBOL ind 512 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMBOL cap 704 160 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL RES 784 144 R0
SYMATTR InstName Rload
SYMATTR Value 4
FLAG 96 256 0
FLAG 352 384 0
FLAG 720 256 0
FLAG 800 256 0
FLAG 800 144 OUT
FLAG 96 144 IN
TEXT 576 352 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2fd9edd809e1_Draft12.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N002 0 N001 0 PNP
V2 N003 0 {V}
R1 N002 N003 10k
V1 v+ 0 12
R2 v+ N001 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 10m
.step param V 0 12 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1032 680
WIRE 112 128 112 80
WIRE 112 256 112 208
WIRE 480 288 480 240
WIRE 48 304 -16 304
WIRE -16 368 -16 304
WIRE 112 400 112 352
WIRE 480 400 480 368
WIRE 624 400 480 400
WIRE 624 448 624 400
WIRE 112 528 112 480
WIRE 112 656 112 608
SYMBOL res 96 112 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 96 384 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL pnp 48 352 M180
SYMATTR InstName Q1
SYMBOL voltage 112 512 R0
SYMATTR InstName V2
SYMATTR Value {V}
SYMBOL voltage 480 272 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG -16 368 0
FLAG 624 448 0
FLAG 480 240 v+
FLAG 112 80 v+
FLAG 112 656 0
TEXT 696 176 Left 2 !.tran 10m\n.step param V 0 12 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6992-1.asc
* Generated by LTspice 26.0.1 for Windows.
* 400Hz, 100% to 0% Duty Cycle\nSwept Pulse Width Modulated Output\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6992-1.asy)
R3 N002 N004 392K
R4 PWMout 0 10K
XU1 N001 0 N003 N004 N002 PWMout LTC6992-1 ;pnba MOD)GND)SET)DIV)V+)OUT
V2 N001 0 PULSE(0 1 10m 50m 50m 5m 110m)
V1 N002 0 3
R1 N003 0 487K
R2 N004 0 1000K
.tran 120m startup
.lib LTC6992-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 996 680
WIRE -208 96 -240 96
WIRE 96 96 -128 96
WIRE 656 96 320 96
WIRE 656 112 656 96
WIRE 96 176 64 176
WIRE 400 176 320 176
WIRE 544 176 400 176
WIRE 400 192 400 176
WIRE 544 192 544 176
WIRE 656 208 656 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 368 256 320 256
WIRE 368 288 368 256
WIRE 400 288 400 272
WIRE 400 288 368 288
WIRE 544 288 544 272
WIRE 400 304 400 288
WIRE 400 400 400 384
SYMBOL res 384 176 R0
SYMATTR InstName R3
SYMATTR Value 392K
SYMBOL voltage 544 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL voltage -112 96 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 1 10m 50m 50m 5m 110m)
SYMATTR InstName V2
SYMBOL res 640 96 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 487K
SYMBOL res 384 288 R0
SYMATTR InstName R2
SYMATTR Value 1000K
SYMBOL SpecialFunctions\\LTC6992-1 208 176 R0
SYMATTR InstName U1
FLAG -240 96 0
FLAG 544 288 0
FLAG 656 96 PWMout
FLAG 656 208 0
FLAG 400 400 0
FLAG -16 256 0
FLAG 64 176 0
TEXT 536 384 Left 2 !.tran 120m startup
TEXT 208 56 Bottom 2 ;400Hz, 100% to 0% Duty Cycle\nSwept Pulse Width Modulated Output\nStartup Modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX1522.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX1522.asy)
C4 OUT 0 33 Rser=60m
V1 IN 0 3.3
M1 N001 N002 0 0 FDC637AN
C1 IN 0 0.1
XU2 0 N003 0 IN N002 IN MAX1522 ;pnba GND)FB)SET)_SHDN)EXT)Vcc
R2 N003 0 90.9K
D1 N001 OUT MBRS130L
C3 N003 0 100p
L1 IN N001 3.3 Rser=86m
C2 OUT N003 100p
R1 OUT N003 274K
R3 OUT 0 14.2 m=2
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 4m startup
.lib MAX1522.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 940 680
WIRE -128 -160 -160 -160
WIRE 16 -160 -128 -160
WIRE 208 -160 16 -160
WIRE 400 -160 288 -160
WIRE 464 -160 400 -160
WIRE 656 -160 528 -160
WIRE 768 -160 656 -160
WIRE 848 -160 768 -160
WIRE 880 -160 848 -160
WIRE -160 -128 -160 -160
WIRE 768 -128 768 -160
WIRE 880 -128 880 -160
WIRE 400 -96 400 -160
WIRE 656 -64 656 -160
WIRE 656 -64 560 -64
WIRE 656 -32 656 -64
WIRE 768 -32 768 -64
WIRE 880 -32 880 -48
WIRE -64 -16 -80 -16
WIRE 16 -16 16 -160
WIRE 16 -16 0 -16
WIRE 64 -16 16 -16
WIRE 352 -16 320 -16
WIRE 560 -16 560 -64
WIRE -160 0 -160 -48
WIRE 400 48 400 0
WIRE 64 80 48 80
WIRE 560 80 560 48
WIRE 560 80 320 80
WIRE 656 80 656 48
WIRE 656 80 560 80
WIRE 560 112 560 80
WIRE 656 112 656 80
WIRE 16 176 16 -16
WIRE 64 176 16 176
WIRE 336 176 320 176
WIRE 560 224 560 176
WIRE 656 224 656 192
SYMBOL cap 0 -32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.1
SYMBOL cap 544 -16 R0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL res 640 96 R0
SYMATTR InstName R2
SYMATTR Value 90.9K
SYMBOL res 640 -48 R0
SYMATTR InstName R1
SYMATTR Value 274K
SYMBOL voltage -160 -144 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 544 112 R0
SYMATTR InstName C3
SYMATTR Value 100p
SYMBOL cap 752 -128 R0
SYMATTR SpiceLine Rser=60m
SYMATTR InstName C4
SYMATTR Value 33
SYMBOL ind 192 -144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 3.3
SYMATTR SpiceLine Rser=86m
SYMBOL nmos 352 -96 R0
SYMATTR InstName M1
SYMATTR Value FDC637AN
SYMBOL MAX1522 192 80 R0
SYMATTR InstName U2
SYMBOL res 864 -144 R0
WINDOW 123 36 60 Left 2
SYMATTR Value2 m=2
SYMATTR InstName R3
SYMATTR Value 14.2
SYMBOL schottky 464 -144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS130L
SYMATTR Description Diode
SYMATTR Type diode
FLAG 400 48 0
FLAG -160 0 0
FLAG -80 -16 0
FLAG 656 224 0
FLAG 560 224 0
FLAG 768 -32 0
FLAG 880 -32 0
FLAG -128 -160 IN
FLAG 848 -160 OUT
FLAG 336 176 0
FLAG 48 80 0
TEXT 152 296 Left 2 !.tran 4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\67d700f8ac95_Diode_Clipping_Circuit.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N001 2860
D1 N002 0 1N914
V1 N001 0 SINE(0 15 50 0 0)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 100ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 0 -64 0
WIRE 224 0 128 0
WIRE 256 0 224 0
WIRE -64 32 -64 0
WIRE 224 32 224 0
WIRE -64 128 -64 112
WIRE 224 128 224 96
WIRE 224 128 -64 128
WIRE 256 128 224 128
WIRE -64 144 -64 128
SYMBOL res 144 -16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2860
SYMBOL diode 208 32 R0
WINDOW 0 36 1 VBottom 0
WINDOW 3 49 54 Top 1
SYMATTR InstName D1
SYMATTR Value 1N914
SYMBOL voltage -64 16 R0
WINDOW 0 24 16 Left 1
WINDOW 3 33 86 Top 1
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 15 50 0 0)
FLAG -64 144 0
TEXT 184 176 Left 2 !.tran 100ms