* Z:\tmp\asc_dec_bjh7r6w2\01c5d2dd95a7_rh_dff_ex_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 o1 D
C4 N007 0 {CL}
M12 N007 N003 VDD VDD iucreate_pmos l=0.5u w=3.5u
M15 N003 CLK N004 0 iucreate_nmos l=0.5u w=1.5u
M2 N006 N001 VDD VDD iucreate_pmos l=0.5u w=3.5u
VD D 0 0 AC 1
M5 N001 CLK N002 0 iucreate_nmos l=0.5u w=1.5u
M8 D CLK N001 VDD iucreate_pmos l=0.5u w=1.5u
ISET o1 0 EXP(0 {IPEAK} {TS} 5p {TS+0.01n} 1n)
C1 N001 0 {CL}
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3092 1476
WIRE 1456 -448 1456 -496
WIRE 1376 -400 1344 -400
WIRE 1504 -400 1472 -400
WIRE 1424 -368 1424 -400
WIRE 1424 -352 1424 -368
WIRE 1344 -288 1344 -400
WIRE 1344 -288 1040 -288
WIRE 1504 -288 1504 -400
WIRE 1744 -288 1504 -288
WIRE 1344 -144 1344 -288
WIRE 1504 -144 1504 -288
WIRE 1200 64 1184 64
WIRE 2400 64 2384 64
WIRE 1184 80 1184 64
WIRE 2384 80 2384 64
WIRE 1136 96 1088 96
WIRE 2336 96 2288 96
WIRE 2080 112 2080 64
WIRE 1200 128 1200 64
WIRE 1200 128 1184 128
WIRE 2400 128 2400 64
WIRE 2400 128 2384 128
WIRE 800 160 768 160
WIRE 928 160 896 160
WIRE 2064 160 2032 160
WIRE 2192 160 2160 160
WIRE 848 192 848 160
WIRE 2112 192 2112 160
WIRE 592 208 592 160
WIRE 848 208 848 192
WIRE 2112 208 2112 192
WIRE 1184 240 1184 176
WIRE 1632 240 1184 240
WIRE 2032 240 2032 160
WIRE 2032 240 1888 240
WIRE 2192 240 2192 160
WIRE 2240 240 2240 -288
WIRE 2240 240 2192 240
WIRE 2288 240 2288 96
WIRE 2288 240 2240 240
WIRE 2384 240 2384 176
WIRE 2752 240 2384 240
WIRE 3008 240 2752 240
WIRE 768 272 768 160
WIRE 768 272 704 272
WIRE 928 272 928 160
WIRE 992 272 928 272
WIRE 1040 272 1040 -288
WIRE 1040 272 992 272
WIRE 1088 272 1088 96
WIRE 1088 272 1040 272
WIRE 592 288 592 272
WIRE 1184 304 1184 240
WIRE 2384 304 2384 240
WIRE 2752 304 2752 240
WIRE 416 336 416 272
WIRE 592 336 592 288
WIRE 992 336 992 272
WIRE 2240 336 2240 240
WIRE 1200 352 1184 352
WIRE 2400 352 2384 352
WIRE 1088 384 1088 272
WIRE 1136 384 1088 384
WIRE 2288 384 2288 240
WIRE 1200 400 1200 352
WIRE 2400 400 2400 352
WIRE 768 416 768 272
WIRE 800 416 768 416
WIRE 848 416 848 368
WIRE 928 416 928 272
WIRE 928 416 896 416
WIRE 2032 416 2032 240
WIRE 2192 416 2192 240
WIRE 2752 432 2752 368
WIRE 416 464 416 416
WIRE 592 464 592 416
WIRE 992 464 992 400
WIRE 880 512 880 464
WIRE 1744 640 1632 640
WIRE 1856 640 1744 640
WIRE 1904 640 1856 640
WIRE 1744 672 1744 640
WIRE 1856 688 1856 640
WIRE 1744 800 1744 752
WIRE 1744 800 1632 800
WIRE 1856 800 1856 752
WIRE 1856 800 1744 800
SYMBOL diode 1872 752 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL cap 2736 304 R0
SYMATTR InstName C4
SYMATTR Value {CL}
SYMBOL pmos4 2336 176 M180
SYMATTR InstName M12
SYMATTR Value iucreate_pmos
SYMATTR Value2 l=0.5u w=3.5u
SYMBOL nmos4 2160 112 R90
SYMATTR InstName M15
SYMATTR Value iucreate_nmos
SYMATTR Value2 l=0.5u w=1.5u
SYMBOL pmos4 1136 176 M180
SYMATTR InstName M2
SYMATTR Value iucreate_pmos
SYMATTR Value2 l=0.5u w=3.5u
SYMBOL voltage 592 320 R0
WINDOW 3 91 111 Right 2
SYMATTR Value 0
SYMATTR InstName D
SYMATTR Value2 AC 1
SYMBOL nmos4 1376 -448 M90
SYMATTR InstName M5
SYMATTR Value iucreate_nmos
SYMATTR Value2 l=0.5u w=1.5u
SYMBOL pmos4 800 464 R270
SYMATTR InstName M8
SYMATTR Value iucreate_pmos
SYMATTR Value2 l=0.5u w=1.5u
SYMBOL current 1744 672 R0
WINDOW 3 24 80 Invisible 0
SYMATTR Value EXP(0 {IPEAK} {TS} 5p {TS+0.01n} 1n)
SYMATTR InstName ISET
SYMBOL cap 976 336 R0
SYMATTR InstName C1
SYMATTR Value {CL}
FLAG 592 464 0
FLAG 880 512 CLK
FLAG 848 368 VDD
FLAG 848 192 0
FLAG 704 272 D
FLAG 1456 -496 CLK
FLAG 1424 -368 0
FLAG 1200 64 VDD
FLAG 2080 64 CLK
FLAG 2112 192 0
FLAG 2400 64 VDD
FLAG 592 208 0
FLAG 1632 640 o1
FLAG 1632 800 0
FLAG 2752 432 0
FLAG 992 464 0
FLAG 416 464 0
FLAG 416 272 N005
FLAG 592 288 D