Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1108-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1108-5.asy)
XU1 IN IN N001 0 0 N002 N003 OUT LT1108 top=753K bot=250K ;pnba Ilim)Vin)SW1)SW2)GND)AO)SET)Sense
C2 OUT 0 100 Rser=0.02
L1 IN N001 33 Rser=0.02 Rpar=5000
D1 N001 OUT MBRS140
Rload OUT 0 25
V1 IN 0 2.8
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LT1108.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2456 1432
WIRE 1472 912 1296 912
WIRE 1600 912 1472 912
WIRE 1632 912 1600 912
WIRE 1744 912 1712 912
WIRE 1776 912 1744 912
WIRE 1904 912 1840 912
WIRE 1952 912 1904 912
WIRE 1296 928 1296 912
WIRE 1952 928 1952 912
WIRE 1472 960 1472 912
WIRE 1600 960 1600 912
WIRE 1296 1024 1296 1008
WIRE 1392 1024 1376 1024
WIRE 1744 1024 1744 912
WIRE 1744 1024 1680 1024
WIRE 1952 1024 1952 1008
WIRE 1904 1104 1904 912
WIRE 1904 1104 1680 1104
WIRE 1904 1120 1904 1104
WIRE 1392 1184 1376 1184
WIRE 1696 1184 1680 1184
WIRE 1904 1200 1904 1184
WIRE 1536 1264 1536 1248
SYMBOL PowerProducts\\LT1108-5 1536 1104 R0
SYMATTR InstName U1
SYMBOL schottky 1776 928 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL VOLTAGE 1296 912 R0
SYMATTR InstName V1
SYMATTR Value 2.8
SYMBOL POLCAP 1888 1120 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL IND 1616 928 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL res 1936 912 R0
SYMATTR InstName Rload
SYMATTR Value 25
FLAG 1952 912 OUT
FLAG 1904 1200 0
FLAG 1952 1024 0
FLAG 1296 1024 0
FLAG 1696 1184 0
FLAG 1536 1264 0
FLAG 1296 912 IN
TEXT 1728 1256 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8421.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8421.asy)
Rload OUT 0 10K
Vcm V- 0 PWL(0 2.4 2.5m 3.1 5m 2.4)
Vref N003 0 2.5
R1 N001 N002 100
V1 +V 0 15
V2 -V 0 0
Vin V+ V- SINE(0 1m 10K)
XU1 V- N001 N002 V+ -V N003 OUT +V AD8421 ;pnba IN-)RG1)RG2)IN+)VEE)REF)OUT)VCC
.tran 5m
.lib AD8421.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 640 -1264 640 -1280
WIRE 752 -1264 752 -1280
WIRE 304 -1184 96 -1184
WIRE 464 -1184 304 -1184
WIRE 640 -1168 640 -1184
WIRE 752 -1168 752 -1184
WIRE 96 -1152 96 -1184
WIRE 464 -1152 368 -1152
WIRE 752 -1104 640 -1104
WIRE 752 -1088 752 -1104
WIRE 368 -1056 368 -1072
WIRE 464 -1056 368 -1056
WIRE 96 -1024 96 -1072
WIRE 304 -1024 96 -1024
WIRE 464 -1024 304 -1024
WIRE 576 -1024 576 -1040
WIRE 96 -1008 96 -1024
WIRE 752 -992 752 -1008
WIRE 576 -928 576 -944
WIRE 96 -912 96 -928
SYMBOL voltage 576 -1040 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName Vref
SYMATTR Value 2.5
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 96 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1m 10K)
SYMBOL AD8421 496 -1104 R0
SYMATTR InstName U1
SYMBOL voltage 96 -1024 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR InstName Vcm
SYMATTR Value PWL(0 2.4 2.5m 3.1 5m 2.4)
SYMBOL voltage 752 -1280 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL res 352 -1168 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 640 -1280 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 15
FLAG 640 -1280 +V
FLAG 640 -1168 0
FLAG 752 -1104 OUT
FLAG 496 -1200 +V
FLAG 752 -1280 -V
FLAG 496 -1008 -V
FLAG 752 -992 0
FLAG 752 -1168 0
FLAG 96 -912 0
FLAG 576 -928 0
FLAG 304 -1024 V-
FLAG 304 -1184 V+
TEXT 328 -960 Left 2 !.tran 5m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1230.asc
* Generated by LTspice 26.0.1 for Windows.
* Single Supply Cable Driver for Composite Video
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1230.asy)
R1 N003 N002 510
R4 P001 OUT 75
R3 +V N002 1.5K
Q1 +V N001 N005 0 2N3904
V1 +V 0 5
R5 OUT 0 10K
R2 N002 0 750
XU1 N005 N002 +V 0 N003 LT1229 ;pnba In+)In-)V+)V-)OUT
C1 P001 N003 1000
C3 N001 0 1
R7 N001 0 2K
C2 N005 N004 1
R6 +V N001 3K
R8 N005 0 150K
V3 N004 0 SINE(0 .7 1K)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 300m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1260 680
WIRE -48 -48 -128 -48
WIRE 224 -48 -48 -48
WIRE 416 -48 224 -48
WIRE -48 -32 -48 -48
WIRE 224 -32 224 -48
WIRE 416 -16 416 -48
WIRE -128 16 -128 -48
WIRE -48 64 -48 48
WIRE -48 64 -64 64
WIRE 32 64 -48 64
WIRE -48 80 -48 64
WIRE 32 96 32 64
WIRE 128 96 112 96
WIRE 224 96 224 48
WIRE 224 96 208 96
WIRE 240 96 224 96
WIRE 352 96 320 96
WIRE 416 96 416 64
WIRE -48 176 -48 160
WIRE 32 176 32 160
WIRE 288 208 288 192
WIRE 224 224 224 96
WIRE 256 224 224 224
WIRE 352 240 352 96
WIRE 352 240 320 240
WIRE 416 240 352 240
WIRE 592 240 560 240
WIRE 640 240 592 240
WIRE -240 256 -336 256
WIRE -128 256 -128 112
WIRE -128 256 -176 256
WIRE 256 256 -128 256
WIRE 592 256 592 240
WIRE -336 272 -336 256
WIRE -128 272 -128 256
WIRE 288 288 288 272
WIRE 592 352 592 336
WIRE -336 368 -336 352
WIRE -128 368 -128 352
SYMBOL npn -64 16 M0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 208 -48 R0
SYMATTR InstName R3
SYMATTR Value 1.5K
SYMBOL res 576 240 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL res -64 -48 R0
SYMATTR InstName R6
SYMATTR Value 3K
SYMBOL opamps\\LT1230 288 176 R0
SYMATTR InstName U1
SYMBOL res 224 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 750
SYMBOL res -144 256 R0
SYMATTR InstName R8
SYMATTR Value 150K
SYMBOL cap 480 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1000
SYMBOL cap -176 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 464 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 75
SYMBOL voltage -336 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 .7 1K)
SYMBOL res 336 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 510
SYMBOL voltage 416 -32 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 16 96 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res -64 64 R0
SYMATTR InstName R7
SYMATTR Value 2K
FLAG 416 96 0
FLAG 288 192 +V
FLAG 416 -48 +V
FLAG 112 96 0
FLAG -336 368 0
FLAG 288 288 0
FLAG 592 352 0
FLAG 640 240 OUT
FLAG -48 176 0
FLAG -128 368 0
FLAG 32 176 0
TEXT 360 360 Left 2 !.tran 300m
TEXT 128 -64 Bottom 2 ;Single Supply Cable Driver for Composite Video
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC7050-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC7050-1.asy)
V5 N010 0 1
R2 N009 N010 100
L1 N001 N002 0.1
Rload2 N008 0 100m
R1 N004 N005 100
V2 N003 0 5
C1 N002 0 200
C2 N008 0 200
Rload1 N002 0 100m
V6 N005 0 1
V1 IN 0 12
L2 N007 N008 0.1
V4 N011 0 PULSE(0 5 0 1n 1n 100n 1u)
V3 N006 0 PULSE(0 5 0 1n 1n 100n 1u)
XU1 N003 N006 N003 0 MP_01 MP_02 N011 N003 N003 IN N001 0 N004 NC_03 NC_04 N009 N007 LTC7050-1 RTon=8m RBon=1.5m OV=18 ;pnba Vcc)PWM1)Run1)SGND)))PWM2)Run2)PVcc)Vin)SW1)PGND)Isns1)Fltb1)Fltb2)Isns2)SW2
.tran 300u
.lib LTC7050-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 920 728
WIRE 192 -16 -32 -16
WIRE 560 -16 480 -16
WIRE 720 -16 640 -16
WIRE 816 -16 720 -16
WIRE -32 0 -32 -16
WIRE 720 0 720 -16
WIRE 816 0 816 -16
WIRE 160 80 48 80
WIRE 192 80 160 80
WIRE 512 80 480 80
WIRE 624 80 592 80
WIRE -32 96 -32 80
WIRE 48 96 48 80
WIRE 624 96 624 80
WIRE 720 96 720 64
WIRE 816 96 816 80
WIRE 160 176 160 80
WIRE 192 176 160 176
WIRE 48 192 48 176
WIRE 624 192 624 176
WIRE 192 272 -224 272
WIRE 560 272 480 272
WIRE 720 272 640 272
WIRE 816 272 720 272
WIRE -224 288 -224 272
WIRE 720 288 720 272
WIRE 816 288 816 272
WIRE 160 368 160 176
WIRE 192 368 160 368
WIRE 512 368 480 368
WIRE 624 368 592 368
WIRE -224 384 -224 368
WIRE 624 384 624 368
WIRE 720 384 720 352
WIRE 816 384 816 368
WIRE 192 464 -224 464
WIRE -224 480 -224 464
WIRE 624 480 624 464
WIRE 160 560 160 368
WIRE 192 560 160 560
WIRE 512 560 480 560
WIRE -224 576 -224 560
WIRE 336 640 336 608
SYMBOL LTC7050-1 336 272 R0
SYMATTR InstName U1
SYMBOL voltage -224 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 1n 1n 100n 1u)
SYMBOL cap 704 288 R0
WINDOW 0 33 12 Left 2
SYMATTR InstName C2
SYMATTR Value 200
SYMBOL ind 544 0 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.1
SYMBOL res 496 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage -224 464 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 5 0 1n 1n 100n 1u)
SYMBOL ind 544 288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 0.1
SYMBOL voltage 624 80 R0
SYMATTR InstName V6
SYMATTR Value 1
SYMBOL cap 704 0 R0
WINDOW 0 33 14 Left 2
SYMATTR InstName C1
SYMATTR Value 200
SYMBOL voltage 624 368 R0
SYMATTR InstName V5
SYMATTR Value 1
SYMBOL res 496 384 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL res 800 272 R0
SYMATTR InstName Rload2
SYMATTR Value 100m
SYMBOL voltage 48 80 R0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 800 -16 R0
SYMATTR InstName Rload1
SYMATTR Value 100m
SYMBOL voltage -32 -16 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG -32 96 0
FLAG 48 192 0
FLAG -224 384 0
FLAG 624 480 0
FLAG 512 560 0
FLAG 336 640 0
FLAG 624 192 0
FLAG 720 96 0
FLAG 720 384 0
FLAG 816 96 0
FLAG 816 384 0
FLAG -224 576 0
FLAG -32 -16 IN
TEXT 704 568 Left 2 !.tran 300u
* Z:\home\khalils\Downloads\files\data\raw_asc\1c04d071f12b_lab02-Capacitor-battery.asc
* Generated by LTspice 26.0.1 for Windows.
R2 Vin Vout .1 pwr=0.5
C1 Vout 0 0.01 V=100
V1 Vin 0 PULSE(0 10 0 .001 .001 .004 .010)
R1 Vout 0 100000
.tran 0.05
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 32 16 32
WIRE 304 64 304 32
WIRE 16 96 16 32
WIRE 304 160 304 144
WIRE 400 160 304 160
WIRE 496 160 400 160
WIRE 304 192 304 160
WIRE 448 192 400 160
WIRE 16 272 16 176
WIRE 304 288 304 272
WIRE 400 288 448 256
WIRE 400 288 304 288
WIRE 304 304 304 288
FLAG 16 272 0
FLAG 304 304 0
FLAG 16 32 Vin
FLAG 496 160 Vout
SYMBOL res 288 48 R0
SYMATTR InstName R2
SYMATTR Value .1
SYMATTR SpiceLine pwr=0.5
SYMBOL cap 432 192 R0
WINDOW 3 22 61 Left 0
SYMATTR InstName C1
SYMATTR Value 0.01
SYMATTR SpiceLine V=100
SYMBOL Misc\\battery 16 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -372 102 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 10 0 .001 .001 .004 .010)
SYMBOL res 288 176 R0
SYMATTR InstName R1
SYMATTR Value 100000
TEXT -16 328 Left 0 !.tran 0.05
* Z:\home\khalils\Downloads\files\data\raw_asc\57dd37ed1955_Inverter.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N002 A Y N002 PMOS
M2 Y A 0 0 NMOS
V1 N002 0 5
V2 A 0 PULSE(0 5 0 1n 1n 50m 100m 2)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL PMOS PMOS LEVEL = 3
+ TOX = 200E-10
+ PHI = 0.7
+ UO = 250
+ KP = 40E-6
+ RSH = 0
+ XJ = 500E-9
+ CGDO = 200E-12
+ CJ = 400E-6
+ CJSW = 300E-12 NSUB = 1E17 VTO = -0.9 ETA = 0
+ VMAX = 5E4 NFS = 1E12 LD = 100E-9 CGSO = 200E-12
+ PB = 1 MJSW = 0.5 GAMMA = 0.6 DELTA = 0.1
+ THETA = 0.1 KAPPA = 1 TPG = -1 CGBO = 1E-10 MJ= 0.5
.MODEL PMOS PMOS LEVEL = 3
+ TOX = 200E-10
+ PHI = 0.7
+ UO = 250
+ KP = 120E-6
+ RSH = 0
+ XJ = 500E-9
+ CGDO = 200E-12
+ CJ = 400E-6
+ CJSW = 300E-12
+ NSUB = 1E17 VTO = -1.0 ETA = 3.0E-6 VMAX = 1E5 NFS = 1E12
+ LD = 100E-9 CGSO = 200E-12 PB = 1 MJSW = 0.5
+ GAMMA = 0.5 DELTA = 3.0 THETA = 0.1
+ KAPPA = 0.3 TPG = 1 CGBO = 1E-10 MJ = 0.5
* Joel Brigida
* A
* Y
* 0
* 0
* 1
* 1
* Inverter [NOT]
.tran 200m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 680
WIRE -112 -32 -160 -32
WIRE -64 -32 -112 -32
WIRE 224 -32 0 -32
WIRE -160 0 -160 -32
WIRE -64 0 -64 -32
WIRE -64 0 -160 0
WIRE 0 0 0 -32
WIRE 224 48 224 -32
WIRE 272 48 224 48
WIRE -160 80 -160 0
WIRE -112 80 -112 -32
WIRE -112 80 -160 80
WIRE -64 80 -64 0
WIRE -64 80 -112 80
WIRE 272 96 272 48
WIRE 272 96 224 96
WIRE 0 112 0 80
WIRE 176 128 128 128
WIRE 128 144 128 128
WIRE 128 144 0 144
WIRE 0 176 0 144
WIRE 224 176 224 144
WIRE 368 176 224 176
WIRE 224 192 224 176
WIRE 272 240 224 240
WIRE 128 272 128 144
WIRE 176 272 128 272
WIRE 0 288 0 256
WIRE 272 288 272 240
WIRE 272 288 224 288
WIRE 224 320 224 288
FLAG 224 320 0
FLAG 0 112 0
FLAG 0 288 0
FLAG 368 176 Y
FLAG 0 144 A
SYMBOL pmos4 176 48 R0
SYMATTR InstName M1
SYMBOL nmos4 176 192 R0
SYMATTR InstName M2
SYMBOL voltage 0 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 32 86 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 0 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 32 30 Left 2
WINDOW 3 -193 100 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1n 1n 50m 100m 2)
TEXT 336 200 Left 2 !.MODEL PMOS PMOS LEVEL = 3\n+ TOX = 200E-10\n+ PHI = 0.7\n+ UO = 250 \n+ KP = 40E-6\n+ RSH = 0\n+ XJ = 500E-9 \n+ CGDO = 200E-12 \n+ CJ = 400E-6\n+ CJSW = 300E-12 NSUB = 1E17 VTO = -0.9 ETA = 0\n+ VMAX = 5E4 NFS = 1E12  LD = 100E-9 CGSO = 200E-12\n+ PB = 1  MJSW = 0.5  GAMMA  = 0.6  DELTA  = 0.1\n+ THETA  = 0.1 KAPPA = 1 TPG = -1  CGBO = 1E-10  MJ= 0.5
TEXT 336 -40 Left 2 !.MODEL PMOS PMOS LEVEL = 3\n+ TOX = 200E-10\n+ PHI = 0.7\n+ UO = 250\n+ KP = 120E-6\n+ RSH = 0\n+ XJ = 500E-9\n+ CGDO = 200E-12\n+ CJ = 400E-6\n+ CJSW = 300E-12\n+ NSUB = 1E17   VTO = -1.0    ETA = 3.0E-6  VMAX = 1E5 NFS = 1E12   \n+ LD = 100E-9   CGSO = 200E-12   PB = 1  MJSW = 0.5\n+ GAMMA  = 0.5  DELTA  = 3.0  THETA  = 0.1\n+ KAPPA  = 0.3  TPG = 1  CGBO = 1E-10  MJ = 0.5
TEXT 8 -56 Left 4 ;Joel Brigida
TEXT -144 -16 Left 3 ;A
TEXT -96 -16 Left 3 ;Y
TEXT -144 24 Left 3 ;0
TEXT -96 56 Left 3 ;0
TEXT -144 56 Left 3 ;1
TEXT -96 24 Left 3 ;1
TEXT -152 -48 Left 2 ;Inverter [NOT]
TEXT 38 310 Left 2 !.tran 200m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG6436.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSwitch shown for a logic 0 input\nParameter performance at 20V supply\nCharge injection is not included\nPin capacitance is not included\nOff isolation and Crosstalk specified at 100KHz only
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG6436.asy)
C1 vD 0 36p
V1 vSA 0 3
V4 V+ 0 20
V5 V- 0 -20
V2 vIN 0 PULSE(0 3.3 0 20n 20n 10u 20u)
R1 vD 0 301
XU1 vIN vSA vD 0 V+ 0 V- vEN ADG6436 ;pnba IN)SA)D)SB)Vdd)GND)Vss)EN
V3 vEN 0 5
.tran 100u
.lib ADG6436.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2888 1548
WIRE -1584 -368 -1600 -368
WIRE -1600 -336 -1600 -368
WIRE -1728 -272 -1904 -272
WIRE -1696 -272 -1728 -272
WIRE -1904 -256 -1904 -272
WIRE -1456 -240 -1504 -240
WIRE -1408 -240 -1456 -240
WIRE -1312 -240 -1408 -240
WIRE -2160 -224 -2176 -224
WIRE -2032 -224 -2048 -224
WIRE -1408 -224 -1408 -240
WIRE -1312 -224 -1312 -240
WIRE -2176 -208 -2176 -224
WIRE -2048 -208 -2048 -224
WIRE -1696 -208 -1712 -208
WIRE -1904 -160 -1904 -176
WIRE -1728 -144 -1824 -144
WIRE -1696 -144 -1728 -144
WIRE -1456 -144 -1504 -144
WIRE -1408 -128 -1408 -144
WIRE -1312 -128 -1312 -160
WIRE -1824 -80 -1824 -144
WIRE -1456 -80 -1456 -144
WIRE -1552 -16 -1552 -32
WIRE -1648 0 -1648 -32
WIRE -1632 0 -1648 0
WIRE -1456 16 -1456 0
WIRE -1824 32 -1824 0
SYMBOL voltage -1456 -96 R0
WINDOW 3 37 72 Left 2
SYMATTR Value 5
SYMATTR InstName V3
SYMBOL voltage -2176 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 20
SYMBOL voltage -2048 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value -20
SYMBOL res -1424 -240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -1904 -272 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL voltage -1824 -96 R0
WINDOW 3 -13 166 Left 2
SYMATTR Value PULSE(0 3.3 0 20n 20n 10u 20u)
SYMATTR InstName V2
SYMBOL ADG6436 -1600 -192 R0
SYMATTR InstName U1
SYMBOL cap -1328 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG -1904 -160 0
FLAG -1824 32 0
FLAG -1584 -368 V+
FLAG -1408 -128 0
FLAG -1552 -16 0
FLAG -1312 -128 0
FLAG -2176 -128 0
FLAG -2176 -224 V+
FLAG -1728 -272 vSA
FLAG -1728 -144 vIN
FLAG -1456 -240 vD
FLAG -2048 -128 0
FLAG -2048 -224 V-
FLAG -1632 0 V-
FLAG -1456 16 0
FLAG -1456 -144 vEN
FLAG -1712 -208 0
TEXT -1360 -40 Left 2 !.tran 100u
TEXT -2056 -584 Left 2 ;Notes:\nSwitch shown for a logic 0 input\nParameter performance at 20V supply\nCharge injection is not included\nPin capacitance is not included\nOff isolation and Crosstalk specified at 100KHz only
* Z:\home\khalils\Downloads\files\data\raw_asc\032be66a6662_Hysteresis_dc_plot.asc
* Generated by LTspice 26.0.1 for Windows.
* Hysteresis Curve With DC-Analysis\n \nA table is used to map the linear DC-sweep of V1 to a "nonlinear" DC-sweep from -3V to +3V and back to -3V.\n \nPlot V(out) and Ic(Q1) versus V(in)\nTherefore change the x-axis to V(in) after the first simulation run.
* Schmitt trigger
* Translation Table\n-10 ... +10 -> -1 ... +1 ... -1\n \n / / \\ \n / / \\ \n / / \\
V3 N001 0 12
V1 in0 0 0
R1 N003 N004 10k
R5 _out N002 10k
R2 N001 _out 1k
R4 N002 N004 12k
B1 in 0 V=1.0*Table(V(in0), -1, -1, 0, 1, 1, -1)
V2 N004 0 -12
Q1 _out in N003 0 NPN
R3 N001 out 1k
Q2 out N002 N003 0 NPN
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 -1 1 0.001
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -432 240 -432 288
WIRE -432 160 -432 112
WIRE -256 240 -256 288
WIRE -256 160 -256 112
WIRE 400 256 480 256
WIRE 480 256 480 336
WIRE 480 256 576 256
WIRE 400 -16 400 64
WIRE 400 -96 400 -144
WIRE 400 -144 576 -144
WIRE 576 -144 576 -96
WIRE 576 -16 576 16
WIRE 688 256 688 208
WIRE 688 208 640 208
WIRE 400 64 688 64
WIRE 400 64 400 160
WIRE 688 64 688 96
WIRE 688 176 688 208
WIRE 688 336 688 448
WIRE 688 448 480 448
WIRE 480 448 480 416
WIRE 256 -112 256 -144
WIRE 256 -144 400 -144
WIRE 256 -32 256 0
WIRE 480 496 480 448
WIRE 480 608 480 576
WIRE 336 208 288 208
WIRE 576 16 784 16
WIRE 576 16 576 160
WIRE 688 64 784 64
IOPIN 288 208 In
IOPIN 784 16 Out
SYMBOL bv -256 144 R0
SYMATTR InstName B1
SYMATTR Value V=1.0*Table(V(in0),  -1, -1,   0, 1,   1, -1)
SYMBOL res 464 320 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage -432 144 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL res 560 -112 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL voltage 480 480 R0
SYMATTR InstName V2
SYMATTR Value -12
SYMBOL res 384 -112 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL npn 336 160 R0
SYMATTR InstName Q1
SYMBOL res 672 80 R0
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL npn 640 160 M0
SYMATTR InstName Q2
SYMBOL res 672 240 R0
SYMATTR InstName R4
SYMATTR Value 12k
SYMBOL voltage 256 -128 R0
SYMATTR InstName V3
SYMATTR Value 12
FLAG -432 288 0
FLAG -432 112 in0
FLAG -256 288 0
FLAG -256 112 in
FLAG 256 0 0
FLAG 480 608 0
FLAG 288 208 in
FLAG 784 16 out
FLAG 784 64 _out
TEXT -440 8 Left 0 !.dc V1 -1 1 0.001
TEXT -456 -368 Left 0 ;Hysteresis Curve With DC-Analysis\n \nA table is used to map the linear DC-sweep of V1 to a "nonlinear" DC-sweep from -3V to +3V and back to -3V.\n \nPlot V(out) and Ic(Q1)  versus V(in)\nTherefore change the x-axis to V(in) after the first simulation run.
TEXT 416 -184 Left 0 ;Schmitt trigger
TEXT -160 40 Left 0 ;Translation Table\n-10 ... +10 -> -1 ... +1 ... -1\n \n         /                      / \\      \n      /                      /       \\    \n   /                      /             \\
TEXT -448 -160 Left 0 !.options plotwinsize=0
* Z:\home\khalils\Downloads\files\data\raw_asc\64037ee6bac7_Ej2.asc
* Generated by LTspice 26.0.1 for Windows.
C2 N003 0 {C2}
C1 N002 0 {C1}
L2 N002 N001 {L2} Rser=0
R1 Vo 0 100000T
L3 Vo N001 {L3} Rser=0
L1 N001 Vi {L1} Rser=0
V1 Vi 0 AC 1 0
L4 N003 Vo {L4} Rser=0
.param Ww=(2*pi)
.param L1=(32)/(45*Ww)
.param L2=(68)/(225*Ww)
.param L3=(374)/(135*Ww)
.param L4=1/(Ww)
.param C1=(25)/(68*Ww)
.param C2=(1)/(2*Ww)
.net I(R1) V1
.ac dec 1000 0.0001 100000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 928 680
WIRE 160 80 64 80
WIRE 352 80 240 80
WIRE 400 80 352 80
WIRE 608 80 480 80
WIRE 768 80 608 80
WIRE 352 112 352 80
WIRE 608 112 608 80
WIRE 64 128 64 80
WIRE 768 128 768 80
WIRE 352 208 352 192
WIRE 608 208 608 192
WIRE 64 272 64 208
WIRE 352 272 64 272
WIRE 608 272 352 272
WIRE 768 272 768 208
WIRE 768 272 608 272
SYMBOL cap 336 208 R0
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL ind 496 64 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L3
SYMATTR Value {L3}
SYMATTR SpiceLine Rser=0
SYMBOL voltage 64 112 R0
WINDOW 123 24 152 Left 2
WINDOW 39 24 124 Left 2
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL ind 368 208 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L2
SYMATTR Value {L2}
SYMATTR SpiceLine Rser=0
SYMBOL cap 592 208 R0
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL ind 256 64 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value {L1}
SYMATTR SpiceLine Rser=0
SYMBOL ind 624 208 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L4
SYMATTR Value {L4}
SYMATTR SpiceLine Rser=0
SYMBOL res 752 112 R0
SYMATTR InstName R1
SYMATTR Value 100000T
FLAG 352 272 0
FLAG 768 80 Vo
FLAG 64 80 Vi
TEXT 64 320 Left 2 !.param Ww=(2*pi)\n.param L1=(32)/(45*Ww)\n.param L2=(68)/(225*Ww)\n.param L3=(374)/(135*Ww)\n.param L4=1/(Ww)\n.param C1=(25)/(68*Ww) \n.param C2=(1)/(2*Ww)
TEXT 464 320 Left 2 !.net I(R1) V1
TEXT 24 512 Left 2 !.ac dec 1000 0.0001 100000
* Z:\home\khalils\Downloads\files\data\raw_asc\2469a3697d1b_circuit.asc
* Generated by LTspice 26.0.1 for Windows.
V2 SYS_PWR 0 PULSE(0 3.3 0 0.001 0.001 0.5 1 15)
M1 5V N001 VDD1 VDD1 PJA3416AE_R1_00001
R3 SYS_PWR 0 10e3
R4 5V N001 10e3
R1 VDD1 0 0.833
V1 5V 0 5
M2 N001 SYS_PWR 0 0 PJA3416AE_R1_00001
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 15 0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1676 680
WIRE 256 -496 256 -528
WIRE -80 -368 -128 -368
WIRE 112 -368 -80 -368
WIRE 256 -352 256 -416
WIRE 432 -352 256 -352
WIRE -80 -336 -80 -368
WIRE -656 -224 -656 -272
WIRE 256 -224 256 -352
WIRE -464 -208 -464 -256
WIRE -80 -208 -80 -256
WIRE 656 -192 656 -240
WIRE 112 -144 112 -368
WIRE 208 -144 112 -144
WIRE -656 -96 -656 -144
WIRE -464 -96 -464 -128
WIRE 656 -96 656 -112
SYMBOL res -96 -352 R0
SYMATTR InstName R3
SYMATTR Value 10e3
SYMBOL res 240 -512 R0
SYMATTR InstName R4
SYMATTR Value 10e3
SYMBOL voltage -656 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3 0 0.001 0.001 0.5 1 15)
SYMBOL nmos 208 -224 R0
SYMATTR InstName M2
SYMATTR Value PJA3416AE_R1_00001
SYMBOL nmos 432 -432 R0
SYMATTR InstName M1
SYMATTR Value PJA3416AE_R1_00001
SYMBOL voltage -464 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 640 -208 R0
SYMATTR InstName R1
SYMATTR Value 0.833
FLAG -16 256 0
FLAG -464 -96 0
FLAG -464 -256 5V
FLAG -80 -208 0
FLAG -128 -368 SYS_PWR
FLAG -656 -96 0
FLAG -656 -272 SYS_PWR
FLAG 656 -96 0
FLAG 256 -128 0
FLAG 256 -528 5V
FLAG 480 -432 5V
FLAG 480 -336 VDD1
FLAG 656 -240 VDD1
TEXT -36 280 Left 2 !.tran 0 15 0