Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\014e455b0668_strom_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
V2 3.3 0 3.3
R3 opout N003 1k
R10 N010 N007 2.4k
C2 sigl 0 18p
R6 0 N002 470
R15 N009 sigl 470
R2 N005 3.3 2.4k
R1 N005 in 470
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 728
WIRE 416 176 -240 176
WIRE 832 176 416 176
WIRE 608 192 304 192
WIRE 800 192 608 192
WIRE 96 224 -64 224
WIRE 304 224 304 192
WIRE 304 224 96 224
WIRE 304 240 304 224
WIRE 480 240 448 240
WIRE 608 240 608 192
WIRE 416 288 416 176
WIRE 368 304 368 240
WIRE 368 304 352 304
WIRE 384 304 368 304
WIRE 480 320 480 240
WIRE 480 320 448 320
WIRE 496 320 480 320
WIRE 528 320 496 320
WIRE 608 320 608 304
WIRE 736 320 688 320
WIRE 304 336 304 320
WIRE 384 336 304 336
WIRE -240 352 -240 176
WIRE -64 352 -64 224
WIRE 112 352 48 352
WIRE 176 352 112 352
WIRE 208 352 176 352
WIRE 304 352 304 336
WIRE 304 352 288 352
WIRE 352 352 352 304
WIRE 640 352 592 352
WIRE 688 352 688 320
WIRE 688 352 640 352
WIRE 592 368 592 352
WIRE -160 432 -240 432
WIRE -64 432 -160 432
WIRE 32 432 -64 432
WIRE 48 432 32 432
WIRE 112 432 48 432
WIRE 352 432 112 432
WIRE 416 432 416 352
WIRE 416 432 352 432
WIRE 592 432 416 432
WIRE 640 432 592 432
WIRE 768 432 640 432
WIRE 832 464 416 464
WIRE 608 480 304 480
WIRE 800 480 608 480
WIRE 304 528 304 480
WIRE 480 528 448 528
WIRE 608 528 608 480
WIRE 416 576 416 464
WIRE 368 592 368 528
WIRE 368 592 352 592
WIRE 384 592 368 592
WIRE 480 608 480 528
WIRE 480 608 448 608
WIRE 496 608 480 608
WIRE 528 608 496 608
WIRE 608 608 608 592
WIRE 736 608 688 608
WIRE 752 608 736 608
WIRE 304 624 304 608
WIRE 384 624 304 624
WIRE 176 640 176 352
WIRE 208 640 176 640
WIRE 304 640 304 624
WIRE 304 640 288 640
WIRE 352 640 352 592
WIRE 640 640 592 640
WIRE 688 640 688 608
WIRE 688 640 640 640
WIRE 592 656 592 640
WIRE -240 720 -240 432
WIRE 352 720 -240 720
WIRE 416 720 416 640
WIRE 416 720 352 720
WIRE 592 720 416 720
WIRE 640 720 592 720
WIRE 768 720 640 720
SYMBOL voltage -64 336 R0
SYMATTR InstName V2
SYMATTR Value 3.3
SYMBOL res 512 336 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 320 624 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R10
SYMATTR Value 2.4k
SYMBOL cap 576 656 R0
SYMATTR InstName C2
SYMATTR Value 18p
SYMBOL res 368 448 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R6
SYMATTR Value 470
SYMBOL res 592 624 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R15
SYMATTR Value 470
SYMBOL res 320 336 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 2.4k
SYMBOL res 304 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 470
FLAG 32 432 0
FLAG 496 320 opout
FLAG 176 352 in
FLAG 96 224 3.3
FLAG -160 352 0V
FLAG 496 608 opoutl
FLAG 736 608 sigl
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1990.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 0 N002 0 -V N003 OUT +V N001 LT1990 ;pnba REF)IN-)IN+)VEE)GAIN2)OUT)VCC)GAIN1
V3 N002 0 SINE(0 1 10K)
V1 +V 0 5
V2 -V 0 -5
.tran 1m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1990.asy)
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 112 144 80
WIRE 368 160 336 160
WIRE -32 192 -256 192
WIRE -256 208 -256 192
WIRE -32 224 -32 192
WIRE -16 224 -32 224
WIRE -496 240 -496 224
WIRE -384 240 -384 224
WIRE 384 240 336 240
WIRE -16 256 -32 256
WIRE 368 288 336 288
WIRE -256 304 -256 288
WIRE -32 304 -32 256
WIRE -32 304 -256 304
WIRE -256 320 -256 304
WIRE -496 336 -496 320
WIRE -384 336 -384 320
WIRE 80 432 80 400
WIRE 144 432 144 400
FLAG -256 320 0
FLAG -496 336 0
FLAG -384 336 0
FLAG 384 240 OUT
FLAG 80 432 0
FLAG -496 224 +V
FLAG -384 224 -V
FLAG 144 80 +V
FLAG 144 432 -V
SYMBOL LT1990 160 240 R0
SYMATTR InstName U1
SYMBOL voltage -256 192 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage -496 224 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -384 224 R0
SYMATTR InstName V2
SYMATTR Value -5
TEXT 368 352 Left 2 !.tran 1m
* Z:\tmp\asc_dec_bjh7r6w2\1585d244dd81_OPA2392_Trans_Amp_AC_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N003 N005 1.5n V=50
L1 SIG_OUT N003 1T
R1 N003 N002 2k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1004 680
WIRE 208 144 32 144
WIRE 416 160 272 160
WIRE 496 160 416 160
WIRE 208 176 144 176
WIRE 192 272 32 272
WIRE 416 272 416 240
WIRE 416 272 272 272
WIRE 448 272 416 272
WIRE 544 272 512 272
WIRE 544 304 544 272
WIRE 192 368 32 368
WIRE 416 368 416 272
WIRE 416 368 256 368
SYMBOL cap 256 352 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1.5n
SYMATTR SpiceLine V=50
SYMBOL ind 400 144 R0
SYMATTR InstName L1
SYMATTR Value 1T
SYMBOL res 288 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2k
FLAG 496 160 SIG_OUT
FLAG 240 192 0
FLAG 240 128 V+
FLAG 144 176 0
* Z:\home\khalils\Downloads\files\data\raw_asc\009751c7ab1c_1818.asc
* Generated by LTspice 26.0.1 for Windows.
* 80MHz, 20dB Gain Block
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1818.asy)
R2 N002 0 200
R1 N003 N002 432
XU2 N003 N001 OUT +V -V LT1818 ;pnba IN+)IN-)OUT)VCC)VEE
XU1 IN N002 N003 +V -V LT1818 ;pnba IN+)IN-)OUT)VCC)VEE
R3 OUT N001 432
V1 +V 0 5
V3 IN 0 AC 1
R4 N001 0 200
V2 -V 0 -5
.ac oct 10 100K 500Meg
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 240 32 224 32
WIRE 336 32 320 32
WIRE 352 32 336 32
WIRE 464 32 432 32
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -160 160 -160 144
WIRE -64 160 -64 144
WIRE 400 192 400 176
WIRE 192 208 192 192
WIRE 336 208 336 32
WIRE 368 208 336 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 464 224 464 32
WIRE 464 224 432 224
WIRE 496 224 464 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 368 240 256 240
WIRE -160 256 -160 240
WIRE -64 256 -64 240
WIRE 160 256 32 256
WIRE 32 272 32 256
WIRE 400 272 400 256
WIRE 192 288 192 272
WIRE 32 368 32 352
SYMBOL res 448 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 432
SYMBOL voltage -160 144 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 336 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL voltage -64 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 32 256 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 432
SYMBOL opamps\\LT1818 400 224 R0
SYMATTR InstName U2
SYMBOL opamps\\LT1818 192 240 R0
SYMATTR InstName U1
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200
FLAG -64 256 0
FLAG 192 192 +V
FLAG -64 144 +V
FLAG 192 288 -V
FLAG -160 256 0
FLAG -160 144 -V
FLAG 16 96 0
FLAG 32 368 0
FLAG 400 176 +V
FLAG 400 272 -V
FLAG 224 32 0
FLAG 496 224 OUT
FLAG 32 256 IN
TEXT 232 344 Left 2 !.ac oct 10 100K 500Meg
TEXT 264 -32 Bottom 2 ;80MHz, 20dB Gain Block
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG712.asc
* Generated by LTspice 26.0.1 for Windows.
V1 vS 0 3
R1 vD 0 301
V2 vIN 0 PULSE(0 3 0 10n 10n 980n 2u)
C1 vD 0 36p
V3 v+ 0 5
XU1 v+ vS vD vIN 0 ADG712 ;pnba Vdd)S)D)IN)GND
.tran 10u
* Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 5V single supply\nOny one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG712.asy)
.lib ADG712.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 256 96 240 96
WIRE 240 160 240 96
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -176 304 -192 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE 240 432 240 400
WIRE -192 464 -192 416
WIRE 48 464 48 416
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 240 432 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -192 304 v+
FLAG 240 96 v+
FLAG -192 464 0
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V2
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL ADG712 240 272 R0
SYMATTR InstName U1
TEXT 336 424 Left 2 !.tran 10u
TEXT -360 -16 Left 2 ;Note:\nSwitch shown for a logic 1 input\nParameter performance modeled at 5V single supply\nOny one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\3a91c7ff7975_Draft7.asc
* Generated by LTspice 26.0.1 for Windows.
* .tran 10000n
C2 N001 0 7.86n
C1 Vout N001 3.25n
R1 Vout 0 2.7k
R3 N002 0 0.5
R2 Vin N001 150
V1 Vin 0 SINE(0 1 10.7Meg 0 0 0 0) AC 1 0
L1 Vout N002 96.2n
C3 Vout 0 8p
.ac dec 1000 100k 100Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3220 680
WIRE 720 64 544 64
WIRE 912 64 720 64
WIRE 1072 64 912 64
WIRE 544 80 544 64
WIRE 112 112 0 112
WIRE 720 128 720 64
WIRE 0 144 0 112
WIRE 912 144 912 64
WIRE 1072 144 1072 64
WIRE 112 176 112 112
WIRE 544 176 544 144
WIRE 544 176 192 176
WIRE 544 208 544 176
WIRE 720 224 720 208
WIRE 0 320 0 224
WIRE 544 320 544 272
WIRE 544 320 0 320
WIRE 720 320 720 304
WIRE 720 320 544 320
WIRE 912 320 912 208
WIRE 912 320 720 320
WIRE 1072 320 1072 224
WIRE 1072 320 912 320
WIRE 0 368 0 320
SYMBOL voltage 0 128 R0
WINDOW 3 24 156 Left 2
WINDOW 123 24 126 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0 1 10.7Meg 0 0 0 0)
SYMATTR Value2 AC 1 0
SYMATTR InstName V1
SYMBOL cap 896 144 R0
SYMATTR InstName C3
SYMATTR Value 8p
SYMBOL res 96 192 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 150
SYMBOL ind 704 112 R0
SYMATTR InstName L1
SYMATTR Value 96.2n
SYMBOL cap 528 80 R0
SYMATTR InstName C1
SYMATTR Value 3.25n
SYMBOL cap 528 208 R0
SYMATTR InstName C2
SYMATTR Value 7.86n
SYMBOL res 704 208 R0
SYMATTR InstName R3
SYMATTR Value 0.5
SYMBOL res 1056 128 R0
SYMATTR InstName R1
SYMATTR Value 2.7k
FLAG 0 368 0
FLAG 0 112 Vin
FLAG 1072 64 Vout
TEXT -400 176 Left 2 !.ac dec 1000 100k 100Meg
TEXT -400 208 Left 2 ;.tran 10000n
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8041.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8041.asy)
XU1 IN N001 +V -V OUT NC_01 AD8041 ;pnba In+)In-)V+)V-)OUT)SHDN
R2 OUT N001 1K
Vin IN 0 SINE(0 1 100K)
V2 -V 0 -5
V1 +V 0 5
R1 N001 0 1K
.tran 100u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1216 416 -1216
WIRE 528 -1216 512 -1216
WIRE 544 -1216 528 -1216
WIRE 640 -1216 624 -1216
WIRE 160 -1152 160 -1168
WIRE 272 -1152 272 -1168
WIRE 528 -1120 528 -1216
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1216
WIRE 640 -1104 608 -1104
WIRE 720 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 432 -1072 432 -1088
WIRE 160 -1040 160 -1072
WIRE 272 -1040 272 -1072
WIRE 432 -976 432 -992
SYMBOL voltage 272 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 160 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 528 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL res 640 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 100K)
SYMBOL opamps\\AD8041 576 -1104 R0
SYMATTR InstName U1
FLAG 160 -1168 +V
FLAG 432 -976 0
FLAG 720 -1104 OUT
FLAG 432 -1088 IN
FLAG 560 -1136 +V
FLAG 272 -1168 -V
FLAG 560 -1072 -V
FLAG 416 -1216 0
FLAG 272 -1040 0
FLAG 160 -1040 0
TEXT 664 -944 Left 2 !.tran 100u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7118-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7118-1.8.asy)
C1 OUT 0 2.2 Rser=1.5m
Rload OUT 0 10
XU1 IN OUT IN N001 OUT 0 ADP7118 Vref=1.8 ;pnba Vin)Sense)EN)SS)Vout)GND
V1 IN 0 2.8
C2 N001 0 4.7n
.tran 6m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
SYMBOL ADP7118-1.8 224 128 R0
SYMATTR InstName U1
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 2.8
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
TEXT 408 264 Left 2 !.tran 6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\920c2e0e9294_Single-phase-rectifier-constant-voltage-load.asc
* Generated by LTspice 26.0.1 for Windows.
* Maximum load voltage so that we have continuous conduction mode: \n \nVs = RMS value of sinusoidal voltage source \nVo_max = (2*sqrt(2)*Vs/pi) / sqrt(1+4/pi^2)
* Single phase AC/DC converter (rectifier)
D2 0 N004 D
L1 N002 N003 10m
D3 N004 N001 D
D1 N003 N001 D
V1 N002 N004 SINE(0 325 50)
V2 N001 0 200
D4 0 N003 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 30m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1420 680
WIRE 208 -32 64 -32
WIRE 352 -32 208 -32
WIRE 64 32 64 -32
WIRE 208 32 208 -32
WIRE 352 112 352 -32
WIRE -112 128 -256 128
WIRE 64 128 64 96
WIRE 64 128 -32 128
WIRE -256 144 -256 128
WIRE -256 240 -256 224
WIRE 208 240 208 96
WIRE 208 240 -256 240
WIRE 64 256 64 128
WIRE 208 256 208 240
WIRE 64 368 64 320
WIRE 208 368 208 320
WIRE 208 368 64 368
WIRE 352 368 352 192
WIRE 352 368 208 368
WIRE 64 384 64 368
SYMBOL diode 80 320 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMBOL diode 224 320 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL voltage -256 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 325 50)
SYMBOL ind -128 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10m
SYMBOL diode 224 96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMBOL diode 80 96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL voltage 352 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 200
FLAG 64 384 0
TEXT -136 16 Left 2 !.tran 30m
TEXT 472 40 Left 2 ;Maximum load voltage so that we have continuous conduction mode: \n \nVs = RMS value of sinusoidal voltage source \nVo_max = (2*sqrt(2)*Vs/pi) / sqrt(1+4/pi^2)
TEXT -16 -104 Left 2 ;Single phase AC/DC converter (rectifier)
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8237.asc
* Generated by LTspice 26.0.1 for Windows.
* Configured for\ngain of 10V/V
* Note:\nIn high bandwidth mode,\nreal part has instability for G < 10 V/V
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8237.asy)
V1 Vs+ 0 5
V5 Vin+ N001 SINE(0 10m 1k)
V4 N001 0 2.5
V2 Vs- 0 0
R1 Vref N002 1k
R2 Vout N002 9k
V6 N001 Vin- SINE(0 10m 1k)
V3 Vref 0 2.5
XU1 Vs- Vin+ Vin- Vs- Vs+ Vref N002 Vout AD8237 ;pnba 1)2)3)4)5)6)7)8
.tran 5m
.lib AD8237.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1776 680
WIRE -128 16 -272 16
WIRE -272 32 -272 16
WIRE 48 48 48 32
WIRE 80 80 80 64
WIRE -128 96 -128 16
WIRE -32 96 -128 96
WIRE 16 96 -32 96
WIRE -272 128 -272 112
WIRE -272 128 -400 128
WIRE 192 128 144 128
WIRE 256 128 192 128
WIRE -272 144 -272 128
WIRE 192 144 192 128
WIRE -752 160 -752 128
WIRE -640 160 -640 128
WIRE -528 160 -528 128
WIRE -400 160 -400 128
WIRE -32 160 -128 160
WIRE 16 160 -32 160
WIRE 48 224 48 208
WIRE 48 224 32 224
WIRE -272 240 -272 224
WIRE -128 240 -128 160
WIRE -128 240 -272 240
WIRE 112 240 112 160
WIRE 192 240 192 224
WIRE 192 240 112 240
WIRE -752 256 -752 240
WIRE -640 256 -640 240
WIRE -528 256 -528 240
WIRE -400 256 -400 240
WIRE 80 256 80 192
WIRE 80 288 80 256
WIRE 96 288 80 288
WIRE 192 288 192 240
WIRE 192 288 176 288
SYMBOL AD8237 80 128 R0
SYMATTR InstName U1
SYMBOL voltage -640 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL res 80 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -272 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 0 133 Left 2
WINDOW 0 26 96 Left 2
SYMATTR Value SINE(0 10m 1k)
SYMATTR InstName V6
SYMBOL voltage -752 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 176 128 R0
SYMATTR InstName R2
SYMATTR Value 9k
SYMBOL voltage -400 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 2.5
SYMBOL voltage -528 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 2.5
SYMBOL voltage -272 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -2 -22 Left 2
SYMATTR Value SINE(0 10m 1k)
SYMATTR InstName V5
FLAG -32 160 Vin-
FLAG -32 96 Vin+
FLAG 256 128 Vout
FLAG -752 128 Vs+
FLAG -640 128 Vs-
FLAG -752 256 0
FLAG -640 256 0
FLAG -528 128 Vref
FLAG -528 256 0
FLAG -400 256 0
FLAG 32 224 Vs-
FLAG 48 32 Vs+
FLAG 80 64 Vs-
FLAG 80 256 Vref
TEXT 224 264 Left 2 ;Configured for\ngain of 10V/V
TEXT -24 352 Left 2 ;Note:\nIn high bandwidth mode,\nreal part has instability for G < 10 V/V
TEXT -816 416 Left 2 !.tran 5m
* Z:\tmp\asc_dec_bjh7r6w2\0cfb06316b97_Impedance_Pt1_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N002 0 SINE(0 1 100e3)
V1 N001 0 SINE(0 1 100e3)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2688 680
WIRE 304 48 16 48
WIRE 864 48 576 48
WIRE 16 128 16 48
WIRE 576 128 576 48
WIRE 16 256 16 208
WIRE 576 256 576 208
SYMBOL voltage 576 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1 100e3)
SYMBOL voltage 16 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 100e3)
FLAG 16 256 0
FLAG 576 256 0
* Z:\home\khalils\Downloads\files\data\raw_asc\3563c70a567f_Fig_9-4_Howland.asc
* Generated by LTspice 26.0.1 for Windows.
* Iout = V(in)/1K
* This example schematic is supplied for informational/educational purposes only.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1001.asy)
R1 N001 N002 1K
R2 IN N001 1K
Rload N003 0 {x}
R3 N003 N002 1K
V2 -V 0 -15
V3 IN 0 SINE(0 1 1K)
V1 +V 0 +15
XU2 N003 N001 +V -V N002 LT1001 ;pnba In+)In-)V+)V-)OUT
R4 0 N003 1K
.tran 3m
.step param X list 1 10 100 1K
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 696
WIRE 16 160 -96 160
WIRE 144 160 96 160
WIRE 192 160 144 160
WIRE 304 160 272 160
WIRE -96 176 -96 160
WIRE 144 256 144 160
WIRE 160 256 144 256
WIRE -96 272 -96 256
WIRE 304 272 304 160
WIRE 304 272 224 272
WIRE 160 288 144 288
WIRE -256 368 -256 352
WIRE -128 368 -128 352
WIRE 16 368 -16 368
WIRE 144 368 144 288
WIRE 144 368 96 368
WIRE 192 368 144 368
WIRE 304 368 304 272
WIRE 304 368 272 368
WIRE 144 416 144 368
WIRE 448 416 144 416
WIRE 560 416 528 416
WIRE -256 464 -256 448
WIRE -128 464 -128 448
SYMBOL res 176 352 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1K
SYMBOL voltage -128 352 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL opamps\\LT1001 192 208 R0
SYMATTR InstName U2
SYMBOL res 0 352 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1K
SYMBOL res 432 432 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName Rload
SYMATTR Value {x}
SYMBOL voltage -256 352 R0
SYMATTR InstName V1
SYMATTR Value +15
SYMBOL res 0 144 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 176 144 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage -96 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
FLAG -128 464 0
FLAG -256 464 0
FLAG 192 240 +V
FLAG -256 352 +V
FLAG -128 352 -V
FLAG 192 304 -V
FLAG -96 272 0
FLAG -96 160 IN
FLAG -16 368 0
FLAG 560 416 0
TEXT -56 496 Left 2 !.tran 3m
TEXT -56 528 Left 2 !.step param X list 1 10 100 1K
TEXT 248 464 Bottom 2 ;Iout = V(in)/1K
TEXT -296 576 Left 2 ;This example schematic is supplied for informational/educational purposes only.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6993-1.asc
* Generated by LTspice 26.0.1 for Windows.
* LTC6993-1 Non-Retriggerable 20ms One Shot\nRising Edge Triggered, Positive Output Pulse\nStartup Modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC6993-1.asy)
V1 N002 0 5
R3 N004 0 392K
V2 N001 0 PULSE(0 3.3 1m 1n 1n 2m 15m 3)
XU1 N001 0 N003 N004 N002 OUT LTC6993-1 ;pnba TRIG)GND)SET)DIV)V+)OUT
R2 N002 N004 1000K
R1 N003 0 243K
R4 OUT 0 100K
.tran 60m startup
.lib LTC6993-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -272 96 -304 96
WIRE 96 96 -192 96
WIRE 592 96 320 96
WIRE 592 112 592 96
WIRE 96 176 80 176
WIRE 368 176 320 176
WIRE 512 176 368 176
WIRE 368 192 368 176
WIRE 512 192 512 176
WIRE 592 208 592 192
WIRE 0 256 -16 256
WIRE 96 256 80 256
WIRE 336 256 320 256
WIRE 336 288 336 256
WIRE 368 288 368 272
WIRE 368 288 336 288
WIRE 512 288 512 272
WIRE 368 304 368 288
WIRE 368 400 368 384
SYMBOL res 352 288 R0
SYMATTR InstName R3
SYMATTR Value 392K
SYMBOL res 576 96 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL SpecialFunctions\\LTC6993-1 208 176 R0
SYMATTR InstName U1
SYMBOL voltage 512 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 352 176 R0
SYMATTR InstName R2
SYMATTR Value 1000K
SYMBOL voltage -176 96 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 3 32 56 VTop 2
WINDOW 0 -32 56 VBottom 2
SYMATTR Value PULSE(0 3.3 1m 1n 1n 2m 15m 3)
SYMATTR InstName V2
SYMBOL res 96 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 243K
FLAG -304 96 0
FLAG 512 288 0
FLAG 592 96 OUT
FLAG -16 256 0
FLAG 368 400 0
FLAG 592 208 0
FLAG 80 176 0
TEXT 488 376 Left 2 !.tran 60m startup
TEXT 208 56 Bottom 2 ;LTC6993-1 Non-Retriggerable 20ms One Shot\nRising Edge Triggered, Positive Output Pulse\nStartup Modeled