* Z:\home\khalils\Downloads\files\data\raw_asc\3baeb775acf8_CHAU_TL082.asc
* Generated by LTspice 26.0.1 for Windows.
* WWW.CHAOTIC-CIRCUITS.COM
* CHUA'S CIRCUIT\nThis circuit is based on the work of Michael P. Kennedy.
* TL082 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT
* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08
* (REV N/A) SUPPLY VOLTAGE: +/-15V
* ------------------------------------------------------------------------
*|(C) Copyright Texas Instruments Incorporated 2007. All rights reserved. |
*| |
*|This Model is designed as an aid for customers of Texas Instruments. |
*|No warranties, either expressed or implied, with respect to this Model |
*|or its fitness for a particular purpose is claimed by Texas Instruments |
*|or the author. The Model is licensed solely on an "as is" basis. The |
*|entire risk as to its quality and performance is with the customer. |
* ------------------------------------------------------------------------
* CONNECTIONS: NON-INVERTING INPUT
* | INVERTING INPUT
* | | POSITIVE POWER SUPPLY
* | | | NEGATIVE POWER SUPPLY
* | | | | OUTPUT
* | | | | |
*
VLN 0 92 DC 25
C1 11 12 3.498E-12
R5 N002 N004 22K tol=5 pwr=1
R6 N004 0 3.3K tol=5 pwr=1
R2 6 9 100.0E3
VB 9 0 DC 0
DC 5 53 DX
V1 N006 0 9V
C2 6 7 15.00E-12
J1 11 2 10 JX
L1 N007 0 .018 Ipk=1 Rser=0
GCM 0 6 10 99 8.942E-9
DP 4 3 DX
R1 Vc1 N001 220 tol=5 pwr=1
VLP 91 0 DC 25
VLIM 7 8 DC 0
R2 N005 N001 220 tol=5 pwr=1
GA 6 0 11 12 282.8E-6
R7 Vc1 Vc2 1.67k tol=5 pwr=1
R8 Vc2 N007 14 tol=5 pwr=1
DLP 90 91 DX
R4 N002 Vc1 22K tol=5 pwr=1
DLN 92 90 DX
RO1 8 5 150
EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5
VE 54 4 DC 2.200
RD2 4 12 3.536E3
RD1 4 11 3.536E3
RP 3 4 2.143E3
RO2 7 99 150
VC 3 53 DC 2.200
RSS 10 99 1.026E6
C2 Vc2 0 1E-7 V=100
J2 12 1 10 JX
FB 7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6
XU2 Vc1 N005 N006 N003 N001 TL082 ;pnba In+)In-)V+)V-)OUT
DE 54 5 DX
XU1 Vc1 N004 N006 N003 N002 TL082 ;pnba In+)In-)V+)V-)OUT
ISS 3 10 DC 195.0E-6
C1 Vc1 0 1E-8 V=100
R3 N005 0 2.2K tol=5 pwr=1
V2 N003 0 -9V
HLIM 90 0 VLIM 1K
.tran 0 .10 0 1E-5
.SUBCKT TL082 1 2 3 4 5
.MODEL DX D(IS=800.0E-18)
.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)
.ENDS
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 924 2032
WIRE -2240 -128 -2240 -176
WIRE -2240 -128 -2336 -128
WIRE -2144 -128 -2240 -128
WIRE -1952 -128 -1952 -176
WIRE -1952 -128 -2064 -128
WIRE -1712 -128 -1952 -128
WIRE -1488 -128 -1712 -128
WIRE -1488 -80 -1488 -128
WIRE -1456 -80 -1488 -80
WIRE -1264 -80 -1376 -80
WIRE -1712 -64 -1712 -128
WIRE -1600 -64 -1632 -64
WIRE -1552 0 -1664 0
WIRE -1360 0 -1552 0
WIRE -2336 16 -2336 -128
WIRE -1664 32 -1664 0
WIRE -1712 48 -1712 -64
WIRE -1696 48 -1712 48
WIRE -1360 48 -1360 0
WIRE -2240 64 -2240 -128
WIRE -1952 64 -1952 -128
WIRE -1600 64 -1600 -64
WIRE -1600 64 -1632 64
WIRE -1488 64 -1488 -80
WIRE -1392 64 -1488 64
WIRE -1696 80 -1744 80
WIRE -1264 80 -1264 -80
WIRE -1264 80 -1328 80
WIRE -1392 96 -1472 96
WIRE -1664 144 -1664 96
WIRE -1504 144 -1664 144
WIRE -1360 144 -1360 112
WIRE -1360 144 -1504 144
WIRE -2336 160 -2336 96
WIRE -1504 176 -1504 144
WIRE -1056 176 -1504 176
WIRE -1744 208 -1744 80
WIRE -1744 208 -1776 208
WIRE -1712 208 -1744 208
WIRE -1600 208 -1600 64
WIRE -1600 208 -1632 208
WIRE -1472 240 -1472 96
WIRE -1408 240 -1472 240
WIRE -1264 240 -1264 80
WIRE -1264 240 -1328 240
WIRE -1056 272 -1056 176
WIRE -1056 304 -1056 272
WIRE -1776 320 -1776 208
WIRE -1472 320 -1472 240
WIRE -1552 512 -1552 0
WIRE -2336 752 -2336 240
WIRE -2240 752 -2240 128
WIRE -2240 752 -2336 752
WIRE -1952 752 -1952 128
WIRE -1952 752 -2240 752
WIRE -1776 752 -1776 400
WIRE -1776 752 -1952 752
WIRE -1680 752 -1776 752
WIRE -1552 752 -1552 592
WIRE -1552 752 -1680 752
WIRE -1472 752 -1472 400
WIRE -1472 752 -1552 752
WIRE -1056 752 -1056 352
WIRE -1056 752 -1472 752
WIRE -1680 816 -1680 752
DATAFLAG -2096 -112 ""
SYMBOL res -1488 304 R0
WINDOW 0 81 36 Left 2
WINDOW 3 75 64 Left 2
SYMATTR InstName R3
SYMATTR Value 2.2K
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL res -2048 -112 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R7
SYMATTR Value 1.67k
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL voltage -1552 496 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V2
SYMATTR Value -9V
SYMBOL Opamps\\opamp2 -1664 128 M180
SYMATTR InstName U1
SYMATTR Value TL082
SYMBOL res -1616 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 22K
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL cap -2256 64 R0
WINDOW 0 59 10 Left 2
WINDOW 3 59 51 Left 2
SYMATTR InstName C2
SYMATTR Value 1E-7
SYMATTR SpiceLine V=100
SYMBOL ind -2320 144 M0
SYMATTR InstName L1
SYMATTR Value .018
SYMATTR SpiceLine Ipk=1 Rser=0
SYMBOL res -1760 304 M0
SYMATTR InstName R6
SYMATTR Value 3.3K
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL cap -1968 64 R0
WINDOW 0 65 5 Left 2
WINDOW 3 58 39 Left 2
SYMATTR InstName C1
SYMATTR Value 1E-8
SYMATTR SpiceLine V=100
SYMBOL res -1616 -48 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 22K
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL Opamps\\opamp2 -1360 144 M180
SYMATTR InstName U2
SYMATTR Value TL082
SYMBOL res -2320 0 M0
SYMATTR InstName R8
SYMATTR Value 14
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL res -1424 256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -7 45 VBottom 2
SYMATTR InstName R2
SYMATTR Value 220
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL res -1472 -64 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 220
SYMATTR SpiceLine tol=5 pwr=1
SYMBOL voltage -1056 256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName V1
SYMATTR Value 9V
FLAG -1680 816 0
FLAG -1952 -176 Vc1
FLAG -2240 -176 Vc2
TEXT -2440 840 Left 2 !.tran 0 .10 0 1E-5
TEXT -384 -1272 Left 5 ;WWW.CHAOTIC-CIRCUITS.COM
TEXT -384 -1200 Left 4 ;CHUA'S CIRCUIT\nThis circuit is based on the work of Michael P. Kennedy.
TEXT -352 -992 Left 3 !* TL082 OPERATIONAL AMPLIFIER "MACROMODEL" SUBCIRCUIT\n* CREATED USING PARTS RELEASE 4.01 ON 06/16/89 AT 13:08\n* (REV N/A)      SUPPLY VOLTAGE: +/-15V\n* ------------------------------------------------------------------------\n*|(C) Copyright Texas Instruments Incorporated 2007. All rights reserved. |\n*|                                                                        |\n*|This Model is designed as an aid for customers of Texas Instruments.    |\n*|No warranties, either expressed or implied, with respect to this Model  |\n*|or its fitness for a particular purpose is claimed by Texas Instruments |\n*|or the author.  The Model is licensed solely on an "as is" basis.  The  |\n*|entire risk as to its quality and performance is with the customer.     |\n* ------------------------------------------------------------------------\n* CONNECTIONS:   NON-INVERTING INPUT\n*                | INVERTING INPUT\n*                | | POSITIVE POWER SUPPLY\n*                | | | NEGATIVE POWER SUPPLY\n*                | | | | OUTPUT\n*                | | | | |\n.SUBCKT TL082    1 2 3 4 5\n*\n  C1   11 12 3.498E-12\n  C2    6  7 15.00E-12\n  DC    5 53 DX\n  DE   54  5 DX\n  DLP  90 91 DX\n  DLN  92 90 DX\n  DP    4  3 DX\n  EGND 99  0 POLY(2) (3,0) (4,0) 0 .5 .5\n  FB    7 99 POLY(5) VB VC VE VLP VLN 0 4.715E6 -5E6 5E6 5E6 -5E6\n  GA    6  0 11 12 282.8E-6\n  GCM   0  6 10 99 8.942E-9\n  ISS   3 10 DC 195.0E-6\n  HLIM 90  0 VLIM 1K\n  J1   11  2 10 JX\n  J2   12  1 10 JX\n  R2    6  9 100.0E3\n  RD1   4 11 3.536E3\n  RD2   4 12 3.536E3\n  RO1   8  5 150\n  RO2   7 99 150\n  RP    3  4 2.143E3\n  RSS  10 99 1.026E6\n  VB    9  0 DC 0\n  VC    3 53 DC 2.200\n  VE   54  4 DC 2.200\n  VLIM  7  8 DC 0\n  VLP  91  0 DC 25\n  VLN   0 92 DC 25\n.MODEL DX D(IS=800.0E-18)\n.MODEL JX PJF(IS=15.00E-12 BETA=270.1E-6 VTO=-1)\n.ENDS