Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1006A.asc
* Generated by LTspice 26.0.1 for Windows.
* Gain 100 Amplifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1006A.asy)
V1 +V 0 5
R1 OUT N001 99K
R2 N001 0 1K
R3 OUT 0 660
V3 IN 0 SINE(5m 1m 1K)
XU1 IN N001 +V 0 OUT LT1006 ;pnba In+)In-)V+)V-)OUT
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 112 16 112
WIRE 128 112 112 112
WIRE 160 112 128 112
WIRE 272 112 240 112
WIRE 192 208 192 192
WIRE 128 224 128 112
WIRE 160 224 128 224
WIRE -80 240 -80 224
WIRE 272 240 272 112
WIRE 272 240 224 240
WIRE 336 240 272 240
WIRE 160 256 48 256
WIRE 336 256 336 240
WIRE 48 272 48 256
WIRE 192 288 192 272
WIRE -80 336 -80 320
WIRE 336 352 336 336
WIRE 48 368 48 352
SYMBOL opamps\\LT1006A 192 176 R0
SYMATTR InstName U1
SYMBOL res 256 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 99K
SYMBOL voltage 48 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(5m 1m 1K)
SYMBOL res 320 240 R0
SYMATTR InstName R3
SYMATTR Value 660
SYMBOL res 128 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -80 224 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -80 336 0
FLAG 192 192 +V
FLAG -80 224 +V
FLAG 16 112 0
FLAG 48 368 0
FLAG 192 288 0
FLAG 336 352 0
FLAG 336 240 OUT
FLAG 48 256 IN
TEXT 288 400 Left 2 !.tran 3m
TEXT 152 56 Bottom 2 ;Gain 100 Amplifier
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1262.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1262.asy)
XU1 N001 N002 N003 N004 IN OUT 0 0 LTC1262 ;pnba C1-)C1+)C2-)C2+)Vcc)OUT)GND)SHDN
V1 IN 0 5
C1 N001 N002 .22
C3 OUT 0 4.7
C2 N003 N004 .22
Rload OUT 0 1K
.tran 1m
.lib LTC1262.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3308 2256
WIRE 2624 1904 2544 1904
WIRE 2960 1904 2912 1904
WIRE 2624 1968 2544 1968
WIRE 2960 1968 2960 1904
WIRE 2960 1968 2912 1968
WIRE 2960 1984 2960 1968
WIRE 2624 2032 2544 2032
WIRE 3056 2032 2912 2032
WIRE 3168 2032 3056 2032
WIRE 3056 2048 3056 2032
WIRE 3168 2048 3168 2032
WIRE 2624 2096 2544 2096
WIRE 2960 2096 2912 2096
WIRE 2960 2112 2960 2096
WIRE 3056 2144 3056 2112
WIRE 3168 2144 3168 2128
WIRE 2960 2208 2960 2192
SYMBOL voltage 2960 2096 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 2528 2032 R0
WINDOW 0 39 14 Left 2
WINDOW 3 36 46 Left 2
SYMATTR InstName C2
SYMATTR Value .22
SYMBOL cap 2528 1904 R0
WINDOW 0 39 18 Left 2
WINDOW 3 33 48 Left 2
SYMATTR InstName C1
SYMATTR Value .22
SYMBOL PowerProducts\\LTC1262 2768 2000 R0
SYMATTR InstName U1
SYMBOL cap 3040 2048 R0
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL res 3152 2032 R0
SYMATTR InstName Rload
SYMATTR Value 1K
FLAG 2960 1984 0
FLAG 2960 2208 0
FLAG 3168 2144 0
FLAG 3056 2144 0
FLAG 3168 2032 OUT
FLAG 2960 2096 IN
TEXT 3128 2240 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\3b21bd6ab2aa_ABC-DQ.asc
* Generated by LTspice 26.0.1 for Windows.
BVsd1 out1 0 V = (2/3) * (cos(V(in4))*V(in1) + cos(V(in4) - 2*pi/3)*V(in2) + cos(V(in4) - 4*pi/3)*V(in3))
BVsq1 out2 0 V = (2/3) * (-sin(V(in4))*V(in1) - sin(V(in4) - 2*pi/3)*V(in2) - sin(V(in4) - 4*pi/3)*V(in3))
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1940 680
WIRE 656 0 416 0
WIRE 304 64 224 64
WIRE 656 64 528 64
WIRE 304 112 224 112
WIRE 416 128 416 0
WIRE 528 128 528 64
WIRE 304 160 224 160
WIRE 304 208 224 208
WIRE 416 224 416 208
WIRE 528 224 528 208
FLAG 224 64 in1
IOPIN 224 64 In
FLAG 224 112 in2
IOPIN 224 112 In
FLAG 224 160 in3
IOPIN 224 160 In
FLAG 224 208 in4
IOPIN 224 208 In
FLAG 416 224 0
FLAG 528 224 0
FLAG 656 0 out1
IOPIN 656 0 Out
FLAG 656 64 out2
IOPIN 656 64 Out
SYMBOL bv 416 112 R0
WINDOW 3 35 188 Left 2
SYMATTR Value V = (2/3) * (cos(V(in4))*V(in1) + cos(V(in4) - 2*pi/3)*V(in2) + cos(V(in4) - 4*pi/3)*V(in3))
SYMATTR InstName Vsd1
SYMBOL bv 528 112 R0
WINDOW 3 -28 224 Left 2
SYMATTR Value V = (2/3) * (-sin(V(in4))*V(in1) - sin(V(in4) - 2*pi/3)*V(in2) - sin(V(in4) - 4*pi/3)*V(in3))
SYMATTR InstName Vsq1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3310-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3310-1.asy)
R4 N003 P002 17.5k
C2 P001 0 4.7n
C3 P002 0 330p
V1 IN 0 3.3
C1 OUT 0 47 x7 Rser=5m
Rload OUT 0 .1
R3 OUT N001 500k
L1 N002 OUT 100n Rser=2m
R5 N004 0 274k
XU1 IN IN N002 OUT 0 0 N004 N001 IN N003 P001 LTC3310-1 ;pnba Vin)EN)SW)Vout)Agnd)Pgnd)Rt)Pgood)Mode/Sync)Ith)SSTT
.tran .4m startup
.lib LTC3310-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2648 1864
WIRE 1536 1248 1424 1248
WIRE 1712 1248 1536 1248
WIRE 1424 1264 1424 1248
WIRE 1712 1280 1712 1248
WIRE 1536 1328 1536 1248
WIRE 1552 1328 1536 1328
WIRE 1920 1328 1872 1328
WIRE 2032 1328 2000 1328
WIRE 1424 1360 1424 1344
WIRE 1536 1424 1536 1328
WIRE 1552 1424 1536 1424
WIRE 1920 1424 1872 1424
WIRE 2032 1424 2032 1328
WIRE 2032 1424 2000 1424
WIRE 2096 1424 2032 1424
WIRE 2208 1424 2096 1424
WIRE 2096 1440 2096 1424
WIRE 2208 1440 2208 1424
WIRE 2032 1520 2032 1424
WIRE 2032 1520 1872 1520
WIRE 2096 1536 2096 1504
WIRE 2208 1536 2208 1520
WIRE 1392 1616 1376 1616
WIRE 1552 1616 1536 1616
WIRE 1888 1616 1872 1616
WIRE 1984 1616 1968 1616
WIRE 1648 1680 1648 1664
WIRE 1776 1680 1776 1664
SYMBOL cap 2080 1440 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 x7
SYMATTR InstName C1
SYMATTR Value 47
SYMATTR SpiceLine Rser=5m
SYMBOL res 1552 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 17.5k
SYMBOL res 1872 1632 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R5
SYMATTR Value 274k
SYMBOL ind 1904 1440 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100n
SYMATTR SpiceLine Rser=2m
SYMBOL res 2192 1424 R0
SYMATTR InstName Rload
SYMATTR Value .1
SYMBOL cap 1552 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL LTC3310-1 1712 1456 R0
SYMATTR InstName U1
SYMBOL cap 1456 1600 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 330p
SYMBOL res 2016 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500k
SYMBOL VOLTAGE 1424 1248 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 3.3
SYMATTR InstName V1
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1424 1360 0
FLAG 2208 1536 0
FLAG 1488 1520 0
FLAG 2208 1424 OUT
FLAG 1424 1248 IN
FLAG 1376 1616 0
FLAG 2096 1536 0
FLAG 1984 1616 0
TEXT 2056 1600 Left 2 !.tran .4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG736.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\n \nCrosstalk = -60 dB Only
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG736.asy)
R1 vD1 0 301
V3 vS1B 0 0
V4 vIN1 0 PULSE(0 3.3 0 1n 1n 100u 200u)
V2 vS1A 0 3
C1 vD1 0 36p
XU1 0 N001 vIN1 0 vD1 vS1A vS1B NC_01 NC_02 0 ADG736 ;pnba GND)VDD)IN1)IN2)D1)S1A)S1B)D2)S2A)S2B
V1 N001 0 {Vdd}
.tran 1m
.param Vdd = 5
.lib ADG736.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2244 1360
WIRE 944 -336 896 -336
WIRE 1088 -336 1024 -336
WIRE 1088 -224 1088 -336
WIRE 784 -160 752 -160
WIRE 928 -160 864 -160
WIRE 976 -160 928 -160
WIRE 1264 -128 1200 -128
WIRE 1312 -128 1264 -128
WIRE 1408 -128 1312 -128
WIRE 640 -96 592 -96
WIRE 928 -96 720 -96
WIRE 976 -96 928 -96
WIRE 1312 -48 1312 -128
WIRE 928 -32 768 -32
WIRE 976 -32 928 -32
WIRE 1408 -32 1408 -128
WIRE 768 0 768 -32
WIRE 976 96 944 96
WIRE 768 112 768 80
WIRE 1312 112 1312 32
WIRE 1408 112 1408 32
WIRE 976 160 944 160
WIRE 1088 352 1088 320
RECTANGLE Normal 768 -432 16 -720 2
SYMBOL cap 1392 -32 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL res 1296 -64 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage 880 -160 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL voltage 1040 -336 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value {Vdd}
SYMBOL voltage 736 -96 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL voltage 768 -16 R0
WINDOW 0 18 8 Left 2
WINDOW 3 -485 107 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(0 3.3 0 1n 1n 100u 200u)
SYMBOL ADG736 1072 -80 R0
SYMATTR InstName U1
FLAG 896 -336 0
FLAG 1312 112 0
FLAG 1408 112 0
FLAG 1088 352 0
FLAG 768 112 0
FLAG 752 -160 0
FLAG 592 -96 0
FLAG 944 96 0
FLAG 944 160 0
FLAG 1264 -128 vD1
FLAG 928 -160 vS1A
FLAG 928 -96 vS1B
FLAG 928 -32 vIN1
TEXT 1392 360 Left 2 !.tran 1m
TEXT 32 -696 Left 2 ;Notes:\n \nCrosstalk = -60 dB Only
TEXT 32 -392 Left 2 !.param Vdd = 5
* Z:\home\khalils\Downloads\files\data\raw_asc\ADR225.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 1 5)
XU1 IN 0 OUT ADR225 ;pnba IN)GND)OUT
C1 OUT 0 1
Rload OUT 0 250
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\ADR225.asy)
.lib ADR.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE 720 -96 528 -96
WIRE 1008 -96 944 -96
WIRE 1120 -96 1008 -96
WIRE 528 -80 528 -96
WIRE 1008 -80 1008 -96
WIRE 1120 -80 1120 -96
WIRE 528 16 528 0
WIRE 1008 16 1008 -16
WIRE 1120 16 1120 0
WIRE 832 64 832 32
FLAG 528 16 0
FLAG 832 64 0
FLAG 1008 16 0
FLAG 1120 16 0
FLAG 1120 -96 OUT
FLAG 528 -96 IN
SYMBOL voltage 528 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 5)
SYMBOL References\\ADR225 832 -48 R0
SYMATTR InstName U1
SYMBOL cap 992 -80 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 1104 -96 R0
SYMATTR InstName Rload
SYMATTR Value 250
TEXT 992 96 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-4.2.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-4.2.asy)
Rload OUT 0 50
C1 OUT 0 10
V1 IN 0 3.3
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-4.2 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
L1 N001 N002 1.5 Rser=80m
.tran 400u startup
.lib ADP2504-4.2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2504-4.2 176 176 R0
SYMATTR InstName U1
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 344 392 Left 2 !.tran 400u startup
TEXT 168 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\31fb91408a68_Draft5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
C1 N001 N003 2.5m IC = 0
R4 N003 N006 200
V1 +Vs 0 5
R2 Ipv N004 3k
V2 N001 N002 0.25
R3 N004 0 1k
XU1 N006 N004 +Vs 0 N005 LT1001 ;pnba In+)In-)V+)V-)OUT
D2 0 N003 D
R1 N002 N003 1k
D1 N005 Ipv 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 20
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 952 680
WIRE 336 96 80 96
WIRE 80 144 80 96
WIRE 336 144 336 96
WIRE 80 256 80 208
WIRE 192 256 80 256
WIRE 336 256 336 208
WIRE 336 256 272 256
WIRE 416 256 336 256
WIRE 336 288 336 256
WIRE 416 304 416 256
WIRE 336 384 336 352
WIRE 512 448 480 448
WIRE 656 464 576 464
WIRE 736 464 720 464
WIRE 752 464 736 464
WIRE 416 480 416 384
WIRE 512 480 416 480
WIRE 384 592 368 592
WIRE 480 592 480 448
WIRE 480 592 464 592
WIRE 576 592 480 592
WIRE 736 592 736 464
WIRE 736 592 656 592
WIRE 368 624 368 592
IOPIN 752 464 Out
SYMBOL zener 352 352 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL cap 320 144 R0
WINDOW 39 24 84 Left 2
SYMATTR InstName C1
SYMATTR Value 2.5m
SYMATTR SpiceLine IC =  0
SYMBOL diode 656 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL Misc\\cell 80 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0.25
SYMBOL res 480 576 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 176 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL OpAmps\\OP07 544 400 R0
SYMATTR InstName U1
SYMBOL res 400 288 R0
SYMATTR InstName R4
SYMATTR Value 200
SYMBOL Misc\\cell 896 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 672 576 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 3k
FLAG 544 432 +Vs
FLAG 544 496 0
FLAG 336 384 0
FLAG 368 624 0
FLAG 896 240 0
FLAG 896 176 +Vs
FLAG 752 464 Ipv
TEXT 72 648 Left 2 !.tran 20
* Z:\home\khalils\Downloads\files\data\raw_asc\16ad8f61cd3b_NOR.asc
* Generated by LTspice 26.0.1 for Windows.
V3 B 0 PULSE(5 0 0 60ps 60ps 4ns 8ns)
M4 Vdd B N001 Vdd PMOS l=0.6u w=6u
V2 A 0 PULSE(5 0 0 60ps 60ps 2ns 4ns)
M1 out A 0 0 NMOS l=0.6u w=3u
V1 Vdd 0 5v
M2 out B 0 0 NMOS l=0.6u w=3u
M3 N001 A out Vdd PMOS l=0.6u w=6u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 20ns 0 0.001ns
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 964 680
WIRE 384 -320 384 -384
WIRE 384 -320 192 -320
WIRE 560 -320 384 -320
WIRE 192 -240 192 -320
WIRE 560 -224 560 -320
WIRE 384 -160 240 -160
WIRE 192 -80 192 -144
WIRE 560 -32 560 -144
WIRE 144 0 -16 0
WIRE 640 16 192 16
WIRE 192 64 192 16
WIRE 192 64 80 64
WIRE 288 64 192 64
WIRE 80 96 80 64
WIRE 288 96 288 64
WIRE -64 176 -64 144
WIRE -16 176 -16 0
WIRE -16 176 -64 176
WIRE 32 176 -16 176
WIRE 384 176 384 -160
WIRE 384 176 336 176
WIRE 560 176 560 144
WIRE 560 176 384 176
WIRE -64 208 -64 176
WIRE 560 208 560 176
WIRE -64 320 -64 288
WIRE 80 320 80 192
WIRE 80 320 -64 320
WIRE 192 320 80 320
WIRE 288 320 288 192
WIRE 288 320 192 320
WIRE 560 320 560 288
WIRE 560 320 288 320
WIRE 192 368 192 320
SYMBOL voltage 560 192 R0
WINDOW 3 73 -165 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(5 0 0 60ps 60ps 4ns 8ns)
SYMATTR InstName V3
SYMBOL voltage -64 192 R0
WINDOW 3 -55 -157 VRight 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(5 0 0 60ps 60ps 2ns 4ns)
SYMATTR InstName V2
SYMBOL pmos4 240 -240 M0
WINDOW 0 56 13 Left 2
WINDOW 3 56 83 Left 2
SYMATTR InstName M4
SYMATTR Value2 l=0.6u w=6u
SYMBOL voltage 560 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5v
SYMBOL nmos4 336 96 M0
WINDOW 0 55 6 Left 2
WINDOW 3 56 84 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=0.6u w=3u
SYMBOL pmos4 144 -80 R0
WINDOW 0 59 5 Left 2
WINDOW 3 56 82 Left 2
SYMATTR InstName M3
SYMATTR Value2 l=0.6u w=6u
SYMBOL nmos4 32 96 R0
WINDOW 0 56 6 Left 2
WINDOW 3 54 85 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=0.6u w=3u
FLAG 192 368 0
FLAG 560 -32 0
FLAG 384 -384 Vdd
FLAG 192 -192 Vdd
FLAG 192 -32 Vdd
FLAG 80 144 0
FLAG 288 144 0
FLAG 640 16 out
FLAG -64 144 A
FLAG 560 144 B
TEXT -96 392 Left 2 !.tran 0 20ns 0 0.001ns
* Z:\home\khalils\Downloads\files\data\raw_asc\a5ca29895578_Q42.asc
* Generated by LTspice 26.0.1 for Windows.
;.dc Vgs 0 1.8 1m
M1 0 N002 N001 N001 pch_tt l=180n w=270n
Vds N001 0 1.8
Vgs N002 0 {Vgs}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC180.lib
.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
.dc Vds 0 1.8 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 688 32 416 32
WIRE 416 112 416 32
WIRE 368 128 160 128
WIRE 688 128 688 32
WIRE 160 240 160 128
WIRE 160 448 160 320
WIRE 416 448 416 208
WIRE 416 448 160 448
WIRE 688 448 688 208
WIRE 688 448 416 448
WIRE 416 480 416 448
SYMBOL voltage 688 112 R0
SYMATTR InstName Vds
SYMATTR Value 1.8
SYMBOL pmos 368 208 M180
SYMATTR InstName M1
SYMATTR Value pch_tt
SYMATTR Value2 l=180n w=270n
SYMBOL voltage 160 224 R0
SYMATTR InstName Vgs
SYMATTR Value {Vgs}
FLAG 416 480 0
TEXT -136 176 Left 2 !.include TSMC180.lib
TEXT -352 224 Left 2 !.step param Vgs list 0.4 0.5 0.6 0.7 0.8 0.9
TEXT -120 264 Left 2 !.dc Vds 0 1.8 1m
TEXT -112 304 Left 2 !;.dc Vgs 0 1.8 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\1ddbf0d90720_Flight_Current_Source.asc
* Generated by LTspice 26.0.1 for Windows.
* 100 Ohm RTD
R7 N003 N002 2.49k
R3 N003 N004 249k
R8 N003 0 100
R2 N002 N001 249k
R1 N001 0 249k
V1 VCC 0 3.3
XU1 N004 N001 VCC 0 N002 LM6142A/NS ;pnba In+)In-)V+)V-)OUT
V2 N005 0 2.5
R4 N004 N005 249k
.inc LM6142A.mod
.tran 0 1 0 .01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1284 680
WIRE 640 48 512 48
WIRE 864 48 720 48
WIRE 576 208 576 176
WIRE 352 224 304 224
WIRE 512 224 512 48
WIRE 512 224 432 224
WIRE 544 224 512 224
WIRE 864 240 864 48
WIRE 864 240 608 240
WIRE 896 240 864 240
WIRE 1024 240 976 240
WIRE 1168 240 1024 240
WIRE 544 256 512 256
WIRE 304 272 304 224
WIRE 1168 272 1168 240
WIRE 576 304 576 272
WIRE 352 352 304 352
WIRE 512 352 512 256
WIRE 512 352 432 352
WIRE 640 352 512 352
WIRE 1024 352 1024 240
WIRE 1024 352 720 352
WIRE 1168 416 1168 352
WIRE 304 432 304 352
RECTANGLE Normal 1264 480 1072 144 2
SYMBOL res 448 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 249k
SYMBOL res 736 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 249k
SYMBOL res 736 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 249k
SYMBOL res 448 208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 249k
SYMBOL res 992 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R7
SYMATTR Value 2.49k
SYMBOL voltage 304 416 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 2.5
SYMBOL voltage 16 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL Opamps\\opamp2 576 176 R0
SYMATTR InstName U1
SYMATTR Value LM6142A/NS
SYMBOL res 1152 256 R0
SYMATTR InstName R8
SYMATTR Value 100
FLAG 16 256 0
FLAG 304 512 0
FLAG 304 272 0
FLAG 576 304 0
FLAG 16 176 VCC
FLAG 576 176 VCC
FLAG 1168 416 0
TEXT -120 408 Left 2 !.inc LM6142A.mod
TEXT -144 512 Left 2 !.tran 0 1 0 .01
TEXT 1104 128 Left 2 ;100 Ohm RTD
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3426.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3426.asy)
L1 IN N001 2.2
R1 OUT N002 95.3K
XU1 N001 0 N002 IN OUT IN LTC3426 ;pnba SW)GND)FB)_SHDN)Vout)Vin
Rload OUT 0 10
C1 OUT 0 22 Rser=100m
R2 N002 0 30.9K
D1 N001 OUT 1N5817
V1 IN 0 3.3
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran .5m startup
.lib LTC3426.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 96 160 0 160
WIRE 128 160 96 160
WIRE 240 160 208 160
WIRE 304 160 240 160
WIRE 400 160 368 160
WIRE 0 176 0 160
WIRE 240 224 240 160
WIRE 0 272 0 256
WIRE 96 272 96 160
WIRE 128 272 96 272
WIRE 400 272 400 160
WIRE 400 272 352 272
WIRE 512 272 400 272
WIRE 608 272 512 272
WIRE 400 288 400 272
WIRE 512 288 512 272
WIRE 608 288 608 272
WIRE 96 384 96 272
WIRE 128 384 96 384
WIRE 400 384 400 368
WIRE 400 384 352 384
WIRE 512 384 512 352
WIRE 608 384 608 368
WIRE 400 400 400 384
WIRE 240 448 240 432
WIRE 400 496 400 480
SYMBOL schottky 304 176 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5817
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage 0 160 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL res 384 272 R0
SYMATTR InstName R1
SYMATTR Value 95.3K
SYMBOL res 384 384 R0
SYMATTR InstName R2
SYMATTR Value 30.9K
SYMBOL cap 496 288 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMATTR SpiceLine Rser=100m
SYMBOL PowerProducts\\LTC3426 240 320 R0
SYMATTR InstName U1
SYMBOL ind 112 176 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMBOL res 592 272 R0
SYMATTR InstName Rload
SYMATTR Value 10
FLAG 0 272 0
FLAG 400 496 0
FLAG 240 448 0
FLAG 512 384 0
FLAG 608 384 0
FLAG 608 272 OUT
FLAG 0 160 IN
TEXT 544 456 Left 2 !.tran .5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC2935-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC2935-2.asy)
XU1 0 0 0 0 N003 N002 N004 N001 LTC2935-2 ;pnba S2)S1)S0)GND)_PFO)_RST)MR)VCC
V2 N005 0 PWL(0 0 9.599 0 9.6 3.6 9.999 3.6 10 0)
V1 N001 0 PWL(0 0 3.6 3.6 16 3.6 19.6 0 20.1 0 23.7 3.6)
MQ1 N004 N005 0 0 BSS123
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 21
.lib LTC2935-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1052 680
WIRE 192 -64 -256 -64
WIRE 192 -48 192 -64
WIRE 96 0 80 0
WIRE 336 0 288 0
WIRE 96 80 80 80
WIRE 336 80 288 80
WIRE 96 160 80 160
WIRE 400 160 288 160
WIRE 400 176 400 160
WIRE -256 192 -256 -64
WIRE 192 224 192 208
WIRE 544 256 448 256
WIRE 544 272 544 256
WIRE -256 304 -256 272
WIRE 400 304 400 272
WIRE 544 368 544 352
SYMBOL nmos 448 176 M0
WINDOW 0 39 -6 Right 2
WINDOW 3 32 97 Right 2
SYMATTR InstName Q1
SYMATTR Value BSS123
SYMBOL voltage -256 176 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 3.6 3.6 16 3.6 19.6 0 20.1 0 23.7 3.6)
SYMBOL voltage 544 256 R0
SYMATTR InstName V2
SYMATTR Value PWL(0 0 9.599 0 9.6 3.6 9.999 3.6 10 0)
SYMBOL LTC2935-2 192 80 R0
SYMATTR InstName U1
FLAG 192 224 0
FLAG 544 368 0
FLAG -256 304 0
FLAG 400 304 0
FLAG 80 160 0
FLAG 80 80 0
FLAG 80 0 0
TEXT 152 352 Left 2 !.tran 21