* Z:\tmp\asc_mix_bvbm4pog\mix_123.asc
* Generated by LTspice 26.0.1 for Windows.
V1 1 0 15
V2 0 -V 15
XU2 IN+ N004 1 -V N003 1 0 LT6018 ;pnba IN+)IN-)V+)V-)OUT)EN)DGND
XU3 N003 MP_01 NC_02 0 NC_03 0 1 OUT 1 NC_04 0 NC_05 MP_06 N002 -V LT6375 ;pnba +IN))+REFA)+REFB)+REFC)REF)_SHDN)OUT)V+)-REFC)-REFB)-REFA))-IN)V-
R1 N002 N001 49.9K
XU1 IN- N001 1 -V N002 1 0 LT6018 ;pnba IN+)IN-)V+)V-)OUT)EN)DGND
R2 N001 N004 49.9
R3 N004 N003 49.9K
V3 IN- IN+ SINE(0 1m 1K)
V4 IN+ 0 0
A1 0 0 0 0 0 0 0 0 BUF
A2 0 0 0 0 0 0 0 0 BUF
A3 0 0 0 0 0 0 0 0 BUF
A4 0 0 0 0 0 0 0 0 SCHMITT
A5 0 0 0 0 0 0 0 0 SCHMITT
A6 0 0 0 0 0 0 0 0 SCHMITT
A7 0 0 0 0 0 0 0 0 SCHMITT
A8 0 0 0 0 0 0 0 0 SCHMITT
A9 0 0 0 0 0 0 0 0 SCHMITT
A10 0 0 0 0 0 0 0 0 AND
A11 0 0 0 0 0 0 0 0 OR
A12 0 0 0 0 0 0 0 0 XOR
A13 0 0 0 0 0 0 0 0 SRFLOP
A14 0 0 0 0 0 0 0 0 DFLOP
A15 IN- IN- IN- IN- IN- IN- IN- IN- PHASEDET
A16 0 0 0 0 0 0 0 0 MODULATOR
A17 0 N001 0 0 0 0 1 0 VARISTOR
.tran 100m
* Low Noise Instrumentation Amplifier\nGain= 2000V/V
* BUF
* BUF
* BUF
* SCHMITT
* SCHMITT
* SCHMITT
* SCHMITT
* SCHMITT
* SCHMITT
* AND
* OR
* XOR
* SRFLOP
* DFLOP
* PHASEDET
* MODULATOR
* VARISTOR
* A-SOURCE NETLISTS:\nA1 1 8 8 8 8 8 7 8 BUF\nA2 1 8 8 8 8 6 8 8 BUF\nA3 1 8 8 8 8 6 7 8 BUF\nA4 1 8 8 8 8 8 7 8 SCHMITT\nA5 1 8 8 8 8 6 8 8 SCHMITT\nA6 1 8 8 8 8 6 7 8 SCHMITT\nA7 1 2 8 8 8 8 7 8 SCHMITT\nA8 1 2 8 8 8 6 8 8 SCHMITT\nA9 1 2 8 8 8 6 7 8 SCHMITT\nA10 1 2 3 4 5 6 7 8 AND\nA11 1 2 3 4 5 6 7 8 OR\nA12 1 2 3 4 5 6 7 8 XOR\nA13 1 2 8 8 8 6 7 8 SRFLOP\nA14 1 8 3 4 5 6 7 8 DFLOP\nA15 1 2 8 8 8 8 7 8 PHASEDET\nA16 1 2 8 8 8 8 7 8 MODULATOR\nA17 1 2 8 8 8 8 7 8 VARISTOR
* LTspice Standard A-Sources (Special Functions)
* NODE ASSIGNMENTS:\nThe first node up through to the fifth are reserved for inputs. For differential inputs the first node is used \nas the noninverting one and the second as the inverting half of the pair. The seventh node is the main \noutput with the sixth node serving as a complementary inverting output if needed. Node 8 serves as the \ngate's common. Unconnected nodes are connected by the netlister to the gate's common (that unlabeled \npin in the corner). This is a flag to the compiler to remove them and is different than tying the node to \ncommon with a wire.
* GENERAL GATE PARAMETERS (defaults shown):\nVhigh=1 Vlow=0 (logic levels); Ref=50% (logic threshold - if set becomes an absolute voltage); \nTd=0 (delay time: should be set to 10ns for shift registers and counters and the like);\nTrise=0 Tfall=Trise OR Tau=0 (transistion time constant) OR Rout=0 and Cout=0;\ntripdt=not specified (sets the maximum step size during logic transistions while between 10% and 90%)
* SCHMITT PARAMETERS:\nVt (threshold) Vh (hysteresis: band = 2*Vh) Note: if not specified Vt defaults to 50% and Vh to 5%
* VARISTOR PARAMETERS:\nRclamp=0 (clamping impedance)
* MODULATOR PARAMETERS:\nmark=? space=? (either specify mark and space frequencies or use a look-up table, not both)
* Library below included based on ModelFile attribute of instance XU2, XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6018.asy)
.lib LT6018.lib
* Library below included based on ModelFile attribute of instance XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6375.asy)
.lib LT6375.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2544 976
WIRE 816 32 816 16
WIRE 944 32 944 16
WIRE 816 128 816 112
WIRE 944 128 944 112
WIRE 1152 128 1136 128
WIRE 1168 128 1152 128
WIRE 1168 144 1168 128
WIRE 1120 176 1072 176
WIRE 1344 192 1232 192
WIRE 1456 192 1344 192
WIRE 944 208 784 208
WIRE 1120 208 944 208
WIRE 1344 208 1344 192
WIRE 1600 240 1600 208
WIRE 1872 240 1872 208
WIRE 1136 272 1136 256
WIRE 1168 272 1168 240
WIRE 784 320 784 208
WIRE 1072 320 1072 176
WIRE 1344 320 1344 288
WIRE 1344 320 1072 320
WIRE 1344 336 1344 320
WIRE 1456 352 1456 192
WIRE 1488 352 1456 352
WIRE 2000 368 1968 368
WIRE 1488 384 1456 384
WIRE 1344 432 1344 416
WIRE 1344 432 1072 432
WIRE 2000 432 1968 432
WIRE 1344 464 1344 432
WIRE 1152 496 1136 496
WIRE 1168 496 1152 496
WIRE 1168 512 1168 496
WIRE 1600 528 1600 496
WIRE 1824 528 1824 496
WIRE 1872 528 1872 496
WIRE 1072 544 1072 432
WIRE 1120 544 1072 544
WIRE 1344 560 1344 544
WIRE 1344 560 1232 560
WIRE 1456 560 1456 384
WIRE 1456 560 1344 560
WIRE 784 576 784 400
WIRE 944 576 784 576
WIRE 1120 576 944 576
WIRE 784 592 784 576
WIRE 1136 640 1136 624
WIRE 1168 640 1168 608
WIRE 784 688 784 672
WIRE 1824 144 1808 144
WIRE 1824 160 1824 176
WIRE 1888 144 1904 144
WIRE 1824 352 1824 368
WIRE 1888 336 1904 336
WIRE 1824 336 1808 336
WIRE 1824 560 1824 576
WIRE 1824 528 1808 528
WIRE 1888 512 1904 512
WIRE 1888 544 1904 544
WIRE 2096 144 2112 144
WIRE 2032 160 2032 176
WIRE 2032 144 2016 144
WIRE 2032 352 2032 368
WIRE 2096 336 2112 336
WIRE 2032 336 2016 336
WIRE 2032 560 2032 576
WIRE 2096 512 2112 512
WIRE 2096 544 2112 544
WIRE 2032 528 2016 528
WIRE 2240 176 2240 192
WIRE 2304 144 2320 144
WIRE 2240 128 2224 128
WIRE 2240 160 2224 160
WIRE 2304 336 2320 336
WIRE 2240 320 2224 320
WIRE 2240 352 2224 352
WIRE 2240 368 2240 384
WIRE 2240 560 2240 576
WIRE 2240 512 2224 512
WIRE 2240 544 2224 544
WIRE 2304 512 2320 512
WIRE 2304 544 2320 544
WIRE 2480 112 2432 112
WIRE 2480 128 2464 128
WIRE 2480 144 2432 144
WIRE 2480 160 2464 160
WIRE 2480 176 2432 176
WIRE 2544 128 2560 128
WIRE 2544 160 2560 160
WIRE 2496 176 2496 192
WIRE 2480 304 2432 304
WIRE 2480 320 2464 320
WIRE 2480 336 2432 336
WIRE 2480 352 2464 352
WIRE 2480 368 2432 368
WIRE 2496 368 2496 384
WIRE 2544 320 2560 320
WIRE 2544 352 2560 352
WIRE 2480 512 2432 512
WIRE 2480 528 2464 528
WIRE 2480 544 2432 544
WIRE 2480 560 2464 560
WIRE 2480 576 2432 576
WIRE 2544 528 2576 528
WIRE 2560 560 2576 560
WIRE 2512 576 2512 592
WIRE 2688 144 2672 144
WIRE 2688 192 2672 192
WIRE 2784 144 2816 144
WIRE 2800 192 2816 192
WIRE 2688 224 2688 240
WIRE 2848 416 2880 416
WIRE 2864 464 2880 464
WIRE 2688 416 2672 416
WIRE 2688 464 2672 464
WIRE 2768 512 2768 544
WIRE 2768 368 2768 336
WIRE 2768 544 2752 544
WIRE 2768 336 2752 336
WIRE 2688 512 2688 528
WIRE 3120 160 3136 160
WIRE 2992 144 2976 144
WIRE 2992 176 2976 176
WIRE 2992 208 2992 224
WIRE 2992 384 2976 384
WIRE 2992 448 2976 448
WIRE 3136 416 3152 416
WIRE 2992 480 2992 496
WIRE 3264 144 3248 144
WIRE 3264 176 3248 176
WIRE 3280 128 3280 112
WIRE 3280 192 3280 208
SYMBOL voltage 816 16 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage 944 128 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL LT6018 1168 560 R0
SYMATTR InstName U2
SYMBOL Opamps\\LT6375 1744 368 R0
SYMATTR InstName U3
SYMBOL res 1328 192 R0
SYMATTR InstName R1
SYMATTR Value 49.9K
SYMBOL LT6018 1168 192 R0
SYMATTR InstName U1
SYMBOL res 1328 320 R0
SYMATTR InstName R2
SYMATTR Value 49.9
SYMBOL res 1328 448 R0
SYMATTR InstName R3
SYMATTR Value 49.9K
SYMBOL voltage 784 304 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 1m 1K)
SYMBOL voltage 784 576 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\buf1 -320 80 R0
SYMATTR InstName A1
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\inv -320 272 R0
SYMATTR InstName A2
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\buf -320 464 R0
SYMATTR InstName A3
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\schmtbuf -112 80 R0
SYMATTR InstName A4
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\schmtinv -112 272 R0
SYMATTR InstName A5
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\schmitt -112 464 R0
SYMATTR InstName A6
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\diffschmtbuf 96 80 R0
SYMATTR InstName A7
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\diffschmtinv 96 272 R0
SYMATTR InstName A8
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\diffschmitt 96 464 R0
SYMATTR InstName A9
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\and 368 80 R0
SYMATTR InstName A10
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\or 368 272 R0
SYMATTR InstName A11
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\xor 384 480 R0
SYMATTR InstName A12
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\srflop 592 96 R0
SYMATTR InstName A13
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\dflop 624 368 R0
SYMATTR InstName A14
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\Digital\phidet 880 160 R0
SYMATTR InstName A15
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\SpecialFunctions\modulate 848 384 R0
SYMATTR InstName A16
SYMBOL C:\PROGRAM\ FILES\LTC\SWCADIII\lib\sym\SpecialFunctions\varistor 1152 96 R0
SYMATTR InstName A17
FLAG 816 128 0
FLAG 816 16 +V
FLAG 944 128 0
FLAG 944 16 -V
FLAG 1168 640 0
FLAG 1152 496 +V
FLAG 1136 640 -V
FLAG 1168 272 0
FLAG 1136 272 -V
FLAG 1872 208 +V
FLAG 1872 528 -V
FLAG 1600 208 0
FLAG 1600 528 0
FLAG 2000 432 0
FLAG 2000 368 OUT
FLAG 784 688 0
FLAG 944 208 IN-
FLAG 944 576 IN+
FLAG 1824 528 +V
FLAG 1152 128 +V
FLAG 1808 144 1
FLAG 1904 144 7
FLAG 1824 176 8
FLAG 1824 368 8
FLAG 1904 336 6
FLAG 1808 336 1
FLAG 1824 576 8
FLAG 1808 528 1
FLAG 1904 512 7
FLAG 1904 544 6
FLAG 2112 144 7
FLAG 2032 176 8
FLAG 2016 144 1
FLAG 2032 368 8
FLAG 2112 336 6
FLAG 2016 336 1
FLAG 2032 576 8
FLAG 2016 528 1
FLAG 2112 512 7
FLAG 2112 544 6
FLAG 2240 192 8
FLAG 2320 144 7
FLAG 2224 128 1
FLAG 2224 160 2
FLAG 2320 336 6
FLAG 2224 320 1
FLAG 2224 352 2
FLAG 2240 384 8
FLAG 2240 576 8
FLAG 2224 512 1
FLAG 2224 544 2
FLAG 2320 512 7
FLAG 2320 544 6
FLAG 2432 112 1
FLAG 2464 128 2
FLAG 2432 144 3
FLAG 2464 160 4
FLAG 2432 176 5
FLAG 2560 128 7
FLAG 2560 160 6
FLAG 2496 192 8
FLAG 2432 304 1
FLAG 2464 320 2
FLAG 2432 336 3
FLAG 2464 352 4
FLAG 2432 368 5
FLAG 2496 384 8
FLAG 2560 320 7
FLAG 2560 352 6
FLAG 2432 512 1
FLAG 2464 528 2
FLAG 2432 544 3
FLAG 2464 560 4
FLAG 2432 576 5
FLAG 2576 528 7
FLAG 2576 560 6
FLAG 2512 592 8
FLAG 2672 144 1
FLAG 2672 192 2
FLAG 2816 144 7
FLAG 2816 192 6
FLAG 2688 240 8
FLAG 2880 416 7
FLAG 2880 464 6
FLAG 2672 416 1
FLAG 2672 464 3
FLAG 2752 336 4
FLAG 2752 544 5
FLAG 2688 528 8
FLAG 3136 160 7
FLAG 2976 144 1
FLAG 2976 176 2
FLAG 2992 224 8
FLAG 2976 384 1
FLAG 2976 448 2
FLAG 3152 416 7
FLAG 2992 496 8
FLAG 3248 144 1
FLAG 3248 176 2
FLAG 3280 112 7
FLAG 3280 208 8
TEXT 1864 728 Left 2 !.tran 100m
TEXT 1528 72 Bottom 2 ;Low Noise Instrumentation Amplifier\nGain= 2000V/V
TEXT -320 56 Left 0 ;BUF
TEXT -320 240 Left 0 ;BUF
TEXT -320 440 Left 0 ;BUF
TEXT -112 56 Left 0 ;SCHMITT
TEXT -112 248 Left 0 ;SCHMITT
TEXT -112 440 Left 0 ;SCHMITT
TEXT 96 56 Left 0 ;SCHMITT
TEXT 96 248 Left 0 ;SCHMITT
TEXT 96 440 Left 0 ;SCHMITT
TEXT 336 56 Left 0 ;AND
TEXT 336 248 Left 0 ;OR
TEXT 336 440 Left 0 ;XOR
TEXT 544 56 Left 0 ;SRFLOP
TEXT 544 296 Left 0 ;DFLOP
TEXT 848 56 Left 0 ;PHASEDET
TEXT 848 296 Left 0 ;MODULATOR
TEXT 1064 56 Left 0 ;VARISTOR
TEXT -368 656 Left 0 ;A-SOURCE NETLISTS:\nA1   1 8 8 8 8 8 7 8 BUF\nA2   1 8 8 8 8 6 8 8 BUF\nA3   1 8 8 8 8 6 7 8 BUF\nA4   1 8 8 8 8 8 7 8 SCHMITT\nA5   1 8 8 8 8 6 8 8 SCHMITT\nA6   1 8 8 8 8 6 7 8 SCHMITT\nA7   1 2 8 8 8 8 7 8 SCHMITT\nA8   1 2 8 8 8 6 8 8 SCHMITT\nA9   1 2 8 8 8 6 7 8 SCHMITT\nA10 1 2 3 4 5 6 7 8 AND\nA11 1 2 3 4 5 6 7 8 OR\nA12 1 2 3 4 5 6 7 8 XOR\nA13 1 2 8 8 8 6 7 8 SRFLOP\nA14 1 8 3 4 5 6 7 8 DFLOP\nA15 1 2 8 8 8 8 7 8 PHASEDET\nA16 1 2 8 8 8 8 7 8 MODULATOR\nA17 1 2 8 8 8 8 7 8 VARISTOR
TEXT 408 -16 Center 0 ;LTspice Standard A-Sources (Special Functions)
TEXT 48 648 Left 0 ;NODE ASSIGNMENTS:\nThe first node up through to the fifth are reserved for inputs.  For differential inputs the first node is used \nas the noninverting one and the second as the inverting half of the pair.  The seventh node is the main \noutput with the sixth node serving as a complementary inverting output if needed.  Node 8 serves as the \ngate's common.  Unconnected nodes are connected by the netlister to the gate's common (that unlabeled \npin in the corner).  This is a flag to the compiler to remove them and is different than tying the node to \ncommon with a wire.
TEXT 48 848 Left 0 ;GENERAL GATE PARAMETERS (defaults shown):\nVhigh=1 Vlow=0 (logic levels); Ref=50% (logic threshold - if set becomes an absolute voltage); \nTd=0 (delay time: should be set to 10ns for shift registers and counters and the like);\nTrise=0 Tfall=Trise OR Tau=0 (transistion time constant) OR Rout=0 and Cout=0;\ntripdt=not specified (sets the maximum step size during logic transistions while between 10% and 90%)
TEXT 48 992 Left 0 ;SCHMITT PARAMETERS:\nVt (threshold) Vh (hysteresis: band = 2*Vh)  Note: if not specified Vt defaults to 50% and Vh to 5%
TEXT 48 1120 Left 0 ;VARISTOR PARAMETERS:\nRclamp=0 (clamping impedance)
TEXT 48 1056 Left 0 ;MODULATOR PARAMETERS:\nmark=? space=? (either specify mark and space frequencies or use a look-up table, not both)