Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1121-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Note Abs. Max SHDN pin voltage 6.5
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1121-3.3.asy)
C1 OUT 0 1
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 100
XU1 OUT MP_01 0 MP_02 NC_03 MP_04 MP_05 IN LT1121-3.3 ;pnba OUT))GND))_SHDN)))IN
.tran 1
.lib LT1121.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 192 -176 192
WIRE 368 192 320 192
WIRE 464 192 368 192
WIRE 368 208 368 192
WIRE 464 208 464 192
WIRE -176 224 -176 192
WIRE 368 304 368 272
WIRE 464 304 464 288
WIRE -176 352 -176 304
WIRE 176 384 176 352
SYMBOL res 448 192 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL PowerProducts\\LT1121-3.3 176 240 R0
SYMATTR InstName U1
SYMBOL voltage -176 208 R0
WINDOW 3 11 117 Left 2
SYMATTR Value PWL(0 0 1 10)
SYMATTR InstName V1
SYMBOL cap 352 208 R0
SYMATTR InstName C1
SYMATTR Value 1u
FLAG -176 352 0
FLAG 176 384 0
FLAG 368 304 0
FLAG 464 304 0
FLAG 464 192 OUT
FLAG -176 192 IN
TEXT 392 408 Left 2 !.tran 1
TEXT -392 400 Left 2 ;Note Abs. Max SHDN pin voltage 6.5
* Z:\home\khalils\Downloads\files\data\raw_asc\17e9c4595543_Draft14.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 48
V1 N003 0 PULSE(0 60 0 0 0 0.01 0.02)
R2 N004 N003 22
R1 N001 N002 0.5
M1 N002 N004 0 0 IRF1310
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 -96 -64 -96
WIRE 320 -80 320 -96
WIRE 320 16 320 0
WIRE 144 96 32 96
WIRE 272 96 224 96
WIRE -64 144 -64 -96
WIRE 32 144 32 96
SYMBOL nmos 272 16 R0
SYMATTR InstName M1
SYMATTR Value IRF1310
SYMBOL voltage -64 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 48
SYMBOL voltage 32 128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 60 0 0 0 0.01 0.02)
SYMBOL res 304 -96 R0
SYMATTR InstName R1
SYMATTR Value 0.5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 22
FLAG 32 224 0
FLAG -64 224 0
FLAG 320 112 0
TEXT -98 248 Left 2 !.tran 1
* Z:\tmp\asc_dec_bjh7r6w2\18c5e05c0d5a_1007A_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V3 IN 0 SINE(0 1m .01)
R1 OUT N001 355K
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 160 96 128 96
WIRE 272 96 240 96
WIRE -144 176 -144 160
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 272 240 272 96
WIRE 272 240 224 240
WIRE 304 240 272 240
WIRE 160 256 0 256
WIRE -144 272 -144 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1m .01)
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 355K
FLAG -144 272 0
FLAG 192 192 +V
FLAG -144 160 +V
FLAG 192 288 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 304 240 OUT
FLAG 0 256 IN
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2504-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2504-3.3.asy)
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2504-3.3 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
C1 OUT 0 10
L1 N001 N002 1.5 Rser=80m
V1 IN 0 3.3
Rload OUT 0 50
.tran 400u startup
.lib ADP2504-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ADP2504-3.3 176 176 R0
SYMATTR InstName U1
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 336 400 Left 2 !.tran 400u startup
TEXT 176 -8 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\tmp\asc_dec_bjh7r6w2\0b4bb343f8e3_LoopGain_Probe_LT1078_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
R2 N001 0 1K
R1 N003 0 10k
V3 Z N002 0
R6 Y N004 1k
R4 Y 0 10k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2412 1728
WIRE 384 80 384 64
WIRE 96 160 96 144
WIRE -80 176 -128 176
WIRE 64 176 -80 176
WIRE 288 192 128 192
WIRE 384 192 384 160
WIRE 384 192 368 192
WIRE 400 192 384 192
WIRE 432 192 400 192
WIRE 624 192 512 192
WIRE -80 208 -80 176
WIRE 64 208 32 208
WIRE 96 240 96 224
WIRE 624 240 624 192
WIRE 688 240 624 240
WIRE 688 256 688 240
WIRE 144 304 48 304
WIRE 240 304 208 304
WIRE -80 320 -80 288
WIRE 688 352 688 336
WIRE -128 384 -128 176
WIRE 48 384 48 304
WIRE 48 384 -128 384
WIRE 80 384 48 384
WIRE 240 384 240 304
WIRE 240 384 160 384
WIRE 624 384 624 240
WIRE 624 384 240 384
WIRE 480 560 448 560
WIRE 608 560 480 560
WIRE 64 576 32 576
WIRE 96 608 96 592
WIRE 608 608 608 560
WIRE 672 608 608 608
WIRE 672 624 672 608
WIRE 144 672 48 672
WIRE 240 672 208 672
WIRE 672 720 672 704
WIRE 48 752 48 672
WIRE 48 752 -128 752
WIRE 80 752 48 752
WIRE 240 752 240 672
WIRE 240 752 160 752
WIRE 608 752 608 608
WIRE 608 752 240 752
SYMBOL res -96 192 R0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 672 240 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL voltage 384 192 R90
WINDOW 0 -32 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName V3
SYMATTR Value 0
SYMBOL res 176 768 M270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res 656 608 R0
SYMATTR InstName R4
SYMATTR Value 10k
FLAG 384 64 0
FLAG -80 320 0
FLAG 688 352 0
FLAG 480 560 Y
FLAG 96 144 +V
FLAG 96 240 -V
FLAG 96 608 -V
FLAG 672 720 0
FLAG 400 192 Z
FLAG 32 208 offs
FLAG 32 576 offs
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1676.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1676.asy)
D1 0 N001 MBRS1100
C3 OUT 0 100
L1 N001 OUT 220
C1 N005 N004 2200p
V1 IN 0 30
R1 N005 0 22K
R2 OUT N003 36.5K
R3 N003 0 12.1K
C2 N004 0 100p
Rload OUT 0 10
XU1 N002 OUT N001 0 IN MP_01 N003 N004 LT1676 ;pnba _SHDN)Vcc)SW)GND)Vin))FB)Vc
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT1676.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2716 2040
WIRE 1792 1024 1552 1024
WIRE 1552 1040 1552 1024
WIRE 1792 1072 1792 1024
WIRE 2224 1104 1936 1104
WIRE 1552 1136 1552 1120
WIRE 2048 1152 1984 1152
WIRE 2096 1152 2048 1152
WIRE 2224 1152 2224 1104
WIRE 2224 1152 2176 1152
WIRE 2352 1152 2224 1152
WIRE 2464 1152 2352 1152
WIRE 2352 1168 2352 1152
WIRE 2464 1168 2464 1152
WIRE 2048 1184 2048 1152
WIRE 2224 1184 2224 1152
WIRE 1648 1200 1616 1200
WIRE 1984 1200 1984 1152
WIRE 1984 1200 1936 1200
WIRE 2048 1264 2048 1248
WIRE 2352 1264 2352 1232
WIRE 2464 1264 2464 1248
WIRE 2224 1296 2224 1264
WIRE 2224 1296 1936 1296
WIRE 2224 1312 2224 1296
WIRE 1968 1392 1936 1392
WIRE 2032 1392 1968 1392
WIRE 2144 1392 2096 1392
WIRE 1968 1408 1968 1392
WIRE 2144 1408 2144 1392
WIRE 2224 1408 2224 1392
WIRE 1792 1456 1792 1424
WIRE 1968 1504 1968 1472
WIRE 2144 1504 2144 1488
SYMBOL res 2448 1152 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL cap 2096 1376 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 2200p
SYMBOL ind 2080 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 220
SYMBOL cap 1952 1408 R0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL VOLTAGE 1552 1024 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMBOL polcap 2336 1168 R0
SYMATTR InstName C3
SYMATTR Value 100
SYMBOL schottky 2032 1248 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS1100
SYMBOL RES 2128 1392 R0
SYMATTR InstName R1
SYMATTR Value 22K
SYMBOL res 2208 1296 R0
SYMATTR InstName R3
SYMATTR Value 12.1K
SYMBOL PowerProducts\\LT1676 1792 1248 R0
SYMATTR InstName U1
SYMBOL res 2208 1168 R0
SYMATTR InstName R2
SYMATTR Value 36.5K
FLAG 2144 1504 0
FLAG 1968 1504 0
FLAG 2352 1264 0
FLAG 2048 1264 0
FLAG 1552 1136 0
FLAG 1792 1456 0
FLAG 2224 1408 0
FLAG 2464 1264 0
FLAG 2464 1152 OUT
FLAG 1552 1024 IN
TEXT 2288 1472 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\08bb55b56f72_Kichroff_Current.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 0 1000
I1 0 N001 10m
R3 N001 0 680
R2 N001 0 470
.tran 0 20s 0 1s
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 -48 176 -48
WIRE 448 -48 320 -48
WIRE 560 -48 448 -48
WIRE 176 16 176 -48
WIRE 320 16 320 -48
WIRE 448 16 448 -48
WIRE 560 16 560 -48
WIRE 176 176 176 96
WIRE 320 176 320 96
WIRE 320 176 176 176
WIRE 384 176 320 176
WIRE 448 176 448 96
WIRE 448 176 384 176
WIRE 560 176 560 96
WIRE 560 176 448 176
WIRE 384 192 384 176
SYMBOL res 432 0 R0
SYMATTR InstName R2
SYMATTR Value 470
SYMBOL res 544 0 R0
SYMATTR InstName R3
SYMATTR Value 680
SYMBOL res 304 0 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL current 176 96 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName I1
SYMATTR Value 10m
FLAG 384 192 0
TEXT 136 184 Left 2 !.tran 0 20s 0 1s
* Z:\home\khalils\Downloads\files\data\raw_asc\ADGS1414D.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
V3 N001 0 10
V4 N003 0 pulse(0 5 0 20n 20n 10u 20u)
R1 N002 0 300
XU1 N003 N002 N001 -V 0 +V ADGS1414D ;pnba IN)D)S)Vss)GND)Vdd
C1 N002 0 35p
.tran 0.0001
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADGS1414D.asy)
.lib ADGS1414D.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -528 -32 -528 -48
WIRE -368 -16 -400 -16
WIRE -240 -16 -288 -16
WIRE 48 -16 -48 -16
WIRE 160 -16 48 -16
WIRE 48 16 48 -16
WIRE 160 32 160 -16
WIRE -240 48 -368 48
WIRE -528 64 -528 48
WIRE -368 112 -368 48
WIRE 48 112 48 96
WIRE 160 112 160 96
WIRE -528 160 -528 144
WIRE -192 176 -192 160
WIRE -96 176 -96 160
WIRE -528 256 -528 240
WIRE -368 256 -368 192
FLAG -528 256 0
FLAG -528 64 0
FLAG -528 -48 +V
FLAG -528 144 -V
FLAG -400 -16 0
FLAG -192 176 -V
FLAG -144 -112 +V
FLAG -96 176 0
FLAG -368 256 0
FLAG 48 112 0
FLAG 160 112 0
SYMBOL voltage -528 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -528 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 10
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
SYMATTR Value pulse(0 5 0 20n 20n 10u 20u)
SYMATTR InstName V4
SYMBOL res 32 0 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL ADGS1414D -144 32 R0
SYMATTR InstName U1
SYMBOL cap 144 32 R0
SYMATTR InstName C1
SYMATTR Value 35p
TEXT 48 184 Left 2 !.tran 0.0001
* Z:\tmp\asc_dec_bjh7r6w2\100b8c4a1db8_Level_shifter_simulation_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V3 In1 0 PULSE(0 3.3 1u 1u 1u 1m 2m)
R1 3V3 In1 1k
M2 Sig2 N001 N002 N002 Si7336ADP
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1400 680
WIRE 816 32 752 32
WIRE 928 32 816 32
WIRE 1184 32 1104 32
WIRE 0 48 -64 48
WIRE 112 48 0 48
WIRE 816 48 816 32
WIRE 1104 48 1104 32
WIRE 0 64 0 48
WIRE 928 144 928 32
WIRE 112 160 112 48
WIRE 816 192 816 128
WIRE 816 192 752 192
WIRE 912 192 816 192
WIRE 1104 192 1104 128
WIRE 1104 192 1008 192
WIRE 1184 192 1104 192
WIRE 0 208 0 144
WIRE 0 208 -64 208
WIRE 96 208 0 208
WIRE 288 208 288 144
WIRE 288 208 192 208
WIRE 368 208 288 208
WIRE 1024 336 1024 304
WIRE 64 352 64 320
WIRE 208 352 208 320
WIRE 64 464 64 432
WIRE 208 464 208 432
SYMBOL voltage 208 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 3.3 1u 1u 1u 1m 2m)
SYMBOL res -16 48 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL nmos 1008 144 R90
WINDOW 0 -41 29 VRight 2
WINDOW 3 -17 -65 VRight 2
SYMATTR InstName M2
SYMATTR Value Si7336ADP
FLAG -64 48 3V3
FLAG -64 208 In1
FLAG 368 208 In2
FLAG 64 464 0
FLAG 64 320 5V0
FLAG 208 464 0
FLAG 208 320 In1
FLAG 1184 192 Sig2
FLAG 1024 304 Sig2
FLAG 1184 32 3V3
* Z:\home\khalils\Downloads\files\data\raw_asc\199ed153eee7_LTC2050HV.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC2050HV.asy)
R1 N002 N001 10K
XU1 N003 N001 +V -V N002 NC_01 LTC2050 ;pnba In+)In-)V+)V-)OUT)SHDN
V2 -V 0 -2.5
V3 N003 0 SINE(0 1 1K)
R2 N001 0 10K
V1 +V 0 2.5
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -48 -64 -64 -64
WIRE 48 -64 32 -64
WIRE 112 -64 48 -64
WIRE 224 -64 192 -64
WIRE -288 16 -288 0
WIRE -160 16 -160 0
WIRE 48 64 48 -64
WIRE 64 64 48 64
WIRE 224 96 224 -64
WIRE 224 96 208 96
WIRE -288 112 -288 96
WIRE -160 112 -160 96
WIRE 64 128 -96 128
WIRE -96 160 -96 128
WIRE 96 192 96 176
WIRE -96 256 -96 240
SYMBOL opamps\\LTC2050HV 96 96 R0
SYMATTR InstName U1
SYMBOL voltage -96 144 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL res 208 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 48 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage -288 0 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL voltage -160 0 R0
SYMATTR InstName V1
SYMATTR Value 2.5
FLAG -160 112 0
FLAG 96 16 +V
FLAG -160 0 +V
FLAG 96 192 -V
FLAG -288 112 0
FLAG -288 0 -V
FLAG -96 256 0
FLAG -64 -64 0
TEXT 224 240 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\2fce557217ca_fig-01-03-12.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4077-2.asy)
XU1 NC_01 NC_02 NC_03 NC_04 NC_05 NC_06 NC_07 NC_08 ADA4077-2 ;pnba +INA)-INA)OUTA)V+)V-)+INB)-INB)OUTB
VS2 0 VEE 15
D1 VOP VOUT 1N4148
R1 VOUT 0 1k
VS1 VCC 0 15
V1 VIN 0 SINE(0 1 1k)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0 2m 0 1u
.lib ADA4077-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 400 80 144 80
WIRE 208 112 208 96
WIRE 208 144 208 112
WIRE 144 160 144 80
WIRE 176 160 144 160
WIRE 288 176 240 176
WIRE 304 176 288 176
WIRE 400 176 400 80
WIRE 400 176 368 176
WIRE 432 176 400 176
WIRE 96 192 48 192
WIRE 176 192 96 192
WIRE 48 208 48 192
WIRE 400 208 400 176
WIRE 208 240 208 208
WIRE 208 256 208 240
WIRE 256 288 256 272
WIRE 320 288 320 272
WIRE 400 320 400 288
WIRE 48 336 48 288
WIRE 256 336 256 288
WIRE 320 336 320 288
WIRE 256 432 256 416
WIRE 320 432 320 416
IOPIN 432 176 Out
SYMBOL Misc\\battery 256 432 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName VS2
SYMATTR Value 15
SYMBOL diode 304 192 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL Opamps\\ADA4077-2 208 112 R0
WINDOW 3 14 122 Left 2
SYMATTR InstName U1
SYMBOL Misc\\battery 320 320 R0
WINDOW 0 12 6 Left 2
WINDOW 3 15 95 Left 2
SYMATTR InstName VS1
SYMATTR Value 15
SYMBOL res 384 192 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 48 192 R0
WINDOW 0 10 99 Left 2
WINDOW 3 -60 179 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 1 1k)
FLAG 48 336 0
FLAG 432 176 VOUT
FLAG 96 192 VIN
FLAG 288 176 VOP
FLAG 256 432 0
FLAG 320 432 0
FLAG 256 288 VEE
FLAG 320 288 VCC
FLAG 208 112 VCC
FLAG 208 240 VEE
FLAG 400 320 0
TEXT -40 64 Left 2 !.tran 0 2m 0 1u
* Z:\home\khalils\Downloads\files\data\raw_asc\225e1c7dd192_circuit1.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N002 N001 22n
R1 N002 0 2k
V1 N001 0 AC 1.005
.ac dec 1000 1 10Meg
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 224 64 80 64
WIRE 400 64 288 64
WIRE 80 112 80 64
WIRE 400 112 400 64
WIRE 80 256 80 192
WIRE 144 256 80 256
WIRE 400 256 400 192
WIRE 400 256 144 256
WIRE 144 272 144 256
SYMBOL cap 288 48 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 22n
SYMBOL voltage 80 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1.005
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL res 384 96 R0
SYMATTR InstName R1
SYMATTR Value 2k
FLAG 144 272 0
TEXT -152 152 Left 2 !.ac dec 1000 1 10Meg
* Z:\tmp\asc_dec_bjh7r6w2\0528c3b2b7b2_TP1-Circ1_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Vcc Vcc 0 10
R3 N002 N001 {R}
V2 N003 0 SINE(0 2 1k)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 48 160 48
WIRE 352 48 272 48
WIRE 480 48 432 48
WIRE 112 144 96 144
WIRE 112 256 112 144
WIRE 112 256 32 256
WIRE 144 256 112 256
WIRE 272 256 272 48
WIRE 272 256 224 256
WIRE 288 256 272 256
WIRE 480 272 480 48
WIRE 480 272 352 272
WIRE 288 288 224 288
WIRE 112 320 112 256
WIRE 112 320 96 320
WIRE 224 320 224 288
WIRE 224 416 224 400
WIRE -48 496 -48 480
WIRE 144 496 144 480
WIRE -48 592 -48 576
WIRE 144 592 144 576
SYMBOL voltage 144 480 R0
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcc
SYMATTR Value 10
SYMBOL res 448 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {R}
SYMBOL voltage 224 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 2 1k)
FLAG 144 592 0
FLAG -48 592 0
FLAG 224 416 0
FLAG 96 320 Vo1
FLAG 144 480 Vcc
FLAG 320 240 Vcc
FLAG -48 480 Vss
FLAG 0 288 Vss
FLAG 320 304 Vss
* Z:\home\khalils\Downloads\files\data\raw_asc\MAXM17225.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 1.5
C1 OUT 0 10 Rser=5m
R1 OUT 0 100
XU1 0 N001 OUT IN NC_01 IN IN MAXM17225 ;pnba GND)RSEL)OUT)EN)LX)IN)INS
R2 N001 0 133K
.tran 4.5m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAXM17225.asy)
.lib MAXM17225.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 960 680
WIRE -80 -32 -112 -32
WIRE 16 -32 -80 -32
WIRE 64 -32 16 -32
WIRE 384 -32 320 -32
WIRE 464 -32 384 -32
WIRE 496 -32 464 -32
WIRE -112 0 -112 -32
WIRE 384 0 384 -32
WIRE 496 0 496 -32
WIRE 16 64 16 -32
WIRE 64 64 16 64
WIRE 384 96 384 64
WIRE 496 96 496 80
WIRE -112 112 -112 80
WIRE 16 160 16 64
WIRE 64 160 16 160
WIRE 384 160 320 160
WIRE 384 192 384 160
WIRE 208 256 208 224
WIRE 384 288 384 272
FLAG -112 112 0
FLAG 384 96 0
FLAG 496 96 0
FLAG -80 -32 IN
FLAG 464 -32 OUT
FLAG 384 288 0
FLAG 208 256 0
SYMBOL voltage -112 -16 R0
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL cap 368 0 R0
SYMATTR SpiceLine Rser=5m
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 480 -16 R0
WINDOW 123 36 60 Left 2
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL MAXM17225 192 64 R0
SYMATTR InstName U1
SYMBOL res 368 176 R0
SYMATTR InstName R2
SYMATTR Value 133K
TEXT 128 344 Left 2 !.tran 4.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2a8b6c5222b7_blinkers.asc
* Generated by LTspice 26.0.1 for Windows.
D1 N001 0 NSCW100
V1 N001 0 12 Rser=0.1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 112 64 112
WIRE 64 128 64 112
WIRE 224 208 64 208
WIRE 320 208 320 176
WIRE 320 208 224 208
WIRE 224 224 224 208
SYMBOL voltage 64 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMATTR SpiceLine Rser=0.1
SYMBOL LED 304 112 R0
SYMATTR InstName D1
SYMATTR Value NSCW100
FLAG 224 224 0
TEXT 30 264 Left 2 !.tran 2
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1004-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1004-1.2.asy)
V1 N001 0 PULSE(0 5 100u 10n 10n 500u 1)
R1 OUT N001 36K
XU1 OUT 0 LT1004-1.2 ;pnba VOUT)GND
.tran 700u
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 980 680
WIRE 96 112 -144 112
WIRE 368 112 176 112
WIRE -144 128 -144 112
WIRE 368 128 368 112
WIRE -144 224 -144 208
WIRE 368 224 368 192
SYMBOL res 192 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 36K
SYMBOL voltage -144 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 100u 10n 10n 500u 1)
SYMBOL LT1004-1.2 368 160 R0
SYMATTR InstName U1
FLAG 368 224 0
FLAG -144 224 0
FLAG 368 112 OUT
TEXT 392 288 Left 2 !.tran 700u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3060-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3060-1.8.asy)
C3 OUT 0 10
V1 IN 0 12
C2 OUT N001 10n
C1 N002 0 10n
Rload OUT 0 18
XU1 N002 N001 OUT MP_01 IN MP_02 IN 0 LT3060-1.8 ;pnba Ref/Byp)ADJ)OUT))IN))_SHDN)GND
.tran .1 startup
.lib LT3060-1.8.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 112 -16 112
WIRE 96 112 0 112
WIRE 112 112 96 112
WIRE 432 112 368 112
WIRE 544 112 432 112
WIRE 624 112 544 112
WIRE -16 128 -16 112
WIRE 544 128 544 112
WIRE 624 128 624 112
WIRE 432 144 432 112
WIRE -16 224 -16 208
WIRE 96 224 96 112
WIRE 112 224 96 224
WIRE 432 224 432 208
WIRE 432 224 368 224
WIRE 544 224 544 192
WIRE 624 224 624 208
WIRE 112 336 80 336
WIRE 400 336 368 336
WIRE 400 352 400 336
WIRE 400 432 400 416
SYMBOL cap 416 144 R0
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL voltage -16 112 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 528 128 R0
SYMATTR InstName C3
SYMATTR Value 10
SYMBOL cap 384 352 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL PowerProducts\\LT3060-1.8 240 224 R0
SYMATTR InstName U1
SYMBOL res 608 112 R0
SYMATTR InstName Rload
SYMATTR Value 18
FLAG 80 336 0
FLAG -16 224 0
FLAG 400 432 0
FLAG 544 224 0
FLAG 624 224 0
FLAG 624 112 OUT
FLAG 0 112 IN
TEXT 480 320 Left 2 !.tran .1 startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1015.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT1015.asy)
V1 N001 0 5
V3 N005 0 PULSE(0 5 0 5n 5n 5u 10u)
V2 N004 0 PULSE(2 3 0 .5u .5u 0 1u)
XU1 N004 N002 N001 0 N003 N005 LT1015 ;pnba In+)In-)VCC)VEE)OUT+)LATCH
R2 N002 0 10K
R1 N001 N002 10K
.tran 30u
.lib LT1015.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 692
WIRE -224 112 -336 112
WIRE -96 112 -224 112
WIRE -336 128 -336 112
WIRE -224 128 -224 112
WIRE -96 192 -96 112
WIRE -336 224 -336 208
WIRE -224 224 -224 208
WIRE -128 224 -224 224
WIRE 32 240 -48 240
WIRE -128 256 -576 256
WIRE -576 272 -576 256
WIRE -224 272 -224 224
WIRE -96 304 -96 288
WIRE -96 304 -128 304
WIRE -80 304 -80 288
WIRE -48 304 -80 304
WIRE -128 320 -128 304
WIRE -48 320 -48 304
WIRE -576 368 -576 352
WIRE -224 368 -224 352
WIRE -48 416 -48 400
SYMBOL res -240 256 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage -336 112 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL LT1015 -96 240 R0
SYMATTR InstName U1
SYMBOL voltage -576 256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value PULSE(2 3 0 .5u .5u 0 1u)
SYMBOL res -240 112 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -48 304 R0
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 5n 5n 5u 10u)
FLAG -336 224 0
FLAG -576 368 0
FLAG -128 320 0
FLAG -224 368 0
FLAG -48 416 0
TEXT 112 312 Left 2 !.tran 30u