Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4120A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4120A.asy)
V3 N003 0 PULSE(0 5 0 2n 2n 998n 2u)
C1 GATE 0 2n
XU1 N001 N003 0 0 N004 N002 ADuM4120xx Glitch=1 Vrun2=4.3 ;pnba Vdd1)Vin)GND1)GND2)Vout)Vdd2
V1 N001 0 5
V2 N002 0 15
R1 GATE N004 5
.tran 10u
.lib ADuM4120xx.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 16 48 16
WIRE 512 16 320 16
WIRE 48 32 48 16
WIRE 512 32 512 16
WIRE 160 48 160 16
WIRE 320 48 320 16
WIRE 48 128 48 112
WIRE 512 128 512 112
WIRE 112 160 -32 160
WIRE 400 160 368 160
WIRE 512 160 480 160
WIRE 544 160 512 160
WIRE 512 176 512 160
WIRE 160 288 160 272
WIRE 320 288 320 272
SYMBOL voltage -16 160 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 2n 2n 998n 2u)
SYMBOL res 496 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5
SYMBOL cap 496 176 R0
WINDOW 0 35 16 Left 2
WINDOW 3 36 51 Left 2
SYMATTR InstName C1
SYMATTR Value 2n
SYMBOL voltage 48 16 R0
WINDOW 0 25 25 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 512 16 R0
WINDOW 0 29 30 Left 2
WINDOW 3 31 84 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL ADuM4120A 240 160 R0
SYMATTR InstName U1
FLAG 160 288 0
FLAG 320 288 0
FLAG 512 240 0
FLAG 544 160 GATE
FLAG 512 128 0
FLAG 48 128 0
FLAG -112 160 0
TEXT 400 280 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\189063a42137_InaE.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX41400.asy)
V6 N004 0 1.65
V2 Vref 0 1.65
V5 N003 0 1.65
V3 N001 N003 PWL file=C:\users\andrei\Documents\Licenta\AchizitionareSemnal\ekg_signal.txt
V1 Vcc 0 3.3V
V4 N002 N004 PWL file=C:\users\andrei\Documents\Licenta\AchizitionareSemnal\ekg_signal2.txt
XU1 0 0 0 0 N002 N001 Out Vref Vcc Vcc MAX41400 ;pnba G0)G1)G2)GND)INM)INP)OUT)REFIN)SHDN_)VDD
.tran 5
.lib MAX41400.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1328 680
WIRE -112 -64 -112 -80
WIRE 16 -64 16 -80
WIRE -112 32 -112 16
WIRE 16 32 16 16
WIRE 416 224 416 192
WIRE 448 224 448 176
WIRE 480 224 480 176
WIRE 512 224 512 176
WIRE 384 288 80 288
WIRE 80 320 80 288
WIRE 592 320 544 320
WIRE 608 320 592 320
WIRE 384 352 304 352
WIRE 304 384 304 352
WIRE 80 416 80 400
WIRE 416 432 416 416
WIRE 512 432 512 416
WIRE 464 448 464 416
WIRE 304 480 304 464
SYMBOL voltage 304 368 R0
WINDOW 3 -431 237 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PWL file=C:\users\andrei\Documents\Licenta\AchizitionareSemnal\ekg_signal2.txt
SYMBOL voltage 304 464 R0
SYMATTR InstName V6
SYMATTR Value 1.65
SYMBOL OpAmps\\MAX41400 416 320 R0
WINDOW 3 141 -89 Left 2
SYMATTR InstName U1
SYMBOL voltage 80 400 R0
SYMATTR InstName V5
SYMATTR Value 1.65
SYMBOL voltage 80 304 R0
WINDOW 3 -777 -50 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PWL file=C:\users\andrei\Documents\Licenta\AchizitionareSemnal\ekg_signal.txt
SYMBOL voltage 16 -80 R0
SYMATTR InstName V2
SYMATTR Value 1.65
SYMBOL voltage -112 -80 R0
SYMATTR InstName V1
SYMATTR Value 3.3V
FLAG 416 432 0
FLAG 512 176 0
FLAG 480 176 0
FLAG 448 176 0
FLAG -112 32 0
FLAG -112 -80 Vcc
FLAG 416 192 Vcc
FLAG 464 448 Vcc
FLAG 16 32 0
FLAG 16 -80 Vref
FLAG 512 432 Vref
FLAG 592 320 Out
FLAG 80 496 0
FLAG 304 560 0
TEXT 424 120 Left 2 !.tran 5
* Z:\home\khalils\Downloads\files\data\raw_asc\1d5ea0425c4a_transistor.asc
* Generated by LTspice 26.0.1 for Windows.
* Example of DC sweep in LTSpice
R1 N002 N001 1k
V1 N001 0
D1 N002 0 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -10 10 3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 80 80 80
WIRE 272 80 240 80
WIRE 80 112 80 80
WIRE 272 128 272 80
WIRE 80 224 80 192
WIRE 272 224 272 192
SYMBOL diode 256 128 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 256 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage 80 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value ""
FLAG 80 224 0
FLAG 272 224 0
TEXT 344 72 Left 2 !.dc V1 -10 10 3
TEXT 128 -8 Left 2 ;Example of DC sweep in LTSpice
* Z:\home\khalils\Downloads\files\data\raw_asc\078b87f0be25_1457.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1457.asy)
V3 N003 0 SINE(0 1 1K)
V2 -V 0 -15
R2 N001 0 1K
V1 +V 0 15
XU2 N003 N001 N002 +V -V LT1457 ;pnba IN+)IN-)OUT)VCC)VEE
R1 N002 N001 1K
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -256 160 -256 144
WIRE -128 160 -128 144
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE -256 256 -256 240
WIRE -128 256 -128 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL voltage -256 144 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL opamps\\LT1457 192 240 R0
SYMATTR InstName U2
SYMBOL voltage -128 144 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1K
FLAG -128 256 0
FLAG 192 192 +V
FLAG -128 144 +V
FLAG 192 288 -V
FLAG -256 256 0
FLAG -256 144 -V
FLAG 16 96 0
FLAG 0 368 0
TEXT -264 344 Left 0 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\f0bda7996e02_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
T1 N001 0 0 N002 Td=50n Z0=50
T2 0 0 N002 0 Td=50n Z0=150
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=50n Z0=150
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\c6b1ca35c5d5_osc_impedance.asc
* Generated by LTspice 26.0.1 for Windows.
* Run ".ac analysis" and plot "Z", (Vgate/I(I1)), in "cartesion coordinate" mode.\nNote that as {R} is decreased, the real part of Z becomes more and more negative.\nAs {R} is further decreased, the real part of Z becomes more positive. A this point,\nthe oscillator fails to start.\nRun ".transient analysis" to see what effect decreasing {R} has on oscillator startup.
;tran 0 50uS 0S 200pS
L2 Vgate 0 159nH Rser=0
J1 N001 Vgate N002 MPF102
C1 Vgate N002 31.8pF
I1 0 Vgate AC 1uA
R2 Vgate 0 {R}
I2 N002 0 1mA
V1 N001 0 9V
C2 N002 0 31.8pF
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.ac oct 10k 98e6 102e6
.step param R 3k 1.5k 500
.meas ac Re find re(V(vgate)/I(I1)) at 100e6
.meas ac Im find im(V(vgate)/I(I1)) at 100e6
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 884
WIRE -736 416 -736 272
WIRE -736 624 -736 496
WIRE -656 272 -736 272
WIRE -656 272 -656 208
WIRE -576 272 -656 272
WIRE -576 416 -576 272
WIRE -576 624 -736 624
WIRE -576 624 -576 496
WIRE -432 272 -576 272
WIRE -432 416 -432 272
WIRE -432 624 -576 624
WIRE -432 624 -432 496
WIRE -304 272 -432 272
WIRE -304 304 -304 272
WIRE -304 416 -304 368
WIRE -304 480 -304 416
WIRE -304 624 -432 624
WIRE -304 624 -304 544
WIRE -224 272 -304 272
WIRE -176 208 -176 176
WIRE -176 416 -304 416
WIRE -176 416 -176 304
WIRE -176 480 -176 416
WIRE -176 624 -304 624
WIRE -176 624 -176 560
WIRE 0 176 -176 176
WIRE 0 288 0 176
WIRE 0 624 -176 624
WIRE 0 624 0 368
WIRE 0 656 0 624
SYMBOL voltage 0 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9V
SYMBOL current -736 496 R180
WINDOW 123 -101 105 Left 0
WINDOW 3 24 88 Invisible 0
SYMATTR Value2 AC 1uA
SYMATTR Value ""
SYMATTR InstName I1
SYMBOL njf -224 208 R0
SYMATTR InstName J1
SYMATTR Value MPF102
SYMBOL ind -448 400 R0
SYMATTR InstName L2
SYMATTR Value 159nH
SYMATTR SpiceLine Rser=0
SYMBOL current -176 480 R0
WINDOW 123 24 116 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 43 47 Left 0
SYMATTR Value 1mA
SYMATTR InstName I2
SYMBOL cap -320 304 R0
SYMATTR InstName C1
SYMATTR Value 31.8pF
SYMBOL cap -320 480 R0
SYMATTR InstName C2
SYMATTR Value 31.8pF
SYMBOL res -592 400 R0
SYMATTR InstName R2
SYMATTR Value {R}
FLAG 0 656 0
FLAG -656 208 Vgate
TEXT -1000 224 Left 0 !;tran 0 50uS 0S 200pS
TEXT -1000 272 Left 0 !.ac oct 10k 98e6 102e6
TEXT -1024 320 Left 0 !.step param R 3k 1.5k 500
TEXT -816 -80 Left 0 ;Run ".ac analysis" and plot "Z", (Vgate/I(I1)), in "cartesion coordinate" mode.\nNote that as {R} is decreased, the real part of Z becomes more and more negative.\nAs {R} is further decreased, the real part of Z becomes more positive. A this point,\nthe oscillator fails to start.\nRun ".transient analysis" to see what effect decreasing {R} has on oscillator startup.
TEXT -1336 392 Left 0 !.meas ac Re find re(V(vgate)/I(I1)) at 100e6\n.meas ac Im find im(V(vgate)/I(I1)) at 100e6
* Z:\home\khalils\Downloads\files\data\raw_asc\1324a7b6fcb0_6230-10.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6230-10.asy)
V3 N003 0 SINE(0 .1 1K)
R1 N002 N001 10K
XU1 N003 N001 N002 +V -V 0 LT6230-10 ;pnba IN+)IN-)OUT)VCC)VEE)EN_L
R2 N001 0 1K
V2 -V 0 -5
V1 +V 0 5
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -112 48 -128 48
WIRE 0 48 -32 48
WIRE 96 48 0 48
WIRE 208 48 176 48
WIRE 64 112 64 96
WIRE -416 160 -416 144
WIRE -288 160 -288 144
WIRE 0 160 0 48
WIRE 32 160 0 160
WIRE 208 192 208 48
WIRE 208 192 176 192
WIRE 32 224 -144 224
WIRE -144 240 -144 224
WIRE -416 256 -416 240
WIRE -288 256 -288 240
WIRE 64 288 64 272
WIRE -144 336 -144 320
SYMBOL voltage -144 224 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 .1 1K)
SYMBOL res -16 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL opamps\\LT6230-10 64 192 R0
SYMATTR InstName U1
SYMBOL res 192 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -416 144 R0
SYMATTR InstName V2
SYMATTR Value -5
FLAG -288 256 0
FLAG 64 96 +V
FLAG -288 144 +V
FLAG 64 288 -V
FLAG -416 256 0
FLAG -416 144 -V
FLAG -128 48 0
FLAG -144 336 0
FLAG 112 272 0
TEXT 176 344 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3645.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 7
L1 N002 OUT 15
R1 OUT N005 52.3K
R2 N005 0 10K
C1 OUT 0 22
D1 N003 N002 MBR0520L
C2 N001 N002 .1
XU1 IN OUT N005 IN 0 N003 N001 N002 N006 OUT OUT2 N004 LT3645 ;pnba Vin)Vcc2)FB)EN/UVLO)GND)DA)Boost)SW)FB2)EN2)OUT2)NPG
R3 OUT2 N006 31.6K
R4 N006 0 10K
C3 OUT2 0 2.2
Rload OUT 0 16.7
Rload1 OUT2 0 16.5
R5 N004 OUT2 100K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3645.asy)
.lib LT3645.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 928 804
WIRE 160 32 96 32
WIRE 288 32 224 32
WIRE 96 96 96 32
WIRE -96 144 -192 144
WIRE -64 144 -96 144
WIRE 288 144 288 32
WIRE 288 144 256 144
WIRE 336 144 288 144
WIRE 432 144 416 144
WIRE 544 144 432 144
WIRE 592 144 544 144
WIRE 688 144 592 144
WIRE -192 160 -192 144
WIRE 592 160 592 144
WIRE 688 160 688 144
WIRE 288 176 288 144
WIRE 432 240 432 144
WIRE -192 256 -192 240
WIRE -96 256 -96 144
WIRE -64 256 -96 256
WIRE 288 256 288 240
WIRE 288 256 256 256
WIRE 592 256 592 224
WIRE 688 256 688 240
WIRE -64 368 -272 368
WIRE 432 368 432 320
WIRE 432 368 256 368
WIRE -272 384 -272 368
WIRE 432 384 432 368
WIRE -272 480 -272 464
WIRE -272 480 -416 480
WIRE -176 480 -272 480
WIRE -64 480 -176 480
WIRE 288 480 256 480
WIRE 432 480 432 464
WIRE -416 496 -416 480
WIRE -272 496 -272 480
WIRE -176 496 -176 480
WIRE -272 576 -272 560
WIRE -416 592 -416 576
WIRE -176 592 -176 576
WIRE -64 592 -176 592
WIRE 288 592 288 480
WIRE 288 592 256 592
WIRE 544 592 544 144
WIRE 544 592 288 592
WIRE -176 608 -176 592
WIRE 96 656 96 640
WIRE -176 704 -176 688
FLAG -192 256 0
FLAG 432 480 0
FLAG 688 256 0
FLAG 592 256 0
FLAG 688 144 OUT
FLAG -192 144 IN
FLAG -176 704 0
FLAG 96 656 0
FLAG -272 576 0
FLAG -416 592 0
FLAG -416 480 OUT2
SYMBOL voltage -192 144 R0
SYMATTR InstName V1
SYMATTR Value 7
SYMBOL ind 320 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 15
SYMBOL res 416 224 R0
SYMATTR InstName R1
SYMATTR Value 52.3K
SYMBOL res 416 368 R0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL cap 576 160 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL schottky 272 240 M180
WINDOW 0 22 62 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBR0520L
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 160 48 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value .1
SYMATTR InstName C2
SYMBOL PowerProducts\\LT3645 96 368 R0
SYMATTR InstName U1
SYMBOL res -192 480 R0
SYMATTR InstName R3
SYMATTR Value 31.6K
SYMBOL res -192 592 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL cap -288 496 R0
SYMATTR InstName C3
SYMATTR Value 2.2
SYMBOL res 672 144 R0
SYMATTR InstName Rload
SYMATTR Value 16.7
SYMBOL res -432 480 R0
SYMATTR InstName Rload1
SYMATTR Value 16.5
SYMBOL res -288 368 R0
SYMATTR InstName R5
SYMATTR Value 100K
TEXT 376 656 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX14575C.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 5
C1 OUT 0 150
S1 0 OUT N001 0 SHORT
V4 N001 0 PULSE(0 1 10m 1m 1m 30m)
R3 N004 N003 20K
R1 N005 N006 52.3K
V3 N004 0 5
V2 N002 0 2
R2 N006 0 348
XU1 IN N005 0 N003 N002 OUT MAX14575C ;pnba IN)SETI)GND)_FLAG)EN)OUT
.model SHORT SW(Ron=0.05 Roff=1K Vt=.5 Vh=-.4)
.tran 50m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX14575C.asy)
.lib MAX14575C.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1800 680
WIRE -16 -352 -224 -352
WIRE 400 -352 272 -352
WIRE 512 -352 400 -352
WIRE 672 -352 560 -352
WIRE -224 -336 -224 -352
WIRE 400 -336 400 -352
WIRE 512 -336 512 -352
WIRE 672 -336 672 -352
WIRE 560 -320 560 -352
WIRE -224 -240 -224 -256
WIRE 400 -240 400 -272
WIRE 512 -240 512 -256
WIRE 672 -240 672 -256
WIRE -16 -160 -224 -160
WIRE 384 -160 272 -160
WIRE 576 -160 464 -160
WIRE -224 -144 -224 -160
WIRE 576 -128 576 -160
WIRE -16 -64 -128 -64
WIRE 336 -64 272 -64
WIRE -224 -48 -224 -64
WIRE -128 -48 -128 -64
WIRE 336 -32 336 -64
WIRE 576 -32 576 -48
WIRE -128 48 -128 32
WIRE -128 144 -128 128
FLAG -224 -240 0
FLAG 400 -240 0
FLAG 512 -352 OUT
FLAG -224 -352 IN
FLAG 512 -240 0
FLAG 560 -272 0
FLAG 672 -240 0
FLAG -128 144 0
FLAG 576 -32 0
FLAG -224 -48 0
FLAG 336 -32 0
SYMBOL voltage -224 -352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 384 -336 R0
SYMATTR InstName C1
SYMATTR Value 150
SYMBOL sw 512 -240 R180
WINDOW 0 -23 102 Right 2
WINDOW 3 -26 2 Right 2
SYMATTR InstName S1
SYMATTR Value SHORT
SYMBOL voltage 672 -352 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V4
SYMATTR Value PULSE(0 1 10m 1m 1m 30m)
SYMBOL res 480 -176 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 20K
SYMBOL res -144 -64 R0
SYMATTR InstName R1
SYMATTR Value 52.3K
SYMBOL voltage 576 -144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage -224 -160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 2
SYMBOL res -144 32 R0
SYMATTR InstName R2
SYMATTR Value 348
SYMBOL MAX14575C 128 -208 R0
SYMATTR InstName U1
TEXT 480 144 Left 2 !.model SHORT SW(Ron=0.05 Roff=1K Vt=.5 Vh=-.4)
TEXT 480 184 Left 2 !.tran 50m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\988395ac13a1_Assignment_4b__ii_.asc
* Generated by LTspice 26.0.1 for Windows.
* Full Wave Rectifier (Diode Bridge) (Practical)
V1 0 N002 SINE(0 10 1000) Rser=0.001
D2 N003 0 1N4148
D1 0 N001 1N4148
R1 N001 N003 1000
D4 N003 N002 1N4148
D3 N002 N001 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 64 144 64
WIRE 144 80 144 64
WIRE 144 80 -16 80
WIRE 304 80 144 80
WIRE 304 112 304 80
WIRE -16 128 -16 80
WIRE 448 192 448 64
WIRE -16 240 -16 192
WIRE 64 240 -16 240
WIRE 144 240 64 240
WIRE 304 240 304 176
WIRE 304 240 224 240
WIRE 64 272 64 240
WIRE 304 272 304 240
WIRE -16 288 -16 240
WIRE -16 384 -16 352
WIRE 144 384 -16 384
WIRE 304 384 304 336
WIRE 304 384 144 384
WIRE 144 400 144 384
WIRE 448 400 448 272
WIRE 448 400 144 400
SYMBOL diode 0 352 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL diode 320 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value 1N4148
SYMBOL diode 320 336 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D4
SYMATTR Value 1N4148
SYMBOL diode 0 192 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL voltage 128 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 2
WINDOW 39 -60 56 VBottom 2
SYMATTR InstName V1
SYMATTR Value SINE(0 10 1000)
SYMATTR SpiceLine Rser=0.001
SYMBOL res 432 176 R0
SYMATTR InstName R1
SYMATTR Value 1000
FLAG 64 272 0
TEXT -16 424 Left 2 !.tran 5ms
TEXT -40 24 Left 2 ;Full Wave Rectifier (Diode Bridge) (Practical)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG849.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nCharge Injection not included\nSwitch shown for a logic 0 input
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG849.asy)
V3 N004 0 PULSE(0 5 25u 20n 20n 25u)
V2 N003 0 5
V4 +V 0 5
XU1 N004 N001 N002 N003 +V 0 ADG849 ;pnba IN)SA)D)SB)Vdd)GND
C1 N002 0 36p
V1 N001 0 0
R1 N002 0 49.9
.tran 75u
.lib ADG849.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2888 1548
WIRE -1600 -336 -1600 -368
WIRE -1696 -272 -2032 -272
WIRE -2032 -256 -2032 -272
WIRE -1424 -240 -1504 -240
WIRE -1312 -240 -1424 -240
WIRE -1424 -224 -1424 -240
WIRE -1312 -224 -1312 -240
WIRE -1696 -208 -1920 -208
WIRE -1920 -192 -1920 -208
WIRE -2032 -160 -2032 -176
WIRE -1696 -144 -1776 -144
WIRE -1424 -128 -1424 -144
WIRE -1312 -128 -1312 -160
WIRE -1920 -96 -1920 -112
WIRE -1776 -80 -1776 -144
WIRE -1600 -16 -1600 -32
WIRE -1776 32 -1776 0
SYMBOL voltage -1776 -96 R0
WINDOW 3 24 136 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 25u 20n 20n 25u)
SYMATTR InstName V3
SYMBOL voltage -1920 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL ADG849 -1600 -192 R0
SYMATTR InstName U1
SYMBOL res -1440 -240 R0
SYMATTR InstName R1
SYMATTR Value 49.9
SYMBOL voltage -2032 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL voltage -2032 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL cap -1328 -224 R0
SYMATTR InstName C1
SYMATTR Value 36p
FLAG -2032 -160 0
FLAG -1920 -96 0
FLAG -1776 32 0
FLAG -1600 -368 +V
FLAG -1424 -128 0
FLAG -1600 -16 0
FLAG -1312 -128 0
FLAG -2032 32 0
FLAG -2032 -48 +V
TEXT -1968 0 Left 2 !.tran 75u
TEXT -2088 -456 Left 2 ;Note:\nCharge Injection not included\nSwitch shown for a logic 0 input
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1761-BYP.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1761-BYP.asy)
C1 OUT 0 10
Rload OUT 0 500
V1 IN 0 PWL(0 0 1 10)
XU1 IN 0 N001 OUT OUT LT1761-BYP ;pnba IN)GND)BYP)ADJ)OUT
.tran 1
.lib LT1761.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -224 48
WIRE 336 48 304 48
WIRE 416 48 336 48
WIRE 512 48 416 48
WIRE -224 64 -224 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 16 144 -16 144
WIRE 336 144 336 48
WIRE 336 144 304 144
WIRE -224 160 -224 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 160 240 160 208
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL PowerProducts\\LT1761-BYP 160 96 R0
SYMATTR InstName U1
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 500
SYMBOL voltage -224 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
FLAG -224 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 160 240 0
FLAG 512 48 OUT
FLAG -224 48 IN
TEXT 376 224 Left 2 !.tran 1