Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\0bb778c1d221_CH04-KP2-01.asc
* Generated by LTspice 26.0.1 for Windows.
V3 ctrl 0 PULSE(0 1 0 1n 1n 50 50 1)
L1 N003 vc 1 Rser=0
S1 N001 N002 ctrl 0 SW1
S2 N004 N002 ctrl 0 SW2
V1 N001 0 5
R1 N003 N002 10
C1 vc 0 0.4
V2 N004 0 8
.model SW2 SW(Ron=1n Roff=1Meg Vt=.5)
.model SW1 SW(Ron=1Meg Roff=1n Vt=.5)
.tran 15
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 992 680
WIRE 16 144 -48 144
WIRE 448 144 96 144
WIRE 560 144 448 144
WIRE 768 144 640 144
WIRE 32 208 32 192
WIRE 768 208 768 144
WIRE 256 256 128 256
WIRE 448 256 448 144
WIRE 448 256 336 256
WIRE 272 320 272 304
WIRE 768 320 768 288
WIRE 768 336 768 320
WIRE -48 352 -48 144
WIRE 128 352 128 256
WIRE 128 448 128 432
WIRE 768 448 768 400
WIRE 768 448 128 448
WIRE -48 464 -48 432
WIRE 128 464 128 448
WIRE 656 640 656 608
SYMBOL sw 0 144 R270
SYMATTR InstName S1
SYMATTR Value SW1
SYMBOL cap 752 336 R0
SYMATTR InstName C1
SYMATTR Value 0.4
SYMBOL ind 752 192 R0
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=0
SYMBOL voltage -48 336 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 656 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL voltage 128 336 R0
SYMATTR InstName V2
SYMATTR Value 8
SYMBOL sw 240 256 R270
SYMATTR InstName S2
SYMATTR Value SW2
SYMBOL voltage 656 512 R0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 0 1n 1n 50 50 1)
FLAG 656 640 0
FLAG 128 464 0
FLAG -48 464 0
FLAG 32 208 0
FLAG 272 320 0
FLAG 656 528 ctrl
FLAG 80 192 ctrl
FLAG 320 304 ctrl
FLAG 768 320 vc
TEXT -56 552 Left 2 !.model SW2 SW(Ron=1n Roff=1Meg Vt=.5)\n.model SW1 SW(Ron=1Meg Roff=1n Vt=.5)\n.tran 15
* Z:\home\khalils\Downloads\files\data\raw_asc\106153839186_URL.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot the quantities V(X1)/V(Y1) and V(X2)/V(Y2) to plot open loop gains.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1014.asy)
V2 -V 0 -15
XU1 0 Y2 +V -V X2 LM324/NS ;pnba In+)In-)V+)V-)OUT
V3 Y2 X2 ac 1
XU2 0 Y1 +V -V X1 LT1013 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 +15
V4 Y1 X1 ac 1
.lib http://www.national.com/models/spice/LM/LM324.MOD
.ac oct 10 1m 100Meg
.lib LT1013.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -112 240 -112 112
WIRE -80 112 -112 112
WIRE -80 240 -112 240
WIRE -80 272 -96 272
WIRE -48 224 -48 208
WIRE -48 304 -48 288
WIRE 16 112 0 112
WIRE 16 256 -16 256
WIRE 16 256 16 112
WIRE 112 240 112 112
WIRE 144 112 112 112
WIRE 144 240 112 240
WIRE 144 272 128 272
WIRE 176 224 176 208
WIRE 176 304 176 288
WIRE 240 112 224 112
WIRE 240 256 208 256
WIRE 240 256 240 112
WIRE 400 160 400 144
WIRE 400 256 400 240
WIRE 512 160 512 144
WIRE 512 256 512 240
SYMBOL voltage 128 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName V3
SYMATTR Value ac 1
SYMBOL opamps\\opamp2 176 192 R0
SYMATTR InstName U1
SYMATTR Value LM324/NS
SYMBOL voltage 400 144 R0
SYMATTR InstName V1
SYMATTR Value +15
SYMBOL opamps\\LT1014 -48 192 R0
SYMATTR InstName U2
SYMBOL voltage 512 144 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -96 112 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName V4
SYMATTR Value ac 1
FLAG 176 208 +V
FLAG 176 304 -V
FLAG 512 256 0
FLAG 400 256 0
FLAG 400 144 +V
FLAG 512 144 -V
FLAG 128 272 0
FLAG 240 112 X2
FLAG 112 112 Y2
FLAG -48 208 +V
FLAG -48 304 -V
FLAG -96 272 0
FLAG 16 112 X1
FLAG -112 112 Y1
TEXT -168 400 Left 0 !.lib http://www.national.com/models/spice/LM/LM324.MOD
TEXT -168 368 Left 0 !.ac oct 10 1m 100Meg
TEXT -184 16 Left 0 ;Plot the quantities V(X1)/V(Y1) and V(X2)/V(Y2) to plot open loop gains.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4611.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4611.asy)
XU1 0 NC_01 OUT 0 OUT N001 N001 NC_02 0 N002 N005 N003 N004 IN IN 0 LTM4611 ;pnba Mode_PLLin)Pgood)Vosns+)Vosns-)Vout)Vout_lcl)DiffVout)IntVcc)SGND)PLLFLTR/Fset)FB)Comp)Track/SS)Run)Vin)PGND
Rload OUT 0 67m
C1 OUT 0 500
V1 IN 0 3.3
C2 N004 0 .001
R1 N005 0 240K
.tran 1m startup
.lib LTM4611.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 -96 -112 -96
WIRE 144 -96 0 -96
WIRE -112 -80 -112 -96
WIRE 144 -80 144 -96
WIRE 0 -32 0 -96
WIRE 16 -32 0 -32
WIRE 416 -32 368 -32
WIRE 496 -32 416 -32
WIRE 592 -32 496 -32
WIRE 496 -16 496 -32
WIRE 592 -16 592 -32
WIRE -112 16 -112 0
WIRE 384 64 368 64
WIRE 496 80 496 48
WIRE 592 80 592 64
WIRE 16 160 0 160
WIRE 384 160 384 64
WIRE 384 160 368 160
WIRE 16 256 -16 256
WIRE 416 256 416 -32
WIRE 416 256 368 256
WIRE 16 352 0 352
WIRE 400 352 368 352
WIRE -64 448 -80 448
WIRE 16 448 0 448
WIRE 384 448 368 448
WIRE 480 448 464 448
WIRE 144 512 144 496
WIRE 240 512 240 496
SYMBOL voltage -112 -96 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL PowerProducts\\LTM4611 192 208 R0
SYMATTR InstName U1
SYMBOL cap 480 -16 R0
SYMATTR InstName C1
SYMATTR Value 500
SYMBOL res 368 464 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 240K
SYMBOL cap 0 432 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .001
SYMBOL res 576 -32 R0
SYMATTR InstName Rload
SYMATTR Value 67m
FLAG -112 16 0
FLAG 400 352 0
FLAG 240 512 0
FLAG 144 512 0
FLAG 480 448 0
FLAG 496 80 0
FLAG 592 80 0
FLAG 592 -32 OUT
FLAG -112 -96 IN
FLAG -80 448 0
FLAG -16 256 0
TEXT 480 312 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\61d9b327f701_iNMOS.asc
* Generated by LTspice 26.0.1 for Windows.
* body diode
* snubber
* binary
* Ideal NMOS
* on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
* Drain
* Source
* Gate
* 2025-7-21
* <Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
C1 N003 S {csnb}
L2 D N002 {esl}
R1 D N003 {rsnb}
S1 S N001 G S SW_iNMOS
L1 D N001 {esl}
D1 S N002 myD
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)
.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
.param ron=10m
.param esl=1f
.param rsnb=1k
.param csnb=10p
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1384 680
WIRE 288 -288 288 -320
WIRE 608 -288 288 -288
WIRE 928 -288 608 -288
WIRE 288 -240 288 -288
WIRE 608 -240 608 -288
WIRE 928 -192 928 -288
WIRE 288 -112 288 -160
WIRE 240 -96 96 -96
WIRE 608 -96 608 -160
WIRE 928 -80 928 -112
WIRE 240 -48 208 -48
WIRE 208 0 208 -48
WIRE 288 0 288 -32
WIRE 288 0 208 0
WIRE 288 80 288 0
WIRE 608 80 608 -32
WIRE 608 80 288 80
WIRE 928 80 928 -16
WIRE 928 80 608 80
WIRE 288 112 288 80
IOPIN 288 -320 BiDir
IOPIN 288 112 BiDir
IOPIN 96 -96 BiDir
SYMBOL ind 592 -256 R0
SYMATTR InstName L2
SYMATTR Value {esl}
SYMBOL cap 912 -80 R0
SYMATTR InstName C1
SYMATTR Value {csnb}
SYMBOL res 912 -208 R0
SYMATTR InstName R1
SYMATTR Value {rsnb}
SYMBOL ind 272 -256 R0
SYMATTR InstName L1
SYMATTR Value {esl}
SYMBOL diode 624 -32 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value myD
SYMBOL sw 288 -16 M180
SYMATTR InstName S1
SYMATTR Value SW_iNMOS
FLAG 288 -320 D
FLAG 288 112 S
FLAG 96 -96 G
TEXT 56 -440 Left 2 !.MODEL SW_iNMOS SW (VT=0.5 RON={ron} ROFF=100Meg)\n.MODEL myD D(RON=10u ROFF=100Meg Vfwd=1p)
TEXT 56 -568 Left 2 !.param ron=10m\n.param esl=1f\n.param rsnb=1k\n.param csnb=10p
TEXT 552 -320 Left 2 ;body diode
TEXT 888 -320 Left 2 ;snubber
TEXT 56 -120 Left 1 ;binary
TEXT 40 -624 Left 4 ;Ideal NMOS
TEXT 312 -568 Left 2 ;on resistance of NMOS/Body Diode\nseries inductance\nsnubber resistance\nsnubber capacitance
TEXT 312 -344 Left 2 ;Drain
TEXT 312 136 Left 2 ;Source
TEXT 56 -64 Left 2 ;Gate
TEXT 1000 -624 Left 2 ;2025-7-21
TEXT 80 208 Left 2 ;<Revision History>\n2024-12-29: Initial version\n2025-07-21: Changed body diode model from SW based to D model based to improve convergence.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP121-1.2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP121-1.2.asy)
C1 IN 0 1
V1 IN 0 5.5
Rload OUT 0 22
C2 OUT 0 1
XU1 OUT MP_01 0 IN MP_02 IN ADP121 K=1/1500 ;pnba Vout))GND)En))Vin
.tran 10m startup
.lib ADP121.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 400 96 352 96
WIRE 480 96 400 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 400 112 400 96
WIRE 480 112 480 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 400 208 400 176
WIRE 480 208 480 192
WIRE 256 272 256 256
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP121-1.2 256 208 R0
SYMATTR InstName U1
SYMBOL cap 384 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 464 96 R0
SYMATTR InstName Rload
SYMATTR Value 22
FLAG 0 208 0
FLAG 256 272 0
FLAG 400 208 0
FLAG 480 208 0
FLAG 480 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\075fbc4ac33a_1126.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
R1 OUT N001 364.76K
R2 N001 0 365
V3 IN 0 ac 1
XU1 IN N001 +V -V OUT LT1126 ;pnba In+)In-)V+)V-)OUT
.ac oct 10 1m 1Meg
* Gain 1000 Amplifier with 0.01% Accuracy, DC to 5Hz
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1126.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -208 112 -208 96
WIRE -112 112 -112 96
WIRE -208 208 -208 192
WIRE -112 208 -112 192
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
FLAG -112 208 0
FLAG 192 192 +V
FLAG -112 96 +V
FLAG 192 288 -V
FLAG -208 208 0
FLAG -208 96 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 288 240 OUT
FLAG 0 256 IN
SYMBOL voltage -112 96 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL voltage -208 96 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 364.76K
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 365
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value ac 1
SYMBOL opamps\\LT1126 192 176 R0
SYMATTR InstName U1
TEXT 160 360 Left 2 !.ac oct 10 1m 1Meg
TEXT 96 40 Bottom 2 ;Gain 1000 Amplifier with 0.01% Accuracy, DC to 5Hz
* Z:\home\khalils\Downloads\files\data\raw_asc\26cab14e2f46_PL-B2.asc
* Generated by LTspice 26.0.1 for Windows.
D2 N001 0 CDZV10B
V1 a 0 PWL REPEAT FOREVER (0 -20 .5 20 1 -20) ENDREPEAT
R1 b a 200
R2 0 b 2000
D1 N001 b CDZV10B
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3
.lib cdzv10b.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 112 -64 112
WIRE 256 112 96 112
WIRE 336 112 256 112
WIRE 352 112 336 112
WIRE 256 128 256 112
WIRE -64 160 -64 112
WIRE 352 160 352 112
WIRE 256 208 256 192
WIRE -64 304 -64 240
WIRE 48 304 -64 304
WIRE 256 304 256 272
WIRE 256 304 48 304
WIRE 352 304 352 240
WIRE 352 304 256 304
WIRE 48 320 48 304
SYMBOL zener 240 208 R0
WINDOW 0 40 29 Left 2
WINDOW 3 -87 116 Left 2
SYMATTR InstName D2
SYMATTR Value CDZV10B
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL Misc\\EuropeanResistor 112 96 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200
SYMBOL Misc\\EuropeanResistor 368 256 R180
WINDOW 0 -42 76 Left 2
WINDOW 3 -64 52 Left 2
SYMATTR InstName R2
SYMATTR Value 2000
SYMBOL voltage -64 144 R0
WINDOW 3 -221 222 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PWL REPEAT FOREVER (0 -20 .5 20 1 -20) ENDREPEAT
SYMATTR InstName V1
SYMBOL zener 272 192 R180
WINDOW 0 -43 33 Left 2
WINDOW 3 -14 101 Left 2
SYMATTR InstName D1
SYMATTR Value CDZV10B
SYMATTR Description Diode
SYMATTR Type diode
FLAG -64 112 a
FLAG 336 112 b
FLAG 48 320 0
TEXT -296 112 Left 2 !.tran 3
TEXT -296 144 Left 2 !.lib cdzv10b.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\54d489d33e68_RN-3.asc
* Generated by LTspice 26.0.1 for Windows.
R1 b 0 100
V1 a 0 SINE(0 14 1k)
D1 b a RFN2L6S
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 144 -208 144
WIRE -112 144 -176 144
WIRE 32 144 -48 144
WIRE 48 144 32 144
WIRE -208 192 -208 144
WIRE 48 192 48 144
WIRE -208 320 -208 272
WIRE -80 320 -208 320
WIRE 48 320 48 272
WIRE 48 320 -80 320
WIRE -80 336 -80 320
SYMBOL diode -48 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value RFN2L6S
SYMBOL Misc\\signal -208 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 14 1k)
SYMBOL Misc\\EuropeanResistor 32 176 R0
SYMATTR InstName R1
SYMATTR Value 100
FLAG -80 336 0
FLAG -176 144 a
FLAG 32 144 b
TEXT -248 336 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\05aa4b2b81ab_transformer_coupled_class_B.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N002 vin 1
L1 vcc N001 8m
R3 vout 0 8
L2 vcc N004 8m
R1 N002 N003 1k
K1 L1 L2 L3 1
V1 vcc 0 12V
Q1 N001 N002 0 0 BD135
Q2 N004 N002 0 0 BD135
L3 0 vout 5m
R2 N003 N002 1k
V2 vin 0 SINE(0 1V 1k)
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 5ms
.lib BD135.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 920 680
WIRE 640 -80 368 -80
WIRE 368 -48 368 -80
WIRE 640 -32 640 -80
WIRE 64 0 32 0
WIRE 144 0 128 0
WIRE 224 0 144 0
WIRE 304 0 224 0
WIRE 864 0 768 0
WIRE 768 48 768 0
WIRE 864 48 864 0
WIRE 368 96 368 48
WIRE 416 96 368 96
WIRE 640 96 640 48
WIRE 640 96 544 96
WIRE 224 112 224 80
WIRE 416 128 416 96
WIRE 368 144 368 96
WIRE 144 192 144 0
WIRE 224 192 144 192
WIRE 304 192 224 192
WIRE 640 192 640 96
WIRE 768 192 768 128
WIRE 864 192 864 128
WIRE 864 192 768 192
WIRE 768 224 768 192
WIRE 368 304 368 240
WIRE 640 304 640 272
WIRE 640 304 368 304
SYMBOL res 848 32 R0
SYMATTR InstName R3
SYMATTR Value 8
SYMBOL res 208 -16 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -80 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12V
SYMBOL ind 624 176 R0
SYMATTR InstName L2
SYMATTR Value 8m
SYMATTR Type ind
SYMBOL cap 128 -16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1u
SYMBOL ind 784 144 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L3
SYMATTR Value 5m
SYMATTR Type ind
SYMBOL npn 304 -48 R0
SYMATTR InstName Q1
SYMATTR Value BD135
SYMBOL npn 304 240 M180
SYMATTR InstName Q2
SYMATTR Value BD135
SYMBOL res 208 96 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage 48 80 R0
WINDOW 3 -63 140 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 1V 1k)
SYMBOL ind 624 64 M180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value 8m
SYMATTR Type ind
FLAG -80 96 vcc
FLAG 416 128 0
FLAG 544 96 vcc
FLAG 48 96 vin
FLAG 48 176 0
FLAG -80 176 0
FLAG 864 0 vout
FLAG 768 224 0
FLAG 32 0 vin
TEXT 408 240 Left 2 !K1 L1 L2 L3 1
TEXT 424 -25 Left 2 !.tran 5ms
TEXT 408 200 Left 2 !.lib BD135.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\0c27a2b21502_final_schematic.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .tf V(Vout) V1
* .tran 5m
V2 Vdd 0 1.8
V1 Vin 0 SINE(0.75 1m 1k) AC 1
M2 Vout Vout Vdd Vdd PMOS l=0.72u w=5.50u
M1 Vout Vin 0 0 NMOS l=0.72u w=3.57u
C1 Vout 0 1p
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.options plotwinsize=0
.include tsmc180.txt
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -80 240 -144
WIRE 352 -80 240 -80
WIRE 240 -32 240 -80
WIRE 192 -16 160 -16
WIRE 352 16 352 -80
WIRE 352 16 240 16
WIRE 160 80 160 -16
WIRE 240 80 240 64
WIRE 240 80 160 80
WIRE 240 112 240 80
WIRE 512 112 240 112
WIRE 576 112 512 112
WIRE 240 144 240 112
WIRE 512 160 512 112
WIRE 352 192 240 192
WIRE 192 224 80 224
WIRE -256 240 -256 192
WIRE -128 240 -128 192
WIRE 240 288 240 240
WIRE 352 288 352 192
WIRE 352 288 240 288
WIRE 512 288 512 224
WIRE 240 336 240 288
WIRE -256 400 -256 320
WIRE -128 400 -128 320
IOPIN 576 112 Out
SYMBOL pmos4 192 64 M180
WINDOW 123 56 4 Left 2
SYMATTR Value2 l=0.72u w=5.50u
SYMATTR InstName M2
SYMBOL voltage -128 224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL cap 496 160 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL voltage -256 224 R0
WINDOW 3 -257 105 Left 2
WINDOW 123 -137 145 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value SINE(0.75 1m 1k)
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL nmos4 192 144 R0
WINDOW 123 66 165 Left 2
SYMATTR Value2 l=0.72u w=3.57u
SYMATTR InstName M1
FLAG -256 400 0
FLAG -128 400 0
FLAG -256 192 Vin
FLAG -128 192 Vdd
FLAG 240 336 0
FLAG 512 288 0
FLAG 80 224 Vin
FLAG 576 112 Vout
FLAG 240 -144 Vdd
TEXT -328 -136 Left 2 !.options plotwinsize=0
TEXT -328 -104 Left 2 !.include tsmc180.txt
TEXT -328 -80 Left 2 ;.op
TEXT -328 -48 Left 2 ;.tf V(Vout) V1
TEXT -328 -16 Left 2 ;.tran 5m
TEXT -328 16 Left 2 !.ac dec 10 10 1gig
* Z:\home\khalils\Downloads\files\data\raw_asc\37b23b6367e5_lpf_0_2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6220.asy)
V1 N002 0 AC 1
V2 +3V3 0 3V3
R1 N003 N002 16k
XU1 N003 N001 +3V3 0 N001 LT6220 ;pnba IN+)IN-)VCC)VEE)OUT
R2 N003 0 100k
C1 N003 0 10n
.ac dec 50 10 100000
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 512 -48 384 -48
WIRE 432 32 432 16
WIRE 384 48 384 -48
WIRE 400 48 384 48
WIRE 512 64 512 -48
WIRE 512 64 464 64
WIRE 64 80 0 80
WIRE 192 80 144 80
WIRE 288 80 192 80
WIRE 400 80 288 80
WIRE 288 96 288 80
WIRE -112 112 -112 96
WIRE 0 112 0 80
WIRE 192 112 192 80
WIRE 432 112 432 96
WIRE -112 208 -112 192
WIRE 0 208 0 192
WIRE 192 208 192 176
WIRE 288 208 288 176
SYMBOL res 272 80 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage 0 96 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value ""
SYMBOL cap 176 112 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL res 160 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 16k
SYMBOL voltage -112 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 3V3
SYMBOL Opamps\\LT6220 432 64 R0
SYMATTR InstName U1
FLAG 192 208 0
FLAG 0 208 0
FLAG 288 208 0
FLAG 432 16 +3V3
FLAG 432 112 0
FLAG -112 208 0
FLAG -112 96 +3V3
TEXT 0 272 Left 2 !.ac dec 50 10 100000
* Z:\home\khalils\Downloads\files\data\raw_asc\0b620862918f_oscillator40.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD820.asy)
C1 N004 0 1nf
D1 N002 N001 1N4148
R5 N002 N001 3k9
V1 +VCC 0 15
C2 N002 P001 1nf
V2 -VCC 0 -15
XU1 N004 N003 +VCC -VCC N002 AD820 ;pnba In+)In-)V+)V-)OUT
R4 N001 N003 18k
R1 N004 0 3k74
D2 N001 N002 1N4148
R3 N003 0 10k
R2 P001 N004 3k74
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran .002 startup uic
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 464 -240 384 -240
WIRE 384 -176 384 -240
WIRE 528 -176 528 -240
WIRE 528 -176 448 -176
WIRE 384 -80 384 -176
WIRE 384 -80 256 -80
WIRE 528 -80 528 -176
WIRE 528 -80 464 -80
WIRE 672 -80 528 -80
WIRE 256 -16 256 -80
WIRE 256 80 256 64
WIRE 400 80 256 80
WIRE 672 96 672 -80
WIRE 672 96 464 96
WIRE 400 112 352 112
WIRE 256 208 256 80
WIRE 352 208 352 112
WIRE 416 208 352 208
WIRE 528 208 416 208
WIRE 672 208 672 96
WIRE 352 288 352 272
WIRE 384 288 352 288
WIRE 416 288 384 288
SYMBOL voltage 32 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL res 400 192 R0
SYMATTR InstName R1
SYMATTR Value 3k74
SYMBOL res 480 -96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 3k9
SYMBOL res 240 192 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL cap 672 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1nf
SYMBOL diode 464 -224 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL OpAmps\\AD820 432 32 R0
SYMATTR InstName U1
SYMBOL cap 336 208 R0
SYMATTR InstName C1
SYMATTR Value 1nf
SYMBOL res 240 -32 R0
SYMATTR InstName R4
SYMATTR Value 18k
SYMBOL voltage 144 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL diode 448 -192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 624 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 3k74
FLAG 32 192 0
FLAG 144 192 0
FLAG 32 112 +VCC
FLAG 144 112 -VCC
FLAG 432 128 -VCC
FLAG 432 64 +VCC
FLAG 384 288 0
FLAG 256 288 0
TEXT -2 312 Left 2 !.tran .002 startup uic
* Z:\home\khalils\Downloads\files\data\raw_asc\04fb32332b97_R1C1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 VIN VOUT 1k
C1 VOUT 0 100n
V1 VIN 0 SINE(0 0.5 1k)
.tran 0 0.01 0 0.001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 -288 16 -288
WIRE 288 -288 192 -288
WIRE 368 -288 288 -288
WIRE 16 -224 16 -288
WIRE 288 -208 288 -288
WIRE 16 -64 16 -144
WIRE 288 -64 288 -144
WIRE 288 -64 16 -64
WIRE 288 -32 288 -64
SYMBOL voltage 16 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 0.5 1k)
SYMBOL res 96 -272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 272 -208 R0
SYMATTR InstName C1
SYMATTR Value 100n
FLAG 368 -288 VOUT
FLAG 288 -32 0
FLAG 288 -64 GROUND
FLAG 16 -288 VIN
TEXT 24 -48 Left 2 !.tran 0 0.01 0 0.001
* Z:\home\khalils\Downloads\files\data\raw_asc\f872a7d16451_Brain.asc
* Generated by LTspice 26.0.1 for Windows.
* DESCRIPTION: Sixteen step analog memory
D2 N004 STEP_TRIGGER 1N4148
J3 N002 N004 CV_OUT 2N3819
C1 N001 0 10n
J1 CV_IN N003 N001 2N3819
R1 N002 -15 2k
D3 N003 PROG_TRIGGER 1N4148
D1 N003 STEP_TRIGGER 1N4148
J2 +15 N001 N002 2N3819
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 352 -128 352 -208
WIRE 64 -64 -192 -64
WIRE 240 -64 160 -64
WIRE 304 -64 240 -64
WIRE 240 -16 240 -64
WIRE 352 -16 352 -32
WIRE 480 -16 352 -16
WIRE 624 -16 576 -16
WIRE 128 0 128 -16
WIRE 128 0 64 0
WIRE 352 0 352 -16
WIRE 64 16 64 0
WIRE 128 16 128 0
WIRE 544 48 544 32
WIRE 64 128 64 80
WIRE 128 128 128 80
WIRE 240 128 240 48
WIRE 352 128 352 80
WIRE 544 128 544 112
SYMBOL diode 80 16 M0
SYMATTR InstName D3
SYMATTR Value 1N4148
SYMBOL njf 480 32 R270
SYMATTR InstName J3
SYMATTR Value 2N3819
SYMBOL njf 304 -128 R0
SYMATTR InstName J2
SYMATTR Value 2N3819
SYMBOL diode 112 16 R0
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL diode 528 48 R0
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL res 336 -16 R0
SYMATTR InstName R1
SYMATTR Value 2k
SYMBOL cap 224 -16 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL njf 64 -16 R270
SYMATTR InstName J1
SYMATTR Value 2N3819
FLAG 352 128 -15
FLAG 352 -208 +15
FLAG 240 128 0
FLAG -192 -64 CV_IN
FLAG 624 -16 CV_OUT
FLAG 128 128 STEP_TRIGGER
FLAG 544 128 STEP_TRIGGER
FLAG 64 128 PROG_TRIGGER
TEXT -8 408 Left 0 ;DESCRIPTION: Sixteen step analog memory