Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\02aa51ef5066_B_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
IREF Vin N005 0.000091 AC 0
RL Vo N005 10k
Q2 Vin N003 N001 0 My2n3906
C1 Vo N004 100T
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1424 680
WIRE -608 -320 -608 -576
WIRE -32 -320 -32 -576
WIRE -336 -272 -544 -272
WIRE -32 -192 -32 -224
WIRE 160 -192 -32 -192
WIRE 160 -128 160 -192
WIRE -608 -112 -608 -224
WIRE -336 -112 -608 -112
WIRE -32 -112 -32 -192
WIRE -608 -64 -608 -112
WIRE -608 48 -608 -64
WIRE -32 48 -32 -112
WIRE 160 48 160 -64
WIRE -608 208 -608 128
WIRE -32 208 -32 128
WIRE -32 208 -608 208
WIRE -32 240 -32 208
SYMBOL current -608 48 R0
WINDOW 3 24 28 Left 2
WINDOW 123 24 56 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName IREF
SYMATTR Value 0.000091
SYMATTR Value2 AC 0
SYMBOL res -48 32 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL pnp -544 -224 R180
SYMATTR InstName Q2
SYMATTR Value My2n3906
SYMBOL cap 144 -128 R0
SYMATTR InstName C1
SYMATTR Value 100T
FLAG -32 -112 Vo
FLAG -608 -64 Vin
* Z:\home\khalils\Downloads\files\data\raw_asc\2f09260894fa_NMOS_CHART_SETUP.asc
* Generated by LTspice 26.0.1 for Windows.
;.dc vgs 0 1.8 10m
vds vds 0 1.8
M1 N001 N002 0 0 NMOS l=0.36u w={wn}
vgs vgs 0 0.625
R1 vds N001 1.5k
R2 N002 vgs 1Meg
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include tsmc180.txt
.step param wn 0.18u 20u 0.18u
.param wn=0.18u
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 -32 208 -48
WIRE -320 32 -320 -32
WIRE -144 32 -144 -48
WIRE 208 96 208 48
WIRE 400 144 208 144
WIRE 48 176 16 176
WIRE 160 176 128 176
WIRE -480 192 -480 80
WIRE -320 192 -320 112
WIRE -144 208 -144 112
WIRE 208 320 208 192
IOPIN 16 176 In
SYMBOL voltage -320 16 R0
WINDOW 3 20 112 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 0.625
SYMATTR InstName vgs
SYMBOL res 192 -48 R0
SYMATTR InstName R1
SYMATTR Value 1.5k
SYMBOL res 144 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage -144 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vds
SYMATTR Value 1.8
SYMBOL nmos4 160 96 R0
WINDOW 123 56 100 Left 2
SYMATTR Value2 l=0.36u w={wn}
SYMATTR InstName M1
FLAG -320 192 0
FLAG -480 192 0
FLAG -144 208 0
FLAG -480 80 vss
FLAG 400 144 vss
FLAG 208 320 vss
FLAG -320 -32 vgs
FLAG -144 -48 vds
FLAG 16 176 vgs
FLAG 208 -48 vds
TEXT -456 320 Left 2 !.include tsmc180.txt
TEXT -448 344 Left 2 !;.dc vgs 0  1.8  10m
TEXT -496 384 Left 2 !.step param wn 0.18u 20u 0.18u
TEXT -432 432 Left 2 !.param wn=0.18u
TEXT -576 312 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1078.asc
* Generated by LTspice 26.0.1 for Windows.
* Absolute Value Circuit(Full-Wave Rectifier)
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1078.asy)
XU2 N002 OUT +V 0 OUT LT1078 ;pnba In+)In-)V+)V-)OUT
V3 IN 0 SINE(0 1 100)
V1 +V 0 5
XU1 0 N001 +V 0 N003 LT1078 ;pnba In+)In-)V+)V-)OUT
R1 N002 N001 200K
D1 N003 N002 1N4148
R2 N001 IN 200K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 30m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 -80 96
WIRE 128 96 112 96
WIRE 224 96 128 96
WIRE 400 96 304 96
WIRE -80 112 -80 96
WIRE 560 128 448 128
WIRE -192 160 -192 144
WIRE 496 192 496 176
WIRE -80 208 -80 192
WIRE 192 208 192 192
WIRE 448 208 448 128
WIRE 464 208 448 208
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE 560 224 560 128
WIRE 560 224 528 224
WIRE 592 224 560 224
WIRE 320 240 224 240
WIRE 400 240 400 96
WIRE 400 240 384 240
WIRE 464 240 400 240
WIRE -192 256 -192 240
WIRE 160 256 128 256
WIRE 496 272 496 256
WIRE 192 288 192 272
SYMBOL voltage -80 96 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
SYMBOL res 320 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 200K
SYMBOL opamps\\LT1078 496 160 R0
SYMATTR InstName U2
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 200K
SYMBOL opamps\\LT1078 192 176 R0
SYMATTR InstName U1
SYMBOL voltage -192 144 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL diode 320 256 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG -192 256 0
FLAG 192 192 +V
FLAG -192 144 +V
FLAG -80 208 0
FLAG 192 288 0
FLAG 496 176 +V
FLAG 496 272 0
FLAG -80 96 IN
FLAG 592 224 OUT
FLAG 128 256 0
TEXT 416 344 Left 2 !.tran 30m
TEXT 392 32 Bottom 2 ;Absolute Value Circuit(Full-Wave Rectifier)
* Z:\home\khalils\Downloads\files\data\raw_asc\35e530be0ccf_F_vo_50k.asc
* Generated by LTspice 26.0.1 for Windows.
R1 PuntaX1Vout 0 10k
V2 N001 0 SINE(0 5 50k)
C2 PuntaX1Vout 0 200p
R4 PuntaX1Vout 0 1Meg
D1 PuntaX1Vin PuntaX1Vout D1N4001
C1 PuntaX1Vin 0 200p
R2 N001 PuntaX1Vin 50
R3 PuntaX1Vin 0 1Meg
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.lib Diodos.sub
.tran 0 80u 40u
.meas Vmedio AVG V(Puntax1Vout) from 0us to 20us
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE -432 64 -480 64
WIRE -288 64 -352 64
WIRE 64 64 -32 64
WIRE 144 64 64 64
WIRE 336 64 208 64
WIRE 432 64 336 64
WIRE 704 64 656 64
WIRE 752 64 704 64
WIRE 432 96 432 64
WIRE 656 96 656 64
WIRE -480 112 -480 64
WIRE 752 112 752 64
WIRE 656 208 656 176
WIRE 704 208 656 208
WIRE 752 208 752 176
WIRE 752 208 704 208
WIRE -480 256 -480 192
WIRE 432 256 432 176
WIRE 704 256 704 208
WIRE 704 336 656 336
WIRE 752 336 704 336
WIRE 656 368 656 336
WIRE 752 384 752 336
WIRE 656 480 656 448
WIRE 704 480 656 480
WIRE 752 480 752 448
WIRE 752 480 704 480
WIRE 704 528 704 480
SYMBOL cap 736 384 R0
SYMATTR InstName C1
SYMATTR Value 200p
SYMBOL diode 144 80 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value D1N4001
SYMBOL res 640 80 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
SYMBOL res -448 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 50
SYMBOL res 416 80 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL cap 736 112 R0
SYMATTR InstName C2
SYMATTR Value 200p
SYMBOL voltage -480 96 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 5 50k)
SYMBOL res 640 352 R0
SYMATTR InstName R3
SYMATTR Value 1Meg
FLAG 432 256 0
FLAG -480 256 0
FLAG -288 64 GenF
FLAG -32 64 GenF
FLAG 704 256 0
FLAG 704 64 PuntaX1Vout
FLAG 336 64 PuntaX1Vout
FLAG 704 528 0
FLAG 704 336 PuntaX1Vin
FLAG 64 64 PuntaX1Vin
TEXT -288 344 Left 2 !.lib Diodos.sub
TEXT -64 344 Left 2 !.tran 0 80u 40u
TEXT -280 400 Left 2 !.meas Vmedio AVG V(Puntax1Vout) from 0us to 20us
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1740-1.1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1740-1.1.asy)
V1 IN 0 1.8
C1 OUT 0 4.7 Rser=3m
Rload OUT 0 0.55
XU1 IN OUT IN N002 OUT N001 MP_01 0 ADP1740-1.1 ;pnba Vin)Sense)EN)SS)Vout)PG))GND
R1 IN N001 100k
C2 N002 0 10n
.tran 10m startup
.lib ADP1740-1.1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE -112 32 -128 32
WIRE -16 32 -112 32
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 416 32 368 32
WIRE 496 32 416 32
WIRE 528 32 496 32
WIRE -128 48 -128 32
WIRE -16 48 -16 32
WIRE 416 48 416 32
WIRE 528 48 528 32
WIRE 80 96 80 32
WIRE 96 96 80 96
WIRE -128 144 -128 128
WIRE 416 144 416 112
WIRE 528 144 528 128
WIRE -16 176 -16 128
WIRE 96 176 -16 176
WIRE 16 240 0 240
WIRE 96 240 80 240
WIRE 368 240 368 32
WIRE 368 240 352 240
WIRE 224 304 224 288
SYMBOL res -32 32 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ADP1740-1.1 224 128 R0
SYMATTR InstName U1
SYMBOL cap 400 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=3m
SYMBOL res 512 32 R0
SYMATTR InstName Rload
SYMATTR Value 0.55
SYMBOL cap 80 224 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL voltage -128 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
FLAG 224 304 0
FLAG -128 144 0
FLAG 0 240 0
FLAG -112 32 IN
FLAG 528 144 0
FLAG 416 144 0
FLAG 496 32 OUT
TEXT 128 352 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\f0bda7996e02_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T2 0 0 N002 0 Td=50n Z0=150
T1 N001 0 0 N002 Td=50n Z0=50
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=50n Z0=150
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3311-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3311-1.asy)
C1 OUT 0 47 x2
L1 N002 OUT 100n Rser=2m
C2 N003 0 3.3n
R3 OUT N001 500K
XU1 IN IN N002 OUT 0 0 N006 N001 IN N005 N003 LTC3311-1 ;pnba Vin)EN)SW)OUT)Agnd)Pgnd)Rt)Pgood)Mode/Sync)Ith)SSTT
R4 N005 N004 4.99k
Rload OUT 0 0.125
V1 IN 0 3.3
C3 N004 0 330p
R5 N006 0 274K
.tran .4m startup
.lib LTC3311-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2648 1864
WIRE 1536 1248 1376 1248
WIRE 1712 1248 1536 1248
WIRE 1376 1264 1376 1248
WIRE 1712 1280 1712 1248
WIRE 1536 1328 1536 1248
WIRE 1552 1328 1536 1328
WIRE 1904 1328 1872 1328
WIRE 2016 1328 1984 1328
WIRE 1376 1360 1376 1344
WIRE 1536 1424 1536 1328
WIRE 1552 1424 1536 1424
WIRE 1904 1424 1872 1424
WIRE 2016 1424 2016 1328
WIRE 2016 1424 1984 1424
WIRE 2096 1424 2016 1424
WIRE 2208 1424 2096 1424
WIRE 2096 1440 2096 1424
WIRE 2208 1440 2208 1424
WIRE 1472 1520 1456 1520
WIRE 1552 1520 1536 1520
WIRE 2016 1520 2016 1424
WIRE 2016 1520 1872 1520
WIRE 2096 1536 2096 1504
WIRE 2208 1536 2208 1520
WIRE 1424 1616 1360 1616
WIRE 1552 1616 1504 1616
WIRE 1904 1616 1872 1616
WIRE 1360 1632 1360 1616
WIRE 1904 1632 1904 1616
WIRE 1648 1680 1648 1664
WIRE 1776 1680 1776 1664
WIRE 1360 1712 1360 1696
WIRE 1904 1728 1904 1712
SYMBOL LTC3311-1 1712 1456 R0
SYMATTR InstName U1
SYMBOL cap 1344 1632 R0
SYMATTR InstName C3
SYMATTR Value 330p
SYMBOL cap 1536 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 3.3n
SYMBOL res 1888 1616 R0
SYMATTR InstName R5
SYMATTR Value 274K
SYMBOL res 1520 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 4.99k
SYMBOL VOLTAGE 1376 1248 R0
SYMATTR Value 3.3
SYMATTR InstName V1
SYMBOL res 2000 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500K
SYMBOL cap 2080 1440 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 x2
SYMATTR InstName C1
SYMATTR Value 47
SYMBOL res 2192 1424 R0
SYMATTR InstName Rload
SYMATTR Value 0.125
SYMBOL ind 1888 1440 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100n
SYMATTR SpiceLine Rser=2m
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1376 1360 0
FLAG 2208 1536 0
FLAG 1456 1520 0
FLAG 2208 1424 OUT
FLAG 1376 1248 IN
FLAG 1360 1712 0
FLAG 2096 1536 0
FLAG 1904 1728 0
TEXT 2048 1616 Left 2 !.tran .4m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\47d2dffe5211_protection.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 12
D1 0 N001 KDZ20B
R1 N002 0 1k
M1 N001 0 N002 N002 IRF7204
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 80 0 80
WIRE 240 80 192 80
WIRE 448 80 336 80
WIRE 0 112 0 80
WIRE 192 112 192 80
WIRE 448 128 448 80
WIRE 0 272 0 192
WIRE 192 272 192 176
WIRE 192 272 0 272
WIRE 320 272 320 128
WIRE 320 272 192 272
WIRE 448 272 448 208
WIRE 448 272 320 272
WIRE 0 288 0 272
SYMBOL res 432 112 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL pmos 240 128 R270
WINDOW 3 76 71 VRight 2
SYMATTR InstName M1
SYMATTR Value IRF7204
SYMBOL voltage 0 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL zener 208 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value KDZ20B
SYMATTR Type tvsdiode
FLAG 0 288 0
TEXT -32 312 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3007-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3007-1.8.asy)
Rload OUT 0 180
C1 OUT 0 1
XU1 IN OUT OUT 0 IN LT3008-1.8 ;pnba IN)OUT)Sense)GND)_SHDN
V1 IN 0 PWL(0 0 1 10)
.tran 1
.lib LT3009.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 48 -208 48
WIRE 32 48 0 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 0 144 0 48
WIRE 32 144 0 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL PowerProducts\\LT3007-1.8 176 96 R0
SYMATTR InstName U1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 180
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 336 248 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8052A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8052A.asy)
R3 N004 0 9.09K
Rload OUT 0 .5
R1 IN N001 510K
V1 IN 0 24
C2 OUT 0 100 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
R2 N007 0 90.9K
XU1 0 N001 N002 N002 OUT N002 MP_01 N006 MP_02 N004 MP_03 MP_04 MP_05 N005 N007 MP_06 MP_07 MP_08 MP_09 MP_10 MP_11 MP_12 MP_13 MP_14 MP_15 MP_16 MP_17 IN LTM8052A ;pnba GND)RUN)Vref)CTL_T)Vout)CTL_I))SS))ADJ))))Comp)Rt)))))))))))))Vin
C1 OUT 0 330 V=6.3 Irms=3.9 Rser=0.01 Lser=0 mfg="KEMET" pn="T520D337M006ASE010" type="Tantalum"
.tran 1.2m startup
.lib LTM8052A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 -80 -144 -80
WIRE 208 -80 -32 -80
WIRE -144 -64 -144 -80
WIRE -32 -64 -32 -80
WIRE 208 -32 208 -80
WIRE -144 32 -144 16
WIRE -32 32 -32 16
WIRE 64 32 -32 32
WIRE 432 32 352 32
WIRE 528 32 432 32
WIRE 624 32 528 32
WIRE 432 48 432 32
WIRE 528 48 528 32
WIRE 624 48 624 32
WIRE 64 128 48 128
WIRE 368 128 352 128
WIRE 432 144 432 112
WIRE 528 144 528 112
WIRE 624 144 624 128
WIRE 48 224 48 128
WIRE 64 224 48 224
WIRE 368 224 352 224
WIRE 464 224 448 224
WIRE 48 320 48 224
WIRE 64 320 48 320
WIRE 368 320 352 320
WIRE 64 416 48 416
WIRE 368 416 352 416
WIRE 464 416 448 416
WIRE 208 496 208 480
SYMBOL PowerProducts\\LTM8052A 208 224 R0
SYMATTR InstName U1
SYMBOL res -48 -80 R0
SYMATTR InstName R1
SYMATTR Value 510K
SYMBOL res 352 432 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 90.9K
SYMBOL voltage -144 -80 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 608 32 R0
SYMATTR InstName Rload
SYMATTR Value .5
SYMBOL res 352 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 9.09K
SYMBOL cap 512 48 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
SYMBOL polcap 416 48 R0
WINDOW 3 24 64 Left 2
SYMATTR Value 330
SYMATTR InstName C1
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=6.3 Irms=3.9 Rser=0.01 Lser=0 mfg="KEMET" pn="T520D337M006ASE010" type="Tantalum"
FLAG 208 496 0
FLAG -144 32 0
FLAG -144 -80 IN
FLAG 464 416 0
FLAG 464 224 0
FLAG 624 144 0
FLAG 432 144 0
FLAG 624 32 OUT
FLAG 528 144 0
TEXT 472 320 Left 2 !.tran 1.2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1389-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1389-2.5.asy)
XU1 N002 0 LT1389-2.5 ;pnba VCC)VEE
V1 N001 0 PULSE(0 5 1.5m 10n 10n 4m 2)
R1 N001 N002 2.8Meg
.tran 10m
.lib LT1389-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3476 836
WIRE 720 -272 544 -272
WIRE 960 -272 800 -272
WIRE 544 -240 544 -272
WIRE 960 -224 960 -272
WIRE 544 -128 544 -160
WIRE 960 -128 960 -160
SYMBOL LT1389-2.5 960 -192 R0
SYMATTR InstName U1
SYMBOL res 704 -256 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 2.8Meg
SYMBOL voltage 544 -256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 1.5m 10n 10n 4m 2)
FLAG 960 -128 0
FLAG 544 -128 0
TEXT 1064 -88 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP162-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP162-1.8.asy)
V1 IN 0 5
C1 OUT 0 1
Rload OUT 0 180
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
XU1 IN 0 N001 OUT ADP16xf K=555.6u ;pnba Vin)GND)En)Vout
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -80 96
WIRE 416 96 352 96
WIRE 512 96 416 96
WIRE -80 112 -80 96
WIRE 416 112 416 96
WIRE 512 112 512 96
WIRE -80 208 -80 192
WIRE 160 208 16 208
WIRE 416 208 416 176
WIRE 512 208 512 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
SYMBOL ADP162-1.8 256 208 R0
SYMATTR InstName U1
SYMBOL cap 400 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 180
SYMBOL voltage -80 96 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -80 208 0
FLAG 256 272 0
FLAG 416 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG -80 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m
* Z:\home\khalils\Downloads\files\data\raw_asc\254ba25cf629_square_current.asc
* Generated by LTspice 26.0.1 for Windows.
* see: HELP (F1)/LTspice/Circuit Elements/B. Arbitr...\n** Raise left hand side to power of right hand side.
V1 sin 0 SINE(0 2 1k)
R1 N001 0 1
B1 0 N001 I=v(sin)**2
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 48 256 48
WIRE 368 64 368 48
WIRE 256 96 256 48
WIRE 368 176 368 144
SYMBOL res 352 48 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage 64 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 2 1k)
SYMBOL bi2 256 96 R0
WINDOW 3 6 122 Left 0
SYMATTR InstName B1
SYMATTR Value I=v(sin)**2
FLAG 64 176 0
FLAG 64 96 sin
FLAG 256 176 0
FLAG 368 176 0
TEXT 50 254 Left 0 !.tran 10m
TEXT -256 304 Left 0 ;see: HELP (F1)/LTspice/Circuit Elements/B. Arbitr...\n**  Raise left hand side to power of right hand side.
* Z:\home\khalils\Downloads\files\data\raw_asc\2dac5c3cd1d2_cs_amp.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .tf V(Vout) V1
* .tran 5m
M2 Vout Vout Vdd Vdd PMOS l=0.36u w=6.1u
V2 Vdd 0 1.8
V1 Vin 0 SINE(0.65 1m 1k) AC 1
C1 Vout 0 1p
M1 Vout Vin 0 0 NMOS l=0.36u w=10.13u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.options plotwinsize=0
.include tsmc180.txt
.ac dec 10 10 1gig
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 16 272 -48
WIRE 352 16 272 16
WIRE 272 32 272 16
WIRE 224 48 176 48
WIRE 352 80 352 16
WIRE 352 80 272 80
WIRE 176 144 176 48
WIRE 272 144 272 128
WIRE 272 144 176 144
WIRE 272 192 272 144
WIRE 512 192 272 192
WIRE 560 192 512 192
WIRE 272 208 272 192
WIRE 512 224 512 192
WIRE 368 256 272 256
WIRE 224 288 144 288
WIRE -288 320 -288 256
WIRE -144 320 -144 256
WIRE 272 320 272 304
WIRE 368 320 368 256
WIRE 368 320 272 320
WIRE 512 320 512 288
WIRE 272 400 272 320
WIRE -288 480 -288 400
WIRE -144 480 -144 400
IOPIN 560 192 Out
SYMBOL voltage -144 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL cap 496 224 R0
SYMATTR InstName C1
SYMATTR Value 1p
SYMBOL pmos4 224 128 M180
WINDOW 123 65 4 Left 2
SYMATTR InstName M2
SYMATTR Value2 l=0.36u w=6.1u
SYMBOL nmos4 224 208 R0
WINDOW 123 62 141 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=0.36u w=10.13u
SYMBOL voltage -288 304 R0
WINDOW 3 -268 103 Left 2
WINDOW 123 -125 139 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0.65 1m 1k)
SYMATTR Value2 AC 1
FLAG 272 -48 Vdd
FLAG 560 192 Vout
FLAG 144 288 Vin
FLAG 272 400 0
FLAG 512 320 0
FLAG -288 256 Vin
FLAG -144 256 Vdd
FLAG -288 480 0
FLAG -144 480 0
TEXT -360 -80 Left 2 !.options plotwinsize=0
TEXT -360 -48 Left 2 !.include tsmc180.txt
TEXT -360 -24 Left 2 ;.op
TEXT -360 0 Left 2 ;.tf V(Vout) V1
TEXT -360 24 Left 2 ;.tran 5m
TEXT -360 48 Left 2 !.ac dec 10 10 1gig