Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\AD5423.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\DAC\AD5423.asy)
V1 0 N007 24
XU1 N001 N001 0 MP_01 MP_02 MP_03 N006 NC_04 N002 N002 MP_05 N007 N005 MP_06 N003 N004 IN AD5423 RANGE = 0, OVRNG_EN = 0, NEG_OFFSET_EN = 0 SR_EN = 0, SR_STEP = 0, SR_CLOCK = 0 VIOUT_PULLDOWN_EN = 0, HART_EN = 0 ;pnba AVDD1)AVDD2)GND))))REFOUT)CHART)VLDO)VLOGIC))AVSS)-VSENSE))+VSENSE)VIOUT)INPUT
R2 N002 0 1k
V2 N001 0 24
R4 OUT N003 1k
R1 N006 0 1k
V4 IN 0 PULSE(1 2 100u 1u 1u 1m)
R6 OUT 0 1k
R5 N004 OUT 10
R3 0 N005 1k
.tran 200u
.lib AD5423.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2016 1328
WIRE -96 -320 -96 -384
WIRE 160 -320 160 -384
WIRE -96 -160 -96 -240
WIRE 32 -160 -96 -160
WIRE 160 -160 160 -240
WIRE 272 -160 160 -160
WIRE -96 -96 -96 -160
WIRE 32 -96 32 -160
WIRE 160 -96 160 -160
WIRE 272 -96 272 -160
WIRE 528 96 464 96
WIRE 816 96 608 96
WIRE -176 224 -512 224
WIRE 576 224 528 224
WIRE 816 224 816 96
WIRE 816 224 656 224
WIRE 864 224 816 224
WIRE 816 240 816 224
WIRE -512 288 -512 224
WIRE 544 352 464 352
WIRE 816 352 816 320
WIRE 816 352 624 352
WIRE -512 432 -512 368
WIRE 816 432 816 352
WIRE 464 464 416 464
WIRE 464 528 464 464
WIRE -16 640 -16 560
WIRE 208 640 208 560
WIRE 464 656 464 608
WIRE -16 800 -16 720
SYMBOL res 640 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 800 224 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res 560 208 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10
SYMBOL voltage -96 -224 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 24
SYMBOL AD5423 80 224 R0
SYMATTR InstName U1
SYMBOL res 624 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage -16 736 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL res 448 512 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL voltage -512 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value PULSE(1 2 100u 1u 1u 1m)
SYMBOL res 144 -224 M180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 1k
FLAG 208 640 0
FLAG -16 800 0
FLAG -96 -384 0
FLAG 464 656 0
FLAG 160 -384 0
FLAG -512 432 0
FLAG 816 432 0
FLAG -512 224 IN
FLAG 864 224 OUT
TEXT 504 -64 Left 2 !.tran 200u
* Z:\home\khalils\Downloads\files\data\raw_asc\09689b9458cf_TDA8425_spatial.asc
* Generated by LTspice 26.0.1 for Windows.
Rfl Vol L- 54k
Rfr Vor R- 54k
Rc L- R- 100k
XUR R- Ri Vor opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
Vir Ri 0 3
Vil Li 0 5
XUL L- Li Vol opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
.tran 1
.lib opamp.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 0 -96 0
WIRE 160 0 0 0
WIRE -96 16 -96 0
WIRE 240 16 224 16
WIRE 304 16 240 16
WIRE 160 32 96 32
WIRE -96 112 -96 96
WIRE 96 128 96 32
WIRE 144 128 96 128
WIRE 240 128 240 16
WIRE 240 128 224 128
WIRE 96 160 96 128
WIRE 96 272 96 240
WIRE 144 272 96 272
WIRE 240 272 224 272
WIRE 96 352 96 272
WIRE 160 352 96 352
WIRE 240 368 240 272
WIRE 240 368 224 368
WIRE 304 368 240 368
WIRE 0 384 -96 384
WIRE 160 384 0 384
WIRE -96 400 -96 384
WIRE -96 496 -96 480
SYMBOL voltage -96 384 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName Vir
SYMATTR Value 3
SYMBOL res 240 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfr
SYMATTR Value 54k
SYMBOL Opamps\\opamp 192 304 R0
SYMATTR InstName UR
SYMBOL res 240 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rfl
SYMATTR Value 54k
SYMBOL voltage -96 0 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 124 Left 2
SYMATTR InstName Vil
SYMATTR Value 5
SYMBOL res 80 144 R0
SYMATTR InstName Rc
SYMATTR Value 100k
SYMBOL Opamps\\opamp 192 80 M180
SYMATTR InstName UL
FLAG -96 112 0
FLAG -96 496 0
FLAG 304 16 Vol
FLAG 304 368 Vor
FLAG 0 0 Li
FLAG 96 32 L-
FLAG 96 352 R-
FLAG 0 384 Ri
TEXT 150 480 Left 2 !.tran 1
TEXT 152 448 Left 2 !.lib opamp.sub
* Z:\home\khalils\Downloads\files\data\raw_asc\30de2612192e_3PhaseRect.asc
* Generated by LTspice 26.0.1 for Windows.
* This is a 3-Phase rectifier circuit.\nReference: Schuler, 7th edition, page 71.\nRun the simulation and probe the waveform across R1.\nLeft-click the vertical axis and change the bottom axis limit to 0 V.\nThe low ripple content of three-phase rectification is apparent.
D4 0 N003 D
D3 N003 N001 D
V1 N003 N005 SINE(0 170 60)
V2 N004 N005 SINE(0 170 60 0 0 120)
D1 N002 N001 D
D6 0 N004 D
D2 0 N002 D
D5 N004 N001 D
V3 N002 N005 SINE(0 170 60 0 0 -120)
R1 N001 0 10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 33.3333e-3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 932 680
WIRE 416 48 336 48
WIRE 496 48 416 48
WIRE 544 48 496 48
WIRE 336 64 336 48
WIRE 416 64 416 48
WIRE 496 64 496 48
WIRE 272 80 -80 80
WIRE 224 128 80 128
WIRE 544 144 544 48
WIRE 272 160 272 80
WIRE 336 160 336 128
WIRE 336 160 272 160
WIRE 224 176 224 128
WIRE 416 176 416 128
WIRE 416 176 224 176
WIRE -80 192 -80 80
WIRE 80 192 80 128
WIRE 496 192 496 128
WIRE 496 192 288 192
WIRE 336 224 336 160
WIRE 416 224 416 176
WIRE 496 224 496 192
WIRE 496 240 496 224
WIRE -80 288 -80 272
WIRE 80 288 80 272
WIRE 80 288 -80 288
WIRE 336 304 336 288
WIRE 416 304 416 288
WIRE 416 304 336 304
WIRE 496 304 496 288
WIRE 496 304 416 304
WIRE 544 304 544 224
WIRE 544 304 496 304
WIRE 544 336 544 304
WIRE 80 352 80 288
WIRE 80 464 80 432
WIRE 288 464 288 192
WIRE 288 464 80 464
SYMBOL voltage 80 176 R0
WINDOW 3 -76 -69 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 56 Left 0
SYMATTR Value SINE(0 170 60)
SYMATTR InstName V1
SYMBOL diode 352 128 R180
WINDOW 0 27 63 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D1
SYMBOL diode 432 128 R180
WINDOW 0 28 64 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D3
SYMBOL res 528 128 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL diode 512 128 R180
WINDOW 0 24 64 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D5
SYMBOL voltage 80 448 R180
WINDOW 0 36 54 Left 0
WINDOW 3 -122 -39 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value SINE(0 170 60 0 0 120)
SYMBOL diode 512 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D6
SYMBOL diode 432 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D4
SYMBOL voltage -80 176 R0
WINDOW 3 -105 139 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 57 Left 0
SYMATTR Value SINE(0 170 60 0 0 -120)
SYMATTR InstName V3
SYMBOL diode 352 288 R180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D2
FLAG 544 336 0
TEXT 344 408 Left 0 !.tran 33.3333e-3
TEXT -128 -104 Left 0 ;This is a 3-Phase rectifier circuit.\nReference: Schuler, 7th edition, page 71.\nRun the simulation and probe the waveform across R1.\nLeft-click the vertical axis and change the bottom axis limit to 0 V.\nThe low ripple content of three-phase rectification is apparent.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG782.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG782.asy)
V2 N001 0 3
C1 N002 0 36p
V1 N003 0 PULSE(0 3 25u 1n 1n 20u)
R1 N002 0 301
XU2 N003 N002 N001 0 +V ADG782 ;pnba IN)D)S)GND)Vdd
V3 +V 0 5
.tran 75u
.lib ADG782.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 16 -48 -32
WIRE -144 96 -400 96
WIRE 128 96 48 96
WIRE 256 96 128 96
WIRE -512 128 -512 80
WIRE -400 128 -400 96
WIRE 128 128 128 96
WIRE 256 128 256 96
WIRE -144 160 -288 160
WIRE -512 224 -512 208
WIRE -400 224 -400 208
WIRE 128 240 128 208
WIRE 256 240 256 192
WIRE -288 272 -288 160
WIRE -48 304 -48 272
WIRE -288 416 -288 352
SYMBOL voltage -512 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL ADG782 -48 144 R0
SYMATTR InstName U2
SYMBOL voltage -288 256 R0
WINDOW 3 24 102 Left 2
SYMATTR Value PULSE(0 3 25u 1n 1n 20u)
SYMATTR InstName V1
SYMBOL cap 240 128 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -400 112 R0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL res 112 112 R0
SYMATTR InstName R1
SYMATTR Value 301
FLAG 128 240 0
FLAG 256 240 0
FLAG -48 304 0
FLAG -288 416 0
FLAG -400 224 0
FLAG -48 -32 +V
FLAG -512 224 0
FLAG -512 80 +V
TEXT -264 392 Left 2 !.tran 75u
* Z:\home\khalils\Downloads\files\data\raw_asc\13c820cefbe1_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
* Tau=69.12n/1m=69.12uS
V1 N001 0 SINE(0 1 {Fre})
C1 N002 0 {C} Rpar=1e37
L1 N001 N002 {L} Rpar=1e37
.param Fre=1/(2*pi*sqrt(L*C))
.param L=69.12n C=19p
.tran 0 70u 0 1n
.opt reltol=1p vntol=1n abstol=1f
.opt itl4=500 chgtol=0.01f
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 304 48 112 48
WIRE 112 64 112 48
WIRE 304 144 304 128
WIRE 112 176 112 144
SYMBOL ind 288 32 R0
SYMATTR InstName L1
SYMATTR Value {L}
SYMATTR SpiceLine Rpar=1e37
SYMBOL voltage 112 48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 {Fre})
SYMBOL cap 288 144 R0
SYMATTR InstName C1
SYMATTR Value {C}
SYMATTR SpiceLine Rpar=1e37
FLAG 304 208 0
FLAG 112 176 0
TEXT 88 -8 Left 2 !.param Fre=1/(2*pi*sqrt(L*C))
TEXT 88 -48 Left 2 !.param L=69.12n C=19p
TEXT 78 232 Left 2 !.tran 0 70u 0 1n
TEXT 128 -88 Left 2 !.opt reltol=1p vntol=1n abstol=1f
TEXT 208 24 Left 2 ;Tau=69.12n/1m=69.12uS
TEXT 128 -120 Left 2 !.opt itl4=500 chgtol=0.01f
* Z:\home\khalils\Downloads\files\data\raw_asc\05ad62ca7a0e_Differential_Amplifier.asc
* Generated by LTspice 26.0.1 for Windows.
;op dec 10 0.01 10000G
;ac dec 10 0.01 1G
R3 N001 N002 545
V3 N005 0 SINE(0 50m 1k) AC -0.5 Rser=1k
M2 N002 N004 N006 N006 IRFP240
R1 N001 N007 500
V4 N004 0 0 AC 0.5 Rser=1k
M4 N007 N007 N008 N008 IRFP240
V2 N001 0 12
V1 N008 0 -12
M3 N006 N007 N008 N008 IRFP240
R2 N001 N003 545
M1 N003 N005 N006 N006 IRFP240
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -384 -352 -688 -352
WIRE 16 -352 -384 -352
WIRE 448 -352 16 -352
WIRE 16 -288 16 -352
WIRE 448 -272 448 -352
WIRE -688 -208 -688 -352
WIRE -688 -80 -688 -128
WIRE -384 -64 -384 -352
WIRE 448 -48 448 -192
WIRE 16 -32 16 -208
WIRE 640 32 496 32
WIRE -32 48 -128 48
WIRE 16 112 16 64
WIRE 288 112 16 112
WIRE 448 112 448 48
WIRE 448 112 288 112
WIRE -128 128 -128 48
WIRE 640 144 640 32
WIRE -384 208 -384 16
WIRE -288 208 -384 208
WIRE -384 240 -384 208
WIRE 288 240 288 112
WIRE 640 272 640 224
WIRE -288 320 -288 208
WIRE -288 320 -336 320
WIRE 240 320 -288 320
WIRE -384 416 -384 336
WIRE -16 416 -384 416
WIRE 288 416 288 336
WIRE 288 416 -16 416
WIRE -16 464 -16 416
WIRE -16 576 -16 544
SYMBOL voltage -128 112 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR Value2 AC -0.5
SYMATTR SpiceLine Rser=1k
SYMATTR InstName V3
SYMATTR Value SINE(0 50m 1k)
SYMBOL voltage -16 448 R0
SYMATTR InstName V1
SYMATTR Value -12
SYMBOL res -400 -80 R0
SYMATTR InstName R1
SYMATTR Value 500
SYMBOL nmos -336 240 M0
SYMATTR InstName M4
SYMATTR Value IRFP240
SYMBOL voltage 640 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 24 152 Left 2
SYMATTR Value2 AC 0.5
SYMATTR SpiceLine Rser=1k
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL nmos -32 -32 R0
SYMATTR InstName M1
SYMATTR Value IRFP240
SYMBOL res 0 -304 R0
SYMATTR InstName R2
SYMATTR Value 545
SYMBOL nmos 240 240 R0
SYMATTR InstName M3
SYMATTR Value IRFP240
SYMBOL res 432 -288 R0
SYMATTR InstName R3
SYMATTR Value 545
SYMBOL voltage -688 -224 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL nmos 496 -48 M0
SYMATTR InstName M2
SYMATTR Value IRFP240
FLAG 640 272 0
FLAG -688 -80 0
FLAG -16 576 0
FLAG -128 208 0
TEXT -600 472 Left 2 !;op dec 10 0.01 10000G
TEXT 408 184 Left 2 !.tran 10m
TEXT 416 392 Left 2 !;ac dec 10 0.01 1G
* Z:\home\khalils\Downloads\files\data\raw_asc\0797888c7ab2_atividade4-1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 N001 1000R
C1 N002 0 1.6pF
V1 N001 0 AC 100
.ac dec 1ms 80meg 180meg
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 176 -112 48 -112
WIRE 320 -112 256 -112
WIRE 48 -48 48 -112
WIRE 320 -48 320 -112
WIRE 48 160 48 32
WIRE 96 160 48 160
WIRE 320 160 320 16
WIRE 320 160 96 160
WIRE 96 176 96 160
SYMBOL cap 304 -48 R0
SYMATTR InstName C1
SYMATTR Value 1.6pF
SYMBOL res 272 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000R
SYMBOL voltage 48 -64 R0
WINDOW 123 24 44 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 100
SYMATTR InstName V1
SYMATTR Value ""
FLAG 96 176 0
TEXT 168 200 Left 2 !.ac dec 1ms 80meg 180meg
* Z:\tmp\asc_dec_bjh7r6w2\031aac2fa88b_1050A_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 0 N002 0 MAT-02
XU2 0 N003 +V -V N007 LTC1050 ;pnba In+)In-)V+)V-)OUT
R2 N001 N005 10K
B1 Exact 0 V=-Log10(V(in)/10m)
C2 N003 N007 22p
D2 0 N008 LT1009
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1050A.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1616 680
WIRE 240 0 80 0
WIRE 624 0 336 0
WIRE 704 0 624 0
WIRE 864 0 800 0
WIRE 624 16 624 0
WIRE 288 80 288 64
WIRE 752 112 752 64
WIRE 752 112 416 112
WIRE 992 128 992 112
WIRE -16 144 -224 144
WIRE 80 144 80 0
WIRE 80 144 64 144
WIRE 176 144 80 144
WIRE 272 144 240 144
WIRE 624 144 624 96
WIRE 784 144 624 144
WIRE 864 144 864 0
WIRE 864 144 848 144
WIRE 128 208 128 192
WIRE 768 208 768 192
WIRE 80 224 80 144
WIRE 96 224 80 224
WIRE 864 224 864 144
WIRE 864 224 800 224
WIRE 880 224 864 224
WIRE 992 224 992 208
WIRE 992 224 960 224
WIRE 272 240 272 144
WIRE 272 240 160 240
WIRE 304 240 272 240
WIRE 416 240 416 112
WIRE 416 240 384 240
WIRE 448 240 416 240
WIRE 624 240 624 144
WIRE 624 240 608 240
WIRE 736 240 624 240
WIRE 96 256 80 256
WIRE 816 256 800 256
WIRE 416 272 416 240
WIRE 128 288 128 272
WIRE 768 288 768 272
WIRE 992 320 992 288
WIRE 32 352 0 352
WIRE -160 368 -160 352
WIRE 0 384 0 352
WIRE 272 384 272 240
WIRE -160 480 -160 448
WIRE 0 480 0 464
SYMBOL npn 240 64 R270
WINDOW 0 39 51 VTop 0
WINDOW 3 -5 66 VRight 0
SYMATTR InstName Q1
SYMATTR Value MAT-02
SYMBOL opamps\\LTC1050A 768 176 M0
SYMATTR InstName U2
SYMBOL res 80 128 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL bv 0 368 R0
SYMATTR InstName B1
SYMATTR Value V=-Log10(V(in)/10m)
SYMBOL cap 848 128 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 22p
SYMBOL zener 976 288 M180
WINDOW 0 24 72 Left 0
WINDOW 3 24 0 Left 0
SYMATTR InstName D2
SYMATTR Value LT1009
FLAG -160 480 0
FLAG 128 192 +V
FLAG -160 352 +V
FLAG 128 288 -V
FLAG 80 256 0
FLAG 288 80 0
FLAG 768 192 +V
FLAG 768 288 -V
FLAG 816 256 0
FLAG 992 320 0
FLAG 992 112 +V
FLAG 0 480 0
FLAG 32 352 Exact
* Z:\home\khalils\Downloads\files\data\raw_asc\faa99329a21d_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T1 N001 0 0 N002 Td=50n Z0=50
T2 0 0 N002 0 Td=30n Z0=150
V1 N001 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE -368 240 -368 192
WIRE 64 272 64 224
WIRE 64 272 -16 272
WIRE 288 272 288 224
WIRE 384 272 288 272
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE -368 368 -368 320
WIRE -16 368 -16 272
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL voltage -368 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 132 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 368 0
FLAG -16 368 0
FLAG 320 192 0
TEXT 264 416 Left 2 !.tran 0 500n 0 1n
TEXT 0 440 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\2a23f10bd77d_Q4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 AC 1
R2 Vout N002 100000
R1 N002 N001 10000
C1 Vout 0 1nF
C2 N002 0 10nF
.ac dec 100 1 1000000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 64 80 64
WIRE 256 64 208 64
WIRE 336 176 336 64
WIRE 496 176 336 176
WIRE 208 192 208 64
WIRE 336 192 336 176
WIRE 208 336 208 256
WIRE 336 336 336 256
SYMBOL res 224 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10000
SYMBOL cap 320 192 R0
SYMATTR InstName C1
SYMATTR Value 1nF
SYMBOL voltage 80 48 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 352 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100000
SYMBOL cap 192 192 R0
SYMATTR InstName C2
SYMATTR Value 10nF
FLAG 80 144 0
FLAG 496 176 Vout
FLAG 208 336 0
FLAG 336 336 0
TEXT 48 -40 Left 2 !.ac dec 100 1 1000000
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1109-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1109-5.asy)
XU1 IN MP_01 N001 0 MP_02 MP_03 N002 OUT LT1109 top=250K bot=83K ;pnba Vin))SW)GND)))_SDN)Sense
D1 N001 OUT MBRS140
L1 IN N001 33 Rser=0.02 Rpar=5000
Rload OUT 0 50
C1 OUT 0 22 Rser=0.02
V1 IN 0 3 Rser=0.1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT1109.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2376 1416
WIRE 1520 944 1296 944
WIRE 1584 944 1520 944
WIRE 1696 944 1664 944
WIRE 1760 944 1696 944
WIRE 1888 944 1824 944
WIRE 2000 944 1888 944
WIRE 1296 960 1296 944
WIRE 2000 960 2000 944
WIRE 1520 1008 1520 944
WIRE 1296 1056 1296 1040
WIRE 2000 1056 2000 1040
WIRE 1696 1072 1696 944
WIRE 1696 1072 1648 1072
WIRE 1392 1104 1360 1104
WIRE 1888 1136 1888 944
WIRE 1888 1136 1648 1136
WIRE 1888 1152 1888 1136
WIRE 1888 1232 1888 1216
WIRE 1520 1248 1520 1200
SYMBOL res 1984 944 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL VOLTAGE 1296 944 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMATTR SpiceLine Rser=0.1
SYMBOL schottky 1760 960 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL POLCAP 1872 1152 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMATTR SpiceLine Rser=0.02
SYMBOL PowerProducts\\LT1109-5 1520 1088 R0
SYMATTR InstName U1
SYMBOL IND 1568 960 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 2000 944 OUT
FLAG 1888 1232 0
FLAG 2000 1056 0
FLAG 1296 1056 0
FLAG 1520 1248 0
FLAG 1296 944 IN
TEXT 1656 1264 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2985d0ecdc51_6605-7.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\FilterProducts\LTC6605-7.asy)
XU1 N001 N004 V+ N004 N006 N005 0 V- V+ N003 LTC6605-7 ;pnba IN4+)IN1+)BIAS)IN1-)IN4-)OUT+)Vocm)V-)V+)OUT-1
R1 0 N003 300
V2 V- 0 -1.5
E2 0 N006 N002 0 .5
V1 V+ 0 1.5
E1 N001 0 N002 0 .5
V3 N002 0 AC 1
E3 OUT 0 N005 N003 1
R2 0 N005 300
.ac oct 20 100k 100Meg
.measure pt1 find V(out) at 3.5Meg
.measure pt2 find V(out) at 5.25Meg
.measure pt3 find V(out) at 7Meg
.measure pt4 find V(out) at 14Meg
.measure pt5 find V(out) at 35Meg
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1756 680
WIRE -304 -32 -304 -48
WIRE -192 -32 -192 -48
WIRE 336 32 336 16
WIRE -304 64 -304 48
WIRE -192 64 -192 48
WIRE 64 64 -64 64
WIRE -64 96 -64 64
WIRE -112 112 -176 112
WIRE 512 112 480 112
WIRE 528 112 512 112
WIRE 624 112 608 112
WIRE 64 128 0 128
WIRE 736 128 672 128
WIRE 672 144 672 128
WIRE -112 160 -128 160
WIRE 480 160 480 112
WIRE 480 160 432 160
WIRE 512 160 512 112
WIRE 624 160 512 160
WIRE -64 192 -64 176
WIRE -64 192 -96 192
WIRE 64 192 48 192
WIRE -64 208 -64 192
WIRE 624 208 512 208
WIRE -176 224 -176 112
WIRE -112 224 -176 224
WIRE 480 224 432 224
WIRE 672 240 672 224
WIRE 0 256 0 128
WIRE 64 256 0 256
WIRE 480 256 480 224
WIRE 512 256 512 208
WIRE 512 256 480 256
WIRE 528 256 512 256
WIRE 624 256 608 256
WIRE -112 272 -128 272
WIRE 448 288 432 288
WIRE -176 320 -176 224
WIRE -64 320 -64 288
WIRE 64 320 -64 320
WIRE 336 368 336 352
WIRE -176 416 -176 400
SYMBOL voltage -304 -48 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V1
SYMATTR Value 1.5
SYMBOL e -64 192 R0
SYMATTR InstName E2
SYMATTR Value .5
SYMBOL LTC6605-7 256 192 R0
SYMATTR InstName U1
SYMBOL e2 672 128 R0
SYMATTR InstName E3
SYMATTR Value 1
SYMBOL res 624 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -192 -48 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value -1.5
SYMBOL e -64 80 R0
SYMATTR InstName E1
SYMATTR Value .5
SYMBOL voltage -176 304 R0
SYMATTR InstName V3
SYMATTR Value AC 1
SYMBOL res 624 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 300
FLAG -304 64 0
FLAG -192 64 0
FLAG 448 288 0
FLAG -304 -48 V+
FLAG 48 192 V+
FLAG -96 192 0
FLAG -128 160 0
FLAG -128 272 0
FLAG -176 416 0
FLAG 672 240 0
FLAG 736 128 OUT
FLAG 624 112 0
FLAG 624 256 0
FLAG 336 16 V+
FLAG 336 368 V-
FLAG -192 -48 V-
TEXT 480 480 Left 2 !.ac oct 20 100k 100Meg
TEXT 472 328 Left 2 !.measure pt1 find V(out) at 3.5Meg\n.measure pt2 find V(out) at 5.25Meg\n.measure pt3 find V(out) at 7Meg\n.measure pt4 find V(out) at 14Meg\n.measure pt5 find V(out) at 35Meg