* Z:\home\khalils\Downloads\files\data\raw_asc\1983368da4c4_AND.asc
* Generated by LTspice 26.0.1 for Windows.
* Implementation of CMOS AND Gate
V2 VDD 0 1.8
M1 VDD A N001 VDD CMOSP l=2*LAMBDA w=2*width ad=2.5*2*LAMBDA*2*width as=2.5*2*LAMBDA*2*width pd=5*2*LAMBDA+2*2*width ps=5*2*LAMBDA+2*2*width
M6 Out N001 0 0 CMOSN l=2*LAMBDA w=width ad=2.5*2*LAMBDA*width as=2.5*2*LAMBDA*width pd=5*2*LAMBDA+2*width ps=5*2*LAMBDA+2*width
M3 N001 A N002 0 CMOSN l=2*LAMBDA w=width ad=2.5*2*LAMBDA*width as=2.5*2*LAMBDA*width pd=5*2*LAMBDA+2*width ps=5*2*LAMBDA+2*width
M4 N002 B 0 0 CMOSN l=2*LAMBDA w=width ad=2.5*2*LAMBDA*width as=2.5*2*LAMBDA*width pd=5*2*LAMBDA+2*width ps=5*2*LAMBDA+2*width
V3 B 0 PULSE(0 1.8 10n 1p 1p 10n 20n)
M2 N001 B VDD VDD CMOSP l=2*LAMBDA w=2*width ad=2.5*2*LAMBDA*2*width as=2.5*2*LAMBDA*2*width pd=5*2*LAMBDA+2*2*width ps=5*2*LAMBDA+2*2*width
M5 VDD N001 Out VDD CMOSP l=2*LAMBDA w=2*width ad=2.5*2*LAMBDA*2*width as=2.5*2*LAMBDA*2*width pd=5*2*LAMBDA+2*2*width ps=5*2*LAMBDA+2*2*width
V1 A 0 PULSE(0 1.8 5n 1p 1p 5n 10n)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include TSMC_180nm.txt
.param width = 20*LAMBDA
.param LAMBDA = 0.09u
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1316 680
WIRE 128 16 -64 16
WIRE 160 16 128 16
WIRE 192 16 160 16
WIRE 528 16 192 16
WIRE 624 16 528 16
WIRE 688 16 624 16
WIRE 160 64 160 16
WIRE 160 64 80 64
WIRE 224 64 160 64
WIRE 80 80 80 64
WIRE 224 80 224 64
WIRE 528 80 528 16
WIRE 352 96 272 96
WIRE 128 128 128 16
WIRE 128 128 80 128
WIRE 192 128 192 16
WIRE 224 128 192 128
WIRE 624 128 624 16
WIRE 624 128 528 128
WIRE 32 160 -16 160
WIRE 480 160 400 160
WIRE 160 176 80 176
WIRE 224 176 160 176
WIRE 160 208 160 176
WIRE 400 208 400 160
WIRE 400 208 160 208
WIRE 528 208 528 176
WIRE 768 208 528 208
WIRE 160 224 160 208
WIRE 528 224 528 208
WIRE 304 272 160 272
WIRE 640 272 528 272
WIRE -624 304 -624 272
WIRE -512 304 -512 272
WIRE -400 304 -400 272
WIRE 112 304 48 304
WIRE 400 304 400 208
WIRE 480 304 400 304
WIRE 160 352 160 320
WIRE 224 400 160 400
WIRE -624 432 -624 384
WIRE -512 432 -512 384
WIRE -512 432 -624 432
WIRE -400 432 -400 384
WIRE -400 432 -512 432
WIRE 112 432 80 432
WIRE -512 528 -512 432
WIRE 160 528 160 448
WIRE 160 528 -64 528
WIRE 192 528 160 528
WIRE 224 528 224 400
WIRE 224 528 192 528
WIRE 304 528 304 272
WIRE 304 528 224 528
WIRE 528 528 528 320
WIRE 528 528 304 528
WIRE 640 528 640 272
WIRE 640 528 528 528
WIRE 192 576 192 528
IOPIN -16 160 In
IOPIN 48 304 In
IOPIN 80 432 In
IOPIN 352 96 In
IOPIN 768 208 Out
IOPIN -64 16 In
IOPIN -624 272 Out
IOPIN -400 272 Out
IOPIN -512 272 Out
SYMBOL pmos4 272 176 R180
SYMATTR InstName M2
SYMATTR Value CMOSP
SYMATTR Value2 l=2*LAMBDA w=2*width ad=2.5*2*LAMBDA*2*width as=2.5*2*LAMBDA*2*width pd=5*2*LAMBDA+2*2*width ps=5*2*LAMBDA+2*2*width
SYMBOL pmos4 32 80 R0
SYMATTR InstName M1
SYMATTR Value CMOSP
SYMATTR Value2 l=2*LAMBDA w=2*width ad=2.5*2*LAMBDA*2*width as=2.5*2*LAMBDA*2*width pd=5*2*LAMBDA+2*2*width ps=5*2*LAMBDA+2*2*width
SYMBOL voltage -400 288 R0
WINDOW 3 -67 126 Left 1
SYMATTR InstName V3
SYMATTR Value PULSE(0 1.8 10n 1p 1p 10n 20n)
SYMBOL voltage -512 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.8
SYMBOL nmos4 480 224 R0
SYMATTR InstName M6
SYMATTR Value CMOSN
SYMATTR Value2 l=2*LAMBDA w=width ad=2.5*2*LAMBDA*width as=2.5*2*LAMBDA*width pd=5*2*LAMBDA+2*width ps=5*2*LAMBDA+2*width
SYMBOL nmos4 112 224 R0
SYMATTR InstName M3
SYMATTR Value CMOSN
SYMATTR Value2 l=2*LAMBDA w=width ad=2.5*2*LAMBDA*width as=2.5*2*LAMBDA*width pd=5*2*LAMBDA+2*width ps=5*2*LAMBDA+2*width
SYMBOL pmos4 480 80 R0
SYMATTR InstName M5
SYMATTR Value CMOSP
SYMATTR Value2 l=2*LAMBDA w=2*width ad=2.5*2*LAMBDA*2*width as=2.5*2*LAMBDA*2*width pd=5*2*LAMBDA+2*2*width ps=5*2*LAMBDA+2*2*width
SYMBOL nmos4 112 352 R0
SYMATTR InstName M4
SYMATTR Value CMOSN
SYMATTR Value2 l=2*LAMBDA w=width ad=2.5*2*LAMBDA*width as=2.5*2*LAMBDA*width pd=5*2*LAMBDA+2*width ps=5*2*LAMBDA+2*width
SYMBOL voltage -624 288 R0
WINDOW 3 -284 92 Left 1
SYMATTR InstName V1
SYMATTR Value PULSE(0 1.8 5n 1p 1p 5n 10n)
FLAG -16 160 A
FLAG 48 304 A
FLAG 192 576 0
FLAG 80 432 B
FLAG 352 96 B
FLAG 768 208 Out
FLAG -64 16 VDD
FLAG -512 528 0
FLAG -624 272 A
FLAG -400 272 B
FLAG -512 272 VDD
TEXT 16 -96 Left 2 ;Implementation of CMOS AND Gate
TEXT 984 -200 Left 2 !.include TSMC_180nm.txt
TEXT 984 -160 Left 2 !.param width = 20*LAMBDA
TEXT 984 -112 Left 2 !.param LAMBDA = 0.09u