* Z:\home\khalils\Downloads\files\data\raw_asc\5647bf579cb2_Fig26_4.asc
* Generated by LTspice 26.0.1 for Windows.
MSU2 VDD N002 N002 VDD P_50n L=1u W=500n
MSU1 N002 Vbiasn 0 0 N_50n l=50n w=500n
MSU3 VDD N002 Vbiasn 0 N_50n L=50n W=500n
M3 VDD Vbiasp Vbiasn VDD P_50n l=50n w=1u
M4 VDD Vbiasp N003 VDD P_50n l=50n w=1u
M1 Vbiasn Vbiasn 0 0 N_50n l=50n w=500n
R1 N004 0 4k
MA4 VDD N001 Vbiasp VDD P_50n l=100n w=1u
MA3 VDD N001 N001 VDD P_50n l=100n w=1u
M5 N001 N003 0 0 N_50n l=100n w=500n
M7 VDD Vbiasp VDD VDD P_50n l=5u w=5u
M2 Vbiasp Vbiasn 0 0 N_50n l=100n w=500n
M6 N003 N003 N004 0 N_50n l=50n w=2u
VDD VDD 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* start-up ckt
* Plot Id(M6) and then Vbiasp and Vbiasn
.DC VDD 0 1.2 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1996 680
WIRE 544 -176 544 -272
WIRE 544 -64 544 -80
WIRE 544 80 544 -64
WIRE 544 176 544 160
WIRE 544 272 544 176
WIRE 608 -96 592 -96
WIRE 608 -64 544 -64
WIRE 608 -64 608 -96
WIRE 640 -64 608 -64
WIRE 688 -144 688 -176
WIRE 688 -48 688 -64
WIRE 688 160 592 160
WIRE 688 160 688 -48
WIRE 816 -304 816 -320
WIRE 816 -192 816 -224
WIRE 848 160 688 160
WIRE 848 160 848 -48
WIRE 1008 -48 848 -48
WIRE 1008 -48 1008 -80
WIRE 1008 48 1008 -48
WIRE 1008 64 1008 48
WIRE 1008 80 1008 64
WIRE 1008 160 1008 144
WIRE 1008 192 1008 160
WIRE 1072 64 1008 64
WIRE 1072 144 1056 144
WIRE 1072 144 1072 64
WIRE 1216 -112 1216 -128
WIRE 1216 64 1216 -112
WIRE 1216 80 1216 64
WIRE 1216 160 1216 144
WIRE 1216 192 1216 160
WIRE 1264 -112 1216 -112
WIRE 1264 -112 1264 -144
WIRE 1280 144 1264 144
WIRE 1280 144 1280 16
WIRE 1328 48 1008 48
WIRE 1328 144 1328 48
WIRE 1344 -144 1264 -144
WIRE 1344 144 1328 144
WIRE 1392 -128 1392 -144
WIRE 1392 -96 1056 -96
WIRE 1392 -96 1392 -128
WIRE 1392 64 1392 -96
WIRE 1392 80 1392 64
WIRE 1392 160 1392 144
WIRE 1392 192 1392 160
WIRE 1504 -96 1392 -96
WIRE 1504 -64 1504 -96
WIRE 1520 144 1520 64
WIRE 1536 -96 1504 -96
WIRE 1536 144 1520 144
WIRE 1584 -80 1584 -96
WIRE 1584 16 1280 16
WIRE 1584 16 1584 -80
WIRE 1584 64 1520 64
WIRE 1584 64 1584 16
WIRE 1584 160 1584 144
WIRE 1584 176 1584 160
WIRE 1584 288 1584 256
WIRE 1824 -64 1504 -64
WIRE 1824 -64 1824 -128
WIRE 1840 -176 1824 -176
WIRE 1856 -64 1824 -64
WIRE 1856 48 1328 48
FLAG 544 -128 VDD
FLAG 688 -176 VDD
FLAG 1008 -128 VDD
FLAG 1008 -176 VDD
FLAG 1584 -128 VDD
FLAG 1584 -176 VDD
FLAG 1584 288 0
FLAG 1584 112 0
FLAG 1392 -176 VDD
FLAG 1392 -224 VDD
FLAG 1216 -176 VDD
FLAG 1216 -224 VDD
FLAG 1392 112 0
FLAG 1792 -176 VDD
FLAG 1744 -176 VDD
FLAG 1840 -176 VDD
FLAG 544 -272 VDD
IOPIN 544 -272 In
FLAG 544 272 GND
IOPIN 544 272 In
FLAG 688 -96 0
FLAG 544 128 0
FLAG 1008 192 0
FLAG 1008 112 0
FLAG 1216 112 0
FLAG 1216 192 0
FLAG 1392 192 0
FLAG 1856 -64 Vbiasp
IOPIN 1856 -64 Out
FLAG 1856 48 Vbiasn
IOPIN 1856 48 Out
FLAG 816 -192 0
FLAG 816 -320 VDD
SYMBOL pmos4 592 -176 M0
WINDOW 0 63 16 Left 0
WINDOW 123 56 100 Left 0
SYMATTR InstName MSU2
SYMATTR Value2 L=1u W=500n
SYMATTR Value P_50n
SYMBOL nmos4 592 80 M0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=50n w=500n
SYMATTR InstName MSU1
SYMATTR Value N_50n
SYMBOL nmos4 640 -144 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 L=50n W=500n
SYMATTR InstName MSU3
SYMATTR Value N_50n
SYMBOL pmos4 1056 -176 M0
WINDOW 0 63 16 Left 0
WINDOW 123 56 100 Left 0
SYMATTR InstName M3
SYMATTR Value2 l=50n w=1u
SYMATTR Value P_50n
SYMBOL pmos4 1536 -176 R0
WINDOW 0 63 16 Left 0
WINDOW 123 56 100 Left 0
SYMATTR InstName M4
SYMATTR Value2 l=50n w=1u
SYMATTR Value P_50n
SYMBOL nmos4 1056 64 M0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=50n w=500n
SYMATTR InstName M1
SYMATTR Value N_50n
SYMBOL res 1568 160 R0
SYMATTR InstName R1
SYMATTR Value 4k
SYMBOL pmos4 1344 -224 R0
WINDOW 0 63 16 Left 0
WINDOW 123 56 100 Left 0
SYMATTR InstName MA4
SYMATTR Value2 l=100n w=1u
SYMATTR Value P_50n
SYMBOL pmos4 1264 -224 M0
WINDOW 0 63 16 Left 0
WINDOW 123 56 100 Left 0
SYMATTR InstName MA3
SYMATTR Value2 l=100n w=1u
SYMATTR Value P_50n
SYMBOL nmos4 1264 64 M0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=100n w=500n
SYMATTR InstName M5
SYMATTR Value N_50n
SYMBOL pmos4 1744 -128 R270
WINDOW 0 63 16 Left 0
WINDOW 123 56 100 Left 0
SYMATTR InstName M7
SYMATTR Value2 l=5u w=5u
SYMATTR Value P_50n
SYMBOL nmos4 1344 64 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=100n w=500n
SYMATTR InstName M2
SYMATTR Value N_50n
SYMBOL nmos4 1536 64 R0
WINDOW 123 56 100 Left 0
SYMATTR Value2 l=50n w=2u
SYMATTR InstName M6
SYMATTR Value N_50n
SYMBOL voltage 816 -320 R0
WINDOW 0 40 56 Left 0
WINDOW 3 40 84 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 5
TEXT 552 48 Left 0 ;start-up ckt
TEXT 952 -328 Left 0 ;Plot Id(M6) and then Vbiasp and Vbiasn
TEXT 760 248 Left 0 !.DC VDD 0 1.2 1m
TEXT 760 272 Left 0 !.lib cmosedu_models.txt