* Z:\home\khalils\Downloads\files\data\raw_asc\14c8707c4203_Draft25.asc
* Generated by LTspice 26.0.1 for Windows.
* Ok. For low gain c1 > c2.\nhere is 10x stable, with op\n- resistor TC does not matter for inner stage. it just aids gain.\n- so use a couple of different switchable pairs.\n- it is the no gain case that is hardest to stabilize.\n----\n- so this is stable with very low gain. and just c3 bypass.\n- I don't see a need for caps on the output resistors.
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP27.asy)
;dc V1 0 10 0.01
C4 0 N003 5p
XU2 N002 N003 VCC VEE VOUT OP27 ;pnba In+)In-)V+)V-)OUT
XU1 N004 N001 VCC VEE N002 OP27 ;pnba In+)In-)V+)V-)OUT
R3 N003 VOUT 4.5k
C2 N003 VOUT 50p
C5 N001 N002 20p
R2 N001 VOUT 4.7k
V3 0 VEE 15
V2 VCC 0 15
C3 0 N001 5p
C1 N001 VOUT 20p
VIN N004 0 SINE(0 0.1 50)
.tran 0.1
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1904 680
WIRE 384 -48 352 -48
WIRE 496 -48 448 -48
WIRE -64 32 -144 32
WIRE -144 48 -144 32
WIRE -64 48 -64 32
WIRE 624 64 560 64
WIRE 352 80 352 -48
WIRE 352 80 320 80
WIRE 384 80 352 80
WIRE 832 80 688 80
WIRE 928 80 832 80
WIRE 1184 80 928 80
WIRE 1296 80 1184 80
WIRE 1408 80 1296 80
WIRE 496 96 496 -48
WIRE 496 96 448 96
WIRE 624 96 496 96
WIRE 384 112 48 112
WIRE 48 128 48 112
WIRE 560 160 560 64
WIRE 720 160 560 160
WIRE 832 160 720 160
WIRE 928 160 928 144
WIRE 928 160 832 160
WIRE 1296 160 1296 144
WIRE 1296 160 1184 160
WIRE 320 272 320 80
WIRE 1184 272 1184 160
WIRE 1184 272 320 272
WIRE 1296 272 1184 272
SYMBOL cap 736 224 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C4
SYMATTR Value 5p
SYMBOL res 848 176 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R3
SYMATTR Value 4.5k
SYMBOL cap 944 144 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C2
SYMATTR Value 50p
SYMBOL OpAmps\\OP27 416 32 R0
SYMATTR InstName U1
SYMBOL voltage 48 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 2
SYMATTR Value SINE(0 0.1 50)
SYMATTR InstName VIN
SYMBOL cap 384 -32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C5
SYMATTR Value 20p
SYMBOL res 1200 176 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 4.7k
SYMBOL voltage -144 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 36 39 Left 2
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL cap 1312 336 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value 5p
SYMBOL OpAmps\\OP27 656 16 R0
SYMATTR InstName U2
SYMBOL voltage -144 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 38 43 Left 2
SYMATTR Value 15
SYMATTR InstName V2
SYMBOL cap 1312 144 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 20p
FLAG 48 208 0
FLAG -64 48 0
FLAG -144 -48 VCC
FLAG 416 64 VCC
FLAG -144 128 VEE
FLAG 416 128 VEE
FLAG 1408 80 VOUT
FLAG 656 48 VCC
FLAG 656 112 VEE
FLAG 832 240 0
FLAG 1184 352 0
FLAG 720 224 0
FLAG 1296 336 0
TEXT -72 264 Left 2 !;dc V1 0 10 0.01
TEXT 136 320 Left 2 !.tran 0.1
TEXT 1008 -272 Left 2 ;Ok. For low gain c1 > c2.\nhere is 10x stable, with op\n- resistor TC does not matter for inner stage. it just aids gain.\n- so use a couple of different switchable pairs.\n- it is the no gain case that is hardest to stabilize.\n----\n- so this is stable with very low gain. and just c3 bypass.\n- I don't see a need for caps on the output resistors.