* Z:\home\khalils\Downloads\files\data\raw_asc\23a7d221a7e3_ft_mos.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot fT versus Ids for constant Vgs\nfT=gm/(2*pi*(Cgs+Cgd))\nTherefore plot Id(M1)/I(V1)*1e7\n \nThe gate current at the test\nfrequency should be much larger\nthan the resistive leakage current.\nThats why the choosen test \nfrequency is so high(10MHz).
* Igate = 1V/(1/2*pi*f*C) = 1V*2*pi*f*C\nC=Igate/1V/(2*pi*f)\nFt=gm/(2*pi*C)\nFt=gm/(2*pi*Igate/1V/(2*pi*f))\nFt=gm*1V*f/Igate\n \n.AC simulation at 10MHz freq << ft\n \nFt=1V*Id*f/Ig*1e7
* .ac dec 10 1k 1e8
I1 s 0 {I1}
VDS D1 0 2
E1 N001 0 0 1 10000
C1 1 0 1
R1 1 s 1k
M1 D1 g s 0 N_50n l=100n w=2.5u
C2 s 0 1
V1 g N001 0 AC 1
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.step I1 .01m 1m .01m
.ac list 1e7
.op
.ic V(1)=0
.savebias abc.bias
.param I1=0.25m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1828 792
WIRE 544 -240 320 -240
WIRE 320 -208 320 -240
WIRE 544 -208 544 -240
WIRE 368 -160 320 -160
WIRE 96 -128 16 -128
WIRE 272 -128 96 -128
WIRE 16 -112 16 -128
WIRE 544 -96 544 -128
WIRE 160 -48 112 -48
WIRE 192 -48 160 -48
WIRE 304 -48 272 -48
WIRE 320 -48 320 -112
WIRE 320 -48 304 -48
WIRE 432 -48 320 -48
WIRE 432 0 432 -48
WIRE 16 16 16 -32
WIRE 160 16 160 -48
WIRE 320 16 320 -48
WIRE 80 32 64 32
WIRE 112 80 112 -48
WIRE 112 80 64 80
WIRE 16 112 16 96
WIRE 80 112 80 32
WIRE 80 112 16 112
WIRE 160 112 160 80
WIRE 160 112 80 112
WIRE 160 128 160 112
WIRE 320 128 320 96
WIRE 432 128 432 64
SYMBOL voltage 544 -224 R0
WINDOW 0 41 55 Left 0
WINDOW 3 41 83 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDS
SYMATTR Value 2
SYMBOL current 320 16 R0
SYMATTR InstName I1
SYMATTR Value {I1}
SYMBOL e 16 0 M0
SYMATTR InstName E1
SYMATTR Value 10000
SYMBOL voltage 16 -128 R0
WINDOW 3 24 93 Left 0
WINDOW 123 18 119 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMBOL res 176 -32 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 144 16 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 416 0 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL nmos4 272 -208 R0
WINDOW 0 59 18 Left 0
WINDOW 3 62 96 Left 0
WINDOW 123 59 127 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=100n w=2.5u
FLAG 544 -96 0
FLAG 368 -160 0
FLAG 320 128 0
FLAG 320 -240 D1
FLAG 160 128 0
FLAG 112 -48 1
FLAG 96 -128 g
FLAG 304 -48 s
FLAG 432 128 0
TEXT 0 -440 Left 0 !.lib cmosedu_models.txt
TEXT 0 -720 Left 0 ;Plot fT versus Ids for constant Vgs\nfT=gm/(2*pi*(Cgs+Cgd))\nTherefore plot Id(M1)/I(V1)*1e7\n \nThe gate current at the test\nfrequency should be much larger\nthan the resistive leakage current.\nThats why the choosen test \nfrequency is so high(10MHz).
TEXT 0 -336 Left 0 !.step I1 .01m 1m .01m
TEXT 0 -368 Left 0 !.ac list 1e7
TEXT 0 -400 Left 0 !.op
TEXT 0 -288 Left 0 !.ic V(1)=0
TEXT 640 -304 Left 0 !.savebias abc.bias
TEXT 440 -536 Left 0 ;Igate = 1V/(1/2*pi*f*C)  = 1V*2*pi*f*C\nC=Igate/1V/(2*pi*f)\nFt=gm/(2*pi*C)\nFt=gm/(2*pi*Igate/1V/(2*pi*f))\nFt=gm*1V*f/Igate\n \n.AC simulation at 10MHz  freq << ft\n \nFt=1V*Id*f/Ig*1e7
TEXT 0 -248 Left 0 !.param I1=0.25m
TEXT 168 -368 Left 0 ;.ac dec 10 1k 1e8