Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\0a17b2107930_Fig28_5a.asc
* Generated by LTspice 26.0.1 for Windows.
* Sample-and-Hold, S/H
A1 Vin 0 clock 0 0 0 Vout 0 SAMPLEHOLD REF=0.5
Vclock clock 0 PULSE(0 1 0 0 0 4.9n 10n)
Vin Vin 0 SINE(0.5 0.5 4MEG)
.tran 500n uic
.options plotwinsize=0
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1344 696
WIRE 384 208 320 208
WIRE 736 208 384 208
WIRE 736 240 672 240
WIRE 992 256 912 256
WIRE 320 272 320 208
WIRE 736 272 608 272
WIRE 608 336 608 272
WIRE 320 416 320 352
WIRE 608 480 608 416
SYMBOL SpecialFunctions\\sample 816 240 R0
WINDOW 3 -28 112 Left 0
SYMATTR Value REF=0.5
SYMATTR InstName A1
SYMBOL voltage 320 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value SINE(0.5 0.5 4MEG)
SYMBOL voltage 608 320 R0
WINDOW 0 36 42 Left 0
WINDOW 3 35 69 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vclock
SYMATTR Value PULSE(0 1 0 0 0 4.9n 10n)
FLAG 320 416 0
FLAG 384 208 Vin
FLAG 608 480 0
FLAG 608 272 clock
FLAG 992 256 Vout
FLAG 672 240 0
TEXT 920 144 Left 0 !.tran 500n uic
TEXT 920 176 Left 0 !.options plotwinsize=0
TEXT 848 432 Left 0 ;Sample-and-Hold, S/H
* Z:\home\khalils\Downloads\files\data\raw_asc\03e42dc53998_Out_Rect.asc
* Generated by LTspice 26.0.1 for Windows.
* V=.6366*{vpeak-2*vf}-.4244*{vpeak-2*vf}*cos (628.31853*time)
D4 N002 Vrect MURS120
D2 0 N002 MURS120
D1 0 N001 MURS120
Vac N001 N002 SINE(0 {vpeak} 50)
D3 N001 Vrect MURS120
B1 Vb 0 V=.6*{vpeak-2*vf}-.4244*{vpeak-2*vf}*cos (628.31853*time)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
.param vpeak 100
.param vf 0.7
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 916 680
WIRE -224 64 -320 64
WIRE -192 64 -224 64
WIRE -112 64 -128 64
WIRE -320 96 -320 64
WIRE 160 96 112 96
WIRE 112 112 112 96
WIRE -224 128 -224 64
WIRE -192 128 -224 128
WIRE -96 128 -128 128
WIRE -80 128 -96 128
WIRE -192 208 -224 208
WIRE -112 208 -112 64
WIRE -112 208 -128 208
WIRE 112 208 112 192
WIRE 112 208 -112 208
WIRE -320 272 -320 176
WIRE -224 272 -224 208
WIRE -224 272 -320 272
WIRE -192 272 -224 272
WIRE -96 272 -96 128
WIRE -96 272 -128 272
WIRE 112 272 112 208
SYMBOL diode -128 192 R90
WINDOW 0 16 69 VBottom 0
WINDOW 3 32 32 Invisible 0
SYMATTR InstName D2
SYMATTR Value MURS120
SYMBOL voltage -320 80 R0
WINDOW 0 7 9 Left 0
WINDOW 3 69 -18 VRight 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vac
SYMATTR Value SINE(0 {vpeak} 50)
SYMBOL diode -192 256 M90
WINDOW 0 16 -6 VBottom 0
WINDOW 3 32 32 Invisible 0
SYMATTR InstName D4
SYMATTR Value MURS120
SYMBOL diode -128 48 R90
WINDOW 0 17 73 VBottom 0
WINDOW 3 32 32 Invisible 0
SYMATTR InstName D1
SYMATTR Value MURS120
SYMBOL bv 112 96 R0
WINDOW 3 34 41 Left 0
SYMATTR InstName B1
SYMATTR Value V=.6*{vpeak-2*vf}-.4244*{vpeak-2*vf}*cos (628.31853*time)
SYMBOL diode -192 112 M90
WINDOW 0 16 -9 VBottom 0
WINDOW 3 32 32 Invisible 0
SYMATTR InstName D3
SYMATTR Value MURS120
FLAG 112 272 0
FLAG -80 128 Vrect
FLAG 160 96 Vb
TEXT 136 216 Left 0 !.tran 1
TEXT 136 248 Left 0 !.param vpeak 100\n.param vf 0.7
TEXT 104 64 Left 0 ;V=.6366*{vpeak-2*vf}-.4244*{vpeak-2*vf}*cos (628.31853*time)
* Z:\home\khalils\Downloads\files\data\raw_asc\5e498846c672_Fig9_24_nmos.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Id(M1) and 1/d(Id(m1)) (to get ro)
VDS N001 0 0
VGS N002 0 1.05
M1 N001 N002 0 0 N_1u l=2u w=10u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc VDS 0 5
.include cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 640 80 448 80
WIRE 448 112 448 80
WIRE 640 112 640 80
WIRE 496 160 448 160
WIRE 400 192 288 192
WIRE 288 208 288 192
WIRE 448 224 448 208
WIRE 640 224 640 192
WIRE 288 304 288 288
SYMBOL voltage 640 96 R0
WINDOW 0 40 56 Left 0
WINDOW 3 24 104 Invisible 0
SYMATTR InstName VDS
SYMATTR Value 0
SYMBOL nmos4 400 112 R0
WINDOW 0 59 18 Left 0
WINDOW 3 64 75 Left 0
WINDOW 123 64 103 Left 0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=2u w=10u
SYMBOL voltage 288 192 R0
WINDOW 0 -85 56 Left 0
WINDOW 3 -85 84 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS
SYMATTR Value 1.05
FLAG 288 304 0
FLAG 448 224 0
FLAG 640 224 0
FLAG 496 160 0
TEXT 392 280 Left 0 !.dc VDS 0 5
TEXT 392 304 Left 0 !.include cmosedu_models.txt
TEXT 416 48 Left 0 ;Plot Id(M1) and 1/d(Id(m1)) (to get ro)
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3631-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3631-3.3.asy)
V1 IN 0 36
L1 N001 OUT 100
C1 OUT 0 10
XU1 N001 IN NC_01 NC_02 IN OUT NC_03 0 LTC3631-3.3 ;pnba SW)Vin)Iset)SS)Run)OUT)Hyst)GND
Rload OUT 0 33
.tran 1.5m startup
.lib LTC3631-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 96 80 0 80
WIRE 112 80 96 80
WIRE 352 80 336 80
WIRE 448 80 432 80
WIRE 512 80 448 80
WIRE 592 80 512 80
WIRE 0 96 0 80
WIRE 512 96 512 80
WIRE 592 96 592 80
WIRE 96 176 96 80
WIRE 112 176 96 176
WIRE 448 176 448 80
WIRE 448 176 336 176
WIRE 0 192 0 176
WIRE 512 192 512 160
WIRE 592 192 592 176
WIRE 352 368 336 368
SYMBOL res 576 80 R0
SYMATTR InstName Rload
SYMATTR Value 33
SYMBOL voltage 0 80 R0
SYMATTR InstName V1
SYMATTR Value 36
SYMBOL PowerProducts\\LTC3631-3.3 224 224 R0
SYMATTR InstName U1
SYMBOL ind 336 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL cap 496 96 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 0 192 0
FLAG 352 368 0
FLAG 512 192 0
FLAG 592 192 0
FLAG 0 80 IN
FLAG 592 80 OUT
TEXT 448 360 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\45f4ef473f35_transistor_Vce_Vbe_and_Vce_Ic_curves.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 Vce Vbe 0 0 2N3904
B1 0 Vbe I={Ib}
V1 Vce 0 20
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc V1 0 20 0.01
* Show \n1. Vce vs Vbe\n2. Vce vs Ic\nfor a set of fixed Ib\nLook at the gain with Ic(Q1)/Ib(Q1)
.step param Ib 10u 150u 10u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 384 -32 192 -32
WIRE 384 128 384 -32
WIRE 192 144 192 -32
WIRE 0 192 -48 192
WIRE 80 192 80 96
WIRE 128 192 80 192
WIRE -48 304 -48 192
WIRE 192 304 192 240
WIRE 384 304 384 208
FLAG -48 304 0
FLAG 192 304 0
FLAG 384 304 0
FLAG 80 96 Vbe
IOPIN 80 96 BiDir
FLAG 384 -32 Vce
IOPIN 384 -32 BiDir
SYMBOL npn 128 144 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL bi 0 192 R270
WINDOW 0 32 40 VTop 2
WINDOW 3 -32 40 VBottom 2
SYMATTR InstName B1
SYMATTR Value I={Ib}
SYMBOL voltage 384 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 20
TEXT -72 328 Left 2 !.dc V1 0 20 0.01
TEXT -456 -96 Left 2 ;Show \n1. Vce vs Vbe\n2. Vce vs Ic\nfor a set of fixed Ib\nLook at the gain with Ic(Q1)/Ib(Q1)
TEXT 144 -80 Left 2 !.step param Ib 10u 150u 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\27eaeb3aefff_Diode-trr-4.asc
* Generated by LTspice 26.0.1 for Windows.
V1 a 0 PULSE(-200 200 1u 5n 5n 3u 20u) Rser=10
R1 b 0 150
D1 a b RRE07VSM6S
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 128 -208 128
WIRE -112 128 -176 128
WIRE 16 128 -48 128
WIRE 32 128 16 128
WIRE -208 176 -208 128
WIRE 32 176 32 128
WIRE -208 304 -208 256
WIRE -80 304 -208 304
WIRE 32 304 32 256
WIRE 32 304 -80 304
WIRE -80 320 -80 304
SYMBOL Misc\\EuropeanResistor 16 160 R0
SYMATTR InstName R1
SYMATTR Value 150
SYMBOL diode -112 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RRE07VSM6S
SYMBOL voltage -208 160 R0
WINDOW 3 10 105 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 0 -71 54 Left 2
SYMATTR Value PULSE(-200 200 1u 5n 5n 3u 20u)
SYMATTR InstName V1
SYMATTR SpiceLine Rser=10
FLAG -80 320 0
FLAG -176 128 a
FLAG 16 128 b
TEXT -208 320 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\44bdf5d38c73_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
M1 N001 N002 N003 N001 PMOS l=90nm w=405nm
M2 N003 N002 0 0 NMOS l=90nm w=135nm
Vin N002 0 1.2
V2 N001 0 1.2
C1 N003 0 50f V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016" type="Tantalum"
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* .tran 100s
.dc Vin 0 1.2 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 16 160 16
WIRE 400 16 240 16
WIRE 400 32 400 16
WIRE 240 64 240 16
WIRE 240 64 160 64
WIRE 80 96 -32 96
WIRE 112 96 80 96
WIRE -32 160 -32 96
WIRE 160 192 160 112
WIRE 384 192 160 192
WIRE 464 192 384 192
WIRE 160 224 160 192
WIRE 384 224 384 192
WIRE 240 272 160 272
WIRE 80 304 80 96
WIRE 112 304 80 304
WIRE 240 304 240 272
WIRE 384 304 384 288
FLAG 160 320 0
FLAG 240 304 0
FLAG -32 240 0
FLAG 400 112 0
FLAG 384 304 0
SYMBOL pmos4 112 16 R0
SYMATTR InstName M1
SYMATTR Value2 l=90nm w=405nm
SYMBOL nmos4 112 224 R0
SYMATTR InstName M2
SYMATTR Value2 l=90nm w=135nm
SYMBOL voltage -32 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value 1.2
SYMBOL voltage 400 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1.2
SYMBOL polcap 368 224 R0
WINDOW 3 24 56 Left 2
SYMATTR InstName C1
SYMATTR Value 50f
SYMATTR Description Capacitor
SYMATTR Type cap
SYMATTR SpiceLine V=16 Irms=0 Rser=11 Lser=0 mfg="AVX" pn="TAJA105K016" type="Tantalum"
TEXT -64 344 Left 2 ;.tran 100s
TEXT -120 304 Left 2 !.dc Vin 0 1.2 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\1be959ee3a0c_fra_eg1.asc
* Generated by LTspice 26.0.1 for Windows.
* .ac oct 4 100 10Meg
* This example shows the basic principle of extracting\nthe small signal AC characteristics from an \nLTspice Frequency Response Analysis (FRA) simulation.
* To use this technique in your own simulations,\n include an fra device and the .fra directive.\nThe fra device controls the frequency analysis parameters.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
@1 A B delay=100u fstart=100 fend=10Meg oct=4 fcoarse=10k nmax=50k 3 500k 1 pp0=100m pp1=10m f0=50k f1=500k tavgmin=100u tsettle=2u acmag=1
XU1 0 N001 +V -V A level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -5
R2 N001 0 1K
C2 N001 0 100p
R1 B N001 10K
V1 +V 0 5
C1 A 0 50n
.fra
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 4156 1252
WIRE 1504 544 1472 544
WIRE 1600 544 1584 544
WIRE 1632 544 1600 544
WIRE 1744 544 1712 544
WIRE 1760 544 1744 544
WIRE 1840 544 1824 544
WIRE 1856 544 1840 544
WIRE 1936 576 1936 560
WIRE 2032 576 2032 560
WIRE 1600 640 1600 544
WIRE 1760 640 1600 640
WIRE 1600 656 1600 640
WIRE 1856 656 1856 544
WIRE 1856 656 1824 656
WIRE 1760 672 1744 672
WIRE 1936 672 1936 656
WIRE 2032 672 2032 656
WIRE 1600 736 1600 720
WIRE 1856 736 1856 720
LINE Normal 1680 672 1680 672 2
LINE Normal 1680 672 1680 672 2
LINE Normal 2128 752 2128 752 2
LINE Normal 2128 752 2128 752 2
LINE Normal 2128 752 2128 752 2
LINE Normal 2128 752 2128 752 2
LINE Normal 1712 464 1760 512 2
LINE Normal 1648 656 1648 656 2
SYMBOL voltage 2032 560 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 1936 560 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 1728 528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL fra 1760 544 R90
WINDOW 0 -19 -26 VBottom 2
WINDOW 40 37 -28 VBottom 2
SYMATTR InstName @1
SYMATTR SpiceLine delay=100u fstart=100 fend=10Meg oct=4 fcoarse=10k nmax=50k 3 500k 1 pp0=100m pp1=10m f0=50k f1=500k tavgmin=100u tsettle=2u
SYMATTR SpiceLine2 acmag=1
SYMBOL res 1600 528 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL cap 1584 656 R0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL cap 1840 656 R0
SYMATTR InstName C1
SYMATTR Value 50n
SYMBOL Opamps\\UniversalOpamp2 1792 656 R0
SYMATTR InstName U1
FLAG 1936 672 0
FLAG 2032 672 0
FLAG 1936 560 +V
FLAG 1792 624 +V
FLAG 2032 560 -V
FLAG 1792 688 -V
FLAG 1744 672 0
FLAG 1472 544 0
FLAG 1856 736 0
FLAG 1600 736 0
FLAG 1840 544 A
FLAG 1744 544 B
TEXT 2200 560 Left 2 !.fra
TEXT 2112 592 Left 2 ;.ac oct 4 100 10Meg
TEXT 1888 288 Center 2 ;This example shows the basic principle of extracting\nthe small signal AC characteristics from an \nLTspice Frequency Response Analysis (FRA) simulation.
TEXT 1576 392 Left 2 ;To use this technique in your own simulations,\n include an fra device and the .fra directive.\nThe fra device controls the frequency analysis parameters.
* Z:\home\khalils\Downloads\files\data\raw_asc\47f00b150a0d_ADR5044.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\ADR5044.asy)
Vin IN 0 4.5
XU1 OUT 0 ADR5044 ;pnba 1)2
Rload OUT 0 10k
Rbias IN OUT 715
.dc TEMP -40 125 .1
.lib ADR5044.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 960
WIRE 32 64 -80 64
WIRE 208 64 112 64
WIRE 464 64 208 64
WIRE -80 112 -80 64
WIRE 208 112 208 64
WIRE 464 112 464 64
WIRE -80 224 -80 192
WIRE 208 224 208 176
WIRE 208 224 -80 224
WIRE 464 224 464 192
WIRE 464 224 208 224
WIRE -80 256 -80 224
SYMBOL res 448 96 R0
SYMATTR InstName Rload
SYMATTR Value 10k
SYMBOL voltage -80 96 R0
WINDOW 3 36 62 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 30 32 Left 2
SYMATTR Value 4.5
SYMATTR InstName Vin
SYMBOL ADR5044 208 144 R0
SYMATTR InstName U1
SYMBOL res 16 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName Rbias
SYMATTR Value 715
FLAG -80 64 IN
FLAG -80 256 0
FLAG 464 64 OUT
TEXT -88 -32 Left 2 !.dc TEMP -40 125 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1170HV.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1170HV.asy)
XU1 N003 N002 0 N001 IN LT1170 ;pnba Vc)FB)GND)SW)Vin
D1 N001 OUT MBRS360
R3 OUT N002 10.7K
C2 OUT 0 500 Rser=0.05
L1 IN N001 150 Rser=0.02 Rpar=5000
C1 N004 0 1
R1 N003 N004 1K
V1 IN 0 5
Rload OUT 0 12
R2 N002 0 1.24K
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 15m startup
.lib LT1170.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 896 1616 896
WIRE 1888 896 1824 896
WIRE 2048 896 1968 896
WIRE 2096 896 2048 896
WIRE 2224 896 2160 896
WIRE 2352 896 2224 896
WIRE 2464 896 2352 896
WIRE 1616 912 1616 896
WIRE 2352 912 2352 896
WIRE 2464 912 2464 896
WIRE 1824 944 1824 896
WIRE 2224 960 2224 896
WIRE 1616 1008 1616 992
WIRE 2352 1008 2352 976
WIRE 2464 1008 2464 992
WIRE 2048 1024 2048 896
WIRE 2048 1024 1952 1024
WIRE 2224 1088 2224 1040
WIRE 2224 1088 1952 1088
WIRE 2224 1104 2224 1088
WIRE 1968 1152 1952 1152
WIRE 2064 1152 2048 1152
WIRE 2064 1168 2064 1152
WIRE 2224 1200 2224 1184
WIRE 1824 1248 1824 1232
WIRE 2064 1248 2064 1232
SYMBOL schottky 2096 912 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS360
SYMBOL polcap 2336 912 R0
SYMATTR InstName C2
SYMATTR Value 500
SYMATTR SpiceLine Rser=0.05
SYMBOL RES 2208 944 R0
SYMATTR InstName R3
SYMATTR Value 10.7K
SYMBOL CAP 2048 1168 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL RES 1952 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL VOLTAGE 1616 896 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL RES 2448 896 R0
SYMATTR InstName Rload
SYMATTR Value 12
SYMBOL PowerProducts\\LT1170HV 1824 1088 R0
SYMATTR InstName U1
SYMBOL RES 2208 1088 R0
SYMATTR InstName R2
SYMATTR Value 1.24K
SYMBOL IND 1872 912 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 150
SYMATTR SpiceLine Rser=0.02 Rpar=5000
FLAG 1616 1008 0
FLAG 1824 1248 0
FLAG 2064 1248 0
FLAG 2464 1008 0
FLAG 2352 1008 0
FLAG 2224 1200 0
FLAG 2464 896 OUT
FLAG 1616 896 IN
TEXT 2152 1248 Left 2 !.tran 15m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\423912f8be62_MRF9411_DC.asc
* Generated by LTspice 26.0.1 for Windows.
*Low Noise, High-Frequency Transistor
*MOT Si 250mW 10V 50mA 8GHz
+ IS = 4.558E-16
+ BF = 136
+ NF = 0.9979
+ VAF = 21
+ IKF = 0.7
+ ISE = 3.087E-14
+ NE = 2
+ BR = 42
+ NR = 0.993
+ VAR = 2.9
+ IKR = 0.016
+ ISC = 3.411E-17
+ NC = 1.087
+ RB = 7
+ IRB = 8E-05
+ RBM = 8
+ RE = 0.45
+ RC = 8
+ XTB = 0
+ EG = 1.11
+ XTI = 3
+ CJE = 8.6E-13
+ VJE = 0.94
+ MJE = 0.42
+ CJC = 4.3E-13
+ VJC = 0.35
+ MJC = 0.21
+ XCJC = 0.44
+ TF = 1.3E-11
+ XTF = 400
+ VTF = 6
+ ITF = 1.5
+ PTF = 47
+ TR = 1E-09
+ FC = 0.98
R1 N003 0 25k
Q1 N001 N002 N003 0 MRF9411
R2 N001 N002 18k
V1 N001 0 5
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.MODEL MRF9411 NPN
.tran 10m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 448 -48 240 -48
WIRE 560 -48 448 -48
WIRE 240 -32 240 -48
WIRE 448 -32 448 -48
WIRE 448 64 448 48
WIRE 560 112 560 -48
WIRE 560 112 448 112
WIRE 240 160 240 48
WIRE 384 160 240 160
WIRE 448 224 448 208
WIRE 448 320 448 304
SYMBOL res 432 208 R0
SYMATTR InstName R1
SYMATTR Value 25k
SYMBOL npn 384 112 R0
SYMATTR InstName Q1
SYMATTR Value MRF9411
SYMBOL voltage 448 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 224 -48 R0
SYMATTR InstName R2
SYMATTR Value 18k
FLAG 448 320 0
FLAG 448 64 0
TEXT -56 -128 Left 0 !*Low Noise, High-Frequency Transistor\n*MOT Si 250mW  10V  50mA 8GHz \n.MODEL MRF9411 NPN \n+ IS = 4.558E-16 \n+ BF = 136 \n+ NF = 0.9979 \n+ VAF = 21 \n+ IKF = 0.7 \n+ ISE = 3.087E-14 \n+ NE = 2 \n+ BR = 42 \n+ NR = 0.993 \n+ VAR = 2.9 \n+ IKR = 0.016 \n+ ISC = 3.411E-17 \n+ NC = 1.087 \n+ RB = 7 \n+ IRB = 8E-05 \n+ RBM = 8 \n+ RE = 0.45 \n+ RC = 8 \n+ XTB = 0 \n+ EG = 1.11 \n+ XTI = 3 \n+ CJE = 8.6E-13 \n+ VJE = 0.94 \n+ MJE = 0.42 \n+ CJC = 4.3E-13 \n+ VJC = 0.35 \n+ MJC = 0.21 \n+ XCJC = 0.44 \n+ TF = 1.3E-11 \n+ XTF = 400 \n+ VTF = 6 \n+ ITF = 1.5 \n+ PTF = 47 \n+ TR = 1E-09 \n+ FC = 0.98
TEXT -58 344 Left 2 !.tran 10m
* Z:\home\khalils\Downloads\files\data\raw_asc\3766afac676e_Figure_2-7_CS_DC_sweep.asc
* Generated by LTspice 26.0.1 for Windows.
;.tran 400u
;.ic v(vout)=1
C1 vout 0 1n
VIN vin 0 SINE(1 0.1 10k) AC 1
VDD vdd 0 5
M1 vout vin 0 0 MyNMOS l=1u w=20u
RD vdd vout 10k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL MyNMOS NMOS (KP=50u VT0=0.5)
.dc VIN 0 5 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1404 680
WIRE 320 16 224 16
WIRE 608 16 320 16
WIRE 608 48 608 16
WIRE 608 144 608 128
WIRE 800 144 608 144
WIRE 864 144 800 144
WIRE 608 160 608 144
WIRE 224 176 224 16
WIRE 736 208 608 208
WIRE 400 240 352 240
WIRE 560 240 400 240
WIRE 800 256 800 144
WIRE 352 272 352 240
WIRE 608 272 608 256
WIRE 736 272 736 208
WIRE 736 272 608 272
WIRE 224 400 224 256
WIRE 352 400 352 352
WIRE 352 400 224 400
WIRE 608 400 608 272
WIRE 608 400 352 400
WIRE 800 400 800 320
WIRE 800 400 608 400
WIRE 224 432 224 400
SYMBOL nmos4 560 160 R0
SYMATTR InstName M1
SYMATTR Value MyNMOS
SYMATTR Value2 l=1u w=20u
SYMBOL cap 784 256 R0
SYMATTR InstName C1
SYMATTR Value 1n
SYMBOL voltage 224 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL res 592 32 R0
SYMATTR InstName RD
SYMATTR Value 10k
SYMBOL voltage 352 256 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName VIN
SYMATTR Value SINE(1 0.1 10k)
FLAG 224 432 0
FLAG 864 144 vout
FLAG 400 240 vin
FLAG 320 16 vdd
TEXT 896 384 Left 2 !.MODEL MyNMOS NMOS (KP=50u VT0=0.5)
TEXT 1024 216 Left 2 !;.tran 400u
TEXT 1000 256 Left 2 !.dc VIN 0 5 0.01
TEXT 1008 296 Left 2 !;.ic v(vout)=1
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7154-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7154-2.5.asy)
V1 IN 0 3.4
C2 N003 0 1
C4 N002 0 1
XU1 N004 OUT N002 0 N003 N003 N001 IN ADM7154_5 Vreg=3.2022 Vref=2.5157 ;pnba Vreg)Vout)Byp)GND)Ref_Sense)Ref)EN)Vin
C3 N004 0 1
R1 IN N001 100K
C1 OUT 0 10
Rload OUT 0 25
.tran 5m startup
.lib ADM7154_5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -144 32
WIRE 80 32 -32 32
WIRE 464 32 400 32
WIRE 560 32 464 32
WIRE -144 48 -144 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE -144 144 -144 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE -16 224 -32 224
WIRE 80 224 48 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE -16 320 -32 320
WIRE 80 320 48 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL res 544 32 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL ADM7154-2.5 240 176 R0
SYMATTR InstName U1
SYMBOL voltage -144 32 R0
SYMATTR InstName V1
SYMATTR Value 3.4
SYMBOL cap 48 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap 48 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 448 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 448 48 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -32 320 0
FLAG -32 224 0
FLAG -144 144 0
FLAG 560 144 0
FLAG -144 32 IN
FLAG 560 32 OUT
TEXT 432 384 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2a347c8b07d4_AD8236.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N004 N003 N002 N001 0 N005 OUT +V AD8236 ;pnba FB)RG2)RG1)In+)V-)REF)OUT)V+
Vcm N004 0 2.5
Vref N005 0 2.5
V1 +V 0 5
Rload OUT 0 10K
Vdiff N001 N004 SINE(0 .1 1K)
Rgain N002 N003 84.5K
.tran 100m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8236.asy)
.lib ADI1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 80 -208 80
WIRE 208 80 208 64
WIRE 96 96 -16 96
WIRE 128 96 128 80
WIRE 144 96 128 96
WIRE -352 112 -352 96
WIRE -208 112 -208 80
WIRE -16 112 -16 96
WIRE 96 128 96 96
WIRE 144 128 96 128
WIRE 400 144 272 144
WIRE 144 160 96 160
WIRE 400 160 400 144
WIRE 144 192 128 192
WIRE -352 208 -352 192
WIRE -16 208 -16 192
WIRE 96 208 96 160
WIRE 96 208 -16 208
WIRE -208 224 -208 192
WIRE 128 224 128 192
WIRE 128 224 -208 224
WIRE 176 224 176 208
WIRE 240 224 240 208
WIRE -208 240 -208 224
WIRE 400 256 400 240
WIRE 240 320 240 304
WIRE -208 336 -208 320
FLAG -352 208 0
FLAG -208 336 0
FLAG 240 320 0
FLAG 400 256 0
FLAG 176 224 0
FLAG 400 144 OUT
FLAG 208 64 +V
FLAG -352 96 +V
SYMBOL AD8236 208 144 R0
WINDOW 3 43 34 Left 2
SYMATTR InstName U1
SYMBOL voltage -208 224 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vcm
SYMATTR Value 2.5
SYMBOL voltage 240 208 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vref
SYMATTR Value 2.5
SYMBOL voltage -352 96 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 384 144 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage -208 96 R0
WINDOW 123 24 132 Left 2
WINDOW 39 24 114 Left 2
SYMATTR Value SINE(0 .1 1K)
SYMATTR InstName Vdiff
SYMBOL res -32 96 R0
SYMATTR InstName Rgain
SYMATTR Value 84.5K
TEXT 360 360 Left 2 !.tran 100m