Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\4585e7bb6cec_555.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 0 N003 N004 N001 N005 N003 N002 N001 NE555 ;pnba GND)TRIG)OUT)RST)CV)THRS)DIS)Vcc
R1 N001 N002 1000
R2 N002 N003 1000
C1 N005 0 1F
C2 N003 0 1F
V1 N001 0 12
D1 N002 N003 D
R4 N004 0 1k
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Misc\NE555.asy)
.lib NE555.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 744
WIRE 400 -400 256 -400
WIRE 256 -320 -288 -320
WIRE 528 -208 -176 -208
WIRE 400 -128 400 -400
WIRE 400 -128 32 -128
WIRE 464 -128 400 -128
WIRE 416 -16 96 -16
WIRE 32 80 32 -128
WIRE 32 80 -48 80
WIRE 80 80 32 80
WIRE 128 96 112 96
WIRE 464 96 464 -128
WIRE 464 96 352 96
WIRE 96 160 96 -16
WIRE 128 160 96 160
WIRE 528 160 528 -208
WIRE 528 160 352 160
WIRE -176 208 -176 -208
WIRE -144 208 -176 208
WIRE -48 208 -48 160
WIRE -48 208 -144 208
WIRE 128 224 -512 224
WIRE 416 224 416 -16
WIRE 416 224 352 224
WIRE -144 256 -144 208
WIRE -48 256 -48 208
WIRE 80 288 80 80
WIRE 128 288 80 288
WIRE 464 288 352 288
WIRE -512 320 -512 224
WIRE -144 336 -144 320
WIRE -48 336 -144 336
WIRE 96 336 96 160
WIRE 96 336 -48 336
WIRE -48 416 -48 336
WIRE 464 416 464 288
WIRE 464 416 240 416
WIRE -288 544 -288 -320
WIRE -48 544 -48 480
WIRE -48 544 -288 544
WIRE -48 560 -48 544
WIRE 112 560 112 96
WIRE 112 560 -48 560
WIRE 240 560 240 480
WIRE 240 560 112 560
WIRE -512 592 -512 400
WIRE 112 592 112 560
WIRE 112 592 -512 592
WIRE 112 656 112 592
WIRE 144 656 112 656
WIRE 144 704 144 656
FLAG 144 704 0
SYMBOL Misc\\NE555 240 192 R0
SYMATTR InstName U1
SYMBOL res -64 64 R0
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL res -64 240 R0
SYMATTR InstName R2
SYMATTR Value 1000
SYMBOL cap 224 416 R0
SYMATTR InstName C1
SYMATTR Value 1F
SYMBOL cap -64 416 R0
SYMATTR InstName C2
SYMATTR Value 1F
SYMBOL voltage 256 -416 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL diode -160 256 R0
SYMATTR InstName D1
SYMBOL res -528 304 R0
SYMATTR InstName R4
SYMATTR Value 1k
TEXT -514 728 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4444-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4444-5.asy)
V2 N008 0 PULSE(0 5 0 10n 10n 1u 2u)
MQ1 N004 N005 N003 N003 IRF7468
V3 N004 0 50
V1 N001 0 10
V4 N006 0 PULSE(5 0 0 10n 10n 1u 2u)
MQ2 N003 N009 0 0 IRF7468
L1 N003 N007 1
D1 N001 N002 1N5819
XU1 N006 N008 N001 N009 MP_01 N002 N005 N003 0 LTC4444-5 ;pnba Tinp)Binp)Vcc)BG))Boost)TG)TS)GND
C2 N007 0 10
C1 N003 N002 .1
R1 N007 0 .5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100u startup
.lib LTC4444-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 48 -192 48
WIRE 0 48 -48 48
WIRE 112 48 64 48
WIRE 176 48 112 48
WIRE 272 48 240 48
WIRE -192 64 -192 48
WIRE 496 80 336 80
WIRE 336 96 336 80
WIRE 496 96 496 80
WIRE 112 112 112 48
WIRE -192 160 -192 144
WIRE -48 176 -48 48
WIRE -16 176 -48 176
WIRE 288 176 240 176
WIRE 496 192 496 176
WIRE -16 256 -192 256
WIRE 272 256 272 48
WIRE 272 256 240 256
WIRE 336 256 336 192
WIRE 336 256 272 256
WIRE 384 256 336 256
WIRE 496 256 464 256
WIRE 576 256 496 256
WIRE 496 272 496 256
WIRE 576 272 576 256
WIRE -16 336 -96 336
WIRE 288 336 240 336
WIRE -96 368 -96 336
WIRE 336 368 336 352
WIRE 496 368 496 336
WIRE 576 368 576 352
WIRE 112 416 112 400
WIRE -192 448 -192 256
WIRE -192 544 -192 528
SYMBOL cap 240 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL cap 480 272 R0
SYMATTR InstName C2
SYMATTR Value 10
SYMBOL nmos 288 256 R0
SYMATTR InstName Q2
SYMATTR Value IRF7468
SYMBOL voltage -96 352 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 10n 10n 1u 2u)
SYMBOL voltage -192 48 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL PowerProducts\\LTC4444-5 112 256 R0
SYMATTR InstName U1
SYMBOL res 560 256 R0
SYMATTR InstName R1
SYMATTR Value .5
SYMBOL nmos 288 96 R0
SYMATTR InstName Q1
SYMATTR Value IRF7468
SYMBOL voltage 496 80 R0
SYMATTR InstName V3
SYMATTR Value 50
SYMBOL schottky 0 64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N5819
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage -192 432 R0
SYMATTR InstName V4
SYMATTR Value PULSE(5 0 0 10n 10n 1u 2u)
SYMBOL ind 368 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
FLAG 112 416 0
FLAG -96 448 0
FLAG -192 160 0
FLAG 336 368 0
FLAG 496 192 0
FLAG 496 368 0
FLAG 576 368 0
FLAG -192 544 0
TEXT 392 440 Left 2 !.tran 100u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\6c98b8d1d2e9_2NAND.asc
* Generated by LTspice 26.0.1 for Windows.
M1 VHIGH A Vout VHIGH PMOS l=50n w=1u
M2 VHIGH NC_01 Vout VHIGH PMOS l=50n w=1u
M5 N001 B VLOW VLOW NMOS l=50n w=0.5u
M4 Vout A N001 VLOW NMOS l=50n w=0.5u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include models.txt
.tran 11u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 960 708
WIRE 256 -32 208 -32
WIRE 160 16 80 16
WIRE 208 16 208 -32
WIRE 208 16 160 16
WIRE 256 16 208 16
WIRE 304 16 256 16
WIRE 160 64 160 16
WIRE 160 64 80 64
WIRE 304 64 304 16
WIRE 304 64 256 64
WIRE 32 96 -16 96
WIRE 80 144 80 112
WIRE 176 144 80 144
WIRE 256 144 256 112
WIRE 256 144 176 144
WIRE 368 144 256 144
WIRE 224 192 176 192
WIRE -16 224 -16 96
WIRE -16 224 -128 224
WIRE 128 224 -16 224
WIRE 176 288 176 240
WIRE 224 336 224 192
WIRE 224 336 176 336
WIRE 128 368 -128 368
WIRE 224 384 224 336
WIRE 224 384 176 384
WIRE 256 384 224 384
WIRE 256 448 256 384
SYMBOL pmos4 208 16 R0
SYMATTR InstName M2
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 128 288 R0
SYMATTR InstName M5
SYMATTR Value2 l=50n w=0.5u
SYMBOL pmos4 32 16 R0
SYMATTR InstName M1
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 128 144 R0
SYMATTR InstName M4
SYMATTR Value2 l=50n w=0.5u
FLAG -128 224 A
FLAG -128 368 B
FLAG 256 -32 VHIGH
FLAG 256 448 VLOW
FLAG 368 144 Vout
TEXT -376 312 Left 2 !.include models.txt
TEXT -352 384 Left 2 !.tran 11u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7182.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7182.asy)
V2 N001 0 PULSE(0 2 200u 1n 1n 10m)
V1 IN 0 -8
R1 OUT N002 120k
R3 OUT 0 50
XU1 OUT MP_01 N002 N001 MP_02 0 IN ADP7182 ;pnba Vout))ADJ)EN))GND)Vin
R2 N002 0 120k
C1 IN 0 2.2
C2 OUT 0 2.2
.tran 1m
.lib ADP7182.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE 32 -48 -80 -48
WIRE 112 -48 32 -48
WIRE 416 -48 368 -48
WIRE 496 -48 416 -48
WIRE 608 -48 496 -48
WIRE -80 -32 -80 -48
WIRE 32 -32 32 -48
WIRE 496 -32 496 -48
WIRE 608 -32 608 -48
WIRE 416 48 416 -48
WIRE -80 64 -80 48
WIRE 32 64 32 32
WIRE 496 64 496 32
WIRE 608 64 608 48
WIRE 112 144 32 144
WIRE 416 144 416 128
WIRE 416 144 368 144
WIRE 32 160 32 144
WIRE 416 160 416 144
WIRE 32 256 32 240
WIRE 240 256 240 208
WIRE 416 256 416 240
SYMBOL res 400 144 R0
SYMATTR InstName R2
SYMATTR Value 120k
SYMBOL res 400 32 R0
SYMATTR InstName R1
SYMATTR Value 120k
SYMBOL res 592 -48 R0
SYMATTR InstName R3
SYMATTR Value 50
SYMBOL voltage 32 144 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 2 200u 1n 1n 10m)
SYMBOL voltage -80 -48 R0
SYMATTR InstName V1
SYMATTR Value -8
SYMBOL cap 480 -32 R0
SYMATTR InstName C2
SYMATTR Value 2.2
SYMBOL cap 16 -32 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL ADP7182 240 48 R0
SYMATTR InstName U1
FLAG -80 64 0
FLAG 32 64 0
FLAG 496 64 0
FLAG 32 256 0
FLAG 240 256 0
FLAG 608 64 0
FLAG 32 -48 IN
FLAG 496 -48 OUT
FLAG 416 256 0
TEXT 528 248 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\287903d9a274_6203.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6203.asy)
R2 N001 0 1K
V3 IN 0 SINE(0 1 1Meg)
R1 OUT N001 1K
XU1 IN N001 OUT +V -V LT6202 ;pnba IN+)IN-)OUT)VCC)VEE
V2 -V 0 -5
V1 +V 0 5
.tran 10u
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 32 96 16 96
WIRE 128 96 112 96
WIRE 144 96 128 96
WIRE 256 96 224 96
WIRE -208 144 -208 128
WIRE -80 144 -80 128
WIRE 192 208 192 192
WIRE 128 224 128 96
WIRE 160 224 128 224
WIRE -208 240 -208 224
WIRE -80 240 -80 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 304 240 256 240
WIRE 160 256 0 256
WIRE 0 272 0 256
WIRE 192 288 192 272
WIRE 0 368 0 352
SYMBOL voltage -80 128 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 128 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 0 256 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1Meg)
SYMBOL opamps\\LT6203 192 240 R0
SYMATTR InstName U1
SYMBOL voltage -208 128 R0
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL res 240 80 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1K
FLAG -80 240 0
FLAG 192 192 +V
FLAG -80 128 +V
FLAG 192 288 -V
FLAG -208 240 0
FLAG -208 128 -V
FLAG 16 96 0
FLAG 0 368 0
FLAG 304 240 OUT
FLAG 0 256 IN
TEXT 280 344 Left 0 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP2503-4.5.asc
* Generated by LTspice 26.0.1 for Windows.
* PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP2503-4.5.asy)
L1 N001 N002 1.5 Rser=80m
C1 OUT 0 10
XU1 N001 N002 OUT IN IN 0 OUT NC_01 ADP2503-4.5 ;pnba SW1)SW2)FB)EN)PVin)GND)Vout)Sync
V1 IN 0 3.3
Rload OUT 0 50
.tran 400u startup
.lib ADP2503-4.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 64 -64 64
WIRE 48 64 32 64
WIRE 336 64 304 64
WIRE -64 80 -64 64
WIRE 32 144 32 64
WIRE 48 144 32 144
WIRE 336 144 304 144
WIRE -64 176 -64 160
WIRE 320 224 304 224
WIRE 368 224 320 224
WIRE 480 224 368 224
WIRE 368 240 368 224
WIRE 480 240 480 224
WIRE 48 304 32 304
WIRE 320 304 320 224
WIRE 320 304 304 304
WIRE 368 336 368 304
WIRE 480 336 480 320
SYMBOL res 464 224 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL ADP2503-4.5 176 176 R0
SYMATTR InstName U1
SYMBOL cap 352 240 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -64 64 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL ind 320 48 R0
SYMATTR InstName L1
SYMATTR Value 1.5
SYMATTR SpiceLine Rser=80m
FLAG 368 336 0
FLAG 32 304 0
FLAG -64 176 0
FLAG 480 336 0
FLAG -64 64 IN
FLAG 480 224 OUT
TEXT 424 392 Left 2 !.tran 400u startup
TEXT 184 0 Bottom 2 ;PSM and forced PWM modes are modelled\nClock Sync is not modelled
* Z:\home\khalils\Downloads\files\data\raw_asc\11b02168e93e_FET03op.asc
* Generated by LTspice 26.0.1 for Windows.
J1 d g s JFET
Vdd N001 0 {Vdd}
Rd N001 d {Rd}
Rs s 0 {Rs}
R1 N001 g {R1}
R2 g 0 {R2}
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.op
.model JFET njf(Beta=3m Vto=-5)
.param Vdd=25 Rs=120 Rd=560 R1=4.7Meg R2=680k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1608 1076
WIRE 192 -128 16 -128
WIRE 384 -128 192 -128
WIRE 16 -80 16 -128
WIRE 192 -80 192 -128
WIRE 192 32 192 0
WIRE 192 48 192 32
WIRE 384 48 384 -128
WIRE 16 112 16 0
WIRE 96 112 16 112
WIRE 144 112 96 112
WIRE 192 160 192 144
WIRE 16 176 16 112
WIRE 192 176 192 160
WIRE 16 272 16 256
WIRE 192 272 192 256
WIRE 192 272 16 272
WIRE 384 272 384 128
WIRE 384 272 192 272
WIRE 192 288 192 272
FLAG 192 288 0
FLAG 96 112 g
FLAG 192 32 d
FLAG 192 160 s
SYMBOL njf 144 48 R0
SYMATTR InstName J1
SYMATTR Value JFET
SYMBOL voltage 384 32 R0
WINDOW 0 55 34 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdd
SYMATTR Value {Vdd}
SYMBOL res 176 -96 R0
SYMATTR InstName Rd
SYMATTR Value {Rd}
SYMBOL res 176 160 R0
SYMATTR InstName Rs
SYMATTR Value {Rs}
SYMBOL res 0 -96 R0
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL res 0 160 R0
SYMATTR InstName R2
SYMATTR Value {R2}
TEXT 16 312 Left 2 !.op
TEXT 16 352 Left 2 !.model JFET njf(Beta=3m Vto=-5)
TEXT 16 392 Left 2 !.param Vdd=25 Rs=120 Rd=560 R1=4.7Meg R2=680k
* Z:\home\khalils\Downloads\files\data\raw_asc\510fad32ea85_1077.asc
* Generated by LTspice 26.0.1 for Windows.
* Half-Wave Rectifier
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1077.asy)
R2 N001 IN 1Meg
R3 N002 0 1Meg
XU1 N002 N001 +V 0 OUT LT1078 ;pnba In+)In-)V+)V-)OUT
V1 +V 0 3
V3 IN 0 SINE(0 1 100)
R1 OUT N001 2Meg
.tran .1
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -96 96 -128 96
WIRE 16 96 -16 96
WIRE 48 96 16 96
WIRE 144 96 128 96
WIRE 160 96 144 96
WIRE 256 96 240 96
WIRE 192 208 192 192
WIRE 144 224 144 96
WIRE 160 224 144 224
WIRE -96 240 -96 224
WIRE 256 240 256 96
WIRE 256 240 224 240
WIRE 288 240 256 240
WIRE 64 256 48 256
WIRE 160 256 144 256
WIRE 192 288 192 272
WIRE -96 336 -96 320
SYMBOL res 144 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL voltage 0 96 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value SINE(0 1 100)
SYMBOL voltage -96 224 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL res 160 240 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1Meg
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 2Meg
SYMBOL opamps\\LT1077 192 176 R0
SYMATTR InstName U1
FLAG -96 336 0
FLAG 192 192 +V
FLAG -96 224 +V
FLAG -128 96 0
FLAG 48 256 0
FLAG 192 288 0
FLAG 16 96 IN
FLAG 288 240 OUT
TEXT 296 320 Left 2 !.tran .1
TEXT 152 32 Bottom 2 ;Half-Wave Rectifier
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG721.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG721.asy)
V1 +V 0 5
R1 N002 0 300
VS N001 0 3
XU2 N003 N002 N001 0 +V ADG721 ;pnba IN)D)S)GND)Vdd
V4 N003 0 PULSE(0 3 0 10n 10n 980n 2u)
C1 N002 0 35p
.tran 10u
.lib ADG721.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -144 -80 -144 -112
WIRE -368 -16 -400 -16
WIRE -240 -16 -288 -16
WIRE 0 -16 -48 -16
WIRE 112 -16 0 -16
WIRE 0 16 0 -16
WIRE -480 32 -480 16
WIRE 112 32 112 -16
WIRE -240 48 -368 48
WIRE -368 112 -368 48
WIRE 0 112 0 96
WIRE 112 112 112 96
WIRE -480 128 -480 112
WIRE -144 176 -144 160
WIRE -368 272 -368 192
SYMBOL res -16 0 R0
SYMATTR InstName R1
SYMATTR Value 300
SYMBOL voltage -368 96 R0
WINDOW 3 17 129 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 3 0 10n 10n 980n 2u)
SYMATTR InstName V4
SYMBOL ADG721 -144 32 R0
SYMATTR InstName U2
SYMBOL voltage -480 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -272 -16 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VS
SYMATTR Value 3
SYMBOL cap 96 32 R0
SYMATTR InstName C1
SYMATTR Value 35p
FLAG -480 128 0
FLAG -480 16 +V
FLAG -400 -16 0
FLAG -144 -112 +V
FLAG -144 176 0
FLAG -368 272 0
FLAG 0 112 0
FLAG 112 112 0
TEXT -536 200 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8062.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8062.asy)
C1 OUT 0 .1m
V1 IN 0 12
R1 OUT N001 274K
XU1 IN IN IN NC_01 NC_02 0 N001 NC_03 OUT MP_04 OUT IN 0 LTM8062 ;pnba Vin)Vin_reg)Run)_CHRG)_Fault)Timer)ADJ)NTC)BAT))Bias)VinA)GND
R2 N001 0 2.87Meg
.tran 2m startup
.lib LTM8062.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 912 680
WIRE 64 -64 -32 -64
WIRE 80 -64 64 -64
WIRE -32 -48 -32 -64
WIRE 64 32 64 -64
WIRE 80 32 64 32
WIRE -32 48 -32 32
WIRE 64 128 64 32
WIRE 80 128 64 128
WIRE 432 128 368 128
WIRE 496 128 432 128
WIRE 496 144 496 128
WIRE 64 224 64 128
WIRE 80 224 64 224
WIRE 432 224 432 128
WIRE 432 224 368 224
WIRE 496 224 496 208
WIRE 432 272 432 224
WIRE 80 320 64 320
WIRE 80 416 64 416
WIRE 432 416 432 352
WIRE 432 416 368 416
WIRE 432 432 432 416
WIRE 432 528 432 512
SYMBOL cap 480 144 R0
SYMATTR InstName C1
SYMATTR Value .1m
SYMBOL res 416 256 R0
SYMATTR InstName R1
SYMATTR Value 274K
SYMBOL PowerProducts\\LTM8062 224 176 R0
SYMATTR InstName U1
SYMBOL res 416 416 R0
SYMATTR InstName R2
SYMATTR Value 2.87Meg
SYMBOL voltage -32 -64 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 64 416 0
FLAG -32 48 0
FLAG 496 224 0
FLAG -32 -64 IN
FLAG 496 128 OUT
FLAG 64 320 0
FLAG 432 528 0
TEXT 608 504 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1474.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1474.asy)
XU1 N005 N003 N002 0 N001 IN IN N004 LTC1474 top=10 bot=1T ;pnba FB)LBO)LBI)GND)SW)Sense)Vin)Run
Rload OUT 0 25
D1 0 N001 MBR0530L
C1 OUT 0 100
L1 N001 OUT 100
V1 IN 0 10
R1 OUT N005 1.68Meg
R2 N005 0 1Meg
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LTC1474.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2704 1608
WIRE 1600 1184 1488 1184
WIRE 1776 1184 1600 1184
WIRE 1488 1200 1488 1184
WIRE 1776 1200 1776 1184
WIRE 1600 1264 1600 1184
WIRE 1632 1264 1600 1264
WIRE 1984 1264 1920 1264
WIRE 2032 1264 1984 1264
WIRE 2160 1264 2112 1264
WIRE 2320 1264 2160 1264
WIRE 2448 1264 2320 1264
WIRE 2320 1280 2320 1264
WIRE 2448 1280 2448 1264
WIRE 1488 1296 1488 1280
WIRE 1984 1296 1984 1264
WIRE 2160 1296 2160 1264
WIRE 1632 1344 1616 1344
WIRE 1936 1344 1920 1344
WIRE 2320 1376 2320 1344
WIRE 2448 1376 2448 1360
WIRE 1984 1392 1984 1360
WIRE 1632 1424 1616 1424
WIRE 2160 1424 2160 1376
WIRE 2160 1424 1920 1424
WIRE 2160 1440 2160 1424
WIRE 1776 1504 1776 1488
WIRE 2160 1536 2160 1520
SYMBOL res 2144 1424 R0
SYMATTR InstName R2
SYMATTR Value 1Meg
SYMBOL POWERPRODUCTS\\LTC1474 1776 1344 R0
SYMATTR InstName U1
SYMBOL res 2432 1264 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL RES 2144 1280 R0
SYMATTR InstName R1
SYMATTR Value 1.68Meg
SYMBOL schottky 1968 1360 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBR0530L
SYMBOL ind 2016 1280 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL polcap 2304 1280 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMBOL VOLTAGE 1488 1184 R0
SYMATTR InstName V1
SYMATTR Value 10
FLAG 1488 1296 0
FLAG 1984 1392 0
FLAG 2320 1376 0
FLAG 2448 1376 0
FLAG 1776 1504 0
FLAG 2160 1536 0
FLAG 2448 1264 OUT
FLAG 1488 1184 IN
TEXT 2256 1456 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\902661a52717_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T2 0 0 OUT 0 Td=30n Z0=150
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T1 IN 0 0 OUT Td=50n Z0=50
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\4098633500c9_Uncompensated.asc
* Generated by LTspice 26.0.1 for Windows.
XX1 NC_01 NC_02 NC_03 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
V1 N001 0 AC 1
.ac oct 20 100 10000k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 128 144 -48 144
WIRE -48 176 -48 144
WIRE 128 176 128 144
WIRE 400 192 288 192
WIRE -48 336 -48 256
WIRE 16 336 -48 336
WIRE 128 336 128 208
WIRE 128 336 16 336
WIRE 16 384 16 336
IOPIN 400 192 Out
SYMBOL voltage -48 160 R0
SYMATTR InstName V1
SYMATTR Value AC 1
SYMBOL OpAmp 208 192 R0
SYMATTR InstName X1
FLAG 400 192 Vout
FLAG 16 384 0
TEXT 112 384 Left 2 !.ac oct 20 100 10000k
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP166-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP166-1.8.asy)
XU1 IN 0 N001 OUT ADP16xf K=555.6u ;pnba Vin)GND)En)Vout
V1 IN 0 5
Rload OUT 0 180
C1 OUT 0 1
V2 N001 0 PULSE(0 5 100u 50n 50n 2.5m)
.tran 4m
.lib ADP16x.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 96 -64 96
WIRE 416 96 352 96
WIRE 512 96 416 96
WIRE -64 112 -64 96
WIRE 416 112 416 96
WIRE 512 112 512 96
WIRE -64 208 -64 192
WIRE 160 208 16 208
WIRE 416 208 416 176
WIRE 512 208 512 192
WIRE 16 224 16 208
WIRE 256 272 256 256
WIRE 16 320 16 304
SYMBOL cap 400 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage 16 208 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 100u 50n 50n 2.5m)
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 180
SYMBOL ADP166-1.8 256 208 R0
SYMATTR InstName U1
SYMBOL voltage -64 96 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG -64 208 0
FLAG 256 272 0
FLAG 416 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG -64 96 IN
FLAG 16 320 0
TEXT 528 320 Left 2 !.tran 4m