* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3882-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time related parameters.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LTC3882-2 . Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope discribed in the datasheet, the resulting simulation outcomes are not meaningful.\n \n Freq -- in Hz, sets switching frequency as one of values of 250K, 300K, 350K, \n 400K, 450K, 500K, 600K, 750K, 900K, 1000K, 1250K,1500k 1750k 200k 2250k 2500k. \n FREQ_CFG pin needs to float (or short to VDD25), to make the value be in effect;\n PHAS_0 & PHAS_1 -- in degree, set phase angle related to SYNC signal. \n Certain combinations are restricted as in datasheet. PHAS_CFG \n pin needs to float (or short to VDD25), to make the value be in effect;\n Ton0_delay & Ton0_rise; Ton1_delay & Ton1_rise -- in sec, set delay and soft-start timers for \n channel0 and channel1. Initialization time is not modeled;\n Toff0_delay & Toff0_fall; Toff1_delay & Toff1_fall -- in sec, set delay and soft-off timers for \n channel0 and channel1;\n Vout_0 & Vout_1 -- in volt, set output voltages respectively. Vout#_CFG pin needs to float \n (or short to VDD25), to make the value be in effect;\n Vout0_range & Vout1_range -- set maximum output range, with value 0\n for 5.5V; value 1 for 2.75V;\n Iout0_fault & Iout1_fault -- in Amper, set maximum inductor peak current value, OC will be triggered \n when the value is exceeded;\n Iout0_warn & Iout1_warn -- in aMper, set the average load current maximum value, which will be used \n with Vout#_AVP to define the AVP operation;\n Iout0_gain & Iout1_gain -- in Ohm, set sensing resistor or inductor DCR values used in the circuit;\n Vout0_AVP & Vout1_AVP -- set the maximum value reference will reduce at Iout#_warn level:
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3882-2.asy)
* Library below included based on ModelFile attribute of instance XU2, XU3 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4449.asy)
D1 N004 N005 1N5818
R2 N002 N014 3.09K
MQ2 N006 N013 0 0 AOB2140L
C1 OUT 0 470 X4 Rser=25m
C10 N016 N019 200p
V1 N004 0 5
C12 N017 N019 11p
C4 N005 N006 .22
V2 IN 0 32
XU3 MP_03 MP_04 N008 N002 N010 0 N011 N001 N004 N003 LTC4449 ;pnba ))TG)TS)BG)GND)IN)Vlogic)Vcc)Boost
C7 N001 0 2.2
MQ4 N002 N010 0 0 AOB2140L
C9 N020 0 100p
C8 N021 0 1
L2 N002 OUT .2 Rser=.3m Rpar=5K
C13 N018 N019 270p
Rload1 OUT 0 82.5m
C3 N015 OUT .22
C5 N014 OUT .22
MQ3 IN N008 N002 N002 SIJA72ADP
L1 N006 OUT .2 Rser=.3m Rpar=5K
C2 OUT 0 100 X2 Rser=3m
R1 N006 N015 3.09K
MQ1 IN N009 N006 N006 SIJA72ADP
R5 OUT N016 1.07k
C6 N003 N002 .22
R3 N007 N001 2K
XU2 MP_01 MP_02 N009 N006 N013 0 N012 N001 N004 N005 LTC4449 ;pnba ))TG)TS)BG)GND)IN)Vlogic)Vcc)Boost
R4 N018 N017 100k
XU1 N019 N017 OUT 0 NC_05 NC_06 N020 OUT N017 N001 0 NC_07 N007 N021 NC_08 MP_09 MP_10 N011 N004 MP_11 0 N014 OUT OUT N015 N001 MP_12 N004 N012 MP_13 MP_14 N020 0 IN NC_15 N004 MP_16 NC_17 LTC3882-2 Vout_0=1 Vout_1=1 Iout0_fault=29.75 Iout1_fault=29.75 Iout0_warn=20 Iout1_warn=20 Iout0_gain=1m Iout1_gain=1m Vout0_AVP=0 Vout1_AVP=1 Freq=500K PHAS_0=0 PHAS_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_rng=0 Vout1_rng=0 ;pnba FB0)COMP0)Vsense0+)Vsense0-)Vout0_cfg)Vout1_cfg)Iavg0)Vsense1+)COMP1)FB1)Iavg_gnd)Freq_cfg)SYNC)VDD25)PHAS_cfg)))PWM1)Run1))GND)Isense1+)Isense1-)Isense0-)Isense0+)VDD33))Run0)PWM0)))Iavg1)Vsense1-)Vinsns)PGood0)Vcc))PGood1
D2 N004 N003 1N5818
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1m startup
.lib LTC3882-2.sub
.lib LTC4449.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3180 964
WIRE 1440 -592 -816 -592
WIRE -752 -560 -768 -560
WIRE -496 -560 -752 -560
WIRE 112 -560 -496 -560
WIRE 960 -560 112 -560
WIRE -768 -528 -768 -560
WIRE 592 -528 -96 -528
WIRE -384 -496 -656 -496
WIRE -288 -496 -320 -496
WIRE -240 -496 -288 -496
WIRE -128 -496 -176 -496
WIRE -32 -496 -128 -496
WIRE 304 -496 -32 -496
WIRE 448 -496 304 -496
WIRE 496 -496 448 -496
WIRE 560 -496 496 -496
WIRE 640 -496 560 -496
WIRE 752 -496 704 -496
WIRE 800 -496 752 -496
WIRE 1136 -496 864 -496
WIRE 496 -480 496 -496
WIRE -496 -464 -496 -560
WIRE 960 -464 960 -560
WIRE -288 -448 -288 -496
WIRE 752 -448 752 -496
WIRE -768 -432 -768 -448
WIRE -96 -432 -96 -528
WIRE 16 -432 -96 -432
WIRE 208 -432 96 -432
WIRE -416 -384 -448 -384
WIRE -96 -384 -96 -432
WIRE -96 -384 -160 -384
WIRE 496 -384 496 -400
WIRE 592 -384 592 -528
WIRE 624 -384 592 -384
WIRE 912 -384 880 -384
WIRE 112 -352 112 -560
WIRE 208 -352 208 -432
WIRE 304 -352 304 -496
WIRE -816 -304 -816 -592
WIRE -768 -304 -816 -304
WIRE -656 -304 -656 -496
WIRE -656 -304 -688 -304
WIRE -496 -304 -496 -368
WIRE -496 -304 -656 -304
WIRE -416 -304 -496 -304
WIRE -128 -304 -128 -496
WIRE -128 -304 -160 -304
WIRE 560 -304 560 -496
WIRE 624 -304 560 -304
WIRE 960 -304 960 -368
WIRE 960 -304 880 -304
WIRE 1136 -304 1136 -496
WIRE 1136 -304 960 -304
WIRE 1168 -304 1136 -304
WIRE 1280 -304 1248 -304
WIRE 1328 -304 1280 -304
WIRE 1440 -304 1440 -592
WIRE 1440 -304 1328 -304
WIRE 1552 -304 1440 -304
WIRE -32 -288 -32 -496
WIRE 0 -288 -32 -288
WIRE 448 -288 448 -496
WIRE 448 -288 416 -288
WIRE 1328 -288 1328 -304
WIRE 1440 -288 1440 -304
WIRE 1552 -288 1552 -304
WIRE -416 -224 -448 -224
WIRE -128 -224 -160 -224
WIRE 624 -224 560 -224
WIRE 912 -224 880 -224
WIRE -128 -192 -128 -224
WIRE 0 -192 -128 -192
WIRE 560 -192 560 -224
WIRE 560 -192 416 -192
WIRE 1328 -192 1328 -224
WIRE 1440 -192 1440 -224
WIRE 1552 -192 1552 -208
WIRE -496 -176 -496 -208
WIRE 960 -176 960 -208
WIRE -288 -144 -288 -160
WIRE 752 -144 752 -160
WIRE -656 -96 -656 -304
WIRE -192 -96 -656 -96
WIRE -64 -96 -112 -96
WIRE 0 -96 -64 -96
WIRE 448 -96 416 -96
WIRE 528 -96 448 -96
WIRE 1136 -96 1136 -304
WIRE 1136 -96 608 -96
WIRE -64 -80 -64 -96
WIRE 448 -80 448 -96
WIRE -816 0 -816 -304
WIRE -64 0 -64 -16
WIRE -64 0 -816 0
WIRE 0 0 -64 0
WIRE 448 0 448 -16
WIRE 448 0 416 0
WIRE 1280 0 1280 -304
WIRE 1280 0 448 0
WIRE -816 96 -816 0
WIRE 0 96 -816 96
WIRE 832 96 416 96
WIRE 1280 96 1280 0
WIRE 1280 96 832 96
WIRE 832 144 832 96
WIRE 0 192 -16 192
WIRE 432 192 416 192
WIRE 832 272 832 224
WIRE 0 288 -16 288
WIRE 432 288 416 288
WIRE 464 288 432 288
WIRE 528 288 464 288
WIRE 656 288 608 288
WIRE 464 304 464 288
WIRE 656 304 656 288
WIRE -16 320 -16 288
WIRE 432 320 432 288
WIRE 432 320 -16 320
WIRE -96 384 -96 -384
WIRE 0 384 -96 384
WIRE 464 384 464 368
WIRE 464 384 416 384
WIRE 656 384 656 368
WIRE 656 384 464 384
WIRE 832 384 832 336
WIRE 832 384 656 384
WIRE 0 576 -16 576
WIRE 432 576 416 576
WIRE 464 576 432 576
WIRE -16 608 -16 576
WIRE 432 608 432 576
WIRE 432 608 -16 608
WIRE 464 640 464 576
WIRE -96 848 -96 384
WIRE 64 848 64 832
WIRE 64 848 -96 848
WIRE 352 848 352 832
WIRE 464 848 464 704
WIRE 464 848 352 848
WIRE 64 864 64 848
WIRE 160 864 160 832
WIRE 256 864 256 832
WIRE 352 864 352 848
WIRE 464 864 464 848
WIRE 64 944 64 928
WIRE 160 944 160 928
SYMBOL cap -320 -512 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value .22
SYMBOL cap 48 864 R0
SYMATTR InstName C7
SYMATTR Value 2.2
SYMBOL res 112 -448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 2K
SYMBOL cap 1312 -288 R0
WINDOW 123 26 65 Left 2
WINDOW 3 41 36 Left 2
SYMATTR Value2 X4
SYMATTR Value 470
SYMATTR InstName C1
SYMATTR SpiceLine Rser=25m
SYMBOL schottky 640 -512 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N5818
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL ind 1152 -288 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value .2
SYMATTR SpiceLine Rser=.3m Rpar=5K
SYMBOL cap 144 864 R0
SYMATTR InstName C8
SYMATTR Value 1
SYMBOL cap 432 -80 R0
SYMATTR InstName C3
SYMATTR Value .22
SYMBOL schottky -176 -512 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D2
SYMATTR Value 1N5818
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res -208 -80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 3.09K
SYMBOL LTC3882-2 208 240 R0
SYMATTR InstName U1
SYMBOL nmos 912 -464 R0
SYMATTR InstName Q1
SYMATTR Value SIJA72ADP
SYMBOL cap 448 304 R0
SYMATTR InstName C12
SYMATTR Value 11p
SYMBOL res 1536 -304 R0
SYMATTR InstName Rload1
SYMATTR Value 82.5m
SYMBOL PowerProducts\\LTC4449 752 -304 R0
SYMATTR InstName U2
SYMBOL cap 1424 -288 R0
WINDOW 123 21 69 Left 2
WINDOW 3 44 37 Left 2
SYMATTR Value2 X2
SYMATTR Value 100
SYMATTR InstName C2
SYMATTR SpiceLine Rser=3m
SYMBOL nmos -448 -304 M0
SYMATTR InstName Q4
SYMATTR Value AOB2140L
SYMBOL cap 800 -512 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value .22
SYMBOL res 624 -112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 3.09K
SYMBOL voltage 496 -496 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL PowerProducts\\LTC4449 -288 -304 M0
SYMATTR InstName U3
SYMBOL cap -80 -80 R0
SYMATTR InstName C5
SYMATTR Value .22
SYMBOL ind -672 -288 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value .2
SYMATTR SpiceLine Rser=.3m Rpar=5K
SYMBOL cap 448 640 R0
SYMATTR InstName C9
SYMATTR Value 100p
SYMBOL nmos 912 -304 R0
SYMATTR InstName Q2
SYMATTR Value AOB2140L
SYMBOL cap 640 304 R0
SYMATTR InstName C13
SYMATTR Value 270p
SYMBOL res 816 128 R0
SYMATTR InstName R5
SYMATTR Value 1.07k
SYMBOL nmos -448 -464 M0
SYMATTR InstName Q3
SYMATTR Value SIJA72ADP
SYMBOL voltage -768 -544 R0
SYMATTR InstName V2
SYMATTR Value 32
SYMBOL res 624 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL cap 816 272 R0
SYMATTR InstName C10
SYMATTR Value 200p
FLAG 1328 -192 0
FLAG 1440 -192 0
FLAG 1552 -192 0
FLAG 1552 -304 OUT
FLAG 752 -144 0
FLAG 960 -176 0
FLAG 496 -384 0
FLAG -768 -432 0
FLAG -288 -144 0
FLAG -496 -176 0
FLAG -752 -560 IN
FLAG 256 864 0
FLAG 352 864 0
FLAG 64 944 0
FLAG 160 944 0
FLAG 464 864 0
FLAG 432 192 0
FLAG -16 192 0
TEXT 1688 -304 Left 2 ;Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time related parameters.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LTC3882-2 . Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope discribed in the datasheet, the resulting simulation outcomes are not meaningful.\n \n    Freq -- in Hz, sets switching frequency as one of values of 250K, 300K, 350K, \n                400K, 450K, 500K, 600K, 750K, 900K, 1000K, 1250K,1500k 1750k 200k 2250k 2500k. \n                FREQ_CFG pin needs to float (or short to VDD25), to make the value be in effect;\n     PHAS_0 & PHAS_1 -- in degree,  set phase angle related to SYNC signal. \n                Certain combinations are restricted as in datasheet. PHAS_CFG \n                pin needs to float (or short to VDD25), to make the value be in effect;\n     Ton0_delay & Ton0_rise; Ton1_delay & Ton1_rise -- in sec, set delay and soft-start timers for \n                channel0 and channel1. Initialization time is not modeled;\n     Toff0_delay & Toff0_fall; Toff1_delay & Toff1_fall -- in sec, set delay and soft-off timers for \n                channel0 and channel1;\n     Vout_0 & Vout_1 -- in volt, set output voltages respectively. Vout#_CFG pin needs to float \n                (or short to VDD25), to make the value be in effect;\n     Vout0_range & Vout1_range -- set maximum output range, with value 0\n                                                      for 5.5V; value 1 for 2.75V;\n     Iout0_fault & Iout1_fault -- in Amper, set maximum inductor peak current value, OC will be triggered \n                                               when the value is exceeded;\n     Iout0_warn & Iout1_warn -- in aMper, set the average load current maximum value, which will be used  \n                                                with Vout#_AVP to define the AVP operation;\n     Iout0_gain & Iout1_gain -- in Ohm, set sensing resistor or inductor DCR values used in the circuit;\n     Vout0_AVP & Vout1_AVP -- set the maximum value reference will reduce at Iout#_warn level:
TEXT 512 896 Left 2 !.tran 1m startup