Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\1fa77d6c4977_or_cmos.asc
* Generated by LTspice 26.0.1 for Windows.
M4 VOut 0 0 0 NMOS
V1 VDD 0 5
M3 VOut N002 0 0 NMOS
R2 VDD N001 1k
R1 VDD N004 1k
M5 Vf VOut N004 N004 PMOS
V2 N002 0 PULSE(0 5 0 0.000001 0.000001 0.0005 0.001 100)
M1 N003 N002 N001 N001 PMOS
M2 VOut 0 N003 N003 PMOS
M6 Vf VOut 0 0 NMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 0.01 0.00001
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 680
WIRE 288 -416 288 -448
WIRE -576 -368 -576 -432
WIRE 608 -336 608 -384
WIRE 288 -320 288 -336
WIRE 240 -304 -112 -304
WIRE -112 -224 -112 -304
WIRE -112 -224 -224 -224
WIRE 288 -224 288 -240
WIRE 608 -160 608 -256
WIRE 288 -144 288 -224
WIRE 560 -144 512 -144
WIRE 240 -128 64 -128
WIRE 64 -48 64 -128
WIRE 64 -48 -192 -48
WIRE 128 -48 64 -48
WIRE 608 -48 608 -64
WIRE 896 -48 608 -48
WIRE 608 -16 608 -48
WIRE 288 0 288 -48
WIRE 288 0 -16 0
WIRE 416 0 288 0
WIRE 512 0 512 -144
WIRE 512 0 416 0
WIRE 288 32 288 0
WIRE -16 48 -16 0
WIRE 512 64 512 0
WIRE 560 64 512 64
WIRE 128 112 128 -48
WIRE 240 112 128 112
WIRE -112 128 -112 -224
WIRE -64 128 -112 128
WIRE 288 144 288 128
WIRE 288 144 -16 144
WIRE 608 160 608 80
WIRE 288 176 288 144
SYMBOL res 592 -352 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL nmos 240 32 R0
SYMATTR InstName M4
SYMBOL voltage -576 -384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL pmos 560 -64 M180
SYMATTR InstName M5
SYMBOL pmos 240 -224 M180
SYMATTR InstName M1
SYMBOL pmos 240 -48 M180
SYMATTR InstName M2
SYMBOL voltage -224 -240 R0
WINDOW 3 -565 105 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 5 0 0.000001 0.000001 0.0005 0.001 100)
SYMATTR InstName V2
SYMBOL nmos 560 -16 R0
SYMATTR InstName M6
SYMBOL res 272 -432 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL nmos -64 48 R0
SYMATTR InstName M3
FLAG 288 176 0
FLAG -576 -288 0
FLAG -576 -432 VDD
FLAG 288 -448 VDD
FLAG -224 -144 0
FLAG 416 0 VOut
FLAG -192 32 0
FLAG -192 -48 0
FLAG 608 160 0
FLAG 608 -384 VDD
FLAG 896 -48 Vf
TEXT -256 200 Left 2 !.tran 0 0.01 0.00001
* Z:\home\khalils\Downloads\files\data\raw_asc\0ed43d3a80f0_Fig5_2.asc
* Generated by LTspice 26.0.1 for Windows.
Vr vr 0 1
R1 vr 0 rmod 10k L=5 W=100
.model rmod R RSH=500 TNOM=27 TC1=0.0024
.dc vr 0.9 1.1 1m
.temp 0 27 100
* Plot V(vr)/(-I(Vr)) to see the change in R\nUse Alt-double-click to enter this expression
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1064 696
WIRE 336 256 336 208
WIRE 336 400 336 336
WIRE 400 208 336 208
WIRE 464 208 400 208
WIRE 464 272 464 208
WIRE 464 400 464 352
FLAG 336 400 0
FLAG 464 400 0
FLAG 400 208 vr
SYMBOL voltage 336 240 R0
WINDOW 0 -76 56 Left 0
WINDOW 3 -74 85 Invisible 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vr
SYMATTR Value 1
SYMBOL res 448 256 R0
SYMATTR InstName R1
SYMATTR Value rmod 10k L=5 W=100
TEXT 184 448 Left 0 !.model rmod R RSH=500 TNOM=27 TC1=0.0024
TEXT 184 480 Left 0 !.dc vr 0.9 1.1 1m
TEXT 184 512 Left 0 !.temp 0 27 100
TEXT 224 144 Left 0 ;Plot V(vr)/(-I(Vr)) to see the change in R\nUse Alt-double-click to enter this expression
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3468-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3468-1.asy)
D1 N001 OUT D
C1 OUT 0 .1
R3 N002 IN 10K
K1 L1 L2 1
L2 0 N001 {20u*10.2*10.2} Rpar=1Meg
V1 IN 0 5
L1 IN N003 20 Rpar=2K Rser=.1
D2 0 N003 1N5817
C3 N001 0 10p
XU1 N003 0 N002 IN IN LT3468-1 ;pnba SW)GND)_Done)Charge)Vin
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10m startup
.lib LT3468-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2740 1752
WIRE 1872 1264 1648 1264
WIRE 2064 1264 1872 1264
WIRE 2368 1264 2112 1264
WIRE 2416 1264 2368 1264
WIRE 2528 1264 2480 1264
WIRE 2064 1280 2064 1264
WIRE 2112 1280 2112 1264
WIRE 1872 1296 1872 1264
WIRE 2368 1296 2368 1264
WIRE 2528 1296 2528 1264
WIRE 1648 1360 1648 1264
WIRE 1664 1360 1648 1360
WIRE 1760 1360 1744 1360
WIRE 2112 1376 2112 1360
WIRE 2368 1376 2368 1360
WIRE 2528 1376 2528 1360
WIRE 2064 1408 2064 1360
WIRE 2064 1408 1984 1408
WIRE 2064 1424 2064 1408
WIRE 1648 1456 1648 1360
WIRE 1760 1456 1648 1456
WIRE 1648 1472 1648 1456
WIRE 2064 1504 2064 1488
WIRE 1872 1536 1872 1520
WIRE 1648 1568 1648 1552
SYMBOL cap 2352 1296 R0
WINDOW 3 28 53 Left 2
SYMATTR Value 10p
SYMATTR InstName C3
SYMBOL ind2 2128 1376 R180
WINDOW 0 -3 72 Right 2
WINDOW 3 0 43 Right 2
SYMATTR InstName L2
SYMATTR Value {20u*10.2*10.2}
SYMATTR SpiceLine Rpar=1Meg
SYMBOL diode 2416 1280 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMBOL VOLTAGE 1648 1456 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL schottky 2048 1488 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMATTR Value 1N5817
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 2512 1296 R0
WINDOW 3 27 55 Left 2
SYMATTR Value .1
SYMATTR InstName C1
SYMBOL ind2 2048 1264 R0
WINDOW 0 -6 35 Right 2
WINDOW 3 -4 73 Right 2
SYMATTR InstName L1
SYMATTR Value 20
SYMATTR SpiceLine Rpar=2K Rser=.1
SYMBOL res 1760 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL PowerProducts\\LT3468-1 1872 1408 R0
SYMATTR InstName U1
FLAG 2528 1376 0
FLAG 1872 1536 0
FLAG 1648 1568 0
FLAG 2368 1376 0
FLAG 2112 1376 0
FLAG 2064 1504 0
FLAG 2528 1264 OUT
FLAG 1648 1264 IN
TEXT 2248 1448 Left 2 !.tran 10m startup
TEXT 2088 1264 Bottom 2 !K1 L1 L2 1
* Z:\home\khalils\Downloads\files\data\raw_asc\39e86ca57ff0_TPMOS2.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 40V
M1 N001 N002 0 0 BS170
V2 N002 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.model BS170 VDMOS(Rg=1.3 Vto=2 Rd=1.436 Rb=2.51m Kp=1.233m Lambda=0.0 Cgdmin=0.25n Cgdmax=7n Cgs=2.8n Cjo=1.89n VJ=.4519 Vds=30 Ron=8m Is=125f N=1.023 Rs=1.281 M=.3423 mfg=Alpha_&_Omega Qg=18n Tt=161.6n)
.dc V1 0 40 0.01 V2 list 0 1 2 3 4 5 6 7 8 9
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2388 680
WIRE 80 96 -96 96
WIRE -96 176 -96 96
WIRE 80 192 80 96
WIRE -144 256 -304 256
WIRE -304 304 -304 256
WIRE -304 432 -304 384
WIRE -96 432 -96 272
WIRE 80 432 80 272
SYMBOL voltage 80 176 R0
SYMATTR InstName V1
SYMATTR Value 40V
SYMBOL voltage -304 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL nmos -144 176 R0
SYMATTR InstName M1
SYMATTR Value BS170
FLAG -304 432 0
FLAG -96 432 0
FLAG 80 432 0
TEXT -432 496 Left 2 !.model BS170 VDMOS(Rg=1.3 Vto=2 Rd=1.436 Rb=2.51m Kp=1.233m Lambda=0.0 Cgdmin=0.25n Cgdmax=7n Cgs=2.8n Cjo=1.89n VJ=.4519 Vds=30 Ron=8m Is=125f N=1.023 Rs=1.281 M=.3423 mfg=Alpha_&_Omega Qg=18n Tt=161.6n)
TEXT -352 64 Left 2 !.dc V1 0 40 0.01 V2 list 0 1 2 3 4 5 6 7 8 9
* Z:\home\khalils\Downloads\files\data\raw_asc\0a6b04c06a8b_Draft1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N002 82k
R2 N001 Vin R
R3 Vin 0 R
R4 N002 0 9.1k
XU1 Vin Vout +9V -6V Vout -6V ADA4898 ;pnba In+)In-)V+)V-)OUT)SHDN
V1 0 -6V 6
V2 +9V 0 9
V3 N001 0 PULSE(0 1 1m 1n 1n 0.5m 1m 4)
R5 N001 0 49.9
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4898.asy)
.lib ADA4898.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 680
WIRE 336 -32 80 -32
WIRE 80 0 80 -32
WIRE 80 0 -32 0
WIRE 336 0 336 -32
WIRE 80 80 80 0
WIRE 208 80 80 80
WIRE -32 112 -32 0
WIRE 80 112 80 80
WIRE 208 112 208 80
WIRE 880 112 880 64
WIRE 336 128 336 80
WIRE 720 144 448 144
WIRE 208 224 208 192
WIRE 288 224 208 224
WIRE 544 224 544 208
WIRE 448 240 448 144
WIRE 528 240 448 240
WIRE 720 256 720 144
WIRE 720 256 592 256
WIRE 880 256 880 192
WIRE 880 256 816 256
WIRE -32 272 -32 192
WIRE 288 272 288 224
WIRE 400 272 288 272
WIRE 528 272 400 272
WIRE 80 288 80 192
WIRE 208 288 208 224
WIRE 816 288 816 256
WIRE 544 304 544 288
WIRE 576 304 576 288
WIRE 576 304 544 304
WIRE 880 304 880 256
WIRE 544 320 544 304
WIRE 80 400 80 368
WIRE 208 400 208 368
WIRE 208 400 80 400
WIRE 80 448 80 400
WIRE 880 448 880 384
FLAG 816 288 0
FLAG 880 64 +9V
FLAG 880 448 -6V
FLAG 544 320 -6V
FLAG 544 208 +9V
FLAG 80 448 0
FLAG -32 272 0
FLAG 336 128 0
FLAG 400 272 Vin
FLAG 720 256 Vout
SYMBOL res 64 96 R0
SYMATTR InstName R1
SYMATTR Value 82k
SYMBOL res 192 96 R0
SYMATTR InstName R2
SYMBOL res 192 272 R0
SYMATTR InstName R3
SYMBOL res 64 272 R0
SYMATTR InstName R4
SYMATTR Value 9.1k
SYMBOL OpAmps\\ADA4898 560 272 R0
SYMATTR InstName U1
SYMBOL voltage 880 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 6
SYMBOL voltage 880 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 9
SYMBOL voltage -32 96 R0
WINDOW 3 -53 -151 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 1m 1n 1n 0.5m 1m 4)
SYMBOL res 320 -16 R0
SYMATTR InstName R5
SYMATTR Value 49.9
* Z:\home\khalils\Downloads\files\data\raw_asc\0eb0c6eecc84_Demonstration_circuit_Step_ac_BF.asc
* Generated by LTspice 26.0.1 for Windows.
* Demonstration Circuit step BF of transistor
* Step AC Transistor BF
* plot FR for different BF
* copyright Cordell Audio 12/03/2010
;op
V3 Vin 0 SINE(0 0.1 1000 0 0 0 10) AC 1
R2 N001 Vout 2500
V1 N001 0 15
Q1 N002 Vin N003 0 2N5551C
R3 N003 N005 225
C1 N001 Vout 50pF
R1 N001 N002 2500
Q2 Vout 0 N004 0 2N5551C
I1 N005 N006 2mA
V2 0 N006 15
R4 N004 N005 225
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.ac dec 10 10k 1Meg
.step NPN 2N5551C (BF) 10 100 10
.include Cordell_Mods
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 764
WIRE 160 64 0 64
WIRE 272 64 160 64
WIRE 400 64 272 64
WIRE 0 112 0 64
WIRE 160 112 160 64
WIRE 272 112 272 64
WIRE 400 144 400 64
WIRE 160 208 160 192
WIRE 208 208 160 208
WIRE 272 208 272 176
WIRE 272 208 208 208
WIRE 0 256 0 192
WIRE 160 256 160 208
WIRE 400 288 400 224
WIRE 480 288 400 288
WIRE -128 304 -176 304
WIRE -64 304 -128 304
WIRE 400 304 400 288
WIRE 400 304 224 304
WIRE 480 304 480 288
WIRE 400 352 400 304
WIRE -176 368 -176 304
WIRE 0 384 0 352
WIRE 160 384 160 352
WIRE -176 496 -176 448
WIRE 0 496 0 464
WIRE 80 496 0 496
WIRE 160 496 160 464
WIRE 160 496 80 496
WIRE 80 512 80 496
WIRE 80 624 80 592
WIRE 400 624 400 432
WIRE 400 624 80 624
SYMBOL voltage 400 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 44 Left 0
WINDOW 3 40 79 Left 0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL npn -64 256 R0
WINDOW 3 26 40 Left 0
WINDOW 0 67 10 Left 0
SYMATTR Value 2N5551C
SYMATTR InstName Q1
SYMBOL voltage -176 352 R0
WINDOW 3 -327 107 Left 0
WINDOW 123 33 84 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 43 43 Left 0
SYMATTR Value SINE(0 0.1 1000 0 0 0 10)
SYMATTR Value2 AC 1
SYMATTR InstName V3
SYMBOL voltage 400 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 40 43 Left 0
WINDOW 3 43 76 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res -16 368 R0
SYMATTR InstName R3
SYMATTR Value 225
SYMBOL res -16 96 R0
WINDOW 0 38 31 Left 0
WINDOW 3 35 63 Left 0
SYMATTR InstName R1
SYMATTR Value 2500
SYMBOL res 144 368 R0
SYMATTR InstName R4
SYMATTR Value 225
SYMBOL cap 256 112 R0
WINDOW 3 33 46 Left 0
WINDOW 0 29 11 Left 0
SYMATTR Value 50pF
SYMATTR InstName C1
SYMBOL npn 224 256 M0
WINDOW 3 26 42 Left 0
WINDOW 0 68 13 Left 0
SYMATTR Value 2N5551C
SYMATTR InstName Q2
SYMBOL current 80 512 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 45 26 Left 0
WINDOW 3 33 64 Left 0
SYMATTR InstName I1
SYMATTR Value 2mA
SYMBOL res 144 96 R0
WINDOW 0 37 30 Left 0
WINDOW 3 36 62 Left 0
SYMATTR InstName R2
SYMATTR Value 2500
FLAG 480 304 0
FLAG -176 496 0
FLAG -128 304 Vin
FLAG 208 208 Vout
TEXT -584 96 Left 0 !;op
TEXT -584 128 Left 0 !.ac dec 10 10k 1Meg
TEXT -280 -104 Left 0 ;Demonstration Circuit step BF of transistor
TEXT -584 168 Left 0 !.step NPN 2N5551C (BF) 10 100 10
TEXT -184 -64 Left 0 ;Step AC Transistor BF
TEXT -184 -24 Left 0 ;plot FR for different BF
TEXT -584 64 Left 0 !.include Cordell_Mods
TEXT 104 720 Left 0 ;copyright Cordell Audio 12/03/2010
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1174-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1174-5.asy)
L1 N001 OUT 100 Rser=0.02 Rpar=5000
C2 OUT 0 100 Rser=0.02
V1 IN 0 9
XU1 OUT N003 N002 0 N001 IN IN IN LTC1174 top=93.5K bot=31.5K ;pnba FB)LBout)LBin)GND)SW)Vin)Ipgm)_SHDN
Rload OUT 0 20
D1 0 N001 MBRS140
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LTC1174.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1584 1140
WIRE 464 480 352 480
WIRE 624 480 464 480
WIRE 352 496 352 480
WIRE 624 512 624 480
WIRE 464 560 464 480
WIRE 496 560 464 560
WIRE 816 560 752 560
WIRE 864 560 816 560
WIRE 976 560 944 560
WIRE 1072 560 976 560
WIRE 816 576 816 560
WIRE 1072 576 1072 560
WIRE 352 592 352 576
WIRE 496 624 480 624
WIRE 768 624 752 624
WIRE 816 656 816 640
WIRE 1072 672 1072 656
WIRE 464 688 464 560
WIRE 496 688 464 688
WIRE 976 688 976 560
WIRE 976 688 752 688
WIRE 976 704 976 688
WIRE 624 752 624 736
WIRE 976 784 976 768
SYMBOL POLCAP 960 704 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL VOLTAGE 352 480 R0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL res 1056 560 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL PowerProducts\\LTC1174-5 624 624 R0
SYMATTR InstName U1
SYMBOL IND 848 576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL SCHOTTKY 800 640 M180
WINDOW 0 24 66 Left 2
WINDOW 3 26 7 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS140
FLAG 1072 560 OUT
FLAG 976 784 0
FLAG 1072 672 0
FLAG 816 656 0
FLAG 624 752 0
FLAG 352 592 0
FLAG 352 480 IN
TEXT 728 768 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\00ec25ef0cb3_cascode_current_mirror.asc
* Generated by LTspice 26.0.1 for Windows.
M3 0 N002 N003 N003 IRFH5207
V1 N001 0 5
V2 0 N005 5
M1 N004 N003 N005 N005 IRFH5207
I1 N001 N002 1m
M2 N003 N003 N005 N005 IRFH5207
M4 N002 N002 N004 N004 IRFH5207
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc I1 0m 1m 0.1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 -336 -80 -336
WIRE -80 -304 -80 -336
WIRE 112 -304 112 -336
WIRE 576 -192 400 -192
WIRE 112 -160 112 -224
WIRE 208 -160 112 -160
WIRE 576 -160 576 -192
WIRE 112 -112 112 -160
WIRE 400 -112 400 -192
WIRE 208 -32 208 -160
WIRE 208 -32 160 -32
WIRE 352 -32 208 -32
WIRE 400 0 400 -16
WIRE 400 0 288 0
WIRE 112 64 112 -16
WIRE 400 64 400 0
WIRE 288 144 288 0
WIRE 288 144 160 144
WIRE 352 144 288 144
WIRE 112 256 112 160
WIRE 288 256 112 256
WIRE 400 256 400 160
WIRE 400 256 288 256
WIRE 288 272 288 256
WIRE 288 384 288 352
SYMBOL nmos 352 -112 R0
SYMATTR InstName M3
SYMATTR Value IRFH5207
SYMBOL nmos 160 -112 M0
SYMATTR InstName M4
SYMATTR Value IRFH5207
SYMBOL nmos 352 64 R0
SYMATTR InstName M2
SYMATTR Value IRFH5207
SYMBOL voltage -80 -320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL current 112 -304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 1m
SYMBOL voltage 288 368 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL nmos 160 64 M0
SYMATTR InstName M1
SYMATTR Value IRFH5207
FLAG -80 -224 0
FLAG 288 384 0
FLAG 576 -160 0
TEXT -296 -40 Left 2 !.dc I1 0m 1m 0.1m
* Z:\home\khalils\Downloads\files\data\raw_asc\1294ef89fee4_HW05P01.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N002 0 12
E1 N001 0 N002 N003 100Meg
R1 N001 N003 12k
R2 N003 0 2k
R3 N001 N004 10k
VI0 N004 0 0
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 592 -32 320 -32
WIRE 736 -32 592 -32
WIRE 320 16 320 -32
WIRE 592 16 592 -32
WIRE 736 16 736 -32
WIRE 272 32 64 32
WIRE 272 80 224 80
WIRE 64 112 64 32
WIRE 224 128 224 80
WIRE 592 128 592 96
WIRE 592 128 224 128
WIRE 592 160 592 128
WIRE 736 160 736 96
WIRE 64 288 64 192
WIRE 400 288 64 288
WIRE 592 288 592 240
WIRE 592 288 400 288
WIRE 736 288 736 240
WIRE 736 288 592 288
FLAG 320 96 0
FLAG 400 288 0
DATAFLAG 432 -32 ""
SYMBOL voltage 64 96 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL e 320 0 R0
SYMATTR InstName E1
SYMATTR Value 100Meg
SYMBOL res 576 0 R0
SYMATTR InstName R1
SYMATTR Value 12k
SYMBOL res 576 144 R0
SYMATTR InstName R2
SYMATTR Value 2k
SYMBOL res 720 0 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL voltage 736 144 R0
SYMATTR InstName I0
SYMATTR Value 0
TEXT 840 280 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1963A-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1963A-3.3.asy)
XU1 IN IN 0 OUT OUT LT1963-3.3 ;pnba _SHDN)IN)GND)OUT)SENSE
V1 IN 0 PWL(0 0 1 10)
Rload OUT 0 1K
C1 OUT 0 1
.tran 1
.lib LT1963.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL PowerProducts\\LT1963A-3.3 176 96 R0
SYMATTR InstName U1
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG 512 48 OUT
FLAG -208 48 IN
TEXT 400 232 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3620.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N001 0 0 NC_01 MP_02 N002 IN IN LTC3620 ;pnba SW)GND)Fmin/Mode)LoBatB))FB)Run)Vin
V1 IN 0 3.6
L1 N001 OUT 22 Rpar=10K
R1 OUT N002 432K
R2 N002 0 523K
C1 OUT N002 22p
C2 OUT 0 1
Rload OUT 0 100
.tran 1m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3620.asy)
.lib LTC3620.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 96 16 96
WIRE 256 96 112 96
WIRE 16 112 16 96
WIRE 256 112 256 96
WIRE 112 160 112 96
WIRE 128 160 112 160
WIRE 16 208 16 192
WIRE 128 256 112 256
WIRE 416 256 384 256
WIRE 528 256 496 256
WIRE 624 256 528 256
WIRE 704 256 624 256
WIRE 784 256 704 256
WIRE 528 272 528 256
WIRE 624 272 624 256
WIRE 704 272 704 256
WIRE 784 272 784 256
WIRE 128 352 112 352
WIRE 528 352 384 352
WIRE 624 352 624 336
WIRE 624 352 528 352
WIRE 528 368 528 352
WIRE 704 368 704 336
WIRE 784 368 784 352
WIRE 528 464 528 448
FLAG 16 208 0
FLAG 112 256 0
FLAG 112 352 0
FLAG 528 464 0
FLAG 704 368 0
FLAG 784 368 0
FLAG 16 96 IN
FLAG 784 256 OUT
SYMBOL LTC3620 256 256 R0
SYMATTR InstName U1
SYMBOL voltage 16 96 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL ind 400 272 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 22
SYMATTR SpiceLine Rpar=10K
SYMBOL res 512 256 R0
SYMATTR InstName R1
SYMATTR Value 432K
SYMBOL res 512 352 R0
SYMATTR InstName R2
SYMATTR Value 523K
SYMBOL cap 608 272 R0
SYMATTR InstName C1
SYMATTR Value 22p
SYMBOL cap 688 272 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 768 256 R0
SYMATTR InstName Rload
SYMATTR Value 100
TEXT 672 440 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\902661a52717_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
T1 IN 0 0 OUT Td=50n Z0=50
T2 0 0 OUT 0 Td=30n Z0=150
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
.tran 0 500n 0 1n
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.