* Z:\home\khalils\Downloads\files\data\raw_asc\56f41dfd2274_Logic-gates-transistors-BJTs.asc
* Generated by LTspice 26.0.1 for Windows.
* NAND gate
* AND gate
* OR gate
* Logic gates with NPN transistors
* NOR gate
R8 N007 Signal_1 10k
R7 Vcc NAND_out 4.7k
Q7 NOR_out N006 0 0 2N3904
Q2 N003 N005 AND_out 0 2N3904
Q3 Vcc N001 OR_out 0 2N3904
Q4 Vcc N004 OR_out 0 2N3904
R4 OR_out 0 4.7k
R1 AND_out 0 4.7k
Q6 N008 N009 0 0 2N3904
V3 Signal_2 0 PULSE(0 12 0.5 1n 1n 1 2 1)
R12 Vcc NOR_out 4.7k
Q5 NAND_out N007 N008 0 2N3904
R9 N009 Signal_2 10k
V1 Vcc 0 12
R5 N001 Signal_1 10k
R2 N002 Signal_1 10k
V2 Signal_1 0 PULSE(0 12 0 1n 1n 1 2 1)
R10 N006 Signal_1 10k
R11 N006 Signal_2 10k
R3 N005 Signal_2 10k
R6 N004 Signal_2 10k
Q1 Vcc N002 N003 0 2N3904
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 3
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1140 1492
WIRE -208 -80 -208 -112
WIRE -64 -80 -64 -96
WIRE 272 -80 272 -96
WIRE -208 32 -208 0
WIRE -64 32 -64 0
WIRE 272 32 272 0
WIRE 800 224 800 192
WIRE 160 272 160 240
WIRE 608 272 496 272
WIRE 736 272 688 272
WIRE -32 320 -112 320
WIRE 96 320 48 320
WIRE 896 320 800 320
WIRE 800 416 800 400
WIRE 160 432 160 368
WIRE 608 464 496 464
WIRE 736 464 688 464
WIRE -32 480 -112 480
WIRE 96 480 48 480
WIRE 800 528 800 512
WIRE 896 528 896 320
WIRE 896 528 800 528
WIRE 992 528 896 528
WIRE 160 560 160 528
WIRE 272 560 160 560
WIRE 800 560 800 528
WIRE 160 576 160 560
WIRE 800 688 800 640
WIRE 160 704 160 656
WIRE 160 928 160 880
WIRE 816 976 816 880
WIRE 160 1056 160 1008
WIRE 272 1056 160 1056
WIRE 160 1088 160 1056
WIRE 608 1088 528 1088
WIRE 720 1088 688 1088
WIRE 816 1088 816 1056
WIRE 912 1088 816 1088
WIRE 816 1120 816 1088
WIRE -32 1136 -112 1136
WIRE 96 1136 48 1136
WIRE 720 1168 720 1088
WIRE 752 1168 720 1168
WIRE 160 1248 160 1184
WIRE 608 1248 528 1248
WIRE 720 1248 720 1168
WIRE 720 1248 688 1248
WIRE -32 1296 -112 1296
WIRE 96 1296 48 1296
WIRE 816 1312 816 1216
WIRE 160 1392 160 1344
RECTANGLE Normal 400 736 -256 128 2
RECTANGLE Normal 1136 736 400 128 2
RECTANGLE Normal 400 1488 -256 736 2
RECTANGLE Normal 1136 1488 400 736 2
SYMBOL res 800 960 R0
SYMATTR InstName R12
SYMATTR Value 4.7k
SYMBOL res 64 1120 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 10k
SYMBOL res 64 1280 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 10k
SYMBOL npn 736 224 R0
SYMATTR InstName Q3
SYMATTR Value 2N3904
SYMBOL res 64 464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 704 1072 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 10k
SYMBOL res 144 912 R0
SYMATTR InstName R7
SYMATTR Value 4.7k
SYMBOL voltage 272 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 12 0.5 1n 1n 1 2 1)
SYMBOL npn 736 416 R0
SYMATTR InstName Q4
SYMATTR Value 2N3904
SYMBOL npn 96 1248 R0
SYMATTR InstName Q6
SYMATTR Value 2N3904
SYMBOL npn 96 432 R0
SYMATTR InstName Q2
SYMATTR Value 2N3904
SYMBOL res 784 544 R0
SYMATTR InstName R4
SYMATTR Value 4.7k
SYMBOL voltage -208 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL npn 96 272 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL res 64 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 704 256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10k
SYMBOL npn 96 1088 R0
SYMATTR InstName Q5
SYMATTR Value 2N3904
SYMBOL res 704 1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 10k
SYMBOL voltage -64 -96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 12 0 1n 1n 1 2 1)
SYMBOL npn 752 1120 R0
SYMATTR InstName Q7
SYMATTR Value 2N3904
SYMBOL res 704 448 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 10k
SYMBOL res 144 560 R0
SYMATTR InstName R1
SYMATTR Value 4.7k
FLAG -64 32 0
FLAG -208 32 0
FLAG -208 -112 Vcc
FLAG 272 32 0
FLAG -64 -96 Signal_1
FLAG 272 -96 Signal_2
FLAG 160 704 0
FLAG 160 240 Vcc
FLAG 800 688 0
FLAG 800 192 Vcc
FLAG -112 320 Signal_1
FLAG -112 480 Signal_2
FLAG 496 464 Signal_2
FLAG 496 272 Signal_1
FLAG 800 400 Vcc
FLAG 160 1392 0
FLAG 160 880 Vcc
FLAG -112 1136 Signal_1
FLAG -112 1296 Signal_2
FLAG 272 1056 NAND_out
FLAG 272 560 AND_out
FLAG 992 528 OR_out
FLAG 528 1088 Signal_1
FLAG 528 1248 Signal_2
FLAG 816 1312 0
FLAG 816 880 Vcc
FLAG 912 1088 NOR_out
TEXT 688 0 Left 2 !.tran 3
TEXT -224 768 Left 2 ;NAND gate
TEXT -208 160 Left 2 ;AND gate
TEXT 448 152 Left 2 ;OR gate
TEXT 200 -304 Left 4 ;Logic gates with NPN transistors
TEXT 448 792 Left 2 ;NOR gate