Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1762-0.95.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1762-0.95.asy)
C4 OUT 0 10
R2 N001 IN 50K
V1 IN 0 1.3
C3 N002 0 1
C2 N003 0 10n
R1 OUT 0 1
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1762 Radj=6333.33 ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
C1 N004 0 1
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value 1
SYMBOL voltage -128 -32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.3
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL ADP1762-0.95 224 176 R0
SYMATTR InstName U1
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 432 384 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\05dae5b29fbe_pmos_sweep.asc
* Generated by LTspice 26.0.1 for Windows.
* LTspice doesn't support\nNF=5 rgeomod=1 geomod=0
* RighMouseClick for specific dialog\nCtrl-RightMouseClick for full SPICE dialog
Vds 0 s -1.2
Vgs g s -1
M1 0 g s s PMOS l=0.09u w=10.0u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc vds 0 -1.2 -.01 vgs 0 -1.2 -0.2
.include modelcard.pmos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 -64 32 -64
WIRE 416 -64 208 -64
WIRE 32 -16 32 -64
WIRE 208 32 208 -64
WIRE 416 48 416 -64
WIRE 208 96 208 32
WIRE 224 96 208 96
WIRE 32 112 32 64
WIRE 128 112 32 112
WIRE 160 112 128 112
WIRE 224 144 224 96
WIRE 224 144 208 144
WIRE 208 240 208 192
WIRE 416 240 416 128
SYMBOL pmos4 160 192 M180
WINDOW 3 79 72 Left 0
WINDOW 123 79 44 Left 0
SYMATTR InstName M1
SYMATTR Value2 l=0.09u w=10.0u
SYMBOL voltage 32 80 M180
WINDOW 0 24 104 Left 0
WINDOW 3 24 16 Left 0
SYMATTR InstName Vgs
SYMATTR Value -1
SYMBOL voltage 416 144 M180
WINDOW 0 24 104 Left 0
WINDOW 3 24 16 Left 0
SYMATTR InstName Vds
SYMATTR Value -1.2
FLAG 208 240 0
FLAG 416 240 0
FLAG 128 112 g
FLAG 208 32 s
TEXT 16 -152 Left 0 !.dc vds 0 -1.2 -.01 vgs 0 -1.2 -0.2
TEXT 16 -200 Left 0 !.include modelcard.pmos
TEXT 24 304 Left 0 ;LTspice doesn't support\nNF=5 rgeomod=1 geomod=0
TEXT 16 384 Left 0 ;RighMouseClick for specific dialog\nCtrl-RightMouseClick for full SPICE dialog
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX40023.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX40023.asy)
RL OUT 0 10k
XU1 IN OUT Vcc Vee OUT Vcc MAX40023 ;pnba In+)In-)V+)V-)OUT)SHDN
Vee 0 Vee 1.5
V1 IN 0 SINE(0 50m 1k)
CL OUT 0 15p
Vcc Vcc 0 1.5
.tran 1m
.lib MAX40023.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1720 800
WIRE 624 256 304 256
WIRE 64 288 64 272
WIRE 416 352 416 320
WIRE 304 368 304 256
WIRE 400 368 304 368
WIRE 624 384 624 256
WIRE 624 384 464 384
WIRE 720 384 624 384
WIRE 64 400 64 368
WIRE 64 400 32 400
WIRE 400 400 304 400
WIRE 32 416 32 400
WIRE 624 416 624 384
WIRE 720 432 720 384
WIRE 64 448 64 400
WIRE 416 448 416 416
WIRE 448 448 448 416
WIRE 304 496 304 400
WIRE 624 528 624 496
WIRE 720 528 720 496
WIRE 64 544 64 528
WIRE 304 592 304 576
SYMBOL MAX40023 432 400 R0
SYMATTR InstName U1
SYMBOL voltage 64 432 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vee
SYMATTR Value 1.5
SYMBOL res 608 400 R0
SYMATTR InstName RL
SYMATTR Value 10k
SYMBOL voltage 64 272 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName Vcc
SYMATTR Value 1.5
SYMBOL voltage 304 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 50m 1k)
SYMBOL cap 704 432 R0
SYMATTR InstName CL
SYMATTR Value 15p
FLAG 720 384 OUT
FLAG 64 272 Vcc
FLAG 64 544 Vee
FLAG 416 320 Vcc
FLAG 416 448 Vee
FLAG 32 416 0
FLAG 304 592 0
FLAG 624 528 0
FLAG 304 400 IN
FLAG 720 528 0
FLAG 448 448 Vcc
TEXT 16 632 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG1534.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\nSwitch shown for a logic 0 input\nQinj not included in the model\nOnly one channel is modeled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG1534.asy)
V2 -V 0 -8
XU1 vIN vSA vD vSB 0 -V 0 +V ADG1534 ;pnba IN)SA)D)SB)EN)Vss)GND)Vdd
V4 vIN 0 PULSE(0 1.8 0 20n 20n 10u 20u)
R1 vD 0 301
C1 vD 0 36p
V1 +V 0 5
V6 vSB 0 -8
V5 vSA 0 2.5
.tran 120u
.lib ADG1534.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2844 1336
WIRE -800 -320 -800 -352
WIRE -1488 -256 -1488 -272
WIRE -1376 -256 -1376 -272
WIRE -928 -256 -960 -256
WIRE -896 -256 -928 -256
WIRE -672 -224 -704 -224
WIRE -640 -224 -672 -224
WIRE -560 -224 -640 -224
WIRE -928 -192 -1040 -192
WIRE -896 -192 -928 -192
WIRE -640 -192 -640 -224
WIRE -560 -176 -560 -224
WIRE -1488 -160 -1488 -176
WIRE -1376 -160 -1376 -176
WIRE -1200 -128 -1248 -128
WIRE -928 -128 -1120 -128
WIRE -896 -128 -928 -128
WIRE -640 -96 -640 -112
WIRE -560 -96 -560 -112
WIRE -896 -64 -928 -64
WIRE -864 16 -864 -16
WIRE -736 16 -736 -16
SYMBOL voltage -1376 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -8
SYMBOL voltage -1488 -272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL ADG1534 -800 -176 R0
SYMATTR InstName U1
SYMBOL cap -576 -176 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -944 -256 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 2.5
SYMBOL voltage -1104 -128 M270
WINDOW 3 -45 209 VLeft 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 44 74 VLeft 2
SYMATTR Value PULSE(0 1.8 0 20n 20n 10u 20u)
SYMATTR InstName V4
SYMBOL voltage -1024 -192 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value -8
SYMBOL res -656 -208 R0
SYMATTR InstName R1
SYMATTR Value 301
FLAG -1376 -160 0
FLAG -1488 -160 0
FLAG -1488 -272 +V
FLAG -1376 -272 -V
FLAG -1248 -128 0
FLAG -1040 -256 0
FLAG -1120 -192 0
FLAG -800 -352 +V
FLAG -736 16 0
FLAG -864 16 -V
FLAG -640 -96 0
FLAG -560 -96 0
FLAG -928 -64 0
FLAG -928 -256 vSA
FLAG -928 -192 vSB
FLAG -928 -128 vIN
FLAG -672 -224 vD
TEXT -1496 -72 Left 2 !.tran 120u
TEXT -1496 -480 Left 2 ;Notes:\nSwitch shown for a logic 0 input\nQinj not included in the model\nOnly one channel is modeled
* Z:\home\khalils\Downloads\files\data\raw_asc\1a1901a8cf10_StageB_LowPassSallenKey_LT1490A.asc
* Generated by LTspice 26.0.1 for Windows.
* This subcircuit is not simulatable. \nPlease open one of the \n"Filter Design*.asc" schematics to \nsimulate your Filter Wizard design.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1490A.asy)
C1 OUT N001 22n
C2 N002 REF 10n
R1 N001 IN 3.9k
XU1 N002 OUT V+ V- OUT LT1490A ;pnba In+)In-)V+)V-)OUT
R3 N002 P001 520
R2 P001 N001 6.8k
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 4112 860
WIRE 512 -128 240 -128
WIRE 320 112 320 -32
WIRE 240 128 240 -128
WIRE 288 128 288 112
WIRE 288 128 240 128
WIRE 304 128 288 128
WIRE 512 144 512 -128
WIRE 512 144 352 144
WIRE -160 160 -176 160
WIRE -128 160 -160 160
WIRE -16 160 -48 160
WIRE 16 160 -16 160
WIRE 240 160 176 160
WIRE 288 160 240 160
WIRE 304 160 288 160
WIRE 512 160 512 144
WIRE 576 160 512 160
WIRE 608 160 576 160
WIRE 288 176 288 160
WIRE 240 192 240 160
WIRE 240 272 240 256
WIRE 320 336 320 176
WIRE -16 400 -16 160
WIRE 176 400 -16 400
WIRE 512 400 512 160
WIRE 512 400 240 400
SYMBOL cap 240 384 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 22n
SYMBOL res 192 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 520
SYMBOL Opamps\\LT1490A 320 80 R0
SYMATTR InstName U1
SYMBOL res -32 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 3.9k
SYMBOL res 112 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 6.8k
SYMBOL cap 224 192 R0
SYMATTR InstName C2
SYMATTR Value 10n
FLAG 320 -32 V+
FLAG 320 336 V-
FLAG 576 160 OUT
FLAG -160 160 IN
FLAG 240 272 REF
TEXT -176 504 Left 4 ;This subcircuit is not simulatable.  \nPlease open one of the \n"Filter Design*.asc" schematics to \nsimulate your Filter Wizard design.
* Z:\tmp\asc_dec_bjh7r6w2\0a2292c5498b_Interview01_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
D3 N010 N004 PTZ6_8B
V1 N001 N009 10
D1 N007 N002 STZ5_6N
Q2 N005 N006 N008 0 BCW60A
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1808 1000
WIRE -48 128 -96 128
WIRE 80 128 80 96
WIRE 80 128 32 128
WIRE 288 128 80 128
WIRE -96 192 -96 128
WIRE 288 272 288 240
WIRE 496 272 288 272
WIRE 656 272 496 272
WIRE 496 288 496 272
WIRE 784 288 784 128
WIRE 288 400 288 272
WIRE 656 400 656 272
WIRE 80 416 80 128
WIRE 496 448 496 368
WIRE 592 448 496 448
WIRE 784 464 784 368
WIRE 496 512 496 448
WIRE 656 512 656 496
WIRE 720 512 656 512
WIRE 288 544 288 464
WIRE 784 576 784 560
WIRE -96 656 -96 272
WIRE 288 656 288 608
WIRE 288 656 80 656
WIRE 496 656 496 576
WIRE 496 656 288 656
WIRE 784 656 496 656
SYMBOL zener 512 576 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMATTR Value PTZ6_8B
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL voltage -96 176 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL zener 304 464 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value STZ5_6N
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL npn 720 464 R0
SYMATTR InstName Q2
SYMATTR Value BCW60A
FLAG 80 96 c
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1219.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 5
V3 IN 0 SINE(2.5 2.5 1K)
XU1 IN OUT +V 0 OUT NC_01 LT1219 ;pnba In+)In-)V+)V-)OUT)SHDN
C1 OUT 0 .1
.tran 3m
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1219.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 368 16 128 16
WIRE -160 96 -160 80
WIRE 192 96 192 80
WIRE 128 144 128 16
WIRE 160 144 128 144
WIRE 368 176 368 16
WIRE 368 176 304 176
WIRE 432 176 368 176
WIRE -160 192 -160 176
WIRE 368 192 368 176
WIRE 160 208 16 208
WIRE 16 240 16 208
WIRE 192 272 192 256
WIRE 368 272 368 256
WIRE 16 336 16 320
FLAG -160 192 0
FLAG 192 80 +V
FLAG -160 80 +V
FLAG 16 336 0
FLAG 192 272 0
FLAG 368 272 0
FLAG 432 176 OUT
FLAG 16 208 IN
SYMBOL voltage -160 80 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 16 224 R0
SYMATTR InstName V3
SYMATTR Value SINE(2.5  2.5 1K)
SYMBOL opamps\\LT1219 192 176 R0
SYMATTR InstName U1
SYMBOL cap 352 192 R0
SYMATTR InstName C1
SYMATTR Value .1
TEXT 416 312 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\902661a52717_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T1 IN 0 0 OUT Td=50n Z0=50
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T2 0 0 OUT 0 Td=30n Z0=150
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7102-9.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7102-9.0.asy)
Rload OUT 0 50
R1 OUT N001 100k
XU1 IN OUT IN N001 OUT 0 ADP7102 Vref=9 ;pnba Vin)Sense)EN)PG)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
V1 IN 0 10
.tran 3m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -16 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -16 48 -16 32
WIRE 384 128 352 128
WIRE 464 128 464 32
WIRE 464 128 384 128
WIRE 560 128 464 128
WIRE -16 144 -16 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 384 224 384 128
WIRE 384 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
SYMBOL voltage -16 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL ADP7102-9.0 224 128 R0
SYMATTR InstName U1
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
FLAG 224 304 0
FLAG -16 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -16 32 IN
FLAG 560 128 OUT
TEXT 432 296 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1377.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1377.asy)
C3 0 N005 .0047
R3 N004 N005 2K
L1 IN N001 4.7 Rser=0.02 Rpar=5000
V1 IN 0 5
R1 OUT N003 53.6K
D1 N001 OUT MBRS340
C4 0 N004 .047
XU1 N005 N003 N006 N002 IN MP_01 0 N001 LT1377 ;pnba Vc)FB)NFB)_SHDN)Vin))GND)SW
Rload OUT 0 50
R2 N003 0 6.19K
C2 OUT 0 22 Rser=.05
C5 OUT 0 .1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 1.5m startup
.lib LT1377.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2820 1384
WIRE 1824 864 1584 864
WIRE 1888 864 1824 864
WIRE 2016 864 1968 864
WIRE 2064 864 2016 864
WIRE 2192 864 2128 864
WIRE 2304 864 2192 864
WIRE 2384 864 2304 864
WIRE 2464 864 2384 864
WIRE 1584 880 1584 864
WIRE 2304 880 2304 864
WIRE 2384 880 2384 864
WIRE 2464 880 2464 864
WIRE 1824 928 1824 864
WIRE 1584 976 1584 960
WIRE 2192 976 2192 864
WIRE 2304 976 2304 944
WIRE 2384 976 2384 944
WIRE 2464 976 2464 960
WIRE 1680 992 1664 992
WIRE 2016 992 2016 864
WIRE 2016 992 1968 992
WIRE 2192 1072 2192 1056
WIRE 2192 1072 1968 1072
WIRE 2192 1088 2192 1072
WIRE 1504 1152 1456 1152
WIRE 1616 1152 1584 1152
WIRE 1680 1152 1616 1152
WIRE 2000 1152 1968 1152
WIRE 1456 1184 1456 1152
WIRE 1616 1184 1616 1152
WIRE 2192 1184 2192 1168
WIRE 1824 1232 1824 1216
WIRE 1456 1264 1456 1248
WIRE 1616 1264 1616 1248
SYMBOL schottky 2064 880 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMBOL RES 2448 864 R0
SYMATTR InstName Rload
SYMATTR Value 50
SYMBOL RES 2176 960 R0
SYMATTR InstName R1
SYMATTR Value 53.6K
SYMBOL RES 2176 1072 R0
SYMATTR InstName R2
SYMATTR Value 6.19K
SYMBOL RES 1488 1168 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 2K
SYMBOL polcap 2288 880 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine Rser=.05
SYMBOL CAP 2368 880 R0
SYMATTR InstName C5
SYMATTR Value .1
SYMBOL CAP 1440 1248 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C4
SYMATTR Value .047
SYMBOL VOLTAGE 1584 864 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL IND 1872 880 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL CAP 1600 1248 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C3
SYMATTR Value .0047
SYMBOL POWERPRODUCTS\\LT1377 1824 1072 R0
SYMATTR InstName U1
FLAG 2464 864 OUT
FLAG 2192 1184 0
FLAG 2304 976 0
FLAG 2464 976 0
FLAG 1456 1264 0
FLAG 1824 1232 0
FLAG 1584 976 0
FLAG 1616 1264 0
FLAG 2384 976 0
FLAG 1584 864 IN
TEXT 2112 1248 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8669.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8669.asy)
XU1 IN N001 +V -V OUT AD8669 ;pnba In+)In-)V+)V-)OUT
Rload OUT 0 10K
R1 N001 0 10K
V1 +V 0 5
Vin IN 0 SINE(0 1 10K)
R2 OUT N001 10K
V2 -V 0 -5
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 416 -1232 400 -1232
WIRE 528 -1232 496 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 128 -1152 128 -1168
WIRE 240 -1152 240 -1168
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 768 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 768 -1088 768 -1104
WIRE 432 -1072 432 -1088
WIRE 128 -1056 128 -1072
WIRE 240 -1056 240 -1072
WIRE 768 -992 768 -1008
WIRE 432 -976 432 -992
SYMBOL res 512 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 128 -1168 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL Opamps\\AD8669 576 -1168 R0
SYMATTR InstName U1
SYMBOL res 752 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 240 -1168 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
FLAG 432 -976 0
FLAG 768 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 576 -1072 -V
FLAG 400 -1232 0
FLAG 768 -992 0
FLAG 128 -1168 +V
FLAG 128 -1056 0
FLAG 240 -1168 -V
FLAG 240 -1056 0
TEXT 784 -896 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\871e0f26f33d_esquematico_circuitos2-regulacion_de_carga.asc
* Generated by LTspice 26.0.1 for Windows.
Q5 N003 N003 N001 0 2N3906
vin ivin 0
Iload vo 0 I
R1 N007 0 4k
R5 ivin N002 1k
QMI_TRANSISTOR N004 N005 vo 0 NPN
R3 vo 0 3.33
R2 vo N007 1k
R4 N008 0 10k
QMI_TRANSISTOR2 vo N004 ivin 0 PNP
vref N006 0 4
R6 ivin N001 1k
Q6 N005 N003 N002 0 2N3906
Q1 N003 N006 N008 0 2N3904
Q4 N005 N007 N008 0 2N3904
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.MODEL MI_TRANSISTOR NPN ( BF=50)
.MODEL MI_TRANSISTOR2 PNP ( BF=50)
.DC vin 12 30 0.01
.step param Iload list 0 0.1 0.5 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1532 680
WIRE -112 -400 -320 -400
WIRE 112 -400 -112 -400
WIRE 448 -400 112 -400
WIRE -112 -288 -112 -320
WIRE 112 -288 112 -320
WIRE 448 -256 448 -400
WIRE 0 -240 -48 -240
WIRE 48 -240 0 -240
WIRE -320 -224 -320 -400
WIRE 384 -208 272 -208
WIRE 272 -160 272 -208
WIRE -112 -144 -112 -192
WIRE 0 -144 0 -240
WIRE 0 -144 -112 -144
WIRE 112 -112 112 -192
WIRE 208 -112 112 -112
WIRE 448 -64 448 -160
WIRE 448 -64 272 -64
WIRE 448 -32 448 -64
WIRE 464 -32 448 -32
WIRE -112 16 -112 -144
WIRE 112 16 112 -112
WIRE -176 64 -272 64
WIRE 240 64 176 64
WIRE 320 64 240 64
WIRE 464 64 464 -32
WIRE 464 64 400 64
WIRE -272 112 -272 64
WIRE 0 112 -112 112
WIRE 112 112 0 112
WIRE 464 112 464 64
WIRE 608 112 464 112
WIRE 464 128 464 112
WIRE 240 144 240 64
WIRE 0 160 0 112
WIRE -272 224 -272 192
WIRE 608 240 608 192
WIRE 464 256 464 208
WIRE 464 256 608 240
SYMBOL res 448 112 R0
SYMATTR InstName R3
SYMATTR Value 3.33
SYMBOL res -16 144 R0
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL pnp -48 -192 R180
SYMATTR InstName Q5
SYMATTR Value 2N3906
SYMBOL voltage -320 -240 R0
WINDOW 3 24 44 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vin
SYMATTR Value ""
SYMBOL res 96 -416 R0
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL pnp 384 -160 M180
SYMATTR InstName MI_TRANSISTOR2
SYMBOL npn 208 -160 R0
SYMATTR InstName MI_TRANSISTOR
SYMBOL npn 176 16 M0
SYMATTR InstName Q4
SYMATTR Value 2N3904
SYMBOL pnp 48 -192 M180
SYMATTR InstName Q6
SYMATTR Value 2N3906
SYMBOL npn -176 16 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL voltage -272 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vref
SYMATTR Value 4
SYMBOL res 224 128 R0
SYMATTR InstName R1
SYMATTR Value 4k
SYMBOL res -128 -416 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL res 416 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL current 608 112 R0
SYMATTR InstName Iload
FLAG 240 224 0
FLAG 464 256 0
FLAG 0 240 0
FLAG -272 224 0
FLAG -320 -144 0
FLAG 464 64 vo
FLAG -320 -400 ivin
TEXT 80 -504 Left 2 !.MODEL MI_TRANSISTOR NPN ( BF=50)
TEXT 616 -480 Left 2 !.MODEL MI_TRANSISTOR2 PNP ( BF=50)
TEXT -592 -232 Left 2 !.DC vin 12 30 0.01
TEXT 560 48 Left 2 !.step param Iload list 0 0.1 0.5 1