* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4700.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 12
C1 OUT1 0 330 X2 Rser=5m
R1 OUT1 0 20m
C2 OUT1 0 100 X3 Rser=5m
C3 OUT0 0 330 X2 Rser=5m
R2 OUT0 0 30m
C4 OUT0 0 100 X3 Rser=5m
C5 0 N003 1n
C6 0 N002 1n
R3 N006 N007 10K
R4 N004 N007 10K
R5 N005 N007 4.99K
XU1 OUT0 0 N001 OUT1 NC_01 N003 N001 OUT0 NC_02 NC_03 N005 NC_04 0 NC_05 NC_06 0 N006 N004 NC_07 N001 NC_08 NC_09 NC_10 NC_11 NC_12 NC_13 NC_14 N007 N002 NC_15 0 OUT1 LTM4700 VIN_ON=5.5 VIN_OFF=5 Vout_0=1.5 Vout_1=1 Ilim0_range=1 Ilim1_range=1 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0 Freq=500K PHs_0=0 PHs_1=180 Ton0_delay=.3m Ton0_rise=.5m Ton1_delay=.3m Ton1_rise=.5m Toff0_delay=.2m Toff0_fall=.3m Toff1_delay=.2m Toff1_fall=.3m Vout0_range=0 Vout1_range=0 ;pnba Vosns0+)Vosns0-)Vin1)Vout1)Comp0a)Comp0b)SVin)Vout0)Vtrim0_cfg)Vtrim1_cfg)SYNC)Runp)SGND)PGood0)SW0)PGND)Run0)Run1)Vbias)Vin0)Vout0_cfg)Vout1_cfg)IntVcc)Fswph_cfg)VDD25)SW1)PGood1)VDD33)Comp1b)Comp1a)Vosns1-)Vosns1+
* Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time related parameters.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LTM4700. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope discribed in the datasheet, the resulting simulation outcomes are not meaningful.\n \n VIN_ON & VIN_OFF -- in volts, set the unit start/stop input voltages;\n Freq -- in Hz, sets switching frequency as one of values of 250K, 350K, \n 425K, 500K, 575K, 650K, 750K, 1000K. FSWPH_CFG pin needs to float \n (or short to VDD25), to make the value be in effect;\n PHs_0 & PHs_1 -- in degree, set phase angle related to SYNC signal. \n Certain combinations are restricted as in datasheet. FSWPH_CFG \n pin needs to float (or short to VDD25), to make the value be in effect;\n Ton0_delay & Ton0_rise; Ton1_delay & Ton1_rise -- in sec, set delay and soft-start timers for \n channel0 and channel1. Initialization time is not modeled;\n Toff0_delay & Toff0_fall; Toff1_delay & Toff1_fall -- in sec, set delay and soft-off timers for \n channel0 and channel1;\n Vout_0 & Vout_1 -- in volt, set output voltages respectively;\n Vout0_range & Vout1_range -- set maximum output range, with value 0\n for 4.096V (CH0) and 5.5V (CH1); value 1\n for 2.75V\n Ilim0_range & Ilim1_range -- set maximum sensed peak current range, with value 0\n for low, and 1 for high;\n OC_limit0 & OC_limit1 -- set ratio of peak current limit to the maximum value defined\n by Ilimit_range. It must be one of values: 0.5, 0.572, 0.642, \n 0.714, 0.786, 0.858, 0.928, 1;\n Mode_II -- sets light load operation mode: 0 for discontinuous, 1 for forced continuous;\n Fault_response -- sets the response mode of the unit to occuring faults:\n 0 for ignore, 1 for latch up, 2 for Hiccup after Retry_delay time;\n Retry_delay -- in sec, sets the timer before the unit turns on after a fault;\n gm -- transconductance of the error amplifier. It must be between 1m mho and 5.73m mho;\n Rth -- Compensation resistor. It must be set between 0k ohms and 62k ohms;\n Sync - value 0 for configuring module as Master, value 1 for Slave
.tran 1.2m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4700.asy)
.lib LTM4700.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1888 1196
WIRE -64 -560 -208 -560
WIRE 48 -560 -64 -560
WIRE 544 -560 48 -560
WIRE -208 -544 -208 -560
WIRE 48 -512 48 -560
WIRE 240 -512 240 -528
WIRE 336 -512 336 -528
WIRE -208 -448 -208 -464
WIRE -64 -448 -64 -560
WIRE -16 -448 -64 -448
WIRE 544 -448 544 -560
WIRE 544 -448 496 -448
WIRE -272 -256 -384 -256
WIRE -160 -256 -272 -256
WIRE -64 -256 -160 -256
WIRE -16 -256 -64 -256
WIRE 544 -256 496 -256
WIRE 592 -256 544 -256
WIRE 704 -256 592 -256
WIRE 816 -256 704 -256
WIRE -384 -240 -384 -256
WIRE -272 -240 -272 -256
WIRE -160 -240 -160 -256
WIRE 592 -240 592 -256
WIRE 704 -240 704 -256
WIRE 816 -240 816 -256
WIRE -64 -160 -64 -256
WIRE -16 -160 -64 -160
WIRE 544 -160 544 -256
WIRE 544 -160 496 -160
WIRE -384 -144 -384 -160
WIRE -272 -144 -272 -176
WIRE -160 -144 -160 -176
WIRE 592 -144 592 -176
WIRE 704 -144 704 -176
WIRE 816 -144 816 -160
WIRE -16 -64 -32 -64
WIRE 512 -64 496 -64
WIRE -112 32 -144 32
WIRE -16 32 -48 32
WIRE 528 32 496 32
WIRE 624 32 592 32
WIRE 48 592 48 576
WIRE 336 592 336 576
WIRE 432 592 432 576
WIRE 48 688 48 672
WIRE 240 688 240 576
WIRE 240 688 48 688
WIRE 336 688 336 672
WIRE 336 688 240 688
WIRE 432 688 432 672
WIRE 432 688 336 688
FLAG -208 -448 0
FLAG 240 -528 0
FLAG 336 -528 0
FLAG -160 -144 0
FLAG -384 -144 0
FLAG -384 -256 OUT1
FLAG -272 -144 0
FLAG 592 -144 0
FLAG 816 -144 0
FLAG 816 -256 OUT0
FLAG 704 -144 0
FLAG -32 -64 0
FLAG 512 -64 0
FLAG 624 32 0
FLAG -144 32 0
SYMBOL voltage -208 -560 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap -176 -240 R0
WINDOW 123 25 58 Left 2
WINDOW 3 36 33 Left 2
SYMATTR Value2 X2
SYMATTR Value 330
SYMATTR InstName C1
SYMATTR SpiceLine Rser=5m
SYMBOL res -400 -256 R0
SYMATTR InstName R1
SYMATTR Value 20m
SYMBOL cap -288 -240 R0
WINDOW 123 26 58 Left 2
WINDOW 3 37 33 Left 2
SYMATTR Value2 X3
SYMATTR Value 100
SYMATTR InstName C2
SYMATTR SpiceLine Rser=5m
SYMBOL cap 576 -240 R0
WINDOW 123 29 59 Left 2
WINDOW 3 39 34 Left 2
SYMATTR Value2 X2
SYMATTR Value 330
SYMATTR InstName C3
SYMATTR SpiceLine Rser=5m
SYMBOL res 800 -256 R0
SYMATTR InstName R2
SYMATTR Value 30m
SYMBOL cap 688 -240 R0
WINDOW 123 28 61 Left 2
WINDOW 3 37 33 Left 2
SYMATTR Value2 X3
SYMATTR Value 100
SYMATTR InstName C4
SYMATTR SpiceLine Rser=5m
SYMBOL cap 592 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 1n
SYMBOL cap -112 16 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 1n
SYMBOL res 416 576 R0
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res 32 576 R0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 320 576 R0
WINDOW 3 25 80 Left 2
SYMATTR InstName R5
SYMATTR Value 4.99K
SYMBOL PowerProducts\\LTM4700 240 32 R0
SYMATTR InstName U1
SYMATTR SpiceLine VIN_ON=5.5 VIN_OFF=5 Vout_0=1.5 Vout_1=1 Ilim0_range=1 Ilim1_range=1 OC_limit0=1 OC_limit1=1 Mode_ll=1 Fault_response=0 Retry_delay=.1m gm0=3m gm1=3m Rth0=5K Rth1=5K Sync=0
TEXT 928 -328 Left 1 ;Please read the following notes carefully, since the model presents different user interface\nthan the real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) Share_clk is not modeled. The default time reference of LTspice is used as the common time \nbase for all time related parameters.\n \n(4) The following parameters can be defined, by right-clicking the symbol of LTM4700. Different \nnomenclature from the datasheet is adopted here. If any value of these parameters are set beyond \nthe scope discribed in the datasheet, the resulting simulation outcomes are not meaningful.\n \n     VIN_ON & VIN_OFF -- in volts, set the unit start/stop input voltages;\n     Freq -- in Hz, sets switching frequency as one of values of 250K, 350K, \n                425K, 500K, 575K, 650K, 750K, 1000K. FSWPH_CFG pin needs to float \n                (or short to VDD25), to make the value be in effect;\n     PHs_0 & PHs_1 -- in degree,  set phase angle related to SYNC signal. \n                Certain combinations are restricted as in datasheet. FSWPH_CFG \n                pin needs to float (or short to VDD25), to make the value be in effect;\n     Ton0_delay & Ton0_rise; Ton1_delay & Ton1_rise -- in sec, set delay and soft-start timers for \n                channel0 and channel1. Initialization time is not modeled;\n     Toff0_delay & Toff0_fall; Toff1_delay & Toff1_fall -- in sec, set delay and soft-off timers for \n                channel0 and channel1;\n     Vout_0 & Vout_1 -- in volt, set output voltages respectively;\n     Vout0_range & Vout1_range -- set maximum output range, with value 0\n                                                      for 4.096V (CH0) and 5.5V (CH1); value 1\n                                                      for 2.75V\n     Ilim0_range & Ilim1_range -- set maximum sensed peak current range, with value 0\n                           for low, and 1 for high;\n     OC_limit0 & OC_limit1 -- set ratio of peak current limit to the maximum value defined\n                      by Ilimit_range. It must be one of values: 0.5, 0.572, 0.642, \n                      0.714, 0.786, 0.858, 0.928, 1;\n     Mode_II -- sets light load operation mode: 0 for discontinuous, 1 for forced continuous;\n     Fault_response -- sets the response mode of the unit to occuring faults:\n                                 0 for ignore, 1 for latch up, 2 for Hiccup after Retry_delay time;\n     Retry_delay -- in sec, sets the timer before the unit turns on after a fault;\n     gm -- transconductance of the error amplifier. It must be between 1m mho and 5.73m mho;\n     Rth -- Compensation resistor. It must be set between 0k ohms and 62k ohms;\n     Sync - value 0 for configuring module as Master, value 1 for Slave
TEXT 928 488 Right 2 !.tran 1.2m startup