* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4360-1.asc
* Generated by LTspice 26.0.1 for Windows.
C1 N002 0 10
R1 N002 0 10
L1 N003 N001 1 Rser=150m
V1 N007 0 5
R2 N007 N006 1K
V2 N005 0 PWL(0u 0 +1n 0)
MQ1 N001 N004 N002 N002 Si4892DY
D1 N002 N001 Davalanche
V3 N003 0 PWL(0u 0 100m 0 +1u 20 150m 20 +10u 0 400m 0 +1u 5 800m 5 +1u 20)
XU1 N001 N004 N005 N002 N006 0 LTC4360-1 ;pnba In)Gate)_On)Out)_Pwrgd)Gnd
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1000m startup
.model Davalanche D (Vfwd=0.7 Vrev=32 Ron=0.1 Rrev=0.1 epsilon=.1 revepsilon=.1)
* To model avalanche behavior of NFET
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\SpecialFunctions\LTC4360-1.asy)
.lib LTC4360-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 9052 3716
WIRE 5728 -1568 5648 -1568
WIRE 5856 -1568 5792 -1568
WIRE 5456 -1488 4576 -1488
WIRE 5616 -1488 5536 -1488
WIRE 5648 -1488 5648 -1568
WIRE 5648 -1488 5616 -1488
WIRE 5712 -1488 5648 -1488
WIRE 5856 -1488 5856 -1568
WIRE 5856 -1488 5808 -1488
WIRE 5968 -1488 5856 -1488
WIRE 6032 -1488 5968 -1488
WIRE 6128 -1488 6032 -1488
WIRE 4576 -1472 4576 -1488
WIRE 6032 -1472 6032 -1488
WIRE 6128 -1472 6128 -1488
WIRE 5792 -1392 5792 -1440
WIRE 4576 -1376 4576 -1392
WIRE 6032 -1376 6032 -1408
WIRE 6128 -1376 6128 -1392
WIRE 5616 -1344 5616 -1488
WIRE 5648 -1344 5616 -1344
WIRE 5968 -1344 5968 -1488
WIRE 5968 -1344 5936 -1344
WIRE 5648 -1184 5376 -1184
WIRE 5984 -1184 5936 -1184
WIRE 6112 -1184 6064 -1184
WIRE 5376 -1168 5376 -1184
WIRE 6112 -1168 6112 -1184
WIRE 5376 -1072 5376 -1088
WIRE 6112 -1072 6112 -1088
WIRE 5792 -1040 5792 -1056
FLAG 5792 -1040 0
FLAG 5376 -1072 0
FLAG 6128 -1376 0
FLAG 6112 -1072 0
FLAG 4576 -1376 0
FLAG 6032 -1376 0
SYMBOL cap 6016 -1472 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL res 6112 -1488 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL ind 5440 -1472 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
WINDOW 39 -16 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1
SYMATTR SpiceLine Rser=150m
SYMBOL voltage 6112 -1184 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 6080 -1200 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL voltage 5376 -1184 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR Value PWL(0u 0 +1n 0)
SYMATTR InstName V2
SYMBOL nmos 5712 -1440 R270
WINDOW 0 55 45 VTop 2
WINDOW 3 -18 64 VLeft 2
SYMATTR InstName Q1
SYMATTR Value Si4892DY
SYMBOL diode 5792 -1584 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value Davalanche
SYMBOL voltage 4576 -1488 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR Value PWL(0u 0 100m 0 +1u 20 150m 20 +10u 0 400m 0 +1u 5 800m 5 +1u 20)
SYMATTR InstName V3
SYMBOL LTC4360-1 5792 -1216 R0
SYMATTR InstName U1
TEXT 5568 -944 Left 2 !.tran 1000m startup\n.model Davalanche D (Vfwd=0.7 Vrev=32 Ron=0.1 Rrev=0.1 epsilon=.1 revepsilon=.1)
TEXT 5760 -1608 Bottom 2 ;To model avalanche behavior of NFET