* Z:\home\khalils\Downloads\files\data\raw_asc\160c1f864169_Fig13_21.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Q_bar N001 0 0 N_50n l=50n w=500n
VDD VDD 0 1
M2 VDD N001 Q_bar VDD P_50n l=50n w=1u
M5 Q Q_bar 0 0 N_50n l=50n w=500n
M6 VDD Q_bar Q VDD P_50n l=50n w=1u
M7 D clock N001 0 N_50n l=50n w=500n
VD D 0 PULSE 0 1 500p 10p 10p 700p 1.9n
Vclock clock 0 PULSE 0 1 0 10p 10p 1n 2n
M3 N001 clock_b D VDD P_50n l=50n w=1u
M4 N001 clock_b Q 0 N_50n l=50n w=500n
M8 Q clock N001 VDD P_50n l=50n w=1u
Vclock1 clock_b 0 PULSE 1 0 0 10p 10p 1n 2n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 0 10n 0
.lib cmosedu_models.txt
* Plot q+2.5 d+1.25 clock
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 64 -400 0 -400
WIRE 64 -400 64 -464
WIRE 80 -176 80 -192
WIRE 80 -160 80 -176
WIRE 80 -48 80 -80
WIRE 160 -400 160 -464
WIRE 240 -448 240 -640
WIRE 240 -400 160 -400
WIRE 240 -400 240 -448
WIRE 240 -176 240 -192
WIRE 240 -160 240 -176
WIRE 240 -48 240 -80
WIRE 272 -640 240 -640
WIRE 272 -640 272 -672
WIRE 272 -608 272 -640
WIRE 352 -160 352 -192
WIRE 352 -48 352 -80
WIRE 368 -640 368 -672
WIRE 368 -608 368 -640
WIRE 416 -640 368 -640
WIRE 416 -448 240 -448
WIRE 416 -448 416 -496
WIRE 416 -368 416 -448
WIRE 448 -640 416 -640
WIRE 448 -496 416 -496
WIRE 448 -368 416 -368
WIRE 496 -448 496 -480
WIRE 496 -304 496 -352
WIRE 544 -192 544 -224
WIRE 544 -80 544 -112
WIRE 704 -448 496 -448
WIRE 704 -256 704 -448
WIRE 736 -448 704 -448
WIRE 736 -448 736 -496
WIRE 736 -368 736 -448
WIRE 768 -496 736 -496
WIRE 768 -368 736 -368
WIRE 816 -448 816 -480
WIRE 816 -304 816 -352
WIRE 992 -448 816 -448
WIRE 992 -256 704 -256
FLAG 496 -400 0
FLAG 80 -48 0
FLAG 80 -176 VDD
FLAG 496 -528 VDD
FLAG 496 -304 0
FLAG 496 -576 VDD
FLAG 816 -400 0
FLAG 816 -528 VDD
FLAG 816 -304 0
FLAG 816 -576 VDD
FLAG 112 -400 0
FLAG 0 -400 D
FLAG 144 -352 clock
FLAG 992 -448 Q
FLAG 240 -48 0
FLAG 240 -176 D
FLAG 992 -256 Q_bar
FLAG 352 -48 0
FLAG 352 -192 clock
FLAG 112 -464 VDD
FLAG 80 -512 clock_b
FLAG 320 -608 0
FLAG 352 -560 clock_b
FLAG 320 -672 VDD
FLAG 288 -720 clock
FLAG 416 -640 Q
FLAG 544 -80 0
FLAG 544 -224 clock_b
SYMBOL nmos4 448 -448 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 80 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1
SYMBOL pmos4 448 -576 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M2
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 768 -448 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M5
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 768 -576 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M6
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 64 -352 R270
WINDOW 0 86 42 Invisible 0
WINDOW 3 82 140 Invisible 0
SYMATTR InstName M7
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL voltage 240 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -161 204 Left 0
SYMATTR Value PULSE 0 1 500p 10p 10p 700p 1.9n
SYMATTR InstName VD
SYMBOL voltage 352 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -99 164 Left 0
SYMATTR Value PULSE 0 1 0 10p 10p 1n 2n
SYMATTR InstName Vclock
SYMBOL pmos4 160 -512 R90
WINDOW 0 71 26 Invisible 0
WINDOW 3 75 133 Invisible 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 272 -560 R270
WINDOW 0 86 42 Invisible 0
WINDOW 3 82 140 Invisible 0
SYMATTR InstName M4
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 368 -720 R90
WINDOW 0 71 26 Invisible 0
WINDOW 3 75 133 Invisible 0
SYMATTR InstName M8
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL voltage 544 -208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 -99 164 Left 0
SYMATTR Value PULSE 1 0 0 10p 10p 1n 2n
SYMATTR InstName Vclock1
TEXT 616 24 Left 0 !.tran 0 10n 0
TEXT 616 48 Left 0 !.lib cmosedu_models.txt
TEXT 232 -696 Right 0 ;Plot q+2.5 d+1.25 clock