* Z:\home\khalils\Downloads\files\data\raw_asc\ADL5309.asc
* Generated by LTspice 26.0.1 for Windows.
* Parameters:\n***********\nMUX_CTRL\nADCREF_MUX_SEL\nPDBG_FIX\nPDBG\nIDZ\nIPDB\nOS1\nOS2\nCF
* Description\n***********\nSet to 0 to connect OUT1 to ADC input. Set to 1 to connect OUT2 to ADC input.\nSet to 0 to use internal ADC reference of 2V. Set to 1 to use external reference.\nSet to 0 to enable photodiode bias transresistance (Rt). Set to 1 to disable.\nSets photodiode bias Rt.\nSets input current threshold which enables photodiode bias Rt.\nSets coarse initial bias adjustment between PDB pin and INP pin on both channels.\nSets channel 1 fine offset voltage.\nSets channel 1 fine offset voltage.\nSelects capacitor feedback for bandwidth and noise adjustment.
* Valid range:\n***********\n0, 1\n0, 1\n0, 1\n0 - 63\n0 - 15\n0 - 15\n-128 - 128\n-128 - 128\n0 - 15
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADL5309.asy)
R2 OUT2 0 10k
R3 OUT1 0 10k
I1 PDB1 INP1 PULSE({100p*decade} {1n*decade} 10u 5n 5n 20u 40u)
R1 ADCOUT 0 1Meg
C1 N001 0 0.1
C2 SUM 0 0.1
V2 ADCREF 0 2
I2 PDB2 INP2 PULSE({100p*decade} {1n*decade} 20u 5n 5n 20u 40u)
XU1 INP1 PDB1 SUM INP2 PDB2 VCC 0 N001 OUT1 OUT2 ADCREF ADCOUT ADL5309 MUX_CTRL=0 ADCREF_MUX_SEL=0 PDBG_FIX=0 PDBG=0 IDZ=0 IPDB=0 OS1=0 OS2=0 CF=0 ;pnba INP1)PDB1)SUM)INP2)PDB2)VCC)GND)CAP)OUT1)OUT2)ADCREF)ADCOUT
V1 VCC 0 3
.tran 0 100u 40u
.step dec param decade 1 100k 1
.lib ADL5309.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2580 1728
WIRE 176 560 144 560
WIRE 288 560 256 560
WIRE 288 576 288 560
WIRE 144 640 144 560
WIRE -112 672 -256 672
WIRE -64 672 -112 672
WIRE 384 672 336 672
WIRE 432 672 384 672
WIRE 432 688 432 672
WIRE -256 704 -256 672
WIRE 432 784 432 768
WIRE -256 816 -256 784
WIRE -112 816 -256 816
WIRE -64 816 -112 816
WIRE 384 816 336 816
WIRE 432 816 384 816
WIRE 432 832 432 816
WIRE -240 912 -256 912
WIRE -112 912 -176 912
WIRE -64 912 -112 912
WIRE -256 928 -256 912
WIRE 432 928 432 912
WIRE 400 976 336 976
WIRE 432 976 400 976
WIRE 432 992 432 976
WIRE -112 1008 -256 1008
WIRE -64 1008 -112 1008
WIRE -256 1040 -256 1008
WIRE 432 1088 432 1072
WIRE -256 1152 -256 1120
WIRE -112 1152 -256 1152
WIRE -64 1152 -112 1152
WIRE 416 1152 336 1152
WIRE 432 1152 416 1152
WIRE 432 1184 432 1152
WIRE 64 1264 64 1216
WIRE 112 1264 64 1264
WIRE 208 1264 208 1216
WIRE 208 1264 176 1264
WIRE 64 1280 64 1264
WIRE 432 1280 432 1264
SYMBOL cap -176 896 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL res 416 672 R0
SYMATTR InstName R3
SYMATTR Value 10k
SYMBOL res 416 976 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL res 416 816 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 432 1168 R0
SYMATTR InstName V2
SYMATTR Value 2
SYMBOL voltage 160 560 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL current -256 784 R180
WINDOW 0 -34 72 Top 2
WINDOW 3 232 151 Bottom 2
WINDOW 123 -60 40 VBottom 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value PULSE({100p*decade} {1n*decade} 10u 5n 5n 20u 40u)
SYMBOL ADL5309 144 912 R0
SYMATTR InstName U1
SYMBOL current -256 1120 R180
WINDOW 0 -34 72 Top 2
WINDOW 3 232 151 Bottom 2
WINDOW 123 -60 40 VBottom 2
WINDOW 39 0 0 Left 0
SYMATTR InstName I2
SYMATTR Value PULSE({100p*decade} {1n*decade} 20u 5n 5n 20u 40u)
SYMBOL cap 176 1248 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 0.1
FLAG 64 1280 0
FLAG 432 1280 0
FLAG 432 1088 0
FLAG 400 976 ADCOUT
FLAG 416 1152 ADCREF
FLAG 432 928 0
FLAG 432 784 0
FLAG 384 816 OUT2
FLAG 384 672 OUT1
FLAG 288 576 0
FLAG 144 560 VCC
FLAG -256 928 0
FLAG -112 672 INP1
FLAG -112 816 PDB1
FLAG -112 912 SUM
FLAG -112 1008 INP2
FLAG -112 1152 PDB2
TEXT -296 552 Left 2 !.tran 0 100u 40u\n.step dec param decade 1 100k 1
TEXT -64 1424 Left 2 ;Parameters:\n***********\nMUX_CTRL\nADCREF_MUX_SEL\nPDBG_FIX\nPDBG\nIDZ\nIPDB\nOS1\nOS2\nCF
TEXT 456 1424 Left 2 ;Description\n***********\nSet to 0 to connect OUT1 to ADC input. Set to 1 to connect OUT2 to ADC input.\nSet to 0 to use internal ADC reference of 2V. Set to 1 to use external reference.\nSet to 0 to enable photodiode bias transresistance (Rt). Set to 1 to disable.\nSets photodiode bias Rt.\nSets input current threshold which enables photodiode bias Rt.\nSets coarse initial bias adjustment between PDB pin and INP pin on both channels.\nSets channel 1 fine offset voltage.\nSets channel 1 fine offset voltage.\nSelects capacitor feedback for bandwidth and noise adjustment.
TEXT 192 1424 Left 2 ;Valid range:\n***********\n0, 1\n0, 1\n0, 1\n0 - 63\n0 - 15\n0 - 15\n-128 - 128\n-128 - 128\n0 - 15