Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\24e51edf974e_mul.asc
* Generated by LTspice 26.0.1 for Windows.
A1 0 A1 0 V 0 N001 0 0 AND
A2 0 0 N001 N002 0 C1 0 0 AND
A3 0 N003 0 B1 0 N002 0 0 AND
A4 V 0 0 0 0 N003 0 0 BUF
A5 0 A2 0 V 0 N004 0 0 AND
A6 0 0 N004 N005 0 C2 0 0 AND
A7 0 N006 0 B2 0 N005 0 0 AND
A8 V 0 0 0 0 N006 0 0 BUF
A9 0 A3 0 V 0 N007 0 0 AND
A10 0 0 N007 N008 0 C3 0 0 AND
A11 0 N009 0 B3 0 N008 0 0 AND
A12 V 0 0 0 0 N009 0 0 BUF
A13 0 A4 0 V 0 N010 0 0 AND
A14 0 0 N010 N011 0 C4 0 0 AND
A15 0 N012 0 B4 0 N011 0 0 AND
A16 V 0 0 0 0 N012 0 0 BUF
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2100 968
WIRE 592 -176 432 -176
WIRE 592 -144 320 -144
WIRE 784 -144 656 -144
WIRE 784 -128 752 -128
WIRE 928 -128 848 -128
WIRE 320 -80 320 -144
WIRE 560 -80 320 -80
WIRE 656 -80 624 -80
WIRE 656 -48 432 -48
WIRE 752 -48 752 -128
WIRE 752 -48 720 -48
WIRE 592 48 432 48
WIRE 320 80 320 -80
WIRE 592 80 320 80
WIRE 784 80 656 80
WIRE 784 96 752 96
WIRE 928 96 848 96
WIRE 320 144 320 80
WIRE 560 144 320 144
WIRE 656 144 624 144
WIRE 656 176 432 176
WIRE 752 176 752 96
WIRE 752 176 720 176
WIRE 320 240 320 144
WIRE 320 240 144 240
WIRE 592 288 432 288
WIRE 320 320 320 240
WIRE 592 320 320 320
WIRE 784 320 656 320
WIRE 784 336 752 336
WIRE 928 336 848 336
WIRE 320 384 320 320
WIRE 560 384 320 384
WIRE 656 384 624 384
WIRE 656 416 432 416
WIRE 752 416 752 336
WIRE 752 416 720 416
WIRE 592 512 432 512
WIRE 320 544 320 384
WIRE 592 544 320 544
WIRE 784 544 656 544
WIRE 784 560 752 560
WIRE 928 560 848 560
WIRE 320 608 320 544
WIRE 560 608 320 608
WIRE 656 608 624 608
WIRE 656 640 432 640
WIRE 752 640 752 560
WIRE 752 640 720 640
IOPIN 432 -176 In
IOPIN 432 -48 In
IOPIN 144 240 In
IOPIN 432 48 In
IOPIN 432 176 In
IOPIN 432 288 In
IOPIN 432 416 In
IOPIN 432 512 In
IOPIN 432 640 In
IOPIN 928 -128 Out
IOPIN 928 96 Out
IOPIN 928 336 Out
IOPIN 928 560 Out
SYMBOL Digital\\inv 560 320 R0
SYMATTR InstName A12
SYMBOL Digital\\and 816 -208 R0
SYMATTR InstName A2
SYMBOL Digital\\and 688 336 R0
SYMATTR InstName A11
SYMBOL Digital\\inv 560 544 R0
SYMATTR InstName A16
SYMBOL Digital\\and 624 464 R0
SYMATTR InstName A13
SYMBOL Digital\\and 816 16 R0
SYMATTR InstName A6
SYMBOL Digital\\and 688 -128 R0
SYMATTR InstName A3
SYMBOL Digital\\inv 560 -144 R0
SYMATTR InstName A4
SYMBOL Digital\\and 624 -224 R0
SYMATTR InstName A1
SYMBOL Digital\\and 688 96 R0
SYMATTR InstName A7
SYMBOL Digital\\and 624 240 R0
SYMATTR InstName A9
SYMBOL Digital\\and 816 256 R0
SYMATTR InstName A10
SYMBOL Digital\\inv 560 80 R0
SYMATTR InstName A8
SYMBOL Digital\\and 688 560 R0
SYMATTR InstName A15
SYMBOL Digital\\and 624 0 R0
SYMATTR InstName A5
SYMBOL Digital\\and 816 480 R0
SYMATTR InstName A14
FLAG 432 -176 A1
FLAG 432 -48 B1
FLAG 144 240 V
FLAG 432 48 A2
FLAG 432 176 B2
FLAG 432 288 A3
FLAG 432 416 B3
FLAG 432 512 A4
FLAG 432 640 B4
FLAG 928 -128 C1
FLAG 928 96 C2
FLAG 928 336 C3
FLAG 928 560 C4
* Z:\home\khalils\Downloads\files\data\raw_asc\25226b232d8f_CMOS_inverter.asc
* Generated by LTspice 26.0.1 for Windows.
M2 N003 N002 0 0 BSP89
V2 N002 0 PULSE(0 5 1 1n 1n 2 4 10)
V1 N001 0 5
M1 N003 N002 N001 N001 AO6407
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 50
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 -96 -160 -96
WIRE 224 32 224 -16
WIRE 272 48 176 48
WIRE -160 208 -160 -96
WIRE 176 208 176 48
WIRE 176 208 -80 208
WIRE 224 240 224 128
WIRE 176 320 176 208
WIRE -160 368 -160 208
WIRE 224 368 224 336
WIRE 224 368 -160 368
WIRE 224 416 224 368
SYMBOL voltage 224 0 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -64 208 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 1 1n 1n 2 4 10)
SYMBOL nmos 176 240 R0
SYMATTR InstName M2
SYMATTR Value BSP89
SYMBOL pmos 272 128 R180
SYMATTR InstName M1
SYMATTR Value AO6407
FLAG 224 416 0
TEXT -272 440 Left 2 !.tran 50
* Z:\home\khalils\Downloads\files\data\raw_asc\19cadbe77e1d_currect_regulator.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 10
R1 N002 0 100
J1 N001 N002 N002 2N4119
.model NJF NJF
.model PJF PJF
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.jft
.dc V1 0 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 48 32 48
WIRE 208 80 208 48
WIRE 160 144 144 144
WIRE 32 160 32 48
WIRE 144 192 144 144
WIRE 208 192 208 176
WIRE 208 192 144 192
WIRE 208 208 208 192
WIRE 32 304 32 240
WIRE 208 304 208 288
WIRE 208 304 32 304
WIRE 208 320 208 304
SYMBOL Misc\\EuropeanResistor 192 192 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 32 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL njf 160 80 R0
SYMATTR InstName J1
SYMATTR Value 2N4119
FLAG 208 320 0
TEXT 280 48 Left 2 !.dc V1 0 10
* Z:\home\khalils\Downloads\files\data\raw_asc\39d0249bd129_fig-01-03-21.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4177-2.asy)
VS2 0 VEE 15
VS1 VCC 0 15
Q1 N001 0 N002 0 2N2222
V1 VIN 0 0
XU1 0 N001 VCC VEE N002 ADA4177 ;pnba In+)In-)V+)V-)OUT
E1 VOUT 0 N002 0 -1
R1 N001 VIN 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc dec V1 10n 100 100
.lib ADA4177.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -32 128 -32
WIRE 304 -32 256 -32
WIRE 208 48 208 32
WIRE 208 96 208 80
WIRE 480 96 432 96
WIRE 208 144 208 96
WIRE -32 160 -48 160
WIRE 16 160 -32 160
WIRE 128 160 128 -32
WIRE 128 160 96 160
WIRE 176 160 128 160
WIRE 432 160 432 96
WIRE 304 176 304 -32
WIRE 304 176 240 176
WIRE 384 176 304 176
WIRE 176 192 128 192
WIRE -48 208 -48 160
WIRE 128 224 128 192
WIRE 384 224 368 224
WIRE 208 240 208 208
WIRE 208 256 208 240
WIRE 368 256 368 224
WIRE 432 256 432 240
WIRE 432 256 368 256
WIRE 432 272 432 256
WIRE 272 288 272 272
WIRE 336 288 336 272
WIRE -48 336 -48 288
WIRE 272 336 272 288
WIRE 336 336 336 288
WIRE 272 432 272 416
WIRE 336 432 336 416
IOPIN 480 96 Out
SYMBOL voltage -48 192 R0
SYMATTR InstName V1
SYMATTR Value 0
SYMBOL Misc\\battery 272 432 R180
WINDOW 0 24 104 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName VS2
SYMATTR Value 15
SYMBOL Opamps\\ADA4177-2 208 176 R0
SYMATTR InstName U1
SYMBOL e 432 144 R0
SYMATTR InstName E1
SYMATTR Value -1
SYMBOL res 112 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL npn 160 32 R270
WINDOW 0 79 -30 VRight 2
WINDOW 3 79 74 VRight 2
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL Misc\\battery 336 320 R0
WINDOW 0 9 8 Left 2
WINDOW 3 15 97 Left 2
SYMATTR InstName VS1
SYMATTR Value 15
FLAG -48 336 0
FLAG -32 160 VIN
FLAG 272 432 0
FLAG 336 432 0
FLAG 272 288 VEE
FLAG 336 288 VCC
FLAG 208 96 VCC
FLAG 208 240 VEE
FLAG 480 96 VOUT
FLAG 208 48 0
FLAG 128 224 0
FLAG 432 272 0
TEXT -72 400 Left 2 !.dc dec V1 10n 100 100
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8029.asc
* Generated by LTspice 26.0.1 for Windows.
R3 N003 0 158K
C2 OUT 0 22 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
R4 IN N001 100K
V1 IN 0 10
Rload OUT 0 8.6
XU1 N002 OUT IN IN 0 MP_01 MP_02 OUT N001 N003 LTM8029 ;pnba FB)OUT)Run)Vin)GND)))Bias)Pgood)Rt
R1 N002 0 309K
.tran 750u startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8029.asy)
.lib LTM8029.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 680
WIRE 48 16 -64 16
WIRE 128 16 48 16
WIRE 144 16 128 16
WIRE 432 16 400 16
WIRE -64 32 -64 16
WIRE 48 112 48 16
WIRE 128 112 128 16
WIRE 144 112 128 112
WIRE 432 112 432 16
WIRE 432 112 400 112
WIRE 560 112 432 112
WIRE 640 112 560 112
WIRE -64 128 -64 112
WIRE 560 128 560 112
WIRE 640 128 640 112
WIRE 48 208 48 192
WIRE 144 208 48 208
WIRE 480 208 400 208
WIRE 480 224 480 208
WIRE 560 224 560 192
WIRE 640 224 640 208
WIRE 48 304 32 304
WIRE 144 304 128 304
WIRE 416 304 400 304
WIRE 480 320 480 304
FLAG 416 304 0
FLAG 32 304 0
FLAG 560 224 0
FLAG 640 224 0
FLAG -64 128 0
FLAG -64 16 IN
FLAG 640 112 OUT
FLAG 480 320 0
SYMBOL res 144 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 158K
SYMBOL cap 544 128 R0
SYMATTR InstName C2
SYMATTR Value 22
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C4532X5ROJ47@M" type="X5R"
SYMBOL res 32 96 R0
SYMATTR InstName R4
SYMATTR Value 100K
SYMBOL voltage -64 16 R0
SYMATTR InstName V1
SYMATTR Value 10
SYMBOL res 624 112 R0
SYMATTR InstName Rload
SYMATTR Value 8.6
SYMBOL PowerProducts\\LTM8029 272 160 R0
SYMATTR InstName U1
SYMBOL res 464 208 R0
SYMATTR InstName R1
SYMATTR Value 309K
TEXT 600 328 Left 2 !.tran 750u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\a09664f18a47_Draft2P.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N001 0 1.8
VGS2 N001 VG 1
VUDS N001 N002 0.9
M1 N001 VG N002 N001 pch l=lset w=wset
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmos018.txt
.dc VGS2 0 1 1m
.param wset=table(n, 1,0.22u, 2,1u, 3,2u, 4,2u, 5,5u, 6,5u, 7,10u, 8,10u, 9,40u)
.param lset=table(n, 1,0.18u, 2,0.5u, 3,0.5u, 4,1u, 5,1u, 6,2u, 7,5u, 8,10u, 9,10u)
.step param n 1 9 1
.meas DC UTH FIND V(VG) WHEN Id(M1)=100n*wset/lset
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1356 680
WIRE 224 176 32 176
WIRE 544 176 224 176
WIRE 720 176 544 176
WIRE 32 192 32 176
WIRE 224 224 224 176
WIRE 240 224 224 224
WIRE 544 224 544 176
WIRE 720 224 720 176
WIRE 240 272 240 224
WIRE 240 272 224 272
WIRE 32 304 32 272
WIRE 112 304 32 304
WIRE 176 304 112 304
WIRE 224 352 224 320
WIRE 544 352 544 304
WIRE 544 352 224 352
WIRE 720 368 720 304
SYMBOL voltage 720 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.8
SYMBOL voltage 544 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName UDS
SYMATTR Value 0.9
SYMBOL voltage 32 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VGS2
SYMATTR Value 1
SYMBOL pmos4 176 224 R0
WINDOW 123 75 75 Left 2
WINDOW 0 75 14 Left 2
WINDOW 3 75 45 Left 2
SYMATTR Value2 l=lset w=wset
SYMATTR InstName M1
SYMATTR Value pch
FLAG 112 304 VG
FLAG 720 368 0
TEXT -40 -64 Left 2 !.lib cmos018.txt
TEXT -40 96 Left 2 !.dc VGS2 0 1 1m
TEXT -40 -16 Left 2 !.param wset=table(n, 1,0.22u, 2,1u, 3,2u, 4,2u, 5,5u, 6,5u, 7,10u, 8,10u, 9,40u)\n.param lset=table(n, 1,0.18u, 2,0.5u, 3,0.5u, 4,1u, 5,1u, 6,2u, 7,5u, 8,10u, 9,10u)\n.step param n 1 9 1\n.meas DC UTH FIND V(VG) WHEN Id(M1)=100n*wset/lset
* Z:\home\khalils\Downloads\files\data\raw_asc\2b157e6c9087_LTC1060_Mode1.asc
* Generated by LTspice 26.0.1 for Windows.
* -5V/5V AGND/LP
* 0V/5V=100/50
* f0=fclk/100(50)\nfn=f0\nHolp=R2/R1\nHobp=-R3/R1\nHont1=-R2/R1\nQ=R3/R2
* Library below included based on ModelFile attribute of instance XX2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\FilterProducts\LTC1060.asy)
A1 IN 0 0 0 0 0 N002 0 MODULATOR space 0k mark 10k
XX2 NC_05 NC_06 NC_07 N001 NC_08 NC_09 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 LTC1060 fclka=1k fclkb=1k divider=50 ;pnba LPA)BPA)HPA/NA)INV A)SA)SA/B)VA+)VD+)VD-)VA-)AGND)SB)INV B)HPB/NB)BPB)LPB
V4 N003 0 5
V2 CLK 0 PULSE(0 5 0 5n 5n 995n 2u)
R2 N001 HP 5k
V1 IN 0 PWL(0 0.01 50m 5)
R4 N001 LP 10g
R3 N001 BP 20k
V3 N004 0 5
R1 N002 N001 5k
.tran 25m
.lib LTC7.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 320 -208 -96 -208
WIRE 496 -208 400 -208
WIRE -96 -96 -96 -208
WIRE 128 -96 -96 -96
WIRE 384 -96 208 -96
WIRE -96 -16 -96 -96
WIRE -32 -16 -96 -16
WIRE 128 -16 48 -16
WIRE 128 16 128 -16
WIRE 384 16 384 -96
WIRE 496 16 496 -208
WIRE 128 48 128 16
WIRE 240 48 240 16
WIRE 384 48 384 16
WIRE 496 48 496 16
WIRE -592 96 -640 96
WIRE -448 96 -592 96
WIRE -240 128 -304 128
WIRE -96 128 -96 -16
WIRE -96 128 -160 128
WIRE -32 128 -96 128
WIRE -640 176 -640 96
WIRE -32 240 -96 240
WIRE -96 272 -96 240
WIRE -640 288 -640 256
WIRE -96 368 -128 368
WIRE 128 368 128 320
WIRE 128 368 -96 368
WIRE -128 400 -128 368
WIRE 240 400 240 320
WIRE 352 400 352 320
WIRE -128 512 -128 480
WIRE 240 512 240 480
WIRE 352 512 352 480
SYMBOL voltage 352 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage 240 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 5
SYMBOL res -256 144 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R1
SYMATTR Value 5k
SYMBOL LTC1060 128 192 R0
SYMATTR InstName X2
SYMBOL res 304 -192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R4
SYMATTR Value 10g
SYMBOL SpecialFunctions\\modulate -448 96 R0
SYMATTR InstName A1
SYMATTR Value2 space 0k mark 10k
SYMBOL res -48 0 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R2
SYMATTR Value 5k
SYMBOL res 112 -80 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 0 56 VBottom 0
SYMATTR InstName R3
SYMATTR Value 20k
SYMBOL voltage -128 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 5n 5n 995n 2u)
SYMBOL voltage -640 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0.01 50m 5)
FLAG -96 272 0
FLAG 352 512 0
FLAG 496 -208 LP
FLAG 384 -96 S1
FLAG 384 16 BP
FLAG -592 96 IN
FLAG -640 288 0
FLAG -96 368 CLK
FLAG -128 512 0
FLAG 240 512 0
FLAG 240 16 0
FLAG 496 16 LP
FLAG 128 16 HP
TEXT -608 -64 Left 0 !.tran 25m
TEXT 400 440 Left 0 ;-5V/5V AGND/LP
TEXT 40 440 Left 0 ;0V/5V=100/50
TEXT -432 -200 Left 0 ;f0=fclk/100(50)\nfn=f0\nHolp=R2/R1\nHobp=-R3/R1\nHont1=-R2/R1\nQ=R3/R2
* Z:\home\khalils\Downloads\files\data\raw_asc\0918470151d3_inductor-theory.asc
* Generated by LTspice 26.0.1 for Windows.
* tc = 1H / 100k = 10us
* Charging\nI = I_0 * [1 - exp(-t / tc)]
* Discharging\nI = I_0 * exp(-t / tc)
R1 out N001 100k
L1 0 out 1H
V1 N001 0 PULSE(0 10 {delay} 1n 1n 150u 300u 1)
.tran {delay + tc*50}
.param tc {1H / 100k}
.param delay 20u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 240 128 240
WIRE 448 240 336 240
WIRE 128 304 128 240
WIRE 448 304 448 240
WIRE 128 432 128 384
WIRE 448 432 448 384
SYMBOL Res 352 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ind 432 400 M180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L1
SYMATTR Value 1H
SYMBOL voltage 128 288 R0
WINDOW 3 -101 186 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 10 {delay} 1n 1n 150u 300u 1)
FLAG 448 432 0
FLAG 128 432 0
FLAG 448 240 out
TEXT 160 120 Left 2 !.tran {delay + tc*50}
TEXT 552 256 Left 2 ;tc = 1H / 100k = 10us
TEXT 408 136 Left 2 !.param tc {1H / 100k}\n.param delay 20u
TEXT 552 296 Left 2 ;Charging\nI = I_0 * [1 - exp(-t / tc)]
TEXT 552 352 Left 2 ;Discharging\nI = I_0 * exp(-t / tc)
* Z:\home\khalils\Downloads\files\data\raw_asc\ADuM4221-2A.asc
* Generated by LTspice 26.0.1 for Windows.
* GND1 is modeled as common GND
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADuM4221-2A.asy)
V3 N003 0 5
R2 Gate_A N001 5.11
V2 VIB 0 PULSE(5 0 0 2n 2n 5u 10u)
R3 Gate_B N006 5.11
V1 VIA 0 PULSE(0 5 0 2n 2n 5u 10u)
V5 N002 0 15
C4 Gate_A 0 2.2n
XU1 VIA VIB N003 0 N005 0 N006 N004 0 N001 N002 ADuM4221-2A ;pnba VIA)VIB)VDD1)GND1)DISABLE)GNDB)VOB)VDDB)GNDA)VOA)VDDA
V4 N005 0 0
V6 N004 0 15
C5 Gate_B 0 2.2n
.tran 50u
.lib ADuM4221-2A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 3080 680
WIRE -1808 -448 -2288 -448
WIRE -1728 -448 -1808 -448
WIRE -1120 -448 -1424 -448
WIRE -992 -448 -1040 -448
WIRE -864 -448 -992 -448
WIRE -816 -448 -864 -448
WIRE -2288 -416 -2288 -448
WIRE -992 -416 -992 -448
WIRE -1808 -384 -2192 -384
WIRE -1728 -384 -1808 -384
WIRE -1232 -384 -1424 -384
WIRE -1232 -368 -1232 -384
WIRE -2192 -352 -2192 -384
WIRE -992 -336 -992 -352
WIRE -1728 -320 -2064 -320
WIRE -1392 -320 -1424 -320
WIRE -1728 -240 -1760 -240
WIRE -1232 -240 -1424 -240
WIRE -2064 -224 -2064 -320
WIRE -1232 -224 -1232 -240
WIRE -1728 -176 -1984 -176
WIRE -1392 -176 -1424 -176
WIRE -1984 -128 -1984 -176
WIRE -1120 -112 -1424 -112
WIRE -992 -112 -1040 -112
WIRE -864 -112 -992 -112
WIRE -816 -112 -864 -112
WIRE -992 -80 -992 -112
WIRE -2288 16 -2288 -336
WIRE -2192 16 -2192 -272
WIRE -2064 16 -2064 -144
WIRE -1984 16 -1984 -48
WIRE -992 16 -992 -16
SYMBOL voltage -1232 -384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 43 29 Left 2
WINDOW 3 46 61 Left 2
SYMATTR InstName V5
SYMATTR Value 15
SYMBOL cap -1008 -80 R0
SYMATTR InstName C5
SYMATTR Value 2.2n
SYMBOL voltage -2064 -240 R0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage -2192 -368 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(5 0 0 2n 2n 5u 10u)
SYMBOL cap -1008 -416 R0
SYMATTR InstName C4
SYMATTR Value 2.2n
SYMBOL res -1024 -128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 5.11
SYMBOL voltage -1232 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 42 34 Left 2
WINDOW 3 45 64 Left 2
SYMATTR InstName V6
SYMATTR Value 15
SYMBOL voltage -1984 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL voltage -2288 -432 R0
WINDOW 0 26 98 Left 2
WINDOW 3 33 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 2n 2n 5u 10u)
SYMBOL ADuM4221-2A -1568 -352 R0
SYMATTR InstName U1
SYMBOL res -1024 -464 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 5.11
FLAG -1984 16 0
FLAG -1392 -176 0
FLAG -1232 -144 0
FLAG -864 -112 Gate_B
FLAG -864 -448 Gate_A
FLAG -992 16 0
FLAG -2288 16 0
FLAG -2064 16 0
FLAG -992 -336 0
FLAG -1808 -448 VIA
FLAG -1392 -320 0
FLAG -1760 -240 0
FLAG -1232 -288 0
FLAG -2192 16 0
FLAG -1808 -384 VIB
TEXT -1728 -8 Left 2 !.tran 50u
TEXT -1728 -32 Left 1 ;GND1 is modeled as common GND
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP150-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP150-1.8.asy)
XU1 IN 0 IN MP_01 OUT ADP150-x.x T=.6Meg ;pnba Vin)GND)EN))Vout
C1 OUT 0 1
V1 IN 0 5
Rload OUT 0 18
.tran 500u startup
.lib ADP150-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 880 1696 880
WIRE 1984 880 1824 880
WIRE 1696 896 1696 880
WIRE 1984 896 1984 880
WIRE 1696 992 1696 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 18
SYMBOL PowerProducts\\ADP150-1.8 1984 1024 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1696 880 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG 2256 1024 OUT
FLAG 2256 1136 0
FLAG 1696 992 0
FLAG 1696 880 IN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0ffce813293d_lab_2-circuito-4_7k.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Vout 0 4.7k
D1 Vin Vout 1N4148
V1 Vin 0 SINE(0 21.21 60)
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 0.17
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 160 -80 64 -80
WIRE 320 -80 224 -80
WIRE 64 0 64 -80
WIRE 320 0 320 -80
WIRE 64 128 64 80
WIRE 320 128 320 80
SYMBOL diode 160 -64 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 304 -16 R0
SYMATTR InstName R1
SYMATTR Value 4.7k
SYMBOL voltage 64 -16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 21.21 60)
FLAG 64 128 0
FLAG 320 128 0
FLAG 64 -80 Vin
FLAG 320 -80 Vout
TEXT 366 -96 Left 2 !.tran 0.17
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1161.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1161.asy)
Rload1 0 N006 5
R2 N001 N008 .01
V3 N009 0 PULSE(0 5 0 100n 100n 2.5m 5m)
C1 N002 0 1000p
R1 N001 N003 .01
MQ1 N003 N005 N006 N006 FDS5670
MQ2 N008 N010 N011 N011 FDS5670
V1 N001 0 24
V2 N007 0 PULSE(0 5 0 100n 100n 2.5m 5m)
Rload2 0 N011 5
XU1 0 N002 N007 N004 N009 MP_01 MP_02 MP_03 MP_04 MP_05 N001 MP_06 MP_07 MP_08 MP_09 N010 N008 N005 N003 LT1161 ;pnba GND)Timer1)INPUT1)Timer2)INPUT2))))))V+)))))Gate2)Sense2)Gate1)Sense1
C2 N004 0 1000p
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20m startup
.lib LT1161.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 544 32 160 32
WIRE 624 32 544 32
WIRE 160 48 160 32
WIRE 624 48 624 32
WIRE -96 96 -112 96
WIRE 0 96 -32 96
WIRE 400 96 320 96
WIRE 448 96 400 96
WIRE 544 96 544 32
WIRE 544 96 528 96
WIRE 400 112 400 96
WIRE 624 144 624 128
WIRE -96 192 -112 192
WIRE 0 192 -32 192
WIRE 352 192 320 192
WIRE 400 240 400 208
WIRE 576 240 400 240
WIRE 688 240 656 240
WIRE -240 288 -288 288
WIRE 0 288 -160 288
WIRE 400 288 320 288
WIRE 448 288 400 288
WIRE 544 288 544 96
WIRE 544 288 528 288
WIRE 400 304 400 288
WIRE -240 384 -288 384
WIRE 0 384 -160 384
WIRE 352 384 320 384
WIRE 400 432 400 400
WIRE 576 432 400 432
WIRE 688 432 656 432
WIRE 160 448 160 432
SYMBOL res 672 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rload1
SYMATTR Value 5
SYMBOL nmos 352 304 R0
SYMATTR InstName Q2
SYMATTR Value FDS5670
SYMBOL voltage 624 32 R0
SYMATTR InstName V1
SYMATTR Value 24
SYMBOL cap -32 176 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 1000p
SYMBOL res 544 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value .01
SYMBOL voltage -144 288 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 100n 100n 2.5m 5m)
SYMBOL PowerProducts\\LT1161 160 240 R0
SYMATTR InstName U1
SYMBOL res 544 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value .01
SYMBOL cap -32 80 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1000p
SYMBOL nmos 352 112 R0
SYMATTR InstName Q1
SYMATTR Value FDS5670
SYMBOL voltage -144 384 R90
WINDOW 0 -3 9 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V3
SYMATTR Value PULSE(0 5 0 100n 100n 2.5m 5m)
SYMBOL res 672 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rload2
SYMATTR Value 5
FLAG 624 144 0
FLAG 160 448 0
FLAG -288 288 0
FLAG -288 384 0
FLAG -112 96 0
FLAG -112 192 0
FLAG 688 240 0
FLAG 688 432 0
TEXT 256 480 Left 2 !.tran 20m startup