* Z:\home\khalils\Downloads\files\data\raw_asc\eb9e00164562_fa1_flatpulse.asc
* Generated by LTspice 26.0.1 for Windows.
VDD VDD 0 5
VB B 0 PULSE(5 0 100n 20n 20n 480n 1u 10)
C1 N013 0 10p
R1 N013 0 200k
VA A 0 PULSE(5 0 100n 20n 20n 230n 500n 10)
Rcout Cout N013 {Rcout}
XX1 N003 A VDD VDD pmos_t1 ;pnba D)G)S)B
XX3 N001 Cin N003 VDD pmos_t1 ;pnba D)G)S)B
XX2 N003 B VDD VDD pmos_t1 ;pnba D)G)S)B
XX7 N005 B VDD VDD pmos_t1 ;pnba D)G)S)B
XX8 N001 A N005 VDD pmos_t1 ;pnba D)G)S)B
XX4 N001 Cin N009 0 nmos_t1 ;pnba D)G)S)B
XX5 N009 A 0 0 nmos_t1 ;pnba D)G)S)B
XX6 N009 B 0 0 nmos_t1 ;pnba D)G)S)B
XX9 N001 A N011 0 nmos_t1 ;pnba D)G)S)B
XX10 N011 B 0 0 nmos_t1 ;pnba D)G)S)B
XX11 Cout N001 VDD VDD pmos_t1 ;pnba D)G)S)B
XX12 Cout N001 0 0 nmos_t1 ;pnba D)G)S)B
XX13 N004 A VDD VDD pmos_t1 ;pnba D)G)S)B
XX16 N007 N001 N004 VDD pmos_t1 ;pnba D)G)S)B
XX15 N004 Cin VDD VDD pmos_t1 ;pnba D)G)S)B
XX17 N007 N001 N010 0 nmos_t1 ;pnba D)G)S)B
XX18 N010 A 0 0 nmos_t1 ;pnba D)G)S)B
XX20 N010 Cin 0 0 nmos_t1 ;pnba D)G)S)B
XX14 N004 B VDD VDD pmos_t1 ;pnba D)G)S)B
XX19 N010 B 0 0 nmos_t1 ;pnba D)G)S)B
XX21 N002 Cin VDD VDD pmos_t1 ;pnba D)G)S)B
XX22 N006 B N002 VDD pmos_t1 ;pnba D)G)S)B
XX23 N007 A N006 VDD pmos_t1 ;pnba D)G)S)B
XX26 N012 Cin 0 0 nmos_t1 ;pnba D)G)S)B
XX25 N008 B N012 0 nmos_t1 ;pnba D)G)S)B
XX24 N007 A N008 0 nmos_t1 ;pnba D)G)S)B
XX27 S N007 VDD VDD pmos_t1 ;pnba D)G)S)B
XX28 S N007 0 0 nmos_t1 ;pnba D)G)S)B
C2 N014 0 10p
R2 N014 0 200k
Rsum S N014 {Rsum}
VCin Cin 0 PULSE(5 0 100n 20n 20n 980n 2u 10)
.lib '../../lib/cfg.lib'
.tran 4u
.param Rcout = 1m, Rsum = 1m
.meas RMS-p-current RMS (Ix(X2:G)+Ix(X2:D)+Ix(X2:S)+Ix(X2:B))
.meas RMS-n-current RMS (Ix(X9:G)+Ix(X9:D)+Ix(X9:S)+Ix(X9:B))
.meas AVG-total power AVG(-V(vdd)*I(vdd))
* Full adder\nfrom paper "Combinational CMOS Logic Circuits", page 15\n \n-28 transistors
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2652 1304
WIRE -208 -336 -256 -336
WIRE 32 -336 32 -384
WIRE 32 -336 -208 -336
WIRE 80 -336 32 -336
WIRE 256 -336 80 -336
WIRE 304 -336 256 -336
WIRE 720 -336 720 -384
WIRE 720 -336 304 -336
WIRE 1088 -336 720 -336
WIRE 1136 -336 1088 -336
WIRE 1392 -336 1392 -384
WIRE 1392 -336 1136 -336
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WIRE -16 -240 -48 -240
WIRE 400 -240 352 -240
WIRE 1040 -240 1008 -240
WIRE 1344 -240 1312 -240
WIRE 1648 -240 1616 -240
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WIRE 1136 -208 1136 -336
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WIRE 1984 -32 1984 -64
WIRE 2304 -32 2304 -48
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WIRE 2080 -16 2032 -16
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WIRE 672 0 640 0
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WIRE 560 112 304 112
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WIRE 2576 112 2304 112
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WIRE 2352 272 2304 272
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WIRE -864 320 -864 288
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WIRE -112 336 -256 336
WIRE 32 336 -112 336
WIRE 1392 336 1392 256
WIRE 1392 336 1088 336
WIRE 1696 336 1392 336
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WIRE 1984 336 1936 336
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WIRE 32 384 32 336
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WIRE 1392 384 1392 336
WIRE 1696 384 1696 336
WIRE 1984 416 1984 384
WIRE -208 432 -256 432
WIRE 80 432 32 432
WIRE 304 432 256 432
WIRE 1136 432 1088 432
WIRE 1440 432 1392 432
WIRE 1744 432 1696 432
WIRE -864 448 -864 400
WIRE -304 464 -336 464
WIRE -16 464 -48 464
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WIRE 1040 464 1008 464
WIRE 1344 464 1312 464
WIRE 1648 464 1616 464
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WIRE -208 560 -256 560
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WIRE 256 560 80 560
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WIRE 304 560 256 560
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WIRE 1136 560 1088 560
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WIRE 1392 560 1136 560
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WIRE 1440 560 1392 560
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WIRE 1696 560 1440 560
WIRE 1744 560 1744 432
WIRE 1744 560 1696 560
WIRE 1936 560 1936 464
WIRE 1936 560 1744 560
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WIRE 1984 560 1936 560
WIRE -864 576 -864 544
WIRE 32 608 32 560
WIRE 1392 608 1392 560
WIRE -864 704 -864 656
WIRE 752 800 752 768
WIRE 992 800 992 768
WIRE 752 912 752 880
WIRE 752 912 704 912
WIRE 800 912 752 912
WIRE 992 912 992 880
WIRE 992 912 944 912
WIRE 1040 912 992 912
WIRE 800 944 800 912
WIRE 1040 944 1040 912
WIRE 704 960 704 912
WIRE 944 960 944 912
WIRE 704 1056 704 1024
WIRE 752 1056 704 1056
WIRE 800 1056 800 1024
WIRE 800 1056 752 1056
WIRE 944 1056 944 1024
WIRE 992 1056 944 1056
WIRE 1040 1056 1040 1024
WIRE 1040 1056 992 1056
WIRE 752 1104 752 1056
WIRE 992 1104 992 1056
FLAG -864 -96 0
FLAG 752 768 Cout
IOPIN 752 768 In
FLAG -864 -272 VDD
IOPIN -864 -272 Out
FLAG -864 288 B
IOPIN -864 288 Out
FLAG -864 448 0
FLAG -864 32 A
IOPIN -864 32 Out
FLAG -864 192 0
FLAG -336 -240 A
IOPIN -336 -240 In
FLAG -192 -16 Cin
IOPIN -192 -16 In
FLAG -48 -240 B
IOPIN -48 -240 In
FLAG 400 -240 B
IOPIN 400 -240 In
FLAG 400 -16 A
IOPIN 400 -16 In
FLAG -192 240 Cin
IOPIN -192 240 In
FLAG -336 464 A
IOPIN -336 464 In
FLAG -48 464 B
IOPIN -48 464 In
FLAG 32 608 0
FLAG 400 240 A
IOPIN 400 240 In
FLAG 400 464 B
IOPIN 400 464 In
FLAG 768 -128 Cout
IOPIN 768 -128 Out
FLAG 720 80 0
FLAG 1008 -240 A
IOPIN 1008 -240 In
FLAG 1616 -240 Cin
IOPIN 1616 -240 In
FLAG 1008 464 A
IOPIN 1008 464 In
FLAG 1616 464 Cin
IOPIN 1616 464 In
FLAG 1312 -240 B
IOPIN 1312 -240 In
FLAG 1312 464 B
IOPIN 1312 464 In
FLAG 2080 -272 Cin
IOPIN 2080 -272 In
FLAG 2080 -144 B
IOPIN 2080 -144 In
FLAG 2080 -16 A
IOPIN 2080 -16 In
FLAG 2080 496 Cin
IOPIN 2080 496 In
FLAG 2080 368 B
IOPIN 2080 368 In
FLAG 2080 240 A
IOPIN 2080 240 In
FLAG 2576 112 S
IOPIN 2576 112 Out
FLAG 1392 608 0
FLAG 32 -384 VDD
IOPIN 32 -384 Out
FLAG 1392 -384 VDD
IOPIN 1392 -384 Out
FLAG 2304 -96 VDD
IOPIN 2304 -96 Out
FLAG 2304 320 0
FLAG 720 -384 VDD
IOPIN 720 -384 Out
FLAG 752 1104 0
FLAG 992 768 S
IOPIN 992 768 In
FLAG 992 1104 0
FLAG -864 544 Cin
IOPIN -864 544 Out
FLAG -864 704 0
FLAG -32 272 0
FLAG 224 272 0
FLAG -32 -16 VDD
IOPIN -32 -16 Out
FLAG 224 -16 VDD
IOPIN 224 -16 Out
FLAG 1456 -16 VDD
IOPIN 1456 -16 Out
FLAG 1456 272 0
SYMBOL voltage -864 -240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL voltage -864 304 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VB
SYMATTR Value PULSE(5 0 100n 20n 20n 480n 1u 10)
SYMBOL cap 688 960 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL res 784 928 R0
SYMATTR InstName R1
SYMATTR Value 200k
SYMBOL voltage -864 48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VA
SYMATTR Value PULSE(5 0 100n 20n 20n 230n 500n 10)
SYMBOL res 736 784 R0
SYMATTR InstName Rcout
SYMATTR Value {Rcout}
SYMBOL pmos4 -304 -160 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X1
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 -160 64 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X3
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 -16 -160 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X2
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 352 -160 R180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X7
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 352 64 R180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X8
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL nmos4 -160 160 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X4
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 -304 384 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X5
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 -16 384 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X6
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 352 160 M0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X9
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 352 384 M0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X10
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL pmos4 672 -176 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X11
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL nmos4 672 -80 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X12
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL pmos4 1040 -160 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X13
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 1344 64 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X16
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 1648 -160 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X15
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL nmos4 1344 160 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X17
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 1040 384 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X18
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 1648 384 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X20
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL pmos4 1344 -160 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X14
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL nmos4 1344 384 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X19
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL pmos4 2032 -192 R180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X21
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 2032 -64 R180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X22
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL pmos4 2032 64 R180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X23
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL nmos4 2032 416 M0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X26
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 2032 288 M0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X25
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL nmos4 2032 160 M0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X24
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL pmos4 2256 64 M180
WINDOW 0 51 80 Left 2
WINDOW 3 52 23 Invisible 2
SYMATTR InstName X27
SYMATTR Value pmos_t1
SYMATTR Prefix X
SYMBOL nmos4 2256 160 R0
WINDOW 0 53 82 Left 2
WINDOW 3 53 23 Invisible 2
SYMATTR InstName X28
SYMATTR Value nmos_t1
SYMATTR Prefix X
SYMBOL cap 928 960 R0
SYMATTR InstName C2
SYMATTR Value 10p
SYMBOL res 1024 928 R0
SYMATTR InstName R2
SYMATTR Value 200k
SYMBOL res 976 784 R0
SYMATTR InstName Rsum
SYMATTR Value {Rsum}
SYMBOL voltage -864 560 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VCin
SYMATTR Value PULSE(5 0 100n 20n 20n 980n 2u 10)
TEXT -248 744 Left 2 !.lib '../../lib/cfg.lib'\n.tran 4u\n.param Rcout = 1m, Rsum = 1m\n.meas RMS-p-current RMS (Ix(X2:G)+Ix(X2:D)+Ix(X2:S)+Ix(X2:B))\n.meas RMS-n-current RMS (Ix(X9:G)+Ix(X9:D)+Ix(X9:S)+Ix(X9:B))\n.meas AVG-total power AVG(-V(vdd)*I(vdd))
TEXT -256 1136 Left 4 ;Full adder\nfrom paper "Combinational CMOS Logic Circuits", page 15\n \n-28 transistors