* Z:\home\khalils\Downloads\files\data\raw_asc\868fcbefb426_diff.asc
* Generated by LTspice 26.0.1 for Windows.
V1 N010 0 20m
V2 N001 0 -20m
XU1 N001 N002 VDD 0 N003 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
XU2 N010 N002 VDD 0 N009 level2 Avol=1Meg GBW=10Meg Slew=10Meg Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
V4 VDD 0 1
C4 N002 N007 0.5n
V9 N007 0 SINE(0.5 0.5 100k)
R7 N002 0 1k
M1 Vgrad N009 0 N008 NMOS l=0.05u w=2u
M2 Vgrad N003 VDD N004 PMOS l=0.05u w=0.1u
C5 N006 N005 0.5n
V7 N005 0 AC 1
R8 N006 0 1k
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
;tran 0 100u 0 100n
.ac dec 1000 1 10G
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2244 680
WIRE 1040 -240 944 -240
WIRE 1040 -224 1040 -240
WIRE 1040 -128 1040 -144
WIRE 1392 -96 1392 -128
WIRE 1056 0 1056 -16
WIRE 1024 16 976 16
WIRE 1216 16 1216 0
WIRE 1392 16 1392 -16
WIRE 1168 32 1088 32
WIRE 944 48 944 -240
WIRE 1024 48 944 48
WIRE 1056 80 1056 64
WIRE 1216 96 1216 64
WIRE 160 112 48 112
WIRE 336 112 224 112
WIRE 688 112 576 112
WIRE 864 112 752 112
WIRE 976 112 976 16
WIRE 976 112 864 112
WIRE 1216 128 1216 112
WIRE 1312 128 1216 128
WIRE 48 144 48 112
WIRE 336 144 336 112
WIRE 576 144 576 112
WIRE 864 144 864 112
WIRE 1216 144 1216 128
WIRE 1056 192 1056 176
WIRE 1216 192 1216 160
WIRE 976 208 976 112
WIRE 1024 208 976 208
WIRE 1168 224 1088 224
WIRE 1024 240 976 240
WIRE 48 256 48 224
WIRE 336 256 336 224
WIRE 576 256 576 224
WIRE 864 256 864 224
WIRE 1216 256 1216 240
WIRE 976 272 976 240
WIRE 1056 272 1056 256
WIRE 976 384 976 352
FLAG 976 384 0
FLAG 1040 -128 0
FLAG 1056 80 0
FLAG 1056 272 0
FLAG 1056 176 VDD
IOPIN 1056 176 BiDir
FLAG 1056 -16 VDD
IOPIN 1056 -16 BiDir
FLAG 1392 16 0
FLAG 1392 -128 VDD
IOPIN 1392 -128 BiDir
FLAG 576 256 0
FLAG 864 256 0
FLAG 1216 256 0
FLAG 1216 0 VDD
IOPIN 1216 0 BiDir
FLAG 1312 128 Vgrad
IOPIN 1312 128 Out
FLAG 48 256 0
FLAG 336 256 0
SYMBOL voltage 976 256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 20m
SYMBOL voltage 1040 -240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -20m
SYMBOL OpAmps\\UniversalOpAmp2 1056 32 R0
SYMATTR InstName U1
SYMBOL OpAmps\\UniversalOpAmp2 1056 224 R0
SYMATTR InstName U2
SYMBOL voltage 1392 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value 1
SYMBOL cap 752 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 0.5n
SYMBOL voltage 576 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V9
SYMATTR Value SINE(0.5 0.5 100k)
SYMBOL res 880 128 M0
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL nmos4 1168 144 R0
WINDOW 3 56 60 Left 2
SYMATTR InstName M1
SYMATTR Value2 l=0.05u w=2u
SYMBOL pmos4 1168 112 M180
SYMATTR InstName M2
SYMATTR Value2 l=0.05u w=0.1u
SYMBOL cap 224 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 0.5n
SYMBOL voltage 48 128 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V7
SYMATTR Value ""
SYMBOL res 352 128 M0
SYMATTR InstName R8
SYMATTR Value 1k
TEXT 832 504 Left 2 !;tran 0 100u 0 100n
TEXT 88 312 Left 2 !.ac dec 1000 1 10G