* Z:\home\khalils\Downloads\files\data\raw_asc\476e635c67b6_Draft23.asc
* Generated by LTspice 26.0.1 for Windows.
* switch /tap 40K/400k for 1:10 acal transfer?\nie for 3V/0.3V ref
* Does a op good at positive rail \nexist in ltspice?
* For HC, don't need bjt, just low RDSon/low leakage fet.\nOk. issue was not headroom. issue was high burden on DUT.\nalso leading to oscillation.
* Library below included based on ModelFile attribute of instance XU2, XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4625.asy)
RISET2 N005 N001 500R
D6 VCC2 P002 D
Q2 VCC2 N002 N004 0 NPN
R2 N007 N006 10k
XU2 N008 N005 VCC2 0 N006 ADA4625-1 ;pnba In+)In-)V+)V-)OUT
D5 P002 P001 D
D4 P001 N003 D
C2 N005 N006 20p
XM2 N009 N007 N005 DMP31D7L ;pnba D)G)S
XU1 N003 N001 VCC2 0 N002 ADA4625-1 ;pnba In+)In-)V+)V-)OUT
RDUT N010 0 100R
V4 N003 N008 5
R1 N008 0 10k
D2 N004 N001 D
C1 N001 N002 20p
V2 VCC2 0 15
D1 N009 N010 D
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.1
.model MYSW SW(Ron=1 Roff=10G Vt=.5 Vh=-.4)
.include my.lib
.lib ADA4625-1.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1768 872
WIRE -128 -144 -272 -144
WIRE 112 -144 -128 -144
WIRE -128 -112 -128 -144
WIRE -272 -48 -272 -144
WIRE -240 -48 -272 -48
WIRE -128 -32 -128 -48
WIRE -128 -32 -176 -32
WIRE -96 -32 -128 -32
WIRE -240 -16 -448 -16
WIRE 16 16 -32 16
WIRE 112 16 112 -144
WIRE 112 16 80 16
WIRE 160 16 112 16
WIRE 304 16 240 16
WIRE 480 16 304 16
WIRE 736 16 480 16
WIRE -448 32 -448 -16
WIRE 480 64 480 16
WIRE 304 112 304 16
WIRE 384 112 304 112
WIRE 736 112 736 16
WIRE 480 128 448 128
WIRE 560 128 480 128
WIRE 688 128 640 128
WIRE -448 144 -448 112
WIRE 384 144 -448 144
WIRE -448 160 -448 144
WIRE 736 272 736 208
WIRE 736 352 736 336
WIRE 832 352 736 352
WIRE 736 384 736 352
SYMBOL OpAmps\\ADA4625 -208 -96 R0
WINDOW 3 -59 187 Left 2
SYMATTR InstName U1
SYMBOL cap 464 64 R0
SYMATTR InstName C2
SYMATTR Value 20p
SYMBOL voltage 16 384 R0
WINDOW 0 54 29 Left 2
WINDOW 3 50 56 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 720 368 R0
SYMATTR InstName RDUT
SYMATTR Value 100R
SYMBOL res 656 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL pmos 688 208 M180
WINDOW 0 63 76 Left 2
WINDOW 3 57 35 Left 2
SYMATTR InstName M2
SYMATTR Value DMP31D7L
SYMATTR Prefix X
SYMBOL res 256 0 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName ISET2
SYMATTR Value 500R
SYMBOL diode 16 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMBOL diode -464 -208 R0
SYMATTR InstName D6
SYMBOL OpAmps\\ADA4625 416 64 R0
WINDOW 3 -59 187 Left 2
SYMATTR InstName U2
SYMBOL voltage -448 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 46 44 Left 2
WINDOW 0 38 16 Left 2
SYMATTR Value 5
SYMATTR InstName V4
SYMBOL cap -144 -112 R0
SYMATTR InstName C1
SYMATTR Value 20p
SYMBOL res -464 144 R0
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL diode -464 -144 R0
SYMATTR InstName D5
SYMBOL npn -96 -80 R0
SYMATTR InstName Q2
SYMBOL diode -464 -80 R0
SYMATTR InstName D4
SYMBOL diode 720 272 R0
SYMATTR InstName D1
FLAG 16 400 VCC2
FLAG 416 96 VCC2
FLAG -208 -64 VCC2
FLAG 736 464 0
FLAG -32 -80 VCC2
FLAG -448 -208 VCC2
FLAG -448 240 0
FLAG -208 0 0
FLAG 416 160 0
FLAG 16 480 0
TEXT -832 -248 Left 2 !.tran 0.1
TEXT -864 480 Left 2 ;switch /tap 40K/400k for 1:10 acal transfer?\nie for 3V/0.3V ref
TEXT -824 576 Left 2 !.model MYSW SW(Ron=1 Roff=10G Vt=.5 Vh=-.4)
TEXT -816 -144 Left 2 ;Does a op good at positive rail \nexist in ltspice?
TEXT -776 -328 Left 2 !.include my.lib
TEXT 560 -136 Left 2 ;For HC, don't need bjt, just low RDSon/low leakage fet.\nOk. issue was not headroom. issue was high burden on DUT.\nalso leading to oscillation.