Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\MAX42403A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\MAX42403A.asy)
R2 vOUT N004 49.9k
C1 N003 0 2.2
Rload vOUT 0 0.95
R1 PGOOD N003 20k
C3 vOUT 0 47 Rser=2m
C4 vOUT N004 33p
L1 N002 vOUT 6.8 Rser=17.6m
R3 N004 0 15.8k
XU1 0 0 vIN vIN N002 N001 N003 N003 N004 PGOOD N003 MAX42403A ;pnba GND)PGND)EN)SUP)LX)BST)BIAS)SPS)FB)PGOOD)SYNC
C2 N001 N002 0.1
V1 vIN 0 12
.tran 3m startup
.lib MAX42403A.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 64 -144 48 -144
WIRE 144 -144 64 -144
WIRE 176 -144 144 -144
WIRE 512 -144 464 -144
WIRE 48 -128 48 -144
WIRE 512 -128 512 -144
WIRE 144 -96 144 -144
WIRE 176 -96 144 -96
WIRE 48 -32 48 -48
WIRE 512 -32 512 -64
WIRE 512 -32 464 -32
WIRE 608 -32 512 -32
WIRE 736 -32 688 -32
WIRE 832 -32 736 -32
WIRE 960 -32 832 -32
WIRE 1024 -32 960 -32
WIRE 1056 -32 1024 -32
WIRE 736 -16 736 -32
WIRE 1056 -16 1056 -32
WIRE 832 0 832 -32
WIRE 960 0 960 -32
WIRE 176 16 112 16
WIRE 736 64 736 48
WIRE 1056 80 1056 64
WIRE 832 96 832 80
WIRE 832 96 464 96
WIRE 960 96 960 64
WIRE 960 96 832 96
WIRE 112 128 112 16
WIRE 176 128 112 128
WIRE 832 128 832 96
WIRE 480 224 464 224
WIRE 832 224 832 208
WIRE 112 272 112 128
WIRE 112 272 32 272
WIRE 176 272 112 272
WIRE 32 288 32 272
WIRE 512 288 464 288
WIRE 608 288 512 288
WIRE 320 352 320 336
WIRE 32 368 32 352
WIRE 112 400 112 272
WIRE 496 400 112 400
WIRE 608 400 608 288
WIRE 608 400 576 400
SYMBOL res 1040 -32 R0
SYMATTR InstName Rload
SYMATTR Value 0.95
SYMBOL MAX42403A 320 96 R0
SYMATTR InstName U1
SYMBOL ind 592 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 6.8
SYMATTR SpiceLine Rser=17.6m
SYMBOL res 592 384 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 20k
SYMBOL voltage 48 -144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL cap 944 0 R0
SYMATTR InstName C4
SYMATTR Value 33p
SYMBOL cap 496 -128 R0
SYMATTR InstName C2
SYMATTR Value 0.1
SYMBOL cap 720 -16 R0
SYMATTR InstName C3
SYMATTR Value 47
SYMATTR SpiceLine Rser=2m
SYMBOL res 816 112 R0
SYMATTR InstName R3
SYMATTR Value 15.8k
SYMBOL cap 16 288 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMBOL res 816 -16 R0
SYMATTR InstName R2
SYMATTR Value 49.9k
FLAG 48 -32 0
FLAG 32 368 0
FLAG 320 352 0
FLAG 736 64 0
FLAG 1056 80 0
FLAG 64 -144 vIN
FLAG 1024 -32 vOUT
FLAG 480 224 0
FLAG 832 224 0
FLAG 512 288 PGOOD
TEXT 648 376 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0a6418f3f0c3_tran.asc
* Generated by LTspice 26.0.1 for Windows.
R1 Vcc Vout 220
V2 Vin 0 PULSE(0 3.3 10n 5n 5n 500u 1m 10)
Q1 Vout N001 0 0 2N3904
V1 Vcc 0 5V
R2 Vin N001 10k
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 12m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 368 112 96 112
WIRE 656 112 368 112
WIRE 96 144 96 112
WIRE 656 144 656 112
WIRE 96 256 96 224
WIRE 656 272 656 224
WIRE 736 272 656 272
WIRE 768 272 736 272
WIRE 656 336 656 272
WIRE 208 384 96 384
WIRE 304 384 208 384
WIRE 592 384 384 384
WIRE 96 528 96 464
WIRE 656 528 656 432
WIRE 656 528 96 528
WIRE 96 592 96 528
SYMBOL res 640 128 R0
SYMATTR InstName R1
SYMATTR Value 220
SYMBOL voltage 96 128 R0
SYMATTR InstName V1
SYMATTR Value 5V
SYMBOL res 288 400 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage 96 368 R0
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3 10n 5n 5n 500u 1m 10)
SYMBOL npn 592 336 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
FLAG 96 256 0
FLAG 736 272 Vout
FLAG 368 112 Vcc
FLAG 208 384 Vin
FLAG 96 592 0
TEXT 336 592 Left 2 !.tran 12m
* Z:\home\khalils\Downloads\files\data\raw_asc\34f34aa41f90_CompPentoCarG1Step.asc
* Generated by LTspice 26.0.1 for Windows.
XU2 0 N003 N002 0 N001 7591Pent Pentrode ;pnba Cathode)G1)G2)G3)Anode
Vg2 N002 0 350
Vp N001 0 0
Vg1 N003 0 0
XU1 0 N003 N002 0 N001 EL34Pent Pentrode ;pnba Cathode)G1)G2)G3)Anode
.dc Vp 0 500 100 Vg1 0 -50 10
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 48 64 -144 64
WIRE 288 64 48 64
WIRE 368 80 144 80
WIRE 208 96 -64 96
WIRE 48 112 48 64
WIRE 288 112 288 64
WIRE -144 128 -144 64
WIRE 0 160 -16 160
WIRE 240 160 224 160
WIRE 144 176 144 80
WIRE 144 176 96 176
WIRE 368 176 368 80
WIRE 368 176 336 176
WIRE -64 192 -64 96
WIRE 0 192 -64 192
WIRE 144 192 144 176
WIRE 208 192 208 96
WIRE 240 192 208 192
WIRE -64 208 -64 192
WIRE 224 256 224 160
WIRE 256 256 256 240
WIRE 256 256 224 256
WIRE -144 304 -144 208
WIRE -64 304 -64 288
WIRE -64 304 -144 304
WIRE -16 304 -16 160
WIRE -16 304 -64 304
WIRE 16 304 16 240
WIRE 16 304 -16 304
WIRE 144 304 144 272
WIRE 144 304 16 304
WIRE 224 304 224 256
WIRE 224 304 144 304
WIRE 16 320 16 304
SYMBOL Valve\\Pentode 48 176 R0
WINDOW 0 -71 -61 Left 0
WINDOW 38 34 105 Center 0
SYMATTR InstName U1
SYMATTR SpiceModel EL34Pent
SYMBOL voltage 144 176 R0
WINDOW 0 -19 60 Left 0
SYMATTR InstName Vg2
SYMATTR Value 350
SYMBOL voltage -64 192 R0
WINDOW 0 -18 61 Left 0
SYMATTR InstName Vg1
SYMATTR Value 0
SYMBOL Valve\\Pentode 288 176 R0
WINDOW 0 -66 -63 Left 0
WINDOW 38 5 104 Center 0
SYMATTR InstName U2
SYMATTR SpiceModel 7591Pent
SYMBOL voltage -144 112 R0
WINDOW 0 -16 57 Left 0
SYMATTR InstName Vp
SYMATTR Value 0
FLAG 16 320 0
TEXT 40 320 Left 0 !.dc Vp 0 500 100 Vg1 0 -50 10
* Z:\home\khalils\Downloads\files\data\raw_asc\4ea2ed881c06_char-pmos-1.asc
* Generated by LTspice 26.0.1 for Windows.
;op
Vdd N001 0 1.8
V1 N002 0 0.4
M1 0 N002 N001 N001 p18.6 l=1u w=10u ad={5*W*LAMBDA} as={5*W*LAMBDA} pd={10*LAMBDA+2*W} ps={10*LAMBDA+2*W}
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib 'ts18sl_scl.lib' tt_18
.param L=180n W=5u n=1 LAMBDA=0.09u
.dc dec V1 1.5 0.2 1000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1308 704
WIRE 640 224 640 208
WIRE 1232 224 640 224
WIRE 640 272 640 224
WIRE 720 272 640 272
WIRE 640 288 640 272
WIRE 1232 288 1232 224
WIRE 592 304 368 304
WIRE 720 336 720 272
WIRE 720 336 640 336
WIRE 368 352 368 304
WIRE 1232 384 1232 368
SYMBOL voltage 368 336 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0.4
SYMBOL pmos4 592 384 M180
SYMATTR InstName M1
SYMATTR Value p18.6
SYMATTR Value2 l=1u w=10u ad={5*W*LAMBDA} as={5*W*LAMBDA} pd={10*LAMBDA+2*W} ps={10*LAMBDA+2*W}
SYMBOL voltage 1232 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vdd
SYMATTR Value 1.8
FLAG 1232 384 0
FLAG 368 432 0
FLAG 640 384 0
TEXT 128 72 Left 2 !.lib 'ts18sl_scl.lib' tt_18
TEXT 368 152 Left 2 !.param L=180n W=5u n=1 LAMBDA=0.09u
TEXT 536 88 Left 2 !;op
TEXT 736 48 Left 2 !.dc dec V1 1.5 0.2 1000
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1174HV-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1174HV-5.asy)
V1 IN 0 9
C2 OUT 0 100 Rser=0.02
Rload OUT 0 15
L1 N001 OUT 100 Rser=0.02 Rpar=5000
XU1 OUT N003 N002 0 N001 IN IN IN LTC1174 top=93.5K bot=31.5K ;pnba FB)LBout)LBin)GND)SW)Vin)Ipgm)_SHDN
D1 0 N001 MBRS140
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LTC1174.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1584 1140
WIRE 464 480 336 480
WIRE 624 480 464 480
WIRE 336 496 336 480
WIRE 624 512 624 480
WIRE 464 560 464 480
WIRE 496 560 464 560
WIRE 816 560 752 560
WIRE 880 560 816 560
WIRE 976 560 960 560
WIRE 1088 560 976 560
WIRE 816 576 816 560
WIRE 1088 576 1088 560
WIRE 336 592 336 576
WIRE 496 624 480 624
WIRE 768 624 752 624
WIRE 816 656 816 640
WIRE 1088 672 1088 656
WIRE 464 688 464 560
WIRE 496 688 464 688
WIRE 976 688 976 560
WIRE 976 688 752 688
WIRE 976 704 976 688
WIRE 624 752 624 736
WIRE 976 784 976 768
SYMBOL IND 864 576 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL res 1072 560 R0
SYMATTR InstName Rload
SYMATTR Value 15
SYMBOL POLCAP 960 704 R0
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL SCHOTTKY 800 640 M180
WINDOW 0 36 62 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL VOLTAGE 336 480 R0
SYMATTR InstName V1
SYMATTR Value 9
SYMBOL PowerProducts\\LTC1174HV-5 624 624 R0
SYMATTR InstName U1
FLAG 1088 560 OUT
FLAG 976 784 0
FLAG 1088 672 0
FLAG 816 656 0
FLAG 624 752 0
FLAG 336 592 0
FLAG 336 480 IN
TEXT 712 792 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1316.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1316.asy)
R3 N005 0 5K
Rload OUT 0 100
R1 OUT N002 1Meg
L1 IN N001 47 Rser=0.02 Rpar=5000
XU1 N004 N003 N005 0 N001 IN IN N002 LT1316 ;pnba LBO)LBI)Rset)GND)SW)Vin)_SHDN)FB
D1 N001 OUT MBRS140
R2 N002 0 324K
V1 IN 0 2
C2 OUT 0 47 Rser=0.02
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 2m startup
.lib LT1316.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1508 1024
WIRE 512 448 400 448
WIRE 624 448 512 448
WIRE 672 448 624 448
WIRE 784 448 752 448
WIRE 864 448 784 448
WIRE 1008 448 928 448
WIRE 1136 448 1008 448
WIRE 1248 448 1136 448
WIRE 400 464 400 448
WIRE 1136 464 1136 448
WIRE 1248 464 1248 448
WIRE 1008 480 1008 448
WIRE 624 512 624 448
WIRE 784 512 784 448
WIRE 400 560 400 544
WIRE 1136 560 1136 528
WIRE 1248 560 1248 544
WIRE 512 608 512 448
WIRE 544 608 512 608
WIRE 1008 608 1008 560
WIRE 1008 608 864 608
WIRE 1008 624 1008 608
WIRE 544 704 528 704
WIRE 880 704 864 704
WIRE 1008 720 1008 704
WIRE 624 816 624 800
WIRE 784 816 784 800
WIRE 624 912 624 896
SYMBOL IND 656 464 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 47
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL RES 1232 448 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL RES 992 464 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL RES 992 608 R0
SYMATTR InstName R2
SYMATTR Value 324K
SYMBOL SCHOTTKY 864 464 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL POLCAP 1120 464 R0
SYMATTR InstName C2
SYMATTR Value 47
SYMATTR SpiceLine Rser=0.02
SYMBOL VOLTAGE 400 448 R0
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL RES 608 800 R0
SYMATTR InstName R3
SYMATTR Value 5K
SYMBOL PowerProducts\\LT1316 704 656 R0
SYMATTR InstName U1
FLAG 1248 448 OUT
FLAG 400 560 0
FLAG 1008 720 0
FLAG 1136 560 0
FLAG 1248 560 0
FLAG 624 912 0
FLAG 784 816 0
FLAG 400 448 IN
TEXT 960 784 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP172-2.9.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP172-2.9.asy)
C1 OUT 0 1
RLOAD OUT 0 9.65
V1 IN 0 3.6
XU1 OUT IN IN 0 ADP172-2.9 ;pnba Vout)Vin)En)GND
.tran 2m startup
.lib ADP172-2.9.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 80 -48 80
WIRE 48 80 -32 80
WIRE 64 80 48 80
WIRE 304 80 256 80
WIRE 336 80 304 80
WIRE 384 80 336 80
WIRE -48 96 -48 80
WIRE 304 96 304 80
WIRE 304 176 304 160
WIRE 384 176 384 160
WIRE -48 192 -48 176
WIRE 48 192 48 80
WIRE 64 192 48 192
WIRE 272 192 256 192
SYMBOL cap 288 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP172-2.9 160 192 R0
SYMATTR InstName U1
SYMBOL voltage -48 80 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL res 368 64 R0
SYMATTR InstName RLOAD
SYMATTR Value 9.65
FLAG -48 192 0
FLAG 304 176 0
FLAG 272 192 0
FLAG 384 176 0
FLAG -32 80 IN
FLAG 336 80 OUT
TEXT 160 256 Center 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\0be18cbf0459_ltinversora.asc
* Generated by LTspice 26.0.1 for Windows.
V1 Vin 0 1V
R1 Vx Vin 1k
R2 Vout Vx 10k
E1 Vout 0 0 Vx 1000000
.op
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 112 -80 112
WIRE 128 112 32 112
WIRE 208 112 128 112
WIRE 352 112 288 112
WIRE -80 176 -80 112
WIRE 288 176 288 112
WIRE 128 192 128 112
WIRE 240 192 128 192
WIRE -80 288 -80 256
WIRE 240 288 240 240
WIRE 240 288 -80 288
WIRE 288 288 288 256
WIRE 288 288 240 288
WIRE 240 320 240 288
FLAG 240 320 0
FLAG -80 112 Vin
FLAG 352 112 Vout
FLAG 128 112 Vx
SYMBOL voltage -80 160 R0
SYMATTR InstName V1
SYMATTR Value 1V
SYMBOL res 48 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res 304 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL e2 288 160 R0
SYMATTR InstName E1
SYMATTR Value 1000000
TEXT -88 320 Left 2 !.op
* Z:\home\khalils\Downloads\files\data\raw_asc\44a1e6405ecf_simulation.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 0 8.2k
R2 vg 0 4.7k
XM1 vd vg vs Si2301CDS ;pnba D)G)S
V2 vin 0 PWL(0 3.4 1 3.24 2 3.4)
D1 N001 vs Dideal
V1 N001 0 PWL(0 3.3 1 3.3 1.001 0)
I1 vs 0 125m
R3 vin vd 390m
Q2 vg N002 vs 0 DI_DMMT3906
Q1 N002 N002 vin 0 DI_DMMT3906
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.include si2301cds_ps_rc.lib
.tran 2
.include DMMT3906.spice
.model Dideal D(Ron=0.0001 Roff=100G Vfwd=0)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1036 680
WIRE -16 0 -128 0
WIRE 128 0 64 0
WIRE 176 0 128 0
WIRE 336 0 272 0
WIRE 592 0 336 0
WIRE 624 0 592 0
WIRE 720 0 688 0
WIRE -128 80 -128 0
WIRE 112 80 -128 80
WIRE 336 80 336 0
WIRE -128 96 -128 80
WIRE 592 96 592 0
WIRE 720 96 720 0
WIRE 192 128 176 128
WIRE 272 128 192 128
WIRE 112 208 112 176
WIRE 192 208 192 128
WIRE 192 208 112 208
WIRE 256 208 256 48
WIRE 336 208 336 176
WIRE 336 208 256 208
WIRE 112 224 112 208
WIRE 336 224 336 208
WIRE -128 352 -128 176
WIRE 112 352 112 304
WIRE 336 352 336 304
WIRE 592 352 592 176
WIRE 720 352 720 176
SYMBOL res 96 208 R0
SYMATTR InstName R1
SYMATTR Value 8.2k
SYMBOL diode 688 -16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMATTR Value Dideal
SYMBOL voltage 720 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 3.3 1 3.3 1.001 0)
SYMBOL res 320 208 R0
SYMATTR InstName R2
SYMATTR Value 4.7k
SYMBOL pnp 272 176 M180
SYMATTR InstName Q2
SYMATTR Value DI_DMMT3906
SYMBOL res -32 16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 390m
SYMBOL pnp 176 176 R180
SYMATTR InstName Q1
SYMATTR Value DI_DMMT3906
SYMBOL current 592 96 R0
SYMATTR InstName I1
SYMATTR Value 125m
SYMBOL pmos 176 48 R270
SYMATTR InstName M1
SYMATTR Value Si2301CDS
SYMATTR Prefix X
SYMBOL voltage -128 80 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PWL(0 3.4 1 3.24 2 3.4)
FLAG 112 352 0
FLAG 336 352 0
FLAG 592 352 0
FLAG -128 352 0
FLAG 336 208 vg
FLAG 336 0 vs
FLAG -128 0 vin
FLAG 720 352 0
FLAG 128 0 vd
TEXT 344 -128 Left 2 !.include si2301cds_ps_rc.lib
TEXT 344 -64 Left 2 !.tran 2
TEXT 344 -96 Left 2 !.include DMMT3906.spice
TEXT 352 -160 Left 2 !.model Dideal D(Ron=0.0001 Roff=100G Vfwd=0)
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1076-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1076-5.asy)
V1 IN 0 20
C2 N002 0 500 Rser=.1
L1 N001 N002 100
Rload N002 0 5
C1 N006 N005 .033
XU1 IN N001 N004 0 N002 N005 N003 LT1076-5 ;pnba Vin)SW)Ilim)GND)Sense)Vc)SHDN
R2 0 N006 1.5K
R1 N004 0 70K
D1 0 N001 MBRS340
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5m startup
.lib LT1076-5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3436 2244
WIRE 1296 1120 1040 1120
WIRE 1472 1120 1440 1120
WIRE 1520 1120 1472 1120
WIRE 1632 1120 1600 1120
WIRE 1696 1120 1632 1120
WIRE 1792 1120 1696 1120
WIRE 1040 1136 1040 1120
WIRE 1296 1136 1296 1120
WIRE 1696 1136 1696 1120
WIRE 1792 1136 1792 1120
WIRE 1472 1152 1472 1120
WIRE 1168 1200 1136 1200
WIRE 1440 1200 1440 1120
WIRE 1440 1200 1424 1200
WIRE 1040 1232 1040 1216
WIRE 1472 1232 1472 1216
WIRE 1696 1232 1696 1200
WIRE 1792 1232 1792 1216
WIRE 1632 1280 1632 1120
WIRE 1632 1280 1424 1280
WIRE 1072 1360 1056 1360
WIRE 1168 1360 1152 1360
WIRE 1440 1360 1424 1360
WIRE 1536 1360 1504 1360
WIRE 1632 1360 1616 1360
WIRE 1296 1440 1296 1424
SYMBOL cap 1680 1136 R0
SYMATTR InstName C2
SYMATTR Value 500
SYMATTR SpiceLine Rser=.1
SYMBOL res 1776 1120 R0
SYMATTR InstName Rload
SYMATTR Value 5
SYMBOL cap 1504 1344 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .033
SYMBOL ind 1504 1136 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100
SYMBOL PowerProducts\\LT1076-5 1296 1280 R0
SYMATTR InstName U1
SYMBOL res 1632 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1.5K
SYMBOL voltage 1040 1120 R0
SYMATTR InstName V1
SYMATTR Value 20
SYMBOL schottky 1456 1216 M180
WINDOW 0 24 72 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 1168 1344 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 70K
FLAG 1040 1232 0
FLAG 1296 1440 0
FLAG 1056 1360 0
FLAG 1472 1232 0
FLAG 1792 1232 0
FLAG 1696 1232 0
FLAG 1632 1360 0
FLAG 1040 1120 IN
TEXT 1656 1312 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\RHP50000-CSL.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\RHP50000-CSL.asy)
XU1 IN IN N002 N004 0 0 N007 N001 IN N006 N003 RHP50000-CSL ;pnba VIN)EN)SW)FB)AGND)PGND)RT)PGOOD)MODE/SYNC)ITH)SSTT
R3 OUT N001 500K
C3 N005 0 470p
C1 OUT 0 47 m=3 Rser=10m
R1 OUT N004 140K
Rload OUT 0 0.1
R5 N007 0 274K
V1 IN 0 5
R2 N004 0 100K
R4 N006 N005 15K
L1 N002 OUT 100n Rser=2m
C2 N003 0 4.7n
C5 OUT N004 10p
.tran 0.6m startup
.lib RHP50000-CSL.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2648 1864
WIRE 1408 1248 1376 1248
WIRE 1520 1248 1408 1248
WIRE 1712 1248 1520 1248
WIRE 1376 1280 1376 1248
WIRE 1712 1280 1712 1248
WIRE 1520 1328 1520 1248
WIRE 1552 1328 1520 1328
WIRE 1904 1328 1872 1328
WIRE 2016 1328 1984 1328
WIRE 1376 1376 1376 1360
WIRE 1520 1424 1520 1328
WIRE 1552 1424 1520 1424
WIRE 1904 1424 1872 1424
WIRE 2016 1424 2016 1328
WIRE 2016 1424 1984 1424
WIRE 2144 1424 2016 1424
WIRE 2256 1424 2144 1424
WIRE 2336 1424 2256 1424
WIRE 2384 1424 2336 1424
WIRE 2144 1440 2144 1424
WIRE 2256 1440 2256 1424
WIRE 2384 1440 2384 1424
WIRE 1424 1520 1408 1520
WIRE 1552 1520 1488 1520
WIRE 2016 1520 2016 1504
WIRE 2016 1520 1872 1520
WIRE 2144 1520 2144 1504
WIRE 2144 1520 2016 1520
WIRE 2016 1536 2016 1520
WIRE 2256 1536 2256 1504
WIRE 2384 1536 2384 1520
WIRE 1424 1616 1360 1616
WIRE 1552 1616 1504 1616
WIRE 1904 1616 1872 1616
WIRE 1360 1632 1360 1616
WIRE 1904 1632 1904 1616
WIRE 2016 1632 2016 1616
WIRE 1648 1680 1648 1664
WIRE 1776 1680 1776 1664
WIRE 1360 1712 1360 1696
WIRE 1904 1728 1904 1712
SYMBOL ind 1888 1440 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 100n
SYMATTR SpiceLine Rser=2m
SYMBOL RES 2000 1408 R0
SYMATTR InstName R1
SYMATTR Value 140K
SYMBOL res 2368 1424 R0
SYMATTR InstName Rload
SYMATTR Value 0.1
SYMBOL cap 1488 1504 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL VOLTAGE 1376 1264 R0
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 2000 1520 R0
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL cap 1344 1632 R0
SYMATTR InstName C3
SYMATTR Value 470p
SYMBOL res 1520 1600 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 15K
SYMBOL RHP50000-CSL 1712 1472 R0
WINDOW 0 0 -80 Center 2
WINDOW 3 0 112 Center 2
SYMATTR InstName U1
SYMBOL res 1888 1616 R0
SYMATTR InstName R5
SYMATTR Value 274K
SYMBOL res 2000 1312 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 500K
SYMBOL cap 2240 1440 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 m=3
SYMATTR InstName C1
SYMATTR Value 47
SYMATTR SpiceLine Rser=10m
SYMBOL cap 2128 1440 R0
SYMATTR InstName C5
SYMATTR Value 10p
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1376 1376 0
FLAG 2384 1536 0
FLAG 2016 1632 0
FLAG 1408 1520 0
FLAG 2336 1424 OUT
FLAG 1408 1248 IN
FLAG 1360 1712 0
FLAG 2256 1536 0
FLAG 1904 1728 0
TEXT 1624 1792 Left 2 !.tran 0.6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\04a7602332df_pwm-tuning.asc
* Generated by LTspice 26.0.1 for Windows.
C3 0 N006 100n
V1 N006 0 9V
C2 N003 0 470nF
XM2 N001 N002 0 2N7000 ;pnba D)G)S
R4 N005 N004 10k
R1 N002 N006 1k
V2 N004 0 PULSE(0 5 0 1n 1n {DutyCycle} 100u)
C1 out 0 470nF
R3 out N003 10k
R2 N003 N001 10k
XM1 N001 N002 N006 BS250 ;pnba D)G)S
Q1 N002 N005 0 0 2N2222
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.4
.inc 2N7000.onsemi.lib
.inc BS250.philips.lib
.meas TRAN rippel PP V(out) FROM 180ms TO 230ms
.meas TRAN medel AVG V(out) FROM 180ms TO 230ms
.param ideal=4.5
.meas TRAN diff PARAM medel-ideal
.param DutyCycle=50u
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 1088 680
WIRE 288 -128 192 -128
WIRE 144 -48 0 -48
WIRE 192 -32 192 -48
WIRE 192 -16 192 -32
WIRE 288 80 288 -128
WIRE 288 80 176 80
WIRE 304 80 288 80
WIRE 480 80 384 80
WIRE 544 80 480 80
WIRE 672 80 672 -32
WIRE 672 80 624 80
WIRE 480 96 480 80
WIRE 672 112 672 80
WIRE 0 160 0 -48
WIRE 0 160 -192 160
WIRE 128 160 0 160
WIRE 480 192 480 160
WIRE 672 192 672 176
WIRE -368 208 -416 208
WIRE -256 208 -288 208
WIRE 176 208 176 176
WIRE 208 208 176 208
WIRE 304 208 272 208
WIRE 304 240 304 208
WIRE -192 304 -192 256
WIRE 0 304 0 240
WIRE 80 304 0 304
WIRE 176 304 176 208
WIRE 176 304 80 304
WIRE 80 400 80 384
IOPIN 672 -32 Out
SYMBOL res 400 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -416 192 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 1n 1n {DutyCycle} 100u)
SYMBOL npn -256 160 R0
SYMATTR InstName Q1
SYMATTR Value 2N2222
SYMBOL cap 464 96 R0
SYMATTR InstName C2
SYMATTR Value 470nF
SYMBOL cap 272 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 100n
SYMBOL voltage 80 288 R0
WINDOW 0 44 55 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 9V
SYMBOL pmos 128 80 R0
SYMATTR InstName M1
SYMATTR Value BS250
SYMATTR Prefix X
SYMBOL res -16 144 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL res -272 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 656 112 R0
SYMATTR InstName C1
SYMATTR Value 470nF
SYMBOL nmos 144 -128 R0
SYMATTR InstName M2
SYMATTR Value 2N7000
SYMATTR Prefix X
SYMBOL res 640 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10k
FLAG -416 288 0
FLAG 672 192 0
FLAG -192 304 0
FLAG 80 400 0
FLAG 192 -16 0
FLAG 480 192 0
FLAG 672 -32 out
FLAG 304 240 0
TEXT -864 432 Left 2 !.tran 0.4
TEXT -512 -104 Left 2 !.inc 2N7000.onsemi.lib
TEXT -512 -64 Left 2 !.inc BS250.philips.lib
TEXT -464 -432 Left 2 !.meas TRAN rippel PP V(out) FROM 180ms TO 230ms\n.meas TRAN medel AVG V(out) FROM 180ms TO 230ms
TEXT -464 -376 Left 2 !.param ideal=4.5\n.meas TRAN diff PARAM medel-ideal
TEXT -464 -320 Left 2 !.param DutyCycle=50u