* Z:\home\khalils\Downloads\files\data\raw_asc\2e98e74b1420_supply_selector_simulation.asc
* Generated by LTspice 26.0.1 for Windows.
M1 V_USB_M V_USB_G VOUT VOUT AO6407
M2 V_BAT_M V_BAT_G V_BAT V_BAT AO6407
M3 V_BAT_M V_BAT_G VOUT VOUT AO6407
M4 V_USB_M V_USB_G V_USB V_USB AO6407
V1 N002 0 5
V2 N003 0 12
R_BAT N003 V_BAT 0.01
R_USB V_USB N002 0.01
R_LOAD VOUT 0 6
XU1 V_BAT V_USB VCC 0 V_USB_G LT118A ;pnba In+)In-)V+)V-)OUT
D1 V_BAT N005 D
D2 V_USB N005 D
XU2 0 V_USB_G VCC 0 V_BAT_G LT118A ;pnba In+)In-)V+)V-)OUT
V5 VCC N005 2.3
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.op
* +2.3V to compensate for\nnon rail-to-rail comparator\nand non schottky diode
* Control
* Power
* Vary V1 and V2 then simulate to verify design
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT318A.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 976 680
WIRE 848 -448 -304 -448
WIRE -208 -192 -240 -192
WIRE -80 -192 -128 -192
WIRE -48 -192 -80 -192
WIRE 64 -192 48 -192
WIRE 80 -192 64 -192
WIRE 224 -192 176 -192
WIRE 272 -192 224 -192
WIRE 384 -192 368 -192
WIRE 416 -192 384 -192
WIRE 560 -192 512 -192
WIRE 608 -192 560 -192
WIRE 752 -192 688 -192
WIRE 224 -144 224 -192
WIRE -32 -112 -32 -144
WIRE 96 -112 -32 -112
WIRE 160 -112 160 -144
WIRE 160 -112 96 -112
WIRE 288 -112 288 -144
WIRE 448 -112 288 -112
WIRE 496 -112 496 -144
WIRE 496 -112 448 -112
WIRE -240 -48 -240 -192
WIRE 752 -32 752 -192
WIRE 224 0 224 -64
WIRE -304 112 -304 -448
WIRE 848 112 848 -448
WIRE 848 112 -304 112
WIRE 848 144 -304 144
WIRE 0 336 -80 336
WIRE 16 336 0 336
WIRE 144 336 96 336
WIRE 192 336 144 336
WIRE 496 336 192 336
WIRE -80 384 -80 336
WIRE 0 384 0 336
WIRE 192 464 192 336
WIRE 0 480 0 448
WIRE 80 480 0 480
WIRE 160 480 80 480
WIRE 496 480 496 336
WIRE 352 496 224 496
WIRE 464 496 352 496
WIRE -80 512 -80 448
WIRE 80 512 -80 512
WIRE 160 512 80 512
WIRE 672 512 528 512
WIRE 736 512 672 512
WIRE 464 528 416 528
WIRE 416 544 416 528
WIRE -304 592 -304 144
WIRE 848 592 848 144
WIRE 848 592 -304 592
FLAG -240 32 0
FLAG 752 48 0
FLAG 224 -192 VOUT
FLAG 560 -192 V_BAT
FLAG 448 -112 V_BAT_G
FLAG 96 -112 V_USB_G
FLAG -80 -192 V_USB
FLAG 224 0 0
FLAG 80 480 V_USB
FLAG 80 512 V_BAT
FLAG 192 528 0
FLAG 144 336 VCC
FLAG 352 496 V_USB_G
FLAG 672 512 V_BAT_G
FLAG 496 544 0
FLAG 416 544 0
FLAG 384 -192 V_BAT_M
FLAG 64 -192 V_USB_M
SYMBOL pmos 80 -144 R270
SYMATTR InstName M1
SYMATTR Value AO6407
SYMBOL pmos 416 -144 R270
SYMATTR InstName M2
SYMATTR Value AO6407
SYMBOL pmos 368 -144 M270
SYMATTR InstName M3
SYMATTR Value AO6407
SYMBOL pmos 48 -144 M270
SYMATTR InstName M4
SYMATTR Value AO6407
SYMBOL voltage -240 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 752 -48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL res 704 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R_BAT
SYMATTR Value 0.01
SYMBOL res -112 -208 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R_USB
SYMATTR Value 0.01
SYMBOL res 208 -160 R0
WINDOW 0 -17 6 VRight 2
WINDOW 3 48 45 VRight 2
SYMATTR InstName R_LOAD
SYMATTR Value 6
SYMBOL OpAmps\\LT318A 192 496 R0
SYMATTR InstName U1
SYMBOL diode -64 448 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMBOL diode 16 448 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL OpAmps\\LT318A 496 512 R0
SYMATTR InstName U2
SYMBOL voltage 112 336 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value 2.3
TEXT 808 -472 Left 2 !.op
TEXT 88 208 Left 2 ;+2.3V to compensate for\nnon rail-to-rail comparator\nand non schottky diode
TEXT -272 200 Left 4 ;Control
TEXT -272 -400 Left 4 ;Power
TEXT -16 80 Left 2 ;Vary V1 and V2 then simulate to verify design