Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2224fe056646_Fig16_67.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot -I(VGS)
R1 N003 0 1G
VGS VGS 0 0
R2 N001 0 1G
VB N002 0 1
M1 N001 VGS N003 N002 N_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib cmosedu_models.txt
.dc VB 0 2 1m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1748 680
WIRE 384 -128 384 -144
WIRE 384 -96 384 -128
WIRE 384 16 384 -16
WIRE 576 -144 384 -144
WIRE 624 -336 624 -368
WIRE 624 -224 624 -256
WIRE 624 -96 624 -128
WIRE 624 16 624 -16
WIRE 736 -176 624 -176
WIRE 880 -176 816 -176
WIRE 880 -112 880 -176
SYMBOL voltage 720 -176 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -32 56 VBottom 0
SYMATTR InstName VB
SYMATTR Value 1
SYMBOL voltage 384 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 39 90 Left 0
WINDOW 0 39 62 Left 0
SYMATTR Value 0
SYMATTR InstName VGS
SYMBOL res 640 -240 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R2
SYMATTR Value 1G
SYMBOL res 608 -112 R0
SYMATTR InstName R1
SYMATTR Value 1G
SYMBOL nmos4 576 -224 R0
WINDOW 0 104 24 Invisible 0
WINDOW 3 179 41 Invisible 0
WINDOW 123 -114 109 Left 0
SYMATTR InstName M1
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
FLAG 384 16 0
FLAG 384 -128 VGS
FLAG 880 -112 0
FLAG 624 16 0
FLAG 624 -368 0
TEXT 376 80 Left 0 !.lib cmosedu_models.txt
TEXT 376 56 Left 0 !.dc VB 0 2 1m
TEXT 416 -264 Left 0 ;Plot -I(VGS)
* Z:\tmp\asc_dec_bjh7r6w2\0118652cfe79_NAND_3_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
M8 N001 A VDD VDD P_50n l=50n w=1u
M12 N001 A N002 0 N_50n l=50n w=500n
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 6288 680
WIRE 912 -400 912 -416
WIRE 1168 -400 912 -400
WIRE 1168 -400 1168 -416
WIRE 1168 -368 1168 -400
WIRE 1168 -256 1168 -272
WIRE 1456 -416 1168 -416
SYMBOL pmos4 864 -416 M180
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M8
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 1120 -368 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M12
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
FLAG 1168 -464 VDD
FLAG 912 -464 VDD
FLAG 1168 -208 0
FLAG 1168 -320 0
FLAG 1168 -512 VDD
FLAG 912 -512 VDD
FLAG 864 -496 A
FLAG 1120 -288 A
FLAG 1120 -496 B
FLAG 1120 -176 B
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7171-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7171-3.3.asy)
C2 N001 0 1n
Rload OUT 0 6
XU1 IN OUT IN N001 OUT 0 ADM7171-3.3 ;pnba Vin)Sense)EN)SS)Vout)GND
C1 OUT 0 4.7 Rser=1.5m
V1 IN 0 3.8
.tran 5m startup
.lib ADM7171-3.3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
SYMBOL ADM7171-3.3 224 128 R0
SYMATTR InstName U1
SYMBOL cap 80 240 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.8
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 6
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
TEXT 408 264 Left 2 !.tran 5m startup
* Z:\tmp\asc_dec_bjh7r6w2\124000622116_CmosLinTest_1_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
V2 N001 0 10
M1 N003 N002 N001 N001 PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -160 80 -256 80
WIRE -160 192 -160 80
WIRE -160 304 -160 192
WIRE -128 192 -160 192
WIRE -48 80 -160 80
WIRE -48 304 -160 304
WIRE 0 64 0 48
WIRE 0 192 -48 192
WIRE 0 192 0 160
WIRE 0 224 0 192
WIRE 0 368 0 320
WIRE 32 192 0 192
WIRE 112 192 96 192
WIRE 112 192 112 176
WIRE 160 336 160 320
WIRE 192 48 0 48
WIRE 192 176 192 48
WIRE 192 320 160 320
WIRE 192 320 192 256
WIRE 192 368 192 320
SYMBOL voltage 192 160 M0
WINDOW 0 4 10 Left 0
WINDOW 3 15 56 Right 0
WINDOW 123 -67 188 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 10
SYMBOL pmos -48 160 M180
SYMATTR InstName M1
FLAG 160 336 0
FLAG 112 176 Out
* Z:\home\khalils\Downloads\files\data\raw_asc\19ac29740603_OP_AMP_impedance_matching.asc
* Generated by LTspice 26.0.1 for Windows.
* Measurement
* Library below included based on ModelFile attribute of instance XU1, XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\ADA4805.asy)
XU1 +2.25 N001 +4.5 0 N002 +4.5 ADA4805 ;pnba 100)101)102)103)104)106
R2 N002 N001 1000
R6 +4.5 +2.25 1k
R3 vout N002 5k
R5 NC_01 N003 50
R4 N004 +2.25 5k
XU2 N004 N003 +4.5 0 N003 +4.5 ADA4805 ;pnba 100)101)102)103)104)106
V2 vin 0 SINE(2.25 10u 10.7Meg) Rser=50
R7 +2.25 0 1k
V1 +4.5 0 4.5
R1 N001 vin 50
.meas vout_max max V(vout)
.meas vout_min min V(vout)
.meas vout_vpp param vout_max-vout_min
.meas vin_max max V(vin)
.meas vin_min min V(vin)
.meas vin_vpp param vin_max-vin_min
.meas amp_gain PARAM -vout_vpp/vin_vpp
.tran 50u
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 -48 48 -48
WIRE 160 -48 144 -48
WIRE 624 -32 512 -32
WIRE 512 64 512 -32
WIRE 528 64 512 64
WIRE 48 80 48 -48
WIRE 48 80 32 80
WIRE 64 80 48 80
WIRE 624 80 624 -32
WIRE 624 80 592 80
WIRE 160 96 160 -48
WIRE 160 96 128 96
WIRE 464 96 432 96
WIRE 528 96 464 96
WIRE 64 112 48 112
WIRE 576 128 576 112
WIRE 48 144 48 112
WIRE 112 144 112 128
WIRE 544 144 544 112
WIRE 80 160 80 128
WIRE -64 256 -160 256
WIRE -160 288 -160 256
WIRE -32 336 -64 336
WIRE -160 416 -160 368
WIRE -64 416 -160 416
WIRE -160 432 -160 416
SYMBOL OpAmps\\ADA4805 96 96 R0
WINDOW 3 61 66 Left 2
SYMATTR InstName U1
SYMBOL res 720 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 50
SYMBOL res -80 320 R0
SYMATTR InstName R7
SYMATTR Value 1k
SYMBOL res -80 240 R0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL voltage -160 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 4.5
SYMBOL res 256 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 5k
SYMBOL voltage -272 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 -147 43 Left 2
WINDOW 3 -325 69 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V2
SYMATTR Value SINE(2.25 10u 10.7Meg)
SYMBOL res 160 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1000
SYMBOL res 48 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL OpAmps\\ADA4805 560 80 R0
WINDOW 3 61 66 Left 2
SYMATTR InstName U2
SYMBOL res 448 80 R0
SYMATTR InstName R4
SYMATTR Value 5k
FLAG 80 64 +4.5
FLAG 80 160 0
FLAG 112 144 +4.5
FLAG -160 432 0
FLAG -160 256 +4.5
FLAG 544 48 +4.5
FLAG 544 144 0
FLAG 576 128 +4.5
FLAG -272 368 0
FLAG -272 288 vin
FLAG -32 336 +2.25
FLAG 48 144 +2.25
FLAG 464 176 +2.25
FLAG -48 80 vin
FLAG 240 96 vout
TEXT -704 -144 Left 4 ;Measurement
TEXT -704 -104 Left 2 !.meas vout_max max V(vout)\n.meas vout_min min V(vout)\n.meas vout_vpp param vout_max-vout_min\n.meas vin_max max V(vin)\n.meas vin_min min V(vin)\n.meas vin_vpp param vin_max-vin_min\n.meas amp_gain PARAM -vout_vpp/vin_vpp
TEXT -706 456 Left 2 !.tran 50u
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6700-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LT6700-3.asy)
R2 N001 N004 10K
XU1 N004 0 N002 N002 N001 N003 LT6700-3 ;pnba OUTA)GND)+INA)+INB)Vs)OUTB
V1 N001 0 5
R1 N001 N003 10K
V3 N002 0 PULSE(0 5 0 .5m .5m 0 1m)
.tran 3m
.lib LT6700-3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 800
WIRE 368 160 144 160
WIRE 496 160 368 160
WIRE 592 160 496 160
WIRE 144 176 144 160
WIRE 496 176 496 160
WIRE 368 208 368 160
WIRE 592 224 592 160
WIRE 304 256 256 256
WIRE 144 272 144 256
WIRE 496 272 496 256
WIRE 496 272 432 272
WIRE 256 336 256 256
WIRE 256 336 -64 336
WIRE -64 352 -64 336
WIRE 592 400 592 304
WIRE 592 400 432 400
WIRE 256 416 256 336
WIRE 304 416 256 416
WIRE -64 448 -64 432
WIRE 368 496 368 464
SYMBOL res 480 160 R0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL LT6700-3 368 336 R0
SYMATTR InstName U1
SYMBOL voltage -64 336 R0
WINDOW 3 17 101 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 5 0 .5m .5m 0 1m)
SYMATTR InstName V3
SYMBOL voltage 144 160 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 576 208 R0
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 144 272 0
FLAG -64 448 0
FLAG 368 496 0
TEXT 464 520 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\71ff928fae1f_rectifier_halfwave_DCtransfer.asc
* Generated by LTspice 26.0.1 for Windows.
R1 OUT 0 100
D1 IN OUT 1N4148
V1 IN 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 -5 5 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 956
WIRE 112 464 96 464
WIRE 208 464 112 464
WIRE 352 464 272 464
WIRE 368 464 352 464
WIRE 96 496 96 464
WIRE 368 496 368 464
WIRE 96 608 96 576
WIRE 368 608 368 576
WIRE 368 608 96 608
WIRE 96 640 96 608
SYMBOL res 352 480 R0
SYMATTR InstName R1
SYMATTR Value 100
SYMBOL voltage 96 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL diode 208 480 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
FLAG 96 640 0
FLAG 112 464 IN
FLAG 352 464 OUT
TEXT 112 696 Left 2 !.dc V1 -5 5 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\3b454430787d_OpAmp_Level_Shift_-5v_Messspannung.asc
* Generated by LTspice 26.0.1 for Windows.
V1 0 N002 5
V2 N001 0 5
XU1 0 N003 N001 N002 out LT1001 ;pnba In+)In-)V+)V-)OUT
R1 N003 N002 5k
R2 out N003 10k
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\OP07.asy)
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 272 80 0 80
WIRE 320 112 304 112
WIRE 272 144 272 80
WIRE 0 160 0 144
WIRE 80 160 0 160
WIRE 128 160 112 160
WIRE 224 160 224 112
WIRE 224 160 208 160
WIRE 240 160 224 160
WIRE 0 176 0 160
WIRE 320 176 320 112
WIRE 320 176 304 176
WIRE 352 176 320 176
WIRE 80 192 80 160
WIRE 240 192 80 192
WIRE 80 208 80 192
WIRE 112 256 112 160
WIRE 112 256 0 256
WIRE 272 256 272 208
WIRE 272 256 112 256
FLAG 80 208 0
FLAG 352 176 out
SYMBOL voltage 0 160 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage 0 64 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL Opamps\\OP07 272 112 R0
SYMATTR InstName U1
SYMBOL res 224 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 5k
SYMBOL res 320 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10k
* Z:\home\khalils\Downloads\files\data\raw_asc\235631e6747d_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
C2 N001 N002 {C2}
R1 N001 Vin {R1}
Vin1 Vin 0 AC 1 0
C1 0 N003 {C1}
XU1 N002 N003 N002 opamp Aol=100K GBW=10Meg ;pnba invin)noninvin)out
R2 N003 N001 {R2}
.lib opamp.sub
.param R1=2/{NG} R2=2/{NG} C1=1*{NG}/{NW} C2=(4/3) *{NG}/{NW}
.ac dec 1000 1m 1MEG
.param NG=1k NW=5k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 984 680
WIRE -64 32 -288 32
WIRE 80 32 0 32
WIRE -448 112 -448 96
WIRE -448 112 -496 112
WIRE -384 112 -448 112
WIRE -288 112 -288 32
WIRE -288 112 -304 112
WIRE -272 112 -288 112
WIRE -144 112 -192 112
WIRE -96 112 -144 112
WIRE -496 128 -496 112
WIRE -96 128 -96 112
WIRE -64 128 -96 128
WIRE 64 144 0 144
WIRE 80 144 80 32
WIRE 80 144 64 144
WIRE -144 160 -144 112
WIRE -64 160 -80 160
WIRE -80 208 -80 160
WIRE 64 208 64 144
WIRE 64 208 -80 208
WIRE -496 224 -496 208
WIRE -144 240 -144 224
SYMBOL cap -128 224 R180
WINDOW 0 24 56 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value {C1}
SYMBOL OpAmps\\opamp -32 208 M180
SYMATTR InstName U1
SYMBOL cap -64 48 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value {C2}
SYMBOL res -176 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value {R2}
SYMBOL res -288 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL voltage -496 112 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1 0
SYMATTR InstName Vin1
SYMATTR Value ""
FLAG -496 224 0
FLAG -448 96 Vin
FLAG -144 240 0
TEXT 104 400 Left 2 !.lib opamp.sub
TEXT -520 320 Left 2 !.param R1=2/{NG} R2=2/{NG} C1=1*{NG}/{NW} C2=(4/3) *{NG}/{NW}
TEXT -496 400 Left 2 !.ac dec 1000 1m 1MEG
TEXT -176 400 Left 2 !.param NG=1k NW=5k
* Z:\home\khalils\Downloads\files\data\raw_asc\038d341974db_hpf.asc
* Generated by LTspice 26.0.1 for Windows.
* .op
* .tran 1u 10m
C1 N001 N004 100n Lser=0 mfg=" ---" pn=" ---" type=" ---"
XU1 N005 N002 N003 N006 N002 TL074 ;pnba In+)In-)V+)V-)OUT
V1 N004 0 SINE(1.6 1.6 500) AC 1.6
C2 N005 N001 100n Lser=408p mfg=" ---" pn=" ---" type=" ---"
R1 N005 N007 160k
V4 N007 0 1.6
R2 N002 N001 160k
V3 N003 0 5
V2 N006 0 -1.6
.ac dec 100 1 100k
.lib TL074.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 1672
WIRE 288 1072 256 1072
WIRE 288 1088 288 1072
WIRE 256 1104 256 1072
WIRE 112 1216 48 1216
WIRE 320 1216 192 1216
WIRE 320 1312 320 1216
WIRE 320 1312 192 1312
WIRE 256 1344 256 1184
WIRE 192 1360 192 1312
WIRE 224 1360 192 1360
WIRE 320 1376 320 1312
WIRE 320 1376 288 1376
WIRE -48 1392 -112 1392
WIRE 48 1392 48 1216
WIRE 48 1392 16 1392
WIRE 64 1392 48 1392
WIRE 144 1392 128 1392
WIRE 224 1392 144 1392
WIRE 144 1424 144 1392
WIRE 256 1472 256 1408
WIRE 144 1520 144 1504
WIRE 144 1632 144 1600
ARC Normal -100 1140 -108 1120 180 1096 76 1088 2
SYMBOL OpAmps/opamp2 256 1312 R0
SYMATTR InstName U1
SYMATTR Value TL074
SYMBOL Res 128 1408 R0
SYMATTR InstName R1
SYMATTR Value 160k
SYMBOL voltage 256 1200 R180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL voltage -112 1376 R0
SYMATTR InstName V1
SYMATTR Value SINE(1.6 1.6 500)
SYMATTR Value2 AC 1.6
SYMBOL cap 128 1376 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 100n
SYMATTR SpiceLine Lser=408p mfg="   ---" pn="   ---" type="   ---"
SYMBOL Res 208 1200 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 160k
SYMBOL cap 16 1376 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMATTR SpiceLine Lser=0 mfg="   ---" pn="   ---" type="   ---"
SYMBOL voltage 144 1504 R0
SYMATTR InstName V4
SYMATTR Value 1.6
SYMBOL voltage 256 1456 R0
SYMATTR InstName V2
SYMATTR Value -1.6
FLAG -112 1472 0
FLAG 288 1088 0
FLAG 256 1552 0
FLAG 144 1632 0
TEXT -144 1568 Left 2 !.ac dec 100 1 100k
TEXT -144 1608 Left 2 ;.op
TEXT -144 1656 Left 2 ;.tran 1u 10m
TEXT -152 1024 Left 2 !.lib TL074.lib
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3225-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Note: \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capacitance is scaled down from its real value;\n2. Load capacitor initial condion can be given to represent the specific \nresidual voltage at the beginning of the charging.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3225-1.asy)
C2 OUT N004 .1m ic=1.5
C3 N004 0 .3m ic=1.2
V1 IN 0 2.7
XU1 N001 N002 N004 IN NC_01 0 N003 0 IN OUT LTC3225-1 ;pnba C+)C-)Cx)_SHDN)Pgood)Vsel)Prog)GND)Vin)Cout
R1 N003 0 12K
C1 N001 N002 1
.tran 2m startup
.lib LTC3225-1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1068 680
WIRE 112 0 16 0
WIRE 240 0 112 0
WIRE 240 16 240 0
WIRE 16 32 16 0
WIRE 112 80 112 0
WIRE 128 80 112 80
WIRE 400 80 352 80
WIRE 400 96 400 80
WIRE 16 144 16 112
WIRE 400 176 400 160
WIRE 400 176 352 176
WIRE 128 272 112 272
WIRE 400 272 352 272
WIRE 400 288 400 272
WIRE 32 368 16 368
WIRE 128 368 112 368
WIRE 400 368 400 352
WIRE 400 368 352 368
WIRE 400 384 400 368
WIRE 240 448 240 432
WIRE 400 464 400 448
SYMBOL PowerProducts\\LTC3225-1 240 224 R0
SYMATTR InstName U1
SYMBOL cap 384 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 128 352 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 12K
SYMBOL cap 384 384 R0
SYMATTR InstName C3
SYMATTR Value .3m ic=1.2
SYMBOL voltage 16 16 R0
SYMATTR InstName V1
SYMATTR Value 2.7
SYMBOL cap 384 288 R0
SYMATTR InstName C2
SYMATTR Value .1m ic=1.5
FLAG 240 448 0
FLAG 16 144 0
FLAG 400 464 0
FLAG 16 368 0
FLAG 112 272 0
FLAG 16 0 IN
FLAG 400 272 OUT
TEXT 552 456 Left 2 !.tran 2m startup
TEXT -72 472 Left 2 ;Note: \n1. To emulate the supercapacitor charging process within acceptable \ntime interval, the capacitance is scaled down from its real value;\n2. Load capacitor initial condion can be given to represent the specific \nresidual voltage at the beginning of the charging.
* Z:\tmp\asc_dec_bjh7r6w2\04276d83d88e_NoiseAnalysis_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
V2 Vp 0 12
V3 Vn 0 -12
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5196 728
WIRE 0 32 0 0
WIRE 128 32 128 0
WIRE 272 32 272 0
WIRE 0 144 0 112
WIRE 128 144 128 112
WIRE 272 144 272 112
WIRE 432 208 304 208
WIRE 304 352 304 208
SYMBOL voltage 0 16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
* Put Vp value from design here
SYMATTR Value 12
SYMBOL voltage 128 16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
* Put Vn value from design here
SYMATTR Value -12
FLAG 0 144 0
FLAG 128 144 0
FLAG 0 0 Vp
FLAG 128 0 Vn
FLAG 272 144 0
FLAG 272 0 Vref
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1550CS8-4.1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1550CS8-4.1.asy)
XU1 IN IN N002 OUT N003 0 N001 OUT LTC1550CS8-4.1 ;pnba _SHDN)Vin)C+)Vout)C-)GND)CPout)Sense
C3 OUT 0 10
C2 N003 N002 .1
Rload OUT 0 1K
V1 IN 0 4.5
C1 N001 0 .1
.tran 2m startup
.lib LTC1550CS8-4.1.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1600 1220
WIRE 576 720 144 720
WIRE 208 784 48 784
WIRE 240 784 208 784
WIRE 576 784 576 720
WIRE 576 784 528 784
WIRE 48 800 48 784
WIRE 208 848 208 784
WIRE 240 848 208 848
WIRE 560 848 528 848
WIRE 656 848 624 848
WIRE 48 896 48 880
WIRE 240 912 208 912
WIRE 544 912 528 912
WIRE 144 976 144 720
WIRE 144 976 32 976
WIRE 240 976 144 976
WIRE 544 976 528 976
WIRE 32 992 32 976
WIRE 144 1008 144 976
WIRE 32 1088 32 1072
WIRE 144 1088 144 1072
WIRE 208 1104 208 912
WIRE 352 1104 208 1104
WIRE 544 1104 544 976
WIRE 544 1104 416 1104
SYMBOL VOLTAGE 48 784 R0
SYMATTR InstName V1
SYMATTR Value 4.5
SYMBOL RES 16 976 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL cap 560 864 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C1
SYMATTR Value .1
SYMBOL cap 416 1088 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL PowerProducts\\LTC1550CS8-4.1 384 880 R0
SYMATTR InstName U1
SYMBOL cap 128 1008 R0
SYMATTR InstName C3
SYMATTR Value 10
FLAG 656 848 0
FLAG 544 912 0
FLAG 48 896 0
FLAG 32 1088 0
FLAG 144 1088 0
FLAG 48 784 IN
FLAG 32 976 OUT
TEXT 616 1064 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\61336bb74f9a_PV-cell_too_simple_V001.asc
* Generated by LTspice 26.0.1 for Windows.
I1 0 N001 1A
D1 N001 0 D
V1 N001 0 0.1V
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.dc V1 0V 1V 1mV
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 256 80 96 80
WIRE 400 80 256 80
WIRE 96 128 96 80
WIRE 256 128 256 80
WIRE 400 128 400 80
WIRE 96 240 96 208
WIRE 256 240 256 192
WIRE 256 240 96 240
WIRE 400 240 400 208
WIRE 400 240 256 240
WIRE 96 256 96 240
SYMBOL voltage 400 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 0.1V
SYMBOL current 96 208 R180
WINDOW 0 24 80 Left 2
WINDOW 3 24 0 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName I1
SYMATTR Value 1A
SYMBOL diode 240 128 R0
SYMATTR InstName D1
FLAG 96 256 0
TEXT 296 40 Left 2 !.dc V1 0V 1V 1mV
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP1762-0.9.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP1762-0.9.asy)
C4 OUT 0 10
R1 OUT 0 .6
C1 N004 0 1
C3 N002 0 1
XU1 N002 IN IN OUT OUT N001 0 N003 N004 N005 ADP1762 Radj=6K ;pnba Vreg)Vin)EN)Vout)Sense)PG)GND)SS)RefCap)Vadj
V1 IN 0 1.1
R2 N001 IN 50K
C2 N003 0 10n
.tran 1m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -16 -32 -128 -32
WIRE 80 -32 -16 -32
WIRE 224 -32 80 -32
WIRE -128 -16 -128 -32
WIRE 224 -16 224 -32
WIRE 80 32 80 -32
WIRE 96 32 80 32
WIRE 384 32 352 32
WIRE 496 32 384 32
WIRE 592 32 496 32
WIRE 496 48 496 32
WIRE 592 48 592 32
WIRE -128 80 -128 64
WIRE -16 128 -16 -32
WIRE 0 128 -16 128
WIRE 96 128 80 128
WIRE 384 128 384 32
WIRE 384 128 352 128
WIRE 496 144 496 112
WIRE 592 144 592 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 368 224 352 224
WIRE 464 224 432 224
WIRE 16 320 -16 320
WIRE 96 320 80 320
WIRE 368 320 352 320
WIRE 224 384 224 368
SYMBOL cap 368 240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C2
SYMATTR Value 10n
SYMBOL cap 480 48 R0
SYMATTR InstName C4
SYMATTR Value 10
SYMBOL ADP1762-0.9 224 176 R0
SYMATTR InstName U1
SYMBOL voltage -128 -32 R0
SYMATTR InstName V1
SYMATTR Value 1.1
SYMBOL res 96 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 50K
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res 576 32 R0
SYMATTR InstName R1
SYMATTR Value .6
SYMBOL cap 80 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1
FLAG 224 384 0
FLAG -128 80 0
FLAG -16 320 0
FLAG 0 224 0
FLAG 464 224 0
FLAG 592 144 0
FLAG 496 144 0
FLAG -128 -32 IN
FLAG 592 32 OUT
TEXT 432 384 Left 2 !.tran 1m startup