Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\3d1fc6d5623d_backlash.asc
* Generated by LTspice 26.0.1 for Windows.
* Backlash-Component\n- this may need UIC in .TRAN ! -
* rel. position
* speed
* speed
* NOTE:\ndepending on Roff/Ron ratio there\nmay be a numerical problem when\nthis component is connected such\nthat pin 2 is used as "input".\nFix:\nLower Roff/Ron or ALTERNATE Solver!
* Bc : compensation for Ron,\ncould be left away.
Bc 2 N002 V=-I(Bc)*(Ron+1n)
C1 pos 0 1
S2 1 N003 0 sw SW1
G1 0 pos 1 N002 1
D2 N002 N003 Dsw
B1 sw 0 V=tbl(V(pos),-bl,-10,-(bl-eps),0,(bl-eps),0,bl,10)
D1 N001 N002 Dsw
S1 N001 1 sw 0 SW1
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model sw1 sw(Roff={Roff} Ron={Ron/2} Vt=0.5 Vh=-0.01)
.model dsw d(Roff={Roff} Ron={Ron/2} Vfwd=0)
.param backlash=20m
.param bl=backlash/2
.param eps=bl/50+1u ;transition slack->coupled
.param Ron=0.5E-9
.param Roff=1MEG
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1276 924
WIRE -160 -16 -224 -16
WIRE -160 112 -160 -16
WIRE -160 192 -160 112
WIRE -96 -16 -160 -16
WIRE -80 64 -80 32
WIRE -80 160 -80 64
WIRE -80 272 -80 160
WIRE -32 112 -160 112
WIRE -16 160 -80 160
WIRE 64 240 -224 240
WIRE 64 288 64 240
WIRE 96 -16 -16 -16
WIRE 96 112 48 112
WIRE 96 240 64 240
WIRE 112 192 -160 192
WIRE 160 112 160 -16
WIRE 160 192 160 112
WIRE 288 -16 160 -16
WIRE 528 -16 368 -16
SYMBOL bv -80 256 R0
WINDOW 3 -46 136 Left 0
SYMATTR Value V=tbl(V(pos),-bl,-10,-(bl-eps),0,(bl-eps),0,bl,10)
SYMATTR InstName B1
SYMBOL sw -48 112 R270
SYMATTR InstName S2
SYMATTR Value SW1
SYMBOL sw 0 -16 M270
WINDOW 0 22 20 VLeft 0
WINDOW 3 29 141 VLeft 0
SYMATTR InstName S1
SYMATTR Value SW1
SYMBOL bv 384 -16 R90
WINDOW 0 -32 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName Bc
SYMATTR Value V=-I(Bc)*(Ron+1n)
SYMBOL diode 160 96 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName D2
SYMATTR Value Dsw
SYMBOL g 80 240 M90
WINDOW 0 48 77 VLeft 0
WINDOW 3 47 103 VLeft 0
SYMATTR InstName G1
SYMATTR Value 1
SYMBOL diode 96 0 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value Dsw
SYMBOL cap 48 288 R0
WINDOW 3 44 38 Left 0
SYMATTR Value 1
SYMATTR InstName C1
FLAG 176 240 0
FLAG 64 352 0
FLAG 528 -16 2
FLAG -224 240 pos
FLAG -224 -16 1
FLAG -80 64 sw
FLAG -80 352 0
FLAG -32 32 0
FLAG 32 160 0
TEXT -232 -112 Left 0 !.model sw1 sw(Roff={Roff} Ron={Ron/2} Vt=0.5 Vh=-0.01)\n.model dsw d(Roff={Roff} Ron={Ron/2} Vfwd=0)
TEXT 64 -208 Left 0 !.param backlash=20m\n.param bl=backlash/2\n.param eps=bl/50+1u ;transition slack->coupled
TEXT -232 -264 Left 0 ;Backlash-Component\n- this may need UIC in .TRAN ! -
TEXT -336 216 Left 0 ;rel. position
TEXT 560 -16 Left 0 ;speed
TEXT -320 -16 Left 0 ;speed
TEXT -232 -176 Left 0 !.param Ron=0.5E-9\n.param Roff=1MEG
TEXT 240 96 Left 0 ;NOTE:\ndepending on Roff/Ron ratio there\nmay be a numerical problem when\nthis component is connected such\nthat pin 2 is used as "input".\nFix:\nLower Roff/Ron or ALTERNATE Solver!
TEXT 360 -80 Left 0 ;Bc : compensation for Ron,\ncould be left away.
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1107.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1107.asy)
Rload OUT 0 25
V1 IN 0 2.8
R1 OUT N003 220K
L1 IN N001 33 Rser=0.02 Rpar=5000
D1 N001 OUT MBRS140
C1 OUT 0 100 Rser=0.02
R2 N003 0 73.5K
XU1 IN IN N001 0 0 N002 N004 N003 LT1107 top=1K bot=1T ;pnba Ilim)Vin)SW1)SW2)GND)AO)SET)FB
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10m startup
.lib LT1107.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2488 1440
WIRE 1472 912 1296 912
WIRE 1600 912 1472 912
WIRE 1632 912 1600 912
WIRE 1744 912 1712 912
WIRE 1792 912 1744 912
WIRE 1920 912 1856 912
WIRE 2032 912 1920 912
WIRE 2144 912 2032 912
WIRE 1296 928 1296 912
WIRE 2032 928 2032 912
WIRE 2144 928 2144 912
WIRE 1472 960 1472 912
WIRE 1600 960 1600 912
WIRE 1920 960 1920 912
WIRE 1296 1024 1296 1008
WIRE 1392 1024 1376 1024
WIRE 1744 1024 1744 912
WIRE 1744 1024 1680 1024
WIRE 2032 1024 2032 992
WIRE 2144 1024 2144 1008
WIRE 1920 1104 1920 1040
WIRE 1920 1104 1680 1104
WIRE 1920 1120 1920 1104
WIRE 1392 1184 1376 1184
WIRE 1712 1184 1680 1184
WIRE 1920 1216 1920 1200
WIRE 1536 1264 1536 1248
SYMBOL POWERPRODUCTS\\LT1107 1536 1104 R0
SYMATTR InstName U1
SYMBOL IND 1616 928 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 33
SYMATTR SpiceLine Rser=0.02 Rpar=5000
SYMBOL RES 1904 1104 R0
SYMATTR InstName R2
SYMATTR Value 73.5K
SYMBOL schottky 1792 928 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS140
SYMBOL RES 2128 912 R0
SYMATTR InstName Rload
SYMATTR Value 25
SYMBOL POLCAP 2016 928 R0
SYMATTR InstName C1
SYMATTR Value 100
SYMATTR SpiceLine Rser=0.02
SYMBOL RES 1904 944 R0
SYMATTR InstName R1
SYMATTR Value 220K
SYMBOL VOLTAGE 1296 912 R0
SYMATTR InstName V1
SYMATTR Value 2.8
FLAG 1536 1264 0
FLAG 1712 1184 0
FLAG 2032 1024 0
FLAG 1920 1216 0
FLAG 1296 1024 0
FLAG 2144 1024 0
FLAG 2144 912 OUT
FLAG 1296 912 IN
TEXT 1904 1280 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2689589476f8_FET-switch-power.asc
* Generated by LTspice 26.0.1 for Windows.
Vdd N001 0 200V
M1 Uds Ugs 0 0 IPP200N25N3
R2 Ugs 0 10k
R3 Ugs N002 10
V1 N002 0 PULSE(0 24V 5m 0.1m 0.1m 20m 50m) Rser=10m
R1 N001 Uds 10
D1 0 Ugs BZX84B12VLY
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 100m
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1292 680
WIRE -464 -288 -720 -288
WIRE -720 -240 -720 -288
WIRE -464 -128 -464 -288
WIRE -720 -112 -720 -160
WIRE -624 -112 -720 -112
WIRE -720 -96 -720 -112
WIRE -992 -16 -1040 -16
WIRE -896 -16 -912 -16
WIRE -864 -16 -896 -16
WIRE -800 -16 -864 -16
WIRE -768 -16 -800 -16
WIRE -1040 32 -1040 -16
WIRE -864 32 -864 -16
WIRE -800 32 -800 -16
WIRE -1040 160 -1040 112
WIRE -864 160 -864 96
WIRE -864 160 -1040 160
WIRE -800 160 -800 112
WIRE -800 160 -864 160
WIRE -720 160 -720 0
WIRE -720 160 -800 160
WIRE -464 160 -464 -48
WIRE -464 160 -720 160
WIRE -720 192 -720 160
SYMBOL voltage -464 -144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 37 60 Left 2
WINDOW 0 36 55 Left 2
WINDOW 3 36 82 Left 2
SYMATTR InstName Vdd
SYMATTR Value 200V
SYMBOL Misc\\EuropeanResistor -896 -32 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 27 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10
SYMBOL voltage -1040 16 R0
WINDOW 123 0 0 Left 2
WINDOW 3 -81 162 Left 2
WINDOW 0 35 44 Left 2
SYMATTR Value PULSE(0 24V 5m 0.1m 0.1m 20m 50m)
SYMATTR InstName V1
SYMATTR SpiceLine Rser=10m
SYMBOL Misc\\EuropeanResistor -736 -256 R0
SYMATTR InstName R1
SYMATTR Value 10
SYMBOL zener -848 96 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value BZX84B12VLY
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL Misc\\EuropeanResistor -816 16 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL nmos -768 -96 R0
SYMATTR InstName M1
SYMATTR Value IPP200N25N3
FLAG -720 192 0
FLAG -624 -112 Uds
FLAG -896 -16 Ugs
TEXT -672 184 Left 2 !.tran 100m
* Z:\home\khalils\Downloads\files\data\raw_asc\1ff4cfea1dcf_t4.asc
* Generated by LTspice 26.0.1 for Windows.
VGS_DC N001 0 1.01
Rd VDD out 92.342k
vgs_ac in N001 AC 1
VDD VDD 0 5V
M1 out in 0 0 N_1u l=4.37u w=87.35u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.ac oct 10 1 1MEG
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 208 96 208 64
WIRE 256 96 208 96
WIRE 208 112 208 96
WIRE 272 160 208 160
WIRE 160 192 32 192
WIRE 32 208 32 192
WIRE 272 208 272 160
WIRE 272 208 208 208
WIRE 32 304 32 288
WIRE 32 400 32 384
WIRE 208 400 208 208
SYMBOL nmos4 160 112 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=4.37u w=87.35u
SYMBOL voltage 384 304 R0
WINDOW 0 -69 12 Left 2
WINDOW 3 -55 -7 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VDD
SYMATTR Value 5V
SYMBOL voltage 32 288 R0
WINDOW 0 -128 47 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
WINDOW 3 -110 75 Left 2
SYMATTR InstName VGS_DC
SYMATTR Value 1.01
SYMBOL voltage 32 192 R0
WINDOW 0 -111 37 Left 2
WINDOW 3 -118 -5 Left 2
WINDOW 123 -101 61 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName vgs_ac
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 192 -32 R0
SYMATTR InstName Rd
SYMATTR Value 92.342k
FLAG 32 400 0
FLAG 208 400 0
FLAG 208 -16 VDD
FLAG 256 96 out
FLAG 384 400 0
FLAG 384 320 VDD
FLAG 32 192 in
TEXT -80 496 Left 2 !.include cmosedu_models.txt
TEXT -80 472 Left 2 !.ac oct 10 1 1MEG
* Z:\tmp\asc_dec_bjh7r6w2\129648a0c45e_AFE_bandpass_v3_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N003 N001 5V -5V N002 level2 Avol=1Meg GBW=33Meg Slew=11Meg Vos=5u Ilimit=25m Rail=0 Vos=0 En=0 Enk=0 In=0 Ink=0 Rin=500Meg ;pnba In+)In-)V+)V-)OUT
R2 N001 0 1k
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\UniversalOpAmp2.asy)
.lib UniversalOpAmp2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1364 680
WIRE 432 -64 368 -64
WIRE 592 -64 512 -64
WIRE 688 -64 592 -64
WIRE 832 -64 768 -64
WIRE 368 -16 368 -64
WIRE 592 80 592 -64
WIRE 688 80 592 80
WIRE 832 96 832 -64
WIRE 832 96 752 96
WIRE 928 96 832 96
WIRE 464 112 352 112
WIRE 592 112 464 112
WIRE 688 112 592 112
WIRE 464 160 464 112
WIRE 592 160 592 112
WIRE 592 272 592 224
WIRE 592 272 464 272
WIRE 592 288 592 272
SYMBOL OpAmps\\UniversalOpAmp2 720 96 R0
SYMATTR InstName U1
SYMATTR Value2 Avol=1Meg GBW=33Meg Slew=11Meg Vos=5u
SYMBOL res 528 -80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1k
FLAG 592 288 0
FLAG 368 -16 0
FLAG 720 64 5V
FLAG 720 128 -5V
* Z:\home\khalils\Downloads\files\data\raw_asc\1d2c6764b354_switches_2.asc
* Generated by LTspice 26.0.1 for Windows.
S3 P3 P2 clk2 Vtrip switmod
S1 P2 P1 clk1 Vtrip switmod
R2 VDD Vtrip 100Meg
R1 Vtrip 0 100Meg
.model switmod SW
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2740 696
WIRE 80 -848 80 -912
WIRE 480 -784 480 -848
WIRE 656 -784 656 -848
WIRE 80 -736 80 -768
WIRE 160 -736 80 -736
WIRE 192 -736 160 -736
WIRE 464 -736 352 -736
WIRE 592 -736 544 -736
WIRE 640 -736 592 -736
WIRE 816 -736 720 -736
WIRE 80 -704 80 -736
WIRE 80 -560 80 -624
IOPIN 80 -912 In
IOPIN 816 -736 BiDir
IOPIN 352 -736 BiDir
IOPIN 480 -848 In
IOPIN 656 -848 In
IOPIN 592 -736 BiDir
SYMBOL res 64 -720 R0
SYMATTR InstName R1
SYMATTR Value 100MEG
SYMBOL res 64 -864 R0
SYMATTR InstName R2
SYMATTR Value 100MEG
SYMBOL sw 560 -736 R90
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S1
SYMBOL sw 736 -736 R90
WINDOW 3 24 -12 Left 0
WINDOW 38 39 67 Left 0
WINDOW 0 38 33 Left 0
SYMATTR Value ""
SYMATTR SpiceModel switmod
SYMATTR InstName S3
FLAG 160 -736 Vtrip
FLAG 80 -912 VDD
FLAG 80 -560 0
FLAG 528 -784 Vtrip
FLAG 704 -784 Vtrip
FLAG 816 -736 P3
FLAG 352 -736 P1
FLAG 480 -848 clk1
FLAG 656 -848 clk2
FLAG 592 -736 P2
TEXT 488 -568 Left 0 !.model switmod SW
* Z:\home\khalils\Downloads\files\data\raw_asc\26f1d0661f66_Draft2.asc
* Generated by LTspice 26.0.1 for Windows.
V3 in 0 SINE(0 0.460 1k)
V1 vcc 0 100
R2 vcc N001 100k
V2 vcc- 0 -100
R1 vcc out 100k
R4 out N002 2.88k
R3 0 N002 1k
Q1 N001 in N003 0 NPN
R1.5k N003 vcc- 1k
Q2 out N002 N003 0 NPN
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran {t}
.param f = 1k n=16 t=n/f
.four {f} 10 8 V(out)
.meas TRAN power_Output AVG I(R_load)*V(Out) TRIG time=0 TARG time={t}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 -64 160 -64
WIRE 320 -64 240 -64
WIRE 160 -16 160 -64
WIRE 320 -16 320 -64
WIRE 320 80 320 64
WIRE 400 80 320 80
WIRE 544 80 400 80
WIRE 160 112 160 64
WIRE 320 112 320 80
WIRE 96 160 48 160
WIRE 400 160 384 160
WIRE 432 160 400 160
WIRE 576 160 512 160
WIRE 576 192 576 160
WIRE 160 320 160 208
WIRE 256 320 160 320
WIRE 320 320 320 208
WIRE 320 320 256 320
SYMBOL voltage -640 48 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value SINE(0 0.460 1k)
SYMBOL res 144 -32 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL npn 384 112 M0
SYMATTR InstName Q2
SYMBOL res 304 -32 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL voltage -640 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 100
SYMBOL npn 96 112 R0
SYMATTR InstName Q1
SYMBOL res 240 304 R0
SYMATTR InstName 1.5k
SYMATTR Value 1k
SYMBOL voltage -528 -112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -100
SYMBOL res 528 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res 384 64 R0
SYMATTR InstName R4
SYMATTR Value 2.88k
FLAG 544 80 out
FLAG -640 -16 0
FLAG -528 -16 0
FLAG -640 -96 vcc
FLAG -528 -96 vcc-
FLAG 256 400 vcc-
FLAG 240 -64 vcc
FLAG 576 192 0
FLAG 48 160 in
FLAG -640 144 0
FLAG -640 64 in
TEXT -674 496 Left 2 !.tran {t}
TEXT -320 -112 Left 2 !.param f = 1k n=16 t=n/f
TEXT -320 -72 Left 2 !.four {f} 10 8 V(out)
TEXT -320 -144 Left 2 !.meas TRAN power_Output AVG I(R_load)*V(Out) TRIG time=0 TARG time={t}
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1515.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1515.asy)
R3 N002 0 100K
R2 OUT N002 170K
C1 N003 N004 1
V1 IN 0 3
R1 IN N001 5K
Rload OUT 0 100
XU1 IN N001 N002 0 N004 N003 IN OUT LTC1515 ;pnba _SHDN)POR)FB)GND)C1-)C1+)Vin)Vout
C2 OUT 0 10
.tran 1m startup
.lib LTC1515.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 3112 2708
WIRE 2016 2176 1920 2176
WIRE 2112 2176 2016 2176
WIRE 2528 2176 2112 2176
WIRE 1920 2192 1920 2176
WIRE 2016 2208 2016 2176
WIRE 2112 2256 2112 2176
WIRE 2128 2256 2112 2256
WIRE 2576 2256 2416 2256
WIRE 2688 2256 2576 2256
WIRE 2784 2256 2688 2256
WIRE 2688 2272 2688 2256
WIRE 2784 2272 2784 2256
WIRE 1920 2288 1920 2272
WIRE 2576 2304 2576 2256
WIRE 2016 2320 2016 2288
WIRE 2128 2320 2016 2320
WIRE 2528 2320 2528 2176
WIRE 2528 2320 2416 2320
WIRE 2688 2368 2688 2336
WIRE 2784 2368 2784 2352
WIRE 2128 2384 2064 2384
WIRE 2464 2384 2416 2384
WIRE 2576 2432 2576 2384
WIRE 2576 2432 2512 2432
WIRE 2128 2448 2112 2448
WIRE 2464 2448 2416 2448
WIRE 2576 2448 2576 2432
WIRE 2064 2528 2064 2384
WIRE 2512 2528 2512 2432
WIRE 2512 2528 2064 2528
WIRE 2576 2544 2576 2528
SYMBOL res 2560 2432 R0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL res 2768 2256 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL VOLTAGE 1920 2176 R0
SYMATTR InstName V1
SYMATTR Value 3
SYMBOL cap 2448 2384 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL RES 2000 2192 R0
SYMATTR InstName R1
SYMATTR Value 5K
SYMBOL PowerProducts\\LTC1515 2272 2352 R0
SYMATTR InstName U1
SYMBOL res 2560 2288 R0
SYMATTR InstName R2
SYMATTR Value 170K
SYMBOL cap 2672 2272 R0
SYMATTR InstName C2
SYMATTR Value 10
FLAG 2688 2368 0
FLAG 2112 2448 0
FLAG 1920 2288 0
FLAG 2576 2544 0
FLAG 2784 2368 0
FLAG 2784 2256 OUT
FLAG 1920 2176 IN
TEXT 2648 2560 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1102A.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1102A.asy)
V3 IN 0 SINE(0 10m 1K)
V2 -V 0 -15
V1 +V 0 15
XU1 0 N001 IN -V +V 0 N002 OUT LT1102 ;pnba GND)Tap1)In-)V-)V+)In+)Tap2)Out
.tran 3m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE 80 64 64 64
WIRE 352 64 336 64
WIRE 80 128 64 128
WIRE 352 128 336 128
WIRE -400 160 -400 144
WIRE -288 160 -288 144
WIRE 80 192 -176 192
WIRE 352 192 336 192
WIRE -176 208 -176 192
WIRE -400 256 -400 240
WIRE -288 256 -288 240
WIRE 80 256 64 256
WIRE 352 256 336 256
WIRE -176 304 -176 288
SYMBOL voltage -288 144 R0
SYMATTR InstName V1
SYMATTR Value 15
SYMBOL opamps\\LT1102A 208 160 R0
SYMATTR InstName U1
SYMBOL voltage -400 144 R0
SYMATTR InstName V2
SYMATTR Value -15
SYMBOL voltage -176 192 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 10m 1K)
FLAG -288 256 0
FLAG -288 144 +V
FLAG 64 256 -V
FLAG -400 256 0
FLAG -400 144 -V
FLAG -176 304 0
FLAG 352 256 +V
FLAG 64 64 0
FLAG 352 192 0
FLAG 352 64 OUT
FLAG -176 192 IN
TEXT 352 328 Left 2 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\525753a43288_Setup_Id_vs_Vgs_nmos.asc
* Generated by LTspice 26.0.1 for Windows.
M1 vdd vgs 0 0 NMOS l=0.18u w=0.36u
vgs vgs 0 0
vdd vdd 0 1.8
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
* .op
.include tsmc180.txt
.dc vgs 0 1.8 0.1m vdd 0 1.8 0.6
* ID VS VGS PLOT SETUP
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -272 160 -272 80
WIRE -208 208 -272 208
WIRE -672 224 -672 176
WIRE -560 224 -560 176
WIRE -320 240 -368 240
WIRE -272 288 -272 256
WIRE -208 288 -208 208
WIRE -208 288 -272 288
WIRE -672 352 -672 304
WIRE -560 352 -560 304
WIRE -272 352 -272 288
FLAG -272 352 0
FLAG -672 352 0
FLAG -672 176 vgs
IOPIN -672 176 In
FLAG -368 240 vgs
IOPIN -368 240 In
FLAG -560 352 0
FLAG -560 176 vdd
IOPIN -560 176 In
FLAG -272 80 vdd
IOPIN -272 80 In
SYMBOL nmos4 -320 160 R0
WINDOW 123 1 100 Left 2
SYMATTR Value2 l=0.18u w=0.36u
SYMATTR InstName M1
SYMBOL voltage -672 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vgs
SYMATTR Value 0
SYMBOL voltage -560 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName vdd
SYMATTR Value 1.8
TEXT -736 24 Left 2 ;.op
TEXT -736 0 Left 2 !.include tsmc180.txt
TEXT -736 56 Left 2 !.dc vgs 0 1.8 0.1m vdd 0 1.8 0.6
TEXT -544 -40 Left 2 ;ID VS VGS PLOT SETUP
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8571.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8571.asy)
R2 OUT N001 10K
Vin IN 0 SINE(0 1 10K)
V1 +V 0 2.5
Rload OUT 0 10K
XU1 IN N001 +V -V OUT AD8571 ;pnba In+)In-)V+)V-)OUT
R1 N001 0 10K
V2 -V 0 -2.5
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 352 -1216 336 -1216
WIRE 448 -1216 432 -1216
WIRE 464 -1216 448 -1216
WIRE 560 -1216 544 -1216
WIRE 112 -1104 112 -1120
WIRE 224 -1104 224 -1120
WIRE 448 -1104 448 -1216
WIRE 464 -1104 448 -1104
WIRE 560 -1088 560 -1216
WIRE 560 -1088 528 -1088
WIRE 672 -1088 560 -1088
WIRE 464 -1072 352 -1072
WIRE 672 -1072 672 -1088
WIRE 352 -1056 352 -1072
WIRE 112 -1008 112 -1024
WIRE 224 -1008 224 -1024
WIRE 672 -976 672 -992
WIRE 352 -960 352 -976
SYMBOL voltage 224 -1120 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL res 448 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 560 -1232 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 656 -1088 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL voltage 352 -1072 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 112 -1120 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL Opamps\\AD8571 496 -1152 R0
SYMATTR InstName U1
FLAG 112 -1120 +V
FLAG 112 -1008 0
FLAG 352 -960 0
FLAG 672 -1088 OUT
FLAG 352 -1072 IN
FLAG 496 -1120 +V
FLAG 224 -1120 -V
FLAG 496 -1056 -V
FLAG 336 -1216 0
FLAG 672 -976 0
FLAG 224 -1008 0
TEXT 704 -880 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\363a615b011c_Buck4.asc
* Generated by LTspice 26.0.1 for Windows.
D1 0 N001 1N4148
V1 N002 0 PULSE(12 0 1p 1p 0 5000n 10u)
L1 Vout N001 110m
RL Vout 0 1k
C1 Vout 0 36n
Vin Vin 0 12
M1 N001 N002 Vin Vin AO6407
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -368 48 -624 48
WIRE 304 48 -272 48
WIRE 400 48 304 48
WIRE 576 48 480 48
WIRE 656 48 576 48
WIRE 656 96 656 48
WIRE 736 96 656 96
WIRE -624 112 -624 48
WIRE 304 112 304 48
WIRE 576 112 576 48
WIRE -352 128 -352 96
WIRE 736 176 656 176
WIRE -624 240 -624 192
WIRE -352 240 -352 208
WIRE -352 240 -624 240
WIRE 304 240 304 176
WIRE 304 240 -352 240
WIRE 576 240 576 176
WIRE 576 240 304 240
WIRE 656 240 656 176
WIRE 656 240 576 240
WIRE -624 288 -624 240
SYMBOL voltage -352 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(12 0 1p 1p 0 5000n 10u)
SYMBOL cap 560 112 R0
SYMATTR InstName C1
SYMATTR Value 36n
SYMBOL res 720 80 R0
SYMATTR InstName RL
SYMATTR Value 1k
SYMBOL diode 320 176 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL pmos -272 96 M270
SYMATTR InstName M1
SYMATTR Value AO6407
SYMBOL ind 496 32 R90
WINDOW 0 5 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName L1
SYMATTR Value 110m
SYMBOL voltage -624 96 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value 12
FLAG -624 288 0
FLAG 656 48 Vout
FLAG -624 48 Vin
TEXT -240 312 Left 2 !.tran 1ms
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6658-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT6658-2.5.asy)
C3 OUT1 0 1
C2 OUT2 0 1
XU1 IN IN IN IN N001 OUT1 OUT1 OUT2 OUT2 0 N002 LT6658-2.5 ;pnba Vin)Vin1)Vin2)_OD)Bypass)Vout1_F)Vout1_S)Vout2_F)Vout2_S)Gnd)NR
C1 N001 0 1
V3 IN 0 PWL(0 0 100u 0 +2u 5)
.tran 500u
.lib LT6658.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1448 1048
WIRE 16 -16 -336 -16
WIRE 128 -16 16 -16
WIRE 224 -16 128 -16
WIRE 320 -16 224 -16
WIRE -336 0 -336 -16
WIRE 128 0 128 -16
WIRE 224 0 224 -16
WIRE 320 0 320 -16
WIRE 432 64 416 64
WIRE 496 64 432 64
WIRE 496 80 496 64
WIRE -336 96 -336 80
WIRE 432 144 432 64
WIRE 432 144 416 144
WIRE 496 160 496 144
WIRE 16 192 16 -16
WIRE 48 192 16 192
WIRE 432 224 416 224
WIRE 496 224 432 224
WIRE 496 240 496 224
WIRE 432 304 432 224
WIRE 432 304 416 304
WIRE 496 320 496 304
WIRE 128 400 128 384
WIRE 224 400 224 384
WIRE 320 400 320 384
WIRE 224 480 224 464
SYMBOL voltage -336 -16 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PWL(0 0 100u 0 +2u 5)
SYMBOL cap 480 240 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL cap 480 80 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 208 400 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL LT6658-2.5 224 192 R0
SYMATTR InstName U1
FLAG 128 400 0
FLAG 224 480 0
FLAG -336 96 0
FLAG 496 160 0
FLAG 496 320 0
FLAG 496 64 OUT2
FLAG 496 224 OUT1
FLAG -336 -16 IN
TEXT 464 464 Left 2 !.tran 500u
* Z:\tmp\asc_dec_bjh7r6w2\007e4987a9c7_eje3_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
rg o 0 {rg}
R2 o 0 {rl}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 64 -32 64
WIRE 144 64 64 64
WIRE 224 64 144 64
WIRE 304 64 224 64
WIRE 384 64 304 64
WIRE 416 64 384 64
WIRE -32 112 -32 64
WIRE 64 112 64 64
WIRE 144 112 144 64
WIRE 224 112 224 64
WIRE 304 112 304 64
WIRE 416 112 416 64
WIRE -32 240 -32 192
WIRE 64 240 64 192
WIRE 144 240 144 176
WIRE 224 240 224 192
WIRE 304 240 304 192
WIRE 416 240 416 192
SYMBOL res 48 96 R0
SYMATTR InstName rg
SYMATTR Value {rg}
SYMBOL res 400 96 R0
SYMATTR InstName R2
SYMATTR Value {rl}
FLAG -32 240 0
FLAG 64 240 0
FLAG 144 240 0
FLAG 224 240 0
FLAG 304 240 0
FLAG 416 240 0
FLAG 384 64 o