* Z:\home\khalils\Downloads\files\data\raw_asc\06d122a902dd_CPL_AND_NAND.asc
* Generated by LTspice 26.0.1 for Windows.
M1 A1 B N001 0 NMOS
M2 A B N002 0 NMOS
M3 B1 B1 N001 0 NMOS
A1 N001 0 0 0 0 AND 0 0 BUF
A2 N002 0 0 0 0 NAND 0 0 BUF
M4 B B1 N002 0 NMOS
V1 A 0 PULSE(0 5 0 0 0 1n 2n)
V2 B 0 PULSE(0 5 0 0 0 2n 4n)
A3 A 0 0 0 0 A1 0 0 BUF
A4 B 0 0 0 0 B1 0 0 BUF
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 20n
.measure delay_A_to_XOR TRIG V(A) VAL=2.5 TARG V(XOR) VAL=0.5
.measure delay_B_to_XOR TRIG V(B) VAL=2.5 TARG V(XOR) VAL=0.5
.measure delay_A_to_XNOR TRIG V(A) VAL=2.5 TARG V(XNOR) VAL=0.5
.measure delay_B_to_XNOR TRIG V(B) VAL=2.5 TARG V(XNOR) VAL=0.5
.measure delay_A_to_AND TRIG V(A) VAL=2.5 TARG V(AND) VAL=0.5
.measure delay_B_to_AND TRIG V(B) VAL=2.5 TARG V(AND) VAL=0.5
.measure delay_A_to_NAND TRIG V(A) VAL=2.5 TARG V(NAND) VAL=0.5
.measure delay_B_to_NAND TRIG V(B) VAL=2.5 TARG V(NAND) VAL=0.5
.measure delay_A_to_OR TRIG V(A) VAL=2.5 TARG V(OR) VAL=0.5
.measure delay_B_to_OR TRIG V(B) VAL=2.5 TARG V(OR) VAL=0.5
.measure delay_A_to_NOR TRIG V(A) VAL=2.5 TARG V(NOR) VAL=0.5
.measure delay_B_to_NOR TRIG V(B) VAL=2.5 TARG V(NOR) VAL=0.5
* CPL NAND AND
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -320 48 -352 48
WIRE -288 48 -320 48
WIRE -160 48 -224 48
WIRE 512 64 512 48
WIRE -320 80 -320 48
WIRE 96 144 32 144
WIRE 464 144 96 144
WIRE 288 240 288 48
WIRE 656 240 656 64
WIRE -320 256 -352 256
WIRE -288 256 -320 256
WIRE -160 256 -224 256
WIRE -320 288 -320 256
WIRE 240 320 32 320
WIRE 608 320 240 320
WIRE 144 352 144 160
WIRE 208 352 144 352
WIRE 288 352 288 336
WIRE 288 352 208 352
WIRE 512 352 512 160
WIRE 576 352 512 352
WIRE 656 352 656 336
WIRE 656 352 576 352
WIRE 208 384 208 352
WIRE 576 384 576 352
FLAG 144 112 0
FLAG 512 112 0
FLAG 288 288 0
FLAG 656 288 0
FLAG -352 48 A
IOPIN -352 48 In
FLAG -160 48 A1
IOPIN -160 48 In
FLAG -352 256 B
IOPIN -352 256 In
FLAG -160 256 B1
IOPIN -160 256 In
FLAG -320 160 0
FLAG -320 368 0
FLAG 512 48 A
IOPIN 512 48 In
FLAG 656 64 B
IOPIN 656 64 In
FLAG 32 144 B
IOPIN 32 144 In
FLAG 32 320 B1
IOPIN 32 320 In
FLAG 144 64 A1
IOPIN 144 64 In
FLAG 288 48 B1
IOPIN 288 48 In
FLAG 576 448 NAND
IOPIN 576 448 Out
FLAG 208 448 AND
IOPIN 208 448 Out
SYMBOL nmos4 96 64 R0
SYMATTR InstName M1
SYMBOL nmos4 464 64 R0
SYMATTR InstName M2
SYMBOL nmos4 240 240 R0
SYMATTR InstName M3
SYMBOL Digital\\inv 272 384 R90
SYMATTR InstName A1
SYMBOL Digital\\inv 640 384 R90
SYMATTR InstName A2
SYMBOL nmos4 608 240 R0
SYMATTR InstName M4
SYMBOL voltage -320 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 5 0 0 0 1n 2n)
SYMBOL voltage -320 272 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 0 0 0 2n 4n)
SYMBOL Digital\\inv -288 -16 R0
SYMATTR InstName A3
SYMBOL Digital\\inv -288 192 R0
SYMATTR InstName A4
TEXT -424 584 Left 2 !.tran 20n
TEXT -256 -408 Left 2 !.measure delay_A_to_XOR TRIG V(A) VAL=2.5 TARG V(XOR) VAL=0.5 \n.measure delay_B_to_XOR TRIG V(B) VAL=2.5 TARG V(XOR) VAL=0.5 \n.measure delay_A_to_XNOR TRIG V(A) VAL=2.5 TARG V(XNOR) VAL=0.5 \n.measure delay_B_to_XNOR TRIG V(B) VAL=2.5 TARG V(XNOR) VAL=0.5 \n.measure delay_A_to_AND TRIG V(A) VAL=2.5 TARG V(AND) VAL=0.5 \n.measure delay_B_to_AND TRIG V(B) VAL=2.5 TARG V(AND) VAL=0.5 \n.measure delay_A_to_NAND TRIG V(A) VAL=2.5 TARG V(NAND) VAL=0.5 \n.measure delay_B_to_NAND TRIG V(B) VAL=2.5 TARG V(NAND) VAL=0.5 \n.measure delay_A_to_OR TRIG V(A) VAL=2.5 TARG V(OR) VAL=0.5 \n.measure delay_B_to_OR TRIG V(B) VAL=2.5 TARG V(OR) VAL=0.5 \n.measure delay_A_to_NOR TRIG V(A) VAL=2.5 TARG V(NOR) VAL=0.5 \n.measure delay_B_to_NOR TRIG V(B) VAL=2.5 TARG V(NOR) VAL=0.5
TEXT 336 536 Left 2 ;CPL NAND AND