Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1693-3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC1693-3.asy)
Rload OUT 0 10
L1 IN N004 22
D2 N004 OUT 1N5819
C2 OUT 0 47
MQ1 N004 N003 0 0 FDS6680A
C1 N001 0 680p
D1 N001 N002 BZX84C6V2L
XU1 N001 MP_01 0 0 MP_02 MP_03 N003 IN LTC1693-3 ;pnba IN))PHI)GND)))OUT)Vcc
R1 N003 N001 13K
R2 N003 N002 7.5K
V1 IN 0 5
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 2m startup
.lib LTC1693-3.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2388 1428
WIRE 1840 864 1760 864
WIRE 2016 864 1840 864
WIRE 1472 880 1424 880
WIRE 1600 880 1536 880
WIRE 1728 880 1680 880
WIRE 2016 880 2016 864
WIRE 1840 896 1840 864
WIRE 2016 976 2016 960
WIRE 1424 992 1424 880
WIRE 1536 992 1424 992
WIRE 1728 992 1728 880
WIRE 1728 992 1616 992
WIRE 1840 1024 1840 976
WIRE 1904 1024 1840 1024
WIRE 2032 1024 1968 1024
WIRE 2128 1024 2032 1024
WIRE 1840 1040 1840 1024
WIRE 2032 1040 2032 1024
WIRE 2128 1040 2128 1024
WIRE 1760 1056 1760 864
WIRE 1760 1056 1568 1056
WIRE 1568 1072 1568 1056
WIRE 1344 1120 1328 1120
WIRE 1424 1120 1424 992
WIRE 1424 1120 1408 1120
WIRE 1440 1120 1424 1120
WIRE 1728 1120 1728 992
WIRE 1728 1120 1696 1120
WIRE 1792 1120 1728 1120
WIRE 2032 1136 2032 1104
WIRE 2128 1136 2128 1120
WIRE 1840 1152 1840 1136
WIRE 1440 1216 1408 1216
WIRE 1568 1280 1568 1264
SYMBOL NMOS 1792 1040 R0
SYMATTR InstName Q1
SYMATTR Value FDS6680A
SYMBOL schottky 1904 1040 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value 1N5819
SYMBOL zener 1472 896 R270
WINDOW 0 36 32 VTop 2
WINDOW 3 -4 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value BZX84C6V2L
SYMBOL POWERPRODUCTS\\LTC1693-3 1568 1168 R0
SYMATTR InstName U1
SYMBOL ind 1824 880 R0
SYMATTR InstName L1
SYMATTR Value 22
SYMBOL voltage 2016 864 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 1408 1104 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 680p
SYMBOL res 1696 864 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 7.5K
SYMBOL res 2112 1024 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL RES 1632 976 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 13K
SYMBOL cap 2016 1040 R0
SYMATTR InstName C2
SYMATTR Value 47
FLAG 2016 976 0
FLAG 1568 1280 0
FLAG 1328 1120 0
FLAG 1840 1152 0
FLAG 2032 1136 0
FLAG 2128 1136 0
FLAG 2128 1024 OUT
FLAG 2016 864 IN
FLAG 1408 1216 0
TEXT 1840 1272 Left 2 !.tran 2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1992-1.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC1992-1.asy)
V2 -V 0 0
V1 +V 0 2.7
XU1 N001 N003 +V N002 N004 -V N003 N005 LTC1992-1 ;pnba IN-)VOCM)V+)OUT+)OUT-)V-)VMID)IN+
V3 N001 N005 SINE(0 0.5 10K)
C1 N002 0 10p
C2 N004 0 10p
.tran 1m
.lib LTC4.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 972 768
WIRE 192 336 -48 336
WIRE 496 368 496 352
WIRE 240 400 240 384
WIRE -272 432 -272 416
WIRE -160 432 -160 416
WIRE -48 432 -48 336
WIRE 192 432 192 336
WIRE 208 432 192 432
WIRE 496 448 496 432
WIRE 496 448 368 448
WIRE 208 464 192 464
WIRE 192 496 192 464
WIRE 208 496 192 496
WIRE 496 512 368 512
WIRE -272 528 -272 512
WIRE -160 528 -160 512
WIRE 208 528 192 528
WIRE 496 528 496 512
WIRE 240 576 240 560
WIRE 496 608 496 592
WIRE -48 624 -48 512
WIRE 192 624 192 528
WIRE 192 624 -48 624
SYMBOL LTC1992-1 272 480 R0
SYMATTR InstName U1
SYMBOL cap 480 528 R0
SYMATTR InstName C2
SYMATTR Value 10p
SYMBOL cap 480 432 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL voltage -272 416 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.7
SYMBOL voltage -48 416 R0
WINDOW 123 40 100 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value SINE(0 0.5 10K)
SYMBOL voltage -160 416 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 0
FLAG -272 528 0
FLAG -160 528 0
FLAG -272 416 +V
FLAG -160 416 -V
FLAG 496 352 0
FLAG 496 608 0
FLAG 240 384 +V
FLAG 240 576 -V
TEXT 608 576 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\562f1ee60c5d_Parte4.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vout N002 0 N003 N_1u l=1.5u w=9.23u
V1 N002 0 1.7858314
Rd N001 Vout 10k
Vdd N001 0 5
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include cmosedu_models.txt
.dc Vdd 0 5 0.01
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 -160 144 -160
WIRE 144 -144 144 -160
WIRE 192 -96 144 -96
WIRE 288 -16 288 -160
WIRE 288 -16 192 -16
WIRE 144 16 144 -96
WIRE 144 128 144 96
WIRE 224 128 144 128
WIRE 64 176 -32 176
WIRE 176 176 144 176
WIRE 64 208 64 176
WIRE 96 208 64 208
WIRE 176 208 176 176
WIRE 176 208 144 208
WIRE 144 272 144 224
WIRE -32 304 -32 256
SYMBOL voltage 192 -112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName Vdd
SYMATTR Value 5
SYMBOL voltage -32 160 R0
SYMATTR InstName V1
SYMATTR Value 1.7858314
SYMBOL res 128 0 R0
SYMATTR InstName Rd
SYMATTR Value 10k
SYMBOL nmos4 96 128 R0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1.5u w=9.23u
FLAG -32 304 0
FLAG 144 272 0
FLAG 144 -144 0
FLAG 224 128 Vout
TEXT -240 -32 Left 2 !.include cmosedu_models.txt
TEXT -240 328 Left 2 !.dc Vdd 0 5 0.01
* Z:\home\khalils\Downloads\files\data\raw_asc\38b10ae2f794_inv_transfer.asc
* Generated by LTspice 26.0.1 for Windows.
AX1 N001 0 0 0 0 0 0 0 BUF ll=180n wn={nnw} wp={nnw*mp}
V2 vin 0 {vv}
V1 vdd 0 {vv}
.param vv=1.8 nnw=1*180n mp=1
.lib BU_180nm.lib
.dc V2 0 {vv} 0.01
.meas dc vil when d(v(out))=-1 fall 1
.meas dc vih when d(v(out))=-1 rise 1
.meas dc vi_mid param (vil+vih)/2/vv
.meas dc voh find v(out) when d(v(out))=-1 fall 1
.meas dc vol find v(out) when d(v(out))=-1 rise 1
.meas dc vo_mid param (vol+voh)/2/vv
.meas dc NMH param abs(voh-vih)
.meas dc NML param abs(vil-vol)
.meas dc voh_fraction param voh/vv
.meas dc vol_fraction param vol/vv
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1168 680
WIRE 416 224 -64 224
WIRE -64 272 -64 224
WIRE 416 304 416 224
WIRE 400 320 96 320
WIRE 496 320 448 320
WIRE 96 400 96 320
WIRE 416 400 416 336
WIRE 416 400 224 400
WIRE 224 416 224 400
SYMBOL /voltage 96 384 R0
WINDOW 3 18 89 Left 2
SYMATTR InstName V2
SYMATTR Value {vv}
SYMBOL inv 416 320 R0
SYMATTR InstName X1
SYMATTR SpiceLine ll=180n wn={nnw} wp={nnw*mp}
SYMBOL /voltage -64 256 R0
SYMATTR InstName V1
SYMATTR Value {vv}
FLAG -64 352 0
FLAG 96 480 0
FLAG 224 416 0
FLAG -64 224 vdd
FLAG 224 400 vss
FLAG 96 320 vin
FLAG 496 320 out
TEXT -88 72 Left 2 !.param vv=1.8 nnw=1*180n mp=1\n.lib BU_180nm.lib\n.dc V2 0 {vv} 0.01
TEXT 560 72 Left 2 !.meas dc vil when d(v(out))=-1 fall 1\n.meas dc vih when d(v(out))=-1 rise 1\n.meas dc vi_mid param (vil+vih)/2/vv\n.meas dc voh find v(out) when d(v(out))=-1 fall 1\n.meas dc vol find v(out) when d(v(out))=-1 rise 1\n.meas dc vo_mid param (vol+voh)/2/vv\n.meas dc NMH param abs(voh-vih)\n.meas dc NML param abs(vil-vol)\n.meas dc voh_fraction param voh/vv\n.meas dc vol_fraction param vol/vv
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7118-5.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7118-5.0.asy)
XU1 IN OUT IN N001 OUT 0 ADP7118 Vref=5 ;pnba Vin)Sense)EN)SS)Vout)GND
C1 OUT 0 2.2 Rser=1.5m
C2 N001 0 4.7n
V1 IN 0 6
Rload OUT 0 30
.tran 6m startup
.lib ADP7102.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 64 32 -32 32
WIRE 96 32 64 32
WIRE 384 32 352 32
WIRE 448 32 384 32
WIRE 544 32 448 32
WIRE -32 48 -32 32
WIRE 448 48 448 32
WIRE 544 48 544 32
WIRE 64 128 64 32
WIRE 96 128 64 128
WIRE -32 144 -32 128
WIRE 448 144 448 112
WIRE 544 144 544 128
WIRE 16 224 0 224
WIRE 96 224 80 224
WIRE 384 224 384 32
WIRE 384 224 352 224
WIRE 224 304 224 288
SYMBOL ADP7118-5.0 224 128 R0
SYMATTR InstName U1
SYMBOL res 528 32 R0
SYMATTR InstName Rload
SYMATTR Value 30
SYMBOL cap 80 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 4.7n
SYMBOL voltage -32 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 6
SYMBOL cap 432 48 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
FLAG 224 304 0
FLAG -32 144 0
FLAG 0 224 0
FLAG 544 144 0
FLAG 448 144 0
FLAG -32 32 IN
FLAG 544 32 OUT
TEXT 408 264 Left 2 !.tran 6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1963A-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1963A-1.8.asy)
C1 OUT 0 1
Rload OUT 0 1K
V1 IN 0 PWL(0 0 1 10)
XU1 IN IN 0 OUT OUT LT1963-1.8 ;pnba _SHDN)IN)GND)OUT)SENSE
.tran 1
.lib LT1963.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 16 48 -208 48
WIRE 32 48 16 48
WIRE 352 48 320 48
WIRE 416 48 352 48
WIRE 512 48 416 48
WIRE -208 64 -208 48
WIRE 416 64 416 48
WIRE 512 64 512 48
WIRE 16 144 16 48
WIRE 32 144 16 144
WIRE 352 144 352 48
WIRE 352 144 320 144
WIRE -208 160 -208 144
WIRE 416 160 416 128
WIRE 512 160 512 144
WIRE 176 240 176 208
SYMBOL PowerProducts\\LT1963A-1.8 176 96 R0
SYMATTR InstName U1
SYMBOL voltage -208 48 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL res 496 48 R0
SYMATTR InstName Rload
SYMATTR Value 1K
SYMBOL cap 400 64 R0
SYMATTR InstName C1
SYMATTR Value 1
FLAG -208 160 0
FLAG 416 160 0
FLAG 512 160 0
FLAG 176 240 0
FLAG -208 48 IN
FLAG 512 48 OUT
TEXT 400 216 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\24c03e797e95_Draft103.asc
* Generated by LTspice 26.0.1 for Windows.
* Can just use a cmos op-amp running at 5V\nAnd a cmos comparator.\nGain has already been added.\nSo noise, and thermal wander of Vos. doesn't matter\nAnd the Vos is within the loop
* No. this isn't right. it is not at an input zero cross.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT1006.asy)
;dc V1 0 10 0.01
R2 0 VOUT 10k
XU2 N003 N005 VCC VEE N006 LT1006 ;pnba In+)In-)V+)V-)OUT
V2 VCC 0 5
D4 N002 P001 1N4148
Q1 N003 N006 VOUT 0 2N3904
R1 N005 N004 10k
V1 0 VEE 5
VIN N004 0 SINE(0 10 50)
D2 N001 P002 1N4148
D1 P001 N001 1N4148
D3 P002 N002 1N4148
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 0.1
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1316 680
WIRE 496 -240 496 -320
WIRE 624 -240 624 -320
WIRE 96 -160 -16 -160
WIRE 576 0 352 0
WIRE 576 16 576 0
WIRE 240 80 -96 80
WIRE 384 80 320 80
WIRE 512 96 512 64
WIRE 512 96 448 96
WIRE 352 112 352 0
WIRE 384 112 352 112
WIRE -96 128 -96 80
WIRE 576 144 576 112
WIRE 736 144 576 144
WIRE 752 144 736 144
SYMBOL diode 560 -256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 -35 -122 VTop 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL diode 496 -304 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 34 179 VBottom 2
SYMATTR InstName D2
SYMATTR Value 1N4148
SYMBOL voltage -16 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 55 55 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 592 240 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -96 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 24 44 Left 2
SYMATTR Value SINE(0 10 50)
SYMATTR InstName VIN
SYMBOL diode 560 -304 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 13 187 VBottom 2
SYMATTR InstName D3
SYMATTR Value 1N4148
SYMBOL voltage -16 -256 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 55 55 Left 2
SYMATTR Value 5
SYMATTR InstName V2
SYMBOL res 336 64 R90
WINDOW 0 -23 59 VBottom 2
WINDOW 3 -25 66 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMBOL diode 624 -256 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 -5 -113 VTop 2
SYMATTR InstName D4
SYMATTR Value 1N4148
SYMBOL npn 512 16 R0
SYMATTR InstName Q1
SYMATTR Value 2N3904
SYMBOL OpAmps\\LT1006 416 32 R0
SYMATTR InstName U2
FLAG -96 208 0
FLAG 96 -160 0
FLAG 448 -96 VOUT
FLAG -16 -240 VCC
FLAG 416 64 VCC
FLAG -16 -80 VEE
FLAG 416 128 VEE
FLAG 144 -32 VEE
FLAG 576 224 0
FLAG 736 144 VOUT
TEXT -168 232 Left 2 !;dc V1 0 10 0.01
TEXT -136 368 Left 2 !.tran 0.1
TEXT 704 -160 Left 2 ;Can just use a cmos op-amp running at 5V\nAnd a cmos comparator.\nGain has already been added.\nSo  noise, and thermal wander of Vos. doesn't matter\nAnd the Vos is within the loop
TEXT 720 48 Left 2 ;No. this isn't right. it is not at an input  zero cross.
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM4649.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM4649.asy)
XU1 N002 NC_01 N003 MP_02 MP_03 MP_04 MP_05 MP_06 N001 OUT 0 N001 MP_07 OUT MP_08 NC_09 MP_10 0 MP_11 0 MP_12 MP_13 MP_14 MP_15 NC_16 IN MP_17 MP_18 MP_19 MP_20 NC_21 NC_22 NC_23 NC_24 NC_25 MP_26 MP_27 NC_28 LTM4649 ;pnba Track/SS)COMP)FB))))))Vout_lcl)Diffp)Diffn)Diffout))Vout))Pgood))GND))Mode)))))INTVcc)Vin)))))SW)CLKout)PHmode)CLKin)FREQ)))Run
V1 IN 0 12
C1 N002 0 .001
R1 N003 0 6.65K
C2 OUT 0 100 x2 V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
Rload OUT 0 .15
.tran 1m startup
.lib LTM4649.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 712
WIRE 64 -80 -48 -80
WIRE 480 -80 448 -80
WIRE 560 -80 480 -80
WIRE 688 -80 560 -80
WIRE -48 -64 -48 -80
WIRE 560 -64 560 -80
WIRE 688 -64 688 -80
WIRE 464 16 448 16
WIRE -48 32 -48 16
WIRE 560 32 560 0
WIRE 688 32 688 16
WIRE 64 112 48 112
WIRE 464 112 464 16
WIRE 464 112 448 112
WIRE 480 208 480 -80
WIRE 480 208 448 208
WIRE 464 304 448 304
WIRE -32 496 -48 496
WIRE 64 496 32 496
WIRE 464 496 448 496
WIRE 560 496 544 496
WIRE 256 672 256 656
SYMBOL cap 544 -64 R0
WINDOW 123 30 76 Left 2
SYMATTR Value2 x2
SYMATTR InstName C2
SYMATTR Value 100
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
SYMBOL PowerProducts\\LTM4649 256 256 R0
SYMATTR InstName U1
SYMBOL cap 32 480 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value .001
SYMBOL res 672 -80 R0
SYMATTR InstName Rload
SYMATTR Value .15
SYMBOL res 448 512 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 6.65K
SYMBOL voltage -48 -80 R0
SYMATTR InstName V1
SYMATTR Value 12
FLAG 256 672 0
FLAG -48 32 0
FLAG 48 112 0
FLAG -48 496 0
FLAG 560 496 0
FLAG 560 32 0
FLAG 688 32 0
FLAG 464 304 0
FLAG -48 -80 IN
FLAG 688 -80 OUT
TEXT 560 616 Left 2 !.tran 1m startup
* Z:\tmp\asc_dec_bjh7r6w2\0185532f378f_Fig18_19_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
M4 VDD N001 N002 VDD P_50n l=50n w=1u
M6 N003 N001 0 0 N_50n l=50n w=500n
M3 VDD N001 N001 VDD P_50n l=50n w=1u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1496 680
WIRE 576 -544 576 -592
WIRE 576 -432 576 -448
WIRE 576 -416 576 -432
WIRE 576 -288 576 -320
WIRE 688 -464 624 -464
WIRE 688 -432 576 -432
WIRE 688 -432 688 -464
WIRE 688 -192 688 -432
WIRE 704 -192 688 -192
WIRE 752 -288 576 -288
WIRE 752 -272 752 -288
WIRE 752 -144 752 -176
WIRE 880 -464 688 -464
WIRE 928 -544 928 -592
WIRE 928 -432 928 -448
WIRE 928 -416 928 -432
WIRE 928 -288 752 -288
WIRE 1136 -432 928 -432
SYMBOL pmos4 880 -544 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M4
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
SYMBOL nmos4 704 -272 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M6
SYMATTR Value N_50n
SYMATTR Value2 l=50n w=500n
SYMBOL pmos4 624 -544 M0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M3
SYMATTR Value P_50n
SYMATTR Value2 l=50n w=1u
FLAG 576 -368 0
FLAG 576 -496 VDD
FLAG 752 -144 0
FLAG 576 -592 VDD
FLAG 928 -496 VDD
FLAG 928 -368 0
FLAG 928 -592 VDD
FLAG 752 -224 0
FLAG 528 -336 Vinm
* Z:\home\khalils\Downloads\files\data\raw_asc\569fb98a0036_Assignment_4a__i_.asc
* Generated by LTspice 26.0.1 for Windows.
* Full Wave Rectifier (Centre Tapped Transformer) (Practical)
L3 N004 0 0.001
L2 0 N002 0.001
D1 N002 N003 1N4148
D2 N004 N003 1N4148
K L1 L2 L3 1
L1 N001 0 0.001
V1 N001 0 SINE(0 5 1000) Rser=0.001
R1 N003 0 1000
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 5ms
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE 128 16 -128 16
WIRE 368 16 240 16
WIRE 496 16 432 16
WIRE 240 48 240 16
WIRE -128 128 -128 16
WIRE 128 128 128 16
WIRE 240 160 240 128
WIRE 288 160 240 160
WIRE 368 160 288 160
WIRE 496 160 496 16
WIRE 496 160 448 160
WIRE 240 192 240 160
WIRE 288 192 288 160
WIRE -128 320 -128 208
WIRE 48 320 -128 320
WIRE 128 320 128 208
WIRE 128 320 48 320
WIRE 240 320 240 272
WIRE 368 320 240 320
WIRE 496 320 496 160
WIRE 496 320 432 320
WIRE 48 336 48 320
SYMBOL diode 368 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4148
SYMBOL res 464 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1000
SYMBOL voltage -128 112 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
SYMATTR SpiceLine Rser=0.001
SYMATTR InstName V1
SYMATTR Value SINE(0 5 1000)
SYMBOL ind2 256 288 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L3
SYMATTR Value 0.001
SYMATTR Type ind
SYMBOL ind2 256 144 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName L2
SYMATTR Value 0.001
SYMATTR Type ind
SYMBOL ind2 112 112 R0
SYMATTR InstName L1
SYMATTR Value 0.001
SYMATTR Type ind
SYMBOL diode 368 336 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value 1N4148
FLAG 288 192 0
FLAG 48 336 0
TEXT -152 -48 Left 2 ;Full Wave Rectifier (Centre Tapped Transformer) (Practical)
TEXT 112 -8 Left 2 !K L1 L2 L3 1
TEXT -144 352 Left 2 !.tran 5ms
* Z:\home\khalils\Downloads\files\data\raw_asc\5328561c41f0_linear_regulator.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1117.asy)
R1 Vout N002 460
R3 N004 0 330
C2 Vout 0 C
V1 N001 0 5
R4 N003 0 120
R2 N002 0 270
XU1 N002 Vout N001 LT1117 ;pnba ADJ)OUT)IN
.dc V1 0 10 0.1
.lib LT1117.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 64 112 -112 112
WIRE 400 112 320 112
WIRE 464 112 400 112
WIRE 592 112 464 112
WIRE 608 112 592 112
WIRE -112 160 -112 112
WIRE 400 160 400 112
WIRE 192 272 192 208
WIRE 400 272 400 240
WIRE 400 272 192 272
WIRE -112 320 -112 240
WIRE 304 368 304 320
WIRE 400 368 400 272
WIRE 496 368 496 320
WIRE 592 368 592 112
WIRE 304 480 304 448
WIRE 400 480 400 448
WIRE 496 480 496 448
WIRE 592 480 592 432
WIRE 0 0 0 0
SYMBOL voltage -112 144 R0
WINDOW 3 48 68 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 47 34 Left 2
SYMATTR Value 5
SYMATTR InstName V1
SYMBOL res 384 144 R0
SYMATTR InstName R1
SYMATTR Value 460
SYMBOL res 480 352 R0
SYMATTR InstName R3
SYMATTR Value 330
SYMBOL cap 576 368 R0
SYMATTR InstName C2
SYMBOL res 384 352 R0
SYMATTR InstName R2
SYMATTR Value 270
SYMBOL PowerProducts\\LT1117 192 112 R0
SYMATTR InstName U1
SYMBOL res 288 352 R0
SYMATTR InstName R4
SYMATTR Value 120
FLAG -112 320 0
FLAG 400 480 0
FLAG 464 112 Vout
FLAG 496 480 0
FLAG 304 480 0
FLAG 592 480 0
TEXT -56 312 Left 2 !.dc V1 0 10 0.1
* Z:\home\khalils\Downloads\files\data\raw_asc\32503b99aa8e_Fig11_4_long.asc
* Generated by LTspice 26.0.1 for Windows.
* Plot Vout and Id(M2)
* 10/1
* 10/1
M1 Vout Vin 0 0 N_1u l=1u w=10u
M2 VDD Vin Vout VDD P_1u l=1u w=10u
VDD VDD 0 5
Vin Vin 0 0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.dc Vin 0 5 1m
.lib cmosedu_models.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE 192 -368 192 -384
WIRE 192 -352 192 -368
WIRE 192 -240 192 -272
WIRE 208 -96 208 -112
WIRE 208 0 208 -16
WIRE 320 -176 304 -176
WIRE 368 -176 320 -176
WIRE 368 -176 368 -224
WIRE 368 -96 368 -176
WIRE 400 -224 368 -224
WIRE 400 -96 368 -96
WIRE 448 -304 448 -352
WIRE 448 -176 448 -208
WIRE 448 -32 448 -80
WIRE 624 -176 448 -176
WIRE 656 -176 624 -176
SYMBOL voltage 192 -368 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 5
SYMBOL voltage 208 -112 R0
WINDOW 0 -72 21 Left 0
WINDOW 3 -60 74 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vin
SYMATTR Value 0
SYMBOL nmos4 400 -176 R0
WINDOW 0 104 24 Right 0
WINDOW 3 179 41 Right 0
WINDOW 123 213 74 Right 0
SYMATTR InstName M1
SYMATTR Value N_1u
SYMATTR Value2 l=1u w=10u
SYMBOL pmos4 400 -304 R0
WINDOW 0 88 9 Right 0
WINDOW 3 168 20 Right 0
WINDOW 123 206 76 Right 0
SYMATTR InstName M2
SYMATTR Value P_1u
SYMATTR Value2 l=1u w=10u
FLAG 208 0 0
FLAG 624 -176 Vout
FLAG 208 -112 Vin
FLAG 448 -128 0
FLAG 192 -240 0
FLAG 192 -368 VDD
FLAG 448 -256 VDD
FLAG 448 -32 0
FLAG 448 -352 VDD
FLAG 320 -176 Vin
TEXT 264 8 Left 0 !.dc Vin 0 5 1m
TEXT 264 32 Left 0 !.lib cmosedu_models.txt
TEXT 496 -360 Left 0 ;Plot Vout and Id(M2)
TEXT 344 -272 Left 0 ;10/1
TEXT 344 -72 Left 0 ;10/1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3415.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3415.asy)
R2 OUT N004 120K
C2 IN 0 66
R1 N004 0 60K
XU1 MP_01 0 0 IN MP_02 N003 MP_03 MP_04 MP_05 IN 0 N002 0 MP_06 MP_07 MP_08 MP_09 MP_10 MP_11 NC_12 NC_13 N001 MP_14 MP_15 MP_16 MP_17 MP_18 MP_19 N004 IN MP_20 IN 0 IN MP_21 MP_22 IN N005 LTC3415 ;pnba )SGND)PLLLPF)PVin))SW))))Mode)CLKin)PHmode)PGND)))))))MGN)BSEL)Pgood)))))))FB)Track))Ith)Ithm)SVin)))Run)CLKout
V1 IN 0 3.6
C1 OUT 0 141
L1 N003 OUT .2
Rload OUT 0 .3
.tran 200u startup
.lib LTC3415.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1040 708
WIRE -112 16 -208 16
WIRE -32 16 -112 16
WIRE 112 16 -32 16
WIRE 240 16 112 16
WIRE 384 16 240 16
WIRE -208 32 -208 16
WIRE -112 32 -112 16
WIRE 112 48 112 16
WIRE 240 48 240 16
WIRE -32 96 -32 16
WIRE -16 96 -32 96
WIRE 384 96 384 16
WIRE 384 96 368 96
WIRE -208 128 -208 112
WIRE -112 128 -112 96
WIRE -32 160 -32 96
WIRE -16 160 -32 160
WIRE 384 160 368 160
WIRE -32 224 -32 160
WIRE -16 224 -32 224
WIRE 384 224 368 224
WIRE -16 288 -32 288
WIRE 400 288 368 288
WIRE 560 288 480 288
WIRE 672 288 560 288
WIRE 672 304 672 288
WIRE -16 352 -32 352
WIRE 416 352 368 352
WIRE 464 352 416 352
WIRE 560 352 560 288
WIRE 560 352 544 352
WIRE 416 368 416 352
WIRE 560 368 560 352
WIRE 672 400 672 384
WIRE -16 416 -32 416
WIRE 416 464 416 448
WIRE 560 464 560 432
WIRE -16 480 -32 480
WIRE 128 544 128 528
WIRE 240 544 240 528
SYMBOL cap 544 368 R0
SYMATTR InstName C1
SYMATTR Value 141
SYMBOL cap -128 32 R0
SYMATTR InstName C2
SYMATTR Value 66
SYMBOL ind 384 304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value .2
SYMBOL voltage -208 16 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL LTC3415 176 288 R0
SYMATTR InstName U1
SYMBOL res 560 336 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 120K
SYMBOL res 400 352 R0
SYMATTR InstName R1
SYMATTR Value 60K
SYMBOL res 656 288 R0
SYMATTR InstName Rload
SYMATTR Value .3
FLAG 672 288 OUT
FLAG -208 16 IN
FLAG 416 464 0
FLAG 560 464 0
FLAG 672 400 0
FLAG 240 544 0
FLAG 128 544 0
FLAG -112 128 0
FLAG -208 128 0
FLAG -32 352 0
FLAG -32 480 0
FLAG 384 160 0
TEXT 552 528 Left 2 !.tran 200u startup