* Z:\home\khalils\Downloads\files\data\raw_asc\ADAQ4224.asc
* Generated by LTspice 26.0.1 for Windows.
* IN+, IN-: Analog inputs. Transients from sampling caps are simulated. Input range is +/-VREF
* REF: For 5V VREF VDD should be 5.4V +/-100mV
* VDD: For REF=4.096V VDD=4.75V to 5.25V For REF=4.5V VDD= 4.8V to 5.25V
* Digital Out: Digital representation of output. +/-2^23 This can be used to drive DAC inputs
* Vout: Analog output +/-VREF
* CNV: 2MHz max 0V-1.8V logic level
* RSTn: Resets ADC. Tie to 1.8V for normal operation
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\ADC\ADAQ4224.asy)
V6 N015 0 3.3
V7 N003 0 5
V5 N012 0 3.3
R1 0 N007 10k
V4 N001 0 18
V12 N013 0 5
XU1 N001 N002 N006 N008 N012 N015 N003 N009 N004 N005 N011 N007 N014 N010 0 N013 ADAQ4224 ;pnba VDD_H)VSS_H)IN+)IN-)A0)A1)VDD_FDA)VSS_FDA)REF)VDD_5V)CNV)VOUT)BUSY)_RST)GND)PDB_FDA
V2 N008 0 SINE(0 0.075 2k 0 0 180)
V10 N005 0 5
V1 N006 0 SINE(0 0.075 2k)
V8 N009 0 -1
R2 N014 0 10k
V9 N004 0 4.096
V13 N011 0 PULSE(0 1.8 500n .2n .2n 19.8n 500n)
V11 N010 0 PWL(0 0 100n 0 200n 1.8)
V3 N002 0 -18
.tran 0 1m 0 10n
.lib ADAQ4224.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2100 788
WIRE -144 -432 -144 -480
WIRE -80 -336 -80 -480
WIRE 128 -336 128 -368
WIRE 448 -336 448 -368
WIRE 544 -336 544 -368
WIRE -144 -224 -144 -352
WIRE -80 -224 -80 -256
WIRE 128 -224 128 -256
WIRE 448 -224 448 -256
WIRE 544 -224 544 -256
WIRE -432 64 -560 64
WIRE -288 64 -352 64
WIRE 736 112 704 112
WIRE 848 112 816 112
WIRE -560 144 -592 144
WIRE -288 144 -480 144
WIRE 736 288 704 288
WIRE 128 448 128 432
WIRE 128 448 48 448
WIRE 432 448 432 432
WIRE 432 448 304 448
WIRE 560 448 560 432
WIRE 688 448 560 448
WIRE -144 464 -144 432
WIRE 48 464 48 448
WIRE 192 464 192 432
WIRE 496 464 496 432
WIRE 688 464 688 448
WIRE 304 528 304 448
WIRE -80 560 -80 432
WIRE 48 560 48 544
WIRE 192 560 192 544
WIRE 496 560 496 544
WIRE 688 560 688 544
WIRE 304 624 304 608
WIRE -144 672 -144 544
WIRE -80 672 -80 640
SYMBOL voltage 304 512 R0
WINDOW 0 15 18 Left 2
WINDOW 3 18 94 Left 2
SYMATTR InstName V11
SYMATTR Value PWL(0 0 100n 0 200n 1.8)
SYMBOL voltage -144 -336 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V4
SYMATTR Value 18
SYMBOL voltage -80 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V3
SYMATTR Value -18
SYMBOL voltage 128 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value 5
SYMBOL voltage 48 448 R0
SYMATTR InstName V8
SYMATTR Value -1
SYMBOL voltage -464 144 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V2
SYMATTR Value SINE(0 0.075 2k 0 0 180)
SYMBOL voltage 448 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V9
SYMATTR Value 4.096
SYMBOL voltage 688 448 R0
SYMATTR InstName V13
SYMATTR Value PULSE(0 1.8 500n .2n .2n 19.8n 500n)
SYMBOL ADAQ4224 80 80 R0
SYMATTR InstName U1
SYMBOL voltage -144 448 R0
SYMATTR InstName V5
SYMATTR Value 3.3
SYMBOL voltage 544 -240 M180
WINDOW 0 24 96 Left 2
WINDOW 3 24 16 Left 2
SYMATTR InstName V10
SYMATTR Value 5
SYMBOL res 480 448 R0
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL voltage -336 64 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value SINE(0 0.075 2k)
SYMBOL voltage 192 448 R0
SYMATTR InstName V12
SYMATTR Value 5
SYMBOL voltage -80 544 R0
SYMATTR InstName V6
SYMATTR Value 3.3
SYMBOL res 832 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10k
FLAG -560 64 0
FLAG -592 144 0
FLAG -80 -480 0
FLAG -144 -480 0
FLAG 736 288 0
FLAG 848 112 0
FLAG -144 672 0
FLAG -80 672 0
FLAG 128 -368 0
FLAG 48 560 0
FLAG 448 -368 0
FLAG 544 -368 0
FLAG 304 624 0
FLAG 496 560 0
FLAG 688 560 0
FLAG 192 560 0
TEXT 728 704 Left 2 !.tran 0 1m 0 10n
TEXT 1000 -240 Left 2 ;IN+, IN-: Analog inputs. Transients from sampling caps are simulated. Input range is +/-VREF
TEXT 1056 -208 Left 2 ;REF: For 5V VREF VDD should be 5.4V +/-100mV
TEXT 1048 -176 Left 2 ;VDD: For REF=4.096V VDD=4.75V to 5.25V For REF=4.5V VDD= 4.8V to 5.25V
TEXT 976 -144 Left 2 ;Digital Out: Digital representation of output. +/-2^23 This can be used to drive DAC inputs
TEXT 1048 -112 Left 2 ;Vout: Analog output +/-VREF
TEXT 1048 -80 Left 2 ;CNV: 2MHz max 0V-1.8V logic level
TEXT 1040 -48 Left 2 ;RSTn: Resets ADC. Tie to 1.8V for normal operation