Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\tmp\asc_dec_bjh7r6w2\137b0f98e3ce_Amp03op_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R3 neg o {R2}
R1 N001 neg {R1}
V1 N001 0 {V1}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 968 680
WIRE -64 80 -192 80
WIRE 80 80 16 80
WIRE 160 80 80 80
WIRE 320 80 240 80
WIRE -64 208 -112 208
WIRE 80 208 80 80
WIRE 80 208 16 208
WIRE 128 208 80 208
WIRE 320 224 320 80
WIRE 320 224 192 224
WIRE 128 240 80 240
WIRE 320 256 320 224
WIRE -192 272 -192 80
WIRE -112 272 -112 208
WIRE 80 304 80 240
WIRE -192 368 -192 352
WIRE -112 368 -112 352
SYMBOL res 144 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value {R2}
SYMBOL res -80 96 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value {R1}
SYMBOL voltage -192 256 R0
WINDOW 3 -98 74 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 -86 45 Left 2
SYMATTR Value {V1}
SYMATTR InstName V1
FLAG -112 368 0
FLAG 160 192 Vpp
FLAG 160 256 Vnn
FLAG -192 368 0
FLAG 320 224 o
FLAG 80 80 neg
* Z:\home\khalils\Downloads\files\data\raw_asc\100ec9b23e07_Pre-charge_FET.asc
* Generated by LTspice 26.0.1 for Windows.
* Battery simulation\nInternal resistance: ~100mOhm per cell, *10/2 (because 10S2P) = 500mOhm
* Pre-charge FET
* Analysis Setup\n1000ms simulation in 1ms increments
* 15V Linear regulator
* System Load
* Operating point:\nCurrent draw (battery engaged): 15uA\nCurrent draw (battery not engaged): 0
R5 SYSTEM_GND Vd 1k
R_SYSTEM CELL_10_POS SYSTEM_GND 10
R4 PRECHG_FET_EN 0 1Meg
M2 Vd PRECHG_FET_EN 0 0 BSS123
V1 CELL_10_POS 0 30 Rser=500m
V3 PRECHG_FET_EN 0 PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
V2 15VO 0 15
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 1m 150m uic
.step param R5 list 100 1k 2k 5k
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 5144 2508
WIRE 352 416 112 416
WIRE 112 560 112 416
WIRE 1216 656 1072 656
WIRE 112 720 112 640
WIRE 224 720 112 720
WIRE 224 736 224 720
WIRE 1072 768 1072 656
WIRE 112 800 112 720
WIRE 352 800 112 800
WIRE 3024 928 2896 928
WIRE 1072 1024 1072 848
WIRE 1216 1024 1072 1024
WIRE 3024 1104 3024 928
WIRE 464 1216 176 1216
WIRE 1488 1232 1296 1232
WIRE 1664 1232 1488 1232
WIRE 1488 1312 1488 1232
WIRE 176 1360 176 1216
WIRE 3024 1376 3024 1184
WIRE 3024 1376 2896 1376
WIRE 1664 1472 1664 1232
WIRE 1488 1520 1488 1392
WIRE 1488 1520 1296 1520
WIRE 1648 1520 1488 1520
WIRE 1792 1520 1744 1520
WIRE 1872 1520 1792 1520
WIRE 2144 1520 1952 1520
WIRE 176 1584 176 1440
WIRE 464 1584 176 1584
DATAFLAG 1488 1232 "$"
RECTANGLE Normal 60 1088 996 1644 2
RECTANGLE Normal 1068 1084 2372 1648 2
RECTANGLE Normal 40 872 564 1064 2
RECTANGLE Normal 32 300 592 832 2
RECTANGLE Normal 2580 824 3200 1448 2
SYMBOL voltage 1072 752 R0
SYMATTR InstName V3
SYMATTR Value PWL(0 0 .005 0 .0051 15 .05 15 .0501 0)
SYMBOL nmos 1744 1472 R90
SYMATTR InstName M2
SYMATTR Value BSS123
SYMBOL res 3008 1088 R0
SYMATTR InstName R_SYSTEM
SYMATTR Value 10
SYMBOL voltage 112 544 R0
SYMATTR InstName V2
SYMATTR Value 15
SYMBOL res 1968 1504 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 1k
SYMBOL battery 176 1344 R0
SYMATTR InstName V1
SYMATTR Value 30
SYMATTR SpiceLine Rser=500m
SYMBOL res 1472 1296 R0
SYMATTR InstName R4
SYMATTR Value 1Meg
FLAG 1296 1520 BMS_GND
FLAG 1296 1232 PRECHG_FET_EN
FLAG 2144 1520 SYSTEM_GND
FLAG 464 1216 CELL_10_POS
FLAG 464 1584 BMS_GND
FLAG 352 416 15VO
FLAG 352 800 BMS_GND
FLAG 1216 656 PRECHG_FET_EN
FLAG 1216 1024 BMS_GND
FLAG 2896 1376 SYSTEM_GND
FLAG 2896 928 CELL_10_POS
FLAG 224 736 0
FLAG 1792 1520 Vd
TEXT 88 968 Left 2 !.tran 1m 150m uic
TEXT 88 1128 Left 2 ;Battery simulation\nInternal resistance: ~100mOhm per cell, *10/2 (because 10S2P) = 500mOhm
TEXT 1120 1120 Left 2 ;Pre-charge FET
TEXT 80 888 Left 2 ;Analysis Setup\n1000ms simulation in 1ms increments
TEXT 72 336 Left 2 ;15V Linear regulator
TEXT 2616 848 Left 2 ;System Load
TEXT 1864 1392 Left 2 !.step param R5 list 100 1k 2k 5k
TEXT 1800 600 Left 2 ;Operating point:\nCurrent draw (battery engaged): 15uA\nCurrent draw (battery not engaged): 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3029.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3029.asy)
R1 OUT1 N002 113K
Rload OUT1 0 36
V1 IN 0 PWL(0 0 1 10)
C4 OUT2 N003 .01
R4 N004 0 237K
C1 OUT1 0 3.3
Rload1 OUT2 0 30
C3 OUT2 0 3.3
R3 OUT2 N004 54.9K
XU1 OUT1 N002 0 N001 IN IN IN IN OUT2 N004 N003 LT3029 ;pnba OUT1)ADJ1)GND)BYP1)_SHDN1)_SHDN2)IN2)IN1)OUT2)ADJ2)BYP2
C2 OUT1 N001 .01
R2 N002 0 237K
.tran 1
.lib LT1763.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 -512 -240 -512
WIRE 0 -512 -32 -512
WIRE 336 -512 304 -512
WIRE 416 -512 336 -512
WIRE 528 -512 416 -512
WIRE 624 -512 528 -512
WIRE -240 -496 -240 -512
WIRE 336 -496 336 -512
WIRE 528 -496 528 -512
WIRE 624 -496 624 -512
WIRE 416 -464 416 -512
WIRE -32 -416 -32 -512
WIRE 0 -416 -32 -416
WIRE 336 -416 336 -432
WIRE 336 -416 304 -416
WIRE -240 -400 -240 -416
WIRE 528 -400 528 -432
WIRE 624 -400 624 -416
WIRE -32 -320 -32 -416
WIRE 0 -320 -32 -320
WIRE 416 -320 416 -384
WIRE 416 -320 304 -320
WIRE 432 -320 416 -320
WIRE 528 -320 512 -320
WIRE -32 -224 -32 -320
WIRE 0 -224 -32 -224
WIRE 336 -224 304 -224
WIRE 416 -224 336 -224
WIRE 528 -224 416 -224
WIRE 624 -224 528 -224
WIRE 336 -208 336 -224
WIRE 528 -208 528 -224
WIRE 624 -208 624 -224
WIRE 416 -176 416 -224
WIRE 336 -128 336 -144
WIRE 336 -128 304 -128
WIRE 528 -112 528 -144
WIRE 624 -112 624 -128
WIRE 416 -32 416 -96
WIRE 416 -32 304 -32
WIRE 432 -32 416 -32
WIRE 528 -32 512 -32
WIRE 160 32 160 16
SYMBOL res 400 -480 R0
SYMATTR InstName R1
SYMATTR Value 113K
SYMBOL PowerProducts\\LT3029 160 -272 R0
SYMATTR InstName U1
SYMBOL res 416 -304 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 237K
SYMBOL cap 320 -496 R0
SYMATTR InstName C2
SYMATTR Value .01
SYMBOL voltage -240 -512 R0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMBOL cap 512 -496 R0
SYMATTR InstName C1
SYMATTR Value 3.3
SYMBOL res 416 -16 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 237K
SYMBOL res 608 -512 R0
SYMATTR InstName Rload
SYMATTR Value 36
SYMBOL cap 320 -208 R0
SYMATTR InstName C4
SYMATTR Value .01
SYMBOL cap 512 -208 R0
SYMATTR InstName C3
SYMATTR Value 3.3
SYMBOL res 608 -224 R0
SYMATTR InstName Rload1
SYMATTR Value 30
SYMBOL res 400 -192 R0
SYMATTR InstName R3
SYMATTR Value 54.9K
FLAG -240 -400 0
FLAG 528 -400 0
FLAG 624 -400 0
FLAG 160 32 0
FLAG 624 -512 OUT1
FLAG -240 -512 IN
FLAG 528 -320 0
FLAG 528 -112 0
FLAG 624 -112 0
FLAG 624 -224 OUT2
FLAG 528 -32 0
TEXT 560 16 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\39a476d90e71_Diode-trr-1.asc
* Generated by LTspice 26.0.1 for Windows.
D1 a N001 1N4007
V1 a 0 PULSE(-50 50 1u 5n 5n 3u 10u) Rser=10
R1 N001 0 150
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10u
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 880 680
WIRE -176 128 -208 128
WIRE -112 128 -176 128
WIRE 32 128 -48 128
WIRE -208 176 -208 128
WIRE 32 176 32 128
WIRE -208 304 -208 256
WIRE -80 304 -208 304
WIRE 32 304 32 256
WIRE 32 304 -80 304
WIRE -80 320 -80 304
SYMBOL voltage -208 160 R0
WINDOW 3 10 105 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 0 -71 54 Left 2
SYMATTR Value PULSE(-50 50 1u 5n 5n 3u 10u)
SYMATTR InstName V1
SYMATTR SpiceLine Rser=10
SYMBOL diode -112 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value 1N4007
SYMBOL Misc\\EuropeanResistor 16 160 R0
SYMATTR InstName R1
SYMATTR Value 150
FLAG -80 320 0
FLAG -176 128 a
TEXT -208 320 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\3416e080d1e0_BLE_Input.asc
* Generated by LTspice 26.0.1 for Windows.
L1 N001 N002 0.6n
L3 N002 0 2.7n
C1 N001 VIN 7.5p
L2 N002 N003 1.5n
L4 N003 VOUT 2.2n
C2 VOUT 0 0.7p
V1 VIN 0 AC 1
.ac dec 100 100Meg 10G
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1072 680
WIRE 96 128 64 128
WIRE 144 128 96 128
WIRE 272 128 208 128
WIRE 400 128 352 128
WIRE 464 128 400 128
WIRE 592 128 544 128
WIRE 720 128 672 128
WIRE 816 128 720 128
WIRE 896 128 816 128
WIRE 64 160 64 128
WIRE 400 160 400 128
WIRE 720 160 720 128
WIRE 64 272 64 240
WIRE 400 272 400 240
WIRE 720 272 720 224
SYMBOL cap 208 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 7.5p
SYMBOL ind 448 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 1.5n
SYMBOL voltage 64 144 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL ind 256 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 0.6n
SYMBOL cap 704 160 R0
SYMATTR InstName C2
SYMATTR Value 0.7p
SYMBOL ind 384 144 R0
SYMATTR InstName L3
SYMATTR Value 2.7n
SYMBOL ind 576 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L4
SYMATTR Value 2.2n
FLAG 64 272 0
FLAG 400 272 0
FLAG 720 272 0
FLAG 816 128 VOUT
FLAG 96 128 VIN
TEXT 30 296 Left 2 !.ac dec 100 100Meg 10G
* Z:\home\khalils\Downloads\files\data\raw_asc\27eaeb3aefff_Diode-trr-4.asc
* Generated by LTspice 26.0.1 for Windows.
R1 b 0 150
V1 a 0 PULSE(-200 200 1u 5n 5n 3u 20u) Rser=10
D1 a b RRE07VSM6S
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 10u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 128 -208 128
WIRE -112 128 -176 128
WIRE 16 128 -48 128
WIRE 32 128 16 128
WIRE -208 176 -208 128
WIRE 32 176 32 128
WIRE -208 304 -208 256
WIRE -80 304 -208 304
WIRE 32 304 32 256
WIRE 32 304 -80 304
WIRE -80 320 -80 304
SYMBOL voltage -208 160 R0
WINDOW 3 10 105 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 0 -71 54 Left 2
SYMATTR Value PULSE(-200 200 1u 5n 5n 3u 20u)
SYMATTR InstName V1
SYMATTR SpiceLine Rser=10
SYMBOL Misc\\EuropeanResistor 16 160 R0
SYMATTR InstName R1
SYMATTR Value 150
SYMBOL diode -112 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RRE07VSM6S
FLAG -80 320 0
FLAG -176 128 a
FLAG 16 128 b
TEXT -208 320 Left 2 !.tran 10u
* Z:\home\khalils\Downloads\files\data\raw_asc\9a33e9b6d45c_AD8554.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8554.asy)
R2 OUT N001 10K
V1 +V 0 5
Vin IN 0 SINE(0 1 10K)
XU1 IN N001 +V -V OUT AD8554 ;pnba In+)In-)V+)V-)OUT
V2 -V 0 -5
R1 N001 0 10K
Rload OUT 0 10K
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 336 -1120 320 -1120
WIRE 432 -1120 416 -1120
WIRE 448 -1120 432 -1120
WIRE 544 -1120 528 -1120
WIRE 80 -1024 80 -1040
WIRE 176 -1024 176 -1040
WIRE 432 -1008 432 -1120
WIRE 448 -1008 432 -1008
WIRE 544 -992 544 -1120
WIRE 544 -992 512 -992
WIRE 656 -992 544 -992
WIRE 448 -976 336 -976
WIRE 656 -976 656 -992
WIRE 336 -960 336 -976
WIRE 80 -928 80 -944
WIRE 176 -928 176 -944
WIRE 656 -880 656 -896
WIRE 336 -864 336 -880
SYMBOL voltage 176 -1040 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -5
SYMBOL voltage 80 -1040 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 640 -992 R0
SYMATTR InstName Rload
SYMATTR Value 10K
SYMBOL Opamps\\AD8554 480 -1056 R0
SYMATTR InstName U1
SYMBOL res 432 -1136 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage 336 -976 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL res 544 -1136 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
FLAG 80 -1040 +V
FLAG 80 -928 0
FLAG 336 -864 0
FLAG 656 -992 OUT
FLAG 336 -976 IN
FLAG 480 -1024 +V
FLAG 176 -1040 -V
FLAG 480 -960 -V
FLAG 320 -1120 0
FLAG 656 -880 0
FLAG 176 -928 0
TEXT 592 -840 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\46fd58aa0614_ADR5041.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\ADR5041.asy)
Rbias IN OUT 1.24k
XU1 OUT 0 ADR5041 ;pnba 1)2
Vin IN 0 3
Rload OUT 0 10k
.dc TEMP -40 125 .1
.lib ADR5041.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 960
WIRE 32 64 -80 64
WIRE 208 64 112 64
WIRE 464 64 208 64
WIRE -80 112 -80 64
WIRE 208 112 208 64
WIRE 464 112 464 64
WIRE -80 224 -80 192
WIRE 208 224 208 176
WIRE 208 224 -80 224
WIRE 464 224 464 192
WIRE 464 224 208 224
WIRE -80 256 -80 224
SYMBOL res 16 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName Rbias
SYMATTR Value 1.24k
SYMBOL res 448 96 R0
SYMATTR InstName Rload
SYMATTR Value 10k
SYMBOL voltage -80 96 R0
WINDOW 3 36 62 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 30 32 Left 2
SYMATTR Value 3
SYMATTR InstName Vin
SYMBOL ADR5041 208 144 R0
SYMATTR InstName U1
FLAG -80 64 IN
FLAG -80 256 0
FLAG 464 64 OUT
TEXT -88 -32 Left 2 !.dc TEMP -40 125 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\AD8572.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\AD8572.asy)
V2 -V 0 -2.5
R2 OUT N001 10K
Vin IN 0 SINE(0 1 10K)
R1 N001 0 10K
Rload OUT 0 10K
V1 +V 0 2.5
XU1 IN N001 +V -V OUT AD8572 ;pnba In+)In-)V+)V-)OUT
.tran 1m
.lib ADI.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 432 -1232 416 -1232
WIRE 528 -1232 512 -1232
WIRE 544 -1232 528 -1232
WIRE 640 -1232 624 -1232
WIRE 160 -1136 160 -1152
WIRE 272 -1136 272 -1152
WIRE 528 -1120 528 -1232
WIRE 544 -1120 528 -1120
WIRE 640 -1104 640 -1232
WIRE 640 -1104 608 -1104
WIRE 752 -1104 640 -1104
WIRE 544 -1088 432 -1088
WIRE 752 -1088 752 -1104
WIRE 432 -1072 432 -1088
WIRE 160 -1040 160 -1056
WIRE 272 -1040 272 -1056
WIRE 752 -992 752 -1008
WIRE 432 -976 432 -992
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(0 1 10K)
SYMBOL voltage 272 -1152 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL Opamps\\AD8572 576 -1168 R0
SYMATTR InstName U1
SYMBOL voltage 160 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL res 640 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMBOL res 528 -1248 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL res 736 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10K
FLAG 432 -976 0
FLAG 752 -1104 OUT
FLAG 432 -1088 IN
FLAG 576 -1136 +V
FLAG 576 -1072 -V
FLAG 416 -1232 0
FLAG 752 -992 0
FLAG 160 -1152 +V
FLAG 160 -1040 0
FLAG 272 -1152 -V
FLAG 272 -1040 0
TEXT 696 -928 Left 2 !.tran 1m
* Z:\home\khalils\Downloads\files\data\raw_asc\822a8fe1bf42_SI8424DB_test.asc
* Generated by LTspice 26.0.1 for Windows.
* Ctrl-Right-Mouse-Click \non the Mosfet.\nChange Prefix:MN\nto Prefix:X
V2 N002 0 1
V1 N001 0 5
XM1 N001 N002 0 Si8424DB ;pnba D)G)S
.dc V1 0 5 0.01 V2 0.7 1 0.1
.include si8424db.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 288 -16 128 -16
WIRE 128 16 128 -16
WIRE 128 128 128 96
WIRE 288 128 288 -16
WIRE 240 208 128 208
WIRE 128 240 128 208
WIRE 288 272 288 224
WIRE 128 352 128 320
SYMBOL voltage 128 224 R0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL voltage 128 0 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL nmos 240 128 R0
SYMATTR InstName M1
SYMATTR Value Si8424DB
SYMATTR Prefix X
FLAG 128 128 0
FLAG 128 352 0
FLAG 288 272 0
TEXT 72 -56 Left 0 !.dc V1 0 5 0.01 V2 0.7 1 0.1
TEXT 80 -104 Left 0 !.include si8424db.lib
TEXT 344 -16 Left 0 ;Ctrl-Right-Mouse-Click \non the Mosfet.\nChange Prefix:MN\nto Prefix:X
* Z:\home\khalils\Downloads\files\data\raw_asc\fa68d6b95b13_PNP-transistor-biasing.asc
* Generated by LTspice 26.0.1 for Windows.
* E
* B
* C
* PNP Transistor biasing
R1 N003 0 1
R3 N002 0 11.2k
V1 N001 0 12
Q1 N003 N002 N001 0 2N2907
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.tran 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 -64 -16 -64
WIRE -16 -32 -16 -64
WIRE 192 16 192 -64
WIRE 272 64 256 64
WIRE 400 64 352 64
WIRE 400 112 400 64
WIRE 192 128 192 112
WIRE 192 288 192 208
SYMBOL voltage -16 -48 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL pnp 256 112 R180
SYMATTR InstName Q1
SYMATTR Value 2N2907
SYMBOL res 256 80 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R3
SYMATTR Value 11.2k
SYMBOL res 176 112 R0
SYMATTR InstName R1
SYMATTR Value 1
FLAG 400 112 0
FLAG 192 288 0
FLAG -16 48 0
TEXT 40 152 Right 2 !.tran 1
TEXT 160 8 Right 2 ;E
TEXT 264 88 Right 2 ;B
TEXT 168 112 Right 2 ;C
TEXT 104 -120 Left 2 ;PNP Transistor biasing
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP150-1.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP150-1.8.asy)
Rload OUT 0 18
C1 OUT 0 1
XU1 IN 0 IN MP_01 OUT ADP150-x.x T=.6Meg ;pnba Vin)GND)EN))Vout
V1 IN 0 5
.tran 500u startup
.lib ADP150-x.x.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2808 1464
WIRE 1824 880 1696 880
WIRE 1984 880 1824 880
WIRE 1696 896 1696 880
WIRE 1984 896 1984 880
WIRE 1696 992 1696 976
WIRE 1824 1024 1824 880
WIRE 1856 1024 1824 1024
WIRE 2160 1024 2112 1024
WIRE 2256 1024 2160 1024
WIRE 2160 1040 2160 1024
WIRE 2256 1040 2256 1024
WIRE 2160 1136 2160 1104
WIRE 2256 1136 2256 1120
WIRE 1984 1168 1984 1152
SYMBOL res 2240 1024 R0
SYMATTR InstName Rload
SYMATTR Value 18
SYMBOL cap 2144 1040 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL PowerProducts\\ADP150-1.8 1984 1024 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1696 880 R0
SYMATTR InstName V1
SYMATTR Value 5
FLAG 2256 1024 OUT
FLAG 2256 1136 0
FLAG 1696 992 0
FLAG 1696 880 IN
FLAG 1984 1168 0
FLAG 2160 1136 0
TEXT 2144 1200 Left 2 !.tran 500u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP124-2.8.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP124-2.8.asy)
XU1 OUT MP_01 OUT 0 IN MP_02 MP_03 IN ADP124 K=43478 ;pnba Vout))Sense)GND)En)))Vin
V1 IN 0 5.5
C2 OUT 0 1
C1 IN 0 1
Rload OUT 0 100
.tran 10m startup
.lib ADP124.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE 80 96 0 96
WIRE 128 96 80 96
WIRE 160 96 128 96
WIRE 384 96 352 96
WIRE 432 96 384 96
WIRE 512 96 432 96
WIRE 0 112 0 96
WIRE 80 112 80 96
WIRE 432 112 432 96
WIRE 512 112 512 96
WIRE 0 208 0 192
WIRE 80 208 80 176
WIRE 128 208 128 96
WIRE 160 208 128 208
WIRE 384 208 384 96
WIRE 384 208 352 208
WIRE 432 208 432 176
WIRE 512 208 512 192
WIRE 256 272 256 256
SYMBOL res 496 96 R0
SYMATTR InstName Rload
SYMATTR Value 100
SYMBOL voltage 0 96 R0
WINDOW 123 24 130 Left 2
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5.5
SYMBOL cap 416 112 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 64 112 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL ADP124-2.8 256 208 R0
SYMATTR InstName U1
FLAG 0 208 0
FLAG 256 272 0
FLAG 432 208 0
FLAG 512 208 0
FLAG 512 96 OUT
FLAG 0 96 IN
FLAG 80 208 0
TEXT 0 272 Left 2 !.tran 10m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3414.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3414.asy)
C2 N004 0 470p
R3 N007 0 294K
L1 N003 OUT .47
R6 N008 0 75K
C1 OUT 0 22
R7 IN N002 2.2Meg
R1 OUT N006 392K
R5 IN N001 10K
Rload OUT 0 1
XU1 N007 N008 0 N003 0 IN IN N001 N006 N005 N002 LTC3414 ;pnba Rt)Mode)SGND)SW)PGND)PVin)SVin)Pgood)FB)Ith)Run/SS
V1 IN 0 5
R4 N005 N004 13K
C3 N002 0 1000p
R2 N006 N008 110K
.tran 1m startup
.lib LTC3414.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2372 1972
WIRE 1488 1152 1360 1152
WIRE 1616 1152 1488 1152
WIRE 1712 1152 1616 1152
WIRE 1824 1152 1712 1152
WIRE 1488 1168 1488 1152
WIRE 1616 1168 1616 1152
WIRE 1360 1184 1360 1152
WIRE 1616 1264 1616 1248
WIRE 1712 1264 1712 1152
WIRE 1824 1264 1824 1152
WIRE 1360 1296 1360 1264
WIRE 1408 1344 1392 1344
WIRE 1488 1344 1488 1248
WIRE 1488 1344 1472 1344
WIRE 1552 1344 1488 1344
WIRE 1888 1344 1872 1344
WIRE 2000 1344 1968 1344
WIRE 2112 1344 2000 1344
WIRE 2208 1344 2112 1344
WIRE 2000 1360 2000 1344
WIRE 2208 1360 2208 1344
WIRE 2112 1376 2112 1344
WIRE 1376 1456 1360 1456
WIRE 1456 1456 1440 1456
WIRE 1552 1456 1536 1456
WIRE 2000 1456 2000 1440
WIRE 2000 1456 1872 1456
WIRE 2112 1456 2112 1440
WIRE 2208 1456 2208 1440
WIRE 2000 1472 2000 1456
WIRE 1408 1568 1376 1568
WIRE 1552 1568 1488 1568
WIRE 2000 1568 2000 1552
WIRE 2000 1568 1872 1568
WIRE 2000 1584 2000 1568
WIRE 1648 1680 1648 1648
WIRE 1776 1680 1776 1648
WIRE 2000 1680 2000 1664
SYMBOL PowerProducts\\LTC3414 1712 1456 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1360 1168 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 1440 1440 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 470p
SYMBOL ind 1872 1360 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value .47
SYMBOL res 1504 1552 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 294K
SYMBOL res 1984 1568 R0
SYMATTR InstName R6
SYMATTR Value 75K
SYMBOL RES 1984 1344 R0
SYMATTR InstName R1
SYMATTR Value 392K
SYMBOL cap 1472 1328 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1000p
SYMBOL res 1984 1456 R0
SYMATTR InstName R2
SYMATTR Value 110K
SYMBOL res 1600 1152 R0
SYMATTR InstName R5
SYMATTR Value 10K
SYMBOL res 2192 1344 R0
SYMATTR InstName Rload
SYMATTR Value 1
SYMBOL cap 2096 1376 R0
SYMATTR InstName C1
SYMATTR Value 22
SYMBOL res 1472 1152 R0
SYMATTR InstName R7
SYMATTR Value 2.2Meg
SYMBOL res 1552 1440 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 13K
FLAG 1776 1680 0
FLAG 1648 1680 0
FLAG 1360 1296 0
FLAG 1376 1568 0
FLAG 2208 1456 0
FLAG 2000 1680 0
FLAG 2112 1456 0
FLAG 1360 1456 0
FLAG 1392 1344 0
FLAG 2208 1344 OUT
FLAG 1360 1152 IN
TEXT 2112 1560 Left 2 !.tran 1m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\2edadce07876_MAX40263.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\MAX40263.asy)
Vin IN 0 SINE(1.65 50m 10k)
V1 +V 0 3.3
Rload OUT 0 10k
XU1 IN OUT +V 0 OUT +V MAX40263 ;pnba In+)In-)V+)V-)OUT)SHDN
.tran 1m
.lib MAX40263.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1240 700
WIRE 720 -1216 512 -1216
WIRE 144 -1136 144 -1152
WIRE 512 -1120 512 -1216
WIRE 544 -1120 512 -1120
WIRE 720 -1104 720 -1216
WIRE 720 -1104 608 -1104
WIRE 784 -1104 720 -1104
WIRE 544 -1088 432 -1088
WIRE 784 -1088 784 -1104
WIRE 432 -1072 432 -1088
WIRE 560 -1056 560 -1072
WIRE 144 -1040 144 -1056
WIRE 784 -992 784 -1008
WIRE 432 -976 432 -992
SYMBOL res 768 -1104 R0
SYMATTR InstName Rload
SYMATTR Value 10k
SYMBOL MAX40263 576 -1088 R0
WINDOW 0 7 -76 Left 2
WINDOW 3 4 -53 Left 2
SYMATTR InstName U1
SYMBOL voltage 432 -1088 R0
WINDOW 123 24 146 Left 2
WINDOW 39 24 125 Left 2
SYMATTR InstName Vin
SYMATTR Value SINE(1.65 50m 10k)
SYMBOL voltage 144 -1152 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 3.3
FLAG 144 -1152 +V
FLAG 144 -1040 0
FLAG 432 -976 0
FLAG 784 -1104 OUT
FLAG 432 -1088 IN
FLAG 560 -1136 +V
FLAG 784 -992 0
FLAG 592 -1072 +V
FLAG 560 -1056 0
TEXT 768 -936 Left 2 !.tran 1m