* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5055.asc
* Generated by LTspice 26.0.1 for Windows.
* Please read the following notes carefully, as the model presents different user interface from\nthe real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) The sequence control on each channel is not modeled. \n \n(4) The following parameters can be defined, by right-clicking the symbol of ADP5055.If any value \nof these parameters are set beyond the scope discribed in the datasheet, the resulting simulation\noutcomes are not meaningful.\n \nVref1, Vref2 and Vref3: set the reference voltage of channal1, channel2 and channel3 respectively\n \nFT1, FT2 and FT3: set the Fast Enhanced Transient Mode for channal1, channel2 and channel3 respectively \n0 for Fast Enhanced Transient Mode disabled\n1 for 1.5% window with 3x Gm \n2 for 1.5% window with 5x Gm\n3 for 2.5% window with 5x Gm
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5055.asy)
R3 OUT2 N014 6.67k
R10 N007 N006 22.6k
R16 N019 N018 40.2k
C3 OUT2 0 470 Rser=6m
R9 N003 0 402k
R13 N009 0 402k
R14 N013 N012 22.6k
R11 OUT1 N002 100K
R5 OUT3 N020 15k
C5 OUT3 0 47 x3 Rser=6m
R4 N014 0 10k
V1 IN 0 13.2
C8 N006 0 1.2n
R6 N020 0 10k
Rload1 OUT1 0 1
C6 0 N001 4.7
L3 N017 OUT3 2.2 Rser=86m
L2 N011 OUT2 .8 Rser=10m
L1 N005 OUT1 .8 Rser=10m
R8 N022 0 23.7k
XU1 0 N022 N003 N008 N007 N021 IN 0 N001 IN IN N004 N016 0 N017 IN N010 IN N015 N020 N019 N002 IN N013 N014 N009 IN N011 N005 IN ADP5055 Vref1=.6 Vref2=.6 Vref3=.6 FT1=3 FT2=3 FT3=3 ;pnba Cfg1)Cfg2)Ramp1)FB1)Comp1)RT)EN1)Agnd)Vreg)Vbias)Mode/Sync)Bst1)Bst3)Pgnd)SW3)Pvin3)Bst2)EN3)Ramp3)FB3)Comp3)Pwrgd)EN2)Comp2)FB2)Ramp2)Pvin2)SW2)SW1)Pvin1
C2 N004 N005 .1
R15 N015 0 499k
R2 N008 0 10k
Rload2 OUT2 0 1
R12 N021 0 215K
C1 OUT1 0 470 Rser=6m
C7 N016 N017 .1
C4 N010 N011 .1
C9 N012 0 1.2n
C10 N018 0 2.7n
R1 OUT1 N008 6.67k
Rload3 OUT3 0 5
.tran 2.5m startup
.lib ADP5055.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2348 992
WIRE 0 -416 -224 -416
WIRE 160 -416 0 -416
WIRE 336 -416 160 -416
WIRE 496 -416 336 -416
WIRE -224 -400 -224 -416
WIRE 160 -400 160 -416
WIRE 336 -400 336 -416
WIRE 0 -352 0 -416
WIRE 16 -352 0 -352
WIRE 496 -352 496 -416
WIRE 496 -352 480 -352
WIRE -224 -304 -224 -320
WIRE -112 -256 -128 -256
WIRE 16 -256 -48 -256
WIRE 512 -256 480 -256
WIRE 688 -256 592 -256
WIRE -112 -160 -128 -160
WIRE 16 -160 -32 -160
WIRE 512 -160 480 -160
WIRE 512 -144 512 -160
WIRE 0 -64 0 -352
WIRE 16 -64 0 -64
WIRE 512 -64 512 -80
WIRE 512 -64 480 -64
WIRE 560 -64 512 -64
WIRE 688 -64 688 -256
WIRE 688 -64 640 -64
WIRE 896 -64 688 -64
WIRE 976 -64 896 -64
WIRE 896 -48 896 -64
WIRE 976 -48 976 -64
WIRE -192 32 -208 32
WIRE -112 32 -128 32
WIRE 16 32 -32 32
WIRE 688 32 688 16
WIRE 688 32 480 32
WIRE 768 32 688 32
WIRE 896 32 896 16
WIRE 896 32 848 32
WIRE 976 32 896 32
WIRE 976 48 976 32
WIRE -112 128 -128 128
WIRE 16 128 -32 128
WIRE 512 128 480 128
WIRE 512 144 512 128
WIRE 0 224 0 -64
WIRE 16 224 0 224
WIRE 512 224 512 208
WIRE 512 224 480 224
WIRE 560 224 512 224
WIRE 688 224 640 224
WIRE 896 224 688 224
WIRE 976 224 896 224
WIRE 896 240 896 224
WIRE 976 240 976 224
WIRE -192 320 -208 320
WIRE -112 320 -128 320
WIRE 16 320 -32 320
WIRE 688 320 688 304
WIRE 688 320 480 320
WIRE 768 320 688 320
WIRE 896 320 896 304
WIRE 896 320 848 320
WIRE 976 320 896 320
WIRE 976 336 976 320
WIRE -112 416 -128 416
WIRE 16 416 -32 416
WIRE 512 416 480 416
WIRE 512 432 512 416
WIRE 0 512 0 224
WIRE 16 512 0 512
WIRE 512 512 512 496
WIRE 512 512 480 512
WIRE 560 512 512 512
WIRE 688 512 640 512
WIRE 896 512 688 512
WIRE 976 512 896 512
WIRE 896 528 896 512
WIRE 976 528 976 512
WIRE -176 608 -192 608
WIRE -96 608 -112 608
WIRE 16 608 -16 608
WIRE 688 608 688 592
WIRE 688 608 480 608
WIRE 768 608 688 608
WIRE 896 608 896 592
WIRE 896 608 848 608
WIRE 976 608 896 608
WIRE 976 624 976 608
WIRE 0 704 0 512
WIRE 16 704 0 704
WIRE 496 704 480 704
WIRE -96 800 -112 800
WIRE 16 800 -16 800
WIRE 512 800 480 800
WIRE 608 800 592 800
WIRE 160 880 160 864
WIRE 336 880 336 864
SYMBOL res 0 816 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R12
SYMATTR Value 215K
SYMBOL ind 544 528 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L3
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=86m
SYMBOL ADP5055 256 224 R0
SYMATTR InstName U1
SYMBOL cap -112 -272 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 4.7
SYMBOL cap -112 592 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C10
SYMATTR Value 2.7n
SYMBOL res -16 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R10
SYMATTR Value 22.6k
SYMBOL voltage -224 -416 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 13.2
SYMBOL res 608 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R11
SYMATTR Value 100K
SYMBOL res 0 592 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R16
SYMATTR Value 40.2k
SYMBOL cap 880 -48 R0
SYMATTR InstName C1
SYMATTR Value 470
SYMATTR SpiceLine Rser=6m
SYMBOL cap 496 -144 R0
SYMATTR InstName C2
SYMATTR Value .1
SYMBOL res 752 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R2
SYMATTR Value 10k
SYMBOL res 672 496 R0
SYMATTR InstName R5
SYMATTR Value 15k
SYMBOL res 960 -64 R0
SYMATTR InstName Rload1
SYMATTR Value 1
SYMBOL res 752 336 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10k
SYMBOL cap 496 144 R0
SYMATTR InstName C4
SYMATTR Value .1
SYMBOL ind 544 -48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value .8
SYMATTR SpiceLine Rser=10m
SYMBOL res -16 -144 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R9
SYMATTR Value 402k
SYMBOL res 960 224 R0
SYMATTR InstName Rload2
SYMATTR Value 1
SYMBOL res -16 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 22.6k
SYMBOL cap 880 240 R0
SYMATTR InstName C3
SYMATTR Value 470
SYMATTR SpiceLine Rser=6m
SYMBOL cap 880 528 R0
WINDOW 123 24 84 Left 2
SYMATTR Value2 x3
SYMATTR InstName C5
SYMATTR Value 47
SYMATTR SpiceLine Rser=6m
SYMBOL res -16 144 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R13
SYMATTR Value 402k
SYMBOL cap -128 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C9
SYMATTR Value 1.2n
SYMBOL res 672 208 R0
SYMATTR InstName R3
SYMATTR Value 6.67k
SYMBOL cap 496 432 R0
SYMATTR InstName C7
SYMATTR Value .1
SYMBOL res 752 624 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 10k
SYMBOL cap -128 16 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C8
SYMATTR Value 1.2n
SYMBOL res 960 512 R0
SYMATTR InstName Rload3
SYMATTR Value 5
SYMBOL res 672 -80 R0
SYMATTR InstName R1
SYMATTR Value 6.67k
SYMBOL res 496 816 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R8
SYMATTR Value 23.7k
SYMBOL ind 544 240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value .8
SYMATTR SpiceLine Rser=10m
SYMBOL res -16 432 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R15
SYMATTR Value 499k
FLAG -224 -304 0
FLAG -224 -416 IN
FLAG 336 880 0
FLAG 160 880 0
FLAG 976 48 0
FLAG 976 -64 OUT1
FLAG -128 -256 0
FLAG -112 800 0
FLAG 976 624 0
FLAG 976 512 OUT3
FLAG 496 704 0
FLAG 608 800 0
FLAG -128 -160 0
FLAG -208 32 0
FLAG -128 128 0
FLAG -192 608 0
FLAG -208 320 0
FLAG -128 416 0
FLAG 976 336 0
FLAG 976 224 OUT2
TEXT 720 776 Left 2 !.tran 2.5m startup
TEXT 1088 -416 Left 2 ;Please read the following notes carefully, as the model presents different user interface from\nthe real part does.\n \n(1) All PMBus communication and memory address related functions and pins are not modeled. \n \n(2) Changes to all parameter values during the simulation running will not be in effect, unless the\nsimulation is stopped and restarted. This is different from the operation of the part, which will\n respond to the commanded changes while running. \n \n(3) The sequence control on each channel is not modeled. \n \n(4) The following parameters can be defined, by right-clicking the symbol of ADP5055.If any value \nof these parameters are set beyond the scope discribed in the datasheet, the resulting simulation\noutcomes are not meaningful.\n \nVref1, Vref2 and Vref3: set the reference voltage of channal1, channel2 and channel3 respectively\n \nFT1, FT2 and FT3: set the Fast Enhanced Transient Mode for channal1, channel2 and channel3 respectively \n0 for Fast Enhanced Transient Mode disabled\n1 for 1.5% window with 3x Gm \n2 for 1.5% window with 5x Gm\n3 for 2.5% window with 5x Gm