Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8083.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8083.asy)
R1 OUT N001 100k
C1 OUT 0 10 V=16 Irms=13.8 Rser=0.00468332 Lser=0 mfg="KEMET" pn="C1210C106K4RAC" type="X7R"
Rload OUT 0 24
R2 N001 0 9.09k
XU1 IN MP_01 IN NC_02 IN 0 0 MP_03 MP_04 NC_05 OUT OUT NC_06 MP_07 NC_08 N001 NC_09 N002 0 MP_10 OUT MP_11 MP_12 MP_13 MP_14 MP_15 MP_16 MP_17 0 LTM8083 ;pnba Vin))SVin)INTVcc)EN/UVLO)OVLO)TST2)))CTRL)ISP)ISN)ISMON))SS)FB)Vc)RT)SYNC))Vout))))))))GND
R3 N002 0 40.2k
V1 IN 0 20
.tran 1.2m startup
.lib LTM8083.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4.1
SHEET 1 2644 1404
WIRE -304 -16 -336 -16
WIRE -208 -16 -304 -16
WIRE -144 -16 -208 -16
WIRE 368 -16 288 -16
WIRE 464 -16 368 -16
WIRE 592 -16 464 -16
WIRE 656 -16 592 -16
WIRE 688 -16 656 -16
WIRE 464 0 464 -16
WIRE -336 32 -336 -16
WIRE 688 32 688 -16
WIRE 592 48 592 -16
WIRE -208 80 -208 -16
WIRE -144 80 -208 80
WIRE 320 80 288 80
WIRE 320 112 320 80
WIRE 464 112 464 80
WIRE 464 112 320 112
WIRE -336 144 -336 112
WIRE 464 144 464 112
WIRE 592 160 592 112
WIRE 688 160 688 112
WIRE -208 176 -208 80
WIRE -144 176 -208 176
WIRE 368 176 368 -16
WIRE 368 176 288 176
WIRE 464 256 464 224
WIRE -144 272 -208 272
WIRE 368 272 368 176
WIRE 368 272 288 272
WIRE -208 560 -208 272
WIRE -144 560 -208 560
WIRE -208 656 -208 560
WIRE -144 656 -208 656
WIRE 320 656 288 656
WIRE 432 656 400 656
WIRE -208 800 -208 656
WIRE 80 800 80 736
WIRE 80 800 -208 800
WIRE 80 832 80 800
SYMBOL res 304 640 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 37 64 VTop 2
SYMATTR InstName R3
SYMATTR Value 40.2k
SYMBOL res 672 16 R0
SYMATTR InstName Rload
SYMATTR Value 24
SYMBOL LTM8083 80 336 R0
SYMATTR InstName U1
SYMBOL cap 576 48 R0
WINDOW 0 24 10 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine V=16 Irms=13.8 Rser=0.00468332 Lser=0 mfg="KEMET" pn="C1210C106K4RAC" type="X7R"
SYMBOL res 448 -16 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 448 128 R0
SYMATTR InstName R2
SYMATTR Value 9.09k
SYMBOL voltage -336 16 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR Value 20
SYMATTR InstName V1
FLAG -336 144 0
FLAG 464 256 0
FLAG 432 656 0
FLAG 592 160 0
FLAG 688 160 0
FLAG 80 832 0
FLAG 656 -16 OUT
FLAG -304 -16 IN
TEXT 360 808 Left 2 !.tran 1.2m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT6005.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 2
V2 -V 0 -2
V3 IN 0 PULSE(-1 1 0 1u 1u 100m 200m)
XU1 IN OUT +V -V OUT LT6003 ;pnba IN+)IN-)VCC)VEE)OUT
.tran 1
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LT6005.asy)
.lib LTC5.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 756
WIRE 288 304 128 304
WIRE -256 368 -256 352
WIRE -160 368 -160 352
WIRE 192 368 192 352
WIRE 128 384 128 304
WIRE 160 384 128 384
WIRE 288 400 288 304
WIRE 288 400 224 400
WIRE 336 400 288 400
WIRE 160 416 -16 416
WIRE -16 432 -16 416
WIRE 192 448 192 432
WIRE -256 464 -256 448
WIRE -160 464 -160 448
WIRE -16 528 -16 512
FLAG -256 464 0
FLAG -160 464 0
FLAG -16 528 0
FLAG -16 416 IN
FLAG 336 400 OUT
FLAG 192 352 +V
FLAG -256 352 +V
FLAG -160 352 -V
FLAG 192 448 -V
SYMBOL voltage -256 352 R0
WINDOW 123 24 132 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 2
SYMBOL voltage -160 352 R0
SYMATTR InstName V2
SYMATTR Value -2
SYMBOL voltage -16 416 R0
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 1u 1u 100m 200m)
SYMBOL LT6005 192 400 R0
SYMATTR InstName U1
TEXT 408 472 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3672B-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3672B-2.asy)
Rload1 OUT1 0 3
V1 IN 0 3.6
XU1 N001 0 IN OUT1 IN OUT2 OUT3 IN LTC3672B-2 ;pnba SW)GND)EnAll)BuckOut)Vin1)LDO1)LDO2)Vin
C2 OUT2 0 1
C1 OUT1 0 4.7
L1 N001 OUT1 4.7
Rload2 OUT2 0 18.6
Rload3 OUT3 0 12
C3 OUT3 0 1
.tran 250u startup
.lib LTC3672B-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1108 740
WIRE 96 -16 -16 -16
WIRE 528 -16 96 -16
WIRE -16 0 -16 -16
WIRE 96 32 96 -16
WIRE 112 32 96 32
WIRE 416 32 400 32
WIRE 512 32 496 32
WIRE 576 32 512 32
WIRE 672 32 576 32
WIRE 576 48 576 32
WIRE 672 48 672 32
WIRE -16 96 -16 80
WIRE 96 128 96 32
WIRE 112 128 96 128
WIRE 512 128 512 32
WIRE 512 128 400 128
WIRE 576 144 576 112
WIRE 672 144 672 128
WIRE -160 224 -288 224
WIRE 112 224 -160 224
WIRE 528 224 528 -16
WIRE 528 224 400 224
WIRE -288 240 -288 224
WIRE -160 240 -160 224
WIRE 64 320 -64 320
WIRE 112 320 64 320
WIRE 416 320 400 320
WIRE -288 336 -288 320
WIRE -160 336 -160 304
WIRE -64 336 -64 320
WIRE 64 336 64 320
WIRE -64 432 -64 416
WIRE 64 432 64 400
SYMBOL voltage -16 -16 R0
SYMATTR InstName V1
SYMATTR Value 3.6
SYMBOL cap 48 336 R0
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL res -304 224 R0
SYMATTR InstName Rload2
SYMATTR Value 18.6
SYMBOL res 656 32 R0
SYMATTR InstName Rload1
SYMATTR Value 3
SYMBOL res -80 320 R0
SYMATTR InstName Rload3
SYMATTR Value 12
SYMBOL cap -176 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL PowerProducts\\LTC3672B-2 256 176 R0
SYMATTR InstName U1
SYMBOL cap 560 48 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMBOL ind 400 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 4.7
FLAG -16 96 0
FLAG -16 -16 IN
FLAG 672 144 0
FLAG 576 144 0
FLAG 672 32 OUT1
FLAG -288 336 0
FLAG -160 336 0
FLAG -288 224 OUT2
FLAG -64 432 0
FLAG 64 432 0
FLAG -64 320 OUT3
FLAG 416 320 0
TEXT 488 376 Left 2 !.tran 250u startup
* Z:\home\khalils\Downloads\files\data\raw_asc\7c138b4877f2_Draft3.asc
* Generated by LTspice 26.0.1 for Windows.
* CMOS Inverter
M2 Out IN 0 0 NMOS
V1 IN 0 V
V2 VDD 0 5V
M1 VDD IN Out VDD PMOS
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 240 96 240 48
WIRE 288 96 240 96
WIRE 288 144 288 96
WIRE 288 144 240 144
WIRE 192 176 128 176
WIRE 128 208 128 176
WIRE 128 208 16 208
WIRE 240 208 240 192
WIRE 368 208 240 208
WIRE 240 224 240 208
WIRE 128 304 128 208
WIRE 192 304 128 304
WIRE -352 320 -352 240
WIRE -240 320 -240 240
WIRE 240 416 240 320
IOPIN 16 208 In
IOPIN 368 208 Out
IOPIN 240 48 In
IOPIN -240 160 In
IOPIN -352 160 In
SYMBOL pmos4 192 96 R0
SYMATTR InstName M1
SYMBOL voltage -240 144 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 5V
SYMBOL voltage -352 144 R0
SYMATTR InstName V1
SYMBOL nmos 192 224 R0
SYMATTR InstName M2
FLAG 240 416 0
FLAG 16 208 IN
FLAG 368 208 Out
FLAG 240 48 VDD
FLAG -240 160 VDD
FLAG -352 160 IN
FLAG -352 320 0
FLAG -240 320 0
TEXT 32 64 Left 2 ;CMOS Inverter
* Z:\home\khalils\Downloads\files\data\raw_asc\2285bf0a8119_2055.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC2055.asy)
R2 N001 0 10K
XU1 N003 N001 N002 +V -V LTC2054 ;pnba IN+)IN-)OUT)VCC)VEE
V1 +V 0 2.5
R1 N002 N001 10K
V3 N003 0 SINE(0 1 1K)
V2 -V 0 -2.5
.tran 3m
.lib LTC2.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 896 680
WIRE -48 -16 -64 -16
WIRE 48 -16 32 -16
WIRE 112 -16 48 -16
WIRE 208 -16 192 -16
WIRE 112 64 112 48
WIRE 48 80 48 -16
WIRE 80 80 48 80
WIRE 208 96 208 -16
WIRE 208 96 144 96
WIRE -400 112 -400 80
WIRE -272 112 -272 80
WIRE 80 112 -16 112
WIRE -16 144 -16 112
WIRE 112 144 112 128
WIRE -400 240 -400 192
WIRE -272 240 -272 192
WIRE -16 256 -16 224
SYMBOL voltage -272 96 R0
SYMATTR InstName V1
SYMATTR Value 2.5
SYMBOL opamps\\LTC2055 112 96 R0
SYMATTR InstName U1
SYMBOL res 208 -32 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 10K
SYMBOL voltage -400 96 R0
SYMATTR InstName V2
SYMATTR Value -2.5
SYMBOL voltage -16 128 R0
SYMATTR InstName V3
SYMATTR Value SINE(0 1 1K)
SYMBOL res 48 -32 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 10K
FLAG -272 240 0
FLAG 112 48 +V
FLAG -272 80 +V
FLAG 112 144 -V
FLAG -400 240 0
FLAG -400 80 -V
FLAG -16 256 0
FLAG -64 -16 0
TEXT -192 296 Left 0 !.tran 3m
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8300.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8300.asy)
K1 L1 L2 1
R2 N003 0 40.2K
XU1 N003 0 N004 N002 IN LT8300 ;pnba EN/UVLO)GND)RFB)SW)Vin
D1 N001 OUT MBRS1100
V1 IN 0 60
R3 N002 N004 210K
R1 IN N003 1Meg
L2 0 N001 19 Rser=20m Cpar=.2p
Rload OUT 0 16.6
L1 IN N002 300 Rser=500m Cpar=1p
C1 OUT 0 4.7 V=6.3 Irms=0 Rser=0.003 Lser=0 mfg="TDK" pn="C2012X5ROJ475M" type="X5R"
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT8300.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 884 680
WIRE -16 16 -112 16
WIRE 416 16 -16 16
WIRE 560 16 464 16
WIRE 688 16 624 16
WIRE 784 16 688 16
WIRE -112 32 -112 16
WIRE 416 32 416 16
WIRE 464 32 464 16
WIRE 688 32 688 16
WIRE 784 32 784 16
WIRE -112 128 -112 112
WIRE 464 128 464 112
WIRE 688 128 688 96
WIRE 784 128 784 112
WIRE -16 144 -16 16
WIRE 96 144 -16 144
WIRE 416 144 416 112
WIRE 416 144 320 144
WIRE -16 176 -16 144
WIRE 416 176 416 144
WIRE -16 272 -16 256
WIRE 96 272 -16 272
WIRE 416 272 416 256
WIRE 416 272 320 272
WIRE -16 288 -16 272
WIRE 208 336 208 320
WIRE -16 384 -16 368
SYMBOL res -32 272 R0
SYMATTR InstName R2
SYMATTR Value 40.2K
SYMBOL res -32 160 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL voltage -112 16 R0
SYMATTR InstName V1
SYMATTR Value 60
SYMBOL ind2 480 128 R180
WINDOW 0 -4 72 Right 2
WINDOW 3 -1 33 Right 2
SYMATTR InstName L2
SYMATTR Value 19
SYMATTR Type ind
SYMATTR SpiceLine Rser=20m Cpar=.2p
SYMBOL schottky 560 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS1100
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL res 768 16 R0
SYMATTR InstName Rload
SYMATTR Value 16.6
SYMBOL cap 672 32 R0
SYMATTR InstName C1
SYMATTR Value 4.7
SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.003 Lser=0 mfg="TDK" pn="C2012X5ROJ475M" type="X5R"
SYMBOL res 400 160 R0
SYMATTR InstName R3
SYMATTR Value 210K
SYMBOL PowerProducts\\LT8300 208 208 R0
SYMATTR InstName U1
SYMBOL ind2 400 16 R0
WINDOW 0 0 39 Right 2
WINDOW 3 0 77 Right 2
SYMATTR InstName L1
SYMATTR Value 300
SYMATTR Type ind
SYMATTR SpiceLine Rser=500m Cpar=1p
FLAG 208 336 0
FLAG -112 128 0
FLAG -16 384 0
FLAG -112 16 IN
FLAG 464 128 0
FLAG 688 128 0
FLAG 784 128 0
FLAG 784 16 OUT
TEXT 440 16 Bottom 2 !K1 L1 L2 1
TEXT 552 376 Left 2 !.tran 3m startup
* Z:\tmp\asc_dec_bjh7r6w2\166bab3509f7_01_CrystalModel_10MHz_0Z_load_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
Ls N002 N003 1.03450713
Cs N003 N004 .244853759f
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 32 176 0 176
WIRE 160 176 112 176
WIRE 304 176 240 176
WIRE 416 176 368 176
WIRE 0 272 0 176
WIRE 160 272 0 272
WIRE 416 272 416 176
WIRE 416 272 224 272
WIRE 0 288 0 272
WIRE 416 288 416 272
WIRE 0 384 0 368
WIRE 416 384 416 368
SYMBOL ind 144 192 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName Ls
SYMATTR Value 1.03450713
SYMBOL cap 304 192 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName Cs
SYMATTR Value .244853759f
FLAG 0 384 0
FLAG 416 384 0
* Z:\tmp\asc_dec_bjh7r6w2\129648a0c45e_AFE_bandpass_v3_dec1.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N002 IN 309
V2 -5V 0 -5
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1364 680
WIRE 432 -64 368 -64
WIRE 592 -64 512 -64
WIRE 368 -16 368 -64
WIRE 272 112 240 112
WIRE 464 112 352 112
WIRE 592 112 464 112
WIRE 464 160 464 112
WIRE 464 272 464 240
WIRE 592 272 464 272
SYMBOL res 368 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 309
SYMBOL voltage 880 -352 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value -5
FLAG 368 -16 0
FLAG 768 -256 0
FLAG 880 -256 0
FLAG 768 -336 5V
FLAG 880 -336 -5V
FLAG 240 112 IN
* Z:\home\khalils\Downloads\files\data\raw_asc\1b6e83d7e59b_transmission_gate.asc
* Generated by LTspice 26.0.1 for Windows.
M1 Vin n_in Vout 0 n_65 l=65n w=1u
M2 Vout p_in Vin VDD p_65 l=65n w=2u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.include 65nm_bulk.txt
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 924
WIRE 64 368 64 288
WIRE 48 416 16 416
WIRE 176 416 144 416
WIRE 16 528 16 416
WIRE 16 528 -16 528
WIRE 176 528 176 416
WIRE 208 528 176 528
WIRE 16 640 16 528
WIRE 48 640 16 640
WIRE 96 640 96 624
WIRE 176 640 176 528
WIRE 176 640 144 640
WIRE 128 752 128 688
IOPIN 128 752 In
IOPIN 64 288 In
IOPIN -16 528 In
IOPIN 208 528 Out
SYMBOL pmos4 144 368 R90
WINDOW 123 56 50 Left 2
SYMATTR Value2 l=65n w=2u
SYMATTR InstName M2
SYMATTR Value p_65
SYMBOL nmos4 48 688 R270
WINDOW 123 56 94 Left 2
SYMATTR Value2 l=65n w=1u
SYMATTR InstName M1
SYMATTR Value n_65
FLAG 96 624 0
FLAG 96 416 VDD
FLAG 128 752 n_in
FLAG 64 288 p_in
FLAG -16 528 Vin
FLAG 208 528 Vout
TEXT -224 88 Left 2 !.include 65nm_bulk.txt
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC1440.asc
* Generated by LTspice 26.0.1 for Windows.
* Power 2.9V Vcc Threshold Detector
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Comparators\LTC1440.asy)
V1 Vcc 0 PWL(0 0 1m 3.3)
R1 N002 0 1.13Meg
XU1 N002 N001 Vcc 0 OUT 0 N001 N001 LTC1440 ;pnba In+)In-)V+)V-)OUT)GND)REF)HYST
R2 Vcc N002 1.65Meg
.tran 1m
.lib LTC.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 800
WIRE 128 176 -144 176
WIRE 368 176 128 176
WIRE -144 192 -144 176
WIRE 128 192 128 176
WIRE 368 208 368 176
WIRE 304 256 272 256
WIRE 480 272 432 272
WIRE -144 288 -144 272
WIRE 128 288 128 272
WIRE 304 288 128 288
WIRE 128 304 128 288
WIRE 272 320 272 256
WIRE 304 320 272 320
WIRE 272 352 272 320
WIRE 304 352 272 352
WIRE 128 400 128 384
WIRE 336 432 336 400
WIRE 400 432 400 400
SYMBOL res 112 288 R0
SYMATTR InstName R1
SYMATTR Value 1.13Meg
SYMBOL Comparators\\LTC1440 368 208 R0
SYMATTR InstName U1
SYMBOL res 112 176 R0
SYMATTR InstName R2
SYMATTR Value 1.65Meg
SYMBOL voltage -144 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1m 3.3)
FLAG -144 288 0
FLAG 400 432 0
FLAG 336 432 0
FLAG 128 400 0
FLAG 480 272 OUT
FLAG -144 176 Vcc
TEXT 464 456 Left 2 !.tran 1m
TEXT 256 160 Bottom 2 ;Power 2.9V Vcc Threshold Detector
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC4123.asc
* Generated by LTspice 26.0.1 for Windows.
* Notes:\n1. To simulate rectifier and input power control, the user needs to construct\n a proper AC source to connect to ACIN pin.\n2. The model supports the charge voltage temperature compensation feature.\n However, the user needs to specify ".temp" for the certain die temperature.\n3. Variables Tzn_air and Tchg, are introduced to reduce the simulation time\n artificially. Please make sure to have Tchg>Tzn_air for meaningful results.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC4123.asy)
XU1 NC_01 N002 NC_02 N003 N001 0 LTC4123 Tzn_air=2 Tchg=100 ;pnba ACIN)VCC)_CHRG)PROG)BAT)GND
C1 N001 0 10 Rser=5m
V1 N002 0 5
R1 N003 0 1K
CBAT N001 0 .1
.tran 100 startup
.lib LTC4123.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1744 680
WIRE 496 112 352 112
WIRE 592 112 496 112
WIRE 496 128 496 112
WIRE 592 128 592 112
WIRE 96 208 0 208
WIRE 432 208 352 208
WIRE 496 208 496 192
WIRE 592 208 592 192
WIRE 0 224 0 208
WIRE 432 224 432 208
WIRE 368 304 352 304
WIRE 0 320 0 304
WIRE 432 320 432 304
SYMBOL res 416 208 R0
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL VOLTAGE 0 208 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 480 128 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR SpiceLine Rser=5m
SYMBOL cap 576 128 R0
SYMATTR InstName BAT
SYMATTR Value .1
SYMBOL PowerProducts\\LTC4123 224 208 R0
SYMATTR InstName U1
SYMATTR Description Low Power Wireless Charger for Hearing Aids
FLAG 0 320 0
FLAG 432 320 0
FLAG 368 304 0
FLAG 496 208 0
FLAG 592 208 0
TEXT 480 320 Left 2 !.tran 100 startup
TEXT -40 400 Left 1 ;Notes:\n1. To simulate rectifier and input power control, the user needs to construct\n     a proper AC source to connect to ACIN pin.\n2. The model supports the charge voltage temperature compensation feature.\n    However, the user needs to specify ".temp" for the certain die temperature.\n3. Variables Tzn_air and Tchg, are introduced to reduce the simulation time\n    artificially. Please make sure to have Tchg>Tzn_air for meaningful results.
* Z:\home\khalils\Downloads\files\data\raw_asc\1c8384e21e7c_Diferencial.asc
* Generated by LTspice 26.0.1 for Windows.
XU1 N003 N001 Vcc Vss Vo1 LM324 ;pnba In+)In-)V+)V-)OUT
R1 Vo1 N001 10K tol=1 pwr=0.1
XU2 N004 N002 Vcc Vss Vo2 LM324 ;pnba In+)In-)V+)V-)OUT
Vcc Vcc 0 10
R5 N002 N001 10K tol=1 pwr=0.1
Vss Vss 0 -10
V2 N004 0 1
R4 Vo2 N002 10K tol=1 pwr=0.1
R3 N002 Vo1 10K tol=1 pwr=0.1
R2 N001 0 10K tol=1 pwr=0.1
V1 N003 0 1
.include C:\Users\Administrador\Downloads\Componentes_Spice\LM324.ti.lib
.tran 5ms
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 112 -48 -16 -48
WIRE 336 -48 192 -48
WIRE -16 48 -16 -48
WIRE 64 48 -16 48
WIRE 176 48 144 48
WIRE 336 80 336 -48
WIRE 416 80 336 80
WIRE 528 80 496 80
WIRE -112 144 -144 144
WIRE -16 144 -16 48
WIRE -16 144 -32 144
WIRE 48 144 -16 144
WIRE -144 160 -144 144
WIRE 176 160 176 48
WIRE 176 160 112 160
WIRE 208 160 176 160
WIRE 336 160 336 80
WIRE 336 160 288 160
WIRE 384 160 336 160
WIRE 48 176 0 176
WIRE 528 176 528 80
WIRE 528 176 448 176
WIRE 560 176 528 176
WIRE 0 192 0 176
WIRE 384 192 336 192
WIRE 336 208 336 192
SYMBOL voltage 0 176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1
SYMBOL OpAmps\\opamp2 416 112 R0
SYMATTR InstName U2
SYMATTR Value LM324
SYMBOL OpAmps\\opamp2 80 96 R0
SYMATTR InstName U1
SYMATTR Value LM324
SYMBOL voltage 336 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
SYMBOL res 208 -64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 10K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL res 160 32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL voltage -416 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vss
SYMATTR Value -10
SYMBOL voltage -416 0 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vcc
SYMATTR Value 10
SYMBOL res 512 64 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL res 304 144 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMATTR SpiceLine tol=1 pwr=0.1
SYMBOL res -16 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10K
SYMATTR SpiceLine tol=1 pwr=0.1
FLAG -144 160 0
FLAG 560 176 Vo2
FLAG 560 224 0
FLAG 336 288 0
FLAG 0 272 0
FLAG -416 96 0
FLAG -416 256 0
FLAG 80 128 Vcc
FLAG 416 144 Vcc
FLAG -416 16 Vcc
FLAG -416 176 Vss
FLAG 80 192 Vss
FLAG 416 208 Vss
FLAG 176 160 Vo1
TEXT -520 -200 Left 2 !.include C:\\Users\\Administrador\\Downloads\\Componentes_Spice\\LM324.ti.lib
TEXT 368 -200 Left 2 !.tran 5ms
* Z:\home\khalils\Downloads\files\data\raw_asc\cab8a9ba309f_TransmissionLineInverter.asc
* Generated by LTspice 26.0.1 for Windows.
* This example schematic is supplied for informational/educational purposes only.
* This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax. The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors. A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements. One for the normal(differential) mode and\nthe other for the common mode. Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world. These modes\nwith have different propagation speeds and impedances. If both modes\nare modeled, then you can simulate a transmission line inverter.
T1 IN 0 0 OUT Td=50n Z0=50
V1 IN 0 PULSE(0 1 0 1n 1n 10n) Rser=50
T2 0 0 OUT 0 Td=30n Z0=150
.tran 0 500n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1272 680
WIRE 128 192 -368 192
WIRE 320 192 224 192
WIRE -368 208 -368 192
WIRE 128 224 64 224
WIRE 288 224 224 224
WIRE 64 272 64 224
WIRE 64 272 16 272
WIRE 288 272 288 224
WIRE 336 272 288 272
WIRE -368 304 -368 288
WIRE 64 304 64 272
WIRE 128 304 64 304
WIRE 288 304 288 272
WIRE 288 304 224 304
WIRE 128 336 64 336
WIRE 288 336 224 336
WIRE 64 368 64 336
WIRE 288 368 288 336
SYMBOL tline 176 208 R0
WINDOW 0 2 -19 Bottom 2
WINDOW 3 3 20 Top 2
SYMATTR InstName T1
SYMBOL voltage -368 192 R0
WINDOW 123 0 0 Left 2
WINDOW 39 40 56 Left 2
SYMATTR SpiceLine Rser=50
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 1n 1n 10n)
SYMBOL tline 176 320 R0
WINDOW 0 -1 -21 Bottom 2
WINDOW 3 0 21 Top 2
SYMATTR InstName T2
SYMATTR Value Td=30n Z0=150
FLAG 64 368 0
FLAG 288 368 0
FLAG -368 304 0
FLAG 16 272 0
FLAG 320 192 0
FLAG -368 192 IN
FLAG 336 272 OUT
TEXT 376 368 Left 2 !.tran 0 500n 0 1n
TEXT 0 408 Top 1 ;This example schematic is supplied for informational/educational purposes only.
TEXT -376 -200 Left 2 ;This examples illustrates the fundamental difference between a SPICE\ntransmission line element and a length of coax.  The SPICE transmission\nline element supports a single transmission line mode whereas a cable\nwill have any many modes as it has independent conductors.  A piece of\ncoax has two conductors, a central conductor and an outer shield, giving\nrise to two modes.\n \nTo model both modes of a length of coax, you will need two SPICE\ntransmission line elements.  One for the normal(differential) mode and\nthe other for the common mode.  Below, T1 is the normal mode and T2 is\nthe mode between the shield and the rest of the world.  These modes\nwith have different propagation speeds and impedances.  If both modes\nare modeled, then you can simulate a transmission line inverter.
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP172-1.5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP172-1.5.asy)
RLOAD OUT 0 5
V1 IN 0 3.6
XU1 OUT IN IN 0 ADP172-1.5 ;pnba Vout)Vin)En)GND
C1 OUT 0 1
.tran 2m startup
.lib ADP172-1.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 80 -48 80
WIRE 48 80 -32 80
WIRE 64 80 48 80
WIRE 304 80 256 80
WIRE 336 80 304 80
WIRE 384 80 336 80
WIRE -48 96 -48 80
WIRE 304 96 304 80
WIRE 304 176 304 160
WIRE 384 176 384 160
WIRE -48 192 -48 176
WIRE 48 192 48 80
WIRE 64 192 48 192
WIRE 272 192 256 192
SYMBOL ADP172-1.5 160 192 R0
SYMATTR InstName U1
SYMBOL cap 288 96 R0
SYMATTR InstName C1
SYMATTR Value 1
SYMBOL res 368 64 R0
SYMATTR InstName RLOAD
SYMATTR Value 5
SYMBOL voltage -48 80 R0
SYMATTR InstName V1
SYMATTR Value 3.6
FLAG -48 192 0
FLAG 304 176 0
FLAG 272 192 0
FLAG 384 176 0
FLAG -32 80 IN
FLAG 336 80 OUT
TEXT 160 256 Center 2 !.tran 2m startup