Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\2344f74474aa_debug_circuit.asc
* Generated by LTspice 26.0.1 for Windows.
LI6 N009 N008 0.1
LI12 0 N014 0.1
C1 Vout N001 1e-06
LI1 N004 N003 0.1
LI9 N012 N011 0.1
LI2 N005 N004 0.1
LI4 N007 N006 0.1
VAC1 N001 0 AC 1
LI8 N011 N010 0.1
LI7 N010 N009 0.1
R1 Vout N001 3000
R2 N003 N002 2000
LI5 N008 N007 0.1
LI11 N014 N013 0.1
LI3 N006 N005 0.1
LI10 N013 N012 0.1
.ac oct 10 1 1000
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 0 -160 -272 -160
WIRE 0 -168 0 1200
WIRE 112 -168 112 1200
WIRE 224 -168 224 1200
WIRE 336 -168 336 1200
WIRE 448 -168 448 1200
WIRE 560 -168 560 1200
WIRE 672 -168 672 1200
WIRE 784 -168 784 1200
WIRE 896 -168 896 1200
WIRE 1008 -168 1008 1200
WIRE 1120 -168 1120 1200
WIRE 1232 -168 1232 1200
WIRE 1344 -168 1344 1200
WIRE 1456 -168 1456 1200
WIRE 1568 -168 1568 1200
WIRE 64 0 112 0
WIRE 80 80 112 80
WIRE 304 160 336 160
WIRE 416 240 448 240
WIRE 528 320 560 320
WIRE 640 400 672 400
WIRE 752 480 784 480
WIRE 864 560 896 560
WIRE 976 640 1008 640
WIRE 1088 720 1120 720
WIRE 1200 800 1232 800
WIRE 1312 880 1344 880
WIRE 1424 960 1456 960
WIRE 1536 1040 1568 1040
SYMBOL ind 544 304 R90
SYMATTR InstName I2
SYMATTR Value 0.1
SYMBOL ind 880 544 R90
SYMATTR InstName I5
SYMATTR Value 0.1
SYMBOL ind 1440 944 R90
SYMATTR InstName I10
SYMATTR Value 0.1
SYMBOL ind 1664 1104 R90
SYMATTR InstName I12
SYMATTR Value 0.1
SYMBOL ind 656 384 R90
SYMATTR InstName I3
SYMATTR Value 0.1
SYMBOL ind 432 224 R90
SYMATTR InstName I1
SYMATTR Value 0.1
SYMBOL ind 1328 864 R90
SYMATTR InstName I9
SYMATTR Value 0.1
SYMBOL ind 1104 704 R90
SYMATTR InstName I7
SYMATTR Value 0.1
SYMBOL cap 64 -16 R90
SYMATTR InstName C1
SYMATTR Value 1e-06
SYMBOL res 96 64 R90
SYMATTR InstName R1
SYMATTR Value 3000
SYMBOL ind 1216 784 R90
SYMATTR InstName I8
SYMATTR Value 0.1
SYMBOL ind 768 464 R90
SYMATTR InstName I4
SYMATTR Value 0.1
SYMBOL res 320 144 R90
SYMATTR InstName R2
SYMATTR Value 2000
SYMBOL ind 1552 1024 R90
SYMATTR InstName I11
SYMATTR Value 0.1
SYMBOL voltage -272 -176 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName AC1
SYMATTR Value AC 1
SYMBOL ind 992 624 R90
SYMATTR InstName I6
SYMATTR Value 0.1
FLAG -272 -80 0
FLAG 112 -144 Vout
FLAG 1648 1120 0
TEXT -380 328 Left 2 !.ac oct 10 1 1000
* Z:\home\khalils\Downloads\files\data\raw_asc\b96ae1f6b705_IRFPE50_Cxss.asc
* Generated by LTspice 26.0.1 for Windows.
M1 d1 N001 0 0 IRFPE50
V1 d1 0 { VDS} AC 1
V2 N001 0 0 AC 0
M2 d2 N002 0 0 IRFPE50
V3 d2 0 { VDS} AC 0
V4 N002 0 0 AC 1
H1 Coss 0 V1 -1e-3
H2 Crss 0 V2 -1e-3
H3 Ciss 0 V4 -1e-3
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL IRFPE50 VDMOS(KP=3.3362 RS=0.0114 RD=1.1438 RG=1.0 VTO=3.31 CGDMAX=6810p
+CGDMIN=100p CJO=3990p Vj=0.75 M=0.6595 CGS=2610p N=1 IS=1.00E-06 RB=0.1781 TT=936n)
.step param VDS 0.1 25 0.1
.ac list {1e3/2/pi} ; jw=1e3
* MOSFET Capacitances Versus Drain-Source Voltage
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1084 788
WIRE 512 96 480 96
WIRE 176 112 112 112
WIRE 256 112 176 112
WIRE 480 128 480 96
WIRE 112 144 112 112
WIRE 64 224 -16 224
WIRE 256 224 256 112
WIRE -16 240 -16 224
WIRE 480 240 480 208
WIRE 512 304 480 304
WIRE -16 336 -16 320
WIRE 112 336 112 240
WIRE 256 336 256 304
WIRE 480 336 480 304
WIRE 176 432 112 432
WIRE 256 432 176 432
WIRE 480 448 480 416
WIRE 112 464 112 432
WIRE 512 512 480 512
WIRE 64 544 -16 544
WIRE 256 544 256 432
WIRE 480 544 480 512
WIRE -16 560 -16 544
WIRE -16 656 -16 640
WIRE 112 656 112 560
WIRE 256 656 256 624
WIRE 480 656 480 624
FLAG 112 336 0
FLAG -16 336 0
FLAG 256 336 0
FLAG 176 112 d1
FLAG 112 656 0
FLAG -16 656 0
FLAG 256 656 0
FLAG 176 432 d2
FLAG 480 240 0
FLAG 480 448 0
FLAG 480 656 0
FLAG 512 96 Coss
FLAG 512 304 Crss
FLAG 512 512 Ciss
SYMBOL NMOS 64 144 R0
SYMATTR InstName M1
SYMATTR Value IRFPE50
SYMBOL voltage 256 208 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V1
SYMATTR Value { VDS}
SYMBOL voltage -16 224 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 0
SYMATTR InstName V2
SYMATTR Value 0
SYMBOL NMOS 64 464 R0
SYMATTR InstName M2
SYMATTR Value IRFPE50
SYMBOL voltage 256 528 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 0
SYMATTR InstName V3
SYMATTR Value { VDS}
SYMBOL voltage -16 544 R0
WINDOW 123 24 132 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value2 AC 1
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL h 480 112 R0
SYMATTR InstName H1
SYMATTR Value V1 -1e-3
SYMBOL h 480 320 R0
SYMATTR InstName H2
SYMATTR Value V2 -1e-3
SYMBOL h 480 528 R0
SYMATTR InstName H3
SYMATTR Value V4 -1e-3
TEXT -376 -8 Left 0 !.MODEL IRFPE50 VDMOS(KP=3.3362 RS=0.0114 RD=1.1438 RG=1.0 VTO=3.31 CGDMAX=6810p\n+CGDMIN=100p CJO=3990p Vj=0.75 M=0.6595 CGS=2610p N=1 IS=1.00E-06 RB=0.1781 TT=936n)
TEXT -376 96 Left 0 !.step param VDS 0.1 25 0.1
TEXT -376 120 Left 0 !.ac list {1e3/2/pi} ; jw=1e3
TEXT -368 -80 Left 0 ;MOSFET Capacitances Versus Drain-Source Voltage
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1084-5.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT1084-5.asy)
Rload OUT 0 10
C1 OUT 0 10
XU1 0 OUT IN LT1084-5 ;pnba GND)OUT)IN
V1 IN 0 PWL(0 0 1 10) Rser=0.1
.tran 1
.lib LT1083.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2800 1520
WIRE 1552 896 1344 896
WIRE 1872 896 1808 896
WIRE 2000 896 1872 896
WIRE 1344 912 1344 896
WIRE 1872 912 1872 896
WIRE 2000 912 2000 896
WIRE 1344 1008 1344 992
WIRE 1872 1008 1872 976
WIRE 2000 1008 2000 992
WIRE 1680 1024 1680 992
SYMBOL RES 1984 896 R0
SYMATTR InstName Rload
SYMATTR Value 10
SYMBOL PowerProducts\\LT1084-5 1680 896 R0
SYMATTR InstName U1
SYMBOL VOLTAGE 1344 896 R0
WINDOW 123 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 1 10)
SYMATTR SpiceLine Rser=0.1
SYMBOL cap 1856 912 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 2000 896 OUT
FLAG 2000 1008 0
FLAG 1344 1008 0
FLAG 1872 1008 0
FLAG 1344 896 IN
FLAG 1680 1024 0
TEXT 1960 1064 Left 2 !.tran 1
* Z:\home\khalils\Downloads\files\data\raw_asc\032ca80e4bbe_transitorio.asc
* Generated by LTspice 26.0.1 for Windows.
R1 N001 N002 28.8k
C1 N002 0 100f
V_IN N003 0 PULSE(0.2 3.3 3n 5n 5n 45n 100n) Rser=0
M1 N002 N003 0 0 NMOS_FDE l=1u w=2.22u
V_DD N001 0 3.3 Rser=0
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.MODEL NMOS_FDE NMOS LEVEL=1 VTO=0.75 KP=60e-6 GAMMA=0.5 PHI=0.6
.tran 0 400n 0 1n
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1064 680
WIRE 240 16 80 16
WIRE 240 48 240 16
WIRE 80 64 80 16
WIRE 240 160 240 128
WIRE 432 160 240 160
WIRE 240 176 240 160
WIRE 160 208 80 208
WIRE 80 240 80 208
WIRE 160 256 160 208
WIRE 192 256 160 256
SYMBOL res 224 32 R0
SYMATTR InstName R1
SYMATTR Value 28.8k
SYMBOL voltage 80 48 R0
SYMATTR InstName V_DD
SYMATTR Value 3.3
SYMATTR SpiceLine Rser=0
SYMBOL cap 416 160 R0
SYMATTR InstName C1
SYMATTR Value 100f
SYMBOL nmos4 192 176 R0
SYMATTR InstName M1
SYMATTR Value NMOS_FDE
SYMATTR Value2 l=1u w=2.22u
SYMBOL voltage 80 224 R0
SYMATTR InstName V_IN
SYMATTR Value PULSE(0.2 3.3 3n 5n 5n 45n 100n)
SYMATTR SpiceLine Rser=0
FLAG 80 320 0
FLAG 80 144 0
FLAG 240 272 0
FLAG 240 224 0
FLAG 432 224 0
TEXT -112 392 Left 2 !.MODEL NMOS_FDE NMOS LEVEL=1 VTO=0.75 KP=60e-6 GAMMA=0.5 PHI=0.6
TEXT 592 280 Left 2 !.tran 0 400n 0 1n
* Z:\home\khalils\Downloads\files\data\raw_asc\LT1009.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\References\LT1009.asy)
R3 N002 0 {10K*x}
R1 N001 OUT 3.6K
V1 N001 0 5
R2 OUT N002 {10K*(1-x)}
XU1 OUT 0 N002 LT1009 ;pnba VCC)VEE)ADJ
.dc TEMP -55 125 .1
.step param x .4 .6 .1
.lib LTC3.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 224 208 96 208
WIRE 224 224 224 208
WIRE 400 256 352 256
WIRE 480 256 400 256
WIRE 96 272 96 208
WIRE 400 272 400 256
WIRE 224 320 224 304
WIRE 352 320 352 256
WIRE 352 320 224 320
WIRE 224 336 224 320
WIRE 400 368 400 352
WIRE 400 368 256 368
WIRE 400 384 400 368
WIRE 96 416 96 352
WIRE 224 416 224 400
WIRE 400 480 400 464
SYMBOL voltage 96 256 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL res 384 256 R0
SYMATTR InstName R2
SYMATTR Value {10K*(1-x)}
SYMBOL LT1009 224 368 R0
SYMATTR InstName U1
SYMBOL res 208 208 R0
SYMATTR InstName R1
SYMATTR Value 3.6K
SYMBOL res 384 368 R0
SYMATTR InstName R3
SYMATTR Value {10K*x}
FLAG 96 416 0
FLAG 224 416 0
FLAG 480 256 OUT
FLAG 400 480 0
TEXT 568 392 Left 2 !.dc TEMP -55 125 .1\n.step param x .4 .6 .1
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC3606B.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTC3606B.asy)
L1 N001 OUT 1.5
XU1 0 N004 MP_01 N001 IN N002 IN N003 LTC3606B ;pnba GND)Rlim))SW)Vin)Pgood)Run)FB
R4 IN N002 499K
R1 N004 0 116K
C1 N004 0 1000p
V1 IN 0 4.2
R3 N003 0 255K
Rload OUT 0 20
R2 OUT N003 1210K
C2 OUT 0 100
.tran 1.5m startup
.lib LTC3606B.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 -32 -144 -32
WIRE 32 -32 -48 -32
WIRE 176 -32 32 -32
WIRE -144 -16 -144 -32
WIRE 176 -16 176 -32
WIRE -48 32 -48 -32
WIRE 32 32 32 -32
WIRE 48 32 32 32
WIRE 336 32 304 32
WIRE 448 32 416 32
WIRE 560 32 448 32
WIRE 656 32 560 32
WIRE 448 48 448 32
WIRE 560 48 560 32
WIRE 656 48 656 32
WIRE -144 80 -144 64
WIRE -48 128 -48 112
WIRE 48 128 -48 128
WIRE 448 128 304 128
WIRE 448 144 448 128
WIRE 560 144 560 112
WIRE 656 144 656 128
WIRE -16 224 -112 224
WIRE 48 224 -16 224
WIRE 320 224 304 224
WIRE -112 240 -112 224
WIRE -16 240 -16 224
WIRE 448 240 448 224
WIRE -112 336 -112 320
WIRE -16 336 -16 304
SYMBOL voltage -144 -32 R0
SYMATTR InstName V1
SYMATTR Value 4.2
SYMBOL res 432 32 R0
SYMATTR InstName R2
SYMATTR Value 1210K
SYMBOL res 432 128 R0
SYMATTR InstName R3
SYMATTR Value 255K
SYMBOL res -128 224 R0
SYMATTR InstName R1
SYMATTR Value 116K
SYMBOL cap -32 240 R0
SYMATTR InstName C1
SYMATTR Value 1000p
SYMBOL res 640 32 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL LTC3606B 176 128 R0
SYMATTR InstName U1
SYMBOL res -64 16 R0
SYMATTR InstName R4
SYMATTR Value 499K
SYMBOL ind 320 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 1.5
SYMBOL cap 544 48 R0
SYMATTR InstName C2
SYMATTR Value 100
FLAG 320 224 0
FLAG -16 336 0
FLAG -112 336 0
FLAG 448 240 0
FLAG 560 144 0
FLAG -144 80 0
FLAG 656 32 OUT
FLAG -144 -32 IN
FLAG 656 144 0
TEXT 360 304 Left 2 !.tran 1.5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADG779.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADG779.asy)
R1 D 0 301
V1 IN 0 PULSE(0 3 25u 1n 1n 20u)
C1 D 0 36p
V2 S2 0 3
V3 +V 0 5
XU1 IN 0 D S2 +V 0 ADG779 ;pnba IN)S1)D)S2)Vdd)GND
.tran 75u
.lib ADG779.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -48 0 -48 -48
WIRE -192 64 -400 64
WIRE -144 64 -192 64
WIRE -512 96 -512 48
WIRE -400 96 -400 64
WIRE 128 96 48 96
WIRE 256 96 128 96
WIRE -144 128 -288 128
WIRE 128 128 128 96
WIRE 256 128 256 96
WIRE -288 160 -288 128
WIRE -512 192 -512 176
WIRE -400 192 -400 176
WIRE -192 192 -288 192
WIRE -144 192 -192 192
WIRE 128 240 128 208
WIRE 256 240 256 192
WIRE -288 304 -288 192
WIRE -48 336 -48 304
WIRE -288 448 -288 384
SYMBOL voltage -400 80 R0
SYMATTR InstName V2
SYMATTR Value 3
SYMBOL ADG779 -48 144 R0
SYMATTR InstName U1
SYMBOL res 112 112 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -512 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 5
SYMBOL cap 240 128 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL voltage -288 288 R0
WINDOW 3 24 102 Left 2
SYMATTR Value PULSE(0 3 25u 1n 1n 20u)
SYMATTR InstName V1
FLAG 128 240 0
FLAG 256 240 0
FLAG -48 336 0
FLAG -288 448 0
FLAG -288 160 0
FLAG -400 192 0
FLAG -48 -48 +V
FLAG -512 192 0
FLAG -512 48 +V
FLAG -192 64 S2
FLAG -192 192 IN
FLAG 128 96 D
TEXT 144 320 Left 2 !.tran 75u
* Z:\home\khalils\Downloads\files\data\raw_asc\62bdc00b1dee_ideal_mult.asc
* Generated by LTspice 26.0.1 for Windows.
V1 A 0 SINE(0 1 41k)
V2 B 0 SINE(0 1 40k)
B1 Aneg 0 V=-V(A)
V3 ref 0 PULSE(-1 1 0 0.5u 0.5u 0 1u)
B2 N001 0 V=if(V(B)>V(ref),V(A),V(Aneg))
B3 out_mult 0 V=V(A)*V(B)
R1 N001 out 1k
C1 out 0 1n
* input signals
* internally generated signals
* output signals
.tran 0 10m 0 10n
* Simulation of analog multiplier
* V1 and V2 represent input signals A and B
* B1 is the inverter for the signal A
* V2 is the internal triangle wave generator
* B2 represents the analog switch which is controlled by a comparator
* B3 generates a reference signal which is the real multiplication of A and B
* ----------------------------------------------
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1716 680
WIRE 592 32 416 32
WIRE 928 32 720 32
WIRE 1408 32 1120 32
WIRE 1520 32 1488 32
WIRE 1584 32 1520 32
WIRE 416 48 416 32
WIRE 720 48 720 32
WIRE 1120 48 1120 32
WIRE 1520 48 1520 32
WIRE 1520 128 1520 112
WIRE 592 176 416 176
WIRE 928 176 720 176
WIRE 1584 176 1120 176
WIRE 416 192 416 176
WIRE 720 192 720 176
WIRE 1120 192 1120 176
FLAG 416 128 0
FLAG 416 272 0
FLAG 592 32 A
FLAG 592 176 B
FLAG 720 128 0
FLAG 720 272 0
FLAG 928 176 ref
FLAG 928 32 Aneg
FLAG 1120 128 0
FLAG 1120 272 0
FLAG 1584 32 out
FLAG 1584 176 out_mult
FLAG 1520 128 0
SYMBOL voltage 416 32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value SINE(0 1 41k)
SYMBOL voltage 416 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value SINE(0 1 40k)
SYMBOL bv 720 32 R0
SYMATTR InstName B1
SYMATTR Value V=-V(A)
SYMBOL voltage 720 176 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V3
SYMATTR Value PULSE(-1 1 0 0.5u 0.5u 0 1u)
SYMBOL bv 1120 32 R0
SYMATTR InstName B2
SYMATTR Value V=if(V(B)>V(ref),V(A),V(Aneg))
SYMBOL bv 1120 176 R0
SYMATTR InstName B3
SYMATTR Value V=V(A)*V(B)
SYMBOL res 1392 48 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL cap 1504 48 R0
SYMATTR InstName C1
SYMATTR Value 1n
TEXT 424 -48 Left 2 ;input signals
TEXT 704 -48 Left 2 ;internally generated signals
TEXT 1256 -48 Left 2 ;output signals
TEXT 382 360 Left 2 !.tran 0 10m 0 10n
TEXT 384 -160 Left 3 ;Simulation of analog multiplier
TEXT 384 464 Left 2 ;V1 and V2 represent input signals A and B
TEXT 384 496 Left 2 ;B1 is the inverter for the signal A
TEXT 384 528 Left 2 ;V2 is the internal triangle wave generator
TEXT 384 560 Left 2 ;B2 represents the analog switch which is controlled by a comparator
TEXT 384 592 Left 2 ;B3 generates a reference signal which is the real multiplication of A and B
TEXT 384 -136 Left 3 ;----------------------------------------------
* Z:\home\khalils\Downloads\files\data\raw_asc\ADM7154-3.3.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADM7154-3.3.asy)
C3 N004 0 1
C1 OUT 0 10
R1 IN N001 100K
C4 N002 0 1
V1 IN 0 3.9
Rload OUT 0 33
C2 N003 0 1
XU1 N004 OUT N002 0 N003 N003 N001 IN ADM7154_5 Vreg=3.6022 Vref=3.3160 ;pnba Vreg)Vout)Byp)GND)Ref_Sense)Ref)EN)Vin
.tran 5m startup
.lib ADM7154_5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -144 32
WIRE 80 32 -32 32
WIRE 464 32 400 32
WIRE 560 32 464 32
WIRE -144 48 -144 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE -144 144 -144 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE -16 224 -32 224
WIRE 80 224 48 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE -16 320 -32 320
WIRE 80 320 48 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL voltage -144 32 R0
SYMATTR InstName V1
SYMATTR Value 3.9
SYMBOL cap 448 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL res 544 32 R0
SYMATTR InstName Rload
SYMATTR Value 33
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap 448 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL ADM7154-3.3 240 176 R0
SYMATTR InstName U1
SYMBOL cap 48 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL cap 48 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -32 320 0
FLAG -32 224 0
FLAG -144 144 0
FLAG 560 144 0
FLAG -144 32 IN
FLAG 560 32 OUT
TEXT 432 384 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LTC6400-20.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\OpAmps\LTC6400-20.asy)
V1 N004 0 SINE(0 10m 100Meg)
V2 N001 0 1.5
XU1 0 0 N001 N002 N006 N007 N007 N004 N005 N003 LTC6400-20 ;pnba IN-)Vocm)V+)OUT+)OUT-)V-)_EN)IN+)OUTF-)OUTF+
V3 N007 0 -1.5
.tran 100n
.lib LTC6.lib
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 192 112 -48 112
WIRE -48 128 -48 112
WIRE 192 128 192 112
WIRE 352 160 336 160
WIRE 80 208 64 208
WIRE 352 208 336 208
WIRE -48 224 -48 208
WIRE -176 272 -192 272
WIRE 80 272 -96 272
WIRE 352 272 336 272
WIRE 352 320 336 320
WIRE 240 384 240 368
WIRE 144 400 144 368
WIRE 192 400 192 368
WIRE 192 400 144 400
WIRE 192 432 192 400
WIRE 192 528 192 512
SYMBOL voltage -48 112 R0
SYMATTR InstName V2
SYMATTR Value 1.5
SYMBOL voltage 192 416 R0
SYMATTR InstName V3
SYMATTR Value -1.5
SYMBOL LTC6400-20 208 240 R0
WINDOW 3 53 144 Left 2
SYMATTR InstName U1
SYMBOL voltage -80 272 R90
WINDOW 123 74 56 VTop 2
WINDOW 39 53 56 VTop 2
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName V1
SYMATTR Value SINE(0 10m 100Meg)
FLAG -48 224 0
FLAG -192 272 0
FLAG 64 208 0
FLAG 240 384 0
FLAG 192 528 0
TEXT 376 448 Left 2 !.tran 100n
* Z:\home\khalils\Downloads\files\data\raw_asc\51c2f1e0f58d_BiTuner_TempDiode.asc
* Generated by LTspice 26.0.1 for Windows.
V1 nVp 0 3.3V
D11 nDa 0 CMAD6001
R1 nVp nDa 10kR
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.step temp 10 50 20
.tran 0 1 0
.model CMAD6001 D( IS=70.1f RS=0.658 BV=75.0 IBV=500p CJO=2.00p M=0.333 N=1.24 TT=4.32u mfg=Central type=silicon )
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1136 680
WIRE -640 -96 -656 -96
WIRE -320 -96 -640 -96
WIRE -320 -80 -320 -96
WIRE -656 -48 -656 -96
WIRE -320 16 -320 0
WIRE -320 32 -320 16
WIRE -656 128 -656 32
WIRE -320 128 -320 96
SYMBOL diode -336 32 R0
SYMATTR InstName D11
SYMATTR Value CMAD6001
SYMBOL res -336 -96 R0
SYMATTR InstName R1
SYMATTR Value 10kR
SYMBOL voltage -656 -64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3V
FLAG -656 128 0
FLAG -640 -96 nVp
FLAG -320 128 0
FLAG -320 16 nDa
TEXT -776 256 Left 2 !.step temp 10 50 20
TEXT -776 224 Left 2 !.tran 0 1 0
TEXT -400 216 Left 2 !.model CMAD6001 D( IS=70.1f RS=0.658 BV=75.0 IBV=500p CJO=2.00p M=0.333 N=1.24 TT=4.32u mfg=Central type=silicon )
* Z:\home\khalils\Downloads\files\data\raw_asc\ADGS2414D.asc
* Generated by LTspice 26.0.1 for Windows.
* Note:\nSwitch shown for a logic 0 input\nQinj not included\nSPI functionality is not modelled\nOny one channel is modelled
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\Switches\ADGS2414D.asy)
V1 vS 0 SINE(0 10 20)
V3 v+ 0 15
C1 vD 0 36p
R1 vD 0 301
V2 vIN 0 PULSE(0 2.5 20n 20n 20n 150m 300m)
XU1 vIN vD vS v- 0 v+ ADGS2414D ;pnba IN)D)S)Vss)GND)Vdd
V4 v- 0 -15
.tran 1
.lib ADGS2414D.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 936 832
WIRE 240 160 240 128
WIRE -80 224 -112 224
WIRE 112 224 0 224
WIRE 144 224 112 224
WIRE 384 224 336 224
WIRE 464 224 384 224
WIRE 576 224 464 224
WIRE 464 256 464 224
WIRE 576 256 576 224
WIRE 112 288 48 288
WIRE 144 288 112 288
WIRE -288 336 -288 304
WIRE -192 336 -192 304
WIRE 48 336 48 288
WIRE 464 352 464 336
WIRE 576 352 576 320
WIRE 288 416 288 400
WIRE 192 432 192 400
WIRE -288 464 -288 416
WIRE -192 464 -192 416
WIRE 48 464 48 416
SYMBOL ADGS2414D 240 272 R0
SYMATTR InstName U1
SYMBOL voltage -288 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 15
SYMBOL cap 560 256 R0
SYMATTR InstName C1
SYMATTR Value 36p
SYMBOL res 448 240 R0
SYMATTR InstName R1
SYMATTR Value 301
SYMBOL voltage -192 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value -15
SYMBOL voltage 48 320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 3 30 177 Left 2
SYMATTR Value PULSE(0 2.5 20n 20n 20n 150m 300m)
SYMATTR InstName V2
SYMBOL voltage 16 224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value SINE(0 10 20)
FLAG -112 224 0
FLAG 48 464 0
FLAG 464 352 0
FLAG 288 416 0
FLAG 384 224 vD
FLAG 112 224 vS
FLAG 112 288 vIN
FLAG 576 352 0
FLAG -288 304 v+
FLAG 240 128 v+
FLAG -288 464 0
FLAG -192 464 0
FLAG -192 304 v-
FLAG 192 432 v-
TEXT 80 528 Left 2 !.tran 1
TEXT -288 8 Left 2 ;Note:\nSwitch shown for a logic 0 input\nQinj not included\nSPI functionality is not modelled\nOny one channel is modelled
* Z:\tmp\asc_dec_bjh7r6w2\197294b203b4_5507_dec2.asc
* Generated by LTspice 26.0.1 for Windows.
B1 N003 0 V=V(rf)*(1+sin(2*pi*50K*time))
R1 N004 N003 50
C2 N001 N002 28p
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1076 948
WIRE 0 128 -208 128
WIRE 368 128 0 128
WIRE -208 144 -208 128
WIRE 0 192 0 128
WIRE 64 192 0 192
WIRE 0 224 0 192
WIRE -208 240 -208 224
WIRE 0 304 0 288
WIRE 64 304 0 304
WIRE -112 416 -176 416
WIRE -16 416 -32 416
WIRE 64 416 48 416
WIRE -176 432 -176 416
WIRE -176 528 -176 512
SYMBOL bv -176 416 R0
SYMATTR InstName B1
SYMATTR Value V=V(rf)*(1+sin(2*pi*50K*time))
SYMBOL res -16 400 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 50
SYMBOL cap -16 224 R0
SYMATTR InstName C2
SYMATTR Value 28p
FLAG -208 240 0
FLAG -176 528 0