Si7li/ltspice-spice-circuits huggingface dataset:
* Z:\home\khalils\Downloads\files\data\raw_asc\1a78975d4cbc_SwitchModule.asc
* Generated by LTspice 26.0.1 for Windows.
S3 Vin Out RST VDD/2 SW
S4 Out N001 VDD/2 RST SW
S2 N001 VrefM VDD/2 Bit SW
S1 VrefP N001 Bit VDD/2 SW
.model SW SW
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 -32 -208 -32
WIRE -80 -32 -80 -112
WIRE -80 -32 -96 -32
WIRE -64 -32 -80 -32
WIRE 176 -32 16 -32
WIRE -160 32 -160 16
WIRE -112 32 -112 16
WIRE -80 32 -112 32
WIRE -48 32 -48 16
WIRE -48 32 -80 32
WIRE 0 32 0 16
WIRE -80 64 -80 32
WIRE 176 144 176 -32
WIRE 176 144 160 144
WIRE 192 144 176 144
WIRE 288 144 272 144
WIRE 96 208 96 192
WIRE 144 208 144 192
WIRE 176 208 144 208
WIRE 208 208 208 192
WIRE 208 208 176 208
WIRE 256 208 256 192
WIRE 176 240 176 208
IOPIN 176 240 In
IOPIN -80 64 In
SYMBOL sw 64 144 R270
WINDOW 0 45 81 VRight 0
WINDOW 3 52 36 VRight 0
SYMATTR InstName S1
SYMBOL sw -80 -32 R270
WINDOW 0 45 40 VLeft 0
WINDOW 3 46 84 VLeft 0
SYMATTR InstName S4
SYMBOL sw 176 144 R270
WINDOW 0 45 40 VLeft 0
WINDOW 3 46 84 VLeft 0
SYMATTR InstName S2
SYMBOL sw -192 -32 R270
WINDOW 0 45 81 VRight 0
WINDOW 3 52 36 VRight 0
SYMATTR InstName S3
FLAG 176 240 Bit
FLAG 80 144 VrefP
FLAG 96 208 VDD/2
FLAG 256 208 VDD/2
FLAG -80 64 RST
FLAG -160 32 VDD/2
FLAG 0 32 VDD/2
FLAG -208 -32 Vin
FLAG -80 -112 Out
FLAG 288 144 VrefM
TEXT -336 184 Left 0 !.model SW SW
* Z:\home\khalils\Downloads\files\data\raw_asc\LTM8027.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LTM8027.asy)
XU1 IN N001 N002 N003 N005 N003 OUT N004 N003 MP_01 MP_02 MP_03 MP_04 MP_05 MP_06 MP_07 0 LTM8027 ;pnba Vin)RUN)SS)Bias2)Adj)Bias1)Vout)Rt)AUX))))))))GND
Rload OUT 0 2.88
C2 OUT 0 100
C1 N002 0 1000p
R3 N005 0 56.2K
R2 N004 0 48.7K
R1 IN N001 1Meg
V1 IN 0 24
.tran 1m startup
.lib LTM8027.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1852 804
WIRE 624 -192 528 -192
WIRE 848 -192 624 -192
WIRE 528 -176 528 -192
WIRE 624 -176 624 -192
WIRE 848 -128 848 -192
WIRE 528 -80 528 -96
WIRE 624 -80 624 -96
WIRE 720 -80 624 -80
WIRE 1072 -80 976 -80
WIRE 1168 -80 1072 -80
WIRE 1072 -64 1072 -80
WIRE 1168 -64 1168 -80
WIRE 640 16 624 16
WIRE 720 16 704 16
WIRE 1008 16 976 16
WIRE 1072 32 1072 0
WIRE 1168 32 1168 16
WIRE 608 112 592 112
WIRE 720 112 688 112
WIRE 1008 112 1008 16
WIRE 1008 112 976 112
WIRE 608 208 592 208
WIRE 720 208 688 208
WIRE 1008 208 1008 112
WIRE 1008 208 976 208
WIRE 848 272 848 256
SYMBOL res 704 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 56.2K
SYMBOL res 1152 -80 R0
SYMATTR InstName Rload
SYMATTR Value 2.88
SYMBOL voltage 528 -192 R0
WINDOW 3 25 101 Left 2
SYMATTR Value 24
SYMATTR InstName V1
SYMBOL res 608 -192 R0
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL cap 704 0 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 1000p
SYMBOL res 704 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 48.7K
SYMBOL PowerProducts\\LTM8027 848 64 R0
SYMATTR InstName U1
SYMBOL cap 1056 -64 R0
SYMATTR InstName C2
SYMATTR Value 100
FLAG 1072 32 0
FLAG 1168 32 0
FLAG 528 -80 0
FLAG 1168 -80 OUT
FLAG 528 -192 IN
FLAG 624 16 0
FLAG 592 112 0
FLAG 848 272 0
FLAG 592 208 0
TEXT 1072 200 Left 2 !.tran 1m startup
* Z:\tmp\asc_dec_bjh7r6w2\12135070757f_totem-pole_driver_low_side_complementary_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
Q3 N004 pulse_source N009 0 BC847B
V2 pulse_source 0 PULSE(0 5 1n 1n 1n 500n 40u)
M1 P001 gate N006 N006 BSB015N04NX3
Q7 N007 N008 N009 0 BC847B
R9 N001 N004 330
R2 N002 P001 5
R3 N001 N005 1k
R13 N005 N008 470
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1708 932
WIRE -1360 32 -1632 32
WIRE -960 32 -1360 32
WIRE -832 32 -960 32
WIRE -640 32 -832 32
WIRE -192 32 -432 32
WIRE 48 32 -192 32
WIRE 448 32 48 32
WIRE 48 64 48 32
WIRE -960 80 -960 32
WIRE -192 112 -192 32
WIRE -1632 160 -1632 32
WIRE 160 160 48 160
WIRE -832 208 -832 32
WIRE -192 224 -192 208
WIRE -128 224 -192 224
WIRE -32 224 -32 128
WIRE -32 224 -48 224
WIRE 0 224 -32 224
WIRE -960 256 -960 160
WIRE -960 256 -1424 256
WIRE -896 256 -960 256
WIRE -192 256 -192 224
WIRE -1632 336 -1632 240
WIRE -1504 336 -1632 336
WIRE 48 352 48 240
WIRE -1632 432 -1632 336
WIRE -1824 480 -1952 480
WIRE -1504 544 -1504 336
WIRE -1264 544 -1504 544
WIRE -1504 608 -1504 544
WIRE -1504 608 -1584 608
WIRE -1136 624 -1136 320
WIRE -1424 640 -1424 256
WIRE -1360 672 -1360 192
WIRE -1264 672 -1264 624
WIRE -1264 672 -1360 672
WIRE -1200 672 -1264 672
WIRE -1824 688 -1824 480
WIRE -1584 688 -1824 688
WIRE -1488 688 -1584 688
WIRE -1584 720 -1584 688
WIRE -1136 736 -1136 720
WIRE -1136 736 -1424 736
SYMBOL npn -1488 640 R0
SYMATTR InstName Q3
SYMATTR Value BC847B
SYMBOL voltage -1952 464 R0
WINDOW 0 -79 39 Left 2
WINDOW 3 -396 103 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 5 1n 1n 1n 500n 40u)
SYMBOL nmos 0 144 R0
SYMATTR InstName M1
SYMATTR Value BSB015N04NX3
SYMBOL npn -1200 624 R0
SYMATTR InstName Q7
SYMATTR Value BC847B
SYMBOL res -976 64 R0
SYMATTR InstName R9
SYMATTR Value 330
SYMBOL res 32 48 R0
SYMATTR InstName R2
SYMATTR Value 5
SYMBOL res -1648 144 R0
SYMATTR InstName R3
SYMATTR Value 1k
SYMBOL res -1280 528 R0
SYMATTR InstName R13
SYMATTR Value 470
FLAG -1952 560 0
FLAG -1824 480 pulse_source
FLAG 160 160 out
FLAG -32 128 gate
FLAG -1424 816 0
FLAG -1632 512 0
FLAG -1584 800 0
* Z:\home\khalils\Downloads\files\data\raw_asc\LT3077.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT3077.asy)
C1 BIAS 0 4.7
R2 OUT 0 1
C3 N001 0 4.7
C2 OUT 0 10 Rser=2m
R1 BIAS PG 51k
XU2 BIAS 0 NC_01 NC_02 PG OUT BIAS BIAS 0 OUT 0 IN N001 LT3077 TA=25 Rth=42 ;pnba EN)Vo0)Vo1)Vo2)PG)OUT)BIAS)BIASF)ILIM)SENSE)GND)IN)REF
V1 IN 0 1.65
V2 BIAS 0 5
.tran 500m startup
.lib LT3077.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2000 1632
WIRE 240 400 32 400
WIRE 704 400 240 400
WIRE 880 400 704 400
WIRE 512 496 368 496
WIRE 624 496 576 496
WIRE 880 512 880 400
WIRE 240 544 240 400
WIRE 368 544 368 496
WIRE 880 608 880 592
WIRE 96 624 -96 624
WIRE 128 624 96 624
WIRE 512 624 480 624
WIRE 544 624 512 624
WIRE 704 624 704 400
WIRE 704 624 624 624
WIRE -96 656 -96 624
WIRE 32 688 32 400
WIRE 128 688 32 688
WIRE 592 688 480 688
WIRE -96 752 -96 736
WIRE 128 752 80 752
WIRE 592 752 592 688
WIRE 592 752 480 752
WIRE 816 752 592 752
WIRE 992 752 816 752
WIRE 80 768 80 752
WIRE 816 768 816 752
WIRE 992 784 992 752
WIRE 672 816 480 816
WIRE 544 880 480 880
WIRE 816 880 816 832
WIRE 992 880 992 864
WIRE 544 896 544 880
WIRE 304 976 304 960
WIRE 544 992 544 960
WIRE 672 992 672 816
SYMBOL voltage 880 496 R0
WINDOW 123 24 138 Left 2
WINDOW 39 24 117 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL voltage -96 640 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 1.65
SYMBOL cap 512 512 R270
WINDOW 3 0 32 VBottom 2
WINDOW 0 32 32 VTop 2
SYMATTR Value 4.7
SYMATTR InstName C1
SYMBOL cap 800 768 R0
WINDOW 3 26 56 Left 2
SYMATTR Value 10
SYMATTR InstName C2
SYMATTR SpiceLine Rser=2m
SYMBOL cap 528 896 R0
WINDOW 0 51 24 Bottom 2
WINDOW 3 64 28 Top 2
WINDOW 39 53 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL PowerProducts\\LT3077 304 720 R0
SYMATTR InstName U2
SYMBOL res 976 768 R0
SYMATTR InstName R2
SYMATTR Value 1
SYMBOL res 640 608 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 51k
FLAG 304 976 0
FLAG -96 752 0
FLAG 96 624 IN
FLAG 880 608 0
FLAG 816 880 0
FLAG 992 752 OUT
FLAG 992 880 0
FLAG 544 992 0
FLAG 624 496 0
FLAG 672 992 0
FLAG 368 496 BIAS
FLAG 240 400 BIAS
FLAG 512 624 PG
FLAG 80 768 0
TEXT 824 1000 Left 2 !.tran 500m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\LT8303.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8303.asy)
R3 N002 N003 316K
V1 IN 0 40
Rload OUT 0 20
XU1 IN 0 N003 N002 IN LT8303 ;pnba EN/UVLO)GND)RFB)SW)Vin
L2 0 N001 4.2 Rser=20m Cpar=.2p
L1 IN N002 150 Rser=500m Cpar=1p
C1 OUT 0 47
K1 L1 L2 1
D1 N001 OUT MBRS340
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 3m startup
.lib LT8303.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 916 680
WIRE 64 16 -32 16
WIRE 416 16 64 16
WIRE 560 16 464 16
WIRE 688 16 624 16
WIRE 784 16 688 16
WIRE -32 32 -32 16
WIRE 416 32 416 16
WIRE 464 32 464 16
WIRE 688 32 688 16
WIRE 784 32 784 16
WIRE -32 128 -32 112
WIRE 464 128 464 112
WIRE 688 128 688 96
WIRE 784 128 784 112
WIRE 64 144 64 16
WIRE 96 144 64 144
WIRE 416 144 416 112
WIRE 416 144 320 144
WIRE 416 176 416 144
WIRE 64 272 64 144
WIRE 96 272 64 272
WIRE 416 272 416 256
WIRE 416 272 320 272
WIRE 208 336 208 320
SYMBOL res 768 16 R0
SYMATTR InstName Rload
SYMATTR Value 20
SYMBOL res 400 160 R0
SYMATTR InstName R3
SYMATTR Value 316K
SYMBOL ind2 480 128 R180
WINDOW 0 -4 74 Right 2
WINDOW 3 0 35 Right 2
SYMATTR InstName L2
SYMATTR Value 4.2
SYMATTR Type ind
SYMATTR SpiceLine Rser=20m Cpar=.2p
SYMBOL PowerProducts\\LT8303 208 208 R0
SYMATTR InstName U1
SYMBOL voltage -32 16 R0
SYMATTR InstName V1
SYMATTR Value 40
SYMBOL cap 672 32 R0
SYMATTR InstName C1
SYMATTR Value 47
SYMBOL schottky 560 32 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value MBRS340
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL ind2 400 16 R0
WINDOW 0 1 37 Right 2
WINDOW 3 0 77 Right 2
SYMATTR InstName L1
SYMATTR Value 150
SYMATTR Type ind
SYMATTR SpiceLine Rser=500m Cpar=1p
FLAG 208 336 0
FLAG -32 128 0
FLAG -32 16 IN
FLAG 464 128 0
FLAG 688 128 0
FLAG 784 128 0
FLAG 784 16 OUT
TEXT 440 16 Bottom 2 !K1 L1 L2 1
TEXT 560 312 Left 2 !.tran 3m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7158-2.0.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7158-2.0.asy)
Rload OUT 0 2.0
C1 OUT 0 10
C2 N003 0 1
R1 IN N001 100K
C4 N002 0 1
V1 IN 0 3.0
XU1 OUT MP_01 OUT N002 N001 N003 N003 N004 IN 0 ADP7158_9 Vreg=2.611 Vref=2.016 ;pnba Vout))Vout_Sense)Byp)EN)Ref_Sense)Ref)Vreg)Vin)GND
C3 N004 0 1
.tran 5m startup
.lib ADP7158_9.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -32 32 -144 32
WIRE 80 32 -32 32
WIRE 416 32 400 32
WIRE 464 32 416 32
WIRE 560 32 464 32
WIRE -144 48 -144 32
WIRE 464 48 464 32
WIRE 560 48 560 32
WIRE -32 128 -32 32
WIRE -16 128 -32 128
WIRE 80 128 64 128
WIRE 416 128 416 32
WIRE 416 128 400 128
WIRE -144 144 -144 128
WIRE 464 144 464 112
WIRE 560 144 560 128
WIRE 80 224 64 224
WIRE 416 224 400 224
WIRE 464 224 416 224
WIRE 464 240 464 224
WIRE 0 320 -16 320
WIRE 80 320 64 320
WIRE 416 320 416 224
WIRE 416 320 400 320
WIRE 464 320 464 304
WIRE 240 400 240 384
SYMBOL cap 448 48 R0
SYMATTR InstName C1
SYMATTR Value 10
SYMBOL voltage -144 32 R0
SYMATTR InstName V1
SYMATTR Value 3.0
SYMBOL res -32 144 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R1
SYMATTR Value 100K
SYMBOL cap 448 240 R0
SYMATTR InstName C2
SYMATTR Value 1
SYMBOL cap 64 208 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 1
SYMBOL res 544 32 R0
SYMATTR InstName Rload
SYMATTR Value 2.0
SYMBOL cap 64 304 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 1
SYMBOL ADP7158-2.0 240 176 R0
SYMATTR InstName U1
FLAG 240 400 0
FLAG 464 320 0
FLAG 464 144 0
FLAG -16 320 0
FLAG 0 224 0
FLAG -144 144 0
FLAG 560 144 0
FLAG -144 32 IN
FLAG 560 32 OUT
TEXT 504 368 Left 2 !.tran 5m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\25cfb85bd944_Exp_4.asc
* Generated by LTspice 26.0.1 for Windows.
Q1 N001 N004 0 0 BC547B
VBE N003 0 3
R1 N004 N003 1K
VCE N002 0 5 Rser=0.001
R2 N002 N001 1K
.model NPN NPN
.model PNP PNP
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.bjt
.dc VBE 0 1 0.1 VCE 0 5 1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 336 -16 224 -16
WIRE 512 -16 416 -16
WIRE 224 96 224 -16
WIRE 512 96 512 -16
WIRE 16 144 -128 144
WIRE 160 144 96 144
WIRE -128 192 -128 144
WIRE -128 304 -128 272
WIRE 224 304 224 192
WIRE 224 304 -128 304
WIRE 368 304 224 304
WIRE 512 304 512 176
WIRE 512 304 368 304
SYMBOL npn 160 96 R0
SYMATTR InstName Q1
SYMATTR Value BC547B
SYMBOL voltage -128 176 R0
SYMATTR InstName VBE
SYMATTR Value 3
SYMBOL res 432 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 1K
SYMBOL res 112 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1K
SYMBOL voltage 512 80 R0
WINDOW 123 0 0 Left 0
WINDOW 39 24 124 Left 2
SYMATTR InstName VCE
SYMATTR Value 5
SYMATTR SpiceLine Rser=0.001
FLAG 368 304 0
TEXT -162 328 Left 2 !.dc VBE 0 1 0.1 VCE 0 5 1
* Z:\home\khalils\Downloads\files\data\raw_asc\6a790f9cfc78_nand.asc
* Generated by LTspice 26.0.1 for Windows.
M4 N001 b out N001 PMOS l=200n w=400n
V2 N001 0 1
M1 out a N002 0 NMOS l=200n w=200n
M2 N002 b 0 0 NMOS l=200n w=200n
V3 b 0 PULSE(0 1 0 0.1n 0.1n 5n 10n)
M3 N001 a out N001 PMOS l=200n w=400n
V1 a 0 PULSE(0 1 0 0.1n 0.1n 10n 20n)
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.lib /Users/young/Documents/LTspice/90nm_bulk.pm
.tran 0 30n 0 0.1n
.meas TRAN tr TRIG v(in)=0.5 FALL=3 TARG v(out)=0.5 RISE=2
.meas TRAN tf TRIG v(in)=0.5 FALL=2 TARG v(out)=0.5 RISE=1
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1244 680
WIRE 272 -32 128 -32
WIRE 496 -32 272 -32
WIRE 640 -32 496 -32
WIRE 960 -32 640 -32
WIRE 272 16 272 -32
WIRE 272 16 128 16
WIRE 640 16 640 -32
WIRE 640 16 496 16
WIRE 448 96 448 48
WIRE 448 96 224 96
WIRE 960 128 960 -32
WIRE 128 176 128 64
WIRE 304 176 128 176
WIRE 496 176 496 64
WIRE 496 176 304 176
WIRE 704 176 496 176
WIRE 304 224 304 176
WIRE -208 272 -304 272
WIRE 80 272 80 48
WIRE 80 272 -208 272
WIRE 192 272 80 272
WIRE 432 272 304 272
WIRE -208 304 -208 272
WIRE 192 304 192 272
WIRE 256 304 192 304
WIRE -208 384 -416 384
WIRE 304 400 304 320
WIRE -208 448 -304 448
WIRE 224 448 224 96
WIRE 224 448 -208 448
WIRE 256 448 224 448
WIRE 432 448 432 272
WIRE 432 448 304 448
WIRE -208 464 -208 448
WIRE 256 480 256 448
WIRE 304 544 304 496
WIRE 304 544 224 544
WIRE 432 544 432 448
WIRE 432 544 304 544
WIRE 960 544 960 208
WIRE 960 544 432 544
WIRE 304 560 304 544
WIRE -416 608 -416 384
WIRE -208 608 -208 544
WIRE -208 608 -416 608
WIRE 224 608 224 544
WIRE 224 608 -208 608
IOPIN 704 176 Out
IOPIN -304 272 In
IOPIN -304 448 In
SYMBOL pmos4 448 -32 R0
SYMATTR InstName M4
SYMATTR Value2 l=200n w=400n
SYMBOL voltage -208 288 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0.1n 0.1n 10n 20n)
SYMBOL pmos4 80 -32 R0
SYMATTR InstName M3
SYMATTR Value2 l=200n w=400n
SYMBOL voltage -208 448 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value PULSE(0 1 0 0.1n 0.1n 5n 10n)
SYMBOL nmos4 256 400 R0
SYMATTR InstName M2
SYMATTR Value2 l=200n w=200n
SYMBOL nmos4 256 224 R0
SYMATTR InstName M1
SYMATTR Value2 l=200n w=200n
SYMBOL voltage 960 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 1
FLAG 704 176 out
FLAG -304 272 a
FLAG -304 448 b
FLAG 304 560 0
TEXT 544 312 Left 2 !.lib /Users/young/Documents/LTspice/90nm_bulk.pm
TEXT 552 360 Left 2 !.tran 0 30n 0 0.1n
TEXT 560 416 Left 2 !.meas TRAN tr TRIG v(in)=0.5 FALL=3 TARG v(out)=0.5 RISE=2
TEXT 560 456 Left 2 !.meas TRAN tf TRIG v(in)=0.5 FALL=2 TARG v(out)=0.5 RISE=1
* Z:\home\khalils\Downloads\files\data\raw_asc\250f3d45fda5_TRR-5.asc
* Generated by LTspice 26.0.1 for Windows.
D1 a b RFN2L6S
R1 b 0 500
V1 a 0 PULSE(200 -200 1u 5n 5n 9u 20u) Rser=10
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.tran 6u
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE -176 128 -208 128
WIRE -112 128 -176 128
WIRE 16 128 -48 128
WIRE 32 128 16 128
WIRE -208 176 -208 128
WIRE 32 176 32 128
WIRE -208 304 -208 256
WIRE -80 304 -208 304
WIRE 32 304 32 256
WIRE 32 304 -80 304
WIRE -80 320 -80 304
FLAG -80 320 0
FLAG -176 128 a
FLAG 16 128 b
SYMBOL diode -112 144 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RFN2L6S
SYMBOL Misc\\EuropeanResistor 16 160 R0
SYMATTR InstName R1
SYMATTR Value 500
SYMBOL voltage -208 160 R0
WINDOW 3 10 105 Invisible 2
WINDOW 123 0 0 Left 2
SYMATTR Value PULSE(200 -200 1u 5n 5n 9u 20u)
SYMATTR SpiceLine Rser=10
SYMATTR InstName V1
TEXT -208 320 Left 2 !.tran 6u
* Z:\tmp\asc_dec_bjh7r6w2\05361c32bfeb_llc_5th_eq_vo-vg_and_Zin_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
B11 N001 N004 V={krs} * I(V_SNS_IC)
B9 N010 N011 I={Omega_s * C } * V(V_SNS_VS)
E3 V_SNS_VS 0 N002 N003 1
V_SNS_IC N011 N012 0
C3 N010 N011 {C}
E1 N005 0 Vg N009 {4/pi}
Vg Vg N009 AC 1
B1 0 N007 I={ks} * I(V_SNS_IS)
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 2152 800
WIRE 544 -336 384 -336
WIRE 544 -288 544 -336
WIRE -80 -240 -176 -240
WIRE 48 -240 0 -240
WIRE 48 -224 48 -240
WIRE -64 -192 -192 -192
WIRE 80 -192 -16 -192
WIRE 544 -160 544 -208
WIRE -192 -128 -192 -192
WIRE -80 -128 -192 -128
WIRE 80 -128 80 -192
WIRE 80 -128 -16 -128
WIRE -672 -16 -768 -16
WIRE -448 -16 -592 -16
WIRE -192 -16 -192 -128
WIRE 80 -16 80 -128
WIRE 384 -16 384 -336
WIRE 800 -16 688 -16
WIRE 1040 -16 800 -16
WIRE -768 32 -768 -16
WIRE 544 32 544 -80
WIRE 800 32 800 -16
WIRE -816 48 -976 48
WIRE 688 64 688 -16
WIRE -976 96 -976 48
WIRE -816 96 -848 96
WIRE -768 144 -768 112
WIRE -144 144 -768 144
WIRE 544 144 544 112
WIRE 544 144 -144 144
WIRE -144 176 -144 144
WIRE 544 176 544 144
WIRE 688 208 688 144
WIRE 800 208 800 112
WIRE 800 208 688 208
WIRE 1040 208 800 208
WIRE 688 240 688 208
WIRE -976 256 -976 176
WIRE -848 256 -848 96
WIRE -848 256 -976 256
WIRE -976 288 -976 256
WIRE -768 320 -768 144
WIRE -192 320 -384 320
WIRE -96 320 -192 320
WIRE 80 320 -16 320
WIRE 176 320 80 320
WIRE 384 320 256 320
WIRE 544 352 544 256
WIRE -192 432 -192 320
WIRE -80 432 -192 432
WIRE 80 432 80 320
WIRE 80 432 -16 432
WIRE -80 544 -160 544
WIRE 48 544 0 544
WIRE 48 560 48 544
WIRE -192 592 -192 432
WIRE -64 592 -192 592
WIRE 80 592 80 432
WIRE 80 592 -16 592
SYMBOL bv 544 -304 R0
SYMATTR InstName B11
SYMATTR Value V={krs} * I(V_SNS_IC)
SYMBOL bi2 -16 320 R90
WINDOW 0 -32 40 VBottom 2
WINDOW 3 32 40 VTop 2
SYMATTR InstName B9
SYMATTR Value I={Omega_s * C } * V(V_SNS_VS)
SYMBOL e -96 -240 R270
SYMATTR InstName E3
SYMATTR Value 1
SYMBOL voltage 160 320 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
SYMATTR InstName V_SNS_IC
SYMATTR Value 0
SYMBOL cap -80 448 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName C3
SYMATTR Value {C}
SYMBOL e -768 16 R0
SYMATTR InstName E1
SYMATTR Value {4/pi}
SYMBOL voltage -976 80 R0
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value2 AC 1
SYMATTR InstName Vg
SYMATTR Value ""
SYMBOL bi2 688 64 R0
SYMATTR InstName B1
SYMATTR Value I={ks} * I(V_SNS_IS)
FLAG -144 176 0
FLAG 688 240 0
FLAG 48 -224 0
FLAG -176 -240 V_SNS_VS
FLAG 48 560 0
FLAG -160 544 V_SNS_VC
FLAG -976 48 Vg
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP5304-2.asc
* Generated by LTspice 26.0.1 for Windows.
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP5304-2.asy)
Rload OUT 0 80
R1 OUT N001 1Meg
L1 N002 OUT 2.2 Rser=80m
V1 IN 0 5
C1 OUT 0 10
XU1 IN IN 0 0 OUT N001 0 0 N002 ADP5304-2 ;pnba EN)PVin)Mode)VID)FB)VinOK)Pgnd)Agnd)SW
.tran .6m startup
.lib ADP5304-2.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 880 680
WIRE 144 64 64 64
WIRE 160 64 144 64
WIRE 480 64 416 64
WIRE 608 64 560 64
WIRE 64 80 64 64
WIRE 144 144 144 64
WIRE 160 144 144 144
WIRE 448 144 416 144
WIRE 560 144 528 144
WIRE 608 144 608 64
WIRE 608 144 560 144
WIRE 688 144 608 144
WIRE 608 160 608 144
WIRE 688 160 688 144
WIRE 64 176 64 160
WIRE 160 224 144 224
WIRE 560 224 560 144
WIRE 560 224 416 224
WIRE 608 256 608 224
WIRE 688 256 688 240
WIRE 160 304 144 304
WIRE 432 304 416 304
WIRE 288 384 288 368
SYMBOL ind 432 160 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=80m
SYMBOL ADP5304-2 288 192 R0
SYMATTR InstName U1
SYMBOL res 576 48 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 1Meg
SYMBOL res 672 144 R0
SYMATTR Value 80
SYMATTR InstName Rload
SYMBOL voltage 64 64 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL cap 592 160 R0
SYMATTR InstName C1
SYMATTR Value 10
FLAG 608 256 0
FLAG 432 304 0
FLAG 64 176 0
FLAG 688 144 OUT
FLAG 688 256 0
FLAG 64 64 IN
FLAG 288 384 0
FLAG 144 304 0
FLAG 144 224 0
TEXT 440 384 Left 2 !.tran .6m startup
* Z:\home\khalils\Downloads\files\data\raw_asc\ADP7104-2.5.asc
* Generated by LTspice 26.0.1 for Windows.
V1 IN 0 PWL(0 0 20u 3.5)
Rload OUT 0 7
C1 OUT 0 2.2 Rser=1.5m
R1 OUT N001 100k
XU1 IN OUT IN N001 OUT 0 ADP7104-2.5 ;pnba Vin)Sense)EN)PG)Vout)GND
.tran 3m startup
* Library below included based on ModelFile attribute of instance XU1 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\ADP7104-2.5.asy)
.lib ADP7104-2.5.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1048 680
WIRE 80 32 -160 32
WIRE 96 32 80 32
WIRE 368 32 352 32
WIRE 464 32 448 32
WIRE -160 48 -160 32
WIRE 368 128 352 128
WIRE 464 128 464 32
WIRE 464 128 368 128
WIRE 560 128 464 128
WIRE -160 144 -160 128
WIRE 464 144 464 128
WIRE 560 144 560 128
WIRE 80 224 80 32
WIRE 96 224 80 224
WIRE 368 224 368 128
WIRE 368 224 352 224
WIRE 464 240 464 208
WIRE 560 240 560 224
WIRE 224 304 224 288
FLAG 224 304 0
FLAG -160 144 0
FLAG 560 240 0
FLAG 464 240 0
FLAG -160 32 IN
FLAG 560 128 OUT
SYMBOL voltage -160 32 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PWL(0 0 20u 3.5)
SYMBOL res 544 128 R0
SYMATTR InstName Rload
SYMATTR Value 7
SYMBOL cap 448 144 R0
SYMATTR InstName C1
SYMATTR Value 2.2
SYMATTR SpiceLine Rser=1.5m
SYMBOL res 464 16 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL ADP7104-2.5 224 128 R0
SYMATTR InstName U1
TEXT 432 288 Left 2 !.tran 3m startup
* Z:\tmp\asc_dec_bjh7r6w2\041af22a3cbd_Draft9_dec0.asc
* Generated by LTspice 26.0.1 for Windows.
C1 0 N001 20p
V2 N002 N001 {Vtest}
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1300 680
WIRE -80 -48 -112 -48
WIRE 16 -48 0 -48
WIRE 128 -48 96 -48
WIRE -112 64 -112 -48
WIRE -32 64 -112 64
WIRE 128 64 128 -48
WIRE 128 64 32 64
WIRE -112 160 -112 64
WIRE -112 160 -176 160
WIRE -80 160 -112 160
WIRE 16 160 -16 160
WIRE 128 160 128 64
WIRE 128 160 16 160
WIRE 16 240 16 160
SYMBOL cap -16 144 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 20p
SYMBOL voltage 16 -48 R90
WINDOW 0 -32 56 VBottom 2
WINDOW 3 32 56 VTop 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value {Vtest}
FLAG 16 240 0