* Z:\home\khalils\Downloads\files\data\raw_asc\LT8277.asc
* Generated by LTspice 26.0.1 for Windows.
* Variable definition\n \nCLKOUT --> Clock out Pin Phase, 0 for 45deg, 1 for 90deg\nCLKOUT_EN --> Enable Clock Out, 0 for Disable, 1 for Enable\nPH2_LL --> Phase 2 Light Load Enable, 0 for Disable, 1 for Enable\nSS --> Enables the 4x faster soft start, 0 for Disable, 1 for Enable\n \nt0, v0 to t9, v9 --> 10 pairs of PWL settings\n \nNote: All 10 pairs must be defined whether the programming features \n are used or not.\n Just make the remaining voltage setting at same level.\n \n t0 must not be lower than 200us, this is to ensure that the first \n command will not be ignored. During this time, the part is still \n initializing the Enable and INTVcc\n \n The time interval between 2 set points must not be lower than 3us\n to allow time for capturing the set value and not greater than 32ms\n else, the Watchdog Timer will expire (for FLOATED and HIGH modes)\n \n A pulse, used to represent a valid CRC is generated to reset \n the WDT in sync with the time set on t0 to t9. After t9, no more \n command can be sent and thus WDT expires after 32ms.\n \n Communication pins are not modeled.
* Library below included based on ModelFile attribute of instance XU2 (C:\users\khalils\AppData\Local\LTspice\lib\sym\PowerProducts\LT8277.asy)
XU2 IN IN IN N001 N003 IN NC_01 NC_02 NC_03 0 NC_04 N011 N008 N007 N010 OUT N005 N006 0 N007 LT8277 CLKOUT=1 CLKOUT_EN=1 SS=1 PH2_LL=0 t0=30m v0=30 t1=50m v1=60 t2=65m v2=45 t3=75m v3=50 t4=85m v4=40 t5=95m v5=35 t6=115m v6=55 t7=125m v7=48 t8=135m v8=32 t9=150m v9=52 ;pnba VIN)EN/UVLO)SNSP1)SNSN1)SNSN2)SNSP2)SDI)_CS)SCK)SYNC/SPRD)CLKOUT)RT)VC)MODE)PGOOD)VOUT)GATE1)GATE2)GND)INTVCC
V1 IN 0 25
M1 N002 N005 0 0 BSC028N06LS3
D2 N004 OUT RB085BM-90
L2 N003 N004 10
D1 N002 OUT RB085BM-90
R2 N003 IN 10m
R4 N009 N008 10K
C3 N007 0 4.7
R6 N011 0 200K
R5 N007 N010 100K
R1 N001 IN 10m
L1 N001 N002 10
RLOAD OUT 0 30.1
C1 OUT 0 10 m=5
M2 N004 N006 0 0 BSC028N06LS3
C2 0 N009 22n
.model D D
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.dio
.model NMOS NMOS
.model PMOS PMOS
.lib C:\users\khalils\AppData\Local\LTspice\lib\cmp\standard.mos
.tran 21m startup
.lib LT8277.sub
.backanno
.end

* LTspice schematic (.asc):
Version 4
SHEET 1 1740 868
WIRE -96 -352 -112 -352
WIRE -16 -352 -96 -352
WIRE 64 -352 -16 -352
WIRE 256 -352 144 -352
WIRE 496 -352 336 -352
WIRE 784 -352 496 -352
WIRE 960 -352 848 -352
WIRE 1024 -352 960 -352
WIRE 1120 -352 1024 -352
WIRE 1136 -352 1120 -352
WIRE 1024 -320 1024 -352
WIRE 1136 -320 1136 -352
WIRE -112 -288 -112 -352
WIRE -16 -256 -16 -352
WIRE 240 -256 -16 -256
WIRE 368 -256 320 -256
WIRE 736 -256 448 -256
WIRE 784 -256 736 -256
WIRE 960 -256 960 -352
WIRE 960 -256 848 -256
WIRE 1024 -208 1024 -256
WIRE 1136 -208 1136 -240
WIRE 496 -192 496 -352
WIRE 64 -176 64 -352
WIRE 144 -176 144 -352
WIRE 240 -176 240 -256
WIRE 320 -176 320 -256
WIRE -112 -160 -112 -208
WIRE -16 -112 -16 -256
WIRE 0 -112 -16 -112
WIRE 448 -112 384 -112
WIRE 736 -112 736 -256
WIRE 496 -64 496 -96
WIRE -16 -32 -16 -112
WIRE 0 -32 -16 -32
WIRE 688 -32 384 -32
WIRE 736 16 736 -16
WIRE -96 48 -112 48
WIRE -16 48 -32 48
WIRE 0 48 -16 48
WIRE 960 48 960 -256
WIRE 960 48 384 48
WIRE -16 128 -16 48
WIRE 0 128 -16 128
WIRE 448 128 384 128
WIRE 560 128 528 128
WIRE 672 128 624 128
WIRE 416 208 384 208
WIRE 592 208 496 208
WIRE 416 368 384 368
WIRE 528 368 496 368
WIRE 96 448 96 432
WIRE 304 448 304 432
WIRE -16 480 -16 128
WIRE 592 480 592 208
WIRE 592 480 -16 480
SYMBOL LT8277 192 128 R0
WINDOW 39 -5 383 Center 2
WINDOW 40 -17 421 Bottom 2
SYMATTR InstName U2
SYMBOL res 512 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 100K
SYMBOL res 336 -272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 10m
SYMBOL ind 352 -240 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L2
SYMATTR Value 10
SYMBOL cap 1008 -320 R0
WINDOW 0 36 7 Left 2
WINDOW 3 35 55 Left 2
WINDOW 123 37 32 Left 2
SYMATTR InstName C1
SYMATTR Value 10
SYMATTR Value2 m=5
SYMBOL res 160 -368 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 10m
SYMBOL ind 240 -336 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName L1
SYMATTR Value 10
SYMBOL res 1120 -336 R0
SYMATTR InstName RLOAD
SYMATTR Value 30.1
SYMBOL res 544 112 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL schottky 784 -336 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value RB085BM-90
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL nmos 448 -192 R0
SYMATTR InstName M1
SYMATTR Value BSC028N06LS3
SYMBOL nmos 688 -112 R0
SYMATTR InstName M2
SYMATTR Value BSC028N06LS3
SYMBOL voltage -112 -304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 25
SYMBOL schottky 784 -240 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value RB085BM-90
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL cap 624 112 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 22n
SYMBOL cap -32 32 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C3
SYMATTR Value 4.7
SYMBOL res 400 352 M90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R6
SYMATTR Value 200K
FLAG -112 -160 0
FLAG 496 -64 0
FLAG 736 16 0
FLAG 1024 -208 0
FLAG 1136 -208 0
FLAG 672 128 0
FLAG -112 48 0
FLAG 304 448 0
FLAG 96 448 0
FLAG 528 368 0
FLAG -96 -352 IN
FLAG 1120 -352 OUT
TEXT 80 576 Left 2 !.tran 21m startup
TEXT 848 152 Left 2 ;Variable definition\n \nCLKOUT --> Clock out Pin Phase, 0 for 45deg, 1 for 90deg\nCLKOUT_EN --> Enable Clock Out, 0 for Disable, 1 for Enable\nPH2_LL --> Phase 2 Light Load Enable, 0 for Disable, 1 for Enable\nSS --> Enables the 4x faster soft start, 0 for Disable, 1 for Enable\n \nt0, v0 to t9, v9 --> 10 pairs of PWL settings\n \nNote: All 10 pairs must be defined whether the programming features \n          are used or not.\n          Just make the remaining voltage setting at same level.\n \n          t0 must not be lower than 200us, this is to ensure that the first \n          command will not be ignored. During this time, the part is still \n          initializing the Enable and INTVcc\n \n          The time interval between 2 set points must not be lower than 3us\n          to allow time for capturing the set value and not greater than 32ms\n          else, the Watchdog Timer will expire (for FLOATED and HIGH modes)\n \n          A pulse, used to represent a valid CRC is generated to reset \n          the WDT in sync with the time set on t0 to t9. After t9, no more \n          command can be sent and thus WDT expires after 32ms.\n \n          Communication pins are not modeled.