* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act}) Rser=100 Cpar=10fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 N001 ra0 mb0 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N002 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n) Rser=2048 Cpar=0.6pF
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act}) Rser=100 Cpar=10fF
Vra1 ra1 0 PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_1 N002 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
R1 N001 bitline0 {mc(bitline_R, process_var)}
R2 bitline1 N002 {mc(bitline_R, process_var)}
M12 N001 ra1 mb1 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_1 mb1 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell1_charge}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n) Rser=2048 Cpar=0.6pf
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
Vra3 ra2 0 PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M13 N001 ra2 mb2 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_3 mb2 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell2_charge}
Vra4 ra4 0 PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M14 N001 ra4 mb4 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_4 mb4 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell3_charge}
Vra5 ra5 0 PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M15 N001 ra5 mb5 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_5 mb5 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell4_charge}
Vra6 ra6 0 PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M16 N001 ra6 mb6 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_6 mb6 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell5_charge}
Vra7 ra7 0 PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M17 N001 ra7 mb7 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_7 mb7 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell6_charge}
Vra8 ra8 0 PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} 20n) Rser=2048 Cpar=0.6pf
M18 N001 ra8 mb8 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_8 mb8 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell7_charge}
VDD_source1 PV 0 {plate_voltage}
.include ../DRAM_models/transistor_model.pm
.tran 120ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=1024
.param core_voltage=0.95V
.param wordline_voltage=2.5V
.param cell0_charge=core_voltage*cells_charge_state
.param cell1_charge=core_voltage*cells_charge_state
.param cell2_charge=core_voltage*cells_charge_state
.param cell3_charge=core_voltage*cells_charge_state
.param cell4_charge=core_voltage*cells_charge_state
.param cell5_charge=core_voltage*cells_charge_state
.param cell6_charge=core_voltage*cells_charge_state
.param cell7_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param wl1_act=1.0
.param wl2_act=1.0
.param wl3_act=1.0
.param wl4_act=1.0
.param wl5_act=1.0
.param wl6_act=1.0
.param wl7_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.93**tech_node}

* LTspice schematic (.asc)
Version 4
SHEET 1 2944 5264
WIRE 880 -2632 576 -2632
WIRE 576 -2600 576 -2632
WIRE 416 -2520 208 -2520
WIRE 528 -2520 416 -2520
WIRE 576 -2376 576 -2504
WIRE 576 -2360 576 -2376
WIRE 576 -2264 576 -2296
WIRE 880 -2200 880 -2632
WIRE 880 -2200 576 -2200
WIRE 576 -2168 576 -2200
WIRE 416 -2088 208 -2088
WIRE 528 -2088 416 -2088
WIRE 576 -1944 576 -2072
WIRE 576 -1928 576 -1944
WIRE 576 -1832 576 -1864
WIRE 880 -1752 880 -2200
WIRE 880 -1752 576 -1752
WIRE 576 -1720 576 -1752
WIRE 416 -1640 208 -1640
WIRE 528 -1640 416 -1640
WIRE 576 -1496 576 -1624
WIRE 576 -1480 576 -1496
WIRE 576 -1384 576 -1416
WIRE 880 -1304 880 -1752
WIRE 880 -1304 576 -1304
WIRE 576 -1272 576 -1304
WIRE 416 -1192 208 -1192
WIRE 528 -1192 416 -1192
WIRE 576 -1048 576 -1176
WIRE 576 -1032 576 -1048
WIRE 576 -936 576 -968
WIRE 880 -808 880 -1304
WIRE 880 -808 576 -808
WIRE 576 -776 576 -808
WIRE 416 -696 208 -696
WIRE 528 -696 416 -696
WIRE 576 -552 576 -680
WIRE 576 -536 576 -552
WIRE 576 -440 576 -472
WIRE -688 -408 -688 -424
WIRE -1344 -376 -1344 -392
WIRE -688 -312 -688 -328
WIRE 880 -296 880 -808
WIRE 880 -296 576 -296
WIRE -1344 -280 -1344 -296
WIRE 576 -264 576 -296
WIRE 416 -184 208 -184
WIRE 528 -184 416 -184
WIRE -1344 -104 -1344 -120
WIRE -688 -104 -688 -120
WIRE 576 -40 576 -168
WIRE 576 -24 576 -40
WIRE -1344 -8 -1344 -24
WIRE -688 -8 -688 -24
WIRE 576 72 576 40
WIRE 880 216 880 -296
WIRE 880 216 576 216
WIRE 576 248 576 216
WIRE -1344 264 -1344 248
WIRE -720 264 -720 248
WIRE 416 328 208 328
WIRE 528 328 416 328
WIRE -1344 360 -1344 344
WIRE -720 360 -720 344
WIRE 576 472 576 344
WIRE 576 488 576 472
WIRE -1280 552 -1280 536
WIRE -720 552 -720 536
WIRE 576 584 576 552
WIRE -1280 648 -1280 632
WIRE -720 648 -720 632
WIRE 880 808 880 216
WIRE 880 808 736 808
WIRE 736 840 736 808
WIRE 416 920 208 920
WIRE 688 920 416 920
WIRE 736 968 736 936
WIRE 736 968 496 968
WIRE -496 1048 -496 1016
WIRE -128 1048 -128 1016
WIRE 496 1048 496 968
WIRE -1472 1064 -1472 1048
WIRE 496 1064 496 1048
WIRE -992 1080 -992 1064
WIRE -1472 1160 -1472 1144
WIRE -496 1160 -496 1128
WIRE -128 1160 -128 1128
WIRE -992 1176 -992 1160
WIRE 496 1224 496 1128
WIRE 880 1352 880 808
WIRE 944 1352 880 1352
WIRE 880 1432 880 1352
WIRE 544 1464 496 1464
WIRE 752 1464 544 1464
WIRE 944 1544 800 1544
WIRE 1024 1544 944 1544
WIRE 1152 1544 1024 1544
WIRE -688 1576 -688 1544
WIRE -400 1576 -400 1544
WIRE -96 1576 -96 1544
WIRE 944 1576 944 1544
WIRE 1152 1576 1152 1544
WIRE 1024 1592 992 1592
WIRE 1104 1592 1072 1592
WIRE 1424 1672 1232 1672
WIRE -688 1688 -688 1656
WIRE -400 1688 -400 1656
WIRE -96 1688 -96 1656
WIRE 880 1688 880 1512
WIRE 944 1688 944 1672
WIRE 944 1688 880 1688
WIRE 1024 1688 1072 1592
WIRE 1024 1688 944 1688
WIRE 1072 1688 1024 1592
WIRE 1152 1688 1152 1672
WIRE 1152 1688 1072 1688
WIRE 1232 1688 1232 1672
WIRE 1232 1688 1152 1688
WIRE 880 1784 880 1688
WIRE 1024 1784 880 1784
WIRE 1232 1784 1232 1688
WIRE 1232 1784 1120 1784
WIRE 752 1832 720 1832
WIRE 992 1832 752 1832
WIRE 1040 1832 992 1832
WIRE 1168 1832 1040 1832
WIRE 1408 1832 1168 1832
WIRE 992 1848 992 1832
WIRE 1168 1848 1168 1832
WIRE 880 1880 880 1784
WIRE 880 1896 880 1880
WIRE 912 1896 880 1896
WIRE 1056 1896 1008 1896
WIRE 1088 1896 1056 1896
WIRE 1232 1896 1232 1784
WIRE 1232 1896 1184 1896
WIRE 1424 1896 1424 1672
WIRE 1232 1912 1232 1896
WIRE 1056 1944 1056 1896
WIRE 1056 1960 1056 1944
WIRE 880 2008 880 1896
WIRE 944 2008 880 2008
WIRE 1024 2008 944 2008
WIRE 1152 2008 1088 2008
WIRE 1232 2008 1232 1912
WIRE 1232 2008 1152 2008
WIRE 944 2024 944 2008
WIRE 1152 2024 1152 2008
WIRE 1424 2056 1424 1976
WIRE 1472 2056 1424 2056
WIRE 1024 2104 1088 2008
WIRE 1024 2104 992 2104
WIRE 1088 2104 1024 2008
WIRE 1104 2104 1088 2104
WIRE 1472 2104 1472 2056
WIRE 944 2152 944 2120
WIRE 944 2152 832 2152
WIRE 1072 2152 944 2152
WIRE 1152 2152 1152 2120
WIRE 1152 2152 1072 2152
WIRE 784 2232 528 2232
WIRE 1424 2328 1424 2056
WIRE 1424 2328 1312 2328
WIRE 1312 2360 1312 2328
WIRE 1200 2472 992 2472
WIRE 1264 2472 1264 2440
WIRE 1264 2472 1200 2472
WIRE 1312 2504 1312 2456
WIRE 1312 2520 1312 2504
WIRE 1424 2632 1424 2328
FLAG -992 1176 0
FLAG -992 1064 Eq
FLAG 832 2200 0
FLAG -496 1160 0
FLAG -496 1016 sense_P
FLAG 1152 2072 0
FLAG 944 2072 0
FLAG 1072 1784 0
FLAG 960 1896 0
FLAG 1136 1896 0
FLAG 752 1832 Eq
FLAG 1056 1944 VDDby2
FLAG 528 2232 sense_N
FLAG 832 2248 0
FLAG 880 1880 bitline0
FLAG 1232 1912 bitline1
FLAG 736 888 0
FLAG 496 1048 mb0
FLAG 416 920 ra0
FLAG 1312 2408 0
FLAG 1312 2584 0
FLAG 1312 2504 mb3
FLAG 1200 2472 ra3
FLAG -1280 648 0
FLAG -1280 536 ra0
FLAG 800 1496 VDD
FLAG 1152 1624 VDD
FLAG 944 1624 VDD
FLAG 800 1448 VDD
FLAG 544 1464 sense_p
FLAG 1024 1544 ACT
FLAG 1072 2152 NLAT
FLAG -128 1160 0
FLAG -128 1016 sense_N
FLAG -720 536 ra1
FLAG -720 648 0
FLAG 944 1416 0
FLAG 1472 2168 0
FLAG 576 296 0
FLAG 576 472 mb1
FLAG 416 328 ra1
FLAG -1472 1048 ra3
FLAG -1472 1160 0
FLAG -688 1688 0
FLAG -688 1544 VDD
FLAG -400 1688 0
FLAG -400 1544 VDDby2
FLAG -720 248 ra2
FLAG -720 360 0
FLAG 576 -216 0
FLAG 576 -40 mb2
FLAG 416 -184 ra2
FLAG -1344 248 ra4
FLAG -1344 360 0
FLAG 576 -728 0
FLAG 576 -552 mb4
FLAG 416 -696 ra4
FLAG -1344 -120 ra5
FLAG -1344 -8 0
FLAG 576 -1224 0
FLAG 576 -1048 mb5
FLAG 416 -1192 ra5
FLAG -688 -120 ra6
FLAG -688 -8 0
FLAG 576 -1672 0
FLAG 576 -1496 mb6
FLAG 416 -1640 ra6
FLAG -1344 -392 ra7
FLAG -1344 -280 0
FLAG 576 -2120 0
FLAG 576 -1944 mb7
FLAG 416 -2088 ra7
FLAG -688 -424 ra8
FLAG -688 -312 0
FLAG 576 -2552 0
FLAG 576 -2376 mb8
FLAG 416 -2520 ra8
FLAG 576 -2264 PV
FLAG 576 -1832 PV
FLAG 576 -1384 PV
FLAG 576 -936 PV
FLAG 576 -440 PV
FLAG 576 72 PV
FLAG 576 584 PV
FLAG 496 1224 PV
FLAG -96 1688 0
FLAG -96 1544 PV
SYMBOL nmos4 784 2152 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -992 1064 R0
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage -496 1032 R0
SYMATTR SpiceLine Rser=100 Cpar=10fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act})
SYMATTR InstName Vsp
SYMBOL nmos4 1104 2024 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 992 2024 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 1120 1832 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 912 1848 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1088 1848 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 688 840 R0
SYMATTR InstName M7
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 480 1064 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 1264 2360 R0
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1296 2520 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -1280 536 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pF
SYMBOL pmos4 752 1544 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 1104 1672 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 992 1672 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage -128 1032 R0
SYMATTR SpiceLine Rser=100 Cpar=10fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act})
SYMATTR InstName Vsn
SYMBOL voltage -720 536 R0
SYMATTR InstName Vra1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL cap 928 1352 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 1456 2104 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 864 1416 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 1408 1880 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL nmos4 528 248 R0
SYMATTR InstName M12
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 488 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_1
SYMATTR SpiceLine IC={-plate_voltage + cell1_charge}
SYMBOL voltage -1472 1048 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL voltage -688 1560 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -400 1560 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage -720 248 R0
SYMATTR InstName Vra3
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 528 -264 R0
SYMATTR InstName M13
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 -24 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_3
SYMATTR SpiceLine IC={-plate_voltage + cell2_charge}
SYMBOL voltage -1344 248 R0
SYMATTR InstName Vra4
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 528 -776 R0
SYMATTR InstName M14
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 -536 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_4
SYMATTR SpiceLine IC={-plate_voltage + cell3_charge}
SYMBOL voltage -1344 -120 R0
SYMATTR InstName Vra5
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 528 -1272 R0
SYMATTR InstName M15
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 -1032 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_5
SYMATTR SpiceLine IC={-plate_voltage + cell4_charge}
SYMBOL voltage -688 -120 R0
SYMATTR InstName Vra6
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 528 -1720 R0
SYMATTR InstName M16
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 -1480 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_6
SYMATTR SpiceLine IC={-plate_voltage + cell5_charge}
SYMBOL voltage -1344 -392 R0
SYMATTR InstName Vra7
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 528 -2168 R0
SYMATTR InstName M17
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 -1928 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_7
SYMATTR SpiceLine IC={-plate_voltage + cell6_charge}
SYMBOL voltage -688 -424 R0
SYMATTR InstName Vra8
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} 20n)
SYMATTR SpiceLine Rser=2048 Cpar=0.6pf
SYMBOL nmos4 528 -2600 R0
SYMATTR InstName M18
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 560 -2360 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_8
SYMATTR SpiceLine IC={-plate_voltage + cell7_charge}
SYMBOL voltage -96 1560 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1