* SPICE netlist
MSU2 N002 N002 VDD VDD P_50n L=1u W=500n
MSU1 N002 Vbiasn 0 0 N_50n l=50n w=500n
MSU3 VDD N002 Vbiasn 0 N_50n L=50n W=500n
M3 Vbiasn Vbiasp VDD VDD P_50n l=50n w=1u
M4 N003 Vbiasp VDD VDD P_50n l=50n w=1u
M1 Vbiasn Vbiasn 0 0 N_50n l=50n w=500n
R1 N004 0 4k
MA4 Vbiasp N001 VDD VDD P_50n l=100n w=1u
MA3 N001 N001 VDD VDD P_50n l=100n w=1u
M5 N001 N003 0 0 N_50n l=100n w=500n
M7 VDD Vbiasp VDD VDD P_50n l=5u w=5u
M2 Vbiasp Vbiasn 0 0 N_50n l=100n w=500n
M6 N003 N003 N004 0 N_50n l=50n w=2u
VDD VDD 0 5
.dc VDD 0 1.2
.include cmosedu_models.txt

* LTspice schematic (.asc)
Version 4
SHEET 1 1344 608
WIRE -400 -288 -400 -304
WIRE 64 -272 48 -272
WIRE 128 -272 64 -272
WIRE -400 -176 -400 -208
WIRE 0 -176 0 -192
WIRE 64 -176 64 -272
WIRE 64 -176 0 -176
WIRE -672 -160 -672 -256
WIRE 656 -160 640 -160
WIRE -608 -144 -624 -144
WIRE 176 -144 176 -192
WIRE 176 -144 -160 -144
WIRE 288 -144 176 -144
WIRE 320 -144 288 -144
WIRE -528 -128 -528 -160
WIRE 368 -64 368 -80
WIRE -672 -48 -672 -64
WIRE -608 -48 -608 -144
WIRE -608 -48 -672 -48
WIRE -576 -48 -608 -48
WIRE 288 -48 288 -144
WIRE 640 -48 640 -112
WIRE 640 -48 288 -48
WIRE 672 -48 640 -48
WIRE -528 -32 -528 -48
WIRE -208 -32 -208 -64
WIRE -208 -32 -368 -32
WIRE 368 32 368 -64
WIRE 368 32 64 32
WIRE -208 64 -208 -32
WIRE 112 64 -208 64
WIRE 672 64 112 64
WIRE -208 80 -208 64
WIRE -144 80 -208 80
WIRE 0 80 0 -176
WIRE 176 80 176 -144
WIRE 368 80 368 32
WIRE 368 80 304 80
WIRE -672 96 -672 -48
WIRE -208 96 -208 80
WIRE 0 96 0 80
WIRE 176 96 176 80
WIRE -144 160 -144 80
WIRE -144 160 -160 160
WIRE 64 160 64 32
WIRE 64 160 48 160
WIRE 112 160 112 64
WIRE 128 160 112 160
WIRE 304 160 304 80
WIRE 320 160 304 160
WIRE -528 176 -528 -32
WIRE -528 176 -624 176
WIRE -368 176 -368 -32
WIRE -368 176 -528 176
WIRE -208 176 -208 160
WIRE 0 176 0 160
WIRE 176 176 176 160
WIRE 368 176 368 160
WIRE -672 192 -672 176
WIRE 368 192 368 176
WIRE -208 208 -208 176
WIRE 0 208 0 176
WIRE 176 208 176 176
WIRE -672 288 -672 192
WIRE 368 304 368 272
FLAG -672 -112 VDD
FLAG -528 -160 VDD
FLAG -208 -112 VDD
FLAG -208 -160 VDD
FLAG 368 -112 VDD
FLAG 368 -160 VDD
FLAG 368 304 0
FLAG 368 128 0
FLAG 176 -240 VDD
FLAG 176 -288 VDD
FLAG 0 -240 VDD
FLAG 0 -288 VDD
FLAG 176 128 0
FLAG 608 -160 VDD
FLAG 560 -160 VDD
FLAG 656 -160 VDD
FLAG -672 -256 VDD
IOPIN 544 -272 In
FLAG -672 288 GND
IOPIN 544 272 In
FLAG -528 -80 0
FLAG -672 144 0
FLAG -208 208 0
FLAG -208 128 0
FLAG 0 128 0
FLAG 0 208 0
FLAG 176 208 0
FLAG 672 -48 Vbiasp
IOPIN 1888 -64 Out
FLAG 672 64 Vbiasn
IOPIN 1888 48 Out
FLAG -400 -176 0
FLAG -400 -304 VDD
SYMBOL pmos4 -624 -64 R180
SYMATTR InstName MSU2
SYMATTR Value2 L=1u W=500n
SYMATTR Value P_50n
SYMBOL nmos4 -624 96 M0
SYMATTR Value2 l=50n w=500n
SYMATTR InstName MSU1
SYMATTR Value N_50n
SYMBOL nmos4 -576 -128 R0
SYMATTR Value2 L=50n W=500n
SYMATTR InstName MSU3
SYMATTR Value N_50n
SYMBOL pmos4 -160 -64 R180
SYMATTR InstName M3
SYMATTR Value2 l=50n w=1u
SYMATTR Value P_50n
SYMBOL pmos4 320 -64 M180
SYMATTR InstName M4
SYMATTR Value2 l=50n w=1u
SYMATTR Value P_50n
SYMBOL nmos4 -160 80 M0
SYMATTR Value2 l=50n w=500n
SYMATTR InstName M1
SYMATTR Value N_50n
SYMBOL res 352 176 R0
SYMATTR InstName R1
SYMATTR Value 4k
SYMBOL pmos4 128 -192 M180
SYMATTR InstName MA4
SYMATTR Value2 l=100n w=1u
SYMATTR Value P_50n
SYMBOL pmos4 48 -192 R180
SYMATTR InstName MA3
SYMATTR Value2 l=100n w=1u
SYMATTR Value P_50n
SYMBOL nmos4 48 80 M0
SYMATTR Value2 l=100n w=500n
SYMATTR InstName M5
SYMATTR Value N_50n
SYMBOL pmos4 560 -112 R270
SYMATTR InstName M7
SYMATTR Value2 l=5u w=5u
SYMATTR Value P_50n
SYMBOL nmos4 128 80 R0
SYMATTR Value2 l=100n w=500n
SYMATTR InstName M2
SYMATTR Value N_50n
SYMBOL nmos4 320 80 R0
SYMATTR Value2 l=50n w=2u
SYMATTR InstName M6
SYMATTR Value N_50n
SYMBOL voltage -400 -304 R0
SYMATTR InstName VDD
SYMATTR Value 5