* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act}) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 N003 ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N007 ra3 mb3 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} {wl0_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act}) Rser=100 Cpar=1fF
CBL_cap_0 N003 0 {mc(short_bitline_cap, process_var)} IC={core_voltage/2}
R1 N003 bitline0 {mc(short_bitline_R, process_var)}
R2 bitline1 N006 {mc(short_bitline_R, process_var)}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
VDD_source1 PV 0 {plate_voltage}
M19 bitline0 CSEL N005 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M20 bitline1 CSEL N004 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
Vwrite0 write0 0 PULSE(0 {wr0_voltage} 5n) Rser=100 Cpar=1fF
Vwrite1 write1 0 PULSE(0 {wr1_voltage} 5n) Rser=100 Cpar=1fF
M21 N004 write1 0 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M22 N004 write1 VDD VDD PMOS l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
M23 N005 write0 0 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M24 N005 write0 VDD VDD PMOS l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
Vcsel CSEL 0 PULSE(0 {core_voltage*2} {20n + csel_act}) Rser=100 Cpar=1fF
CBL_cap_2 N001 0 {mc(long_bitline_cap, process_var)} IC={core_voltage/2}
M12 N002 isol_tran N003 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
M13 N001 ra1 mb1 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_1 mb1 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell1_charge}
R4 N001 N002 {mc(long_bitline_R, process_var)}
Vra1 ra1 0 PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Visol_tran isol_tran 0 PULSE(0 {wordline_voltage} {isol_tran_act}) Rser=100 Cpar=1fF
R3 N006 N007 {mc(long_bitline_R, process_var)}
CBL_cap_1 N007 0 {mc(long_bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_3 N007 0 {mc(short_bitline_cap, process_var)} IC={core_voltage/2}
.include ../DRAM_models/transistor_model.pm
.tran 220ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param short_bitline_cap={F_per_cell*cells_per_BL_short}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param short_bitline_R={R_per_cell*cells_per_BL_short}
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={255nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={255nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL={cells_per_BL_short + cells_per_BL_long}
.param core_voltage=0.95V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cell0_charge_state
.param cell1_charge=core_voltage*other_cells_charge_state
.param cell0_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=0.0
.param wl1_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=1024
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.param wr0_voltage=0V
.param wr1_voltage=0V
.param other_cells_charge_state=0.8
.param wl0_act_time=20ns
.param other_wls_act_time=20ns
.param SA_nWR_L={70nm*SA_nWR_L_factor}
.param SA_nWR_W={840nm*SA_nWR_W_factor}
.param SA_nWR_L_factor={0.93**tech_node}
.param SA_nWR_W_factor={0.93**tech_node}
.param SA_pWR_L={70nm*SA_pWR_L_factor}
.param SA_pWR_W={840nm*SA_pWR_W_factor}
.param csel_act=400ns
.param SA_pWR_L_factor={0.93**tech_node}
.param SA_pWR_W_factor={0.93**tech_node}
.param F_per_cell=0.0815fF
.param long_bitline_cap={F_per_cell*cells_per_BL_long}
.param cells_per_BL_short=8
.param cells_per_BL_long=1016
.param long_bitline_R={R_per_cell*cells_per_BL_long}
.param isol_tran_act=0ns

* LTspice schematic (.asc)
Version 4
SHEET 1 4496 2416
WIRE 1144 -1208 1016 -1208
WIRE -2248 -1176 -2248 -1192
WIRE 1016 -1144 1016 -1208
WIRE 1144 -1112 1144 -1208
WIRE 1272 -1112 1144 -1112
WIRE -2248 -1080 -2248 -1096
WIRE 696 -1064 488 -1064
WIRE 968 -1064 696 -1064
WIRE 1016 -1016 1016 -1048
WIRE 1016 -1016 776 -1016
WIRE 1144 -952 1144 -1112
WIRE 776 -936 776 -1016
WIRE 776 -920 776 -936
WIRE -2184 -904 -2184 -920
WIRE -1016 -872 -1016 -888
WIRE -2184 -808 -2184 -824
WIRE 1144 -808 1144 -872
WIRE -1016 -776 -1016 -792
WIRE 776 -760 776 -856
WIRE 1224 -728 1192 -728
WIRE 1144 -616 1144 -712
WIRE 1144 -616 1000 -616
WIRE 1000 -584 1000 -616
WIRE 680 -504 472 -504
WIRE 952 -504 680 -504
WIRE 1000 -456 1000 -488
WIRE 1000 -456 760 -456
WIRE -232 -376 -232 -408
WIRE 136 -376 136 -408
WIRE 760 -376 760 -456
WIRE 760 -360 760 -376
WIRE -1896 -344 -1896 -360
WIRE -1320 -344 -1320 -360
WIRE -728 -344 -728 -360
WIRE 1144 -328 1144 -616
WIRE 1256 -328 1144 -328
WIRE -232 -264 -232 -296
WIRE 136 -264 136 -296
WIRE -1896 -248 -1896 -264
WIRE -1320 -248 -1320 -264
WIRE -728 -248 -728 -264
WIRE 760 -200 760 -296
WIRE 1144 -168 1144 -328
WIRE 808 40 760 40
WIRE 1016 40 808 40
WIRE 1208 120 1064 120
WIRE 1288 120 1208 120
WIRE 1416 120 1288 120
WIRE -1400 136 -1400 104
WIRE -1032 136 -1032 104
WIRE -424 152 -424 120
WIRE -136 152 -136 120
WIRE 168 152 168 120
WIRE 1208 152 1208 120
WIRE 1416 152 1416 120
WIRE 1288 168 1256 168
WIRE 1368 168 1336 168
WIRE 2184 200 2136 200
WIRE -1400 248 -1400 216
WIRE -1032 248 -1032 216
WIRE 1688 248 1496 248
WIRE -424 264 -424 232
WIRE -136 264 -136 232
WIRE 168 264 168 232
WIRE 1144 264 1144 -88
WIRE 1208 264 1208 248
WIRE 1208 264 1144 264
WIRE 1288 264 1336 168
WIRE 1288 264 1208 264
WIRE 1336 264 1288 168
WIRE 1416 264 1416 248
WIRE 1416 264 1336 264
WIRE 1496 264 1496 248
WIRE 1496 264 1416 264
WIRE 1848 280 1848 232
WIRE 1688 328 1688 248
WIRE 1768 328 1688 328
WIRE 2088 328 2088 280
WIRE 2088 328 1864 328
WIRE 2184 328 2184 200
WIRE 2248 328 2184 328
WIRE 1144 360 1144 264
WIRE 1288 360 1144 360
WIRE 1496 360 1496 264
WIRE 1496 360 1384 360
WIRE 2088 392 2088 328
WIRE 1016 408 984 408
WIRE 1256 408 1016 408
WIRE 1304 408 1256 408
WIRE 1432 408 1304 408
WIRE 1672 408 1432 408
WIRE 1256 424 1256 408
WIRE 1432 424 1432 408
WIRE 520 456 472 456
WIRE 1144 456 1144 360
WIRE 1144 472 1144 456
WIRE 1176 472 1144 472
WIRE 1320 472 1272 472
WIRE 1352 472 1320 472
WIRE 1496 472 1496 360
WIRE 1496 472 1448 472
WIRE 1688 472 1688 328
WIRE 2184 472 2184 328
WIRE 2184 472 2136 472
WIRE 1496 488 1496 472
WIRE 1320 520 1320 472
WIRE 776 536 776 488
WIRE 1320 536 1320 520
WIRE 1144 552 1144 472
WIRE 1144 552 1000 552
WIRE 472 584 472 456
WIRE 472 584 408 584
WIRE 568 584 568 536
WIRE 760 584 568 584
WIRE 1000 584 1000 552
WIRE 1000 584 856 584
WIRE 1144 584 1144 552
WIRE 1208 584 1144 584
WIRE 1288 584 1208 584
WIRE 1416 584 1352 584
WIRE 1496 584 1496 488
WIRE 1496 584 1416 584
WIRE 1688 584 1688 552
WIRE 1208 600 1208 584
WIRE 1416 600 1416 584
WIRE 568 648 568 584
WIRE 1288 680 1352 584
WIRE 1288 680 1256 680
WIRE 1352 680 1288 584
WIRE 1368 680 1352 680
WIRE 1688 712 1688 664
WIRE 1784 712 1688 712
WIRE 472 728 472 584
WIRE 520 728 472 728
WIRE 1208 728 1208 696
WIRE 1208 728 1096 728
WIRE 1336 728 1208 728
WIRE 1416 728 1416 696
WIRE 1416 728 1336 728
WIRE 1048 808 792 808
WIRE 1688 856 1688 712
WIRE 1784 856 1688 856
WIRE 1688 904 1688 856
WIRE 1688 904 1576 904
WIRE 1576 936 1576 904
WIRE 1464 1048 1256 1048
WIRE 1528 1048 1528 1016
WIRE 1528 1048 1464 1048
WIRE 1576 1080 1576 1032
WIRE 1576 1096 1576 1080
WIRE 1688 1208 1688 904
FLAG -728 -248 0
FLAG -728 -360 Eq
FLAG 1096 776 0
FLAG -232 -264 0
FLAG -232 -408 sense_P
FLAG 1416 648 0
FLAG 1208 648 0
FLAG 1336 360 0
FLAG 1224 472 0
FLAG 1400 472 0
FLAG 1016 408 Eq
FLAG 1320 520 VDDby2
FLAG 792 808 sense_N
FLAG 1096 824 0
FLAG 1144 456 bitline0
FLAG 1496 488 bitline1
FLAG 1000 -536 0
FLAG 760 -376 mb0
FLAG 680 -504 ra0
FLAG 1576 984 0
FLAG 1576 1160 0
FLAG 1576 1080 mb3
FLAG 1464 1048 ra3
FLAG -1016 -776 0
FLAG -1016 -888 ra0
FLAG 1064 72 VDD
FLAG 1416 200 VDD
FLAG 1208 200 VDD
FLAG 1064 24 VDD
FLAG 808 40 sense_p
FLAG 1288 120 ACT
FLAG 1336 728 NLAT
FLAG 136 -264 0
FLAG 136 -408 sense_N
FLAG 1256 -264 0
FLAG -2248 -1192 ra3
FLAG -2248 -1080 0
FLAG -424 264 0
FLAG -424 120 VDD
FLAG -136 264 0
FLAG -136 120 VDDby2
FLAG 760 -200 PV
FLAG 168 264 0
FLAG 168 120 PV
FLAG 776 488 CSEL
FLAG 808 584 0
FLAG 1816 328 0
FLAG -1400 248 0
FLAG -1400 104 write0
FLAG -1032 248 0
FLAG -1032 104 write1
FLAG 2088 488 0
FLAG 2088 232 VDD
FLAG 2088 184 VDD
FLAG 2088 440 0
FLAG 1848 232 CSEL
FLAG 2248 328 write1
FLAG 568 744 0
FLAG 568 488 VDD
FLAG 568 440 VDD
FLAG 568 696 0
FLAG 408 584 write0
FLAG -1320 -248 0
FLAG -1320 -360 CSEL
FLAG 1272 -1048 0
FLAG 1016 -1096 0
FLAG 776 -936 mb1
FLAG 696 -1064 ra1
FLAG 776 -760 PV
FLAG -2184 -808 0
FLAG -2184 -920 ra1
FLAG 1224 -728 isol_tran
FLAG 1144 -760 0
FLAG -1896 -248 0
FLAG -1896 -360 isol_tran
FLAG 1784 920 0
FLAG 1784 776 0
SYMBOL nmos4 1048 728 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -728 -360 R0
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage -232 -392 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act})
SYMATTR InstName Vsp
SYMBOL nmos4 1368 600 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 1256 600 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 1384 408 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 1176 424 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1352 424 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 952 -584 R0
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 744 -360 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 1528 936 R0
SYMATTR InstName M8
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1560 1096 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -1016 -888 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} {wl0_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 1016 120 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 1368 248 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 1256 248 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage 136 -392 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act})
SYMATTR InstName Vsn
SYMBOL cap 1240 -328 R0
SYMATTR Value {mc(short_bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 1128 -184 R0
SYMATTR Value {mc(short_bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 1672 456 R0
SYMATTR Value {mc(short_bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -2248 -1192 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -424 136 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -136 136 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage 168 136 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 856 536 R90
SYMATTR InstName M19
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL nmos4 1768 280 M90
SYMATTR InstName M20
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL voltage -1400 120 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {wr0_voltage} 5n)
SYMATTR InstName Vwrite0
SYMBOL voltage -1032 120 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {wr1_voltage} 5n)
SYMATTR InstName Vwrite1
SYMBOL nmos4 2136 392 M0
SYMATTR InstName M21
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL pmos4 2136 280 R180
SYMATTR InstName M22
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL nmos4 520 648 R0
SYMATTR InstName M23
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL pmos4 520 536 M180
SYMATTR InstName M24
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL voltage -1320 -360 R0
SYMATTR InstName Vcsel
SYMATTR Value PULSE(0 {core_voltage*2} {20n + csel_act})
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMBOL cap 1256 -1112 R0
SYMATTR Value {mc(long_bitline_cap, process_var)}
SYMATTR InstName BL_cap_2
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL nmos4 1192 -808 M0
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL nmos4 968 -1144 R0
SYMATTR InstName M13
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 760 -920 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_1
SYMATTR SpiceLine IC={-plate_voltage + cell1_charge}
SYMBOL res 1128 -968 R0
SYMATTR Value {mc(long_bitline_R, process_var)}
SYMATTR InstName R4
SYMBOL voltage -2184 -920 R0
SYMATTR InstName Vra1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -1896 -360 R0
SYMATTR InstName Visol_tran
SYMATTR Value PULSE(0 {wordline_voltage} {isol_tran_act})
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMBOL res 1672 568 R0
SYMATTR Value {mc(long_bitline_R, process_var)}
SYMATTR InstName R3
SYMBOL cap 1768 856 R0
SYMATTR Value {mc(long_bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 1768 712 R0
SYMATTR Value {mc(short_bitline_cap, process_var)}
SYMATTR InstName BL_cap_3
SYMATTR SpiceLine IC={core_voltage/2}