* SPICE netlist
VDD VDD 0 PULSE(0 1 50n 10p)
MSU2 VDD N002 N002 VDD P_50n L=1u W=500n
MSU1 N002 Vbiasn 0 0 N_50n L=100n W=2.5u
MSU3 Vbiasp N002 Vbiasn 0 N_50n L=50n W=500n
M3 VDD Vbiasp Vbiasn VDD P_50n l=100n w=5u
M4 VDD Vbiasp N003 VDD P_50n l=100n w=5u
M1 Vbiasn Vbiasn 0 0 N_50n L=100n W=2.5u
M2 N003 N003 N004 0 N_50n l=100n w=10u
R1 N004 0 5.5k
MA4 VDD N001 Vbiasp VDD P_50n l=100n w=5u
MA3 VDD N001 N001 VDD P_50n l=100n w=5u
M5 N001 N003 0 0 N_50n L=100n W=2.5u
M6 Vbiasp Vbiasn 0 0 N_50n L=100n W=2.5u
M7 VDD 0 VDD VDD P_50n l=5u w=5u
M8 0 0 0 0 N_50n l=5u w=5u
.tran 500n

* LTspice schematic (.asc)
Version 4
SHEET 1 1632 512
WIRE -816 -160 -816 -192
WIRE -816 -144 -816 -160
WIRE -544 -96 -544 -112
WIRE -544 48 -544 -96
WIRE -544 176 -544 144
WIRE -480 -128 -496 -128
WIRE -480 -96 -544 -96
WIRE -480 -96 -480 -128
WIRE -448 -96 -480 -96
WIRE -400 -176 -400 -208
WIRE -400 128 -496 128
WIRE -400 128 -400 -80
WIRE -240 128 -400 128
WIRE -240 128 -240 -80
WIRE -80 -80 -240 -80
WIRE -80 -80 -80 -112
WIRE -80 16 -80 -80
WIRE -80 32 -80 16
WIRE -80 160 -80 128
WIRE -16 32 -80 32
WIRE -16 112 -32 112
WIRE -16 112 -16 32
WIRE 128 -144 128 -160
WIRE 128 32 128 -144
WIRE 128 160 128 128
WIRE 176 -144 128 -144
WIRE 176 -144 176 -176
WIRE 192 112 176 112
WIRE 192 112 192 -16
WIRE 240 16 -80 16
WIRE 240 112 240 16
WIRE 256 -176 176 -176
WIRE 256 112 240 112
WIRE 304 -128 -32 -128
WIRE 304 -128 304 -160
WIRE 304 32 304 -128
WIRE 304 160 304 128
WIRE 416 -128 304 -128
WIRE 416 -96 416 -128
WIRE 432 112 432 32
WIRE 448 -128 416 -128
WIRE 448 112 432 112
WIRE 496 -16 192 -16
WIRE 496 -16 496 -112
WIRE 496 32 432 32
WIRE 496 32 496 -16
WIRE 496 144 496 128
WIRE 496 256 496 224
WIRE 768 -96 416 -96
WIRE 768 16 240 16
FLAG -816 -64 0
FLAG -816 -160 VDD
FLAG -544 -160 VDD
FLAG -544 -208 VDD
FLAG -544 176 0
FLAG -544 96 0
FLAG -400 -128 0
FLAG -400 -208 Vbiasp
FLAG -80 -160 VDD
FLAG -80 -208 VDD
FLAG 496 -160 VDD
FLAG 496 -208 VDD
FLAG 768 -96 Vbiasp
FLAG -80 160 0
FLAG -80 80 0
FLAG 496 256 0
FLAG 496 80 0
FLAG 768 16 Vbiasn
FLAG 304 -208 VDD
FLAG 304 -256 VDD
FLAG 128 -208 VDD
FLAG 128 -256 VDD
FLAG 128 80 0
FLAG 304 80 0
FLAG 128 160 0
FLAG 304 160 0
FLAG 704 -208 VDD
FLAG 656 -208 VDD
FLAG 752 -208 VDD
FLAG 768 160 0
FLAG 720 160 0
FLAG 816 160 0
FLAG 736 112 0
FLAG 736 -160 0
SYMBOL voltage -816 -160 R0
SYMATTR InstName VDD
SYMATTR Value PULSE(0 1 50n 10p)
SYMBOL pmos4 -496 -208 M0
SYMATTR InstName MSU2
SYMATTR Value2 L=1u W=500n
SYMATTR Value P_50n
SYMBOL nmos4 -496 48 M0
SYMATTR Value2 L=100n W=2.5u
SYMATTR InstName MSU1
SYMATTR Value N_50n
SYMBOL nmos4 -448 -176 R0
SYMATTR Value2 L=50n W=500n
SYMATTR InstName MSU3
SYMATTR Value N_50n
SYMBOL pmos4 -32 -208 M0
SYMATTR InstName M3
SYMATTR Value2 l=100n w=5u
SYMATTR Value P_50n
SYMBOL pmos4 448 -208 R0
SYMATTR InstName M4
SYMATTR Value2 l=100n w=5u
SYMATTR Value P_50n
SYMBOL nmos4 -32 32 M0
SYMATTR Value2 L=100n W=2.5u
SYMATTR InstName M1
SYMATTR Value N_50n
SYMBOL nmos4 448 32 R0
SYMATTR Value2 l=100n w=10u
SYMATTR InstName M2
SYMATTR Value N_50n
SYMBOL res 480 128 R0
SYMATTR InstName R1
SYMATTR Value 5.5k
SYMBOL pmos4 256 -256 R0
SYMATTR InstName MA4
SYMATTR Value2 l=100n w=5u
SYMATTR Value P_50n
SYMBOL pmos4 176 -256 M0
SYMATTR InstName MA3
SYMATTR Value2 l=100n w=5u
SYMATTR Value P_50n
SYMBOL nmos4 176 32 M0
SYMATTR Value2 L=100n W=2.5u
SYMATTR InstName M5
SYMATTR Value N_50n
SYMBOL nmos4 256 32 R0
SYMATTR Value2 L=100n W=2.5u
SYMATTR InstName M6
SYMATTR Value N_50n
SYMBOL pmos4 656 -160 R270
SYMATTR InstName M7
SYMATTR Value2 l=5u w=5u
SYMATTR Value P_50n
SYMBOL nmos4 816 112 R90
SYMATTR Value2 l=5u w=5u
SYMATTR InstName M8
SYMATTR Value N_50n