* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 2n 2n 14n)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 2n 2n) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 N001 ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N002 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 2n 2n) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 2n 2n) Rser=100 Cpar=1fF
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_1 N002 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
R1 N001 bitline0 {mc(bitline_R, process_var)}
R2 bitline1 N002 {mc(bitline_R, process_var)}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 2n 2n) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
VDD_source1 PV 0 {plate_voltage}
.include ./transistor_model.pm
.tran 120ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=512
.param core_voltage=1.1V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=512
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}

* LTspice schematic (.asc)
Version 4
SHEET 1 2944 2096
WIRE -1280 -1032 -1280 -1048
WIRE -1280 -936 -1280 -952
WIRE 880 -776 736 -776
WIRE 736 -744 736 -776
WIRE 416 -664 208 -664
WIRE 688 -664 416 -664
WIRE 736 -616 736 -648
WIRE 736 -616 496 -616
WIRE -496 -536 -496 -568
WIRE -128 -536 -128 -568
WIRE 496 -536 496 -616
WIRE -1472 -520 -1472 -536
WIRE 496 -520 496 -536
WIRE -992 -504 -992 -520
WIRE -1472 -424 -1472 -440
WIRE -496 -424 -496 -456
WIRE -128 -424 -128 -456
WIRE -992 -408 -992 -424
WIRE 496 -360 496 -456
WIRE 880 -232 880 -776
WIRE 944 -232 880 -232
WIRE 880 -152 880 -232
WIRE 544 -120 496 -120
WIRE 752 -120 544 -120
WIRE 944 -40 800 -40
WIRE 1024 -40 944 -40
WIRE 1152 -40 1024 -40
WIRE -688 -8 -688 -40
WIRE -400 -8 -400 -40
WIRE -96 -8 -96 -40
WIRE 944 -8 944 -40
WIRE 1152 -8 1152 -40
WIRE 1024 8 992 8
WIRE 1104 8 1072 8
WIRE 1424 88 1232 88
WIRE -688 104 -688 72
WIRE -400 104 -400 72
WIRE -96 104 -96 72
WIRE 880 104 880 -72
WIRE 944 104 944 88
WIRE 944 104 880 104
WIRE 1024 104 1072 8
WIRE 1024 104 944 104
WIRE 1072 104 1024 8
WIRE 1152 104 1152 88
WIRE 1152 104 1072 104
WIRE 1232 104 1232 88
WIRE 1232 104 1152 104
WIRE 880 200 880 104
WIRE 1024 200 880 200
WIRE 1232 200 1232 104
WIRE 1232 200 1120 200
WIRE 752 248 720 248
WIRE 992 248 752 248
WIRE 1040 248 992 248
WIRE 1168 248 1040 248
WIRE 1408 248 1168 248
WIRE 992 264 992 248
WIRE 1168 264 1168 248
WIRE 880 296 880 200
WIRE 880 312 880 296
WIRE 912 312 880 312
WIRE 1056 312 1008 312
WIRE 1088 312 1056 312
WIRE 1232 312 1232 200
WIRE 1232 312 1184 312
WIRE 1424 312 1424 88
WIRE 1232 328 1232 312
WIRE 1056 360 1056 312
WIRE 1056 376 1056 360
WIRE 880 424 880 312
WIRE 944 424 880 424
WIRE 1024 424 944 424
WIRE 1152 424 1088 424
WIRE 1232 424 1232 328
WIRE 1232 424 1152 424
WIRE 944 440 944 424
WIRE 1152 440 1152 424
WIRE 1424 472 1424 392
WIRE 1472 472 1424 472
WIRE 1024 520 1088 424
WIRE 1024 520 992 520
WIRE 1088 520 1024 424
WIRE 1104 520 1088 520
WIRE 1472 520 1472 472
WIRE 944 568 944 536
WIRE 944 568 832 568
WIRE 1072 568 944 568
WIRE 1152 568 1152 536
WIRE 1152 568 1072 568
WIRE 784 648 528 648
WIRE 1424 744 1424 472
WIRE 1424 744 1312 744
WIRE 1312 776 1312 744
WIRE 1200 888 992 888
WIRE 1264 888 1264 856
WIRE 1264 888 1200 888
WIRE 1312 920 1312 872
WIRE 1312 936 1312 920
WIRE 1424 1048 1424 744
FLAG -992 -408 0
FLAG -992 -520 Eq
FLAG 832 616 0
FLAG -496 -424 0
FLAG -496 -568 sense_P
FLAG 1152 488 0
FLAG 944 488 0
FLAG 1072 200 0
FLAG 960 312 0
FLAG 1136 312 0
FLAG 752 248 Eq
FLAG 1056 360 VDDby2
FLAG 528 648 sense_N
FLAG 832 664 0
FLAG 880 296 bitline0
FLAG 1232 328 bitline1
FLAG 736 -696 0
FLAG 496 -536 mb0
FLAG 416 -664 ra0
FLAG 1312 824 0
FLAG 1312 1000 0
FLAG 1312 920 mb3
FLAG 1200 888 ra3
FLAG -1280 -936 0
FLAG -1280 -1048 ra0
FLAG 800 -88 VDD
FLAG 1152 40 VDD
FLAG 944 40 VDD
FLAG 800 -136 VDD
FLAG 544 -120 sense_p
FLAG 1024 -40 ACT
FLAG 1072 568 NLAT
FLAG -128 -424 0
FLAG -128 -568 sense_N
FLAG 944 -168 0
FLAG 1472 584 0
FLAG -1472 -536 ra3
FLAG -1472 -424 0
FLAG -688 104 0
FLAG -688 -40 VDD
FLAG -400 104 0
FLAG -400 -40 VDDby2
FLAG 496 -360 PV
FLAG -96 104 0
FLAG -96 -40 PV
SYMBOL nmos4 784 568 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -992 -520 R0
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 2n 2n 14n)
SYMBOL voltage -496 -552 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 2n 2n)
SYMATTR InstName Vsp
SYMBOL nmos4 1104 440 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 992 440 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 1120 248 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 912 264 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1088 264 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 688 -744 R0
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 480 -520 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 1264 776 R0
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1296 936 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -1280 -1048 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 2n 2n)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 752 -40 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 1104 88 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 992 88 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage -128 -552 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 2n 2n)
SYMATTR InstName Vsn
SYMBOL cap 928 -232 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 1456 520 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 864 -168 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 1408 296 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -1472 -536 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 2n 2n)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -688 -24 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -400 -24 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage -96 -24 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1