* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq1 Eq1 0 PULSE({core_voltage*1.2} {core_voltage*1.2} 0 0 0 0)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 0 0) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq2 bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq2 VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq2 bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 bitline ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N001 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 0 0) Rser=100 Cpar=1fF
CBL_cap_0 bitline 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_1 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
R1 bitline bitline0 {mc(bitline_R, process_var)}
R2 bitline1 N001 {mc(bitline_R, process_var)}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
VDD_source1 PV 0 {plate_voltage}
M12 NC_01 bl_en NC_02 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vbl_en bl_en 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Veq0 Eq0 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
Veq2 Eq2 0 PULSE(0 0 0 0 0 0)
CBL_starting_value_cap bl_ival 0 10f V=1
R3 bl_ival bl_ival 1m
.include ./transistor_model.pm
.tran 120ns uic
.param process_var=0.25
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=512
.param core_voltage=1.1V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=512
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.ic V(bitline)=1

* LTspice schematic (.asc)
Version 4
SHEET 1 5888 2608
WIRE -80 -1288 -80 -1304
WIRE -80 -1192 -80 -1208
WIRE -80 -1048 -80 -1064
WIRE -80 -952 -80 -968
WIRE 2112 -936 2080 -936
WIRE 2176 -936 2112 -936
WIRE 2080 -840 2080 -856
WIRE 2176 -840 2176 -936
WIRE 2176 -840 2080 -840
WIRE 2080 -792 1936 -792
WIRE 1936 -760 1936 -792
WIRE 1616 -680 1408 -680
WIRE 1888 -680 1616 -680
WIRE 1936 -632 1936 -664
WIRE 1936 -632 1696 -632
WIRE 704 -552 704 -584
WIRE 1072 -552 1072 -584
WIRE 1696 -552 1696 -632
WIRE -272 -536 -272 -552
WIRE 1696 -536 1696 -552
WIRE -2944 -504 -2944 -520
WIRE -2192 -504 -2192 -520
WIRE -1264 -504 -1264 -520
WIRE -272 -440 -272 -456
WIRE 704 -440 704 -472
WIRE 1072 -440 1072 -472
WIRE -2944 -408 -2944 -424
WIRE -2192 -408 -2192 -424
WIRE -1264 -408 -1264 -424
WIRE 1696 -376 1696 -472
WIRE 2080 -248 2080 -792
WIRE 2144 -248 2080 -248
WIRE 2080 -56 2080 -248
WIRE 512 -24 512 -56
WIRE 800 -24 800 -56
WIRE 1104 -24 1104 -56
WIRE 2768 40 2720 40
WIRE 2896 40 2768 40
WIRE 512 88 512 56
WIRE 800 88 800 56
WIRE 1104 88 1104 56
WIRE 2080 104 2080 -56
WIRE 1744 136 1696 136
WIRE 1952 136 1744 136
WIRE 2144 216 2000 216
WIRE 2224 216 2144 216
WIRE 2352 216 2224 216
WIRE 2144 248 2144 216
WIRE 2352 248 2352 216
WIRE 2224 264 2192 264
WIRE 2304 264 2272 264
WIRE 2624 344 2432 344
WIRE 2080 360 2080 184
WIRE 2144 360 2144 344
WIRE 2144 360 2080 360
WIRE 2224 360 2272 264
WIRE 2224 360 2144 360
WIRE 2272 360 2224 264
WIRE 2352 360 2352 344
WIRE 2352 360 2272 360
WIRE 2432 360 2432 344
WIRE 2432 360 2352 360
WIRE 2080 456 2080 360
WIRE 2224 456 2080 456
WIRE 2432 456 2432 360
WIRE 2432 456 2320 456
WIRE 1952 504 1920 504
WIRE 2192 504 1952 504
WIRE 2240 504 2192 504
WIRE 2368 504 2240 504
WIRE 2608 504 2368 504
WIRE 2192 520 2192 504
WIRE 2368 520 2368 504
WIRE 2080 552 2080 456
WIRE 2080 568 2080 552
WIRE 2112 568 2080 568
WIRE 2256 568 2208 568
WIRE 2288 568 2256 568
WIRE 2432 568 2432 456
WIRE 2432 568 2384 568
WIRE 2624 568 2624 344
WIRE 2432 584 2432 568
WIRE 2256 616 2256 568
WIRE 2256 632 2256 616
WIRE 2080 680 2080 568
WIRE 2144 680 2080 680
WIRE 2224 680 2144 680
WIRE 2352 680 2288 680
WIRE 2432 680 2432 584
WIRE 2432 680 2352 680
WIRE 2144 696 2144 680
WIRE 2352 696 2352 680
WIRE 2624 728 2624 648
WIRE 2672 728 2624 728
WIRE 2224 776 2288 680
WIRE 2224 776 2192 776
WIRE 2288 776 2224 680
WIRE 2304 776 2288 776
WIRE 2672 776 2672 728
WIRE 2144 824 2144 792
WIRE 2144 824 2032 824
WIRE 2272 824 2144 824
WIRE 2352 824 2352 792
WIRE 2352 824 2272 824
WIRE 1984 904 1728 904
WIRE 2624 1000 2624 728
WIRE 2624 1000 2512 1000
WIRE 2512 1032 2512 1000
WIRE 2400 1144 2192 1144
WIRE 2464 1144 2464 1112
WIRE 2464 1144 2400 1144
WIRE 2512 1176 2512 1128
WIRE 2512 1192 2512 1176
WIRE 2624 1304 2624 1000
FLAG -2192 -408 0
FLAG -2192 -520 Eq1
FLAG 2032 872 0
FLAG 704 -440 0
FLAG 704 -584 sense_P
FLAG 2352 744 0
FLAG 2144 744 0
FLAG 2272 456 0
FLAG 2160 568 0
FLAG 2336 568 0
FLAG 1952 504 Eq2
FLAG 2256 616 VDDby2
FLAG 1728 904 sense_N
FLAG 2032 920 0
FLAG 2080 552 bitline0
FLAG 2432 584 bitline1
FLAG 1936 -712 0
FLAG 1696 -552 mb0
FLAG 1616 -680 ra0
FLAG 2512 1080 0
FLAG 2512 1256 0
FLAG 2512 1176 mb3
FLAG 2400 1144 ra3
FLAG -80 -952 0
FLAG -80 -1064 ra0
FLAG 2000 168 VDD
FLAG 2352 296 VDD
FLAG 2144 296 VDD
FLAG 2000 120 VDD
FLAG 1744 136 sense_p
FLAG 2224 216 ACT
FLAG 2272 824 NLAT
FLAG 1072 -440 0
FLAG 1072 -584 sense_N
FLAG 2144 -184 0
FLAG 2672 840 0
FLAG -272 -552 ra3
FLAG -272 -440 0
FLAG 512 88 0
FLAG 512 -56 VDD
FLAG 800 88 0
FLAG 800 -56 VDDby2
FLAG 1696 -376 PV
FLAG 1104 88 0
FLAG 1104 -56 PV
FLAG 2944 8 0
FLAG -80 -1192 0
FLAG -80 -1304 bl_en
FLAG 2768 40 bl_en
FLAG -1264 -408 0
FLAG -1264 -520 Eq0
FLAG -2944 -408 0
FLAG -2944 -520 Eq2
FLAG 2240 -936 0
FLAG 2112 -936 bl_ival
FLAG 2080 -56 bitline
SYMBOL nmos4 1984 824 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -2192 -520 R0
SYMATTR InstName Veq1
SYMATTR Value PULSE({core_voltage*1.2} {core_voltage*1.2} 0 0 0 0)
SYMBOL voltage 704 -568 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0 0)
SYMATTR InstName Vsp
SYMBOL nmos4 2304 696 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 2192 696 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 2320 504 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 2112 520 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 2288 520 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1888 -760 R0
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1680 -536 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 2464 1032 R0
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 2496 1192 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -80 -1064 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 1952 216 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 2304 344 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 2192 344 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage 1072 -568 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 0 0)
SYMATTR InstName Vsn
SYMBOL cap 2128 -248 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 2656 776 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 2064 88 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 2608 552 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -272 -552 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage 512 -40 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage 800 -40 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage 1104 -40 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 2896 -40 R0
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -80 -1304 R0
SYMATTR InstName Vbl_en
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -1264 -520 R0
SYMATTR InstName Veq0
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage -2944 -520 R0
SYMATTR InstName Veq2
SYMATTR Value PULSE(0 0 0 0 0 0)
SYMBOL cap 2176 -920 R270
SYMATTR Value 10f
SYMATTR InstName BL_starting_value_cap
SYMATTR SpiceLine V=1
SYMBOL res 2064 -952 R0
SYMATTR InstName R3
SYMATTR Value 1m