* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act}) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 N001 ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N004 ra3 mb3 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} {wl0_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act}) Rser=100 Cpar=1fF
Vra1 ra1 0 PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_1 N004 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
R1 N001 bitline0 {mc(bitline_R, process_var)}
R2 bitline1 N004 {mc(bitline_R, process_var)}
M12 N001 ra1 mb1 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_1 mb1 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell1_charge}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
Vra3 ra2 0 PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M13 N001 ra2 mb2 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_3 mb2 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell2_charge}
Vra4 ra4 0 PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M14 N001 ra4 mb4 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_4 mb4 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell3_charge}
Vra5 ra5 0 PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M15 N001 ra5 mb5 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_5 mb5 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell4_charge}
Vra6 ra6 0 PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M16 N001 ra6 mb6 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_6 mb6 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell5_charge}
Vra7 ra7 0 PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M17 N001 ra7 mb7 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_7 mb7 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell6_charge}
Vra8 ra8 0 PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} {other_wls_act_time}) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M18 N001 ra8 mb8 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_8 mb8 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell7_charge}
VDD_source1 PV 0 {plate_voltage}
M19 bitline0 CSEL N003 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M20 bitline1 CSEL N002 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
Vwrite0 write0 0 PULSE(0 {wr0_voltage} 5n) Rser=100 Cpar=1fF
Vwrite1 write1 0 PULSE(0 {wr1_voltage} 5n) Rser=100 Cpar=1fF
M21 N002 write1 0 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M22 N002 write1 VDD VDD PMOS l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
M23 N003 write0 0 0 NMOS l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
M24 N003 write0 VDD VDD PMOS l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
Vcsel CSEL 0 PULSE(0 {core_voltage*2} {20n + csel_act}) Rser=100 Cpar=1fF
.include ../DRAM_models/transistor_model.pm
.tran 220ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={255nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={255nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=1024
.param core_voltage=0.95V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cell0_charge_state
.param cell1_charge=core_voltage*other_cells_charge_state
.param cell2_charge=core_voltage*other_cells_charge_state
.param cell3_charge=core_voltage*other_cells_charge_state
.param cell4_charge=core_voltage*other_cells_charge_state
.param cell5_charge=core_voltage*other_cells_charge_state
.param cell6_charge=core_voltage*other_cells_charge_state
.param cell7_charge=core_voltage*other_cells_charge_state
.param cell0_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param wl1_act=1.0
.param wl2_act=1.0
.param wl3_act=1.0
.param wl4_act=1.0
.param wl5_act=1.0
.param wl6_act=1.0
.param wl7_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=1024
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.param wr0_voltage=0V
.param wr1_voltage=0V
.param other_cells_charge_state=0.8
.param wl0_act_time=20ns
.param other_wls_act_time=20ns
.param SA_nWR_L={70nm*SA_nWR_L_factor}
.param SA_nWR_W={840nm*SA_nWR_W_factor}
.param SA_nWR_L_factor={0.93**tech_node}
.param SA_nWR_W_factor={0.93**tech_node}
.param SA_pWR_L={70nm*SA_pWR_L_factor}
.param SA_pWR_W={840nm*SA_pWR_W_factor}
.param csel_act=400ns
.param SA_pWR_L_factor={0.93**tech_node}
.param SA_pWR_W_factor={0.93**tech_node}

* LTspice schematic (.asc)
Version 4
SHEET 1 4496 5264
WIRE 1144 -2632 840 -2632
WIRE 840 -2600 840 -2632
WIRE 680 -2520 472 -2520
WIRE 792 -2520 680 -2520
WIRE 840 -2376 840 -2504
WIRE 840 -2360 840 -2376
WIRE 840 -2264 840 -2296
WIRE 1144 -2200 1144 -2632
WIRE 1144 -2200 840 -2200
WIRE 840 -2168 840 -2200
WIRE 680 -2088 472 -2088
WIRE 792 -2088 680 -2088
WIRE 840 -1944 840 -2072
WIRE 840 -1928 840 -1944
WIRE 840 -1832 840 -1864
WIRE 1144 -1752 1144 -2200
WIRE 1144 -1752 840 -1752
WIRE 840 -1720 840 -1752
WIRE 680 -1640 472 -1640
WIRE 792 -1640 680 -1640
WIRE 840 -1496 840 -1624
WIRE 840 -1480 840 -1496
WIRE 840 -1384 840 -1416
WIRE 1144 -1304 1144 -1752
WIRE 1144 -1304 840 -1304
WIRE 840 -1272 840 -1304
WIRE 680 -1192 472 -1192
WIRE 792 -1192 680 -1192
WIRE 840 -1048 840 -1176
WIRE 840 -1032 840 -1048
WIRE 840 -936 840 -968
WIRE 1144 -808 1144 -1304
WIRE 1144 -808 840 -808
WIRE 840 -776 840 -808
WIRE 680 -696 472 -696
WIRE 792 -696 680 -696
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WIRE 840 -40 840 -168
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WIRE 840 584 840 552
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WIRE 1000 840 1000 808
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WIRE 1208 1352 1144 1352
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WIRE 1016 1464 808 1464
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WIRE 1288 1544 1208 1544
WIRE 1416 1544 1288 1544
WIRE -1400 1560 -1400 1528
WIRE -1032 1560 -1032 1528
WIRE -424 1576 -424 1544
WIRE -136 1576 -136 1544
WIRE 168 1576 168 1544
WIRE 1208 1576 1208 1544
WIRE 1416 1576 1416 1544
WIRE 1288 1592 1256 1592
WIRE 1368 1592 1336 1592
WIRE 2184 1624 2136 1624
WIRE -1400 1672 -1400 1640
WIRE -1032 1672 -1032 1640
WIRE 1688 1672 1496 1672
WIRE -424 1688 -424 1656
WIRE -136 1688 -136 1656
WIRE 168 1688 168 1656
WIRE 1144 1688 1144 1512
WIRE 1208 1688 1208 1672
WIRE 1208 1688 1144 1688
WIRE 1288 1688 1336 1592
WIRE 1288 1688 1208 1688
WIRE 1336 1688 1288 1592
WIRE 1416 1688 1416 1672
WIRE 1416 1688 1336 1688
WIRE 1496 1688 1496 1672
WIRE 1496 1688 1416 1688
WIRE 1848 1704 1848 1656
WIRE 1688 1752 1688 1672
WIRE 1768 1752 1688 1752
WIRE 2088 1752 2088 1704
WIRE 2088 1752 1864 1752
WIRE 2184 1752 2184 1624
WIRE 2248 1752 2184 1752
WIRE 1144 1784 1144 1688
WIRE 1288 1784 1144 1784
WIRE 1496 1784 1496 1688
WIRE 1496 1784 1384 1784
WIRE 2088 1816 2088 1752
WIRE 1016 1832 984 1832
WIRE 1256 1832 1016 1832
WIRE 1304 1832 1256 1832
WIRE 1432 1832 1304 1832
WIRE 1672 1832 1432 1832
WIRE 1256 1848 1256 1832
WIRE 1432 1848 1432 1832
WIRE 520 1880 472 1880
WIRE 1144 1880 1144 1784
WIRE 1144 1896 1144 1880
WIRE 1176 1896 1144 1896
WIRE 1320 1896 1272 1896
WIRE 1352 1896 1320 1896
WIRE 1496 1896 1496 1784
WIRE 1496 1896 1448 1896
WIRE 1688 1896 1688 1752
WIRE 2184 1896 2184 1752
WIRE 2184 1896 2136 1896
WIRE 1496 1912 1496 1896
WIRE 1320 1944 1320 1896
WIRE 776 1960 776 1912
WIRE 1320 1960 1320 1944
WIRE 1144 1976 1144 1896
WIRE 1144 1976 1000 1976
WIRE 472 2008 472 1880
WIRE 472 2008 408 2008
WIRE 568 2008 568 1960
WIRE 760 2008 568 2008
WIRE 1000 2008 1000 1976
WIRE 1000 2008 856 2008
WIRE 1144 2008 1144 1976
WIRE 1208 2008 1144 2008
WIRE 1288 2008 1208 2008
WIRE 1416 2008 1352 2008
WIRE 1496 2008 1496 1912
WIRE 1496 2008 1416 2008
WIRE 1208 2024 1208 2008
WIRE 1416 2024 1416 2008
WIRE 1688 2056 1688 1976
WIRE 1736 2056 1688 2056
WIRE 568 2072 568 2008
WIRE 1288 2104 1352 2008
WIRE 1288 2104 1256 2104
WIRE 1352 2104 1288 2008
WIRE 1368 2104 1352 2104
WIRE 1736 2104 1736 2056
WIRE 472 2152 472 2008
WIRE 520 2152 472 2152
WIRE 1208 2152 1208 2120
WIRE 1208 2152 1096 2152
WIRE 1336 2152 1208 2152
WIRE 1416 2152 1416 2120
WIRE 1416 2152 1336 2152
WIRE 1048 2232 792 2232
WIRE 1688 2328 1688 2056
WIRE 1688 2328 1576 2328
WIRE 1576 2360 1576 2328
WIRE 1464 2472 1256 2472
WIRE 1528 2472 1528 2440
WIRE 1528 2472 1464 2472
WIRE 1576 2504 1576 2456
WIRE 1576 2520 1576 2504
WIRE 1688 2632 1688 2328
FLAG -728 1176 0
FLAG -728 1064 Eq
FLAG 1096 2200 0
FLAG -232 1160 0
FLAG -232 1016 sense_P
FLAG 1416 2072 0
FLAG 1208 2072 0
FLAG 1336 1784 0
FLAG 1224 1896 0
FLAG 1400 1896 0
FLAG 1016 1832 Eq
FLAG 1320 1944 VDDby2
FLAG 792 2232 sense_N
FLAG 1096 2248 0
FLAG 1144 1880 bitline0
FLAG 1496 1912 bitline1
FLAG 1000 888 0
FLAG 760 1048 mb0
FLAG 680 920 ra0
FLAG 1576 2408 0
FLAG 1576 2584 0
FLAG 1576 2504 mb3
FLAG 1464 2472 ra3
FLAG -1016 648 0
FLAG -1016 536 ra0
FLAG 1064 1496 VDD
FLAG 1416 1624 VDD
FLAG 1208 1624 VDD
FLAG 1064 1448 VDD
FLAG 808 1464 sense_p
FLAG 1288 1544 ACT
FLAG 1336 2152 NLAT
FLAG 136 1160 0
FLAG 136 1016 sense_N
FLAG -456 536 ra1
FLAG -456 648 0
FLAG 1208 1416 0
FLAG 1736 2168 0
FLAG 840 296 0
FLAG 840 472 mb1
FLAG 680 328 ra1
FLAG -2248 232 ra3
FLAG -2248 344 0
FLAG -424 1688 0
FLAG -424 1544 VDD
FLAG -136 1688 0
FLAG -136 1544 VDDby2
FLAG -456 248 ra2
FLAG -456 360 0
FLAG 840 -216 0
FLAG 840 -40 mb2
FLAG 680 -184 ra2
FLAG -1080 248 ra4
FLAG -1080 360 0
FLAG 840 -728 0
FLAG 840 -552 mb4
FLAG 680 -696 ra4
FLAG -1080 -120 ra5
FLAG -1080 -8 0
FLAG 840 -1224 0
FLAG 840 -1048 mb5
FLAG 680 -1192 ra5
FLAG -424 -120 ra6
FLAG -424 -8 0
FLAG 840 -1672 0
FLAG 840 -1496 mb6
FLAG 680 -1640 ra6
FLAG -1080 -392 ra7
FLAG -1080 -280 0
FLAG 840 -2120 0
FLAG 840 -1944 mb7
FLAG 680 -2088 ra7
FLAG -424 -424 ra8
FLAG -424 -312 0
FLAG 840 -2552 0
FLAG 840 -2376 mb8
FLAG 680 -2520 ra8
FLAG 840 -2264 PV
FLAG 840 -1832 PV
FLAG 840 -1384 PV
FLAG 840 -936 PV
FLAG 840 -440 PV
FLAG 840 72 PV
FLAG 840 584 PV
FLAG 760 1224 PV
FLAG 168 1688 0
FLAG 168 1544 PV
FLAG 776 1912 CSEL
FLAG 808 2008 0
FLAG 1816 1752 0
FLAG -1400 1672 0
FLAG -1400 1528 write0
FLAG -1032 1672 0
FLAG -1032 1528 write1
FLAG 2088 1912 0
FLAG 2088 1656 VDD
FLAG 2088 1608 VDD
FLAG 2088 1864 0
FLAG 1848 1656 CSEL
FLAG 2248 1752 write1
FLAG 568 2168 0
FLAG 568 1912 VDD
FLAG 568 1864 VDD
FLAG 568 2120 0
FLAG 408 2008 write0
FLAG -1320 1176 0
FLAG -1320 1064 CSEL
SYMBOL nmos4 1048 2152 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -728 1064 R0
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage -232 1032 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act})
SYMATTR InstName Vsp
SYMBOL nmos4 1368 2024 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 1256 2024 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 1384 1832 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 1176 1848 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1352 1848 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 952 840 R0
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 744 1064 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 1528 2360 R0
SYMATTR InstName M8
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1560 2520 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -1016 536 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} {wl0_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 1016 1544 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 1368 1672 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 1256 1672 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage 136 1032 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act})
SYMATTR InstName Vsn
SYMBOL voltage -456 536 R0
SYMATTR InstName Vra1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl1_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL cap 1192 1352 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 1720 2104 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 1128 1416 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 1672 1880 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL nmos4 792 248 R0
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 488 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_1
SYMATTR SpiceLine IC={-plate_voltage + cell1_charge}
SYMBOL voltage -2248 232 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -424 1560 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -136 1560 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage -456 248 R0
SYMATTR InstName Vra3
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl2_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 792 -264 R0
SYMATTR InstName M13
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 -24 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_3
SYMATTR SpiceLine IC={-plate_voltage + cell2_charge}
SYMBOL voltage -1080 248 R0
SYMATTR InstName Vra4
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl3_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 792 -776 R0
SYMATTR InstName M14
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 -536 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_4
SYMATTR SpiceLine IC={-plate_voltage + cell3_charge}
SYMBOL voltage -1080 -120 R0
SYMATTR InstName Vra5
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl4_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 792 -1272 R0
SYMATTR InstName M15
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 -1032 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_5
SYMATTR SpiceLine IC={-plate_voltage + cell4_charge}
SYMBOL voltage -424 -120 R0
SYMATTR InstName Vra6
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl5_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 792 -1720 R0
SYMATTR InstName M16
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 -1480 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_6
SYMATTR SpiceLine IC={-plate_voltage + cell5_charge}
SYMBOL voltage -1080 -392 R0
SYMATTR InstName Vra7
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl6_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 792 -2168 R0
SYMATTR InstName M17
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 -1928 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_7
SYMATTR SpiceLine IC={-plate_voltage + cell6_charge}
SYMBOL voltage -424 -424 R0
SYMATTR InstName Vra8
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl7_act, process_var)} {other_wls_act_time})
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL nmos4 792 -2600 R0
SYMATTR InstName M18
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 824 -2360 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_8
SYMATTR SpiceLine IC={-plate_voltage + cell7_charge}
SYMBOL voltage 168 1560 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 856 1960 R90
SYMATTR InstName M19
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL nmos4 1768 1704 M90
SYMATTR InstName M20
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL voltage -1400 1544 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {wr0_voltage} 5n)
SYMATTR InstName Vwrite0
SYMBOL voltage -1032 1544 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {wr1_voltage} 5n)
SYMATTR InstName Vwrite1
SYMBOL nmos4 2136 1816 M0
SYMATTR InstName M21
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL pmos4 2136 1704 R180
SYMATTR InstName M22
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL nmos4 520 2072 R0
SYMATTR InstName M23
SYMATTR Value2 l={mc(SA_nWR_L, process_var)} w={mc(SA_nWR_W, process_var)}
SYMBOL pmos4 520 1960 M180
SYMATTR InstName M24
SYMATTR Value2 l={mc(SA_pWR_L, process_var)} w={mc(SA_pWR_W, process_var)}
SYMBOL voltage -1320 1064 R0
SYMATTR InstName Vcsel
SYMATTR Value PULSE(0 {core_voltage*2} {20n + csel_act})
SYMATTR SpiceLine Rser=100 Cpar=1fF