* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 0 0) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 N001 ra0 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N004 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra0 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 0 0) Rser=100 Cpar=1fF
CBL_cap_0 N001 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_1 N004 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
R1 N001 bitline0 {mc(bitline_R, process_var)}
R2 bitline1 N004 {mc(bitline_R, process_var)}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
VDD_source1 PV 0 {plate_voltage}
M12 N002 N003 FF VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M13 N003 N002 FF VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
M14 FF bl_en ACT 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vbl_en1 bl_en 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 40n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
.include ./transistor_model.pm
.tran 120ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=512
.param core_voltage=1.1V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=512
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}
.ic V(ff)=0

* LTspice schematic (.asc)
Version 4
SHEET 1 3280 2096
WIRE -1448 -1032 -1448 -1048
WIRE -1448 -936 -1448 -952
WIRE 712 -776 568 -776
WIRE 568 -744 568 -776
WIRE 248 -664 40 -664
WIRE 520 -664 248 -664
WIRE 568 -616 568 -648
WIRE 568 -616 328 -616
WIRE 1336 -616 1336 -632
WIRE -664 -536 -664 -568
WIRE -296 -536 -296 -568
WIRE 328 -536 328 -616
WIRE -1640 -520 -1640 -536
WIRE 328 -520 328 -536
WIRE 1336 -520 1336 -536
WIRE -1160 -504 -1160 -520
WIRE -1640 -424 -1640 -440
WIRE -664 -424 -664 -456
WIRE -296 -424 -296 -456
WIRE -1160 -408 -1160 -424
WIRE 328 -360 328 -456
WIRE 712 -232 712 -776
WIRE 776 -232 712 -232
WIRE 1272 -184 1272 -264
WIRE 712 -152 712 -232
WIRE 376 -120 328 -120
WIRE 584 -120 376 -120
WIRE 1272 -88 1272 -184
WIRE 776 -40 632 -40
WIRE 856 -40 776 -40
WIRE 984 -40 856 -40
WIRE 1256 -40 984 -40
WIRE 1432 -40 1352 -40
WIRE 1512 -40 1432 -40
WIRE 1640 -40 1512 -40
WIRE -856 -8 -856 -40
WIRE -568 -8 -568 -40
WIRE -264 -8 -264 -40
WIRE 776 -8 776 -40
WIRE 984 -8 984 -40
WIRE 1432 -8 1432 -40
WIRE 1640 -8 1640 -40
WIRE 856 8 824 8
WIRE 936 8 904 8
WIRE 1512 8 1480 8
WIRE 1592 8 1560 8
WIRE 1256 88 1064 88
WIRE -856 104 -856 72
WIRE -568 104 -568 72
WIRE -264 104 -264 72
WIRE 712 104 712 -72
WIRE 776 104 776 88
WIRE 776 104 712 104
WIRE 856 104 904 8
WIRE 856 104 776 104
WIRE 904 104 856 8
WIRE 984 104 984 88
WIRE 984 104 904 104
WIRE 1064 104 1064 88
WIRE 1064 104 984 104
WIRE 1432 104 1432 88
WIRE 1512 104 1560 8
WIRE 1512 104 1432 104
WIRE 1560 104 1512 8
WIRE 1640 104 1640 88
WIRE 1640 104 1560 104
WIRE 712 200 712 104
WIRE 856 200 712 200
WIRE 1064 200 1064 104
WIRE 1064 200 952 200
WIRE 584 248 552 248
WIRE 824 248 584 248
WIRE 872 248 824 248
WIRE 1000 248 872 248
WIRE 1240 248 1000 248
WIRE 824 264 824 248
WIRE 1000 264 1000 248
WIRE 712 296 712 200
WIRE 712 312 712 296
WIRE 744 312 712 312
WIRE 888 312 840 312
WIRE 920 312 888 312
WIRE 1064 312 1064 200
WIRE 1064 312 1016 312
WIRE 1256 312 1256 88
WIRE 1064 328 1064 312
WIRE 888 360 888 312
WIRE 888 376 888 360
WIRE 712 424 712 312
WIRE 776 424 712 424
WIRE 856 424 776 424
WIRE 984 424 920 424
WIRE 1064 424 1064 328
WIRE 1064 424 984 424
WIRE 776 440 776 424
WIRE 984 440 984 424
WIRE 1256 472 1256 392
WIRE 1304 472 1256 472
WIRE 856 520 920 424
WIRE 856 520 824 520
WIRE 920 520 856 424
WIRE 936 520 920 520
WIRE 1304 520 1304 472
WIRE 776 568 776 536
WIRE 776 568 664 568
WIRE 904 568 776 568
WIRE 984 568 984 536
WIRE 984 568 904 568
WIRE 616 648 360 648
WIRE 1256 744 1256 472
WIRE 1256 744 1144 744
WIRE 1144 776 1144 744
WIRE 1032 888 824 888
WIRE 1096 888 1096 856
WIRE 1096 888 1032 888
WIRE 1144 920 1144 872
WIRE 1144 936 1144 920
WIRE 1256 1048 1256 744
FLAG -1160 -408 0
FLAG -1160 -520 Eq
FLAG 664 616 0
FLAG -664 -424 0
FLAG -664 -568 sense_P
FLAG 984 488 0
FLAG 776 488 0
FLAG 904 200 0
FLAG 792 312 0
FLAG 968 312 0
FLAG 584 248 Eq
FLAG 888 360 VDDby2
FLAG 360 648 sense_N
FLAG 664 664 0
FLAG 712 296 bitline0
FLAG 1064 328 bitline1
FLAG 568 -696 0
FLAG 328 -536 mb0
FLAG 248 -664 ra0
FLAG 1144 824 0
FLAG 1144 1000 0
FLAG 1144 920 mb3
FLAG 1032 888 ra3
FLAG -1448 -936 0
FLAG -1448 -1048 ra0
FLAG 632 -88 VDD
FLAG 984 40 VDD
FLAG 776 40 VDD
FLAG 632 -136 VDD
FLAG 376 -120 sense_p
FLAG 856 -40 ACT
FLAG 904 568 NLAT
FLAG -296 -424 0
FLAG -296 -568 sense_N
FLAG 776 -168 0
FLAG 1304 584 0
FLAG -1640 -536 ra3
FLAG -1640 -424 0
FLAG -856 104 0
FLAG -856 -40 VDD
FLAG -568 104 0
FLAG -568 -40 VDDby2
FLAG 328 -360 PV
FLAG -264 104 0
FLAG -264 -40 PV
FLAG 1640 40 VDD
FLAG 1432 40 VDD
FLAG 1512 -40 FF
FLAG 1304 -40 0
FLAG 1272 -184 bl_en
FLAG 1336 -520 0
FLAG 1336 -632 bl_en
SYMBOL nmos4 616 568 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -1160 -520 R0
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage -664 -552 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0 0)
SYMATTR InstName Vsp
SYMBOL nmos4 936 440 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 824 440 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 952 248 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 744 264 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 920 264 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 520 -744 R0
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 312 -520 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 1096 776 R0
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1128 936 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -1448 -1048 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 584 -40 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 936 88 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 824 88 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage -296 -552 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 0 0)
SYMATTR InstName Vsn
SYMBOL cap 760 -232 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 1288 520 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 696 -168 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 1240 296 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -1640 -536 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -856 -24 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage -568 -24 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage -264 -24 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL pmos4 1592 88 M180
SYMATTR InstName M12
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 1480 88 R180
SYMATTR InstName M13
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL nmos4 1352 -88 R90
SYMATTR InstName M14
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage 1336 -632 R0
SYMATTR InstName Vbl_en1
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 40n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}