* SPICE netlist
R5 N001 Va 6.2k
R2 N005 0 100k
V1 VCC 0 12
R3 Va N003 390k
R4 Vb N003 100k
V2 Vr 0 SINE(6.1 1.8 10k)
C1 Vb N001 470p
XU1 N002 N001 VCC 0 Vb ADTL082 ;pnba In+)In-)V+)V-)OUT
XU4 N005 N002 VCC 0 N002 ADTL082 ;pnba In+)In-)V+)V-)OUT
V3 N005 0 6
XU2 N003 N002 VCC 0 Va LM393A ;pnba In+)In-)V+)V-)OUT
R1 VCC Va 1k
XU5 Vr Vb VCC 0 N004 LM393A ;pnba In+)In-)V+)V-)OUT
R6 VCC N004 10k
.tran 0 100u 20u startup
+ Tox=100n Uo=300 Phi=.6 Rs=64.15m Kp=10.18u W=1.5 L=2u
+ Vto=-3.646 Rd=62.45m Rds=444.4K Cbd=2.029n Pb=.8 Mj=.5 Fc=.5
+ Cgso=1.033n Cgdo=469.4p Rg=.3371 Is=54.08E-18 N=2 Tt=140n)
.SUBCKT LM324 1 2 99 50 28
IOS 2 1 5N
R1 1 3 500K
R2 3 2 500K
I1 99 4 100U
R3 5 50 517
R4 6 50 517
Q1 5 2 4 QX
Q2 6 7 4 QX
C4 5 6 128.27P
I2 99 50 75U
EOS 7 1 POLY(1) 16 49 2E-3 1
R8 99 49 60K
R9 49 50 60K
V2 99 8 1.63
D1 9 8 DX
D2 10 9 DX
V3 10 50 .635
EH 99 98 99 49 1
G1 98 9 POLY(1) 5 6 0 9.8772E-4 0 .3459
R5 98 9 101.2433MEG
C3 98 9 200P
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 7.9577E-14
G4 98 16 3 49 5.6234E-8
L2 98 17 15.9M
R13 17 16 1K
F6 50 99 POLY(1) V6 300U 1
E1 99 23 99 15 1
R16 24 23 17.5
D5 26 24 DX
V6 26 22 .63V
R17 23 25 17.5
D6 25 27 DX
V7 22 27 .63V
V5 22 21 0.27V
D4 21 15 DX
V4 20 22 0.27V
D3 15 20 DX
L3 22 28 500P
RL3 22 28 100K
.SUBCKT LM393A 1 2 3 4 5
F1 9 3 V1 1
IEE 3 7 DC 100.0E-6
VI1 21 1 DC .75
VI2 22 2 DC .75
Q1 9 21 7 QIN
Q2 8 22 7 QIN
Q3 9 8 4 QMO
Q4 8 8 4 QMI
E1 10 4 9 4 1
V1 10 11 DC 0
Q5 5 11 4 QOC
DP 4 3 DX
RP 3 4 46.3E3
.SUBCKT LM311 IN+ IN- VCC+ VCC- STROB COL_OUT EMIT_OUT
X_U4 CMP N840186 Prop_Delay
X_U2 IN-BUFF IN+BUFF INRANGE V+_BUFFER V-_BUFFER INPUTRANGE
X_U5 COL_OUT EMIT_OUT N21237 INRANGE 0 STROB V+_BUFFER V-_BUFFER VCC+ N884250
+ Output_Stage
X_U6 VCC+ V+_BUFFER VCC- V-_BUFFER Supply_Buffer
X_U3 N785573 IN-BUFF CMP V+_BUFFER V-_BUFFER 0 HPA_COMPHYS
I_IS N843683 VCC- DC 5.1m
X_U7 N21237 0 V+_BUFFER V-_BUFFER Supply_Enable
X_U1 IN+ IN+BUFF IN- IN-BUFF Input_Buffer
I_IBP IN+ VCC- DC 100n
I_IBN IN- VCC- DC 100n
V_VOS N785573 IN+BUFF 2mV
R_RIS N843683 VCC+ 1u TC=0,0
C_CINPL VCC- IN+ 0.5p TC=0,0
C_CINNL VCC- IN- 0.5p TC=0,0
C_CINPH IN+ VCC+ 0.5p TC=0,0
C_CINNH IN- VCC+ 0.5p TC=0,0
R_RS N856907 CMP 50 TC=0,0
R_RT 0 N856913 50 TC=0,0
T_TPD N856907 0 N856913 0 Z0=50 TD=125n
X_S1 CMP 0 N857434 N840186 Top_Level_S1
X_S2 CMP 0 N857434 N856913 Top_Level_S2
E_E1 N884250 V-_BUFFER N857434 V-_BUFFER 2
.SUBCKT Input_Buffer IN+ IN+_BUFF IN- IN-_BUFF
X_U1 IN+ IN- IN+_BUFF IN-_BUFF SUPPLY_BUFFER1
.SUBCKT Supply_Enable EN POR V+_BUFFER V-_BUFFER
X_U5 N16973 N20377 N16955 1V 0 VCC_Range
X_U15 N20310 N16973 POR 1V 0 VCC_Range
X_U13 V+_BUFFER V-_BUFFER N16973 1V 0 Difference
V_VS_MIN_SET N20310 0 3.49
V_VS_MAX_SET N20377 0 30.01
V_VLOGIC 1V 0 1
V_VS_MIN_SET1 N777117 0 3.49
X_U16 N777117 N16973 N777171 1V 0 VCC_Range
X_U17 N16955 N777171 EN 1V 0 ORGATE
.SUBCKT Supply_Buffer V+ V+_BUFFER V- V-_BUFFER
X_U1 V+ V- V+_BUFFER V-_BUFFER SUPPLY_BUFFER1
.SUBCKT Output_Stage COL_OUT EMIT_OUT EN IN_RANGE POR STROB V+_BUFFER V-_BUFFER
+ VCC+ VIN
X_SMID CONTROL_MID 0 N778484 MID Output_Stage_SMID
X_U3 VIN DS_OUT V+_BUFFER V-_BUFFER VCC+ VSS_NEW DIGLEVSHIFT
X_U7 MID V+_BUFFER V-_BUFFER MID_SUPPLY
V_VLOGIC 1V 0 1
V_V1 VCC+ VSS_NEW 1
X_SHIZ CONTROL_HIZ 0 N778484 N778496 Output_Stage_SHIZ
X_U8 POR IN_RANGE EN EN CONTROL_HIZ 1V 0 4ORGATE
X_U9 CONTROL_HIZ N789513 1V 0 INVERTER
X_U10 N789513 POR CONTROL_MID 1V 0 ORGATE
L_L1 N778484 COL_OUT 1n
C_COUTH COL_OUT VCC+ 0.045p TC=0,0
C_COUTL EMIT_OUT COL_OUT 0.045p TC=0,0
X_SVOL CTRL_OUT VSS_NEW EMIT_OUT N850209 Output_Stage_SVOL
R_ROUTL N850209 N778496 150 TC=0,0
X_H1 V+_BUFFER N857381 N864891 VSS_NEW Output_Stage_H1
X_U11 N864896 DS_OUT CTRL_OUT VCC+ VSS_NEW ORGATE
X_U1 N863109 STROB N864245 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPS N863109 V+_BUFFER 0.01
X_U12 STROB N864069 N864233 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPS1 N864069 V-_BUFFER -0.01
X_U13 N864245 N864233 N864257 VCC+ VSS_NEW ORGATE
X_U14 N864257 N864882 VCC+ VSS_NEW INVERTER
X_U15 N864891 N864882 N864896 VCC+ VSS_NEW ANDGATE
R_RS1 N857381 STROB 500 TC=0,0
.SUBCKT INPUTRANGE INN INP INRANGE V+_BUFFER V-_BUFFER
V_VCMNP N20415 V-_BUFFER 0.49
V_VCMPN N32047 V+_BUFFER -1.49
X_U1 N20155 INP N20826 V+_BUFFER V-_BUFFER VINRANGE_393
V_VCMPP N20155 V+_BUFFER -1.49
V_VCMNN N20539 V-_BUFFER 0.49
X_U21 N32047 INN N20833 V+_BUFFER V-_BUFFER VINRANGE_393
X_U22 INP N20415 N20840 V+_BUFFER V-_BUFFER VINRANGE_393
X_U23 INN N20539 N20531 V+_BUFFER V-_BUFFER VINRANGE_393
X_U24 N20826 N20833 N20840 N20531 INRANGE V+_BUFFER V-_BUFFER 4ORGATE
.SUBCKT Prop_Delay VIN VOUT
T_TPD N03175 0 VOUT 0 Z0=50 TD=115n
R_RT 0 VOUT 50 TC=0,0
R_RS N03175 VIN 50 TC=0,0
.subckt Top_Level_S1 1 2 3 4
S_S1 3 4 1 2 _S1
RS_S1 1 2 1G
.subckt Top_Level_S2 1 2 3 4
S_S2 3 4 1 2 _S2
RS_S2 1 2 1G
.subckt Output_Stage_SMID 1 2 3 4
S_SMID 3 4 1 2 _SMID
RS_SMID 1 2 1G
.subckt Output_Stage_SHIZ 1 2 3 4
S_SHIZ 3 4 1 2 _SHIZ
RS_SHIZ 1 2 1G
.subckt Output_Stage_SVOL 1 2 3 4
S_SVOL 3 4 1 2 _SVOL
RS_SVOL 1 2 1G
.subckt Output_Stage_H1 1 2 3 4
H_H1 3 4 VH_H1 250
VH_H1 1 2 0V
.SUBCKT ANDGATE 1 2 3 VDD VSS
E1 4 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) & (V(2)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 4 3 1
C1 3 0 1e-12
.SUBCKT HPA_COMPHYS INP INN OUT_OUT VDD VSS VHYS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EVH VH 0 VALUE = { ( V(VHYS)/2) }
EINNNEW INNNEW 0 VALUE = { IF( ( V(OUT_OUT) < V(VMID) ),(V(INN) + (V(VH))),( V(INN) - V(VH) ) ) }
EOUT OUT 0 VALUE = { IF( ( V(INP) > V(INNNEW) ), V(VDD), V(VSS) ) }
R1 OUT OUT_OUT 1
C1 OUT_OUT 0 1e-12
.SUBCKT DIGLEVSHIFT 1 2 VDD_OLD VSS_OLD VDD_NEW VSS_NEW
E1 3 0 VALUE = { IF( V(1) < 1, V(VSS_NEW), V(VDD_NEW) ) }
R1 3 2 1
.SUBCKT ENABLE_LOGIC 1 2 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(VSS) ) }
R1 OUT 2 1
C1 2 0 1e-12
.SUBCKT ENABLE_TLV7021 1 2 3 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) > V(VMID) ), V(2), V(3) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.SUBCKT INNNEWPOR 1 2 3 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VSS), V(VDD) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.SUBCKT INPNEWPOR 1 2 3 OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT2 0 VALUE = { IF( ( V(1) < V(VMID) ), V(VDD), V(VSS) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.SUBCKT VIN_INV 1 2 VDD VSS
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
C1 2 0 1e-12
.SUBCKT INVERTER 1 2 VDD VSS
E2 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
C1 1 0 1e-12
.SUBCKT MID_SUPPLY OUT VDD VSS
EVMID VMID 0 VALUE = { ( V(VDD) + V(VSS) )/2 }
EOUT OUT 0 VALUE = {V(VMID)}
.SUBCKT ORGATE 1 2 3 VDD VSS
E1 4 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VSS), V(VDD) ) }
R1 4 3 1
C1 3 0 1e-12
.SUBCKT NOR_GATE 1 2 OUT VDD VSS
EOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 OUT 2 1
C1 OUT 0 1e-12
.SUBCKT ORGATE1701 1 2 3 4 OUT VDD VSS
EOUT OUT 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(3), V(4) ) }
.SUBCKT PORCHECK 1 2 OUT VDD VSS
EOUT OUT 0 VALUE = { IF( ( V(2) < V(1) ), V(VSS), V(VDD) ) }
R1 OUT 2 1
C1 2 0 1e-12
.SUBCKT Difference 1 2 OUT VDD VSS
EOUT OUT1 0 VALUE = { V(1)- V(2)}
R1 OUT1 OUT 1
.SUBCKT SUPPLY_BUFFER1 1 2 VDD_NEW VSS_NEW
EVDD_NEW VDD_NEW 0 VALUE = {V(1)}
EVSS_NEW VSS_NEW 0 VALUE = {V(2)}
.SUBCKT VCC_Range 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VDD), V(VSS) ) }
R1 OUT OUT2 1
C1 OUT 0 1e-12
.SUBCKT VINRANGE_393 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ( V(1) >= V(2) ), V(VSS), V(VDD) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.subckt SHUTDOWNCURRENT SHUTDOWN 2 3 OUT VDD VSS
EOUT OUT2 0 VALUE = {IF ((V(SHUTDOWN) > (V(VSS) + 0.4)), V(2), V(3))}
R1 OUT OUT2 1
C1 OUT 0 1e-12
.subckt SHUTDOWNOUTPUT DISABLE ENABLE SHUTDOWN VSS OUT
EOUT OUT 0 VALUE = {IF ((V(SHUTDOWN) <= (V(VSS) + 0.4)), V(DISABLE), V(ENABLE))}
C1 OUT 0 1e-12
.SUBCKT NORGATE 1 2 OUT VDD VSS
EOUT OUT2 0 VALUE = { IF( ((V(1)< (V(VDD)+V(VSS))/2 ) & (V(2)< (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 OUT2 OUT 1
C1 OUT 0 1e-12
.SUBCKT LE_HYST LEHYST V- V-_BUF V+_BUF LATCH_OUT HYST_OUT
V_VLATCH N00729 V- 1.25
R_RPU N00729 LEHYST 40k TC=0,0
E_EIN VLE V-_BUF LEHYST V- 1
R_R1 V-_BUF LATCH_OUT 1k TC=0,0
R_R2 V-_BUF VLE 1k TC=0,0
R_R3 V-_BUF HYST_OUT 1k TC=0,0
E_ELATCH LATCH_OUT V-_BUF VALUE = { IF( V(VLE)<= 0.4, 0, 5 ) }
E_EHYST HYST_OUT V-_BUF TABLE {V(VLE)} = (0.4,0)
+(0.5,0.0636)
+(0.55,0.0636)
+(0.6,0.0636)
+(0.65,0.0636)
+(0.7,0.0635)
+(0.71,0.0636)
+(0.72,0.0635)
+(0.73,0.0636)
+(0.74,0.0634)
+(0.75,0.0635)
+(0.76,0.0638)
+(0.77,0.0637)
+(0.78,0.0637)
+(0.79,0.0637)
+(0.8,0.0636)
+(0.81,0.0636)
+(0.82,0.0636)
+(0.83,0.0636)
+(0.84,0.0425)
+(0.85,0.0411)
+(0.86,0.0398)
+(0.87,0.0386)
+(0.88,0.0371)
+(0.89,0.0359)
+(0.9,0.0347)
+(0.91,0.0334)
+(0.92,0.032)
+(0.93,0.0309)
+(0.94,0.0296)
+(1,0.0223)
+(1.05,0.0164)
+(1.1,0.0108)
+(1.15,0.0056)
+(1.2,0.0007)
+(1.25,0)
.SUBCKT IS_SET VCC VEE DISABLE VIEN VIDIS PBAD
GIS VCC1 VEE VALUE = { IF ( (V(PBAD) > 2.5V) , 1u , IF ( V(DISABLE) > 2.5, V(VIEN), V(VIDIS) ) ) }
RIS VCC1 VCC 1
.SUBCKT 4ORGATE 1 2 3 4 5 VDD VSS
E1 6 0 VALUE = { IF( ((V(1)> (V(VDD)+V(VSS))/2 ) | (V(2)> (V(VDD)+V(VSS))/2 ) | (V(3)> (V(VDD)+V(VSS))/2 ) | (V(4)> (V(VDD)+V(VSS))/2 )), V(VDD), V(VSS) ) }
R1 5 6 1

* LTspice schematic (.asc)
Version 4
SHEET 1 1136 944
WIRE 216 -456 120 -456
WIRE 360 -456 280 -456
WIRE -56 -376 -56 -424
WIRE 24 -328 -8 -328
WIRE -200 -280 -200 -328
WIRE -232 -264 -280 -264
WIRE 200 -264 200 -296
WIRE -56 -248 -56 -296
WIRE -56 -248 -168 -248
WIRE -8 -248 -8 -328
WIRE -8 -248 -56 -248
WIRE 24 -248 -8 -248
WIRE 120 -248 120 -456
WIRE 120 -248 104 -248
WIRE 168 -248 120 -248
WIRE -232 -232 -248 -232
WIRE 360 -232 360 -456
WIRE 360 -232 232 -232
WIRE 408 -232 360 -232
WIRE 168 -216 120 -216
WIRE -200 -184 -200 -216
WIRE -408 -152 -408 -264
WIRE 200 -152 200 -200
WIRE -248 -104 -248 -232
WIRE -184 -104 -248 -104
WIRE -56 -104 -56 -248
WIRE -56 -104 -104 -104
WIRE 472 -24 472 -88
WIRE -248 -8 -248 -104
WIRE -136 -8 -248 -8
WIRE 360 -8 360 -232
WIRE 360 -8 -56 -8
WIRE 440 -8 360 -8
WIRE 520 8 504 8
WIRE 568 8 520 8
WIRE 440 24 312 24
WIRE -408 56 -408 -72
WIRE 312 88 312 24
WIRE 344 88 312 88
WIRE -280 104 -280 -264
WIRE 120 104 120 -216
WIRE 120 104 -280 104
WIRE 312 120 312 88
WIRE 472 152 472 40
WIRE -200 264 -200 216
WIRE 312 264 312 200
WIRE -280 280 -280 104
WIRE -232 280 -280 280
WIRE 120 296 120 104
WIRE 120 296 -168 296
WIRE -376 312 -568 312
WIRE -232 312 -376 312
WIRE -376 328 -376 312
WIRE -568 344 -568 312
WIRE -200 376 -200 328
WIRE -568 456 -568 424
WIRE -376 472 -376 408
FLAG -376 472 0
FLAG -408 56 0
FLAG 200 -152 0
FLAG -200 376 0
FLAG 472 152 0
FLAG -200 -184 0
FLAG -408 -264 VCC
IOPIN -656 -752 BiDir
FLAG -200 -328 VCC
IOPIN -448 -816 BiDir
FLAG 200 -296 VCC
IOPIN -48 -784 BiDir
FLAG -200 216 VCC
IOPIN -448 -272 BiDir
FLAG 24 -328 Va
IOPIN -224 -816 Out
FLAG 408 -232 Vb
IOPIN 160 -720 Out
FLAG 312 264 0
FLAG 472 -88 VCC
IOPIN 224 -576 BiDir
FLAG 344 88 Vr
IOPIN 96 -400 Out
FLAG -568 456 0
FLAG -56 -424 VCC
IOPIN -304 -912 BiDir
FLAG 520 -72 VCC
IOPIN 272 -560 BiDir
SYMBOL res 120 -264 R90
SYMATTR InstName R5
SYMATTR Value 6.2k
SYMBOL res -392 312 R0
SYMATTR InstName R2
SYMATTR Value 100k
SYMBOL voltage -408 -168 R0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL res -88 -120 R90
SYMATTR InstName R3
SYMATTR Value 390k
SYMBOL res -40 -24 R90
SYMATTR InstName R4
SYMATTR Value 100k
SYMBOL voltage 312 104 R0
SYMATTR InstName V2
SYMATTR Value SINE(6.1 1.8 10k)
SYMBOL cap 280 -472 R90
SYMATTR InstName C1
SYMATTR Value 470p
SYMBOL OpAmps\\ADTL082 200 -296 R0
SYMATTR InstName U1
SYMBOL OpAmps\\ADTL082 -200 232 R0
SYMATTR InstName U4
SYMBOL voltage -568 328 R0
SYMATTR InstName V3
SYMATTR Value 6
SYMBOL OpAmps\\opamp2 -200 -312 R0
SYMATTR InstName U2
SYMATTR Value LM393A
SYMBOL res -72 -392 R0
SYMATTR InstName R1
SYMATTR Value 1k
SYMBOL OpAmps\\opamp2 472 -56 R0
SYMATTR InstName U5
SYMATTR Value LM393A
SYMBOL res 504 -88 R0
SYMATTR InstName R6
SYMATTR Value 10k