* SPICE netlist
M1 0 post_synaptic_input N002 0 NMOS l=180n w=2.3u
M2 N002 N002 VDD VDD PMOS l=180n w=2.3u
M3 post_synaptic_input N002 VDD VDD PMOS l=180n w=1u
C1 post_synaptic_input 0 35f
M4 0 N003 post_synaptic_input 0 NMOS l=3.96u w=1.3u
M7 N003 N002 VDD VDD PMOS l=2.52u w=1.3u
M6 0 N003 N003 0 NMOS l=3.24u w=1.3u
C2 N003 0 550f
M8 N003 spike_out d VDD PMOS l=180n w=1.3u
M5 c N001 post_synaptic_input 0 NMOS l=180n w=1u
M12 spike_out post_synaptic_input N004 0 NMOS l=180n w=1.3u
M9 VDD spike_out N001 VDD PMOS l=684n w=1u
M10 spike_out spike_out VDD VDD PMOS l=234n w=1.8u
M11 N004 Vth N001 0 NMOS l=774n w=1u
M13 N004 N004 0 0 NMOS l=540n w=2.3u
M14 0 Vbias N004 N005 NMOS l=540n w=2.3u
V1 VDD 0 0.9
V2 c 0 0.5
V4 Vth 0 0.4
V5 Vbias 0 0.3
V6 d 0 0.07
I1 post_synaptic_input 0 PULSE(0 0.1uA 100ns 0.1ns 0.1ns 10ns 100ns 0A)
.include p18_cmos_models_tt.inc
.tran 0.1n 2u
.op

* LTspice schematic (.asc)
Version 4
SHEET 1 1744 832
WIRE 776 -160 88 -160
WIRE -792 -48 -824 -48
WIRE -632 -48 -792 -48
WIRE -584 -48 -632 -48
WIRE -488 -48 -584 -48
WIRE -440 -48 -488 -48
WIRE -264 -48 -264 -112
WIRE -264 -48 -440 -48
WIRE -136 -48 -264 -48
WIRE 328 -48 -136 -48
WIRE 424 -48 328 -48
WIRE 696 -48 424 -48
WIRE 744 -48 696 -48
WIRE 552 -32 472 -32
WIRE -104 0 -168 0
WIRE 328 0 328 -48
WIRE 424 0 328 0
WIRE 744 0 744 -48
WIRE 744 0 696 0
WIRE -792 16 -792 -48
WIRE -584 16 -584 -48
WIRE -440 16 -440 -48
WIRE -104 16 -104 0
WIRE -728 32 -744 32
WIRE -536 32 -728 32
WIRE -392 32 -536 32
WIRE -24 32 -56 32
WIRE 552 32 552 -32
WIRE 568 32 552 32
WIRE 648 32 568 32
WIRE -824 64 -824 -48
WIRE -792 64 -824 64
WIRE -632 64 -632 -48
WIRE -584 64 -632 64
WIRE -488 64 -488 -48
WIRE -440 64 -488 64
WIRE -136 64 -136 -48
WIRE -104 64 -136 64
WIRE 696 80 696 48
WIRE 776 80 776 -160
WIRE 776 80 696 80
WIRE 424 96 424 48
WIRE 568 96 568 32
WIRE 568 96 424 96
WIRE -24 112 -24 32
WIRE 136 112 -24 112
WIRE 248 112 136 112
WIRE 424 112 424 96
WIRE 424 112 248 112
WIRE 776 112 776 80
WIRE 872 128 824 128
WIRE -792 144 -792 112
WIRE -728 144 -728 32
WIRE -728 144 -792 144
WIRE -440 144 -440 112
WIRE -200 144 -440 144
WIRE 328 160 248 160
WIRE 776 160 712 160
WIRE 40 192 -424 192
WIRE 200 192 40 192
WIRE 88 208 88 -160
WIRE 376 208 248 208
WIRE 520 208 376 208
WIRE 776 208 520 208
WIRE -792 224 -792 144
WIRE 520 224 520 208
WIRE 520 224 440 224
WIRE 600 224 520 224
WIRE -680 240 -744 240
WIRE -584 240 -584 112
WIRE -584 240 -680 240
WIRE -568 240 -584 240
WIRE -424 240 -424 192
WIRE -424 240 -568 240
WIRE 40 240 -24 240
WIRE 776 240 648 240
WIRE -568 256 -568 240
WIRE -232 256 -376 256
WIRE -200 256 -200 144
WIRE -200 256 -232 256
WIRE -184 256 -200 256
WIRE -104 256 -104 112
WIRE -104 256 -184 256
WIRE -792 272 -824 272
WIRE -184 272 -184 256
WIRE -104 272 -104 256
WIRE 456 272 440 272
WIRE -424 288 -488 288
WIRE -232 304 -296 304
WIRE 40 304 40 288
WIRE 376 304 376 208
WIRE 392 304 376 304
WIRE 600 304 600 272
WIRE 456 320 456 272
WIRE 456 320 440 320
WIRE 520 320 456 320
WIRE 600 320 520 320
WIRE -824 352 -824 272
WIRE -792 352 -792 320
WIRE -792 352 -824 352
WIRE -568 352 -568 320
WIRE -568 352 -792 352
WIRE -488 352 -488 288
WIRE -488 352 -568 352
WIRE -424 352 -424 336
WIRE -424 352 -488 352
WIRE -296 352 -296 304
WIRE -296 352 -424 352
WIRE -232 352 -296 352
WIRE -104 352 -104 336
WIRE -104 352 -232 352
WIRE -24 352 -24 240
WIRE -24 352 -104 352
WIRE 24 352 -24 352
WIRE 328 352 328 160
WIRE 328 352 24 352
WIRE 520 352 520 320
WIRE 520 352 328 352
WIRE 712 352 712 160
WIRE 712 352 520 352
WIRE -680 384 -680 240
WIRE -680 384 -872 384
WIRE 24 416 24 352
WIRE 136 416 136 112
WIRE 456 416 136 416
FLAG 24 416 0
FLAG -264 -112 VDD
FLAG -744 -400 VDD
FLAG -744 -320 0
FLAG 456 416 spike_out
FLAG 776 240 Vbias
FLAG 872 128 Vth
FLAG 40 304 c
FLAG -168 0 d
FLAG -872 384 post_synaptic_input
FLAG -568 -320 0
FLAG 216 -320 0
FLAG -424 -320 0
FLAG -280 -320 0
FLAG -568 -400 c
FLAG 216 -400 post_synaptic_input
FLAG -424 -400 Vth
FLAG -280 -400 Vbias
FLAG -152 -320 0
FLAG -152 -400 d
SYMBOL nmos4 -744 320 R180
SYMATTR InstName M1
SYMATTR Value2 l=180n w=2.3u
SYMBOL pmos4 -744 112 R180
SYMATTR InstName M2
SYMATTR Value2 l=180n w=2.3u
SYMBOL pmos4 -536 112 R180
SYMATTR InstName M3
SYMATTR Value2 l=180n w=1u
SYMBOL cap -584 256 R0
SYMATTR InstName C1
SYMATTR Value 35f
SYMBOL nmos4 -376 336 R180
SYMATTR InstName M4
SYMATTR Value2 l=3.96u w=1.3u
SYMBOL pmos4 -392 112 R180
SYMATTR InstName M7
SYMATTR Value2 l=2.52u w=1.3u
SYMBOL nmos4 -184 352 R180
SYMATTR InstName M6
SYMATTR Value2 l=3.24u w=1.3u
SYMBOL cap -120 272 R0
SYMATTR InstName C2
SYMATTR Value 550f
SYMBOL pmos4 -56 112 R180
SYMATTR InstName M8
SYMATTR Value2 l=180n w=1.3u
SYMBOL nmos4 88 288 R180
SYMATTR InstName M5
SYMATTR Value2 l=180n w=1u
SYMBOL nmos4 200 112 R0
SYMATTR InstName M12
SYMATTR Value2 l=180n w=1.3u
SYMBOL pmos4 648 -48 R0
SYMATTR InstName M9
SYMATTR Value2 l=684n w=1u
SYMBOL pmos4 472 48 R180
SYMATTR InstName M10
SYMATTR Value2 l=234n w=1.8u
SYMBOL nmos4 824 208 R180
SYMATTR InstName M11
SYMATTR Value2 l=774n w=1u
SYMBOL nmos4 392 224 R0
SYMATTR InstName M13
SYMATTR Value2 l=540n w=2.3u
SYMBOL nmos4 648 320 R180
SYMATTR InstName M14
SYMATTR Value2 l=540n w=2.3u
SYMBOL voltage -744 -416 R0
SYMATTR InstName V1
SYMATTR Value 0.9
SYMBOL voltage -568 -416 R0
SYMATTR InstName V2
SYMATTR Value 0.5
SYMBOL voltage -424 -416 R0
SYMATTR InstName V4
SYMATTR Value 0.4
SYMBOL voltage -280 -416 R0
SYMATTR InstName V5
SYMATTR Value 0.3
SYMBOL voltage -152 -416 R0
SYMATTR InstName V6
SYMATTR Value 0.07
SYMBOL current 216 -400 R0
SYMATTR InstName I1
SYMATTR Value PULSE(0 0.1uA 100ns 0.1ns 0.1ns 10ns 100ns 0A)