* SPICE netlist
M1 NLAT sense_N 0 0 NMOS l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
Veq Eq 0 PULSE(0 {core_voltage*1.2} 0 0 0 14n)
Vsp sense_P 0 PULSE({core_voltage} 0 {20n + psense_act} 0 0) Rser=100 Cpar=1fF
M2 bitline1 bitline0 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
M3 bitline0 bitline1 NLAT 0 NMOS l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
M4 bitline1 Eq bitline0 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
M5 bitline0 Eq VDDby2 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M6 VDDby2 Eq bitline1 0 NMOS l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
M7 N001 ra01 mb0 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_0 mb0 PV {mc(cell_cap, process_var)} IC={-plate_voltage + cell0_charge}
M8 N002 ra3 mb3 0 NMOS l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
cell_cap_2 mb3 0 {mc(cell_cap, process_var)}
Vra0 ra00 0 PULSE(0 0 0 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
M9 ACT sense_p VDD VDD PMOS l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
M10 bitline1 bitline0 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
M11 bitline0 bitline1 ACT VDD PMOS l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
Vsn sense_N 0 PULSE(0 {core_voltage} {20n + nsense_act} 0 0) Rser=100 Cpar=1fF
CBL_cap_0 bitline 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
CBL_cap_1 N002 0 {mc(bitline_cap, process_var)} IC={core_voltage/2}
R1 bitline bitline0 {mc(bitline_R, process_var)}
R2 bitline1 N002 {mc(bitline_R, process_var)}
Vra2 ra3 0 PULSE(0 {mc(0, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
VDD_source VDD 0 {core_voltage}
VDD_source2 VDDby2 0 {core_voltage/2}
VDD_source1 PV 0 {plate_voltage}
M12 bitline match1 N001 0 nmos_access_tran l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
Vra1 match0 0 PULSE(0 0 0 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Vra3 match1 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
Vra4 ra01 0 PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0) Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
.include ./transistor_model.pm
.tran 120ns uic
.param process_var=0.05
.step param run 1 100 1
.param cell_cap={24.0fF*cell_cap_factor}
.param bitline_cap={85fF*bl_cap_factor}
.param access_tran_L={85nm*access_tran_L_factor}
.param access_tran_W={55nm*access_tran_W_factor}
.param bitline_R=R_per_cell*cells_per_BL
.param R_per_cell=40
.param SA_nmos_L={160nm*SA_nmos_L_factor}
.param SA_nmos_W={1900nm*SA_nmos_W_factor}
.param SA_pmos_L={160nm*SA_pmos_L_factor}
.param SA_pmos_W={1330nm*SA_pmos_W_factor}
.param SA_eq_L=96.3nm
.param SA_eq_W=541nm
.param SA_nset_L={270nm*SA_nset_L_factor}
.param SA_nset_W={220nm*SA_nset_W_factor}
.param SA_pset_L={270nm*SA_pset_L_factor}
.param SA_pset_W={220nm*SA_pset_W_factor}
.param cells_per_BL=512
.param core_voltage=1.1V
.param wordline_voltage=2.9V
.param cell0_charge=core_voltage*cells_charge_state
.param cells_charge_state=0.8
.param pv_modifier=0.5
.param plate_voltage={core_voltage*pv_modifier}
.param psense_act=4ns
.param nsense_act=4ns
.param wl0_act=1.0
.param tech_node=7
.param cell_cap_factor={0.95**tech_node}
.param bl_cap_factor={0.95**tech_node}
.param access_tran_L_factor={0.95**tech_node}
.param access_tran_W_factor={0.85**tech_node}
.param SA_nmos_L_factor={0.93**tech_node}
.param SA_nmos_W_factor={0.93**tech_node}
.param SA_pmos_L_factor={0.93**tech_node}
.param SA_pmos_W_factor={0.93**tech_node}
.param SA_nset_L_factor={0.93**tech_node}
.param SA_nset_W_factor={0.93**tech_node}
.param SA_pset_L_factor={0.93**tech_node}
.param SA_pset_W_factor={0.95**tech_node}
.param wordline_C={WL_C_per_cell*cells_per_LWL}
.param WL_C_per_cell=0.07fF
.param cells_per_LWL=512
.param WL_R_per_cell=40ohm
.param wordline_R={WL_R_per_cell*cells_per_LWL}
.param WL_cap_factor={0.95**tech_node}
.param WL_res_factor={0.95**tech_node}

* LTspice schematic (.asc)
Version 4
SHEET 1 4032 2336
WIRE -2016 -1152 -2016 -1168
WIRE -736 -1152 -736 -1168
WIRE -2016 -1056 -2016 -1072
WIRE -736 -1056 -736 -1072
WIRE -736 -912 -736 -928
WIRE -2016 -896 -2016 -912
WIRE 1424 -848 1280 -848
WIRE -736 -816 -736 -832
WIRE -2016 -800 -2016 -816
WIRE 1280 -784 1280 -848
WIRE 960 -704 752 -704
WIRE 1232 -704 960 -704
WIRE 1280 -624 1280 -688
WIRE 1424 -592 1424 -848
WIRE 960 -544 752 -544
WIRE 1232 -544 960 -544
WIRE 1280 -496 1280 -528
WIRE 1280 -496 1040 -496
WIRE 48 -416 48 -448
WIRE 416 -416 416 -448
WIRE 1040 -416 1040 -496
WIRE -928 -400 -928 -416
WIRE 1040 -400 1040 -416
WIRE -448 -384 -448 -400
WIRE -928 -304 -928 -320
WIRE 48 -304 48 -336
WIRE 416 -304 416 -336
WIRE -448 -288 -448 -304
WIRE 1040 -240 1040 -336
WIRE 1424 -112 1424 -592
WIRE 1488 -112 1424 -112
WIRE 1424 -32 1424 -112
WIRE 1088 0 1040 0
WIRE 1296 0 1088 0
WIRE 1488 80 1344 80
WIRE 1568 80 1488 80
WIRE 1696 80 1568 80
WIRE -144 112 -144 80
WIRE 144 112 144 80
WIRE 448 112 448 80
WIRE 1488 112 1488 80
WIRE 1696 112 1696 80
WIRE 1568 128 1536 128
WIRE 1648 128 1616 128
WIRE 1968 208 1776 208
WIRE -144 224 -144 192
WIRE 144 224 144 192
WIRE 448 224 448 192
WIRE 1424 224 1424 48
WIRE 1488 224 1488 208
WIRE 1488 224 1424 224
WIRE 1568 224 1616 128
WIRE 1568 224 1488 224
WIRE 1616 224 1568 128
WIRE 1696 224 1696 208
WIRE 1696 224 1616 224
WIRE 1776 224 1776 208
WIRE 1776 224 1696 224
WIRE 1424 320 1424 224
WIRE 1568 320 1424 320
WIRE 1776 320 1776 224
WIRE 1776 320 1664 320
WIRE 1296 368 1264 368
WIRE 1536 368 1296 368
WIRE 1584 368 1536 368
WIRE 1712 368 1584 368
WIRE 1952 368 1712 368
WIRE 1536 384 1536 368
WIRE 1712 384 1712 368
WIRE 1424 416 1424 320
WIRE 1424 432 1424 416
WIRE 1456 432 1424 432
WIRE 1600 432 1552 432
WIRE 1632 432 1600 432
WIRE 1776 432 1776 320
WIRE 1776 432 1728 432
WIRE 1968 432 1968 208
WIRE 1776 448 1776 432
WIRE 1600 480 1600 432
WIRE 1600 496 1600 480
WIRE 1424 544 1424 432
WIRE 1488 544 1424 544
WIRE 1568 544 1488 544
WIRE 1696 544 1632 544
WIRE 1776 544 1776 448
WIRE 1776 544 1696 544
WIRE 1488 560 1488 544
WIRE 1696 560 1696 544
WIRE 1968 592 1968 512
WIRE 2016 592 1968 592
WIRE 1568 640 1632 544
WIRE 1568 640 1536 640
WIRE 1632 640 1568 544
WIRE 1648 640 1632 640
WIRE 2016 640 2016 592
WIRE 1488 688 1488 656
WIRE 1488 688 1376 688
WIRE 1616 688 1488 688
WIRE 1696 688 1696 656
WIRE 1696 688 1616 688
WIRE 1328 768 1072 768
WIRE 1968 864 1968 592
WIRE 1968 864 1856 864
WIRE 1856 896 1856 864
WIRE 1744 1008 1536 1008
WIRE 1808 1008 1808 976
WIRE 1808 1008 1744 1008
WIRE 1856 1040 1856 992
WIRE 1856 1056 1856 1040
WIRE 1968 1168 1968 864
FLAG -448 -288 0
FLAG -448 -400 Eq
FLAG 1376 736 0
FLAG 48 -304 0
FLAG 48 -448 sense_P
FLAG 1696 608 0
FLAG 1488 608 0
FLAG 1616 320 0
FLAG 1504 432 0
FLAG 1680 432 0
FLAG 1296 368 Eq
FLAG 1600 480 VDDby2
FLAG 1072 768 sense_N
FLAG 1376 784 0
FLAG 1424 416 bitline0
FLAG 1776 448 bitline1
FLAG 1280 -576 0
FLAG 1040 -416 mb0
FLAG 960 -544 ra01
FLAG 1856 944 0
FLAG 1856 1120 0
FLAG 1856 1040 mb3
FLAG 1744 1008 ra3
FLAG -736 -816 0
FLAG -736 -928 ra00
FLAG 1344 32 VDD
FLAG 1696 160 VDD
FLAG 1488 160 VDD
FLAG 1344 -16 VDD
FLAG 1088 0 sense_p
FLAG 1568 80 ACT
FLAG 1616 688 NLAT
FLAG 416 -304 0
FLAG 416 -448 sense_N
FLAG 1488 -48 0
FLAG 2016 704 0
FLAG -928 -416 ra3
FLAG -928 -304 0
FLAG -144 224 0
FLAG -144 80 VDD
FLAG 144 224 0
FLAG 144 80 VDDby2
FLAG 1040 -240 PV
FLAG 448 224 0
FLAG 448 80 PV
FLAG 1280 -736 0
FLAG 960 -704 match1
FLAG -736 -1056 0
FLAG -736 -1168 match0
FLAG -2016 -1056 0
FLAG -2016 -1168 match1
FLAG -2016 -800 0
FLAG -2016 -912 ra01
FLAG 1424 -592 bitline
SYMBOL nmos4 1328 688 R0
SYMATTR InstName M1
SYMATTR Value2 l={mc(SA_nset_L, process_var)} w={mc(SA_nset_W, process_var)}
SYMBOL voltage -448 -400 R0
SYMATTR InstName Veq
SYMATTR Value PULSE(0 {core_voltage*1.2} 0 0 0 14n)
SYMBOL voltage 48 -432 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE({core_voltage} 0 {20n + psense_act} 0 0)
SYMATTR InstName Vsp
SYMBOL nmos4 1648 560 R0
SYMATTR InstName M2
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W, process_var)}
SYMBOL nmos4 1536 560 M0
SYMATTR InstName M3
SYMATTR Value2 l={mc(SA_nmos_L,process_var)} w={mc(SA_nmos_W,process_var)}
SYMBOL nmos4 1664 368 M270
SYMATTR InstName M4
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W, process_var)}
SYMBOL nmos4 1456 384 M90
SYMATTR InstName M5
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1632 384 M90
SYMATTR InstName M6
SYMATTR Value2 l={mc(SA_eq_L,process_var)} w={mc(SA_eq_W,process_var)}
SYMBOL nmos4 1232 -624 R0
SYMATTR InstName M7
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1024 -400 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_0
SYMATTR SpiceLine IC={-plate_voltage + cell0_charge}
SYMBOL nmos4 1808 896 R0
SYMATTR InstName M8
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL cap 1840 1056 R0
SYMATTR Value {mc(cell_cap, process_var)}
SYMATTR InstName cell_cap_2
SYMBOL voltage -736 -928 R0
SYMATTR InstName Vra0
SYMATTR Value PULSE(0 0 0 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL pmos4 1296 80 M180
SYMATTR InstName M9
SYMATTR Value2 l={mc(SA_pset_L, process_var)} w={mc(SA_pset_W, process_var)}
SYMBOL pmos4 1648 208 M180
SYMATTR InstName M10
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W,process_var)}
SYMBOL pmos4 1536 208 R180
SYMATTR InstName M11
SYMATTR Value2 l={mc(SA_pmos_L, process_var)} w={mc(SA_pmos_W, process_var)}
SYMBOL voltage 416 -432 R0
SYMATTR SpiceLine Rser=100 Cpar=1fF
SYMATTR Value PULSE(0 {core_voltage} {20n + nsense_act} 0 0)
SYMATTR InstName Vsn
SYMBOL cap 1472 -112 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_0
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL cap 2000 640 R0
SYMATTR Value {mc(bitline_cap, process_var)}
SYMATTR InstName BL_cap_1
SYMATTR SpiceLine IC={core_voltage/2}
SYMBOL res 1408 -48 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R1
SYMBOL res 1952 416 R0
SYMATTR Value {mc(bitline_R, process_var)}
SYMATTR InstName R2
SYMBOL voltage -928 -416 R0
SYMATTR InstName Vra2
SYMATTR Value PULSE(0 {mc(0, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -144 96 R0
SYMATTR Value {core_voltage}
SYMATTR InstName VDD_source
SYMBOL voltage 144 96 R0
SYMATTR Value {core_voltage/2}
SYMATTR InstName VDD_source2
SYMBOL voltage 448 96 R0
SYMATTR Value {plate_voltage}
SYMATTR InstName VDD_source1
SYMBOL nmos4 1232 -784 R0
SYMATTR InstName M12
SYMATTR Value nmos_access_tran
SYMATTR Value2 l={mc(access_tran_L,process_var)} w={mc(access_tran_W,process_var)}
SYMBOL voltage -736 -1168 R0
SYMATTR InstName Vra1
SYMATTR Value PULSE(0 0 0 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -2016 -1168 R0
SYMATTR InstName Vra3
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}
SYMBOL voltage -2016 -912 R0
SYMATTR InstName Vra4
SYMATTR Value PULSE(0 {mc(wordline_voltage*wl0_act, process_var)} 20n 0 0)
SYMATTR SpiceLine Rser={mc(wordline_R*WL_res_factor, process_var)} Cpar={mc(wordline_C*WL_cap_factor, process_var)}