* SPICE netlist
M1 N002 N001 0 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
V1 Vdd 0 5
V2 N001 0 1.5
V3 N003 0 1.5
M2 0 N001 N002 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
M3 N002 N001 0 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
M4 0 N001 N002 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
M5 N002 N001 0 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
M6 0 N001 N002 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
M7 N002 N001 0 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
V4 N002 N003 0
M8 0 N001 N002 Vdd PMOS l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
.dc V3 0 5 1m
.param Wbuf=5.7u
.param Lmin = 0.6u, W = 2.4u, Ld=1.2u
.include C5_models.txt

* LTspice schematic (.asc)
Version 4
SHEET 1 768 1056
WIRE 320 -528 112 -528
WIRE 208 -480 112 -480
WIRE 64 -448 -16 -448
WIRE -80 -416 -80 -432
WIRE 112 -416 112 -432
WIRE 112 -416 -80 -416
WIRE 112 -400 112 -416
WIRE 144 -352 112 -352
WIRE 208 -352 208 -480
WIRE 208 -352 144 -352
WIRE -16 -320 -16 -448
WIRE 64 -320 -16 -320
WIRE 112 -288 112 -304
WIRE 208 -288 112 -288
WIRE 320 -288 320 -528
WIRE 320 -288 208 -288
WIRE 112 -272 112 -288
WIRE 144 -224 144 -352
WIRE 144 -224 112 -224
WIRE -16 -192 -16 -320
WIRE 64 -192 -16 -192
WIRE -80 -160 -80 -416
WIRE 112 -160 112 -176
WIRE 112 -160 -80 -160
WIRE 112 -144 112 -160
WIRE 144 -96 144 -224
WIRE 144 -96 112 -96
WIRE -16 -64 -16 -192
WIRE 64 -64 -16 -64
WIRE 112 -32 112 -48
WIRE 208 -32 208 -288
WIRE 208 -32 112 -32
WIRE 112 -16 112 -32
WIRE 144 32 144 -96
WIRE 144 32 112 32
WIRE -16 64 -16 -64
WIRE 64 64 -16 64
WIRE -80 96 -80 -160
WIRE 112 96 112 80
WIRE 112 96 -80 96
WIRE 112 112 112 96
WIRE -272 144 -384 144
WIRE -80 144 -80 96
WIRE -80 144 -192 144
WIRE 144 160 144 32
WIRE 144 160 112 160
WIRE -16 192 -16 64
WIRE 64 192 -16 192
WIRE 112 224 112 208
WIRE 208 224 208 -32
WIRE 208 224 112 224
WIRE 112 240 112 224
WIRE 144 288 144 160
WIRE 144 288 112 288
WIRE -16 320 -16 192
WIRE 64 320 -16 320
WIRE -80 352 -80 144
WIRE 112 352 112 336
WIRE 112 352 -80 352
WIRE 112 368 112 352
WIRE 384 384 384 368
WIRE 144 416 144 288
WIRE 144 416 112 416
WIRE 160 416 144 416
WIRE -16 448 -16 320
WIRE 64 448 -16 448
WIRE 208 464 208 224
WIRE 208 464 112 464
WIRE 112 480 112 464
FLAG 160 416 Vdd
FLAG 112 480 0
FLAG 384 464 0
FLAG 384 368 Vdd
FLAG -16 528 0
FLAG -384 224 0
SYMBOL pmos4 64 368 R0
SYMATTR InstName M1
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL voltage 384 368 R0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -16 432 R0
SYMATTR InstName V2
SYMATTR Value 1.5
SYMBOL voltage -384 128 R0
SYMATTR InstName V3
SYMATTR Value 1.5
SYMBOL pmos4 64 240 R0
SYMATTR InstName M2
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL pmos4 64 112 R0
SYMATTR InstName M3
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL pmos4 64 -16 R0
SYMATTR InstName M4
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL pmos4 64 -144 R0
SYMATTR InstName M5
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL pmos4 64 -272 R0
SYMATTR InstName M6
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL pmos4 64 -400 R0
SYMATTR InstName M7
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1
SYMBOL voltage -176 144 R90
SYMATTR InstName V4
SYMATTR Value 0
SYMBOL pmos4 64 -528 R0
SYMATTR InstName M8
SYMATTR Value2 l='Lmin' w='Wbuf' ad='Ld*Wbuf' as='Ld*Wbuf' pd='2*Ld+2*Wbuf' ps='2*Ld+2*Wbuf' m=1