Package: vsg
Coding style enforcement for VHDL.AnnouncementsUpdate 11/05/2023Release 3.18.0There were several alignment rules which were ignoring thecomment_line_ends_groupoption.
Please be aware that some alignment rules may trigger from the previous release.
Refer to issue #988 for more details.There was also an issue with YAML configurations with options usingyesandno.
These options could be converted to booleans by PyYAML according to the YAML spec if they were not strings.
Due to this an effort was made to change all theTrueandFalseoptions toyesandnostrings.
The originalTrueandFalseare still supported, but going forward all options will be strings.
Refer to issue #1009 for more details.Platform independent features were added in this release.
This includes line separators and file path separators.
The type of line separator can be based on the platform or hard coded.Regards,–JeremyTable of ContentsOverviewKey BenefitsKey FeaturesKnown LimitationsInstallationUsageDocumentationContributingOverviewVSG was created after participating in a code review where a real issue in the code was masked by a coding style issue.
A finding was created for the style issue, while the real issue was missed.
When the code was re-reviewed, the real issue was discovered.Depending on your process, style issues can take a lot of time to resolve.Create finding/ticket/issueDisposition finding/ticket/issueFixVerify fixSpending less time on style issues leaves more time to analyze the substance of the code.
This ultimately reduces the amount of time performing code reviews.
It also allows reviewers to focus on the substance of the code.
This will result in a higher quality code base.Key BenefitsDefine VHDL coding standardsMakes coding standards visible to everyoneImprove code reviewsQuickly bring code up to current standardsVSG allows the style of the code to be defined and enforced over part or the entire code base.
Configurations allow for multiple coding standards.Key FeaturesCommand line toolintegrate into continuous integration flow with JUnit outputReports and fixes issues foundwhitespacehorizontalverticalupper and lower casekeyword alignmentsetc…Fully configurable rules via JSON or YAML configuration fileDisable rulesAlter behavior of existing rulesLocalize rule setsCreate your own rules using pythonUse existing rules as a templateFully integrates into base rule setBuilt in stylesUse existing style or create your ownKnown LimitationsVSG is a continual work in progress.
As such, this version has the following known limitations:Parser will not process embedded PSLParser will not process VHDL 2019InstallationYou can get the latest released version of VSG viapip.pipinstallvsgThe latest development version can be cloned…gitclonehttps://github.com/jeremiah-c-leary/vhdl-style-guide.git…and then installed locally…pythonsetup.pyinstallUsageVSG is a both a command line tool and a python package.
The command line tool can be invoked with:$vsgusage:VHDLStyleGuide(VSG)[-h][-fFILENAME[FILENAME...]][-lrLOCAL_RULES][-cCONFIGURATION[CONFIGURATION...]][--fix][-fpFIX_PHASE][-jJUNIT][-jsJSON][-of{vsg,syntastic,summary}][-b][-ocOUTPUT_CONFIGURATION][-rcRULE_CONFIGURATION][--style{indent_only,jcl}][-v][-ap][--fix_onlyFIX_ONLY][--stdin][--quality_reportQUALITY_REPORT][-pJOBS][--debug][FILENAME...]AnalyzesVHDLfilesforstyleguideviolations.Referencedocumentationislocatedat:http://vhdl-style-guide.readthedocs.io/en/latest/index.htmlpositionalarguments:FILENAMEFiletoanalyzeoptions:-h,--helpshowthishelpmessageandexit-fFILENAME[FILENAME...],--filenameFILENAME[FILENAME...]Filetoanalyze-lrLOCAL_RULES,--local_rulesLOCAL_RULESPathtolocalrules-cCONFIGURATION[CONFIGURATION...],--configurationCONFIGURATION[CONFIGURATION...]JSONorYAMLconfigurationfile(s)--fixFixissuesfound-fpFIX_PHASE,--fix_phaseFIX_PHASEFixissuesuptoandincludingthisphase-jJUNIT,--junitJUNITExtractJunitfile-jsJSON,--jsonJSONExtractJSONfile-of{vsg,syntastic,summary},--output_format{vsg,syntastic,summary}Setstheoutputformat.-b,--backupCreatesacopyofinputfileforcomparisonwithfixedversion.-ocOUTPUT_CONFIGURATION,--output_configurationOUTPUT_CONFIGURATIONWriteconfigurationtofilename.-rcRULE_CONFIGURATION,--rule_configurationRULE_CONFIGURATIONDisplayconfigurationofarule--style{indent_only,jcl}Usepredefinedstyle-v,--versionDisplaysversioninformation-ap,--all_phasesDonotstopwhenaviolationisdetected.--fix_onlyFIX_ONLYRestrictfixingviaJSONfile.--stdinReadVHDLinputfromstdin,disablesallotherfileselections,disablesmultiprocessing--quality_reportQUALITY_REPORTCreatecodequalityreportforGitLab-pJOBS,--jobsJOBSnumberofparalleljobstouse,defaultisthenumberofcpucores--debugDisplaysverbosedebuginformationHere is an example output running against a test file:pre-commit IntegrationHere is an example of.pre-commit-config.yamlfile:repos:-repo:https://github.com/jeremiah-c-leary/vhdl-style-guiderev:v3.18.0hooks:-id:vsgDocumentationAll documentation for VSG is hosted atread-the-docs.ContributingI welcome any contributions to this project.
No matter how small or large.There are several ways to contribute:Bug reportsCode base improvementsFeature requestsPull requestsPlease refer to the documentation hosted atread-the-docsfor more details on contributing.