Package: uvm-python
UVM library for PythonThis is a port of SystemVerilog (SV) Universal Verification Methodology (UVM)
1.2 to Python and cocotb. Icarus Verilog (iverilog) and Verilator have been used for
testing the code so far.See documentation for more details:uvm-python Documentation.uvm-python User's GuideSystemVerilog UVM is not currently supported by any open source/free tools. cocotb offers
excellent solution to interact with any simulator (free/proprietary), so
testbenches can be written in Python as well.uvm-pythontries to offer
an API similar to the original SV-UVM version. This means that many UVM verificaton
skills and API knowledge are transferable from SV to Python very easily.If you want to port a larger bulk of SV code to useuvm-python, you can try the
scriptbin/sv2py.plas the first step. It's a regex-based solution, and code
will still require lots of manual edits to work.DocumentationThe documentation is available onreadthedocs.ioinuvm-python HTML documentation.InstallationYou can install uvm-python as a normal Python package. It is recommended to usevenvto create a virtual
environment for Python prior to installation.Install from PyPi using pip:python-mpipinstalluvm-pythonor directly from source files (for the latest development version):gitclonehttps://github.com/tpoikela/uvm-python.gitcduvm-python
python-mpipinstall.# If venv is used# Or without venv, and no sudo:python-mpipinstall--user.# Omit --user for global installationSeeMakefilefor working examples. You can
also use Makefiles intest/examples/simpleas a
template for your project.Running the examples and developmentSeetest/examples/simple/Makefilefor working examples. More features/examples will be added
incrementally.To run all tests:SIM=icarusmaketest# Use iverilog as a simulatorTo run unit tests only:make test-unit  # Does not require simulatorMinimal working exampleuvm-pythonmust be installed prior to running the example. Alternatively, you
can create a symlink to theuvmsource folder:cdtest/examples/minimal
ln-s../../../src/uvmuvmSIM=icarusmakeYou can find the
source code for this examplehere. This example
creates a test component, registers it with the UVM factory, and starts the test.You can execute the example by runningSIM=icarus make. Alternatively, you can
run it withSIM=verilator make.# File: MakefileTOPLEVEL_LANG?=verilogVERILOG_SOURCES?=new_dut.svTOPLEVEL:=new_dutMODULE?=new_testinclude $(shell cocotb-config --makefiles)/Makefile.simThe top-level module must matchTOPLEVELinMakefile:// File: new_dut.svmodulenew_dut(inputclk,inputrst,output[7:0]byte_out);assignbyte_out=8'hAB;endmodule:new_dutThe Python test file name must matchMODULEinMakefile:# File: new_test.pyimportcocotbfromcocotb.triggersimportTimerfromuvmimport*@uvm_component_utilsclassNewTest(UVMTest):asyncdefrun_phase(self,phase:UVMPhase):phase.raise_objection(self)awaitTimer(100,"NS")uvm_info("NEW_TEST","Test passed, all OK",UVM_MEDIUM)phase.drop_objection(self)@cocotb.test()asyncdeftest_dut(dut):awaitrun_test('NewTest')Current statusTestbenches can already be written with all the typical UVM
components. UVM Phasing is in place, and working. Stimulus can be generated
using (even hierarchical) sequences. Register
layer supports already read/write to registers (via frontdoor), and to
memories (frontdoor and backdoor). TLM 1.0 is implemented,
put/get/analysis interfaces are done, and master/slave interfaces work. Initial
implementation of TLM2.0 has also been added. The table below summarizes the
status:FeatureStatusTLM1.0DoneTLM2.0DoneComponentsDonePhasesDoneObjectionsTest and env-level objections workSequencesPartially done, hier sequences workRegistersReg/mem access working, built-in sequences partially donePlease try it out, and let me know if
something you require should be added, or even better, add it yourself, test it
and create a pull request!HDL SimulatorsTested with Icarus Verilog (iverilog v13.0 (devel)) and verilator (v5.008). The
exact commit for iverilog can be found fromci/install_iverilog.sh.Icarus Verilog and verilator are free simulators, which can
be used with cocotb. uvm-python uses cocotb to interface with these simulators.
Memory backdoor access has issues with packed multi-dimensional arrays in
verilator. Also, some other examples are not working with verilator yet.Proprietary simulators that work with cocotb should work with
uvm-python as well, but haven't been tested.Related projectscocotbcosimulation library for writing testbenches in Pythonuvm-python-verification-libUVM Python Verification Agents Library