Package: rapidstream-cocotb
cocotbis a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.Read thedocumentationGet involved:Raise a bug / request an enhancement(Requires a GitHub account)Join the Gitter chat roomInstallationThe current stable version of cocotb requires:Python 3.6+GNU Make 3+An HDL simulator (such asIcarus Verilog,Verilator,GHDLorother simulator)After installing these dependencies, the latest stable version of cocotb can be installed with pip.pip install cocotbFor more details on installation, including prerequisites,
seethe documentation.For details on how to install thedevelopmentversion of cocotb,
seethe preliminary documentation of the future release.!!! Bus and Testbenching Components !!!The reusable bus interfaces and testbenching components have recently been moved to thecocotb-buspackage.
You can easily install these at the same time as cocotb by adding thebusextra install:pip install cocotb[bus].UsageAs a first trivial introduction to cocotb, the following example "tests" a flip-flop.First, we need a hardware design which we can test. For this example, create a filedff.svwith SystemVerilog code for a simpleD flip-flop. You could also use any other language acocotb-supported simulatorunderstands, e.g. VHDL.// dff.sv`timescale1us/1nsmoduledff(outputlogicq,inputlogicclk,d);always@(posedgeclk)beginq<=d;endendmoduleAn example of a simple randomized cocotb testbench:# test_dff.pyimportrandomimportcocotbfromcocotb.clockimportClockfromcocotb.triggersimportRisingEdgefromcocotb.typesimportLogicArray@cocotb.test()asyncdefdff_simple_test(dut):"""Test that d propagates to q"""# Assert initial output is unknownassertLogicArray(dut.q.value)==LogicArray("X")# Set initial input value to prevent it from floatingdut.d.value=0clock=Clock(dut.clk,10,units="us")# Create a 10us period clock on port clk# Start the clock. Start it low to avoid issues on the first RisingEdgecocotb.start_soon(clock.start(start_high=False))# Synchronize with the clock. This will regisiter the initial `d` valueawaitRisingEdge(dut.clk)expected_val=0# Matches initial input valueforiinrange(10):val=random.randint(0,1)dut.d.value=val# Assign the random value val to the input port dawaitRisingEdge(dut.clk)assertdut.q.value==expected_val,f"output q was incorrect on the{i}th cycle"expected_val=val# Save random value for next RisingEdge# Check the final input on the next clockawaitRisingEdge(dut.clk)assertdut.q.value==expected_val,"output q was incorrect on the last cycle"A simple Makefile:# MakefileTOPLEVEL_LANG=verilogVERILOG_SOURCES=$(shellpwd)/dff.svTOPLEVEL=dffMODULE=test_dffinclude $(shell cocotb-config --makefiles)/Makefile.simIn order to run the test with Icarus Verilog, execute:make SIM=icarusFor more information please see thecocotb documentationandour wiki.Tutorials, examples and related projectsthe tutorial sectionin the official documentationcocotb-busfor pre-packaged testbenching tools and reusable bus interfaces.cocotb-based USB 1.1 test suitefor FPGA IP, with testbenches for a variety of open source USB corescocotb-coverage, an extension for Functional Coverage and Constrained Randomizationuvm-python, an almost 1:1 port of UVM 1.2 to Pythonour wikion extension modulesthe list ofGitHub projects depending on cocotb