Package: ruapu
ruapuDetect CPU ISA features with single-fileCPU✅ x86, x86-64✅ arm, aarch64✅ mips✅ powerpc✅ s390x✅ loongarch✅ risc-v✅ openrisc#define RUAPU_IMPLEMENTATION#include"ruapu.h"intmain(){// initialize ruapu onceruapu_init();// now, tell me if this cpu has avx2inthas_avx2=ruapu_supports("avx2");return0;}OS✅ Windows✅ Linux✅ macOS✅ Android✅ iOS✅ FreeBSD✅ NetBSD✅ OpenBSDCompiler✅ GCC✅ Clang✅ MSVC✅ MinGWBest practice for usingruapu.hin multiple compilation unitsCreate oneruapu.cfor your projectruapu.cisONLY#define RUAPU_IMPLEMENTATIONand#include "ruapu.h"Other sources#include "ruapu.h"butNO#define RUAPU_IMPLEMENTATIONLet's ruapuruapu with CCompile ruapu test program# GCC / MinGWgccmain.c-oruapu# Clangclangmain.c-oruapu# MSVCcl.exe/Fe:ruapu.exemain.cRun ruapu in command line./ruapummx=1sse=1sse2=1sse3=1ssse3=1sse41=1sse42=1sse4a=1xop=0...morelinesomitted...ruapu with PythonCompile and install ruapu library# from source codepip3install.Use ruapu in pythonimportruapuruapu.supports("avx2")# Trueruapu.supports(isa="avx2")# TrueGithub-hosted runner result (Linux)mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0Github-hosted runner result (macOS)mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 0
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0Github-hosted runner result (macOS M1)neon = 1
vfpv4 = 1
cpuid = 0
asimdhp = 1
asimddp = 1
asimdfhm = 1
bf16 = 0
i8mm = 0
sve = 0
sve2 = 0
svebf16 = 0
svei8mm = 0
svef32mm = 0Github-hosted runner result (Windows)mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0FreeBSD/NetBSD/OpenBSD VM result (x86_64)mmx = 1
sse = 1
sse2 = 1
sse3 = 1
ssse3 = 1
sse41 = 1
sse42 = 1
sse4a = 1
xop = 0
avx = 1
f16c = 1
fma = 1
fma4 = 0
avx2 = 1
avx512f = 0
avx512bw = 0
avx512cd = 0
avx512dq = 0
avx512vl = 0
avx512vnni = 0
avx512bf16 = 0
avx512ifma = 0
avx512vbmi = 0
avx512vbmi2 = 0
avx512fp16 = 0
avxvnni = 0
avxvnniint8 = 0
avxifma = 0FeaturesDetectCPU ISA with single-filesse2,avx,avx512f,neon, etc.Detectvendor extended ISAappleamx, risc-v vendor ISA, etc.Detectricher ISA on Windows ARMIsProcessorFeaturePresent()returns little ISA informationDetectx86-avx512on macOS correctlymacOS hides it incpuidDetectnew CPU's ISA on old systemsthey are usually not exposed inauxvorMISADetectCPU hidden ISAfma4on zen1, ISA in hypervisor, etc.Supported ISA(more is comming ... :)CPUISAx86mmxssesse2sse3ssse3sse41sse42sse4axopavxf16cfmafma4avx2avx512favx512bwavx512cdavx512dqavx512vlavx512vnniavx512bf16avx512ifmaavx512vbmiavx512vbmi2avx512fp16avxvnniavxvnniint8avxifmaarmedspneonvfpv4idivaarch64neonvfpv4cpuidasimdrdmasimdhpasimddpasimdfhmbf16i8mmmtesvesve2svebf16svei8mmsvef32mmpmullcrc32aessha1sha2sha3sha512sm3sm4amxmipsmsapowerpcvsxs390xzvectorloongarchlsxlasxrisc-vimafdczfazfhzfhminzicsrzifenceizmmulopenriscorbis32orbis64orfpx32orfpx64orvdx64Techniques inside ruapuruapu is implemented in C language to ensure the widest possible portability.ruapu determines whether the CPU supports certain instruction sets by trying to execute instructions and detecting whether anIllegal Instructionexception occurs. ruapu does not rely on the cpuid instructions and registers related to the CPU architecture, nor does it rely on theMISAinformation and system calls of the operating system. This can help us get more detailed CPU ISA information.FAQWhy is the project named ruapuruapu is the abbreviation of rua-cpu, which means using various extended instructions to harass and amuse the CPU (rua!). Based on whether the CPU reacts violently (throws an illegal instruction exception), it is inferred whether the CPU supports a certain extended instruction set.Why is ruapu API designed like thisWe consider gcc builtin functions to be good practice, saying__builtin_cpu_init()and__builtin_cpu_supports(). ruapu refers to this design, which can be a 1:1 replacement for gcc functions, and supports more operating systems and compilers, giving it better portability.Why does SIGILL occur when executing in debugger or simulator, such asgdb,lldb,qemu-user,sdeetc.Because debuggers and simulators capture the signal and stop the ruapu signal handler function by default, we can continue execution at this time, or configure it specifically, such ashandle SIGILL nostopin gdb. ruapu technically cannot prevent programs from stopping in debuggers and emulatorsHow to add detection capabilities for new instructions to ruapuAssume that the new extended instruction set is namedruaAddRUAPU_INSTCODE(rua, rua-inst-hex) // rua r0,r0andRUAPU_ISAENTRY(rua)inruapu.hAddPRINT_ISA_SUPPORT(rua)inmain.cto print the detection resultAdd entries aboutruain README.mdCreate a pull request!https://godbolt.org/is a good helper to view the compiled binary code of instructions.Repos that use ruapuncnnHigh-performance neural network inference frameworklibllmEfficient inference of large language modelsCredits@nihuiWrite the initial POC code and ruapu maintainer@kernelbinImplement exception handling for Windows@zchrissirhczDetect x86 FMA4@MollySophiaFix C++ export symbol@strongtzDetect more aarch64 ISA@monkeykingDetect apple arm64 AMX@junchao-loongsonAdd loongarch support@ziyao233Detect more risc-v ISA@dreamcmiDetect more risc-v ISA@cocoa-xuAdd FreeBSD support, python support@YuzukiTsuruAdd OpenRISC supportLicenseMIT License