Package: mnt.pyfiction
fiction– Design Automation for Field-coupled NanotechnologiesThis code base provides a C++17 framework forfield-coupledtechnology-independentopennanocomputing developed as part of theMunich Nanotech Toolkit(MNT) by theChair for Design Automationat theTechnical University of Munich.
Withinfiction, algorithms for logic synthesis, placement, routing, clocking, verification, and simulation forField-coupled Nanocomputing (FCN)technologies are implemented.To this end, most physical design tasks can be performed on generic data structures that abstract from particular
technology or cell design. Using an extensible set of gate libraries, technologies, and cell types, these can easily
be compiled down to any desired FCN technology for physical simulation.For these use cases,fictionprovides
aheader-only librarythat provides data types and algorithms for recurring tasks, e.g., logic network and layout types on different
abstraction levels, clocking schemes, gate libraries, design automation algorithms, etc. Additionally,fictioncomes
with an ABC-likeCLI toolthat allows quick access to its core functionality.If you have any questions, feel free to contact us viafcn.cda@xcit.tum.deor by
creating an issue onGitHub.Quick StartClone the repository and its submodules:gitclone--recursivehttps://github.com/cda-tum/fiction.gitThe CLIInside the newly clonedfictionfolder, trigger the build process:cmake.-Bbuildcdbuild
cmake--build.-j4Run the CLI tool:cli/fictionHere is an example of runningfictionto perform a full physical design flow on a QCA circuit layout that can
afterward be simulated in QCADesigner:The Header-only LibraryAddfictionas a sub-directory to your CMake project and link againstlibfiction(assuming your project is
calledfanfiction):add_subdirectory(fiction/)target_link_libraries(fanfictionlibfiction)Include the headers you need:#include<fiction/layouts/cell_level_layout.hpp>#include<fiction/layouts/clocking_scheme.hpp>#include<fiction/technology/qca_one_library.hpp>#include<fiction/io/write_qca_layout.hpp>#include<fiction/...>For a full getting started guide, please refer to
thedocumentation.Supported TechnologiesPhysical design infictioncan be performed technology-independent. Only if resulted layouts are to be physically,
simulated, a specific technology implementation is required. To this end,fictionsupports various potential FCN
implementations together with gate libraries to compile gate-level layout abstractions down to the cell level.
Additionally, output formats for external physical simulator engines are also supported.Quantum-dot Cellular Automata (QCA)Gate libraries:QCA ONEFile formats:*.qcaforQCADesigner*.qllforMagCADandSCERPA*.fqcaforQCA-STACK*.svgfor visual representationMany thanks to Frank Sill Torres for his support with the QCADesigner format, to Willem Lambooy for his support with the
QCA-STACK format, and to Sophia Kuhn for implementing the SVG writer!in-plane Nanomagnet Logic (iNML)Gate libraries:ToPoliNanoFile formats:*.qccforToPoliNano*.qllforToPoliNano & MagCADMany thanks to Umberto Garlando, Fabrizio Riente, and Giuliana Beretta for their support!Silicon Dangling Bonds (SiDBs)Gate libraries:BestagonFile formats:*.sqdforSiQADMany thanks to Samuel Sze Hang Ng for his support!Implemented Design Automation AlgorithmsThefictionframework provides implementations of state-of-the-art design automation algorithms for FCN technologies.
These algorithms can be used in evaluation scripts to perform logic synthesis, physical design, layout verification, and
physical simulation.Logic SynthesisFor logic synthesis,fictionrelies on themockturtle librarythat offers a
multitude of logic network types and optimization algorithms. Logic synthesis can be performed in external tools and
resulting Verilog/AIGER/BLIF/... files can be parsed byfiction. Alternatively, sincemockturtleis included infiction, synthesis can be applied in the same evaluation script.Physical DesignFor automatic FCN layout obtainment,fictionprovides algorithms that
receivemockturtle logic networksas input
specification and output placed, routed, and clocked generic FCN circuits.Among these algorithms areSMT-basedexact placement and routingOGD-basedscalable placement and routingSAT-basedone-pass synthesisSAT-basedmulti-path routingplus several path-finding algorithms that work on generic layouts:shortest path via theA* algorithmkshortest paths viaYen's algorithmVerificationLayout correctness can bevalidatedusingDesign Rule Violation (DRV)checkingSAT-basedformal verification(equivalence checking)Physical SimulationWhen a layout is compiled to the cell level via the application of a technology-dependent gate library, it can be
simulated using a physical model. Currently, the following simulation algorithms are implemented infiction:Silicon Dangling Bonds (SiDBs)QuickExactQuickSimGroundstate SimulationCritical TemperatureExhaustive Groundstate Simulation(ExGS)Clocking SchemesRegular clocking schemes have been proposed in the FCN literature, which can be used as a floor plans for physical
design. However, sometimes it can make sense to have more freedom and assign clock numbers on the fly. That is
whyfictionsupports bothregular and irregular clocking schemeswith variable amounts of clock numbers as QCA for instance uses four clock phases but iNML needs only three.Built-in schemes areColumnarRow2DDWaveUSERESESRCFEBANCSplus the mentioned irregular open clocking that works via a clock map instead of a regular extrapolated cutout.Wire CrossingsWith many FCN technologies considered planar, wire crossings should be minimized if possible. However, there are some
options in QCA where, using a second layer, crossings over short distances and co-planar rotated cells become possible.
As both are just technical implementations of the same concept,fictionsupports crossings as wires in a second grid
layer in its data structures for all FCN technologies. They will also be represented as such in corresponding SVG and
QCADesigner output. However, note that it is to be interpreted as the concept of crossings and could also be realized
co-planar.Wires are only allowed to cross other wires! Wires crossing gates is considered to lead to unstable signals.Gate Pins vs. Designated I/OsIn the literature, both are seen: having input cells (pins) directly located in the gate structure or using designated
I/O elements that are located outside of gates. This distinction only makes sense on the gate level andfictionsupports both approaches and offers usage in the implemented physical design algorithms.Multi WiresGate-level abstraction has its limits. Often, chip area is wasted when only using a single wire per tile. Infiction,
cell-level layouts allow for precise control over cell placement and can, thus, also create multiple wire segments per
clock zone. Physical simulation can give an indication of whether the built structures are implementing the intended
functionality.Synchronization ElementsA technology extension proposes to utilize the external clock signal generator in an unconventional way: by creating
further asymmetric clock signals with extendedHoldphases that are assigned to specific wire
tiles,synchronization elementscan be created that stall signals over
multiple clock cycles. These artificial latches are able to feed information to any other clock number, but their usage
reduces the overall throughput of the layout. In return, long wire detours for signal synchronization can be prevented.Cost MetricsDesigned layouts can be evaluated with regard to several cost functions. The following metrics are currently
implemented:Gate-level layouts:Circuit dimension in tilesNumber of gate tilesNumber of wire tilesNumber of wire crossingsNumber ofsynchronization elementsCritical pathThroughputBounding boxEnergy dissipation based on aphysical model(QCA only)Cell-level layouts:Circuit dimension in cellsNumber of cellsBounding boxArea usage in nm²ReferenceSincefictionis academic software, we would be thankful if you referred to it by citing the following publication:@misc{fiction,author={Walter, Marcel and Wille, Robert and Sill Torres, Frank and Gro{\ss}e, Daniel and Drechsler, Rolf},title={{fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits}},archivePrefix={arXiv},eprint={1905.02477},note={arXiv:1905.02477},year={2019},month={May}}Additionally, many algorithms implemented infictionhave been published individually. For a full list of
publications, please refer to thedocumentation.