Package: litex
Copyright 2012-2023 / Enjoy-Digital & LiteX developersWelcome to LiteX!The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and createfull FPGA based  systems.LiteX SoC builder framework quick tour/overview:SlidesWant to get started and/or looking for documentation? Make sure to visit theWiki!A question or want to get in touch? Join us onDiscordor on our IRC channel: [#litex at irc.libera.chat].LiteX provides all the common components required to easily create an FPGA Core/SoC::heavy_check_mark: Buses and Streams (Wishbone, AXI, Avalon-ST) and their  interconnect.:heavy_check_mark: Simple cores: RAM, ROM, Timer, UART, JTAG, etc….:heavy_check_mark: Complex cores through the ecosystem of cores:LiteDRAM,LitePCIe,LiteEth,LiteSATA, etc...:heavy_check_mark: Various CPUs & ISAs: RISC-V, OpenRISC, LM32, Zynq, X86 (through a PCIe), etc...:heavy_check_mark: Mixed languages support with VHDL/Verilog/(n)Migen/Spinal-HDL/etc... integration capabilities.:heavy_check_mark: Powerful debug infrastructure through the variousbridgesandLitescope.:heavy_check_mark: Direct/Fast simulation throughVerilator.:heavy_check_mark: Build backends for open-source and vendors toolchains.:heavy_check_mark: And a lot more... :)By combining LiteX with the ecosystem of cores, creating complex SoCs becomes a lot easier than with traditional approaches while providing better portability and flexibility: Here is for example a Multi-core Linux Capable SoC based on VexRiscv-SMP CPU, LiteDRAM, LiteSATA built and integrated with LiteX, running on a cheap repurposedAcorn CLE215+ Mining Board:For more info, have a look atLinux-on-LiteX-Vexriscvproject and try running Linux on your FPGA board!LiteX's digital logic is currently described withMigenwhich does not prevent users to create mixed language projects:It's very common and easy to integrate VHDL/Verilog/SystemVerilog/nMigen/Spinal-HDL code in LiteX!It's also very common to do the opposite and generate the LiteX design as a verilog file and integrate it in a traditional flow.LiteX was initially developed byEnjoy-Digitalto create projects for clients (and we are still using it for that :)) and trying to take the different clients' requirements/needs consideration made, we think, the framework very flexible:Some users only want to use it to easily interconnect their existing VHDL/Verilog/SV cores.Some users are only interested to reuse the PCIe/Ethernet/SATA/etc cores as regular core and just integrate them in their traditional flow.Some users with a hardware background start with the above approaches and then switch later to the full Python flow since find it more efficient.Some users with a software background and fluent with Python start playing with FPGAs while they would probably never touch FPGA otherwise :)Etc...We are well aware that everyone has a different background, so it's up to you to pick the right approach with LiteX that will be convenient for you!To get started we encourage you to read thewiki.You already have a FPGA board(s)? VisitLiteX-Boardsto see if your board(s) is already supported!The framework is also far from perfect and we'll be happy to have yourfeedback or/and contributions.Have fun! :wink:Moral precisions: The project is shared with a permissive BSD 2-Clause License and we are encouraged to continue sharing it this way thanks to the awesome community and clients willing to support the project!
If the projet is useful for your research, hobby or commercial projects, we are just asking you to be coherent and behave with integrity: Don't expect free support or that the community will be welcoming if your spent your time complaining about the project (and then direspect developers) or don't pay the custom developments you asked for... (While it's probably natural for 99% of users/clients, it  does seems useful to add this for the 1% remaining that are eating lots of our energy/time).Typical LiteX design flow:+---------------+
                                      |FPGA toolchains|
                                      +----^-----+----+
                                           |     |
                                        +--+-----v--+
                       +-------+        |           |
                       | Migen +-------->           |
                       +-------+        |           |        Your design
                                        |   LiteX   +---> ready to be used!
                                        |           |
              +----------------------+  |           |
              |LiteX Cores Ecosystem +-->           |
              +----------------------+  +-^-------^-+
               (Eth, SATA, DRAM, USB,     |       |
                PCIe, Video, etc...)      +       +
                                         board   target
                                         file    fileLiteX already supports various softcores CPUs: VexRiscv, Rocket, LM32, Mor1kx, PicoRV32, BlackParrot and is compatible with the LiteX's Cores Ecosystem:NameBuild StatusDescriptionLiteX-BoardsBoards supportLiteDRAMDRAMLiteEthEthernetLitePCIePCIeLiteSATASATALiteSDCardSD cardLiteICLinkInter-Chip communicationLiteJESD204BJESD204BLiteSPISPI/SPI-FlashLiteScopeLogic analyzerExamples of designs built with LiteX:Custom PCIe SDI Capture/Playback board built around LitePCIe and integrated with LiteX, allowing full control of the SDI flow and very low latency.Alternative firmware/gateware for the SDS1104X-E Scope:HBM2 test infrastructure on Forest Kitten 33:To discover more products/projects built with LiteX, visit theprojects pageon the Wiki.Sponsors/Partners:A huge shoutout to our awesome industrial clients who have given us the green light to incorporate some of the developments we initially created for them directly into LiteX! These innovative developments often provide the building blocks for the features that the wider community can then use and improve upon. Your support has been instrumental for the project, and we are incredibly grateful for your partnership. Thanks!Papers, Presentations, Tutorials, LinksFPGA lessons/tutorials:https://github.com/enjoy-digital/fpga_101Migen tutorial:https://m-labs.hk/migen/manualOSDA 2019 paper/slides:https://osda.gitlab.io/19/1.1.pdfhttps://osda.gitlab.io/19/1.1-slides.pdfLinux on LiteX-Vexriscv:https://github.com/litex-hub/linux-on-litex-vexriscvRISC-V Getting Started Guide:https://risc-v-getting-started-guide.readthedocs.io/en/latest/LiteX vs. Vivado First Impressions:https://www.bunniestudios.com/blog/?p=501835C3 - Snakes and Rabbits - How CCC shaped an open hardware success:https://www.youtube.com/watch?v=AlmVxR0417cTim has to many projects - LatchUp Edition:https://www.youtube.com/watch?v=v7WrTmexod0Sub-packageslitex.genProvides specific or experimental modules to generate HDL that are not integrated in Migen.litex.build:Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to simulate HDL code or full SoCs.litex.soc:Provides definitions/modules to build cores (bus, bank, flow), cores and tools to build a SoC from such cores.Quick start guideInstall Python 3.6+ and FPGA vendor's development tools and/orVerilator.Install Migen/LiteX and the LiteX's cores:$wgethttps://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
$chmod+xlitex_setup.py
$./litex_setup.py--init--install--user(--usertoinstalltouserdirectory)--config=(minimal,standard,full)Later, if you need to update all repositories:$./litex_setup.py--updateNote:On MacOS, make sure you haveHomeBrewinstalled. Then do,brew install wget.Note:On Windows, it's possible you'll have to setSHELLenvironment variable toSHELL=cmd.exe.Install a RISC-V toolchain (Only if you want to test/create a SoC with a CPU):$pip3installmesonninja
$./litex_setup.py--gcc=riscvBuild the target of your board...:Go to litex-boards/litex_boards/targets and execute the target you want to build.... and/or installVerilatorand test LiteX directly on your computer without any FPGA board:On Linux (Ubuntu):$sudoaptinstalllibevent-devlibjson-c-devverilator
$litex_sim--cpu-type=vexriscvOn MacOS:$brewinstalljson-cverilatorlibevent
$brewcaskinstalltuntap
$litex_sim--cpu-type=vexriscvRun a terminal program on the board's serial port at 115200 8-N-1.You should get the BIOS prompt like the one below.CommunityOver the years a friendly community has grown around LiteX and the ecosystem of cores. Feedbacks and contributions have already greatly improved the project, EnjoyDigital still leads the development but it is now a community project and collaborative projects created around/with LiteX can be found athttps://github.com/litex-hub.ContactE-mail:florent@enjoy-digital.fr