Package: litepcie
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                               Copyright 2015-2022 / EnjoyDigital

                            A small footprint and configurable PCIe core
                                     powered by Migen & LiteX[> IntroLitePCIe provides a small footprint and configurable PCIe core.LitePCIe is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations
of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...Using Migen to describe the HDL allows the core to be highly and easily configurable.LitePCIe can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core.[> FeaturesPHY:Xilinx Ultrascale(+) (up to PCIe Gen3 X16).Xilinx 7-Series (up to PCIe Gen2 X8).Intel Cyclone5  (up to PCIe Gen2 X4).64/128/256/512-bit datapath.Clock domain crossing.Core:TLP layer.Reordering.MSI (Single, Multi-vector)/MSI-X.Crossbar.Frontend:DMA (with Scatter-Gather).MMAP (AXI/Wishbone Slave/Master).Software:Linux Driver (MMAP and DMA).[> FPGA ProvenLitePCIe is already used in commercial and open-source designs:3G-SDI Capture/Playback board:http://www.enjoy-digital.fr/experience/pcie_3g_sdi.jpgSDR MIMO 2x2 board:https://www.amarisoft.com/products-lte-ue-ots-sdr-pcie/#sdrSDR MIMO 4x4 board:http://www.enjoy-digital.fr/experience/pcie_ad937x.jpgSDR CPRI board:http://www.enjoy-digital.fr/experience/pcie_sfp.jpgPCIe TLP sniffer/injector:https://ramtin-amin.fr/#nvmedmaand others commercial designs...[> Possible improvementsadd standardized interfaces (AXI, Avalon-ST)add Intel Stratix supportadd Lattice supportadd more documentation... See below Support and consulting :)If you want to support these features, please contact us at florent [AT]
enjoy-digital.fr.[> Getting startedInstall Python 3.6+ and FPGA vendor's development tools.Install LiteX and the cores by following the LiteX's wikiinstallation guide.You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.[> TestsUnit tests are available in ./test/.
To run all the unit tests:$./setup.pytestTests can also be run individually:$python3-munittesttest.test_name[> LicenseLitePCIe is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use LiteEth for closed-source
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:tell us that you are using LitePCIecite LitePCIe in publications related to research it has helpedsend us feedback and suggestions for improvementssend us bug reports when something goes wrongsend us the modifications and improvements you have done to LitePCIe.[> Support and consultingWe love open-source hardware and like sharing our designs with others.LitePCIe is developed and maintained by EnjoyDigital.If you would like to know more about LitePCIe or if you are already a happy
user and would like to extend it for your needs, EnjoyDigital can provide standard
commercial support as well as consulting services.So feel free to contact us, we'd love to work with you! (and eventually shorten
the list of the possible improvements :)[> ContactE-mail: florent [AT] enjoy-digital.fr