Package: kratos
Kratos is a hardware design language written in C++/Python. It
differentiates itself from other DSL with the following design
philosophy:Fully debuggable: debug hardware just like debugging Python code!
Thanks tohgdb.Highly efficient: Python frontend powered by
Modern C++ binding. Designed with multi-processing in mind.Human-readable verilog: we know how difficult it is to read machine
generated verilog. kratos has multiple passes to produce nice-looking
verilog.Generator of generators: every python object is a generator
that can be modified at any time, even after instantiation. This allows
complex passes on the generators without ripping old structure apart.Keep the good parts of SystemVerilog, such asalways_ff,always_comb,interface, andunique case. Users control
how and when to generate these semantics.Single source of truth: kratos encourages users to infuse generator
information inside generator itself. This makes debugging and
verification much easier.Static elaboration: kratos allows user to write parametrized code,
even in thealwaysblock, all in Python.Type checking: kratos check the variable types
for each assignment to make sure there is no implicit conversion.Installpip install kratosPre-built wheels support all Python 3.6+ on Linux, Windows, and
OSX. To build it from scratch, you need aC++17compatible
compiler, such asg++-8orclang-8.Documentation and ExamplesYou can check the documentation atRead the
Docs.Here are some examples to showcase the ability of kratos.Async Reset RegisterPython code that parametrizes based on thewidth. Notice that we
specify the sensitivity of thealways_ffblock when definingseq_code_block.classAsyncReg(Generator):def__init__(self,width):super().__init__("register")# define inputs and outputsself._in=self.input("in",width)self._out=self.output("out",width)self._clk=self.clock("clk")self._rst=self.reset("rst")# add combination and sequential blocksself.add_code(self.seq_code_block)@always_ff((posedge,"clk"),(posedge,"rst"))defseq_code_block(self):ifself._rst:self._out=0else:self._out=self._inHere is the generated SystemVerilogmoduleregister(inputlogicclk,inputlogic[15:0]in,outputlogic[15:0]out,inputlogicrst);always_ff@(posedgeclk,posedgerst)beginif(rst)beginout<=16'h0;endelseout<=in;endendmodule// registerFanout moduleThis is another example to showcase the kratos’ ability to produce high-quality
SystemVerilog. In practice we would not write it this way.classPassThrough(Generator):def__init__(self,num_loop):super().__init__("PassThrough")self.in_=self.input("in",1)self.out_=self.output("out",num_loop)self.num_loop=num_loopself.add_code(self.code)@always_combdefcode(self):ifself.in_:foriinrange(self.num_loop):self.out_[i]=1else:foriinrange(self.num_loop):self.out_[i]=0Here is generated SystemVerilog. Notice that the iteration variableihas been properly checked and resized to avoid index out of range.modulePassThrough(inputlogicin,outputlogic[3:0]out);always_combbeginif(in)beginfor(intunsignedi=0;i<4;i+=1)beginout[2'(i)]=1'h1;endendelsebeginfor(intunsignedi=0;i<4;i+=1)beginout[2'(i)]=1'h0;endendendendmodule// PassThroughHow to debugBecause Python is quite slow, By default the debug option is off. You
can turn on debugging for individual modules. Seetests/test_generator.pyfor more details).Use an IDE DebuggerThanks to the native support ofhgdb, you can debug the generated RTL with a
professional debugger as if you are debugging Python code.gdb-like console version
is also available. Check outhgdbto see how it works!