Package: ipsocgen
IP SoC GeneratorIP SoC genis a framework to generate MP/SoCs with different configurations through a set of masters/slaves for fast
digital design development. To install through pip:pipinstall--upgradeipsocgenTemplate projectsIn order to get started generating your own designs, check thetemplate
repositorywhich contains an example of SoC and MPSoC usingNoXprocessor as the main CPU. The configuration files that were used for theipsocgen_templateare available inipsocgen/examples/template_soc.yamlandipsocgen/examples/template_mpsoc.yaml.To contribute/develop/extend the workPlease follow the steps below to build the virtual environment and install the dependencies.python3-mvenvvenvsourcevenv/bin/activatepython3setup.pyinstallConfiguration file referenceHere is a list of all inputs that can be listed for the IPSoCGen configuration file in yaml format.proj_name:#Project Namedesc:#Short descriptiontype:#System type (soc or mpsoc)###################### If type == soc#####################soc_desc:bus_name:#Name for the bus Interconnectbus_type:#Type of the busaddr_width:#Bus adress widthdata_width:#Bus data widthtxn_id_width:#Bus transaction ID widthnum_masters:#Number of master in the bus (min == 1)num_slaves:#Number of slave in the bus (min == 1)proc_required:#Set if a processor is required (y or n)mmap_type:#Memory map type (manual or auto)clk:name:#Clock nameclk_int:#Internal signal name for the clockio_in_clk:#Wrapper input pin for the clocktype:#Type of clock (pll or direct)pll:#Only applicable if type == plldivclk_divide:#PLL parametersclkfbout_mult:#PLL parametersclkout_divide:#PLL parametersio_rst_pin:#Wrapper input pin for the PLL resetrst_in_type:#Type of reset for the PLL (act_l or act_h)clkin_period:#PLL parametersrst:name:#Reset namerst_int:#Internal signal name for the resetio_in_rst:#Wrapper input pin for the resetrst_in_type:#Type of reset for the PLL (act_l or act_h)type:#Type of reset (acc_rst or direct)proc:name:#Name of the main CPU that will be usedtype:#Type of processor (nox, vex…)clk:#Describe the clock of the processorrst:#Describe the reset of the processorboot:#Describe the boot for this processortype:#Type of boot (slave, value or signal)signal:#Only applicable if type == signalslave:#Only applicable if type == slavevalue:#Only applicable if type == valueirq_mapping:timer:#Internal signal name for RV timer interruptssoftware:#Internal signal name for RV software interruptsexternal:#Internal signal name for RV external interruptsmasters:#Describe all masters within the systemx:#Master ID, start always from 0name:#Unique name for the instancedesc:#Brief description of the master I/Ftype:#Master typeif:#Interface name (must be a valid one supported)...slaves:x:#Slave ID, start always from 0name:#Unique name for the instancedesc:#Brief description of the slavetype:#Slave typebase_addr:#Base address if mmap_type == manualaddr_width:#Base address if mmap_type == manualmem_size_kib:#Slave kib size, only applicable if type == ram_mem/rom_mem/acc_custom_slaveirq_timer:#Timer internal signal name, only applicable if type == acc_timerrst_def_addr:#Reset default address, only applicable if type == acc_rstrst_addr_out:#Reset address signal name [usually for CPUs], only applicable if type == acc_rstrst_pulse_width:#Reset address signal name [usually for CPUs], only applicable if type == acc_rstio_bootloader:#Wrapper input pin for the bootloader, only applicable if type == acc_rstbootloader_type:#Bootloader type (act_l or act_h), only applicable if type == acc_rstirq_dma_done:#Internal signal name for the DMA done IRQ, only applicable if type == acc_dmairq_dma_error:#Internal signal name for the DMA error IRQ, only applicable if type == acc_dmaio_tx:#Wrapper output pin for the UART TX, only applicable if type == acc_uartio_rx:#Wrapper input pin for the UART TX, only applicable if type == acc_uartirq_uart_rx:#Internal signal name for the UART IRQ, only applicable if type == acc_uartirq_type:#IRQ type (0-level, 1-edge) for all incomming IRQs, only applicable if type == acc_irqirq_summary:#Internal signal name for the IRQ summary, only applicable if type == acc_irqvec_mapping:#List of all internal signal names for the IRQ vector, only applicable if type == acc_irq-highest_prior_irq_1-…-lowest_prior_irq_nirq_noc:#Internal signal name for the NoC IRQ, only applicable if type == acc_nocpkt_recv_irq:#Internal signal name for the Received Packet IRQ, only applicable if type == acc_ethpkt_sent_irq:#Internal signal name for the Packet sent IRQ, only applicable if type == acc_ethpkt_recv_full_irq:#Internal signal name for the Full FIFO Recv. Packet IRQ, only applicable if type == acc_etheth_type:#Ethernet slave type (csr, infifo or outfifo), only applicable if type == acc_eth...###################### If type == mpsoc#####################mpsoc_desc:clk:name:#Clock nameclk_int:#Internal signal name for the clockio_in_clk:#Wrapper input pin for the clocktype:#Type of clock (pll or direct)pll:#Only applicable if type == plldivclk_divide:#PLL parametersclkfbout_mult:#PLL parametersclkout_divide:#PLL parametersio_rst_pin:#Wrapper input pin for the PLL resetrst_in_type:#Type of reset for the PLL (act_l or act_h)clkin_period:#PLL parametersrst:name:#Reset namerst_int:#Internal signal name for the resetio_in_rst:#Wrapper input pin for the resetrst_in_type:#Type of reset for the PLL (act_l or act_h)type:#Type of reset (acc_rst or direct)noc:type:#Type of the noc (currently only ravenoc is available)name:#Unique name for the NoC instancesize_x:#Num. of rowssize_y:#Num. of collumnsflit_data_width:#Data width of the flitflit_buff:#Num. of flit buffersh_priority:#Priority of the virtual channels (ZeroHighPrior or ZeroLowPrior)n_virt_chn:#Num. of virtual channelsrouting_alg:#Routing algorithm (XYAlg or YXAlg)max_sz_pkt:#Max. size of packet in flits (usually 256)base_addr:#NoC common base address across all Tilestiles:x:#Tile ID, always start from zero....#Same description pattern as soc_desc