Package: hdlConvertor-binary
hdlConvertor(generated code)This library is a System Verilog and VHDL parser, preprocessor and code generator for Python/C++.
It contains:ANTLR4 generated VHDL/(System) Verilog parser with full language support.Convertors from raw VHDL/SV AST to universal HDL AST (hdlConvertor::hdlAstand it'spython equivalent.).Convertors from this HDL ASTto SV/VHDL/JSONand other formats.Compiler focusedutilsfor manipulation with HDL AST.HdlAstVisitor, id resolution, sensitivity detection, vhdl <-> verilog type conversion, ...Supported languages:IEEE 1076-2008 (VHDL 2008)and all previous standard, (currently withouttool_directiveandPSL)[IEEE 1076-2019] WIPIEEE 1800-2017 (SystemVerilog 2017)and all previous standards.InstallationLinux:
Installing dependencies (Ubuntu 20.10)# we recommend to use gcc>=9, Visual Studio 2017 or equivalent
sudo apt install build-essential uuid-dev cmake default-jre python3 python3-dev python3-pip libantlr4-runtime-dev antlr4 ninja-buildInstalling this library# note this may be older version than you see in repo
sudo pip3 install hdlConvertor

# or download repository and run
sudo pip3 install --upgrade --force-reinstall --no-cache-dir git+https://github.com/Nic30/hdlConvertorAst.git
sudo pip3 install -r requirements.txt
sudo python3 setup.py install

# if you are using version from git rather uninstall
# old library first if required
# sudo pip3 uninstall hdlConvertorInstaller also supports other options which may be usefullpython setup.py install --prefix /tmp/python_install/ --build-type Debug -- -DANTLR_JAR_LOCATION=/antlr-4.7.1-complete.jar -- VERBOSE=1You can also install only C++ library/generate .deb package (nothing specific, just normal cmake-based library)mkdir build && cd build
cmake .. && cmake . --build
cpack # to generate .deb packageWindows:Take a look at appveyor.yml anddoc/windows_installation_and_build.rst. It is required to download antlr4 first and have visual studio or other c++ compiler installed.UsageThe HDL AST (the parsed code) is represented by objects fromhdlConvertor.hdlAst. Parsing and code modification is straightforward, as you can see in following exampleSimilar projects:(Tell us If you know about some other project!)circt- C++, LLVM based infrastructutre for SV/VHDL/FIRRTL compilation and simulationcl-vhdl- lisp, Parser of VHDL into lisp-expressionsHDL_ANTLR4- C# projects that use ANTLR4 library to analyse VHDL and Verilog codehdlparse- vhdl/verilog parser in pythonieee1800_2017- Java, SystemVerilog preprocessoristyle-verilog-formatter- c++, Verilog formatterPyverilog- python verilog toolkitpyvsc- C++, library for Verification Stimulus and Coverage descriptionpyVHDLParser- python vhdl parser with 2008 supportRgGen- CSR (Configuration and Status Registers) generatorrust_hdl- rust vhdl 2008 parserslang- Parser and compiler library for SystemVerilog.sv-parser- Rust, SystemVerilog parser library fully complient with IEEE 1800-2017systemc-clang- SystemC Parser using the Clang Front-endv2sc- vhdl to systemcveelox- Java+ANTLR, An experiment in SystemVerilog Preprocessingverible-C++, SystemVerilog parser, style-linter, and formatterverilog-parser- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.vbpp- C, Verilog PreProcessortree-sitter-verilog- JS,  Verilog grammar for tree-sitterVerilog-Perlvpp.pl- verilog preprocessor with integrated Perlsv2v- Haskell, SystemVerilog to VerilogSurelog- C++, System Verilog 2017 Pre-processor and parserverible- C++, System Verilog 2017 parserUHDM- rust, universal hardware data model