Package: hwtLib
hwtLibhwtLib is the library of hardware components writen usinghwt library.
Any component can be exported as Xilinx Vivado (IP-exact) or Quartus IPcore usingIpPackageror as raw Verilog/VHDL/SystemC code and constraints byto_rtl() function. Target language is specified by keyword parameterserializer.ContentFor example there is a componentAxiLiteEndpoint, wich is configured using c-like data type description and it generates a address decoders and convertors to other intefaces if requested.
Another example isAxiS_frameParser, which is configured in same way and performs an extraction of the data fields from an input stream. Hwt type system does contains all c-like and SystemVerilog-like types but in addition it allows for better specification of padding and allignment and has an explicit data type for streams. This allows AxiS_frameParser to be easily configured to change alignemnt of the stream, cut/split/replace part of the steam with an easy to read HLS-like description.Verifications are write in UVM like style and ashwtbased design are actually a graph we can easily analyse them.
This is every usefull as it allows us to generate most of the test environment automatically in a user controlled and predictable way and write mostly only a test scenario. For example there is no need to build bus transactions manually asAddressSpaceProbecan discover the mapped address space (for any interface) and we can set register values using a proxy as if it was a normal value.
This means that you can write a verification which will have a component with arbitrary bus/address space and it will work as long as you keep the names of the registers the same.Clock frequencies and target chips usually does not matter but if componetgenerates constraintsit surely needs a correct clock period to generate them correctly.Also note that the code of the components should be shared if@serializeParamsUniqis used, the design for largest FPGAs takes 5s to generate. The verification should be also fast (take look at travis build) if this is not your case you are probably doing something wrong.abstract- abstract classes for component classes like bus endpoint, etcamba- AXI interfaces and components for them (AXI3/4 DMAs, interconnects, Axi-stream components, Axi4Lite address decoders etc...)avalon- same thing as amba just for Avalon interfaces (AvalonST, AvalonMM, ... and components for them)cesnet- components and interfaces specific to Cesnet designsclocking- various generic PLLs, timer generators etc.examples- demonstrative examples ofhwtfunctionalityhandshaked- components for handshaked interfaces (FIFO, AsyncFifo, Resizer, interconnects, Register, ...)img- image preprocessing utils (parse PNG font to bits for OLED, ...)interfaces- various interfaces which does not have it's package yetlogic- various components like CRC generator, gray counter, decoders-encoders ...mem- various memories (BRAM, ROM, FIFO, Async FIFO, CAM, LUT, ...)peripheral- various peripheral interfaces and components (I2C, MDIO, SPI, UART, USB, Ethernet, ...)sim- simulation utilsstructManipulators- DMAs for specific data structurestests- tests which are not related to another componentstypes- deffinitions of common types (uint32_t, ipv6_t, udp_t, ...)xilinx- components, primitives and interfaces specific to Xilinx based designs (IPIF, LocalLink, ...)If you see any problem/do not underestand something/do miss something open the github issue as others may step uppon same problem sooner or later.Installation# from PYPI (latest release)sudopip3installhwtLib# or from git (latest)sudopip3install-rhttps://raw.githubusercontent.com/Nic30/hwtLib/master/doc/requirements.txtgit+git://github.com/Nic30/hwtLib#egg=hwtLib--upgrade--no-cacheRepositories with opensource HW:analogdevicesinc/hdl/connectal- framework for software-driven hardware developmentcorundum- Packet DMAElphel repositories- Verilog, firmware for Zynq based camera with DDR3, HiSPi, JPEGenjoy-digital repositories- Migen, SoC level modulesFPGAwars FPGA-peripherals- Verilog, simple peripheralshdl4fpga- Verilog/VHDL various peripheralshdl-util- SV, various IOanalogdevicesinc/hdl- Verilog, Library of common components for AnalogDevices chip interfacingleon/grlib- Library of SoC componentsmyhdl-resources- MyHDL list of projectsNyuziProcessor- GPGPUopencores- everythingopenrisc- OpenRISC, FuseSoC, peripherals and cpu partspicorv32- Verilog, A Size-Optimized RISC-V SoCPoC- VHDL, utilspulp-platformrhea- MyHDL, SoC level modulesSpinalCrypto- SpinalHDL, various crypto/hash functionssurf- VHDL, SoC/DSP/IO/Ethernet focused componentstinyfpgaxultraembedded/cores- mostly Verilog, mostly peripheralsZipCPU repositories- Verilog, mostly peripherals, DSPhls-fpga-machine-learning- Python -> HSL C++, mostyl ML and video processingfpgasystems- HLS C++, SystemVerilog, FPGA @ Systems Group, ETH Zurich, mostly networkingLimago- SV/VHDL - 100G TCP/IP stack