Package: hwt
HWToolkit (hwt),the library for hardware development in PythonKeywordsMetaprogramming (Hardware Construction Language HCL, templatization) + HLS.Simulator API, UVMBuildtool, IP core generatorHow HWT can help you?The lower layer (IR, HDL serializers) is a shield against a problems related to VHDL/Verilog. It is checking for correctness and synthetisability and removing specific of HDLs.The system level and HLS layer allows you to quickly build desing generators with advance optimisation techniques of your choice.Simulator API and it's UVM simulation environment is just python object with C++ binding. This makes it easy to use while not sacrificing performance.Rich type system can describe also data locality and packet features. This significantly simplifies configuration of component which are working with packets or any data over remote bus.HWT is not compiler nor transpiler but it is actually a core library. It contains only necessary stuff and you can can modify/extend any part any time.
Because the word of HW developement is always full of unexpected situations.FeaturesHardware Construction Language (HCL) (examplesimple,showcase). It is somewhere between HLS and HDL. It offers HLS style of coding but at the same time it allows you to manipulate HDL objects. This means it is a little bit slower to write a prototype than you would in HLS, but you always know what, how and why is happening.Digital circuit simulator with UVM like verification environment (example usageCAM,structWriter_test.py)Tools for static analysis (resourceAnalyzer, example usagecntr_test.py)Serializers to export HWT designs into multiple target HDLs (verilog, VHDL, system-c, IP-core packager, hwt itself...)HWT uses hilevel-netlists for internal representation of target design. Optimized netlists are generated from usual code statements, function calls, statements etc (hw processes are automatically resolved). This netlist is easy to use and easy to modify or analyse by user if there is something missing in main library.
Alsoserialization modesallows to tweaks how component should behave during serialization.HWT performs no HLS planing or schedueling. HWT is also good as API for code generating by more advanced tools. Hierarchy of components/interfaces/types is not limited. User specifed names are checked for collision with target language.HWT designs are objects. No specific exceution is required, just runpython3, import the thing and useto_rtlmetod or other (take a look atexamples).HWT ecosystemInstallationThis library is a regular python package. You can install it using:# system-wide, use -u for local use only
sudo pip3 install hwt

# or directly from git
pip3 install --upgrade --force-reinstall --no-cache-dir -r https://raw.githubusercontent.com/Nic30/hwt/master/doc/requirements.txt git+git://github.com/Nic30/hwt.git@master#egg=hwtThen you are able to use functions and classes defined in the hwt library from a python console or script.
Installation ofhwtLibis recomended as it contains common interfaces, agents, components etc...FAQWhere is the entry point of the compiler?This is not a compiler, it is library of the objects which can be converted to Verilog/VHDL and back.How do I get Verilog/VHDL?Useto_rtlmethodexampleHow do I define my interface type, protocol and simulation agent?Derive from any Interface class.exampleI do have c structure of UDP header, how do I send/recieve UDP packet over AXI-stream interface?Define HStruct type composed of eth_header_t, IPv4_header_t and HStream(uint8_t) and useAxisFrameGen. There is and example ofping responderSimilar projectsautofpga- C++, A utility for Composing FPGA designs from PeripheralsBinPy- Python, An electronic simulation libraryblarney- Haskell, HCLbsc- Haskell, C++, BSV - Bluespec Compilerchisel- 2012-?, Scala, HCLChips-2.0- , , FPGA Design Suite based on C to Verilog design flowcirct- 2020-?, C++/LLVM, compiler infrastructurecircuitgraph- Tools for working with circuits as graphs in pythonconcat- 2016-?, Haskell, Haskell to hardwareDUH- JS, simple convertor between verilog/scala/ipxactDFiant2019-?, Scala, dataflow based HDLedalize- 2018-?, Python, abstraction layer for eda toolsgarnet-2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magmahammer- 2017-?, Python, Highly Agile Masks Made Effortlessly from RTLheterocl- 2017-?, C++, A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computinghoodlum- 2016-?, Rust, HCLILAng- modeling and verification platform for SoCs where Instruction-Level Abstraction (ILA) is used as the formal model for hardware components.:skull:jhdl- ?-2017, C++ Verilog/VHDL -> systemC, prototypeKactus2- IP-core packagerkratos- C++/Python, hardware generator/simulatorlgraph- C, generic graph libraryllhd- Rust, HCLlivehd- mainly C++, An infrastructure designed for Live Hardware Development.Lucid HDL in Alchitry-Labs- Custom language and IDE inspired by Verilogmagma- 2017-?, Python, HCLmigen- 2013-?, Python, HCLmockturtle- logic network librarymoore- Rust, HDL -> model compilerMyHDL- 2004-?, Python, Process based HDLnmigen-, Python, A refreshed Python toolbox for building complex digital hardwareOpenTimer- , C++,  A High-Performance Timing Analysis Tool for VLSI Systemspercy- Collection of different synthesizers and exact synthesis methods for use in applications such as circuit resynthesis and design exploration.PyChip-py-hcl- , Python, Chisel3 like HCLpygears- , Python, function style HDL generatorPyMTL32018-?PyMTL- 2014-?, Python, Process based HDLPipelineC- 2018-?, Python, C++ HLS-like automatic pipelining as a language construct/compilerPyRTL- 2015-?, Python, HCLPyverilog- 2013-? Python-based Hardware Design Processing Toolkit for Verilog HDLrogue, C++/Python - Hardware Abstraction & Data Acquisition Systemsail2018-?, (OCaml, Standard ML, Isabelle) - architecture definition languagespatial- Scala, an Argon DSL like, high level abstractionSpinalHDL- 2015-?, Scala, HCLSilice- ?, C++, Custom HDL:skull:SyDpy- ?-2016, Python, HCL and verif. framework operating on TML/RTL levelsystemrdl-compiler- Python,c++, register description language compilerUHDM- C++ SystemVerilog -> C++ model:skull:Verilog.jl- 2017-2017, Julia, simple Julia to Verilog transpilerveriloggen- 2015-?, Python, Verilog centric HCL with HLS like features:skull:wyre- 2020-2020, Mupad, Minimalistic HDLRelated open-sourcefusesoc- package manager and a set of build tools for FPGA/ASIC developmentOpenSTA- a gate level static timing verifierRePlAce- global placement toolverilator- Verilog -> C/C++ simulatorvtr-verilog-to-routingyosys- RTL synthesis frameworkUHDM- SV -> C++Board support libraries (Potential candidates for public integration)litex- Buildsystem for migenloam- Buildsystem for magmavivado-boards- Vivado XML/TCL files with board descriptionnmigen-boards- board and connector meta fo nmigenSources of informations in this areacomputer-engineering-resources- list of conferences and hardware projects