Package: cocotbext-ahb
Cocotb AHB bus driverTable of ContentsIntroductionInstallationClasses and usage exampleLicenseIntroductionThis repository contains AHB drivers (AHB and AHB Lite) and a monitor forcocotb.InstallationInstallation from pip (release version, stable):$pipinstallcocotbext-ahbInstallation for active development:$gitclonehttps://github.com/aignacio/cocotbext-ahbThe repository contains a small script that starts a container fetched from Docker Hub, equipped with all the required development tools.$cdcocotbext-ahb/
$./ship.shOnce the container is up and running, to run the tests throughnoxandpytest, run the following:$nox-l# See the available build options$nox-srun-3.xx# Replace xx by a python version you want to testThe command above will take some time to complete (depends on your machine cfg) because it will run all the tests and its variants, generating waveforms in eachrun_dir/*folder. At the end of the test run, you can open the waveforms for each test in this format using gtkwave:gtkwaverun_dir/sim_build_icarus_(TEST_NAME)/ahb_template.fstdocs_utils/template.gtkwRunning specific tests:$nox-srun-3.10---k"test_ahb_monitor_slave"# Runs on python 3.10, the test_ahb_monitor_slaveFor the list of test, please check thetests/directory.Classes and usage exampleThis AHB extension is composed by master, slaves and a single monitor. Thus, the following available classes are:AHB Master- WIP for burst support, base class AHB Lite MasterAHB Lite Master- Perform AHB transactions in non-/pipeline modeAHB Slave- WIP for burst support, base class AHB Lite SlaveAHB Lite Slave- Support any type of AHB transaction but burst with back-pressure option and configurable default valueAHB Monitor- Basic monitor to check AHB transactionsAHB BusAll the different master/slaves and also the monitor requires anAHBBusobject to be passed to their constructors. This AHBBus object will map each of the AHB I/F pins the dut, some IOs are mandatory but others are optional. In order to create an AHBBus object, here are the two ways.With a prefix:# In case your DUT has some prefix for the AHB I/F# For instance if all AHB signals are following this convention:# - test_haddr# - test_hsel# - ...AHBBus.from_prefix(dut,"test")Without a prefix:# In case your DUT has no prefix for the AHB I/F# For instance if all AHB signals are following this convention:# - haddr# - hsel# - ...AHBBus.from_entity(dut)For reference, down below is the class header ofAHB Bus. More arguments can also be passed as this extends fromcocotb-busbase class.classAHBBus(Bus):_signals=["haddr","hsize","htrans","hwdata","hrdata","hwrite","hready","hresp"]_optional_signals=["hburst","hmastlock","hprot","hnonsec","hexcl","hmaster","hexokay","hsel","hready_in"]Mandatory vs optional AHB signalsAHB Master signalsMandatoryhaddr - Indicates AHB txn addresshsize - Indicates AHB txn sizehtrans - Indicates AHB txn typehwdata - Indicates AHB data to be writtenhwrite - Indicates type of AHB txnOptionalhbursthmastlockhprothnonsechexclhmasterhselhready_inAHB Slave signalsMandatoryhresp - Indicates AHB txn response typehrdata - Indicates AHB txn read datahready - Indicates AHB slave availabilityOptionalhexokaySignal customization for your designTo customize signals name to your designsignalsandoptional_signalsdictionnary can be provide.AHBBus.from_prefix(dut,prefix="slave_driver",signals={"haddr":"haddr","hsize":"hsize","htrans":"htrans","hwdata":"hwdata","hrdata":"hrdata","hwrite":"hwrite","hready":"hreadyout","hresp":"hresp"},optional_signals={"hsel":"hsel","hready_in":"hready"})Mandatory vs optional AHB signalsAHB Master signalsMandatoryhaddr - Indicates AHB txn addresshsize - Indicates AHB txn sizehtrans - Indicates AHB txn typehwdata - Indicates AHB data to be writtenhwrite - Indicates type of AHB txnOptionalhburstAHB MasterBoth AHB Master [WIP] and AHB Lite Master classes have the same constructor arguments. Within the arguments, it is required to pass the AHB Bus object, the clock and reset DUT pins. As optional args, a timeout value in clock cycles (per AHB txn), the default value of the master driven IOs and the name of the object.classAHBLiteMaster:def__init__(self,bus:AHBBus,clock:str,reset:str,timeout:int=100,def_val:Union[int,str]="Z",name:str="ahb_lite",**kwargs,):In case of AHB Slave error response, the master will cancel the current transaction changing HTRANS from NSEQ to IDLE in the second clock cycle of the error response and then it will retry immediately after (following clock cycle). This is not mandatory but gives time for the master to decide whether it needs to be aborted or not the following transaction.Its methods are composed byread(),write()andcustom().WriteFor writes, the arguments are listed here:asyncdefwrite(self,address:Union[int,Sequence[int]],value:Union[int,Sequence[int]],size:Optional[Union[int,Sequence[int]]]=None,pip:Optional[bool]=False,)->Sequence[dict]:Argumentsaddress - Single or a list of integer addresses to be writtenvalue - Single or a list of integer values to be writtenOptional[size] - Integer number of bytes to be written (for instance, in 32-bit bus, 1, 2 or 4 bytes), default is the max bus sizeOptional[pip] - Define if the address/data phase will overlap in a pipeline manner or not, default non-pipelinedReturnSequence[dict] - Once all transactions are dispatched and their responses are received, the function returns a list of dict withAHBRespresponses along with the data.Note: address, value and size have to match their length if provided.ReadFor reads, the arguments are listed here:asyncdefread(self,address:Union[int,Sequence[int]],size:Optional[Union[int,Sequence[int]]]=None,pip:Optional[bool]=False,)->Sequence[dict]:Argumentsaddress - Single or a list of integer addresses to be read fromOptional[size] - Integer number of bytes to be read (for instance, in 32-bit bus, 1, 2 or 4 bytes), default is the max bus sizeOptional[pip] - Define if the address/data phase will overlap in a pipeline manner or not, default non-pipelinedReturnSequence[dict] - Once all transactions are dispatched and their responses are received, the function returns a list of dict withAHBRespresponses along with the data.Note: address and size have to match their length if provided.CustomA third method provides flexibility in case the user wants to perform read or writes together like back-to-back operations such as WAR or RAW. For this, the arguments are listed here:asyncdefcustom(self,address:Union[int,Sequence[int]],value:Union[int,Sequence[int]],mode:Union[int,Sequence[int]],size:Optional[Union[int,Sequence[int]]]=None,pip:Optional[bool])->Sequence[dict]:Argumentsaddress - Single or a list of integer addresses to be written to or read fromvalue - Single or a list of integer addresses to be written to or read frommode - Single or a list of operation types - 0 (Read) or 1 (Write)Optional[size] - Integer number of bytes to be written/read (for instance, in 32-bit bus, 1, 2 or 4 bytes), default is the max bus sizeOptional[pip] - Define if the address/data phase will overlap in a pipeline manner or not, default non-pipelinedReturnSequence[dict] - Once all transactions are dispatched and their responses are received, the function returns a list of dict withAHBRespresponses along with the data.Note: address, value, mode and size have to match their length if provided.AHB SlaveBoth AHB Slave [WIP] and AHB Lite Slave classes have the same constructor arguments. Within the arguments, it is required to pass the AHB Bus object, the clock and reset DUT pins. As optional arg, the default value of the slave driven IOs, a generator function to force back-pressure and the name of the object.classAHBLiteSlave:def__init__(self,bus:AHBBus,clock:str,reset:str,def_val:Union[int,str]="Z",bp:Generator[int,None,None]=None,name:str="ahb_lite",**kwargs,):The AHB slaves will not provide any specific data (always zero) or unexpected response, they serve as a basic slave just to check its connectivity while testing AHB Master and as a base class for the AHB Lite Slave RAM. The back-pressure feature is a way to force the slave to demonstrated unavailability while the master issue AHB transactions. The generator needs to return bool type values where bool True indicates slave available and bool False indicate slave unavailable.In case of an AHB error response, the Slave inserts a wait state (HREADY == LOW && HRESP == OKAY) however this not required and might change in the future sticking only to the mandatory obligation of 2-cycle error response:First: HREADY == LOW / HRESP == ERRORSecond: HREADY == HIGH / HRESP == ERRORAHB Lite Slave RAMThe AHB Lite Slave RAM is a basic memory slave that can receive reads and write like a normal memory-mapped device. The only difference between the normal slave vs this one is the fact that as part of its constructor, a new argumentmem_sizeis listed. This argument defines a memory size in bytes for the AHB slave. The only limitation for now, is the fact that all memory addresses have to be aligned to the data bus width, i.e for 32-bit slaves, address[1:0] == 2'b00.classAHBLiteSlaveRAM(AHBLiteSlave):def__init__(self,bus:AHBBus,clock:str,reset:str,def_val:Union[int,str]="Z",bp:Generator[int,None,None]=None,name:str="ahb_lite_ram",mem_size:int=1024,**kwargs,):Thank you@alexforencichfor your work on the memory classes that were leveraged in this project.AHB MonitorA basic AHB monitor was also developed, the idea is to ensure that basic protocol assumptions are respected throughout assertions, its constructor arguments are very similar to the previous discussed classes. For now, only two aspects are checked through this monitor, the first one ensure the master does not change its address phase transaction qualifier once a transaction is issued and the slave is not available. The second property checks that an AHB error response coming from the slave is following the 2-cycle response defined in the AMBA spec.classAHBMonitor:def__init__(self,bus:AHBBus,clock:str,reset:str,name:str="ahb_monitor",**kwargs,):ExampleA basic example of this extension usage is demonstrated below and also within thetests folderthat are available.importcocotbimportosimportrandomimportmathfromconstimportcfgfromcocotb_test.simulatorimportrunfromcocotb.triggersimportClockCyclesfromcocotb.clockimportClockfromcocotbext.ahbimportAHBBus,AHBLiteMaster,AHBLiteSlaveRAM,AHBResp,AHBMonitordefrnd_val(bit:int=0,zero:bool=True):ifzeroisTrue:returnrandom.randint(0,(2**bit)-1)else:returnrandom.randint(1,(2**bit)-1)defpick_random_value(input_list):ifinput_list:returnrandom.choice(input_list)else:returnNone# Return None if the list is emptyasyncdefrun_test(dut):data_width=32mem_size_kib=16N=1000# Map the bus monitor to the I/F slave_h* I/Fahb_lite_mon=AHBMonitor(AHBBus.from_prefix(dut,"slave"),dut.hclk,dut.hresetn)# Create an AHB Lite Slave RAM connected to the master I/Fahb_lite_sram=AHBLiteSlaveRAM(AHBBus.from_prefix(dut,"master"),dut.hclk,dut.hresetn,def_val=0,bp=bp_fn,mem_size=mem_size_kib*1024,)# Create an AHB Lite Master connected to the slave I/Fahb_lite_master=AHBLiteMaster(AHBBus.from_prefix(dut,"slave"),dut.hclk,dut.hresetn,def_val="Z")# Create a lit of non-repeated addresses spaces by 8 from 0->2*current RAM sizeaddress=random.sample(range(0,2*mem_size_kib*1024,8),N)value=[rnd_val(data_width)for_inrange(N)]size=[pick_random_value([1,2,4])for_inrange(N)]# Perform the writes and readsresp=awaitahb_lite_master.write(address,value,size,pip=pip_mode)resp=awaitahb_lite_master.read(address,size,pip=pip_mode)Example waveformsLicensecocotbext-ahb is licensed under the permissive MIT license.Please refer to theLICENSEfile for details.