Package: circuitbrew
Welcome to CircuitBrewCircuitBrew provides a framework for building SPICE-based circuits and generating test vectors
for arbitrarily complex transistor-based circuits directly in Python.Free and open-source software: ASL2 licenseBlog:http://virantha.com/category/projects/circuitbrewDocumentation:http://virantha.github.io/circuitbrewSource:https://github.com/virantha/circuitbrewSome notable features of CircuitBrew over a schematic capture tool or a Domain
Specific Language based circuit design tool:Built-in test vector generation: With most other tools, I end up needing
to build a behavioral model in a high-level language like Python to
generate test vectors.  CircuitBrew provides the hooks to build the model inline with the
circuit description, and uses a built-in event simulator to generate expected vectors.Simplicity: Schematic capture for complex digital circuitdesigncan be
tedious. And learning/re-learning a circuit design DSL creates a lot of
overhead, especially when you want to jump in quickly and prototype a custom circuit. Here,
subckts are just Python classes, and ports are just init args; all the power of Python is
available to assemble complex digital circuits at the transistor level.Ease of maintenance: Extending a circuit design DSL, as SPICE models
evolve and become more complex, becomes incredibly time-consuming, especially
when the original tool authors have moved on from the code base.  Everything
here is built on standard Python features, and should be easily extensible.The examples below show SPICE files emitted for the open-source SkyWater 130nm PDK, to avoid
revealing any proprietary data, but I generally use this in my own work for advanced 7nm
and smaller-node foundries.Installation$pipinstallcircuitbrewUsagePlease see theusage guide.DisclaimerThe software is distributed on an "AS IS" BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.Simple exampleHere's a simple inverter implemented directly in Python:Inverter in PythonclassInv(Module):inp=InputPort()out=OutputPort()p=SupplyPort()defbuild(self):vdd,gnd=self.p.vdd,self.p.gndself.pup=Pfet(g=self.inp,d=vdd,s=self.out,b=vdd)self.ndn=Nfet(g=self.inp,d=self.out,s=gnd,b=gnd)self.finalize()classMain(Module):defbuild(self):self.inv=Inv('myinv')self.finalize()SPICE for a simple inverterCircuitBrew directly emits SPICE from this:.subcktMainxmyinvinp_0out_1p_2p_3Inv.ends.subcktInvinpoutp.gndp.vddxmn0outinpp.gndp.gndsky130_fd_pr__nfet_01v8_lvtw=1.0l=0.5xmp0p.vddinpoutp.vddsky130_fd_pr__pfet_01v8_lvtw=1.0l=0.5.endsxmainMainMore complex example with test vector generationHere's a more complex example that generates a simulation harness with test vector
generation and digital checking of outputs.  We generate random values that get
fed into the inverter, and verify them on the output in the SPICE sim.  CircuitBrew
contains custom Verilog-A modules that can handle driving and checking values digitally
inside an analog hspice simulation.Python for simulation/verification of an InverterclassInv(Module):inp=InputPort()out=OutputPort()p=SupplyPort()defbuild(self):vdd,gnd=self.p.vdd,self.p.gndself.pup=Pfet(g=self.inp,d=vdd,s=self.out,b=vdd)self.ndn=Nfet(g=self.inp,d=self.out,s=gnd,b=gnd)self.finalize()asyncdefsim(self):whileTrue:val=awaitself.inp.recv()awaitself.out.send(1-val)classMain(Module):defbuild(self):self.supply=Supply('vdd',self.sim_setup['voltage'],)p=self.supply.pvdd,gnd=p.vdd,p.gndself.inv=Inv('myinv',p=p)self.clk_gen=VerilogClock('clk',freq=750e3,enable=vdd)src_clk=self.clk_gen.clkself.clk_buc=VerilogClock('clk2',freq=750e3,offset='100p',enable=vdd)sample_clk=self.clk_buc.clkself.src=VerilogSrc('src',[randint(0,1)foriinrange(10)],d=self.inv.inp,clk=src_clk,_reset=vdd)self.bucket=VerilogBucket(name='buc',clk=sample_clk,_reset=vdd,d=self.inv.out)self.finalize()Generated SPICE with test bench.subcktMainxbucsample_clkp.vddd_0VerilogBucket_0xclk2p.vddsample_clkVerilogClockfreq=750000.0offset=100pxclkp.vddsrc_clkVerilogClockfreq=750000.0offset=0xmyinvinp_1d_0gndp.vddInvxsrcsrc_clkp.vddinp_1VerilogSrc_0xvddgndp.vddSupply.ends.subcktSupplyp.gndp.vddVvdd_vssp.gnd00.0Vvdd_vddp.vdd01.8.ends.subcktInvinpoutp.gndp.vddxmn0outinpp.gndp.gndsky130_fd_pr__nfet_01v8_lvtw=1.0l=0.5xmp0p.vddinpoutp.vddsky130_fd_pr__pfet_01v8_lvtw=1.0l=0.5.ends.hdlhspice_clk.va.hdltemplate_0_hspice_src.va.hdltemplate_0_hspice_bucket.vaxmainMain