Package: cengal-cpu-info
cengal_cpu_infoExtended, cached CPU info with consistent output format.AdvantagesConsistent output format of memory-related values (unlike backend 'py-cpuinfo' package). Provides additional information. Provides cached instance (backend 'py-cpuinfo' package requires several seconds per an each call to gather CPU information).Installationpipinstallcengal_cpu_infoDocumentationImportfromcengal_cpu_infoimportcpu_info,CpuInfoCached instanceci:CpuInfo=cpu_info()Methodsprint(f'{ci.is_arm=}')print(f'{ci.is_x86=}')print(f'{ci.cores_num=}')print(f'{ci.virtual_cores_num=}')print(f'{ci.l2_cache_size_per_core=}')print(f'{ci.l2_cache_size_per_virtual_core=}')print(f'{ci.l3_cache_size_per_core=}')print(f'{ci.l3_cache_size_per_virtual_core=}')print(f'{ci.arch=}')print(f'{ci.arch_string_raw=}')print(f'{ci.bits=}')print(f'{ci.brand_raw=}')print(f'{ci.count=}')print(f'{ci.cpuinfo_version=}')print(f'{ci.cpuinfo_version_string=}')print(f'{ci.family=}')print(f'{ci.flags=}')print(f'{ci.hardware_raw=}')print(f'{ci.hz_actual=}')print(f'{ci.hz_actual_friendly=}')print(f'{ci.hz_advertised=}')print(f'{ci.l1_data_cache_size=}')print(f'{ci.l1_instruction_cache_size=}')print(f'{ci.l2_cache_associativity=}')print(f'{ci.l2_cache_line_size=}')print(f'{ci.l2_cache_size=}')print(f'{ci.l3_cache_size=}')print(f'{ci.model=}')print(f'{ci.processor_type=}')print(f'{ci.python_hz_advertised_friendlyversion=}')print(f'{ci.python_version=}')print(f'{ci.stepping=}')print(f'{ci.vendor_id_raw=}')Example outputci.is_arm=Falseci.is_x86=Trueci.cores_num=4ci.virtual_cores_num=4ci.l2_cache_size_per_core=262144ci.l2_cache_size_per_virtual_core=262144ci.l3_cache_size_per_core=1572864ci.l3_cache_size_per_virtual_core=1572864ci.arch='X86_64'ci.arch_string_raw='x86_64'ci.bits=64ci.brand_raw='Intel(R) Core(TM) i5-3570 CPU @ 3.40GHz'ci.count=4ci.cpuinfo_version=[9,0,0]ci.cpuinfo_version_string='9.0.0'ci.family=6ci.flags=['aes','apic','arch_capabilities','arch_perfmon','avx','clflush','cmov','constant_tsc','cpuid','cx16','cx8','de','erms','f16c','flush_l1d','fpu','fsgsbase','fxsr','ht','hypervisor','ibpb','ibrs','lahf_lm','lm','mca','mce','md_clear','mmx','msr','mtrr','nopl','nx','osxsave','pae','pat','pcid','pclmulqdq','pdcm','pge','pni','popcnt','pse','pse36','pti','rdrand','rdrnd','rdtscp','rep_good','sep','smep','ss','ssbd','sse','sse2','sse4_1','sse4_2','ssse3','stibp','syscall','tsc','vme','xsave','xsaveopt','xtopology']ci.hardware_raw=''ci.hz_actual=[3403348000,0]ci.hz_actual_friendly='3.4033 GHz'ci.hz_advertised=[3400000000,0]ci.l1_data_cache_size=131072ci.l1_instruction_cache_size=131072ci.l2_cache_associativity=6ci.l2_cache_line_size=256ci.l2_cache_size=1048576ci.l3_cache_size=6291456ci.model=58ci.processor_type=0ci.python_hz_advertised_friendlyversion='3.4000 GHz'ci.python_version='3.8.10.final.0 (64 bit)'ci.stepping=9ci.vendor_id_raw='GenuineIntel'Based on CengalRepresents part of Cengal library:https://pypi.org/project/cengal/https://github.com/FI-Mihej/CengalAn equivalent import:fromcengal.hardware.info.cpuimportcpu_info,CpuInfoCengal library can be installed by:pipinstallcengalProjects using Cengalflet_async- wrapper which makesFletasync and brings booth Cengal.coroutines and asyncio to Flet (Flutter based UI)justpy_containers- wrapper aroundJustPyin order to bring more security and more production-needed features to JustPy (VueJS based UI)Bensbach- decompiler from Unreal Engine 3 bytecode to a Lisp-like script and compiler back to Unreal Engine 3 bytecode. Made for a game modding purposesRealistic-Damage-Model-mod-for-Long-War- Mod for both the original XCOM:EW and the mod Long War. Was made with a Bensbach, which was made with CengalSmartCATaloguer.com- TagDB based catalog of images (tags), music albums (genre tags) and apps (categories)LicenseCopyright © 2012-2023 ButenkoMS. All rights reserved.Licensed under the Apache License, Version 2.0.