A Remedial Control for Short-Circuit Fault in NPC/H-Bridge Inverters without Redundant Component

<jats:p>In this paper, a five-level neutral-point-clamped (NPC) inverter with short-circuit fault-tolerant capability is presented. Based on the proposed approach, in order to ensure service continuity subsequent to a short-circuit fault event in a switch, two steps are carried out. First of all, destructive consequences arising from short-circuit fault in a power switch is prevented. Afterwards, according to the defected component, remedial actions are taken. The proposed strategy does not require any redundant component. The service continuity is acquired by applying a remedial control and modifying switching commands applied to the power switches. Using the proposed approach helps to restore the rated voltage and rated current at the terminal, and there is no limit for modulation index during fault-tolerant operation under remedial control. Furthermore, compared to healthy operation, harmonic content of the terminal voltage and current is not deteriorated during fault-tolerant operation. Moreover, additional components, such as bidirectional switches and contactors, are not employed in this strategy. Only some fast fuses are placed in the converter circuit for protection purposes which do not impose a noticeable cost compared to the bidirectional switches and contactors.</jats:p>

section_content: Multilevel inverters have been extensively employed in industry for decades. Thanks to the significant advantages, such as less total harmonic distortion, less switching losses, limited voltage transients, reduced common-mode voltage, and small size of filter elements, multilevel inverters have become a worthy substitute for two-level conventional ones [1] [2] [3]. Since three-level neutral-point-clamped (NPC) inverters do not include any isolating transformer or flying capacitor, they are widely employed in industry. However, in highvoltage applications, dynamic and static voltage sharing problems would arise across the components in NPC topology [4]. To overcome this constraint, NPC/H-Bridge topology is employed instead of the classical NPC topology. As illustrated in Figure 1a, each phase of a three-phase five-level NPC/H-Bridge inverter comprises a single-phase five-level NPC module fed by isolated DC power supplies. 

Ensuring fault-tolerant operation is of considerable importance in many safety-critical applications, such as ship propulsion, aircrafts, and railroad vehicles [5]. This matter is particularly significant in the applications where a multilevel inverter is employed, because the breakdown possibility is higher as the number of semiconductor switches increases [6]. Furthermore, the semiconductor power switches are so prone to breakdown [7]. Several research works have been conducted on fault-tolerant operation of multilevel inverters. 

The research works presented in [8] [9] [10] [11] deal with fault-tolerant operation for cascaded H-Bridge (CHB) converters. The approaches presented in [12] [13] [14] [15] [16] propose remedial operation for modular multilevel converters (MMC). The research works dealing with fault-tolerant operation of NPC inverters, active neutral-point-clamped (ANPC) inverters, and T-type inverters can be assessed based on several criteria, such as ensuring rated terminal voltage and current during post-fault operation, the number of employed redundant components, harmonic distortion of terminal voltage and current during remedial operation, utilization of external and auxiliary components, and the transition time between healthy and faulttolerant operation. In [17], a fault-tolerant control method for three-level T-type and NPC rectifiers is proposed. In the case of a fault event in an external switch, direct-axis current is injected to the rectifier. In the case of a fault in an internal switch, the converter operates with two-level switching which can cause distortion at the terminal current. The research work presented in [18] solely presents a fault-tolerant approach when a clamping diode of a three-level inverter encounters to an open-circuit fault. Because of the post-fault two-level modulation, the harmonic content of the terminal current is increased. The fault occurrence in a switch is overlooked in this work. In [19], a fault-tolerant operation of a three-level NPC inverter is ensured by using an additional leg. In this work, besides the redundant leg, six contactors are employed to carry out the reconfiguration which leads to a high response time (tens of ms). In the work presented in [1], a fault-tolerant single-phase five-level inverter is proposed which is almost derived from the combination of an NPC and a T-type topology. In this work, a degraded mode and a rated mode solution are proposed. In the rated mode solution, during fault-tolerant operation, the rated voltage is achievable at the expense of using 14 active switches. In [20], a fault-tolerant strategy is proposed for a three-level NPC inverter. During fault-tolerant operation, the rated voltage is not achievable at the terminal and the power rating has to be reduced. The fault-tolerant topology proposed in [21] is evolved from the combination of a three-level NPC inverter and an additional leg with flying capacitor structure. In [22], a fault-tolerant strategy is proposed for a three-level NPC inverter. During fault-tolerant operation, the two-level switching is adopted instead of three-level switching which increases the harmonic content of the terminal voltage. The research work in [23] has been presented with the aim of ensuring fault-tolerant operation for a three-level NPC rectifier. This strategy is similar to that presented in [17] but it is not able to realize fault-tolerant operation in the case of a fault event in an internal switch. In [24], a fault-tolerant topology for a three-level ANPC inverter is proposed. The topology includes a fourth leg which is identical to each one of the main three legs. However, in some fault cases, the two-level switching is adopted which leads to increase the harmonic distortion in the terminal voltage and current. In [25], using a modified carrier based pulse width modulation method, a fault-tolerant strategy is presented for a three-level ANPC inverter. During fault-tolerant operation, the modulation index is limited to 0. 5. The research work presented in [26] ensures fault-tolerant operation of a three-level T-type inverter using a fourth redundant leg. In the proposed method, fuses and bidirectional switches are employed to carry out fault isolation and system reconfiguration, respectively. However, in the case of a fault event in the half-bridge legs or in the neutral point legs, two-level modulation is adopted which causes an increase in the terminal voltage distortion. Furthermore, fault occurrence in a half bridge leg decreases the power delivered during the fault-tolerant mode. In [27] [28] [29], fault-tolerant operation of a three-level T-type inverter is acquired without using any additional component. In the case of a fault event in one of the half bridge legs, the modulation index is limited to 0. 5. When the fault occurs in a neutral point leg, the harmonic content of the terminal voltage is increased. In spite of using a redundant half bridge leg and a redundant neutral point leg for a three-level T-type inverter in [30], total harmonic distortion of the terminal voltage is increased during fault-tolerant operation, which is caused by the two-level voltage modulation. In [31], the authors propose a cascaded H-bridge multicell inverter. Fault tolerance is achieved by using a bypass design. Ensuring fault-tolerant operation is of considerable importance in many safe cal applications, such as ship propulsion, aircrafts, and railroad vehicles [5]. This is particularly significant in the applications where a multilevel inverter is employ cause the breakdown possibility is higher as the number of semiconductor switc creases [6]. Furthermore, the semiconductor power switches are so prone to brea [7]. Several research works have been conducted on fault-tolerant operation of mu inverters. The research works presented in [8] [9] [10] [11] deal with fault-tolerant opera cascaded H-Bridge (CHB) converters. The approaches presented in [12] [13] [14] [15] [16] propos dial operation for modular multilevel converters (MMC). The research works dealin fault-tolerant operation of NPC inverters, active neutral-point-clamped (ANPC) in and T-type inverters can be assessed based on several criteria, such as ensuring ra minal voltage and current during post-fault operation, the number of employed dant components, harmonic distortion of terminal voltage and current during re operation, utilization of external and auxiliary components, and the transition t tween healthy and fault-tolerant operation. In [17], a fault-tolerant control meth This paper presents a short-circuit fault-tolerant topology which provides the rated voltage and current at the terminals of a three-phase five-level NPC inverter during postfault operation. The fault-tolerant topology does not contain any redundant component. Compared with the healthy operation, the harmonic content of the terminal voltage and current is not increased during post-fault operation. Since no bidirectional switch is employed neither in single-phase modules or between the phases, fast transition between healthy operation and post-fault operation is acquired. 

The rest of this paper is organized as follows. The second section presents the operation of the proposed topology under a short-circuit switch fault. In Section 3, the proposed remedial action in the case of short-circuit fault occurrence in a switch is explained. In Section 4, some selected simulation results are provided and discussed. Finally, in Section 5, conclusions are drawn.
section_name: Introduction

section_content: Since no redundant component is connected between the phases of the three-phase inverter illustrated in Figure 1a, a fault-tolerant study can be carried out for a singlephase module including fuses for fault-tolerant purposes, as illustrated in Figure 1b. The switching states associated with the corresponding switching patterns are summarized in Table 1. In a healthy condition, the components conducting the load current corresponding to each switching state for positive and negative load currents are indicated in Table 2. As mentioned earlier, the first step to be taken to realize service continuity is eliminating the consequences arising from a short-circuit fault event in a power switch. Short-circuit fault occurrence in a power switch can lead to a short circuit in a DC link capacitor. In this research work, fast fuses are employed to prevent short-circuit occurrence in DC link capacitors. The cost of the fuses compared to that of the other components of the inverter is negligible. In order to locate the fuses in the converter, two matters should be taken into account. Firstly, in the case of a short-circuit fault event in any switch, the DC link capacitors should be protected for all switching states. Secondly, in the case of blowing a fuse, all voltage levels at the terminal should be achievable during post-fault operation. The fuse cannot be connected in series with S11, S12, S23, or S24 because if the fuse blows, at least the voltage level +Vdc is no longer achievable at the terminal (see Table 2, conducting components corresponding to state 1). In addition, the fuse cannot be connected in series with S21, S21, S13, or S14 because, in these cases, at least the voltage level-Vdc is no longer attainable (see Table 2, conducting components corresponding to state 9). Furthermore, the fuses cannot be connected in series with the DC link capacitors since in the case of a flowing short-circuit current through the fuse and blowing the fuse, the DC link capacitor cannot be served to form the terminal voltage. In this research work, as can be seen in Figure 1b, fuses F1, F2, F3, and F4 are connected in series with clamping diodes DC1, DC2, DC3, and DC4, respectively. In the rest of this section, the role of the fuses to protect the DC link capacitors from a short circuit is investigated and verified. In the next section, the appropriate remedial operation to acquire service continuity is also presented. 

Since the presented topology is symmetric, only the left leg is investigated in this section. First of all, it should be noted that, according to Table 1, in switching states 1, 2, and 4, S11 and S12 are switched on; in switching states 3, 5, and 7, switches S12 and S13 are switched on; and in switching states 6, 8, and 9, switches S13 and S14 are switched on. Hence, from the view point of the left leg, the switching states fall into three sets. In the first one, switch pairs (S11, S12) are switched on; in the second one, switch pairs (S12, S13) are switched on; and in the third one, switch pairs (S13, S14) are switched on. In this paper, the first, second, and third set of the switching states are denoted by P, O, and N, respectively. It should be noted that, when a switch encounters to a short-circuit fault, the fault is not eliminated but also the fault consequence is eliminated. In other words, even if the fuse blows, the defected switch remains on short circuit. 

In the case of a short-circuit fault occurrence in S11, switching states P and N are applicable to the left leg because, in these switching states, none of the DC link capacitors (neither lower one nor upper one) are short-circuited. Furthermore, in accordance with Table 2, the short-circuit fault in S11 does not hinder the current path in switching states P either for positive or for negative currents. Furthermore, for switching states N, in accordance with Table 2, the short-circuit fault in S11 has no impact on the current path and consequently on the terminal voltage. When switching states, O are applied while S11 is on a short circuit, a clamping diode DC2 is forward-biased, and, as shown in Figure 2a, a current looped is formed by S11, S12, S13, DC2, and the upper DC link capacitor. Thus, the upper DC link capacitor is short-circuited once switching states O are applied and, as a consequence, fuse F2 blows. After blowing fuse F2, applying switching states O do not short-circuit any DC link capacitor.
section_name: Operation of the Inverter under Short-Circuit Fault Condition

section_content: -Vdc/2 D14, D13, S23, DC4 S13, S14, DC 9 -Vdc D14, D13, D22, D21 S13, S14, S22

Since the presented topology is symmetric, only the left leg is inve section. First of all, it should be noted that, according to Table 1, in switc and 4, S11 and S12 are switched on; in switching states 3, 5, and 7, switch are switched on; and in switching states 6, 8, and 9, switches S13 and S14 a Hence, from the view point of the left leg, the switching states fall into th first one, switch pairs (S11, S12) are switched on; in the second one, switch are switched on; and in the third one, switch pairs (S13, S14) are switched o the first, second, and third set of the switching states are denoted by P, O tively. It should be noted that, when a switch encounters to a short-circui is not eliminated but also the fault consequence is eliminated. In other wo fuse blows, the defected switch remains on short circuit. 

In the case of a short-circuit fault occurrence in S11, switching stat applicable to the left leg because, in these switching states, none of the DC (neither lower one nor upper one) are short-circuited. Furthermore, in a Table 2, the short-circuit fault in S11 does not hinder the current path in s P either for positive or for negative currents. Furthermore, for switching cordance with Table 2, the short-circuit fault in S11 has no impact on the c consequently on the terminal voltage. When switching states, O are appl on a short circuit, a clamping diode DC2 is forward-biased, and, as shown current looped is formed by S11, S12, S13, DC2, and the upper DC link c the upper DC link capacitor is short-circuited once switching states O are a consequence, fuse F2 blows. After blowing fuse F2, applying switching short-circuit any DC link capacitor. In the case of a short-circuit fault event in S12, applying switching st not short-circuit the DC link capacitors because, when the switching sta applied, two clamping diodes, i. e., DC1 and DC2, are reversed biased. W states N are applied, clamping diode DC1 is forward biased. Hence, the capacitor is short-circuited through DC1, S12, S13, and S14, as illustrat Once the short-circuit current flows, fuse F1 blows. Thus, after blowing fu states N can be applied. 

In the case of a fault occurrence in S13, switching states N and O can out short-circuiting any DC link capacitor because clamping diodes DC1 verse biased. When switching states P are applied, clamping diode DC2 is Consequently, the upper DC link capacitor is short-circuited through S1 DC2 and, as shown in Figure 2c, fuse F2 blows. After blowing fuse F2, sw O, and N can be applied. 

When S14 encounters a short-circuit fault, switching states O short-c DC link capacitor. As seen in Figure 2d, in this case, the short-circuit curren DC1, S12, S13, S14, and the lower DC link capacitor which blows fuse F1 F1, all switching states can be applied. It should be reminded that, after all switching states can be applied without any restriction. 

Likewise, all analysis presented for a short-circuit fault event in S1 S14 can be applied to that in S21, S22, S23, and S24. The presented analy tions are summarized in Table 3. In the case of a short-circuit fault event in S12, applying switching states P and O do not short-circuit the DC link capacitors because, when the switching states P and O are applied, two clamping diodes, i. e., DC1 and DC2, are reversed biased. When switching states N are applied, clamping diode DC1 is forward biased. Hence, the lower DC link capacitor is short-circuited through DC1, S12, S13, and S14, as illustrated in Figure 2b. Once the short-circuit current flows, fuse F1 blows. Thus, after blowing fuse F1, switching states N can be applied. 

In the case of a fault occurrence in S13, switching states N and O can be applied without short-circuiting any DC link capacitor because clamping diodes DC1 and DC2 are reverse biased. When switching states P are applied, clamping diode DC2 is forwardbiased. Consequently, the upper DC link capacitor is short-circuited through S11, S12, S13, and DC2 and, as shown in Figure 2c, fuse F2 blows. After blowing fuse F2, switching states P, O, and N can be applied. 

When S14 encounters a short-circuit fault, switching states O short-circuit the lower DC link capacitor. As seen in Figure 2d, in this case, the short-circuit current flows through DC1, S12, S13, S14, and the lower DC link capacitor which blows fuse F1. After blowing F1, all switching states can be applied. It should be reminded that, after blowing a fuse, all switching states can be applied without any restriction. 

Likewise, all analysis presented for a short-circuit fault event in S11, S12, S13, and S14 can be applied to that in S21, S22, S23, and S24. The presented analysis and explications are summarized in Table 3. The protection of IGBTs by very fast-acting fuses has already been investigated and validated experimentally in several research works. The research works presented in [32] [33] [34] propose a short-circuit protection method of power IGBTs by inserting the fast fuses in various places in a power electronic inverter and validate them experimentally. In [33, 34], the authors present the consequence arising from the added inductance by standard high-speed fuses. In [34], in order to improve the protection procedure and suppress the consequence of fuse rupture, they investigate the IGBT protection by Tpower fuses instead of standard high speed fuses. In the latter case study, it can be observed that the resulted inductance in the short-circuit current path is lower than those resulted in the former case. The authors in [35] determine the fast fuse rated values according to the switching frequency and characteristics of a power IGBT. 

One of the advantages offered by multilevel inverters compared with two-level conventional inverters is the possibility to reduce the switching frequency. Thus, the proposed strategy would be more appropriate for multilevel inverters compared with two level conventional inverters because, as the switching frequency decreases, the practical problem for an IGBT protection decreases.
section_name: 8

section_content: As mentioned earlier, to ensure service continuity in the case of a short-circuit fault event in a power switch, two major steps should be carried out. In the previous section, the first step was elaborated in which the consequences arising from a short-circuit fault event in a power switch is eliminated. In accordance with the studies summarized in Table 3, a short-circuit fault event in each power switch blows a fuse. As a fuse is connected in series with a clamping diode, it can be deduced that blowing a fuse is equivalent to an open-circuit fault occurrence in the clamping diode connected in series with the blown fuse. Thus, the remedial strategy should be presented in the case of an open-circuit fault event in each clamping diode. 

It should be mentioned that, for realization of the proposed strategy, short-circuit fault identification is not required. Corresponding to a short-circuit fault event in an IGBT, a specific fuse blows. After blowing the fuse, the destructive consequence of the short-circuit fault (short-circuiting the DC link capacitors) is prevented. Therefore, after blowing the fuse, all of switching states can be applied without forming any short-circuit current loop. The fuse blows when certain switching states are applied (see Table 3 ). Hence, it can be concluded that blowing a fuse does not require any short-circuit fault identification. 

Blowing the fuse can be treated as an open-circuit fault in the clamping diode connected in series with the melted fuse. Hereafter, the open-clamping diode (or blown fuse) has to be identified in order to apply the relevant remedial control (see Table 4 ). In summary, the short-circuited IGBT is not identified but also the blown fuse (the open-circuited clamping diode) is identified which is prerequisite to applying the relevant remedial control approach. The short-circuited IGBT remains on a short circuit but it does not lead to any restriction or harmful consequence.
section_name: Principle of the Proposed Remedial Strategy

section_content: As mentioned above, blowing fuse F1 or F2 can be considered as an open-circuit fault event in clamping diode DC1 or DC2, respectively. According to Table 3, a short-circuit fault event in S12 or S14 leads to blow fuse F1 (open-circuit fault in DC1) and short-circuit fault occurrence in S11 or S13 results in blowing fuse F2 (an open-circuit fault event in DC2). As can be seen in Table 2, in switching states 3, 5, and 7, clamping diodes DC1 (while the terminal current is positive) and DC2 (while the terminal current is negative) form the current path. Hence, in the case of an open-circuit fault event in DC1 or DC2 (blowing F1 or F2), by applying switching states 3, 5, and 7, the desired terminal voltages are no longer achievable. To solve this matter, these infeasible switching states are substituted with other switching states with which the desired terminal voltages are attainable. According to Table 2, by applying switching states 2 and 3, the same terminal voltage (+Vdc/2) is acquired while, by applying switching state 2, the terminal current flows neither through DC1 nor through DC2 either for positive or negative currents. Thus, infeasible switching state 3 is replaced by switching state 2. Furthermore, applying switching states 4, 5, or 6, results in the same terminal voltage (0 V). Hence, instead of applying switching state 5, switching state 4 or 6 can be applied in which neither DC1 nor DC2 form the terminal current path. It should be noted that both switching states 4 and 6 have the same impact on the DC link capacitors' voltages and, consequently, on the neutral point voltage. According to Table 2, while switching state 4 or 6 is applied, either for positive current or for negative terminal currents, no current is injected to the neutral point. Likewise, it can be concluded that infeasible switching state 7 (corresponding to -Vdc/2 at the terminal) is replaced by switching state 8. The analysis presented in this subsection is summarized in Table 4.
section_name: Remedial Strategy in the Case of Blowing Fuse F1 or Fuse F2

section_content: Similar to the analysis presented in the previous subsection, blowing fuse F3 or F4 can be interpreted as an open-circuit fault occurrence in clamping diode DC3 or DC4, respectively. In accordance with Table 2, while switching states 2, 5, and 8 are applied in healthy condition, clamping diodes DC3 (for positive terminal currents) and DC4 (for negative terminal currents) contribute to form the terminal current path. Hence, in the case of an open-circuit fault event in DC3 (blowing F3) or in DC4 (blowing F4), switching states 2, 5, and 8 are infeasible. 

By applying the similar analysis presented in the previous subsection, it can be deduced that the switching states 2, 5, and 8 should be substituted with switching states 3, 4 or 6, and 7, respectively. The analysis presented in this subsection is also summarized in Table 4.
section_name: Remedial Strategy in the Case of Blowing Fuse F3 or Fuse F4

section_content: The simulation results are presented in two subsections. In the first one, the simulation results regarding a short-circuit fault-tolerant approach applied to switches S11, S12, S13, or S14 (fuse F1 or fuse F2 blows) are provided and discussed. In the second subsection, fault-tolerant operation of the inverter in the case of a short-circuit fault event in switches S21, S22, S23, and S24 (fuse F3 or fuse F4 blows) are represented. 

The simulation parameters associated with their values are provided in Table 5. The inverter feeds a resistive-inductive load. It should be mentioned that the fault-tolerant operation of the inverter begins once the blown fuse (resulting in an open-circuit fault in the clamping diode) is detected. 

In other words, prior to applying remedial control, localization of the open-circuit fault in the clamping diode is necessary. Since this research work only deals with fault-tolerant operation and solely targets the remedial actions to ensure service continuity of the inverter, the fault localization step is not addressed in this paper. Open-circuit fault localization for clamping diodes in an NPC inverter presented in research works [18, 36, 37 ] can be applied. The simulations are carried out in MATLAB/Simulink environment.
section_name: Simulation Results

section_content: As presented in Table 3, short-circuit fault occurrence in switches S11, S12, S13, or S14 leads to blow fuse F1 or F2. In addition, in accordance with the analysis summarized in Table 4, it can be observed that, in the case of blowing F1 or F2, the same remedial control is applied to ensure service continuity of the inverter because the infeasible and substituted switching states corresponding to these two cases are same. It is worth reminding that blowing fuse F1 or F2 are considered as an open-circuit fault event in DC1 or DC2, respectively. 

As can be observed in Table 1, the gate signals corresponding to switches S11, S12, S23, and S24 are complementary to those corresponding to switches S13, S14, S21, and S22, respectively. In this regard, in the simulation results only the gate signals applied to switches S11, S12, S23, and S24 are presented and denoted by G11, G12, G23, and G24, respectively. 

Before presenting the applied remedial control, the operation of inverter under shortcircuit fault occurrence without applying remedial control is represented. For this purpose, and in order to avoid presenting similar and repetitive results, solely the results regarding the inverter operation under a short-circuit fault event in switch S11 are selected and presented in Figure 3. As can be seen in Figure 3, before a short-circuit fault event at instant t f, the inverter operates in healthy operation. During post-fault operation, fuse F2 is blown (equivalent to an open-circuit fault in clamping diode DC2). As mentioned earlier, the fuses connected in series with the clamping diodes protect the DC link capacitors in the case of a short-circuit fault event. Subsequent to blowing a fuse which leads to an open-circuit fault in a clamping diode, the terminal voltage and current of the inverter are distorted compared to the healthy operation. Thus, by applying a remedial control during post-fault operation, the terminal voltage and current obtained during healthy operation would be restored. In order to represent the applied remedial approach, the inverte healthy condition is compared with the post-fault operation of the inv the switching states applied during healthy operation are compared during post-fault operation. Figure 4 represents the simulation resu tolerant operation of the inverter in the case of a short-circuit fault e Before instant ta, the inverter operates in healthy condition. At insta fault occurs in S11. As explained earlier, according to Table 3, in the ca fault event in S11, once one of switching states 3, 5, or 7 is applied, fu alent to an open-circuit fault in DC2). According to Figure 4, at instan (faulty clamping diode) is identified and, subsequent to the fault iden dial control is applied to ensure the service continuity. As seen in Fig tolerant operation, the rated voltage and current are acquired, and t and voltage are not distorted compared to those during healthy opera In order to represent the applied remedial approach, the inverter operation during healthy condition is compared with the post-fault operation of the inverter. In this regard, the switching states applied during healthy operation are compared with those applied during post-fault operation. Figure 4 represents the simulation results regarding faulttolerant operation of the inverter in the case of a short-circuit fault event in switch S11. Before instant t a, the inverter operates in healthy condition. At instant t a, a short-circuit fault occurs in S11. As explained earlier, according to Table 3, in the case of a short-circuit fault event in S11, once one of switching states 3, 5, or 7 is applied, fuse F2 blows (equivalent to an open-circuit fault in DC2). According to Figure 4, at instant t b, the blown fuse (faulty clamping diode) is identified and, subsequent to the fault identification, the remedial control is applied to ensure the service continuity. As seen in Figure 4, during fault-tolerant operation, the rated voltage and current are acquired, and the terminal current and voltage are not distorted compared to those during healthy operation. In order to investigate the applied remedial operation in Figure 4, inter c1 (healthy operation) are compared to intervals a2, b2, and c2 (fault-tolera respectively. During interval a1, gate signals of S12 and S23 (G12 and G23 and gate signals of S11 and S24 (G11 and G24) toggle between '1′ and '0′. 

with Table 1, it can be concluded that, during interval a1, switching states applied to the power switches. As seen in Figure 4, during interval a2, the levels are obtained compared to interval a1 while, during interval a2, gate (G11), S12 (G12), and S23 (G23) are set at '1′ and gate signal of S24 (G24) to '1′ and '0′. Hence, in accordance with Table 1, it can be deduced that only sw 1 and 2 are applied. Thus, by comparing the switching states applied in inte applied during interval a2, it can be observed that, during fault-tolerant op case of a fault in S11 (F2 blows according to Table 4 ), switching state 3 is no l during fault-tolerant operation and this infeasible switching state is replaced state 2 which complies with the analysis presented in Table 4 (the subsectio ing to F2). During interval b1, gate signals of S12 (G12) and S23 (G23) are set signals of S11 (G11) and S24 (G24) toggle between '0′ and '1′. Thus, accord In order to investigate the applied remedial operation in Figure 4, intervals a 1, b 1, and c 1 (healthy operation) are compared to intervals a 2, b 2, and c 2 (fault-tolerant operation), respectively. During interval a 1, gate signals of S12 and S23 (G12 and G23) are set at '1 and gate signals of S11 and S24 (G11 and G24) toggle between '1 and '0. In accordance with Table 1, it can be concluded that, during interval a 1, switching states 1, 2, and 3 are applied to the power switches. As seen in Figure 4, during interval a 2, the same voltage levels are obtained compared to interval a 1 while, during interval a 2, gate signals of S11 (G11), S12 (G12), and S23 (G23) are set at '1 and gate signal of S24 (G24) toggles between '1 and '0. Hence, in accordance with Table 1, it can be deduced that only switching states 1 and 2 are applied. Thus, by comparing the switching states applied in interval a 1 to those applied during interval a 2, it can be observed that, during fault-tolerant operation in the case of a fault in S11 (F2 blows according to Table 4 ), switching state 3 is no longer applied during fault-tolerant operation and this infeasible switching state is replaced by switching state 2 which complies with the analysis presented in Table 4 (the subsection corresponding to F2). During interval b 1, gate signals of S12 (G12) and S23 (G23) are set at '1 and gate signals of S11 (G11) and S24 (G24) toggle between '0 and '1. Thus, according to Table 1, switching states 2, 3, and 5 are applied to the power switches. Over entire interval b 2, signals G11 and G12 are set at '1, G24 is set at '0, and signal G23 toggles between '1 and '0. Referring to Table 1, it can be observed that, during interval b 2, switching states 2 and 4 are applied. Thus, by comparing the switching states applied during intervals b 1 and b 2, it is deduced that the infeasible switching states 3 and 5 are substituted with switching states 2 and 4 which complies with the analysis provided in Table 4 (the subsection corresponding to fuse F2). As mentioned previously, infeasible switching state 5 can be replaced either by switching state 4 or 6 (here, switching state 4 is chosen). Likewise, by observing the switching states applied during intervals c 1 and c 2 in Figure 4, it is deduced that, during interval c 1, switching states 7, 8, and 9 are applied while, during post-fault operation (interval c 2 ), switching states 8 and 9 are applied. Thus, infeasible switching state 7 is substituted with switching state. The similar analysis applied to Figure 4 can also be applied to Figures 5 6 7, which illustrate fault-tolerant operation of the inverter in the case of a short-circuit fault event in switches S12, S13, and S14, respectively. It should be reminded that, according to Table 3, a short-circuit fault event in S12, S13, or S14 blows fuses F1, F2, or F1, respectively. On the other hand, according to Table 4, in the case of a blowing fuse F1 or F2, the same remedial strategy is carried out to ensure service continuity. The presented analysis consisting of the applied switching states during the healthy operation and post-fault operation of the inverter in the case of a short-circuit fault in S11, S12, S13, and S14 are summarized in Table 6. 

Electronics 2021, 10, x FOR PEER REVIEW Table 6. Applied switching states corresponding to each interval in Figures 4 5 6 7.
section_name: Simulation Results Regarding Service Continuity in the Case of Blowing Fuse F1 or Fuse F2

section_content: Applied Switching States

It should be noted that the length of the intervals located between the fault generation instant and the beginning of the remedial control (interval [t a, t b ]), in the results presented in Figures 4 5 6 7, are not equal. As explained previously, these intervals correspond to the open-circuit fault localization time of the clamping diodes which is not targeted in this research work. In the following, this matter is clarified.
section_name: Interval

section_content: By referring to Table 3, it is observed that short-circuit fault occ S23, or S24 blows fuse F3 or F4. Thus, this subsection deals with a faul study of the inverter in the case of a short-circuit fault event in S21, addition, according to the analysis summarized in Table 4, in the case (equivalent to an open-circuit fault event in DC3) or fuse F4 (equivalen fault event in DC4), the same remedial strategy is applied during fault In other words, the same remedial strategy is applied in the case of S22, S23, and S24. In this subsection, the simulation results regarding ation of the inverter in the case of a short-circuit fault in switch S21, depicted in Figures 8 9 10 11, respectively. 

As can be seen in Figures 8 9 10 11, the acquired terminal current and In the case of a short-circuit fault event in S11, fuse F2 blows (resulting in an opencircuit fault in clamping diode DC2). From one hand, according to Figure 4, a short-circuit fault occurs (instant t a ) when the terminal current is positive. On the other hand, clamping diode DC2 conducts only when the terminal current is negative (see Table 2 ). Thus, as long as the terminal current is positive (during interval [t a, t b ]), the clamping diode DC2 does not have any contribution to make the terminal current and voltage. Thus, during this interval, the fault localization cannot be accomplished and, consequently, applying the remedial control does not begin. This interval (localization time) should elapse and it is not avoidable. The similar analysis can be applied to the three other cases.
section_name: Simulation Results Regarding Service Continuity in the Case of Blowin

section_content: By referring to Table 3, it is observed that short-circuit fault occurrence in S21, S22, S23, or S24 blows fuse F3 or F4. Thus, this subsection deals with a fault-tolerant operation study of the inverter in the case of a short-circuit fault event S21, S22, S23, or S24. In addition, according to the analysis summarized in Table 4, in the case of blowing fuse F3 (equivalent to an open-circuit fault event in DC3) or fuse F4 (equivalent to an open-circuit fault event in DC4), the same remedial strategy is applied during fault-tolerant operation. In other words, the same remedial strategy is applied in the case of a fault event in S21, S22, S23, and S24. In this subsection, the simulation results regarding fault-tolerant operation of the inverter in the case of a short-circuit fault in switch S21, S22, S23, or S24 are depicted in As can be seen in Figures 8 9 10 11, the acquired terminal current and voltage waveforms during post-fault operation are similar to those obtained during healthy operation. Similar to the previous subsection, in order to elaborate the employed remedial control, the applied switching states during three intervals a 1, b 1, and c 1 are compared to those applied during three intervals a 2, b 2, and c 2, respectively. To avoid verbosity, the comparison results are provided in Table 7. As can be observed in Table 7, infeasible switching states 2, 5, and 8 are substituted by switching states 3, 4, and 7.
section_name: Simulation Results Regarding Service Continuity in the Case of Blowing Fuse F3 or Fuse F4

section_content: The NPC inverter is constituted of IGBTs SKM50GB12
section_name: Experimental Results

section_content: The NPC inverter is constituted of IGBTs SKM50GB123D of SEMIKRON (SEMIKRON, Nuremberg, Germany), commanded by SKHI22A drivers (SEMIKRON, Nuremberg, Germany). For the experimental setup, the load resistance, the load inductance, the switching frequency, the fundamental frequency, the DC link capacitors, the DC link voltage, and modulation index are set at 27. 7 Ω, 9 mH, 1 kHz, 50 Hz, 2. 2 mF, 50 V, and 0. 8, respectively. The modulation part is implemented on a real-time processor of a MicroLabBox (dSpace ® platform) (SEMIKRON, Nuremberg, Germany), and the fault diagnosis and the fault-tolerant control subsections are implemented on the FPGA chip of the MicroLabBox (Xilinx ® Kintex ® -7 XC7K325T). The clock frequency of the FPGA chip is set at 100 MHz. In the experimental results, the switching pattern is illustrated by four selected IGBTs gate signals. Based on these four IGBTs gate signals, the switching state can be determined according to Table II The proposed short-circuit fault-tolerant strategy does not require any additional component. As mentioned earlier, a short-circuit fault in a switch or in a diode leads to blow in a fuse which is treated as an open-circuit fault in a clamping diode. Solely by modifying the infeasible switching states applied in healthy operation, the fault-tolerant operation is realized. Figure 13 represents the inverter operation in the case of a shortcircuit fault in S21 (blowing fuse F4) without applying fault-tolerant strategy. As can be seen, once the fault occurs (after blowing fuse F4), the two DC link capacitors' voltages start to diverge from their rated values in such a way that one of them attains entire DC link voltage and the other one would be discharged completely. Thus, one of the capacitors would be exposed to overvoltage. Furthermore, after the fault event, the output voltage and current are deteriorated in terms of distortion. The outcomes of the applied faulttolerant strategy (in the case of blowing F4) are illustrated in Figures 14 and 15. As shown in Figure 14, by applying the fault-tolerant strategy, the output voltage and current obtained during fault-tolerant operation are identical to those obtained during healthy operation. The proposed short-circuit fault-tolerant strategy does not require any additional component. As mentioned earlier, a short-circuit fault in a switch or in a diode leads to blow in a fuse which is treated as an open-circuit fault in a clamping diode. Solely by modifying the infeasible switching states applied in healthy operation, the fault-tolerant operation is realized. Figure 13 represents the inverter operation in the case of a shortcircuit fault in S21 (blowing fuse F4) without applying fault-tolerant strategy. As can be seen, once the fault occurs (after blowing fuse F4), the two DC link capacitors' voltages start to diverge from their rated values in such a way that one of them attains entire DC link voltage and the other one would be discharged completely. Thus, one of the capacitors would be exposed to overvoltage. Furthermore, after the fault event, the output voltage and current are deteriorated in terms of distortion. The outcomes of the applied fault-tolerant strategy (in the case of blowing F4) are illustrated in Figures 14 and 15. As shown in Figure 14, by applying the fault-tolerant strategy, the output voltage and current obtained during fault-tolerant operation are identical to those obtained during healthy operation. The proposed short-circuit fault-tolerant strategy does not require any additiona component. As mentioned earlier, a short-circuit fault in a switch or in a diode leads to blow in a fuse which is treated as an open-circuit fault in a clamping diode. Solely by modifying the infeasible switching states applied in healthy operation, the fault-toleran operation is realized. Figure 13 represents the inverter operation in the case of a short circuit fault in S21 (blowing fuse F4) without applying fault-tolerant strategy. As can be seen, once the fault occurs (after blowing fuse F4), the two DC link capacitors' voltages start to diverge from their rated values in such a way that one of them attains entire DC link voltage and the other one would be discharged completely. Thus, one of the capaci tors would be exposed to overvoltage. Furthermore, after the fault event, the output volt age and current are deteriorated in terms of distortion. The outcomes of the applied fault tolerant strategy (in the case of blowing F4) are illustrated in Figures 14 and 15. As shown in Figure 14, by applying the fault-tolerant strategy, the output voltage and current ob tained during fault-tolerant operation are identical to those obtained during healthy op eration. Moreover, despite low-frequency oscillation with negligible ripple amplitude in th DC link capacitors' voltages, the middle-point voltage of a DC bus is stabilized. In Figur 15, by comparing the healthy operation with the fault-tolerant operation of the inverte (in the case of blowing F4), the modifications of the switching states are represented. I this regard, the switching states corresponding to the same voltage levels (healthy opera tion and fault-tolerant operation) obtained at the output are compared. It should be re minded that blowing fuse F4 can be treated as an open-circuit fault event in DC4. In Figur 15, four gate signals comprising G11 (gate signal of S11), G12 (gate signal of S12), G2 (gate signal of S23), and G24 (gate signal of S24) are selected to represent the applie switching states. Gate signals applied to S13, S14, S21, and S22 are complementary to thos corresponding to S11, S12, S23, and S24, respectively (see Table 1 ). Thus, from the fou mentioned gate signals, the corresponding switching state is determined. In interval a1 the voltage levels made at the output in healthy mode are +Vdc and +Vdc/2. According t the gate signals and Table 1, switching states 1, 2, and 3 are applied in this interval. I interval a2, the same output voltage levels are obtained compared with interval a1 but th switching state 2 is substituted with switching state 3. Indeed, over entire interval a2, G12 G23, and G24 are set at '1′ and solely G11 is toggled between '0′ and '1′ which complie with Table 7, according to the switching patterns provided in Table 1 for switching state 1, 2, and 3. In interval b1, the output voltage levels -Vdc and -Vdc/2 are achieved. Base on the represented gate signals in interval b1 and Table 1, switching states 7, 8, and 9 ar applied in this interval. By performing a detailed comparison between the gate signal applied in interval b2 (fault-tolerant operation) with those applied in interval b1, one ca deduce that switching state 8 is replaced by switching state 7 (G11, G23, and G24 are se at '0′ and G12 is toggled between '0′ and '1′) which conforms to the data provided in Tabl 7. Likewise, by comparison of interval c1 with interval c2, it is deduced that, during fault tolerant operation, switching states 2 and 5 are substituted with switching states 3 and 4 respectively.
section_name: Experimental Results

section_content: In this paper, a short-circuit fault-tolerant five-level NPC/H-Bridge inverter associ ated with the remedial strategy is presented. The proposed fault-tolerant strategy consist of two major parts. In the first part, by connecting the fuses in series with the clamping diodes, two paramount purposes are achieved. Firstly, the DC link capacitors are pro tected. Secondly, in the case of blowing a fuse, all voltage levels are still achievable at th terminal by applying remedial control. In the second part, by applying the proposed re medial control, the rated terminal voltage and current are obtained during fault-toleran Moreover, despite low-frequency oscillation with negligible ripple amplitude in the DC link capacitors' voltages, the middle-point voltage of a DC bus is stabilized. In Figure 15, by comparing the healthy operation with the fault-tolerant operation of the inverter (in the case of blowing F4), the modifications of the switching states are represented. In this regard, the switching states corresponding to the same voltage levels (healthy operation and fault-tolerant operation) obtained at the output are compared. It should be reminded that blowing fuse F4 can be treated as an open-circuit fault event in DC4. In Figure 15, four gate signals comprising G11 (gate signal of S11), G12 (gate signal of S12), G23 (gate signal of S23), and G24 (gate signal of S24) are selected to represent the applied switching states. Gate signals applied to S13, S14, S21, and S22 are complementary to those corresponding to S11, S12, S23, and S24, respectively (see Table 1 ). Thus, from the four mentioned gate signals, the corresponding switching state is determined. In interval a1, the voltage levels made at the output in healthy mode are +Vdc and +Vdc/2. According to the gate signals and Table 1, switching states 1, 2, and 3 are applied in this interval. In interval a2, the same output voltage levels are obtained compared with interval a1 but the switching state 2 is substituted with switching state 3. Indeed, over entire interval a2, G12, G23, and G24 are set at '1 and solely G11 is toggled between '0 and '1 which complies with Table 7, according to the switching patterns provided in Table 1 for switching states 1, 2, and 3. In interval b1, the output voltage levels -Vdc and -Vdc/2 are achieved. Based on the represented gate signals in interval b1 and Table 1, switching states 7, 8, and 9 are applied in this interval. By performing a detailed comparison between the gate signals applied in interval b2 (fault-tolerant operation) with those applied in interval b1, one can deduce that switching state 8 is replaced by switching state 7 (G11, G23, and G24 are set at '0 and G12 is toggled between '0 and '1 ) which conforms to the data provided in Table 7. Likewise, by comparison of interval c1 with interval c2, it is deduced that, during fault-tolerant operation, switching states 2 and 5 are substituted with switching states 3 and 4, respectively.
section_name: Conclusions

section_content: In this paper, a short-circuit fault-tolerant five-level NPC/H-Bridge inverter associated with the remedial strategy is presented. The proposed fault-tolerant strategy consists of two major parts. In the first part, by connecting the fuses in series with the clamping diodes, two paramount purposes are achieved. Firstly, the DC link capacitors are protected. Secondly, in the case of blowing a fuse, all voltage levels are still achievable at the terminal by applying remedial control. In the second part, by applying the proposed remedial control, the rated terminal voltage and current are obtained during fault-tolerant operation. Furthermore, the harmonic content of the terminal voltage and current is not deteriorated compared to the healthy operation. The remedial control is realized by modifying the switching states which does not require any redundant component. Only four fast fuses are connected in series with the clamping diodes whose cost, compared with the other components of the inverter, is negligible. The proposed fault-tolerant strategy has been solely examined and experimentally validated for a NPC/H-bridge structure. However, the general concept of the proposed method could be developed for the other structures, such as T-type, A-NPC, and flying capacitor.
section_name: Conclusions

section_content: Funding: This research work is the result of the collaboration between University of Lorraine (France) and Iran University of Science and Technology (IUST) started in October 2017. It has been partially financially supported by the Scientific and Technologique Cooperation Service of French Embassy in Tehran that we would like to thank.

section_name: Conflicts of Interest:

section_content: Author Contributions: Investigation: S. A., P. P. and S. S. ; Methodology: S. A., P. P. and S. S. ; Supervision: P. P., S. S. and D. A. K. ; Writing-original draft: S. A. ; Writing-review & editing: P. P., D. A. K. and S. S. All authors have read and agreed to the published version of the manuscript.

section_content: The authors declare no conflict of interest.
section_name: Conflicts of Interest: