Inductance Model of a Backside Integrated Power Inductor in 2.5D/3D Integration

<jats:p>Inductor integration is of vital importance for miniaturization of power supply on chips. In this paper, a backside integrated power inductor is presented. The inductor is placed at the backside of a silicon interposer and connected to the front side metal layers by through-silicon vias (TSVs) for area saving and simple fabrication. An inductance model is proposed to effectively capture the total inductance of the power inductor by an analytical method. The results obtained from the analytical model and finite element method exhibit good agreement with various design parameters and the error between the proposed model and measurement remains less than 7.91%, which indicates that the proposed model can predict the inductance suitably.</jats:p>

section_content: An inductor is a fundamental component for electronic devices, which is used for energy storage and filtering, but it dominates in size and loss. To achieve its miniaturization and aid lowering the cost of the power supply on chip, monolithic integration of power inductors is essential [1] [2] [3] [4]. Lots of design methodologies and fabrication technologies have been proposed for potential monolithic integration. 

The increase in switching frequencies of power circuits up to megahertz can significantly reduce the inductor's size [5, 6]. A tiny 0. 47 µH inductor has been used in a commercial 8 MHz PWM synchronous Buck regulator [5]. A 250 MHz buck regulator has been implemented with a 12 nH wire-bond power inductor in [6]. However, such a high frequency will cause high power switching and result in poor efficiency (e. g., 71% [6] ). Furthermore, the power inductor with low inductance easily introduces a high ripple current. Various magnetic core materials have been adopted to enhance the inductance density for monolithic integration of power inductors [7] [8] [9]. A 3D in-silicon magnetic core toroidal inductor is presented in [7], in which the magnetic powder-based core is embedded into an air-core inductor using a casting method. A 3D solenoid inductor that is embedded in the substrate and integrated an iron core is reported in [8]. However, the introduction of magnetic material not only causes a core saturation issue but also increases the design and fabrication complexity. 

In this paper, a fully integrated air-core power inductor is proposed, which is developed for a high-density silicon-interposer based on 2. 5D and 3D integrated circuits, and a compact analytical model has been derived to capture the total inductance of the proposed inductor, where the screw pitch and cross-sectional sharp are considered. Comparted to traditional circular coil method [10, 11] and the model developed for coils with a circular section-area [12], the proposed model can offer a better Appl. Sci. 2020, 10, 8275; doi:10. 3390/app10228275 www. mdpi. com/journal/applsci Appl. Sci. 2020, 10, 8275 2 of 9 accuracy and is more suitable for the inductance prediction of power inductance fabricated with 2D planar technology.
section_name: Introduction

section_content: Figure 1a shows the cross-section schematic of a silicon-interposer-based 3D IC package, in which the interposer acts as bridges between the active chips and printed circuit board package [13, 14]. In addition to the interconnection, the interposer provides the functionalities with passive components integration. Various integrated passive devices, such as TSV inductors, TSV capacitors and TSV filters, have been presented [15] [16] [17]. However, these studies focus on the utilization of tiny TSVs. The TSV-based solenoid inductor has a low inductance and is not suitable for power device applications. In this design, a fully integrated power inductor is proposed, as shown in Figure 1. The proposed inductor is designed to be placed at the backside of the interposer for efficiently utilizing the silicon area and can be connected to the front side power circuits through TSVs. A thin oxide dielectric is inserted between the inductor and silicon substrate to obtain a high-quality factor. 

Appl. Sci. 2020, 10, x FOR PEER REVIEW 2 of 8 and the model developed for coils with a circular section-area [12], the proposed model can offer a better accuracy and is more suitable for the inductance prediction of power inductance fabricated with 2D planar technology.
section_name: Inductance Model Description

section_content: Figure 1a shows the cross-section schematic of a silicon-interposer-based 3D IC package, in which the interposer acts as bridges between the active chips and printed circuit board package [13, 14]. In addition to the interconnection, the interposer provides the functionalities with passive components integration. Various integrated passive devices, such as TSV inductors, TSV capacitors and TSV filters, have been presented [15] [16] [17]. However, these studies focus on the utilization of tiny TSVs. The TSV-based solenoid inductor has a low inductance and is not suitable for power device applications. In this design, a fully integrated power inductor is proposed, as shown in Figure 1. The proposed inductor is designed to be placed at the backside of the interposer for efficiently utilizing the silicon area and can be connected to the front side power circuits through TSVs. A thin oxide dielectric is inserted between the inductor and silicon substrate to obtain a high-quality factor. Figure 2 shows the major fabrication steps of the proposed power inductors. Firstly, the via structure is formed at the front side of the interposer by deep reactive ion etching (Figure 2a ). The etched via is then processed with an oxide dielectric, a Ta barrier and a Cu seed layer, followed by the acid Cu electroplating (Figure 2b ). The Cu damascene technique [18] is adopted to fabricate the redistribution layers (RDLs) and the vias connecting the TSVs to the RDLs (Figure 2c ). The topside of the interposer wafer is temporarily bonded to a carrier by adhesive and a back grinding is carried out to a few microns to the TSVs (Figure 2d ). The proposed inductor is implemented by the RDLs at the backside with the Cu damascene method and the vias connecting the TSVs and the inductor are completed (Figure 2e ). Finally, one de-bonds the carrier wafer and assembles the TSV module on the package substrate (Figure 2f ). 

With the help of the finite-element method simulation with HFSS software, the electrical performance of the proposed backside integrated inductor with a size of 1 mm 2 is investigated. Table 1 provides a performance comparison for the proposed backside integrated inductor with other stateof-the-art works. Where L, Q, f and RDC are the inductor inductance, qualify factor, switching frequency and dc resistance, respectively; η is the inductor efficiency, which is estimated by the inductor parameters and the equation in [19, 20] for power efficiency. Since the oxide dielectric provides a good isolation between the inductor and the silicon substrate, it is observed that the proposed inductor achieves a higher qualify factor, leading to a peak inductor efficiency of 87. 3% for a typical voltage conversion ratio of 1. 8 V:0. 9 V and load current of 100 mA. On the contrary, substrate loss and eddy current loss significantly decrease the quality and efficiency of the silicon-core inductors and magnetic-core inductors. Furthermore, in comparison to the toroidal inductor, the proposed embedded inductor is more compatible with the standard CMOS process. Figure 2 shows the major fabrication steps of the proposed power inductors. Firstly, the via structure is formed at the front side of the interposer by deep reactive ion etching (Figure 2a ). The etched via is then processed with an oxide dielectric, a Ta barrier and a Cu seed layer, followed by the acid Cu electroplating (Figure 2b ). The Cu damascene technique [18] is adopted to fabricate the redistribution layers (RDLs) and the vias connecting the TSVs to the RDLs (Figure 2c ). The topside of the interposer wafer is temporarily bonded to a carrier by adhesive and a back grinding is carried out to a few microns to the TSVs (Figure 2d ). The proposed inductor is implemented by the RDLs at the backside with the Cu damascene method and the vias connecting the TSVs and the inductor are completed (Figure 2e ). Finally, one de-bonds the carrier wafer and assembles the TSV module on the package substrate (Figure 2f ). 

With the help of the finite-element method simulation with HFSS software, the electrical performance of the proposed backside integrated inductor with a size of 1 mm 2 is investigated. Table 1 provides a performance comparison for the proposed backside integrated inductor with other state-of-the-art works. Where L, Q, f and R DC are the inductor inductance, qualify factor, switching frequency and dc resistance, respectively; η is the inductor efficiency, which is estimated by the inductor parameters and the equation in [19, 20] for power efficiency. Since the oxide dielectric provides a good isolation between the inductor and the silicon substrate, it is observed that the proposed inductor achieves a higher qualify factor, leading to a peak inductor efficiency of 87. 3% for a typical voltage conversion ratio of 1. 8 V:0. 9 V and load current of 100 mA. On the contrary, substrate loss and eddy current loss significantly decrease the quality and efficiency of the silicon-core inductors and magnetic-core inductors. Furthermore, in comparison to the toroidal inductor, the proposed embedded inductor is more compatible with the standard CMOS process. Based on the above structure, the resistance-inductance-capacitance (RLC) model of the backside integrated inductor can be established. Considering that the inductance is one of the critical parameters for inductors in power management applications, this work focuses on the modeling and analysis of the inductance of the proposed inductor. For the basis analysis, it is assumed that the track width is w, the track spacing is s and the track thickness is t. The linked flux of the inductor determined its inductance. For a one-turn inductor, the overall inductance of the inductor is equal to its self-inductance. For multi-turn inductors, there is mutual coupling between each turn, and then the magnetic field strength through the inductor and the linked flux significantly increases with the number of turns, as shown in Figure 3. Therefore, the overall inductance of the inductor is the sum of the self-inductance and increased mutual inductance between each turn [22]. For the proposed Archimedean spiral coil with a rectangular cross section area and n concentric turns, the total inductance LT can be written as the sum over the self-inductance LS and the mutual inductance LM of all turns,

where Mij represent the mutual inductance between the ith turn coil and jth turn coil. The overall selfinductance LS can be further approximated as a function of coil geometry [23], Based on the above structure, the resistance-inductance-capacitance (RLC) model of the backside integrated inductor can be established. Considering that the inductance is one of the critical parameters for inductors in power management applications, this work focuses on the modeling and analysis of the inductance of the proposed inductor. For the basis analysis, it is assumed that the track width is w, the track spacing is s and the track thickness is t. The linked flux of the inductor determined its inductance. For a one-turn inductor, the overall inductance of the inductor is equal to its self-inductance. For multi-turn inductors, there is mutual coupling between each turn, and then the magnetic field strength through the inductor and the linked flux significantly increases with the number of turns, as shown in Figure 3. Therefore, the overall inductance of the inductor is the sum of the self-inductance and increased mutual inductance between each turn [22]. For the proposed Archimedean spiral coil with a rectangular cross section area and n concentric turns, the total inductance L T can be written as the sum over the self-inductance L S and the mutual inductance L M of all turns,

where M ij represent the mutual inductance between the ith turn coil and jth turn coil. The overall self-inductance L S can be further approximated as a function of coil geometry [23],

where l eng is the total length of the n-turn coil, and µ = 4π × 10 -7 H/m is the permittivity of the surrounding medium. For an Archimedean spiral coil with an inner radius R 0 and screw pitch p (p = w + s), l eng can be calculated by

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where leng is the total length of the n-turn coil, and μ = 4π × 10 -7 H/m is the permittivity of the surrounding medium. For an Archimedean spiral coil with an inner radius R0 and screw pitch p (p = w + s), leng can be calculated by The mutual inductance Mij can be calculated using the classical magnetic vector potential approach as [22, [24] [25] [26]

For an Archimedean spiral coil, the tangent vector of point P (Ricosθ1, Risinθ1, 0) on the ith coil and point Q (Rjcosθ2, Rjsinθ2, 0) on the jth coil can be derived as

and then

The distance between two points P and Q can be expressed as ( ) ( )

cos -cos sin -sin

Substituting Equation ( 5 )-Equation ( 7 ) into Equation ( 4 ), Mij can be obtained as

) The mutual inductance M ij can be calculated using the classical magnetic vector potential approach as [22,24-26]

For an Archimedean spiral coil, the tangent vector of point P (R i cosθ 1, R i sinθ 1, 0) on the ith coil and point Q (R j cosθ 2, R j sinθ 2, 0) on the jth coil can be derived as

The distance between two points P and Q can be expressed as

Substituting Equation ( 5 )-Equation ( 7 ) into Equation ( 4 ), M ij can be obtained as

dθ 1 dθ 2 (8) Appl. Sci. 2020, 10, 8275 5 of 9

Substituting Equations ( 3 ) and ( 8 ) into Equation ( 1 ), the total inductance of the proposed Archimedean coil can be calculated.
section_name: Inductance Model Description

section_content: In this section, the inductances obtained from the proposed model, the traditional circular coil method (CCM), quasi-static electromagnetic simulation with Q3D, are compared [26]. Q3D is a fast-quasi-static electromagnetic field simulator and is good at RLCG parameter extraction. For the proposed power inductor with the inductance of ~1 µH, its switching frequency would not exceed 100 MHz. Therefore, Q3D can provide an accurate inductance extraction for the proposed power inductor. In the simulation environment, the two terminals of the inductor are defined as a source and sink, respectively, and the AC RL solver are adopted for inductance extraction. In the circular coil method [10, 11], each loop is approximated as a circle and the radius of the ith turn is treated as R 0 + (i-1)p. The base parameters are w = 40 µm, t = 20 µm, s = 20 µm, R 0 = 20 µm and n = 26. As shown in Figure 4, the inductances with the proposed model agree well with the results of 3D simulators over various design parameters: the error with respect to the EM results is less than 9. 5%, while the error of the traditional circular coil method is 40. 2%. The comparison indicates that the proposed model can be used for inductance extraction of the fully integrated power inductor. 

Substituting Equations ( 3 ) and ( 8 ) into Equation (1), the total inductance of the proposed Archimedean coil can be calculated.
section_name: Validation and Discussion

section_content: In this section, the inductances obtained from the proposed model, the traditional circular coil method (CCM), quasi-static electromagnetic simulation with Q3D, are compared [26]. Q3D is a fastquasi-static electromagnetic field simulator and is good at RLCG parameter extraction. For the proposed power inductor with the inductance of ~1 μH, its switching frequency would not exceed 100 MHz. Therefore, Q3D can provide an accurate inductance extraction for the proposed power inductor. In the simulation environment, the two terminals of the inductor are defined as a source and sink, respectively, and the AC RL solver are adopted for inductance extraction. In the circular coil method [10, 11], each loop is approximated as a circle and the radius of the ith turn is treated as R0 + (i-1)p. The base parameters are w = 40 μm, t = 20 μm, s = 20 μm, R0 = 20 μm and n = 26. As shown in Figure 4, the inductances with the proposed model agree well with the results of 3D simulators over various design parameters: the error with respect to the EM results is less than 9. 5%, while the error of the traditional circular coil method is 40. 2%. The comparison indicates that the proposed model can be used for inductance extraction of the fully integrated power inductor. 

Furthermore, the results in Figure 4a,b demonstrate that LT increases with the track width w and track spacing s, due to the increased partial self-inductance and mutual inductance according to Equations ( 2 ) and ( 8 ). Since the variation in partial self-inductance and mutual inductance with track thickness t is little, it can be seen in Figure 4c that the impact of the parameter on LT can be negligible. Moreover, the results in Figure 4d show the overall inductance would increase with the inner radius of the inductor. Furthermore, the results in Figure 4a,b demonstrate that L T increases with the track width w and track spacing s, due to the increased partial self-inductance and mutual inductance according to Equations ( 2 ) and (8). Since the variation in partial self-inductance and mutual inductance with track thickness t is little, it can be seen in Figure 4c that the impact of the parameter on L T can be negligible. Moreover, the results in Figure 4d show the overall inductance would increase with the inner radius of the inductor. 

Table 2 investigates the computational efficiency of the model by comparing the simulation time of the proposed analytical model and 3D EM simulator using the parameters listed. The simulation was performed on an Intel i5 core with a processor speed of 3. 0 GHz and 8 GB of RAM. It was found that lots of computational time can be saved using the proposed model. To verify the accuracy of the analytical expressions, the proposed model was applied to the fabricated power inductors. Taking into account the additional process steps for the 3D integration and the weak impact of the interposer materials on the inductor's performance, the proposed power inductor was fabricated with 2-layer Print Circuit Board (PCB) technology. In the emulated 3D integration environment shown in Figure 5a, the inductor is realized on the backside planar track. The vias in the PCB technology imitate the TSVs to connect the inductor to the frontside power circuits. Table 3 compares the inductances obtained from this model, the circular coil method (CCM) [10, 11] and electrical measurement with a Hioko IM3570 Impedance Analyzer. By connecting the two terminals of the inductor to the two probes of the impedance analyzer, capable of measurement frequencies of 4 Hz to 5 MHz, the inductance at 1 MHz can be captured. It is observed that the proposed model shows a higher accuracy in comparison to CCM. The maximum error and average error of the proposed model are 7. 91% and 3. 72%, respectively, which indicates the feasibility of the proposed model for inductance prediction. 

Appl. Sci. 2020, 10, x FOR PEER REVIEW 6 of 8

Table 2 investigates the computational efficiency of the model by comparing the simulation time of the proposed analytical model and 3D EM simulator using the parameters listed. The simulation was performed on an Intel i5 core with a processor speed of 3. 0 GHz and 8 GB of RAM. It was found that lots of computational time can be saved using the proposed model. To verify the accuracy of the analytical expressions, the proposed model was applied to the fabricated power inductors. Taking into account the additional process steps for the 3D integration and the weak impact of the interposer materials on the inductor's performance, the proposed power inductor was fabricated with 2-layer Print Circuit Board (PCB) technology. In the emulated 3D integration environment shown in Figure 5a, the inductor is realized on the backside planar track. The vias in the PCB technology imitate the TSVs to connect the inductor to the frontside power circuits. Table 3 compares the inductances obtained from this model, the circular coil method (CCM) [10,11] and electrical measurement with a Hioko IM3570 Impedance Analyzer. By connecting the two terminals of the inductor to the two probes of the impedance analyzer, capable of measurement frequencies of 4 Hz to 5 MHz, the inductance at 1 MHz can be captured. It is observed that the proposed model shows a higher accuracy in comparison to CCM. The maximum error and average error of the proposed model are 7. 91% and 3. 72%, respectively, which indicates the feasibility of the proposed model for inductance prediction.
section_name: Validation and Discussion

section_content: In this paper, a power inductor integration technology for 2. 5D/3D integrated power management applications is presented and experimentally demonstrated. The inductor can be integrated at the backside of the silicon interposer and interconnects with the frontside power circuits TSVs. A compact and accurate inductance model is developed to capture the overall inductance of the proposed inductor. A comparison with 3D EM results shows that the proposed analytical model has a good prediction capability and a high computational efficiency. Furthermore, the model results show that the increase in track width, track spacing and inner radius of the inductor would increase the overall inductance, while the variation in the inductance with track thickness is less. Finally, the inductance from the proposed model and the measurements were compared, and an error of less than 7. 91% was obtained.
section_name: Conclusions

section_content: Funding: This work was supported by the National Natural Science Foundation of China under Grants 61771268, U1709218 and the K. C. Wong Magna Fund in Ningbo University.

section_name: Conflicts of Interest:

section_content: Author Contributions: Conceptualization, K. Q. ; methodology, K. Q. ; validation, K. Q and L. Q. ; formal analysis, K. Q and L. Q. ; investigation, K. Q. ; resources, K. Q. ; data curation, K. Q. ; writing-original draft preparation, K. Q. ; writing-review and editing, K. Q and L. Q. ; supervision, L. Q. ; project administration, L. Q. ; funding acquisition, L. Q. All authors have read and agreed to the published version of the manuscript.

section_content: The authors declare no conflict of interest.
section_name: Conflicts of Interest: