How to Reduce Parasitic Capacitance in PCB Layout | Sierra Circuits
Channel: Sierra Circuits
Date: 2021-07-12

PCB traces, along with dielectric material, form a capacitor, resulting in an unwanted parasitic capacitance or stray capacitance effect. This effect is prominent in high-frequency boards.

Parasitic capacitance can exist between conductors on PCBs, bare boards PCBAs, assembled boards, and within component packages, especially surface mount devices.

The parasitic capacitance is calculated as C=q/v. Where C is the capacitance in farads, v is the voltage in volts, and q is the charge in coulombs.

Parasitic capacitance is caused by parasitic elements such as inductors formed by package leads, long traces, pad to ground, pad to power plane, and pad to trace capacitors, including vias etc. These elements are responsible for parasitic capacitance.

To reduce parasitic capacitance in PCB layout, avoid parallel routing of traces, remove power planes from the vicinity of conductor, and use faraday shield between traces.

Other ways to reduce parasitic capacitance are to minimize the number of vias, increase the space between traces using 2W or 3W rule, use low permittivity dielectric material, and choose right layer thickness are also helpful.

Lastly, careful separation of components and wires, guard rings, power and ground planes, shielding between input and output, and properly terminated transmission line are essential for parasitic capacitance reduction. 

Unfortunately, it is not possible to completely eliminate parasitic elements. Accurate design and manufacturing decisions can control these parasitics.

Learn more on our blog:
https://www.protoexpress.com/blog/how-to-reduce-parasitic-capacitance-pcb-layout/?utm_source=youtube&utm_medium=social&utm_campaign=blog%2B2021

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