I2C - Bus Master - Step 3
Channel: BOPV
Date: 2013-03-14

Step 3 of designing an I2C Bus Master in Verilog.  This step looks at configuring a clock divider to handle the high-speed (100MHz) clock on the XUPV5 board and stepping it down to 100KHz.  It also looks at how to handle timing in the ISIM simulator.