ECE 111 End Semester Project Lab Video
Channel: Ayush Kumar Aggarawal
Date: 2021-05-21

My Credentials:
Name: Ayush Kumar
Roll No. 2020290
Branch: CSAM
Date of Document: 5 April 2021
Group 7

Problem Statement: Design a synchronous decade UP counter. Realize D-flip flops' inputs with 4-input multiplexers and using NOR gate in its inputs of MUX using Q1Q0 as the select inputs. (Use Hex- display for output).

Components used: 4 (4:1 MUX), 4 (2-input NOR Gate), 4 (D Flip-Flop), 5 constant value inputs, Clock Pulse Input, Hex Display, 1 Splitter of 4 bit divided into 1 bit each, 1 Splitter of 2 bit divided into 1 bit each and Wires.

0:00 Intro
0:19 Problem Statement
0:40 Truth Table, Kmap
1:19 Simplification, Inputs to the MUX
1:51 Circuit Working and breifing
2:32 Observation and Application