The Verilog to Verilog Decompiler - Katie Liszewski
Channel: 0xdade
Date: 2020-03-12

Methods have been developed for conducting integrated circuit decomposition on fabricated chips to extract the as-fabricated design files such as the GDSII layout or gate-level netlist. While mature netlist equivalency checking tools are included with any design flow, there is a lack of tools for performing deeper analyses on the extracted designs for the purposes of hardware assurance or design recovery from obsolete parts. To this end, there is a need for a tool to extract functionality from netlists at a higher abstraction level to reconstruct behavioral Register Transfer Level (RTL) code.

Software decompilation is a well-established technique that has been used since the 1960s to recover lost source code, verify code against design changes produced by the compiler, and support detection of malicious code. In seeking to recover RTL, these 80 years of expertise in reconstructing functionality are invaluable. We introduce the terminology of “hardware decompilation” and explore where software techniques are relevant, how existing netlist structure recovery techniques fit into the decompilation pipeline, and present new techniques that are unique to hardware decompilation.

Katie Liszewski has a mathematics PhD and, since graduating, has specialized in solving computationally hard firmware and hardware security problems. At Battelle she leads efforts in emerging nondestructive counterfeit detection methods and process automation for hardware security. She has authored several papers in scalable second order effects based counterfeit detection.

This video is mirrored from the original upload to Internet Archive: https://archive.org/details/ShmooCon_2020