Designing an Efficient MIPS III Load Store Unit
Channel: RTL Engineering
Date: 2018-10-02

A short video detailing an implementations for an FPGA based MIPS III load-store unit to be used in a VR4300 CPU implementation.

*Correction. The NEC version of the VR4300 claims an additional 1 cycle delay for unaligned loads, and that the main shifter is used for all store instructions.
The SGI Documentation on the R4300i claims the same, making no statement of an additional 1 cycle delay.
The internal Nintendo SGI document for the R4300i makes no claim either way, and neglects to mention the Left-Right instructions, so it's possible that the Nintendo version of the R4300 did not implement them... 
In the end, combining everything into a single unit is simpler, at the cost of some additional resources.

I am not affiliated with any of the companies mentioned in the video. This video is intended for educational purposes.