FPGA InsideOut Session1 | CRC calculation | parallel CRC circuit
Channel: EtherBladeNet
Date: 2022-01-18

Visualisation of FPGA internal logic of the following hardware design concepts (CRC - cyclic redundancy check, Parallel CRC, LFSR, sequential and combinational logic, reset, clock).


If you want to replicate this exercise yourself on FPGA, you can find Verilog source code on:
https://github.com/FPGA-InsideOut/FPGA_InsideOut_Session1

#FPGA #ErrorDetection #CRC