Developing and testing TensorFlow Lite Micro edge AI algorithms on RISC-V and FPGAs
Channel: British Computer Society Open Source Specialists
Date: 2021-02-12

Presented by Michael Gielda, Antmicro

With the increasing demand for small and energy-efficient devices with AI capabilities, new tools and workflows are needed to develop so-called TinyML applications. In a project with Google’s TensorFlow Lite MCU team, Antmicro has been helping improve the CI infrastructure for one of the world’s most famous ML frameworks. TF Lite Micro users can now run their machine learning framework on virtual hardware for demonstration, CI and testing. Renode allows ML developers to repeatedly and reliably test various demos, models and scenarios on a variety of hardware, including a wide range of RISC-V platforms, both soft and ASIC implementation, e.g. the recently added Core-V MCU, while its co-simulation capability enables co-development with physical FPGAs, which can be used to build AI/ML accelerators. In collaboration with QuickLogic, Antmicro has also been enabling source FPGA tooling for the eFPGA found in the Core-V MCU, enabling users to kick-start flexible prototyping and pre-silicon development of ML-capable systems based on RISC-V + FPGA. Join the talk to learn more about the advantages of using Renode’s simulation, testing and CI capabilities for the development of machine learning applications.

Michael Gielda is VP Business Development and co-founder of Antmicro. With a background in both computer science and the humanities, he is an ardent believer in using open source to advance entire industries. Michael is vice-chair of Marketing in the RISC-V Foundation and Chair of Marketing and Outreach in CHIPS Alliance.