An introduction to RISC-V, Dr Graham Markall (OSHCamp 2017)
Channel: AB Open
Date: 2018-06-25

An Instruction Set Architecture (ISA) defines the interface between a computer's hardware and software, the valid instructions that the machine may execute. Unlike other ISAs (such as those from ARM, MIPS, Intel, etc.), the RISC-V ISA is provided under an open-source licence, giving anyone the freedom to create a RISC-V implementation.

This freedom has enabled a proliferation of RISC-V implementations for a wide range of applications, from small 32-bit embedded cores up to complex 64-bit multicore superscalar designs. As RISC-V is a relatively new ISA, there are many parts of the ecosystem such as compilers, assemblers, simulators, debugging tools, and other supporting infrastructure in rapid concurrent development.

This talk gives an overview of the RISC-V ISA, and takes a look at some of the more interesting RISC-V cores. We will take a short look at the present state of the RISC-V software ecosystem, and try to predict where we will see RISC-V implementations used in the future.

— Dr Graham Markall has a background in languages and compilers for scientific computing, and is well known for his work on the Numba project. He is part of Embecosm’s GNU tool chain team, where his current projects include the implementation of security enhancements to the GCC and LLVM compilers for RISC-V and ARM, and the development a GCC-based toolchain for a customised RISC-V processor.