Mod-01 Lec-14 Interconnect aware design: Impact of scaling, buffer insertion and inductive peaking
Channel: nptelhrd
Date: 2016-03-01

Advanced VLSI Design by Prof. A.N. Chandorkar, Prof. D.K. Sharma, Prof. Sachin Patkar, Prof. Virendra Singh,Department of Electrical Engineering,IIT Bombay. For more details on NPTEL visit http://nptel.ac.in