VLSI L2B Logical Effort
Channel: Studio IIT Bombay
Date: 06/04/2016

This is Part B of 2nd session of Analog and Mixed Signal Design and VLSI Design workshop arranged for teachers. It was delivered by Prof. Arun N. Chandorkar from IIT Bombay. 

In this session he talked about Multi stage logic network and also talked about delay in multi stage network.

The syntax used in the video title is as follow :
VLSI – Analog and Mixed Signal Design and VLSI Design workshop
L2B - Lecture 2B

This Analog and Mixed Signal Design and VLSI Design workshop for teachers was conducted from Aug 19 to Aug 21, 2008 under eOutreach project, sponsored by TIFAC, MHRD, Government of India, New Delhi.

This workshop had been arranged for teachers who attended it at IIT Bombay as a coordinator from the respective collages to get trained by IIT Bombay faculty.