oreboot on VisionFive 1 009: Docker over cpu
Channel: Daniel aka CyReVolt 🐢
Date: 2022-08-19

As part of the RISC-V International developer program, I received a StarFive VisionFive board, based on the JH7100 SoC featuring two SiFive U74 cores. My goal is to bring the oreboot port forward that we already had in progress for the predecessor board, the BeagleV. At the same time, I'm sharing the development process with the world doing live streams.

In this video, we take the cpu command to the next level: Leveraging environments described by Docker images, we run any software from them on our RISC-V CPU. With the VisionFive booted into LinuxBoot and running cpud, we showcase how a Dockerfile can be composed from scratch or an image from a container registry. In doing so, we compose ourselves a cpu namespace that lets us play with the commands from the RISC-V BusyBox image. Viewers can follow along via the RISC-V VM image in the cpubinaries repository.

Previous video: https://www.youtube.com/watch?v=llKU4lOXkjM&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6&index=8
Next video: https://www.youtube.com/watch?v=YPXWTjacUBs&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6&index=10

Twitch channel: https://twitch.tv/cyrevolt

References:
https://riscv.org/risc-v-developer-boards/
https://groups.google.com/a/riscv.org/g/devboard-community
https://starfivetech.com/en/site/boards
https://starfivetech.com/en/site/archive
https://github.com/starfive-tech
https://github.com/starfive-tech/bootloader_recovery
https://github.com/starfive-tech/JH7100_secondBoot
https://github.com/oreboot/oreboot/tree/main/src/mainboard/seeed/beaglev
https://github.com/starfive-tech/linux
https://www.linuxboot.org/
https://github.com/u-root/cpu#cpu-and-docker
https://github.com/u-root/cpubinaries
https://github.com/orangecms/hello-linux-rv64-rs/
https://hub.docker.com/r/riscv64
https://hub.docker.com/r/riscv64/busybox
https://github.com/carlosedp/riscv-bringup/issues/42