Designing an Efficient Combined Register File
Channel: RTL Engineering
Date: 2018-02-03

A short video detailing a few different implementations for an FPGA based MIPS Register File to be used in the VR4300 CPU implementation.

After editing this video, I realized that I had made a mistake with the final implementations. The BRAM implementation with with the bypass register would not work, since it requires the read addresses to be latched with the register clock. Instead of using the rsws BRAM, we would need to use a raws BRAM, which results in worse performance than simply using the raws BRAM. 
In short, the the final implementation choice should be switched.

Additionally, I did try some quick implementations of different register file configurations with Vivado, using performance optimization settings. They are as follows:

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==            Using .GT. for greater than, and .LT. for less than 
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==                              Artix-7  Speed Grade -1 
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- VR4300 using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 323.4 MHz .GT. 93.75 MHz
- Psuedo R5900 with 32 lines of 128-bits, only having 1 write and 2 read ports, using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 304.0 MHz .GT. 295 MHz
- R3000 with 32 lines of 32-bits, using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 331.4 MHz .GT. 33.86 MHz
- Pseudo PPC Gekko with 32 lines of 32-bits and clock rephasing, only having 1 write and 2 read ports,  using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 392.3 MHz .LT. 485 MHz

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==                              Artix-7  Speed Grade -3 
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- VR4300 using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 404.3 MHz .GT. 93.75 MHz
- Psuedo R5900 with 32 lines of 128-bits, only having 1 write and 2 read ports, using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 381.8 MHz .GT. 295 MHz
- R3000 with 32 lines of 32-bits, using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 410.5 MHz .GT. 33.86 MHz
- Pseudo PPC Gekko with 32 lines of 32-bits and clock rephasing, only having 1 write and 2 read ports,  using BRAM(raws) with the Performance_Retiming strategy results in an FMAX of 491.6 MHz .GT. 485 MHz

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Note that these are only best case numbers, especially considering the test setup.
Also note that the register file is only the slowest component in that simple datapath. In reality, the TLB will most likely be the slowest component, with the L1 Cache being a close second.



I am not affiliated with any of the companies mentioned in the video. This video is intended for educational purposes.