LMARV-1 reboot part 6: About CSRs and interrupts
Channel: Robert Baruch
Date: 2020-12-11

This part explains a bit about CSRs (Control and Status Registers) and how interrupts get handled.

nMigen exercises: https://github.com/RobertBaruch/nmigen-exercises/blob/main/README.md

github repo for code: https://github.com/RobertBaruch/riscv-reboot

RISC-V specs: https://riscv.org/technical/specifications/

nMigen tutorial: https://github.com/RobertBaruch/nmigen-tutorial/blob/master/README.md