LMARV-1 reboot part 7: Interrupts and exceptions, code complete???!
Channel: Robert Baruch
Date: 2020-12-18

This part explains mostly correctly how interrupts and exceptions work. And, that pretty much completes the initial phase of the project. Now to clean things up and make it mappable to real hardware. That isn't on an FPGA.

nMigen exercises: https://github.com/RobertBaruch/nmigen-exercises/blob/main/README.md

github repo for code: https://github.com/RobertBaruch/riscv-reboot

RISC-V specs: https://riscv.org/technical/specifications/

nMigen tutorial: https://github.com/RobertBaruch/nmigen-tutorial/blob/master/README.md