Analysis of a Tensor Core
Channel: RTL Engineering
Date: 2018-12-29

A video analyzing the architectural makeup of an Nvidia Volta Tensor Core.

References:

Pu, J., et. al. "FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI" (2016) https://arxiv.org/abs/1606.07852

Markidis, S., et. al. "NVIDIA Tensor Core Programmability, Performance & Precision" (2018). https://arxiv.org/pdf/1803.04014.pdf

Tensor Core overview:
https://www.nvidia.com/en-us/data-center/tensorcore/

Tensor Core + Volta Architecture Whitepaper:
http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf

CUDA programing details for Tensor Cores:
https://devblogs.nvidia.com/programming-tensor-cores-cuda-9/


I am not affiliated with any of the companies mentioned in the video. This video is intended for educational purposes.