Adders using structural modeling in Verilog HDL Part2
Channel: Nehal Shah
Date: 2021-08-22

VERILOG code for 8-bit ripple carry adder (RCA) using two 4-bit RCA where 1-bit full adder is used as component. 
Measure synthesis delay and resource utilization for 4 bit as well as 8 bit adder.

Verilog code is written and simulated using Vivado 15.3 version.