Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning
Channel: British Computer Society Open Source Specialists
Date: 2021-02-12

Presented by Pete Alexander, John Holden, Harry Cooper, Byron Theobald, Aaryaman Bhattacharya, Matthew Johns, University of Southampton

The open-source RISC-V instruction set architecture is gaining interest throughout industry and academia. One advantage of RISC-V is the ability to add custom instruction extensions to the processor targeting specific applications. This project has taken an existing core and designed an accelerator to handle vector instructions to speed up the inference of neural networks. As a benchmark, tinyMLperf has been used which has required vector instructions to be integrated into Tensorflow Lite for Microcontrollers. The goal is to show the benefits of custom instructions and stimulate similar work in the community.

This project has been completed by six fourth-year Electrical and Electronic Engineering students from the University of Southampton. This group project is required for the MEng degree and ran over 10 weeks in Autumn 2020. Each member of the team has different backgrounds, from digital design, to AI expertise, to compiler experience. The project has been supported by Embecosm.