x86 Front End Complexity (Part 1 - Pentium P5)
Channel: RTL Engineering
Date: 2022-04-27

The first part of a longer video talking about the complications introduced by the x86 instructions set as it relates to front end architecture design, and how early processors handled this complexity. This video covers some of the background needed, gives a short historic overview with the 8086, 286, 386/486, and then dives into the original Pentium (P5). 
The next part will cover the Pentium MMX (P55C).

The second part to this video can be found here:
https://youtu.be/7xBKHGLMkr4

A more detailed simulation of the Pentium decoding can be seen in this video:
https://youtu.be/f--MBGeVSSg

Correction: 
After posting this video, I realized that the 7B+7B explanation was inconsistent with the 1 byte offset heuristic. Likely, the V rotator and instruction buffer (after V decode 1) were both 11 bytes wide, while the U rotator and instruction buffer were both 7 bytes wide. This would allow for a full 12 bytes to be passed to the next stage, and 12 byte length instructions to be uncached (no need to take up length cache space if you can't decode 2 instructions, thus falling back to the 1 byte heuristic).

Chapters:
0:00 Architecture Goals and Performance
4:08 General Architectural Performance Methods
6:22 Processor Division - Front and Back
7:41 x86 Instruction Layout
10:03 8086 Decoding
11:00 386 Decoding
12:45 Pentium Decoding
14:53 x86 Statistics
16:20 Pentium Length Caching
18:12 Pentium Front End