Building a high throughput low-latency PCIe based SDR (33c3)
Channel: media.ccc.de
Date: 2016-12-27

https://media.ccc.de/v/33c3-8338-building_a_high_throughput_low-latency_pcie_based_sdr

Lessons learnt implementing PCIe on FPGA for XTRX Software Defined Radio

Software Defined Radios (SDRs) became a mainstream tool for wireless engineers and security researches and there are plenty of them available on the market. Most if not all SDRs in the affordable price range are using USB2/USB3 as a transport, because of implementation simplicity. While being so popular, USB has limited bandwidth, high latency and is not really suitable for embedded applications. PCIe/miniPCIe is the only widespread bus which is embedded friendly, low latency and high bandwidth at the same time. But implementing PCIe/miniPCIe is not for the faint of heart - you have to write your own FPGA code, write your own Linux kernel driver and ensure compatibility with different chipsets, each with its own quirks. In this talk we will look at the requirements for a high performance SDR like XTRX, how this leads to certain design decisions and share pitfalls and gotchas we encountered (and solved).



['Alexander Chemeris', 'Sergey Kostanbaev']