Learn Verilog 1: Ports and Assignments
Channel: Intriguing Chip Design
Date: 2022-07-14

We will use the problems at hdlbits, https://hdlbits.01xz.net , in order to learn Verilog. In this class we will cover basics such as what is a module, input and output ports, connecting wires.

Verilog is a language for hardware chip design. It is used to design silicon chips such as GPUs and CPUS.

This video is part of a series. You can find the full playlist at https://www.youtube.com/playlist?list=PLcmjvtERZNGhJ7LAE_qdtQ34ACfvFjelp .

Content:
00:00 - Introduction to this series of videos based on HDLBits website
01:16 - Chip Design Languages
02:01 - Assume some programming background
02:30 - Problem 1, background
03:22 - Ports
04:35 - Wires
06:41 - Module as code
09:49 - Assign values
11:19 - Problem 1 Statement
13:08 - A solution to Problem 1