Hardware accelerated Posit Computation (XOHW19-212)
Channel: casualengineering
Date: 2019-06-30

This video is part of my contribution to the Xilinx open hardware contest 2019.

Report: https://mp-force.ziti.uni-heidelberg.de/pdoebler/posit_xohw19-212/blob/master/doc/report_xohw19-212.pdf
Code: https://mp-force.ziti.uni-heidelberg.de/pdoebler/posit_xohw19-212
3D printable case for Zybo Z7-20: https://www.thingiverse.com/thing:3706028 
Xilinx Open HW Contest: http://www.openhw.eu/

Abstract:
Posits are a new approach for representation of real numbers. In contrast to IEEE floating point values, they do not have a fixed amount of bits for mantissa and exponent. Instead the mantissa gets larger for numbers with small exponent meaning that posits have a higher accuracy for numbers close to 1 compared to floats. The posit standard also allows data types with arbitrary bit lengths, which makes them interesting for certain use cases. In this report, a configurable HLS implementation of the posit standard is presented. A SAXPY kernel, as well as a block matrix multiplication unit are used to test the posit implementation. The results show, that the resource consumption is comparable to IEEE floats, but the variable bit length allows for higher degree of vectorization for bandwidth limited algorithms (SAXPY) and more effecient cache usage for cache limited algorithms (block matrix multiplication).