Very Basic Introduction to Formal Verification
Channel: Robert Baruch
Date: 22/07/2019

This is an extremely basic introduction to getting up and running with formally verifying modules written in Verilog using the open source tools Yosys and SymbiYosys. I'm definitely no expert, I'm just getting started. But hopefully this can help you get started too, so you can then find other resources to become better at it.

Installation cheat sheet: https://docs.google.com/document/d/1O4ql42YJcig84rhgrAEA04R7u-7LIisieX5QDgd68aI/edit

Some more advanced tutorials: https://zipcpu.com/