Mod-01 Lec-05 Logical Effort - A way of Designing Fast CMOS Circuits -Part III
Channel: nptelhrd
Date: 01/03/2016

Advanced VLSI Design by Prof. A.N. Chandorkar, Prof. D.K. Sharma, Prof. Sachin Patkar, Prof. Virendra Singh,Department of Electrical Engineering,IIT Bombay. For more details on NPTEL visit http://nptel.ac.in