oreboot on VisionFive 1 019: from stage to stage
Channel: Daniel aka CyReVolt 🐢
Date: 10/11/2022

As part of the RISC-V International developer program, I received a StarFive VisionFive board, based on the JH7100 SoC featuring two SiFive U74 cores. My goal is to bring the oreboot port forward that we already had in progress for the predecessor board, the BeagleV. At the same time, I'm sharing the development process with the world doing live streams.

In this video, after a look at the RISC-V Exchange website and the new Rust release, we pick up the two stages we had set up last time, and stitch them together into one image, changing the jump address so that we call the second stage from the first one. Succeeding to run, we then look at the work in progress pull request on GitHub, and based on a comment, bump the version of the riscv crate we are using. Eventually, we take a brief peek into the vendor provided DRAM initialization code, and leave including it for next time.

Previous video: https://www.youtube.com/watch?v=ucy_c_UTZwE&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6&index=18
Next video: https://www.youtube.com/watch?v=WlLCyMOTtzY&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6&index=20

Twitch channel: https://twitch.tv/cyrevolt

References:
https://riscv.org/risc-v-developer-boards/
https://groups.google.com/a/riscv.org/g/devboard-community
https://groups.google.com/a/riscv.org/g/devboard-community/c/utStFu8Q3A0
https://starfivetech.com/en/site/boards
https://doc-en.rvspace.org/
https://github.com/starfive-tech/linux
https://github.com/oreboot/oreboot
https://github.com/oreboot/oreboot/pull/606
https://riscv.org/exchange/
https://dprint.dev/
https://blog.rust-lang.org/2022/11/03/Rust-1.65.0.html
https://crates.io/crates/riscv