oreboot on VisionFive 2 007: SBI, alignment, Linux
Channel: Daniel aka CyReVolt 🐢
Date: 2023-09-18

During this video series, we develop firmware in Rust, targeting application processors. Continuing from the season on the VisionFive 1 board, we now work with the VisionFive 2, featuring the StarFive JH7110 RISC-V SoC.

In this video, we take a look at the programmatic surface of SBI in oreboot in breadth. We discuss aligned and unaligned memory access and how different platform levels may handle it, from hardware to software and compilers, and eventually look at the device tree that got a Linux kernel to boot up with ethernet enabled.

Previous series on the VisionFive 1:
https://www.youtube.com/watch?v=e9Momh944B8&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6

References:
https://github.com/oreboot/oreboot/pull/686
https://github.com/starfive-tech/linux
https://groups.google.com/a/groups.riscv.org/g/sw-dev/c/bmQJ8HVmquY/m/QDmPndFlCwAJ
https://forums.sifive.com/t/ld-sd-alignment/5530/2
https://github.com/riscv/riscv-platform-specs/pull/2
https://github.com/riscv-software-src/opensbi/blob/0ad866067d7853683d88c10ea9269ae6001bcf6f/lib/sbi/sbi_misaligned_ldst.c#L162
https://lore.kernel.org/all/20230704140924.315594-1-cleger@rivosinc.com/
https://lore.kernel.org/all/ZKnCOs0uyzdt7UFf@antec/
https://lists.riscv.org/g/tech-prs/message/569