Accelerating Physical Verification Productivity Part Two -- Synopsys
Channel: EE Journal
Date: 27/01/2021

January 27, 2021 -- Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process.
Watch the first episode in this series: Accelerating Physical Verification Productivity: http://bit.ly/2MuwLau
More information about Physical Verification using IC Validator: https://bit.ly/36iGO9J