FPGA implementation of the BABY or Manchester SSEM
Channel: Dave Wade
Date: 11/06/2015

This is an FPGA emulation of the baby written in VHDL and running on a Digilent NEXYS2 board with a Spartan 3E FPGA. The code uses the Spartan 3E on-chip RAM. It uses around 1% of the login on the chip and 3% of the on-chip RAM.

Its a functional implementation as the is parallel and the original is serial.

At present the program is pre-loaded. The next phase will be to add an interface to load code into the machine.