oreboot on VisionFive 2 002: Logging and DRAM
Channel: Daniel aka CyReVolt 🐢
Date: 2023-03-10

During this video series, we develop firmware in Rust, targeting application processors. Continuing from the season on the VisionFive 1 board, we now work with the VisionFive 2, featuring the StarFive JH7110 RISC-V SoC.



In this episode, we look at the recently released PDF version of the manual that is now available from StarFive's website, and recap the issue we had with printing over serial last time - which turned out to have been a linker setup issue where the SRAM base address was wrong. We then note down how this can be debugged with the help of oreboot's log crate, and eventually take a deep dive throgh the DRAM controller initialization code in StarFive's U-Boot fork, which we translate to Rust for oreboot.


Previous series on the VisionFive 1:
https://www.youtube.com/watch?v=e9Momh944B8&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6


References:
https://github.com/oreboot/oreboot/pull/686
https://github.com/orangecms/vf2-loader
https://github.com/starfive-tech/u-boot/tree/visionfive2
https://github.com/starfive-tech/VisionFive2/releases
https://doc-en.rvspace.org/JH7110/TRM/JH7110_TRM/sys_crg.html
https://doc-en.rvspace.org/JH7110/PDF/JH7110_TRM_StarFive_Preliminary.pdf
https://search.bilibili.com/all?keyword=oreboot