Making use of SIMD Vectorisation to Improve Code Performance
Channel: SciNet HPC at the University of Toronto
Date: 18/02/2023

We are reaching the end of Moore's Law, the number of cores per chip is increasing and clock rates are peaking. Applications must be parallelised in order to reach peak theoretical performance of modern hardware. Alongside larger core counts, CPU vector registers have also increased in size. The latest chips support 512-bit vector registers operating with AVX512 instructions, which can give up to a 16x speed-up. In this talk we will introduce the concept of SIMD vectorisation and go through a simple example. We will also look at some optimisation techniques to improve vectorisation efficiency. Finally we will go over a few analysis tools that help identify potential code optimisations.
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This webinar was presented by James Willis (SciNet) on February 15, 2023, as a part of a series of weekly Compute Ontario Colloquia. The webinar was hosted by SciNet. The colloquia cover different advanced research computing (ARC) and high performance computing (HPC) topics, are 45 to 60 minutes in length, and are delivered by experts in the relevant fields. Further details can be found at https://www.computeontario.ca/training-colloquia