oreboot on VisionFive 1 015: Rust embedded HAL
Channel: Daniel aka CyReVolt 🐢
Date: 17/10/2022

As part of the RISC-V International developer program, I received a StarFive VisionFive board, based on the JH7100 SoC featuring two SiFive U74 cores. My goal is to bring the oreboot port forward that we already h
ad in progress for the predecessor board, the BeagleV. At the same time, I'm sharing the development process with the world doihackingng live streams.

In this video, we talk about portability and the design of the Rust embedded HAL (hardware abstraction layer). We start off with a look at the RISC-V development board program relaunch, the 2022 RISC-V TSC (technical steering committee) election, and the recordings from OSFC (Open Source Firmware Conference), where we had a talk on the status of the oreboot project with a focus on RISC-V. Then we read from the Embedded Rust Book how the different components of the embedded HAL design work together, and what the relationship with global instances, mutexes and concurrency is. Investigating what the problem in our current code is that is the same as for the D1 SoC, but stopping to output on the serial on the JH7100, we look at the objdump (disassembly of our binary) and low-level instructions in the RISC-V spec. After cross-checking with the U74 core manual and looking into other options than the spin crate that we use, we finally leave the problem for another day.

Previous video: https://www.youtube.com/watch?v=TuwIqQ0r_0Q&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6&index=14
Next video: https://www.youtube.com/watch?v=qNkE8Szu9g4&list=PLenOHeTI_A9PSGshDnEc4dYK-GSnCshk6&index=16

Twitch channel: https://twitch.tv/cyrevolt

References:
https://riscv.org/risc-v-developer-boards/
https://groups.google.com/a/riscv.org/g/devboard-community
https://groups.google.com/a/riscv.org/g/devboard-community/c/utStFu8Q3A0
https://starfivetech.com/en/site/boards
https://doc-en.rvspace.org/
https://github.com/starfive-tech/linux
https://github.com/oreboot/oreboot
https://github.com/oreboot/oreboot/pull/606
https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf
https://groups.google.com/a/riscv.org/g/devboard-community/c/gXSyRxRGDsE
https://riscv.org/blog/2022/10/announcing-risc-v-internationals-expanded-developer-boards-program-heres-how-to-participate-risc-v-international/
https://groups.google.com/a/riscv.org/g/devboards-program
https://wiki.riscv.org/display/HOME/2022+TSC+Election+-+Community+and+Individual+Members
https://www.osfc.io/2022/talks/oreboot-2022-status-report-on-to-risc-v/
https://docs.rust-embedded.org/book/portability/index.html
https://docs.rust-embedded.org/book/concurrency/index.html#mutexes