Video Interfacing with Zynq (FPGAs): Part 6 Combining Image Processing and Video Output
Channel: Vipin Kizheppatt
Date: 14/04/2020

#Xilinx #Zedboard #VDMA #SDK 
In this tutorial we combine the previously developed image processing IP (sobel edge detector) and the Video display system
Source code
https://github.com/vipinkmenon/imageProcessingVideoOut
Prerequisite Videos
Part 1 Intro: https://youtu.be/_o4FbVFLbuw
Part 2: AXI4 to Stream Video: https://youtu.be/a6OXozk1Ix8
Part 3: VDMA : https://youtu.be/cADto95fV7Q
Part 4: Software for VDMA : https://youtu.be/IGdr4QRrOcs
Part 5: Displaying image on monitor https://youtu.be/-i15JlWp57c
Developing edge detection IP
https://youtu.be/TcjqZG2pbHw