Designing an Efficient MIPS TLB [Part 2]
Channel: RTL Engineering
Date: 2018-05-01

Part 2 of 2 detailing the design an implementation of a FPGA based MIPS Translation Look aside Buffer (TLB) to be used in the VR4300 CPU implementation. Additionally looks at expanding the TLB for an Emotion Engine R5900 CPU.

------------- Vivado Synthesis Settings ----------
Optimization Settings:

Synthesis - Flow_AlternateRoutability
-directive FewerCarryChains
-retiming
Implementation -Performance_Retiming
Place Design
-directive ExtraPostPlacementOpt
Post-Place Phys Opt
-enabled
-directive AlternateFlowWithRetiming
Post-Route Phys Opt Design
-enabled
-directive default
Additional optimizations
Phys_Opt_Design -critical_Cell_Opt
Phys_Opt_Design -routing_opt
Phys_Opt_Design -placement_opt
Phys_Opt_Design -rewire
Phys_Opt_Design -retime


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