Efficient programmable power‐of‐two scaler for the three‐moduli set {2 <i> <sup>n</sup> </i> <sup>+</sup> <i> <sup>p</sup> </i> , 2 <i> <sup>n</sup> </i> − 1, 2 <i> <sup>n</sup> </i> <sup>+1</sup> − 1}

ETRI JournalVolume 42, Issue 4 p. 596-607 ORIGINAL ARTICLEFree Access Efficient programmable power-of-two scaler for the three-moduli set {2n+p, 2n − 1, 2n+1 − 1} MohammadReza Taheri, Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, IranSearch for more papers by this authorKeivan Navi, Corresponding Author navi@sbu.ac.ir orcid.org/0000-0002-5586-7766 Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran Correspondence Keivan Navi, Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran. Email: navi@sbu.ac.irSearch for more papers by this authorAmir Sabbagh Molahosseini, Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, IranSearch for more papers by this author MohammadReza Taheri, Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, IranSearch for more papers by this authorKeivan Navi, Corresponding Author navi@sbu.ac.ir orcid.org/0000-0002-5586-7766 Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran Correspondence Keivan Navi, Faculty of Computer Science and Engineering, Shahid Beheshti University, Tehran, Iran. Email: navi@sbu.ac.irSearch for more papers by this authorAmir Sabbagh Molahosseini, Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, IranSearch for more papers by this author First published: 27 May 2020 https://doi.org/10.4218/etrij.2018-0408AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat Abstract Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter-modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well-known moduli sets {2n − 1, 2n, 2n + 1} and {2n, 2n − 1, 2n+1 − 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic-friendly moduli set {2n+p, 2n − 1, 2n+1 − 1}. The proposed algorithm yields high speed and energy-efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed-radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler. 1 INTRODUCTION Digital signal processors (DSPs) lie at the heart of many digital products in numerous areas, including multimedia processing, telecommunications, and cryptography. Power consumption and performance are key factors that should be considered in the design of such products. Arithmetic parallelism can be exploited to achieve high-performance and power-efficient implementations of DSPs because many DSP algorithms, such as the finite impulse response, infinite impulse response, fast Fourier transform, and discrete wavelet transform, rely on sum-of-products computations. The parallelism of such arithmetic operations can be realized by using the residue number system (RNS) as an alternative number representation instead of the weighted binary number system [1]. The parallel and modular arithmetic nature of the RNS enhances the performance of the RNS data path and reduces power dissipation without degrading latency [2]. However, the iterative nature of DSP algorithms necessitates the prevention of overflow to avoid generating erroneous results. At first glance, selecting a moduli set that guarantees a sufficiently large dynamic range may appear to be the most appropriate method for solving the overflow issue. This method can be applied by increasing the number of moduli or increasing the size of one or more moduli. However, the downsides of adopting such an approach lead to overall system performance degradation, increased circuit timing uncertainly, and higher delay variation in the system data path. Therefore, scaling operations (ie, division by an integer) are employed to reduce the word length of intermediate results. Scaling in the RNS is known as a complex operation due to the use of inter-modulo computations. The long delay and significant hardware complexity of scaling in DSP applications has turned efficient scaler design into a major issue when designing RNS-based DSPs. Several contributions to RNS scaling problems have been reported in the literature. Previous RNS scaler schemes can be categorized based on different criteria [3-5]. The accuracy of an RNS scaler is the first criterion. According to this criterion, an RNS scaler can be categorized into two classes. In the first class, the Chinese remainder theorem approach can be utilized to derive inexact scaled results with some fractional errors [6-10]. Scalers belonging to this class may not be appropriate for certain critical applications. The second class focuses on the exact RNS scaling problem. In such techniques, in the first step, a ceiling function is applied to the division of a weighted number X by a scaling factor. In the second step, modulo reduction is applied to the result of the first step. In the latter step, an expected result is generated via base extension or other iterative algorithms [11-13]. Another criterion is the scaling factor of an RNS scaler, which can be categorized into three main classes: scaling using one modulus or the product of several moduli, scaling using a co-prime factor with the moduli of an RNS, and scaling using a power-of-two factor. Most recent contributions to the RNS scaling problem are based on the third class because implementations using the first and second classes result in poor performance and considerable hardware costs [14-17]. The hardware implementation technique is another criterion and can be classified into two groups. The hardware realization of the first group requires lookup tables [6-12, 15, 16], while the second group, which is known as adder-based implementation, uses combinational logic [3-5, 13, 14, 17-20]. The implementation of the former approach suffers from two main problems. First, there is a dramatic increase in hardware costs when increasing the dynamic range. Second, processing throughput is restricted and degraded by poor pipelining efficiency. In recent years, the design of exact, memoryless, power-of-two scalers has attracted the attention of many researchers owing to the excellent efficiency of such systems [5]. In [4], a high-performance, low-hardware-cost exact scaler was proposed for the three-moduli set {2n − 1, 2n, 2n + 1}. A 2n signed integer scaler, which is an extension of the method in [4], was proposed in [18] based on a low-complexity and high-performance hardware implementation. In [19], an efficient programmable power-of-two scaler was presented for the three-moduli set {2n − 1, 2n, 2n + 1} to reduce the risk of over-scaling problems (ie, scaling more than necessary, which leads to unnecessary accuracy reduction). In this method, the scaling factor can be identified at run time. Recent works in [5] and [20] have presented power-of-two scalers for the extended moduli set {2n − 1, 2n+p, 2n + 1}. The former presented an accurate and efficient 2n scaler for the augmented three-moduli set, as well as its extension set an with an additional co-prime moduli. The latter presented 2n and 2n+p scalers for the augmented moduli set {2n − 1, 2n+p, 2n + 1} with efficient hardware structures. Another class of moduli sets in the form of {2a, 2b − 1, 2c − 1} with c = b − 1 or c = b + 1 has also attracted the attention of researchers due to its efficient and modulo-(2n + 1)-free internal arithmetic operations [21-28]. Based on the impressive theoretical properties of this type of moduli set, different algorithms and hardware implementations for a variety of RNS operations have been proposed in the literature. In the search for an efficient hardware implementation of the reverse converter, several contributions have been proposed for the moduli sets {2n, 2n − 1, 2n±1 − 1} [21-23], {2n+p, 2n − 1, 2n−1 − 1} [24], and {22n, 2n − 1, 2n±1 − 1} [25]. For {2n, 2n − 1, 2n+1 − 1}, efficient sign detectors have also been proposed in [26] and [27]. Recently, a remarkable effort resulted in the efficient hardware implementation of a sign-magnitude comparator for the moduli set {2n, 2n − 1, 2n+1 − 1} [28]. Additionally, an elegant design approach for the enhanced arithmetic unit of an RNS was proposed in [29] based on a shared hardware/software method. The chosen moduli set consists of an even modulus 2n with remaining moduli of type 2m − 1. Although a few contributions have been made regarding the design of RNS scalers for the aforementioned three-moduli sets [30, 31], scaling problems with programmability features for this class of moduli sets have not yet been considered. This paper proposes a novel exact scaler for the efficient moduli set {2n+p, 2n − 1, 2n+1 − 1} . The proposed scaler has the ability to determine the scaling factor at run time. To achieve this goal, for the first time, a programmable power-of-two scaler is presented for this augmented three-moduli set. By using a variable scaling factor 2λ, up to half of the dynamic range of a given RNS can be scaled during runtime for the particular case of p = n. The design approach in [29] can be considered as a potential application of the proposed programmable scaler to ensure its reliability. The efficiency of the proposed RNS scaler has a direct impact on the efficiency of various applications, such as that presented in [29]. The remainder of this paper is organized as follows. Section 2 introduces notational conventions that are used throughout this paper as well as the essential theoretical background of the RNS. The algorithm and architecture for the proposed programmable power-of-two RNS scaler are presented in Section 3. The very-large-scale integration (VLSI) architecture of the proposed scaler based on the derived formulations is presented in Section 4. Performance evaluations based on gate-level and experimental results are presented in Section 5. Section 6 contains our concluding remarks. 2 BACKGROUND 2.1 Notations The following notations have been adopted in this paper: denotes the residue of α modulo β. is the greatest integer that is less than or equal to ∂. is the multiplicative inverse of . Aα:β refers to an (α – β + 1)-bit slice of the A vector from position β to position α (ie, ) CLS (α, β) indicates shifting α circularly to the left by β bits. denotes the one's complement of ω vector. || is an operator that concatenates two integer numbers in a binary representation. refers to a vector that is formed by β concatenated α strings (i.e., ). ∧, ∨, ⊕, and ⊙ are bitwise AND, OR, XOR, and XNOR operators, respectively. 2.2 RNS preliminaries An RNS is characterized by a finite set of the L co-prime numbers {m1, m2, …, mL} with L ≥ 2, where mi are moduli. The dynamic range M of an RNS is defined by the product of all the moduli. Any integer has a unique representation with an L-tuple (x1, x2, …, xL), where xi is the minimum non-negative remainder of the division of X by mi. Based on the isomorphic relationship between and , where and , the computations of residues are performed in parallel in independent arithmetic channels [2]. The scaled result of a given weighted number X with a scaling factor of K can be expressed as follows [7]: (1) In the RNS {m1, m2, …, mL} with the mixed-radix representation [vL, vL−1, …, v1], the weighted number X can be derived as follows [2]: (2)where the mixed-radix coefficients vi can be formulated as the following expressions: (3)which can be generalized as follows: (4) The following modular arithmetic properties were exploited in this study to simplify the hardware realization of the proposed scaling algorithm. Property 1 [4]: (5) Property 2 [4]: (6) Property 3: k-bit binary number R modulo 2n−1, where n < k ≤ 2n is equal to , R1 = Rn−1:0, and . Proof: Because n < k ≤ 2n, the following statement holds: (7) Property 4: For any integer ρ, . Proof: Consider ρ = i × n + r with . Therefore, the following statement holds: (8) For the three-moduli set {2n+p, 2n − 1, 2n+1 − 1}, the weighted number X can be obtained using mixed-radix conversion (MRC) as follows: (9)where (10) 3 PROPOSED PROGRAMMABLE POWER-OF-TWO SCALER ALGORITHM By using MRC, the scaled integer S with a programmable scaling factor 2λ for the moduli set {2n+p, 2n−1, 2n+1−1} can be obtained from the following equation: (11) Because the results of scaling should be directly processed by the arithmetic unit of a given RNS in each moduli channel, it is necessary to generate a scaled number S in residue form. The scaled residue corresponding to the modulo 2n+p channel can be obtained by applying the modulo 2n+p to (11) as follows: (12) From (12), it is clear that the calculation of Y lies at the heart of realizing s1. The multiplicative inverses required for calculating Y are , , and , where m1 = 2n+p, m2 = 2n−1, and m3 = 2n+1−1. Proof.According to the definition of the multiplicative inverse, it is easy to derive the following results: By substituting the values of , and into (3), v2 and v3, can be simplified using the following expressions: (13) (14) The derivation of Y considering the operands v2 and v3 can be defined as follows: (15)where and . For the modulo 2n − 1 and 2n+1 − 1 channels, si is given by (16)where and . The scaled residues of the modulo m2 and m3 channels can be simplified according to (17), (18), (19), and (20). For the modulo m2 channel, Properties 1 to 4 and the equality are considered in the derivation of the scaled residue s2 according to the value of λ as follows: (17) It should be noted that for p = 0, the second condition does not appear as λ ≤ n. Therefore, the formulation of s2 for p = 0 can be simplified as (18) For the modulo m3 channel, the scaled residue s3 considering and Properties 1 to 4 can be derived using the following detailed formulations according to the value of λ: (19) It is notable that for p ∈ {0, 1}, the second condition is not satisfied as λ ≤ n + 1. Therefore, the formulation of s3 for p ∈ {0, 1} can be shortened to (20) The concept behind the consideration of the dummy terms and in the first conditions of (17) and (19) will be discussed in the next section. Numerical Example: Consider the moduli set {64, 15, 31} with n = 4 and p = 2. The goal is to achieve power-of-two scaling of the weighted number X = (23456)10 with a residue representation (32, 11, 20) using different scaling factors of 21, 22, 24, and 26. Based on these scaling factors, the scaled values of X are equal to S = 11728, 5864, 1466, and 366, respectively. The numerical computation of s1, s2, and s3 for these scaling factors is outlined in Table 1. TABLE 1. Computation of scaled residues for different scaling factors of 21, 22, 24, and 26 based on numerical examples λ i si 1 1 2 3 2 1 2 3 4 1 2 3 6 1 2 3 4 VLSI ARCHITECTURE OF THE PROPOSED SCALER The proposed programmable RNS scaler for the moduli set {2n+p, 2n − 1, 2n+1 − 1} consists of three independent blocks that perform modular scaling on each channel in parallel. The detailed implementation of each block will be discussed in the following sections. Three types of shifters are utilized for the realization of these blocks. The type-I shifter performs logical right shifting, where the empty bit positions in its most significant output bits are filled with zeroes. The type-II shifter performs circular left shifting and the type-III shifter performs a logical left shift on the one's complement of its input data. The empty least significant bits in the output of the type-III shifter are padded with ones. 4.1 s1 generator From (12), the generation of s1 can be obtained from an (n + p)-bit slice from position λ to position n + p + λ − 1 in the vector that is generated by the concatenation of Y and x1. The implementation of s1 for the proposed moduli set is realized using a (3n + p + 1)-bit type-I shifter (Shifter 1) with λ as the shift value and the concatenation of Y and x1 as the data input. The (n + p)-least significant bits of the Shifter 1 output yield the expected value. As stated previously, the well-organized realization of Y plays a crucial role in determining how well the scaler block operates in an RNS. For calculating the Y signal, the VLSI architecture is defined as follows. To implement the v2 architecture, two intermediate signals S and C can be considered. From (13), for p = 0, S and C are equal to x2 and , respectively. For p > 0, S and C can be generated from an n-bit carry save adder (CSA) with end-around carry (EAC) [32]. The inputs of the CSA are v2,a = CLS(x2, n − p), , and . The addition of S and C in the modulo 2n − 1 should be performed to realize the value of v2. Figures 1A and 1B illustrate the hardware architectures of v2 for p = 0 and p > 0, respectively. FIGURE 1Open in figure viewerPowerPoint (A) Schematic of v2 for p = 0. (B) Schematic of v2 for p > 0 The substantial computational delay of v3 in its serial form with v2 can be mitigated using a multiplexer-based approach, which parallelizes v2 and v3 computations. To this end, we removed the imposed delay of v2 from the v3 computational critical path as follows. Considering (14), can be described for two different cases. For S + C ≠ 2n − 1, is equal to (co = 1 if S + C > 2n-1). Otherwise, the value of is equal to zero and can be detailed as . The correction bit is equal to one when S and C are bitwise complements (S + C = 2n − 1). is generated using the available Pn−1:0 and Gn−1:0 in a parallel prefix structure as [33]. When considering these cases, because co and cannot both receive a value of one simultaneously, can be expressed as , where . As a result, v2, v3,τ = 0 and v3,τ = 1 are computed concurrently and the expected result of v3 based on τ is selected from v3,τ = 0 and v3,τ = 1. For τ = 0 and τ = 1, v3 can be expressed as follows: (21) (22)where I0 is equal to and for p = 0 and p > 0, respectively. I1 can be represented as . is also obtained by inverting each bit of x3, followed by a -bit circular left shift. For p < 2 and p ≥ 2, J0 can be represented as and , respectively. J1 and J2 are equal to and , respectively. Because the three (four) first terms of v3 when p ≤ 2 (p > 2) are similar for both values of τ and the difference in the last term is only in one bit, relative to the achieved speedup, the hardware redundancy of this parallelism is insignificant. The n most significant bits of J1 and J2 are absolutely identical terms and the difference is only in the least significant bit. Therefore, one n-bit EAC CSA with C, zn:1 and wn:1 as input operands can be utilized to save additional hardware elements instead of using J1 and J2 in the reduction process. The remaining terms f0, f1, f2, and f3 are also yielded by AND, OR, XOR, and XNOR operators because the least significant bits of z, and w should be incremented by constant values of zero and one, respectively. The hardware architecture of v3 is depicted in Figures 2A and 2B for p ≤ 2 and p > 2, respectively. In Figure 2, z and are the carry vectors, and w and are the summation outputs of the EAC CSA. Furthermore, the expressions of Q0, Q1, Q2, and Q3 are defined as follows: (23)where f0 = z0 ⊕ w0, f1 = z0 ∧ w0, f2 = z0 ⊙ w0, and f3 = z0 ∨ w0. FIGURE 2Open in figure viewerPowerPoint (A) Schematic of v3 for p ≤ 2. (B) Schematic of v3 for p > 2 According to (15), Y can be obtained from two different adders. The first is an adder with and as input signals and one as a carry input. The second is an adder with and v3,n:1 as input vectors and a carry input driven by the first adder's carry output. Based on its constant inputs, the structure of the second adder can be modified to achieve enhanced performance. This approach is appropriate for a parallel prefix adder structure, where the carry input of a binary adder can be applied in the final stage of the adder with insignificant latency. For another type of realization using ripple carry adders, a multiplexing approach is more appropriate. In this paper, we consider the parallel-prefix-adder-based realization. An example of the realization of Y using a parallel prefix adder for n = 4 is presented in Figure 3. It is clear that this approach imposes less latency on the adder architecture compared to the previous method presented in [34]. The overall architecture of the Y generator is also presented in Figure 4. FIGURE 3Open in figure viewerPowerPoint Realization of Y with a parallel prefix adder for n = 4 FIGURE 4Open in figure viewerPowerPoint Overall architecture of the Y generator 4.2 s2 generator According to (18), for the special case of p = 0, the first and second terms are yielded by an n-bit type-II shifter (Shifter 2) and type-III shifter (Shifter 3), respectively, followed by a modulo 2n − 1 adder to produce s2. The shift value for both Shifter 2 and Shifter 3 is n − λ. From (17), for p > 0, the first term in s2 is equal for both conditions and the differences lie in the second and third terms. The first term is realized through a -bit circular left shift of x2 by an n-bit type-II shifter (Shifter 4). For the second and third terms, it is worth noting that based on λ, which is determined at run time, two distinct hardware realizations increase the hardware cost of s2. We will demonstrate that the hardware implementation of the second and third terms can be realized independently from λ by using as a dummy term in the first condition of (17). By adopting this approach, the second and third terms of s2 can be produced simultaneously through a 2n − λ-bit left shift of the one's complement of x1 and padding with ones by using a 2n-bit type-III shifter (Shifter 5). The n most significant bits and n least significant bits of the output of Shifter 5 yield the second and third terms, respectively. Finally, s2 is derived by an EAC CSA followed by a modulo 2n − 1 adder. 4.3 s3 generator For p ∈ {0, 1}, s3 consists of only two terms (see (20)). The first is produced by an (n + 1)-bit type-II shifter (Shifter 6) and the second is produced by an (n + 1)-bit type-III shifter (Shifter 7). Next, the outputs of Shifters 6 and 7 are fed into a modulo 2n + 1 − 1 adder to generate the expected value s3. For Shifters 6 and 7, the shift value is n – λ + 1. According to (19), for p > 1, similar to s2, the first term in s3 has the same value for both conditions of the scaling factor. The first term in s3 is a circular left shift of x3 with a value of produced by an (n + 1)-bit type-II shifter (Shifter 8). The mechanism for generating the second and third terms of s3 is analogous to that applied to the second and third terms of s2. Therefore, the realization of the second and third terms of s3 can be accomplished independently of λ to avoid hardware redundancy. To this end, a (2n + 2)-bit type-III shifter (Shifter 9) is utilized to produce the second and third terms of s3 concurrently. This shifter generates a (2n + 2)-bit output with 2n – λ + 2 as the shift value. The second and third terms of s3 are yielded by the n + 1 most significant bits and n + 1 least significant bits of the output of Shifter 9, respectively. These three terms produce s3 with an EAC CSA, which is followed by a modulo 2n+1 − 1 adder. The overall architecture of the proposed programmable scaler for the VLSI implementation of the proposed algorithm with different p-values is presented in Figure 5. FIGURE 5Open in figure viewerPowerPoint Block diagram of the proposed programmable scaler. (A) Overall architecture, (B) s1 generator, (C) s2 generator for p = 0, (D) s2 generator for p > 0, (E) s3 generator for p ∈ {0, 1}, and (F) s3 generator for p > 1. The λi values are determined according to the s2 and s3 generator subsections 5 PERFORMANCE EVALUATIONS AND COMPARISONS 5.1 Theoretical evaluation In this study, the unit-gate (U-G) model [35] was adopted to conduct a technology-independent assessment of the area and time requirements of the evaluated designs. According to the U-G model, two-input monotonic gates, such as AND and OR gates, have one unit of area and delay. In this model, both the area and delay of two-input XOR, XNOR, and 2:1 multiplexer gates are considered as two units. This model also considers an area of three units and delay of two units for half adders, and an area of seven units and delay of four units for full adders. The area and delay of inverters are not considered in the U-G model. Furthermore, it is assumed that multi-input logic gates are constructed from two-input basic logic gates in an efficient manner. The binary adder, modulo 2n − 1 adder, modulo 2n + 1 adder, and different types of CSAs and shifters are the main requirements for the architectures of the reviewed designs. In this theoretical evaluation, the adders adopted in [36, 37] were considered. Binary adders are considered as and units of area and delay, respectively [32]. The modulo 2n−1 adders are considered to have an area of units and imposes a delay of units. The area complexity and delay of modulo 2n + 1 diminished-one adders are units and units, respectively [36]. For shifters and CSAs, the area and delay differ based on the structures of their components. In additional to the proposed programmable scaler, our comparison pool included the following works. Hybrid programmable power-of-two scaler: To the best of our knowledge, no specific programmable scaler for the moduli set {2n+p, 2n − 1, 2n+1 − 1} has been developed. An appropriate method for evaluating the proposed programmable scaler is to consider a hybrid approach as a primary reference. This type of evaluation is a conventional method that has been adopted in numerous studies, such as [5] and [19]. In general, the hybrid RNS scaler performs the RNS scaling algorithm in three steps. In the first step, by using a reverse converter (RC), residues are decoded into a weighted value. Next, the weighted value is scaled by a binary scaler (BS). Finally, a forward converter (FC) unit produces the expected scaled residues [5]. For the sake of fair comparison, the calculation of weighted number X from its residues (as first step of programmable hybrid scaler for the moduli set {2n+p, 2n−1, 2n+1 − 1}) in the hybrid model was performed by concatenating Y and x1 based on (9). [19]: Among state-of-the-art RNS scalers, a design that offers programmability can be found in [19]. This scaler provides a fully combinational architecture for an arbitrary moduli set {2n − 1, 2n, 2n + 1}. The evaluation of [19] in this paper is considered for . It is worth noting that the proposed moduli set and the balanced three-moduli set {2n − 1, 2n, 2n + 1} are not in the same class. One major advantage of the moduli set {2n+p, 2n − 1, 2n+1 − 1} is that it has more efficient modular arithmetic operations, especially multiplication, when compared to the balanced three-moduli set {2n − 1, 2n, 2n + 1}. The advantage of the arithmetic unit of the moduli set {2n+p, 2n − 1, 2n+1 − 1} over the balanced three-moduli set {2n − 1, 2n, 2n + 1} stems from the existence of the modulus 2n + 1 in the latter moduli set. A recent study [38] demonstrated the superiority of the moduli set {2n+p, 2n-−1, 2n+1 − 1} in terms of its arithmetic unit. However, based on the conjugation of 2n − 1 and 2n + 1 in {2n − 1, 2n, 2n + 1}, this moduli set has much simpler inter-modulo operations, such as RC, compared to the class of the proposed moduli set. In applications for which the arithmetic unit has a significant impact on system performance, employing the {2n+p, 2n − 1, 2n+1 − 1} RNS is more affordable. Because the circuit area and delay of the proposed programmable scaler are strongly dependent on the p-value, various theoretical complexity descriptions can be derived based on the U-G model. To avoid ambiguity, the maximum p-value (‘n’) was considered as the worst-case scenario for area and delay complexity assessment. According to the U-G model, the area and delay of the considered designs can be estimated as follows. Based on the assumptions above, the areas and delays of the RC, BS, FC blocks of the hybrid programmable power-of-two scaler are and , and , and and units, respectively. According to the scaling algorithm in [19], the scaler architecture contains three parallel channels. By considering as t