Reviewerly/exHarmony huggingface dataset:
Analysis of intrinsic elements of poetry for class IV students of SDIT Insan Karima Cigombong

Background: Poetry is results work literature, which arises from expression feelings and thought, and arises in situation certain. Thing this seen in statement that nothing, rhythm, and pressure play role important in poetry, language imaginative and choice say (vocabulary) arranged by bait, which is total CLASSIFIED in each table, and so on. Poetry is of course not a simple work of art, but a very complex organism. Poetry is created with different linguistic and aesthetic elements. Poetry is also an important record and interpretation of human experience and is written in the most memorable form. There are two main elements in building a poem, namely intrinsic and extrinsic elements.&#x0D; Purpose: The purpose of this study was to determine students' ability to compose poetry based on the intrinsic elements of class VI SDIT Insan Karima.&#x0D; Design and methods: The research was conducted using a qualitative approach. The method used by researchers is descriptive qualitative. The subjects in this study were documents made by students, totaling 17 poems. The data collection tool used by the researcher was a document written by a class IV student at SDIT Insan Karima and filling in the rubric carried out by the researcher was based on the theory of Saefu Zaman&#x0D; Results: The results of this study are that out of 17 student works, almost 100% of the poems made are in accordance with the intrinsic elements requested, but the need for further guidance to students in managing vocabulary that will be poured into these poems.
Auto-LUT: Auto Approximation of Non-Linear Operations for Neural Networks on FPGA

The approximation of non-linear operation can simplify the logic design and save the system resources during the neural network inference on Field-Programmable Gate Array (FPGA). Prior work can approximate the non-linear operations with piecewise linear (PWL) function, but such approximation neglects considering the hardware overhead simultaneously. This paper proposes a novel approximation framework called Auto-LUT, which leverages a neural network to automatically approximate the non-linear operations. The framework formulates the approximation error and hardware overhead as a multi-objective optimization problem and employs an automated search mechanism to find the minimum number of segments and data bit width. To improve the approximation accuracy, we propose a bias clipping operation during the training of approximation networks, which enforces the model to approximate within the range of interest. Moreover, a hardware-friendly quantization scheme is further introduced to simulate the hardware behavior, thereby reducing the hardware overhead. Finally, a customized hardware architecture based on FPGA is utilized to deploy the quantized result. The experimental results show that Auto-LUT costs 56.32% less LUTs and 32.31% less flip-flops (FF) while reducing 4.32% approximation error compared to the state-of-the-art method.
Fast Vehicle Detection and Tracking on Fisheye Traffic Monitoring Video using Motion Trail

We develop a vehicle detection and tracking scheme based on the concept of motion trails for fisheye traffic monitoring videos. The motion trail combines the moving object traces in several frames into one image. Because it collects information from multiple frames, the accuracy of detecting a trail is higher than a single-frame object detector. Essentially, it merges the detection and tracking processes into one process. In addition, a lightweight neural net is sufficient to detect the trail, which saves computing time and memory. After detecting the trails, we extract individual car locations at each frame using a multi-head trail extractor. Then, a multi-modal bidirectional LSTM can further improve detection accuracy. We adopt the public ICIP2020 VIP Cup dataset for training and testing. Our approach is 14 percentage points (pp) better than the state-of-the-art single-frame rotated object detector (R3Det) on the challenging nighttime video, and it is 5 FPS faster in inference speed. Our scheme achieves the AP <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">50</inf> accuracy comparable with the state-of-the-art video object detector (MEGA), but its speed is 3 times faster, and its model size is only 28% of that of MEGA.
REGAL: Reprogrammable Engines for Genome Analysis on LPDDR4x-based Stacked DRAM

Genomic big data analysis pipelines are bottlenecked with massive data movement between CPU and memory hierarchy. Recently developed Stacked Embedded DRAM (SEDRAM) with high density hybrid bonding offers not only high bandwidth concurrent data accesses, but also highly parallel distributed data processing on the logic layer. However, the complex logical flow and data dependencies pose challenges to existing Near-DRAM Processing (NDP) solutions for analysis such as string pattern matching using FM-Index. In this work, we propose REGAL, a highly scalable and re-programmable solution on SEDRAM memory system. REGAL architecture maximizes intra-query parallelism and enhances occupancy of all components. The efficient data layout and mapping minimizes round-trip communications between processing engines. The programmability of REGAL further enables effective prefetching to support variations in data characteristics and involved algorithms. REGAL demonstrates up-to 17.3x and 70.6x speedup and energy reductions compared to multithreaded CPU implementation for FM-Index queries, while achieving performance comparable to state-of-the-art fixed-function NDP implementation.
An FPGA-based Lightweight Deblocking CNN for Edge Devices

The demand for multimedia data is rapidly increasing in many applications running on edge devices. The data compression method is essential for efficient communication in limited network bandwidth. However, the compressed data contains blocking artifacts that cause perceptual quality degradation and visual recognition problems. Recently, deep learning-based works have shown excellent progress in deblocking tasks. However, most previous works have used complex and deep network architectures that require high computational cost and large amounts of memory to improve performance. Therefore, deploying these networks as edge device applications is highly challenging work. In this paper, we propose an FPGA-based lightweight deblocking convolutional neural network (CNN) for edge devices. We present a lightweight CNN architecture to efficiently reduce blocking artifacts in the color domain. In addition, two optimization methods were introduced to further decrease the computation and memory requirement. Compared with CNNs proposed in other works, the number of MAC operations and the model size were reduced by approximately <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 145$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 2,300$</tex> , respectively. Finally, the proposed deblocking CNN has been implemented on a ZCU104 FPGA board. As a result of measuring the frame rate, it achieved 30.73 FPS.
Optimizing Density-Based Ant Colony Stream Clustering Using FPGA-Based Hardware Accelerator

In the era of IoT, a massive amount of data will be generated from various sensors and corresponding IoT devices. Density-based Ant Colony Stream Clustering (ACSC) is one of the best solutions for big data processing for real-world applications, due to its many inherent traits. Also, FPGAs are one of the best avenues to support/accelerate complex algorithms, such as ACSC. In this paper, we introduce an FPGA-based hardware accelerator for ACSC, which achieves maximum speedups of 603 and 2.5 vs. its software counterparts on embedded processor and PC, respectively, without compromising cluster accuracy. No similar FPGA-based ACSC hardware accelerator exists in the literature.
Impact of Structure of Network Based Data on Performance of Graph Neural Networks

Graph neural networks (GNNs) have been widely applied to network related tasks in recent years, including node classification, link prediction, community detection, etc. The core idea of GNNs is neighborhood aggregation where nodes in a network can learn adequate representations by aggregating the information from their neighbors. Despite the great success of GNNs, few studies investigate how different types of structure of the network based data, such as random networks, small-world networks, and scale-free networks, affect the performance of GNNs in completing network related tasks. Moreover, recent studies have pointed out that the homophily of labels is one of the key properties that influence the performance of GNNs. In this work, we study the performance of GNNs for different types of network structure at different homophily levels. Comprehensive simulations on synthetic networks show the considerable impact of network structure and homophily on the performance of GNNs in terms of prediction effectiveness in node classification tasks. The findings of this work emphasize the necessary consideration of network structure of datasets in designing reliable GNNs so that the performance of these GNNs will not deviate due to structural change of the underlined data.
PhotoSaver: Group Photographing Guidance System Using Multi-Task Cascaded Convolutional Networks

This paper illustrates a group photographing guidance system that enables to detect the eyes if closed and the face if occluded by another subject in group photo. To consider the practical issue, the proposed auxiliary system is designed to remind the photographer when any face of subject is occluded, or eyes closed. We perform eyes-closed detection on every detected face region. If the eyes of subject were closed during the shot, system will notice the photographer automatically. In this study, the Multi-task Cascaded Convolutional Networks (MTCNN) is applied for face detection. MTCNN is efficient for the group photo with a large amount subject. Compared with media-pipe contributed by Google, the number of human and bounding box detected by MTCNN is more accurate and complete. For eyes detection, a simple convolution neural network is used. In the experiments, we demonstrated that the results well-performed in terms of the occluded ratio of every covered face as well as whose eyes are closed.
Efficient Implementation of Activation Function on FPGA for Accelerating Neural Networks

In this paper, we present the Integer Lightweight Softmax (ILS) algorithm for approximating the Softmax activation function. The accurate implementation of Softmax on FPGA can be huge resource-intensive and memory-hungry. Then, we present the implementation of ILS on a Xilinx XCKU040 FPGA to evaluate the effectiveness of ILS. Evaluations on CIFAR 10, CIFAR 100 and ImageNet show that ILS achieves up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.47\times, 40\times$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$323\times$</tex> speedup over CPU implementation, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times, 63\times$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$51\times$</tex> speedup over GPU implementation, respectively. In comparison to previous FPGA-based Softmax implementations, ILS strikes a better balance between resource consumption and precision accuracy.
Cascade-LogoNet: Eliminating Classification Ambiguity with Cascaded Logo Detection

Due to a large number of brand logos and similar text appearances, existing deep detection networks are prone to generating multiple overlapping logos at a single location. In this paper, we propose a two-stage approach, Cascade-LogoNet, by adding a verification stage to eliminate the classification ambiguity. We group overlapping logo proposals and verify the class predictions inside each group by learning more discriminative features with strong inter-class discrepancy. We also design a lightweight detector to improve computational efficiency and prevent over-fitting given limited training data. In addition, we propose a new data augmentation strategy, named small logo preserving stitching (SLPS), to improve the detection accuracy of small logos. When stitching training images to increase the loss ratio of small logos, we keep the original small logos on the stitched image to avoid extremely undistinguishable small ones. Our Cascade-LogoNet achieves 63.5 mAP and 64.4 mAP on the dataset QMUL-OpenLogo [1] when using ResNet-50 and ResNet-50-DCN [2] as backbone respectively, which surpasses previous methods by a large margin.
Improved Chroma From Luma Intra Prediction Mode Beyond AV1

In AV1, Chroma from Luma (CfL) intra prediction mode is adopted to predict chroma samples by exploiting the linear correlation between the co-located samples of luma and chroma components, wherein the scaling factor of the linear model is transmitted to the decoder side and the offset factor is derived as the average of neighboring chroma pixels. In this paper, the CfL prediction mode is improved in following three aspects. Firstly, the calculation of DC contribution between luma and chroma is aligned to improve the accuracy of CfL prediction. Secondly, to further enhance the CfL prediction mode, a new cross-component intra prediction mode without signaling of scaling factor is employed. Thirdly, the down-sampling filter for CfL mode is adaptively selected at the encoder side for each video sequence. Simulation results show that, on top of AOMedia Video Model (AVM) v3.0.0, an average coding gain of 0.9%, 0.5%, and 0.4% in terms of YUV-PNSR is achieved for all intra, random access, and low delay configurations, respectively.
Padding-Aware Learned Image Compression

For current learned image compression methods, padding input images is necessary to meet the resolution requirements of down-sampling layers. However, the impact of padding has not been studied thoroughly. Most previous studies ignore padded images in the training process. In this paper, we analyze the impact of padding on compression performance. Then, we propose a padding-aware training (PAT) strategy, handling the padding effect during the training. Specifically, our PAT strategy calculates the loss of pre-padding image through a masking operation. Finally, according to our systematic experimental results, we find that images with different resolutions tend to favor different padding modes. Therefore, we further propose to conduct padding mode decision in the encoding process for rate-distortion optimization. Experiments demonstrate that our proposed PAT strategy and padding mode decision effectively compensate for the performance drop caused by padding.
Streaming phishing scam detection method on Ethereum

Phishing is a widespread scam activity on Ethereum, causing huge financial losses to victims. Most existing phishing scam detection methods abstract accounts on Ethereum as nodes and transactions as edges, then use manual statistics of static node features to obtain node embedding and finally identify phishing scams through classification models. However, these methods can not dynamically learn new Ethereum transactions. Since the phishing scams finished in a short time, a method that can detect phishing scams in real-time is needed. In this paper, we propose a streaming phishing scam detection method. To achieve streaming detection and capture the dynamic changes of Ethereum transactions, we first abstract transactions into edge features instead of node features, and then design a broadcast mechanism and a storage module, which integrate historical transaction information and neighbor transaction information to strengthen the node embedding. Finally, the node embedding can be learned from the storage module and the previous node embedding. Experimental results show that our method achieves decent performance on the Ethereum phishing scam detection task.
Zero-LEINR: Zero-Reference Low-light Image Enhancement with Intrinsic Noise Reduction

Zero-reference deep learning-based methods for low-light image enhancement sufficiently mitigate the difficulty of paired data collection while keeping the great generalization on various lighting conditions. However, color bias and unin-tended intrinsic noise amplification are still issues that remain unsolved. This paper proposes a zero-reference end-to-end two-stage network (Zero-LEINR) for low-light image enhancement with intrinsic noise reduction. In the first stage, we introduce a Color Preservation and Light Enhancement Block (CPLEB) that consists of a dual branch structure with different constraints to correct the brightness and preserve the correct color tone. In the second stage, Enhanced-Noise Reduction Block (ENRB) is applied to remove the intrinsic noises being enhanced during the first stage. Due to the zero-reference two-stage structure, our method is generalized to enhance low-light images with correct color tone on unseen datasets and reduce the intrinsic noise simultaneously.
A Scalable RDMA Network Interface Card with Efficient Cache Management

Remote Direct Memory Access (RDMA) has been applied in large-scale clusters due to its high bandwidth and low latency features in recent decades. However, the scalability issue is a known intractable problem that the current RDMA Network Interface Card (RNIC) cannot overcome as the number of connections increases to thousands. The key to the scalability bottleneck is managing the connection information cached on the RNIC. To solve the scalability problem, firstly, we test and analyze the behavior of the commercial RNIC when the network performance declines in the case of large-scale connections. Further, we give the performance model of RNIC and point out that the cache design is the key to scalability issues. Then, we propose a Scalable RDMA NIC (ScalaRNIC) architecture with a non-blocking and priority-programmable cache design. Besides, our cache design supports parametric configuration by the extended API. ScalaRNIC can maintain <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{a}\approx 100\%$</tex> cache hit ratio for higher priority connections and keep message rates nearly equal to peak performance. In contrast, commercial RNIC's performance drops by 47% when there are a few thousand connections.
Physical Computing for Hopfield Networks on a Reconfigurable Analog IC

This paper discusses physical computing for solving optimization problems using a Hopfield network built on a Field Programmable Analog Array (FPAA). A core Hopfield circuit is presented that uses a programmable Vector-Matrix-Multiply (VMM) and Transconductance Amplifier (TA). The circuit dynamics of the VMM and effects of mismatch are discussed. The analog Hopfield network is evaluated by inputting a graph to the network and solving the NP-hard max-cut problem. Experimental results show convergence time in the order of microseconds towards a optimal solution on a four and ten node graph.
Information-Theoretic Perspective to Thermal Covert Channels

Covert communication channels are a significant security threat where the host computer's security policy is bypassed to establish a communication link that can leak sensitive data. Establishing thermal covert channels is feasible because modern processors have accessible temperature sensors that are typically used for dynamic thermal management. In this paper, we first provide an information-theoretic discussion on thermal cover channels and important characteristics such as channel capacity and data modulation methods. Next, we summarize existing thermal covert channel detection methods, including their limitations. We then propose a novel runtime detection method for thermal covert channels where the secret data is encoded via low power programs. Our results demonstrate that the proposed technique can achieve 100% detection accuracy with 0% false positive rate.
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs

We present a side-channel attack (SCA) resistant asynchronous-logic (async-logic) AES accelerator that integrates synchronous-logic (sync-logic) Block RAMs (BRAMs) in FPGA as the Substitution-Box. We successfully identify the timing requirements to integrate sync-logic BRAMs in our async-logic AES accelerator and validate our proposed AES accelerator on the Sakura-X FPGA board. With the integration of BRAMs, we improve the resource utilization on FPGA by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.6\times$</tex> when compared to the state-of-the-art async-logic AES accelerator, while reducing the power overhead by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.4\times$</tex> . We comprehensively evaluate the SCA resistance of our proposed async-logic AES accelerator with 11 attacking models in both time and frequency domains. Based on our evaluations, we show that our proposed async-logic AES accelerator is highly secure against SCA with 30 million EM traces. This is more than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6000\times$</tex> improvement when compared to the benchmark sync-logic AES accelerator and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.5\times$</tex> improvement when compared to the state-of-the-art async-logic AES accelerator.
Unified Accelerator for Attention and Convolution in Inference Based on FPGA

Many models combining Transformers with convolutional neural networks (CNNs) for computer vision tasks have achieved state-of-the-art results. However, due to the different computation patterns between attention and convolution, using a dedicated Transformer or CNN accelerator will inevitably reduce the computing efficiency of the other. To overcome this problem, we propose a unified architecture for attention and convolution on FPGA. We reduce runtime overhead by offloading part of self-attention computations offline before inference. Furthermore, we present a unified mapping method according to the computing characteristics of attention-based and convolution-based models. This accelerator implements multi-head attention in Transformer, independent ResNet-50 and hybrid blocks of attention and con-volution in BoTNet-50 at 200MHz on Xilinx Virtex Ultrascale+ XCVU37P. Experimental results show that the solution is nearly 3.62 times more energy-efficient than the NVIDIA V100 GPU, and the computational efficiency is 11.86% and 28.29% higher than the state-of-the-art Transformer and ResNet-50 accelerators, respectively.
More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers

We present a training tool flow for deep neural networks (DNN) optimized for a hardware-efficient FPGA-implementation based on reconfigurable constant-coefficient multipliers (RCCMs). RCCMs replace the costly generic multipliers by shift-and-add operations. In previous work, it was shown that RCCMs offer a better alternative for saving FPGA area than utilizing low-precision arithmetic. This work proposes an improved tool flow that enables layer-wise weight quantization, a larger search space by additional RCCM coefficient sets and an optimized retraining. This leads to an improved accuracy compared to the previous method. In addition, hardware requirements are lower as only 1 to 3 adders per multiplication are used. This reduces the overall complexity and the required memory bandwidth simultaneously. We evaluate our tool flow using multiple networks (ResNets) on the ImageNet data set.