Reviewerly/exHarmony huggingface dataset:
SAT-Based Quantum Circuit Adaptation

As the nascent field of quantum computing develops, an increasing number of quantum hardware modalities, such as superconducting electronic circuits, semiconducting spins, trapped ions, and neutral atoms, have become available for performing quantum computations. These quantum hardware modalities exhibit varying characteristics and implement different universal quantum gate sets that may e.g. contain several distinct two-qubit quantum gates. Adapting a quantum circuit from a, possibly hardware-agnostic, universal quantum gate set to the quantum gate set of a target hardware modality has a crucial impact on the fidelity and duration of the intended quantum computation. However, current quantum circuit adaptation techniques only apply a specific decomposition or allow only for local improvements to the target quantum circuit potentially resulting in a quantum computation with less fidelity or more qubit idle time than necessary. These issues are further aggravated by the multiple options of hardware-native quantum gates rendering multiple universal quantum gates sets accessible to a hardware modality. In this work, we developed a satisfiability modulo theories model that determines an optimized quantum circuit adaptation given a set of allowed substitutions and decompositions, a target hardware modality and the quantum circuit to be adapted. We further discuss the physics of the semiconducting spins hardware modality, show possible implementations of distinct two-qubit quantum gates, and evaluate the developed model on the semiconducting spins hardware modality. Using the developed quantum circuit adaptation method on a noisy simulator, we show the Hellinger fidelity could be improved by up to 40 % and the qubit idle time could be decreased by up to 87 % compared to alternative quantum circuit adaptation techniques.
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers

After the success of the transformer networks on natural language processing (NLP), the application of transformers to computer vision has followed suit to deliver unprecedented performance gains on vision tasks including image recognition and object detection. The multi-head self-attention (MSA) is the key component in transformers, allowing the models to learn the amount of attention paid to each input position. In particular, hierarchical vision transformers (HVTs) utilize window-based MSA to capture the benefits of the attention mechanism at various scales for further accuracy enhancements. Despite its strong modeling capability, MSA involves complex operations that make transformers prohibitively costly for hardware deployment. Existing hardware accelerators have mainly focused on the MSA workloads in NLP applications, but HVTs involve different parameter dimensions, input sizes, and data reuse opportunities. Therefore, we design the RAWAtten architecture to target the window-based MSA workloads in HVT models. Each w-core in RAWAtten contains near-memory compute engines for linear layers, MAC arrays for intermediate matrix multiplications, and a lightweight reconfigurable softmax. The w-cores can be combined at runtime to perform hierarchical processing to accommodate varying model parameters. Compared to the baseline GPU, RAWAtten at 40nm provides 2.4x average speedup for running the window-MSA workloads in Swin transformer models while consuming only a fraction of GPU power. In addition, RAWAtten achieves 2x area efficiency compared to prior ASIC accelerator for window-MSA.
BOMP- NAS: Bayesian Optimization Mixed Precision NAS

Bayesian Optimization Mixed-Precision Neural Architecture Search (BOMP-NAS) is a method to quantizationaware neural architecture search that leverages both Bayesian optimization and mixed-precision quantization to efficiently search for compact, high performance deep neural networks. It is able to find neural networks that achieve state of the art accuracy with less search time. Compared to the closest related work, BOMP-NAS can find these neural networks in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{6}\times$</tex> less search time.
Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive Test

In-memory-computing (IMC) has become an efficient solution for implementing neural networks on hardware. However, IMC platforms request weights in neural networks to be programmed to exact values. This is a very demanding task due to programming complexity, process variations, noise, as well as thermal effects. Accordingly, new methods should be introduced to counter such uncertainties. In this paper, we first discuss a method to train neural networks statistically with process variations modeled as correlated random variables. The statistical effect is incorporated in the cost function during training. Consequently, a neural network after statistical training becomes robust to uncertainties. To deal with variations and noise further, we also introduce a compensation method with extra layers for neural networks. These extra layers are trained offline again after the weights in the original neural network are determined to enhance the inference accuracy. Finally, we will discuss a method for testing the effect of process variations in an optical acceleration platform for neural networks. This optical platform uses Mach-Zehnder Interferometers (MZIs) to implement the multiply-accumulate operations. However, trigonometric functions in the transformation matrix of an MZI make it very sensitive to process variations. To address this problem, we apply a recursive test procedure to determine the properties of MZIs inside an optical acceleration module, so that process variations can be compensated accordingly to maintain the inference accuracy of neural networks.
Evaluation of heterogeneous AIoT Accelerators within VEDLIoT

Within VEDLIoT, a project targeting the development of energy-efficient Deep Learning for distributed AIoT applications, several accelerator platforms based on technologies like CPUs, embedded GPUs, FPGAs, or specialized ASICs are evaluated. The VEDLIoT approach is based on modular and scalable cognitive IoT hardware platforms. Modular microserver technology enables the integration of different, heterogeneous accelerators into one platform. Benchmarking of the different accelerators takes into account performance, energy efficiency and accuracy. The results in this paper provide a solid overview regarding available accelerator solutions and provide guidance for hardware selection for AIoT applications from far edge to cloud. VEDLIoT is an H2020 EU project which started in November 2020. It is currently in an intermediate stage. The focus is on the considerations of the performance and energy efficiency of hardware accelerators. Apart from the hardware and accelerator focus presented in this paper, the project also covers toolchain, security and safety aspects. The resulting technology is tested on a wide range of AIoT applications.
Lightspeed Binary Neural Networks using Optical Phase-Change Materials

This paper investigates the potential of a compute-in-memory core based on optical Phase Change Materials (oPCMs) to speed up and reduce the energy consumption of the Matrix-Matrix-Multiplication operation. The paper also proposes a new data mapping for Binary Neural Networks (BNNs) tailored for our oPCM core. The preliminary results show a significant latency improvement irrespective of the evaluated network structure and size. The improvement varies from network to network and goes up to ~1053x.
SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels

Timing side channels can be inadvertently introduced into processor microarchitecture during the design process, mainly due to optimizations carried out to improve processor performance. These timing side channels have been used in various attacks including transient execution attacks on recent commodity proces-sors. Hence, we need a tool to detect timing side channels during the design process. This paper presents SIGFuzz, a fuzzing-based framework for detecting microarchitectural timing side channels. A designer can use SIGFuzz to detect side channels early in the design flow and mitigate potential vulnerabilities associated with them. SIGFuzz generates a cycle-accurate microarchitectural trace for a program that executes on the target processor, it then uses two trace properties to identify side channels that would have been formed by the program. These two trace properties evaluate the effect of each instruction in the program, on the timing of its prior and later instructions, respectively. SIGFuzz also uses a statistical distribution of execution delays of instructions with the same mnemonic to flag potential side channels that manifest with different operands of an instruction. Furthermore, SIGFuzz automatically groups the detected side channels based on the microarchitectural activity trace (i.e. signature) of the instruction that triggered it. We evaluated SIGFuzz on two real-world open-source processor designs: Rocket and BOOM, and found three new side channels and two known side channels. We present a novel Spectre-style attack on BOOM based on one of the newly detected side channel.
Power data attribution revocation searchable encrypted cloud storage

Grid business data contains a large amount of electricity data customer privacy data, serving more than 1.1 billion people, involving personnel, financial, material, assets and other ten areas of data resources. The existing grid data has the security problem of privacy leakage due to reverse analysis in the process of publishing, and the data permission is difficult to revoke. To address these problems, this paper proposes a CP-ABE (ciphertext policy attribute based encryption) cloud storage scheme with revocable attributes, which can ensure the security of attribute permissions, dynamic change of user attributes and complete protection of user privacy. The paper is based on a subset-covered attribute revocation technique, which generates a corresponding user tree for each user attribute to enable revocation of user attributes without updating the user key after revocation, reducing the corresponding computational overhead. Then, multiple attribute authorisation authorities are used to distribute and manage keys without introducing any other trusted authorities, protecting user privacy and avoiding security issues caused by a single attribute authorisation authority. Finally, a pre-decryption algorithm is designed to reduce the computational overhead of the user when decrypting. The security analysis yields that the scheme has ciphertext privacy and keyword privacy; the performance analysis finds that the scheme has low computation and communication overheads; the experimental analysis reflects that the scheme has low key storage overhead, ciphertext storage overhead and index storage overhead.
A Cross-layer Self-attention Learning Network for Fine-grained Classification

Fine-grained image classification refers to the more fine-grained sub-categories division based on the basic categories that have been divided. It has become a very challenging research task, due to the characteristics of data with large inter-class differences and small intra-class differences. This paper proposes a cross-layer self-attention (CS) network for learning refined discriminative image features across layers. The network consists of a backbone and a cross-layer self-attention module including three submodules, i.e., cross-layer channel attention, cross-layer space attention and feature fusion submodules. Cross-layer channel attention module can bring a channel self-attention by interacting information between low-layer and high-layer in convolutional networks and then load the channel self-attention into low-level to obtain finer low-level features. Cross-layer spatial attention module has similar effect and can obtain finer low level features in the spatial dimension. The feature fusion module fuses low-level features with high-level features where low-level features can be obtained through combining channel and spatial features. The experiments on three benchmark datasets show that the network based on backbone ResNet101 outperform the most mainstream models on the classification accuracy.
Pixel Attention Activation Function for Single Image Super-Resolution

In recent years, the development of deep neural networks leads significant advances in image restoration tasks, especially in image super-resolution. The widely used activation functions in deep super-resolution models like ReLU and MTLU are suboptimal. Both ReLU and MTLU provide static scaling factors for the input image feature. Therefore, in this paper, motivated by the channel attention and spatial attention mechanism, we propose a simple and effective Pixel Attention Activation Function (PAAF) for image super-resolution. Our method provides dynamic element-wise (i.e., spatial-wise and channel-wise) scaling factors for input image features. Our PAAF obtains a specific scaling factor for every single pixel in input features and can capture rich spatial and channel-wise interactions. The experiments on several standard benchmarks demonstrate our proposed method is superior to other activation functions for super-resolution.
LoCoExNet: Low-Cost Early Exit Network for Energy Efficient CNN Accelerator Design

Early exit techniques, where the inference process of convolutional neural networks (CNNs) is early terminated by using auxiliary classifiers (called branches) to reduce data processing energy for easy inputs, have been actively researched. However, the conventional early exit works have suffered from the large size of branches, whose memory access energy is significantly large compared to that of the main network. In this article, we propose a low-cost early exit network (LoCoExNet), which significantly improves energy efficiencies by reducing the parameters used in inference with efficient branch structures. To further reduce the energy consumption of branches, based on the observation that the classification difficulties of the images can be predicted using the magnitudes of input activations, we also propose hardware-friendly dynamic branch pruning (DBP). Given the network and target dataset, we can construct an energy-efficient early exit network through the branch structure determination algorithm and DBP algorithm. Finally, we develop several architectural supporting modules to improve the energy efficiency of the proposed LoCoExNet with DBP. The experimental results show that the LoCoExNet uses 28.7% of the total network parameters on average for Tiny-ImageNet dataset using VGG-16 without accuracy loss. The CNN accelerator that implements LoCoExNet with DBP has been implemented using the 65nm CMOS process. The implementation results show that the LoCoExNet accelerator achieves up to 91% of energy savings and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.46\mathbf {\times }$ </tex-math></inline-formula> of speedups without accuracy loss for CIFAR-10 dataset using VGG-16 compared to the state-of-the-art CNN accelerators.
OTB-AAE: Semi-Supervised Anomaly Detection on Industrial Images Based on Adversarial Autoencoder With Output-Turn-Back Structure

Due to the unbalanced proportion of positive (non-anomalous) and negative (anomalous) samples obtained from industrial data collection, the development prospect of supervised algorithms in industrial field is limited. Recently, Adversarial Autoencoder (AAE) has been used in the field of anomaly detection, and the complexity and unknown of negative samples increase the difficulty of this task. Here we propose an anomaly detection framework based on AAE to capture the normality distribution of high-dimensional images and identify abnormalities in industry. The Output-Turn-Back structure (OTB) is proposed to be added to the AAE structure to improve the discriminant capability of the discriminator. In particular, the L1 loss function and the Structural Similarity (SSIM) loss function are combined to assist the OTB. Then the Squeeze-and-Excitation (SE) model is embedded into AAE to improve the ability to capture the normality distribution of positive samples. The characteristic distribution of the negative and positive samples is different in testing, which leads to the significant reconstruction error of the latent space vector encoding, indicating anomaly. We test the model and compare it with the other models on different datasets, using the existing anomaly detection evaluation indexes to evaluate their performance. Experiments prove the superiority of the proposed method and its unique application prospect.
LARNeXt: End-to-End Lie Algebra Residual Network for Face Recognition

Face recognition has always been courted in computer vision and is especially amenable to situations with significant variations between frontal and profile faces. Traditional techniques make great strides either by synthesizing frontal faces from sizable datasets or by empirical pose invariant learning. In this paper, we propose a completely integrated embedded end-to-end Lie algebra residual architecture (LARNeXt) to achieve pose robust face recognition. First, we explore how the face rotation in the 3D space affects the deep feature generation process of convolutional neural networks (CNNs), and prove that face rotation in the image space is equivalent to an additive residual component in the feature space of CNNs, which is determined solely by the rotation. Second, on the basis of this theoretical finding, we further design three critical subnets to leverage a soft regression subnet with novel multi-fusion attention feature aggregation for efficient pose estimation, a residual subnet for decoding rotation information from input face images, and a gating subnet to learn rotation magnitude for controlling the strength of the residual component that contributes to the feature learning process. Finally, we conduct a large number of ablation experiments, and our quantitative and visualization results both corroborate the credibility of our theory and corresponding network designs. Our comprehensive experimental evaluations on frontal-profile face datasets, general unconstrained face recognition datasets, and industrial-grade tasks demonstrate that our method consistently outperforms the state-of-the-art ones.
Arithmetic Autocorrelation Distribution of Binary <i> <b>m</b> </i>-Sequences

Binary <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> -sequences are those with the largest period <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$n=2^{m}-1$ </tex-math></inline-formula> among the binary sequences produced by linear shift registers with length <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m$ </tex-math></inline-formula> . They have a wide range of applications in communication since they have several desirable pseudorandom properties, such as balance, uniform pattern distribution, and ideal (classical) autocorrelation. In 1967, Mandelbaum introduced a 2-adic version of classical autocorrelation of binary sequences, called arithmetic autocorrelation, in his research on arithmetic codes. Later, Goresky and Klapper generalized this notion to the nonbinary case and got several properties of arithmetic autocorrelation related to linear shift registers with carry. Recently, Z. Chen et al. showed an upper bound on the arithmetic autocorrelation of binary <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> -sequences and raised a conjecture on the absolute value distribution of the arithmetic autocorrelation of binary <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> -sequences. In this paper, we present a general formula for computing arithmetic autocorrelation, from which we completely determine the arithmetic autocorrelation distribution of arbitrary binary <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${m}$ </tex-math></inline-formula> -sequences. In particular, the conjecture raised by Z. Chen et al. is verified.
CMFTC: Cross Modality Fusion Efficient Multitask Encrypt Traffic Classification for Efficient Management of IIoT

Traffic classification, which deduces task-relevant traffic types, is required for network management, security, and quality of service (QoS). In recent studies, deep learning has been used to distinguish encrypted traffic without using handcraft features. However, higher-performance deep learning models often come with a significant computational overhead and parameter count. In this article, we present a novel cross-modal fusion model, CMFTC, which achieves comparable performance to the state-of-the-art (SOTA) model DISTILLER, but with only 18% of its parameters and half the floating-point operations (FLOPs). The CMFTC model is designed to carefully capture the relationship between different modalities and employs a lightweight design for efficient computation. Our model achieves better performance by fusing packet, context, and flow-level modalities. Additionally, we propose a pair of homogeneous student and teacher models with similar architectures, and we adjust the distillation algorithm to improve the student model's inference speed without compromising performance. Our experimental results demonstrate that the proposed model outperforms the current SOTA on several benchmark datasets, including Ton_IoT, IoT-23, ISCX-Tor-2016, ISCX-VPN-2016, and USTC-TFC, with significantly fewer parameters and FLOPs. Furthermore, our model has a better inference speed on real IoT devices, as demonstrated by our experiments.
A Deep Learning-Based No-Reference Quality Metric for High-Definition Images Compressed With HEVC

An accurate no-reference image quality assessment metric for compression artifacts is essential for the broadcasting and streaming industries. Although we have witnessed impressive advances in the capturing, delivery and display technologies, we have not managed to match them with an accurate and perceptual based no-reference image quality metric. In this paper, we propose a unique perceptual based no-reference quality metric for compressed HD frames/images that is based on the DenseNet network architecture. We focus on the effect HEVC (High Efficiency Video Coding) compression artifacts have on the visual quality of a broadcasted and streamed video, as this is a requirement of immense importance for these industries. We chose the Video Multi-Method Assessment Fusion (VMAF) metric as our base measure to map visual quality of HEVC compression artifacts to five visual quality levels. The original VMAF classification was changed to reflect High Definition (HD) resolution images. We trained a DenseNet network to classify compressed images into five visual categories using the dataset generated by the modified VMAF. DenseNet was chosen for its ability to process HD images. Our evaluations have shown that our no-reference metric achieves an impressive average accuracy of 94.13% in classifying the visual quality of compressed images.