Reviewerly/exHarmony huggingface dataset:
Reliability Analysis of Memristive Reservoir Computing Architecture

Neuromorphic computing systems have emerged as powerful computation tools in the field of object recognition and control systems. However, training these systems, which are usually characterized by recurrent connectivity, requires abundant computational resources: memory, computation, data, and time. Reservoir computing (RC) framework reduces this high computational training cost by focusing the training effort on only a small subset of connections thus allowing these systems to be amenable to hardware implementation. Using memristors to construct these reservoir computers reduce the area/power consumption even further. However, the inherent variability of memristors poses specific challenges. Here, we conduct an in-depth reliability analysis of challenges posed by HfO2 memristors, including cycle-to-cycle variability, read/write noise, and conductance drift in the context of RC hardware. We also explore plasticity mechanisms such as Spike-Timing Dependent Plasticity (STDP) within the scope of the spiking recurrent neural networks (SRNN) reservoir and their impact on memristor conductance drift (MCD). We present a chaotic time series prediction task applied to a Python model of the constrained hardware design achieving very low Normalized Root Mean Square Error (NRMSE) of 2 × 10-3. The analog neuron and memristive synapse circuits employed for constructing the SRNN are simulated in Cadence Spectre and the energy consumption for the Mackey-Glass (MG) time-series prediction task was found to be approximately 90 nJ.
TDAG: Tree-based Directed Acyclic Graph Partitioning for Quantum Circuits

We propose the Tree-based Directed Acyclic Graph (TDAG) partitioning for quantum circuits, a novel quantum circuit partitioning method which partitions circuits by viewing them as a series of binary trees and selecting the tree containing the most gates. TDAG produces results of comparable quality (number of partitions) to an existing method called ScanPartitioner (an exhaustive search algorithm) with an 95% average reduction in execution time. Furthermore, TDAG improves compared to a faster partitioning method called QuickPartitioner by 38% in terms of quality of the results with minimal overhead in execution time.
Dynamic Gold Code-Based Chaotic Clock for Cryptographic Designs to Counter Power Analysis Attacks

Research on side-channel attacks has recently made a lot of progress, and one of the most potential solutions is a power analysis attack. Thus, focusing on countermeasures to improve the security level of cryptographic devices is a matter of concern. This paper proposes a time-based hiding countermeasure by using a dynamic Gold code-based chaotic clock. In our work, 36.95% (143 out of 387) of parameter sets that pass two standard statistical test suites can be used to reconfigure the Gold code generator's initial vector. The experimental results demonstrate that our countermeasure helped to harden the targeted Advanced Encryption Standard against several alignment pre-processing methods. When compared to the Random Dynamic Frequency Scaling countermeasure, the number of traces required to reveal the secret key must be increased by three times, but the overhead is approximately four times lower.
Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters

To ensure that accuracy and latency are not compromised while deploying Deep Neural Networks (DNNs) on edge devices, trained DNN models can be partitioned across many collaborating edge devices for inference. However, this collaborative inference paradigm raises new security risks because one of the collaborating edge devices could be malicious or compromised, leading to compromised accuracy and reliability of inference results. To address this challenge, this paper explores the use of low-pass filters to enhance the robustness of Collaborative DNNs. The study deploys a VGG16 network, trained on the German Traffic Sign Recognition Benchmarks (GTSRB) dataset, and a MobileNet network trained on the ImageNet dataset, using two prevalent collaborative inference methodologies. The output feature maps (FMs) of a vulnerable edge device are perturbed using four advanced adversarial noises, namely Speckle, Salt-and-Pepper, Gaussian noise, and the Fast Gradient Signed Method (FGSM). Experimental results demonstrate that implementing low-pass filtering can significantly enhance the robustness of Collaborative DNNs. On average, the top-1 classification accuracy is improved by 2.1x times, making the DNNs more robust to adversarial attacks.
IMA-GNN: In-Memory Acceleration of Centralized and Decentralized Graph Neural Networks at the Edge

In this paper, we propose IMA-GNN as an In-Memory Accelerator for centralized and decentralized Graph Neural Network inference, explore its potential in both settings and provide a guideline for the community targeting flexible and efficient edge computation. Leveraging IMA-GNN, we first model the computation and communication latencies of edge devices. We then present practical case studies on GNN-based taxi demand and supply prediction and also adopt four large graph datasets to quantitatively compare and analyze centralized and decentralized settings. Our cross-layer simulation results demonstrate that on average, IMA-GNN in the centralized setting can obtain ~790x communication speed-up compared to the decentralized GNN setting. However, the decentralized setting performs computation ~1400x faster while reducing the power consumption per device. This further underlines the need for a hybrid semi-decentralized GNN approach.
Optimize the TX Architecture of RDMA NIC for Performance Isolation in the Cloud Environment

Remote Direct Memory Access (RDMA) is a promising technology for achieving low latency and high bandwidth access to remote memory. However, performance interference exists when multiple tenants share an RDMA Network Interface Card (RNIC) in the cloud environment. Although some initial studies have investigated the root cause and possible solutions to RDMA performance interference, there is no research to analyze and solve the performance interference from the RNIC architecture. Compared with the existing software approach, optimizing RNIC architecture can introduce less performance and CPU overhead. This paper addresses performance isolation by modeling, analyzing, and optimizing the transmit-side (TX) RNIC architecture. First, we introduce a baseline TX RNIC architecture to explain the existing performance interference. Then, we propose separate caching and slicing execution to avoid the bandwidth-sensitive tenants affecting latency-sensitive tenants. Later, we add isolated backpressure and adaptive Weighted Round-robin scheduling to ensure the bandwidth-sensitive tenants share the bandwidth equally. Our experiments show that these optimizations achieve near-optimal performance isolation.
High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures

In this paper, we present microring resonator (MRR) based polymorphic E-O circuits and architectures that can be employed for high-speed and energy-efficient non-binary reconfigurable computing. Our polymorphic E-O circuits can be dynamically programmed to implement different logic and arithmetic functions at different times. They can provide compactness and polymorphism to consequently improve operand handling, reduce idle time, and increase amortization of area and static power overheads. When combined with flexible photodetectors with the innate ability to accumulate a high number of optical pulses in situ, our circuits can support energy-efficient processing of data in non-binary formats such as stochastic/unary and high-dimensional reservoir formats. Furthermore, our polymorphic E-O circuits enable configurable E-O computing accelerator architectures for processing binarized and integer quantized convolutional neural networks (CNNs). We compare our designed polymorphic E-O circuits and architectures to several circuits and architectures from prior works in terms of area, latency, and energy consumption.
Multi-Transverse-Mode Silicon Photonics for Quantum Computing

Photonics has been identified as a highly promising platform for optical classical and quantum computing. In the realm of classical computing, the inherent parallelism of optics, as opposed to the sequential operations of electronics, offers significant potential for achieving faster and more energy-efficient computational capabilities. Photonics also represents a highly advantageous option for the pursuit of integrated quantum computing, primarily due to the noise- and decoherence-free nature of single photons. Optical qubits can be effectively generated by encoding single photons in a given degree of freedom, such as polarization, path, or wavelength. Path encoded programmable quantum gates have already been realized in Silicon Photonics (SiPh), a technology platform offering several appealing features such as compatibility with complementary metal oxide semiconductor (CMOS) for high integration density. To achieve a large-scale photonic quantum system, encoding the information on other degrees of freedom, such as polarization and transverse mode, is essential. Here, we present an open access process design kit (PDK) for multi-transverse-mode components compatible with standard 220 nm thick SiPh technology. Then, we discuss the use of the PDK components in developing multi-transverse-mode classic optical computing. We also investigate multiple transverse modes of light for encoding and manipulating information in quantum photonics.
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units

Layer-wise mixed-precision quantization (MPQ) has become prevailing for edge inference since it strikes a better balance between accuracy and efficiency compared to the uniform quantization scheme. Existing MPQ strategies either lacked hardware awareness or incurred huge computation costs, which gated their deployment at the edge. In this work, we propose a novel MPQ search algorithm that obtains an optimal scheme by "sampling" layer-wise sensitivity with respect to a newly proposed metric that incorporates both accuracy and proxy of hardware cost. To further efficiently deploy post-training MPQ on edge chips, we propose to tightly integrate the quantized inference units as part of the processor pipeline through micro-architecture and Instruction Set Architecture (ISA) co-design. Evaluation results show that the proposed search algorithm achieves 3% ~ 11% higher inference accuracy with similar hardware cost compared to the state-of-the-art MPQ strategies. In addition, the tightly integrated MPQ units achieve speedup of 15.13x ~ 29.65x compared to a baseline RISC-V processor.
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning

With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of system and package-level co-design methods make it difficult for the designers to create the optimum design choices. In this research, considering the colossal design space of advanced packaging technologies, resource allocation, and chiplet placement, we design an optimizer that looks for the design choices that maximize the Power, Performance, and Area (PPA) and minimize the cost of the chiplet-based AI accelerator. Inspired by the Bayesian approach for black-box function optimization, our optimizer guides the search space toward global maxima instead of randomly traversing through the search space. We analytically synthesize a dataset from the search space and train an ML model to predict the target value of our defined cost function at the optimizer-suggested points. The optimizer locates the optimum design choices from the specified search space (≥ 1M data points) with minimal iterations (≤ 200 iterations) and trivial run time.
RAGA: Resource-Aware Tree-Splitting for High Performance Knuth-Yao-based Discrete Gaussian Sampling on FPGAs

In this work, we present a high-performance architecture for Discrete Gaussian (DG) sampling used in lattice-based cryptography (LBC) through lookup table (LUT) optimization for the combinational datapath as well as FPGA architecture aware pipelining to reduce resource utilization and decrease latency. The proposed tree-splitting technique translates the discrete distribution generating (DDG) tree for Knuth-Yao-based non-uniform sampling into a LUT-based logic with pipelined architecture. This allows a reduction in the area-time product (ATP) compared to the most efficient current state-of-the-art (SotA) designs for DG sampling with standard deviation, (σ = 3.19/6.15543/8.5) by 96%/14%/56% on Virtex-7/Virtex-6/Artix-7 FPGAs, while running at 709/580/440 MHz, respectively. The simplicity of the translation technique also allows us to automate the design flow, resulting in quick design-space exploration for different DG distributions.
Search Space Reduction for Efficient Quantum Compilation

Quantum computers have demonstrated exponential speedup for certain computational tasks like integer factorization, molecular simulation, and machine learning, compared to the classical computers. One of the most challenging problems in quantum computing is quantum compilation, which involves the translation of a quantum circuit into a representation that adheres to the constraints imposed by the quantum hardware. However, this process of mapping the logical qubits to physical qubits incurs a significantly large search space, which needs to be analyzed to obtain the optimal mapping. A non-optimal mapping or compilation strategy introduces additional hardware overhead, thereby rendering inefficiency. Recently, researchers have proposed a technique to reduce the search space for efficient quantum compilation. However, this approach focuses on a generic solution involving only the physical architecture, and hence, as shown in our paper, often fails to incorporate the optimal solution in the reduced search space. To this end, we propose PERM and SGO (PAS), which, to the best of our knowledge, is the first quantum compilation strategy that facilitates a reduced search space comprising a more optimal solution in terms of additional CNOT gates compared to the existing technique. Our experimental evaluation using the MQT benchmarks demonstrates the efficacy of our approach, which furnishes up to 428x reduction compared to the unoptimized search space, and 57.1x reduction compared to existing research, while providing savings in terms of additional CNOT gates by up to 53.85%.
Enhancing Solver-based Generic Side-Channel Analysis with Machine Learning

Generic side-channel attacks, unlike traditional CPA/DPA which are specialized to individual cryptographic circuits, can take in an arbitrary circuit or its power model and try to learn user-designated secrets from its side-channel traces. In this paper, we explore the use of machine learning in the context of such generic attacks. We discuss and demonstrate the challenges of using end-to-end (trace-to-key) learning on generic circuits with larger key sizes. We instead propose a couple of ways to use machine learning to assist recent pseudo-Boolean solver-based generic attacks and report their effectiveness on FPGA power traces.
Automatic ply detection and finite element model generation for composite laminates

This paper presents a novel methodology to detect and isolate individual ply information contained within a relatively low-resolution cross-section image of thick composite laminate specimens. The proposed method can process laminate sample images and construct detailed geometric models in a fast and automated manner with minimal user interaction. The finite element models can be used directly for structural and strength simulations to analyse the effect of waviness defects. The algorithm processes the greyscale sample image and splits it into multiple slices. The initial starting points for each ply were identified by analysing the pixel brightness of the image. The pixel brightness variation was used to identify the different plies in all image slices and a list of possible ply centreline coordinate is generated. The ply centreline points are grouped and connected by selecting the points with minimal distance to the previous one in the ply. A finite element mesh is created for each ply by creating a boundary at the midpoint between two adjacent plies. The geometric information of the isolated plies is then used to create structured finite element models using an in-house meshing algorithm.
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline

There has been growing interest in improving the BERT inference throughput on resource-constrained edge devices for a satisfactory user experience. One methodology is to employ heterogeneous computing, which utilizes multiple processing elements to accelerate inference. Another methodology is to deploy Neural Architecture Search (NAS) to find optimal solutions in accuracy-throughput design space. In this paper, for the first time, we incorporate NAS with pipelining for BERT models. We show that performing NAS with pipelining achieves on average 53% higher throughput, compared to NAS with a homogeneous system.
Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform

Many deep convolutional neural network (CNN) inference accelerators on the field-programmable gate array (FPGA) platform have been widely adopted due to their low power consumption and high performance. In this paper, we develop the following to improve performance and power efficiency. First, we use a high bandwidth memory (HBM) to expand the bandwidth of data transmission between the off-chip memory and the accelerator. Second, a fully-pipelined manner, which consists of pipelined inter-layer computation and a pipelined computation engine, is implemented to decrease idle time among layers. Third, a multi-core architecture with shared-dual buffers is designed to reduce off-chip memory access and maximize the throughput. We designed the proposed accelerator on the Xilinx Alveo U280 platform with in-depth Verilog HDL instead of high-level synthesis as the previous works and explored the VGG-16 model to verify the system during our experiment. With a similar accelerator architecture, the experimental results demonstrate that the memory bandwidth of HBM is 13.2× better than DDR4. Compared with other accelerators in terms of throughput, our accelerator is 1.9×/1.65×/11.9× better than FPGA+HBM2 based/low batch size (4) GPGPU/low batch size (4) CPU. Compared with the previous DDR+FPGA/DDR+GPGPU/DDR+CPU based accelerators in terms of power efficiency, our proposed system provides 1.4-1.7×/1.7-12.6×/6.6-37.1× improvement with the large-scale CNN model.
Brief Announcement: Regular and Dyck Languages in MPC

Regular languages are some of the most widely studied languages in computer science history. Given a regular language L ⊆ {0, 1} ⋆ and string ω ∈ {0, 1} ⋆, two of the most fundamental regular language problems are recognition, the problem of determining if w is in L, and testing, the problem of determining if w is at most ε-far from L. In this paper we modernize regular language recognition and testing algorithms for the Massively Parallel Computations (MPC) model used everyday in big data engineering. First we give a regular language testing algorithm, which succeeds with high probability using Õ(1 over ε) queries to the input string. Following the testing algorithm, we give a simple dynamic programming solution for regular language recognition. Both algorithms run in constant communication rounds and O(n) total memory in MPC where n is the size of the input.
Strain fields measurement using frequency domain Savitzky–Golay filters in digital image correlation

Abstract Savitzky–Golay (SG) filter is an effective and convenient gradient calculation method employed for full-field strain measurement in digital image correlation (DIC). Currently, the strain field can be conveniently obtained by moving smoothing filtering with SG filters. This is a method of spatial filtering, which offers the advantages of easy implementation and high accuracy. This study proposed a strain calculation method based on frequency domain SG (FD-SG) filtering. Prior to performing FD-SG filtering, data extension operations involving outer-boundary padding and zero-padding were performed on the displacement field data. Similarly, the SG filters template was extended with zero-padding and circularly shift operations. Subsequently, FD-SG filters were generated by applying the fast Fourier transform (FFT) to the expanded SG template. Thereafter, FD-SG filtering was implemented through the multiplication of the displacement in the Fourier-domain by an FD-SG filter. Finally, the strain field was obtained via inverse FFT and valid data interception operation. The simulation and practical experiments confirmed the equivalent accuracy exhibited by FD-SG and spatial domain SG filtering. Thus, the proposed FD-SG filtering method has great potential for real-time strain measurement in DIC.
Classification of Motion Differences While Ascending a Step Caused by Differences of Pants Using Doppler Radars

The application of Doppler radar to classify the motion differences related to the differences of pants is presented. The deep learning of the Doppler radar spectrogram using a convolutional neural network achieved a 90% of the accuracy for the classification of whether the participants wore denim pants or trekking pants while ascending a step.
A Model for Business System Infrastructure’s Vulnerability Assessment

The proposed intelligent management tool is related to the vulnerability assessment of business systems infrastructure. A three-stage infrastructure vulnerability assessment model is considered and proposed. A business system is defined as an organization operating in a competitive market environment. Infrastructure is disclosed as the business system environment that supports the core processes. The problem of accounting for and assessing infrastructure vulnerabilities is solved by developing an intelligent decision support information system. This work contributes to the creation of a learning development environment for mediated domain-specific knowledge acquisition. The knowledge base includes technologies related to information and communication systems for knowledge realization. The main idea is to integrate the requirements of information security audit standards and the concept of organizational performance management.