Reviewerly/exHarmony huggingface dataset:
TBERT: Dynamic BERT Inference with Top-k Based Predictors

Dynamic inference is a compression method that adaptively prunes unimportant components according to the input at the inference stage, which can achieve a better trade-off between computational complexity and model accuracy than static compression methods. However, there are two limitations in previous works. The first one is that they usually need to search the threshold on the evaluation dataset to achieve the target compression ratio, but the search process is non-trivial. The second one is that these methods are unstable. Their performance will be significantly degraded on some datasets, especially when the compression ratio is high. In this paper, we propose TBERT, a simple yet stable dynamic inference method. TBERT utilizes the top-k-based pruning strategy which allows accurate control of the compression ratio. To enable stable end-to-end training of the model, we carefully design the structure of the predictor. Moreover, we propose adding auxiliary classifiers to help the model's training. Experimental results on the GLUE benchmark demonstrate that our method achieves higher performance than previous state-of-the-art methods.
Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack

Electromagnetic fault injection (EMFI) attack has posed serious threats to the security of integrated circuits. Memory storing sensitive codes and data has become the first choice of attacking targets. This work performs a thorough characterization of the induced faults and the associated fault model of EMFI attacks on DRAM. Specifically, we firstly carry out a set of experiments to analyse the sensitivity of various types of memory to EMFI. The analysis shows that DRAM is more sensitive to EMFI than EEPROM, Flash, and SRAM in this experiment. Then, we classify the induced faults in DRAM and formulate the fault models. Finally, we find the underlying reasons that explain the observed fault models by circuit-level simulation of DRAM under EMFI. The in-depth understanding of the fault models will guide design of DRAM against EMFI attacks.
Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project Intermediate stage

OPTIMA is an SME-driven project (intermediate stage) that aims to port and optimize industrial applications and a set of open-source libraries into two novel FPGA-populated HPC systems. Target applications are from the domain of robotics simulation, underground analysis and computational fluid dy-namics (CFD), where data processing is based on differential equations, matrix-matrix and matrix-vector operations. Moreover, the OPTIMA OPen Source (OOPS) library will support basic linear algebraic operations, sparse matrix-vector arithmetic, as well as computer-aided engineering (CAE) solvers. The OPTIMA target platforms are JUMAX, an HPC system that couples an AMD Epyc Server with Maxeler FPGA-based Dataflow Engines (DFEs), and server-class machines with Alveo FPGA cards in-stalled. Experimental results on applications up to now, show that performance on robotic simulation can be enhanced up to 1.2x, CFD calculations up to 4.7x, and BLAS routines up to 7x compared to optimized software implementations from OpenBLAS.
Self-awareness in Cyber-Physical Systems: Recent Developments and Open Challenges

Self-aware computing systems enable computing systems to reflect on their actions and behavior. This becomes even more relevant in Cyber-Physical Systems where computing systems have to control and interact with elements in the real world. This paper reports on recent advances made in computational self-awareness for cyber-physical systems.
Chameleon: Dual Memory Replay for Online Continual Learning on Edge Devices

Once deployed on edge devices, a deep neural network model should dynamically adapt to newly discovered environments and personalize its utility for each user. The system must be capable of continual learning, i.e., learning new information from a temporal stream of data in situ without forgetting pre-viously acquired knowledge. However, the prohibitive intricacies of such a personalized continual learning framework stand at odds with limited compute and storage on edge devices. Existing continual learning methods rely on massive memory storage to preserve the past data while learning from the incoming data stream. We propose Chameleon, a hardware-friendly continual learning framework for user-centric training with dual replay buffers. The proposed strategy leverages the hierarchical memory structure available on most edge devices, introducing a short-term replay store in the on-chip memory and a long-term replay store in the off-chip memory to acquire new information while retaining past knowledge. Extensive experiments on two large-scale continual learning benchmarks demonstrate the efficacy of our proposed method, achieving better or comparable accuracy than existing state-of-the-art techniques while reducing the mem-ory footprint by roughly <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$16\times$</tex> . Our method achieves up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7\times$</tex> speedup and energy efficiency on edge devices such as ZCU102 FPGA, NVIDIA Jetson Nano and Google's EdgeTPU. Our code is available at https://github.com/ecolab-nus/Chameleon.
Table Re-Computation Based Low Entropy Inner Product Masking Scheme

is a popular countermeasure due to its provable security. Table re-computation based Boolean masking (BM) is efficient at small masking share number, and addition chain based inner product masking (IPM) provides higher security order than BM. As a result, the natural question is: can we design a masking scheme that costs close to that of re-computation based BM while providing security comparable to that of addition chain based IPM? In this paper, we propose a table re-computation based IPM scheme that provides 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -order security while being slightly more expensive than table re-computation based BM. Furthermore, we improve the side-channel security of IPM by randomly selecting the parameter <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> from an elaborated low entropy set, which we call low entropy inner product masking (LE-IPM). In an Intel Core i7-4790 CPU and ARM Cortex M4 based MCU for AES, we implemented four masking schemes, namely the addition chain based IPM and table re-computation based BM, IPM, and LE-IPM. Our proposals perform slightly slower (by about 0.8 times) than table re-computation based BM but significantly faster (at least 30 times) than addition chain based IPM. Furthermore, we assess the security of our proposals using a standard method named test vector leakage assessment methodology (TVLA). Our proposals provide the expected security against side-channel attacks according to the evaluation.
Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints

Deep Neural Networks (DNNs) are utilized in a variety of domains, and their computation intensity is stressing embedded devices that comprise limited power budgets. DNN compression has been employed to achieve gains in energy consumption on embedded devices at the cost of accuracy loss. Compression-induced accuracy degradation is addressed through fine-tuning or retraining, which can not always be feasible. Additionally, state-of-art approaches compress DNNs with respect to the average accuracy achieved during inference, which can be a misleading evaluation metric. In this work, we explore more fine-grain properties of DNN inference accuracy, and generate energy-efficient DNNs using signal temporal logic and falsification jointly through pruning and quantization. We offer the ability to control at run-time the quality of the DNN inference, and propose an automated framework that can generate compressed DNNs that satisfy tight fine-grain accuracy requirements. The conducted evaluation on the ImageNet dataset has shown over 30% in energy consumption gains when compared to baseline DNNs.
Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware Implementation

As the number of IoT objects is growing fast, power consumption and security become a major concern in the design of integrated circuits. Lightweight Cryptography (LWC) algorithms aim to secure the communications of these connected objects at the lowest energy impact. To reduce the energy footprint of cryptographic primitives, several LWC hardware implementations embedding hybrid CMOS/MRAM-based cells have been investigated. These architectures use the non-volatile characteristic of MRAM to store data manipulated in the algorithm computation. We provide in this work a security evaluation of a hybrid CMOS/MRAM hardware implementation of the ASCON cipher, a finalist of the National Institute of Standards and Technology LWC contest. We focus on a simulation flow using the current EDA tools capable of carrying out power analysis for side-channel attacks, for the purpose of assessing potential weaknesses of MRAM hybridization. Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) are conducted on the postroute and parasitic annoted netlist of the design. The results show that the hybrid implementation does not significantly lower the security feature compared to a reference CMOS implementation.
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement

Deep neural networks (DNNs) have successfully been applied in many fields in the past decades. However, the in-creasing number of multiply-and-accumulate (MAC) operations in DNNs prevents their application in resource-constrained and resource-varying platforms, e.g., mobile phones and autonomous vehicles. In such platforms, neural networks need to provide ac-ceptable results quickly and the accuracy of the results should be able to be enhanced dynamically according to the computational resources available in the computing system. To address these challenges, we propose a design framework called SteppingNet. SteppingNet constructs a series of sub nets whose accuracy is incrementally enhanced as more MAC operations become avail-able. Therefore, this design allows a trade-off between accuracy and latency. In addition, the larger sub nets in SteppingNet are built upon smaller subnets, so that the results of the latter can directly be reused in the former without recomputation. This property allows SteppingNet to decide on-the-fly whether to enhance the inference accuracy by executing further MAC operations. Experimental results demonstrate that SteppingNet provides an effective incremental accuracy improvement and its inference accuracy consistently outperforms the state-of-the-art work under the same limit of computational resources.
EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI

In this paper, we propose a multi-dimensional pruning framework, EMNAPE, to jointly prune the three dimensions (depth, width, and resolution) of convolutional neural networks (CNNs) for better execution efficiency on embedded hardware. In EMNAPE, we introduce a two-stage evaluation strategy to evaluate the importance of each pruning unit and identify the computational redundancy in the three dimensions. Based on the evaluation strategy, we further present a heuristic pruning algorithm to progressively prune redundant units from the three dimensions for better accuracy and efficiency. Experiments demonstrate the superiority of EMNAPE over existing methods.
Efficient Software Masking of AES through Instruction Set Extensions

Masking is a well-studied countermeasure to protect software implementations against side-channel attacks. For the case of AES, incorporating masking often requires to implement internal transformations using finite field arithmetic. This results in significant performance overheads, mostly due to finite field multiplications, which are even worsened when no lookup tables are used. In this work, we extend a RISC-V core with custom instructions to accelerate AES finite field arithmetic. With a 3.3 % area increase, we measure 7.2x and S.4x speed up over software-only implementations of first-order Boolean Masking and Inner Product Masking, respectively. We also investigate vectorized instructions capable of exploiting the intra-block and inter-block parallelism in the implementation. Our implementations avoid the use of lookup tables, run in constant time, and show no evidence of first-order leakage when evaluated on an FPG A.
A Decentralized Frontier Queue for Improving Scalability of Breadth-First-Search on GPUs

Breath-first-search (BFS) algorithm is the fundamen-tal building block of broad applications from the electronic design automation (EDA) field to social network analysis. With the targeting data set size growing considerable, researchers have turned to developing parallel BFS (PBFS) algorithms and accelerating them with graph processing units (GPUs). The frontier queue, the core idea among state-of-the-art designs of PBFS, opens the door to neighbor visiting parallelism. However, the traditional centralized frontier queue in PBFS suffers from a dramatic collision and explosive growth of memory space when excessive threads simultaneously operate on it. Therefore, we identify the challenges of current frontier queue implementations. To solve these challenges, we proposed the decentralized frontier queue (DFQ), which separates a centralized queue into multiple tiny sub-queues for scattering the atomic operation collision on these queues. We also developed the novel overflow-free enqueue and asynchronous sub-queue drain methods to avoid dramatic growing size of the frontier queue and the overflow issue on the naive sub-queue design. In our experiments, we showed that our design could have better scalability and grain averagely 1.04x speedup on the execution in the selected benchmark suit with considerable memory space efficiency.
Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision

It is difficult to employ transformer models for computer vision in mobile devices due to their memory- and computation-intensive properties. Accordingly, there is ongoing research on various methods for compressing transformer models, such as pruning. However, general computing platforms such as central processing units (CPUs) and graphics processing units (GPUs) are not energy-efficient to accelerate the pruned model due to their structured sparsity. This paper proposes a low-power accelerator for transformers with various sizes of structured sparsity induced by pruning with different granularity. In this study, we can accelerate a transformer that has been pruned in a head-wise, line-wise, or block-wise manner. We developed a head scheduling algorithm to support head-wise skip operations and resolve the processing engine (PE) load imbalance problem caused by different number of operations in one head. Moreover, we implemented a sparse general matrix-to-matrix multiplication (sparse GEMM) module that supports line-wise and block-wise skipping. As a result, when compared with a mobile GPU and mobile CPU respectively, our proposed accelerator achieved <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6.1\times$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$13.6\times$</tex> improvements in energy efficiency for the detection transformer (DETR) model and achieved approximately <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.6\times$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7.9\times$</tex> improvements in the energy efficiency on average for the vision transformer (ViT) models.
UVMMU: Hardware-Offloaded Page Migration for Heterogeneous Computing

In a heterogeneous computing system with multiple memories, placing data near its current processing unit and migrating data over time can significantly improve performance. GPU vendors have introduced Unified Memory (UM) to automate data migrations between CPU and GPU memories and support memory over-subscription. Although UM improves software programmability, it can incur high costs due to its software-based migration. We propose a novel architecture to offload the migration to hardware and minimize UM overheads. Unified Virtual Memory Management Unit (UVMMU) detects access to remote memories and migrates pages without software intervention. By replacing page faults and software handling with hardware offloading, UVMMU can reduce the page migration latency to a few <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu s$</tex> . Our evaluation shows that UVMMU can achieve 1.59× and 2.40× speed-ups over the state-of-the-art UM solutions for no over-subscription and 150% over-subscription, respectively.
Machine Vision and Artificial Intelligence in Robotics for Smart Factory

In this work, we have illustrated how machine vision and artificial intelligence could enhance operations in a smart factory along with a robot via several use cases. The first use case is to teach the robots with a leap motion sensor. In Industry 4.0 environment, the intelligent factories decide the subsequent actions based on the sensor data. The leap motion sensor can control a robot’s movements and is beneficial, particularly in smart factory environments. We have demonstrated how a leap motion sensor could control picking and dropping off cylindrical objects. The second use case is to control a robot using a mouse and how the robot could play chess. For this use case, we taught the robot to grip a chess object and put it in the designated place. Similarly, we also use a machine vision camera for detecting several entities, such as wingnuts and bolts. The TensorFlow algorithm has been utilized for detecting different shapes and colors.
Performance Evaluation of Deep Learning Models for Breast Cancer Classification

Globally, breast carcinoma is the most prevalent type of cancer, causing almost nine hundred thousand deaths yearly. It is possible to reduce the fatality rate if the disease is detected at an early stage and appropriately diagnosed. Early diagnosis may prevent it from dissemination and prevent premature casualties from contracting it. Breast cancer (BC) researchers encounter several challenges when trying to distinguish benign from malignant tumours and when trying to draw conclusions about mild and advanced cancer. Through the use of machine learning algorithms, all tumours can be identified using algorithms that can locate and recognize patterns. Most patients with breast cancer die from improper diagnosis and treatment every year. Deep learning algorithms have proven quite effective in the detection of breast cancer in recent years. However, there remains considerable scope for improving these techniques. Despite considerable advancements, the use of deep learning methods, specifically in the context of machine learning, can further enhance their efficiency. In this paper, we compared three different models on the BreakHis dataset, which is openly available, and we demonstrated effecienctv2 accurate classification among all. It achieved an accuracy of 99% and 98% for training and validation, respectively.
Enhanced Model for Data Security in Cyber Space Using Combined Steganographic and Encryption Techniques

In today’s digital reality, transmitting data over an insecure channel is a major concern due to intruders actively expanding across the internet. Security measures must be implemented to prevent sensitive data theft, and encryption is a widely used strategy. While steganography and cryptography are two well-known encryption methods, they are more effective when used together. This article proposes an enhanced model for double encryption of steganographic data. Sensical, nonsensical, and suspicious images can be filtered using advanced artificial intelligence systems, and hidden data can be decrypted through image saturation and segmentation techniques. The proposed model reads pixels and changes the last bit of each character by embedding secret data and creating a sensical, nonsuspicious, and trustworthy encrypted image. This model follows the LSB model and uses the symmetric-key encryption method. The resulting image is indistinguishable from an unencrypted steganographic photo, even to the human eye, and is not recognizable by a computer without a stego-image for comparison. The encrypted data remains unreadable, even after applying image saturation or data extraction techniques.
Research on Byzantine Fault Tolerant algorithm based on Node Weights

In order to solve the problems of low consensus efficiency and slow query speed of PBFT consensus algorithm in alliance chain, a Byzantine Fault Tolerance based on Node Weights (NW-BFT) algorithm is proposed. NW-BFT algorithm measures node weight by using ledger model to record the historical online time and workload of nodes. To solve the problem of lack of reliable time source, the algorithm uses node history proof to verify the online time of nodes, so as to provide consistent verifiable time interval data for the network. Set the decentralization mechanism to select the subLeader to ensure the effectiveness of view change protocol. The experiment shows that NW-BFT is better than PBFT and TWV in efficiency and safety.
Classification of images using Extreme Learning Machine and Regularization Extreme learning Machine (ELM) with the leave-one-out cross validation

Image classification is an essential task, which can be considered as a central point to handle image datasets for improving the accuracy of image retrieval. Traditional image classification methods commonly utilize Support Vector Machines (SVM) as image classifiers. On the other hand, there are several disadvantages of using SVM, such as the high computational cost and large number of parameters to be optimized. In this paper we propose an Extreme Learning Machine (ELM) based regularized extreme learning machine with leave-one-out (RELM-LOO) to improve the accuracy of classification using Mammographic Image Analysis Society (MIAS) mammography breast cancer images and USPS digits datasets. The leave-one-out cross validation LOO approach to optimize the regularization parameter of ELM and accordingly the best classification hyperplane is attained. Experiments on the widely used MIAS breast cancer mammography datasets and USPS digits database images demonstrate that our approach can effectively improve the accuracy of image classification and achieve performance at extremely high speed. There are no works where such modification is applied to mammography breast cancer images. Results obtained in terms of classification accuracy and training time compared to the original ELM and regularized ELM using LOO With USPS digits dataset, it achieved 89.23% in Extreme Learning Machine, 94.18% in Artificial Neural Network ANN-Adam and 94.47% in regularized ELM via leave-one-out (RELM-LOO). Further improved accuracy and reduced computational complexity.
A Self-Attention based Network for Low Resolution Multi-View Stereo

We present SA-MVSNet, a novel two-stage multi-view stereo network equipped with self-attention mechanism, which can improve the quality of low-resolution image 3D reconstruction. SA-MVSNet consists of two stages, and the lower resolution depth maps predicted in the first stage provide a priori information for the second stage. To increase the utilization of image information, a pyramid scheme was used to fuse the feature maps at different resolutions. Moreover, we introduce an improved self-attention module in the first stage to improve reconstruction accuracy by learning the long-term dependence information of feature maps. The experiments on the DTU dataset show a promising result in both completeness and accuracy metrics of the 3D scene reconstructed by the proposed method.