Reviewerly/exHarmony huggingface dataset:
SuperCut

The parallel execution of many graph algorithms is frequently dominated by data communication overheads between compute nodes. This bottleneck becomes even more pronounced in Near-Memory Processing (NMP) architectures with multiple memory cubes as local memory accesses are less expensive. Existing near-memory architectures typically use graph partitioning methods with a fixed vertex assignment, which limits their potential to improve performance and reduce energy consumption. Here, we argue that an NMP-based graph processing system should also consider the distribution of vertices onto memory cubes. We propose SuperCut, a framework for near-memory architectures to effectively reduce communication overheads while maintaining computational balance. We evaluate SuperCut via architectural simulation with 6 real-world datasets and 4 representative applications. The results show that it provides up to 1.8x total energy reduction and 2.6x speedup relative to current state-of-the-art approaches.
An FPGA Implementation of SipHash

Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, cryptographic hashing can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements. As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function. Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture’s throughput and acceleration vs. software were measured on Xilinx’s Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes. These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can exceed 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks. A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.
Can hierarchical client clustering mitigate the data heterogeneity effect in federated learning?

Federated learning (FL) was proposed for training a deep neural network model using millions of user data. The technique has attracted considerable attention owing to its privacy-preserving characteristic. However, two major challenges exist. The first is the limitation of simultaneously participating clients. If the number of clients increases, the single parameter server easily becomes a bottleneck and is prone to have stragglers. The second is data heterogeneity, which adversely affects the accuracy of the global model. Because data should remain at user devices to preserve privacy, we cannot use data shuffling, which is used to homogenize training data in traditional distributed deep learning. We propose a client clustering and model aggregation method, CCFed, to increase the number of simultaneously participating clients and mitigate the data heterogeneity problem. CCFed improves the learning performance using set partition modeling to let data be evenly distributed between clusters and mitigate the effect of a non-IID environment. Experiments show that we can achieve a 2.7-14% higher accuracy using CCFed compared with FedAvg, where CCFed requires approximately 50% less number of rounds compared with FedAvg training on benchmark datasets.
FlexSEE

In this paper, we present a comprehensive security architecture, Flexible Secure Execution Environment (FlexSEE), for confidential computing in modern cloud environments. FlexSEE does not require the trust of system software on the compute server and guarantees that the user data is visible only in non-privileged mode to a designated program trusted by the data owner on a designated hardware, thus protecting the data from an untrusted hardware, hypervisor, OS, or other users' applications, on the compute server.
Maximum Clique Enumeration on the GPU

We present an iterative breadth-first approach to maximum clique enumeration on the GPU. The memory required to store all of the intermediate clique candidates poses a significant challenge. To mitigate this issue, we employ a variety of strategies to prune away non-maximum candidates and present a thorough examination of the performance and memory benefits of each of these options. We also explore a windowing strategy as a middle-ground between breadth-first and depth-first approaches, and investigate the resulting tradeoff between parallel efficiency and memory usage. Our results demonstrate that when we are able to manage the memory requirements, our approach achieves high throughput for large graphs indicating this approach is a good choice for GPU performance. We demonstrate an average speedup of 1. 9x over previous parallel work, and obtain our best performance on graphs with low average degree.
SAT-MapIt

The need for low power and high performance architectures - that can efficiently handle compute-intensive tasks while working with tight power and resource constraints - has been steadily rising due to the constant growth of computational demands in everyday applications.
A Domain-Specific Language for Reconfigurable, Distributed Software Architecture

A program’s architecture—how it organizes the invocation of application-specific logic—influences important program characteristics including its scalability and security. Architecture details are usually expressed in the same programming language as the rest of a program, and can be difficult to distinguish from non-architecture code. And once defined, architecture is difficult and risky to change because it couples tightly with application logic over time.We introduce C-Saw: an approach to express a software’s architecture using a new embedded domain-specific language (EDSL) designed for that purpose. It decouples application-specific logic from architecture, making it easier to identify architectural details of software. C-Saw leverages three ideas: (i) introducing a new, formally-specified EDSL to separate an application’s architecture description from its programming language; (ii) reducing architecture implementation to the definition and management of distributed key-value tables, and (iii) introducing an expressive state-management abstraction for distributed applications.We describe a prototype implementation of C-Saw for C programs and use it to build end-to-end examples of expressing and changing the architecture of widely-used, third-party software. We evaluate this on Redis, cURL, and Suricata and find that C-Saw provides expressiveness and reusability, requires fewer lines of code when compared to directly using C to express architectural patterns, and imposes low performance overhead on typical workloads.
Application-specific FPGAs: cryptographic agility through customized reconfigurable architectures

Cryptography is an important feature in modern devices, especially in Internet-of-Things (IoT) networks. When a deployed cryptographic algorithm is not secure anymore, then devices that use it are immediately vulnerable to attacks and secret information can be exposed or devices themselves could be compromised. Because of the widespread need of cryptography, several application domains would certainly benefit from the use a small embedded Field-Programmable Gate Array (eFPGA) for cryptography. To this end, Mentens et al. proposed an eFPGA tailored towards symmetric-key algorithms and designed to be more resource-efficient than general-purpose Lookup Table (LUT) based FPGA structures for the configuration of symmetric-key algorithms, while showing a similar performance.In this paper, we extend that earlier work (that was mostly focused on the architectural aspect of the eFPGA) and we complete it considering also the routing overhead of the proposed solution. We use an open-source design flow to estimate the potential of cryptography-tailored eFPGA structures and compare them with classical LUT-based FPGAs. With our design flow, that we describe in details in the paper, we are able to precisely estimate the overhead due to the routing. Our results confirm that for symmetric ciphers, just like for many other applications, the routing overhead is predominant. The methodology we followed for estimation and the precise estimation of the routing overhead that we provide are a fundamental information for the future exploration of cryptography-tailored eFPGAs.
Designing Secure Performance Metrics for Last Level Cache

In modern CPU architectures, last level caches (LLC) are typically shared among multiple CPU cores. LLCs enable data sharing across application threads and promote data re-usability. However, due to limited resources, an efficient utilization of LLCs is vital for application performance. One effective way to understand the LLC usage is using hardware performance counters to measure the LLC performance metrics such as hit and miss ratios.Given the benefits of hardware counter based performance metrics, enabling these metrics in a multi-tenant environment is challenging due to security implications. An adversary can exploit these metrics for various side-channel attacks. Current mitigation policies simply restrict the access of performance metrics which limits the legitimate use of these metrics for performance monitoring and optimization. This paper addresses the vulnerability of LLC metrics as an accessory to side-channel attacks.This paper proposes novel secure performance metrics, CER-BERUS, aimed at limiting LLC performance counter-based side-channel vulnerability while providing usable performance insights. The key insight in CERBERUS is that it leverages a differentially private mechanism to make the side-channels undetectable to adversaries. Through a systematic evaluation of benchmark performance monitoring scenarios, we show that CERBERUS’s performance metrics are usable for LLC-aware profile-guided compiler optimization.
Optimizing Irregular Dense Operators of Heterogeneous GNN Models on GPU

GNN models on heterogeneous graphs have achieved state-of-the-art (SOTA) performance in various graph tasks such as link prediction and node classification. Despite their success in providing SOTA results, popular GNN libraries, such as PyG and DGL, fail to provide fast and efficient solutions for heterogeneous GNN models. One common key bottlenecks of models like RGAT, RGCN, and HGT is relation-specific linear projection. In this paper, we propose two high-performing tensor operators: gather-mm and segment-mm to address the issue. We demonstrate the effectiveness of the proposed operators in training two popular heterogeneous GNN models – RGCN and HGT. Our proposed approaches outperform the full-batch training time of RGCN by up to 3× and mini-batch by up to 2×.
Inverse Quantum Fourier Transform Inspired Algorithm for Unsupervised Image Segmentation

Image segmentation is a very popular and important task in computer vision. In this paper, inverse quantum Fourier transform (IQFT) for image segmentation has been explored and a novel IQFT-inspired algorithm is proposed and implemented by leveraging the underlying mathematical structure of the IQFT. Specifically, the proposed method takes advantage of the phase information of the pixels in the image by encoding the pixels’ intensity into qubit relative phases and applying IQFT to classify the pixels into different segments automatically and efficiently. To the best of our knowledge, this is the first attempt of using IQFT for unsupervised image segmentation. The proposed method has low computational cost comparing to the deep learning based methods and more importantly it does not require training, thus make it suitable for real-time applications. The performance of the proposed method is compared with K-means and Otsu-thresholding. The proposed method outperforms both of them on the PASCAL VOC 2012 segmentation benchmark and the xVIEW2 challenge dataset by as much as 50% in terms of mean Intersection-Over-Union (mIOU).
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs

High performance and on-time calculations of Machine Learning (ML) algorithms are essential for emerging technologies such as autonomous driving, Internet of Things (IoT) or edge computing. One of the major algorithms used in such systems is Convolutional Neural Networks (CNNs), which require high computational resources. That leads designers to leverage ML accelerators like GPGPUs to meet design constraints. However, selecting the most appropriate accelerator requires Design Space Exploration (DSE), which is usually time-consuming and needs high manual effort. In this paper, we present a novel automated approach, enabling designers to fast and accurately estimate the performance of CNNs for GPGPUs in the early stage of the design process. The proposed approach uses static analysis for feature extraction and Decision Tree regression analysis for the performance estimation model. Experimental results demonstrate that our approach can predict CNNs performance with an absolute percentage error of 5.73% compared to the actual hardware.
Metaheuristic based framework for Deep Neural Networks compression via DeepCABAC Arithmetic Coding and Fractional Filter

This paper is dedicated to the deep neural network compression problem. To deal with this issue, we propose a new framework that includes the compression-efficient DeepCABAC arithmetic coding, a neural network preprocessing strategy for parameter reduction, a fractional filter (FF) to reduce the number of kernels in the considered deep CNNs, and the convolution-batch norm fusion to increases the inference speed. The whole framework is, then, optimized via a metaheuristic. The proposed framework demonstrates an impressive compression efficiency of up to 94% on VGG-16 without loss on the classification quality, as measured by top-l and top-5 accuracy metrics. For applications where accuracy is not a primary concern, the coding gains can be further increased.
Parallel Techniques for Compressing and Querying Massive Social Networks

The growing popularity of social networks and the massive influx of users have made it challenging to store and process the network/graph data quickly before the properties of the graph change due to graph evolution. Storing graphs or networks that represent entities and their relationships (such as individuals and their friends/followers in a social network) becomes more difficult as the number of users increases, resulting in massive graphs that are challenging to store in standard structures like matrices or adjacency lists. Research in this field has focused on reducing the memory footprint of these large graphs and minimizing the extra memory required for processing. However, there is a trade-off between time and space, as rigorous redundancy removal to achieve a small memory footprint consumes time, and querying becomes more time-consuming when traversing compressed structures compared to matrices or adjacency lists. In this paper, we introduce a parallel technique for constructing graphs using compressed sparse rows (CSR), which offers a smaller memory footprint and allows for parallel querying algorithms, such as fetching neighbors or checking edge existence. We extend our work to include parallel time-evolving differential compression of (CSR) using the prefix sum approach. Additionally, we measure the speed-up gained by using multiprocessors to compress the graph data. To evaluate our techniques, we perform empirical analysis on massive anonymized graphs, including LiveJournal, Pokec, Orkut, and WebNotreDame, which are publicly available. Overall, our results demonstrate that our proposed methods achieve a smaller memory footprint and faster querying compared to traditional storage structures, with additional speedup gained (up to 83% for the biggest graph with 3. 07M nodes and 117. 18M edges) through the use of multiprocessors.
NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs

Recent research widely deployed Neural Networks (NNs) in various scenarios, such as IoT systems, wearable devices, or smart sensors. However, the complex application scenarios cause the rapid extension of network model size and the requirement for higher-performance hardware platforms. Related works apply Heterogeneous Streaming Dataflow (HSD) and Processing Element Matrix (PEM) architectures as the most popular schemes for FPGA-based implementation of NN accelerator: 1) HSD architecture implements a complete network for given trained models on FPGA with simplified control but more hardware consumption; 2) PEM architecture implements reusable neuron structures controlled by runtime environments/drivers providing the generic acceleration supports for different network models. Our work explores a new hybrid architecture based on HSD and PEM to implement a reusable partial network structure on FPGA and achieve generic acceleration supports for different network models with simplffied runtime control. This architecture supports scalable, mixable, quantized precision, and selectable activation functions, including ReLU, Sigmoid, Tanh, Sign, and Multi-Thresholds. Data stream transmission can reset the accelerator configuration in runtime without hardware implementation changes for different networks. Our design fully supports the generic inference acceleration for different Multi-Layer Perceptron (MLP) models.
Implementing An Outsourced Dual-Proxy Signing and Decryption Scheme in Mobile Cloud Computing

Existing access control schemes that support fine-grained and secure data sharing for mobile cloud computing system typically focus on the design and development of secure and lightweight cryptographic protocols to enable data users efficiently decrypt the data by using mobile devices. However, some business requirements such as industrial cloud users may require the proof of authenticity of the data owner. Accordingly, both privacy-preserving and strong authenticity that data users can verify the authenticity of data owners to make trust the shared data are essential. To this end, we proposed a secure and efficient access control featured with efficient revocation in mobile cloud computing environment. Our proposed scheme is based on the outsourced dual proxy model where the expensive digital signing, encryption and decryption are partially offloaded to be executed by the delegated proxies in the cloud. We employed the symmetric encryption and the ciphertext policy attribute-based encryption (CP-ABE) as a core encryption scheme. In addition, we introduced a user revocation algorithm to enable the efficient user revocation in the mobile cloud computing. For the evaluation, we run the experiments to measure the performance of our core access control algorithms and the results demonstrated that our proposed scheme is efficient.
Towards xBGAS on CHERI: Supporting a Secure Global Memory

Modern computing systems embrace heterogeneous system architectures to meet high-performance computing requirements. As a result, the Extended Base Global Address Space (xBGAS) project introduced an extension to the RISCV instruction set architecture (ISA) to provide extended addressing capabilities. Although the xBGAS project is currently implemented on the RISC-V ISA, the project’s central vision is to include a broad domain of ideas that is not dependent on any single microarchitecture. Therefore, demonstrating the existing xBGAS benchmarks on the ARM ISA would enable working on a real system prototype. The ARM Morello platform is intended as an industrial demonstrator of a capability architecture using Capability Hardware Enhanced RISC Instructions (CHERI). Consequently, understanding the CHERI semantics and identifying the desired features for xBGAS are crucial for making xBGAS portable across platforms. In this work, we investigate creating a software-based xBGAS solution for the Morello platform by porting the xBGAS runtime onto the ARM ISA. First, we revisit the basics of the xBGAS project and the CHERI project to learn what the security benefits of CHERI on xBGAS are by taking advantage of CHERI capabilities. Then, we explore the implementation of the CHERI capabilities and Morello simulators to discuss an adaptation of the scalable xBGAS runtime library to support other ISAs such as ARM.
Q2Logic: A Coarse-Grained FPGA Overlay targeting Schrödinger Quantum Circuit Simulations

Quantum computing is emerging as an important (but radical) technology that might take us beyond Moore’s law for certain applications. Today, in parallel with improving quantum computers, computer scientists are relying heavily on quantum circuit simulators to develop algorithms. Most existing quantum circuit simulators run on general-purpose CPUs or GPUs. However, at the same time, quantum circuits themselves offer multiple opportunities for parallelization, some of which could map better to other architecture– architectures such as reconfigurable systems. In this early work, we created a quantum circuit simulator system called Q2Logic. Q2Logic is a coarse-grained reconfigurable architecture (CGRA) implemented as an overlay on Field-Programmable Gate Arrays (FPGAs), but specialized towards quantum simulations. We described how Q2Logic has been created and reveal implementation details, limitations, and opportunities. We end the study by empirically comparing the performance of Q2Logic (running on a Intel Agilex FPGA) against the state-of-the-art framework SVSim (running on a modern processor), showing improvements in three large circuits(#qbit≥27), where Q2Logic can be up-to 7x faster.
A Trace-driven Performance Evaluation of Hash-based Task Placement Algorithms for Cache-enabled Serverless Computing

Data-driven interactive computation is widely used for business analytics, search-based decision-making, and log mining. These applications' short duration and bursty nature makes them a natural fit for serverless computing. Data processing serverless applications are composed of many small tasks. Application tasks that use remote storage encounter bottlenecks in the form of high latency, performance variability, and throttling. Caching has been used to mitigate this bottleneck for intermediate data. However, the use of caching for input data, albeit widely used in industry, has yet to be studied. We present the first performance study of scaling, a key feature of serverless computing, on serverless clusters with input data caches. We compare 8 task placement algorithms and quantify their impact on task slowdown and resource usage before and after scaling. We quantify the consequences of using work stealing. We quantify the performance impact of scaling in the buffer period immediately after scaling. We find up to a 420% increase in task slowdown after scaling without work stealing and a 22% slowdown with work stealing. We also find that cache misses after scaling can lead to an additional 21% resource usage.