Reviewerly/exHarmony huggingface dataset:
OpenPose Based Yoga Poses Difficulty Estimation for Dynamic and Static Yoga Exercises

Assessing the difficulty of a Yoga pose is a challenging task, often dependent on individuals’ subjective judgement or consultation with professionals to choose poses that fit their needs. In this study, a preliminary difficulty calculation method for estimating the difficulty of Yoga poses is proposed, and it is applied to the Yoga poses in the proposed system in order to provide a user-friendly difficulty reference. OpenPose is applied in the system to detect user’s movements and extract the key-points information. In the experimental results, seven users are inquired to participate in practicing Yoga by the proposed system, and they are asked to provide the difficulty levels rating from 1 to 5. These subjective difficulty levels are used to compare the estimated difficulty levels. The results indicate a positive correlation between the subjective and estimated difficulty results.
Consideration of Varying Training Lengths for Short-Duration Speaker Verification

We present an efficient training scheme for speaker verification (SV) networks in short-duration speech input scenarios. We analyze the effects of varying training lengths on SV performance, with a particular focus on short utterances. Despite the high demand for short-duration SV in real-world applications, state-of-the-art SV systems have primarily been evaluated on long utterances, and little research has been conducted on short-duration SV. By considering the innate characteristics of SV architectures and the performance discrepancies associated with varying training data lengths, we propose a training scheme that accounts for varying length conditions. We categorize speaker characteristics as coarse-grained and fine-grained features and demonstrate that training models to learn both features can result in length-robust speaker embeddings. Our proposed training scheme improves model performance by 28.7% and 37.9% in terms of equal error rate on short-duration speech scenarios compared to baseline models.
PQC Cloudization: Rapid Prototyping of Scalable NTT /INTT Architecture to Accelerate Kyber

The advent of quantum computers poses a serious challenge to the security of cloud infrastructures and services, as they can potentially break the existing public-key cryptosystems, such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC). Even though the gap between today's quantum computers and the threats they pose to current public-key cryptography is large, the cloud landscape should act proactively and initiate the transition to the post-quantum era as early as possible. To comply with that, the U.S. government issued a National Security Memorandum in May 2022 that mandated federal agencies to migrate to post-quantum cryptosystems (PQC) by 2035. To ensure the long-term security of cloud computing, it is imperative to develop and deploy PQC resistant to quantum attacks. A promising class of post-quantum cryptosystems is based on lattice problems, which require polynomial arithmetic. In this paper, we propose a scalable number-theoretic transform (NTT) architecture that significantly enhances the performance of polynomial multiplication. Our proposed design exploits multilevels of parallelism to accelerate the NTT computation on reconfigurable hardware. We use the high-level synthesis (HLS) method to implement our design, which allows us to describe the NTT algorithm in a high-level language and automatically generate optimized hardware code. HLS facilitates rapid prototyping and enables us to explore different design spaces and trade-offs on the hardware platforms. Our experimental results show that our design achieves 11× speedup compared to the state-of-the-art requiring only 14 clock cycles for an NTT computation over a polynomial of degree 256. To demonstrate the applicability of our design, we also present a coprocessor architecture for Kyber that utilizes our scalable NTT core.
A Research on Scattering Removal Technology Using Compact GPU Machine for Real-Time Visualization

In this paper, we propose a system that enables visualization under the situation of scattering media such as fog and smoke by Peplography which is scattering media removal system, on a small GPU machine. Compared to conventional haze removal techniques, peplography technology is capable of removing more dense scattering media and can handle cases where the density of fog varies in the image. On the other hand, the conventional peplography process is performed on a desktop PC, and no system has yet been developed to perform peplography in an outside environment. Thus, we have developed a peplography system using the Jetson AGX Xavier, a single-board computer equipped with a GPU, which is superior to conventional methods in terms of portability, execution speed, and power consumption. We also demonstrate the performance of this system by conducting experiments using this system under a simulated scattering media scene and evaluating the obtained results in terms of FPS and the image evaluation metric.
Fault Diagnosis Using Kernel Linear Independence Test in Reproducing Kernel Hilbert Space

Fault detection and identification (FDI) is essential for ensuring the safety of mechanical systems. Typically, FDI algorithms begin by establishing fault detection methods and subsequently identifying the faults. The fault detection process aims to detect abnormalities within the system. To initiate the fault detection process, a mathematical model is required for comparison. However, this mathematical model may not be fully known in advance. In this study, we propose the implementation of Gaussian process regression (GPR) to learn the current nominal model using sensor datasets. The learned model is then compared with newly acquired data to detect any occurrence of faults. GPR learns the model using a nonparametric Bayesian kernel defined in the reproducing kernel Hilbert space. Consequently, the kernel linear independence (KLI) test is employed to examine the new data set for fault detection. The simulation environment incorporates the NASA-developed generic fixed-wing aircraft transport model (GTM), specifically considering cases involving severed left-wing configurations for simulation purposes.
Automated Carina Detection in Chest X-ray Images Using Non-Overlapping and Cross-Squeeze Convolutional Neural Networks

A chest X-ray test is necessary to verify the correct positioning of several medical devices and to check for any issues that may have resulted from improper placement. The trachea, carina, and bronchi localization in chest radiography is a crucial test for patients in the Intensive Care Unit (ICU). Most of the images become affected by the machine or the shooting camera's position, so a physician is required to manually adjust the images to locate Carina. Therefore, this research aim is to automate Carina detection in chest X-ray images without manual adjustment. We proposed a Non-Overlapping Max Pooling (NOMP) connection and Cross-Squeeze Convolutional Attention (CSCA) to make up the design architecture. In addition, a convexity defect technique is combined with the post-processing algorithm to determine Carina's final placement. The experimental results show that the overall performance for average error distance is 0.3097 cm, the accuracy rate is 81.5% when the error falls within 0.5 cm, and the accuracy rate is 97% when the error falls within 1 cm.
Collaborative Pseudo Labeling for Prompt-Based Learning

Prompt-based learning has been recently popular as an emerging data efficient approach to parameter fine-tuning for various few-shot classification tasks. The knowledge transfer from a large-scale pre-trained language model could be systematically performed. It is challenging to conduct transfer learning from unlabeled data. Pseudo labeling is feasible to enhance the model generalization by unsupervised learning where additional pseudo labeled data are augmented. However, this method likely suffers from the model bias problem due to the incorrect pseudo labels. This paper presents a new collaborative pseudo labeling for prompt learning which is implemented through a teacher-student model where teacher and student are learned collaboratively. Accordingly, the resulting pseudo labels do not mislead the model while the few-shot classification task can be improved. The experiments on few-shot sentiment classification and natural language inference show the merit of collaborative pseudo labeling and prompt tuning compared with the other methods.
A Case Study on Formally Verifying an Open-source Deep Learning Accelerator Design

Deep learning accelerators play a crucial role in accelerating the performance of deep neural networks. As these accelerators become more complex, ensuring their correctness and reliability becomes increasingly challenging. Formal verification techniques offer a systematic approach to rigorously validate the design and verify its functional correctness. In this case study, we present a detailed analysis of verifying an open-source deep learning accelerator design (at RTL abstraction), highlighting the methodology, challenges, steps and outcomes of an enhanced formal verification process.
Posture Estimation for Bed Monitoring System Using RFID

In Japan, the proportion of the population aged 65 or older has escalated to 28.8%, intensifying the issue of elderly wandering. Concurrently, there has been a surge in incidents involving seniors falling from their beds, necessitating prompt detection and intervention in the healthcare and nursing sectors. Various bed departure sensors and monitoring systems have been suggested to address this issue. In this study, we introduce an RFID-based bed monitoring system tailored for the elderly and delineate a methodology for classifying in-bed postures using machine learning. Our previous research indicated a decline in posture recognition accuracy when the individual in the training data differed from the one in the testing data. In this study, we examine inter-individual differences by projecting subject data onto a two-dimensional space, and explore the reasons behind the diminished recognition accuracy observed in prior research. Furthermore, we discuss future directions for enhancing the posture recognition rate.
Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design

Number Theoretic Transform (NTT) and Secure Hash Algorithm 3 (SHA3), are the two main operators in the lattice-based Post-Quantum Cryptography (PQC) algorithms. Lattice-based PQC algorithms have different parameter settings, e.g., the length and modulus of NTT polynomials and the different hash functions. Motivated by the demands for more versatile NTT and SHA3 hardware accelerators, we implement the NTT and SHA3 designs that can accommodate to different parameters at run-time. Furthermore, to reduce the running cycles of the whole NTT operation and whole SHA3 operation including data transferring and calculation, we propose a pipelined architecture to optimize the gap between data transfer and calculation process in high-level. The designed configurable accelerators can be embedded in SoC to accelerate different lattice-based PQC algorithms efficiently. The experimental results show that our high-level pipelined and configurable NTT and SHA3 designs have good area-time efficiency. In specific, for the NTT design, our architecture is 4.1 times more area-time efficient compared with the state-of-the-art. For SHA3, our architecture is 1.4 times more area-time efficient over the existing configurable SHA3 designs.
Exploiting Hardware Imperfections for GPS Spoofing Detection Using Clock Variations

The security of location-dependent systems is jeopardized by the act of GPS spoofing, which involves the transmission of deceptive signals to receivers. The detection of such attacks poses a significant challenge in the absence of dedicated hardware or a comprehensive dataset for training purposes. In this study, we present an innovative approach for detecting spoofing attempts by examining distinct clock instability patterns exhibited by electronic devices as a result of manufacturing inconsistencies. The identification of spoofing signals originating from counterfeit GPS transmitters is achieved through fingerprinting timing characteristics. The proposed algorithm utilizes clock fingerprints to quantify temporal fluctuations. Spoofed signals are identified through discrepancies between the observed time measurements and the anticipated satellite characteristics. This solution offers a software-based method for detecting spoofing, eliminating the need for extra hardware or pre-existing data. The proposed technique is assessed in the context of various spoofing strategies, showcasing its ability to reliably detect even low-cost spoofs with unstable clocks. Our research enhances the capabilities of GPS anti-spoofing in comparison to previous studies by offering an implementation that is easily accessible and requires minimal assumptions. By capitalizing on hardware limitations instead of attempting to mitigate them, we transform fabrication variations into deceptive fingerprints. By exploiting inherent hardware limitations, the proposed spoofing detection approach only requires a standard receiver. The experimental results shows that the proposed technique can effectively detect the spoofing attack with 100% accuracy.
An Empirical Study of the Inherent Resistance of Knowledge Distillation Based Federated Learning to Targeted Poisoning Attacks

An empirical study of the inherent resistance of knowledge distillation based federated learning to targeted poisoning attacks
Investigating the Effect of Electromagnetic Fault Injections on the Configuration Memory of SRAM-Based FPGA Devices

This paper presents an analysis of the impact of Electromagnetic Fault Injections (EMFI) on the behaviour of Field-Programmable Gate Arrays (FPGA). We investigate how EMFIs affect the FPGA's configuration memory and fabric. Using a specialized EMFI apparatus and a custom-built test bench, we perform a series of tests and discuss the accuracy and precision achieved with this equipment and its impact on device security. Furthermore, we use the FPGA's readback capability along with bitstream reverse-engineering techniques to analyze and confirm the impact of EMFIs.
SMASh: A State Encoding Methodology Against Attacks on Finite State Machines

Finite State Machines (FSMs) are critical components that control the functionality of chips and their individual components. They can be compromised by introducing unwanted transitions to the security-critical states. This makes them vulnerable to several attacks that aim to identify the FSM transitions. This work handles the Differential Power Analysis (DPA) attacks and Fault Injection Attacks (FIA) on FSMs. Therefore, this paper proposes a state encoding technique that ensures the maintenance of hamming distance across all transitions, providing protection against DPA. This property of hamming distance preservation is further utilized to detect and mitigate potential faults injected into the system. Hence, addresses the FIA attacks. The proposed scheme is independent of the number of FSM transitions. It also introduces confusion to attackers by dynamically varying the state encoding based on the additional bits required to maintain the Hamming Distance (HD). The effectiveness of the proposed scheme is demonstrated in terms of resource utilization compared to traditional encoding schemes through extensive experimentation on MCNC benchmark circuits. Moreover, the technique proposed in this paper is quite flexible for a wide range of FSM designs. Thus, provide generic framework to enhance the security of digital systems.
Development and Validation of Reconfigurable Autonomous Mobile Manipulator for Flexible Manufacturing Process

The utilization of Automatic Mobile Manipulators (AMM) is on the rise for flexible production systems in the manufacturing industry. AMM provides a distinct advantage by surpassing the constraints of robot workspaces through enhanced mobility and efficient task execution. This research focuses on the development and validation of an AMM for flexible production processes in the manufacturing industry. The AMM combines manipulation and navigation intelligence to enable complex assembly tasks and autonomous navigation in non-standardized environments. Through virtual and real-world experiments, the AMM demonstrates robust manipulation skills, accurate object detection and tracking, and efficient task execution. The results confirm the feasibility of using AMM to enhance production processes and address unique manufacturing challenges. Future work will involve further improving AMM capabilities and addressing diverse and dynamic environments.
Comparative Analysis of IR-IR Image Matching Applying the Deep Learning-Based Template Matching Techniques

Template matching technology is a technique that can be applied to various computer vision technologies such as object detection, object recognition, and object tracking. A powerful template matching technique can improve the accuracy and effectiveness of computer vision techniques. In this paper, the template matching techniques are compared with Infrared Radiation images. The techniques are based on deep learning and this paper is to evaluate the performance of deep learning-based techniques for IR images. The techniques consist of QATM(Quality Aware Template Matching), Deep-DIM (Divisive Input Modulation) and SiamFC. The input IR image pairs consist of a search image and a template image, and the template image is an image that crop out of the search image. Each technique is compared and analyzed for runtime and accuracy. The runtime means whole matching time include making feature maps and the accuracy is calculated with RMSE (Root Mean Squared Error).
IPRec and Isoblaze: Fuzzy Subcircuit Isomorphism for IP Detection in Physical Netlists

Netlist reverse engineering has many uses, from detecting hardware trojans to recovering missing design source files. However, the basic problem of finding IP in a netlist has not been widely discussed. The problem boils down to subgraph isomorphism on graphs constructed from netlists. We present two approaches to identifying IP in larger circuits. IPRec focuses on exploiting hierarchy in the IP design and is a rather conservative approach, while Isoblaze focuses on local properties and connectivity and is more liberal in matching.
Verifying RISC-V Privilege Transition Integrity Through Symbolic Execution

Ensuring privilege transition integrity during execution context switch is crucial for protecting the processor from unauthorized access and malicious actions. However, existing methods fall short in covering potential attack paths and vectors in a complete manner. In this work, we propose a method for formal verification of privilege correctness targeting privilege escalation attacks, where the program processes on non-privileged mode may access the sensitive information stored in Special purpose registers (SPRs). We specify assertion property and utilize the Klee symbolic execution engine to formally check the consistency in privilege when accessing contents in critical registers. The formal solver performs state space exploration through heuristic search to identify the possible integrity violation test cases that can trigger an illegal privilege escalation, which further allows creating a minimal simulation system consisting of the CPU and Quick Memory (QMEM) modules to replay the privilege violation process. Experimental results have demonstrated that our method can systematically verify the privilege validity to protect the system from privilege escalation attacks on a RISC-V processor.
MicroBitstreams: Reducing Configuration Time of Encrypted Bitstreams

Field Programmable Gate Arrays (FPGAs) are powerful re-programmable hardware devices. The functionality of a FPGA is determined through the configuration file, or bitstream, programmed in at boot-up. However, the boot-up configuration time requires tens to hundreds of milliseconds too long for some boot time-sensitive systems. This problem is exacerbated if bitstream encryption and authentication are used. State-of-the-art techniques to reduce the configuration times of bitstreams consists of configuration frame removal, compressing the bitstream, or partial reconfiguration of the fabric during run time. Often these solutions do not apply encryption or authentication to the final bitstream leaving the user design susceptible to tamper, cloning, and malicious insertions. Our work approaches this problem by splitting the design into two separate bitstreams, a fast “mission critical” bitstream, or MicroBitstream, and a “full feature” bitstream, or secondary bitstream. On boot, only the MicroBitstream is loaded into the FPGA. Even with authentication and encryption, the MicroBitstream is able to load into the FPGA in an average of 1.13 seconds. In addition to the “mission mission critical” features, the MicroBitstream contains a bootloader that will leverage partial reconfiguration to dynamically reprogram the FPGA at run-time to incorporate the full feature set. This technique, named MicroBitstreams, can also be used to enable a wide variety of encryption and authentication schemes on the secondary bitstream. MicroBitstreams applies encryption and authentication to secure the MicroBitstream from tamper, cloning, and malicious insertions. The average decrease in total configuration time when using a MicroBitstream compared to a normal encrypted bitstream is 88.70%, and 57.61% when compared to a encrypted compressed bitstream. MicroBitstreams enables the use of FPGAs in boot time-sensitive systems, thus decreasing program development costs and time spent in the design process.
High-Quality Font Generation Based on StyleGAN2 and FSFont Font Generation Model

This paper proposes a high-quality font generation method based on StyleGAN2 and FSFont font generation model. In our previous work, we proposed a system that expresses emotions by using font changes and call it an EmoEditor (Emotion-Expressive Editor). This system uses a deep neural network based on zi2zi that is able to generate a desired rendered character by giving a fixed rendered character and a font label which distinguishes between fonts. By changing the font label, the system generates the different font characters which corresponds to several emotions. However, the system was not able to reconstruct the expected ones for our collected fonts that is needed to express emotions. Considering the rapid development of DNN technology, in this paper, we propose an extension of the StyleGAN2 model for font generation. Specifically, we enhance StyleGAN2 by incorporating an Encoder which is come from FSFont generation model and a class label input structure. By adopting a class label input, the proposed model is able to generate indicated font by users. Experimental results show that the proposed method can generate better fonts qualitatively and quantitatively than previous studies on font generation.
Preliminary Study on Data Augmentation Methods for Sign Language Recognition

Sign language dataset is composed of video and corresponding sentence pairs, which reflect the characteristics of a visual language. Since constructing a sufficient amount of sign language dataset is challenging due to the high cost of collecting and creating videos, it becomes difficult to apply large language model approaches to the sign language translation tasks, unlike other natural language processing problems. In this paper, we suggest augmentation methods for sign language data to address the data scarcity issue. To categorize the methods in the context of the sign language translation task, we introduce three criteria: signer's individuality, filming environment, and grammar. Then, we analyze how the augmentation methods can be utilized in existing sign language translation datasets.