Reviewerly/exHarmony huggingface dataset:
Histopathological Gastric Cancer Detection Using Transfer Learning

Gastric cancer is a leading cause of cancer-related deaths worldwide, underscoring the need for early detection to improve patient survival rates. Histopathological image analysis (HIA) is the gold standard for this purpose but it is time-consuming and laborious, leading to interest in computer-aided diagnosis to assist pathologists. Deep learning has shown promise in various HIA tasks, but the limited amount of training data in medical imaging has posed a significant obstacle. In this paper, we propose transfer learning-based CNNs for binary classification of gastric cancer patches, overcoming this limitation. We validate our approach on the publicly available GasHisSDB dataset, which includes three sub-databases with patch sizes of 80 x 80 pixels, 120 x 120 pixels, and 160 x 160 pixels. Our experimental results show that the DenseNet121 model achieved the highest accuracy of 98.68 % and AUC of 98.58% on the 160-pixels sub-database. These results suggest that our proposed work can assist pathologists in the detection of gastric cancer through histopathological image analysis.
DiffPattern: Layout Pattern Generation via Discrete Diffusion

Deep generative models dominate the existing literature in layout pattern generation. However, leaving the guarantee of legality to an inexplicable neural network could be problematic in several applications. In this paper, we propose DiffPattern to generate reliable layout patterns. DiffPattern introduces a novel diverse topology generation method via a discrete diffusion model with compute-efficiently lossless layout pattern representation. Then a white-box pattern assessment is utilized to generate legal patterns given desired design rules. Our experiments on several benchmark settings show that DiffPattern significantly outperforms existing baselines and is capable of synthesizing reliable layout patterns.
An Efficient Accelerator for Point-based and Voxel-based Point Cloud Neural Networks

The 3D point cloud neural networks, including point-based and voxel-based networks, play an essential role in various 3D applications. Many previous works have proposed dedicated accelerators to speed up 3D point cloud neural network processing. Yet, two major challenges still exist: (1) Inefficient memory access due to large off-chip data access volume. The point-based method visits massive redundant points, while the voxel-based method fails to reuse on-chip voxel data, leading to up to 983× data access compared with original input data. (2) Poor scalability due to low computing unit utilization. The computing unit is under-utilized when scaled with a larger computing array size, as low as 16.37% when scaling the current accelerator’s computing capability to general-purpose processors (e.g., GPUs).To solve the above challenges, we propose MARS, a memory access reduced and scalable accelerator for both point-based and voxel-based 3D point cloud neural networks. To reduce the memory access, MARS filters out unnecessary off-chip point data access by 6.52× in volume for point-based networks and increases on-chip data reuse to reduce off-chip data access by 26.31× for voxel-based networks. To improve scalability, MARS also features an elastic computing array architecture that can be dynamically configured at runtime to fit different tasks, providing 7.09× higher computing unit utilization. Extensive experiments show that MARS achieves 1.76× over speedup and 3.97× PointAcc for point-based and end-to-end voxel-based point cloud neural networks, respectively.
C<sup>2</sup>PI: An Efficient Crypto-Clear Two-Party Neural Network Private Inference

Recently, private inference (PI) has addressed the rising concern over data and model privacy in machine learning inference as a service. However, existing PI frameworks suffer from high computational and communication costs due to the expensive multi-party computation (MPC) protocols. Existing literature has developed lighter MPC protocols to yield more efficient PI schemes. We, in contrast, propose to lighten them by introducing an empirically-defined privacy evaluation. To that end, we reformulate the threat model of PI and use inference data privacy attacks (IDPAs) to evaluate data privacy. We then present an enhanced IDPA, named distillation-based inverse-network attack (DINA), for improved privacy evaluation. Finally, we leverage the findings from DINA and propose C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> PI, a two-party PI framework presenting an efficient partitioning of the neural network model and requiring only the initial few layers to be performed with MPC protocols. Based on our experimental evaluations, relaxing the formal data privacy guarantees C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> PI can speed up existing PI frameworks, including Delphi [1] and Cheetah [2], up to 2.89× and 3.88× under LAN and WAN settings, respectively, and save up to 2.75× communication costs.
Consumers’ Intention to Use Drone Food Delivery Service: Belief-Desire-Intention Model and Big Five Personality Traits Approach

Delivery accidents, pollution, and deaths in Malaysia have highlighted the need for safer alternatives like drone food delivery services (DFDS). However, the impact of consumers’ personality traits on their intention to use DFDS is not well understood. This study uses the belief-desire-intention (BDI) model, and the big five personalities (BFP) to explain behavioral intention towards DFDS and proposes desire as a mediator. It contributes to the existing literature by providing insights into the effect of personality traits on desire and intention towards DFDS. This study has the potential to inform managers’ strategies for developing DFDS and aid the Malaysian government in encouraging adoption to reduce air pollution and food delivery accidents.
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms

Optimal deployment of deep neural networks (DNNs) on state-of-the-art Systems-on-Chips (SoCs) is crucial for tiny machine learning (TinyML) at the edge. The complexity of these SoCs makes deployment non-trivial, as they typically contain multiple heterogeneous compute cores with limited, programmer-managed memory to optimize latency and energy efficiency. We propose HTVM – a compiler that merges TVM with DORY to maximize the utilization of heterogeneous accelerators and minimize data movements. HTVM allows deploying the MLPerf™ Tiny suite on DIANA, an SoC with a RISC-V CPU, and digital and analog compute-in-memory AI accelerators, at 120x improved performance over plain TVM deployment.
Shoggoth: Towards Efficient Edge-Cloud Collaborative Real-Time Video Inference via Adaptive Online Learning

This paper proposes Shoggoth, an efficient edge-cloud collaborative architecture, for boosting inference performance on real-time video of changing scenes. Shoggoth uses online knowledge distillation to improve the accuracy of models suffering from data drift and offloads the labeling process to the cloud, alleviating constrained resources of edge devices. At the edge, we design adaptive training using small batches to adapt models under limited computing power, and adaptive sampling of training frames for robustness and reducing bandwidth. The evaluations on the realistic dataset show 15%–20% model accuracy improvement compared to the edge-only strategy and fewer network costs than the cloud-only strategy.
Towards A Formally Verified Fully Homomorphic Encryption Compute Engine*

We present a scalable approach for formally verifying the correctness of the Compute Engine (CE) against its ISA (Instruction Set Architecture) specification in an FHE (Fully Homomorphic Encryption) accelerator, critical to many applications where safety and security of information is of vital importance. It combines algorithmic verification of the micro-architecture modules in the CE against their functional specifications and implementation verification of the CE hardware against its micro-architecture algorithmic specifications. The correctness of the CE is guaranteed by treating micro-architecture modules as semantic-preserving program transformations and leveraging the composability of the semantic-preserving properties well established in compiler design and verification.
Ever more optimized simulations of fermionic systems on a quantum computer

Despite using a novel model of computation, quantum computers break down programs into elementary gates. Among such gates, entangling gates are the most expensive. In the context of fermionic simulations, we develop a suite of compilation and optimization techniques that massively reduce the entangling-gate counts. We exploit the well-studied non-quantum optimization algorithms to achieve up to 24% savings over the state of the art for several small-molecule simulations, with no loss of accuracy or hidden costs. Our methodologies straightforwardly generalize to wider classes of near-term simulations of the ground state of a fermionic system or real-time simulations probing dynamical properties of a fermionic system.
Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed

Memory Disambiguation Unit (MDU) is widely used on modern processors to speculatively execute load instructions and improve pipeline performance. Given that the MDU design details on ARM processors are not available to the public, it is unclear whether there are any security vulnerabilities associated with its MDU. In this paper, we first reverse engineer the undocumented features of ARM MDU, then we discover three potential user-privilege attacks to leak secret data via MDU: cross-process attack that allows users to communicate through a convert channel, cross-domain attack that leaks kernel information and a new variant of inner-process and inter-processes Spectre attacks. These attacks pose serious security challenges as they can bypass both all the known countermeasures against cache side-channel attacks and those against transient execution attacks. Potential mitigation against the proposed MDU-based attacks are also discussed.
Review of Optimization Strategy in Pose Transfer

Optimization strategy in Generative Adversarial Network (GAN) for pose transfer is crucial for improving the model performance, enhancing the quality of the person image generated, and achieving better evaluation metrics. Three optimization strategies are widely applied in GAN improvement, i.e. (a) architecture, (b) loss function, and (c) optimizer. Many variants of architecture, loss function, and optimizer have been proposed to further enhance the model performance focusing on mode collapse, vanishing gradient, and image quality. In this paper, the commonly used optimization strategies such as architecture, loss function, and optimizer in GAN for pose transfer are reviewed. A comparative study of the quantitative performance obtained by various GAN architectures with the respective optimization strategies on the DeepFashion dataset is summarized in chronological order. The optimization strategies in the Pose with Style, SCA-GAN, BiGraphGAN, and XingGAN are the current state-of-the-art methods for pose transfer based on the quantitative results obtained. The potential future development of optimization in GAN for pose transfer is concluded to provide insights into GAN development.
Primer: Fast Private Transformer Inference on Encrypted Data

It is increasingly important to enable privacy-preserving inference for cloud services based on Transformers. Post-quantum cryptographic techniques, e.g., fully homomorphic encryption (FHE), and multi-party computation (MPC), are popular methods to support private Transformer inference. However, existing works still suffer from prohibitively computational and communicational overhead. In this work, we present, Primer, to enable a fast and accurate Transformer over encrypted data for natural language processing tasks. In particular, Primer is constructed by a hybrid cryptographic protocol optimized for attention-based Transformer models, as well as techniques including computation merge and tokens-first ciphertext packing. Comprehensive experiments on encrypted language modeling show that Primer achieves state-of-the-art accuracy and reduces the inference latency by 90.6% ∼ 97.5% over previous methods.
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms

Graph neural networks (GNNs) have emerged as a popular strategy for handling non-Euclidean data due to their state-of-the-art performance. However, most of the current GNN model designs mainly focus on task accuracy, lacking in considering hardware resources limitation and real-time requirements of edge application scenarios. Comprehensive profiling of typical GNN models indicates that their execution characteristics are significantly affected across different computing platforms, which demands hardware awareness for efficient GNN designs. In this work, HGNAS is proposed as the first Hardware-aware Graph Neural Architecture Search framework targeting resource constraint edge devices. By decoupling the GNN paradigm, HGNAS constructs a fine-grained design space and leverages an efficient multi-stage search strategy to explore optimal architectures within a few GPU hours. Moreover, HGNAS achieves hardware awareness during the GNN architecture design by leveraging a hardware performance predictor, which could balance the GNN model accuracy and efficiency corresponding to the characteristics of targeted devices. Experimental results show that HGNAS can achieve about 10.6× speedup and 88.2% peak memory reduction with a negligible accuracy loss compared to DGCNN on various edge devices, including Nvidia RTX3080, Jetson TX2, Intel i7-8700K and Raspberry Pi 3B+.
Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications

Deep Neural Network (DNN) applications are pervasive. However as demands for these applications continue to increase, so is the challenges for designing flexible and scalable architectures for multi-application implementation. Such accelerators require innovative architecture with flexible Network-on-Chips (NoCs), parallelism exploitation, and better on-chip memory organization to adequately support the diverse computation, memory, and communication needs. In this paper, we propose Venus, a versatile DNN accelerator design that can provide efficient communication and computation support for multi-applications. Venus is a tile-based architecture with a distributed buffer where each tile consists of an array of processing elements (PEs) and a portion of the distributed buffer. The other salient feature of Venus is a flexible Network-on-Chip (NoC) that can dynamically adapt to the communication needs of various running applications thus maximizing data reuse, reducing DRAM accesses, and supporting multiple dataflows with an overall aim of better execution time and better energy efficiency. Simulation results show that our proposed Venus design outperforms state-of-art accelerators (NVDLA [1], ShiDianNao [2], Eyeriss [3], Planaria [4], Simba [5]).
Explainability in process outcome prediction: Guidelines to obtain interpretable and faithful models

Process outcome prediction pertains to the classification of ongoing cases of (business) processes into a given set of categorical outcomes. This field of research has seen a strong uptake in recent years due to advances in machine and deep learning. Although a recent shift has been made in the field of process outcome prediction to use models from the explainable artificial intelligence field, the evaluation still occurs mainly through predictive performance-based metrics, thus not accounting for the explainability, actionability, and the implications of the results of the models. This paper addresses explainability through the properties interpretability and faithfulness in the field of process outcome prediction. We introduce metrics to analyse these properties along the main dimensions of process data: the event, case, and control flow attributes. This allows for comparing explanations produced by transparent models with explanations generated by (post-hoc) explainability techniques on top of opaque black box models. We utilise thirteen real-life event logs and seven classifiers, encompassing a variety of transparent and non-transparent machine learning and deep learning models, complemented with (post-hoc) explainability techniques. Next, this paper contributes a set of guidelines named X-MOP for obtaining explainable models for outcome prediction, which helps to select the most suitable model by providing insight into how the varying preprocessing, model complexity, and explainability techniques typical in process outcome prediction influence the explainability of the model.
Sidekick: Near Data Processing for Clustering Enhanced by Automatic Memory Disaggregation

Near Data Processing (NDP) is a promising solution for data mining/analysis techniques, which extract useful information from big data. In this paper, we propose a novel NDP-enabled memory disaggregation system called Sidekick, based on a type-2 CXL device and enhanced by an automated allocation technique for clustering algorithms. The key enabler of our migration technique is to understand clustering workflows in a unit of the program context, which is the function call stack for functions, threads, and memory allocations to drive the automated decision. The proposed technique relates the migrated computation tasks with a series of function calls and performs GA-based optimization to identify the optimal allocation scenario for a target clustering algorithm. In Scikit-learn, a popular machine learning library, we use the genetic algorithm to find the optimal memory allocation policy and the operation offloading policy using the program context. The results show that the proposed technique increases the clustering performance as compared to the case, which only uses disaggregated memory without NDP cores, by up to 92% in terms of execution time, while reducing the majority of remote CXL memory accesses.
OmniBoost: Boosting Throughput of Heterogeneous Embedded Devices under Multi-DNN Workload

Modern Deep Neural Networks (DNNs) exhibit profound efficiency and accuracy properties. This has introduced application workloads that comprise of multiple DNN applications, raising new challenges regarding workload distribution. Equipped with a diverse set of accelerators, newer embedded system present architectural heterogeneity, which current run-time controllers are unable to fully utilize. To enable high throughput in multi-DNN workloads, such a controller is ought to explore hundreds of thousands of possible solutions to exploit the underlying heterogeneity. In this paper, we propose OmniBoost, a lightweight and extensible multi-DNN manager for heterogeneous embedded devices. We leverage stochastic space exploration and we combine it with a highly accurate performance estimator to observe a ×4.6 average throughput boost compared to other state-of-the-art methods. The evaluation was performed on the HiKey970 development board. Our code is publicly available at https://github.com/AndreasKaratzas/omniboost-v1.
Skellam Rank: Fair Learning to Rank Algorithm Based on Poisson Process and Skellam Distribution for Recommender Systems

Recommender system is a widely adopted technology in a diversified class of product lines. Modern day recommender system approaches include matrix factorization, learning to rank and deep learning paradigms, etc. Unlike many other approaches, learning to rank builds recommendation results based on maximization of the probability of ranking orders. There are intrinsic issues related to recommender systems such as selection bias, exposure bias and popularity bias. In this paper, we propose a fair recommender system algorithm that uses Poisson process and Skellam distribution. We demonstrate in our experiments that our algorithm is competitive in accuracy metrics and far more superior than other modern algorithms in fairness metrics.
R-TOSS: A Framework for Real-Time Object Detection using Semi-Structured Pruning

Object detectors used in autonomous vehicles can have high memory and computational overheads. In this paper, we introduce a novel semi-structured pruning framework called R-TOSS that overcomes the shortcomings of state-of-the-art model pruning techniques. Experimental results on the JetsonTX2 platform show that R-TOSS has a compression rate of 4.4× on the YOLOv5 object detector with a 2.15× speedup in inference time and 57.01% decrease in energy usage. R-TOSS also enables 2.89× compression on RetinaNet with a 1.86× speedup in inference time and 56.31% decrease in energy usage. We also demonstrate significant improvements compared to various state-of-the-art pruning techniques.
HammerDodger: A Lightweight Defense Framework against RowHammer Attack on DNNs

RowHammer attacks have become a serious security problem on deep neural networks (DNNs). Some carefully induced bit-flips degrade the prediction accuracy of DNN models to random guesses. This work proposes a lightweight defense framework that detects and mitigates adversarial bit-flip attacks. We employ a dynamic channel-shuffling obfuscation scheme to present moving targets to the attack, and develop a logits-based model integrity monitor with negligible performance loss. The parameters and architecture of DNN models remain unchanged, which ensures lightweight deployment and makes the framework compatible with commodity models. We demonstrate that our framework can protect various DNN models against RowHammer attacks.
Lightning Talk: Scaling Up Quantum Compilation – Challenges and Opportunities

The past decade witnessed exciting advances in quantum computing (QC) platforms. For example, superconducting qubit systems of over a hundred qubits have been developed and are now commercially available [1] , [2] . Trapped ion systems in long chains or quantum charge-coupled device (CCD) [3] architectures have also been developed, reaching very low gate errors [4] , [5] . Recently, neutral atoms trapped in arrays of optical tweezers emerged as a very promising experimental platform with hundreds of qubits at room temperature for programmable quantum simulations and quantum computation [6] , [7] . Figure 1 illustrates the rapid growth of the capacity of these QC platforms in recent years. With IBM’s recent announcement of the plan for building a 100,000-qubit quantum processing unit (QPU) [8] , there is a strong need to scale up the capacity and performance of quantum compilation tools to match the rapid advances of quantum hardware.
PASNet: Polynomial Architecture Search Framework for Two-party Computation-based Secure Neural Network Deployment

Two-party computation (2PC) is promising to enable privacy-preserving deep learning (DL). However, the 2PC-based privacy-preserving DL implementation comes with high comparison protocol overhead from the non-linear operators. This work presents PASNet, a novel systematic framework that enables low latency, high energy efficiency & accuracy, and security-guaranteed 2PC-DL by integrating the hardware latency of the cryptographic building block into the neural architecture search loss function. We develop a cryptographic hardware scheduler and the corresponding performance model for Field Programmable Gate Arrays (FPGA) as a case study. The experimental results demonstrate that our light-weighted model PASNet-A and heavily-weighted model PASNet-B achieve 63 ms and 228 ms latency on private inference on ImageNet, which are 147 and 40 times faster than the SOTA CryptGPU system, and achieve 70.54% & 78.79% accuracy and more than 1000 times higher energy efficiency. The pretrained PASNet models and test code can be found on Github <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .