Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

In the modern-day era of technology, a paradigm shift has been witnessed in the areas involving applications of Artificial Intelligence (AI), Machine Learning (ML), and Deep Learning (DL).Specifically, Deep Neural Networks (DNNs) have emerged as a popular field of interest in most AI applications such as computer vision, image and video processing, robotics, etc.In the context of developed digital technologies and the availability of authentic data and data handling infrastructure, DNNs have been a credible choice for solving more complex real-life problems.The performance and accuracy of a DNN is a way better than human intelligence in certain situations.However, it is noteworthy that the DNN is computationally too cumbersome in terms of the resources and time to handle these computations.Furthermore, general-purpose architectures like CPUs have issues in handling such computationally intensive algorithms.Therefore, a lot of interest and efforts have been invested by the research fraternity in specialized hardware architectures such as Graphics Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), and Coarse Grained Reconfigurable Array (CGRA) in the context of effective implementation of computationally intensive algorithms.This paper brings forward the various research works on the development and deployment of DNNs using the aforementioned specialized hardware architectures and embedded AI accelerators.The review discusses the detailed description of the specialized hardware-based accelerators used in the training and/or inference of DNN.A comparative study based on factors like power, area, and throughput, is also made on the various accelerators discussed.Finally, future research and development directions, such as future trends in DNN implementation on specialized hardware accelerators, are discussed.This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research. INDEX TERMSMachine learning, field programmable gate array (FPGA), deep neural networks (DNN), deep learning (DL), application specific integrated circuits (ASIC), artificial intelligence (AI), central processing unit (CPU), graphics processing unit (GPU), hardware accelerators.an alternative to ASIC-based accelerators, and they can provide superior performance at an affordable cost with reconfigurability and low power dissipation [213].FPGA, ASIC, and GPU-based AI accelerators have been the subject of numerous research [97], [150], [154], [155], [158], [210].This survey, however, also looks at various embedded AI accelerators for DNN acceleration.This survey supplements the existing work and contributes towards providing the complete background on DNN acceleration using various specialized hardware architectures.The contributions of this survey can be summarized as follows: 1) The survey discusses the various research works carried out on the development and deployment of DNN using FPGA-based accelerators.2) The survey covers the work done in ASIC-based AI accelerators in the last decade, from 2012 to 2022.3) The survey describes the various GPU-based DNN accelerators.4) The survey provides a comprehensive overview of CGRA-based accelerators for DNN implementation.5) The survey covers the research works carried out on the implementation of DNNs on edge using embedded AI accelerators.6) The survey provides a comparative study of existing hardware architectures: FPGAs, GPUs, ASICs, and embedded AI accelerators.7) The survey highlights the future research trends in DNN acceleration on specialized hardware architectures, including FPGA, ASIC, GPU, CGRA, and Edge AI accelerators.