Reviewerly/exHarmony huggingface dataset:
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms

Today we see lightweight computer hardware utilized in large volumes, especially with the growing use of IoT devices in homes. However, such devices often ignore security until it is too late and sensitive data breaches have occurred.From here, the importance of finding lightweight cryptographic primitives to secure IoT devices is exponentially increasing, while not impacting the limited resources and limitation of the battery lifetime. In the search for a lightweight cryptographic standard, one must consider how to implement such algorithms optimally. For example, certain parts of an algorithm might be faster in hardware than in software and vice versa.This paper presents a hardware extension supporting the MicroBlaze softcore processor to efficiently implement one of the Lightweight Cryptography (LWC) finalists (TinyJAMBU) on Digilent Nexys A7-100T. The proposed hardware extension consists of a reconfigurable Non-Linear Feedback Shift Register (NLFSR), the central computing part for the authenticated encryption with associated data (AEAD) TinyJAMBU. The proposed NLFSR can run different variants of TinyJAMBU while only consuming 186 mWh in just ten minutes at 100 MHz. The total resources needed to host the proposed NLFSR on the FPGA are 610 LUT and 505 Flip-Flops while executable the binary size is 352 bytes smaller. Therefore, the proposed solution based on the hardware extension is x2.17 times faster than the pure software implementation of the whole TinyJAMBU using MicroBlaze while consuming six mWh more. To our knowledge, this is the first implementation of TinyJAMBU using software/hardware partitioning on FPGA with the softcore processor MicroBlaze.
Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy

The rapid advancement in quantum technology has initiated a new round of exploration of efficient implementation of post-quantum cryptography (PQC) on hardware platforms. Key encapsulation mechanism (KEM) Saber, a module lattice-based PQC, is one of the four encryption scheme finalists in the third-round National Institute of Standards and Technology (NIST) standardization process. In this paper, we propose a novel Toeplitz Matrix-Vector Product (TMVP)-based design strategy to efficiently implement polynomial multiplication (essential arithmetic operation) for KEM Saber. The proposed work consists of three layers of interdependent efforts: (i) first of all, we have formulated the polynomial multiplication of KEM Saber into a desired mathematical form for further developing into the proposed TMVP-based algorithm for high-performance operation; (ii) then, we have followed the proposed TMVP-based algorithm to innovatively transfer the derived algorithm into a unified polynomial multiplication structure (fits all security ranks) with the help of a series of algorithm-to-architecture co-implementation/mapping techniques; (iii) finally, detailed implementation results and complexity analysis have confirmed the efficiency of the proposed TMVP design strategy. Specifically, the field-programmable gate array (FPGA) implementation results show that the proposed design has at least less 30.92% area-delay product (ADP) than the competing ones.
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories

Deep neural networks (DNN) use a wide range of network topologies to achieve high accuracy within diverse applications. This model diversity makes it impossible to identify a single "dataflow" (execution schedule) to perform optimally across all possible layers and network topologies. Several frameworks support the exploration of the best dataflow for a given DNN layer and hardware. However, switching the dataflow from one layer to the next layer within one DNN model can result in hardware inefficiencies stemming from memory data layout mismatch among the layers. Unfortunately, all existing frameworks treat each layer independently and typically model memories as black boxes (one large monolithic wide memory), which ignores the data layout and can not deal with the data layout dependencies of sequential layers. These frameworks are not capable of doing dataflow cross-layer optimization. This work, hence, aims at cross-layer dataflow optimization, taking the data dependency and data layout reshuffling overheads among layers into account. Additionally, we propose to exploit the multibank memories typically present in modern DNN accelerators towards efficiently reshuffling data to support more dataflow at low overhead. These innovations are supported through the Cross-layer Memory-aware Dataflow Scheduler (CMDS). CMDS can model DNN execution energy/latency while considering the different data layout requirements due to the varied optimal dataflow of layers. Compared with the state-of-the-art (SOTA), which performs layer-optimized memory-unaware scheduling, CMDS achieves up to 5.5× energy reduction and 1.35× latency reduction with negligible hardware cost.
Efficient Decryption Architecture for Classic McEliece

As one of the candidates evaluated in the process of the National Institute of Standards and Technology (NIST) post-quantum cryptography standardization, the Classic McEliece, is being widely studied for its strong security. In existing decryption architectures, the Goppa decoder is logic resource intensive, and the fast Fourier transform (FFT) unit limits its achievable frequency. In this paper, a novel folded Goppa decoder based on enhanced parallel inversionless Berlekamp-Massey (ePiBM) algorithm is proposed for complexity reduction, and a two-dimensional optimization is adopted to eliminate the frequency bottleneck caused by the FFT unit. In addition, for the finite field inversion, which is a commonly used operation in decryption, an even power-based computation scheme is presented to reduce the cost of logic resources. Based on these optimizations, a complete decryption architecture is finally developed and implemented on the Altera Stratix V FPGA. Experimental results show that the proposed decryption processor can reduce up to 37.6% of logic resources and save the Time×Logic by up to 56.9% over the prior art.
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators

As the demand for data analysis increases rapidly, artificial intelligence (AI) models have been developed for various applications. Many deep neural networks are presented with millions or billions of parameters and operations for AI computation. Therefore, many AI accelerators apply pipelined architectures with simple but dense computational elements for numerous operations. However, manufacturing-induced faults cause a challenge to computational robustness or yield degradation on those AI accelerators. In this paper, we propose a fault mitigation methodology based on decomposable systolic arrays. By leveraging the inherent error resilience of AI applications, our data arrangement can reduce the difference between accurate results and faulty results. Additionally, utilizing both our proposed data arrangement and sign compensation can further mitigate the influence of faults in AI accelerators. In the experiments, our proposed fault mitigation methodology can maintain the application accuracy at a certain level, which outperforms state-of-the-art methods. When 0.1% of multiplier-accumulators are faulty in a systolic array, the array with our proposed fault mitigation methodology can have less than 0.5% accuracy loss while executing ResNet-18 for ImageNet classification.
DAGGER: Exploiting Language Semantics for Program Security in Embedded Systems

Without the isolation abstractions of operating systems, low-level embedded systems are especially vulnerable to attacks that exploit flaws in either software or hardware to gain control of program behavior. Runtime monitors at the hardware level have shown promise towards by identifying malicious instructions and enforcing programmer-defined policy at runtime. However, the efficiency of monitors comes at the cost of ease of implementation, as policies for ensuring the safe execution of software must be defined at the hardware level. To bridge the abstraction gap, high-level security policy languages have been defined with the ability to be synthesized into hardware monitors, but are limited by semantics that only define policies whose behavior remains static throughout a program’s execution, which limits the practical use case.In this paper, we enable dynamically reconfigurable security policies through a high-level language named DAGGER. Alongside static policies, DAGGER’s semantics support policies that dynamically change behavior in response to expert-defined conditions at runtime. Additionally, we introduce a Verilog compiler to support realizing policies as hardware monitors. DAGGERis developed using the Coq proof assistant, enabling the formal verification of policy correctness and other properties. This approach takes advantage of the abstractions and expressiveness of a higher-level language while minimizing the overhead that comes with other general-purpose approaches implemented purely in hardware, as well as offering the groundwork for a formally verified tool chain.
Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA

The paper presents optimized implementations of Edwards curve digital signature algorithm (EdDSA) which is based on a popular Ed25519 instance. When compared to current digital signature methods, this algorithm considerably reduces the execution time without compromising security. Despite being used in several popular applications, hardware implementation and characteristics is not reported. The proposed work aims to characterize on-chip EdDSA using four different state-of-the-art (SOTA) multipliers. Multiplier forms critical design component in the EdDSA implementation, hence different SOTA multipliers are characterized for hardware metrics and its impact on the overall EdDSA module is investigated. Four different multipliers in the form of Conventional polynomial (CA), Karat-suba (KA), overlap-free-Karatsuba (OKA), overlap-free based multilpier strategy (OBS), along with the default array multiplier which are traditionally employed in hardware designs were investigated for 32-bit and 64-bit data format individually. These multipliers were further employed for designing on-chip EdDSA and its characteristics are presented. CA based on-chip EdDSA was characterized to work reliably at a maximum operating frequency of 120 MHz, whereas OBS and OKA derived on-chip EdDSA presented the most compact on-chip designs. The on-chip EdDSA work is a step towards attaining reliable on-chip cryptosystems in the future.
Online Training from Streaming Data with Concept Drift on FPGAs

In dynamic environments, the inputs to machine learning models may exhibit statistical changes over time, through what is called concept drift. Incremental training can allow machine learning models to adapt to changing conditions and maintain high accuracy by continuously updating network parameters. In the context of FPGA-based accelerators however, online incremental learning is challenging due to resource and communication constraints, as well as the absence of labelled training data. These challenges have not been fully evaluated or addressed in existing research. In this paper, we present and evaluate strategies for performing incremental training on streaming data with concept drift on FPGA-based platforms. We first present FPGA-based implementations of existing training algorithms to demonstrate the viability of online training with concept shift and to evaluate design tradeoffs. We then propose a technique for online training without labelled data and demonstrate its potential in the context of FPGA-based hardware acceleration.
SpotOn: A Gradient-based Targeted Data Poisoning Attack on Deep Neural Networks

Deep neural networks (DNNs) are vulnerable to adversarial inputs, which are created by adding minor perturbations to the genuine inputs. Previous gradient-based adversarial attacks, such as the "fast gradient sign method" (FGSM), add an equal amount (say ϵ) of noise to all the pixels of an image. This degrades image quality significantly, such that a human validator can easily detect the resultant adversarial samples. We propose a novel gradient-based adversarial attack technique named SpotOn, which seeks to maintain the quality of adversarial images high. We first identify an image’s region of importance (ROI) using Grad-CAM. SpotOn has three variants. Two variants of SpotOn attack only the ROI, whereas the third variant adds an epsilon (ϵ) amount of noise to the ROI and a much smaller amount of noise (say ϵ/3) to the remaining image. On Caltech101 dataset, compared to FGSM, SpotOn achieves comparable degradation in CNN accuracy while maintaining much higher image quality. For example, for ϵ = 0.1, FGSM degrades VGG19 accuracy from 92% to 8% and leads to an SSIM value of 0.48 by attacking all pixels in an image. By contrast, SpotOn-VariableNoise attacks only 34.8% of the pixels in the image; degrades accuracy to 10.5% and maintains an SSIM value of 0.78. This makes SpotOn an effective data-poisoning attack technique. The code is available from https://github.com/CandleLabAI/SpotOn-AttackOnDNNs.
ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning

The Last Level Cache (LLC) of modern multicore processors is normally shared between different cores and applications. Dynamic cache partitioning is applied to the LLC for fairly distributing the LLC space among the applications. Recently, Covert Channel Attacks (CCA) becomes a major security issue for modern multicore systems. In CCA, two malicious applications: spy and Trojan, run in two different cores. Trojan normally runs in a secure core and knows some secret information. Through CCA, Trojan communicates this information to the spy. A well-known technique to perform such an attack is Prime Probe (P+P). It performs the attack by using the shared behavior of LLC space. Cache partitioning is considered a defense against such CCA. Partitioning makes the applications isolated in the LLC and they cannot evict each other block from the LLC. Hence, the existing P+P based attacks are not possible while dynamic partitioning is applied to LLC. However, in this work, we have proposed a modified CCA (based on P+P) which can establish a covert channel on top of the dynamic cache partitioning technique applied to LLC. Such kinds of attacks must need to be handled carefully in modern processors. A possible defense mechanism for the new attack is also discussed in this paper.
Shared dynamics learning for large-scale traveling salesman problem

In this work, we study generalization in reinforcement learning for traveling salesman problem (TSP). While efforts have been made for designing deep reinforcement learning-based solvers to achieve near optimal results in small tasks, it is still an open problem to apply such solvers to larger-scale tasks by retaining performance. In this research, we learn the shared dynamics in TSP environments based on multi-task learning, which can be generalized to new tasks. To accurately estimate such dynamics, we consider leveraging the node visitation information. Besides designing RL-based models to attentively aggregate the visitation information during decision making, we propose a scheduled data utilization strategy to stabilize learning with various problem sizes. The experimental result shows that our model achieves improved generalizability for unseen larger TSPs in both zero-shot and few-shot settings.
Investigating the applicable position of established cloud servers using the hybrid partitional clustering

This paper proposes a hybrid partition clustering, which is the combination of three techniques: partitional clustering, proportional allocation, and center-of-gravity. The objective of this hybrid clustering is to identify the applicable position of established cloud servers to support the testing of a high-speed internet platform. These cloud servers will be installed in the Eastern region of Thailand. Moreover, hybrid clustering is developed using RStudio and R packages. The latitude-longitude position and the number of populations from each district that has internet service providers are considered as main factors to do the cluster. Regarding the experiment, we found that K-Means provide a better solution than K-Medoid with a silhouette width value equal to 0.45. In addition, the results of this hybrid clustering will also be compared with the existing solution. The difference in sample users between these two methods is approximately 25 percent.
Coordinated-axis Weight for Real-Time Trace Transform

This paper presents a method for building Coordinated-axis Weight (CW) that has the advantage can be used to increase the speed for converting image data into the domain of real-time trace transforms. The main idea for this method is to use a feature reduction method for image data that must be used in cooperation with supervised machine learning outcome predictions. But the obtained result still retains the distinctive features of the data image in the form of a trace transform. Start by reducing the number of features from the image data, which will be used to reduce the size of the image to the appropriate image size, which in this article will reduce the image size to 45x45 pixels. The next step is to train the data using a Decision Tree (DT) method by aligning the reduced image data in a 1D model. In addition to the image data, two more features are added, i.e. the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\phi$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\rho$</tex> positions, to inform the prediction that each position has a different value. And the last step is to bring the data to create a model for predicting the answer. The weights obtained from the model are called Coordinated-axis Weights (CW). The experiments within this paper were experimented using the Caltech-256 database, which was able to measure the MSE, RMSE, and PNSR of the images compared to the original trace transform response images at 4.1, 2.02, and 42.00, respectively, including the highest predictive speed of 0.2 ms per image.
Ad-hoc Aerial-view Vehicle Detection and Tracking for Real-Time Traffic Monitoring Using YOLOv7

We have proposed an aerial view vehicle detection, classification, and tracking system using the You Look Only Once Version 7 (YOLOv7) machine learning model for automatic ad-hoc traffic statistical information gathering. The unmanned aerial vehicle (UAV) flies and gathers real-time visual data in areas where stationary cameras are unavailable such as rural roads or highway traffics. Eight different types of vehicles are detected and classified followed by tracking. Statistical data such as flow rate, direction, and car density are obtained afterward. The overall accuracy for the classification part is 93%, while the individual accuracies go as high as 99.5% for some classes.
Performance Evaluation of Infrastructure as a Service across Cloud Service Providers

The purpose of this research aims to monitor, analyze, and compare the performance of infrastructure as a service (IaaS) between the selective cloud providers. To assure which cloud provider has more stability, reliability, and scalability. This paper focuses on performance testing based on a deployed web server in the cloud environment. The main feature of cloud computing is scalability thus most common IaaS cloud service providers (CSPs) have Auto Scaling features for instances or virtual machines. Not only does this paper gives the experimental results of the scaling scalability testing, but it also provides the results of recovery testing to inspect how long a web server is able to recover from failures and load testing which simulated traffic requests. Testing was conducted in the major public clouds of Google Cloud Platform (GCP), Microsoft Azure, and Amazon Web Services (AWS). Azure performs the most efficiently of almost all testing but hardest to configure.
Low Complexity Nonbinary Decoder: Correct Only Data part with Implementation

For systematic nonbinary codes, there is no need to correct erroneous parity check symbols since users need only the decoded data symbols. This idea can be generally applied for systematic nonbinary codes. In particular, the complexity of Vector Symbol Decoding (VSD) is greatly reduced because its step for calculating error values need a matrix inversion whose size depends on the number of error symbols. Results show that for a (40,20) code with 32 bits/symbol, the decoding time for VSD decreases from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6.32\times 10^{-5}\mathrm{s}$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3.02\times 10^{-5}\mathrm{s}$</tex> with the proposed method at probability of symbol error = 0.05. Experiments on Raspberry-pi boards are also shown.
Impacts of ResNet Skip Connection levels on Inception Convolutional Neural Network using Different Resized Images in Object Recognition

This paper focuses on impacts of using 1 -and 2 - level ResNet skip connection on inception convolutional neural network (ICNN), named here as 1L - and 2L -ICRN in object recognition. The 1L- and 2L -ICRN as well as ICNN are brought into comparison studies using CIFAR-10 image dataset, with 70x70, 90x90 and 110x110 resized images. Recognition performance appraisements count on averages of F1, accuracy scores, recall and precision, relying upon 5-fold cross validation for bias reduction purpose. Confusion matrix is also examined for more detail of results inspection. The results denote that 1L-ICRN yields 83.02%, 84.85%, 85.06% best recognition accuracy based on 70x70, 90x90 and 110x110 images, consecutively. However, using 70 × 70 images, 1L-ICRN generates 1.05% and 1.68% more accuracy than 2L-ICRN and ICNN, respectively. As image size increases, 1L - and 2L -ICRN generate better performance but in decreasing rate; whilst, ICNN exhibits decreasing performance when expanding the size from 90 X 90 to 110 X 110. Nevertheless, at most, 2-second difference of time consumed by each model is pointed, which is insignificant.
Reinforced Deep Learning By Discriminant Feature Trace Transform

Classification of objects using YOLO deep learning is currently very popular. When the discovered object is rotated, however, the pre-trained YOLO model frequently generates incorrect answer predictions. In order to improve the accuracy of the YOLO deep learning pre-trained model, we present in this paper a method for rotating an object's image back to its initial gain using the DFTF algorithm. The DFTF algorithm is designed to take the results of the trace transform and accumulate the values for each column in order to predict the object's degree of rotation. The results of this calculation are then used to rotate the object back to its normal axis. The experiment is therefore a collaboration between YOLO and DFTF with the aim of more accurately predicting the object's responses. Five groups of data will be chosen for experimentation, each of which can be used to determine the precision of the experimental image with rotational issues. The average of accuracy is 98.56%.