Reviewerly/exHarmony huggingface dataset:
TransLearn-YOLOx: Improved-YOLO with Transfer Learning for Fast and Accurate Multiclass UAV Detection

The emergence of unmanned aerial vehicles (UAVs) raised multiple concerns, given their potential for malicious misuse in unlawful acts Vision-based counter-UAV applications offer a reliable solution compared to acoustic and radio frequencybased solutions because of their high detection accuracy in diverse weather conditions. The existing solutions work well on trained datasets, but their accuracy is relatively low for real-time detection. In this paper, we model deep learning-empowered solutions to improve the multi-class UAV’s classification performance using single-shot object detection algorithms YOLOv5 and YOLOv7. Transfer learning is employed for performance improvement and rapid training with improved results. We customized a multiclass dataset containing single-rotor, fixed-wing and multi-rotor UAVs in challenging weather conditions. Experiments show that the integration of transfer learning has achieved good results, with an overall best average-classification precision of 94%, an average recall of 93.1%, a mAP@0.5 average of 95.3%, and an average F1 score of 92.33%. The dataset and code are available as an open source: https://github.con ZeeshanKaleem/YOLOV5-Large-vs-YOLOV7.git
Deep Skeleton Modeling and Hybrid Hand-crafted Cues over Physical Exercises

Human activities have always been complex and most important concern for researchers especially when it comes to physical exercises. Multiple methods have been proposed for physical exercise recognition using different sensors where the conventional approaches focused on either videos or motion-based sensors. Whereas, the combination of both types of data can improve the physical exercise recognition particularly for complex motion patterns. For that reason, a hybrid handcrafted cues-based method has been proposed in this paper. Data has been collected from the multi-modality-based datasets that are publicly available. Next, three different filters have been used to sift the noise from multiple sensors-based data. Then, an overlapping windowing technique along with human silhouette extraction has been utilized to pre-process the filtered data. Further, the hybrid hand-crafted cues have been extracted using linear prediction cepstral coefficients, Gaussian markov random field, and saliency maps. Finally, the cues have been reduced using multi-layer sequential forward selection methodology and the physical exercise activities have been classified using a deep belief network.
EdgeHARNet: An Edge-Friendly Shallow Convolutional Neural Network for Recognizing Human Activities Using Embedded Inertial Sensors of Smart-Wearables

Human Activity Recognition (HAR) is a well-known area of study in the Internet of Medical and Health Things. The goal of HAR is to monitor complex, subtle, and postural human behaviours in the domains of Ambient Assisted Living (AAL), injury prevention, well-being management, medical diagnostics, and, in particular, geriatric care. The use of inertial sensors in smart devices for HAR is becoming more common, as it eliminates all of the constraints of traditional computer vision techniques. The usage of artificial neural networks improves classification, but their larger complexity makes them harder to deploy near the edge, where latency is reduced. This article presents a deep learning model that is lite in terms of trainable parameters and hence enables Edge-AI. The model is named EdgeHARNet. It assessed WISDM Activity Prediction and WISDM Actitracker datasets. The presented model has only 2031 trainable parameters. It has achieved 94.036% average accuracy for the WISDM Activity Prediction dataset and 74.06% average accuracy for the WISDM Actitracker dataset. Fl-score have also been reported for all individual classes. The performance comparison is carried out with existing models. We have done inference on Raspberry Pi 4 which is a single board computer as well.
Identification of Human Activity and Associated Context Using Smartphone Inertial Sensors in Unrestricted Environment

Smartphones are increasing ubiquitously due to the need and demand in the modern era. The world is transmuting into a global village with the cumulation of smart devices. Nowadays, smartphones are enriched with inertial sensors which can be used to recognize physical human activities in the wild. Human activity recognition (HAR) lies at the core of many applications like health monitoring, fall detection, road safety, personal assistance, and behavior-based context awareness. Context-based HAR is a new dimension that provides fine-grained information about the action being performed and leads us towards the automated and intelligent system design, which is useful to furnish the smart solution to real-life problems. In this paper, smartphone sensors are utilized to propose a framework for human activity and context recognition. This framework performs activity-dependent context recognition on the ExtraSensory dataset using random forest, decision tree, and k-nearest neighbor classifiers, and achieves an accuracy of 93.10%, demonstrating the effectiveness of the proposed framework.
Hybrid Deep Learning Approach for Nonfunctional Software Requirements Classifications

This paper explores the concept of algorithmic hybridization, which involves combining various machine learning (ML) algorithms to enhance performance by utilizing the benefits of both simultaneously. This study presents a framework that utilizes a combination of long short-term memory (LSTM) and bidirectional LSTM (BiLSTM) with artificial neural networks (ANN) to classify non-functional requirements (NFR). The task of NFR classification is challenging due to the scarcity of supervised learning data. The effectiveness of the proposed approach was assessed by comparing the performance of our integrated model with that of single LSTM and BiLSTM models. To conduct this evaluation, we combined two datasets consisting of 1000 non-functional requirements (NFR). The experimental findings revealed that the proposed approach is effective as the hybrid models exhibited better precision, recall, and F-1 score compared to its counterparts.
Voice Presentation Attacks Detection using Acoustic MLTP Features and BiLSTM

Automatic speaker verification (ASV) systems have been used in numerous voice-controlled technologies including voice banking, automobiles, smartphones, smart homes, etc. The growth of voice-operated devices is increasing exponentially, and it is mandatory to secure the ASV systems against voice spoofing attacks such as cloned and synthetic voices. The research community has worked to develop spoofing countermeasures to improve the security of ASV systems. However, existing spoofing countermeasures have limitations to detect voice conversion, synthetic speech, and voice replay attacks. There still exists a need for the development of voice spoofing detectors to further strengthen the security of voice-controlled systems. Therefore, in this study, we designed a novel spoofing countermeasure for identifying physical access (PA) and logical access (LA) attacks. More precisely, we proposed a novel acoustic feature descriptor, namely, modified local ternary patterns (MLTP), and used them to train a BiLSTM classifier for voice spoofing detection. We assessed the performance of our approach using the standard ASVspoof-2019 dataset and attained an equal error rate (EER) of 1.87% and 2.66% for the PA and LA attacks, respectively. Experimental results obtained from a detailed assessment signify that our approach has the capability to accurately classify the bonafide and spoofed audio samples over contemporary methods.
Hardware Acceleration of FHEW

The magic of Fully Homomorphic Encryption (FHE) is that it allows operations on encrypted data without decryption. Unfortunately, the slow computation time limits their adoption. The slow computation time results from the vast memory requirements (64Kbits per ciphertext), a bootstrapping key of 1.3 GB, and sizeable computational overhead (10240 NTTs, each NTT requiring 5120 32-bit multiplications). We accelerate the FHEW bootstrapping in hardware on a high-end U280 FPGA.To reduce the computational complexity, we propose a fast hardware NTT architecture modified from [5] with support for negatively wrapped convolution. The IP module includes large I/O ports to the NTT accelerator and an index bit-reversal block. The total architecture requires less than 225000 LUTs and 1280 DSPs.Assuming that a fast interface to the FHEW bootstrapping key is available, the execution speed of FHEW bootstrapping can increase by at least 7.5 times.
AIOIML: Automatic Integration of Ontologies for IoT Domain Using Hybridized Machine Learning Techniques

There is a need for Ontology modelling and automatic generation of Ontologies in order to assimilate knowledge World Wide Web knowledge as a strategic model. Ontologies are the best knowledge descriptor model as they have some amount of human cognition associated with them because either humans are major contributors when they are generated manually or are indirect contributors when they are semi automatically generated. Internet of Things is a domain which has strategically evolved in the last few years, and there is a need for integrating several facets of Internet of Things Ontology. In this paper a strategic scheme for Internet of Things Ontology integration for Internet of Things domain with different perspective are proposed wherein the dataset are subjected to tag generation which is further classified using the AdaBoost classifier which are aligned with the random core classes of the existing variational Ontologies in the Internet of Things domain using Shannon’s entropy and the pointwise mutual information measure with differential step deviation measure. Which yields average precision and recall of 96.83 and 97.95 respectively.
Interactive Zira Voice Assistant- A Personalized Desktop Application

Since we know that python is a developing language so it is easy to write a voice assistant script in python. Day by day life became smarter and more connected to technology. We already know some voice services like google, Siri etc. Now in our Zira voice assistance system, it can act as a daily schedule reminder, send email, calculator, play music and a search tool. Our project works on voice input and provides voice output and displays text on screen. Our main voice help agenda makes people smarter and delivers faster results with a computer. Voice Help captures voice input with our microphone and transforms our voice into understandable computer language providing the necessary solutions and answers that the user asks. By doing this project, I realized that the concept of AI in all fields reduced human effort and time saving.
Gradient Descent Adversarial Attacks on SVM for CAP EEG signals

Machine learning models have been widely adopted in various applications, but their vulnerability to evasion attacks has become a significant concern. Evasion attacks on machine learning models aim to manipulate the test data in a way that causes the model to make incorrect predictions. In this paper, we performed gradient-based attacks on the support vector machine (SVM) model for cyclic alternating patterns (CAP) sleep phase test dataset. Performance of the classifier is evaluated under evasion attacks and detailed analysis on robustness of model has been done.
Audio de-noising and quality assessment for various noises in lecture videos

Online teaching has taken up its importance post-pandemic period. Today, online teaching is considered to be one of the teaching pedagogy. This means every teacher and professor is generating online lecture videos and sharing them for students’ later use. Mostly, the environment for the video creation is in real time either in the live classroom or at home, various environmental noises interfere with the actual speech of the presenter. Therefore, there is a need for identifying the various noises that may be part of the lecture video to assess the quality of the video. Towards this, very few research works are observed. Researchers have worked on additive noises, but identifying convolutional noises is a challenge. We propose to work on the audio signal of the video lectures to identify the positions and durations of various convolutional noises and measure the amount of noise present in the audio part of the video lectures. We used various filters for identifying simultaneous talks, long silences, baby crying, kitchen sounds, and vehicle noises. The average accuracy of the proposed solution in identifying the noises and the noise positions is 97.37%. The MSE of the noise in the audio of each clip varies depending on the various noises present. This defines the quality of the audio in the lecture video.
Anomaly Detection by Predicting Future Frames using Convolutional LSTM in Video Surveillance

Events that do not confront normal behavior are called anomalies and they are extremely arduous to recognize. The recent approaches that deploy a reconstruction approach for anomaly detection, predominantly emphasize minimizing the reconstruction error of training data. These techniques cannot assure larger reconstruction errors in the event of an anomaly. In our work, we propose to systematize the issue of abnormal event detection within a regime of future frame prediction. Provided a set of input video frames $i_1, i_2, i_3 \ldots i_n$, our next-frame prediction model predicts a new frame $i_{n+1}$ instead of reconstructing the same frame $i_{n+1}$. By extending the contributions of Convolutional Neural Networks (CNNs) and Long Short Term Memory (LSTM), we propose ConvolutionalLSTM (C-LSTM) as a predictor to predict the next frame. To scrutinize the capability of the prediction model, we determine the intensity loss between the actual frame and the predicted frame. The larger error between the predicted frame and ground truth facilitates the detection of anomalous events that do not confront the expectation. This paper mainly emphasizes how well the model predicts the future frame and provides a new baseline for abnormal event detection.
Bio-inspired Autonomous Exploration Policies with CNN-based Object Detection on Nano-drones

Nano-sized drones, with palm-sized form factor, are gaining relevance in the Internet-of-Things ecosystem. Achieving a high degree of autonomy for complex multi-objective missions (e.g., safe flight, exploration, object detection) is extremely challenging for the onboard chip-set due to tight size, payload (< 10g), and power envelope constraints, which strictly limit both memory and computation. Our work addresses this complex problem by combining bio-inspired navigation policies, which rely on time-of-flight distance sensor data, with a vision-based convolutional neural network (CNN) for object detection. Our field-proven nano-drone is equipped with two microcontroller units (MCUs), a single-core ARM Cortex-M4 (STM32) for safe navigation and exploration policies, and a parallel ultra-low power octa-core RISC-V (GAP8) for onboard CNN inference, with a power envelope of just 134 mW, including image sensors and external memories. The object detection task achieves a mean average precision of 50% (at 1.6 frame/s) on an in-field collected dataset. We compare four bio-inspired exploration policies and identify a pseudo-random policy to achieve the highest coverage area of 83% in a ~36 m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> unknown room in a 3 minutes flight. By combining the detection CNN and the exploration policy, we show an average detection rate of 90 % on six target objects in a never-seen-before environment.
CEST: Computation-Efficient N:M Sparse Training for Deep Neural Networks

N:M fine-grained structured sparsity has attracted attention due to its practical sparsity ratio and hardware-friendly pattern. However, the potential to accelerate N:m sparse deep neural network (DNN) training has not been fully exploited, and there is a lack of efficient hardware supporting N:M sparse training. To tackle these challenges, this paper presents a computation-efficient scheme for N:M sparse DNN training, called CEST. A bidirectional weight pruning method, dubbed BDWP, is firstly proposed to significantly reduce the computational cost while maintaining model accuracy. A sparse accelerator, namely SAT, is further developed to neatly support both the regular dense operations and N:M sparse operations. Experimental results show CEST significantly improves the training throughput by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.89-12.49\times$</tex> and the energy efficiency by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.86-2.76\times$</tex> .
Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications

ML accelerators have largely focused on building general platforms for deep neural networks (DNNs), but less so on shallow machine learning (SML) algorithms. This paper proposes Axiline, a compact, configurable, template-based generator for SML hardware acceleration. Axiline identifies computational kernels as templates that are common to these algorithms and builds a pipelined accelerator for efficient execution. The dataflow graphs of individual ML instances, with different data dimensions, are mapped to the pipeline stages and then optimized by customized algorithms. The approach generates energy-efficient hardware for training and inference of various ML algorithms, as demonstrated with post-layout FPGA and ASIC results.
Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP

Recent work has shown that Side-Channel Attacks (SCA) and Fault Attacks (FA) can be combined, forming an extremely powerful adversarial model, which can bypass even some strongest protections against both FA and SCA. However, such strongest form of combined attack comes with some practical challenges - 1) a profiled setting with multiple fault locations is needed; 2) fault models are restricted to single-bit set-reset/flips; 3) the input needs to be repeated several times. In this paper, we propose a new combined attack strategy called SCA-NFA that works in a non-profiled setting. Assuming knowledge of plaintexts/ciphertexts and exploiting bitsliced implementations of modern ciphers, we further relax the assumptions on the fault model, and the number of fault locations - random multi-bit fault at a single fault location is sufficient for recovering several secret bits. Furthermore, the inputs are allowed to be varied, which is required in several practical use cases. The attack is validated on a recently proposed countermeasure called DOMREP, which individually provides SCA and FA protection of arbitrary order. Practical validation for an open-source masked implementation of GIMLI with DOMREP extension on STM32F407G, using electromagnetic fault and electromagnetic SCA, shows that SCA- NFA succeeds in around 10000 measurements.
Digital Emulation of Oscillator Ising Machines

Ising problem is an NP-hard combinatorial op-timization problem. Recently, networks of mutually coupled, nonlinear, self-sustaining oscillators known as Oscillator Ising Machines (OIMs) were shown to heuristically solve Ising prob-lems. The phases of the oscillators in OIMs can be modeled as systems of Ordinary Differential Equations (ODEs) known as Generalized Kuramoto (Gen-K) models. In this paper, we solve Gen-K Ode systems efficiently using cleverly designed fixed point operations. To demonstrate this idea, we fabricated a prototype chip containing 33 spins with programmable all-to-all connectivity. We test this design using Multi-Input Multi-Output decoding problems, and show that the OIM emulator achieves near-optimal Symbol Error Rates (SER).
Scalable Coherent Optical Crossbar Architecture using PCM for AI Acceleration

Optical computing has recently been proposed as a new compute paradigm to meet the demands of future AI/ML workloads in datacenters and supercomputers. However, proposed implementations so far suffer from lack of scalability, large footprints and high power consumption, and incomplete system-level architectures inhibit integration within existing datacenter systems for real-world applications. In this work, we present a truly scalable optical AI accelerator based on a crossbar architecture. We have considered all major roadblocks and address them in this design. Weights will be stored on-chip using phase change material (PCM) that can be monolithically integrated in silicon photonic processes. All electro-optical components and circuit blocks are modeled based on measured performance metrics in a 45nm monolithic silicon photonic process, which can be co-packaged with advanced CPU/GPUs and HBM memories. We also present a system-level modeling and analysis of our chip's performance for the Resnet-50V1.5, considering all critical parameters, including memory size, array size, photonic losses, and energy consumption of peripheral electronics. Both on-chip SRAM and off-chip DRAM energy overheads have been considered in this modeling. We additionally address how using a dual-core crossbar design can eliminate programming time overhead at practical SRAM block sizes and batch sizes. Our results show that a 128 × 128 proposed architecture can achieve inference per second (IPS) similar to Nvidia A100 GPU at 15.4× lower power and 7.24× lower area.
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities

Systems-on-chip (SoCs) have become increasingly large and complex, resulting in new threats and vulnerabilities, mainly related to system-level flaws. However, the system-level verification process, whose violation may lead to exploiting a hardware vulnerability, is not studied comprehensively due to the lack of decisive (security) requirements and properties from the SoC designer's perspective. To enable a more comprehensive verification for system-level properties, this paper presents HUnTer (Hardware Underneath Trigger), a framework for identifying sets (sequences) of instructions at the processor unit (PU) that unveils the underneath hardware vulnerabilities. The HUnTer framework automates (i) threat modeling, (ii) threat-based formal verification, (iii) generation of counterexamples, and (iv) generation of snippet code for exploiting the vulnerability. The HUnTer framework also defines a security coverage metric (HUnT_Coverage) to measure the performance and efficacy of the proposed approach. Using the HUnTer framework on a RISC-V-based open-source SoC architecture, we conduct a wide variety of case studies of Trust-HUB vulnerabilities to demonstrate the high effectiveness of the proposed framework.