New advances in high‐performance computing systems

This Special Issue of Concurrency and Computation: Practice and Experience gathers seven selected research articles, which are the result of extended work previously presented at the Brazilian “XVII Simpósio em Sistemas Computacionais de Alto Desempenho,” WSCAD 2016, held in conjunction with the 28th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2016, Aracaju, SE, Brazil, October 5-7, 2016. Since 2000, this workshop has presented important and interesting research in the fields of computer architecture, high-performance computing, and distributed systems. The scope of the current special Issue is broad and representative of the multidisciplinary nature of high-performance and distributed computing, covering important issues of the field, such as parallel applications, GPU computing, energy consumption, and cloud computing. The papers and their main focus are the following. The paper entitled “Parallel rule-based selective sampling and on-demand learning to rank” by Mateus F. e Freitas, Daniel X. Sousa, Wellington S. Martins, Thierson C. Rosa, Rodrigo M. Silva, and Marcos A. Gonçalves uses parallelism techniques to improve the performance of the Learning to Rank (L2R) task. More specifically, the authors1 propose two methods to exploit parallelism on rule-based systems: Learning to Rank (L2R) training data sets using selective sampling and query-customized ranking models generated on the fly. The authors propose parallel algorithms and GPU implementations for these two cases showing that data set reduction takes only a few seconds with speedups of up to 148× over a serial baseline and that queries can be processed in only a few milliseconds with speedups of 1000× over a serial baseline and 29× over a parallel baseline for the best case. The extended work provides the implementations on multiple GPUs, further increasing the speedup over the baselines. Focusing on GPU computing, in the contribution2 entitled “Maximizing the GPU resource usage by reordering concurrent kernels submission,” authors Rommel A.Q. Cruz, Cristiana Bentes, Bernardo Breder, Eduardo Vasconcellos, Esteban Clua, Pablo M.C. de Carvalho, and Lúcia M.A. Drummond propose a reordering strategy to identify the best order to submit the kernels to execute on the GPU, aiming at maximizing its utilization and increasing the overall throughput. The authors model the problem as a series of knapsack problems and use a dynamic programming approach to solve them. The amount of resources is modeled as the knapsack capacity, and the strategy tries to fulfill the knapsack with kernels that take the most advantage of the available resources, favoring kernels with smaller execution time. The proposed strategy was evaluated using real-world and synthetic applications with different numbers of kernels and resource requirements. The results show that the reordering strategy provides significant gains in the average turnaround time and system throughput compared to the kernels submission implemented in modern GPUs. Tackling energy efficiency issues, in the work3 entitled “Energy efficiency and I/O performance of low-power architectures,” authors Pablo J. Pavan, Ricardo K. Lorenzoni, Vinícius R. Machado, Jean L. Bez, Edson L. Padoin, Francieli Z. Boito, Philippe O.A. Navaux, and Jean-François Méhaut present an energy efficiency and I/O performance analysis of low-power architectures with the goal of evaluating the viability of using them as storage servers. The results show that despite the fact that the power demand of the storage device accounts for a small fraction of the power demand of the whole system, significant increases in power demand are observed when accessing the storage device. The authors also investigate the access pattern impact on power demand, looking at the whole system and at the storage device by itself, finally comparing all of the tested configurations regarding energy efficiency. This study provides guidelines for the replacement of traditional storage servers by low-power alternatives. As a consequence, the choice will depend on the expected workload, estimates of power demand of the system, and factors limiting the performance. Related to cloud computing models, in the contribution4 entitled “Statistical analysis of Amazon EC2 cloud pricing models,” authors Gustavo Portella, Genaina N. Rodrigues, Eduardo Nakano, and Alba C.M.A. Melo show a statistical analysis for two Amazon cloud pricing models: on demand and spot. While the on-demand cloud instances are charged a fixed price and can only be terminated by the user, with very high availability, the spot instances are charged dynamically, which price is determined by a market-driven model and can be revoked by the provider when the spot price becomes higher than the user-defined price, having possibly low availability. The analysis for on-demand instances resulted in multiple linear regression equations that represent the influence of the characteristics of the processor and RAM memory in the composition of the price of different types of instances available on the Amazon EC2 provider. To analyze the Amazon spot pricing, the authors used time-smoothed moving averages by 12-hour periods, aiming to provide a price-availability trade-off to the user. With an extensive experimental evaluation, the authors conclude that the user's bid can be set at 30% of the on-demand price, with an availability above 90%, depending on the instance type. Also dealing with GPU computing, in the contribution5 entitled “DTM@GPU: characterizing and evaluating trace redundancy in GPU,” authors Leandro A. J. Marzulo, Alexandre C. Sena, Alexandre S. Nery, Cristiana Bentes, Igor M. Coelho, Maria Clicia S. de Castro, Saulo T. Oliveira, Tiago A. O. Alves, and Felipe M. G. França explore the concept of instruction reuse in GPUs. They propose the DTMGPU model that adapts the DTM (Dynamic Trace Memoization) technique to the NVIDIA GPU architecture. The proposed model considers the particularities of the GPU architecture in the reuse mechanism. Instruction reuse can be of two types: intra-thread and inter-threads. The authors perform a detailed investigation on the characteristics of the reused traces. This characterization shows the number and size of the reused traces, the influence of the cache size on reuse rates, and the cycles that are saved when all threads in a warp reuse instructions or traces. The results show approximately up to 35.3% of reuse, yielding an estimated speedup gain of 10.7%. Dealing with parallel and dataflow models, the paper6 entitled “DF-DTM: Dynamic Task Memoization and reuse in dataflow” and authored by Leandro Rouberte, Alexandre C. Sena, Alexandre S. Nery, Leandro A. J. Marzulo, Tiago A. O. Alves, and Felipe M. G. França also discusses instruction reuse and the DTM (Dynamic Trace Memoization) technique, but in a different environment, a Dataflow System. The authors propose the Dataflow Dynamic Task Memoization (DF-DTM) technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF-DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. This work also evaluates how reuse rates can be affected by limiting the subgraph size, memoization table size, task granularity, and problem size, showing that DF-DTM can yield good reuse rates in more realistic environments. Finally, considering GPU issues, the paper in this Special Issue,7 “Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs,” authored by Thiago Nasciutti, Jairo Panetta, and Pedro Lopes, presents a performance study on different optimizations for 3D stencil computations on GPUs. The focus is on memory-oriented optimizations with varying grid and stencil sizes. The optimizations reduce global memory contention caused by the set of multiprocessors. The optimizations evaluated are grid tiling, inserting spatial and temporal loops into kernels, register reuse, and some of their combinations. A standardized experiment evaluates performance variation with grid size and stencil size for each optimization. Experimental data show that codes that use these optimizations are up to 3.3 times faster than the classical stencil formulation and that the optimization degree depends on the grid and stencil sizes. We hope that the readers can benefit from the perspectives presented in this Special Issue. The topics covered in the papers are timely and important, and the authors have done an excellent job in presenting their innovative contributions. Regarding the reviewing process, our referees (integrated by recognized researchers from the international community) made a great effort in evaluating the papers. We would like to acknowledge their effort in providing us with excellent feedback at the right time. Therefore, we wish to thank all the authors and reviewers. Finally, we would also like to express our gratitude to the Editor in Chief of this Journal, for his advice, vision, and support.