Reviewerly/exHarmony huggingface dataset:
Visualization Dashboard for Recommending Attack Patterns Using Topic Modeling

The Common Attack Pattern Enumeration and Classification (CAPEC) database is a great resource that software developers can consult to gain a deeper understanding of techniques used by attackers to exploit the vulnerabilities of a software. Attack patterns define the steps and perquisites needed for an attacker to exploit a system and include mitigations for the given attack pattern. However, the time required to manually search and find relevant attack patterns can quickly become a time-consuming process. We utilize topic modeling to recommend attack patterns relevant to software requirement specifications. This paper introduces a visualization dashboard for recommending CAPEC attack patterns using topic modeling. The tool allows the user to upload a software requirements specification document and select the topic modeling algorithm. The most relevant attack patterns will be returned to the user through visualization. This tool helps developers make use of CAPEC attack pattern efficiently.
Authentication System and Authorization System Using Blockchain Technology

Blockchain technology has experienced a tremendous increase in popularity in recent years due to its potential to change a number of industries, including finance, healthcare, and logistics. One of the key features of blockchain technology is its capacity to provide safe authentication and permission. In order to maintain and verify identities and rights, traditional authentication and authorization techniques rely on a centralised authority. However, this strategy has a number of shortcomings, including single points of failure, security flaws, and constrained scalability. A decentralised, secure method of maintaining identities and permissions is provided by blockchain technology. The development of a transparent, impenetrable record of all transactions and data is made possible by blockchain technology. The positives of adopting blockchain technology for authentication and authorisation over more traditional methods are examined in this article, along with its cons and potential applications. This study contributes to the evolving discourse on blockchain technology by specifically examining its applications in authentication and authorization systems. By investigating the strengths and weaknesses of this decentralized approach, we aim to provide valuable insights for researchers, practitioners, and decision-makers seeking to harness the full potential of blockchain in enhancing security and transparency in identity management.
Offline Digital Signature Validation Model with Enhanced Time-Stamping

The growing advantage of digital signature has raised an increasing interest in government entities as well as in enterprises to integrate digital signature within their workflows specially with the Egyptian government plans of digital transformation, however this transformation is faced by many challenges, in this paper we will focus on two of the main technical challenges and threats facing digital signature systems the first challenge is offline environments , some government entities and highly secured facilities enforce security regulations that prevent users from having access to the internet , that is a huge challenge when it comes to digital signature validation. Another challenge is the lack of a technically viable way to determine the exact time- of the digital signature creation with accurate precision. This paper is an approach for addressing these two problems [1].
Spam Email Detection using Deep Learning Techniques

Anything that is connected to the internet is vulnerable, for example mobile phones, personal laptops, tablets, routers, and smart speakers. Cybercriminals need one point of weakness like unprotected devices or a weak password or any attachment to potentially enter into the system. There is a need to pause before proceeding with any mail or downloading any document or accessing any link in a message because there is a risk of phishing. Every day 320 billion spam emails are sent to many people. According to statistics of spam mail, it was noted that out of every 3000 emails, 1 mail is spam that contains phishing links, malware, fake messages, fake offers, etc. The hacker tries to get confidential information about people, companies, and bank account details. In 2023, Spam mails are still a big real-life problem because some people are still not aware of spam emails and they aren’t able to detect spam mail manually. So, there is a need for the development of a spam detector system that can detect spam emails with higher accuracy. In this paper, there will be a discussion about implementation, execution and obtained results of deep learning algorithms like LSTM (one-directional), BiLSTM (Bi-directional), BERT, and Convolution Neural Networks using a dataset that was downloaded from Kaggle. An accuracy of 98% was obtained with the CNN, 96% was obtained with the LSTM (one-directional) model, 97% with the BiLSTM (Bi-directional) model, and 99% was obtained with the BERT model. The best accuracy ‘of 99%’ with great recall value, less precision, and a great F1 score was attained by implementing the BERT model for spam detection. Keywords-Deep Learning, CIA, SIANN, RFC
How Blockchain Disrupts Business Model Innovation Counting on Lock-In Effects

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A Comprehensive Review on Anomaly Detection in Images: Challenges and Future Research Directions

Identifying irregularities in data, or "anomalies," is essential in several fields, like medical imaging, intrusion detection (ID), fraud detection (FD), etc. A brief review of various approaches and methods presented by numerous researchers is presented in this paper. These approaches range from transformer models to image filters, autoencoders to low-rank representation, vision transformers to isolation forests, and convolutional autoencoders to deep neural networks. The primary goal of these methods is to capture the anomaly in the images. The significance of anomaly detection in numerous other applications viz. healthcare, cybersecurity, and industrial control systems are also highlighted in the paper and it also provides a brief insight into a variety of machine-learning methods to accurately detect anomalies.
A Max Pooling Hardware Architecture Supporting Inference And Training For CNN Accelerators

Hardware accelerators optimized for CNN model are being researched to process the increasing amount of computation with the advancement of CNNs. Most CNN accelerators for mobile devices only support inference and are designed with a focus on convolutional layer. However, existing accelerators in mobile devices often lack the ability to perform on-device training, limiting their potential for adaptive learning. In this paper, we propose a hardware design for max pooling, one of the main operations of CNNs, to support inference and training. The proposed hardware is designed as a parallel structure to perform inference and training in real-time. In addition, the ReLU activation function can be per-formed without additional hardware design.
Efficient Object Detection through Migration-Based Neural Architecture Search

Neural Architecture Search (NAS) has revolutionized network design by automating the search for optimal architectures, albeit often requiring substantial computational resources. This paper introduces a novel approach to mitigate this challenge by strategically shuffling channel depth and masking less critical channels during the search process. Subsequently, the discovered backbone is migrated to an object detection network and fine-tuned, circumventing the need for training from scratch. This innovative method yields competitive results in terms of mean Average Precision (mAP), parameters, and Floating Point Operations Per Second (FLOPs), aligning with conventional hand-designed methods and existing NAS networks.
Considerations in Evaluation of Deep Hashing Networks for Information Retrieval System

Deep hashing is a method utilized in information retrieval systems, involving learning hash functions using deep neural networks. Mean Average Precision (mAP), a popular metric for evaluating hashing models, faces critical challenges in providing reliable performance scores. Despite the development of recent metrics like Mean Local Group Average Precision (mL-GAP) and Radius Aware Mean Average Precision (RAMAP), only a limited number of papers evaluated their hashing algorithms using these metrics. In this paper, we compare the performance of common deep hashing models using various evaluation metrics for precise comparison.
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis

A cryptographically secure pseudo-random number generators (CS-PRNG) is a key building block in many privacy-enhancing techniques such as differential privacy, cryptography, and secure multi-party computation, so designing an energy-efficient CS-PRNG is essential to make energy-constrained embedded devices secure. This paper presents four different types of energy-efficient CS-PRNGs designed in a 28nm CMOS process using high-level synthesis (HLS). Thanks to HLS, design space is efficiently explored by sweeping the microarchitectural parameters through which the optimal implementation is found. Performance of the designed CS-PRNGs is found to be comparable to that of prior art based on manually coded RTL implementations.
Distance Searching-based Hyperparameter Optimization for Restricted Coulomb Energy-based Neural Network

In this paper, we propose an optimal hyperparameter searching algorithm for the restricted coulomb energy (RCE) network-based classification algorithm. The proposed algorithm analyzes the input data to compute the distances between their features belonging to different classes. Based on these computed distances, the algorithm obtains the minimum and maximum distance values, which are then set as hyperparameters. To evaluate the performance of the proposed algorithm, we conducted experiments using benchmark datasets and compared its performance against a full search approach for hyperparameter settings. The results demonstrate that the proposed algorithm outperforms the full search method.
Twiddle Factor Generator Architecture for Number Theoretic Transform

The computational complexity and the large off-chip memory access of the Number Theoretic Transform (NTT) in Fully Homomorphic Encryption (FHE) are the most dominant processes in terms of the overall execution time. Furthermore, it becomes even more complicated with the Residue Number System (RNS) due to the requirement of multiple executions with different moduli. Therefore, modern RNS-based homomorphic encryption hardware architectures need the twiddle factor sets to be frequently changed from off-chip memory. To address this problem, this paper proposes an FPGA implementation of a twiddle factor generator for NTT, which can reduce off-chip memory access for different twiddle factor sets.
Enhancing Performance and Energy Efficiency of Reconfigurable CNN Accelerator

This paper aims to improve the performance, area, speed, and energy efficiency of Convolutional Neural Network(CNN) Accelerator while retaining the accuracy level suggested in [2]. The accelerator is made up of four Diagonal Cyclic Arrays (DCAs), which are a type of systolic array of Processing Elements (PEs). To obtain the enhanced accelerator architecture, we present the following three design optimization methods: decreasing the number of FIFO modules in PEs, minimizing the quantization block size, and modifying the data format for efficient access of DDR DRAM. Compared to the previous CNN Accelerator [2], the proposed architecture based on the three methods has been reduced the FPGA LUT usage by 28.77%, the Flip-Flop count by 6.30%, the Block RAM size by 31.75%, and the DSP usage by 2.41%. In addition, the computation speed has been accelerated by 23% compared to the previous architecture.
Efficient Layout Pattern Matching Based on Local Information

Pattern matching is a widely used technique in IC physical verification. As the circuit feature size shrinks and the complexity of the pattern grows, the searching and matching process for layout pattern matching becomes increasingly time-consuming. To address this issue, a more efficient layout pattern matching method that takes into account the specific characteristics of the layout is developed. Our method first partitions and groups layout patterns, and then utilizes an efficient memory model to store rectangular data. Secondly, features of layout patterns are considered, and local information about the pattern is used for filtering and matching. Furthermore, multi-threading is employed to further improve the algorithm’s efficiency. Experimental results demonstrate that the proposed method achieves a speedup ranging from 2.0× to 3.8× when compared to the most advanced pattern matching algorithm and even higher acceleration when compared to other approaches while maintaining a query success rate of 100%. These results highlight the effectiveness and superiority of this method for layout pattern matching in the physical verification of integrated circuits.
Design and Implementation of a Special Operator for Neural Networks Based on Noise Reduction and Super Resolution

This paper designs and implements a dedicated operator called FUSE, which implements the function of image fusion in any channel and is applied to the noise reduction and super-resolution neural network designed by Witmem. The FUSE operator we designed uses 32 parallel pipeline calculations, which are internally divided into two clock domains based on the proportion of input and output data volume. We design an algorithm to search for weight address index, making the FUSE operator applicable to images of any size. Under the 28 nm standard CMOS technology, We propose the architecture of the operator and implement the hardware design. FUSE’s area is 236460.2 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , interface frequency is 1GHz, internal working frequency is 500MHz, and the throughput is 13.7GOPS when image channel is 3.
A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture

Different modes of convolution, as the main operations of convolutional neural networks, determine the efficiency of the entire network. This paper proposes a multi-mode convolution coprocessor based on the RISC-V instruction set in order to accelerate convolution operation. In the coprocessor, a round-based convolution unit and dataflows for different convolution modes are designed to reduce memory access frequency. A custom instruction subset based on RISC-V ISA is designed, and the common convolution algorithm is implemented on the coprocessor. Finally, performance analysis and resource consumption evaluation of the coprocessor are completed on a Xilinx FPGA. Implementing different modes of convolution based on the designed instruction subset takes fewer cycles than using the standard instruction set. And the acceleration ratio of pointwise convolution is 8.74 times that of the standard instruction set.
A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation

With the rapid advancement of deep neural networks, the automatic generation of accelerator design is a very important problem for the deployment of AI applications, especially for edge computation. In this paper, we propose a general purpose compiler design for instruction-based CNN accelerator design. Our compiler incorporates network pruning and quantization capabilities for better performance. CDFG-based layer fusion and scheduling are used for heterogeneous computing with consideration of data transformation and synchronization between CPU and accelerator. A device file is used to define the instruction set and data space so that our compiler supports various accelerator designs uniformly. We used our compiler to implement VGG16 and yolo2 in FPGAs and achieved better performance than existing designs.
An Optimized Dataflow Based Accelerator for Sparse Convolutional Neural Networks

Field-programmable gate arrays (FPGAs) have emerged as a highly promising hardware platform for accelerating convolutional neural networks(CNNs) inference. However, most existing accelerators focus on dense or sparse structured CNN models and fail to fully exploit the inherent sparsity in CNNs. To address this limitation, we propose a reconfigurable accelerator for sparse CNNs. The irregularity caused by sparsity presents challenges in hardware implementation, including load imbalance and on-chip buffer access conflicts. To overcome these challenges, we propose a convolution-decomposition dataflow that transforms the spatial convolution into matrix-vector multiplication, thus effectively leveraging the sparsity of activations and weights. Then we introduce a bitmap-nonzero encoding scheme that matches the dataflow, resulting in lower decoding overhead during the nonzero detection process. Moreover, to mitigate load imbalance, we designed a reconfigurable processing element(PE) array where each PE operates independently, ensuring a high PE utilization. Experiments demonstrate that our accelerator achieves a high performance of 202.68 GOPs and a DSP efficiency of 1.583 GOPs/DSP for VGG-16 on Intel Arria10 SX660 platform, which provides an 8.79× speedup over dense CNN accelerator and a DSP efficiency improvement of 1.39× ~ 2.24× over previous sparse CNN accelerators.
UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN

Convolution Neural Networks (CNN) and Transpose Convolution Neural Networks (TCNN) play a significant role in deep learning and has a wide range of application in algorithms such as generative adversarial networks (GAN), U-Net based image segmentation networks, super-resolution networks. However, TCNN has a completely different computational mode from CNN, which poses a significant challenge for designing a unified architecture for both CNN and TCNN. Some former researchers have proposed several hardware architectures, but they introduce massive hardware overhead and reduce energy efficiency, which can be a significant problem in low-power embedded applications. To alleviate this problem, we propose UACT, an energy-efficient unified Architecture of CNN and TCNN, co-designed with a unified approach for CNN and TCNN address generation. UACT is designed and evaluated under TSMC 28nm library, which costs 655 K logic gates and 128 KB SRAM, with a power of 106.7 mW and a throughput of 117.8 GOPS at 1GHz, achieving an energy efficiency of 1104 GOPS/W, which is more efficient than previous state-of-the-art TCNN processors.
DSSMNeRF: Depth Self-supervised MVS NeRF

Due to the inability of capturing enough scene-specific details, existing view synthesis algorithms suffer largely from the trade off between the high-frequency information and the requirement of matching appropriate hyperparameters for different datasets. In this paper, we propose a novel Depth Self-supervised MVS NeRF (DSSMNeRF). As a generalizable model, DSSMNeRF learns geometry priors across different scenes and captures high frequency appearance in a single scene through self-supervised training, using only 3 images and depth maps. DSSMNeRF extracts geometry-aware features through plane-swept cost volumes, and then synthesizes diffuse color, blending color and final color sequentially. For self-supervised training, we propose two new loss functions, re-synthesis loss and pseudo-supervision loss, to provide pixel-level self-supervision at any viewpoint. And, to filter out the inappropriate supervisions, occlusion mask and blending mask are applied before computing pseudo-supervision loss. We validate DSSMNeRF on different scenes of the DTU dataset. Experimental results show that, in comparison with its peer works, DSSMNeRF reaches the best PSNR (19.19) in the three input views setting.
DFNet: Towards Real-Time Semantic Segmentation with Depthwise Separable Convolution

Semantic segmentation refers to assigning a category label (such as pedestrian, car, building, road, sky) to each pixel in the image to help the computer understand the content of the image and conduct subsequent processing, such as the automatic driving car to identify roads, vehicles, pedestrians from the acquired images to make correct driving decisions, or help doctors diagnose diseases in medical image analysis. It also can provide semantic information for robot navigation. Running semantic segmentation algorithms in edge devices requires powerful hardware performance, most of the current deep neural networks is large, which seriously limits their application and deployment in practical scenarios. For this purpose, we propose a new convolutional network architecture named DFNet, which employ dilated convolution and depthwise separable convolution into segmentation networks, aiming to find the best balance between accuracy and speed. Tests on cityscapes dataset show that our model is almost as accurate as UNet, but model parameters are reduced by 4 times and the segmentation speed is increased 75%.
Neighborhood-based User Preference Modeling for Conversational Recommender Systems

In this paper, we propose a new end-to-end framework called NUPM (Neighborhood-based User Preference Modeling). In order to enrich the item information and better understand the user intent, we highlight that similar neighbors are essential sources of user preference except for dialogue history in a conversational recommender system. Specifically, we extract sentiment-consistent words and entities, then introduce the neighborhood-based user preference modeling process, performing knowledge-enriched and neighborhood-based recommendations for item suggestions. Finally, we adopt an encoder-decoder based on standard Transformers for response generation. Experiments on the public dataset have shown the effectiveness of our method on both the dialogue system and recommender system.
Multi-Label Text Classification Based on Multi-Task Dynamic Decoding

Recent advances in deep learning-based multi-label text classification methods have shown substantial progress in both theoretical research and practical applications. However, current studies rely exclusively on threshold-based decoding methods to interpret the model-generated label probabilities. This approach overlooks valuable information about the number of labels within a given text, leading to the prediction of numerous irrelevant labels and ultimately compromising the model's classification performance. To address this issue, we propose a novel approach, the DDA-RoBERTa model, which leverages the probability vectors for dynamically decoding labels in a multi-task architecture. Our model employs the RoBERTa model to generate document representation vectors. Simultaneously, we model two tasks: multi-label text classification and label quantity classification. By asynchronously and dynamically decoding the label probabilities generated by the multi-label text classification task using the predicted results of the label quantity classification task, we take into account latent label quantity information within the text, resulting in improved classification performance. Furthermore, we introduce a learnable loss function based on the homoscedasticity-uncertainty assumption to balance the training scale across multiple tasks. Our experimental results on English public datasets, such as Reuters-21578 and AAPD, demonstrate significant enhancements in the overall F1 value for the model's performance, with an increase of 0.30% and 1.94%, respectively, compared to the RoBERTa model. Additionally, recall improved by 1.76% and 4.38% for these datasets.