Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach

AbstractMultipliers are widely used in various fields of engineering, and they are considered to have complex designs. The efficient design of multipliers to meet various design requirements is still an active area of research. In this paper, a thermo-inspired metaheuristic called population-based simulated annealing algorithm, for the design of multipliers using four different resource types, is proposed. Metaheuristics suffers from the problem of scalability and non-convergence as the size and complexity of the circuit increase. Four types of partitioning approaches- output, input, input-output and hybrid-output partitioning are proposed to overcome the same. Proposed partitioning approaches have increased the success rate and reduced the time to realize the circuit. The multipliers designed are synthesized on Cadence Genus with 90 nm technology and compared with traditional designs such as Array, Wallace tree, Dadda and Booth multipliers to conclude that metaheuristics are capable of generating near-optimal solutions in terms of power, area and delay.KEYWORDS: AreaConventionalDelayMetaheuristicMultiplierOptimizationPartitioningSimulated annealingSynthesis Disclosure statementNo potential conflict of interest was reported by the author(s).Additional informationNotes on contributorsPavitra Y.J.Y J Pavitra obtained her BE degree in ECE from Kuvempu University, MTech from Visvesvaraya Technological University, Belgaum and currently pursuing PhD degree in EEE from VTU, Belgaum. She has been serving as assistant professor in the Department of Electronics and Communication at PES University since 2007. She has filed two patents and has published eight papers in International Conferences. She has secured 2nd rank in the University for MTech Degree. Her areas of interest lie in the optimization of digital circuits and embedded system.Jamuna S.S Jamuna has been working as a professor in the department of ECE, Dayananda Sagar College of Engineering, Bangalore, India since 2008. She has done MTech in VLSI design and embedded systems from VTU, Belgaum and PhD from JNTU, Hyderabad. Her research domain includes VLSI design, verification and testing. Recently she has executed a DRDO-funded project as principal investigator. Email: jamuna-ece@dayanandasagar.eduManikandan J.J Manikandan obtained his BE degree in ECE from Madras University, ME in communication systems from National Institute of Technology (NIT), Trichy and PhD degree in ECE from NIT, Trichy. Before pursuing his PhD, he served as project trainee at Indian Space Research Organization (ISRO) and as a scientist at DRDO [Aeronautical Development Agency (ADA)], Bangalore, for 6 Years working on electronics for LCA aircraft and spacecraft systems. Currently he is working as a professor with the Department of ECE and Director of Crucible of Research and Innovation (CORI) and Center for Research in Space Science and Technology (CRSST). He has filed seven patents and has published 100+ papers in International Journals/ Conferences with 750+ citations received for his research papers. Three of his research papers published in reputed International Journals were listed in the Top 25 hottest articles ranking 3rd (IET Signal Processing), 8th (Elsevier Microprocessor and Microsystems), and 22nd (Elsevier Neurocomputing) and has received a couple of best paper awards too. He received the Best PhD thesis award for the year 2012–2013 from the Board for IT Education Standards, followed by the Young Engineer Award from the Institution of Engineers (India) in the year 2013, IETE Biman Behari SenMemorial Award in the year 2015 from the Institution of Electronics and Telecommunication Engineering (IETE) and the Best MTech Thesis Award to Research Supervisor for the year 2021 from Indian Society for Technical Education (ISTE). He has worked on various funded projects fromISRO,DRDO, AICTE, etc in the areas of wireless power transfer systems, electronic nose, wireless sensor networks, reconfigurable computing, FPGA and microcontroller based system design. Email: manikandanj@pes.edu