Reviewerly/exHarmony huggingface dataset:
Exploring Discriminability of Categorical Anchors for Heterogeneous Domain Adaptation*

Heterogeneous Domain Adaptation (HDA) is an attractive task generalizing a model across source domain and target domain with distinct distributions and features. Previous HDA approaches have revealed the effectiveness to obtain shareable features between heterogeneous domains by benefiting from the pseudo labels of target data. Unfortunately, there are two primary limitations in the existing heterogeneous domain adaptation methods. Firstly, target pseudo labels are a two-edged sword to feature alignment. Secondly, The decision boundaries are not adequately discriminative since the margin among different categories of the target domain are not explicitly maximized. In this paper, we propose an HDA method that unifies categorical anchors of the target domain to align the feature distribution between domains and avoid direct utilization of target pseudo labels. Specifically, the intra-class feature variance and the interclass feature variance between source and target domain are simultaneously optimized to learn shared discriminative features. The margin among different categories of the target domain is explicitly maximized to make the decision boundaries clearer. To reduce the bias of limited supervision of target domain, this paper proposes to select the categorical anchors in the shared subspace to boost the performance of classifier since they are reliable to characterize the distribution of different categories. Comprehensive experiments verify that the proposed method can gain remarkable margins over state-of-the-art visual domain adaptation methods.
TensorRT Implementations of Model Quantization on Edge SoC

Deep neural networks have shown remarkable capabilities in computer vision applications. However, their complex architectures can pose challenges for efficient real-time deployment on edge devices, as they require significant computational resources and energy costs. To overcome these challenges, TensorRT has been developed to optimize neural network models trained on major frameworks to speed up inference and minimize latency. It enables inference optimization using techniques such as model quantization which reduces computations by lowering the precision of the data type. The focus of our paper is to evaluate the effectiveness of TensorRT for model quantization. We conduct a comprehensive assessment of the accuracy, inference time, and throughput of TensorRT quantized models on an edge device. Our findings indicate that the quantization in TensorRT significantly enhances the efficiency of inference metrics while maintaining a high level of inference accuracy. Additionally, we explore various workflows for implementing quantization using TensorRT and discuss their advantages and disadvantages. Based on our analysis of these workflows, we provide recommendations for selecting an appropriate workflow for different application scenarios.
Revealing Secret Key from Low Success Rate Deep Learning-Based Side Channel Attacks

Non-profiled deep learning-based side channel attacks utilize deep neural networks to extract highly accurate sensitive information. These attacks pose a significant threat to the security of cryptographic devices. Unlike profiled attacks, non-profiled attacks do not require prior knowledge of the target device, making them more versatile. Deep learning algorithms enable attackers to learn complex relationships between side channel signals and secret information, enabling the recovery of cryptographic keys, even the common SCA countermeasure deployed. However, non-profiled DLSCA can not reveal the secret key if the correct key’s metric is not clearly distinguished from the incorrect candidates. This paper discusses the mentioned issue of non-profiled DLSCA. Then, a new metric based on the inversion of exponential rank (IER) is proposed to enhance the performance of these attacks. The experimental results show that the proposed technique could reveal the secret subkey even if the partial success rate percentage is only 10% in the ASCAD dataset. Furthermore, when utilizing minimally tuned models and IER metric to execute attacks on the CHES-CTF 2018 data, there is a substantial increase in the percentage of correctly revealed bytes, rising from 62.5% to 93.75%.
FPGA Accelerated Decentralized Reinforcement Learning for Anomaly Detection in UAV Networks

As cyber-threats become more adaptive, the need for an intelligent defense network increases. Reinforcement learning, a subset of machine learning, provides a method for abstracting relationships that may be difficult to define mathematically. Specifically, a reinforcement learning network learns the environment as opposed to the data in the environment. In this paper, reinforcement learning is used to create an intrusion detection system (IDS) for Unmanned Aerial Vehicles (UAVs). A Deep-Q Learning approach is used for training, and the CICIDS2017 data set is used for generating training data. Xilinx’s Vitis-AI toolkit is used to accelerate the neural network trained onto an field-programmable gate array (FPGA), which can realistically fit on a UAV. Previous implementations train the network in this application, but do not take advantage of the hardware such as FPGA. After training, the agent is able to effectively identify between benign traffic, DDoS attacks, and port scan attacks with an accuracy of over 90%, running inference at a speed of 51.3 frames-per-second (FPS) on a AMD Ryzen 5600x CPU. Through the use of Vitis-AI, the neural network achieved 5886.85 FPS with no accuracy loss on the Xilinx Zynq UltraScale+ ZCU102 FPGA, providing a 100× increase in performance. This demonstrates the benefit of hardware acceleration when in deployed intrusion detection systems.
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing

In decentralized IoT ecosystems, four cryptographic algorithms, including SHA256, BLAKE256, BLAKE2s, and Chacha20, are principal to ensure data integrity and confidentiality. However, existing cryptographic hardware is often limited to supporting a single algorithm and suffers from low performance, which falls short of meeting the diverse requirements of these systems. To address these limitations, we introduce a reconfigurable crypto accelerator (RCA) that offers high flexibility, superior performance, and optimal hardware efficiency. Our RCA includes three novel optimizations, specifically, a homogeneous multi-core architecture, a register-adder sharing approach, and a multilevel pipeline scheduler. The RCA was successfully verified and implemented at the system-on-chip level on a ZCU102 FPGA. The real-time performance evaluation of the RCA, during the execution of various cryptographic algorithms, demonstrates an energy efficiency ranging from 94.3-160.4 Mbps/W, which is 3.1-10.5 times higher compared to modern CPUs. Experiments conducted on several FPGAs show that the RCA is higher flexibility while still outperforming previous works by 1.63-31.65 times in throughput and 1.04-2.76 times in area efficiency. Furthermore, in ASIC synthesis, the RCA exhibits exceptional throughput (48.79-92.16 Gbps), area efficiency (66.2-102.31 Gbps/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), and energy efficiency (186.22-287.8 Gbps/W), surpassing other related ASIC-based works.
Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach

Hardware-aware Neural Architectural Search (NAS) is gaining momentum to enable the deployment of deep learning on edge devices with limited computing capabilities. Incorporating device-related objectives such as affordable floating point operations, latency, power, memory usage, etc. into the optimization process makes searching for the most efficient neural architecture more complicated, since both model accuracy and hardware cost should guide the search. The main concern with most state-of-the-art hardware-aware NAS strategies is that they propose for evaluation also trivially infeasible network models for the capabilities of the hardware platform at hand. Moreover, previously generated models are frequently not exploited to intelligently generate new ones, leading to prohibitive computational costs for practical relevance. This paper aims to boost the computational efficiency of hardware-aware NAS by means of a neuro-symbolic framework revolving around a Probabilistic Inductive Logic Programming module to define and exploit a set of symbolic rules. This component learns and refines the probabilities associated with the rules, allowing the framework to adapt and improve over time, thus quickly narrowing down the search space toward the most promising neural architectures.
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags

Passive Radio Frequency Identification (RFID) tags are high-constrained devices in terms of power consumption, throughput, area, and security. While Elliptic Curve Cryptography (ECC) has commonly been used in RFID authentication protocols to address security and privacy concerns, its implementation cost does not meet the specifications of the low-cost passive RFID tags. In this paper, we proposed a low-cost low-power architecture using Binary Edwards Curves that satisfies the physical requirements of the passive RFID tags. The implementation of our proposal shows with TSMC 65nm library. Additionally, the security evaluation conducted through TVLA confirms that our implementation is resilient against popular Side-Channel Attacks.
Combining Decision Tree and Convolutional Neural Network for Energy Efficient On-Device Activity Recognition

Activity recognition and the sub-problem of motion classification can be performed by using the data provided by inertial measurements units. For many applications it is of high interest to process the data in an energy efficient manner. This can be realized by processing the data close to the sensor on a low-cost, low power embedded device. In this paper, we explore a hybrid, hierarchical architecture that combines a decision tree (DT) with a convolutional neural network (CNN). Different DTs are executed in the sensor whereas the CNN is executed on a central processing unit close to the sensor. We show to which extent the hybrid models allow to reduce the amount of required energy and how the accuracy is affected.
Fault-Tolerant Ensemble CNNs Increasing Diversity Based on Knowledge Distillation

False inference of convolutional neural networks (CNNs) can lead to serious accidents in mission-critical artificial intelligence (AI) applications such as self-driving and medical systems. It is important not only to achieve sufficient accuracy but also to detect hardware faults and continue reliable inferences. Triple Modular Redundancy (TMR) is a conventional fault-tolerant method taking the majority voting of the outputs of three identical modules. However, it increases the computational cost three times, leading to increasing the power consumption and circuit area. In this paper, we propose a computationally low-cost fault-tolerant ensemble model consisting of multiple CNN models and its training approach to improve the accuracy. Each CNN model involves a shared part that has common parameters among all CNN models. It can detect the fault of each hardware module running on each CNN model by comparing the outputs of shared parts and dynamically reconfigure the ensemble model by taking the average of the outputs only for non-faulted CNN models. In the experiments, we demonstrate that the proposed method significantly reduces the computational cost to 43% while achieving comparable accuracy and robustness.
Parallel Verification in RISC-V Secure Boot

Assuring the reliability of the OS boot process is essential to realize reliable computer systems. Secure Boot enables it by introducing the verification of the boot image with digital signature and hash values. This can be the basis for various security mechanisms. However, Secure Boot requires a long boot time due to their expensive computation costs, resulting in extended downtime. In this paper, we first implement Secure Boot in an ordinary RISC-V boot process on U-Boot, a representative open-source bootloader, and clarify the overhead introduced by the verification process. Based on the insight obtained above, we propose a parallelization of the verification process on a multi-core in Secure Boot. It accelerates the boot process while securely authenticating the boot image. We implement the proposed parallel verification process on U-Boot. The evaluation on a HiFive Unmatched RISC-V board shows that the parallelized hash computation on four cores achieves 3.96 times better performance than the original.
Hybrid Hardware-Software Architecture for Quantum Secure IoT Embedded Systems

The Internet of Things (IoT) communication prevents information from being decrypted or tampered with by unauthorized third parties. Post-quantum cryptography ensures that the information exchange between IoT devices can resist potential quantum computer attacks, thereby enhancing the quantum security of the IoT. This paper presents a quantum-secure hardware-software architecture for embedded systems. An FPGA-based post-quantum cryptographic Kyber accelerator and an STM32 microcontroller with AES encryption are integrated into the system. Customized hardware structures such as hash and modular arithmetic unit provide faster calculation speed. The command exchange protocol bridges embedded software and FPGA hardware. The server handles key generation and decryption, while the client manages encryption. AES-256 encryption is utilized to ensure the confidentiality and integrity of the data and keys, with the Kyber algorithm encrypting the session keys. Compared to previous works, this implementation demonstrates better resource utilization as well as enhanced performance in key generation, encryption, and decryption. Hardware implementation operates at 100MHz on the Artix-7 FPGA platform, consuming 20,782 LUTs, 5,077 FFs, 7.5 BRAMs, and 8 DSPs. The architecture also achieves up to 1.5× speed improvements in encryption and similar enhancements in decryption across various security levels.
LCT-TL : Learning Classifier Table (LCT) with Transfer Learning for runtime SoC performance-power optimization

Learning classifier tables (LCTs) are lightweight and classifier-based reinforcement learning building blocks in hardware that inherit the concepts of learning classifier systems. LCTs are deployed to learn and optimize potentially conflicting objectives and constraints e.g., achieving a desired performance target (IPS) under a constraint (power budget). These are reflected by the reward function which provides rewards for the LCT. A supervisor provides LCTs with the objectives/targets and constraints by translating application requirements and system policies for the LCT. The supervisor combined with the LCTs enable self-adaptive and self-optimization properties in a system-on-chip. The objectives and constraints for the LCTs are changed in runtime by the supervisor resulting in different reward functions. The LCT has to learn these different reward functions by trial and error. The rate at which the LCT learns about these changes can be accelerated by applying transfer learning. LCS systems are represented by a population of classifiers. Each classifier is made up of condition, action and bookkeeping parameters like prediction, error, accuracy, experience and numerosity which directly influence the performance of an LCT. In this work, we propose LCT-TL: LCT with transfer learning, where we propose two strategies that selectively transfer the bookkeeping parameters for a change in target/constraint. We evaluate the strategies by deploying LCTs as DVFS controllers for performance-power optimization. Experimental results show that the LCT-TL performs significantly better than the state-of-the-art LCT and a tabular Q-learning agent. LCT-TL doesn’t require any additional hardware resources and negligible soft-ware overhead.
A Many-core Architecture for an Ensemble Ternary Neural Network Toward High-Throughput Inference

Machine learning is expanding in various applications, such as image processing in data centers. With the spread of deep learning, neural-network-based models have frequently been adopted in recent years. Due to the slow processing speed of machine learning evaluation on a CPU, high-speed, dedicated hardware accelerators are often used. In particular, the demand for hardware accelerators in data centers is increasing, with a need for low power consumption and high-speed processing in a limited space. Here, we propose an implementation method for a ternary neural network, utilizing the rewritable look-up table (LUT) of a field-programmable gate array (FPGA). Ternary neural networks (TNNs), quantized to 2 bits, can be realized with LUT-based combinational circuits, allowing inference processing in a single cycle. Thus, a very high-speed inference system can be realized. Moreover, we have reduced the hardware quantity by 70% by introducing sparsity, i.e., approximating the parameters to zero. However, there was a downside of reduced recognition accuracy due to the low-bit representation. In this paper, we used an ensemble to achieve recognition accuracy equivalent to that of the 32-bit float model to prevent the decrease in recognition accuracy. We also designed a voting circuit for the ensemble TNN that does not decrease throughput. By implementing it on the AMD Alveo U50 FPGA card, we achieved a high processing speed of 100 Mega Frames Per Second (MFPS). Our FPGA-based system was 1,286 times faster than the CPU and 1,364 times faster than the GPU. Therefore, we achieve a high-speed inference system without compromising recognition accuracy.
Linguistics for Crimes in the World by AI-Based Cyber Security

Effective communication and comprehension of cyber threats in varied linguistic contexts are crucial for robust defense mechanisms in the ever-changing global cybersecurity scene. This study centers on incorporating language processing and translation technologies into advanced artificial intelligence (AI)-based cybersecurity frameworks to improve the identification and handling of cyber crimes worldwide. The frequency of cyber-attacks is steadily increasing due to the various types of online transactions, such as internet banking and shopping. Web applications are vulnerable to numerous types of attacks, such as Cross Site Scripting (XSS) and Structured Query Language (SQL) injection attacks, among others. SQL injection is a significant threat to web applications, as it allows attackers to manipulate the backend database through the server. Meanwhile, artificial intelligence (AI) and deep learning algorithms are commonly employed to detect or address various online security concerns. This paper presents various AI algorithms and compares them to determine the most optimal one.
Elderly Fall Detection System with ESP32 Module and Edge Impulse Studio

Falls are a common occurrence, particularly among the elderly, often leading to unintentional injuries and accidents that can have severe consequences, necessitating swift intervention. Individuals living alone frequently face delays in obtaining the essential emergency medical assistance they require during such incidents. Consequently, accurately detecting falls and promptly initiating emergency aid is of paramount importance. In this work, a fall detection system was developed using machine learning algorithms, utilizing data collected from the MPU6050 IMU sensor through the Edge-Impulse platform. This system automatically identifies when a person experiences a fall and promptly notifies the user or relevant individuals. The primary goal of this project is to enhance the safety of elderly and injured individuals by enabling rapid intervention during fall incidents. The system leverages Edge Impulse to streamline the development of machine learning algorithms. A dataset containing accelerometer signal recordings of five normal activities and four falling cases is constructed. A sequential neural network model was trained and accuracy of 88.29% on the test set was obtained. Further enhancements in the accuracy of the real-time system can be achieved by increasing the size of the dataset.
Classification of Sign language Using VGG16 and VGG19

The Translation System (TS) serves as a communication bridge for individuals with disabilities to interact with others in society. As computers play a vital role in our daily lives, advancements in human-computer interaction (HCI) have particularly benefited the deaf and mute community. Our proposed system aims to develop an intelligent translator that facilitates seamless communication between individuals with speech impairments and the general population. This system seeks to establish an effective and efficient means of communication for those with speaking deficiencies and regular individuals. The proposed system aims to convert sign language into written text using pre-trained models of VGG16 and VGG19, we used The Sign Language dataset consists of 27,455 training samples and 7,172 test samples, This model gave 97.5% with VGG16 and 96% with VGG19.
Comparative Performance Evaluation of Fractional Fuzzy Inference System for A High-Order System

In this study, the effect of the Fractional Fuzzy Inference System (FFIS) on the performance of the fuzzy logic-based control system was examined, with comparisons made to both a typical fuzzy controller and a PID controller. Additionally, a Genetic Algorithm (GA) was utilized to fine-tune the universe of input and output variables for the Fuzzy Logic Controller (FLC) built with FFIS. A high-order system, in which control with classical methods is considered difficult, was chosen to be employed for the performance evaluation. As a result, it has been observed that the use of FFIS in controlling the high-order system leads to a more satisfactory control performance. This study demonstrates that FFIS has the capacity to enhance performance in fuzzy logic-based control systems and can serve as a more effective control strategy.
Enhanced Preprocessing Stage For Feature Extraction of Deepfake Detection Based on Deep Learning Methods

Biometric identities are at risk of deepfake facial manipulation. Over the past few years, deepfake detection has been the subject of extensive research, most which centered on the application of machine learning strategies. However, the recognition of deepfake is still one of the most challenging problems in computer vision today. Deep learning has recently gained popularity due to its potential to solve a wide range of real-world problems, including detecting deepfakes. Our research focused on improving feature extraction methods by using deep learning and comparing preprocessing methods to show how they affect detection performance. A preprocessing approach was proposed to improve the regions of interest (ROIs) used to feed Moodle feature extraction. The proposed algorithmic approach involves finding one key frame extracted from a video by using the oriented fast and rotated brief algorithm, detecting the face oval region using the DLIB library as an ROI and performing quality improvement via contrast-limited adaptive histogram equalization (CLAHE)/adaptive histogram equalization (AHE) and comparing them. On the FaceForensics ++ dataset, CLAHE demonstrated superior performance compared with AHE with InceptionV3 as a feature extractor. The final classification result had an accuracy ratio of 89%, and the area under the curve was measured to be 77%.