Efficient VLSI architectures of lifting based 3D discrete wavelet transform

IET Computers & Digital TechniquesVolume 14, Issue 6 p. 247-255 Research ArticleFree Access Efficient VLSI architectures of lifting based 3D discrete wavelet transform M. Mohamed Asan Basiri, Corresponding Author asanbasiri@gmail.com Department of ECE, IIITDM Kurnool, Kurnool, IndiaSearch for more papers by this author M. Mohamed Asan Basiri, Corresponding Author asanbasiri@gmail.com Department of ECE, IIITDM Kurnool, Kurnool, IndiaSearch for more papers by this author First published: 18 September 2020 https://doi.org/10.1049/iet-cdt.2020.0038Citations: 1AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinked InRedditWechat Abstract Discrete wavelet transform (DWT) is widely used in the image and video compression due to its high compression ratio and resolution. This study proposes efficient very large scale integration (VLSI) architectures of lifting based 3D-DWT using (5,3) and (9,7) Daubechies wavelets. The advantage of these proposed architectures is the absence of storage buffer in between the row, column, and temporal processes. Also, five and nine numbers of frames of the 3D signal can be processed in parallel using the proposed (5,3) and (9,7) lifting based DWTs, respectively. Due to this parallelism and the elimination of storage buffers, the throughput of the proposed design is greater than other existing techniques. The authors have implemented all the existing and proposed 3D-DWTs using 45 nm CMOS library with Cadence and Artix-7 FPGA with Xilinx Vivado. The synthesis results show that the proposed designs achieve significant improvement in throughput than various existing designs. For example, the proposed (9,7) lifting based 3D-DWT achieves 85.4% of improvement in the throughput than the conventional design. 1 Introduction Wavelet transform (WT) was developed to fix the resolution problems of the short time Fourier transform and checkerboard effect in discrete cosine transform. The WT is capable of providing the time and frequency information simultaneously, hence giving a time–frequency representation of the signal. We basically need WT to analyse non-stationary signals, whose frequency response varies in time. Discrete WT (DWT) is used in the lossy compression [1] or irreversible compression (e.g. JPEG, MP3, MPEG, and so on) techniques, which permit the reconstruction only of an approximation of the original data, though this usually improves compression ratios (and therefore reduces file sizes). Lossy compression methods, especially when used at low bit rates, introduce compression artefacts. In general, VLSI architecture for DWT is classified into three categories, (i) convolution based [2]; (ii) lifting based [3, 4]; and (iii) B-spline based. If the N-point signal is 1D transformed using DWT, the output will have number of samples. Fig. 1 shows the -point 3D-DWT [5], which includes row, column, and temporal processes. The -point signal includes eight frames and each frame is of pixels. During the row process, each row of the each frame will be 1D transformed. In the column process, each row of each transposed frame of row process output would be 1D transformed. In the temporal process, each row of each aligned and transposed frame of column process output would be 1D transformed. Hence, the output of the 3D-DWT is . Fig. 1Open in figure viewer -point 3D DWT The lifting based DWT has an advantage over convolution based DWT. The low-pass (LP) and high-pass (HP) filters in convolution based DWT are replaced by upper and lower triangular matrices in the lifting based DWT and hence computation complexity is reduced as compared with the convolution based DWT. The (5,3) lifting based DWT is explained from (1) to (10). Similarly, the (9,7) lifting based DWT is explained from (11) to (19). The four-tap LP and HP filters are (1) (2) The polyphase decompositions of four-tap LP and HP filters are (3) (4) Here, and are HP and LP filter representations using Z-transform, respectively. The three-tap HP filter can be represented as (5) (6) Similarly, five-tap LP filter can be represented as (7) (8) (9) (10) The (5,3) lifting based DWT outputs are and . Here, the suffixes e and o represent sample values with even and odd positions, respectively. The seven-tap HP filter can be represented as (11) (12) Similarly, nine-tap LP filter can be represented as (13) (14) (15) (16) (17) (18) (19) The (9,7) lifting based DWT outputs are and , where and . The signal flow graph for lifting based (5,3) 1D-DWT with two levels is shown in Fig. 2. The signal flow graph for lifting based (9,7) 1D-DWT with two levels is shown in Fig. 3. The main difference between the (9,7) and (5,3) DWT is the number of multiplication constants and scaling factor. In (5,3) lifting based 1D-DWT, the number of multiplicative constants is two, they are a and b. In (9,7) lifting based 1D-DWT, the number of multiplicative constants is four, they are a, b, c, and d. The scaling factors 1/k and k are used to obtain the HP and LP outputs, respectively. Due to the additional multiplication constants, the height of the signal flow graph for (9,7) 1D-DWT is greater than (5,3) 1D-DWT. In both the signal flow graphs as shown in Figs. 2 and 3, the number of inputs is 16. The inputs are represented as x[−1], x[0], x[1], … Few zeros are appended at x[0] and x[15]. For example, x[−1] = x[16] = x[17] = 0 in (5,3) lifting based 1D-DWT. Similarly, x[−4] = x[−3] = x[−2] = x[15] = x[16] = x[17] = x[18] = 0 in (9,7) lifting based 1D-DWT. The number of outputs at the first and second levels of DWT would be eight and four, respectively. The LP outputs from the previous level would be the input of present level. The maximum number of levels of -point 3D DWT is . Fig. 2Open in figure viewer Signal flow graph of (5,3) lifting based 1D-DWT with two levels Fig. 3Open in figure viewer Signal flow graph of (9,7) lifting based 1D-DWT with two levels 1.1 Related work There are several research works available in the VLSI architectures of 3D-DWT. A convolution based 3D-DWT architecture is shown in [6], where the HP and LP FIR filters are used to perform the DWT operation. The 3D discrete Haar WT architectures are explained in [7–9]. The direct form of (5,3) lifting based 3D-DWT is explained in [10], where four adders and two multipliers are serially connected. Also, the row, column, and temporal processes use unique (5,3) filters. A similar work is shown in [11], where four-tap Daubechies 3D-DWT is used. This design accepts two input frames at a time. Hence, the throughput of [11] is greater than [10]. A set of processing elements for 3D-DWT is used in row, column, and temporal processes of [12]. The direct form of (9,7) lifting based 3D-DWT is explained in [13], where eight adders and six multipliers are serially connected. The (9,7) lifting based 3D-DWT is explained in [14], where two outputs can be obtained per cycle in parallel. Two numbers of each row, column, and temporal processors are used in the (9,7) lifting based 3D-DWT as shown in [15], where two frames can be processed in parallel. Hence, the throughput of [15] is greater than [13]. A memory efficient lifting based 3D-DWT is shown in [16], where four numbers of row processors, four numbers of column processors, and one temporal processor are used. Also, this design is flexible to perform both (5,3) and (9,7) filter operations. The flipping based (9,7) 3D-DWT is shown in [17], where the multiplicative constants are inversed to reduce the critical path depth of the design. In most of the aforementioned lifting based 3D-DWT designs, there is a requirement for the memory in between row, column, and temporal processes. Our proposed designs avoid this temporary storage. Also, the critical path depth of the most of the aforementioned lifting based 3D-DWT designs includes two adders and one multipliers. Our proposed 3D-DWT designs replace a multiplier followed by an adder with fused multiply add (FMA) [18]. The multiplier followed by an adder is to perform (AB + C), where A, B, and C are inputs. The same operation in our proposed 3D-DWT designs is done with FMA. The circuit depth of FMA is equal to the circuit depth of multiplier. Hence, the critical path depth of our proposed designs avoids the depth of an adder. Hence, the critical path depth of our proposed designs is less than the existing designs. 1.2 Contribution of this paper This paper proposes efficient (i.e. high throughput) VLSI architectures of lifting based 3D-DWT using (5,3) and (9,7) Daubechies wavelets. The benefits of these proposed architectures are high parallelism along with the absence of storage buffers between the row, column, and temporal processes. The throughput of our proposed design is greater than other existing techniques due to this parallelism and the elimination of storage buffers. In all the implementations of existing and proposed techniques of this paper, IEEE 754 signal precision floating point format (32-bit) is used, because the pixels of high dynamic range images require IEEE 754 floating point representation [19, 20]. The conventional video processing needs 30 fps (fps – frames per second). However, the ultra high speed video processing (such as video acquisition, compression etc.) in Phantom v710 video camera [21], i-speed 716 video camera, Fastcam APX-RS video camera [22], ultra high speed high efficiency video coding [23], and X-VIT LS high speed video camera [24] can process from 30 to 2,50,000 fps. Therefore, our proposed designs are highly opted in these applications. We have implemented all the existing and proposed 3D-DWTs using 45 nm CMOS library with Cadence and Artix-7 FPGA with Xilinx Vivado. The synthesis results show that the proposed designs achieve significant improvement in throughput than various existing designs. In general, the high performance design will optimise delay at the expense of area and power [25]. Therefore, the trade-offs of our proposed high throughput 3D-DWT designs are area and power dissipation. The rest of the paper is organised as follows. Section 2 elaborates the proposed lifting based 3D-DWT architectures. Design modelling, implementations, and results are shown in Section 3, followed by a conclusion in Section 4. 2 Proposed lifting based 3D-DWT architectures Let us assume the size of 3D digital signal that is going to be transformed is . The total number of frames is N and each frame is of size. Our proposed 3D-DWTs as shown in Figs. 4 and 5 contain row, column, and temporal processes. The position of the frames is represented using j. The position of the row in each frame is represented using i. The position of the sample value in each row is represented using k. Throughout our proposed implementations, we use FMA to perform the multiplication and addition. The FMA includes carry save adder tree, an adder, and a register. The circuit depth of FMA is equal to the multiplier [18]. In all our proposed designs, the critical path depth is equal to , where and are the circuit depth of an adder and FMA, respectively. The critical path depth of multiplier is . In all our proposed implementations, . Throughout this paper, the shaded boxes represent the synchronous registers. Fig. 4Open in figure viewer Proposed (5,3) lifting based 3D-DWT with one level Fig. 5Open in figure viewer Proposed (9,7) lifting based 3D-DWT with one level Fig. 4 shows the proposed (5,3) lifting based 3D-DWT with one level, where 25, 5, and 1 numbers of 1D-DWTs are used in the row, column, and temporal processes, respectively. Here, five frames can be processed in parallel. In the each frame, five rows can be processed in parallel. Hence, the total number of 1D-DWTs used in the row process is 25. The input from each of all the five frames will be sent as the input to all the 25 serial direct forms of (5,3) lifting based 1D-DWTs, where i = −1, 1, 3,…N + 1, j = 1, 3, 5,…N − 1, and k = −1, 1, 3,…N + 1. The serial direct form of (5,3) lifting based 1D-DWT is shown in Fig. 6a, which requires six cycles to produce the output. The number of FMAs, adders, registers, and multipliers used in Fig. 6a are 2, 2, 8, and 0, respectively. Therefore, the total number of FMAs, adders, registers, and multipliers used in the row process of Fig. 4 are 50, 50, 400, and 0, respectively. In Fig. 6a, the inputs are x[−1], x[0], x[1], x[2], …x[N + 1], where x[−1] = x[N] = x[N + 1] = 0. The inputs x[−1], x[0], x[1], x[2], …x[N + 1] are split into two categories. They are the input samples with odd positions (x[−1], x[1], x[3], …) and even positions (x[0], x[2], x[4], …). Each serial direct form of (5,3) 1D-DWT can produce one LP output after six cycles. Therefore, the number of LP outputs from the row process can be produced in parallel is 25. All these 25 LP outputs from the row process can be processed using five parallel direct forms of (5,3) lifting based 1D-DWTs in column process. The parallel direct form of (5,3) lifting based 1D-DWT is shown in Fig. 6b, which requires two cycles to produce the output. The number of inputs to this parallel DWT is five that are represented as in-0, in-1, in-2, in-3, and in-4. These inputs are sent from the ROW process of the proposed design as shown in Fig. 4. The number of FMAs, adders, registers, and multipliers used in Fig. 6b are 3, 3, 1, and 0, respectively. Therefore, the total number of FMAs, adders, registers, and multipliers used in the column and temporal processes of Fig. 4 are 18, 18, 6, and 0, respectively. Each parallel direct form of (5,3) lifting based 1D-DWT can produce one LP output after two cycles. Therefore, the number of LP outputs from the column process can be produced in parallel is five. All these five LP outputs from the column process can be processed using one parallel direct form of (5,3) lifting based 1D-DWT in temporal process. The temporal process will produce the sample values of the final 3D-DWT output. Since the data path of Fig. 4 can process seven set of inputs in parallel, the total number of cycles required to complete the 3D-DWT using the proposed design as shown in Fig. 4 is (20) The total number of FMAs, adders, registers, and multipliers used in the proposed design as shown in Fig. 4 are 68, 68, 406, and 0, respectively. Fig. 6Open in figure viewer Architectures of (5,3) lifting based (a) Serial, (b) Parallel 1D-DWTs with one level Fig. 5 shows the proposed (9,7) lifting based 3D-DWT with one level, where 81, 9, and 1 numbers of 1D-DWTs are used in the row, column, and temporal processes, respectively. Here, nine frames can be processed in parallel. In the each frame, nine rows can be processed in parallel. Hence, the total number of 1D-DWTs used in the row process is 81. The input from each of all the nine frames will be sent as the input to all the 81 serial direct forms of (9,7) lifting based 1D-DWTs, where i = −4, 2, 0, 2,…N + 3, j = 1, 3, 5,…N − 1, and k = −4, 2, 0, 2,…N + 3. The serial direct form of (9,7) lifting based 1D-DWT is shown in Fig. 7, which requires 12 cycles to produce the output. The number of FMAs, adders, registers, and multipliers used in Fig. 7 are 4, 4, 16, and 2, respectively. Therefore, the total number of FMAs, adders, registers, and multipliers used in the row process of Fig. 5 are 324, 324, 1296, and 162 respectively. In Fig. 7, the inputs are x[−4], x[−3], x[−2], x[−1], x[0], x[1], x[2], … x[N + 3], where x[−4], x[−3] = x[−2] = x[−1] = x[N] = x[N + 1] = x[N + 2] = x[N + 3] = 0. The inputs x[−4], x[−3], x[−2], x[−1], x[0], x[1], x[2], …x[N + 3] are split into two categories. They are the input samples with odd positions (x[−3], x[−1], x[1], x[3], …) and even positions (x[−4], x[−2], x[0], x[2], x[4], …). Each serial direct form of (9,7) 1D-DWT can produce one LP output after 12 cycles. Therefore, the number of LP outputs from the row process can be produced in parallel is 81. All these 81 LP outputs from the row process can be processed using nine parallel direct forms of (9,7) lifting based 1D-DWTs in column process. The parallel direct form of (9,7) lifting based 1D-DWT is shown in Fig. 8, which requires six cycles to produce the output. The number of inputs to this parallel DWT is nine that are represented as in-0, in-1, in-2, in-3, in-4, in-5, in-6, in-7, and in-8. These inputs are sent from the ROW process of the proposed design as shown in Fig. 5. The number of FMAs, adders, registers, and multipliers used in Fig. 8 are 10, 10, 8, and 3, respectively. Therefore, the total number of FMAs, adders, registers, and multipliers used in the column and temporal processes of Fig. 5 are 100, 100, 80, and 30, respectively. Each parallel direct form of (9,7) lifting based 1D-DWT can produce one LP output after six cycles. Therefore, the number of LP outputs from the column process can be produced in parallel is nine. All these nine LP outputs from the column process can be processed using one parallel direct form of (9,7) lifting based 1D-DWT in temporal process. The temporal process will produce the sample values of the final 3D-DWT output. Since the data path of Fig. 5 can process 21 set of inputs in parallel, the total number of cycles required to complete the 3D-DWT using the proposed design as shown in Fig. 5 is (21) The total number of FMAs, adders, registers, and multipliers used in the proposed design as shown in Fig. 5 are 424, 424, 1376, and 192, respectively. Fig. 7Open in figure viewer Serial direct form of (9,7) lifting based 1D-DWT with one level Fig. 8Open in figure viewer Parallel direct form of (9,7) lifting based 1D-DWT with one level 3 Design modelling, implementations, and results All the existing and proposed designs are modelled in Verilog HDL. The synthesis of all these designs is done with Cadence Genus and Innovus 15.20 using 45 nm CMOS technology, where the operating voltage is 0.9 V. The actual implementations (CMOS library or FPGA device) used in the reference papers for all the existing techniques are different. Due to the unavailability of those CMOS libraries and FPGA devices, the existing techniques are implemented in this manuscript as per the reference papers using the available one particular 45 nm library. Therefore, the comparisons of the existing designs with proposed techniques are valid. In all our implementations, Ip_asserted_probability and Ip_asserted_toggle_count are taken as 0.5 and 0.02, respectively. Ip_asserted_probability is the probability for the net to be one (high). For example, the tool considers all nets in the design to be at logic level 1 for total of 50% of the simulation time, and then the probability is 0.5. Ip_asserted_toggle_count is the toggle count per toggle rate unit. For example, considering a signal toggling two times in 100 ns, then the toggle rate is 2/100 = 0.02. Table 1 shows the theoretical analysis of various -point 3D-DWT architectures. Table 2 shows the performance analysis of various -point 3D-DWT architectures 45 nm CMOS technology using the Cadence ASIC design tool. Also, all the existing and proposed techniques are implemented in this manuscript as per the reference papers using Artix-7 NEXYS-4 FPGA (XC7A100T-CSG324) with Xilinx Vivado. Table 3 shows the synthesis results of various -point 3D-DWT architectures using the Artix-7 NEXYS-4 FPGA implementation. Table 1. Theoretical analysis for various (5,3) and (9,7) lifting based -point 3D-DWT architectures with one level DWT architectures Critical path depth Total cycles Total FMAs Total adders Total registers Total multipliers Temporary storage buffer size (5,3) lifting based [10] 0 — — — four-tap Daubechies in [11] 0 30 — — (5,3) lifting based [12] 0 276 239 44 (9,7) lifting based [13] 0 78 — — (9,7) lifting based [14] 0 — — — (9,7) lifting based [15] 0 30 — 48 (9,7) lifting based [16] 0 144 — — — (9,7) lifting based [17] — — — — — (5,3) proposed lifting based (Fig. 4) 68 68 406 0 0 (9,7) proposed lifting based (Fig. 5) 424 424 1376 192 0 Table 2. Performance analysis of various -point 3D-DWT architectures with one level using 45 nm CMOS technology with Cadence ASIC design tool 3D-DWT architectures Critical path delay ( in ps) Frequency, MHz Throughput, Mop/s Number of cycles (latency) Number of frames per, ms Total area, Switching power, nW Leakage power, nW PDP, fJ (5,3) lifting based [10] 4633.6 215.8 262,144 1.5 0627721.2 0742339.0 0539911.2 005941.4 four-tap Daubechies in [11] 9879.3 101.2 131,077 1.5 0608122.3 07532194.1 0509812.1 079449.3 (5,3) lifting based [12] 4633.6 215.8 087,381 25 1556411.0 33991124.3 2016866.2 166846.6 (9,7) lifting based [13] 2824.7 354.0 524,288 3 0750243.1 08337700.3 0662289.2 025422.2 (9,7) lifting based [14] 1832.2 545.7 525,312 6 0811742.1 09335119.1 0751127.4 018480.0 (9,7) lifting based [15] 4633.6 215.8 393,231 3 0679889.3 08121224.3 0567892.0 040261.8 (9,7) lifting based [16] 4633.6 215.8 131,077 13 0299788.2 05993211.1 0315501.3 029232.0 (9,7) lifting based [17] 2824.7 354.0 131,077 11 0348798.3 07755233.0 0463795.1 023216.2 (5,3) proposed lifting based (Fig. 4) 2801.0 357.0 047,186 68.5 0303561.3 06853232.0 0382695.4 020267.8 (9,7) proposed lifting based (Fig. 5) 2801.0 357.0 036,700 222 1747382.0 44747339.0 2447536.0 132192.8 Table 3. Performance analysis of various -point 3D-DWT architectures with one level using Artix-7 NEXYS-4 FPGA (XC7A100T-CSG324) with Xilinx Vivado 3D-DWT architectures Critical path delay (Tc in ns) Throughput, Mop/s No. of cycles No. of frames per ms No. of slices (≤15,850) No. of LUTs (≤63,400) No. of flip-flops (≤126,800) Switching power, W Leakage power, W (5,3) lifting based [10] 51.3 262,144 0.15 2901 11,989 44,567 0.068 0.098 four-tap Daubechies in [11] 86.7 131,077 0.18 2607 10,988 40,456 0.062 0.098 (5,3) lifting based [12] 51.3 087,381 2.28 8688 29,986 80,997 1.002 0.099 (9,7) lifting based [13] 36.1 524,288 0.21 4134 14,656 54,443 0.085 0.099 (9,7) lifting based [14] 24.2 525,312 0.24 5688 19,854 60,133 0.110 0.099 (9,7) lifting based [15] 51.2 393,231 0.30 3310 12,109 48,777 0.073 0.099 (9,7) lifting based [16] 51.2 131,077 1.19 1395 05,902 19,890 0.029 0.099 (9,7) lifting based [17] 36.2 131,077 0.85 1967 06,988 27,356 0.039 0.099 (5,3) proposed lifting based (Fig. 4) 35.4 047,186 5.38 1589 06,189 22,456 0.032 0.098 (9,7) proposed lifting based (Fig. 5) 35.2 036,700 17.42 9865 38,879 92,566 1.145 0.099 In all the implementations as shown in Table 2, IEEE 754 single precision floating point (32-bits) format has been used. Energy per operation or power delay product [26] = (switching power + leakage power) × critical path delay. Throughput is represented as mega operations per second (Mop/s). The total number of cycles required (i.e. latency) of each design in Table 2 follows the theoretical value as shown in Table 1. In 3D-DWT architecture, the first processing unit is row processor that will accept the frames of 3D-input. The number of row processors in (5,3) 3D-DWT of [10], four-tap Daubechies 3D-DWT of [11], (5,3) 3D-DWT of [12], (9,7) 3D-DWT of [13], (9,7) 3D-DWT of [14], (9,7) 3D-DWT of [15], (9,7) 3D-DWT of [16], (9,7) 3D-DWT of [17], proposed (5,3) 3D-DWT, and proposed (9,7) 3D-DWT are 1, 2, 5, 1, 1, 2, 4, 4, 25, and 81, respectively. Similarly, the number of frames that can be accepted per cycle by all the row processors in (5,3) 3D-DWT of [10], four-tap Daubchies 3D-DWT of [11], (5,3) 3D-DWT of [12], (9,7) 3D-DWT of [13], (9,7) 3D-DWT of [14], (9,7) 3D-DWT of [15], (9,7) 3D-DWT of [16], (9,7) 3D-DWT of [17], proposed (5,3) 3D-DWT, and proposed (9,7) 3D-DWT are 1, 2, 5, 1, 1, 2, 2, 4, 5, and 9, respectively. The total number of input samples values () that can be processed per cycle by all the row processors in (5,3) 3D-DWT of [10], four-tap Daubchies 3D-DWT of [11], (5,3) 3D-DWT of [12], (9,7) 3D-DWT of [13], (9,7) 3D-DWT of [14], (9,7) 3D-DWT of [15], (9,7) 3D-DWT of [16], (9,7) 3D-DWT of [17], proposed (5,3) 3D-DWT, and proposed (9,7) 3D-DWT are (), (), (), (), (), (), (), (), (), and (), respectively. The number of cycles required to send one frame to the row process is . The time required to send one frame to the row process is , where is the clock period that is available in the first column of Table 2 of this manuscript. Therefore, the number of frames that can be sent to the 3D-DWT in a second is . This formula is used to find the number of frames can be completed per ms in Table 2, where . Similarly, the number of frames that can be sent to the 3D-DWT in a second is , where . These values will not be reflected in the total number of cycles required to complete the 3D DWT operation, because the total number of cycles (as shown in the fourth column of Table 2 of this manuscript) includes the cycles for row process, cycles for column process, cycles for temporal process, and/or cycles to access the storage buffers. For example, the proposed designs as shown in [13, 15] accept three frames per ms, but their total number of cycles to complete the 3D-DWT operation is varied due to the variation in the cycles to access the storage buffers. Similarly, the proposed design as shown in [14] accepts six frames per ms, but the total number of cycles to complete the 3D-DWT operation is greater than [13, 15] due to the variation in the cycles to access the storage buffers. Our proposed architectures need one FMA and an adder in the critical path. Therefore, the critical path delay of our proposed designs is much less than the existing designs [10, 12, 15, 16], because these existing techniques need two adders and one multiplier in their critical path. Also, the critical path of four-tap Daubechies 3D-DWT as shown in [11] requires more than four adders. Therefore, the critical path delay of this design is much greater than all the other techniques. Similarly, the critical path delay of the existing designs as shown in [13, 17] require one multiplier and an adder. Since the critical path depth of FMA is equal to the multiplier, the critical path delay of these existing designs is more similar to our proposed designs. Similarly, the critical path of the existing design as shown in [14] needs an adder. Therefore, critical path delay of this existing design is much less than all the other designs. Our proposed designs as shown in Figs. 4 and 5 require 31 and 91 numbers of 1D-DWTs, whereas the other existing techniques do not require this many 1D-DWTs to perform the 3D-DWT operation. Also, the number of input pairs can be processed in parallel using the data path of our proposed designs as shown in Figs. 4 and 5 are 7 and 21, respectively. Therefore, the throughputs of our proposed designs are much greater than others. For example, our proposed (5,3) lifting based 3D-DWT design as shown in Fig. 5 achieves 91.4% of improvement in the throughput than the existing design as shown in [10]. Similarly, our proposed (9,7) lifting based 3D-DWT as shown in Fig. 5 achieves 85.4% of improvement in the throughput than the conventional design as shown in [14]. Both the proposed designs achieve this improvement in the throughput at the cost of area and power dissipation. As shown in Table 1, the number of adders and multipliers required in our proposed 3D-DWTs are greater than the existing designs. Also, the number of 1D-DWTs used in our proposed design is greater than the other existing techniques. Hence, the area and power dissipation of our proposed designs are greater than the existing techniques. The outputs of the proposed designs are obtained assuming all data are available simultaneously at the processor input. The proposed (5,3) and (9,7) 3D-DWTs require 50 and 162 input data sample values per cycle, respectively. In case of limited width interface, all the required data will not be available at the processor input. Hence, the data has to be temporarily stored in the hardware storage buffer [27]. Once the sufficient data are received, then the storage buffer can send the data to 3D-DWT hardware. Now, few cycles will be sent on pumping the data from the external environment to the storage buffer. Also, area overhead is there due to the extra storage buffer. Let us assume the number of input ports in the design is I and K is the number of bits allowed per port (e.g. K = 32 for IEEE 754 single precision format). If and , then the number of cycles required using the proposed -point (5,3) and (9,7) 3D-DWTs are and , respectively. If and , then the cycles overhead due to this limited width interface using the proposed -point (5,3) and (9,7) 3D-DWTs are and , respectively. If and , then the area overhead due to the requirement of storage buffer includes and numbers of storage cells using the proposed (5,3) and (9,7) 3D-DWTs, respectively. According to [27], each storage cell contains a D-flip-flop and a 2-to-1 multiplexer. Therefore, the overhead in the required numbers of D-flip-flops using the proposed (5,3) and (9,7) 3D-DWTs are and , respectively. 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