Напиши текст вакансии для должности "ASIC Verification Engineer (Verilog)". Название компании: "Kelly Services". Расположение: Санкт-Петербург. График работы: Полный день. Опыт работы: От 1 года до 3 лет. Ключевые навыки: 

Vacancy of the company: KellyA company that is engaged in MEMS and analog semiconductor development, is looking for a new employee.Job Summary: Develop function models for analog and mixed-signal circuit and perform full chip functional verificationResponsibilities:  Develop functional models for analog and mixed-signal circuits using Verilog or similar languages Write verification specifications based on requited test cases Top level digital verifications Develop test benches in Verilog or similar languages/environments to verify the top level functions of full chips Run verification test benches and communicate results to the team for any fixes/improvements Requirements:  BA/BS Degree or higher in electrical engineering Experience with analog and digital circuit design Understanding of Analog schematic and experience with Cadence Virtuoso Experience with digital design languages, such as Verilog/SystemVerilog Education: не имеет значенияWorking conditions:  Official registration in accordance with the Labor Code of the Russian Federation; Opportunity to work in the leading company of the industry; Work in an international company; Assistance with employee relocation; Opportunity to use English every day at work.