Напиши текст вакансии для должности "FPGA Designer". Название компании: "Синтелс". Расположение: Москва. График работы: Полный день. Опыт работы: От 3 до 6 лет. Ключевые навыки: 

Responsibilities  Design optimized digital blocks in VHDL/Verilog meeting design specifications. Run simulations to debug and verify the design. Work with verification engineers to develop test bench and verification methodology. Work with physical design team on synthesis, verification and static timing. Collaborate with system engineers, test engineers on digital specifications and debugging. Write and hold detailed design reviews. Written and oral communication with the development team regarding design reviews, code reviews, deliverables, project updates and issues.  Requirements  Solid understanding of Digital Design fundamentals. Proficiency with Verilog &amp; System Verilog RTL coding and verification. Experience with RTL Linting, Synthesis, Static Timing and logical equivalency checking (desired). Logic design, RTL coding, verification, synthesis, and timing closure. Hardware description languages (Verilog, System Verilog and VHDL).     Programming/Scripting skills with languages such as Python, TCL, and BASH. Knowledge of RF, OFDM, MIMO and transmit beamforming. Protocol knowledge in one or more of the following areas: TCP/IP, Ethernet. AMBA bus standards such as AXI, AHB, and ACE. Scripting/programming in C/C++, Tcl, Perl/Csh.