Repository: intel/rohd (dart)

Issue:
Constants in generated SystemVerilog are unsized
## Describe the bug
Generated SystemVerilog from ROHD will be unsized like `0` or `15` instead of with an explicit size like `2'b0` and `16'd15`.  This can cause anything from a lint failure to a swizzling width mismatch/misalignment.

## To Reproduce
Generate SystemVerilog with constant value assignments using `Const`.

## Expected behavior
All constants are sized.

## Actual behavior
No constants are sized.

Pull request:
## Description & Motivation

Fix #89 which caused `Const`s in `swizzle`s to break in generated SystemVerilog.

## Related Issue(s)

#89 

## Testing

Added a new test which fails without this fix.

## Backwards-compatibility

> Is this a breaking change that will not be backwards-compatible?  If yes, how so?

No, but it does change the way SystemVerilog gets printed for constants.

## Documentation

> Does the change require any updates to documentation?  If so, where?  Are they included?

No

Patch:
diff --git a/lib/src/synthesizers/systemverilog.dart b/lib/src/synthesizers/systemverilog.dart
index b43ab03aa..9c211e320 100644
--- a/lib/src/synthesizers/systemverilog.dart
+++ b/lib/src/synthesizers/systemverilog.dart
@@ -401,7 +401,7 @@ class _SynthModuleDefinition {
           assignments.add(_SynthAssignment(synthDriver!, synthReceiver));
         }
       } else if (driver == null && receiver.hasValidValue()) {
-        assignments.add(_SynthAssignment(receiver.valueInt, synthReceiver));
+        assignments.add(_SynthAssignment(receiver.value, synthReceiver));
       } else if (driver == null && !receiver.isFloating()) {
         // this is a signal that is *partially* invalid (e.g. 0b1z1x0)
         assignments.add(_SynthAssignment(receiver.value, synthReceiver));
@@ -627,7 +627,7 @@ class _SynthAssignment {
     } else if (_src is LogicValues) {
       return (_src as LogicValues).toString();
     } else if (_src is _SynthLogic) {
-      return _src.name;
+      return (_src as _SynthLogic).name;
     } else {
       throw Exception("Don't know how to synthesize value: $_src");
     }
diff --git a/lib/src/values/logic_values.dart b/lib/src/values/logic_values.dart
index a50366589..a78fed8d1 100644
--- a/lib/src/values/logic_values.dart
+++ b/lib/src/values/logic_values.dart
@@ -732,11 +732,12 @@ abstract class LogicValues {
   /// print(lv); // This prints `3b'1x0`
   /// ```
   @override
-  String toString() =>
-      "$length'b" +
-      List<String>.generate(length, (index) => this[index].toString())
-          .reversed
-          .join();
+  String toString() => isValid
+      ? "$length'h" + toInt().toRadixString(16)
+      : "$length'b" +
+          List<String>.generate(length, (index) => this[index].toString())
+              .reversed
+              .join();
 
   /// Returns the `i`th bit of this [LogicValues]
   LogicValue operator [](int index) {


Test patch:
diff --git a/test/logic_values_test.dart b/test/logic_values_test.dart
index 78cb584b5..6cf0b97f1 100644
--- a/test/logic_values_test.dart
+++ b/test/logic_values_test.dart
@@ -270,7 +270,7 @@ void main() {
       expect(
           // toString
           LogicValues.ofString('0').toString(),
-          equals('1\'b0'));
+          equals('1\'h0'));
       expect(
           // toList
           LogicValues.ofString('0101').toList(),
diff --git a/test/swizzle_test.dart b/test/swizzle_test.dart
index e1be705ea..219839543 100644
--- a/test/swizzle_test.dart
+++ b/test/swizzle_test.dart
@@ -9,8 +9,17 @@
 ///
 
 import 'package:rohd/rohd.dart';
+import 'package:rohd/src/utilities/simcompare.dart';
 import 'package:test/test.dart';
 
+class SwizzlyModule extends Module {
+  SwizzlyModule(Logic a) {
+    a = addInput('a', a);
+    var b = addOutput('b', width: 3);
+    b <= [Const(1), a, Const(1)].swizzle();
+  }
+}
+
 void main() {
   group('LogicValue', () {
     test('simple swizzle', () {
@@ -38,4 +47,20 @@ void main() {
           equals(LogicValues.ofString('xz10')));
     });
   });
+
+  group('Logic', () {
+    test('simple swizzle', () async {
+      var mod = SwizzlyModule(Logic());
+      await mod.build();
+      var vectors = [
+        Vector({'a': 0}, {'b': bin('101')}),
+        Vector({'a': 1}, {'b': bin('111')}),
+      ];
+      await SimCompare.checkFunctionalVector(mod, vectors);
+      var simResult = SimCompare.iverilogVector(
+          mod.generateSynth(), mod.runtimeType.toString(), vectors,
+          signalToWidthMap: {'b': 3});
+      expect(simResult, equals(true));
+    });
+  });
 }