Medium-scale integrated circuits based on p-type 2D semiconducting MoTe_2

Domain: physics
Published: 2026-03-23
Editorial outcome: minor_revision

Abstract
Two-dimensional (2D) semiconductors hold promise for next-generation electronics, yet the lack of scalable p-type counterparts remains a major bottleneck, with prior studies largely limited to discrete devices or simple circuits. Here we report the realization of medium-scale integrated circuits (MSICs) based on wafer-scale p-type 2D semiconductors, enabled by the controlled synthesis of uniform 4-inch 2H-MoTe films. A precursor-engineering strategy that integrates thickness-tunable Mo precursors with a sustained-release chalcogen supply enables deterministic thickness control and wafer-scale uniformity. The resulting p-type transistors exhibit highly reproducible characteristics, including on/off ratios of ~105 and mobilities of ~7 cm2 V-1 s-1under low operating voltages. Leveraging a device density exceeding 1300 cm-2, we demonstrate a 140-transistor full adder, showing the potential of our approach towards the realization of future large-scale 2D complementary metal-oxide-semiconductor (CMOS) circuits.

Introduction
The relentless scaling of silicon transistors now faces fundamental or fabrication limits, driving urgent exploration of alternative channel materials for next-generation integrated circuits (ICs)1, 2, 3. Among emerging candidates, two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as promising materials due to their dangling-bond-free surfaces4 superior electrostatic control5, 6 and generous band structures7, 8, offering improved device performance, energy efficiency and circuit functionality1, 7, 9. While n-type 2D TMDs (e.g. the MoS ) 4, 5, 6, 7, 10, 11, 12, 13, 14 have achieved wafer-scale synthesis 13, 14 (up to 12-inch), high-performance device construction12, 15 and functional circuit integration with over 1,000 transistors12, 13, 14, 15, 16, their p-type counterparts remain trapped in a discrete device level demonstrations despite years of efforts.

Recent progress in metal-organic chemical vapor deposition (MOCVD) has enabled 2-inch tungsten diselenide (WSe ) epitaxy14, 15, and tellurization strategies produced 2H-MoTe films with promising individual-device metrics17, 18, 19. However, as with all p-type 2D semiconductors, there exists a substantial gap between the emerging demonstration—be integrated with only several discrete devices (or even of single device)8, 20, 21—and industrial ICs that comprise at least hundreds of transistors. From the standpoint of integrated circuitry, there are three fundamental challenges need to be simultaneously addressed for transitioning the p-type 2D devices from proof-of-concept devices to functional ICs.

(i) Manufacturability: Current p-type 2D-TMD demonstrations (e.g., WSe , MoTe ) are typically confined to dimensions only at a few millimeters or centimeters, which is impractical and ineffective for industry standards8, 20, 21, 22, 23, 24, 25, 26. Within the IC industry, 2D semiconductors must be scaled up to match industry-standard substrate sizes of 100 mm or larger in diameter 1, 9, 13, thereby enabling high-throughput manufacturing processes that are economically viable and scalable for commercial applications.

(ii) Device performance: While p-type transistors fabricated from mechanically exfoliated or single-domain-sized 2D TMD flakes have demonstrated exceptional electrical characteristics, however, their wafer-scale synthesized counterparts typically suffer from compromised performance metrics - including limited current on-off ratios, and high operating voltages (generally reaching tens of volts). This performance gap is primarily attributed to insufficient electrostatic gate control in these p-type 2D transistors 21, 26, 27. These characteristics suggest more intensive efforts are necessary in device engineering to refine the large-scale 2D transistors, such as scaling down the thickness of the 2D semiconducting channel and the oxide thickness.

(iii) Uniformity and integration density: Previous attempts to integrate 2D TMDs into circuits have frequently utilized materials that are not air-stable 5or have had to rely on fabrication processes incompatible with commercial industrial facilities (e.g. the transfer printing of contacts and dielectrics)25, 28, 29. These factors would lead to substantial challenges in process control, robustness, and reproducibility of p-type 2D semiconducting devices, thereby significantly hindering their potential for large-scale and high-density integration (present 2D circuits utilize p-type transistors are in the scale of only a few discrete devices8, 20, 21, 22, 23, 24, 25, 26).

In this article, we address these challenges through a co-optimization approach: (i) Controlled Material synthesis: sustained-release Te precursor engineering combined with ultrathin metal precursor deposition enables 4-inch 2H-MoTe growth with great uniformity and thickness-controllability. (ii) Device engineering: Scaling down the semiconductor and oxide thickness to enhance the electrostatic control, enabling p-type 2D transistors with large current on/off ratios of (1.29±0.36)×105 and 4V operation voltages. (iii) Utilizing highly-controllable fabrication processes to yields 1,346 transistors/cm2 device density and performance uniformity (standard deviation in threshold voltage of 42.71 mV). The achieved uniformity parameters are superior than the most reported 2D transistors and even comparable to the state-of-art silicon-based transistors in foundries. In summary, the key advances of this material growth are the scaling of uniform 2H-MoTe to a 4-inch wafer and the precise thinning of the channel down to 3 layers. Together, these achievements enable the realization of medium-scale integration of more than 100 p-type 2D transistors with significantly improved device performance. These demonstrations effectively bridge the gap between current several discrete device-level demonstrations and the practical mass device integration, validating the utility of p-type 2D semiconductors in medium-scale integrated circuits that consist of hundreds of transistors. Such results will lay a solid foundation for the future large-scale integration of 2D CMOS circuits, further advancing the progress of 2D semiconductors towards industrial applications.

Results
4-inch uniform synthesis of 2H-MoTe via precursor engineering

Achieving uniform growth of 2D semiconductors on large-scale wafers requires overcoming fundamental limitations in precursor dynamics13, 30. Conventional chemical vapor deposition (CVD) systems suffer from temporal and spatial fluctuations in chalcogen precursor supply due to rapid sublimation and low vapor pressure of solid powders, leading to non-uniform nucleation30. Our custom-designed CVD systems (shown in Fig. 1a and Supplementary Figure 1) integrates two key metrics: (i) Sustained-release tellurium delivery through tellurium source resolidification and molecular sieve envelopment; and (ii) ultrathin Mo precursor deposition enabled by oxygen plasma-activated substrate engineering.

The tellurium precursor management system (Fig. 1b) addresses the critical challenge of maintaining stable and controlled supply across wafer-scale growth. By melting Te powder at 450 ℃ followed by natural cooling recondensation, more stable Te flux could be realized compared to conventional powder sublimation methods. According to previous TMD growth reports, chalcogen precursors, in comparison to metal precursors, exhibit significantly higher melting points and a slower sublimation rate30. This difference can result in excessive nucleation and the formation of localized chalcogen vacancies within the synthesized 2D TMDs. Therefore, we envelop molecular sieves on the resolidified Te (shown in Fig.1b), which could ensure stoichiometric Te:Mo ratio during the wafer-scale growth by directing the tellurium vapor release exclusively through the sieve's pores, thereby precisely control the precursor evaporation rate and suppresses Te vacancy formation. Concurrently, the metal precursor thickness control was also critical during MoTe growth, which would have significant influence on the resulting thickness of the MoTe films.

Despite recent advances that have facilitated the wafer-scale growth of 2H-MoTe 18, 19, 26, the thinning of the resultant MoTe to the necessary dimensions remains challenging. Previous reports have typically yielded films with thicknesses exceeding six layers or even higher18, 26, 27, 31, 32, which would ultimately limit their electrostatic control capabilities in high-performance transistors. Generally, the direct deposition of metal precursors often results in island-shaped and discontinuous structures according to the Volmer-Weber model33, which set unavoidable barriers for the growth of ultrathin continuous MoTe films. We overcome this Volmer-Weber limitation for ultrathin Mo precursors through substrate surface modification. High-energy oxygen plasma treatment could enhance wettability and adhesion of Mo precursor on the substrates. This treatment changed the substrate surface energy, endowing it with hydrophilic properties (Supplementary Figure 2), and activates the surface with a greater number of active sites, thereby enabling the deposition of an ultrathin Mo film of 2 nm (Fig. 1c). Furthermore, the enhanced adhesion resulting from the oxygen plasma treatment also effectively suppress Mo islanding and evaporation during high-temperature tellurization, ensuring more consistent and uniform film growth processes.

Following the meticulous preparation of the precursors, the homogeneous growth of 4-inch MoTe was achieved within our CVD system, and detailed CVD growth procedures were present in Method section.

The synergy of these precursor engineering yields 4-inch 2H-MoTe₂ films with high uniformity. High-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) cross-sectional analysis (Fig. 1d) has confirmed the growth of the wafer-scale 2H-MoTe film with 2D-layered structures, and the elemental mapping in Fig. 1d identifies the presence of molybdenum and tellurium. In addition, as present in Supplementary Figure 3, X-ray photoelectron spectroscopy (XPS) spectra across of the synthesized MoTe film was analyzed, which also confirmed the presence of molybdenum and tellurium. The high-resolution XPS peaks were observed at 228.6 eV (Mo 3d ), 231.8 eV (Mo 3d ), 573.2 eV (Te 3d ), and 583.6 eV (Te 3d ), respectively, which are also consistent with the characteristics of 2H-MoTe in previous reports18, 26, 27. To elucidate the growth mechanism during tellurization, we find that the formation of MoTe does not proceed via direct crystallization into the 2H phase. Instead, a metastable 1T′ phase forms at the early stage and subsequently transforms into the thermodynamically stable 2H phase with continued Te supply, with the coexistence of both phases observed during growth providing direct experimental evidence for this phase-transition pathway (Supplementary Figure 4). As inferred from Supplementary Figure 4, the largest continuous crystalline domain reaches approximately 900 μm, approaching the millimeter scale. Consequently, despite being polycrystalline, the film’s large crystalline domains result in a substantially reduced density of grain boundaries, with typically only one or two intersecting a transistor channel. This microstructural feature is a critical factor enabling uniform device performance and the successful fabrication of medium-scale integrated circuits based on MoTe . Owing to the controlled-thickness pretreatment of Mo metal precursor, we achieved precise thickness regulation of the resulting MoTe films from 3 to 20 layers, respectively, which is present in the optical images and corresponding AFM height profiles of Supplementary Figure 5. Such layer number control capability directly correlates with the precursor's initial thickness, enabling predictable synthesis of the 2H-MoTe with designed dimensionality. In addition, the synthesized 2H-MoTe exhibits great thickness uniformity and macroscopic smoothness (surface roughness <1.15 Å), as evidenced by large-area cross-sectional STEM imaging (in Supplementary Figure 6), which demonstrate good thickness control during the material synthesis. The amplified cross-sectional STEM image of Fig. 1e reveal a uniform A-B stacking sequence across the entire film with a well-ordered crystalline structure. Meanwhile, the absence of atomic intermixing or defects could also be demonstrated in Fig. 1e. As shown in Fig. 1f, STEM analysis along the c-axis of MoTe was conducted, which present a highly-crystalline 2H-MoTe lattice with very few defects, such as the adatoms and vacancies. The selected-area electron diffraction (SAED) pattern presented in the inset of Fig. 1f further conformed the uniform highly-crystalline characteristics of the obtained MoTe thin films. To further assess the structural uniformity and crystallinity of the films at the wafer scale, additional transmission electron microscopy (TEM) characterizations were performed at multiple spatial locations across the MoTe films, and the corresponding selected-area electron diffraction (SAED) patterns were obtained (Supplementary Figure 7). The SAED patterns collected from different regions exhibit well-defined and consistent diffraction spots, indicating good crystallinity and a uniform crystal structure across the wafer. Notably, the 2H-MoTe growth could also achieve full coverage on a 4-inch wafer, which is demonstrated in Fig. 1g. To characterize the crystalline quality and homogeneity of the synthesized 2H-MoTe thin films, a comprehensive Raman spectroscopic analysis was performed at 25 equidistant points across the 4-inch wafer, as demonstrated and numbered in Fig. 1g. The Raman spectra in Supplementary Figure 8 corroborate the growth of 2H-MoTe , with distinct vibrational modes of A (171cm-1), B1 (291cm-1) and E1 (234cm-1) consistently observed across all sampled points, which are consistent with previous reports18, 19, 27. In pursuit of more understandings of the 2H-MoTe films quality, Raman mapping was conducted over a 50 μm × 50 μm area at the 25 discrete points across the 4-inch wafer, as detailed in Fig. 1h and 1i. The homogenous color distribution within these mappings, coupled with the uniform peak intensity and full width at half maximum (FWSHM) of the E1 (234cm-1) Raman shift. The statistic standard deviations in peak intensity and FWHM demonstrate very barrow distributions of 10.36±2.61 CDD cts and 4.48±0.54 cm-1, respectively (with comprehensive statistical histograms provided in Supplementary Figure 9). Such small distributions demonstrate the great uniformity of the wafer-scale 2H-MoTe thin films, not only within a microscale area but also across the entire 4-inch wafer. Therefore, we also conducted additional measurements to more rigorously evaluate the quality and uniformity of the thin film across 4-inch wafers. Atomic force microscopy imaging was performed with scan sizes ranging from 5×5 μm2 to 15×15 μm2, sampled from multiple locations on the wafer. These images (Supplementary Figure 10) clearly reveal grain morphology. Concurrently, statistical analysis of surface roughness across 16 representative regions (each 15×15 μm2) (Supplementary Figure 11) confirmed exceptional uniformity and minimal variability. Notably, we also performed large-area scanning electron microscopy (SEM) imaging (Supplementary Figure 12) to present the micrometre-scale film continuity and topographical features more clearly. This confirms that the 2H-MoTe films prepared on wafers exhibit high uniformity on a wafer scale, providing a robust foundation for subsequent transistor and circuit fabrication.

Electrostatic control via thickness scaling and high-k

The limitations of wafer-scale p-type 2D transistors, including the limited current on-off ratio (~104 or lower) and high operating voltages (typically in tens of volts18, 19, 27, 31), stem form inadequate electrostatic control within the 2D transistors. Accordingly, we address this through two optimization strategies, including the atomic-scale channel thinning enabled by precursor engineering and sub-20 nm high-κ dielectric integration.

Firstly, we systematically investigated thickness-dependent characteristics in MoTe transistors (device schematic in Fig. 2a). Cross-sectional STEM analysis (Fig. 2b) confirms our CVD-grown 2H- MoTe maintains high crystallinity and layered structure from 20 down to 3-layer thickness. Notably, our precursor engineering eliminated conventional CVD growth defects such as discontinuities and surface contamination through precise vapor-phase precursor regulation. In addition, the thickness of the Mo precursor defines the total amount of Mo available for conversion, thereby imposing an intrinsic constraint on the final MoTe layer number (Fig. 2c). When the precursor approaches the ultrathin regime, the growth enters a Mo-limited conversion mode that suppresses excessive nucleation and vertical stacking, enabling the formation of thickness-controlled and uniform few-layer films. Precise layer control of 2H-MoTe (3L-20L) via Mo precursor thickness tuning (Fig. 2c) enables linear thickness controllability, which is a significant advancement over previous CVD methods that produced ≥6-layer films18, 19 and achieved the thinnest wafer-scale p-TMD reported (3 layers). Fig. 2d compares the transfer characteristics (drain current I ds . gate-to-source voltage V gs ) of MoTe transistors with channel thicknesses ranging from 3 to 20 layers, which reveal significant thickness dependence: reducing channel thickness from 20L to 3L enhances on-current 21.8 times (from 0.30 to 6.54 μA) while suppressing off-current 81times (from 12.95 to 0.16 nA) (Fig. 2d). This indicates a three-order-of-magnitude improvement in current on/off ratios (I /I ) (from 23 to 1.47×105), outperforming previously-reported CVD-synthesized MoTe transistors (benchmarking in Fig.2e). 18, 19, 21, 26, 27, 34, 35, 36, 37, 38, 39, 40.

To further enhance electrostatic control in MoTe transistors, we engineered gate dielectric architectures by replacing 280-nm SiO with high-κ alternatives. The high-κ material HfO offers the following core advantages: i). Higher gate capacitance and improved electrostatic control: The high dielectric constant (κ) of HfO enables a larger gate capacitance per unit area (C ox ) for a given physical thickness. As described by the relationship for the subthreshold swing, 𝑆𝑆 = ln⁡(10)(𝑘𝑇/𝑞)(1+𝐶 𝑖𝑡 /𝐶 𝑜𝑥) , a larger C ox directly leads to a smaller SS, signifying a steeper switching characteristic. This enhanced gate control is crucial for achieving low-power operation in transistors. ii). Scaled equivalent oxide thickness (EOT): The high κ value allows for the realization of a very small EOT while maintaining a physically thicker dielectric layer. This combination is key to enhancing gate control efficiency while effectively suppressing the gate leakage current that becomes prohibitive with ultra-thin conventional dielectrics. In this study, we demonstrate that the ALD-grown HfO dielectric, with higher κ compared to SiO and Al O , provides superior electrostatic control over the MoTe channel. Fig. 2f illustrates devices integrating three-layer MoTe channels with three dielectric configurations: 280-nm SiO , 20-nm Al O , and 16-nm HfO . The corresponding transfer characteristics are detailed in Fig. 2g. Transistors with SiO dielectrics required 150 V gate swings (-100 V to +50 V) for full on-off switching (shown in Fig. 2d and 2g), which is a voltage regime incompatible with low-power electronics. Leveraging high-κ materials (Al O , HfO ) validated in silicon CMOS technologies, we achieved 37.5× voltage reduction (4 V operation at -4 V to 0 V) while maintaining I on /I off of beyond 105 (Fig. 2g). As Fig. 2h illustrates, the MoTe devices achieve a combination of low-voltage operation (4 V) and high current on/off ratios (1.47×105), demonstrating operational superiority against the previously reported CVD-synthesized counterparts18, 19, 21, 26, 27, 34, 35, 36, 37, 38, 39, 40. Although a local back-gate configuration is adopted in this study to preserve channel quality, top-gate architectures remain important for achieving high-density integration in two-dimensional electronics. However, the direct deposition of high-k dielectrics on two-dimensional semiconductors presents intrinsic interfacial challenges. Owing to the absence of dangling bonds, ALD growth is nucleation-limited and can introduce interface defects, thereby degrading carrier transport and device uniformity. Interface engineering strategies, such as the introduction of an ultrathin seed layer, appropriate surface modification, and interfacial treatments,1, 9 can promote continuous dielectric growth and reduce interfacial defect density, providing a feasible pathway toward high-quality top-gated device integration.

Highly uniform MoTe transistors for integration

The transition from discrete 2D devices to integrated circuits demands achieving silicon-level uniformity in threshold voltage (V th ) and on/off ratio, which is a challenge for 2D semiconductors. As depicted in Fig. 3a, our p-type MoTe transistors employ a gate-first architecture that synergizes two strategic advantages: processes enable precise atomic-layer-deposited (ALD) dielectrics, and minimized thermal/chemical exposure (<3 processing steps) to the 2D channel post-transfer. It is noteworthy that the material transfer procedure is employed solely once to transfer the MoTe films from the growth substrate to pre-patterned substrates 5-nm Ti/20-nm Au local gates and 16-nm HfO high-κ dielectrics. For this reason, we therefore intentionally adopted the bottom-gate configuration to ensure a high-quality MoTe /dielectric interface, and to enable reliable fundamental functions of the transistors without the effects of a non-ideal top dielectric interface. This approach allows us to present a baseline performance that reflects the material’s potential under well-controlled manufacturing processes, particularly for evaluating scalability in large-scale circuit integration. The remaining components of the MoTe transistors utilize the standard semiconductor manufacturing facilities, with the objective of making the entire device fabrication process as controllable and reproducible as feasible. Concurrently, the transfer stamp, fabricated from thermal release tape (TRT) and polymethyl methacrylate (PMMA) (for detailed procedures, see Methods), in conjunction with heat pressing, has been proved to be reliable for single-layer nanomaterials transferring41, 42. Our wafer-scale integration strategy enables high-density fabrication of MoTe transistor arrays and functional circuits across 4-inch substrates (Fig. 3b), achieving a device integration density of over 1.3 × 103 cm-2. In comparison to previously reported p-type 2D transistors18, 19, 24, 31, this represents a great improvement over prior p-type 2D transistor platforms, and there remains great potential for further dense integration through the reduction of device dimensions.

Fig. 3c displays wafer-scale MoTe transistor arrays with the same 14 μm × 100 μm channel dimensions (magnified view in Supplementary Figure 13), while cross-sectional STEM imaging (Fig. 3d) confirms the structural integrity of the MoTe transistors with sharp interfaces between the MoTe channel and 16-nm HfO dielectric. Electrical characterization of 100 individual sampled devices (Fig. 3e) demonstrates 100% operational yield with p-type enhancement-mode operation (complete current cut-off at V gs = 0 V). Here, enhancement-mode functionality enables single-supply operation, which is an advancement over conventional depletion-mode 2D transistors requiring dual voltage sources and larger power consumptions. The superior characteristics of this high-performance field-effect transistor are attributable to two factors. First, we employed precursor engineering to achieve highly thickness-controlled growth of MoTe , enabling the fabrication of uniform, ultrathin 3-layer channels across a 4-inch wafer. Second, the use of an ALD-grown HfO dielectric with a high dielectric constant enables a substantially reduced equivalent oxide thickness (EOT). This enhances the gate capacitance and improves electrostatic control over the MoTe channel, exhibiting a steeper subthreshold swing and lower operating voltage. For a more detailed description of the uniformity of our fabricated MoTe transistors, statistical analysis of the electrical performance parameters was conducted based on the transfer characteristics presented in Fig . 3e. The statistical results in Fig. 3f reveal a highly sharp distribution in carrier mobility of 7.04±1.65 cm2 V−1 s−1, offering good current driving capability necessary for further medium-scale IC construction. Here, the carrier mobility is evaluated via the formula 𝜇 = (𝐿 /𝑊)(1/𝐶 𝑜𝑥)(1/𝑉 𝑑𝑠)(𝜕𝐼 𝑑𝑠/𝜕𝑉 𝑔𝑠),where⁡the oxide capacitance C ox of approximately 0.05 μF/cm2 was by parallel-plate C-V measurements (details are provided in Supplementary Figure 14). In order to investigate the fundamental reasons for the relatively low carrier mobility in thin-film transistors (TFTs), the source/drain metal-semiconductor contact was analyzed using the Y-function method. As shown in Supplementary Figure 15 and Supplementary Note 1, the contact resistivity of four classical MoTe TFT is on the order of 108 Ω∙μm, suggesting the presence of poor metal-semiconductor interface quality. The contact resistance in our MoTe TFT is relatively large compared with other reports, which reduces the source–drain current under the same applied voltage. As a result, the mobility extracted directly from the transfer characteristics is significantly underestimated. We believe that this does not reflect an intrinsic limitation of the material itself; rather, the mobility could be further improved with optimized contact engineering that remains compatible with scalable fabrication processes. Fig. 3g presents the statistical distribution of the on/off current ratio (I on /I off ) for the p-type transistors, with an average value of 1.29×105 and a standard deviation of 3.68×104. This distribution ensures a clear distinction between the on and off states, enabling the transistors as effective switching devices. In Fig. 3h, the threshold voltage (V th ) shows a narrow distribution of -3.38±0.042 V. Here, V th is calculated by the intercept of the line extrapolated at the point of maximum transconductance (illustrated in Supplementary Figure 16). The variation in V th is only 42 mV, accounting for only 1.07% of the 4V operating gate voltage window, which is superior to previously reported p-type 2D transistors18, 19, 21, 26, 27, 34, 35, 36, 37, 38, 39, 40 and even approaching the foundry-fabricated silicon-based field-effect transistors at the 32 nm43 and 45 nm44 technology nodes, with standard deviations of 37 and 30 mV, respectively. Such high-uniformity in I on /I off and V th , greatly contribute to consistent switching characteristics across the operating voltage window, which lay a robust foundation for constructing ICs based on these transistors. It should be noted that, in order to validate the long-term stability of the fabricated MoTe devices, they were subjected to extended storage under vacuum conditions. Transfer characteristics were measured after 14 months, as shown in the corresponding Supplementary Figure 17 the devices exhibit negligible shift the transfer characteristics, also the extracted parameters (e.g., current on/off ratio (in Supplementary Figure 17b) and threshold voltage (in Supplementary Figure 17c)), confirming excellent operational stability over an extended long period. The devices were also exposed to ambient air, where performance degradation was observed, consistent with previous reports18. Although surface oxidation may induce p-type doping, adsorption of O and H O at surface defects can introduce carrier scattering and moisture-related trapping that affect carrier transport. These results highlight the importance of effective encapsulation for maintaining device stability, which will be explored in future work. To evaluate device performance at the sub-micron scale, MoTe transistors with varying channel lengths, including sub-micron dimensions, were characterized (in Supplementary Figure 18). As the channel length decreases, the devices retain well-behaved switching and stable transfer characteristics, with the on-state current increasing in accordance with typical scaling behavior. Although these devices with sub-micron dimensions exhibit slightly inferior uniformity compared to their counterparts with larger dimensions, their performance remains acceptable for circuit integration, demonstrating the practical utility of the grown MoTe films.

2D PMOS logic: from uniform transistors to MSICs

The high uniformity of MoTe transistors paves the way for the fabrication of logic gates and more complex integrated circuits. As a preliminary demonstration, logic gates that serve as the essential building block of digital ICs, including inverters (or the NOT gate), NAND, and NOR gates, are constructed using p-type metal-oxide-semiconductor (PMOS) logic. The inverter, depicted in Fig. 4a, employs two MoTe transistors with distinct channel width-to-length ratios of 2 and 14, serving as the driver and active load, respectively (as illustrated in the accompanying circuit diagram of Fig. 4b). Key electrical parameters of inverters that influence the cascading capability, such as the output logic level and noise margin (NM), can be derived from the voltage transfer characteristics (VTCs). The VTCs of a representative inverter, measured under varied biases of V dd = -2 V, -3 V, and -4 V, are presented in Fig. 4c. Owing to the narrowly controlled distribution of threshold voltages and the substantial on/off ratio of the MoTe transistors, the output voltage level can be effectively pulled up or down to V dd or GND (0V), representing logical "1" and "0," respectively. As a result, near rail-to-rail output is achieved, which ensures good cascading capability for the integration of logic circuits. Fig. 4d shows VTC (red solid line) and its mirror curve (blue dotted line) under a V dd bias of -4 V. The large area of the 'butterfly' diagram, representing high noise tolerance with the noise margin of 63% for the inverter. These properties attributes great tolerance to the input noise, and enabling the further development of more intricate ICs with increased logic depths. Leveraging the highly-uniform MoTe transistors, fundamental PMOS logic NAND gate (Fig. 4e-g) and NOR gate (Fig. 4h-j) have been realized, demonstrating accurate time-varying Boolean output functionalities corresponding to logic "1" and "0," respectively. It is worth emphasizing that these gates exhibit nearly ideal high (5 V) and low (0 V) logic level outputs, thereby ensuring the cascading capability essential for further large-scale integration. Such results are attributed to the utilization of highly uniform MoTe transistors with well-controlled threshold voltages in this study.

The construction of ring oscillators (ROs) by cascading the inverters is an effective and reliable way to evaluate the yield, uniformity and speed of logic gates. Accordingly, ring oscillators with different stage numbers—5 stage (depicted in Supplementary Figure 19), 15 stage (in Supplementary Figure 20), and 59 stage (in Fig. 4k-m)—have been constructed utilizing the MoTe based inverters. At a supply voltage of 5 V, the oscillation frequencies achieved are 2065 Hz for the 5-stage RO, 816 Hz for the 15-stage RO, and 238 Hz for the 59-stage RO. Correspondingly, the propagation delays for single-state MoTe -based logic gates (τ=1/2Nf, where N is the RO stage number, f is the oscillation frequency) are 48.43 μs, 40.85 μs, and 35.61 μs, respectively. The consistency in propagation delay across ring oscillators with differing stage numbers strongly indicates the excellent performance uniformity and high yield of the basic logic gates. It is worth noting that the measured characteristics of the MoTe transistors exhibit a small degree of hysteresis. As shown in Supplementary Figure 21, the forward (red curve) and reverse (blue curve) transfer characteristics of a representative device display a slight shift. However, the magnitude of this hysteresis is very small compared to the operational voltage of 5 V, which would not affect practical circuit operation. Both the oscillation waveforms and logic outputs are stable, reproducible, and fully functional, underscoring the robustness of our device design and fabrication process. Future enhancements may be realized by downsizing the MoTe transistors or by elevating the supply voltage, which could further reduce the gate propagation delay.

Given the robust logic operation of the basic gates demonstrated, attributed to the high uniformity of the transistors, a more complex arithmetic integrated circuit (IC) has been constructed using these MoTe PMOS logic gates. The full adder is an important combinational logic circuit for arithmetic operations and is usually used as a basic building block for arithmetic logic units (ALUs). However, the implementation of a full adder based on p-type 2D transistors has been rarely reported due to the deep logic depth requirements, which necessitate a high level of uniformity and finely tuned output voltages for each constituent element. Here, as shown in Fig. 5a, we present a 4-bit full adder based on the PMOS MOTe logic gates, which integrates 140 transistors and spans a logical depth of 12 stages. This is a medium-scale integrated circuit (MSIC, i.e., circuits with over 100 integrated devices) that has not previously been achieved using MoTe or even other p-type 2D materials. The circuit design diagram of the 4-bit full adder is portrayed in Fig. 5b, which incorporates four sequential 1-bit full adders. Each sub-component, the 1-bit full adder, is composed of three NAND gates and two XOR gates with 35 p-type MoTe transistors (as illustrated in Fig. 5c). Here, the input terminals A and B in Fig. 5b and 5c represent the inputs to be summed, with C indicating the carry-in from previous additions. The output terminal S denotes the sum, while C represents the carry-out for subsequent arithmetic operations.

To verify the operational accuracy of the 4-bit MoTe full-adder, we conducted a comprehensive test of the output logic values across 16 distinct addition combinations for the input set (A A A A , B B B B ), specifically including pairs such as (1110, 1111), (0101, 1101), (0011, 1100), and so forth, as detailed in Fig. 5d. The results confirm the correct logical functionality of the 4-bit full adder., illustrating that the 4-bit full-adder exhibits right time-varying Boolean logical functions. As depicted in Fig. 5e, a comparison is implemented of wafer size and integrated device counts with previous works based on p-type 2D materials14, 15, 18, 19, 20, 21, 23, 26, 27, 34, 35, 36, 37, 38, 39, 40, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60. From the comparison, it can be concluded that although there have been prior instances of arrayed transistors14, 15, 18, 19, 34, 35, 38, 39or simple logic gate circuits20, 23, 48, 51, 54, 56, 57, 58, 59fabricated from p-type 2D materials, the realization of the medium-scale integrated circuit, such as the 4-bit adder demonstrated here, marks a significant advancement to meet the criteria for practical application in terms of scale and wafer size. In contrast19, our approach utilizes nearly standard nanodevice fabrication processes and conventional contact materials, enabling highly uniform and reproducible device performance across a 4-inch wafer. We achieve an on/off ratio of ~1.47×105—comparable and even superior to the reported values—while simultaneously demonstrating, a functional medium-scale integrated circuit comprising over 100 p-type 2D transistors. This balance between high performance and process scalability represents a key step toward practical applications of p-type 2D semiconductors in integrated electronics. Furthermore, as shown in Supplementary Table 1, this successful demonstration showcases a substantial increase of p-type 2D circuits in a deeper logical depth and a denser integration density. These achievements signify that integrated circuits utilizing p-type 2D transistors are progressing towards the medium-scale domain, which would expand the horizons for their application in future advanced electronic systems.

Methods
Growth of ultrathin 2H-MoTe Films: The MoTe films were synthesized by tellurizing the Mo films at atmospheric pressure in a horizontal tube furnace equipped with mass flow controllers and a vacuum pump. Firstly, the substrate was treated by high-energy oxygen plasma (inductive coupled plasma in CF /O atmosphere) to change the hydrophilicity of the substrate surface. Subsequently, we employed magnetron sputtering with molybdenum as the target material to deposit a molybdenum film. To ensure uniform deposition on 4-inch wafers, we controlled the deposition rate between 0.1-0.3 Å s-1 by adjusting the sputtering DC power (8 W) and chamber pressure (0.7-0.8 Pa). Then the tellurium powder (99.9%, Alfa Aesar) is put into the alumina boat, and the alumina boat is inserted into a 5-inch diameter quartz tube in the furnace. The growth temperature was set at 450°C, the Ar flow rate was 80 sccm, and the growth time was 10 minutes. The Mo source is placed vertically in the middIle of the quartz tube, the Te source and the molecular sieve are placed together in the alumina boat, and then the alumina boat is inserted into the upstream position of the 5-inch diameter quartz tube in the furnace. When the quartz tube is vacuumized to below 10 mTorr, high-purity Ar gas is introduced, and the flow rate is 500 standard cubic centimeters per minute (sccm) until the atmospheric pressure is reached. This process was repeated three times. After that, the Ar flow rate was set to 60 sccm, and high-purity H gas was introduced at a flow rate of 80 sccm. The growth temperature and time were 600 °C and 2 h, respectively. After the growth period, the furnace was turned off and naturally cooled to room temperature.

Transfer of MoTe films: First, a layer of PMMA is spin coated on a MoTe /Si/SiO substrate at 4000 RPM and then baked at 150 °C for 5 minutes. Then, the hot release tape is applied to the sample and the sample is immersed in 10% KOH solution for 30 minutes. Peel the hot strip tape /PMMA /MoTe layer with tweezers, move to the surface of pure water to wash several times, and then transfer the layer to the target substrate. Heat thermal release tapes (TRT) are used to keep the MoTe film flat and release the PMMA /MoTe layer onto the substrate at 120°C. After complete release, the sample was washed in acetone for 5 minutes to remove all polymers.

MoTe transistor fabrication and electrical characterization: For back-gated MoTe field-effect transistors, Firstly, the Ti/Au (5/20 nm) local gate is defined by standard lithography on the substrate, followed by an electron beam evaporation (EBE) and lift-off process. Secondly, atomic layer deposition was employed to prepare 16 nm HfO or 20 nm Al O insulating layers. The HfO film is deposited at a deposition temperature of 250℃ using tetrakis (ethylmethylamido) hafnium and H O as the precursors. The tetrakis (ethylmethylamido) hafnium precursor was pulsed for 500 ms with a purge time of 5 s. The H O precursor was pulsed for 500 ms with a purge time of 8 s. The Al O film is deposited at 250 ℃ using trimethylaluminium and H O as the precursors. The trimethylaluminium precursor was pulsed for 500 ms with a purge time of 5 s. The H O precursor was pulsed for 500 ms with a purge time of 8 s. Subsequently, photolithography was performed using standard photolithography techniques, followed by process etching employing inductively coupled plasma reactive ion etching (ICP-RIE) under an atmosphere of 80W RF bias power with SF 6 /O 2 /Ar = 120/40/40 s. c. c. m . The MoTe film is then transferred to the substrate, the source and drain on the MoTe film of the device are prepared using lithography and electron beam evaporation of Ti/Pd/Au (1/40/20 nm). Finally, the MoTe films is patterned using photolithography and the aforementioned ICP-RIE etching process. All electrical measurements were taken under moderate vacuum conditions. using a semiconductor parameter analyzer (Keysight B1500), digital oscilloscope (Siglent SDS1024X) and signal generators (Siglent SDG1022X). The output analysis of the 4-bit full adder was implemented by a logic analyzer (DSLogic, DreamSourceLab. Co. LTD). A better electrical performance is expected if the vacuum level of the metal evaporation chamber can be improved.

Characterization of the morphology and structure: Raman spectra of the CVD-grown few layers 2H-MoTe Films were collected using a confocal Raman microscope system (Alpha300, WiTec) with an excitation wavelength of 532 nm. The Raman spectra were obtained at a laser power of 200 μW and an accumulation time of 10 s (using a grating of 1800 grooves per mm). The atomic structure and chemical composition of the MoTe were investigated by STEM, energy dispersive X-ray spectroscopy (EDS), high-resolution STEM (HRSTEM) and selected-area electron diffraction (SAED). X-ray photoelectron spectroscopy (XPS, SHIMADZU AXIS SUPRA+ ) was used to obtain the MoTe signals.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The authors have adequately addressed the previous concerns regarding the stability of the MoTe₂ devices and have improved the overall quality of the manuscript. Therefore, this reviewer recommend it for publication.", "reviewer_2": "In the revised version of their manuscript the authors provide additional data to support the original claims of their publication, that their uniform growth of 2H-MoTe2 at a wafer scale enables the fabrication of highly uniform p-type transistors that can be used to produce medium scale integrated logic circuits with industry compatible techniques. The additional data in the SI on the characterisation of their grown thin films provides insight as to their quality. The scale up from previously reported 39 transistor p-type circuits to a 4 bit full adder medium scale integrated circuit is an advancement over previous publications for p-type 2D material transistors.\n\nThis work presents an alternative approach to other p-type 2D material growth, and the revised manuscript clarifies that the advance is the scale up to 4 inch wafers of 3 layer 2H-MoTe2, rather than the growth methods themselves, the films produced in this work are polycrystalline with lots of individual grains and a relatively rough surface. The authors claim that their growth method is comparable with existing industry techniques for applications however the MoTe2 film’s novel uniformity is uncertain on a scale useful for technology.\n\nWhilst the results presented here are interesting and worth reporting I do not believe their novelty is sufficient for publication in nature communications and that they would be suited to a more specialised publication.\n\nI provide the following more detailed comments to the authors.\n\n1. The quality of the 2H-MoTe2 films\nThe authors have conducted significant extra work to characterise their thin MoTe2 films in more detail compared to the original manuscript showing AFM characterisation and TEM surface characterisation. Whilst the new characterisation does indicate consistency across the wafer in the new fig S9, on a smaller scale it does re-enforce my original concerns about the quality of the grown MoTe2. The AFM analysis in figure S8 shows the grain morphology with many connected grains. Additionally, the averaged roughness from fig S9 is high, 0.3nm average roughness with individual high points of several nm. Compared with a layer thickness for MoTe2 of 0.6-0.65nm, this would be challenging to work with for further device development. The surface quality would be an additional hinderance for inclusion of the grown MoTe2 into more advanced heterostructures, either for atmospheric protection or, as mentioned by my fellow reviewer, for top gated devices.\n\n2. The environmental stability of MoTe2\nIn the revised manuscript the authors confirm that their devices are stable over a period of 14 months with minimal change in transfer characteristics whilst under vacuum. Although this is sufficient for this demonstration, as the paper is heavily focussed of the applicability of the growth technique for industry over other published methods and its comparability with existing processes, it is important that devices can continue to perform after storage in ambient conditions as well as only under vacuum storage.\n\n3. Device size.\nThe authors acknowledge the importance of sub micron devices in the revised manuscript and highlight the importance of these devices for future work as the large device size presented of 14x100μm will average out imperfections due to grain boundaries and defects present in the grown films. The devices presented are of a similar size to those shown in previously published work on p-type 2D material transistors. Smaller devices would likely have a much less uniform distribution of key transport characteristics. Whilst uniformity in smaller devices is not required for the key aim of this paper, to demonstrate for the first time a medium scale integrated circuit with p-type MoTe2, this miniaturisation would show the usefulness of the growth techniques to modern technological applications.", "reviewer_3": "The manuscript by Wang et al. presents a significant milestone in the field of 2D electronics. The authors report the fabrication of the first medium-scale integrated circuit (MSIC) based on p-type 2D semiconductors, specifically realizing a 140-transistor full adder. This achievement is underpinned by their successful synthesis of highly uniform, wafer-scale (4-inch) 2H-MoTe2 films via a clever precursor engineering strategy.\n\nThe work addresses a critical bottleneck in the field: while n-type 2D devices have seen rapid progress, scalable and high-performance p-type counterparts have lagged behind. The reported electrical uniformity (e.g., small threshold voltage variation) and the successful demonstration of complex logic gates represent a substantial leap from discrete device demonstrations toward practical integrated circuits. The experimental design is rigorous, and the results are convincing.\n\nI recommend the publication of this manuscript. However, I have listed a few specific queries and suggestions below regarding the material growth mechanism and fabrication processes. Addressing these points will further strengthen the manuscript and provide valuable insights to the community.\n\nSpecific Comments:\nGrowth Mechanism and Nucleation: The authors synthesize the MoTe2 films by tellurizing Mo precursor films. Could the authors clarify the phase evolution during this process? specifically, does the reaction lead directly to the formation of the 2H phase, or does it involve a phase transition (e.g., from a metastable 1T' phase to 2H phase)? Furthermore, the work highlights the use of ultrathin Mo precursors. It would be scientifically valuable to discuss how the thickness of the precursor, especially in the ultra-thin regime (limiting case), influences the nucleation density and growth mode of the MoTe2.\n\nCrystalline Domain Size: The manuscript provides excellent data on the macroscopic uniformity of the film across the 4-inch wafer. However, as the film is polycrystalline, quantitative information regarding the microstructure is necessary. Please provide data or an estimation of the average crystalline domain size (grain size) of the synthesized thin films.\n\nExperimental Parameters: To ensure the reproducibility of this impressive work, the \"Methods\" section requires more specific details. Please explicitly list the detailed parameters for the micro-fabrication steps, specifically for the Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching, and magnetron sputtering processes (e.g., power, pressure, gas flow rates, and bias voltage where applicable).\n\nDevice Integration and Interface Engineering:\nTransfer Process: The current fabrication flow relies on transferring the MoTe2 films. While successful for this demonstration, transfer processes inevitably introduce defects, interface impurities, and yield challenges that are generally incompatible with large-scale CMOS manufacturing. It would be beneficial for the authors to acknowledge these limitations and briefly discuss pathways toward transfer-free (direct growth) integration in the future.\n\nDielectric Integration: The authors utilize a local back-gate configuration, likely to preserve the channel quality. Top-gate integration is typically preferred for high-density scaling but is often hindered by damage or unintended doping during the Atomic Layer Deposition (ALD) of high-k dielectrics. I suggest the authors discuss potential strategies to solve or mitigate the ALD-induced doping/damage on the MoTe2 channel, which would be a necessary step for future top-gate MSIC implementation.", "reviewer_4": "This manuscript reports the growth of 4-inch, wafer-scale 2D MoTe2 thin films via the optimization of the tellurium source supply. Using these as-prepared thin films, the authors successfully demonstrated the fabrication of a 140-transistor full adder, which illustrates the potential of their material for 2D CMOS circuit integration. I recommend accepting this manuscript, provided that the authors appropriately address the following comments.\n\n1.Regarding the novelty of the growth method: The manuscript highlights a precursor engineering strategy. However, the authors should more clearly delineate the fundamental advancements of their method compared to the early CVD growth of 2H-MoTe2 reported a decade ago (J. Am. Chem. Soc. 2015, 137, 37, 11892–11895) and subsequent studies. The current description suggests modifications rather than a paradigm shift. A more detailed discussion of the specific innovations and their impact would be beneficial.\n\n2.Regarding the evidence for uniformity and quality: The claim of high quality and uniformity across the 4-inch wafer is central to this work. To more robustly substantiate this claim, the authors should provide structural characterization, such as selected area electron diffraction (SAED) patterns, from multiple, well-defined locations across the wafer. This data would serve as crucial evidence to support the asserted uniformity.\n\n3.Regarding the device performance: The authors report a field-effect mobility of ~7 cm2/Vs. This value is lower than what has been previously achieved for MoTe2 FETs (often in the range of 10-50 cm2/Vs), which creates a potential conflict with the claim of “high-quality” material. Furthermore, the recent report of 2D β-Bi2O3 with a hole mobility of 136.6 cm2/Vs (Nat. Mater. 24, 688–697, 2025) sets a new benchmark for p-type 2D semiconductors. To enhance the potential of the 2H MoTe synthesized by authors, it is critical to improve the mobility of single FET before pushing to integrated devices.", "reviewer_5": "I co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature Communications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career Researchers who co-review manuscripts."}, "author_response": "Response to the Reviewers’ comments:\nResponse to Reviewer #1\nThe authors have adequately addressed the previous concerns regarding the stability of the MoTe devices and have improved the overall quality of the manuscript. Therefore, this reviewer recommend it for publication.\nResponse: We sincerely thank the reviewer for their positive assessment of our work and for recognizing the improvements made regarding the stability of MoTe devices. We greatly appreciate the reviewer’s evaluation of the manuscript and their recommendation for publication, which is invaluable to us.\nResponse to Reviewer #2\n1. The authors have conducted significant extra work to characterise their thin MoTe films in more detail compared to the original manuscript showing AFM characterisation and TEM surface characterisation. Whilst the new characterisation does indicate consistency across the wafer in the new fig S9, on a smaller scale it does re-enforce my original concerns about the quality of the grown MoTe . The AFM analysis in figure S8 shows the grain morphology with many connected grains. Additionally, the averaged roughness from fig S9 is high, 0.3nm average roughness with individual high points of several nm. Compared with a layer thickness for MoTe of 0.6-0.65nm, this would be challenging to work with for further device development. The surface quality would be an additional hinderance for inclusion of the grown MoTe into more advanced heterostructures, either for atmospheric protection or, as mentioned by my fellow reviewer, for top gated devices.\nResponse: We sincerely thank the reviewer for this insightful comment. Here, it should be emphasized that, in order to rigorously evaluate the morphological quality of the MoTe films, decoupling the intrinsic roughness of the films from the baseline topography of the silicon substrate is essential. As illustrated in Fig. R1, the standard Si/SiO substrate exhibits an average roughness of 0.2 nm. As the as-grown MoTe film has an average roughness of 0.3 nm, the net contribution of the surface roughness from the MoTe growth process is merely ~0.1 nm. This marginal increase suggests that the film maintains atomic-level planarity and good conformality to the substrate surface. Crucially, the achieved roughness of 0.3 nm is comparable to state-of-the-art benchmarks and has been shown to be sufficiently robust for subsequent device integration [shown in ref. 18[Ra~0.25 nm], 19[Ra<0.90 nm] of the manuscript].\nFigure R1. a. Detailed atomic force microscopy surface topography images of 6 sampling points on Si/SiO . Scale bar 1 μm. b. Atomic force microscopy surface topography images of Si/SiO at the 1 μm scale. Scale bar 200 nm. c. Atomic force microscopy surface topography images of Si/SiO at the 5 μm scale. Scale bar 1 μm. d. Atomic force microscopy surface topography images of Si/SiO at the 15 μm scale. Scale bar 3 μm.\n2. In the revised manuscript the authors confirm that their devices are stable over a period of 14 months with minimal change in transfer characteristics whilst under vacuum. Although this is sufficient for this demonstration, as the paper is heavily focussed of the applicability of the growth technique for industry over other published methods and its comparability with existing processes, it is important that devices can continue to perform after storage in ambient conditions as well as only under vacuum storage.\nResponse: We thank the reviewer for raising the important issue of the environmental stability of MoTe devices. Following the reviewer’s suggestion, we performed periodic electrical measurements on devices stored under ambient air conditions. Over a 7-day exposure period (Fig. R2), the devices exhibited some degree of performance degradation, primarily manifested as small threshold-voltage shifts and a slight reduction in on-state current. We attribute these changes mainly to the absence of effective device encapsulation at the present stage, which allows adsorption of ambient species such as H O and O at the MoTe surface or interfaces. Such adsorption can introduce non-intrinsic defects, thereby affecting carrier transport.\nImportantly, despite these performance variations, the fundamental transistor functionality of the devices remains intact. Throughout the ambient exposure period, the devices continue to operate as normally switching field-effect transistors, and the current on/off ratio remains at a level sufficient to support logic-state switching in digital circuits. This indicates that the devices could retain functional stability for certain periods.\nIn contrast, our results clearly demonstrate that the devices exhibit excellent stability under vacuum storage, maintaining nearly unchanged electrical characteristics over a period of 14 months. Based on this observation, we believe that the introduction of appropriate device-level or wafer-level encapsulation strategies would effectively suppress environmental adsorption effects and enable similarly robust stability under ambient conditions.\nFinally, we would like to emphasize that the primary objective of this work is not to establish the ultimate limits of device stability, but rather to demonstrate the feasibility of realizing medium-scale integrated circuits based on wafer-scale p-type two-dimensional semiconductors. The manuscript is therefore focused on validating that p-type 2D materials can support complex digital circuit functionality at the integration level. We appreciate the reviewer’s valuable suggestion regarding stability, and investigations into long-term ambient stability and encapsulation strategies will constitute an important focus of our future work toward practical p-type two-dimensional integrated circuits.\nFigure R2. Transfer characteristics of the FET measured during a 7-day exposure period in an air atmosphere.\n3. The authors acknowledge the importance of sub micron devices in the revised manuscript and highlight the importance of these devices for future work as the large device size presented of 14 × 100 μm will average out imperfections due to grain boundaries and defects present in the grown films. The devices presented are of a similar size to those shown in previously published work on p-type 2D material transistors. Smaller devices would likely have a much less uniform distribution of key transport characteristics. Whilst uniformity in smaller devices is not required for the key aim of this paper, to demonstrate for the first time a medium scale integrated circuit with p-type MoTe , this miniaturisation would show the usefulness of the growth techniques to modern technological applications.\nResponse: We thank the reviewer for emphasizing the importance of sub-micron devices in assessing material uniformity and technological relevance. In response, we included additional measurements on devices with varying channel lengths (shown in Fig. S18 of the revised supporting information).\nAs shown in Fig. S18b, with the down-scaling of channel length, the MoTe based transistors continue to exhibit well-behaved switching functionality and normal transfer characteristics. The on-state current increases, which is consistent with typical down-scaling behaviors. Meanwhile, we performed statistical measurements on multiple devices with sub-micron dimensions (Fig. S18d). Despite the expected short-channel effects at reduced sizes, the devices still maintain good uniformity with limited device-to-device variation in transfer characteristics. Although these devices with sub-micron dimensions exhibit slightly inferior uniformity compared to their counterparts with larger dimensions, their performance remains acceptable for circuit integration, demonstrating the practical utility of the grown MoTe films.\nFinally, we note that the primary goal of this work is to demonstrate medium-scale integrated circuits based on wafer-scale p-type two-dimensional materials. Systematic sub-micron scaling studies will be pursued in future work. The corresponding data and discussion have been added to the revised manuscript.\nIn page 20 of the revised Supporting information:\nFigure S18. MoTe transistors with different channel dimensions. a, Optical micrograph of MoTe field-effect transistors with varying channel lengths (L). Scale bar 9 μm. b, Transfer characteristics of MoTe transistors with different channel lengths measured under identical conditions. c, Optical image of an array of MoTe transistors with scaled device dimensions. Scale bar 90 μm. d, Transfer characteristics of 12 representative devices with identical geometry, showing good device-to-device uniformity.\nIn page 12 of the revised manuscript:”\n“To evaluate device performance at the sub-micron scale, MoTe transistors with varying channel lengths, including sub-micron dimensions, were characterized (in Fig. S18). As the channel length decreases, the devices retain well-behaved switching and stable transfer characteristics, with the on-state current increasing in accordance with typical scaling behavior. Although these devices with sub-micron dimensions exhibit slightly inferior uniformity compared to their counterparts with larger dimensions, their performance remains acceptable for circuit integration, demonstrating the practical utility of the grown MoTe films.”\nResponse to Reviewer #3\nThe manuscript by Wang et al. presents a significant milestone in the field of 2D electronics. The authors report the fabrication of the first medium-scale integrated circuit (MSIC) based on p-type 2D semiconductors, specifically realizing a 140-transistor full adder. This achievement is underpinned by their successful synthesis of highly uniform, wafer-scale (4-inch) 2H-MoTe films via a clever precursor engineering strategy.\nThe work addresses a critical bottleneck in the field: while n-type 2D devices have seen rapid progress, scalable and high-performance p-type counterparts have lagged behind. The reported electrical uniformity (e.g., small threshold voltage variation) and the successful demonstration of complex logic gates represent a substantial leap from discrete device demonstrations toward practical integrated circuits. The experimental design is rigorous, and the results are convincing.\nI recommend the publication of this manuscript. However, I have listed a few specific queries and suggestions below regarding the material growth mechanism and fabrication processes. Addressing these points will further strengthen the manuscript and provide valuable insights to the community.\nResponse: We sincerely thank the reviewer for the assessment of our work and for the encouraging comments regarding the clarity and quality of the manuscript. We have carefully considered all the comments provided by the referee, and have revised the manuscript accordingly to further improve its quality, which are present point-by-point as follows.\n1.Growth Mechanism and Nucleation: The authors synthesize the MoTe films by tellurizing Mo precursor films. Could the authors clarify the phase evolution during this process? Specifically, does the reaction lead directly to the formation of the 2H phase, or does it involve a phase transition (e.g., from a metastable 1T' phase to 2H phase)? Furthermore, the work highlights the use of ultrathin Mo precursors. It would be scientifically valuable to discuss how the thickness of the precursor, especially in the ultra-thin regime (limiting case), influences the nucleation density and growth mode of the MoTe .\nResponse: We thank the reviewer for the insightful comments regarding the growth mechanism and phase evolution during the tellurization of Mo precursor films.\nBased on our systematic experimental observations during growth optimization, which are consistent with previously reported phase-transition behaviors [such as ref. 17, 18, 26 in the manuscript], the formation of MoTe in this work does not proceed via direct crystallization into the 2H phase. Instead, we identify a clear phase evolution process. At the early stage of tellurization, when Te availability is limited, the metastable 1T′- MoTe phase preferentially forms. As the tellurization process continues with sustained Te supply, a gradual transformation from the 1T′ phase to the thermodynamically more stable 2H phase occurs. Importantly, during growth we observe the coexistence of 1T′ and 2H phases, as shown in Fig. S4, which provides direct experimental evidence that the final 2H phase is achieved through a phase transition rather than by direct formation.\nIn our growth process, the thickness of the Mo precursor plays a decisive role in determining the final thickness of the converted MoTe films, which have been experimentally demonstrated in Fig. 2c of the manuscript. Specifically, the Mo precursor thickness directly defines the total amount of Mo available for conversion during tellurization, thereby imposing an intrinsic upper limit on the achievable MoTe layer number. By reducing the Mo precursor into the ultrathin regime, the growth process enters a Mo-limited conversion regime, in which both nucleation density and vertical growth are constrained by the finite Mo supply. Under these conditions, excessive multilayer stacking is suppressed, and the growth proceeds toward few-layer MoTe with well-defined thickness. This leads to a reduced and more controllable nucleation density and favors a continuous, thickness-limited growth mode rather than uncontrolled multilayer accumulation. As a result, precise control over the Mo precursor thickness enables deterministic regulation of the final MoTe thickness and promotes the formation of uniform few-layer films over large areas.\nTo provide a visual representation of the material growth process, we have added the corresponding images and descriptions in the revised manuscript and supporting information, which are present as below.\nIn page 6 of the revised Supporting information:\nFigure S4. Optical image showing the coexistence of 1T′ and 2H phases of MoTe .\nScale bar 200 μm.\nIn page 6 of the revised manuscript:\n“To elucidate the growth mechanism during tellurization, we find that the formation of MoTe does not proceed via direct crystallization into the 2H phase. Instead, a metastable 1T′ phase forms at the early stage and subsequently transforms into the thermodynamically stable 2H phase with continued Te supply, with the coexistence of both phases observed during growth providing direct experimental evidence for this phase-transition pathway (Fig. S4).”\nIn page 8 of the revised manuscript:\n“In addition, the thickness of the Mo precursor defines the total amount of Mo available for conversion, thereby imposing an intrinsic constraint on the final MoTe layer number (Fig. 2c). When the precursor approaches the ultrathin regime, the growth enters a Mo-limited conversion mode that suppresses excessive nucleation and vertical stacking, enabling the formation of thickness-controlled and uniform few-layer films.”\n2.Crystalline Domain Size: The manuscript provides excellent data on the macroscopic uniformity of the film across the 4-inch wafer. However, as the film is polycrystalline, quantitative information regarding the microstructure is necessary. Please provide data or an estimation of the average crystalline domain size (grain size) of the synthesized thin films.\nResponse: We thank the reviewer for emphasizing the importance of providing quantitative information on the microstructure of the polycrystalline MoTe films.\nAlthough the MoTe films synthesized in this work are polycrystalline, their grain sizes are relatively large. During the growth process, we clearly observe an intermediate state characterized by the coexistence of the 1T′ and 2H phases, as shown in Fig. S4. These phase-coexisting regions provide direct real-space evidence of laterally continuous crystalline domains and allow an estimation of the characteristic grain domain size. As inferred from Fig. S4, the largest continuous crystalline domain reaches approximately 900 μm, approaching the millimeter scale. Moreover, even in regions where the film has fully merged into a continuous layer, the typical crystalline domain size remains on the order of hundreds of micrometers. This behavior indicates a low nucleation density and a growth mode dominated by lateral domain expansion. Consequently, despite being polycrystalline, the film’s large crystalline domains result in a substantially reduced density of grain boundaries, with typically only one or two intersecting a transistor channel. This microstructural feature is a critical factor enabling uniform device performance and the successful fabrication of medium-scale integrated circuits based on MoTe .\nIn page 6 of the revised manuscript:\n“As inferred from Fig. S4, the largest continuous crystalline domain reaches approximately 900 μm, approaching the millimeter scale. Consequently, despite being polycrystalline, the film’s large crystalline domains result in a substantially reduced density of grain boundaries, with typically only one or two intersecting a transistor channel. This microstructural feature is a critical factor enabling uniform device performance and the successful fabrication of medium-scale integrated circuits based on MoTe .”\n3.Experimental Parameters: To ensure the reproducibility of this impressive work, the \"Methods\" section requires more specific details. Please explicitly list the detailed parameters for the micro-fabrication steps, specifically for the Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching, and magnetron sputtering processes (e.g., power, pressure, gas flow rates, and bias voltage where applicable).\nResponse: We sincerely thank the reviewer for highlighting the importance of experimental parameters. We fully agree that providing precise fabrication parameters is essential for the community to replicate and build upon our work.\nTo make these experimental details explicit and ensure the reproducibility of our work, we have significantly improved the descriptions in the \"Methods\" section of the revised manuscript, which is presented below.\nIn page 18 of the revised manuscript:\n“Subsequently, we employed magnetron sputtering with molybdenum as the target material to deposit a molybdenum film. To ensure uniform deposition on 4-inch wafers, we controlled the deposition rate between 0.1-0.3 Å s-1 by adjusting the sputtering DC power (8 W) and chamber pressure (0.7-0.8 Pa).”\nIn page 19 of the revised manuscript:\nSecondly, atomic layer deposition was employed to prepare 16 nm HfO or 20 nm Al O insulating layers. The HfO film is deposited at a deposition temperature of 250℃ using tetrakis (ethylmethylamido) hafnium and H O as the precursors. The tetrakis (ethylmethylamido) hafnium precursor was pulsed for 500 ms with a purge time of 5 s. The H O precursor was pulsed for 500 ms with a purge time of 8 s. The Al O film is deposited at 250 ℃ using trimethylaluminium and H O as the precursors. The trimethylaluminium precursor was pulsed for 500 ms with a purge time of 5 s. The H O precursor was pulsed for 500 ms with a purge time of 8 s. Subsequently, photolithography was performed using standard photolithography techniques, followed by process etching employing inductively coupled plasma reactive ion etching (ICP-RIE) under an atmosphere of 80W RF bias power with SF /O /Ar = 120/40/40 s. c. c. m. The MoTe film is then transferred to the substrate, the source and drain on the MoTe film of the device are prepared using lithography and electron beam evaporation of Ti/Pd/Au (1/40/20 nm). Finally, the MoTe films is patterned using photolithography and the aforementioned ICP-RIE etching process.\n4.Transfer Process: The current fabrication flow relies on transferring the MoTe2 films. While successful for this demonstration, transfer processes inevitably introduce defects, interface impurities, and yield challenges that are generally incompatible with large-scale CMOS manufacturing. It would be beneficial for the authors to acknowledge these limitations and briefly discuss pathways toward transfer-free (direct growth) integration in the future.\nResponse: We thank the reviewer for raising the important point regarding the transfer process and its implications for large-scale integration. We fully agree that the transfer of two-dimensional materials can introduce defects, interface impurities, and yield challenges for device yield and uniformity, which are critical considerations for CMOS-compatible manufacturing.\nIn our current demonstration, the reliance on transfer arises primarily from the challenges of top-gated 2D transistor fabrication using standard nanodevice fabrication processes. It is well known that the atomically flat and chemically clean surface of two-dimensional (2D) materials lacks sufficient nucleation sites for the atomic layer deposition (ALD) of gate dielectrics, making it highly challenging to achieve high-quality, conformal growth directly on 2D material surfaces using standard ALD processes. Therefore, in this work, to ensure device stability, yield, and performance uniformity, we employed a back-gate architecture in which the gate dielectric is pre-deposited on the substrate using well-established and controllable processes. Consequently, a transfer process is necessarily employed in this work, since the high temperatures involved in direct MoTe growth would adversely affect the ALD-deposited gate dielectrics.\nWe fully agree We fully agree that avoiding transfer processes is essential for improving industrial scalability and compatibility. Consequently, devising direct deposition strategies for high-k gate dielectrics on 2D semiconductors, which are compatible with standard industrial equipment, constitutes a significant challenge. Success in this area would not only streamline manufacturing but also better preserve the intrinsic properties of the 2D channels, and it remains an important objective for the 2D material community.\nTo make this issue more clearly, we have added new description of such issue in the revised manuscript (in page 16), which is present as below.\n“However, the fabrication flow still relies on film transfer to ensure device performance and process yield. Owing to the absence of dangling bonds on two-dimensional materials’ surfaces, conventional atomic layer deposition is nucleation-limited and struggles to form uniform and conformal high-quality gate dielectrics, thereby hindering direct top-gate integration and necessarily need to employ a transfer process of 2D materials in this work. The development of transfer-free, industry-compatible dielectric deposition and in situ integration strategies is expected to simplify processing and facilitate the scalable implementation of two-dimensional CMOS technologies.”\n5.Dielectric Integration: The authors utilize a local back-gate configuration, likely to preserve the channel quality. Top-gate integration is typically preferred for high-density scaling but is often hindered by damage or unintended doping during the Atomic Layer Deposition (ALD) of high-k dielectrics. I suggest the authors discuss potential strategies to solve or mitigate the ALD-induced doping/damage on the MoTe2 channel, which would be a necessary step for future top-gate MSIC implementation.\nResponse: We thank the reviewer for raising the important point regarding top-gate integration and the potential impact of ALD on MoTe channel damage or doping. Top-gate architectures are essential for achieving high-density device scaling and large-scale integration; however, the direct deposition of high-k dielectrics on two-dimensional semiconductors presents intrinsic interfacial challenges. Owing to the absence of dangling bonds and reactive surface sites, ALD on two-dimensional materials is typically nucleation-limited, making it difficult to form continuous and high-quality dielectric films and often leading to a high density of interface or body defects of the gate dielectrics. These abundant defects can induce electrostatic doping to the channel, thereby affecting carrier transport characteristics and device uniformity.\nTo address these issues, we consider interface engineering to be an effective strategy for achieving high-quality top-gate integration. Specifically, introducing an ultrathin and uniform seed layer on the MoTe surface can provide stable nucleation sites, thereby promoting continuous high-k dielectric growth and reducing interface defect density. Furthermore, appropriate surface modification and interfacial treatments can improve dielectric adhesion and interfacial integrity, mitigating unintended doping. [ ref 1, ref 9] Together, these approaches offer a viable pathway toward high-quality top-gated MoTe devices while preserving channel integrity.\nTo make this issue more clearly, we have added new description of such issue in the revised manuscript (in page 9), which is present as below.\n“Although a local back-gate configuration is adopted in this study to preserve channel quality, top-gate architectures remain important for achieving high-density integration in two-dimensional electronics. However, the direct deposition of high-k dielectrics on two-dimensional semiconductors presents intrinsic interfacial challenges. Owing to the absence of dangling bonds, ALD growth is nucleation-limited and can introduce interface defects, thereby degrading carrier transport and device uniformity. Interface engineering strategies, such as the introduction of an ultrathin seed layer, appropriate surface modification, and interfacial treatments ,1, 9 can promote continuous dielectric growth and reduce interfacial defect density, providing a feasible pathway toward high-quality top-gated device integration.”\nResponse to Reviewer #4\nThis manuscript reports the growth of 4-inch, wafer-scale 2D MoTe2 thin films via the optimization of the tellurium source supply. Using these as-prepared thin films, the authors successfully demonstrated the fabrication of a 140-transistor full adder, which illustrates the potential of their material for 2D CMOS circuit integration. I recommend accepting this manuscript, provided that the authors appropriately address the following comments.\nResponse: We sincerely thank the reviewer for the thorough and constructive comments. We have carefully revised the manuscript to address each point in detail. Below are our itemized responses.\n1.Regarding the novelty of the growth method: The manuscript highlights a precursor engineering strategy. However, the authors should more clearly delineate the fundamental advancements of their method compared to the early CVD growth of 2H-MoTe reported a decade ago (J. Am. Chem. Soc. 2015, 137, 37, 11892-11895) and subsequent studies. The current description suggests modifications rather than a paradigm shift. A more detailed discussion of the specific innovations and their impact would be beneficial.\nResponse: We thank the reviewer for pointing out these relevant references and offering us the opportunity to clarify the key advances of our work. We fully acknowledge that substantial progress has been made in previous studies on MoTe synthesis, which have laid an important foundation for the field. However, the objective of this study extends beyond optimizing the performance of individual devices and instead targets the realization of medium-scale integrated circuits. To this end, two critical materials challenges remain: achieving wafer-scale growth of highly uniform MoTe films, particularly at the 4-inch scale or larger that could be compatible in industrial facilities, and maintaining precise control over the layer number (especially down to only 3 layers) while preserving such large-area uniformity. These factors directly govern device-to-device consistency and integration feasibility, and thus constitute key bottlenecks for scalable p-type two-dimensional electronics.\nTo address these challenges, the present work introduces two fundamental advances in materials growth, which together enable the realization of medium-scale integrated circuits, as detailed below.\n1) Achievement of 4-inch wafer-scale uniformity. Just as described in our manuscript, While previous reports have demonstrated MoTe growth, the maximum wafer size has been limited to approximately 1 inch or below 2 cm. [ref 17, ref 27 (J. Am. Chem. Soc. 2015, 137, 37, 11892-11895)]. For practical industrial adoption, 2D semiconductors must be scalable to substrate sizes of 100 mm (4 inches) or larger to be compatible with industry-standard high-throughput fabrication tools. The work cited by the reviewer, while valuable, does not meet this scalability requirement.\nIn our manuscript, we introduce a sustained-release tellurium precursor engineering strategy that could provide slow, precise and continuous tellurium vapor during growth process, which enables the uniform growth of 2H-MoTe across a full 4-inch wafer. This level of homogeneity is essential for circuit integration and has allowed us to demonstrate the first medium-scale integrated circuit comprising over 100 transistors based on a p-type 2D semiconductor, which is an achievement not yet reported elsewhere.\n2) Precise thickness control down to 3 layers. Scaling the semiconductor body thickness is critical for enhancing gate control and device performance. In this work, we achieve linear thickness tuning from 3 to 20 layers by controlling the Mo precursor thickness. This represents the thinnest wafer-scale MoTe reported to date (3 layers) and delivers a marked improvement in device performance, including an on/off ratio of ~ 1.29×105, nearly an order of magnitude higher than previously achieved values (~104).\nIn summary, the key innovations of this work are the scaling of uniform 2H-MoTe to a 4-inch wafer and the precise thinning of the channel to 3 layers, which together enable the first demonstration of a p-type medium-scale integrated circuit. Taken together, these results demonstrate that our work achieves substantive advances over previous CVD methods in terms of both large-area uniformity and electrical performance, highlighting the fundamental improvements enabled by our precursor and growth engineering strategies, rather than representing a simple modification of existing approaches.\nTo make this issue more clearly, we have added new description of such issue in the revised manuscript (in page 3), which is present as below.\n“In summary, the key advances of this material growth are the scaling of uniform 2H-MoTe to a 4-inch wafer and the precise thinning of the channel down to 3 layers. Together, these innovations enable the first realization of medium-scale integration, that is, with more than 100 devices, of p-type 2D semiconductors with significantly improved device performance.”\n2.Regarding the evidence for uniformity and quality: The claim of high quality and uniformity across the 4-inch wafer is central to this work. To more robustly substantiate this claim, the authors should provide structural characterization, such as selected area electron diffraction (SAED) patterns, from multiple, well-defined locations across the wafer. This data would serve as crucial evidence to support the asserted uniformity.\nResponse: We sincerely thank the reviewer for this insightful comment regarding the need for more comprehensive wafer-scale characterisation. In response, we have performed additional measurements to more rigorously evaluate the film quality and uniformity across the 4-inch wafer.\nAs suggested, we have supplemented SAED images (as shown in Fig. S7) at multiple locations, which clearly demonstrate the crystallinity of the film. Collectively, these new datasets provide stronger evidence for the high crystallinity and wafer-level uniformity of the MoTe films.\nWe have added the corresponding figures and discussion in the revised manuscript to address the reviewer’s concern more thoroughly, which are present as below.\nIn page 9 of the revised Supporting information:\nFigure S7. The figures show SAED patterns selected from different regions of MoTe thin films grown on 4-inch wafers. Scale bar 5 nm.\nIn page 6 of the revised manuscript:\n“To further assess the structural uniformity and crystallinity of the films at the wafer scale, additional transmission electron microscopy (TEM) characterizations were performed at multiple spatial locations across the MoTe films, and the corresponding selected-area electron diffraction (SAED) patterns were obtained (Fig. S7). The SAED patterns collected from different regions exhibit well-defined and consistent diffraction spots, indicating good crystallinity and a uniform crystal structure across the wafer.”\n3.Regarding the device performance: The authors report a field-effect mobility of ~7 cm2/V∙s. This value is lower than what has been previously achieved for MoTe FETs (often in the range of 10-50 cm2/V∙s), which creates a potential conflict with the claim of “high-quality” material. Furthermore, the recent report of 2D β-Bi O with a hole mobility of 136.6 cm2/V∙s (Nat. Mater. 24, 688–697, 2025) sets a new benchmark for p-type 2D semiconductors. To enhance the potential of the 2H MoTe synthesized by authors, it is critical to improve the mobility of single FET before pushing to integrated devices.\nResponse: We thank the reviewer for the important comments regarding the reported field-effect mobility and its relevance to the assessment of material quality and integration potential. We acknowledge that the average mobility reported in this work (~7 cm2/V∙s) is lower than some previously reported peak values for MoTe field-effect transistors (typically 10–50 cm2/V∙s). However, this difference should be interpreted in the context of device statistics, material form, and fabrication objectives.\nFirst, it is important to note that many of the higher mobilities reported in the literature correspond to best-performing devices (or the “champion” device), rather than statistically representative datasets. In our wafer-scale device arrays, we likewise observe individual devices with mobilities exceeding 10 cm2/V∙s (~ 11 cm2/V∙s), falling within the previously reported range. The mobility values presented in this work represent statistically averaged results obtained from a large number of devices across a 4-inch wafer, which more accurately reflect device performance under realistic integration conditions.\nSecond, most prior high-mobility MoTe transistors were fabricated on mechanically exfoliated flakes or single-domain materials, which can be effectively regarded as single crystalline within the channel region. In contrast, the present work employs wafer-scale polycrystalline MoTe films. The presence of grain boundaries in such films is known to introduce additional carrier scattering, which can reduce mobility compared with single-domain or single-crystal devices. Therefore, a moderate reduction in mobility for wafer-scale polycrystalline films is expected and consistent with established transport physics in two-dimensional semiconductors.\nThird, the extracted mobility in our devices does not directly reflect the intrinsic transport capability of the MoTe channel. To ensure compatibility with standard semiconductor manufacturing processes and enable wafer-scale batch fabrication, we adopted scalable and conventional contact schemes rather than highly specialized contact engineering approaches that are challenging to be scalable and highly controllable, e.g., the transferred van de walls contacts. As a result, the contact resistance in the present devices remains relatively high (extracted by Y function methods shown in supplementary note 1, shown in Fig. S15), which limits the measured channel current and leads to an underestimation of the apparent field-effect mobility. When the influence of contact resistance is decoupled, the effective channel mobility could be higher. While some previously reported high-mobility devices benefit from unconventional contact strategies, such approaches often face challenges in reproducibility, scalability, and integration.\nAs noted in the references cited by the reviewer (Nat. Mater. 24, 688-697, 2025), the reported carrier mobilities were primarily obtained from discrete devices fabricated within single crystalline domains of approximately 40 μm, which are intended to evaluate the intrinsic transport potential of the material in locally ideal regions. In contrast, the present work focuses on achieving statistically mobility distribution and device-to-device consistency across an entire 4-inch wafer, extending the evaluation scale from isolated domains to wafer-scale uniform films. The realization of this level of material uniformity and integration scalability highlights the practical value of our approach for large-area and application-oriented electronics.\nIn future work, we will focus on developing low-resistance contact strategies that remain compatible with semiconductor manufacturing processes, with the goal of further enhancing the extracted carrier mobility from transfer characteristics while preserving scalability and integration feasibility.\nIn page 17 of the revised Supporting information:\nFigure S15. The Y function method analysis. a Calculated Y function for the devices shown in a as a function of V . b The R of devices with different L (W =100μm).\ngs c ch ch\nResponse to Reviewer #5\nI co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature Communications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career Researchers who co-review manuscripts.\nResponse: We sincerely thank the reviewer for their positive assessment of our work. We greatly appreciate their constructive evaluation of the manuscript and the recommendation for publication, which is highly valuable to us."}, {"round": 2, "reviewer_comments": {"reviewer_2": "The authors have included further characterisation of their MoTe2 devices. The additional SAED measurements of the wafer scale grown MoTe2, discussion of the MoTe2 domain size, tests to explore the effects of ambient storage on these devices, and initial scalability experiments to produce smaller devices strengthen the author’s claims and improve the overall quality of the manuscript. With these new measurements, and their related discussion in the text the authors have addressed my previous concerns and I recommend this paper for publication in Nature Communications.", "reviewer_3": "I would like to thank the authors for their hard work and the comprehensive point-by-point response to the reviewers' comments.The revised manuscript has been substantially improved. Before final acceptance, I suggest the following minor refinements:The author observes a decrease in the ON-state current (Ion) after exposing the device to air. However, it is widely reported in the literature that the surface oxidation of MoTe2 typically results in the formation of MoOx, which induces a strong p-doping effect. Theoretically, this p-doping should lead to an increase in the Ion for p-type or ambipolar MoTe2 devices. The author should provide a detailed explanation or additional experimental evidence to clarify why the current decreased in this specific case, addressing whether factors such as increased scattering, contact resistance degradation, or moisture-induced trapping are dominant.", "reviewer_4": "The authors have adequately addressed my previous concerns. Therefore, I recommend accepting this manuscript in its current form.", "reviewer_5": "I co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature Communications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career Researchers who co-review manuscripts."}, "author_response": "Response to the Reviewers’ comments:\nResponse to Reviewer #3\nI would like to thank the authors for their hard work and the comprehensive point-by-point response to the reviewers' comments. The revised manuscript has been substantially improved. Before final acceptance, I suggest the following minor refinements: The author observes a decrease in the ON-state current (Ion) after exposing the device to air. However, it is widely reported in the literature that the surface oxidation of MoTe typically results in the formation of MoO , which induces a strong p-doping effect. Theoretically, this p-doping should lead to an increase in the Ion for p-type or ambipolar MoTe devices. The author should provide a detailed explanation or additional experimental evidence to clarify why the current decreased in this specific case, addressing whether factors such as increased scattering, contact resistance degradation, or moisture-induced trapping are dominant.\nResponse: We thank the reviewer for this important point. Surface oxidation of MoTe 2 can indeed form MoO and induce p-type doping, which in principle may increase I on for p-type or ambipolar devices [ref.18 and ref. 49]. However, previous studies indicate that the response of MoTe to ambient exposure is more complex than oxidation alone, as adsorption of O and H O at surface defects can significantly influence carrier transport [Adv. Mater. 2018, 30, 1706995].\nIn our devices, after 7 days of air exposure the transistors remain fully operational but show a slight reduction in I with minimal threshold-voltage shift. This behavior on suggests that air-induced adsorption may introduce additional carrier scattering, moisture-related trapping, which will outweigh the beneficial effect of oxidation-induced p-doping. Further studies will be conducted to distinguish channel- and contact-limited contributions."}]

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