Atomically sharp heteroepitaxial Hf_2C edge contacts enabling barrier-free carrier injection in 2D HfSe_2 semiconducting channels

Domain: physics
Published: 2026-03-10
Editorial outcome: minor_revision

Abstract
Achieving high-quality source/drain contacts in two-dimensional (2D) semiconductors remains
challenging due to Fermi-level pinning induced by metal-induced gap states (MIGS). Here, we
demonstrate an atomically sharp Hf C/HfSe edge contact formed via a laterally directed chemical
2 2
conversion, driven by catalyst-assisted hydrodeselenization and carbonization under epitaxial alignment.
Classical and ab initio molecular dynamics elucidate the atomistic mechanism of heteroepitaxial interface
formation. Scanning tunneling microscopy and spectroscopy measurements confirm suppressed MIGS at
the heteroepitaxial interface, indicating an electronically transparent junction. Electrical measurements
reveal a near-zero Schottky barrier height (≈5 meV) and reduced contact resistance (≈475 Ω·μm) when
compared with previously reported 2D edge-contact systems. When co-integrated with a van der Waals-
integrated native high-κ HfO gate dielectric within a single HfSe channel, the devices exhibit a
2 2
subthreshold swing of 62 mV/dec and on-state current density of 920 μA/μm. This integrated platform
establishes a scalable design framework that couples contact and gate-stack engineering for next-
generation 2D logic technologies.

Introduction
As outlined in the International Roadmap for Devices and Systems (IRDS), two-dimensional (2D)
semiconductors are considered promising channel innovations for sub-1-nm logic nodes1, due to their
intrinsic advantages, particularly in terms of strong immunity to short-channel effects and the potential
for high on-off current ratios2. These merits originate from their atomically thin nature, low dielectric
permittivity, dangling-bond-free surface, moderate density of states, favorable effective mass, and
efficient in-plane thermal dissipation3,4. Translating these intrinsicS advantages into practical device
S
performance, however, requires the formation of high-quality junctions with atomically clean and
E
crystallographically coherent interfaces. In particular, the source/drain contact is critical; achieving low
R
contact resistance (R ) approaching the quantum limit iPs essential for efficient carrier injection and for
C
sustaining high drive current in aggressively scaledN logic technologies5. However, achieving high-quality
contacts in 2D semiconductors remains a long-Istanding and fundamental challenge, primarily due to
E
Fermi-level pinning (FLP) at the metal–2D semiconductor interface, which originates from metal-induced
L
gap states (MIGS). During conventional metal deposition, the metal wavefunction penetrates into the
C
bandgap of the 2D semiconductor, Igenerating interface states localized near the charge-neutrality level
T
and thereby strongly pinning the metal Fermi level6,7. Structural and chemical perturbations introduced
R
during deposition—such aAs chalcogen vacancies, interstitial incorporation, interfacial strain, and metal–
chalcogen reactions—further increase the density of interfacial states8. As a result, the Schottky barrier
height (SBH) becomes largely insensitive to the metal work function, deviating from the ideal Schottky–
Mott limit and severely limiting efficient carrier injection across metal–2D semiconductor junctions9.

To address these limitations, a variety of contact-engineering strategies have been explored, including
doping, van der Waals (vdW) contacts, and semimetal contacts. Doping approaches aim to emulate the
heavily doped source/drain regions in silicon technology, where high doping concentrations narrow the
depletion width and enable direct carrier tunneling into the band edges, thereby facilitating near-ohmic
contact formation. For example, atomic-layer yttrium doping of MoS has been shown to induce a silicide-
2
like metallic phase, yielding an R as low as 69 Ω·μm10. Despite such promising results in tailored systems,
C
the intrinsically high dopant ionization energies and the atomically thin nature of 2D semiconductors
fundamentally limit dopant solubility, generally leading to structural defects and deep-level traps that
degrade contact performance11. Moreover, in 2D semiconductors, the depletion width at the interface
depends only weakly on carrier concentration, making it difficult to realize true ohmic behavior through
tunneling alone. Alternatively, non-disruptive approaches such as charge-transfer doping and interfacial
dipole engineering have also been proposed, enabling localized carrier accumulation via spontaneous
Fermi-level equilibration without introducing structural disorder12. However, these methods are highly
sensitive to ambient conditions and typically require full encapsulation, posing significant challenges for
scalable integration and long-term stability13.

vdW contacts—first demonstrated by Liu et al. using dry-transferred metal electrodes14—offer a
promising pathway to mitigating FLP by physically decoupling the metal–2D semiconductor interface,
thereby minimizing interface disorder and suppressing the formation oSf MIGS. Nevertheless, the inherent
S
tunneling barrier imposed by the vdW gap fundamentally limits carrier injection by reducing the spatial
E
overlap between the metal and 2D semiconductor wavefunctions, even when favorable band alignment is
R
present15. More recently, semimetal contacts have emerPged as a frontier strategy, leveraging their low
density of states near the Fermi level to intrinsically suppress MIGS and mitigate FLP. Shen et al.
N
demonstrated that bismuth (Bi) contact to monolaIyer MoS results in a near-zero SBH and reduced R of
2 C
≈123 Ω·μm, maintaining linear transport bEehavior even at cryogenic temperatures16. Li et al. further
L
advanced this approach by forming oriented antimony (Sb) interfaces, achieving coherent band
C
hybridization across the interface anId R
C
values approaching the quantum limit (≈42 Ω·μm)17. However,
T
such elemental semimetals inherently possess material constraints that hinder their practical use in
R
advanced device integratiAon. Specifically, Bi has a melting point below 300 °C, and Sb exhibits high
atomic diffusivity18, making both incompatible with the stringent thermal budget and reliability
requirements of back-end-of-line processes19. Their propensity for metal diffusion further exacerbates
integration challenges, particularly as diffusion control has become a critical reliability issue in modern
industrial contact integration processes.

Despite remarkable progress in contact engineering for 2D semiconductors, most state-of-the-art
approaches still rely on top-contact geometries. As device dimensions enter the extremely scaled regime,
the contact length (L ) proportionally shrinks, leading to insufficient transfer length (L ) and pronounced
C T
current crowding, which exponentially increases the R 20. Edge-contact architecture has therefore
C
attracted considerable attention, as they enable in-plane carrier injection with nanometer-scale L .
Early
T
demonstrations formed such contacts by plasma etching to expose the 2D semiconductor edge prior to
metal deposition21, validating the conceptual advancement of edge injection but inevitably generating
interfacial disorder that induces FLP and non-ideal Schottky barriers. To mitigate interfacial damage,
subsequent strategies such as epitaxial lateral junctions and thermally induced on-device phase
engineering have been proposed22,23. However, these approaches still suffer from unacceptably high R
C
and inherent limitations in achieving precise, localized stoichiometry, which remain fundamental
bottlenecks to scalable integration. More fundamentally, such approaches are incompatible with the
evolution toward multi-sheet systems, where the physical underlap between the contact and the gated
channel becomes a non-negligible component of the total series resistance3. This parasitic resistance
introduces an additional voltage drop between the contact and the active channel region, lowering the
effective gate overdrive and partially offsetting the gains from R reduction and ultimately constraining
C
overall supply voltage scaling. Hence, establishing and understanding a genuinely laterally directed, high-
quality edge contact to 2D semiconductors is essential for advancing contact engineering beyond the
current limits.

In this work, we present an interface-engineered straPtegy for integrating an atomically sharp-edge-
embedded contact in a 2D semiconductor. By inducing simultaneous edge-initiated hydrodeselenization
and carbonization of HfSe under thermally anId catalytically activated conditions via a controllable
2
chemical vapor deposition (CVD) process—Ethereby converting HfSe into Hf C—an atomically sharp
2 2
L
heteroepitaxial interface was achieved. Ab initio molecular dynamics (AIMD) simulations based on
C
density functional theory (DFT)I further elucidated the atomistic mechanism of edge-initiated
T
heteroepitaxial interface formation and the evolution of directionally oriented atomic configurations.
R
Furthermore, we employeAd scanning tunneling microscopy/spectroscopy (STM/STS) and Kelvin probe
force microscopy (KPFM) to investigate the local density of states (LDOS) and work function. These
measurements revealed the metallic nature of Hf C with a work function of ≈4 eV, distinct from the
2
semiconducting HfSe . Notably, line STS (LSTS) directly confirmed suppressed MIGS across the
2
heteroepitaxial junction, providing critical insight for heteroepitaxial contact engineering. The high-
quality Hf C/HfSe interface was further demonstrated by the fabricated Hf C/HfSe field-effect
2 2 2 2
transistors (FETs), which exhibited a near-zero SBH (≈5 meV) and a reduced R (≈475 Ω·μm),
C
outperforming previously reported 2D semiconductor-based edge-contact technologies. To further
demonstrate the potential of the proposed edge-contact, FETs with a gate length (L = 200 nm),
g
incorporating a vdW interface-integrated native high-κ dielectric (HfO ) within a single HfSe channel
2 2
were fabricated, exhibiting a nearly ideal subthreshold swing (SS) of 62 mV/dec at room temperature (300
K) along with a high on/off ratio (≈108). The obtained on-state current density (I ) reaches up to 920
on
μA/μm at a drain bias (V ) = 1 V, surpassing the projected IRDS targets. These results underscore the
DS
pivotal role of atomically engineered edge-contacts in achieving low R , representing a major step toward
C
scalable contact engineering and the integration of 2D semiconductor logic architectures beyond silicon.

Results
Atomically sharp heteroepitaxial edge-embedded Hf C/HfSe lateral junction
2 2
Figure 1a presents a schematic of the heteroepitaxial lateral edge-contact structure of the Hf C/HfSe
2 2
heterojunction studied in this work. A pristine HfSe flake (≈ 40 nm) was prepared and selectively
2
converted into a 2D metallic carbide (Hf C) via edge-initiated hydrodeselenization and carbonization
2
S
under a thermally activated process with CH and H gas injection. The detailed experimental conditions
4 2 S
and procedures are provided in the Methods section and SuEpplementary Fig. 1. This edge-initiated
R
chemical conversion process24 is schematically illustrated in Fig. 1b. Under a CH /H /Ar gas atmosphere,
4 2
P
molecular H
2
dissociates into reactive H° radical on the catalyst surface, which selectively cleave the
N
weak Hf–Se bonds exposed at the edges of HfSe
2
. The liberated Se atoms react with H° radicals to produce
I
volatile H Se molecules that desorb from the su rface. Simultaneously, CH ° radicals generated from CH
2 E 3 4
decomposition occupy the Se vacancies Lcreated during this hydrodeselenization process and bond with
C
exposed Hf atoms, leading to the formation of Hf–C bonds and subsequent Hf C conversion. As the
2
I
reaction progresses, this lateral Tconversion front propagates inward from the edges, yielding a well-
R
defined heteroepitaxial Hf C/HfSe interface. The converted Hf C area can be controlled by adjusting the
2 2 2
A
reaction time (Supplementary Fig. 2).

By employing the proposed methodology, the formation of the Hf C/HfSe heterojunction was
2 2
experimentally demonstrated, as evidenced by the cross-sectional scanning transmission electron
microscopy (STEM) image and the corresponding energy-dispersive spectroscopy (EDS) elemental
mapping (Fig. 1c). The EDS mapping clearly reveals a distinct boundary between the C and Se elements,
consistent with the STEM contrast, thereby confirming the formation of a well-defined interface between
Hf C and HfSe (see Supplementary Figs. 6-8 for additional material characterization details). The fast
2 2
Fourier transform patterns further verify the layered-crystalline structure of HfSe together with the
2
crystallographically oriented Hf C, consistent with other layered transition-metal carbides25 (see also
2
Supplementary Fig. 3). Notably, the enlarged cross-sectional STEM image of the dashed-square region in
Fig. 1c clearly reveals an edge-embedded heteroepitaxial junction, demonstrating the formation of an
atomically sharp interface between Hf C and HfSe achieved through the edge-initiated chemical
2 2
conversion process (Fig. 1d). The converted Hf C region exhibits a lattice spacing of 2.25 Å, whereas
2
HfSe retains its characteristic 6.1 Å spacing, accompanied by an interfacial lattice tilting of ≈150°,
2
consistent with the mechanistic study discussed in the following section. Additional structural analysis—
confirming atomically sharp interfaces on both the right and left sides and revealing the top-view
morphology of the Hf C/HfSe heterojunctions—further verifies the formation of an atomically sharp
2 2
interface (Supplementary Figs. 4 and 5). These comprehensive structural and materials characterizations
verify the formation of a high-quality, atomically sharp Hf C/HfSe heteroepitaxial interface, thereby
2 2
establishing a robust laterally configured heterojunction within the 2D semiconductor channel. The
scalability of the proposed methodology toward uniform wafer-scale integration can be investigated by
coupling it with established wafer-scale channel-formation routes, while maintaining compatibility with
standard lithography and enabling a practical overlay-tolerancEe window through a globally controlled,
self-aligned conversion step.

Atomistic mechanism of heteroepitaxial Hf
2
C /HfSe
2
interface formation
To investigate the growth mechanism of Hf C/HfSe upon the introduction of C atoms, we performed
2 2
classical molecular dynamics (CMD) simulations by employing machine-learned potentials, as shown in
Fig. 2a,b (see Methods section foTr details). The simulation was initiated with a pristine HfSe
2
crystal. To
simulate the edge-initiated chemical conversion process, we iteratively performed 97 cycles of
modification and CMD simulation. For each cycle, one C atom was substituted for every four Se atoms
removed from the left side of the HfSe slab. Starting from the initial structure, the output structure from
2
each step was used as the input for the next iteration. Our results reveal that, when a C atom initially
replaces a Se atom, the C atom bonds with three Hf atoms, but as more Se atoms are removed, it becomes
surrounded by more Hf atoms, and finally, it is surrounded by six Hf atoms, as in the bulk structure
(Supplementary Fig. 11a). As the coordination number of the Hf atom changes from 6 to 3, the newly
formed Hf C layer possesses a distinct crystal structure from the parent HfSe with a thinner thickness
2 2
(Supplementary Fig. 11b), consistent with our experimental results (Supplementary Figs. 9 and 10), and
furthermore, a significant tilting of the Hf C layers with respect to the HfSe is observed at the interface.
2 2
To further investigate the atomic structure and identify a more precise, stable configuration of the interface,
we performed AIMD simulations (see Supplementary Video). The initial configuration for the AIMD
simulation was constructed by taking the HfSe crystal structure and substituting a portion of the Hf and
2
Se atoms with C and Hf atoms, respectively, thereby creating a Hf C region within the HfSe matrix.
2 2
Following this, an AIMD simulation and subsequent structure relaxation were performed to find a
plausible interface structure. The resulting atomic configuration reveals a tilting of the hafnium (Hf) layer,
which is consistent with the observations from our CMD simulations. When viewed along the plane of
the 2D HfSe layer, the interfacial lattice tilting is measured to be ≈150° (Fig. 2c), whereas an observation
2
along the c-axis reveals a tilting of ≈165° for the Hf layer (Fig. 2d). This structural rotation results from
the formation of more Hf-Se bonds at the interface, which is associated with the increased Hf density in
the Hf C layers.
2

Electronic characterization of Hf C/HfSe interface
2 2
To investigate the local electronic structure and directly probeE for MIGS, we performed high-resolution
STM/STS measurements to map the LDOS at the Hf C/HfSe lateral heterojunction. A key advantage of
2 2
the lateral architecture is that it enables direct in-plane STM/STS analysis across the interface, as
illustrated in Fig. 3a. An STM tip is scanned from the Hf C region to the HfSe region across the
2 2
heterojunction. Figure 3b shows a typical STM image of the junction, which exhibits the bright Hf C
2
region against the relatively darker HfSe region, with the white arrow indicating the lateral location along
2
which line spectroscopy was performed. This topographic contrast indicates a higher LDOS near the
Fermi level for Hf
2
C. The poinTt-specific differential conductance (dI/dV) spectra (Fig. 3c) reveal the
LDOS for both Hf C and HfSe . The HfSe exhibits a bandgap of approximately 1.1 eV and displays
2 2 2
typical n-type semiconducting characteristics, consistent with its known electronic behavior26. In contrast,
Hf C demonstrates a metallic LDOS profile with no bandgap, evidencing its metallic nature. This
2
spectroscopic evidence underscores the distinct electronic properties of the two materials. To investigate
the lateral heterojunction in detail, spatially resolved LSTS was performed following the white arrow in
Fig. 3b. The resulting LSTS mapping (Fig. 3d) presents the evolution of the LDOS across the Hf C/HfSe
2 2
interface. The LSTS result demonstrates an exceptionally sharp transition between the metallic LDOS
characteristic of Hf C and the semiconducting LDOS of HfSe . Crucially, there are no detectable in-gap
2 2
states within the HfSe bandgap at the interface. This abrupt electronic change and clear preservation of
2
the bandgap at the junction confirm the suppressed MIGS, indicating the formation of a well-defined and
electronically clean structure. These results are further corroborated by first-principles DFT calculations
of the electronic band structure (Supplementary Fig. 13). These findings provide direct experimental
evidence for the realization of suppressed MIGS at the Hf C/HfSe interface. On the basis of the
2 2
experimentally resolved interfacial electronic structure, the electron energy barrier can be determined
from the measured work function of Hf C (≈4 eV) obtained by KPFM analysis (Supplementary Fig. 14)
2
together with the known electron affinity of HfSe 27, indicating barrier-less carrier injection at the
2
interface and the formation of an ohmic contact (Supplementary Fig. 15).

Electrical characterization of Hf C/HfSe interface
2 2
To elucidate the contact properties between Hf C and HfSe , electrical characterization was performed,
2 2
as detailed in the Methods section. Prior to evaluating the electrical contact characteristics of the
Hf C/HfSe heterojunction, the intrinsic electrical properties of Hf C were examined, confirming its
2 2 2
purely metallic nature consistent with the LDOS results (Fig. 3c and Supplementary Fig. 16). Figure 4a
compares the transfer characteristics of Hf
2
C- and Ti/Au-contacEted HfSe
2
FETs with a 40-nm-thick HfSe
2
channel (see Supplementary Fig. 17 for the Au-only-contacted device characteristics). The Hf C/HfSe
2 2
FET exhibits markedly enhanced conduction with an improved I , in contrast to the Ti/Au-HfSe FET.
on 2
Moreover, the Hf C/HfSe interface shows linear output characteristics at both room and low temperatures
2 2
(Fig. 4b and Supplementary Fig. 18), indicati ve of efficient carrier injection across the interface. The
linear output behavior observed under various on-state gate-bias conditions further confirms the stable
ohmic contact behavior at the Hf C/HfSe interface (Fig. 4c). Similar results are also observed in devices
2 2
with scaled channel lengths (SupTplementary Fig. 19). In contrast, the Ti/Au-HfSe
2
FET exhibits nonlinear
output characteristics (see Supplementary Fig. 20 for details), reflecting the presence of a potential barrier,
consistent with previous reports on Schottky- or interfacial-layer-limited contacts28. To further validate
the contact nature, temperature-dependent transfer characteristics were measured for both Hf C/HfSe and
2 2
Ti/Au-HfSe FETs (Fig. 4d). For the Hf C/HfSe FET, enhanced phonon scattering at elevated
2 2 2
temperatures reduces the I , whereas the suppression of scattering at lower temperatures enables more
on
efficient carrier transport, resulting in a higher I — consistent with the ohmic contact behavior reported
on
in previous studies29. By contrast, the Schottky-type Ti/Au-HfSe FET exhibits thermally activated
2
transport behavior. At low temperatures, insufficient thermal energy limits carrier injection across the
barrier, leading to a reduced I , while at higher temperatures, increased thermal excitation enables carriers
on
to surmount the SBH, thereby enhancing the conduction. To quantitatively evaluate the barrier height of
Hf C/HfSe interface, the SBH was extracted from temperature-dependent transfer characteristics using
2 2
the Arrhenius plot (Fig. 4e), following the thermionic emission model, I = A* T2exp (-𝜑 /𝑘 T), where
DS 2D 𝐵 𝐵
A* = 𝑞 (8𝜋𝑘3𝑚∗ )1/2/ℎ 2, 𝜑 is the effective barrier height, 𝑘 is the Boltzmann constant, 𝑞 is the
2D 𝐵 𝐵 𝐵
elementary charge, 𝑚∗ is the effective carrier mass, T is the absolute temperature, and ℎ is Planck’s
constant30. The extracted SBH was found to be suppressed (≈5 meV), demonstrating nearly barrierless
contact consistent with the electronic demonstration discussed above. Figure 4f compares the nonlinearity
factor (N) of the HfSe /Hf C and Ti/Au-HfSe FETs, obtained from their output characteristics. For
2 2 2
quantitative assessment, N was estimated using the differential relation31, N = [(V/I) (dI/dV)] – 1, which
represents the deviation from the linear regime (N = 0). This formulation is closely related to a curvature-
based definition, N = (d2I/dV2)/[2(dI/dV)], but provides greater numerical stability for experimental data
analysis31. An increase in N corresponds to enhanced nonlinearity, indicating a higher potential barrier at
the interface. As shown in the inset of Fig. 4f, N ≈ 0 was maintained across all V ranges and throughout
DS
the entire temperature range, confirming ohmic contact behavior originating from the atomically sharp
interface-integrated edge contact. In contrast, the Ti/Au-HfSe FET exhibited a pronounced nonlinearity
2
factor of approximately N ≈ 3, characteristic of Schottky-typEe contact behavior. Furthermore, the R ,
C
extracted using the transfer-length method, exhibited a reduced R of ≈475 Ω·μm (Fig. 4g and
C
Supplementary Fig. 21). Similar results were also obtai ned upon scaling the channel length and thickness
(down to bilayer), further confirming stable ohmic contact behavior and the benefits of the proposed
Hf C/HfSe edge-contact geometry (Supplemen tary Figs. 22 and 23). This performance surpasses that of
2 2
recently reported edge-contact systems baLsed on 2D semiconductors21-24,32-36, demonstrating the superior
contact performance of the Hf C/HfSe interface (Fig. 4h and Supplementary Table 1). A current-density
2 2
plot as a function of 2D-channTel thickness for reported edge-contacted devices is also provided in
Supplementary Fig. 24. To further demonstrate the intrinsic advantage of the proposed edge contact, we
examined the transfer characteristics of devices with varying L (Fig. 4i). For the Hf C/HfSe edge contact,
C 2 2
devices with different L exhibit nearly identical I , indicating a genuine edge profile and pure in-plane
C on
carrier injection, as the current remains invariant with changes in L . In contrast, for the Ti/Au-HfSe top-
C 2
contact architecture, reducing L results in a pronounced degradation in device performance, particularly
C
when L becomes shorter than the L (30–40 nm for 2D semiconductors)37, which defines the
C T
characteristic distance over which most carriers are injected (see Supplementary Fig. 25 for details).

Electrical performance of Hf C-HfO co-integrated HfSe FET
2 2 2
To demonstrate the scalability and practical integration of the proposed edge-embedded contact
architecture, we further implemented a co-integrated HfSe FET (Fig. 5a), in which an atomically sharp
2
Hf C edge contact and a vdW interface-integrated native HfO gate dielectric were simultaneously
2 2
incorporated within a single HfSe channel (≈15 nm) with a gate length (L ) of 200 nm (Fig. 5b). The
2 g
detailed fabrication procedures are provided in the Methods section and Supplementary Fig. 1. To evaluate
the device performance, transfer characteristics were measured under various V
DS
(Fig. 5c). The co-
integrated HfSe FET exhibited an enhanced I of up to 920 μA/μm at V = 1 V, along with a near-ideal
2 on DS
SS value of 62 mV/dec (over four orders of I where I denotes the drain-to-source current) at room
DS, DS
temperature (300 K), a high on/off current ratio (≈108), and a low gate leakage current (≈10-6 A/cm2).
Furthermore, negligible gate hysteresis (≈2.8 mV), which is closely associated with dielectric and
interfacial trap states38, confirms the effective suppression of charge trapping at the vdW interface and
within the HfO dielectric layer (Supplementary Figs. 26a and 27). Comparable field-effect mobility to
2
that reported for MoS upon channel-thickness scaling39,40 was also observed (Supplementary Figs. 35-
2
37). Detailed electrical and interfacial characterization of the vdW interface-integrated gate stack is
provided in Supplementary Figs. 28-30. In addition, highlEy reproducible device performance was
confirmed across 20 identically processed co-integrated HfSe FETs, all showing consistent I values
2 on
(Fig. 5d). Device statistics and a summary of key perfor mance metrics are also provided in Supplementary
Fig. 31 and Supplementary Table 2. For stability evaluation, within the repeated dual-direction transfer
sweep of 200 cycles, the co-integrated HfSe FET exhibited negligible variation in I , suggesting the
2 on
robust and clean interface between Hf
2
C Land HfSe
2
(Fig. 5e). The thermal stability and reliability of the
co-integrated HfSe FETs were further assessed through thermal cycling and bias–temperature stress test
2
(Supplementary Figs. 32 and 33)T. The improved current drive primarily arises from the seamless lateral
conversion of HfSe into Hf C from the channel edge, producing an atomically coherent interface that
2 2
effectively suppresses MIGS, unlike conventional deposited metal contacts. This advancement not only
surpasses the projected IRDS targets but also achieves performance comparable to the most advanced
contact technologies reported to date (Fig. 5f)1,16,17,20,41-48. Co-integrated HfSe FETs with an atomically
2
thin bilayer channel also achieved improved electrostatic control while preserving carrier-injection
efficiency, offering a scaling demonstration that is technologically relevant to the channel-thickness
regime of state-of-the-art Si nanosheet nodes (Supplementary Fig. 34). To further assess the intrinsic drive
capability beyond the DC limit, pulsed measurements with150-ns drain pulses were conducted (Fig. 5g).
While the device exhibited an I of 920 μA/μm under DC operation, the pulsed I increased to 1070
on on
μA/μm at V = 1 V, accompanied by a delayed onset of the saturation regime. This enhancement is
DS
attributed to the suppression of self-heating and hot-electron trapping49, which delays the velocity
saturation, facilitated by the atomically coherent Hf C/HfSe interface, thereby more closely reflecting
2 2
the intrinsic current-driving capability relevant to circuit operation. Based on the measured I values, the
on
intrinsic gate delay was estimated to be 35 ps at 920 μA/μm and 18.8 ps at 1070 μA/μm (Supplementary
Fig. 26b), which is comparable to advanced Si FETs and industrial roadmap targets. Further optimization
toward ultimate scaling while maintaining functional device operation will be pursued in future work,
guided by sub-50-nm device simulations (Supplementary Fig. 38) and gate-stack engineering (e.g., EOT
scaling via thinner dielectrics and/or higher-κ materials). Collectively, these results underscore that the
Hf C/HfSe edge-contact, when co-integrated with a high-κ HfO gate stack, offers a scalable and high-
2 2 2
performance contact architecture capable of delivering high drive current, low power consumption, and
the possibility of circuit-level applicability—establishing a promising platform for next-generation 2D
semiconductor logic technologies.

Methods
Fabrication of the fully converted Hf C
2
Initial HfSe flakes (≈40 nm) were mechanically exfoliated using Scotch tape and dry-transferred onto
2
the cleaned SiO /p+-Si substrates. All exfoliation and transfer processes were carried out in an Ar-filled
2
glove box, where the O and H O concentrations were maintained below 0.1 ppm to prevent oxidation
2 2
and contamination. Prior to the conversion process, the HfSe flakes were patterned into elongated square
2
regions (5 μm × 3 μm) using inductively coupled plasma etching to define the conversion area. Edge-
initiated conversion of HfSe into Hf C was performed in a low-pressure chemical vapor deposition (CVD)
2 2
system operating at 2.0 × 10-4 Torr. The samples were placed beneathS folded Cu foil (99.9%, Alfa Aesar)
and positioned at the center of a 4-inch quartz tube furnace. The quartz tube was first purified at 800 °C
under a 100 sccm Ar flow for 1 h to remove residual contaminants. After cooling, the chamber atmosphere
was stabilized under a CH
4
(100 sccm), H
2
(5 sccm) and APr (100 sccm) gas mixture. The temperature was
then raised to 800 °C and maintained for 2 h to initiate the chemical conversion process and achieve the
full conversion into Hf C. Following the reactionI, the system was cooled to room temperature at a rate of
2
4.75 °C/min under continuous gas flow. TEhe conversion rate of the Hf C was estimated to be ≈41.5
2
nm/min (2.5 µm/h) toward the flake center (Supplementary Figs. 9 and 10).

Fabrication of the Hf C/HfSe edge-contact
2 2
Prior to the conversion procesRs, the ≈40 nm HfSe flakes were patterned into elongated square regions (5
2
μm × 3 μm) using inductively coupled plasma etching to define the conversion area. Selective conversion
to realize the Hf C/HfSe heteroepitaxial interface was achieved using a lithographically defined SiO
2 2 2
mask layer. Electron-beam lithography (EBL) was used to pattern the regions to be protected, followed
by deposition of a 180 nm-thick SiO layer using electron-beam deposition (EBD). The conversion
2
process was then repeated under identical CVD conditions, with the temperature held at 800 °C for 1 h
under a CH /H /Ar gas flow (100/5/100 sccm). The masked regions remained as pristine HfSe , whereas
4 2 2
the exposed areas were converted into Hf C, resulting in the formation of a lateral Hf C/HfSe /Hf C
2 2 2 2
heterostructure. All structural and compositional characterizations were performed on samples fabricated
using this procedure.

Fabrication of the Hf C/HfSe FET
2 2
Following the same fabrication procedure used for the Hf C/HfSe edge-contact structures, Ti (10 nm)/Au
2 2
(40 nm) source and drain electrodes were deposited by EBD under a high vacuum of 4 × 10⁻⁷ Torr. All
electrical measurements of the Hf C/HfSe devices were performed on samples fabricated using this
2 2
process.

Fabrication of the HfO /HfSe gate-stack
2 2
HfSe flakes were mechanically exfoliated using Scotch tape and dry-transferred onto the cleaned
2
substrates. All exfoliation and transfer processes were conducted inside a glove box under controlled
conditions to prevent ambient contamination, where both O and H O concentrations were maintained
2 2
below 0.1 ppm. To form HfO as a high-κ gate dielectric with a vdW interface on HfSe , O plasma
2 2 2
oxidation was carried out at a power of 10 W with an O flow rate of 5 sccm and a chamber pressure of
2
470 mTorr under fixed process conditions50,51. The thickness of the converted HfO layer was controlled
2
by adjusting the plasma exposure time and the initial thickness of prSistine HfSe
2
, based on an oxidation
rate of ≈2.1 nm/min (see Supplementary Fig. 20 for details).

Fabrication of the Hf C-HfO co-integrated HfSe FET
2 2 2
All process parameters for carbonization and plasma oxidation were identical to those described above.
≈40 nm-thick HfSe flakes were transferred onto th N e SiO /p+-Si substrate. Prior to the device fabrication
2 2
process, the HfSe
2
flakes were patterned into el ongated square regions using inductively coupled plasma
etching to define the conversion area. Subsequently, polymethyl methacrylate (PMMA) 495 and 950
layers were spin-coated at 2000 rpm Cfor 5 s and 4000 rpm for 35 s, respectively, followed by baking at
180 °C for 2 min on a hot plate. A SiO masking layer was then partially deposited on the HfSe surface
2 2
by the EBL and EBD processR. During the subsequent CVD process, the exposed regions of HfSe were
2
laterally converted into Hf C, whereas the areas covered by SiO remained unreacted. After carbonization,
2 2
the SiO masking layer was removed by a peel-off process, yielding a lateral Hf C/HfSe /Hf C
2 2 2 2
heteroepitaxial structure. A PMMA layer was then once again applied, and EBL was employed to expose
the unconverted channel region previously protected by the SiO mask. Partial vertical oxidation of the
2
exposed region was performed by O plasma, yielding ≈10 nm of HfO . Through this process, a FET was
2 2
realized in which the atomically sharp interface-integrated Hf C/HfSe edge-contact and the vdW
2 2
interface-integrated HfO /HfSe gate-stack were co-integrated within a single HfSe channel.
2 2 2
Finalelectrodes0 nm)/Au (40 nm) source and drain electrodes and a 20 nm-thick Au top-gate electrode
were deposited by EBD under high-vacuum conditions (4 × 10⁻⁷ Torr). The overall fabrication process
flow and corresponding OM images are shown in Supplementary Fig. 1.

Sample characterization
OM (Olympus, BX51M) and FE-SEM (JEOL, JSM7500F) were used to observe the sizes and colors of
the prepared samples and fabricated devices. Raman spectroscopy at an excitation wavelength of 523 nm
was used to characterize HfSe , Hf C and HfO . The thickness of the flakes was determined using an
2 2 2
atomic force microscope (AFM, Park Systems Corp., NX-10) in the non-contact mode with PPP-NCHR
probe tips (nanosensors). The work function of Hf C was also measured using the same AFM equipment.
2
A scanning rate of 0.2 Hz with 256 scanning lines was used. The measurements utilized an Au-coated tip
(HQ:NSC36/Cr-Au, Cantilever type B, MikroMasch). The tip had a nominal radius below 35 nm and a
height of 15 μm. Three cantilevers were present per chip, with typical properties: force constant 2 N/m,
resonance frequency 130 kHz, and cantilever length 90 μm. The 30 nm Au coating with a 20 nm Cr
sublayer ensures both electrical conductivity and laser reflectivity. The cross-sections were observed using
transmission electron microscopy (TEM, JEOL, TEM2100F) at an accelerating voltage of 200 kV. X-ray
photoelectron spectroscopy (XPS, MultiLab 2000, Thermo VGE, Mg Kα source) was employed to analyze
the chemical states and composition, with the binding energy calibrated to the C 1s peak at 284.8 eV.

Electrical characterization
All the electrical measurements were performed iIn a probe station (MSTECH) with a vacuum pressure of
10-6 torr using a semiconductor analyzer (KeEithley 4200). A Keithley 4200 instrument was used to provide
the supply voltage to all the devices in this study. Pulsed I–V measurements were carried out using the
4225-PMU and 4225-RPM modulesI with Keithley 4200.

Electronic characterization
STM/STS experiments were carried out in a commercial LT-STM (Omicron, Germany) with a base
pressure of approximately 10-10 Torr. All the STM/STS measurements were performed at room
temperature. Electrochemically etched tungsten tips were used after the removal of surface oxide by
electron bombardment in the ultrahigh vacuum chamber. STM images were acquired in the constant-
current mode, and the bias voltages were applied to the sample with respect to the STM tip. The dI/dV
spectra were collected by using the standard lock-in technique with a voltage modulation of 50 mV and
frequency of 817 Hz. For STM measurements, a 50 nm-thick Au electrode was deposited on the substrate
using EBD to provide electrical contact to the sample.

Computational details
Classical molecular dynamics simulations were performed using the Atomic Simulation Environment
(ASE)52. The interatomic interactions were described using a pre-trained machine learning interatomic
potential, specifically the Machine Learning Atomic Cluster Expansion (MACE) model (mace-mp-0b3-
medium)53. Molecular dynamics simulations were performed using the NVT (canonical) ensemble. The
system temperature was maintained at around 1000 K using a Langevin thermostat (Supplementary Fig.
12). Each molecular dynamics simulation was run for 500 steps with a time step of 1 fs, corresponding to
a total simulation time of 0.5 ps. HfSe on the right side (c.a. 10 Å) were kept fixed to maintain the bulk
2
structure. Following the CMD simulation, the final atomic structure was fully optimized using the
Broyden–Fletcher–Goldfarb–Shanno algorithm until the residual forces on all atoms were converged to
below 0.01 eV/Å. To predict the interface structure between HfSe and Hf C, we performed spin-polarized
2 2
DFT calculations using the Perdew-Burke-Ernzerhof (PBE) exchange-correlation functional54. The
interactions between ions and electrons were described by the Projector Augmented-Wave (PAW)
method55, as implemented in Vienna Ab initio Simulation Package (VASP)56. For a better description of
dispersion interactions, DFT-D3 method with Becke-Johnson Edamping function was used57. The initial
interface structure was prepared by building a supercell of HfSe and substituting Hf and Se atoms in the
2
middle for C and Hf atoms, respectively. We performe d ab initio molecular dynamics simulations using
an NVT ensemble with a Nosé–Hoover thermostat to maintain a constant temperature of 500 K58. The
simulations were run for a total of 1500 fs, with a time step of 1 fs. The energy cutoff for the plane waves
was set to 400 eV. After the AIMD simuLlation, we further optimized the cell parameters using a higher
energy cutoff of 500 eV until the residual forces become less than 0.03 eV/Å.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "Bhin et al examine edge contacts for semiconducting 2D HfSe2, via selectively converting semiconductor region to a metallic Hf2C. They conduct STEM imaging, STM mapping, and employ molecular dynamics simulations to understand the Hf2C and HfSe2 interfaces. Lastly, they demonstrate high-performance 2D transistors using these edge contacts and achieve >900 uA/um on-state current. The work is reasonably comprehensive, however there are major points that should be addressed in order to meet the high standards of Nature Communications:\n1) The work is quite timely and takes some inspiration from the bismuth oxyselenide work (https://www.nature.com/articles/s41563-025-02117-w) -- obtaining clean high-k and contact interfaces via converting the existing 2D semiconductor. However, the original appeal of 2D transistors is retaining device performance in monolayer semiconducting channels. Because these HfSe2 samples are exfoliated, these are certainly thicker than monolayer and may even have nonuniform thicknesses through the manuscript, which raises several questions:\n1a - Can the authors clarify the approximate HfSe2 thickness for all devices throughout the manuscript? This should be inside all of the figure captions and appropriately described throughout the main text + SI discussions. Otherwise, the authors are accidentally comparing monolayer TMD studies to their very thick HfSe2 work, which could be misleading.\n1b - Achieving high current densities is an easier task for thick 2D semiconducting channels, even with standard electron-beam evaporated contacts. Is it possible for the authors to demonstrate these contacts on a monolayer HfSe2 semiconductor channel? They have two optional approaches: (1) it appears that the authors can convert HfSe2 to high-quality HfO2. In other words, it looks straight-forward for them to oxidize their already existing devices down to monolayer (or few layer) thick channels and have thicker Hf2C contacts. (2) Reconstruct their edge-contact devices with a fully monolayer HfSe2 to start (e.g., have monolayer contacts too).\n1c - It should be clear inside the benchmarking plot which devices are monolayers or few-layers (Fig. 5f). Perhaps a plot with current density as a function of semiconductor channel thickness would be fruitful for the readers to see and contextualize this work's impact also.\n1d - HfSe2 has been less studied than MoS2 and WSe2 -- from a theoretical perspective, the band gap is much smaller (1.1 eV bulk rather than 2.1 eV in monolayer MoS2). Is the mobility also smaller? Please cite relevant 2D semiconductor computational work (https://www.nature.com/articles/s41524-024-01417-0). Having this comparison for their devices would be excellent, and again, ideally experimentally measured values for monolayer or few-layer HfSe2.\n1e - Si nanosheets have mitigated mobility degradation down to 2-3 nm thicknesses (https://ieeexplore.ieee.org/document/10873367). Thus, if monolayer channels are not possible for the authors to fabricate and test, it is important to achieve as close as possible to current Si nanosheet technology thicknesses (ideally below!). Please put some discussion for context -- especially where claiming to meet IRDS targets.\n2) Because HfSe2 is a 2D semiconductor that has been less explored all together, it is important that the authors provide adequate control samples using standard top-down contacts. They provide some \"Au/HfSe2\" data in Supplementary Fig. 18 and Fig. 4a-f, however the inset schematic displays Ti/Au as the source/drain contacts. This is an important point, because Ti or Cr interfacial layers (typically used for adhesion purposes) often lead to high contact resistances across a variety of 2D materials (owing to their high reactivity with O and intermixing, https://pubs.acs.org/doi/10.1021/acs.nanolett.6b01309). If there is a Ti interfacial layer, the Reviewer highly recommends comparing against Au or Ni alone contact schemes, which are more standard for the 2D field for a proper comparison.\n3) All contact resistance extractions (both for Hf2C and top-down comparison contacts) should have proper TLM extractions. Although the authors show some TLM data in Figure 4, the extracted contact resistance is not reliable because of exceptionally long channel lengths (3-20 microns long!). Please provide a TLM extraction containing sub-micron long devices - ideally with multiple devices per channel length and thickness for reproducibility - and report those Rc values only. The extraction should be done at a fixed gate overdrive, thus some discussion about threshold voltage extraction is appropriate as well. Output characteristics of short channel devices are also required to strengthen the claim of good contact resistance (both for Hf2C and top-down controls).\n4) Please include some hysteresis discussion and plots -- even for the devices without the HfO2 conversion.\n5) DFT calculations would strengthen the claim of no in-gap states -- especially for scaled thickness dimension.\nMinor points:\n6) Please revise for typos and formatting inconsistencies (e.g., μ in SI figures).\n7) Having device statistics and a summary table would be good for the reader -- for future works that want to benchmark.", "reviewer_2": "In this manuscript, the authors present a strategy for forming atomically sharp, heteroepitaxial edge contacts to 2D semiconductors via lateral chemical conversion of HfSe2 to metallic Hf2C. The work represents a significant advance in the field of 2D electronics by directly addressing the fundamental challenge of Fermi-level pining. The combination of a novel materials synthesis approach, comprehensive structural/electronic characterization (STEM, STS), electrical measurements, and insightful molecular dynamics simulations is exceptionally strong and compelling. The demonstrated device performance, including a near-ideal subthreshold swing and high on-current, not only surpasses most reported 2D edge-contact systems but also meets critical industry roadmap targets. The methodology and integrated platform established here are likely to have broad implications for future 2D semiconductor technology. However, to fully establish the significance and applicability of this work, the authors need to address several key points regarding the generality, fundamental limits, and practical integration of their technology.\n1. The successful conversion is demonstrated on ~40 nm thick HfSe2 flakes. Is this method equally effective and non-destructive for much thinner, monolayer HfSe2, which is crucial for ultimate electrostatic control? For wafer-scale applications, how can the uniformity and control of the lateral conversion process be ensured?\n2. The elegance of this technique lies in its potential generality. Beyond HfSe2, is this “hydrochalcogenation + carbonization” strategy applicable to other TMDs like MoS2 or p-type WSe2? Does any preliminary experimental or computational evidence support its generality?\n3. The manuscript demonstrates excellent on-state current and contact properties. However, to provide a more complete assessment of the intrinsic channel material quality and the overall device performance, it is essential to quantify the field-effect mobility (μFE). Could the authors please extract and report this key parameter for both the Hf2C/HfSe2 edge-contact FETs and the co-integrated FETs?\n4. The contact resistance (RC ~475 Ω·μm) is superior to many 2D edge-contacts but higher than top-tier semimetal top-contacts. Do the authors consider this an inherent trade-off of the edge-contact architecture? What are the strategies for further reducing RC? Furthermore, the RC remains orders above the quantum limit. What are the key factors limiting the intrinsic transport? Are theoretical calculations available to reveal the interface’s transmission coefficient and guide further optimization?\n5. In the co-integrated FET, HfO2 is formed by oxidizing part of the HfSe2 channel. Does this introduce a series resistance trade-off? How was this managed during device optimization?\n6. Beyond 200 electrical sweeps, what is the interface’s stability under high-temperature operation, high-current stress, or long-term bias? Data from accelerated aging tests would be highly valuable.\n7. The manuscript rightly notes the incompatibility of semimetals like Bi and Sb with BEOL due to low melting point or high diffusivity. How does Hf₂C perform in these aspects? Is the Hf2C structure and interface stable upon exposure to typical BEOL thermal budgets? Would it react with interconnect metals or interlayer dielectrics?\n8. Finally, to enhance the clarity and professionalism of the manuscript, this reviewer recommends streamlining the reference list by citing the most representative studies. Furthermore, the reference format requires standardization to comply with the journal’s style guide.", "reviewer_3": "In this manuscript, the authors report a lateral chemical-conversion strategy to form embedded Hf₂C/HfSe₂ edge contacts, together with the integration of native HfO₂ gate dielectrics. The work addresses an important challenge in 2D electronics, namely the realization of low-resistance, barrier-free carrier injection without relying on conventional metal deposition. The overall concept is clearly formulated, the experimental implementation is systematic, and the device performance is well characterized.\nFrom a structural and materials perspective, the authors provide convincing evidence for the formation of atomically sharp in-plane heterointerfaces through comprehensive STEM, EDS, Raman, XPS, and simulation analyses. From an electronic standpoint, the STM/STS and KPFM measurements consistently support the claim of suppressed metal-induced gap states and near-zero injection barriers. From a device perspective, the reported contact resistance (~475 Ω·μm), Schottky barrier height (~5 meV), near-ideal subthreshold swing (~62 mV/dec), and high drive current in short-channel devices collectively indicate that the proposed contact and dielectric integration strategy functions as intended.\nAt the same time, several points would benefit from further clarification to strengthen the rigor and generality of the work:\n1. Scalability and process controllability.\nThe contact formation relies on a spatially selective chemical conversion using masks. While the authors have convincingly demonstrated the feasibility at the flake level, it remains unclear how precisely this process can be controlled over large areas or dense device arrays. A short discussion on lithography compatibility and overlay tolerance would strengthen the manuscript from a manufacturing perspective.\n2. Distinction from conventional edge contacts.\nSince many recent studies use etched sidewalls followed by metal deposition, the authors should more clearly distinguish “chemically converted embedded edge contacts” from “deposited edge contacts” in the benchmarking discussion to avoid ambiguity in literature comparison.\n3. Role of interface dipoles and charge transfer.\nThe manuscript presents KPFM-derived work function values and a band diagram suggesting nearly zero electron injection barrier. However, the quantitative role of interface dipoles is not fully discussed. It remains unclear whether the observed near-zero barrier is governed primarily by work-function alignment or whether interfacial charge redistribution and dipole formation play a non-negligible role. If possible, an estimate of the interface dipole density or potential step would be helpful.\n4. Short-channel transport limits.\nGiven the very high pulsed current densities, a brief discussion on the dominant current-limiting mechanisms (e.g., velocity saturation, self-heating) would further improve completeness.\n5. Device operation at logic-relevant voltages.\nSince the reported devices operate at voltages higher than those used in advanced CMOS logic nodes, a brief discussion on possible routes toward voltage scaling (e.g., thinner dielectrics, higher-κ stacks, or reduced channel length) would further enhance the technological relevance of the work.\n6. Lin 237-242: Fig 4d presents the temperature-dependent transfer characteristics of Hf₂C/HfSe₂ devices with a long channel length (Lch=3 μm). For such long-channel devices, the Ion is primarily limited by channel resistance; thus, lowering the temperature reduces phonon scattering and enhances Ion. However, when the channel is scaled down to a few hundred nanometers, the current is expected to be dominated by contact-limited current. To clarify this scaling effect, temperature-dependent transfer and output characteristics of shorter-channel devices should be provided.\n7. Figure 5 presents the electrical characteristics of Hf2C/HfSe2 devices with a short channel length (Lch = 200 nm). Based on the observed performance, can the channel length be further scaled to sub-50 nm while maintaining functional device behavior? If available, scaling trends or simulations supporting such scalability would be valuable.\n8. The HfSe2/HfO2 heterostructure is fabricated through layer-by-layer plasma oxidation. If the terminal HfSe2 layer undergoes incomplete oxidation, could this partial oxidation state introduce oxygen vacancies at the HfSe2/HfO2 interface? Please comment on how oxidation completeness is ensured and whether interfacial oxygen vacancies are detected or controlled.\n9. Can the thickness of HfSe2 be further scaled to sub-5nm while maintaining acceptable mobility and gate control? If relevant data or estimates exist, please include them."}, "author_response": "Response to Reviewer #1\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in red.\nComments:\nBhin et al examine edge contacts for semiconducting 2D HfSe , via selectively converting\n2\nsemiconductor region to a metallic Hf C. They conduct STEM imaging, STM mapping, and\n2\nemploy molecular dynamics simulations to understand the Hf C and HfSe interfaces. Lastly,\n2 2\nthey demonstrate high-performance 2D transistors using these edge contacts and achieve >900\nμA/μm on-state current. The work is reasonably comprehensive, however there are major\npoints that should be addressed in order to meet the high standards of Nature Communications:\n1. The work is quite timely and takes some inspiration from the bismuth oxyselenide work\n(https://www.nature.com/articles/s41563-025-02117-w) -- obtaining clean high-κ and contact\ninterfaces via converting the existing 2D semiconductor. However, the original appeal of 2D\ntransistors is retaining device performance in monolayer semiconducting channels. Because\nthese HfSe samples are exfoliated, these are certainly thicker than monolayer and may even\n2\nhave nonuniform thicknesses through the manuscript, which raises several questions:\n1a - Can the authors clarify the approximate HfSe thickness for all devices throughout the\n2\nmanuscript? This should be inside all of the figure captions and appropriately described\nthroughout the main text + SI discussions. Otherwise, the authors are accidentally comparing\nmonolayer TMD studies to their very thick HfSe work, which could be misleading.\n2\n In response to the reviewer’s comment, we have indicated the HfSe 2 thickness for all\ndevices that were previously unspecified throughout the revised Manuscript and the\nSupplementary Information, including the relevant Figure captions. The corresponding\ninformation is summarized below.\n[Revised Manuscript] page: 5, 8, 10, Figure caption: Figure 4, 5\n[Revised Supplementary Information] Figure caption: Supplementary Figures 17-27, 32-\n37\n1b - Achieving high current densities is an easier task for thick 2D semiconducting channels,\neven with standard electron-beam evaporated contacts. Is it possible for the authors to\ndemonstrate these contacts on a monolayer HfSe semiconductor channel? They have two\n2\noptional approaches: (1) it appears that the authors can convert HfSe to high-quality HfO . In\n2 2\nother words, it looks straight-forward for them to oxidize their already existing devices down\nto monolayer (or few layer) thick channels and have thicker Hf C contacts. (2) Reconstruct\n2\ntheir edge-contact devices with a fully monolayer HfSe to start (e.g., have monolayer contacts\n2\ntoo).\n Following the reviewer’s comment, we newly fabricated co-integrated HfSe 2 FETs using\nthe proposed integration strategy with an atomically thin bilayer HfSe channel (revised\n2 2\nlateral edge-contact regions were first defined via selective lateral conversion. The same\n≈\nplasma oxidation step described in the Methods section was then applied locally to the\nchannel region for 5 min, yielding an HfO ( 10 nm)/bilayer-HfSe heterostructure. In\n2 2\nthis configuration, an atomically flat vdW HfO /HfSe interface and an atomically sharp\n≈2 2\nheteroepitaxial Hf C/HfSe interface were co-integrated within a single device, enabling\n2 2\neffective electrostatic control and efficient carrier injection. While monolayer channels\nrepresent the ultimate thickness-scaling limit, recent 2D CMOS roadmap discussions\nsuggest that bilayer/trilayer channels offer a practical compromise, providing lower\ncontact resistance and reduced sensitivity to extrinsic scattering and\ninterface/environmental perturbations [R1–4]. In this context, we respectfully note that\nbilayer/trilayer 2D channels are also being actively considered for scalable integration, as\nthey offer a balanced combination of electrostatic control, transport robustness, and\nprocess tolerance.\nThe corresponding results have been included in the revised Supplementary Information and\nare briefly mentioned in the revised Manuscript as follows:\n…...advanced contact technologies reported to date (Fig. 5f)1,16,17,20,41-48. “Co-integrated HfSe\nwhile preserving carrier-injection efficiency, offering a scaling demonstration that is\ntechnologically relevant to the channel-thickness regime of state-of-the-art Si nanosheet nodes\n(Supplementary Fig. 34).” To further assess the intrinsic drive capability beyond…...\n(revised Manuscript, page 11)\nSupplementary Figure 34. Characteristics of co-integrated HfSe FET with an atomically\n2\nthin channel. a, Upper panel: Schematic of the co-integrated HfSe FET incorporating a\n2\nbilayer HfSe channel. Lower panel: Enlarged cross-sectional STEM image of the HfO /HfSe\n2 2 2\nheterostructure, showing a well-preserved, atomically flat vdW interface. b, Transfer curves of\nthe co-integrated bilayer HfSe FET measured at a gate-voltage sweep rate of 0.01 V/s. The\n2\ndrain current was normalized by a channel width of 2.5 μm.\n“To evaluate the performance of co-integrated HfSe FET at an atomically thin channel\n2\nthickness, we fabricated co-integrated bilayer HfSe FET. Starting from an initial ≈25-nm-thick\n2 2\nsame plasma oxidation step described in the Methods was then applied locally to the channel\nregion for 5 min, yielding a HfO (≈10 nm)/bilayer-HfSe heterostructure. As shown in\n2 2\nSupplementary Fig. 34a, cross-sectional STEM reveals an atomically flat HfO /HfSe interface,\n2 2\nconfirming the well-preserved vdW interface. Consistent with this structural integrity, the\nfabricated FET exhibits an SS of 64 mV/dec, indicative of effective gate controllability\n4order\n(Supplementary Fig. 34b).”\n(revised Supplementary Information, page 44)\nReferences\n[R1] Jiang, J., Zheng, X., Liu, Y. et al. Advancing 2D CMOS electronics with high-\nperformance p-type transistors. Nat. Commun.16, 10233 (2025).\n[R2] Lembke, D., Allain, A. & Kis, A. Thickness-dependent mobility in two-dimensional MoS\n2\ntransistors. Nanoscale7, 6255–6260 (2015).\n[R3] Kwon, J. et al. Thickness-dependent Schottky barrier height of MoS field-effect\n2\ntransistors. Nanoscale9, 6151–6157 (2017).\n[R4] Pal, A. et al. Three-dimensional transistors with two-dimensional semiconductors for\nfuture CMOS scaling. Nat. Electron.7, 1147–1157 (2024).\n1c - It should be clear inside the benchmarking plot which devices are monolayers or few-\nlayers (Fig. 5f). Perhaps a plot with current density as a function of semiconductor channel\nthickness would be fruitful for the readers to see and contextualize this work's impact also.\n Following the reviewer’s comment, the benchmarking plot has been revised and is\nincluded in the revised Manuscript as follows:\nFigure 5. Electrical characteristics of Hf C edge-contact and vdW interface HfO co-\n2 2\nintegrated HfSe FET. f, Benchmark of I versus L for co-integrated HfSe FETs, compared\n2 on g 2\nwith recently reported planar FET with advanced contact technologies, FinFET, and GAAFET\nbased on 2D semiconductors (1L: monolayer channel, 2L: bilayer channel, FL: few-layer\nchannel)22,23,27,50-57.\n(revised Manuscript, page 27, 28)\nA comparison of current density as a function of 2D-semiconductor channel thickness for\nreported edge-contacted 2D devices is also provided, based on the benchmarking plot in the\nrevised Figure 4h. This comparison has been included in the revised Supplementary\nInformation and is briefly mentioned in the revised Manuscript as follows:\n…...the Hf C/HfSe interface (Fig. 4h and Supplementary Table 1). “A current-density plot as\n2 2\na function of 2D-channel thickness for reported edge-contacted devices is also provided in\nSupplementary Fig. 24.” To further demonstrate the intrinsic advantage…...\n(revised Manuscript, page 10)\nSupplementary Figure 24.Current density as a function of channel thickness for reported\n2D edge-contact systems. Circular symbols denote chemically converted, embedded edge\ncontacts, and triangular symbols denote deposited edge contacts. Channel thickness is\ncategorized as 1L (monolayer), 2L (bilayer), and FL (few-layer).\n(revised Supplementary Information, page 31)\n1d – HfSe has been less studied than MoS and WSe -- from a theoretical perspective, the\n2 2 2\nband gap is much smaller (1.1 eV bulk rather than 2.1 eV in monolayer MoS ). Is the mobility\n2\nalso smaller? Please cite relevant 2D semiconductor computational work\n(https://www.nature.com/articles/s41524-024-01417-0). Having this comparison for their\ndevices would be excellent, and again, ideally experimentally measured values for monolayer\nor few-layer HfSe .\n2\n As per the reviewer’s comments, we evaluated carrier mobility by extracting the field-\neffect mobility ( ) for both the bulk and bilayer HfSe devices, as well as the Hall\n2\nmobility ( ) (revised Supplementary Figures 35 and 36). The values were\n𝜇FE\nextracted from the transfer characteristics of the co-integrated HfSe FETs (original Figure\n𝜇Hall 2 𝜇𝐹𝐸\n5c for the 15-nm-thick channel and revised Supplementary Figure 34 for the bilayer\nchannel) using the standard transconductance-based method. The estimated for bulk\nHfSe channel (≈35 cm2/V·s) is comparable values recently reported monolayer for MoS\n2 𝜇𝐹𝐸 2\n[R1,2]. Regarding the reviewer’s theoretical point, bulk(-like) HfSe has a smaller band\n2\ngap (1.1eV) than monolayer MoS (2.1 eV). As reported in the reviewer-recommended\n2\nhigh-throughput first-principles transport study [npj Comput. Mater. 10, 229 (2024)], a\nsmaller band gap does not intrinsically imply lower mobility: the correlation between\neffective mass and band gap across a broad set of 2D semiconductors is reported to be\nrelatively weak, and HfSe is included among the down-selected candidate materials under\n2\ntheir screening criteria. These results support that mobility is governed primarily by\neffective mass and dominant scattering mechanisms, rather than by band gap alone.\nConsistent with this framework, the extracted values in bilayer and bulk (15 nm) co-\nintegrated HfSe FETs are similar ( ≈ 33 and 35 cm2/V·s, respectively), indicating that\n2 𝜇𝐹𝐸\nin-plane transport is largely preserved upon thickness scaling in our devices. Moreover,\n𝜇𝐹𝐸\nthe closely agrees with the 2-probe , suggesting that the gate stack and contacts\nare effectively integrated and that carrier transport is not severely limited by extrinsic\n𝜇𝐻𝑎𝑙𝑙 𝜇𝐹𝐸\ncontact or interface artifacts.\nDetailed characterization and results have been added to the revised Supplementary\nInformation and are briefly discussed in the revised Manuscript, with citations to the reviewer’s\nsuggested computational work.\n…...HfO dielectric layer (Supplementary Figs. 26a and 27). “Comparable field-effect mobility\n2\nto that reported for MoS upon channel-thickness scaling39,40 was also observed\n2\n(Supplementary Figs. 35-37).” Detailed electrical and interfacial characterization…...\n(revised Manuscript, page 11)\nReferences\n[39] Ha, V.-A. & Giustino, F. High-throughput screening of 2D materials identifies p-type\nmonolayer WS as potential ultra-high mobility semiconductor. npj Comput. Mater. 10, 229\n2\n(2024).\n[40] Sebastian, A. et al. Benchmarking monolayer MoS and WS field-effect transistors. Nat.\n2 2\nCommun.12, 693 (2021).\nSupplementary Figure 35. Field-effect mobility of co-integrated HfSe FETs varying with\n2\nchannel thickness. a,b, Transfer characteristic and extracted of a co-integrated HfSe\n2\n𝜇𝐹𝐸\nchannel width of 2.5 μm. Gae-voltage sweep rate = 0.01 V/s. c,d, Transfer characteristic and\nextracted of a co-integrated HfSe FET fabricated with a bilayer HfSe channel. The drain\n2 2\ncurrent was normalized by a channel width of 2.5 μm. Gae-voltage sweep rate = 0.01 V/s.\n𝜇𝐹𝐸\n“The field-effect mobility ( ) of the co-integrated HfSe FETs fabricated with a ≈15-nm-\n2\nthick HfSe channel and a bilayer HfSe channel was extracted from the linear-regime of the\n2 𝜇𝐹𝐸 2\ntransfer characteristics (Supplementary Fig. 35a,c) using the following relation: =\n( /C V )(L/W), where W and L are the channel width and length, respectively, C is the\nox DS o𝜇x 𝐹𝐸\noxide capacitance, is the transconductance, V is the drain voltage. The transconductance,\n𝑔𝑚 DS\nwas extracted from the linear region, where |V - V | > |V |. Based on this analysis, the\n𝑔𝑚 GS th DS\nvalues of the two devices were estimated to be ≈35 and ≈33 cm2/V·s, respectively\n𝑔𝑚\n(Supplementary Fig. 35b,d). The preservation of comparable values down to the bilayer\n𝜇𝐹𝐸\n𝜇𝐹𝐸\nthickness indicates that the in-plane carrier transport properties of HfSe are largely maintained\n2\nupon aggressive thickness scaling. This trend is consistent with a key advantage of 2D\nsemiconductors with dangling-bond-free surfaces, in contrast to conventional Si nanosheet\nchannels where mobility degradation is commonly observed as the channel thickness is\nreduced73. Importantly, the result further confirms that both the vdW interface and the\nunreacted top surface of the HfSe channel remain well preserved during the plasma oxidation\n2\nprocess, even in the atomically thin channel regime.”\n(revised Supplementary Information, page 45)\nSupplementary References\n[73] Agrawal, A. et al. Silicon RibbonFET CMOS at 6 nm gate length. IEEE Int. Electron\nDevices Meet. (IEDM), 1–4 (2024).\nSupplementary Figure 36. Hall mobility analysis of HfSe .a, Left: Schematic of the device\n2\ngeometry used for Hall measurements. Right: Enlarged SEM image showing the 200-nm\nelectrode spacing, together with the magnetic-field configuration used in the measurement.\nHfSe thickness = 15 nm. b, Comparison of and two-probe as a function of gate\n2\nvoltage at V = 0.1 V. The two-probe were extracted from the transfer curve in Fig. 5c.\nDS\n𝜇𝐻𝑎𝑙𝑙 𝜇𝐹𝐸\n“The bulk mobility of was evaluated usi𝜇n𝐹g𝐸 Hall measurements. A constant current was applied\nbetween the source and drain electrodes, while a perpendicular magnetic field of 0.525 T was\napplied normally to the channel plane (Supplementary Fig. 36a). The transverse Hall resistance\n( ) was measured to obtain the average Hall resistance ( ), and the carrier density (\nw\n𝑅\na𝑋s𝑌 simultaneously obtained using equation\n𝑅\n,𝑎 w𝑣𝑔here is the electron charg\n𝑛\ne\n)\n.\n𝑛 = 1/(𝑒𝑅𝑎𝑣𝑔) 𝑒\nBy taking and the measured conductivity ( , the as a function of gate voltage were\nestimated using equation Notably, is comparable to the\n𝑛 𝜎) 𝜇𝐻𝑎𝑙𝑙\ncorresponding two-probe over the same carrier concentration (Supplementary Fig. 36b).\n𝜇𝐻𝑎𝑙𝑙 = 𝜎/(𝑛𝑒). 𝜇Hall\nThis consistency indicates that the measured device performance is governed by intrinsic\n𝜇FE\nchannel transport rather than contact resistance or interfacial scattering, thereby confirming the\nhigh quality of the vdW interface as well as the integrity of the heteroepitaxial Hf C/HfSe\n2 2\nlateral edge contacts.”\n(revised Supplementary Information, page 47)\nReferences\n[R1] Sebastian, A. et al. Benchmarking monolayer MoS and WS field-effect transistors. Nat.\n2 2\nCommun.12, 693 (2021).\n[R2] Kayal, A. et al. Mobility enhancement in CVD-grown monolayer MoS via patterned\n2\nsubstrate-induced non-uniform straining. Nano Lett. 23, 6629–6636 (2023).\n1e – Si nanosheets have mitigated mobility degradation down to 2 ~ 3 nm thicknesses\n(https://ieeexplore.ieee.org/document/10873367). Thus, if monolayer channels are not possible\nfor the authors to fabricate and test, it is important to achieve as close as possible to current Si\nnanosheet technology thickness (ideally below!). Please put some discussion for context –\nespecially where claiming to meet IRDS targets.\n Together with our responses to comments #1b and #1d, these results have been included\nin the revised Supplementary Information and are discussed in the revised Manuscript in\nthe context of meeting the IRDS targets, as follows:\n…...advanced contact technologies reported to date (Fig. 5f)1,16,17,20,41-48. “Co-integrated\nHfSe FETs with an atomically thin bilayer channel also achieved improved electrostatic\n2\ncontrol while preserving carrier-injection efficiency, offering a thickness-scaling\ndemonstration that is technologically relevant to the channel-thickness regime of state-of-\nthe-art Si nanosheet nodes (Supplementary Fig. 34).” To further assess the intrinsic drive\ncapability beyond…...\n(revised Manuscript, page 11)\n2. Because HfSe is a 2D semiconductor that has been less explored all together, it is important\n2\nthat the authors provide adequate control samples using standard top-down contacts. They\nprovide some \"Au/HfSe \" data in Supplementary Fig. 18 and Fig. 4a-f, however the inset\n2\nschematic displays Ti/Au as the source/drain contacts. This is an important point, because Ti\nor Cr interfacial layers (typically used for adhesion purposes) often lead to high contact\nresistances across a variety of 2D materials (owing to their high reactivity with O and\nintermixing, https://pubs.acs.org/doi/10.1021/acs.nanolett.6b01309). If there is a Ti interfacial\nlayer, the reviewer highly recommends comparing against Au or Ni alone contact schemes,\nwhich are more standard for the 2D field for a proper comparison.\n We apologize for the inconsistent labeling in some schematics/text: the deposited top-\ncontact control devices in this study used Ti/Au electrodes, and all instances previously\ndescribed as “Au/HfSe ” have been corrected to “Ti/Au–HfSe ” in the revised Manuscript\n2 2\nand Supplementary Information. In addition, as recommended, we newly fabricated Au-\nonly-contacted HfSe FETs (without a Ti layer) under identical device geometry and\n2\nprocessing conditions and directly compared their injection characteristics with those of\nTi/Au-contacted HfSe FETs. As shown in the revised Supplementary Figure 17, the Au-\n2\nonly and Ti/Au-contacted devices exhibited comparable transfer characteristics and\nsimilar output nonlinearity, with no observable improvement in carrier injection upon\nremoving Ti, within the experimental and device-to-device variation.\nThese results have been included in the revised Supplementary Information, and the\ncorresponding description has been briefly added to the revised Manuscript as follows:\n…...Ti/Au-contacted HfSe FETs “(see Supplementary Fig. 17 for the Au-only-contacted\n2\ndevice characteristics).” The Hf C/HfSe FET exhibits markedly…...\n2 2\n(revised Manuscript, page 8)\nSupplementary Figure 17. Comparison of electrical characteristics between Au-HfSe\n2 2\ndevice (L = 3 μm, channel width = 2.5 μm, V = 1 V, back-gate voltage sweep: –60 to +60\nch DS\nV, Back-gate dielectric = SiO 285 nm, HfSe thickness = 40 nm). Inset: schematic illustration\n2 2\nof the device structure used for the measurement. b, Output characteristics of the Ti/Au-HfSe\n2\ndevice measured at 300 K with the back-gate voltage varied from 0 to 60 V. c, Transfer\ncharacteristics (linear scale) of the Au-HfSe device (L = 3 μm, channel width = 2.5 μm, V\n2 ch DS\n= 1 V, Back-gate voltage sweep: –60 to +60 V, Back-gate dielectric = SiO 285 nm, HfSe\n2 2\nthickness = 40 nm). Inset: schematic illustration of the device structure used for the\nmeasurement. d, Output characteristics of the Au-HfSe device measured at 300 K with the\n2\nback-gate voltage varied from 0 to 60 V.\n“We fabricated Au-only-contacted HfSe FETs (without a Ti adhesion layer) under identical\n2\ndevice geometry and processing conditions and directly compared their injection\ncharacteristics with those of Ti/Au-contacted HfSe FETs. As shown in the revised\ntransfer characteristics and similar output nonlinearity.”\n(revised Supplementary Information, page 22)\n3. All contact resistance extractions (both for Hf C and top-down comparison contacts) should\n2\nhave proper TLM extractions. Although the authors show some TLM data in Figure 4, the\nextracted contact resistance is not reliable because of exceptionally long channel lengths (3-20\nmicrons long!). Please provide a TLM extraction containing sub-micron long devices - ideally\nwith multiple devices per channel length and thickness for reproducibility - and report those\nRc values only. The extraction should be done at a fixed gate overdrive, thus some discussion\nabout threshold voltage extraction is appropriate as well. Output characteristics of short channel\ndevices are also required to strengthen the claim of good contact resistance (both for Hf C and\n2\ntop-down controls).\n (TLM analysis under channel length and thickness variation of Hf 2 C/HfSe 2 FETs)\nFollowing the reviewer’s comment, we newly fabricated a dedicated set of sub-micron\nTLM structures spanning L = 100–500 nm, with the HfSe thickness varied from bilayer\nch 2\nup to 15 nm (15 TLM samples in total) (revised Supplementary Figure 22). The resulting\nsub-micron TLM dataset provides that the extracted R remains nearly similar values\nC\nacross various channel thicknesses and channel-length configurations. Notably, the weak\ndependence of R on channel thickness is aligned with edge-injection–dominated contacts,\nC\nwhere carrier injection occurs through the in-plane edge interface rather than through a\ntop-contacted area, reducing sensitivity to thickness-dependent under-contact transport\neffects [R1].\n (Analysis on deposited Ti/Au-HfSe 2 FETs) Following the reviewer’s suggestion, Ti/Au\ntop-contacted HfSe FETs were also investigated by measuring the R and output\ncharacteristics for devices with channel length ranging from 100 to 500 nm (revised\nSupplementary Figure 23). In contrast to the Hf C edge-contacted devices, the Ti/Au top-\n2\ncontacted HfSe FETs exhibit pronounced nonlinearity in the output characteristics,\n2\nconsistent with contact-limited injection and barrier-like behavior at the\nmetal/semiconductor interface. Furthermore, the extracted R increases as the channel\nC\nthickness decreases, in sharp contrast to the edge-contacted devices where R remains\nC\nlargely insensitive to channel thickness. This thickness dependence on Ti/Au top-contacted\ndevices can be attributed to increased current crowding and under-contact/access\nresistance that become more prominent in thinner channels.\nThese results have been included in the revised Supplementary Information and are briefly\ndiscussed in the revised Manuscript as follows:\n…...exhibited a reduced R of ≈475 Ω·μm (Fig. 4g and Supplementary Fig. 21). “Similar\nC\nresults were also obtained upon scaling the channel length and thickness (down to bilayer),\nfurther confirming stable ohmic contact behavior and the benefits of the proposed Hf C/HfSe\n2 2\nedge-contact geometry (Supplementary Figs. 22 and 23).” This performance surpasses that\nof…...\n(revised Manuscript, page 10)\nSupplementary Figure 22. Extraction of contact resistance using the transfer length\nmethod for Hf C/HfSe FETs as a function of channel thickness and channel length. a-f,\n2 2\nR as a function of channel length for each channel thickness, extracted at a fixed carrier\ntotal\ndensity of a n ≈ 6 x 1012 cm-2, together with the corresponding output characteristics (Back-\n2D\ngate dielectric = SiO 285 nm, channel width = 2.5 μm). The V was extracted from\n2 th\nsemilogarithmic transfer characteristics measured at 300 K using a constant-current method,\nwhere V was defined at a width-normalized drain current of 0.1 μA/μm59. This criterion was\nth\nchosen to lie in the near-threshold regime and to avoid the strong on-state where the drain\ncurrent can be affected by contact and series resistances. All analyses were then performed\nunder a fixed gate-overdrive condition, defined as V = V - V corresponding to n ≈ 6 x\nov GS th 2D\n1012 cm-2. The proposed Hf C/HfSe interface exhibits consistent R and linear output\n2 2 C\ncharacteristics across a wide range of channel thicknesses at scaled channel lengths, indicating\nstable ohmic contact formation. Notably, the weak dependence of R on channel thickness is\nC\nconsistent with edge-injection–dominated contacts, where carriers are injected through the in-\nplane edge interface rather than through the top surface, thereby reducing the sensitivity to\nunder-contact transport limitations typically observed in top-contact geometries60.\n(revised Supplementary Information, page 28)\nSupplementary References\n[59] Lan, H.-Y. et al. Reliability of high-performance monolayer MoS transistors on scaled\n2\nhigh-κ HfO . npj 2D Materials and Applications 9, 5 (2025).\n2\n[60] Chu, T. & Chen, Z. Understanding the electrical impact of edge contacts in few-layer\ngraphene. ACS Nano8, 3584–3589 (2014).\nSupplementary Figure 23. Extraction of contact resistance using the transfer length\nmethod for Ti/Au-HfSe FETs as a function of channel thickness and channel length.a-d,\ntotal\noutput characteristics (Back-gate dielectric = SiO 285 nm, channel width = 2.5 μm). The\n2\ninvestigated channel length range, consistent with contact-limited injection and barrier-like\nbehavior at the metal/semiconductor interface. In addition, the extracted R increases as the\nC\nchannel thickness decreases, which can be attributed to enhanced current crowding and\nincreased under-contact/access resistance that become more prominent in thinner channels for\ntop-contact geometries61.\n(revised Supplementary Information, page 30)\nSupplementary References\n[61] Kwon, J. et al. Thickness-dependent Schottky barrier height of MoS field-effect\n2\ntransistors. Nanoscale9, 6151–6157 (2017).\nReferences\n[R1] Chu, T. & Chen, Z. Understanding the electrical impact of edge contacts in few-layer\ngraphene. ACS Nano8, 3584–3589 (2014).\n4. Please include some hysteresis discussion and plots -- even for the devices without the HfO\n2\nconversion.\n (Hysteresis of co-integrated HfSe 2 FET) Gate hysteresis is a critical device parameter\nclosely related to interfacial quality and defect states within the dielectric layer [R1,2]. In\nthe original Supplementary Figure 23a, the co-integrated HfSe FET exhibits small\n2\nhysteresis (≈2.8 mV) under reversible +/- sweep conditions at a sweep rate of 0.01 V/s,\nindicating a low density of interface states and border traps in the HfO layer of the\n2\nproposed HfO /HfSe heterostructure. This interpretation is further supported by multi-\n2 2\nfrequency capacitance–voltage measurements shown in the original Supplementary Figure\n22a, which exhibit negligible frequency dispersion in both the depletion and accumulation\nregimes, a behavior typically associated with suppressed interfacial and border traps\n[R3,4].\n (Hysteresis of devices without HfO 2 conversion) For direct comparison, the hysteresis\nbehavior of Hf C/HfSe FETs without HfO conversion, previously investigated using a\n2 2 2\n285 nm SiO back-gate dielectric, is presented in the revised Supplementary Figure 27.\n2 2 2 2\ndielectric exhibits extremely large hysteresis (≈60,000 mV) under the same gate sweep\nrate of 0.01 V/s, a behavior commonly observed in 2D semiconductor FETs employing\nSiO back-gate dielectrics. This stark contrast indicates that the suppressed hysteresis in\n2\nthe co-integrated HfSe FET originates from the well-preserved vdW interface of\n2 2 2\nsuppressed interface trap density (D ≈5 × 1010 cm-2 eV1) and low gate leakage current\nit\ndensity (original Supplementary Figure 21).\nThese results have been included in the revised Supplementary Information and are briefly\ndiscussed in the revised Manuscript as follows:\n…...a high on/off current ratio (≈108), and a low gate leakage current (≈10-6 A/cm2).\n“Furthermore, negligible gate hysteresis (≈2.8 mV), which is closely associated with dielectric\nand interfacial trap states38, confirms the effective suppression of charge trapping at the vdW\ninterface and within the HfO dielectric layer (Supplementary Figs. 26a and 27).” Comparable\n2\nfield-effect mobility to…...\n(revised Manuscript, page 10-11)\nReferences\n[38] Illarionov, Y. Y. et al. Energetic mapping of oxide traps in MoS field-effect transistors.\n2\n2D Mater.4, 025108 (2017).\nSupplementary Figure 27. Hysteresis characteristic of a Hf C/HfSe FET.\n2 2\nTransfer\ncharacteristics of an Hf C/HfSe FET with a 285-nm-thick SiO back-gate dielectric measured\n2 2 2\nunder forward and reverse gate-voltage sweeps. HfSe thickness = 40 nm, Channel width = 2.5\n2\nμm. In contrast to the co-integrated HfSe FET, the Hf C/HfSe FET employing the SiO back-\n2 2 2 2\ngate dielectric exhibits an extremely large hysteresis (≈60,000 mV) under the same gate sweep\nrate of 0.01 V/s, a behavior commonly observed in 2D semiconductor FETs using SiO back-\n2\ngate dielectrics. This stark contrast indicates that the suppressed hysteresis observed in the co-\nintegrated HfSe FET (Supplementary Fig. 26a) originates from the well-preserved vdW\n2 2 2\nwith the suppressed interfacial trap density (D ≈5 × 1010 cm-2 eV1) and the low gate-leakage\nit\ncurrent density shown in Supplementary Figs. 29 and 30.\n(revised Supplementary Information, page 34)\nReferences\n[R1] Knobloch, T. et al. Improving stability in two-dimensional transistors with amorphous\ngate oxides by Fermi-level tuning. Nat. Electron.5, 356–366 (2022).\n[R2] Illarionov, Y. Y. et al. Energetic mapping of oxide traps in MoS field-effect transistors.\n2\n2D Mater. 4, 025108 (2017).\n[R3] Zhao, P. et al. Interface states and border traps in two-dimensional semiconductor devices.\n2D Mater. 5, 031002 (2018).\n[R4] Mitta, S. B. et al. Trap-assisted charge dynamics in two-dimensional field-effect\ntransistors. 2D Mater. 8, 012002 (2020).\n5. DFT calculations would strengthen the claim of no in-gap states -- especially for scaled\nthickness dimension.\n Following the reviewer’s suggestion, we additionally analyzed the electronic structure of\nthe interface for larger cells (revised Supplementary Figure 13). Because the calculation\nsize was extremely large, we optimized the atomic structure using a machine-learned\npotential. In the optimized structure, the length of the entire interface structure and that of\nHf C layer was around 8 and 6 nm, respectively. Using this structure, we then performed\ngap, we added on-site Coulomb potential to Hf d orbitals by 6 eV. After that, we obtained\nthe LDOS using the atom-projected density of states by applying Gaussian smearing. Our\ncalculation shows no detectable localized trap states in HfSe ,consistent with the measured\n2\nelectronic structure.\nThese results have been incorporated into the revised Supplementary Information and are\nbriefly mentioned in the revised Manuscript as follows:\n…...indicating the formation of a well-defined and electronically clean structure. “These\nresults are further corroborated by first-principles DFT calculations of the electronic band\nstructure (Supplementary Fig. 13).” These findings provide direct experimental\nevidence…...\n(revised Manuscript, page 8)\nSupplementary Figure 13. DFT-calculated LDOS of the Hf C/HfSe interface. a, Atomic\n2 2\nstructure of the Hf C/HfSe interface, optimized by using a machine-learned potential. b, Local\n2 2\ndensity of states of the Hf C/HfSe interface model. The Fermi energy is set to 0 eV, and the\n2 2\nhorizontal dashed lines denote the band edges of HfSe in the interface model.\n2\n“We additionally analyzed the electronic structure of the interface for larger cells\n(Supplementary Fig. 13a). Because the calculation size was extremely large, we optimized the\natomic structure using a machine-learned potential. In the optimized structure, the length of the\nentire interface structure and that of Hf C layer was around 8 and 6 nm, respectively. Using\n2\nthis structure, we then performed DFT calculations to analyze the electronic structure. To\nreproduce the experimental band gap, we added on-site Coulomb potential to Hf d orbitals by\n6 eV. After that, we obtained the LDOS using the atom-projected density of states by applying\nGaussian smearing (Supplementary Fig. 13b). Our calculation shows no detectable localized\ntrap states in HfSe ,consistent with the measured electronic structure.”\n2\n(revised Supplementary Information, page 17)\nMinor points:\n6. Please revise for typos and formatting inconsistencies (e.g., μ in SI figures).\n All typographical errors and formatting inconsistencies have been corrected throughout\nthe revised Manuscript and the Supplementary Information.\n7. Having device statistics and a summary table would be good for the reader -- for future\nworks that want to benchmark.\n Following the reviewer’s suggestion, the device statistics and a summary table have been\nincluded in the revised Supplementary Information and are briefly mentioned in the\nrevised Manuscript as follows:\n……all showing consistent I values (Fig. 5d)”. “Device statistics and a summary of key\non\nperformance metrics are also provided in Supplementary Fig. 31 and Supplementary Table\n2.” For stability evaluation…...\n(revised Manuscript, page 11)\nSupplementary Table 2. The device statistics summary for the co-integrated HfSe FETs.\n1 920.1 62.4 2.8 0.49\n2 914.6 62.6 3.3 0.50\n3 919.8 63.1 3.3 0.50\n4 918.9 63.8 3.3 0.49\n5 893.2 62.7 3.3 0.50\n6 909.4 63.9 3.3 0.51\n7 905.6 63.2 3.4 0.50\n8 912.8 63.7 3.4 0.50\n9 883.5 63.9 3.3 0.49\n10 917.6 63.3 3.2 0.50\n11 902.3 64.4 3.3 0.51\n12 916.9 63.1 3.3 0.49\n13 889.1 62.6 3.4 0.50\n14 910.7 63.8 3.4 0.50\n15 896.4 63.7 3.3 0.51\n16 918.8 64.5 3.4 0.49\n17 879.6 65 3.3 0.49\n18 907.5 63.2 3.3 0.50\n19 8992 64.6 3.4 0.50\n20 919.7 64.4 3.4 0.51\n(revised Supplementary Information, page 4)\nSupplementary Figure 31. Statistical performance distribution of co-integrated HfSe\nI , SS, hysteresis, and V .\non th\n“To quantitatively evaluate device-to-device variability, cumulative probability distributions of\nthe I , SS, hysteresis, and V , extracted from the transfer curves of 20 co-integrated HfSe\non th 2\nFETs shown in Fig. 5d, are presented in Supplementary Fig. 31a-d. Device variation was\nquantified using the coefficient of variation (CV), which measures the dispersion of a\nprobability distributions and is defined as CV = ( / ) × 100 (%), where and represent\nthe standard deviation and mean value, respectively. All key electrical parameters exhibit\n𝜎 𝜇 𝜎 𝜇\nnarrow variations with suppressed CV values, indicating highly reproducible integration of\nHf C/HfSe edge contact and vdW interface-integrated HfO /HfSe gate stack.”\n2 2 2 2\n(revised Supplementary Information, page 40)\nResponse to Reviewer #2\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in red.\nComments:\nIn this manuscript, the authors present a strategy for forming atomically sharp, heteroepitaxial\nedge contacts to 2D semiconductors via lateral chemical conversion of HfSe to metallic Hf C.\n2 2\nThe work represents a significant advance in the field of 2D electronics by directly addressing\nthe fundamental challenge of Fermi-level pining. The combination of a novel materials\nsynthesis approach, comprehensive structural/electronic characterization (STEM, STS),\nelectrical measurements, and insightful molecular dynamics simulations is exceptionally strong\nand compelling. The demonstrated device performance, including a near-ideal subthreshold\nswing and high on-current, not only surpasses most reported 2D edge-contact systems but also\nmeets critical industry roadmap targets. The methodology and integrated platform established\nhere are likely to have broad implications for future 2D semiconductor technology. However,\nto fully establish the significance and applicability of this work, the authors need to address\nseveral key points regarding the generality, fundamental limits, and practical integration of\ntheir technology.\n1. The successful conversion is demonstrated on ~40 nm thick HfSe flakes. Is this method\n2\nequally effective and non-destructive for much thinner, monolayer HfSe , which is crucial for\n2\nultimate electrostatic control? For wafer-scale applications, how can the uniformity and control\nof the lateral conversion process be ensured?\n (Integration for thinner channel thickness) To address the reviewer’s concern regarding\nthe applicability of the proposed approach to thinner channels, we conducted additional\nexperiments and evaluated the electrical characteristics of co-integrated HfSe FETs\n2\nfabricated with an atomically thin (bilayer) HfSe channel (revised Supplementary Figure\n2\n34). The demonstrated co-integrated bilayer HfSe FETs preserved the integrity of both\n2\nthe atomically flat vdW interface and the heteroepitaxial edge-contact interface, while\nexhibiting effective gate controllability. These results indicate that the proposed\nintegration strategy is compatible with atomically thin channels.\nThese results are incorporated in the revised Supplementary Information and are briefly\nmentioned in the revised Manuscript as follows:\n…...advanced contact technologies reported to date (Fig. 5f)1,16,17,20,41-48. “Co-integrated HfSe\nwhile preserving carrier-injection efficiency, offering a scaling demonstration that is\ntechnologically relevant to the channel-thickness regime of state-of-the-art Si nanosheet nodes\n(Supplementary Fig. 34).” To further assess the intrinsic drive capability beyond…...\n(revised Manuscript, page 11)\nSupplementary Figure 34. Characteristics of co-integrated HfSe FET with an atomically\n2\nthin channel. a, Upper panel: Schematic of the co-integrated HfSe FET incorporating a\n2\nbilayer HfSe channel. Lower panel: Enlarged cross-sectional STEM image of the HfO /HfSe\n2 2 2\nheterostructure, showing a well-preserved, atomically flat vdW interface. b, Transfer curves of\nthe co-integrated bilayer HfSe FET measured at a gate-voltage sweep rate of 0.01 V/s. The\n2\ndrain current was normalized by a channel width of 2.5 μm.\n“To evaluate the performance of co-integrated HfSe FET at an atomically thin channel\n2\nthickness, we fabricated co-integrated bilayer HfSe FET. Starting from an initial ≈25-nm-thick\n2 2\nsame plasma oxidation step described in the Methods was then applied locally to the channel\nregion for 5 min, yielding a HfO (≈10 nm)/bilayer-HfSe heterostructure. As shown in\n2 2\nSupplementary Fig. 34a, cross-sectional STEM reveals an atomically flat HfO /HfSe interface,\n2 2\nconfirming the well-preserved vdW interface. Consistent with this structural integrity, the\nfabricated FET exhibits an SS of 64 mV/dec, indicative of effective gate controllability\n4order\n(Supplementary Fig. 34b).”\n(revised Supplementary Information, page 44)\n (Approaches for uniform and controllable wafer-scale integration) We acknowledge\nthe reviewer’s concern regarding the uniformity and controllability required for wafer-\nscale implementation of the lateral conversion strategy. Fundamentally, the formation of\nHf C proceeds via an edge-initiated lateral conversion mechanism, rather than surface-\n2\nwide nucleation. Consequently, the lateral propagation length is governed by deterministic\nreaction kinetics and globally controlled process parameters—including temperature, gas\ncomposition, and reaction time—rather than by wafer position or local material variations.\nAs a result, under identical process conditions, the lateral conversion depth remains\nuniform across the wafer. We believe that this edge-confined, kinetics-controlled process\nenables reproducible Hf C/HfSe junction formation and provides a physically grounded\n2 2\npathway toward uniform and controllable wafer-scale integration. Building on recent\nreports of wafer-scale grown HfSe films [R1,2], we plan to investigate uniform and\n2\ncontrollable lateral conversion processes at the wafer scale in future studies.\nTo indicate the potential extension toward uniform large-area integration, the revised\nManuscript briefly includes the following description:\n……within the 2D semiconductor channel. “The scalability of the proposed methodology\ntoward uniform wafer-scale integration can be investigated by coupling it with established\nwafer-scale channel-formation routes, while maintaining compatibility with standard\nlithography and enabling a practical overlay-tolerance window through a globally\ncontrolled, self-aligned conversion step.”\n(revised Manuscript, page 6)\nReferences\n[R1] Li, S. et al. Wafer-scale 2D hafnium diselenide based memristor crossbar array for\nenergy-efficient neural network hardware. Adv. Mater. 34, e2103376 (2022).\n[R2] Chu, W. et al. Stable alkali halide vapor assisted chemical vapor deposition of 2D\nHfSe templates and controllable oxidation of its heterostructures. Front. Phys.19, 33212\n2\n(2024).\n2. The elegance of this technique lies in its potential generality. Beyond HfSe , is this\n2\n“hydrochalcogenation + carbonization” strategy applicable to other TMDs like MoS or p-type\n2\n The generality of the hydrochalcogenation + carbonization strategy stems from the\nbonding configuration and defect chemistry of TMDs. In layered TMDs, where a\ntransition-metal plane is sandwiched between two chalcogen planes, the formation of\nchalcogen vacancies/defects at exposed edges is a broadly shared feature under thermal or\nchemical activation. These chalcogen-deficient edge sites can therefore act as reactive\ninitiation points for carbon incorporation, enabling edge-initiated chalcogen-to-carbon\nreplacement and subsequent lateral carbide conversion to proceed in a similar manner\nacross diverse TMDs. Our previous findings are summarized as follows.\nFor instance, we previously examined this strategy to MoS , yielding an atomically\n2\ncoherent Mo C/MoS junction, and elucidated the edge-initiated lateral carbonization\n2 2\nmechanism via reaction-energy profiling and thermodynamic analysis (Figure R1a).\nSimilarly, we are also extending this strategy to p-type TMDs such as WSe and MoTe .\n2 2\nIn particular, we have recently obtained prototype results for a W C/WSe junction (Figure\nx 2\nR1b), supporting the feasibility of edge-initiated lateral conversion in p-type TMD systems.\nOn this basis, and given the structural and chemical similarities, we expect MoTe to\n2\nexhibit analogous behavior under comparable hydrochalcogenation + carbonization\nconditions.\n[REDACTED]\nFigure R1. Hydrochalcogenation + carbonization strategy applied to diverse TMDs. a,\nCross-sectional STEM image of the Mo C/MoS junction formed via edge-initiated lateral\n2 2\nconversion process [ACS Nano12, 338–346 2018, DOI: 10.1021/acsnano.7b06417]. b, Cross-\nsectional STEM image of a prototype W C/WSe junction.\nx 2\n3. The manuscript demonstrates excellent on-state current and contact properties. However, to\nprovide a more complete assessment of the intrinsic channel material quality and the overall\ndevice performance, it is essential to quantify the field-effect mobility (μ ). Could the authors\nFE\nplease extract and report this key parameter for both the Hf C/HfSe edge-contact FETs and\n2 2\nthe co-integrated FETs?\n Following the reviewer’s suggestion, the field-effect mobility ( ) for both the\nHf C/HfSe FET and the co-integrated HfSe FET was extracted.\n2 2 2 𝜇𝐹𝐸\nThese results are incorporated in the revised Supplementary Information, as follows:\nSupplementary Figure 37. Comparison of field-effect mobilitybetween the Hf C/HfSe\n2 2\nFET and the co-integrated HfSe FET. a,b, Extracted as a function of carrier\n2\nconcentration. The carrier concentration and were extracted from the transfer\n𝜇𝐹𝐸\ncharacteristics (at V = 0.1 V) for each device configuration. The device dimensions are\nDS\n𝜇𝐹𝐸\nidentical for both devices (L = 200 nm, channel width = 2.5 μm, and HfSe thickness = 15\nch 2\nnm). The inset shows the schematic used for the measurements.\n“For the Hf C/HfSe FET, transfer characteristics were measured using a back-gate\n2 2\nconfiguration with a 285-nm-thick SiO dielectric, whereas for the co-integrated HfSe FET, a\n2 2\ntop-gate configuration with a 10-nm-thick HfO dielectric was employed. The was\n2\nobtained from the linear regime of the transfer characteristics using the following relation:\n𝜇𝐹𝐸\n= ( /C V )(L/W), where W and L are the channel width and length, respectively, C is the\nox DS ox 𝜇𝐹𝐸\noxide capacitance, is the transconductance, V is the drain voltage. The transconductance,\n𝑔𝑚 DS\nwas extracted from the linear region, where |V - V | > |V |. Using this approach, the\n𝑔𝑚 GS th DS\n𝑔𝑚\nextracted of the Hf C/HfSe edge-contact FET was approximately 3 cm2/V·s at a carrier\n2 2\nconcentration of 6 × 1012 cm-2 (corresponding to V = 60 V), whereas the co-integrated HfSe\n𝜇𝐹𝐸 GS 2\nFET exhibited a of approximately 35 cm2/V·s at the same carrier concentration\n(corresponding to V = 1 V). Because both devices exhibit ohmic contacts and were compared\nG𝜇S𝐹𝐸\nat an identical carrier concentration, this pronounced difference in can be attributed\nprimarily to differences in channel and interfacial scattering rather than contact resistance or\n𝜇𝐹𝐸\ncarrier injection effects. In particular, the substantially higher mobility observed in the co-\nintegrated HfSe FET is consistent with reduced impurity- and trap-induced Coulomb\n2\nscattering at the vdW interface74, in contrast to the SiO -gated configuration, where interfacial\n2\ndisorder is more prominent.”\n(revised Supplementary Information, page 48)\nSupplementary References\n[74] Knobloch, T. et al. The performance limits of hexagonal boron nitride as an insulator for\nscaled CMOS devices based on two-dimensional materials. Nat. Electron. 4, 98–108 (2021).\n4. The contact resistance (R ~475 Ω·μm) is superior to many 2D edge-contacts but higher than\nC\ntop-tier semimetal top-contacts. Do the authors consider this an inherent trade-off of the edge-\ncontact architecture? What are the strategies for further reducing R ? Furthermore, the R\nC C\nremains orders above the quantum limit. What are the key factors limiting the intrinsic transport?\nAre theoretical calculations available to reveal the interface’s transmission coefficient and\nguide further optimization?\n (Edge-contact architecture) We agree that it is important to discuss whether the present\nR is fundamentally constrained by the edge-contact geometry, practical routes for further\nC\nreduction, and the origin of the remaining gap to the quantum limit. At the present stage,\nwe interpret the measured R as being governed primarily by non-ideal but potentially\nC\noptimizable factors, most notably non-unity transmission (T < 1) in the injection region,\nrather than by an intrinsic geometric trade-off. In principle, an edge contact can approach\nvery low R when the local mode count in the semiconductor near the injection region is\nC\nsufficiently high and the interface transmission approaches unity [R1-4]. In our devices,\nthe extracted SBH is nearly barrierless and the output characteristics remain highly linear,\nindicating that thermionic injection over a Schottky barrier is unlikely to be the dominant\nlimitation; instead, the remaining R is more plausibly governed by the effective\nC\ntransmission and near-interface non-idealities.\n (Considerable origin of the remaining gap to the quantum limit) The quantum limit\ncorresponds to ballistic injection with unity transmission, and its value depends on the\navailable number of modes (carrier density) and the transmission coefficient. Importantly,\nR extracted from TLM represents an effective contact resistance obtained from a two-\nC\nterminal resistance decomposition. Within standard planar-contact models, the measured\nR can include not only the interfacial term but also current crowding/spreading–related\nC\ncontributions associated with non-uniform current transfer in the vicinity of the junction,\nsuch that the experimentally extracted R can exceed an idealized quantum-limit value\nC\neven when the interfacial barrier is small [R5]. To further identify the limiting factors that\ncould reduce the effective transmission, we performed additional first-principle DFT\ncalculations (Figure R2). It is known that intermixing can happen at the interface, leading\nto the formation of C defects in HfSe . To accurately reproduce the experimental band gap,\n2\nan on-site Coulomb potential (U) of 6 eV was applied to the Hf d orbitals, which yielded\na calculated band gap of approximately 1.07 eV for HfSe . Given that Se atoms are being\n2\nreplaced by C atoms at the interface, we adopted Se-poor conditions for the defect\ncalculations. Under these conditions, C atoms preferentially substitute for Se atoms. Our\ncalculations indicate that these substitutions act as acceptor defects, suggesting they are\nlikely to be negatively charged at the interface. Consequently, if the population of these\ncharged defects is high, the Fermi level may become pinned at the interface, thereby\nhampering efficient charge injections.\n (Approaches for further reduction of R C ) Based on established contact-physics\nframeworks [R1-4] and our findings above, we envision several routes to further reduce\nR : (i) increasing the local mode count near the injection region (e.g., via local electrostatic\nC\ndoping/contact gating or charge-transfer/dipole engineering), (ii) suppressing interfacial\ndisorder/defect formation and maintaining interface cleanliness to improve transmission\n(e.g., by process optimization and post-processing steps such as rapid thermal annealing\nwhere compatible), (iii) mitigating current crowding by increasing the effective injection\nperimeter (e.g., multi-edge/interdigitated layouts), and (iv) further improving the\nconductivity of the metallic region to reduce any series contribution in the contact stack.\nFurthermore, we acknowledge that calculating the transmission coefficient using the Non-\nEquilibrium Green's Function (NEGF) formalism would provide valuable insights.\nHowever, to accurately model the realistic interface structure, an extremely large supercell\nis required. This results in a computational cost that is prohibitively high for the current\nstudy. We hope you understand this constraint.\nFigure R2. Calculated formation energy of C defects in HfSe .\n[R1] Beenakker, C. W. J. & van Houten, H. Quantum transport in semiconductor nanostructures.\nSolid State Phys. 44, 1–228 (1991).\n[R2] Jena, D., Banerjee, K. & Xing, G. H. 2D crystal semiconductors: Intimate contacts. Nat.\nMater.13, 1076–1078 (2014).\n[R3] Shen, P.-C. et al. Ultralow contact resistance between semimetal and monolayer\nsemiconductors. Nature 593, 211–217 (2021).\n[R4] Li, W. et al. Approaching the quantum limit in two-dimensional semiconductor contacts.\nNature613, 274–279 (2023).\n[R5] Berger, H. H. Models for contacts to planar devices. Solid-State Electron. 15, 145–158\n(1972).\n5. In the co-integrated FET, HfO is formed by oxidizing part of the HfSe channel. Does this\n2 2\nintroduce a series resistance trade-off? How was this managed during device optimization?\n We acknowledge the reviewer’s concern that forming HfO 2 by local oxidation of the HfSe 2\nchannel could introduce an additional series/access resistance if unintended lateral\noxidation encroachment extends into the current injection/access path. Practically, to\nmitigate risk of lateral oxidation intrusion during co-integration, the oxidation step is\nrestricted to a lithographically defined oxidation window that is spatially separated from\nthe Hf C edge-contact/access region (Figure R3a), while the oxidation exclusion (keep-out)\n2\nmargin is kept minimal so as not to introduce an unnecessarily segment. Cross-sectional\nSTEM/EDS in the co-integrated device (original Figure 5b; reproduced in Figure R3b)\nverifies that oxide formation is confined to the intended gate-stack region without lateral\nintrusion toward the contact/access region, consistent with the co-integrated dielectric\nformation being unlikely to introduce a dominant series/access resistance penalty in the\noptimized devices.\nNevertheless, we acknowledge that a deliberately introduced underlap segment may\nappear as a finite access/extension resistance in the channel extension region. However, in\nadvanced logic integration, underlap/inner-spacer engineering is widely recognized as an\nintentional co-optimization knob to reduce gate–S/D parasitic capacitances\n(overlap/fringing components) and thereby improve circuit-level RC delay (and intrinsic\ngate-delay metrics) [R1]. For example, in GAA nanosheet technologies, inner spacers are\nexplicitly implemented between the gate and the S/D regions to suppress parasitic\ncapacitance coupling [R2]. Consistently, device-level studies report that increasing the\nspacer/underlap length can reduce fringing/overlap capacitance contributions, leading to a\nlower effective gate capacitance [R3]. More generally, the overlap/underlap (or spacer)\ndimension is a key geometry parameter that foundries routinely control and optimize to\nmeet balanced R–C targets at advanced nodes [R4]. In this context, the lithography-\ndefined underlap in our architecture can be viewed as a controlled, designable feature—\nsupported by the improved delay results in the original Supplementary Fig. 23b—rather\nthan an uncontrolled parasitic penalty.\nFigure R3. Fabrication process optimization to prevent additional series resistance. a,\nDevice fabrication schematic of the co-integrated HfSe FET, highlighting the physical\n2\nseparation between the gate-stack region and the Hf C edge-contact region, implemented to\n2\nprevent any overlap that could potentially induce additional series/access resistance. b,\nResulting device schematic and corresponding cross-sectional STEM image of the co-\nintegrated HfSe FET, confirming the clear spatial separation between the gate-stack region\n2\nand the edge-contact region.\nReferences\n[R1] Pal, A. et al. Three-dimensional transistors with two-dimensional semiconductors for\nfuture CMOS scaling. Nat. Electron.7, 1147–1157 (2024).\n[R2] Zhang, Q., Zhang, Y., Luo, Y. & Yin, H. New structure transistors for advanced\ntechnology node CMOS ICs. Natl Sci. Rev. 11, nwae008 (2024).\n[R3] Lee, S. et al. Sensitivity of inner spacer thickness variations for sub-3-nm node silicon\nnanosheet field-effect transistors. Nanomaterials12, 3349 (2022).\n[R4] Jing, Y., Zhou, J. & Zhou, P. Parasitic Capacitance Modeling of Si-Bulk FinFET-Based\npMOS. IEEE Trans. Electron Devices68, 4819–4825 (2021).\n6. Beyond 200 electrical sweeps, what is the interface’s stability under high-temperature\noperation, high-current stress, or long-term bias? Data from accelerated aging tests would be\nhighly valuable.\n (Evaluation under high-temperature operation & thermal stability of the interface)\nThe electrical characterizations of the co-integrated HfSe FETs were conducted over an\n2\nelevated temperature range (revised Supplementary Figure 32). To probe trapping &\ndetrapping dynamics and ohmic contact behavior under thermally activated conditions, the\ndevice temperature was increased from 300 K to 500 K. Even at 500 K, the devices exhibit\nnegligible hysteresis (≈3.1 mV), indicating that trap activity at the proposed vdW interface\nis strongly suppressed. Furthermore, the weak temperature dependence of the on-state\ncurrent confirms the robust ohmic contact behavior of the heteroepitaxial interface,\nconsistent with our results demonstrating barrier-free edge contacts (revised\nSupplementary Figure 32a). The interface behavior under thermal cycling was also\ninvestigated. In accordance with industry-standard reliability protocols [R1,2], the cycling\nconditions were defined with a temperature range from –40 °C to +125 °C, a controlled\nheating/cooling ramp rate limited to ±10 °C/min, and a dwell time of 2–3 min at each\ntemperature. Within this framework, the co-integrated HfSe FETs were subjected to up to\n2\n100 thermal cycles. The post-cycling electrical characteristics show negligible variation,\nas evidenced by a SS remaining near the Boltzmann limit and minimal change in the on-\nstate current, further confirming the thermal stability of the proposed vdW and\nheteroepitaxial interfaces (revised Supplementary Figure 32b).\n (Reliability under bias-temperature stress) To further assess reliability, bias-\ntemperature stress measurements were performed on co-integrated HfSe FETs. The\n2\ndevices were subjected to a stress bias of V = 4 V (corresponding to E = 4 MV/cm)\nstress stress\nat 300 K and 380 K for progressively increasing stress durations (revised Supplementary\nFigure 33). Following the generally implemented reliability criteria, measurements were\ncarried out over a temperature range from room temperature to 380 K. The measured |ΔV |\nth\nvalues were ≈0.025 V at 300 K (revised Supplementary Figure 33a,c), while under more\nstringent high-temperature stress conditions at 380 K, |ΔV | remained controlled at 0.08 V\nth\n(revised Supplementary Figure 33b,c). Importantly, the normalized |ΔV |/E value of\nth stress\n≈0.00625 V/(MV/cm) demonstrates improved reliability compared with the very limited\nnumber of assessments previously reported for 2D gate stacks [R3–12].\nDetailed characterization procedures and measurement results have been added in the revised\nSupplementary Information, and the relevant descriptions are mentioned in the revised\nManuscript as follows:\n…… suggesting the robust and clean interface between Hf C and HfSe (Fig. 5e). “The thermal\n2 2\nstability and reliability of the co-integrated HfSe FETs were further assessed through thermal\n2\ncycling and bias–temperature stress test (Supplementary Figs. 32 and 33).” The improved\ncurrent drive primarily arises from the seamless lateral conversion of HfSe ……\n2\n(revised Manuscript, page 11)\nSupplementary Figure 32. Thermal stability of the co-integrated HfSe FETs. a, Dual-\n2\nsweep transfer characteristics of the co-integrated HfSe FET measured over a range of\n2\ntemperatures. All measurements were performed at V = 1.0 V with a gate sweep rate of 0.01\nDS\nV/s (L = 200 nm, channel width = 2.5 μm, and HfSe thickness = 15 nm). b, Transfer\nch 2\ncharacteristics of the co-integrated HfSe FET recorded every 50 thermal cycles.\nDS ch\n200 nm, channel width = 2.5 μm, and HfSe thickness = 15 nm). The negligible variation in\nafter repeated thermal cycling, highlights the robustness of the proposed vdW and\nheteroepitaxial interfaces.\n“Temperature-dependent transfer characteristics of co-integrated HfSe FETs are shown in\nbehavior under thermally activated conditions, the device temperature was increased from 300\nK to 500 K. Even at 500 K, the devices exhibit negligible hysteresis (≈3.1 mV), indicating that\ntrap activity at the proposed vdW interface is strongly suppressed. Furthermore, the weak\ntemperature dependence of the I confirms the stable ohmic contact behavior of the\non\nheteroepitaxial interface, consistent with our electrical and electronic results demonstrating\nbarrier-free edge contacts. The thermal stability of the proposed HfO /HfSe vdW interface and\n2 2\nHf C/HfSe heteroepitaxial interface was further evaluated under thermal cycling conditions\n2 2\n(Supplementary Fig. 32b). Following the industry reliability standards62,63, the thermal cycling\nrange was set from –40 °C to +125 °C, with a controlled ramp rate (heating/cooling) limited to\n10 °C/min and a dwell time of 2–3 min at each temperature. Under these conditions,\nHfO /HfSe vdW interface and Hf C/HfSe heteroepitaxial interface were subjected to up to\n± 2 2 2 2\n100 thermal cycles. The negligible variation in the electrical characteristics confirms that the\nvdW and heteroepitaxial interfaces remain clean and abrupt, with no detectable interfacial\nreactions, structural collapse, or delamination, thereby demonstrating the robust thermal\nstability of the proposed interfaces.”\n(revised Supplementary Information, page 41)\nSupplementary References\n[62] JEDEC Solid State Technology Association. JESD22-A104F.01 Temperature Cycling\n(JEDEC, Arlington, VA, USA).\n[63] Automotive Electronics Council. AEC-Q100 Rev. G – Failure Mechanism Based Stress\nTest Qualification for Integrated Circuits (AEC Council).\nSupplementary Figure 33. Electrical characteristics of co-integrated HfSe FETs under\n2\nbias-temperature stress. a,b, Time-evolution transfer characteristics of co-integrated HfSe\nch\nchannel width = 2.5 μm, and HfSe thickness = 15 nm). c, Summarized variations in V as a\n2 th\nfunction of the applied stress time at 300 K and 380 K, respectively.\n“To further verify the reliability of the co-integrated HfSe FET, bias–temperature stress\n2\nmeasurements were performed using ≈10 nm HfO gate dielectrics under a stress bias of V\n2 stress\n= 4 V (corresponding to E = 4 MV/cm), at temperatures of 300 K (Supplementary Fig. 33a)\nstress\nand 380 K (Supplementary Fig. 33b), with progressively increasing stress durations. The\nextracted |ΔV | values were approximately 0.025 V at 300 K (black dots in Supplementary\nth\nFig.33c), and 0.08 V under high-temperature stress at 380 K (blue dots in the Supplementary\nFig. 33c). The observed negligible V shift under elevated-temperature stress suggests that the\nth\ndensity of interfacial states available to participate in trap-assisted charge dynamics is\nintrinsically suppressed in the proposed HfO /HfSe structures, consistent with extracted\n2 2\ninterface trap density (D it ≈5 × 1010 cm-2 eV-1), shown in the Supplementary Fig. 30. This result\nhighlights that, even when thermal energy is sufficient to activate trap dynamics, the vdW\ninterface presents only a very limited number of active states, thereby ensuring superior\ninterfacial stability. Furthermore, the I exhibits negligible variation during the bias–\non\ntemperature stress evaluation, indicating that carrier injection at the Hf C/HfSe junction\n2 2\nremains stable under electrical and thermal stress. Notably, the exceptionally low normalized\n|ΔV |/E value of approximately 0.00625 V/(MV/cm) highlights the markedly enhanced\nth stress\nreliability of the proposed vdW interface-integrated HfO /HfSe structure, representing a\n2 2\nadvancement over previously reported 2D gate stacks59,64-72.”\n(revised Supplementary Information, page 43)\nSupplementary References\n[59] Lan, H.-Y. et al. Reliability of high-performance monolayer MoS transistors on scaled\n2\nhigh-κ HfO . npj 2D Mater. Appl.9, 5 (2025).\n2\n[64] Illarionov, Y. Y. et al. The role of charge trapping in MoS /SiO and MoS /hBN field-\n2 2 2\neffect transistors. 2D Mater. 3, 035004 (2016).\n[65] Illarionov, Y. Y. et al. Bias-temperature instability in single-layer MoS transistors. Appl.\n[66] Yuan, H.-W. et al. PBTI investigation of MoS n-MOSFET with Al O gate dielectric.\n2 2 3\nIEEE Electron Device Lett. 38, 677–680 (2017).\n[67] Illarionov, Y. Y. et al. Long-term stability and reliability of black phosphorus field-effect\ntransistors. ACS Nano 10, 9543–9554 (2016).\n[68] Illarionov, Y. Y. et al. Improved hysteresis and reliability of MoS transistors with high-\n2\nquality CVD growth and Al O encapsulation. IEEE Electron Device Lett. 38, 1763–1766\n2 3\n(2017).\n[69] Illarionov, Y. Y. et al. Ultrathin calcium fluoride insulators for two-dimensional field-\neffect transistors. Nat. Electron.2, 230–236 (2019).\n[70] Grasser, T. et al. Analytic modeling of the bias temperature instability using\ncapture/emission time maps. In 2011 IEEE International Electron Devices Meeting (IEDM),\n27.4.1–27.4.4 (IEEE, 2011).\n[71] O’Sullivan, B. J. et al. Overview of bias temperature instability in scaled DRAM logic for\nmemory transistors. IEEE Trans. Device Mater. Reliab. 20, 258–266 (2020).\n[72] Yao, Z. et al. Transferrable, wet-chemistry-derived high-κ amorphous metal oxide\ndielectrics for two-dimensional electronic devices. Nat. Commun.16, 1482 (2025).\nReferences\n[R1] JEDEC Solid State Technology Association. JESD22-A104F.01 Temperature Cycling\n(JEDEC, Arlington, VA, USA).\n[R2] Automotive Electronics Council. AEC-Q100 Rev. G – Failure Mechanism Based Stress\nTest Qualification for Integrated Circuits (AEC Council).\n[R3] Illarionov, Y. Y. et al. The role of charge trapping in MoS /SiO and MoS /hBN field-\n2 2 2\neffect transistors. 2D Mater. 3, 035004 (2016).\n[R4] Illarionov, Y. Y. et al. Bias-temperature instability in single-layer MoS transistors. Appl.\n[R5] Yuan, H.-W. et al. PBTI investigation of MoS n-MOSFET with Al O gate dielectric.\n2 2 3\nIEEE Electron Device Lett. 38, 677–680 (2017).\n[R6] Illarionov, Y. Y. et al. Long-term stability and reliability of black phosphorus field-effect\ntransistors. ACS Nano 10, 9543–9554 (2016).\n[R7] Illarionov, Y. Y. et al. Improved hysteresis and reliability of MoS transistors with high-\n2\nquality CVD growth and Al O encapsulation. IEEE Electron Device Lett. 38, 1763–1766\n2 3\n(2017).\n[R8] Illarionov, Y. Y. et al. Ultrathin calcium fluoride insulators for two-dimensional field-\neffect transistors. Nat. Electron.2, 230–236 (2019).\n[R9] Grasser, T. et al. Analytic modeling of the bias temperature instability using\ncapture/emission time maps. In 2011 IEEE International Electron Devices Meeting (IEDM),\n27.4.1–27.4.4 (IEEE, 2011).\n[R10] O’Sullivan, B. J. et al. Overview of bias temperature instability in scaled DRAM logic\nfor memory transistors. IEEE Trans. Device Mater. Reliab.20, 258–266 (2020).\n[R11] Yao, Z. et al. Transferrable, wet-chemistry-derived high-κ amorphous metal oxide\ndielectrics for two-dimensional electronic devices. Nat. Commun.16, 1482 (2025).\n[R12] Lan, H.-Y. et al. Reliability of high-performance monolayer MoS transistors on scaled\n2\nhigh-κ HfO . npj 2D Mater. Appl.9, 5 (2025).\n2\n7. The manuscript rightly notes the incompatibility of semimetals like Bi and Sb with BEOL\ndue to low melting point or high diffusivity. How does Hf C perform in these aspects? Is the\n2\nreact with interconnect metals or interlayer dielectrics?\n (Thermal stability & diffusivity) Typical BEOL processing is widely treated as a\n≤400 °C thermal-budget regime to protect the interconnect stack [R1]. From an integration\nperspective, the primary BEOL concerns for contact materials are (i) thermal/phase\nstability and (ii) undesired diffusion. In this regard, Hf–C carbides belong to the\nrefractory/ultra-high-temperature family; for example, HfC is reported to have a very high\nmelting point (3890 °C), reflecting strong bonding and high intrinsic thermal stability\n[R2,3]. Consistent with this materials trend, SIMS-based studies report minimal Hf\ndiffusion in Si even after high-temperature anneals, with extracted diffusion coefficients\nof (1–3)×10-15 cm2/s at 1000 °C and (3–10)×10-14 cm2/s at 1100 °C [R4], suggesting that\nHf transport is strongly suppressed and unlikely to be limiting under BEOL-relevant\ntemperatures (≤400 °C). For C atom, C in Si is predominantly substitutional, and the\ndiffusivity of substitutional carbon under thermal-equilibrium point-defect conditions\nfollows D = 1.99 exp (–3.1 eV/k T) cm2/s [R5], which extrapolates to the suppressed\nS B\ndiffusivity (≈10-23 cm2/s) at 400 °C, indicating strongly suppressed C atomic transport\nunder BEOL-relevant temperatures.\n (Interconnect/ILD compatibility) Hf-based layers have been explicitly evaluated in Cu\nmetallization stacks at temperatures well above BEOL budgets. For instance, ultrathin\nALD HfO films are reported to act as effective diffusion barriers between Cu and Si, with\n2\na high failure temperature of ≈750 °C (N anneal, 5 min) [R6]. In addition, Cu/Hf stacks\n2\nshow Cu–Hf compound formation (e.g., CuHf ) after 550 °C annealing, whereas nitrogen\n2\nincorporation (Hf–N) suppresses Cu–Hf compound formation under the same anneal\ncondition and improves thermal stability in Cu/Hf–N/Si stacks (depending on N content)\n[R7]. From the C–Cu perspective, the Cu–C equilibrium assessment reports no carbide\nphases, and measured carbon solubility in solid Cu is very small (4.8–7.4 at. ppm at 1143–\nBEOL is also engineered around mandatory barrier/cap schemes to prevent Cu diffusion\nand oxidation. Representative dual-damascene flows employ a TaN/Ta barrier to prevent\nCu diffusion into dielectrics [R9] and use SiN/SiCN as an etch-stop (Cu barrier dielectric)\nto protect Cu from oxidation and suppress Cu diffusion into low-κ dielectrics [R10]. In the\nsemiconductor industry, SiCOH (organosilicate) low-κ films are widely used as inter-\nmetal dielectrics in interconnects [R11]. Within this established BEOL paradigm, potential\nreaction pathways between an underlying functional material and the interconnect/ILD are\nnormally managed by these standard barrier/cap/encapsulation modules rather than by\ndirect metal–dielectric contact.\n (Summary) The Hf–C carbide family offers a fundamentally larger thermal margin than\nlow-melting semimetals, and quantified diffusion data indicate strongly suppressed atomic\ntransport under BEOL-relevant temperatures (≤400 °C). Cu-metallization precedents\nfurther suggest strong diffusion/chemical robustness of Hf-based layers at temperatures\nwell above typical BEOL budgets, while Cu-C exhibits very low solubility and no carbide\nphases in equilibrium assessments. Taken together with standard BEOL barrier/cap\nintegration modules for Cu/low-κ stacks, we believe these literature-based considerations\nsupport the proposed contact integration as a BEOL-compatible strategy without\nintroducing dominant thermal or reactivity limitations.\nReferences\n[R1] Bong, J. H., Yoon, S. J., Yoon, A., Hwang, W. S. & Cho, B. J. Ultrathin graphene and\ngraphene oxide layers as a diffusion barrier for advanced Cu metallization. Appl. Phys. Lett.\n106, 063112 (2015).\n[R2] Verdon, C., Szwedek, O., Allemand, A., Jacques, S., Le Petitcorps, Y. & David, P. High\ntemperature oxidation of two- and three-dimensional hafnium carbide and silicon carbide\ncoatings. J. Eur. Ceram. Soc. 34, 879–887 (2014).\n[R3] Buinevich, V. S. et al. Ultra-high-temperature tantalum-hafnium carbonitride ceramics\nfabricated by combustion synthesis and spark plasma sintering. Ceram. Int. 47, 30043–30050\n(2021).\n[R4] Vyvenko, O. F. et al. Study of diffusivity and electrical properties of Zr and Hf in silicon.\nIn Semiconductor Silicon 2002 (eds Huff, H. R., Fabry, L. & Kishino, S.) 440–451 (The\nElectrochemical Society, 2002).\n[R5] Gösele, U., Laveant, P., Scholz, R., Engler, N. & Werner, P. Diffusion engineering by\ncarbon in silicon. Mater. Res. Soc. Symp. Proc.610, B7.1.1–B7.1.12 (2000).\n[R6] Majumder, P., Katamreddy, R. & Takoudis, C. G. Characterization of atomic layer\ndeposited ultrathin HfO film as a diffusion barrier in Cu metallization. MRS Online Proc. Libr.\n2\n990, 0990-B09-03 (2007).\n[R7] Ou, K.-L., Chiou, S.-Y., Lin, M.-H. & Hsu, R.-Q. Barrier capability of Hf-N films with\nvarious nitrogen concentrations against copper diffusion in Cu/Hf-N/n⁺-p junction diodes. J.\nElectrochem. Soc. 152, G138–G143 (2005).\n[R8] López, G. A. & Mittemeijer, E. J. The solubility of C in solid Cu. Scripta Mater. 51, 1–5\n(2004)\n[R9] Li, Z., Tian, Y., Teng, C. & Cao, H. Recent advances in barrier layer of Cu interconnects.\nMaterials 13, 5049 (2020).\n[R10] Martin, J. et al. Integration of SiCN as a low-κ etch stop and Cu passivation in a high\nperformance Cu/low-κ interconnect. In Proc. IEEE 2002 Int. Interconnect Technol. Conf. (Cat.\nNo.02EX519) 42–44 (IEEE, 2002).\n[R11] Hong, N. et al. The evolution of organosilicon precursors for low-κ interlayer dielectric\nfabrication driven by integration challenges. Materials 14, 4827 (2021).\n8. Finally, to enhance the clarity and professionalism of the manuscript, this reviewer\nrecommends streamlining the reference list by citing the most representative studies.\nFurthermore, the reference format requires standardization to comply with the journal’s style\nguide.\n In response to the reviewer’s comment, the reference list has been streamlined to focus on\nthe most representative studies, and the reference format has been standardized in\naccordance with the journal’s style guide throughout the revised Manuscript and the\nSupplementary Information.\nResponse to Reviewer #3\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in red.\nComments:\nIn this manuscript, the authors report a lateral chemical-conversion strategy to form embedded\nHf C/HfSe edge contacts, together with the integration of native HfO gate dielectrics. The\n2 2 2\nwork addresses an important challenge in 2D electronics, namely the realization of low-\nresistance, barrier-free carrier injection without relying on conventional metal deposition. The\noverall concept is clearly formulated, the experimental implementation is systematic, and the\ndevice performance is well characterized. From a structural and materials perspective, the\nauthors provide convincing evidence for the formation of atomically sharp in-plane\nheterointerfaces through comprehensive STEM, EDS, Raman, XPS, and simulation analyses.\nFrom an electronic standpoint, the STM/STS and KPFM measurements consistently support\nthe claim of suppressed metal-induced gap states and near-zero injection barriers. From a\ndevice perspective, the reported contact resistance (~475 Ω·μm), Schottky barrier height (~5\nmeV), near-ideal subthreshold swing (~62 mV/dec), and high drive current in short-channel\ndevices collectively indicate that the proposed contact and dielectric integration strategy\nfunctions as intended. At the same time, several points would benefit from further clarification\nto strengthen the rigor and generality of the work:\n1. Scalability and process controllability.\nThe contact formation relies on a spatially selective chemical conversion using masks. While\nthe authors have convincingly demonstrated the feasibility at the flake level, it remains unclear\nhow precisely this process can be controlled over large areas or dense device arrays. A short\ndiscussion on lithography compatibility and overlay tolerance would strengthen the manuscript\nfrom a manufacturing perspective.\nWe acknowledge the reviewer’s concern regarding scalability to large-area implementations\nand dense device arrays, including compatibility with standard lithography and practical\noverlay tolerance.\n (Process controllability) The spatial selectivity of the proposed contact formation is\nfundamentally governed by an edge-initiated, laterally propagating conversion mechanism.\nSpecifically, the conversion initiates at defined exposed edges and proceeds in-plane,\nrather than via a vertical (top-down) reaction through the basal plane. Accordingly, we\nconsider that the channel interior is inherently less susceptible to unintended conversion,\nand selectivity is achieved by defining where conversion is allowed to initiate (i.e., by\nlithographically patterning the exposure/edge geometry) rather than by relying solely on\nshielding the channel from a vertical reaction. In addition, the converted length/area can\nbe treated as a process parameter that is tunable by reaction time, enabling a controllable\nlateral conversion distance. The reproducible conversion-induced geometric changes\nobserved in our experiments (e.g., consistent thickness/area changes) further suggest that\npredictable processing can be incorporated into layout/design rules for scaled\nimplementations.\n (Lithography compatibility and overlay tolerance) In our demonstration, a\nlithographically patterned masking module (e.g., the SiO hard mask) is used as a standard\n2\nprocess-integration aid to define conversion-initiation windows and to maintain\ncompatibility with conventional patterning/etch/deposition workflows [R1]. Because the\nconversion boundary is tied to the lithographically defined edge/exposure geometry and\nthe conversion front propagates laterally from that pre-defined geometry, we believe the\nresulting boundary can be viewed as effectively self-aligned to the patterned features,\nwhich is favorable for dense integration [R2,3]. From an overlay perspective, we consider\nthat misalignment primarily maps onto conventional design margins—namely (i) ensuring\nsufficient overlap between the converted metallic contact region and the subsequently\ndeposited interconnect metal, and (ii) setting the intended registration between the gate\nedge and the contact boundary, as in standard device scaling [R4,5]. Importantly, since the\nmechanism does not rely on a vertical conversion through the basal plane, overlay errors\ndo not translate into uncontrolled conversion of the channel interior; instead, they mainly\nappear as a deterministic shift of the intended converted/unconverted boundary (i.e.,\ncontact extension/underlap) that can be accommodated through standard overlap margins\n[R4].\nBuilding on recent reports of wafer-scale HfSe films [R6,7], we will evaluate wafer-scale\n2\nuniformity and define practical process windows for large-area integration in future work.\nFrom this perspective, we have included a brief discussion in the revised Manuscript as follows:\n……within the 2D semiconductor channel. “The scalability of the proposed methodology\ntoward uniform wafer-scale integration can be investigated by coupling it with established\nwafer-scale channel-formation routes, while maintaining compatibility with standard\nlithography and enabling a practical overlay-tolerance window through a globally controlled,\nself-aligned conversion step.”\n(revised Manuscript, page 6)\nReferences\n[R1] Jaeger, R. C. Introduction to Microelectronic Fabrication. 2nd edn (Pearson Education,\n2002).\n[R2] Auth, C. et al. A 22nm high performance and low-power CMOS technology featuring\nfully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In\n[R3] Dennard, R. H. et al. Design of ion-implanted MOSFET’s with very small physical\ndimensions. IEEE J. Solid-State Circuits 9, 256–268 (1974).\n[R4] Levinson, H. J. Principles of Lithography. 4th edn (SPIE Press, 2019).\n[R5] International Technology Roadmap for Semiconductors (ITRS). Lithography (2007).\n[R6] Li, S. et al. Wafer-scale 2D hafnium diselenide based memristor crossbar array for energy-\nefficient neural network hardware. Adv. Mater. 34, e2103376 (2022).\n[R7] Chu, W. et al. Stable alkali halide vapor assisted chemical vapor deposition of 2D HfSe\n2\ntemplates and controllable oxidation of its heterostructures. Front. Phys. 19, 33212\n(2024).\n2. Distinction from conventional edge contacts.\nSince many recent studies use etched sidewalls followed by metal deposition, the authors\nshould more clearly distinguish “chemically converted embedded edge contacts” from\n“deposited edge contacts” in the benchmarking discussion to avoid ambiguity in literature\ncomparison.\n As per the reviewer’s comment, the benchmarking in the original Figure 4h have been\ncorrected and included in the revised Manuscript as follows.\nFigure 4. Electrical characterization of Hf C/HfSe edge contact. h, Benchmark of R\n2 2 C\nversus n for various edge-contact technologies with 2D semiconductors (Circles denote\n2D\nchemically converted embedded edge contacts, whereas triangles denote deposited edge\ncontacts)21-24, 32-36.\n(revised Manuscript, page 25-26)\n3. Role of interface dipoles and charge transfer.\nThe manuscript presents KPFM-derived work function values and a band diagram suggesting\nnearly zero electron injection barrier. However, the quantitative role of interface dipoles is not\nfully discussed. It remains unclear whether the observed near-zero barrier is governed primarily\nby work-function alignment or whether interfacial charge redistribution and dipole formation\nplay a non-negligible role. If possible, an estimate of the interface dipole density or potential\nstep would be helpful.\n We thank the reviewer for the insightful comment. While neither the semiconductor HfSe 2\nnor the metal Hf C exhibits spontaneous polarization individually due to the symmetry of\n2\nthe crystal, dipoles could be formed at the interface as new kinds of bonds are formed, as\nthe reviewer pointed out. However, if dipoles exist and are aligned at the interface, the\nband of HfSe must be bent accordingly due to the finite dielectric constant, in contrast to\n2\nmetallic Hf C layers. But this was not observed in the experiment (LDOS measurement),\n2\nindicating that the effect of interface dipoles is limited.\nTo further provide a brief quantitative estimate, we relate the potential step to an effective\n(screened) interfacial dipole density using the standard electrostatics of a dipole layer\n(Helmholtz relation) [R5]: . Here, denotes the areal dipole\nmoment density (net dipole mo\n𝑝\nm𝑠\n≈\nen\n𝜀\nt 0p\n𝜀\neerf fu\nΔ\nn\n𝑉\nitd iaproelae normal to\n𝑝\nth𝑠e interface; , with\nunits of cm-1), is the vacuum permittivity, is an effective relative permittivity that\n𝑝𝑠 = 𝑛𝜇⊥\ncaptures electrostatic screening by the surrounding media, and is the dipole-\n𝜀0 𝜀eff\ninduced electrostatic potential step across the interface. Becau Δ s 𝑉 ed ipole depends on\nscreening, we express the constraint in the form . Taking\n𝜀eff\n5 meV gives / ≈ 4.4×10-1 𝑝 4 𝑠c / m 𝜀e -1 f f( ≤ 0 𝜀 .00Δ 13 𝑉 dDip nolme -2 per Δ ) 𝑉 , dwiphoilceh ≤ is\norders of magn\n𝑝\ni𝑠tu\n𝜀\ndeef fsm\n≤\na l\n𝜀\nle0r t\nΔ\nh\n𝑉\nadni pvoalleues implied by comm\n≈\nonly reported inter\n𝜀\nfeafcfe potential\nsteps at metal/2D-material interfaces (e.g., ~0.3–0.4 eV for MoS /metal [R6] and ~0.4–1.8\n2\neV for metal/h-BN [R7]). Nevertheless, a rigorous quantitative determination of the\ninterfacial dipole (and the associated potential step) would require dedicated\nmeasurements and analysis beyond the scope of the present study.\nReferences\n[R1] Tung, R. T. The physics and chemistry of the Schottky barrier height. Appl. Phys. Rev.1,\n011304 (2014).\n[R2] Cowley, A. M. & Sze, S. M. Surface states and barrier height of metal–semiconductor\nsystems. J. Appl. Phys. 36, 3212–3220 (1965).\n[R3] Tersoff, J. Schottky barrier heights and the continuum of gap states. Phys. Rev. Lett. 52,\n465–468 (1984).\n[R4] Robertson, J. Band offsets, Schottky barrier heights, and their effects on electronic devices.\nJ. Vac. Sci. Technol. A31, 050821 (2013).\n[R5] Wagner, C. et al. Quantitative imaging of electric surface potentials with single-atom\nsensitivity. Nat. Mater.18, 853–859 (2019).\n[R6] Farmanbar, M. & Brocks, G. First-principles study of van der Waals interactions and\nlattice mismatch at MoS /metal interfaces. Phys. Rev. B93, 085304 (2016).\n2\n[R7] Bokdam, M. et al. Schottky barriers at hexagonal boron nitride/metal interfaces: a first-\nprinciples study. Phys. Rev. B90, 085415 (2014).\n4. Short-channel transport limits.\nGiven the very high pulsed current densities, a brief discussion on the dominant current-\nlimiting mechanisms (e.g., velocity saturation, self-heating) would further improve\ncompleteness.\n Under DC bias, the measured drive current can be further reduced by self-heating (Joule\nheating → increased phonon population → reduced mobility/effective ) and by hot\ncarrier/trap dynamics, making the onset of apparent saturation more pronounced.\n𝑣sat\nConsistent with this picture, pulsed operation increases I from 920 μA/μm to 1070\non\nμA/μm and delayed the onset of the saturation regime, indicating suppressed electro-\nthermal and transient trapping contributions under short-time operation and more closely\nrevealing the intrinsic high-field transport limit.\nFollowing the reviewer’s suggestion, we revised lines 298–301 of the original Manuscript\nas follows:\n…...accompanied by a delayed onset of the saturation regime. “This enhancement is\nattributed to the suppression of self-heating and hot-electron trapping49, which delays the\nvelocity saturation, facilitated by the atomically coherent Hf C/HfSe interface, thereby\n2 2\nmore closely reflecting the intrinsic current-driving capability relevant to circuit operation.”\nBased on the measured I values…...\non\n(revised Manuscript, page 11)\nReferences\n[49] Nathawat, J. et al. Transient hot-carrier dynamics and intrinsic velocity saturation in\nmonolayer MoS . Phys. Rev. Mater.4, 014002 (2020).\n2\n5. Device operation at logic-relevant voltages.\nSince the reported devices operate at voltages higher than those used in advanced CMOS logic\nnodes, a brief discussion on possible routes toward voltage scaling (e.g., thinner dielectrics,\nhigher-κ stacks, or reduced channel length) would further enhance the technological relevance\nof the work.\n We acknowledge the reviewer’s concern regarding voltage scaling toward logic-relevant\noperating regimes and practical pathways to reduce the operating voltage. As one\nrepresentative route, we are investigating conversion-enabled, higher‑κ gate dielectrics\nformed from stacked 2D-precursor layers (e.g., TMD1/TMD2/TMD1). In ongoing work,\nultraviolet–ozone oxidation of such multilayer 2D-precursor stacks yields a fully\nintermixed dielectric (Figure R5a). This converted dielectric exhibits an enhanced\ndielectric constant (κ > 50), exceeding that of conventional HfO , while maintaining a\n2\nsufficiently wide bandgap to preserve gate‑stack integrity and suppress gate leakage\n(Figure R5b,c). Leveraging this higher‑κ platform, we are currently pursuing a scaled‑EOT\ndemonstration targeting EOT < 0.5 nm and logic‑relevant operating voltages around 0.5\nV. The origin of the enhanced dielectric response and further gate-stack optimization for\naggressive voltage scaling will be investigated in our future studies.\nThe relevant discussion, together with the response to comment #7, has been included in\nthe revised Manuscript and the Supplementary Information as follows:\n…… which is comparable to advanced Si FETs and industrial roadmap targets. “Further\noptimization toward ultimate scaling while maintaining functional device operation will\nbe pursued in future work, guided by sub-50-nm device simulations (Supplementary Fig.\n38) and gate-stack engineering (e.g., EOT scaling via thinner dielectrics and/or higher-κ\nmaterials).” Collectively, these results underscore that the Hf C/HfSe edge-contact, when\n2 2\nco-integrated with a high-κ HfO gate stack……\n2\n(revised Manuscript, page 11-12)\nFigure R5. Possible route toward voltage scaling via higher-κ stack. a, Upper panel:\nSchematic illustration of higher-κ dielectric formation via UV-ozone oxidation of multiple\nstacked 2D precursors, which is currently under active investigation as a future extension of\nthis work. Lower panel: Cross-sectional STEM image of the fully intermixed higher-κ\ndielectric layer with EDS mapping. b, Dielectric constant as a function of frequency, showing\nan enhanced dielectric constant of κ > 50 for higher-κ dielectric compared with κ ≈ 23 for HfO .\n2\nc, Tauc plot derived from the ultraviolet visible (UV-vis) absorption spectrum of higher-κ\ndielectric (≈10 nm) on quartz, where is the absorption coefficient, Planck’s constant and\nthe frequency. Inset: Corresponding absorption spectrum of higher-κ dielectric prepared on\n𝛼 ℎ\nquartz and a schematic illustration of the measurement configuration.\n𝑣\n6. Lin 237-242: Fig 4d presents the temperature-dependent transfer characteristics of\nHf C/HfSe devices with a long channel length (L = 3 μm). For such long-channel devices,\n2 2 ch\nthe I is primarily limited by channel resistance; thus, lowering the temperature reduces\non\nphonon scattering and enhances I . However, when the channel is scaled down to a few\non\nhundred nanometers, the current is expected to be dominated by contact-limited current. To\nclarify this scaling effect, temperature-dependent transfer and output characteristics of shorter-\nchannel devices should be provided.\n To address reviewer’s comment, we additionally fabricated Hf 2 C/HfSe 2 FETs with a scaled\nchannel length down to L = 100 nm and carried out temperature-dependent electrical\nch\nmeasurements, including transfer and output characteristics (revised Supplementary\nFigure 19). In our current short-channel devices, the output characteristics remain linear\nacross the measured temperature range without the appearance of pronounced rectifying\nfeatures, indicating that carrier injection at the Hf C/HfSe junction remains efficient even\n2 2\nwhen contact/access contributions are increased. Consistently, Arrhenius analysis of the\ntemperature-dependent data yields an effective Schottky barrier height near zero (within\nexperimental uncertainty), suggesting that thermionic emission over a barrier is not the\ndominant injection mechanism in the scaled devices. Therefore, the remaining temperature\ndependence of I is most reasonably attributed to the residual channel component (e.g.,\non\nmobility changes due to phonon scattering) and other series contributions, rather than a re-\nemergent contact barrier. Overall, these short-channel results support that the Hf C/HfSe\n2 2\njunction maintains robust near-ohmic injection upon channel-length scaling.\nThese results have been included in the revised Supplementary Information and are briefly\ndiscussed in the revised Manuscript as follows:\n…...the stable ohmic contact behavior at the Hf C/HfSe interface (Fig. 4c). “Similar\n2 2\nresults are also observed in devices with scaled channel lengths (Supplementary Fig. 19).”\nIn contrast, the Ti/Au-HfSe FET exhibits nonlinear output…...\n2\n(revised Manuscript, page 9)\nSupplementary Figure 19. Temperature-dependent electrical characteristics of short-\nchannel Hf C/HfSe FET. a-d, Output characteristics of the Hf C/HfSe FET measured over\n2 2 2 2\na wide range of temperatures and back-gate voltages (L = 100 nm, Temperature = 77 – 300\nch\nK, V = 0 – 60 V, Back-gate dielectric = SiO 285 nm, HfSe thickness = 40 nm). e, Transfer\nGS 2 2\ncharacteristics of the Hf C/HfSe FET measured over a wide range of temperatures. f, Energy\n2 2\nbarrier extracted from the temperature-dependent transfer characteristics (Inset: Arrhenius plot).\n“Temperature-dependent transfer and output characteristics were measured for shorter-channel\ndevices (L = 100 nm) to assess carrier-injection efficiency under channel-length scaling\nch\n(Supplementary Fig. 19a-e). The short-channel devices exhibit similarly linear output\ncharacteristics and negligible Schottky behavior over the entire measured temperature range,\nindicating that efficient, near-ohmic injection is maintained upon channel-length scaling, where\ncontact/access contributions become more pronounced. Consistently, the Schottky barrier\nheight extracted from Arrhenius analysis of the temperature-dependent data remains near zero,\nfurther supporting robust ohmic contact behavior at the Hf C/HfSe junction even at the scaled\n2 2\nchannel length.”\n(revised Supplementary Information, page 24)\n7. Figure 5 presents the electrical characteristics of Hf C/HfSe devices with a short channel\n2 2\nlength (L = 200 nm). Based on the observed performance, can the channel length be further\nch\nscaled to sub-50 nm while maintaining functional device behavior? If available, scaling trends\nor simulations supporting such scalability would be valuable.\n To address the reviewer’s comment, we performed device simulations to evaluate scaling\ntrends down to L = 50 nm. TCAD simulations were performed to assess the scaling\ng\nbehavior of the co-integrated HfSe FETs down to a L of 40 nm. To ensure realistic\n2 g\nelectrical characteristics, we rigorously incorporated key physical parameters, including\nSchottky barrier height, low-field mobility, effective mass, effective density of states, band\ngaps of HfSe and HfO , and contact resistance. The simulated transfer characteristics for\n2 2\nthe L = 200 nm device exhibit good agreement with the measurement results at both V\ng DS\n= 0.1 V and 1.0 V (revised Supplementary Figure 38a). To accurately capture carrier\ntransport physics, we incorporated the density-gradient quantum correction, velocity\nsaturation, and the inversion and accumulation layer mobility model. Based on this\ncalibrated framework, we carried out a gate-length scaling study from L = 200 nm down\ng\nto 40 nm while keeping other geometric parameters fixed to isolate the intrinsic impact of\nL scaling. Revised supplementary Figure 38b summarizes the evolution of the transfer\ng\ncharacteristics as L is reduced. The devices maintain steep subthreshold slopes and low\ng\nDIBL down to L = 100 nm, with SS remaining close to the Boltzmann limit (~60 mV /dec\ng\nat room temperature) and negligible V roll-off (revised Supplementary Figure 38c,d).\nth\nWhen L is further reduced to below 50 nm, the simulations show a pronounced increase\ng\nin subthreshold leakage and a negative shift of V , indicating the onset of severe short-\nth\nchannel effects (revised Supplementary Figure 38c,d). In this study, such degradation\narises primarily from the electrostatic scaling limit imposed by the fixed gate-dielectric\nthickness (i.e., limited EOT scaling). Accordingly, improved electrostatic designs with\nstronger gate–channel wrap-around control (e.g., gate-all-around geometries), together\nwith continued EOT scaling, are expected to be effective routes to suppress DIBL and V\nth\nroll-off in the sub-50-nm regime.\nThe relevant discussion, together with the response to comment #5, has been included in\nthe revised Manuscript and the Supplementary Information as follows:\n…… which is comparable to advanced Si FETs and industrial roadmap targets. “Further\noptimization toward ultimate scaling while maintaining functional device operation will\nbe pursued in future work, guided by sub-50-nm device simulations (Supplementary Fig.\n38) and gate-stack engineering (e.g., EOT scaling via thinner dielectrics and/or higher-κ\nmaterials).” Collectively, these results underscore that the Hf C/HfSe edge-contact, when\n2 2\nco-integrated with a high-κ HfO gate stack……\n2\n(revised Manuscript, page 11-12)\nSupplementary Figure 38. TCAD simulations of co-integrated HfSe FETs. a, Calibration\n2\nof TCAD simulation results against experimental data for L = 200 nm at V = 0.1 V and 1.0\ng DS\nV. The inset shows a schematic of the simulated device structure. b, Simulated transfer\ncharacteristics as L is scaling from 200 nm down to 40 nm. c, Extracted DIBL and SS as a\ng\nfunction of L . d, V scaling characteristics as a function of L at V = 0.1 V and 1.0 V.\ng th g DS\n“TCAD simulations were performed to assess the scaling behavior of the co-integrated HfSe\ng\nincorporated key physical parameters, including Schottky barrier height, low-field mobility,\neffective mass, effective density of states, band gaps of HfSe and HfO , and contact resistance.\n2 2\nThe simulated transfer characteristics for the L = 200 nm device exhibit good agreement with\ng\nthe measurement results at both V = 0.1 V and 1.0 V (Supplementary Fig. 38a). To accurately\nDS\ncapture carrier transport physics, we incorporated the density-gradient quantum correction,\nvelocity saturation, and the inversion and accumulation layer mobility model. Based on this\ncalibrated framework, we carried out a gate-length scaling study from L = 200 nm down to 40\ng\nnm while keeping other geometric parameters fixed to isolate the intrinsic impact of L scaling.\ng\nSupplementary Fig. 38b summarizes the evolution of the transfer characteristics as L is\ng\nreduced. The devices maintain steep subthreshold slopes and low DIBL down to L = 100 nm,\ng\nwith SS remaining close to the Boltzmann limit (~60 mV /dec at room temperature) and\nnegligible V roll-off (Supplementary Fig. 38c,d). When L is further reduced to below 50 nm,\nth g\nthe simulations show a pronounced increase in subthreshold leakage and a negative shift of V ,\nth\nindicating the onset of severe short-channel effects (Supplementary Fig. 38c,d). In this study,\nsuch degradation arises primarily from the electrostatic scaling limit imposed by the fixed gate-\ndielectric thickness (i.e., limited EOT scaling). Accordingly, improved electrostatic designs\nwith stronger gate–channel wrap-around control (e.g., gate-all-around geometries), together\nwith continued EOT scaling, are expected to be effective routes to suppress DIBL and V roll-\nth\noff in the sub-50-nm regime.”\n(revised Supplementary Information, page 49)\n8. The HfSe /HfO heterostructure is fabricated through layer-by-layer plasma oxidation. If the\n2 2\nterminal HfSe layer undergoes incomplete oxidation, could this partial oxidation state\n2\nintroduce oxygen vacancies at the HfSe /HfO interface? Please comment on how oxidation\n2 2\ncompleteness is ensured and whether interfacial oxygen vacancies are detected or controlled.\n To address the reviewer’s concern about oxidation completeness and controllability in\nHfSe , we performed additional experiments by varying key process parameters, focusing\n2\non oxygen density (plasma power) as the most interface-relevant knob. Approximately 40\nnm-thick HfSe flakes were transferred onto the substrate and subsequently oxidized under\n2\nthe given plasma conditions (O gas, 5 W, 5 sccm, 470 mTorr, 15 min), resulting in the\n2\nformation of ≈10 nm HfO . The fabricated HfO /HfSe heterostructures retained the\n2 2 2\natomically flat vdW interface; however, unconverted HfSe layers were clearly observed\n2\nwithin the HfO film (Figure R6a). These results are also consistent with our investigation\n2\nof oxidation characteristics under reduced plasma power, which was conducted to explore\nthe possibility of further optimized oxidation conditions (Figure R6e). Cross-sectional\nSTEM imaging of the 10 nm HfO layer converted under a plasma power of 5 W reveals\n2\nlocally unconverted HfSe domains embedded within the HfO layer, indicating\n2 2\nincomplete oxidation under reduced plasma power. To quantitatively examine the residual\nSe atoms, XPS depth profiling was further conducted (Figure R6f). For this analysis, the\nHfO samples were sequentially thinned by ≈2.5 nm at a sputtering rate of 0.5 nm/min,\n2\nand the XPS spectra were collected after each thinning step. In contrast to the 10 W\ncondition (Figure R7), where all HfSe was fully oxidized and no Se signal was detected,\n2\ndistinct Se 3d peaks were observed under the lower-power condition. This finding is\nconsistent with the locally unconverted HfSe region in the cross-sectional STEM images.\n10–13 W, complete conversion into HfO was achieved while maintaining an atomically\n2\nflat vdW interface, as evidenced in Figure R6b. Beyond this range (14–30 W), a clear\ncollapse of the vdW interface accompanied by severe interfacial disorder was observed\n(Figure R6c), indicating that this method is no longer applicable under such conditions.\nConsidering both vdW interface integrity and dielectric conversion, the process window\nfor plasma power is summarized in Figure R6d, which clearly identifies 10–13 W as the\noptimal range to achieve complete oxidation while preserving a clean vdW interface.\nFigure R6. Process parameter window for vdW interface-integrated HfO /HfSe\n2 2\nheterostructures. a-c, Cross-sectional STEM images of HfO /HfSe heterostructures\n2 2\nfabricated under different plasma power conditions. d, Process window summarized in terms\nof plasma power, highlighting the overlap region (red arrow) where both a clean vdW interface\nand robust dielectric integrity are simultaneously preserved. e, Cross-sectional STEM image\nof HfO formed from HfSe under reduced plasma power (5 W, 5 sccm, 470 mTorr). f, XPS\n2 2\ndepth profiling of the converted HfO layer shown in (e). The O 1s and Se 3d peak ratios were\n2\nmonitored from the top surface of the ≈10 nm HfO down to the bottom through sequential\n2\nthinning steps at a sputtering rate of 0.5 nm/min. The detection of the Se 3d signal at a depth\nof ≈5 nm indicates the presence of locally unconverted HfSe . These results indicates that such\n2\nlow-power plasma conditions are insufficient to ensure complete oxidation of HfSe into HfO .\n2 2\nFigure R7. Complete oxidation of HfO converted from thick HfSe a, Cross-sectional\n2 2.\nSTEM image, and corresponding elemental mapping of an ≈50 nm HfO layer converted from\n2\n≈120 nm thick HfSe . b, XPS depth profiling of the converted HfO layer. The O 1s and Se 3d\n2 2\npeaks were monitored from the top surface of the HfO down to the bottom through sequential\n2\nthinning steps at a sputtering rate of 0.5 nm/min. The absence of detectable Se 3d signals\nthroughout the overall depth profile indicates the full conversion of the pristine ≈120 nm HfSe .\n2 2\nthe given plasma conditions (10 W, 5 sccm, 470 mTorr) employed in this study.\n9. Can the thickness of HfSe be further scaled to sub-5 nm while maintaining acceptable\n2\nmobility and gate control? If relevant data or estimates exist, please include them.\n Following the reviewer’s comment, we newly fabricated co-integrated HfSe 2 FET with an\natomically thin bilayer HfSe channel (revised Supplementary Figure 34). After forming\n2 2\nprocess described in the Methods section was applied. Through this process, the\nunconverted 25-nm-thick HfSe region was selectively oxidized for 5 min, resulting in the\n2\nformation of a HfO (10 nm)/bilayer HfSe heterostructure. In this bilayer configuration,\n2 2\nthe atomically flat vdW interface (HfO /HfSe ) and the atomically sharp heteroepitaxial\n2 2\ninterface (Hf C/HfSe ) are seamlessly co-integrated, enabling effective electrostatic\n2 2\ncontrol in the resulting devices. Furthermore, we evaluated carrier mobility by extracting\nthe field-effect mobility ( ) for both the bulk and bilayer HfSe devices, as well as the\n𝜇FE\n𝜇Hall\nDetailed characterization and results have been included in the revised Supplementary\nInformation and are briefly discussed in the revised Manuscript as follows:\n…...HfO dielectric layer (Supplementary Figs. 26a and 27). “Comparable field-effect\n2\nmobility to that reported for MoS upon channel-thickness scaling39,40 was also observed\n2\n(Supplementary Figs. 35-37)” Detailed electrical and interfacial characterization…...\n(revised Manuscript, page 11)\n…...advanced contact technologies reported to date (Fig. 5f) 1,16,17,20,41-48. “Co-integrated\nHfSe FETs with an atomically thin bilayer channel also achieved improved electrostatic\n2\ncontrol while preserving carrier-injection efficiency, offering a scaling demonstration that\nis technologically relevant to the channel-thickness regime of state-of-the-art Si nanosheet\nnodes (Supplementary Fig. 34).” To further assess the intrinsic drive capability beyond…...\n(revised Manuscript, page 11)\nReferences\n[39] Ha, V.-A. & Giustino, F. High-throughput screening of 2D materials identifies p-type\nmonolayer WS as potential ultra-high mobility semiconductor. npj Comput. Mater. 10, 229\n2\n(2024).\n[40] Sebastian, A. et al. Benchmarking monolayer MoS and WS field-effect transistors. Nat.\n2 2\nCommun.12, 693 (2021).\nSupplementary Figure 34. Characteristics of co-integrated HfSe FET with an atomically\n2\nthin channel. a, Upper panel: Schematic of the co-integrated HfSe FET incorporating a\n2\nbilayer HfSe channel. Lower panel: Enlarged cross-sectional STEM image of the HfO /HfSe\n2 2 2\nheterostructure, showing a well-preserved, atomically flat vdW interface. b, Transfer curves of\nthe co-integrated bilayer HfSe FET measured at a gate-voltage sweep rate of 0.01 V/s. The\n2\ndrain current was normalized by a channel width of 2.5 μm.\n“To evaluate the performance of co-integrated HfSe FET at an atomically thin channel\n2\nthickness, we fabricated co-integrated bilayer HfSe FET. Starting from an initial ≈25-nm-thick\n2 2\nsame plasma oxidation step described in the Methods was then applied locally to the channel\nregion for 5 min, yielding a HfO (≈10 nm)/bilayer-HfSe heterostructure. As shown in\n2 2\nSupplementary Fig. 34a, cross-sectional STEM reveals an atomically flat HfO /HfSe interface,\n2 2\nconfirming the well-preserved vdW interface. Consistent with this structural integrity, the\nfabricated FET exhibits an SS of 64 mV/dec, indicative of effective gate controllability\n4order\n(Supplementary Fig. 34b).”\n(revised Supplementary Information, page 44)\nSupplementary Figure 35. Field-effect mobility of co-integrated HfSe FETs varying with\n2\nchannel thickness. a,b, Transfer characteristic and extracted of a co-integrated HfSe\n2\n𝜇𝐹𝐸\nchannel width of 2.5 μm. Gae-voltage sweep rate = 0.01 V/s. c,d, Transfer characteristic and\nextracted of a co-integrated HfSe FET fabricated with a bilayer HfSe channel. The drain\n2 2\ncurrent was normalized by a channel width of 2.5 μm. Gae-voltage sweep rate = 0.01 V/s.\n𝜇𝐹𝐸\n“The field-effect mobility ( ) of the co-integrated HfSe FETs fabricated with a ≈15-nm-\n2\nthick HfSe channel and a bilayer HfSe channel was extracted from the linear-regime of the\n2 𝜇𝐹𝐸 2\ntransfer characteristics (Supplementary Fig. 35a,c) using the following relation: =\n( /C V )(L/W), where W and L are the channel width and length, respectively, C is the\nox DS o𝜇x 𝐹𝐸\noxide capacitance, is the transconductance, V is the drain voltage. The transconductance,\n𝑔𝑚 DS\nwas extracted from the linear region, where |V - V | > |V |. Based on this analysis, the\n𝑔𝑚 GS th DS\nvalues of the two devices were estimated to be ≈35 and ≈33 cm2/V·s, respectively\n𝑔𝑚\n(Supplementary Fig. 35b,d). The preservation of comparable values down to the bilayer\n𝜇𝐹𝐸\n𝜇𝐹𝐸\nthickness indicates that the in-plane carrier transport properties of HfSe are largely maintained\n2\nupon aggressive thickness scaling. This trend is consistent with a key advantage of 2D\nsemiconductors with dangling-bond-free surfaces, in contrast to conventional Si nanosheet\nchannels where mobility degradation is commonly observed as the channel thickness is\nreduced73. Importantly, the result further confirms that both the vdW interface and the\nunreacted top surface of the HfSe channel remain well preserved during the plasma oxidation\n2\nprocess, even in the atomically thin channel regime.”\n(revised Supplementary Information, page 45)\nSupplementary References\n[73] Agrawal, A. et al. Silicon RibbonFET CMOS at 6 nm gate length. IEEE Int. Electron\nDevices Meet. (IEDM), 1–4 (2024).\nSupplementary Figure 36. Hall mobility analysis of HfSe .a, Left: Schematic of the device\n2\ngeometry used for Hall measurements. Right: Enlarged SEM image showing the 200-nm\nelectrode spacing, together with the magnetic-field configuration used in the measurement.\nHfSe thickness = 15 nm. b, Comparison of and two-probe as a function of gate\n2\nvoltage at V = 0.1 V. The two-probe were extracted from the transfer curve in Fig. 5c.\nDS\n𝜇𝐻𝑎𝑙𝑙 𝜇𝐹𝐸\n“The bulk mobility of was evaluated usi𝜇n𝐹g𝐸 Hall measurements. A constant current was applied\nbetween the source and drain electrodes, while a perpendicular magnetic field of 0.525 T was\napplied normally to the channel plane (Supplementary Fig. 36a). The transverse Hall resistance\n( ) was measured to obtain the average Hall resistance ( ), and the carrier density (\nw\n𝑅\na𝑋s𝑌 simultaneously obtained using equation\n𝑅\n,𝑎 w𝑣𝑔here is the electron charg\n𝑛\ne\n)\n.\n𝑛 = 1/(𝑒𝑅𝑎𝑣𝑔) 𝑒\nBy taking and the measured conductivity ( , the as a function of gate voltage were\nestimated using equation Notably, is comparable to the\n𝑛 𝜎) 𝜇𝐻𝑎𝑙𝑙\ncorresponding two-probe over the same carrier concentration (Supplementary Fig. 36b).\n𝜇𝐻𝑎𝑙𝑙 = 𝜎/(𝑛𝑒). 𝜇Hall\nThis consistency indicates that the measured device performance is governed by intrinsic\n𝜇FE\nchannel transport rather than contact resistance or interfacial scattering, thereby confirming the\nhigh quality of the vdW interface as well as the integrity of the heteroepitaxial Hf C/HfSe\n2 2\nlateral edge contacts.”\n(revised Supplementary Information, page 47)"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors have thoroughly addressed all of the reviewer's comments/concerns, thus the reviewer recommends to publish as is.", "reviewer_2": "The authors resolved all of scientific concerns raised by reviewers. I agree to publish this article on Nature Communications without further revision.", "reviewer_3": "The author has satisfactorily addressed the concerns I raised in this revised manuscript. Moreover, the novelty of this work and the quality of the data are outstanding, which will offer valuable insights and provide a significant push forward for the development of the two-dimensional transistor field. Therefore, I recommend its acceptance."}, "author_response": ""}]

Decision letter