Nonlinear optical vector processing using linear silicon photonic circuits for 50 Gb/s memory and string similarity functions

Domain: physics
Published: 2025-12-17
Editorial outcome: major_revision

Abstract
The need for high-speed, energy-efficient computing in machine learning and communications necessitates innovations beyond conventional electronics to sustain computational power advances without requiring prohibitive energy amounts. Photonics have emerged in various applications, demonstrating significant highlights in optical linear transformations, while if successfully employed can also be used in nonlinear processes and matching functionalities. Towards this we demonstrate nonlinear optical vector processing in the form of hamming distance calculations and content addressable memory banks, using linear silicon photonic circuits at the high-speed of 50 Gb/s, enabling pattern matching and look-up operations. The processor employs a 4×4 crossbar architecture utilizing silicon germanium modulators computing hamming distance between 2-bit optical vectors. It achieves error-rates of ~10⁻³ in binary/ternary content matching, improving state-of-the-art demonstration speeds by >2.5×. Scalability is enhanced through space-wavelength multiplexing via a wavelength-division multiplexing cell, experimentally demonstrated at 50 Gb/s, offering increased computational capacity with reduced insertion losses and power consumption.

Introduction
The demand for high-speed and energy-efficient computing continues to rise with the proliferation of data-intensive applications, such as machine learning, genomic analysis, and real-time communication1. In this race, digital electronic systems comprise still the steam engine in today’s computational landscape, though analog electronics are also gaining momentum as a viable alternative for energy efficient computations directly in the analog domain2. However, as data rates and dataset sizes continue to grow, electronic computing in both its digital and analog versions is facing diminishing returns due to the native physical constraints of electronic technology: the size and energy advantages of electronic circuitry are naturally counteracted by the speed and power limits of the electronic interconnects inside the circuits due to RC parasitic effects3, with current electronic processors hardly exceeding GHz clock frequencies. These limitations indicate that a radical shift from conventional electronic computing architectures towards novel hardware computing paradigms need to be realized.

In this direction, silicon photonics (SiPho) emerge as a promising candidate for penetrating the processing and compute domains to turn their well-known dominance in the interconnect sector into a profound advantage also in the computational segment. Migrating, however, into a light-enabled processor technology paradigm has to ensure the successful deployment of fundamental computing operations at both symbol- and vector-/string-level in the optical domain. In this realm, photonics have already shown an impressive potential in implementing universal linear transformations over analog optical vectors4–8 facilitating critical matrix and tensor multiplier building blocks in application fields like quantum9,10, neuromorphic11–16 and microwave photonics17,18. However, a broad range of applications like pattern matching, error correction and similarity searches require nonlinear processing functions like comparison and distance calculation processes between strings. These necessitate typically the use of memory and register blocks that are certainly not yet among the strengths of the photonic circuitry19,20. The calculation of string metrics, like the well-known Hamming Distance (HD), provides critical quantitative information about string and vector similarity21, with certain distance values leading often to completely new functional blocks. Content Addressable Memories (CAMs), for example, form a specialized yet highly important pattern matching application22 that correspond to a zero HD and constitute a critical element in high-speed routers, address and database lookups, and associative search functions23. Although optical CAMs experienced a significant progress during the last decade24–26 and raised expectations even for complete high-speed look-up operations via silicon photonic Microring Resonator- (MRRs)27 or electro-absorption modulator-based (EAM) setups28, the transition from the specific vector matching to the more generic nonlinear processes like vector distance calculation has still not identified a viable photonic implementation route that would broaden the computational portfolio of integrated optics.

In this paper we introduce, to the best of our knowledge, the nonlinear transformation of optical vectors by using a linear SiPho circuit and demonstrate HD calculation and CAM operation between binary optical strings at record-high data rates of 50 Gb/s. The processor relies on the recently introduced Crossbar (Xbar) architecture5, configured as a 4×4 matrix arrangement and employing 56 GHz bandwidth silicon germanium (SiGe) EAMs as its core computational cells. Its performance was experimentally evaluated in calculating the HD between 2-bit optical vectors, presenting also successful operation as optical CAM and Ternary CAM (TCAM) memory bank for 2-bit optical words with matching error-rates of ~10−3 at operational speeds 2.5× higher than current state-of-the-art CAMs clock speed. Moreover, we introduce a viable roadmap for increasing computational capacity by using space-wavelength multiplexed memory cells, demonstrating experimentally a wavelength division multiplexing (WDM)-enabled architecture that encodes optical vectors across a 2D space-wavelength dimension and performs vector processing at 50 Gb/s.

Results
Hamming distance calculation using a silicon photonic crossbar integrated circuit
HD is a metric widely employed in coding theory and error correction codes29, in information theory30, in Hamming clustering methods for data clustering31, as well as in bioinformatics for DNA sequencing32, underscoring its wide-reaching impact across computational and scientific disciplines. It is a nonlinear operation defined as the number of positions at which the corresponding symbols (characters or bits) differ. An illustrative example of its application is depicted in Fig. 1a, where the HD metric is applied to two N-length binary vectors X and Y. Mathematically the HD operation is defined by the following equation:

HD(X,Y) = \sum_{i=1}^{N} L(X(i)≠Y(i)) (1)

with the function L(X(i)≠Y(i)) indicating all the positions in the N-length vectors X and Y where their corresponding values differ. The most prominent implementation of the HD operator in digital electronics comprises a XOR-gate array, followed by a Full-Adder Tree, as schematically illustrated in Fig. 1b33. Implementing this nonlinear HD calculation process via linear transformations can be realized by doubling the vector dimensions to incorporate also the inverted vector values and applying a dot product operation, as has been initially demonstrated via a rather low-speed analog electronic HD circuitry, depicted in Fig. 1c21. In this layout, the actual and complementary values of array Y are programmed in a memristor array, while the X actual and complementary values are injected as voltage signals across the memristor array. The resulting output current is, due to Kirchhoff’s law, directly correlated to the HD of the input X and Y vectors.

The employment of this mathematical concept and the transfer of the memristor-based architectural approach into the photonic domain can be realized by adopting an equivalent analog optical circuit, as depicted in Fig. 1d, e, by: (i) encoding the X actual and complementary vector values into a modulated optical light carrier (ii) encoding the Y actual and complementary values in the transmission values of optical amplitude modulators, which can be assumed to act as optical memory cells that store the corresponding transmission value, (iii) injecting the encoded X modulated light beams to the Y amplitude modulating elements and adding coherently the resulting optical fields, by utilizing thermo-optic phase shifters that ensure proper phase matching between the two branches. The comparison cell highlighted in Fig. 1d, comprises the basic building block of this comparison operation (details for its functionality are also provided in Supplementary Section 1). The basic analog photonic HD circuitry that performs a dot product operation between two optical vectors has been initially presented in ref. 34 and is shown in Fig. 1d. This can be expanded to a parallel HD processor by employing the coherent Xbar architecture, originally proposed in ref. 5 and depicted in Fig. 1e. In this layout the X actual and complementary values are equally broadcasted to the corresponding M Xbar columns using directional couplers, with properly selected splitting ratios. Each column of the Xbar is configured to hold different predefined/target vectors, with each comparison cell assigned to a distinct symbol value. Hence, the HD operation between the incoming X vector and the respective target #M Y Vectors of the Xbar array, is executed in parallel across all Xbar columns allowing up to M parallel HD calculations.

The functionality of the proposed analog photonic HD processor architecture was assessed via a 4×4 SiPho integrated Xbar layout that is capable of 2-bit vector distance processing, surpassing prior optical CAM implementations27,28, which have demonstrated only 1-bit comparison operations. The photonic chip was fabricated in imec’s SiPho platform, using PDK-ready components. Particularly, every computing cell of the Xbar prototype incorporates 50 μm long, 56 GHz Franz–Keldysh (FK) SiGe EAMs and 170 μm long thermo-optic phase shifters (TO-PSs). The deployed photonic integrated circuit (PIC) supports 2-bit search vectors, encoded through the search vector encoding unit (SVEU), highlighted with the yellow rectangle in Fig. 2a, that utilizes four EAMs to generate two pairs of complementary search values. The encoded search information is then forwarded into the Xbar-based HD processor, with the corresponding chip area marked with an orange rectangle. The optical signals are distributed across all Xbar columns, which statically encode all the target vectors at every EAM column. The HD result (“match”/degree of “mismatch”) between the search and target vectors is generated at each Xbar output column.

The experimental testbed, established for the evaluation of the HD operations, is depicted in Fig. 2b. A tunable laser source (TLS) is employed to generate a continuous wave (CW) optical signal at 1563 nm which is injected into the 4×4 Xbar chip. A 4-channel arbitrary waveform generator (AWG) is used to generate the 2-bit electrical search vector. The first and third channel produces the Bit1 and Bit2, respectively, while the second and fourth channels generates their complementary values, i.e. Bit1 and Bit2. After electrical amplification, the electrical signals are fed into the input EAMs (yellow rectangle) to encode the optical SVEU. The target 2-bit vectors (i.e., “00”, “01”, “10” and “11”) are implemented by setting the optical attenuation of EAMs located at each Xbar row. Thermo-optic phase shifters are deployed to ensure constructive interference at the output columns of the Xbar. Both EAMs and TOPSs are controlled by a multi-channel DC control plane, that consists of 16 programmable 2-channel DC power supplies. The output of each column is captured by an oscilloscope, after being amplified and detected by a photodiode. More details of the experimental setup can be found in methods section.

Experimental validation of hamming distance calculation and ternary CAM memory bank at 50 Gb/s
The performance of the proposed parallel HD processor was experimentally assessed with 2-bit optical vectors encoded onto the SVEU and compared with respective 2-bit optical vectors stored onto the four Xbar columns. The case of HD=0 designates an exact vector matching and corresponds to the match-line (ML) operation of a complete CAM memory bank, with the incoming optical vector representing the search word and the stored optical vectors the respective address words. The photonic comparison cells are used for representing all the memory states of a Binary CAM cell, i.e. “0”, “1”, but can also support the wildcard/ternary value “X” by storing a zero-transmission value to both EAMs within the comparison cell, allowing in this way for an extension to ternary CAM (TCAM) applications.

The HD and ML operations performed through the Xbar processor have been experimentally validated for search vector streams at 20 Gb/s and 50 Gb/s. Figure 3a, c illustrates the time sequences of the 2-bit optical vector within the first two rows of the figure for a 10-bit time window at 20 Gb/s and 50 Gb/s operation, respectively, with the additional rows depicting the respective time sequences obtained at the Xbar column output port when the column stored content matches the designated target vector. The corresponding eye diagrams for every time sequence are shown in Fig. 3b and d, respectively. For all cases, the cross-shaped scatter points indicate the optimum sampling points, corresponding to one of the three possible output states of the HD operation i.e. HD=0 (ML operation), HD=1, and HD=2. Particularly, the green highlighted area showcases the principle of operation for a search vector value of ‘01’, that corresponds to Bit1 and Bit2 values of ‘0’ and ‘1’, respectively. A logical “match” state occurs, only when compared with the target vectors of “01”, “0X”, “X1” and “XX”. As expected, this results in a “zero” output power (HD=0), since the wildcard value “X” represents a “don’t care state” leading to a logical “match” regardless of the corresponding search value. On the other hand, if the compared vectors have different values, the comparison operation indicates a logical “mismatch”, resulting in an HD > 0. Specifically, if only one of the two search bits matches the content of the Xbar array, the HD is “1” (HD=1). Conversely, if none of the search bits match the array values, the HD is “2” (HD=2), as illustrated in the case of the “10” case time trace.

The performance of the 4×4 vector processor was assessed by calculating the projected symbol error rate (SER), when HD calculation is targeted, and the match error rate (MER) when optical CAM operation is intended, for each different target vector case. The SER quantifies the HD performance, while the MER specifically refers to the error rate of the ‘0’ level that corresponds solely to the matching functionality without accounting for the degree of mismatch (for more details see Supplementary Material Section 3). Figure 3e, f illustrates the calculated MER and SER when the Xbar HD processor operates at 20 Gb/s and 50 Gb/s, respectively. As can be observed, all error-rates are in the order of 10−3, comparable with the performance achieved by multi-symbol electronic HD and CAM computing cells35–37. The results indicate a degradation in both SER/MER measurements as the data rate increases, primarily due to noise arising from the limited frequency response of the deployed electro-optic components. Finally, it is worth mentioning that when the wildcard ‘X’ is included, the output signals are restricted to two levels and MER becomes equivalent to SER, resulting at the same time in improved performance compared to 3-level signals.

WDM-enabled comparison cell architecture for scalable hamming distance processor layouts
In the previous section, we validated the capabilities of the coherent Xbar architecture in performing HD operations between vectors by leveraging spatially distributed comparison cells and the interference properties of a single coherent light beam. Synergizing the WDM capabilities of the Xbar architecture38,39, with the HD architectural approach, can offer an additional axis of computational capacity at a reduced insertion loss budget (for more information see Supplementary Material Section 4), thereby enhanced energy efficiency. Figure 4a illustrates the proposed WDM-enabled comparison cell. The actual and complementary search vector symbol (Bit and Bit) are used to modulate two multi-wavelength light beams. The resulting modulated streams are demultiplexed to their wavelength constituents via a demultiplexer40, with each wavelength propagating through an intensity modulator (IM) that encodes a value from the target vector. The resulting signals are subsequently multiplexed and coherently recombined on a wavelength basis via constructive interference, achieved using TOPSs. Finally, the output is demultiplexed, with each wavelength carrying the dot-product between the assigned symbol and the search bit value. Further information about the functionality of the WDM-based cell is presented in Supplementary Material Section 1. This WDM-enabled comparison cell facilitates the parallel execution of HD operations within a single output, where the number of wavelengths represents the level of parallelism. In order to validate the advantages of the WDM-enabled approach a 3λ−2×1 comparison cell was fabricated using the same technological building blocks (i.e. EAM and TO-PS) as in the 4×4 Xbar. A microscope photo of the fabricated chip is depicted in Fig. 4b, while the circuit schematic of the WDM-enabled chip along with the experimental setup used to assess its performance in executing HD operations are presented in Fig. 4c. Additional information about the experimental testbed of the WDM-enabled HD chip can be found in the methods section. It is worth noting that our photonic integrated chip incorporates (de)multiplexers originally designed to support 4 different wavelengths. However, due to fabrication issues, only 3 wavelength channels were fully functional, while the fourth exhibited significant insertion losses. Therefore, we successfully demonstrated parallel operation of 3 wavelengths at up to 50 Gbps.

The experimental validation of the proposed WDM-enabled HD processor was conducted at data rates of 20 and 50 Gb/s, employing 3 different wavelengths. Figure 5a depicts indicative 10-bit long time traces at 20 Gb/s operation for the search Bit and Bit values encoded in all three wavelengths (λ1, λ2 and λ3) and the target Values ‘0’, ‘1’ and ‘X’ indicatively encoded at wavelengths (λ1, λ2 and λ3) respectively. Figure 5b illustrates their respective eye diagrams. The green highlighted area focuses on the case of the search value of logical “0”, meaning the Bit value is “0” and the Bit is “1”. As observed, when the search value is compared with the target symbol “0”, the HD circuit output is zero (HD=0), meaning that logical “match” state is acquired. Conversely, when the target symbol is “1”, the HD=1 indicating a “mismatch”. For TCAM operation, when the target symbol is the wildcard “X”, the output power remains always at zero level, signifying a match with any incoming search value. Similarly, Fig. 5c, d present the respective time traces and eye diagrams, when the WDM-enabled processor operates at 50 Gb/s, revealing successful HD/TCAM functionality. In view of evaluating the performance at 20 and 50 Gb/s, Fig. 5e, f depict the acquired Q factor values for both the actual and supplementary input (Bit and Bit) along with the results when targets ‘1’ and ‘0’ are sequentially encoded to different available wavelength cells. Similarly to the single-λ 4×4 Xbar layout, the 50 Gb/s cases exhibit a performance degradation compared to the 20 Gb/s, stemming from the bandwidth limitation of the deployed electro-optic components.

Discussion
Following the experimental validation of photonic Xbar-based CAM and HD implementations at up to 50 Gb/s and 3λ parallel layouts, we proceed by developing an analytical framework capable of: (i) assessing the theoretical error rate performance of Xbar-based HD and CAM-layouts for different scales, operational rates and injected laser powers (ii) quantifying the required single-λ laser power for different HD, CAM and WDM HD and CAM scales and operational rates and (iii) projecting the achieved energy efficiency of the different targeted HD and CAM single-λ and WDM layouts. A detailed breakdown of the opto-electronic noise sources and different properties of the constituent photonic and electronic components incorporated in the analytical framework can be found in Supplementary Material Section 3.

Figure 6a indicatively showcases the simulation framework’s projected error rates vs input laser power for HD and CAM operation, when targeting a single-λ 32×32 Xbar based layout, equivalent to a search word bit length of 16 (N/2) and a stored word capacity of 32 (N). The simulation results highlight: (a) the increased input laser power requirement when targeting high-rate operations, originating from the increased noise-bandwidth and as such noise profile of the photonic layout (b) decreased input laser power requirements when targeting CAM-only operations i.e. the specific case of HD=0. This decrease is attributed to the binomial statistical distribution of the power levels arising at the output of the HD photonic processor, originating from the actual and complementary nature of the input representation and the analog XOR operation between the input and target vector. (c) A different error-rate response when CAM-only operations are targeted, as highlighted by the black rectangle in Fig. 6a. This is due to the fact that the noise percentage characterizing the error-rate response of each signal level decreases more slowly, from the highest to the lowest power signal level, as the laser power increases. Additionally, since each signal level is associated with unequal probabilities of occurrence at the output of the system, this effect is reflected in the corresponding graphs (detailed correlation is described in Supplementary Section 3). By setting an operational threshold comparable to the performance of state-of-the-art electronic CAM implementations (i.e. Error Rate of 10−3)35–37, we can derive the required single-λ input laser power for different scales and operational rates.

Figure 6b illustrates the required single-λ and 4-λ laser power for the HD, CAM architectures when targeting Xbar layouts with a search word bit length in the range of [2–64] and a stored word capacity range of [4–128]. These layouts correspond to Xbar scales of 4×4 to 128×128 for the single λ case, and 4×1 to 128×32 for the 4-λ case, as the 4λ WDM design effectively acts as a capacity enhancement factor of λ=4. The derived results showcase that WDM layouts, using 4λ, for both CAM and HD designs, can offer significant insertion loss benefits as compared to the single-λ case (for more details see Supplementary Section 4), that can reach up to 20 dB when targeting 64-bit long search word and 128 stored word capacity for CAM operation at 20 Gb/s. Taking into account, that the currently maximum achievable power of an integrated laser source reaches ~22 dBm41, the analysis also reveal that WDM designs can also significantly extend the currently achievable CAM designs to up to 64-bit long search words. Finally, Fig. 6c puts in juxtaposition the achieved energy efficiency of single-λ and WDM CAM and HD layouts, taking into account the consumption of the constituent electro-optical components and the increased number of laser sources required for WDM layouts (For details see Supplementary Section 4). In Xbar scales where the required laser power surpasses the current practical limit i.e. >22 dBm, energy efficiency deteriorates because the total power consumption increases substantially and gets dominated by the laser’s power requirements. The results also showcase the power consumption reduction properties of WDM layouts, that get even more significant as the targeted scale increases. This highlights the capabilities of photonic WDM CAM layouts to achieve down to 400 fJ/bit and 200 fJ/bit energy efficiencies, while reaching operating speeds of 20 Gb/s and 50 Gb/s, up to 20 times higher than state-of-the-art electronic counterparts2,42–44.

Methods
Experimental setup of single-wavelength 4×4 crossbar-based hamming distance processor
A tunable laser source (Santec TSL550) is employed to generate a CW signal at the wavelength of 1563 nm. The operational wavelength has been appropriately selected to comply with the response of the grating couplers (GCs) and the EAMs, providing an optimal extinction ratio (ER), as well as insertion losses (ILs). The optical signal, is propagated into the 4×4 Χbar-based comparison structure within the PIC through an angled multi-port fiber array unit, retaining a constant TE polarization mode. The GCs of the integrated structure were found to have an IL of around 3.5 dB, which is independent from the Xbar scale. After entering the structure, the signal is split (1×4 splitting stage) and gets injected into the four-search word vector EAMs, with an electro-optical (EO) bandwidth of 56 GHz. Each EAM is driven by a waveform generator (AWG Keysight M8194A), generating non-return-to-zero (NRZ) pseudo random bit sequences (PRBS7) at 50 Gb/s, in order to emulate the incoming search vector information cases. The AWG generates the electrical signals with the channels having a power raging between [270–380 mV], for all the different cases of the 20 and 50 Gb/s, which were further amplified using RF amplifiers (SHF S804B), reaching the required ~1.9 Vpp to drive the EAM modules. A pair of EAMs was exploited to encode the information of a single search bit as a pair of complementary data, and as such the first pair of EAMs imprints the Bit1 and Bit1, while the second pair the Bit2 and Bit2 values. The encoded search bits of the second EAM pair were time-shifted during the electrical signal generation stage relative to the first EAM pair, enabling the acquisition of all possible 2-bit combinations. The search vector values are propagated into the device, where the EAMs of the array are statically assigned to encode all the different binary and ternary vector values, being configured with the use of a multi-channel DC control plane. The DC plane incorporates 8 different programmable 2-channel DC power supplies (Rigol DP831 LXI) that apply the necessary voltage values to every EAM module. Additional information about the specific driving voltage values can be found in the Supplementary Section 1 of the Supplementary Material. Each optical signal at every Xbar output column, representing the logical comparison between the incoming search and statically assigned vectors, exits the optical chip via the same fiber array. It is then amplified by an EDFA, filtered through an optical band-pass filter (OBPF) with a 0.8 nm bandwidth, and directed to a 70 GHz photodiode (Finisar XPDV3120) before being recorded by a 75 GHz sampling oscilloscope (Keysight DCA-X N1000A). Moreover, the EAMs that were responsible for the generation of the search vector values have been reversely biased at voltages ranging between [−1.6, −1.4 V] for 20 Gb/s, while the biasing values were ranging between [−1.6, −1.3] for the 50 Gb/s cases. In both operational cases the EAMs of the comparison cells were biased with either 0 or −4 V. Furthermore, a 4th-order butterworth software-based filter was implemented via the OSC module and applied to the captured signals, with a manually adjusted 3 dB bandwidth for the 20 and 50 GHz, respectively, in order to mitigate the excess noise bandwidth response of the transmitting channel. Pattern correlation and error rate calculations were performed off-line.

Experimental setup of WDM comparison cell
Three TLSs are deployed to generate three CW signal beams at the wavelengths of, λ1=1548.4 nm, λ2=1558 nm and λ3=1554.9 nm. The three signals are then multiplexed via a multiplexer (Mux) module (details about the design of (de)mux are given in Supplementary Material Section 2), creating a WDM stream. The combined signal stream is amplified by an EDFA prior entering the chip, through an angled multi-fiber array. A constant TE mode is ensured for the signals upon entering to the respective GCs, via in-line polarization controllers during CW signal generation. The GCs are calculated to have ~4 dB of ILs. Within the optical chip, the WDM signal is split and directed to two input EAMs of the SVEU, each with an EO bandwidth of 56 GHz. Each input EAM was driven by an AWG (Keysight M8194A) to generate, as in the single wavelength case, 50 Gb/s PRBS7 data sequences for the Bit and Bit complementary search value information. The generated electrical signals have amplitudes ranging between [260–370 mV], at the 20 Gb/s and 50 Gb/s cases, being amplified by RF amplifiers (SHF S804B), reaching the necessary voltage of ~1.9 Vpp to drive the EAMs. After the optical generation of the Bit and Bit signals, the WDM stream is propagated to the De-Mux components of each arm of the “outer” MZI structure. Every branch contains a demultiplexer (De-Mux1 and De-Mux2), which filters the incoming WDM stream up to three different paths, each containing a statically configured EAM and a PS, driven by the same DC control plane mentioned above (single-wavelength 4×4 Xbar-based HD processor). All possible combinations between the wavelengths (λ1=1548.4 nm, λ2=1558 nm, λ3=1554.9 nm) and symbol values (“0”, “1”, “X”) have been investigated. The optical signals are then multiplexed by the corresponding multiplexers (Mux1 and Mux2) and the two recombined WDM streams are constructively interfered before exiting the Xbar through a single output port. The output of the photonic crossbar is filtered to each wavelength-constituent and was amplified via an EDFA, followed by a BPF with 0.8 nm bandwidth prior entering a 70 GHz PD (Finisar XPDV3120) and being recorded by a 75 GHz OSC (Keysight DCA-X N1000A). Additionally, the EAMs used for the search bit’s information have been reversely biased at voltages between [−1.5, −1.2 V] for all the cases of the 20 and 50 Gb/s, while the EAMs that were used for the statically configured cells have been biased at 0 or −3 V. As before, a software-based 4th-order butterworth filter is implemented and applied via the OSC upon receiving the signals, with manually adjusting a 3 dB bandwidth of 20 or 50 GHz in order to mitigate the excess noise response of the PD. Pattern correlation and Q-factor calculations were performed off-line.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This study marks the first time that nonlinear vector processing based on linear optical circuits has been realized in silicon\nphotonics, offering a novel technological approach for fields such as pattern matching and error correction, and has made\ncertain progress. Overall, this paper is highly innovative and holds promising applications in the field of photonic computing.\nHowever, there are some issues with the paper that require further improvement. It is recommended that the authors carefully\naddress the following issues in the revised manuscript and make major revisions to the content of the paper.\n1. The paper claims this is the first time nonlinear vector processing has been achieved in silicon photonics, but a 2023\nstudy in Nanophotonics [27] also explored a similar direction. Could you further compare the differences between the\nmethods in this paper and those in references [27-28], especially regarding the error rates of ~10⁻³ for HD calculations and\nCAM operations at 50 Gb/s achieved in this paper, and how they differ from the performance in references [27-28]?\n2. The experiment used a 4×4 crossbar structure, but the theoretical simulation part was extended to a 32×32 scale. The\npaper mentions an insertion loss of about 3.5 dB. Has the change in insertion loss and crosstalk in larger-scale structures\n(such as 32×32) been evaluated?\n3. The paper mentions the use of a 56 GHz SiGe EAM but does not explain why this parameter was chosen. Is the 56 GHz\nbandwidth crucial for 50 Gb/s operation, especially considering the error rate of ~10⁻³ observed in the experiments in this\npaper? Have the performance of other modulators (such as MRR) been considered for comparison?\n4. In Figure 3, the eye diagram opening at 50 Gb/s is significantly smaller than that at 20 Gb/s. The paper states this is\nmainly due to the bandwidth limitations of the electro-optical components. Has the specific impact of noise sources (such as\nthermal noise and crosstalk) on the bit error rate been quantitatively analyzed?\n5. The paper mentions that the error rate of ~10⁻³ is comparable to that of electronic devices [31-33], but it does not clearly\nstate the specific advantages of the photonic scheme in terms of power consumption and delay. Could you supplement the\nenergy efficiency comparison data with electronic CAMs, especially regarding the energy efficiency of 400 fJ/bit and 200\nfJ/bit achieved by the WDM layout mentioned in this paper, and what are the specific advantages compared to the pJ/bit of\nelectronic devices?\n6. The WDM scheme increases capacity through wavelength multiplexing, but the experiment only verified the performance\nof 3 wavelengths in parallel. How is the performance of the 3-wavelength parallel operation mentioned in the paper? Has the\nperformance with more wavelengths (such as 4λ or 8λ) been tested, especially the impact of multi-wavelength crosstalk on\nmatching accuracy?\n7. In the current WDM scheme, the lasers and multiplexing/demultiplexing modules have not yet been fully integrated into\nthe on-chip system. How is the performance of the 3-wavelength parallel operation mentioned in the paper? If full integration\nis achieved in the future, thermal drift may cause wavelength misalignment. Are there plans to introduce temperature control\nsolutions (such as on-chip thermal phase shifters) or dynamic wavelength calibration technologies (such as feedback control\ncircuits) to mitigate thermal stability", "reviewer_2": "In this work, the authors demonstrated high-speed Hamming distance (HD) calculations and content addressable memory\n(CAM) bank operations using linear silicon photonic circuits. The first silicon photonic circuit was initially developed for\noptical matrix multiplications and reported in their previous work [Ref. 4]. The second circuit uses wavelength-division\nmultiplexing (WDM) to enable parallel processing, which also originates from their previous works [Refs. 34 & 35]. The use\nof these linear photonic circuits for HD calculations and CAM operations is novel. However, the potential impact of\nperforming these operations in the optical domain is not very clear, given the additional complexity introduced by the\nphotonic circuits. Before I can make a recommendation, the authors should consider the following concerns and comments.\nMajor concerns:\n1. The silicon photonic circuits in this work were initially developed for matrix multiplications, which have significant\napplications in optical neural networks. However, in this manuscript, the authors focus on HD calculations and CAM bank\noperations, which, while important for specific applications such as pattern matching, may not have the same broad\ntechnological impact. The scope of these operations is relatively narrow compared to the extensive influence of matrix\nmultiplications in neural network accelerators. As a result, the work may not achieve the level of general interest expected for\npublication in a high-impact journal such as Nature Communications.\n2. A comprehensive comparison between the demonstrated photonic circuits and previous digital and analog electronic\ncircuits is lacking. The authors claim that their photonic circuit outperforms “state-of-the art CAM speed performance by >\n2.5×.” However, this evaluation focuses solely on speed and does not consider other critical metrics. Factors such as chip\nsize, system complexity, and overall energy efficiency are equally important when assessing the practicality of a hardware\narchitecture. Without addressing these aspects, it is difficult to fully understand the trade-offs involved in using photonic\ncircuits for these operations. In particular, the scalability of this scheme could be an issue. To process an N-bit binary vector,\nthis scheme requires 2N modulators to generate the actual and complementary values. This can significantly limit the\nscalability of this scheme in terms of chip size.\n3. The operation principle in Fig. 1(d) is not clearly explained. The authors mentioned “…adding coherently the resulting\noptical fields”. However, Fig. 1(d) only depicts intensity modulators. Does the right part of Fig. 1(d) represent a cascade\nstage of 1-by-2 optical splitters? Phase shifters are necessary for coherent light summation, which are not shown in this\nfigure. While the supplementary material does provide more details on the operation principle, it should be sufficiently clear\nwithin the main text and figures.\n4. What is the extinction ratio of the SiGe electro-absorption modulator (EAM)? Could an improvement in the extinction ratio\nfurther reduce the error rates in Figs. 3(e-f)?\n5. Page 4, line 116. Please provide more details on the multi-channel DC control plane.\nMinor comments:\n6. The current title may be too broad. “Nonlinear optical vector processing” does not accurately summarize the HD\ncalculations and CAM bank operations.\n7. The authors should try to use high-resolution images of their circuits. The current images have poor resolutions,\nparticularly in Fig.2(a) and Fig. 4(b). No effective information is available from the current figures.\n8. Page 1, line 21. Please provide the definition of “WDM”.\n9. Page 4, line 123. Please provide the definition of “ML”.\n10. Please use the correct multiplication sign “×” instead of the letter “x” throughout the manuscript.", "reviewer_3": "The manuscript presents a novel approach to nonlinear optical vector processing using linear SiPho circuits, achieving 50\nGb/s Hamming Distance (HD) and CAM operations. However, several limitations in experimental validation, scalability\nanalysis, and technical comparisons need addressing to strengthen the claims and ensure reproducibility. I will suggest a\ncomment of Major Revision.\n---\n1. Expand experimental validation to larger-scale architectures.\nTo conduct small-scale extended tests (e.g., 8×8 or 16x16 X-bar) to verify theoretical scalability models. To discuss\nmanufacturing challenges (e.g., crosstalk, cumulative losses) for large-scale integration.\n2. Enhance error rate analysis with noise source quantification and energy efficiency measurements.\nTo quantify or evaluate the contributions of thermal noise, crosstalk, and nonlinear effects to SER/MER. To provide\nmeasured energy efficiency data (including laser and driver circuitry) for WDM vs. single-λ designs. It seems that the energy\nefficiency has not consider the optical-electrical conversion power.\n3. Update technical comparisons with state-of-the-art electronic CAM/TCAM benchmarks.\nTo compare against recent CMOS advancements (e.g., 5nm-node TCAMs) in speed, power, and area efficiency.\n4. Clarify WDM engineering challenges and mitigation strategies.\nTo detail wavelength stabilization methods and difficualty (e.g., thermal feedback loops) to counter temperature drift. What is\nthe inter-channel crosstalk suppression (e.g., optimized filter bandwidths, guard bands)?"}, "author_response": "Aristotle University of Thessaloniki\nDepartment of Informatics\n54124 Thessaloniki, Greece\nTel: +30 2310 990588\nE-mail moschost@csd.auth.gr\n5th July 2025\nDear Reviewers,\nWe would like to thank the reviewers for their prompt reply and constructive criticism on\naddressing the respective comments, regarding our submitted manuscript in Nature Communications,\nentitled “Nonlinear Optical Vector Processing using Linear Silicon Photonic Circuits for 50 Gb/s\nMemory and String Similarity functions”, since we have modified the manuscript’s title based on one\nthe reviewer’s consideration, by T. Moschos, C. Pappas, S. Kovaios, I. Roumpos, A. Prapas, A. Tsakyridis,\nM. Moralis-Pegios, C. Vagionas, Y. London, B. Tossoun, T. Van Vaerenbergh and N. Pleros.\nWith this reply letter you can find attached our respective changes and our thorough replies to the\ncomments provided, along with the respective changes in the overall manuscript material.\nWe hope that these changes will meet the appropriate requirements and will cover the concerns of\nthe reviewers and thus lead to the consideration of our work being published in the specific scientific\njournal.\nBest regards,\nTheodoros Moschos\nDepartment of Informatics\nAristotle University of Thessaloniki\nRevisions on the scientific journal of Nature Communications for the submitted manuscript of\n“Nonlinear Optical Vector Processing at 50Gb/s using Linear Silicon Photonic Circuits”-\nNCOMMS-25-11055-T\nReviewer #1\nThis study marks the first time that nonlinear vector processing based on linear optical circuits has been\nrealized in silicon photonics, offering a novel technological approach for fields such as pattern matching\nand error correction, and has made certain progress. Overall, this paper is highly innovative and holds\npromising applications in the field of photonic computing. However, there are some issues with the paper\nthat require further improvement. It is recommended that the authors carefully address the following\nissues in the revised manuscript and make major revisions to the content of the paper.\nComment #1:\nThe paper claims this is the first time nonlinear vector processing has been achieved in silicon photonics,\nbut a 2023 study in Nanophotonics [27] also explored a similar direction. Could you further compare the\ndifferences between the methods in this paper and those in references [27-28], especially regarding the\nerror rates of ~10⁻³ for HD calculations and CAM operations at 50 Gb/s achieved in this paper, and how\nthey differ from the performance in references [27-28]?\nReply:\nWe would like to thank the reviewer for his/her kind remarks and the constructive comments. In\nresponse to the first comment, we would first like to clarify the differences between our current work and\nthe studies cited in references [27] and [28] of the main manuscript.\n• Reference [27] proposes and analyzes WDM and TDM optical TCAM architectures using silicon\nphotonic microring resonators as the primary comparison units, presenting:\no Just simulation studies for 10Gb/s search operations\no and experimental validation at an operational rate of only 4 Gbps.\n• Reference [28] presents the first experimental demonstration of a 20 Gbps optical TCAM cell using a\ncrossbar configuration that utilizes solely the space dimension.\nThe current work extends well beyond the previous demonstrations along the following items:\na) It demonstrates, for the first time, a complete 2-symbol optical word comparison, while references\n[27] and [28] demonstrated only single-cell and single-symbol search operations.\nb) It performs at a record-high operational speed of 50 Gbps, i.e. 12.5x faster than the search speed\nreported for microring-based WDM and TDM optical TCAMs reported in [27], and 2.5x faster than the\nsingle TCAM cell in [28]. To the best of our knowledge, this represents the highest reported data rate\nfor optical CAMs and Hamming distance comparison operations to date.\nc) It introduces a new architectural scheme that combines both spatial and wavelength dimensions,\nproviding a highly efficient layout for scaling to multi-bit demonstrations.\nd) It goes beyond conventional CAM cell operation reported in [27] and [28] and addresses two different\nnon-linear computing processes, i.e. Hamming distance and ‘CAM Match-line’. We also\nincorporate an analytical framework to efficiently compute both the match-error rate (MER) and the\nsymbol-error rate (SER) for: (i) the experimentally obtained data, and (ii) a theoretical model of larger-\nscale crossbar architectures. This model accounts for the noise characteristics associated with multi-\nlevel signal scenarios, as thoroughly detailed in the supplementary material. This extended error-rate\nanalysis, along with the use of multiple signal metrics, introduces a new signal processing perspective\nwithin our 2-symbol, 4×4 comparison unit—something not addressed in the previous demonstrations\nof [27] and [28]. The analysis distinguishes between the two error types based on the intended\nevaluation objective: The calculation of MER quantifies the likelihood of failure in detecting a Match-\nLine event, where the input search vector is identical to the stored content (i.e., Hamming distance =\n0). The focus here is on accurately distinguishing the ‘0’-signal power level from the noise levels of all\nother signal states. The calculation of the SER, on the other hand, evaluates the system’s ability to\nresolve various multi-level signals that arise from differing degrees of mismatch between vectors. It\nconsiders the aggregate noise impact across all signal levels, yielding a comprehensive measure of\nsignal integrity. Compared to the referenced works, the present study introduces a more accurate and\nnuanced error model that incorporates: (i) the binomial distribution behavior of the XOR operation at\nthe comparison output, (ii) noise-dependent variability across the signal levels, and (iii) the architectural\nimplications of scaling the crossbar to higher dimensions.\ne) Finally, our work establishes an error rate threshold of 10⁻³, which is well-aligned with the standards\nemployed in multi-bit electronic HD and CAM computing cells [1]-[3]. The authors in references [27]\nand [28] demonstrated 1-bit comparison operations, achieving error rates in the range of [10⁻⁵ - 10⁻¹²]\ncomparable to those achieved in our WDM-based scenario, where 1-bit comparison is also targeted.\nIn order to make these differences clearer and complying with the reviewer’s comment, we introduce the\nfollowing changes in our manuscript:\nChanges in the text:\nIn the “Results” section in page 4 in line 103, we have added the following:\n“….The functionality of the proposed analog photonic HD processor architecture was assessed via a 4×4\nSiPho integrated Xbar layout that is capable of 2-bit vector distance processing, surpassing prior optical\nCAM implementations [27] [28], which have demonstrated only 1-bit comparison operations”\nIn the “Results” section in page 6 in line 153, we have added the following:\n“…As can be observed, all error-rates are in the order of 10-3, comparable with the performance achieved\nby multi-symbol electronic HD and CAM computing cells”\nComment #2:\nThe experiment used a 4×4 crossbar structure, but the theoretical simulation part was extended to a 32×32\nscale. The paper mentions an insertion loss of about 3.5 dB. Has the change in insertion loss and crosstalk\nin larger-scale structures (such as 32×32) been evaluated?\nReply:\nThere is probably a\nmisunderstanding regarding the 3.5 dB\nloss. As is explicitly stated in Section\nmethods, first paragraph, line 240 (“The\nGCs of the integrated structure were\nfound to have an IL of around 3.5 dB”),\nthis value refers to the losses of a\nstandalone grating coupler, which does\nnot relate to the Xbar scale. The insertion\nloss for various Xbar scales was\ncalculated using the theoretical\nframework, thoroughly analyzed in [4],\nas also mentioned in section 3 of the\nsupplementary material. Therefore, we\nhave already evaluated the insertion loss\nevolution in higher scale crossbar Figure 1: Average dot product error, induced by the crosstalk of waveguide\ncrossings for various Xbar scales.\nstructures.\nTo address the reviewer’s comment, we should also take into account the crosstalk induced by the\nwaveguide crossings of the current architecture. Considering the deployment of waveguide crossings\npresented in the work of reference [5], that demonstrated -55 dB of crosstalk, we performed a simulation\nanalysis, based on this specific performance metric. For the theoretical model we used a Monte Carlo\nanalysis to evaluate the impact of crosstalk and scaling on the performance of our architecture. The study\ninvolves varying the size of a square crossbar array, across values of N = [4, 8, 16, 32, 64, 128], while\nmaintaining a fixed crosstalk level of -55 dB. For each crossbar scale, the simulation conducts 100 trials to\ncompute the dot product between the search and target vectors, both initialized with discrete binary values.\nThe dot products are calculated under two conditions: (i) an ideal scenario and (ii) a noisy scenario where\ncrosstalk-induced interference is introduced to the layout. In the case where noise is applied, the dot\nproducts are derived by applying a crosstalk factor, corresponding to the -55 dB and additionally, random\nphase shifts ranging from [0-2pi] are considered for the incoming search vector’s signals. Following this,\nthe average error between the ideal and noisy dot products is then calculated. Figure 1 illustrates the\nsimulation results showing the average dot product error, induced by the waveguide crosstalk, for different\ncrossbar scales. As shown, the performance degradation due to crosstalk remains negligible even for\ncrossbar scales as high as 128x128, reaching only ~8×10−3 %, showcasing that this specific crosstalk\nparameter does not limit the scalability of the architecture.\nChanges in the text: In methods section, page 9, line 246, we have added the following:\n“The GCs of the integrated structure were found to have an IL of around 3.5 dB, which is independent from\nthe Xbar scale”.\nIn supplementary material, we have added a section “Crosstalk and Extinction Ratio analysis”, where the\ncrossings-induced crosstalk is investigated.\nComment #3:\nThe paper mentions the use of a 56 GHz SiGe EAM but does not explain why this parameter was chosen.\nIs the 56 GHz bandwidth crucial for 50 Gb/s operation, especially considering the error rate of ~10⁻³\nobserved in the experiments in this paper? Have the performance of other modulators (such as MRR) been\nconsidered for comparison?\nReply:\nThe deployed SiPho chip was\nfabricated on imec’s ISIPP50G\nplatform using PDK (process design\nkit)-ready components. Therefore, the\nintentionally chosen, but rather\ninherited from the platform’s standard\nEAM design. While this high\nbandwidth offers advantages for high-\nspeed modulation, it is not essential for\nbandwidth of the deployed electro-\noptic link in our case is mainly\ndetermined by the digital-to-analog\nconverter (DAC), which has an analog\nFigure 2: Projected error rates for a 4x4 Xbar implementation at 50 Gb/s CAM\nbandwidth of 45 GHz, the lowest and HD operation under different search vector’s ER conditions. An ER of 6 dB\namong all system components. corresponds to microring modulators, while ER ≥10 dB corresponds to Mach-\nNevertheless, despite this bandwidth Zehnder modulators.\nvalue is lower than the targeted operational rate, our experimental measurements reveal that 50Gb/s\nperformance could still be successfully obtained in the case of NRZ data signal modulation, as shown by\nFig. 3(d) and (f) in the main manuscript. Figure 3 (d) illustrates in its first two rows the eye diagrams\nacquired during 50 Gb/s NRZ modulation of respective EAMs to produce the two bits of the search vector\n(Bit and Bit ), showing clearly eye openings. Moreover, the error-rate for these two signals is <10-9, as\n1 2\nshown in Fig. 3(f), clearly indicating error-free operation.\nThe ~10-3 error-rate is observed only during HD calculation and CAM operation, where 3-level\ninstead of binary signals are obtained at the output of each Xbar column. One of the main sources of error-\nrate degradation in this case is the limited extinction ratio (ER) of the search-vector-encoding EAMs. These\nEAMs operate at GHz regime exhibiting an ER of ~3 dB, while the EAMs responsible for CAM table\nencoding operate in a static dc regime and have a sufficiently high ER of ~8 dB. However, the resulting 3-\nlevel signal will be bounded by the maximum and minimum power levels of the search-vector bits, implying\nthat now 3 different power levels have to be accommodated within an ER of 3dB between the maximum\nand minimum power level. To assess the impact of the search vector’s ER on the error rate, we performed\na simulation analysis projecting the error rates of a 4x4 Xbar as a function of the received average power\nfor 50 Gb/s HD and CAM operation under different ER conditions. Figure 2 depicts the simulation results,\nclearly highlighting that higher ER values reduce the receiver’s sensitivity requirements. This suggests that\nadopting a different modulator technology for search vector encoding could enhance overall system\nperformance. For example, microring resonators (MRRs) typically exhibit ER values of 6 dB [6], which,\naccording to Figure 2, corresponds to a 37% reduction in the receiver’s required power to achieve an error\nrate of 10-3. A further reduction of over 50% can be achieved by employing Mach-Zehnder Modulators\n(MZMs) for search-vector-encoding, which can yield ER values of ≥10 dB [7]. However, each modulator\ntechnology introduces distinct requirements and limitations. For instance, MRRs are sensitive to\ntemperature variations, while MZMs significantly increase the footprint. These trade-offs should be\ncarefully evaluated when designing a fully integrated system in order to apply the proper mitigation\nstrategies and finally ensure optimal performance.\nChanges in the text: In supplementary material, we have added a section “Crosstalk and Extinction Ratio analysis”, where the ER limitation is investigated.\nComment #4:\nIn Figure 3, the eye diagram opening at 50 Gb/s is significantly smaller than that at 20 Gb/s. The paper\nstates this is mainly due to the bandwidth limitations of the electro-optical components. Has the specific\nimpact of noise sources (such as thermal noise and crosstalk) on the bit error rate been quantitatively\nanalysed?\nReply:\nWe would like to thank the Reviewer for his/her comment. To begin with, we would like to refer the\nReviewer to comments #2 and #6, where a quantitative analysis of both coherent and in-coherent crosstalk\nwas performed, revealing negligible signal distortion. Considering the breakdown of the other noise sources\nand the relationship with the achieved BER, our approach is two-fold:\n• The simulations results presented in the discussion section of the manuscript, are derived from an\nin-house developed optical simulator, that considers shot, thermal and RIN noise as extensively\ndiscussed in Supplementary Section part 3.\n• A quantitative analysis of the noise contributions in the experimental results presented in Figure 3\nof the main manuscript follows.\nOur analysis begins by depicting in Figure 3, the optical eye-diagram analysis of the 20 Gbit/s NRZ signal.\nSpecifically, Fig. 3 (a) depicts the optical eye diagram, with the yellow, red and green lines corresponding\nto the crossing points, the 20%, 80% transitions, and the Y axis eye center, respectively. Figure 3 (b)\nillustrates the probability density plots at the 10% percentage boundary of the X-axis eye center for the two\nFigure 3: (a) Optical Eye Diagram of 20 Gbit/s NRZ signal (b) Horizontal histogram in the 10% boundary of the X-axis center (c)\nFitted gaussian distributions characteristics for binary zero and one levels.\nbinary levels. Fitting a gaussian distribution in each binary symbol class allows the calculation of the mean\nand standard deviation values of the noise profiles, with the respective results along with other eye-diagram\nmetric illustrated in Fig. 3 (c). Observation of the experimental data leads to some important conclusions:\n• The noise profiles at both binary levels follows a gaussian distribution.\n• As the noise profile of the ‘1’ binary level is significantly higher than the respective ‘0’ level, the\nexpected noise seems to be dominated by a receiver power dependent phenomenon, suggesting that\nthermal noise is not the highest noise contributor.\nTo quantify the contribution of the digital sampling scope thermal noise, we plot in Fig. 4, the\nprobability density plot of a scope measurement, when no input power is injected and a 20 GHz low-pass\nfilter is applied to the sampling scope signal. Fitting a gaussian distribution to the density plot reveals a\nstandard deviation of 0.33 mV, that as expected is significantly lower than the measured 0.58 and 1.1 mV\nstandard deviations at the zero and one binary levels respectively.\nHaving isolated the thermal noise contribution of the receiver, we experimentally replicated, using DC\nsignals, the opto-electronic component chain employed in our experiments. Specifically, a tunable laser\nsource tuned to the same wavelength as in the experiment, was attenuated to match the power level arising\nat the chip output (-27 dBm). Following the attenuated signal was injected into an EDFA amplifier, filtered\nin a 1 nm 3dB bandwidth optical filter and finally injected into a photodiode and sampled in the digital\nFigure 4: Probability density plot of the signal at the digital sampling scope, after a 20 GHz low pass filter.\noscilloscope. The injected power at the photodiode was tuned based on the mean values of the binary zero\nand one levels of the previously acquired eye diagram (i.e. 18.4 and 36.1 mV, respectively).\nFigure 5 (a) illustrates the experimental derived probability density plot for the DC measurements for both\nbinary levels 0 and 1. The respective plots are overlayed in Fig. 5 (b) with the optical eye diagram\nexperimental derived probability density plots, revealing perfect matching. As such, the increased noise\nprofiles at the optical eye diagram measurements, as compared to the scope’s thermal noise, is attributed to\nthe EDFA originating noise, with the largest contribution attributed to the beating of the EDFA’s ASE with\nthe signal power, resulting in a receiver power dependent noise profile [8].\nFigure 5 (a) Probability density plot of DC measurement of noise profile at binary level ‘0’ and ‘1’ at 20 Gb/s (b) Overlayed DC\nand RF noise profiles\nThe previous analysis is repeated for 50 Gb/s NRZ signals, with Fig. 6, 7 and 8 illustrating the\nthermal noise after a 50 GHz low pass filter, the optical eye diagram and respective metrics and the\noverlayed DC and RF density plots, respectively. It is evident that the noise profiles at 50 Gb/s operations\nis increased due to higher thermal and signal-to-ASE beating noise at 50 GHz. However, the overlayed\nplots showcase almost perfect matching, distorted only slightly at the ‘1’ binary level, due to the eye skew\noriginating from the limited frequency response.\nFigure 6: (a) Optical Eye Diagram of 50 Gbit/s NRZ signal (b) Horizontal histogram in the 10% boundary of the X-axis center\n(c) Fitted gaussian distributions characteristics for binary zero and one levels.\nFigure 7: Probability density plot of the signal at the digital sampling scope, after a 50 GHz low pass filter.\nFigure 8 (a) Probability density plot of DC measurement of noise profile at binary level ‘0’ and ‘1’ at 50 Gb/s(b) Overlayed DC\nand RF noise profiles.\nThis analysis leads to the following conclusions, considering the eye closure between 20 and 50 Gb/s\noperations\n• While the electro-optic frequency response is indeed limited, its effect on the eye opening is\nsignificantly minimized through a pre-emphasis procedure. However, the pre-emphasis procedure\nresults in a reduction in the achieved ER, from 2.9 dB to 2.1 dB, when transitioning from 20 to 50 Gb/s\noperation.\n• The increased noise profile at higher operating rates and as such operating bandwidths, is also a\nsignificant contributor in the reduction of the achieved eye opening.\nQuantifying these distortions (ER and increased noise profile) in terms of theoretically achieved Bit Error\nRate, can be performed through the use of the optical eye Q-factor :\n1\n𝑃 −𝑃 𝑃 −𝑃 /𝛦𝑅 1−\n1 0 1 1 𝐸𝑅\n𝑄 = = = 𝑃 ∗\n𝜎 +𝜎 𝜎 +𝜎 1 𝜎 +𝜎\n1 0 1 0 1 0\nWith P1, P0, σ1 and σ0 corresponding to the mean power levels and noise standard deviation of the signal\nat binary logic levels ‘1’ and ‘0’ respectively.\nChanges in the text: In supplementary material, we have added a section “Experimental noise analysis: Impact of different noise sources”, where the experimental noise is investigated.\nComment #5:\nThe paper mentions that the error rate of ~10⁻³ is comparable to that of electronic devices [31-33], but it\ndoes not clearly state the specific advantages of the photonic scheme in terms of power consumption and\ndelay. Could you supplement the energy efficiency comparison data with electronic CAMs, especially\nregarding the energy efficiency of 400 fJ/bit and 200 fJ/bit achieved by the WDM layout mentioned in\nthis paper, and what are the specific advantages compared to the pJ/bit of electronic devices?\nReply:\nTernary features used in vector comparisons, similarity matching as well as look-up tables require\ndeveloping hardware CAMs/TCAMs, that comprise two storage cells, one for the actual data-bit and one\nfor the ternary state. While TCAMs offer simplicity and high performance, they come at the cost of\nincreased power consumption and complex interconnect circuitry. This circuitry broadcasts input data\nacross all TCAM match-lines to enable fast parallel comparisons, with the final result collected at the\nTCAM table output as a single Matchline signal. The first practical integrated electronic CAM was\nintroduced by Koo in 1970 [9], yet emerged in the memory market in mid-90s and flourished after 2000,\nowing to the established Von-Neumann architectures, favouring enhanced search-performance and\nmemory-intensive operations when compared against conventional electronic RAMs. Since then, TCAMs\nfollowed a rapid progress as summarized in the Table 1 that benchmarks various electronics TCAMs\noptimized for high-performance at various CMOS nodes from 250 nm down to even 2nm.\n• Early T-CAMs targeted combining the performance of NOR gates with the power efficiency of\nNAND gates by activating only a few MLs using NAND cells and NOR cells for the rest, as e.g.\nthe device built on 250 nm CMOS node at 260 MHz [10]. Similarly, a T-CAM at a 180 nm CMOS\nnode achieved a maximum frequency of 210 MHz [11], while devices on 130 nm CMOS exhibited\nfJ/bit respectively.\n• When using CMOS lines of 65 nm, electronic T-CAMs achieved to deliver frequencies up to 500\nMHz, at an energy efficiency value of 0.2 fJ/bit and footprint of 3.98 μm2 per cell in 2015 (not\nsimultaneously at the same device) [13]-[15].\n• Although T-CAM developed at CMOS nodes between 32nm and 12nm achieved frequencies in the\norder of 1GHz to 1.5 GHz [16]-[21], the energy efficiency values were still not improved (values\n>0.2 fJ/bit are reported), resulting only in 4x increased footprint efficiency of 0.945 μm2 per cell.\nTable 1: State-of-the-art electronic T-CAMs\nCMOS Area/cell Energy/sear Freq.\nRef. Array size\nTechn. (nm) (μm2) ch/bit (fJ) (GHz)\n[9] 250 316.2 17.2 0.26 128×32\n[10] 180 53.2 2.82 0.21 128×144\n[12] 130 6.73 5.6 0.20 9.4 Mb\n[13] 65 - - 0.50 -\n[14] 65 6.53 0.2 0.13 32 Kbit\n[15] 65 3.98 0.6 0. 50 8 Kbit\nM\nA [16] 32 0.84 0.58 1.00 2048×640\nC\nT\nc\n[17] 28 0.6 - 0.40 20 Mbit\ni\nn\no [18] 28 0.304 0.74 0.37 32×64\nr\nt\nc\ne [19] 16 1.8 1.25 10 Kbit\nl\nE\n[20] 14 2.01 - 1.40 2K×640 bit\n[21] 12 0.945 - 1.50 10 Kbit\n[22] 7 0.248 - 1.60 640 Kbits\n[23] 5 0.287 - 2.00 512×220\n[24] 3 0.201 0.305 2.20 512×220\n[25] 2 0.024 0.120 - 128×128\nThis Work SiPho EAM 95,000 32 50 4×4\n• More recently, shifting to the most advanced CMOS nodes of lower than 7 nm [22]-[25], energy\nefficiency values were not significantly improved, revealing a plateau of around 0.12 fJ/bit, bounded by the nature of the underlying electrical interconnect.\nAll this analysis of the demonstrated electronic state-of-the-art architectures declares that electronic\nTCAMs have revealed energy efficiencies that can reach even sub-fJ/bit values. However, as shown they\nare struggling to advance their data-rate performance. Even in the cases of the most advanced electronic\nnano-sheet layers of NAND-gates at 2nm nodes, operational-speeds seem to be constrained to less than 2.2\nGHz, implying that electronic TCAMs are hard-limited within a few GHz and hence struggle to keep pace\nwith the rising line rates of optical systems, downgrading their overall performance.\nIn this context, photonic CAMs have emerged as a promising alternative computing circuitry, as\ndescribed also in the main manuscript. The presented 4x4 and WDM TCAM prototypes reveal a limitation\nin terms of footprint and energy capabilities being characterized by the trade-offs of the current photonic\nintegration, compared to the electronic state of the art works. In the experimental case of the 4x4 layout the\nrequired energy for a search operation is approximated to be ~32 fJ/bit, occupying an area of 0.095 mm2\n(included in the respective state-of-the-art table 1), with the WDM alternative requiring ~38 fJ/bit, with a\nrelatively higher footprint occupation, due to the multiplexer/demultiplexer modules required for the\nparallel WDM operation. However, the current prototypes deliver up to a 20x times speed enhancement in\nboth cases, over the electronic performance plateau. These speed credentials along with the utilization of\nthe space and wavelength dimensions show some promising computing capabilities.\nMoreover, in the case of the WDM implementation, our theoretical analysis highlights the\nadvantage of our SDM+WDM configuration when scaling to higher dimensional crossbar arrays, in terms\nof energy requirements. For higher scales such as 32-bit configuration and above the energy efficiency for\nthe HD operation remains below 800 fJ/bit in all cases, while the respective CAM operations reveals\nefficiency values of 400 fJ/bit and 200 fJ/bit respectively, for 20 Gb/s and 50 Gb/s. The WDM\nimplementation can potentially allow minimized laser consumption compared to the single λ layout when\nscaling to higher crossbar dimensions, showcasing promising energy efficiency characteristics. This\nanalysis shows that a possible scale-up approach for multi-comparison high speed operations can maintain\nreasonable footprint requirements and energy efficiency metrics. Detailed explanation about the laser\nconsumption reduction can be found in the Supplementary material Section 4.\nAddressing the delay aspect, based on the comment of the reviewer we assume that by “delay”\nhe/she refers to the latency time, required to perform a comparison operation in the given architecture. Our\nexperimental work is focused on the modulation operational rate and does not take into consideration any\nexplicit time delay measurements. It needs to be mentioned that photonic integrated circuits offer inherently\nlower delay metrics compared to their electronic counterparts, especially in the cases of interconnect-\ndominated and parallel-processing applications. In cases of dielectric media, such as silicon waveguides\nthat we utilise in our photonic circuits, light’s high group velocity, estimated to be ~ 2×108 m/s, reduces\nsignificantly the propagation time of the photonic signal, through the respective photonic circuits.\nAdditionally, the presented photonic architectures are characterised by passive, interference-based\ncomputation, without requiring sequential logic/switching circuits, that pose additional delay times in the\nrespective CMOS-based electronic schemes. As such the overall system delay in our approach is mostly\ndetermined by the optical path routing and coupling efficiencies, with the only limiting factor being the\nmodulator limitation characteristics, which in our case operates at the GHz regime. Hence, we can reach to\nthe conclusion that the signal delay in our photonic implementation can be estimated to be at the ps time\nregime, being comparable with the electronic alternatives.\nChanges in the text: The table with state-of-the-art electronic T-CAMs has been added to the section\n“State-of-the-art electronic CAM demonstrations” of the supplementary material.\nComment #6:\nThe WDM scheme increases capacity through wavelength multiplexing, but the experiment only verified\nthe performance of 3 wavelengths in parallel. How is the performance of the 3-wavelength parallel\noperation mentioned in the paper? Has the performance with more wavelengths (such as 4λ or 8λ) been\ntested, especially the impact of multi-wavelength crosstalk on matching accuracy?\nReply:\nThe performance of a 3-wavelength parallel operation has been experimentally verified in our\nimplementation and is thoroughly described in the main manuscript in the section: “WDM-Enabled\nComparison Cell Architecture for Scalable HD Processor Layouts”. The proposed WDM-enabled\ncomparison cell facilitates the parallel execution of HD operations within a single output, where the number\nof wavelengths represents the level of parallelism. Our photonic integrated chip incorporates\n(de)multiplexers originally designed to support 4 different wavelengths with a channel spacing of ~3 nm.\nHowever, due to fabrication issues, only 3 wavelength channels were fully functional, while the fourth\nexhibited significant insertion losses. Therefore, we successfully demonstrated parallel operation of 3\nwavelengths at up to 50 Gbps, with the experimental results summarized in Figure 5 of the main manuscript.\nWe agree with the reviewer’s concern that optical crosstalk might affect the performance of the WDM\ncrossbar layout, particularly as the number of wavelength channels increases and/or the channel isolation\nperformance of the underlying photonic components decreases. In order to quantify the effects of the optical\ncrosstalk in a k number of wavelength channels WDM-crossbar, we begin by depicting in Figure 9 (a) the\nequivalent circuit layout of a single column of the WDM layout. We also assume a crosstalk value of A dB\nand symmetric channel operation. Figure 9 (b) illustrates the optical power evolution of the\nmultiwavelength signals traversing the crossbar layout for each of the k wavelength channels. By denoting\nλ as the signal of interest and identifying all the other wavelength channels as crosstalk inducing\n1\naggressors, we conclude to the following:\n• Channel 1 crosstalk power:\n• 𝑃 = (𝑘−1)∗(𝑃 ∗3∗𝑀𝑈𝑋 ) (1)\n𝑥𝑡𝑎𝑙𝑘1 𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘\nwhere 𝑃 is the optical power for each wavelength channel at the input of the first De-MUX, while\n𝑖𝑛𝑝𝑢𝑡\n𝑀𝑈𝑋 is the isolation of each of the WDM components in linear form and the factor 3 indicates the\n𝑥𝑡𝑎𝑙𝑘\nchannel spacing.\n• Channel 2-k crosstalk power:\n𝑃 = (𝑃 ∗2∗𝑀𝑈𝑋 )+(𝑃 ∗𝑀𝑈𝑋 ) (2)\n𝑥𝑡𝑎𝑙𝑘2 𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘 𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘\n+ (𝑘−2)∗(𝑃 ∗3∗ 𝑀𝑈𝑋 ),\n𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘\nwith the first component being the intra-band crosstalk at λ , the second component originating from λ\n1 2(κ=2)\nand the (k-2) components corresponding to the crosstalk of all channels to the signal bearing signal.\nAdding up these contributions we conclude to:\n𝑃 =𝑃 +(𝒌−𝟏)∗𝑃 (3)\n𝑥𝑡𝑎𝑙𝑘 𝑥𝑡𝑎𝑙𝑘1 𝑥𝑡𝑎𝑙𝑘2\n(𝑘−1)∗(𝑃 −3∗𝑀𝑈𝑋 )+𝑘∗{(𝑃 −2∗𝑀𝑈𝑋 )+(𝑃 −𝑀𝑈𝑋 )+ (𝑘\n𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘 𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘 𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘\n−2)∗(𝑃 −3∗ 𝑀𝑈𝑋 )}.\n𝑖𝑛𝑝𝑢𝑡 𝑥𝑡𝑎𝑙𝑘\nFigure 9: (a) Equivalent circuit layout of a WMD-Xbar with k wavelength channels and (b) Schematic illustration of crosstalk\naggressors for single column operation.\nIt should be noted that typical SiPho MUX/DEMUX designs have significant crosstalk only on the\ncase of the adjacent channels, and as such the (k-1) factor on the 𝑃 can be reduced to 2.\n𝑥𝑡𝑎𝑙𝑘2\nFigure 10 (a) and (b) illustrate the relationship between crosstalk to signal power for different\nmultiplexer isolation (crosstalk) and wavelength configurations, taking into consideration the cases of\nadjacent and non-adjacent crosstalk contributions. Specifically, Figure 10 (a) and (b) illustrate the scenarios\nwhere crosstalk is symmetric across all channels and when only adjacent channels contribute to crosstalk\npower. As can be observed for the case of the adjacent channel crosstalk, a typical performance of -27 dB\nof crosstalk [26] results in a negligible crosstalk to signal power of 0.004 or 0.4 % and as such we conclude\nthat it would not have any significant effect on the error rates performance.\nChanges in the text:\nIn “Results” section, page 7, line 177, we have added the following:\n“It is worth noting that our photonic integrated chip incorporates (de)multiplexers originally designed to\nsupport 4 different wavelengths. However, due to fabrication issues, only 3 wavelength channels were fully\nFigure 10: Crosstalk to signal power (a) Assuming symmetric crosstalk performance across or multiplexer channels and (b)\nAssuming only adjacent channel crosstalk.\nfunctional, while the fourth exhibited significant insertion losses. Therefore, we successfully demonstrated\nparallel operation of 3 wavelengths at up to 50 Gbps”\nIn supplementary material, we have added a section “Crosstalk and Extinction Ratio analysis”, where the\nmux/demux-induced crosstalk is investigated.\nComment #7:\nIn the current WDM scheme, the lasers and multiplexing/demultiplexing modules have not yet been fully\nintegrated into the on-chip system. How is the performance of the 3-wavelength parallel operation\nmentioned in the paper? If full integration is achieved in the future, thermal drift may cause wavelength\nmisalignment. Are there plans to introduce temperature control solutions (such as on-chip thermal phase\nshifters) or dynamic wavelength calibration technologies (such as feedback control circuits) to mitigate\nthermal stability.\nReply:\nIndeed, in the current WDM implementation the deployed laser sources, as well as the multiplexer\nand filter modules have not yet been fully integrated into the photonic chip, as we rely on external\ncomponents to allow greater flexibility in testing, optimization and proof-of-concept of the WDM CAM\noperation. Our target for future implementation is to integrate a frequency comb laser device on the\ntransmitter side, eliminating the need for the input multiplexer, while also reducing the footprint and\nimproving energy efficiency. Considering the 3-wavelength operation performance, we would like to kindly\nrefer the Reviewer to comment #6.\nMoreover, the reviewer successfully pointed out that thermal drift may lead to wavelength\nmisalignments, potentially hindering the implementation of this layout; therefore, closed-loop temperature\ncontrol subsystems should be used to ensure thermal stability. In this direction, several approaches have\nbeen proposed to lock the resonant wavelength of the ring-based multiplexers, with the dominant method\nbeing the employment of energy efficient integrated heaters, [27],[28] as also mentioned by the reviewer.\nApart from this solution, one promising approach is to utilize a dithering technique [29] combined with\ncontactless integrated photonic probe (CLIPP) sensors [30], which enable automated wavelength\nstabilization and thermal drift compensation, by efficiently controlling the working point of each\nmux/demux in real-time. We believe that this kind of integration will be crucial in realizing a fully\nembedded WDM CAM system, ultimately improving scalability and deployment feasibility for practical\napplications.\nReviewer #2\nIn this work, the authors demonstrated high-speed Hamming distance (HD) calculations and content\naddressable memory (CAM) bank operations using linear silicon photonic circuits. The first silicon\nphotonic circuit was initially developed for optical matrix multiplications and reported in their previous\nwork [Ref. 4]. The second circuit uses wavelength-division multiplexing (WDM) to enable parallel\nprocessing, which also originates from their previous works [Refs. 34 & 35]. The use of these linear\nphotonic circuits for HD calculations and CAM operations is novel. However, the potential impact of\nperforming these operations in the optical domain is not very clear, given the additional complexity\nintroduced by the photonic circuits. Before I can make a recommendation, the authors should consider the\nfollowing concerns and comments.\nComment #1:\nThe silicon photonic circuits in this work were initially developed for matrix multiplications, which have\nsignificant applications in optical neural networks. However, in this manuscript, the authors focus on HD\ncalculations and CAM bank operations, which, while important for specific applications such as pattern\nmatching, may not have the same broad technological impact. The scope of these operations is relatively\nnarrow compared to the extensive influence of matrix multiplications in neural network accelerators. As a\nresult, the work may not achieve the level of general interest expected for publication in a high-impact\njournal such as Nature Communications.\nReply:\nWe would like to thank the reviewer for his/her insightful comment regarding the scope and impact\nof our work, as it gives us the opportunity to better clarify the broader significance of our research and its\nalignment with high-impact applications.\nAlthough the reviewer notes that HD calculations and CAM operations may appear niche, these\nfunctionalities are critical for a great range of both traditional and emerging applications such as coding\ntheory, data clustering, in-memory computing, memory augmented neural networks (MANNs),\nassociative memory systems, and pattern recognition tasks. These applications are increasingly relevant\nin areas like communications and networking, computing, bioinformatics, image processing, deep learning\nand real-time data retrieval, where efficient pattern matching and similarity searches are essential [31]-[34].\nFor instance, recent works in the high-impact journal of Nature Communications [35],[36],\nhave demonstrated CAM-based memory modules for implementing attention mechanisms and associative\nmemory operations in the electronic domain, which are essential for one and few-shot learning tasks. CAM\nbanks allow for rapid content-based retrieval of stored patterns, bypassing the von Neumann bottleneck and\nenabling analog in-memory computation on high-dimensional vectors. This capability is particularly\nvaluable for tasks such as image classification and pattern recognition, where the ability to quickly identify\nand retrieve similar patterns from memory is crucial. Beyond MANNs, CAM-based systems also offer\ntransformative potential for accelerating decision trees and random forests, which are top performers in\ndomains requiring interpretability and robust performance with limited training data. Specifically, the\nauthors in [37] have proposed CAM devices for fast look-up table operations, enabling efficient in-memory\ncomputation for tree-based model inference.\nIn addition, such architectures are critical for address look-up (AL) and routing table\nimplementations [38], supporting high-intensity network applications and bandwidth-demanding\noperations in high-performance computing and data center environments [39],[40]. In these systems, high-\nspeed header processing and packet forwarding are essential for interoperability. However, these functions\nare often limited by conventional electronic CAMs, which suffer from slow processing speeds due to their\nelectronic structure [35],[37],[41],[42]. Therefore, optical CAM architectures that offer both high-speed\noperation and energy efficiency represent a valuable advancement in this domain.\nHD calculations comprise also critical functions in a wide range of application domains and can\ncertainly not be considered as “not having a broad technological impact”. HD metrics are widely employed\nin coding theory and error correction codes [43], in information theory [44], in Hamming clustering\nmethods for data clustering [45], as well as in bioinformatics for DNA sequencing [46]. On top of that, our\nwork on HD calculation declares a first successful attempt in the optical domain, using linear circuits for\ncomputing a certain distance metric, which may unlock new capabilities for computing a broader range of\ndistance metrics and similarity measures that are fundamental to numerous high-impact applications. In\nparticular, our architecture can efficiently perform HD calculations but can be also extended to support\nother key non-linear distance metric operations, such as cosine distance and Euclidean distance\ncalculations, which are essential for data clustering (e.g. nearest neighbor algorithm), classification, and\nsimilarity search in machine learning and computer vision tasks.\nTherefore, our work not only advances CAM-based photonic computing but also demonstrates the\npotential of linear silicon photonic circuits to perform a wide array of fundamental linear and non-linear\nmathematical operations, further broadening its relevance and impact.\nChanges in the text:\nIn “Results” section, line 71, we have added the following:\n“HD is a metric widely employed in coding theory and error correction codes [43], in information theory\n[44], in Hamming clustering methods for data clustering [45], as well as in bioinformatics for DNA\nsequencing [46], underscoring its wide-reaching impact across computational and scientific disciplines”\nWe have also added the respective references in the main manuscript.\nComment #2:\nA comprehensive comparison between the demonstrated photonic circuits and previous digital and analog\nelectronic circuits is lacking. The authors claim that their photonic circuit outperforms “state-of-the art\nCAM speed performance by > 2.5×.” However, this evaluation focuses solely on speed and does not\nconsider other critical metrics. Factors such as chip size, system complexity, and overall energy efficiency\nare equally important when assessing the practicality of a hardware architecture. Without addressing these\naspects, it is difficult to fully understand the trade-offs involved in using photonic circuits for these\noperations. In particular, the scalability of this scheme could be an issue. To process an N-bit binary vector,\nthis scheme requires 2N modulators to generate the actual and complementary values. This can\nsignificantly limit the scalability of this scheme in terms of chip size.\nReply:\nRegarding the comparison of state-of-the-art electronic CAMs, please refer to the response of\nComment #5 of the 1st reviewer. On the other hand, regarding the scalability of the proposed architecture,\nthe reviewer is correct in stating that an N-bit binary processing requires 2N search modulators. However,\nthis is not an oversight but rather a deliberate design choice consistent with the approach used in electronic\nCAMs e.g. [10]-[15], where both the actual and complementary bit values are generated to enable\ncomparison operations. As such, this requirement is a shared limitation inherent to both electronic and\nphotonic implementations.\nComment #3:\nThe operation principle in Fig. 1(d) is not clearly explained. The authors mentioned “…adding coherently\nthe resulting optical fields”. However, Fig. 1(d) only depicts intensity modulators. Does the right part of\nFig. 1(d) represent a cascade stage of 1-by-2 optical splitters? Phase shifters are necessary for coherent\nlight summation, which are not shown in this figure. While the supplementary material does provide more\ndetails on the operation principle, it should be sufficiently clear within the main text and figures.\nReply:\nAs the reviewers mentions, indeed the detailed explanation of the operational principle of the\nanalog comparison cell has been initially included in the supplementary material of the manuscript. Figure\n1 (d) of the main manuscript depicts the main concept of the principle of operation, without illustrating the\ndetailed layout of the architecture along with all the respective building blocks .\nBased on the reviewer’s comment we have made the necessary changes in Figure 1 (d) as well as\nFigure 1 (e) of the main manuscript, in order to present in more detail, the operational principle and the\nrespective building blocks of the comparison circuit. Additionally, changes in the main text have also been\nperformed accordingly.\nChanges in the text: The following changes have been performed in the main manuscript, Section:\nHamming Distance using a silicon photonic Xbar PIC.\n- Page 3, Figure 1:\n- Page 3, Figure 1 caption:\n“Analog photonic HD circuit, based on amplitude modulators and coherent light summation with\nthe use of thermo-optic phase shifters”\n- Page 3, line 89:\n“(iii) Injecting the encoded X modulated light beams to the Y amplitude modulating elements and\nadding coherently the resulting optical fields, by utilizing thermo-optic phase shifters that ensure\nproper phase matching between the two branches. The Comparison Cell highlighted in Fig. 1(d),\ncomprises the basic building block of this comparison operation (details for its functionality are\nalso provided in Supplementary section 1).”\nComment #4:\nWhat is the extinction ratio of the SiGe electro-absorption modulator (EAM)? Could an improvement in\nthe extinction ratio further reduce the error rates in Figs. 3(e-f)?\nReply:\nThe reviewer can refer to the response we have provided at the Comment#3 of Reviewer#1,\nregarding the extinction ratio parameter. We have also included the respective analysis in the supplementary\nmaterial, adding the section “Crosstalk and Extinction Ratio analysis”, where the ER limitation is\ninvestigated. Based on our provided analysis it becomes clear that improvement in ER can reduce the\nreceiver’s sensitivity requirements, meaning that the overall performance of our architecture can be\nimproved, taking into consideration the implementation of different modulation technologies, as well as\ncareful design and evaluation approaches of the whole system.\nComment #5:\nPage 4, line 116. Please provide more details on the multi-channel DC control plane.\nReply:\nBased on the comment of the reviewer, we have added additional information regarding the multi-\nchannel DC control plane that has been used in our experimental evaluations.\nChanges in the text: The following changes have performed in the section : Hamming Distance\nCalculation using a silicon photonic Xbar PIC, of the main manuscript.\n- Page 4, line 120:\n“Both EAMs and TO PSs are controlled by a multi-channel DC control plane, that consists of 16\nprogrammable 2-channel DC power supplies.”\n- Page 10, line 257:\n“..., being configured with the use of a multi-channel DC control plane. The DC plane incorporates\n8 different programmable 2-channel DC power supplies (Rigol DP831 LXI) that apply the\nnecessary voltage values to every EAM module. Additional information about the specific driving\nvoltage values can be found in the section 1 of the Supplementary material.”\n- Page 10, line 283:\n“..., driven by the same DC control plane mentioned above (single-wavelength 4x4 Xbar-based HD\nprocessor).”\nComment #6:\nThe current title may be too broad. “Nonlinear optical vector processing” does not accurately summarize\nthe HD calculations and CAM bank operations.\nReply:\nWe have made the following change in the title of the presented manuscript:\n“Nonlinear Optical Vector Processing using Linear Silicon Photonic Circuits for 50 Gb/s Memory\nand String Similarity functions”\nChanges in the text: The titles of both the main manuscript and the supplementary material have been\nupdated accordingly.\nComment #7:\nThe authors should try to use high-resolution images of their circuits. The current images have poor\nresolutions, particularly in Fig.2(a) and Fig. 4(b). No effective information is available from the current\nfigures.\nReply:\nThe provided images of the manuscript have been created by a specific graphic software and the\ncurrent resolution is the highest available that can be exported. Regarding the provided images of Figure 2\n(a) and Figure 4 (b), that showcase the integrated photonic structures, have been acquired with the use of a\nmicroscope image camera. The current provided figures demonstrate the highest resolution available based\non the camera equipment that is currently available in our laboratory. Complying with the comment of the\nreviewer we have included an inset that indicates the sizing of the layouts of the photonic structures,\ntaking into consideration the dimensions of the integrated components (200 um inset). Based on that, the provided\nimages (Fig.2 (a) and Fig. 4 (b)) have been modified accordingly:\nChanges in the text:\n- Page 4, Figure 2 (a):\n- Page 6, Figure 4 (b):\nComment #8:\nPage 1, line 21. Please provide the definition of “WDM”.\nReply:\nBased on the comment, WDM stands for wavelength-division multiplexing.\nChanges in the text: The following changes have performed in the Abstract section of the main manuscript.\n- Page1, line 21:\n“Scalability is enhanced by employing space-wavelength multiplexing schemes via a wavelength-\ndivision multiplexing (WDM)-enabled SiPho processor cell, …”\nComment #9:\nPage 4, line 123. Please provide the definition of “ML”.\nReply:\nThe acronym for the definition ML is referred to match-line.\nChanges in the text: The following changes have performed in the Abstract section of the main manuscript.\n- Page 5, line 127:\n“The case of HD=0 designates an exact vector matching and corresponds to the match-line (ML)\noperation of a complete CAM memory bank, …”\nComment #10:\nPlease use the correct multiplication sign “×” instead of the letter “x” throughout the manuscript.\nReply:\nBased on the respective comment, the letter “x” has been replaced with the sign “×”, throughout\nthe whole manuscript.\nChanges in the text: The following changes have conducted in the overall manuscript.\n- Page 1, line 20:\n“…, improving state-of-the-art CAM speed performance by >2.5×.”\n- Page 2, line 61:\n- “configured as a 4×4 matrix arrangement and employing 56 GHz bandwidth silicon germanium\n(SiGe) EAMs as its core computational cells.”\n- Page 2, line 64:\n- “…with matching error-rates of ~10-3 at operational speeds 2.5× higher than current state-of-the-\nart CAMs clock speed.”\n- Page 4, Figure 2 caption:\n“Fig. 2. (a) Microscope photo of the integrated 4×4 crossbar prototype comparison unit. Inset:\nSingle Xbar comparison cell, consisting of two EAMs and two TO PSs. The search vector encoding\nunit and the 4×4 crossbar, are marked with yellow and orange rectangles, respectively, (b)\nExperimental testbed for the HD comparison operation at 20 and 50 Gb/s, highlighting the search\nvector encoding unit (yellow) and the 4×4 Xbar-based HD processor (orange), along with the\nrespective comparison cells (red). A DC control plane is employed for biasing the static EAMs and\nPSs located in the Xbar layout.”\n- Page 6, line 143:\n“The performance of the 4×4 vector processor was assessed by calculating the projected symbol\nerror rate (SER)…”\n- Page 6, line 169 and 170:\n“In order to validate the advantages of the WDM-enabled approach a 3λ-2×1 comparison cell was\nfabricated using the same technological building blocks (i.e. EAM and TO-PS) as in the 4×4 Xbar.”\n- Page 6, Figure 4 caption:\n“(c) Circuit schematic and experimental setup of the 3λ-2×1 HD processor.”\n- Page 8, line 186:\n“Similarly to the single-λ 4×4 Xbar layout,”\n- Page 8, line 198:\n“…, when targeting a single-λ 32×32 Xbar based layout, …”\n- Page 8, Figure 6 caption:\n“Fig.6. (a) Projected Error Rates for a 32×32 Xbar implementation at 20 and 50 Gb/s operation.”\n- Page 9, line 214:\n“These layouts correspond to Xbar scales of 4×4 to 128×128 for the single λ case, and 4×1 to\n128×32 for the 4-λ case, …”\n- Page 9, line 233:\n“Single-wavelength 4×4 Xbar-based HD processor”\n- Page 9, line 239:\n“After entering the structure, the signal is split (1×4 splitting stage) and gets injected into the four-\nsearch word vector EAMs, …”\nReviewer #3\nThe manuscript presents a novel approach to nonlinear optical vector processing using linear SiPho\ncircuits, achieving 50 Gb/s Hamming Distance (HD) and CAM operations. However, several limitations\nin experimental validation, scalability analysis, and technical comparisons need addressing to strengthen\nthe claims and ensure reproducibility. I will suggest a comment of Major Revision.\nComment #1:\nExpand experimental validation to larger-scale architectures. To conduct small-scale extended tests (e.g.,\n8×8 or 16x16 X-bar) to verify theoretical scalability models. To discuss manufacturing challenges (e.g.,\ncrosstalk, cumulative losses) for large-scale integration.\nReply:\nWith all the respect to the reviewer’s comment, the 8x8 and even more the 16x16 Xbar\nconfigurations can definitely not be considered as “small-scale extended tests” within the context of a\nuniversity research laboratory. For instance, testing an 8×8 Xbar layout at 50Gb/s would require 8\nindependent 50 Gb/s RF channels to be provided by Arbitrary Waveform Generator modules (AWG)\nsimilar to the AWG Keysight M8194A that we employed in our experiment. Taking into account that the\nAWG Keysight M8194A provides up to 4 independent RF channels and has a cost of approximately\n300,000–400,000 $, it can be easily understood that such a setup for generating the 8 different electrical\nchannels falls well beyond what should be expected by a university research lab. The cost and complexity\nobviously increase even more dramatically for a 16×16 configuration, as it would require double the number\nof channels and significantly more advanced testing infrastructure. Beyond AWG requirements, additional\nhigh-bandwidth optical and electrical components such as clock generators for synchronization, high-\nbandwidth driver amplifiers for electrical amplification and custom RF probes for high-frequency signal\ndelivery further contribute to the cost and of course the complexity of scaling up the experiment. This has\nbeen the main reason that we have “limited” our experimental demonstration to a maximum Xbar circuit\ndimension of 4x4. However, even this circuit dimension provides meaningful insights into the scalability\nof our theoretical models taking into account that:\n• the Xbar insertion loss and fidelity performance theoretical models have been validated using up\nto 4x4 Xbar prototypes, as reported in our previous Nature Communications article (M. Moralis-\nPegios et al, “Perfect linear optics using silicon photonics”, Nat Commun 15, 5468 (2024).\nhttps://doi.org/10.1038/s41467-024-49768-y, reference [4] in our current manuscript),\n• the Xbar noise and energy performance theoretical models were validated in a number of\npublications where 2x2 Xbar prototypes were utilized for analog matrix-vector multiplication tasks\n(see reference [13] in our original manuscript G. Giamougiannis et al., “Analog nanophotonic\ncomputing going practical: Silicon photonic deep learning engines for tiled optical matrix\nmultiplication with dynamic precision,” Nanophotonics 12(5), 963 (2023), see also S.\nKovaios et al, “Scaling photonic neural networks: A silicon photonic GeMM leveraging a Time-\nSpace multiplexed Xbar”, IEEE/OSA J. on Lightwave Technol., vol. 42, no. 22, pp. 7825-7833,\nNov. 2024 )\nWe believe that all this previously published work confirms the consensus of the scientific community that\nXbar circuit dimensions of up to 4x4 can reliably validate the respective theoretical models for higher Xbar\nscales, without requiring 8x8 or even 16x16 experimental prototypes.\nRegarding the manufacturing challenges (crosstalk, cumulative losses) for large-scale integration\nplease the reviewer can refer to our response on Comments #2 and #6 of the Reviewer #1.\nComment #2:\nEnhance error rate analysis with noise source quantification and energy efficiency measurements. To\nquantify or evaluate the contributions of thermal noise, crosstalk, and nonlinear effects to SER/MER. To\nprovide measured energy efficiency data (including laser and driver circuitry) for WDM vs. single-λ\ndesigns. It seems that the energy efficiency has not consider the optical-electrical conversion power.\nReply:\nRegarding noise source quantification please refer to the response of Comment #4 of the 1st\nreviewer. On the other hand, non-linear effects in photonic systems mainly arise due to high optical power\nlevels which in our system may lead to two photon absorption (TPA) in silicon waveguides [47] and/or\nself-heating effects in electro-absorption modulators (EAMs) [48]. TPA typically becomes significant at\npower levels above 10 mW [47], while self-heating in EAMs can occur when the incident optical power\nexceeds 6 mW [48]. Accordingly, we carefully monitor and control the optical power to ensure operation\nwithin safe and stable limits.\nThe calculation of energy efficiency for both single and WDM layouts includes lasers power,\naccounted for through wall-plug efficiency, as well as optical-to-electrical conversion via transimpedance\namplifiers, as thoroughly analysed in Section 4 of the supplementary material. It is worth noting that the\nnumber of TIAs remains unchanged between the single and WDM layouts, as the 4λ-WDM design\neffectively introduces a capacity enhancement factor of λ = 4, as well as minimized losses and enhanced\nenergy efficiency. As a result, a 128×32 layout using 4λ-WDM achieves the same word capacity as a single-\nλ 128×128 layout. The same principle is also valid for the driver circuitry (DACs) of the static EAMs\nemployed for encoding the target vectors.\nOn the other hand, the driver circuitry of the EAMs used to encode the search vectors has indeed\nnot been considered in our simulations, as the generation of the search vector is not part of the CAM table,\nbut is instead employed in order to facilitate the proof-of-concept demonstration. This is fully consistent\nwith the approach taken in the electronic CAMs [35], [36], [41], [42], where the energy efficiency is\ncalculated based solely on the implementation of the CAM table.\nChanges in the text: To address the reviewer's concern and provide clearer clarification on the energy\nefficiency comparison between the single-λ and WDM layouts, we have provided the following:\nIn supplementary material, section 4, line 268:\n“This approach allows for minimization in the overall scale of the layout, allowing for a reduced\nnumber of output columns, thus reducing the splitting and combination required components achieving the\nsame number of comparison operations. Based on that, due to the reduced splitting stages the required\nlaser power launched into the crossbar array will be minimized, since less power will be needed in order\nto propagate the same power value at every column of the array. On top of that the component losses of the\nsplitter/combiner stages will be also reduced, with the only additional loss parameter being the Mux and\nDemux stages that the different wavelengths will propagate through (3 stages for every column).\nConsidering state-of-the-art low-loss multiplexer and demultiplexer components that can be utilized in the\nWDM-architectures, a minimal losses of 0.2 dB per Mux/De-Mux module Error! Reference source not\nfound., can be estimated.\nThis leads to significantly reduced overall insertion losses for the WDM implemented schemes\n(IL ) compared to the total losses of the conventional Xbar layouts (IL ), with the loss\nWDM single-wavelength\nreduction being correlated to the number of allocated wavelengths that are used for the parallel\ncomparisons and the reduced columns of every layout. Such an approach significantly reduces the overall\ninsertion losses of the architecture, especially when scaling to 32 and 64-bit long comparison schemes.\nThe method of calculating the total losses of the conventional architecture (IL ) are\nsingle-wavelength\nthoroughly explained in Error! Reference source not found., while the loss reduction parameters of the\nWDM layouts are provided below for every respective scale case of [4-128]:”\nComment #3:\nUpdate technical comparisons with state-of-the-art electronic CAM/TCAM benchmarks.\nTo compare against recent CMOS advancements (e.g., 5nm-node TCAMs) in speed, power, and area\nefficiency.\nReply:\nPlease refer to the response that we have provided at Comment#5 of the 1st Reviewer.\nComment #4:\nClarify WDM engineering challenges and mitigation strategies. To detail wavelength stabilization\nmethods and difficulty (e.g., thermal feedback loops) to counter temperature drift. What is the inter-\nchannel crosstalk suppression (e.g., optimized filter bandwidths, guard bands)?\nReply:\nThe reviewer has made a quite accurate statement regarding the possible problems that can occur in our\nWDM implementation, regarding the utilised wavelength’s stabilization of the layout. The reviewer can see\nour respective reply, detailed in Comment #7 of Reviewer #1, where we propose possible methods that can\nbe used to stabilize and compensate the thermal drifting of ring resonator effects, as well as calibrate the\nmultiplexer/demultiplexer elements, ensuring proper operation of the WDM scheme.\nThe reviewer can also our reply of Comment #6 and #7 of Reviewer #1, where we analyze the crosstalk\nresponse in our WDM layout.\nAdditional changes:\n- The Data Availability section has been modified accordingly:\n“The data cases that support the experimental results and findings of the study, as well as all the\nvalidation methods and procedures for the additional analysis performed have been provided with this\npaper during the submission process, with supplementary information files. In case of additional\ninformation and data of the study, complementary material can be provided upon request.”\n- An additional Code Availability section has been added to the main manuscript:\n“All software and source code files, as well as documentation and instructions for the analysis and\nvalidation of the experimental and theoretical findings of the study, have been provided with this paper,\nas supplementary material and documents. Any additional specifications regarding the methods that have\nbeen followed can be provided upon request.”\n- The References section has been updated with the following manuscripts:\n“- K. Huffman, W. C. & Pless, V. Fundamentals of Error‑Correcting Codes, Chs. 1, 3 (Cambridge Univ. Press,\n2003).\n- Hamming, R. W. Coding and Information Theory, Chs. 1–2 (Prentice‑Hall, 1980).\n- Argiento, H. Filippi-Mazzola, E. Paci, L., Model-based clustering of categorical data based on the Hamming\ndistance, arXiv:2212.04746.\n- Pinheiro A., Pinheiro Prisco H., et. al., The use of Hamming distance in bioinformatics. In Handbook of\nStatistics 28, 129–162 (Elsevier, 2012).”\n- Respective changes in the Supplementary material have been performed, according to the\ncomments.\nReferences:\n[1] E. Garzón, et al., \"A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With\nReliable Sub-Nanosecond Search Operation,\" in IEEE Access, vol. 11, pp. 16812-16819, 2023,\ndoi: 10.1109/ACCESS.2023.3245981\n[2] C. Wang, et al., \"A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for\nHigh-Speed, Low-Power, and High-Reliable Search Operation,\" in IEEE Transactions on Circuits\nand Systems I: Regular Papers, vol. 66, no. 4, pp. 1454-1464, April 2019, doi:\n10.1109/TCSI.2018.2885343.\n[3] X. Wang, et al., \"A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and\nMulti-Level Architecture for High Reliability and Density,\" 2021 IEEE 10th Non-Volatile\nMemory Systems and Applications Symposium (NVMSA), Beijing, China, 2021, pp. 1-6, doi:\n10.1109/NVMSA53655.2021.9628720.\n[4] G. Giamougiannis et. al., \"A Coherent Photonic Crossbar for Scalable Universal Linear Optics,\"\nin JLT, vol. 41, no. 13 8, pp. 2425-2442, 15 2023.\n[5] Tae Joon Seok, Niels Quack, Sangyoon Han, Richard S. Muller, and Ming C. Wu, \"Large-scale\nbroadband digital silicon photonic switches with vertical adiabatic couplers,\" Optica 3, 64-70\n(2016).\n[6] M. Pantouvaki et al., \"Active Components for 50 Gb/s NRZ-OOK Optical Interconnects in a\nSilicon Photonics Platform,\" JLT, 35, 4, 2017.\n[7] C. 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Kasai et al.,“200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with\nnew charge injection match detect circuits and bank selection scheme”IEEE C. Int.Circuits\nConf.,2003, pp. 387–390\n[13] T. Nagakartnik and J.R. Choi, “500-MHz high-speed, low-power ternary CAM design\nusing selective match line sense amplifier in 65nm CMOS”, 6th Inform. and Commun. Syst., pp.\n60-63, Amman, 2015\n[14] E. Garzon, et. al. \"A 128-kbit Approximate Search-Capable Content-Addressable Memory\n(CAM) With Tunable Hamming Distance,\" IEEE J. of Solid-State Circuits, article in press\n[15] K. Lee, et. al. \"A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an\nAdaptive Match-Line Discharge,\" IEEE J. Solid-Sate Circuits, vol. 56, no. 8, pp.2574-2584, Aug.\n2021\n[16] I. Arsovski, T. Hebig, D. Dobson, R. Wistort, \"A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary\nContent Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing\nWith Embedded Deep-Trench Capacitor Noise Mitigation,\"IEEE J.Solid-State Circ,vol.48 (4),\n932-939, 2013\n[17] K. N ii, et. al. \"A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM,\" IEEE\nInternational Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA,\nFeb. 2014\n[18] S. Jeloka, et. al. \"A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-\nRule 6T Bit Cell Enabling Logic-in-Memory,\" IEEE Journal of Solid-State Circuits ( Volume: 51,\nIssue: 4, pp. 1009-1021, April 2016,\n[19] Y. Tsukamoto, \"1.8 Mbit/mm2 Ternary-CAM macro with 484 ps Search Access Time in\n16 nm Fin-FET Bulk CMOS Technology,\" IEEE Symposium on VLSI Circuits, Kyoto, Japan, June\n2015\n[20] I. Avrovski, et. al. \"1.4Gsearch/s 2Mb/mm2 TCAM Using Two-Phase-Precharge ML\nSensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%,\" IEEE\nInternational Solid-State Circuits Conference (ISSCC), San Fransisco, CA, USA, Feb. 2017\n[21] M. Yabuuchi, et. al. \"12-nm Fin-FET 3.0G-search/s 80-bit × 128-entry Dual-port Ternary\nCAM,\" IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 2018\n[22] M. Yabuuchi, et. al. \"A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved\nElectromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-\nLine Amplifier,\" IEEE Sympos. VLSI Circuits, Honolulu, HI, USA, June 2020\n[23] C. Deshpande, et. al. \"A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single\nCycle Entry Update Capability for Data Center ASICs,\" IEEE VLSI Symposium, Kyoto, Japan,\n13-19 June 2021\n[24] S. Kumar, et. al., \"A 3nm FinFET 2.2Gsearch/s 0.305fJ/b TCAM with Dynamically Gated\nSearch Lines for Data-Center ASICs,\" IEEE Intern. Solid-State Circuits Conf, San Francisco, CA,\nUSA, Feb. 2025\n[25] L.-A. Yu, et. al. \"Design of the 2-nm Nanosheet NAND-type TCAM with High Speed and\nCompat Cell-size: 45% Layout-reduction of 3-nm TCAM,\" IEEE Silicon Nanoelectronics\nWorkshop, Honolulu, HI, USA, June 2024\n[26] S. Pathak, P. Dumon, D. Van Thourhout and W. Bogaerts, \"Comparison of AWGs and Echelle\nGratings for Wavelength Division Multiplexing on Silicon-on-Insulator,\" in IEEE Photonics\nJournal, vol. 6, no. 5, pp. 1-9, Oct. 2014.\n[27] E. Timurdogan, et. al., “Automated wavelength recovery for microring resonators,” in Proc. Conf.\nLasers Electro-Opt., 2012, pp. 1–2.\n[28] K. Padmaraju, J. Chan, L. Chen, M. Lipson, and K. Bergman, “Thermal stabilization of a\nmicroring modulator,” Opt. Exp., vol. 20, no. 27, pp. 27999–28008, 2012.\n[29] K. Padmaraju, et. al., “Wavelength locking and thermally stabilizing microring resonators using\ndithering signals,” JLT, vol. 32, no. 3, pp. 505–512, Feb. 2014.\n[30] F. Zanetto et al., \"WDM-Based Silicon Photonic Multi-Socket Interconnect Architecture With\nAutomated Wavelength and Thermal Drift Compensation,\" in Journal of Lightwave Technology,\nvol. 38, no. 21, pp. 6000-6006, 1 Nov.1, 2020\n[31] S.M. Lundberg, et al. Explainable machine-learning predictions for the prevention of hypoxaemia\nduring surgery. Nat Biomed Eng 2, 749–760 (2018).\n[32] Y.C. Su, et.al., Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time\nObject Recognition in Full-HD Resolution, IEEE VLSI, 2000.\n[33] T. M. Chan, et. al., Approximating text-to-pattern Hamming distances, ACM SIGACT\nSymposium on Theory of Computing, STOC 2020, New York, NY, USA, 643–656.\n[34] C. Wang, et. al., Using Hamming Distance as Information for SNP-Sets Clustering and Testing\nin Disease Association Studies, 2015.\n[35] R. Mao, et al., Experimentally validated memristive memory augmented neural network with\nefficient hashing and similarity search. Nat Commun 13, 6284 (2022).\n[36] G. Karunaratne, et al., Robust high-dimensional memory-augmented neural networks. Nat\nCommun 12, 2468 (2021).\n[37] G. Pedretti, et al. Tree-based machine learning performed in-memory with memristive analog\nCAM, Nat Comm. 12, 5806 (2021).\n[38] K. Pagiamtzis and A. Sheikholeslami, “Content-Addressable Memory (CAM) Circuits and\nArchitectures: A tutorial and survey,” IEEE Journal of Solid-state Circuits, vol. 41, no. 3, pp.\n712–727, Mar. 2006.\n[39] C. Minkenberg, et al., “Co‐packaged datacenter optics: Opportunities and challenges,” IET\nOptoelectronics, vol. 15, no. 2, pp. 77–91, Mar. 2021.\n[40] R. S. Williams, \"What's Next? [The end of Moore's law],\" in Computing in Science &\nEngineering, vol. 19, no. 2, pp. 7-13, Mar.-Apr. 2017.\n[41] C. E. Graves, et al., \"Memristor TCAMs Accelerate Regular Expression Matching for Network\nIntrusion Detection,\" in IEEE Transactions on Nanotechnology, vol. 18, pp. 963-970, 2019.\n[42] Y. Goh, et al., “High performance and self-rectifying Hafnia-based ferroelectric tunnel junction\nfor neuromorphic computing and TCAM applications,” 2021 IEEE International Electron Devices\nMeeting (IEDM), Dec. 2021\n[43] Huffman, W. C. & Pless, V. Fundamentals of Error‑Correcting Codes, Chs. 1, 3 (Cambridge\nUniv. Press, 2003).\n[44] Hamming, R. W. Coding and Information Theory, Chs. 1–2 (Prentice‑Hall, 1980).\n[45] Argiento, H. Filippi-Mazzola, E. Paci, L., Model-based clustering of categorical data based on\nthe Hamming distance, arXiv:2212.04746.\n[46] Pinheiro A., Pinheiro Prisco H., et. al., The use of Hamming distance in bioinformatics. In\nHandbook of Statistics 28, 129–162 (Elsevier, 2012).\n[47] Q. Lin, Oskar J. Painter, and Govind P. Agrawal, \"Nonlinear optical phenomena in silicon\nwaveguides: Modeling and applications,\" Opt. Express 15, 16604-16644 (2007).\n[48] D. Coenen et al., \"Electro-Absorption Modulator Thermo-Optical Self-Heating Analysis,\" in\nJournal of Lightwave Technology, vol. 41, no. 18, pp. 6000-6006, 15 Sept.15, 2023."}, {"round": 2, "reviewer_comments": {"reviewer_1": "From an academic and research point of view, for conceptual proof, small-scale architecture is acceptable.\nThe authors have answered all the questions from the three reviewers, and I believe the answers are accurate. There are no further comments.", "reviewer_2": "I thank the authors for addressing some of my concerns. In response to my comment #2, the authors\nprovided “Table 2: State-of-the-art electronic TCAMs” in the revised supplementary document.\nWhile it is true that the chip in this work operates at a significantly higher clock frequency (50\nGHz) than electronic TCAMs, its energy efficiency (energy/search/bit), array size, and area per\ncell are significantly worse than those of its electronic counterparts. For example, compared with\nRef. 26, which uses an outdated CMOS technology node of 32 nm, the area/cell in this work is\n113,095 times larger and the energy/search/bit is 55 times higher; compared with Ref. 34, which\nuses an advanced CMOS node of 3 nm, the area/cell in this work is 472,637 times larger and the\nenergy/search/bit is 105 times higher.\nMore importantly, it is nearly impossible that the array size of a photonic circuit can reach the\nsame scale as that of electronic TCAMs, which can easily achieve 512×220. The array size is an\nimportant parameter that cannot be ignored in TCAM applications. Lightmatter and Lightelligence\nhave indeed presented large-scale photonic chips for matrix multiplications (128×128 and 64×64,\nrespectively). However, the operating clocks of their photonic chips are 2 GHz and 1GHz,\nrespectively. I am not convinced that each modulator can still be operated at 40 GHz in a practical\nscenario when the photonic circuit demonstrated in this work is scaled up (for example, to\n128×128).\nTherefore, while I think this work provides a novel approach, I do not think that the results\npresented in this work represent a significant advancement compared to electronic TCAMs. Thus,\nI cannot recommend its publication in Nature Communications."}, "author_response": "Aristotle University of Thessaloniki\nDepartment of Informatics\n54124 Thessaloniki, Greece\nTel: +30 2310 990588\nE-mail moschost@csd.auth.gr\n3rd October 2025\nDear Reviewers,\nWe would like to thank the reviewers for their constructive feedback and thorough comments on\nour submitted manuscript in Nature Communications, entitled “Nonlinear Optical Vector Processing\nusing Linear Silicon Photonic Circuits for 50 Gb/s Memory and String Similarity functions”, by T.\nMoschos, C. Pappas, S. Kovaios, I. Roumpos, A. Prapas, A. Tsakyridis, M. Moralis-Pegios, C. Vagionas,\nY. London, B. Tossoun, T. Van Vaerenbergh and N. Pleros, rendering it suitable for publication.\nWith this reply letter you can find attached our final changes and replies to the provided comments,\nalong with the respective changes in the overall manuscript material.\nBest regards,\nTheodoros Moschos\nDepartment of Informatics\nAristotle University of Thessaloniki\nRevisions on the scientific journal of Nature Communications for the submitted manuscript of\n“Nonlinear Optical Vector Processing at 50Gb/s using Linear Silicon Photonic Circuits”-\nNCOMMS-25-11055A\nReviewer #1\nFrom an academic and research point of view, for conceptual proof, small-scale architecture is acceptable.\nThe authors have answered all the questions from the three reviewers, and I believe the answers are\naccurate. There are no further comments.\nReply:\nWe would like to sincerely thank the reviewer for the positive evaluation on our proposed\narchitectures. We are glad that our responses have addressed all comments and questions. The constructive\nfeedback that has been provided through the review process has helped us improve and strengthen the\nclarity and overall quality of the current manuscript.\nReviewer #2\nComment:\nI thank the authors for addressing some of my concerns. In response to my comment #2, the authors\nprovided “Table 2: State-of-the-art electronic TCAMs” in the revised supplementary document. While it is\ntrue that the chip in this work operates at a significantly higher clock frequency (50\nGHz) than electronic TCAMs, its energy efficiency (energy/search/bit), array size, and area per\ncell are significantly worse than those of its electronic counterparts. For example, compared with\nRef. 26, which uses an outdated CMOS technology node of 32 nm, the area/cell in this work is\n113,095 times larger and the energy/search/bit is 55 times higher; compared with Ref. 34, which\nuses an advanced CMOS node of 3 nm, the area/cell in this work is 472,637 times larger and the\nenergy/search/bit is 105 times higher.\nMore importantly, it is nearly impossible that the array size of a photonic circuit can reach the\nsame scale as that of electronic TCAMs, which can easily achieve 512×220. The array size is an\nimportant parameter that cannot be ignored in TCAM applications. Lightmatter and Lightelligence\nhave indeed presented large-scale photonic chips for matrix multiplications (128×128 and 64×64,\nrespectively). However, the operating clocks of their photonic chips are 2 GHz and 1GHz,\nrespectively. I am not convinced that each modulator can still be operated at 40 GHz in a practical\nscenario when the photonic circuit demonstrated in this work is scaled up (for example, to\n128×128).\nTherefore, while I think this work provides a novel approach, I do not think that the results\npresented in this work represent a significant advancement compared to electronic TCAMs. Thus,\nI cannot recommend its publication in Nature Communications.\nReply:\nWe would like to thank the reviewer for the effective criticism and comments on our presented\nwork, and also for recognizing the novelty of our approach. At first, we are delighted that we managed to\naddress a part of the reviewers’ comments. We completely understand the reviewer’s concern,\nmentioning\na detailed comparison and highlighting the maturity of the electronic TCAM technologies compared to our\noptical one.\nWe fully agree that in terms of energy/search/bit as well as area/cell efficiency the current electronic\nCMOS TCAMs, after decades of maturity and optimization across their nodes, remain superior compared\nto the presented photonic layouts. However, our current contributed work does not lie in matching CMOS\nat its maturity level, but in demonstrating a fundamentally new direction where photonics offer some key\nadvantages:\n• Bandwidth & Parallelism: Our prototypes operate at clock rates of 50 GHz, i.e. 25x higher than\ncurrent electronic TCAMs, offering also parallel operations via wavelength multiplexing. This\nparallelism is not available to electronic implementations, and it becomes increasingly critical as\nsystem I/O line rates move toward multi-Tb/s.\n• Interconnect Bottleneck Relief: In modern systems, it is revealed that the dominant energy cost\nis actually data movement and not storage of the information itself. Photonic circuits naturally\nprovide low-latency and low-energy interconnects, which scale favourably in energy-delay product\ncompared to electronics at multi-Gb/s per lane operations.\n• Passive Computation: Unlike CMOS TCAMs, which rely on sequential transistor switching and\ncomplex interconnects, our schemes perform all the respective computations via passive\ninterference, with delays mostly determined by the optical path length. This results in intrinsic ps-\nscale latency that is independent of logic depth.\nBy comprehending all the above characteristics, our presented coherent photonic prototypes\nshowcase promising energy requirements as well as latency-free interference processes. Moreover, apart\nfrom the high clock rate of our implementations our proposed WDM layout enables a parallel computational\napproach, offering multi-dimensional operations without necessarily requiring high-scale photonic arrays,\nsimilar to the respective electronics. This allows for a reasonable node array, allowing for realistic photonic\nstructures that can efficiently be controlled retaining their functionality across their scale and also remain\ninto a reasonable energy cost in the cases of required scalability, even at high data rates, as highlighted by\nour additional analysis.\nFinally, we would like to emphasize that silicon photonics, while still being less mature than\nCMOS, undergo very rapid technological progress [1]. Over the past decade, we have witnessed dramatic\nimprovements in footprint reduction, wafer-scale integration, heterogeneous integration with III-V\nmaterials and advanced packaging. These trends are very similar to the evolutionary trajectory that\nelectronic TCAMs themselves experienced over several decades. Given this continuous progress, we are\nconfident that the density and energy efficiency gap with CMOS will gradually shrink, while maintaining\nthe unique advantages of photonics in terms of bandwidth scaling, interconnect efficiency, and parallelism,\nrendering also our proposed prototypes efficient in larger-scale implementations.\nAdditional changes:\nBased on the editorial requests respective text formatting across all the main manuscript and\nsupplementary material of the presented work have been modified. Additionally, the respective manuscript\nfigures have been modified and changed in order to comply with the respective requests.\nReferences:\n[1] N. Margalit et al., “Perspective on the future of silicon photonics and electronics,” Appl. Phys.\nLett. 118, 220501 (2021)."}]

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