Cryogenic neuromorphic circuits using gate-controlled negative differential resistance in silicon carbide

Domain: physics
Published: 2026-03-23
Editorial outcome: minor_revision

Abstract
Cryogenic electronic circuits are crucial for interfacing and controlling scalable quantum computing platforms at millikelvin temperatures, yet face stringent thermal constraints demanding ultra-low power operation. Neuromorphic circuits, emulating the spiking behavior of biological neurons, offer solution for achieving energy-efficient electronics under these conditions. Here, we report the gate-controlled negative differential resistance (NDR) in silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). This NDR effect, arising from electron-donor impact ionization (EDII) in SiC MOSFET, achieves on/off current ratio over 107. Meanwhile, the behavior of NDR can be fully controlled by the gate voltage of the MOSFET. Leveraging this gate-controlled NDR, we demonstrate programmable cryogenic spiking neuromorphic circuits, including sensory, logic, and integrate-and-fire neurons, with functionality tuned by gate or drain voltages. The established manufacturability of SiC technology highlights the potential of this approach for scalable integration in cryogenic systems for sensing, computing, and quantum information.

Introduction
Cryogenic electronics find their applications in computing, sensing, medical imaging, and space exploration. For example, superconducting nanowire single-photon detectors1 enable single photon counting with quantum-limited noise; cryogenic-compatible integrated circuits could be operated in the deep universe at the cosmic microwave background temperature of 2.7 K2,3. More energy-efficient computing is possible at cryogenic temperatures by overcoming the fundamental thermal limit of subthreshold swing at room temperature4,5. The significant challenges of cryogenic electronics stem from the need to interface and control quantum systems6–9, such as superconducting qubits and solid-state quantum centers, which are typically operating in millikelvin (mK) dilution refrigerators with a limited cooling power of sub-milliwatts. Currently, most cryogenic qubit control electronics9,10 consume tens to hundreds of milliwatts; thus, they are anchored to the 4 K plate of a dilution refrigerator where greater cooling power is available. However, this configuration requires extensive wiring between the 4 K and mK plates, which introduces additional heat loads to the mK plate and potential cross-talks between wires, ultimately limiting scaling of quantum circuits. To address this, efficient local processing hardware at mK plates is desired to overcome the interconnect bottleneck, particularly for large-scale quantum error correction (QEC)11 and real-time quantum control12.

Compared to conventional synchronous circuits, neuromorphic circuits mimicking the event-driven spiking behavior of neurons can offer more energy-efficient cryogenic circuits. Neuromorphic circuits based on conventional complementary metal-oxide-semiconductor (CMOS) technologies use multiple transistors to form one neuron13, resulting in a low computing area density on a chip. Several cryogenic CMOS circuits have been demonstrated at 3 K to 50 mK10,14–16, although tailored cooling solutions are required to address their heat loads. Emerging devices, including memristors17–22, ferroelectric devices23,24, phase-change memory (PCM)25, resistive random-access memory (ReRAM)26, spintronic devices27,28, and metal-oxide-semiconductor field-effect transistors (MOSFET)29,30 implement neurons using fewer or a single device, paving the way to a high on-chip density. Meanwhile, cryogenic memories based on ReRAM31,32, ferroelectric33, spintronic34,35, and quantum anomalous Hall effect36 devices have been demonstrated down to 4 K temperature, providing a pathway to build cryogenic neuromorphic circuits. Superconducting devices and circuits37–39 open another pathway, although large-scale superconducting circuits, for example, with over 1,000 qubits, are still challenging.

Implementation of cryogenic neuromorphic circuits in quantum and space applications requires a combination of several key features. The active computing devices must exhibit ultralow leakage current, high on/off ratios, and operate at CMOS-compatible voltages. At the integrated circuit level, desired hardware platforms should provide neuromorphic circuit elements that can perform all essential functions, feature a high area density on chip, ensure consistent performance across devices and fabrication batches, and enable high-yield wafer-scale manufacturing capability. However, no fundamental device technology to date has met all these criteria. In particular, many emerging devices suffer from poor uniformity and lack scalability to wafer-level manufacturing.

In this work, we report the gate-controlled negative differential resistance (NDR) in silicon carbide (SiC) MOSFET–a device with industry-mature manufacturability up to 300-mm wafers–when operating at cryogenic temperature. Distinct from thermally induced NDR, our NDR stems from the carrier dynamics involving impact ionization with dual dopant levels in SiC. This mechanism leads to an S-type NDR with fast responses and on/off current ratios over 107 at transition points, which exceeds previously reported NDR based on Joule heating40,41 or molecules42,43 and thus is desired to build power-efficient spiking neuromorphic circuits. Using this gate-controlled NDR, we demonstrate versatile and programmable neuromorphic circuit elements, including sensory, logic, and integrate-and-fire circuit units. We further demonstrate the cascade between two devices, rendering its feasibility and high potential in building large-scale cryogenic neuromorphic circuits.

Results
Negative differential resistance at cryogenic temperature

Our device is a vertical SiC MOSFET with a gate-modulated vertical current flow through the lightly doped drift region. A cross-sectional scanning electron microscopy (SEM) image of the device is provided (Fig. 1a). We characterized the device down to millikelvin temperatures using a dilution refrigerator system (Methods and Supplementary Note 1). At room temperature, when a gate-source voltage V is applied to turn on the MOS channel, the drain-source current I and voltage V characteristic curve shows a linear ohmic behavior (Supplementary Fig. 7a). During cooling, the device exhibits diode-like (non-Ohmic) I -V curves, where the threshold voltage increases as temperature decreases (Supplementary Fig. 7b). When the device is cooled below a threshold temperature of 2 K, the I -V curves reveal an S-shape NDR behavior (Fig. 1b and Supplementary Fig. 7c). We observe NDR within a current range of 50 μA to 100 mA and a voltage range of 4.2 V to 2.4 V (Fig. 1b). Notably, we observe a high on/off current ratio of 1.4×107 in this single transistor-based NDR. Remarkably, this NDR behavior is gate controllable, i.e., the transition voltages and currents depend on the applied gate voltage (Fig. 1c). For example, tuning the gate voltage from 18 V to 6 V increases the transition voltages and narrows the current ranges. This controllability enables the programmability of our NDR-based cryogenic neuromorphic circuits. Furthermore, this NDR is also bidirectional, i.e., it presents symmetric characteristics under positive and negative V (Supplementary Fig. 10b), enabling efficient connection between neurons. More device characterizations are provided in Supplementary Note 3.

Distinct from thermally induced NDR, which are more common in previous works, such as Joule heating in oxides40,41, the observed NDR in this work is not thermally induced, evidenced by the following measurement results. First, the NDR region persists under 2 K down to our base temperature of 9.4 mK (Supplementary Fig. 10e). Second, we performed a time-depending measurement, after initial stabilization, the voltage in the NDR region is stable with a constant current (10 mA) drive generating 25.9 mW on the device (Supplementary Fig. 10f), which is a large thermal load at sub-Kelvin temperature. Third, we performed pulsed I-V measurements with pulse widths ranging from 50 ms to 500 ms. The NDR behavior remained consistent across different pulse widths (Supplementary Fig. 10g). Subsequently, we measured one device four times consecutively; the device exhibited minimal parametric shifts in a temperature range from 100 mK to 600 mK (Supplementary Fig. 10h). The device also demonstrates the long-term stability of NDR characteristics through one-hour repetitive tests (Supplementary Fig. 9), showing only slight variations attributed to temperature fluctuations. Finally, three SiC MOSFETs from different wafer batches were tested, all demonstrating consistent NDR behavior with only a 0.06 V variation in the NDR threshold voltage V , indicating strong uniformity(Supplementary Fig. 10i).

The NDR phenomenon we observed in SiC MOSFETs can be described by the electron-donor impact ionization (EDII) effect, which involves the interaction of conduction-band electrons with the ground state and excited states of the donor level in the lightly doped drift region (Supplementary Fig. 12a). Meanwhile, the electron injection originates from the highly doped source region via an inversion-mode MOS channel below the gate, enabling gate control over the NDR behavior. At cryogenic temperatures, in the equilibrium condition, free electrons within the drift region freeze out and are captured by donor levels, leading to an ultralow leak current in the off-state. When applying a V greater than the channel threshold voltage along with a sufficient V , electrons from the source region are injected into the drift region via the gate-controlled MOS channel (Supplementary Fig. 12b). Notably, the preservation of an inversion-mode MOS channel at cryogenic temperatures is supported by recent reports demonstrating its operation down to 15 mK44. Our analytical model based on the EDII effect reproduces the experimental I-V data (Supplementary Fig. 12c). Considering the two unique donor levels associated with the nitrogen (N) substitutional donor in 4H-SiC45, we find that a 50 meV donor level on the hexagonal carbon site, combined with an excited state at 2.75 meV, can closely match modeled NDR characteristics with the experimental results (Supplementary Figs. 12c-12f). The model is further validated by its prediction of a threshold temperature for NDR onset near 2 K, consistent with experimental observations. This model also explains the NDR characteristics under negative V ; Slightly different from the positive V case, the electrons are initially injected from the highly doped substrate and then flow through the drift region and inversion-mode MOS channel.

The NDR observed in SiC MOSFETs exhibits a favorable combination of performance metrics, including an orders-of-magnitude higher on/off current ratio, a wide NDR voltage range, a low critical electric field for NDR onset, and a low leak current density46–63 (Figs. 1d and 1e). The high on/off ratio and wide NDR voltage range provide a broad modulation window for circuit operations, while the low turn-on field and leakage current reduce power dissipation in both on- and off-states, minimizing thermal load. Notably, compared to previous EDII-induced NDRs – reported primarily in two-terminal devices based on materials such as Si, SiC, Ge, GaAs, CdS, CdSe, and ZnTe51,46–48,64,65 (Fig. 1d) – our demonstration achieves a higher on/off ratio and features a distinct three-terminal transistor implementation with gate-controllability.

Leveraging this high-performance programmable NDR, we propose a cryogenic neuromorphic computing architecture (Fig. 1f). We can build three types of neuromorphic units: (1) sensory neurons as input units, (2) spiking logic gates, and (3) integrate-and-fire neurons based on the NDR in SiC MOSFET. We thus establish a high-performance and versatile neuromorphic hardware platform at cryogenic temperatures.

Sensory neuron

Biological sensory neurons convert external stimuli like light, sound, and touch into impulses that are sent to the central nervous system. In our neuromorphic architecture, sensory neurons are used as input interfaces for subsequent stages in the circuit. We demonstrate programmable sensory neurons using the gate-controlled NDR (Fig. 2a and Supplementary Fig. 13). The main idea is to initiate spikes in the output according to the input voltage V mimicking the basic function of biological sensory neurons. The circuit implementation involves a resistor (R ) and a capacitor (C) to achieve a charging-discharging cycle between the resistance region at low current levels and the NDR regions.

Two processes govern the spiking behavior in this circuit (Fig. 2b). First, the circuit node at Drain of the SiC MOSFET is charged by a current I , showing a slowly rising output voltage, V . The time to reach the NDR threshold voltage V , is determined by V , R , and C. Second, the NDR characteristic of MOSFET initiates the discharging of capacitor C, resulting in a fast-falling voltage at the output. This process ends when the drain voltage is below the lower threshold voltage V . We note that the difference between V and the minimum voltage of V is due to the presence of resistor R (Supplementary Note 7), which is the resistance of cables from the cryogenic plate to our measuring point at room temperature. R also determines the discharge current I from capacitor C. To have continuous spiking processes, two requirements must be satisfied: (1) I must be within the NDR region, i.e., 50 μA to 100 mA, and (2) I , must reach the high current positive resistance region (> 100 mA).

Figure 2c shows output waveforms with five sections of the enabled/disabled periods, demonstrating controllable and repeatable sensory neuron behavior on the millisecond timescale. The spiking rates for the first and fifth sections are 42 kHz and 47 kHz, respectively, accompanied by a discernible decrease in the peak-to-peak oscillation voltage. This phenomenon could be attributed to a temperature-induced dynamic shift in V (Supplementary Fig. 17). Notably, the observed increase in spiking rate and the reduction in voltage effectively mimic the adaptation process found in biological neurons66,67, adding more neuromorphic features to our circuits. The spiking rate can be configured by adjusting the circuit parameters V , R , and C (Fig. 2d). Increasing V results in a higher spiking rate due to a larger charging current. Meanwhile, the overall sensitivity of the neuron is determined by the R /C ratio. For example, a smaller resistance R of 9 kΩ and capacitance C of 10 nF yields a higher spiking rate than alternatives such as 9 kΩ/101 nF and 91 kΩ/10 nF.

Spiking logic neuron

Logic gates, as fundamental components in digital circuits, provide essential computational capabilities. Here, we demonstrate logic neurons in spiking neuromorphic circuits based on the NDR devices (Fig. 3). The logic neurons can take multiple asynchronous inputs and generate an output spike conditionally, following the truth table of corresponding logic gates (Fig. 3a). We note that these inputs are implemented as time-domain pulses at different windows (Window 1 and Window 2) applied sequentially to a single physical input terminal; thus, the logic operation is based on the integration of these temporal events. Asynchronous input spikes charge the STATE circuit node (electronic charge is held by capacitor C ), and the accumulated inputs are then processed when the NDR device is activated by a trigger signal. The voltage of the trigger signal defines the logic, for example, OR and AND gates (Figs. 3b and 3c). The STATE node discharges only when two conditions are met: (1) a gate control signal (trigger signal) is applied, and (2) the device voltage (V ) exceeds the threshold V , which itself is controlled by the gate voltage. The voltage drop of the STATE node initiates the discharge of C through R and D /R , resulting in a negative voltage spike measured at the output.

We define logic-0 and logic-1 inputs as the absence and presence of spikes, respectively (Figs. 3d-3f). Here, we use 14-V 100-µs spikes as proof of concept; however, the device unit can accept shorter or longer spikes with correspondingly higher or lower voltages, and the capacitor C determines the total electronic charge needed for a logic-1 input. A single input spike charges the V to approximately 4.7 V, and two input spikes raise it to 7.7 V. To execute an OR gate operation, we apply a trigger signal with V = 18 V, which results in a lower threshold voltage V below 4.7 V. Thus, as long as there is a logic-1 input, the output spike will be triggered (Fig. 3d). For the AND gate operation, we apply a trigger signal with V = 8 V, which results in a higher threshold voltage V = 4.8 V. When there is none or just one input spike (none or only one input is logic-1), no output spike occurs, representing a logic-0 output (Fig. 3e). Only when there are two input spikes (logic-1 in both windows), an output spike is triggered, representing a logic-1 (Fig. 3f).

Integrate-and-fire neuron

Integrate-and-fire is a critical component of neuromorphic circuits, offering great promise for applications in analog computing and spiking neural networks. We demonstrate two types of integrate-and-fire neurons with different input/output polarities (Fig. 4 and Supplementary Note 8), allowing efficient analog cascade between neurons. The positive integrate-and-fire (P-IF) neuron accumulates positive input spikes and outputs a negative spike (Figs. 4a–4c). A constant 18 V V is applied to the gate. Input spikes sequentially charge the V node until it reaches the threshold, triggering the discharge process and producing a negative output voltage across R . In the example shown in Fig. 4c, five 12.5 V input spikes with different widths are applied, and the output spikes are at the fifth spike. The triggering threshold and output spike amplitude can be configured through input spike characteristics (e.g., voltage, width), circuit parameters (R -R ,C ), and the control voltage (Supplementary Fig. 19).

The bidirectional nature of the proposed NDR enables implementation of negative integrate-and-fire (N-IF) neurons, which take negative-voltage spikes as inputs and generate positive-voltage spikes as outputs (Figs. 4d-4f). At the circuit level, the orientation of the diodes in N-IF is flipped compared to that in P-IF, which allows accumulations of negative inputs. The N-IF process involves a sequence of negative input spikes and a triggered positive output at the fifth input spike, producing a peak voltage of 0.9 V (Fig. 4f).

Cascade of negative differential resistance-based neurons

Efficient cascading between neurons is crucial for large-scale cryogenic neuromorphic circuits. Leveraging the unique bidirectional NDR, we demonstrate cascaded circuits by connecting P-IF and N-IF neurons alternatively (Fig. 5a). We note that a buffer amplifier (Supplementary Fig. 14) is used in this proof of concept, allowing us to wire out the signal to room temperature for measurements, and could be eliminated by integrating all components on a cryogenic circuit board. Figure 5b shows the waveforms of input spikes, the state voltages for the first-stage P-IF neuron (V ), the second-stage N-IF neuron (V ), and the output signals. With the 10-V input spikes charging V , after six input spikes, the output spike of the first stage is triggered. As input spikes continue, the output of the first stage is also triggered regularly. The output of the first stage charges the second-stage neuron. At the 45th input spike, the output of the second-stage neuron is triggered, and subsequent outputs are also triggered periodically, demonstrating a stable operation.

Energy consumption analysis and integration pathway

As a proof-of-concept demonstration using discrete electronic components, we employ the SiC MOSFET with a relatively large current rating and thus a large footprint of ~ mm2. The sensory neuron consumes an energy of 76 nJ per spike during stable cycling, the spiking logic neuron consumes 620 nJ per operation (with a 100 μs trigger time), and the IF neuron consumes 24 nJ per spike. Details of energy consumption estimation are provided in Supplementary Note 9 and Supplementary Fig. 21. Towards a monolithic platform of our technology, we projected the energy consumption to a device with an active area of 1 μm2, compatible with standard SiC fabrication processes. Under this scenario, the energy consumption per spike is reduced to 42 fJ, 335 fJ, and 13 fJ, for sensory, logic, and IF neurons, respectively. Benchmarking against existing cryogenic platforms confirms that these energy densities are competitive with state-of-the-art CMOS and memristive technologies (Supplementary Fig. 22, Supplementary Tables 1 and 2).

The pathway to large-scale integration also involves monolithic fabrication of both active and passive components on SiC. The active elements—NDR device, MOSFET, and diode—are inherent to the SiC platform. For passive components, we consider integrating thin-film resistors (e.g., NiCr or TaN) and high-dielectric-constant Metal-Insulator-Metal (MIM) capacitors (e.g., HfO ) directly on the chip to ensure stability at millikelvin temperatures. Our analysis estimates that a fully integrated, scaled IF neuron would occupy a footprint of ~230 μm2 (Supplementary Table 3), paving the way towards a realistic solution for high-density cryogenic neuromorphic computing.

Methods
Device structure

The vertical SiC MOSFET features a gate-modulated vertical current flow from the bottom drain to the top source terminal under a positive V (Fig. 1a). Current conduction is controlled by the gate-source voltage, which governs the formation of an inversion-type carrier channel in the p-type region beneath the MOS gate. Additionally, an accumulation-type carrier channel can also be formed between the MOS structure and the n-type junction gate field-effect transistor (JFET) region. The MOS structure comprises a 0.2-µm-thick poly gate, 0.02-µm-thick silicon oxide, and a 0.9-µm-thick p-type region (see Fig. 1a). A 6-µm-thick lightly doped n-type drift region and a 0.6-µm-thick p-well region form a pn junction, designed to block high voltage when the device is in the off-state. This device has a voltage rating of 650 V, capable of blocking over 900 V at room temperature.

Cryogenic measurements

The cryogenic measurements were conducted using a cryogen-free Bluefors LD250 dilution refrigerator, capable of reaching a base temperature of 10 mK. The schematic of the experimental setup is shown in Supplementary Fig. 1. The device under test (DUT) was mounted on a custom-designed printed circuit board (PCB) and secured to the mixing (mK) plate with thermal paste to ensure efficient thermal conductivity. For high-power signals at the drain and source terminals, a Kelvin connection scheme was employed, separating high-current force lines from sense lines for precise voltage measurement (Supplementary Fig. 2). This configuration effectively mitigates parasitic effects arising from long cabling within the refrigerator system. The gate signal, being a low-current signal, was transmitted via a single cable for both control and measurement. These signals were interfaced with both dynamic and static measurement systems as required for specific tests.

Static and dynamic measurements

The static characteristics of DUT were measured using a power device analyzer (Keysight B1505A). This system is equipped with multiple source measurement units (SMUs) capable of handling high voltage and current ranges, adjustable pulse widths, and offering high-resolution accuracy. The high-power SMU (HPSMU) was utilized for on-state current-voltage (I-V) tests. A current sweep mode was employed to characterize the NDR performance, covering a range from ±1 nA to ±1 A with automatically adjusted resolution for each measurement range (Supplementary Fig. 3). All signals were connected to the B1505A via Kelvin connections.

Dynamic measurements encompassed single-pulse tests (SPT) and the demonstrative tests for three neuron types. The SPT approach was used to overcome the current range limitations of the static tests on the power device analyzer, enabling measurements for currents exceeding 1 A. Supplementary Fig. 4 shows the circuit schematic and switching waveforms for the SPT setup. To achieve a linearly increasing current, a load inductor (L) was placed in series with the DC power supply (V ) and the DUT. When the DUT was switched on, current flowed through the inductor and DUT; any remaining current was then conducted by the free-wheeling diode (FWD) once the device was turned off. Current was precisely measured using a serially connected 0.1 Ω coaxial shunt resistor (SSDN-10), chosen for its low parasitic parameters and suitability for high-frequency current measurements. Output signals from the shunt resistor and device voltage from the sense line were connected to an oscilloscope (R&S RTA4004), featuring a high sampling rate (5 GSa/s), via BNC coaxial cables. Gate signals were generated by a commercial gate driver IC (Si8271), which isolates and amplifies input signals (0-5 V) from a function generator to the desired gate driving voltage (-5 to 20 V) for the SiC MOSFETs. By plotting the current-time (I-t) and voltage-time (V-t) waveforms concurrently, the relationship between voltage and current was clearly illustrated (Supplementary Fig. 5c). The custom-designed motherboard (Supplementary Fig. 5b) was situated outside the refrigerator, with all signals connected to the DUT inside via coaxial cables, adhering to the Kelvin connection principle. Similarly, all electrical components for the neuron demonstrations were mounted on a dedicated demonstration board outside the refrigerator, with control signals generated by additional driver IC circuits.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This manuscript reports the discovery of a gate-controlled negative differential resistance (NDR) effect in foundry-available\nsilicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) when operated at cryogenic\ntemperatures. The NDR originates from an electron-donor impact ionization (EDII) process involving the two distinct nitrogen\ndopant energy levels intrinsic to 4H-SiC. This is fundamentally different from thermally induced NDR and results in a highly\nstable, bidirectional, and gate-voltage programmable S-type NDR characteristic. The NDR exhibits an unprecedented on/off\ncurrent ratio of up to 10^7, which is the highest reported for any NDR device. It also operates over a wide voltage range (4.2\nV to 2.4 V) with low leakage current. Leveraging this gate-controlled NDR, the authors demonstrate three fundamental,\nprogrammable neuromorphic building blocks using a single transistor as the core active element: a sensory neuron, spiking\nlogic gates (OR, AND), and both positive and negative integrate-and-fire (I&F) neurons. They successfully cascade these\nneurons to show the potential for more complex networks.\nTo my knowledge, this is the first demonstration of a gate-controlled, three-terminal NDR device in a wide-bandgap\nsemiconductor (SiC) at millikelvin temperatures. The use of a mature, foundry-fabricated SiC power MOSFET as the\nfundamental neuromorphic element is a highly innovative approach. The work addresses a critical bottleneck in scalable\nquantum computing and space electronics: the need for ultra-low-power, high-density control and readout electronics that\ncan operate at the same cryogenic temperatures as the quantum processors or sensors. By providing a pathway to build\ncomplex neuromorphic circuits with industry-standard, manufacturable devices that exhibit excellent uniformity, this work\nrepresents a significant leap towards practical large-scale cryogenic systems. I strongly recommend this work.\nStill, I have a few comments and suggestions for the authors to improve their manuscript:\n(i) The manuscript excellently characterizes the performance metrics of the NDR effect (on/off ratio, leakage current, voltage\nrange) but does not explicitly quantify the energy efficiency of the demonstrated neuromorphic foundation cells (one\ndefinition of foundation cell: https://www.nature.com/articles/s44287-024-00106-w). Given that the primary motivation is\noperation within a millikelvin fridge with limited cooling power (~sub-mW), a discussion on energy consumption is critical.\nThe authors should estimate and report the energy per spike for the sensory and I&F neurons under the various operating\nconditions shown. This would allow for a direct comparison with other cryogenic computing paradigms and clearly highlight\nthe potential energy advantage of this approach.\n(ii) The demonstrations are highly compelling but currently rely on discrete passive components (resistors, capacitors,\ndiodes) located on room-temperature circuit boards. For the claim of \"large-scale integration\" to be fully convincing, the\nauthors should address the practical pathway to cryogenic integration. A brief discussion is needed on the following:(a) Is\nthe plan to integrate these passive components onto the same SiC MOSFET chip or application-specific integrated circuit\n(ASIC) alongside the SiC MOSFET chips? The authors should comment on the feasibility of cryogenic-compatible passive\ncomponents. (b) While a single transistor per neuron is excellent, the total area footprint may be dominated by these passive\ncomponents. The authors should provide an estimate of the area a single I&F neuron would occupy in an integrated system\n(including the SiC transistor and the necessary capacitors/resistors), and how this compares to other cryogenic neuron\nimplementations. This is crucial for assessing the true scaling potential.\n(iii) The manuscript mentions potential in \"quantum information applications\" and \"space exploration\" but does not provide a\nconcrete example. To strengthen the impact, the authors should briefly describe at least one specific application scenario.\nThis would help readers vividly envision the practical utility of this technology.", "reviewer_2": "The manuscript presents a concept for a SiC-based device aimed at neuromorphic computing under cryogenic conditions.\nThe topic is relevant to the development of energy-efficient computing in quantum and cryogenic environments. However, in\nits current form, the paper lacks sufficient clarity and quantitative benchmarking to convincingly demonstrate the advantages\nof the proposed device. The following points should be carefully addressed to strengthen the manuscript:\n1. The motivation for implementing neuromorphic computing at cryogenic temperatures should be more clearly articulated. In\nthe introduction, the authors claim that “no fundamental device technology to date has met all these criteria…”, yet it remains\nunclear how the proposed SiC-based device satisfies these criteria. The authors should explicitly explain the intended\napplication scenario and clarify what specific performance requirements are being addressed. It is also recommended to\ndiscuss recent progress on cryogenic Si-based FET memories for neuromorphic computing (e.g., Y. Han et al., Nano Lett.,\n2024, DOI: 10.1021/acs.nanolett.4c05855), and to highlight the distinct advantages, if any, of the present approach.\n2. For cryogenic neuromorphic systems, energy efficiency is of paramount importance. Given the wide bandgap of SiC, the\nrelatively high operating voltage reported in this work raises concerns regarding total power dissipation. The authors are\nencouraged to provide quantitative estimates of the energy consumption per operation and to discuss its relevance for\nintegration in large-scale cryogenic circuits.\n3. To contextualize the performance, a comparison with state-of-the-art cryogenic or neuromorphic device technologies is\nessential. Key parameters such as operating voltage, energy per operation, and operating frequency should be summarized\nand benchmarked. Without such comparison, it is difficult to assess the claimed benefits of the proposed approach.\n4. In Figure 3, the logic operation is insufficiently explained. It is not clear where Input 1 and Input 2 are applied in the circuit.\nMoreover, in Figures 3d–f, the inputs appear to be applied sequentially, while the truth table suggests simultaneous input.\nThis inconsistency must be clarified."}, "author_response": "We appreciate the comments from the editor and both reviewers, which we found very helpful to improve\nour manuscript. Here, we provide a point-by-point response to all the comments and make revisions in the\nmanuscript accordingly.\nBelow is a summary of major revisions and additions to our manuscript.\n1. Energy efficiency analysis: We estimate the energy consumption of our sensory, logic, and integrate-\nand-fire neurons based on a circuit model using the measured IV curve. Looking into future\ndevelopment, we project the energy efficiency and footprint to devices with an active area of 1 μm2,\nwhich we believe will be more ideal for developing neuromorphic circuits. Our analysis shows that the\nproposed approach is highly competitive with current state-of-the-art cryogenic platforms.\n2. Monolithic integration: We provide a detailed feasibility analysis for integrating active and passive\ncomponents on a monolithic SiC platform, including footprint estimation for a fully integrated neuron\nunit.\n3. Quantum application scenarios: In the revised manuscript, we include concrete examples of\napplications in quantum error correction (QEC) and real-time quantum control, highlighting the specific\nutility of our device in potentially overcoming the current \"interconnect bottleneck\" between quantum\ncircuits at mK and classical circuits at room temperature.\n4. Formatting: We reorganize the contents in Methods and Supplementary Materials for better readability\nand to match the journal format.\n[... full point-by-point response text omitted for brevity as per instructions to include verbatim text ...]"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors have addressed my comments very well.", "reviewer_2": "No further comments"}, "author_response": ""}]

Decision letter