Hundred-layer photonic deep learning

Domain: physics
Published: 2025-11-24
Editorial outcome: major_revision

Abstract
In the artificial intelligence era propelled by complex computational models, photonic computing represents a promising approach for energy-efficient machine learning; however, error accumulation inherent to the analog nature limits their depth to around ten layers, restricting advanced computing capabilities towards large language models (LLMs). In this study, we identify that such error accumulation arises from propagation redundancies. By introducing perturbations on-chip to decouple computational correlations, we eliminate the redundancy and develop deep photonic learning with a single-layer photonic computing (SLiM) chip that exhibits error tolerance. The SLiM chip overcomes the depth limitations of optical neural networks, allowing for error rates to be constrained across more than 200 layers, and extends spatial depth from millimeter to hundred-meter scale, enabling a three-dimensional chip cluster. We experimentally constructed a neural network with 100 layers for image classification, along with a 0.345-billion-parameter LLM with 384 layers for text generation, and a 0.192-billion-parameter LLM with 640 layers for image generation, all achieving performances comparable to ideal simulations at 10-GHz data rate. This error-tolerant single-layer chip initiates the advancement of state-of-the-art deep learning models on efficient analog computing hardware.

Introduction
Notable progress has been witnessed in the field of artificial intelligence (AI), primarily driven by the advancement of deep learning 1–4. It is known that by extending the depth of neural network layers and the complexities of the neural network structures, a renaissance of AI debuts, and large models are developed for generating contents close to human level 5–14. However, the ever-increasing demand for deeper models also exacerbates the speed and energy exhaustion on digital electronic computational devices, which are unfortunately reaching their extremes 15–18.

One promising route in the saturating digital intelligence era is physical intelligence, which computes with efficient physical media, including photonics, electronics, spintronics 19–28. Especially, exploiting the large bandwidth and high parallelism of optics, the optical neural network (ONN) is prosperous and has potential in high-performance AI computing. In free-space lens systems and photonic integrated circuits, the spatial and temporal computing approaches have yielded prototypes in linear ONNs 29,30, multi-layer all-optical ONNs 31,32, and optoelectronic nonlinear neural networks 33–36. These neural networks facilitate sequence 34,37, image 38–40, video 25,32, and three-dimensional (3D) volumetric scene 41,42 processing in the optical domain. Notably, based on the evolution of integration, the silicon photonic platform represents the most mature platform to be exploited to map neural networks for the processing of the signals intelligently 30,37,43–45. The large bandwidth of the silicon photonic chip proves an ideal analog machine learning module for high-speed signal processing in the radio frequency domain 46,47.

However, existing ONNs cannot achieve the deep structures necessary for the advanced AI tasks. The primary reason is that, due to the analog nature of physical computing, numerical errors accumulated during deep-layer propagation cause the computed results to deviate significantly from the ideal simulation (Fig. 1a, left). One solution is to reach precise numerical operations by carefully calibrating the transmission properties of the system 48, or by employing multiple steps for asymptotically approaching the high-precision results 49,50. However, these approaches would require extensive spatial and temporal overhead, proving infeasible for large models containing hundred layers and billion-scale parameters. In addition, even if these approaches improve the precision of system calibration, the inherent data noise in direct proportion to the input speed remains hardly compensated 51. As a result, it is still elusive to realize deep models with a high data rate based on existing analog computing methods.

Instead of striving for ultrahigh precision operations with the physical architecture, it is more practical to accommodate the errors as part of the ONN and tolerate these errors during the computing 52,53. Nonetheless, realizing an error-tolerant architecture remains technically challenging. Firstly, the spread and accumulation of the noise-induced error should be inhibited. Existing photonic chip designs utilizing the MZI mesh, cross-bar mesh, and diffractive meta-lines require multilayer propagation for one linear matrix-vector multiplication 37,54–56. The multi-layer structure inevitably exacerbates the issue of error accumulation. Also, the commonly used nonlinear layers like the rectified linear unit, sigmoid 57, or optical analog activation functions 33,34,58 are not resilient to the errors and amplify the noise with detection processes, which disseminates the errors to the subsequent layers. To achieve very deep neural network architectures, it would be necessary to minimize the error propagation and bound the error rate throughout the entire ONN.

Here we report a single-layer photonic computing (SLiM) chip that removes all the error-prone propagation layers, targeting ONNs with a hundred-layer depth working at tens of GHz data rate. To realize SLiM, we incorporate perturbations within the photonic chip design, which breaks the on-chip wavelength correlation to realize arbitrary matrices and decorrelates the signal from the error with the detection-based activation function. The single-layer photonic chip minimizes the error propagation and guarantees bounded errors regardless of the number of network layers, surpassing the depth limit (DL) of ONNs. The arbitrary error-tolerant computing with single-layer propagation and detection facilitates chip clusters with computational connections at hundred-meter spatial depth. Experiments were conducted at 10 GHz to build 100-layer residual network, classifying the full ImageNet-1000 (photonic accuracy 85.2%, digital accuracy 85.9%). Transformer-based error-tolerant ONN of 384 and 640 layers with billion-scale parameters (0.345B and 0.192B) were then experimentally evaluated to generate prompted language (photonic loss function value 3.04, digital loss function value 2.96) and conditioned image (photonic loss function value 7.32, digital loss function value 7.28).

Results
Errortolerancewithsingle-layerphotoniccomputing
Conventionally,implementingonelayerofONNon-chipconsistsofmultiplelayersofphysicalpropagationsandnonlinearactivations,whichisformulatedasY=f(L i=1 W i X)withX,Y,f,andW denotingtheinput,output,nonlinear,andpropagationlayers(Fig.1a,left).Takingtheper-layererrorintoaccount,thefinalerror-distortedisexpressedasY+ΔY=f(L i=1 W i +ΔW i)(X+ΔX),wheretherelativeerrorVar(ΔY/Y)L Var(ΔW/W),meaningthattheerrorisamplifiedbyafactorofLafterpropagation.Asaresult,theextralayers,includingthesecondtothefinallinearlayerandtheerror-pronenonlinearfunction,exacerbatetheerroraccumulation.However,inviewofthecomputation,theselayersareindispensableasthepropagationlayernumberLindirectproportiontotheoutputdimensionsMsupportsafullytunablematrixandthenonlinearlayersfacilitatetheneuronactivations.Here,weeliminatetheseerror-proneONNpropagationsandnonlinearlayersbyproposingaphotonicchipimplementingerror-tolerantmatrix-vectormultiplicationswithonlyasinglepropagationlayer,achievingboundederrorevenwhendeeplyconcatenated(Fig.1a,right).Thedetailederrormodelispresentedin[SupplementaryNote1TheerrormodelofONN].

AsillustratedintheFig.1b,inSLiMchip,theinputsxiareassignedtospecificwavelengthsλi.Multi-wavelengthlightismultiplexedintoasinglefiberchannelandcoupledintoaninputloadingchipfortheconfigurationofinputsxiontocorrespondinglightintensities.TorealizethecomputingmatrixW,thetransmissionchannelsaremodulatedonchipbyexertingwavefrontΦ,derivedfromtheequationW=|GΦ|2,whereGrepresentschip-to-chippropagation.However,becauseofthespectralproximity,thewavefrontΦandthetransmissionmatrixGbothexhibitahighcorrelation,resultinginlineardependenceontherighthandsideoftheequationthatdoesnotguaranteeasolution.Weintroduceon-chipperturbativenoisetobreakthecorrelation,mathematicallyrepresentedasΦ^k=Φk*ejn2πΔk/λi,whereksymbolizesthewaveguidecoordinatewithcorrespondingnoiseΔk.Thelinearlycorrelatedequationsarenowreformulatedas

W=||GΦb||2,1≤i≤N (1)

ThesetincludesNlinearlyindependentequations,enablingtherealizationofarbitrarymatrices.InrealizationofthetargetweightmatrixW,themodulationwavefrontΦ^iisfirstsolvedwiththecalibratedpropagationmatrixG,afterwhichthecorrespondingmodulationcoefficientsareloadedontothesingle-layerchips.

Tofurtherprecludethedisseminationoftheseminimalerrors,itnecessitatesanonlinearfunctiontodecorrelatetheoutputerrorsfromthesignals.Theerror-isolatingfunctionfeatureszerogradientwithrespecttotheerror,∂f=0.However,thesolutionseasilydegeneratetotrivialconstant-valuedfunctions,nullifyingthecontributionsofsubsequentlayer.Weinjectnoisetothegradientsothatsignaldiversityismaintainedwhiletheerrorsareonlytransmittedtothesubsequentlayerthroughfinitepositions.ThesolutionRcanbeformulatedastheKroneckerdeltafunctionthroughf=δ(x*Δf),whereΔfrepresentsthenoisepositioninthenonlinearfunction.Note,thatthisactivationfunctioncanbeimplementedatthedetectionwiththeanalog-to-digitalconversion(D),byassigningtheerror-distortedvaluestothenearestsignallevels.AsanillustrationinFig.1b,withsingle-layercomputing,despitetheinputerrors,fluctuationofthepropagationisminimizedandtheoutputsarethenpushedtowardsthecorrectlevels.ItcanbetheoreticallyprovedthattheproposedSLiMconstrainstheerrorratebyadheringtothefollowinginductiveerrorboundingcriterion,

E((W+ΔW)(X+ΔX))≤E0,ifE(X)≤E0: (2)

AnalysisshowsthattheSLiMcouldtolerateinputerrorwithstandarddeviation(Std)ashighas44%([SupplementaryNote3Error-boundingwithSLiM]).WeadoptedtheinjectedpropagationnoiseaskΔdforΔk,andΔd=20μmshowedthelargestrankforthe256elementsonchip,whichwasselectedforphotonicchipfabrication.TheinjecteddetectionnoiseΔxisdata-dependentanddeterminedduringthetrainingprocess.Thedetailsofthechipsareprovidedin[Methods “Implementationofsingle-layerchips”].Fordetailedderivationspleasereferto[SupplementaryNote1TheerrormodelofONN]and[SupplementaryNote2FormulationsoftheSLiM].

Thesingle-layerphotonicchipsliftthecomputationaldimensionfromon-chipcomputingtochip-to-chipconnections,suchthatlargenumbersofphotonicchipscanbeconnectedtocomputeinthe3Dspacetoexecutebillion-parameterlargemodels(Fig.1c),whichenablestheadvancedAItasks,includingtextcompletion,imagerecognition,andimagegeneration.

Deepmatrixmultiplicationwithsingle-layercomputing
WefirstconfirmthatperturbationinjectionoftheSLiMchipfacilitatesmatricesofanysizewhileenablingfullDOFs,whichisessentialforachievingerror-tolerantmatrix-vectormultiplication(refertoFig.2a).Thephase-voltagedynamicsinfluencedbyperturbationaremeasured(Fig.2b).Leveragingthesymmetricstructureofthedesignederror-tolerantchip,ananalysiswasconductedon128spatialwaveguidechannelsusingdrivingvoltageswith0-4Vmodulationrange.Fourdistinctwavelengthsarehighlighted,eachdemonstratingrandomstartingphasesacrossbothspatialandspectraldomains.Toillustratethedecorrelatedtransmissionproperties,matriceswerecreatedusingone-hotvectorsderivedfromthewavelengthchannelsat1530,1540,1550,and1560nm.InFig.2c,thefirstrowshowcasesexample[e2,e1,e4,e3],whereeisymbolizesthevectorwiththeithwavelengthactiveandtheothersnullified.Theentriescanbereconfiguredflexibly,withthefinalrowrepresentedas[e3,e4,e1,e2].Theaverageratiosofactivetoinactivestatesweredeterminedtobe215.16insimulationsand244.32inexperimentalconditions.Thisindependentpropagationmakesitpossibletoimplementmatriceswithdiversesizesandvalues.AsillustratedintheuppersectionofFig.2d,variouscombinationsofinputsizesandoutputchannelnumbersweretested,witheachiterationfocusingon100randommatrixsamples.ThematricesdisplayingfullDOFswereextractedanddisplayedinthelowersectionofthefigure.Bygraduallyincreasingtheinputsize,thenormalizedmeansquareerror(NMSE)recordedwerefoundtobe0.41%(withinputsize2)/0.46%(withinputsize4)/0.25%(withinputsize8)/0.03%(withinputsize16),respectively.Incontrast,theNMSEsrosesignificantlyto4.59%/5.77%/11.22%/17.57%withouttheperturbationincorporation.

Toexperimentallyassesserrortolerance,weconfiguredtheoutputchannelnumberas8andexaminedallpossible256occasions.Thefindingsindicatemaximummeanerrorbeing0.16%(Fig.2e).Additionally,weevaluatedtemporalstability.During10-hourmeasurements,themeanerrorofWforthe8-dimensionaloutputsstayedlessthan1.0%,withhighestabsolutedeviationbeing0.90%(Fig.2f).ToverifyerrorboundingcriterionofEq.(1),weexaminedthemultiplicationerroracross200layersbyemployingtheperturbedpropagationsanddetections.TheresultingerrorrateswereanalyzedundervaryinglevelsofGaussiannoiseΔXat5%/10%/20%(Fig.2g).Incontrasttotheperturbedsingle-layeroutcomes,themulti-layerresultswithoutperturbationprogressivelyworsened,ultimatelyhitting41.5%/48.8%/50.7%duetoerroraccumulation.Meanwhile,theerrorsfromsingle-layermultiplicationremainedbelow0.76%/33.5%/44.5%.Thepeakerrorratesassociatedwithdistinctsystemnoiselevelswerecalculated(Fig.2h),wheretheerrorratewithmulti-layerphotoniccomputingreached50%oncethenoiselevelexceeded6.5%standarddeviation,indicatingthatperformancedegradedtorandomguessingunderhigh-speedconditions.Incomparison,theerrorsE0resultingfromerror-tolerantmultiplicationswereeffectivelyconstrainedbelow33.5%/41.3%/44.5%acrossnoiselevelsof10%/15%/20%standarddeviationover200layers.Statisticalassessmentscorroboratedbyproofin[SupplementaryNote3Error-boundingwithSLiM]indicatethatastandarddeviationof44.3%intheinputsleadstoa47.1%errortoleranceinthenetwork,whichalignswiththetheoreticallimitof50%random-guesserrortolerance.Theimplementationofsingle-layercomputingoperationsthusfacilitatesthefunctioningofdeepONNs.

Deepsingle-layercomputingbeyondthespatialdepthlimit
TheinterchipcomputingofSLiMscanbeinterconnectedtocreateanexpansiveONNchipcluster(seeFig.3a).Herewedemonstratethesechip-to-chipconnectionscanspandistancesrangingfromcentimetersuptohundredsofmeters.BycombiningKchipsintoasingleunit,theDOFsincreaseK-fold,andthespatialdepthcanfurtherextendtokilometers,makingitfeasibletodevelopanONNchipclusterwith3Dcomputationalconnection.Forillustration,atwo-layerONNwasdevelopedtoclassifytheMNISTdatasetasameansofassessingthespatialcapabilitiesoftheerror-tolerantcomputingconfiguration([Methods “Datasetpreparation”;Methods “Networkarchitectureandtrainingmethods”]).Thisexperimentalsetuputilizedfiverelaystoextendthetransmissiondistancebetween0.1and45m(Fig.3a,rightandFig.S2;[Methods “SpatialdepthofSLiMcomputing”]).Theneuralnetworkfeaturedinputsandhiddenneurons,bothwith64dimensions.InFig.3b,weinvestigatedtheclassificationaccuraciesatvariousreceiversizes,withfourdetectorsevenlydistributed.Foraccuracyratesabove95%,theupper(andlower)thresholdswere8m(0.02m)/28m(0.8m)/80m(2.5m)determinedbasedon5,20,and70mmaperturesizes.Furthermore,Fig.3chighlightsresultsfromthreeexperimentatspatialdepthsof0.1m/5m/45m,achievingaccuraciesof95.75%/95.76%/95.53%,whichareclosetothesimulatedaccuracyof95.78%.ItisimportanttonotethatthefindingsinFig.3b,c,areconstrainedbythespatialpropagationdepthlimitationsassociatedwithindividualchips.ThespatialDLisdefinedbytheequationDL=D inD out/λ,whereDin,Dout,andDLrefertotheinputaperture,outputaperture,andthespatialDL,respectively.Forthethreeaperturesizes,thespatialDLswerecalculatedtobe17,65,and230m.Whenthetargetdetectorsareevenlyspacedwithinthereceiveraperture,theeffectivecomputingdepthwiththe4-DoutputisexpectedtobeathirdoftheDLs(5.7,21.7,and76.7m,Fig.3b),aligningwellwiththeeffectiverangesidentifiedduringclassificationtests(8,28,and80m).

SincetheSLiMoperateswithspatial-spectralpropagation,itfacilitatestheintegrationofmultiplechipstoperformcomputationaltaskswithgreaterDOFsandextendedoperationalrange.AsillustratedinFig.3d,inputscanbeloadedontonumerouschips,whichareinterconnectedandfunctionasasinglecomputationalunit.BycombiningKchips,theDOFsincreasebyafactorofK,resultinginatotalcomputingcapabilitythatisKtimesgreater.TheuppersectionofFig.3ddisplaysanensemblecomprising16chipspost-fabricationandpackaging,withinter-chipgapsof30mm.Consequently,thecumulativeDOFsrise4096,resultinginacomputingperformanceof335.54PetaOPS.Spatialpropagationdepthwasalsoenhancedbyoptimizingtheemissionapertureviaatunableconfiguration.ThediffractionresolutioncanbeexpressedasDL=EDinDout/λ,whereErepresentsthetunableenhancementfactor,whichcanbeadjustedbymodifyingtheinter-chipdistance(H).Byassembling2/4/8/16chips,theclassificationaccuraciesimprovedto85.27%/94.67%/95.34%/95.78%,respectively(Fig.3e).Thetunableensembleincreasedtheaccuraciesfurtherto93.80%/95.78%/95.78%/95.78%,witheffectivelysurpassingthelimitationsofasinglechip’sperformance.Thisframeworkcanfurthersupportkilometer-scaledistances,accommodatingmillionsoferror-tolerantchips.

ReachingONNsbeyondthedepthlimitforadvancedartificialintelligence
Theerror-tolerantSLiMcomputationalpropagationswerethenintegratedtoformdeepONNswithover100layers(seeFig.4a).Fordemonstrationpurposes,wecreateddeepnetworksaimedatimageclassificationusingthefullImageNet-1000dataset([Methods “Datasetpreparation”;Methods “Networkarchitectureandtrainingmethods”]).Botherror-tolerant(single-layercomputing)andnon-error-tolerant(multi-layercomputing)ONNswithresidualconnectionsweredevelopedatdepthsof18/34/100layers,withdetailedstructuralinformationoutlinedinFig.S3.Figure4billustratestheparameterconvergencefortheerror-tolerantONNswithdownsamplingforvisualization.Toassesserrortolerance,varyinglevelsofnoisewereintroducedasthelayerdepthincreased,andtheclassificationaccuraciesundertheseconditionsarepresented(Fig.4c).Inascenariowithoutnoise(wherenoise-distortedlayerswereconfiguredtozero),bothsingle-layerandmulti-layernetworksobtainedtop-5accuraciesashighas85.9%and93.0%,respectively.However,when5%-StdGaussiannoisewasintroduced,theaccuracyofmulti-layernetworksplummetedto37.0%.Increasingthenoisestandarddeviationto10%/20%furtherreducedtheiraccuraciesto2.2%/1.2%atthe2nd/10thlayers,respectively.Incontrast,thesingle-layernetworksexhibitedaccuraciesof85.5%/85.6%/81.2%.Notably,asignificantdeclineinaccuracyforthesingle-layernetworksto16.4%wasonlyrecordedwhenthenoisereacheda50%standarddeviation.

Utilizingerrortolerance,weassessedtheperformanceofthedevelopeddeepONNsathighspeeds.Intheexperiments,theoperationsinONNweredecomposedto8×8matrixcomputations,withinputsbeingloadedontoan8-channelinputarraybeforebeingsettothetransmitterarray([Methods “DeepneuralnetworkwithSLiMchips”]).FigureS11illustratesthemeasuredhigh-speedcharacterizationwitheyediagrams,coveringfrequencyrangesfrom1to10GHz.FromFig.4d,weobservethattheerror-tolerantONNswith18/34/100layersoperateat1/5/10GHz,stablyachievinghighaccuraciesof80.9%/83.8%/85.9%and80.7%/83.8%/85.7%atthe1and5-GHzsettings,respectively.Evenatthemaximumspeedof10GHz,theaccuraciesremainedrelativelyhighat80.4%/83.2%/85.4%,showingonlyaslightdeclinebyupto0.48%fromtheidealsimulations.Incontrast,themulti-layerONNsexperiencedsignificantperformancedegradation,recordingaccuraciesofonly3.6%/10.6%/15.5%at1GHz,withfurtherdeclinesto0.58%/1.2%/1.4%and0.46%/0.62%/0.34%at5and10GHz,respectively.IntermediateactivationresultsareprovidedinFig.S3.TheerrorevaluationthroughouttheentiredeepONNindicatedthattheanalognoiseatthehighestfrequencyof10GHzisequaltoGaussiannoisewithStdsrangingfrom20to50%.Thisnoisecouldbeeffectivelymitigatedinthesingle-layerphotonicchip.

ToillustratetheSLiMchipsinlargerAImodels,wedevelopeddseveralvariationsofONNmodelsakintoGPT(generativepretrainedtransformer),featuringparametersof5million/30million/60million/0.117billion/0.345billion,whichcorrespondtonetworkdepthsof8/16/32/48/96layersandtheerror-tolerantmatrixmultiplicationswereemployed(Fig.S4, [Methods “Datasetpreparation”;Methods “Networkarchitectureandtrainingmethods”]).Figure5apresentstheexperimentaloutcomesfrom356tokensamplesfromtheevaluationdataset([Methods “DeepneuralnetworkwithSLiMchips”]).Asthemodelsizeincreased,theaverageloss(withstandarddeviation)decreasedfrom4.91(0.4108)forthe5-million-parametermodelto4.10(0.4844)/3.72(0.4950)/3.34(0.5753)/3.04(0.5864)forthe30-million/60-million/0.117-billion/0.345-billion-parametermodels,respectively.Concurrently,thetokenpredictionaccuraciesimprovedsignificantly,risingfrom28.58to34.51%/37.29%/40.14%/43.92%.Tofurtherassessthepredictableperformanceenhancementsrealizedbyenlargingthemodelsize,weexaminedthetrendofthescalinglaw.Wespecificallyfittedthenumberofparameters(inmillions)andtheircorrespondinglossvaluestothefunctionL=βN-α.TheanalysisrevealedastrongPearsoncorrelationof0.9956,withparametersβas5.97andαas0.116.Wealsoprovidedstandardinputpromptsthatwerenotincludedinthetrainingortestingdatasetstothelanguagemodel,whichinturngeneratedhuman-likeresponses(Fig.5b).Ateachgenerationstep,theerror-tolerantsingle-layerchipsproduceatokenpoolwithtop80%probabilitythreshold(highlightedingreen)andatokenwasgenerated.Thefullsentencewasconstructedbasedonfourrecursivegenerations.Theoutputtokencloselymatchedtheidealsimulations,displayingonlyminorvariationsinindividualprobabilities.FigureS4providesacomprehensiveoverviewoftheparametersinthewholenetworkalongwiththeintermediateactivationsforthetestedsentences.

Anerror-tolerantSLiMmodelcontaining16blocksand64layerswasthendevelopedtoproduceconditionalimageseachwith256×256pixels,utilizingtheImageNetdatasetfortraining(seeFig.S5).Afterthetrainingphase,theerror-tolerantchipsgeneratedimagesacrosssixcategories(Fig.5c).Intheexperiments,theerrorratesremainedwithin37.2%/38.6%/40.2%/38.8%/42.1%/39.1%forthesecategories(Fig.5d).Fortheassessmentofthefidelityofthesegeneratedimagesagainsttheactualdataset,werandomlyevaluated24,000imagesfromthetrainedmodelacrossthreenoiseconditionsnumerically:zero,0.2-Std(akintothenoiselevelobservedfromthe10-GHzexperiments,[SupplementaryNote3Error-boundingwithSLiM],Fig.S3),and0.5-Std(stronglydistortedinputs).Followingstandardprocedures,FID(Fréchetinceptiondistance)featureswith2048-Dwerecomputedforeachinputimage.WethencomparedtheaveragedfeaturesexhibitingdifferentnoiselevelstothosefromtheactualImageNetdataset.Theaverageerrorsforthemodelswithzeronoiseand0.2-Stdnoisewere0.019/0.012,withStdsof0.027/0.028,respectively(Fig.5e).Incomparison,themodelwith0.5-Stdnoiseshowedalargeraverageerrorof−0.078withaStdof0.089.Thisindicatesthatwhiletheoutputsfromthenoise-freeandlow-noisemodelsremainclosetotheidealsimulation,theabsenceoferrortoleranceresultsinsignificantdivergenceinoutputfeatureswhenhighernoiselevelsareencountered.

Methods
Implementationofsingle-layerchips
Chipfabrication.TheSLiMchipsweredesignedandproducedusingasilicon-on-insulatorplatformtoshowcasetheircapabilitieseffectively.Theprimarysingle-layerchipintegratedbothtransmitterandemitterfunctions,servingacriticalroleinpropagation-baseddataprocessing.Lightwasinputthroughwaveguideedgecouplers,thensplitviamultimodalinterferometersandsubsequentlyroutedtoa256-elementarray.Duringthepropagationofsignalsonchip,dispersiveperturbationwasintroducedbyprogressivelyextendingguided-wavestances.Thermal-opticalphaseshiftersenabledindependentphaseadjustmentsforeachelementinthearray,withroutingmadepossiblebyagratingcouplerarray.Thereceivercomponentcomprised256on-chipgermaniumphotodiodes,eachindividuallyconnectedtotheprintedcircuitboard(PCB).ThecircuitdiagramoftheSLiMchipisdisplayedinFig.S14.Aseparatelow-powermodulatorchipwasfabricatedusingthesameprocess,whichfeaturedan8×8transmitterarray.Eachmodulatorwasdesignedasanall-passcarrier-basedringstructureassociatedwithanemissiongrating.Tooptimizetheefficiencyofphasemodulationwhileminimizingenergyconsumption,themodulatorsoperatedinanover-couplingmode.Theinput-loadingchipincludedinterconnectedringmodulatorsarrangedinacascade,linkedthroughasharedbuswaveguide.Eachmodulatordemonstrateda3-dBbandwidthexceeding35GHzasconfirmedbyprocesscontrolmonitoringassessments;however,duetothelimitationsofthetestingequipment,measurementsindicatedabandwidthofonly10GHz.Taperededgecouplerswereutilizedtofacilitateinputandoutputconnections.

Chip packaging. Electrical packaging. PCB boards were designed and manufactured to serve as the interface for the chip. By employing gold wire bonding technology, electrical connections were formed between the chip bond pads and the pins on the PCB board. This setup facilitated the interface for the 256-channel phase shifter and receiver array on each chip. Seven multichannel connectors (Samtec ERF8-040-05.0) were mounted on the PCB bottom layer to enhance electrical connectivity. The input-loading chip was wire-bonded onto a high-frequency PCB (Rogers RO3006) to minimize gold wire lengths and reduce parasitic inductance. This high-frequency PCB utilized a grounded coplanar waveguide structure to maintain a transmission line impedance of 50 ohms. Additionally, a grounding structure and shielding vias were incorporated between channels to ensure electromagnetic shielding. Multi-channel signals were subsequently interfaced through side-mounted high-speed connectors (Gwave SMA-KHD7) (see Fig. S8b). Die Bonding: the assembly of the PCB and metal substrate was secured using M2.5 screws. The error-tolerant chip and NTC thermistor were then affixed to the metal substrate with silver epoxy, finalizing the die bonding process after curing the epoxy at 110 degrees Celsius. Optical Packaging: for optical signal transmission, an 8-channel fiber array (FA) with a 127 μm pitch was employed, formed by fusing single-mode fibers with ultra-high numerical aperture (NA) fibers to convert the mode field diameter from 3 to 9 μm. The optical interface of the error-tolerant chip featured a 7-channel edge coupler array with pitches aligned to the FA. Straight waveguides were added on both ends, serving as the alignment aids, ensuring precise coupling between the error-tolerant chip and the FA through motorized 6-axis stages. The measured alignment loss between the chip and the FA was 3.1 dB per facet, and the FA was securely attached to the chip with UV curing. The input-loading chip utilized single-lensed fibers for edge coupling, resulting in an alignment loss of 1.5–2.0 dB per facet. Packaging was conducted using a 1550-nm light source. Thermal Control: to effectively manage heat dissipation, thermal silicone grease (Thermalright TF8) was applied to attach the Peltier cooler and heat sink fins to the metal substrate of the error-tolerant chip. The Peltier cooler and NTC thermistor (B3950 10K) were connected to a TEC controller, enabling precise temperature regulation through proportional–integral–derivative control. Furthermore, a fan mounted on the heat sink enhanced heat dissipation from the chip module.

Chip calibration. To evaluate the modulation characteristics of the phase modulation array, we implemented an on-axis interference system. As shown in Fig. S9a,b, the input laser beam was split using a fiber splitter, with one path directed to the chip and the other collimated to serve as the reference beam. The interference pattern resulting from this setup was captured using an infrared sensor (ARTCAM-991SWIR), as illustrated in Fig. S9c. We then applied a control voltage to each individual phase shifter, varying it from 0 to 4 volts. By fitting the resulting data to a sinusoidal function, as demonstrated in Fig. S9d, we extracted the initial phase values and the relationship between phase and voltage. The modeling of the modulators is based on the recognition that the phase shift, Δϕ, induced by the grating is influenced by the refractive index change, n, which is proportional to the applied voltage V from the Ohm’s law. This relationship can be expressed as Δϕ/Δn/ΔV2. Furthermore, the phase variation is related to the intensity of interference between the signal and reference beams, represented by a sinusoidal function. The detected intensity is parameterized as I(ϕ)=p1 sin(p2 V2+p3)+p4, where these four parameters, p1, p2, p3, p4 denote the signal amplitude, modulation coefficients, the initial phase, and background light, respectively. After measuring interference intensities at various voltages, an iterative fitting process employing the nonlinear least squares method was applied to determine all parameters, enabling us to calculate the phase terms from p2 to p3. This calibration process was conducted repeatedly for all wavelengths analyzed in the study using a tunable laser (TSL-570, Santec). The experiments spanned a wavelength range from 1480 to 1640 nm, with 10 nm step size to demonstrate performance across a broad spectrum. Modulation curves for 24 wavelengths spanning ITU channels C13 to C59 were measured for these experiments (as illustrated in Fig. S13). High-speed calibration to assess the on-chip signal quality across various input frequencies, we calibrated optical signals within the range of 1–10 GHz. A 25-GHz waveform generator (Keysight M8195A) produced non-return-to-zero signal sequences, which were fed into the ring modulator. Signal detection was performed using a germanium photodetector from an error-tolerant chip and a commercial InGaAs photodetector. The resulting photocurrents were recorded with a 10-GHz oscilloscope (Tektronix MSO64B). To ensure the modulator and detectors were appropriately biased, we employed 40-GHz bias tees (Anritsu K251) for high-speed signals transmission and detection. Figure S11 displays the eye diagrams obtained from the experiments. Both the on-chip photodetector and the germanium photodetector showcased distinctly defined open eye patterns at frequencies of 1, 5, and 10 GHz. However, at the frequency of 10 GHz, some distortion in the eye pattern was noted, which was due to the limitations of the testing setup. Nevertheless, the system effectively demonstrated signal transmission and detection capabilities up to 10 GHz. Following detailed bandwidth evaluations, deep neural networks were studied, designed for tasks including image classification and general-purpose generation (Figs. 4, 5 and S1).

Dedicatedcontrolboard
Todemonstratetheintegrationofcontrolanddetection-basednonlinearfunctionalities,wedevelopedaspecializedapplication-specificintegratedcircuit(ASIC)interfacethatlinksthemodulesandperformingthedetectionperturbationandperturbedweightloading.Uponreceivingsignals,ananalog-to-digitalconverter(ADC)transitiontheanalogsignalsintothedigitaldomain.Thedetectedsignalsaretheperturbedwithbiasesimplementedonboardwithparallelaccesstoregisters,effectivelyimplementingthenonlinearfunctionsandbypassingtheneedformemoryread/writeoperations.FigureS10presentsanillustrativeexampleofthepackagedchipfeaturingtheASICinterface.

Specifically,theADC,equippedwith256channels,digitizedthedetectedanalogsignalsaftertheypass-through249-Kgaintransimpedanceamplifiers.Theresultingdigitalsignalsaresubsequentlyprocessedbytheapplication-specificunit,capableofexecutingnonlinearactivationfunctions.Thesefunctionalitiesaretailoredforthedetectionperturbations,withtheperturbationdatastoreddirectlyontheboard,thusfacilitatingprocessingtaskswhileminimizingthememoryaccess.Theresultsfromdetectionperturbationarethenconvertedagaintoanalogregimeforthedrivingofthesubsequentpropagationmodules.Thecontrollerboardisdesignedwithtwodrivingarrays:onearraydrivesthepropagationmodulatorsusing256digital-to-analogconverters(DACs)forperturbedweightloading,whiletheotherDACsmanagetheringmodulators,transmittingsignalstosubsequentprocessinglayers.

Low-powerphasemodulation
Toachieveminimizedenergyconsumption,weintroducedastrategythatemploysringresonatorsalongwithelectricalmodulation-inducedcarrierplasmadispersion.Thisdesigncapitalizesonresonancewithintheringcavitytoimprovephasemodulationeffectivenesswhilesimultaneouslyminimizingamplitudemodulationviaover-couplingoftheringstructure.Theapproachinvolvestheapplicationofelectro-opticalmodulationforphaseshifting.Achipfeaturinganarrayofringresonatorswasfabricatedtoconductexperimentsonelectro-opticmodulation.Theassembledchip,asshowninFig.S6,underwentbothelectricalandopticalpackagingprocesses.Noteworthyelementsofmodulation,especiallytheNP-dopedringstructure,areillustratedinFig.S6b.Theemittedpatternfromthechip,capturedthroughafocalplanearrangement(Fig.S6c),illustratedthephasemodulationprocess,whichwasfurtheranalyzedthroughinterferencepatternsinconjunctionwithareferencebeam(Fig.S6d).Byvaryingtheinputvoltagefrom0to4.0V,weattainedaphaseshiftof0.07radians,registeringapowerconsumptionofabout18.96nWataninputof4.0V.Throughmode-couplinganalysis,itwasdeterminedthatapπ-phaseshiftwouldcorrespondinglyconsumeapproximately1.7µW.

Datasetpreparation
Languagecorpusdataset.ThelanguagecorpusdatasetwasderivedfromaselectionoftextpagesfromtheWikipedia dump dated 20240220 (available at https://dumps.wikimedia.org/enwiki/20240220/). Sentences shorter than 64 characters were omitted, and the tokenized dataset consists of a vocabulary of 8000 tokens. This dataset was divided into training and evaluation sets, containing 2,172,312 and 241,370 sentences, respectively. During the training process, initial tokens from the training sentences were input to predict subsequent tokens. The predicted tokens were then compared with the actual tokens to compute losses, which guided the model’s training. For evaluation, a total of 356 samples from ten different sentences were utilized, and the average accuracies, loss values, and standard deviations of loss are presented in Fig. 5a.

ImageNet-dataset.TheImageNetdataset60compriseslabeledimagesthatencompass1000differentobjectcategories.Itcontainsatrainingsetof1,281,167samplesandatestingsetof50,000samples,witheachimagehaving224×224pixels.Dataaugmentationtechniquesappliedtothetrainingsetincluderandomresizing,cropping,horizontalflipping,andcoloradjustments(brightness,contrast,andsaturationvariationsof0.4).Forthetestingset,acentercropwasused.Inthecontextof1000-categoryrecognition,eachsamplewasencodedintomulti-wavelengthlightinput.Thecategoriesweregroupedinto10setsof100,eachhaving500testingsamples.Figure4dpresentstheaverageaccuraciesalongsidetheircorrespondingstandarddeviations.Fortheimagegenerationexperiments,sixdatacategorieswereutilizedfortraining.Thedatasetincludes7800trainingsamplesand300testingsamples,witheachresizedtoanimageof256×256pixels,servingasthegroundtruthoftraining.

MNIST-dataset.TheMNISTdatasetcompriseshandwrittendigitsacrosstencategories,containing60,000samplesfortrainingand10,000samplesfortesting.Eachimage,witharesolutionof28×28pixels,wasconvertedinto64dimensionsthroughprincipalcomponentanalysis.Fortheevaluationofdeepsingle-layerchipcluster,eachsamplefromthetencategorieswastransformedintoaninputencodedwithmulti-wavelengthlightintensity.ThefindingsfromthisanalysisaredocumentedinFig.3.

Networkarchitectureandtrainingmethods
ImageNetclassification.TotackletheImageNetclassificationtask,wedevelopedadeepneuralnetworkarchitecturecomprisingupto100layers.Thisarchitecture,whichincludes18-layer,34-layer,and100-layernetworks,isbasedonaresidualconnectionframework.Eachofthesenetworkscontainsfourblockswithsizesstructuredas[3,8,35,3]forthe100-layerversion(and[2,2,2,2]forthe18-layerversion,and[3,4,6,3]forthe34-layerversion).Eachblockisequippedwithtwoerror-tolerantconvolutionallayers,eachutilizingakernelsizeof3,inadditiontotheresidualconnections.Theconvolutionaloperationsaredecomposedintofundamentalmatrix-vectormultiplications,whichareexecutedbyencodingtheinputvectorontolightintensityacrosseightdifferentwavelengths.Subsequently,thelightatthesewavelengthsismodulatedwithpre-trainedarbitraryweightmatrices.Thecombinedeffectofthesemultiplicationsfacilitatestherequiredconvolutionoperationswithinthedeeplearningframework.Weemployedacross-entropylossfunctiontogetherwithastochasticgradientdescent(SGD)optimizer,initializedwithalearningrateof0.4(whichwasreducedbyafactorof10every30epochs),amomentumof0.9,andaweightdecayof2×10−5,totrainthenetworksoveraspanof90epochsacrossallthreearchitectures.Wealsoevaluateddigitalmodelsofthesamesizetothe100-layerSLiMnetwork.Forbothnetworkswith11.475MegaByteparameters,theSLiMnetworkreached85.4%accuracy,whilethenetworkofsamesizewith32-bitfloatingpointweightsreached79.19%accuracy.

Large language model. The foundational components of the deep neural networks utilized in the language models were built on transformers, organized into four error-tolerant linear layers and one attention block. The attention mechanism was structured into multiple heads, enabling multi-head attention. We closely adhered to the specifications of the GPT-2 model regarding the number of layers, dimensions, and attention heads, assigning configurations of 2, 4, 8, 12, and 24 attention blocks, with dimensions set to 256, 512, 640, 768, 1024, and head counts of 4, 8, 10, 12, 16, resulting in a total of 4, 16, 32, 48, and 96 layers, respectively. The training employed a cross-entropy loss function alongside the SGD optimizer, initialized at a learning rate of 0.001 (which decayed proportionally to the current step relative to the total steps) and a weight decay value of 1×10−2. The networks were trained until convergence, requiring 11, 18, 79, 132, and 240 GPU hours for their respective configurations.

Conditionedimagegeneration.TheONNdesignedforconditionedgenerationwasbasedonatransformerarchitecture,comprisingfourerror-tolerantlinearlayersalongsidetheattentionblock.Thisnetworkspecificallyfeatured16attentionblocks,eachwith1024-Dinputsand16heads.Thevocabularyforimagegenerationwassegmentedinto4096wordsusingVQ-VAE61,whileaGPTtrainingmethodologywasutilizedtogeneratesubsequenttokensinthefollowingscale.Commencingwithonetokenwithaclass-conditionedembeddingatthe1×1scale,thenetworkprocessesthisthroughall16blockstopredictthegenerationofsubsequenttokens,followingascalingorderof1,2,3,4,5,6,8,10,13,and16.Theresultant16×16tokensweredecodedintoanimagewitharesolutionof256×256×3.Theemployedlossfunctionwascross-entropy,andtheAdamWoptimizerwasutilizedwithparametersβ1=0.9,β2=0.95,learningratesetto0.0005(decreasingproportionallytotheratioofcurrentstepstototalsteps),andbatchsizesetto128.Thetrainingprocesstookaround576GPU-hourstoreachconvergence.

Scalablephotonicneuralnetwork.Forthecentimeter-tohundredmeter-scalephotonicAIcomputingexperiment,weconstructedatwo-layerfullyconnected(FC)networkcomposedoffault-tolerantmatricesized(64,64)and(64,10).Theoutputfromthisnetworkisa10-dimensionalclassificationresult.Implementingtheerror-toleranttwo-layerFCstructurerequiredthedecompositionofmatrix-vectormultiplicationsintosmallergroupsof4×4matrixunits.Eachunitwasencodedbymodulatingtheinput’sintensityacrossmulti-wavelengthlight,whichwasthenadjustedaccordingtopre-trainedweightstoachievethenecessaryarbitrarymatrixmultiplications.Across-entropylossfunctionwasutilized,andtheSGDoptimizer,configuredwithaninitiallearningrateof0.01andamomentumof0.9wasemployedfor60epochstofine-tunethenetworkparameters.

SpatialdepthofSLiMcomputing
Inourdemonstrationofadeepsingle-layerchipcluster(Fig.S2),weutilizedapackagedchipthatwasconnectedtoaspecializedcontrolboard,facilitatingrapidelectricaladjustments.Aftermodulation,theemittedlightwasdirectedthroughagrating,whichfeatureduniqueinitialphasesandamplitudes.Aplano-convexcylindricallens(LJ1636L2-C,Thorlabs)wasemployedtocollimatethedivergentlightfromaone-dimensionalarrayof128emitters,maintainingaconsistenthorizontalseparationof15mmbetweenthechipandthelens,correspondingtothelens’sfocallength.Thisconfigurationeffectivelyreducedlightdivergenceinthetransversedirection,therebyconcentratingenergyalongthegratingarray.

Thesetupincorporatedaseriesoffivemirrors(PF20-03-G01,Thorlabs)withreflectancegreaterthan95%,allowingforwirelesstransmissionthroughfivesuccessivereflections,whichsignificantlyextendedthepropagationdistance.Thisenabledlong-rangeexperimentscoveringdistancesfromcentimeterstonearlyonehundredmeters.Uponpropagation,thelightwascapturedbyacameralens(Nikon50mm1.8D)aimedatthedetectorarraytoanalyzetheresultingpropagationoutcomesacrossvariousreceivingranges,rangingfrom5to70mm.FigureS12presentsfourdistinctmatricesobservedatpropagationdistancesof0.5,5.0,and45mbeforelensimaging,alldemonstratingrelativeerrorswithin2%(0.97%,1.14%,and0.86%,respectively).

TheintegrationofmultipleSLiMchipsusinganensemblemethodsignificantlyenhancesboththespatialdepthandscale,aswellasthecomputationalflexibility.Themaximumspatialscale,identifiedasthespatialDL,canbededucedbyexaminingthediffractionbehavior.Thediffractionlimitofthesystem’sreceiveraperture,denotedasDout,ismathematicallyrepresentedasDout=0:5*λ/N:A:,whereN.A.signifiestheNAderivedfromtheemissionaperture,De,andthepropagationdistance,representedasN.A.=(1/2)De/DL.Therefore,therelationshipDL=DinDout/λ,isestablished.ImplementingtheensemblemethodwithintegratedchipsnotonlybroadensthespatialscalebyincreasingaperturesizesbutenhancestheDOFsaswell,thusaugmentingtheoverallcomputationalcapacity.Thisscalablespatialandcomputationalabilitypavesthewayforthedevelopmentofextensivecomputingclustersutilizingerror-tolerantchips.AsillustratedinFig.3,anensembleof16chipsdemonstratesacomputingcapabilityof335.54PetaOPS,andthepotentialincorporationofmillionsofchipsoverdistancesspanningkilometerscouldelevatethesystem’sperformanceintotheZettaOPSdomain.

DeepneuralnetworkwithSLiMchips
Duringtheconstructionofthedeepnetwork,toavoidthenon-differentiableissueoftheperturbednonlinearactivations,inthegradientpropagationphase,gradientsforweightsexceedinganabsolutevalueofonewereclipped,whilegradientswithinboundsnavigatedpastthenonlinearlayers.Specifically,theforwardnonlinearfunctionisdelineatedasfD(x)=1forx≥0and−1forx<0.TheadjustedgradientforthisprocedureisexpressedasfD(x)’=1for−1≤x≤1and0otherwise.ThistailoredgradientdescentframeworkproficientlyfacilitatesthetrainingofdeepONNsThroughthenoiseperturbednonlinearities.Aftertrainingtodeterminetheneuralnetworkparameters,wedecomposetheinferenceprocessesintoelementarymatrix-vectormultiplications.Wesegmentextensivematrixoperationsintoaseriesofsmalleroperationalunits.Duringtheexperimentalphase,thenetworkwasexecutedusing8×8elementalmatrixcores(Figs.4and5),withinputdataallocatedacrosseightITUwavelengthchannels(multi-channellasersCBDX-NC-NC-NC-NC,Fig.S13)facilitatedbyadensewavelengthdivisionmultiplexingmultiplexer,acrossapropagationdistanceof0.5m.Thephasetermsforrealizingeachmatrixarerealizedbytrainedoffline,taking0.167sonone3090TiGPU.High-speedinputandoutputsignalsweremanagedanddetectedusingarbitrarywaveformgenerators(KeysightM8195A)andoscilloscopes(TektronixMSO64B),withperturbedweightsloadedbythecontrollerboard.TheillustrationoftheexperimentsystemispresentedinFig.S1.Theoutputsarecapturedandactivatedbyfeedingtheresulttothededicatedcontrolboard.

Inourdeepnetworkevaluations,thestandarddeviationsoftheobservederrorsrangedfrom6%to20%ofsignalintensity;however,duetoSLiMoperations,theerror-affectedinputstransformedintonoise-reducedactivations,facilitatingtheirtransfertosubsequentlayers.Thiserrormitigationoccursateachlayer,enhancingtheresilienceofthenetworkwithinthecontextofa100-layerdeepneuralnetwork.AsdepictedinFig.4d,theexperimentalmeasurementsrevealstandarddeviationsatoperationalfrequenciesof[1G/5G/10G]correspondingtovaluesof[5.757%/5.845%/6.240%], [5.182%/5.331%/5.893%],and [4.454%/4.352%/4.776%]for18-layer,34-layer,and100-layerSLiMnetworks,respectively.Conversely,thestandarddeviationsformulti-layerchipswererecordedat[1.482%/0.494%/0.482%], [2.432%/1.071%/0.533%],and[2.922%/0.660%/0.297%].Theintermediateoutputsfromthe100-layerneuralnetworkandtheidealsimulatedresultsareillustratedinFig.S3.Theseintermediateresultsarerescaledbyafactorof110andadjustedforuniformcolumnwidthsforpresentation.Theper-layererrorratesaredetailedintheuppersectionofFig.S3b,indicatingthattheexperimentaloutcomesatspeedsof1,5,and10Gachievedaverageerrorratesof9.04%,9.22%,and10.34%,respectively.TheseerrorratesalignwithintheestablishederrorassessmentrangeinfluencedbyGaussiannoisestandarddeviations,aspresentedinthelowersectionofFig.S3b,yieldingerrorratesof10.48%,11.56%,and18.78%under15%,20%,and50%standarddeviationsofnoise,respectively.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This work introduces perturbations on-chip to decouple computational correlations to eliminate the redundancies and develop deep photonic learning with a single-layer photonic computing (SLiM) chip. The SLiM chip overcomes the depth limitations of optical neural networks, which allows error rates constrained across over 200 layers, and extends spatial depth from millimeter to hundred-meter scale, which enables the 3-D chip clusters. The authors experimentally realized a neural network with 100 layers for image classification, a 0.345 billion-parameter LLM model with 384 layers for text generation, and a 0.192 billion-parameter LLM model with 640 layers for image generation.\n\nThe perturbation-introduction approach is novel and attractive, and the experimental results are also impressive. However, the reviewers have some questions and requests for explanation.\n1.The structure of the SLiM chip is not illustrative. A structure figure is recommended.\n2.Why the perturbations incorporated within the photonic chip can eliminate the redundancies? What do the redundancies refer to? Where do the redundancies come from?\n3.How does the single-layer photonic chip minimize the error propagation? Does the “single-layer chip” mean that the photonic chip can process one layer of a LLM? Then, to build a 100-layer network, do the authors utilize 100 single-layer photonic chips? In one layer of LLM, there are many multiplications between vectors and matrices. The SLiM chip appears to complete only one MVM at one computing cycle. How does one SLiM chip correspond to the operations in the LLM?\n4.The authors claim that W_i = |G_i *Phi_i|^2 in SI-2.1. When no perturbation, G_i~=G_0, Phi_i~=Phi_0, then W_i=W_0. If the perturbation is introduced, Phi_i != Phi_0, W_i are different. At the same time, the authors claim that the phase distribution appears random. Therefore, the W are random. How can a random W process the information effectively?\n5.How is the propagation perturbation injected? Since the propagation perturbation can decorrelate the weights, does it mean that propagation perturbation can be trained and programmed? Is the training completed online or offline? If online, how is it realized? If offline, will the offline training be complicated and cost too much offline computational resources?\n6.Besides the SLiM chip configuration and perturbation injection, many operations are processed in the electronic domain, like the nonlinear activation functions and the data transfer among the SLiM chips. During the experiments, how do the authors control the total computing cluster to process billions of parameters of the LLM and complete the LLM computing? How is the coordination of multiple SLiM chips managed for processing billion-parameter LLMs?\n7.Regarding the computing power, the 327.68 TOPS is clear, but where does the 335.54 Peta OPS come from?\n8.The computing energy 1510.4Peta OPS/W appears to only include the energy cost of the phase shifters. However, the authors claim that the SLiM achieves ExaOPS/W (10^6 TOPS/W) efficiency, which is unacceptable. The authors should assess the energy efficiency more accurately. The energy cost should include energy cost from the phase shifters, weight matrix programming, and detectors, as well as the energy cost to complete the nonlinear activation computing. Otherwise, the energy comparison between the SLiM chips and GPUs which include complete MVM computing is unfair.\n\nIn summary, the work is impressive and introduces novel methods to overcome the depth limitations. However, the details of the SLiM chip and the experiments should be described.", "reviewer_2": "What are the noteworthy results?\nThe results are very noteworthy, the scale of the transmitter and SLiM chips are very impressive with respect to complexity and scale. Additionally, the packaging, control, and extension to multiple chiplets is state-of-the-art. The demonstrated architecture is novel. Congratulations to the authors for the sucessful results.\n-Will the work be of significance to the field and related fields? How does it compare to the established literature? If the work is not original, please provide relevant references.\nThis work will be of significance within the field of neuromorphic photonics. The performance with respect to depth and scale is equal or greater than other approaches within the field.\n-Does the work support the conclusions and claims, or is additional evidence needed?\nThe claims are very significant and as impressive as this experiment is. I think additional evidence would be useful to back up the claim. Additionally, the flow of the writing and logical conclusions are at time difficult to follow. I think it would be helpful to have more clearly presented performance metrics with respect to RF noise figure and loss per layer. With the addition of noise figure analysis, one could understand the required signal-to-noise of the input signal as well as the scalability of this system without error correction. If the photonic loss and digital loss are 3.04 and 2.96, respectively then only a few layers would be possible. The claim of deep learning within neuromophic photonic approaches is the key limiting factor and claiming to overcome this goal is a significant claim.\n-Are there any flaws in the data analysis, interpretation and conclusions? Do these prohibit publication or require revision?\nNot identified but also I am not confident with respect to the Machine Learning Data Analysis. It would be helpful to see more optical / electronic analysis with respect to noise and loss.\n-Is the methodology sound? Does the work meet the expected standards in your field?\nThe methodology is sound and meet standards.\n-Is there enough detail provided in the methods for the work to be reproduced?\nI believe so, but more information regarding how the nonlinearity is achieved and the transfer function would be useful.\nAdditional Comments:\nThe experiment presented within this paper is tremendously impressive but the claims made are very significant. I think more information regarding loss per layer, nonlinearity, and noise performance is required. Some of the sections are difficult to comprehend and the writing should be improved before publication.\nI believe the introduction should be expanded to focus a bit on the history of photonic neural networks and the need for this approach. There are very condensed statements made by the authors about noise, physical analog computing, but there is no discussion of other research within the field which has focused on tackling these limitations to scaling and analysis of scaling photonic neural networks. I would recommend the authors look into literature on silicon photonic neural networks for analog machine learning approaches, e.g. RF fingerprinting or automatic modulation classification", "reviewer_3": "The authors present a single-layer photonic computing chip that by injecting purposely designed perturbations in both the linear transfer matrix and the detection non-linearity suppresses the classical error-accumulation bottleneck of analog optical neural networks.\n\nThe paper is well written, well structured and well documented.\n\nI have some minor concerns:\n- Authors state that energy measures rely on resonant phase shifters and excludes laser, ADC/DAC, CMOS drivers and control FPGA. Supplementary Note 4 states these are “additional overhead” yet does not quantify them.\n- Authors state to reach 85.2 % accuracy on ImageNet for 100-layer SLiM, far below 91% reached by state-of-the-art digital models. Why this difference? Is the digital sota model not implementable with the SLiM?\n- The theoretical model introduced to justify linear error accumulation across layers (rather than exponential) is good but lacks direct empirical validation. It would be useful to show variance or error growth as a function of depth from actual hardware measurements\n(Remarks on code availability)\nThe paper does not appear to be accompanied by publicly available code, nor does it reference any repository containing implementation details, model weights, or control software used in the experiments. As such, I was not able to assess the usability or reproducibility of the code.\nWithout access to this material, the work remains difficult to replicate and reuse by the broader community, particularly for researchers interested in benchmarking or building upon the SLiM architecture. Making this codebase available would significantly increase the impact and credibility of the results."}, "author_response": "Response to referees:\nWe sincerely thank all the reviewers for their constructive and insightful comments. In this response\nletter, we address each remark point by point. Reviewer comments are highlighted in blue, and\ncorresponding changes to the manuscript are marked in red. References specific to this response are\ndenoted as Ref. [rX].\nSummary of the main revisions:\n1. We have included the analysis of the system efficiency of the SLiM chip. The revisions can be\nfound in the [Main text], [Supplementary Note 4. Computing capabilities of single-layer\nphotonic chip], and [Supplementary Table S1. Comparisons of deep AI experiments].\n2. We have provided a detailed circuit diagram of the SLiM chip. Revisions are reflected in\n[Supplementary Fig. S14] and [Methods Section. Implementation of single-layer chips.].\n3. We have provided additional explanations on the noise and errors, and have supplemented the\nvalidation of the error model. The corresponding revisions appear in [Supplementary Note 1.\nThe error model of ONN.] and [Supplementary Figure S15].\n4. We have discussed the implementation of parallel processing with the SLiM cluster. This\ndiscussion is included in [Supplementary Figure S16].\n5. We have added further details regarding the SLiM matrix design and realization, as well as the\ntraining procedure for the SLiM network. The entire manuscript has also been thoroughly\nproofread and revised for clarity and precision.\n6. We have open-sourced the SLiM model and data for the community.\nThe detailed, point-by-point responses are provided below.\n*******************************************************************************\nReviewer #1 (Remarks to the Author):\nThis work introduces perturbations on-chip to decouple computational correlations to eliminate the\nredundancies and develop deep photonic learning with a single-layer photonic computing (SLiM)\nchip. The SLiM chip overcomes the depth limitations of optical neural networks, which allows error\nrates constrained across over 200 layers, and extends spatial depth from millimeter to hundred-meter\nscale, which enables the 3-D chip clusters. The authors experimentally realized a neural network\nwith 100 layers for image classification, a 0.345 billion-parameter LLM model with 384 layers for\ntext generation, and a 0.192 billion-parameter LLM model with 640 layers for image generation.\nThe perturbation-introduction approach is novel and attractive, and the experimental results are also\nimpressive. However, the reviewers have some questions and requests for explanation.\nResponse: We sincerely thank the reviewer for recognizing our innovations. Please find our point-\nby-point responses to the comments below.\n1.The structure of the SLiM chip is not illustrative. A structure figure is recommended.\nResponse: We thank the reviewer for the suggestions. We have provided a more detailed structure\nillustration in Fig. S14. As we described in the Methods section, the input is coupled onto the chip\nvia a single-mode fiber, which is then uniformly distributed through an 8-level splitter tree. Each of\nthe resulting 256 channels is independently modulated, followed by a perturbation region where the\noptical path length is varied by 20 μm. On the detection path, light can be coupled to the detector\neither through a 256-element grating array or sensed directly via free-space propagation.\nRevision: We have added the detailed circuit diagram of the SLiM chip in Fig. S14 as below. We\nhave also modified the description of the SLiM chip implementation in the Methods section\nas …The circuit diagram of the SLiM chip is displayed in Fig. S14.\nSupplementary Figure S14. Circuit diagram of the SLiM circuit.\n2.Why the perturbations incorporated within the photonic chip can eliminate the redundancies?\nWhat do the redundancies refer to? Where do the redundancies come from?\nResponse: We thank the reviewer for the comments. Please find our detailed responses below.\nQ: What do the redundancies refer to?\nResponse: The redundancies refer to the unnecessary layers on photonic integrated circuits in\nrealizing matrix operations. In conventional photonic computing architectures, the layer number is\nin direct proportion to the size of the target matrix. For example, to realize an M×N matrix, an L-\nlayer photonic circuit is required, where L~O(N). Here we discovered that the (L-1) layers from\nlayer-2 to layer-N are actually redundant: matrix could be realized with single layer propagation.\nThese extra (L-1) layers amplify the processing errors.\nQ: Where do the redundancies come from?\nResponse: The redundancies come from the correlation of the on-chip wavelength and spatial\nchannels, because of which it is hard to realize arbitrary matrices with single layer circuits through\nexisting methods. Specifically, to realize the computing matrix 𝑊, the transmission channels are\nmodulated on chip by exerting wavefront 𝛷 , derived from the euuation 𝑊 =𝐺𝛷 . oowever,\nbecause of the spectral proximity, the wavefront 𝛷 and the transmission matrix 𝐺 both exhibit\nhigh correlation, resulting in linear dependence on the right-hand side of the euuation that does not\nguarantee a solution.\nQ: Why the perturbations incorporated within the photonic chip can eliminate the redundancies?\nResponse: By incorporating the perturbations on chip, diverse wavelength channels are decorrelated,\nenabling arbitrary matrices to be realized with minimal error propagations. We introduce on-chip\nperturbative noise to break the correlation, mathematically represented as 𝛷̂ =𝛷 ·𝑒𝑗𝑛2𝜋Δ𝑘/𝜆𝑖,\n𝑘 𝑘\nwhere 𝑘 symbolizes the waveguide coordinate with corresponding noise Δ𝑘 . hhe linearly\ncorrelated euuations can be reformulated as 𝑊 =𝐺𝛷̂, which is independent set and guarantees a\nsolution for matrix 𝑊 with single-layer propagation.\n3.How does the single-layer photonic chip minimize the error propagation? Does the “single-layer\nchip” mean that the photonic chip can process one layer of a LLM? Then, to build a 100-layer\nnetwork, do the authors utilize 100 single-layer photonic chips? In one layer of LLM, there are many\nmultiplications between vectors and matrices. The SLiM chip appears to complete only one MVM\nat one computing cycle. How does one SLiM chip correspond to the operations in the LLM?\nQ: How does the single-layer photonic chip minimize the error propagation?\nResponse: We thank the reviewer for the comments. By reducing the layers from L layer to single\nlayer, the error accumulation is minimized. As the output error is in proportion to the depth of layers\n𝑉𝑎𝑟(𝛥𝑌/𝑌)~∑𝐿 (𝑉𝑎𝑟(𝛥𝑊/𝑊)), The single layer chip reduces the errors by L times, through\n𝑖=1 𝑖 𝑖\ndecreasing the layer number from L to 1. To illustrate this point, we employ a simulation validation:\nwe randomly draw 10 samples of 10×10 matrices, with each entry drawn from gaussian distribution.\nDuring the validation, each layer is distorted with gaussian noise with 0.1 standard deviation.\nThe mean squared error are calculated and averaged among 10,000 trials, which is visualized below,\nwhich shows the error accumulation is linear, and the single layer propagation has the least error.\nQ: Does the “single-layer chip” mean that the photonic chip can process one layer of a LLM? Then,\nto build a 100-layer network, do the authors utilize 100 single-layer photonic chips? In one layer of\nLLM, there are many multiplications between vectors and matrices. The SLiM chip appears to\ncomplete only one MVM at one computing cycle. How does one SLiM chip correspond to the\noperations in the LLM?\nResponse: Although a deep neural network may contain numerous layers, its computations can be\ndecomposed into a series of basic matrix operations. These operations can be flexibly mapped onto\nSLiM chips without requiring a one-to-one correspondence between layers and chips. Each SLiM\nchip is capable of performing a matrix-vector multiplication. Therefore, even a model with 100\nlayers does not necessarily require 100 individual SLiM chips for implementation. As described in\nthe Methods section [Deep neural network with SLiM chips], our large language model\nimplementation partitions the overall computation into submatrices, with each submatrix handled\nby a single SLiM chip. In our experiments, we demonstrate this by reusing a single packaged SLiM\nchip to sequentially implement the entire model, validating the chip's capability to support deep\narchitectures through time-multiplexed execution.\nRevision:\nWe have updated the related discussion and figure analysis in the supplementary note 1, as,\nWe numerically validated the error trend by employing 10 samples of 10×10 matrices, with each\nentry randomly sampled from gaussian distribution. During the validation, a 10×1 random vector is\nsequentially multiplied with these 10 matrices, the computation is gradually distorted with the noise.\nFor example, to analyze the errors with k layers, the first k layers are distorted with the noise. Finally,\nthe errors are calculated for these 10 consecutive matrix multiplications. This procedure was\nrepeated 10,000 times, and the mean and standard deviation of the errors were computed. As shown\nin Fig. S15, the mean error increases linearly with the number of noisy layers, corroborating our\ntheoretical analysis.\nSupplementary Figure S15. Analysis of the error accumulation with respect to layers. Left panel:\naverage error, right panel: standard deviation.\nWe have discussed the parallelization method in Fig. S16.\n4.The authors claim that W_i = |G_i *Phi_i|^2 in SI-2.1. When no perturbation, G_i~=G_0,\nPhi_i~=Phi_0, then W_i=W_0. If the perturbation is introduced, Phi_i != Phi_0, W_i are different.\nAt the same time, the authors claim that the phase distribution appears random. Therefore, the W\nare random. How can a random W process the information effectively?\nResponse：We thank the reviewer for the comments. Even through the phase distribution is random,\nthe W is not random because (1) the random perturbation remains fixed after chip fabrication as a\nrandom initialization from the view of neural network training; (2) the phase term 𝛷 can then be\n𝑖𝑘\ndesigned for the realization of target matrices. As we showed in the Fig. 2d (we replicate below),\nby designing the values of 𝛷 , matrices of diverse dimensions can be realized.\n𝑖𝑘\nFig. 2d. Matrices with arbitrary dimension and full degree-of-freedom (DOF). The relative error is\nquantitatively evaluated by sweeping the input dimensions as well as the output dimensions, where\nthe error with full DOF as delineated with dashed lines, were plotted against the method without\nredundancy elimination. With redundancy elimination, the relative error dropped from ~10% to\n~0.1%.\n5.How is the propagation perturbation injected? Since the propagation perturbation can decorrelate\nthe weights, does it mean that propagation perturbation can be trained and programmed? Is the\ntraining completed online or offline? If online, how is it realized? If offline, will the offline training\nbe complicated and cost too much offline computational resources?\nResponse: We thank the reviewer for the questions. The perturbation is injected by tuning the\nwaveguide lengths in the chip fabrication process. As we described in the main text [Error tolerance\nwith single-layer photonic computing] and [Supplementary Note 2. Formulations of the single-layer\nphotonic computing], the propagation lengths of the 𝑘-th on-chip emitter are selected as 𝑘Δ𝑑 and\nΔ𝑑 is optimized to be 20 μm.\nIn the experiments, the phase modulation of the channels is trained offline with experimentally\ncalibrated characteristics as shown in Fig. S13, which combined with the perturbation, helps\nrealizing arbitrary matrices. In the experiment, each matrix design takes 0.167s on 3090ti GPU.\nRevision: We have provided the training time of matrix on the GPU in the [Methods section Deep\nneural network with SLiM chips.]: The phase terms for realizing each matrix are realized by trained\noffline, taking 0.167 second on one 3090 Ti GPU.\n6.Besides the SLiM chip configuration and perturbation injection, many operations are processed\nin the electronic domain, like the nonlinear activation functions and the data transfer among the\nSLiM chips. During the experiments, how do the authors control the total computing cluster to\nprocess billions of parameters of the LLM and complete the LLM computing? How is the\ncoordination of multiple SLiM chips managed for processing billion-parameter LLMs?\nResponse: We thank the reviewer for the questions. In the experiment, we reuse one packaged SLiM\nchip for the implementation of the matrix vector multiplication, and the output is directed to the\ndedicated control board for the activation. Before the experiments, the computations are first\ndecomposed into matrix multiplications with an offline computer. To parallelize the process and\nfurther enhanced the speed, computations could be amortized into the SLiM chip cluster.\nComputations in one layer of the SLiM network can be distributed across a chip cluster and\nprocessed concurrently, while N cluster facilitates the N layer network. The N cluster can process\nN inputs in a streamline mode. We supplement the discussion for parallelism in supplementary Fig.\nS16 as presented below.\nSupplementary Figure S16. Parallel processing with SLiM chip cluster. a, The N layer neural\nnetwork could be realized by N SLiM cluster. Each SLiM chip in one cluster parallelly implements\nthe computations of one layer. The chips are scheduled by a controller that allocates the input data\nand collect the outputs. b, The streamline of the cluster processing, the N cluster can process N\nsamples concurrently.\n7.Regarding the computing power, the 327.68 TOPS is clear, but where does the 335.54 Peta OPS\ncome from?\nResponse: We thank the reviewer for the questions. For 335.54 Peta OPS metrics are results of the\n16 chip ensemble as displayed in Fig. 3 (we duplicate below). As described in [Supplementary Note\n4. Computing capabilities of single-layer photonic chip], the total number of operations sums to\n2𝐾 𝐾 . On the 16-chip ensemble, 𝐾 =𝐾 =256×16=4096, which can reach 33,554,432\n𝑚 𝑑 𝑚 𝑑\noperations and 335.54 Peta OPS at 10 GHz speed.\nFig. 3 d, hhe DOF can be expanded from 256 up to 256K by utilizing spatial ensemble techniuues.\nhhe top panel displays the ensemble configuration of K=16.\n8.The computing energy 1510.4Peta OPS/W appears to only include the energy cost of the phase\nshifters. However, the authors claim that the SLiM achieves ExaOPS/W (10^6 TOPS/W) efficiency,\nwhich is unacceptable. The authors should assess the energy efficiency more accurately. The energy\ncost should include energy cost from the phase shifters, weight matrix programming, and detectors,\nas well as the energy cost to complete the nonlinear activation computing. Otherwise, the energy\ncomparison between the SLiM chips and GPUs which include complete MVM computing is unfair.\nResponse: We acknowledge the insightful question from the reviewer.\nWe have provided the system energy efficiency calculations to include the other components\nnecessary for the implementation, such as the Digital-to-Analog Converters (DACs), Analog-to-\nDigital Converters (ADCs), optical power sources, and detectors. hhe SLiM computing employs 1-\nbit data conversions in high-speed experiments, which simplifies the circuit design and reduces\nenergy consumption compared to higher-bit converters. With current technologies, the power\ndissipation of 1-bit DAC driving corresponds to the capacitance charge of the modulators, which\nconsumes 6.3 fJ/bit [r1]. hhe ADC process could be simplified to a low-power comparator, which\ndraws 27.3fJ/bit [r2]. Accordingly, the average power consumptions per channel for each component\nare as follows: 𝑃 = 1.7 μW, 𝑃 = 63 μW, 𝑃 = 200 μW, 𝑃 = 250 μW, and 𝑃 =\n𝑆𝐿𝑖𝑀 𝐷𝐴𝐶 𝑜𝑝𝑡 𝐷𝐸𝑇 𝐴𝐷𝐶\n273 μW.\nDenoting the input channel number, output channel number, and working freuuency as N, M,\nand F (10-Goz), the overall system efficiency is calculated as 𝜂 =2𝑀𝑁𝐹/(𝑁(𝑃 +𝑃 )+\n𝐷𝐴𝐶 𝑜𝑝𝑡\n𝑀(𝑃 +𝑃 )+𝑀𝑁𝑃 ). Our findings indicate that the system efficiency reaches 3.25×103\n𝐴𝐷𝐶 𝐷𝐸𝑇 𝑆𝐿𝑖𝑀\nhOPS/W (as in the high-speed experiments), while considering the considering the power\nconsumption of modulators, detectors, optical power sources, Digital-to-Analog Converters (DACs),\nand Analog-to-Digital Converters (ADCs).\n[r1] Yuan, Y. et al. A 5× 200 Gbps microring modulator silicon chip empowered by two-segment\nZ-shape junctions. Nature Communications 15, 918 (2024).\n[r2] Wang, J., Ye, F. & Ren, J. in 2021 IEEE 14th International Conference on ASIC (ASICON).\n1-4 (IEEE).\nRevision:\nWe have included the revised content in the main and supplementary information.\nSupplementary Note 4:\n…We also included the other components of the system including the Digital-to-Analog\nConverters (DACs), Analog-to-Digital Converters (ADCs), optical power sources, detectors, and\ncalculate system energy efficiency. hhe SLiM chip employs 1-bit converters in high-speed\nexperiments, which simplifies the circuit design and reduces energy consumption compared to\nhigher-bit converters. With current technologies, the power dissipation of 1-bit DAC driving\ncorresponds to the capacitance charge of the modulators, which consumes 6.3 fJ/bit 7. hhe ADC\nprocess could be simplified to a low-power comparator, which draws 27.3fJ/bit 8. hhe specific\npower consumptions per channel for each component are as follows: 𝑃 = 1.7 μW, 𝑃 = 63\n𝑆𝐿𝑖𝑀 𝐷𝐴𝐶\nμW, 𝑃 = 200 μW, 𝑃 = 250 μW, and 𝑃 = 273 μW. Denoting the input channel number,\n𝑜𝑝𝑡 𝐷𝐸𝑇 𝐴𝐷𝐶\noutput channel number, and working freuuency as N, M, and F (10-Goz), the overall system\nefficiency is calculated as 𝜂 =2𝑀𝑁𝐹/(𝑁(𝑃 +𝑃 )+𝑀(𝑃 +𝑃 )+𝑀𝑁𝑃 ) . We\n𝐷𝐴𝐶 𝑜𝑝𝑡 𝐴𝐷𝐶 𝐷𝐸𝑇 𝑆𝐿𝑖𝑀\nhave plotted the energy efficiency against the degrees of freedom (DOFs) in Fig. S14. Our findings\nindicate that in the high-speed experiments, the system efficiency reaches 3.25×103 hOPS/W, while\nconsidering the power consumption of modulators, detectors, optical power sources, Digital-to-\nAnalog Converters (DACs), and Analog-to-Digital Converters (ADCs)….\nZ-shape junctions. Nature Communications 15, 918 (2024).\n1-4 (IEEE).\nWe have also included the discussion of system energy efficiency in the main text and have updated\nthe supplementary table 1.\nMethods Task Depth Cycle time Energy efficiency\nImage Classification\nAcc. 85.4% 100\n(ImageNet 1000 Classes)\nSLiM chip Text generation\n384 0.1 ns\n(Optoelect Loss function value 3.0397 3.25×103 TOPS/Wa\n(96×4) @10 GHz\nronics) (Wikipedia text)\nImage Generation\n(64×10)\n(ImageNet dataset)\na. Calculation includes the power consumption of modulators, detectors, optical power sources,\nDigital-to-Analog Converters (DACs), and Analog-to-Digital Converters (ADCs).\nIn summary, the work is impressive and introduces novel methods to overcome the depth limitations.\nHowever, the details of the SLiM chip and the experiments should be described.\nResponse: We sincerely thank the reviewer for the constructive comments. We hope that with point-\nby-point response, the details of the work could be better understood.\n*******************************************************************************\nReviewer #2 (Remarks to the Author):\n- What are the noteworthy results?\nThe results are very noteworthy, the scale of the transmitter and SLiM chips are very impressive\nwith respect to complexity and scale. Additionally, the packaging, control, and extension to multiple\nchiplets is state-of-the-art. The demonstrated architecture is novel. Congratulations to the authors\nfor the sucessful results.\n-Will the work be of significance to the field and related fields? How does it compare to the\nestablished literature? If the work is not original, please provide relevant references.\nThis work will be of significance within the field of neuromorphic photonics. The performance with\nrespect to depth and scale is equal or greater than other approaches within the field.\n-Does the work support the conclusions and claims, or is additional evidence needed?\nThe claims are very significant and as impressive as this experiment is. I think additional evidence\nwould be useful to back up the claim. Additionally, the flow of the writing and logical conclusions\nare at time difficult to follow.\nResponse: we sincerely acknowledge the reviewer for the recognition of our innovations. We have\nthoroughly proofread the manuscripts to improve the readability. The comments are replied point-\nby-point below.\nI think it would be helpful to have more clearly presented performance metrics with respect to RF\nnoise figure and loss per layer. With the addition of noise figure analysis, one could understand the\nrequired signal-to-noise of the input signal as well as the scalability of this system without error\ncorrection. If the photonic loss and digital loss are 3.04 and 2.96, respectively then only a few layers\nwould be possible. The claim of deep learning within neuromophic photonic approaches is the key\nlimiting factor and claiming to overcome this goal is a significant claim.\nResponse: We sincerely thank the reviewer for the comments. We apologize for the ambiguity\ncaused here. The figures 3.04 and 2.96 are the loss function values realized in the SLiM network,\nwhich is a quantification of the difference between the system outputs and the target in the dataset,\nrather than the noise in the system.\nIn response to the concerns on the noise, we calibrated the system noise in Fig. S3b (we\nduplicated below), which shows the error rates associated to the experiments carried out using the\n100-layer error-tolerant model. The upper section showcases results from tests conducted at\nfrequencies of 1 G, 5 G, and 10 G, yielding error rates of 9.04%, 9.22%, and 10.34%, respectively.\nThe lower section details the outcomes under conditions of Gaussian noise, where standard\ndeviations of 0.15, 0.20, and 0.50 corresponded to error rates of 10.48%, 11.56%, and 18.78%.\nAccordingly, the noise figure of the system is equivalent to the 0.15 standard deviation noise under\nthe 10 GHz experiment scenario.\nb, The error rates associated to the experiments carried out using the 100-layer error-tolerant model.\nThe upper section showcases results from tests conducted at frequencies of 1 G, 5 G, and 10 G,\nyielding error rates of 9.04%, 9.22%, and 10.34%, respectively. The lower section details the\noutcomes under conditions of Gaussian noise, where standard deviations of 0.15, 0.20, and 0.50\ncorresponded to error rates of 10.48%, 11.56%, and 18.78%.\nRevision:\nTo avoid misunderstanding, we have updated the expression of the loss, to loss function value, in\nsupplementary table S1, when ambiguity may arise.\n-Are there any flaws in the data analysis, interpretation and conclusions? Do these prohibit\npublication or require revision?\nNot identified but also I am not confident with respect to the Machine Learning Data Analysis. It\nwould be helpful to see more optical / electronic analysis with respect to noise and loss.\nResponse: We thank the reviewer for the suggestion. We will illustrate the noise and error rates\npresented throughout the manuscript.\nThe 100-layer image classification:\nAs described in the response 2.2, the experimental noise is benchmarked with the 100-layer network,\nand calibrated to be equivalent to gaussian noise of 0.15 standard deviation, with which the error\nrate is controlled to below 10.34%. We also calibrate the maximal noise tolerated of the architecture\nin Fig. 4c (duplicated below) as ~20%-std gaussian noise, when the performance deteriorates\nobviously beyond this error regime.\nFig. 4. c, Analysis was conducted for the deep ONNs involved in classifying the ImageNet-1000\ndataset. The networks were tested against various levels of Gaussian noise featuring different\nstandard deviations (Stds), focusing on both the ONNs with single-layer and the multi-layer chip\nimplementation as noise gradually distorted the layers.\nThe Billion-parameter ONN:\nWe present in Fig. 5d, the error rate controlled throughout the 640 layers. Under the experiment\nnoise, the error rates maintained within 37.2%/38.6%/40.2%/38.8%/42.1%/39.1% for six-category\nimage generation.\nFig. 5. d, The bounded error rate across 640 layers during a 10-step image generation process.\nTheoretically proof:\nThe error model of ONN is presented in [Supplementary Note 1. The error model of ONN.], where\nwe show that the error increase at least linearly. To corroborate the theoretical analysis, we\nsupplement the validation of the error trend by employing 10 samples of 10×10 matrices, with each\nentry randomly sampled from gaussian distribution. During the validation, a 10×1 random vector is\nsequentially multiplied with these 10 matrices, the computation is gradually distorted with the noise.\nFor example, to analyze the errors with k layers, the first k layers are distorted with the noise. Finally,\nthe errors are calculated for these 10 trials. The above process is repeated for 10000 times and\naverages, the mean and standard deviation of the errors are plotted as Fig. S15, which shows a linear\nscale of the mean errors.\nThe error bounding is presented in Fig. S15 as [Supplementary Note 3. Error-bounding with single-\nlayer photonic computing.], where we prove that the error rate can be controlled below 50%, which\nis validated by the experiment results of 100-layer image classification and The Billion-parameter\nONN.\nRevision:\nWe have updated the related discussion and figure analysis in the supplementary note 1, as,\nWe numerically validated the error trend by employing 10 samples of 10×10 matrices, with each\nentry randomly sampled from gaussian distribution. During the validation, a 10×1 random vector is\nsequentially multiplied with these 10 matrices, the computation is gradually distorted with the noise.\nFor example, to analyze the errors with k layers, the first k layers are distorted with the noise. Finally,\nthe errors are calculated for these 10 consecutive matrix multiplications. This procedure was\nrepeated 10,000 times, and the mean and standard deviation of the errors were computed. As shown\nin Fig. S15, the mean error increases linearly with the number of noisy layers, corroborating our\ntheoretical analysis.\nSupplementary Figure S15. Analysis of the error accumulation with respect to layers. Left panel:\naverage error, right panel: standard deviation.\n-Is the methodology sound? Does the work meet the expected standards in your field?\nThe methodology is sound and meet standards.\n-Is there enough detail provided in the methods for the work to be reproduced?\nI believe so, but more information regarding how the nonlinearity is achieved and the transfer\nfunction would be useful.\nResponse: We thank the reviewer for the suggestion. As is described in the section [Error tolerance\nwith single-layer photonic computing], the nonlinear activation function has the form of 𝑓 =\n∫𝛿(𝑥−𝛥𝑓), where 𝛥𝑓 represents the perturbation position in the nonlinear function. This\nactivation function can be implemented at the detection with the analog-to-digital conversion (·)_D,\nby assigning the error-distorted values to the nearest signal levels. In this implementation of the\nhigh-speed experiments (Fig. 4 and Fig. 5), the outputs are captured and activated by feeding the\nresult to the dedicated control board, and the distribution of the perturbation position 𝛥𝑓 are\nvisualized in the Fig. 4b, Fig. S4, and Fig. S5.\nRevision:\nWe have updated the implementation of the nonlinearity in the Methods section as:\n…The outputs are captured and activated by feeding the result to the dedicated control board.. …\nAdditional Comments:\nThe experiment presented within this paper is tremendously impressive but the claims made are\nvery significant. I think more information regarding loss per layer, nonlinearity, and noise\nperformance is required. Some of the sections are difficult to comprehend and the writing should be\nimproved before publication.\nResponse: We thank the reviewer for the suggestion. We have presented the loss and noise analysis\nin the response 2.2&2.3. We have described the nonlinear realization in response 2.4. We have\nthoroughly proofread the manuscripts to improve the readability.\nI believe the introduction should be expanded to focus a bit on the history of photonic neural networks and the need for this approach. There are very condensed statements made by the authors about noise, physical analog computing, but there is no discussion of other research within the field which has focused on tackling these limitations to scaling and analysis of scaling photonic neural networks. I would recommend the authors look into literature on silicon photonic neural networks for analog machine learning approaches, e.g. RF fingerprinting or automatic modulation classification\nResponse: We thank the reviewer for the suggestion. We provided more discussion on silicon\nphotonic neural networks in the introduction.\nRevision:\nWe have modified the introduction part as:\n…Notably, with the ongoing evolution of photonic integration, the silicon photonic platform has\nemerged as the most mature and scalable solution for mapping neural networks onto hardware for\nintelligent signal processing29,34,39-41. Its large bandwidth and compatibility with CMOS\nprocesses make it particularly well-suited as an analog machine learning module for high-speed\nsignal processing tasks, especially in the radio freuuency (RF) domain42,43….\nScientific reports 7, 7430 (2017).\n(2017).\n(2006).\nprocessing. Nature Communications 16, 5087 (2025).\nradiofrequency applications. Nature Communications 15, 1563 (2024).\n*******************************************************************************\nReviewer #3 (Remarks to the Author):\nThe authors present a single-layer photonic computing chip that by injecting purposely designed\nperturbations in both the linear transfer matrix and the detection non-linearity suppresses the\nclassical error-accumulation bottleneck of analog optical neural networks.\nThe paper is well written, well structured and well documented.\nResponse: We sincerely thank the reviewer for recognizing our innovations. Please find our point-\nby-point responses to the comments below.\nI have some minor concerns:\n- Authors state that energy measures rely on resonant phase shifters and excludes laser, ADC/DAC,\nCMOS drivers and control FPGA. Supplementary Note 4 states these are “additional overhead” yet\ndoes not quantify them.\nResponse: We sincerely thank the reviewer for the comments.\nWe have provided the system energy efficiency calculations to include the other components\nnecessary for the implementation, such as the Digital-to-Analog Converters (DACs), Analog-to-\nDigital Converters (ADCs), optical power sources, and detectors. hhe SLiM computing employs 1-\nbit data conversions in high-speed experiments, which simplifies the circuit design and reduces\nenergy consumption compared to higher-bit converters. With current technologies, the power\ndissipation of 1-bit DAC driving corresponds to the capacitance charge of the modulators, which\nconsumes 6.3 fJ/bit [r1]. hhe ADC process could be simplified to a low-power comparator, which\ndraws 27.3fJ/bit [r2]. Accordingly, the average power consumptions per channel for each component\nare as follows: 𝑃 = 1.7 μW, 𝑃 = 63 μW, 𝑃 = 200 μW, 𝑃 = 250 μW, and 𝑃 =\n𝑆𝐿𝑖𝑀 𝐷𝐴𝐶 𝑜𝑝𝑡 𝐷𝐸𝑇 𝐴𝐷𝐶\n273 μW.\nDenoting the input channel number, output channel number, and working freuuency as N, M,\nand F (10-Goz), the overall system efficiency is calculated as 𝜂 =2𝑀𝑁𝐹/(𝑁(𝑃 +𝑃 )+\n𝐷𝐴𝐶 𝑜𝑝𝑡\n𝑀(𝑃 +𝑃 )+𝑀𝑁𝑃 ). Our findings indicate that the system efficiency reaches 3.25×103\n𝐴𝐷𝐶 𝐷𝐸𝑇 𝑆𝐿𝑖𝑀\nhOPS/W (as in the high-speed experiments), while considering the considering the power\nconsumption of modulators, detectors, optical power sources, Digital-to-Analog Converters (DACs),\nand Analog-to-Digital Converters (ADCs).\n[r1] Yuan, Y. et al. A 5× 200 Gbps microring modulator silicon chip empowered by two-segment\nZ-shape junctions. Nature Communications 15, 918 (2024).\n[r2] Wang, J., Ye, F. & Ren, J. in 2021 IEEE 14th International Conference on ASIC (ASICON).\n1-4 (IEEE).\nRevision:\nWe have included the revised content in the main and supplementary information.\nSupplementary Note 4:\n…We also included the other components of the system including the Digital-to-Analog\nConverters (DACs), Analog-to-Digital Converters (ADCs), optical power sources, detectors, and\ncalculate system energy efficiency. hhe SLiM chip employs 1-bit converters in high-speed\nexperiments, which simplifies the circuit design and reduces energy consumption compared to\nhigher-bit converters. With current technologies, the power dissipation of 1-bit DAC driving\ncorresponds to the capacitance charge of the modulators, which consumes 6.3 fJ/bit 7. hhe ADC\nprocess could be simplified to a low-power comparator, which draws 27.3fJ/bit 8. hhe specific\npower consumptions per channel for each component are as follows: 𝑃 = 1.7 μW, 𝑃 = 63\n𝑆𝐿𝑖𝑀 𝐷𝐴𝐶\nμW, 𝑃 = 200 μW, 𝑃 = 250 μW, and 𝑃 = 273 μW. Denoting the input channel number,\n𝑜𝑝𝑡 𝐷𝐸𝑇 𝐴𝐷𝐶\noutput channel number, and working freuuency as N, M, and F (10-Goz), the overall system\nefficiency is calculated as 𝜂 =2𝑀𝑁𝐹/(𝑁(𝑃 +𝑃 )+𝑀(𝑃 +𝑃 )+𝑀𝑁𝑃 ) . We\n𝐷𝐴𝐶 𝑜𝑝𝑡 𝐴𝐷𝐶 𝐷𝐸𝑇 𝑆𝐿𝑖𝑀\nhave plotted the energy efficiency against the degrees of freedom (DOFs) in Fig. S14. Our findings\nindicate that in the high-speed experiments, the system efficiency reaches 3.25×103 hOPS/W, while\nconsidering the power consumption of modulators, detectors, optical power sources, Digital-to-\nAnalog Converters (DACs), and Analog-to-Digital Converters (ADCs)….\nZ-shape junctions. Nature Communications 15, 918 (2024).\n1-4 (IEEE).\nWe have also included the discussion of system energy efficiency in the main text and have updated\nthe supplementary table 1.\nMethods Task Depth Cycle time Energy efficiency\nImage Classification\nAcc. 85.4% 100\n(ImageNet 1000 Classes)\nSLiM chip Text generation\n384 0.1 ns\n(Optoelect Loss function value 3.0397 3.25×103 TOPS/Wa\n(96×4) @10 GHz\nronics) (Wikipedia text)\nImage Generation\n(64×10)\n(ImageNet dataset)\na. Calculation includes the power consumption of modulators, detectors, optical power sources,\nDigital-to-Analog Converters (DACs), and Analog-to-Digital Converters (ADCs).\n- Authors state to reach 85.2 % accuracy on ImageNet for 100-layer SLiM, far below 91% reached\nby state-of-the-art digital models. Why this difference? Is the digital sota model not implementable\nwith the SLiM?\nResponse: We thank the reviewer for the comments. In the experiments, the SLiM network for\nimagenet-1000 classification tasks reached 85.4 %, while the purely digital simulation reached 93.0 %\n(as shown in section [Reaching ONNs beyond the depth limit for advanced artificial intelligence)).\nThis is because the SLiM network employs 1-bit weights contains 11.475 MB parameter and thus\nhas smaller model size than the digital model with 32-bit floating point weights of 220.32 MB\nparameter. For fair comparison, we decrease the size parameter of digital model to 11.48MB by\nuniformly reducing the number of channels to (14, 28, 56, 115) in the blocks while maintaining the\ndepth of network. The network accuracy converged to 79.19% accuracy after 90 epochs of training,\nwhich is below the 85.4% accuracy reached by SLiM network.\nRevision:\nWe have updated the SLiM network training in the Methods section [Network architecture and\ntraining methods.] as:\n…We also evaluated digital models of the same size to the 100-layer SLiM network. For both\nnetworks with 11.475 MegaByte parameter, the SLiM network reached 85.4% accuracy, while the\nnetwork of same size with 32-bit floating point weights reached 79.19% accuracy…\n- The theoretical model introduced to justify linear error accumulation across layers (rather than\nexponential) is good but lacks direct empirical validation. It would be useful to show variance or\nerror growth as a function of depth from actual hardware measurements\nResponse: The theoretical model shows that 𝑉𝑎𝑟( Δ𝐴 )≥∑𝐿 𝑉𝑎𝑟( Δ𝑊𝑖), indicating that the\n𝐴 𝑖=1 𝑊𝑖\naccumulation of error in a multi-layer optical neural network scales at least linearly with the number\nof layers. Since our fabricated chip features a single-layer design, this architecture intrinsically\nminimizes cumulative error. To empirically validate this theoretical result, we conducted a\nsimulation experiment in which 10 samples of 10 × 10 matrices were generated, with each element\ndrawn from a standard Gaussian distribution. In each simulation trial, Gaussian noise with a\nstandard deviation of 0.1 was injected into each matrix layer to simulate system errors. The resulting\nmean squared error (MSE) was computed after 10 consecutive matrix multiplications, and the\nresults were averaged across all 10,000 trials. The simulation results, visualized below, confirm a\nclear linear scaling trend in error accumulation with increasing layer depth.\nRevision:\nWe have updated the related discussion and figure analysis in the supplementary note 1, as,\nWe numerically validated the error trend by employing 10 samples of 10×10 matrices, with each\nentry randomly sampled from gaussian distribution. During the validation, a 10×1 random vector is\nsequentially multiplied with these 10 matrices, the computation is gradually distorted with the noise.\nFor example, to analyze the errors with k layers, the first k layers are distorted with the noise. Finally,\nthe errors are calculated for these 10 consecutive matrix multiplications. The above process is\nrepeated for 10000 times and averages, the mean and standard deviation of the errors are plotted as\nFig. S15, which shows a linear scale of the mean errors.\nFig. S15. Analysis of the error accumulation with respect to layers. Left panel: average error, right\npanel: standard deviation.\nReviewer #3 (Remarks on code availability):\nThe paper does not appear to be accompanied by publicly available code, nor does it reference any\nrepository containing implementation details, model weights, or control software used in the\nexperiments. As such, I was not able to assess the usability or reproducibility of the code.\nWithout access to this material, the work remains difficult to replicate and reuse by the broader\ncommunity, particularly for researchers interested in benchmarking or building upon the SLiM\narchitecture. Making this codebase available would significantly increase the impact and credibility\nof the results.\nResponse: We sincerely acknowledge the comments from the reviewer. We have uploaded the code\nand data to a publicly available repository: https://github.com/Yheechou/SLiM.\nWe sincerely acknowledge and follow the correction notes in the text associated file. Regarding the\nLow-power phase modulation, we have followed the suggestion of the reviewer, and the modulation\nefficiency is 0.753 π·cm corresponding to a modulation length of 43.5μm.\nRevision:\nWe have updated the modulation efficiency as,\nWith a calibrated modulation efficiency of 1.7 µW/π (VπL = 0.753 V-cm, as elaborated in [Methods\nLow-power phase modulation] and Fig. S6)."}, {"round": 2, "reviewer_comments": {"reviewer_1": "The reviewer appreciates the authors' explanation and response.\nThe experimental implementation based on TDM technology and chip reusability is well presented. Although the engineering workload is substantial, the approach appears reasonable for demonstrating SLiM's effectiveness.\nHowever, several critical issues remain:\n1. The working principle of the SLiM chip requires further clarification, particularly regarding:\n1.1 The physical implementation of Y=WX in the chip architecture\n1.2 The encoding mechanism for input X\n1.3 The programming mechanism for the weight matrix W\n1.4 The process of obtaining output Y\n1.5 The error tolerance mechanism and whether it relies on O-E-O and A-D-A conversions between layers\nIt is strongly recommended to incorporate SI Figure 14 (chip structure diagram) and Supplementary Note 2 into the main manuscript, supported by clear explanations and relevant equations. Some descriptions create confusion. For instance, Line 125 states, \"as shown in Figure 1b...the inputs x_i are assigned to specific wavelengths lambda_i.\" While this suggests N different wavelengths are individually modulated to encode x_i, SI Figure 14 shows only one input port. The mechanism enabling individual modulation of different wavelengths needs clarification.\n2. The energy consumption claims appear optimistic. The current calculations exclude essential peripheral components (drivers, TIAs) and the energy overhead from necessary O-E-O conversions between layers, as the SLiM chip only performs matrix-vector multiplications.", "reviewer_3": "All my concerns have been addressed.\nPlease, carefully proofread the paper once again."}, "author_response": "Response to referees:\nWe sincerely thank all the reviewers for their constructive and insightful comments. In this response\nletter, we address each remark point by point. Reviewer comments are highlighted in blue, and\ncorresponding changes to the manuscript are marked in red. References specific to this response are\ndenoted as Ref. [rX].\nSummary of the main revisions:\n1. We have provided a detailed working principle of the SLiM chip. Revisions are reflected in\n[Fig. 1 Single-layer photonic computing], and [Supplementary Fig. S14].\n2. We have added further details regarding the SLiM matrix design and realization. Revisions are\nreflected in [Main text].\n3. The entire manuscript has been thoroughly proofread and revised for clarity and precision.\n4. We have provided the source data.\nThe detailed, point-by-point responses are provided below.\n*******************************************************************************\nReviewer #1 (Remarks to the Author):\nThe reviewer appreciates the authors' explanation and response. The experimental implementation\nbased on TDM technology and chip reusability is well presented. Although the engineering\nworkload is substantial, the approach appears reasonable for demonstrating SLiM's effectiveness.\nHowever, several critical issues remain.\nResponse: We sincerely thank the reviewer for recognizing our innovations. Please find our point-\nby-point responses to the comments below.\n1. The working principle of the SLiM chip requires further clarification, particularly regarding:\n1.1 The physical implementation of Y=WX in the chip architecture\nResponse: We thank the reviewer for the comments. The implementation of Y=WX is divided into\nthe realization of X and the realization of W.\nThe implementation of X: as we illustrate in the main text, in single-layer photonic computing\n(SLiM) chip, the inputs 𝑥 are assigned to specific wavelengths 𝜆 . In the experiment, the\n! !\nbroadband light of multiple wavelengths is multiplexed into single channel and is fed into the input\nloading chip consisting of cascaded ring modulators (shown in Fig. 4a and detailed structures\nillustrated in Methods section) for individually configuring the input intensities to specific\nwavelength, after which the light encoding X is fed into the single-layer chip for processing. The\nentire pipeline is shown in Supplementary Fig. S1c.\nThe implementation of W: as we illustrated in the main text, to realize the computing matrix 𝑊, the\ntransmission channels are modulated on chip by exerting wavefront 𝛷, derived from the equation\n𝑊 =|𝐺𝛷|\", with 𝐺 the transmission matrix and 𝛷 the wavefront profile. We introduce on-chip\nperturbative noise to break the correlation, mathematically represented as 𝛷( =𝛷 ·𝑒$%"}, {"round": 3, "reviewer_comments": {"reviewer_1": "All my concerns have been addressed."}, "author_response": "Response: We sincerely thank the reviewer for recognizing our innovations."}]

Decision letter