High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems

Domain: physics
Published: 2025-11-26
Editorial outcome: minor_revision

Abstract
The integration of high-κ dielectrics with two-dimensional (2D) semiconductors has long been limited by the low reactivity of their dangling-bond-free surfaces and the scalability issues of conventional deposition techniques. Here, we report a universal van der Waals (vdW) integration strategy using HfSe2 as a high-κ precursor that is dry-transferred onto MoS2 and WSe2 and fully converted into amorphous HfO2 via plasma oxidation, while preserving atomically flat vdW interfaces. The resulting HfO2/MoS2 and HfO2/WSe2 gate stacks exhibit suppressed interface trap densities (Dit ≈ 7–8 × 1010 cm-2 eV-1) and high dielectric constants (κ ≈ 23). MoS2 n-type field-effect transistors (nFETs) and WSe2 p-type field-effect transistors (pFETs) fabricated with this approach achieve nearly ideal subthreshold swing (≈ 60 mV/dec) and negligible hysteresis (≈ 3 mV). This scalable methodology enables the vertical integration of complementary logic, demonstrated by complementary FET inverters and ring oscillators, establishing a promising route toward three-dimensional, energy-efficient logic technologies.

Introduction
The International Roadmap for Devices and Systems (IRDS) outlines a vertically integrated complementary metal-oxide-semiconductor (CMOS) architecture as a transformative strategy for advancing ultimate scaling design rules1. Within this framework, two-dimensional (2D) van der Waals (vdW) semiconductors, particularly transition metal dichalcogenides (TMDs) such as MoS2 and WSe2, are representative of n- and p-type channels. Known for their immunity to short-channel effects, chemical stability, and high mobility, they outperform strained silicon with similar thinness2–4, making them the most compelling combination for realising future three-dimensional (3D) logic gates5,6. Furthermore, their ability to reduce the overall stack height effectively suppresses parasitic capacitance, whereas their high on-current densities enable exceptional operating frequencies, making them a highly attractive option for advanced 3D integrated circuits7. Despite this promising potential, significant challenges remain for their use in practical applications. The most critical concern is exploring universal high-κ dielectric integration with superior interfacial and dielectric properties for both n- and p-type field-effect transistors (nFET and pFET), respectively, thereby improving gating efficiency in terms of scaled equivalent oxide thickness (EOT) and achieving desirable 3D complementary logic functionality for high-speed and low power dissipation systems considering industrial requirements8.

To date, recent advancements in high-κ dielectric integration on 2D semiconductors have primarily involved direct deposition, native oxidation, and vdW integration. Atomic layer deposition (ALD) is the most preferred method for high-κ dielectric integration owing to its industrial compatibility and capability for wafer-scale integration. However, the dangling-bond-free surface of 2D semiconductors reduces the surface reactivity during initial nucleation, fundamentally leading to non-uniform dielectric formation9–11. To address this issue, surface functionalisation using O2 plasma, UV-O3, and electron-beam irradiation has been introduced to assist the adsorption of precursors by creating activated sites12–18. However, directly modified interfaces introduce defect sites, including chalcogen vacancies in the channel, oxygen vacancies in the dielectric, and impurities, resulting in threshold voltage instability, increased subthreshold swing (SS), and hysteresis19–22. Sb2O3, an inorganic molecular crystal, is an alternative interlayer material23. Its cage-like molecular structure, which is free of dangling bonds, has shown improvements in the interfacial quality, allowing for high-quality ALD-grown dielectrics on 2D semiconductors. However, its relatively low dielectric constant (≈ 11.5) and unproven versatility in other TMDs require further consideration.

Native oxidation, an in-situ process, facilitates chemical conversion within the channel layer, resulting in an atomically sharp interface that is comparable to the SiO2/Si interface24. We recently demonstrated the layer-by-layer oxidation of 2D HfSe2 and HfS2 into HfO2 and HfO2, particularly for the HfSe2 case achieved a low interface charge trap density (Dit) of ≈ 5 × 1010 cm-2 eV-1 25. Moreover, single-crystalline Bi2SeO5 native oxide layers have been successfully integrated even in vertically grown 2D Bi2O2Se channels, enabling fin field-effect transistors and broadening structural freedom26–28. However, this methodology is only feasible for a limited number of channel materials, excluding Mo- and W-based TMDs, which have the highest application potential, thereby restricting its wide adoption in future 3D complementary logic systems.

vdW integration, which forms an atomically smooth vdW interface between the dielectric and channel (i.e., physical separation with weak vdW coupling), ensures the chemical inertness and mechanical stability of 2D semiconductors, making it a promising approach for dielectric integration29–31. vdW integration is typically achieved via transfer methods and can be categorised by the transferred materials, such as single-crystalline dielectrics, amorphous dielectrics, and transferred and oxidised dielectrics. Since the discovery of 2D layered crystalline dielectrics, h-BN has been widely adopted because of its dangling-bond-free surface, which allows for the formation of a clean vdW interface32. Its large-scale synthesis using up to 4-inch wafers has also been demonstrated33, but its inherently low dielectric constant remains a significant limitation for low-power applications. Bi2SeO5 is a single-crystalline vdW-layered dielectric with a high dielectric constant (≈ 16.5). This system has shown potential, but its practical device applications and interface quality require further comprehensive verification34. Zeng et al. reported single-crystalline Al2O3 using intercalative oxidation on an aluminium surface and demonstrated a remarkably reduced interfacial trap density (≈ 8.4 × 109 cm-2 eV-1) with MoS2 35. They fabricated MoS2 FETs that exhibited a low SS of 61 mV/dec at room temperature. Despite this strategy, the minimum EOT is limited to ≈ 0.77 nm owing to the lowered dielectric constant after crystallisation, which remains a challenge for future scaled nodes. Recently, the transfer of ALD-grown amorphous dielectrics (e.g., HfO2 and Al2O3) on a wafer scale has been proposed as an alternative36,37. However, the use of sacrificial layers (e.g., PVA and TRT/PMMA) during the peel-off and lamination processes causes interfacial contamination, leading to increased SS and performance variability38–41. The most recent emerging strategy for vdW integration is to transfer and oxidise the dielectric, which process utilises Hf- and Zr-based TMDs as precursors. Jing et al. reported ultrathin amorphous HfOx sandwiched within vdW heterostructures obtained by the selective thermal oxidation of HfSe2 precursors, demonstrating a low leakage current density (≈ 10−6 A/cm2) and high breakdown field (≈ 9.5 MV/cm)42. Furthermore, the integration of high-κ HfO2 on MoS2 has been achieved by oxidising transferred 2D HfSx layer with UV-ozone treatment, showing promise as a 2D-compatible dielectric with a vdW interface and a low SS of 63.1 mV/dec43. Despite the progress in vdW integration, recent efforts have predominantly focused on n-type 2D semiconductors, leaving p-type 2D semiconductors underexplored. Moreover, the integration of these 2D semiconductors into circuit-level applications within 3D CMOS architectures remains unaddressed, revealing a critical gap toward realising 3D logic gates. Therefore, the scalable and advanced vdW integration of high-κ dielectric must be studied to successfully realise future 2D semiconductor-based 3D CMOS systems.

In this paper, we present a scalable approach for integrating vdW-interface-based high-κ dielectrics on both n- and p-type 2D semiconductors. By transferring HfSe2, a high-κ precursor, onto both MoS2 and WSe2 channels and subsequently converting HfSe2 into HfO2 via controllable plasma oxidation, an atomically flat vdW interface with a suppressed interface trap density (Dit, HfO2/MoS2: ≈ 7.1 × 1010 cm−2 eV−1 and HfO2/WSe2: ≈ 8.4 × 1010 cm−2 eV−1) was achieved. Large-scale ab initio molecular dynamics (AIMD) simulations based on density functional theory (DFT) were performed to clarify the mechanism of the layer-by-layer oxidation in HfSe2 and explain why the HfSe2-to-HfO2 conversion facilitates clean vdW interfaces with MoS2 or WSe2. The HfO2 layer exhibited a high dielectric constant (≈ 23) and low gate leakage current across various EOT ranges. The universality of this approach was further demonstrated by fabricating MoS2 nFET and WSe2 pFET systems, which exhibited nearly ideal SS values of 61 and 63 mV/dec (over four orders of magnitude of IDS) at room temperature (300 K), along with a high on-off ratio (≈ 108) and negligible hysteresis (≈ 3 mV). The consistent results observed in 40 devices further suggest the reproducibility of the proposed vdW interface-integrated FETs. Furthermore, we fabricated a vertically interconnected complementary field-effect transistor (CFET) inverter by sequentially stacking the MoS2 nFET and WSe2 pFET systems, demonstrating a high inverter gain (≈ 115), noise margin (NML, NMH = 98% of 1/2VDD), and reduced static power consumption (≈ 19 pW). Subsequently, ring oscillators (ROs) incorporating the proposed CFETs were demonstrated. These ROs achieved a reduced propagation stage delay time (≈ 1.83 ns), demonstrating their potential for high-performance circuit applications. These findings represent a major step forward in achieving scalable and universal vdW interface engineering, laying the groundwork for the future development of integrated circuits with 3D logic gates for post-Si technology.

Results
Universal high-κ dielectric integration with a vdW interface
Figure 1a illustrates the integration process for a vdW-interface high-κ dielectric onto 2D semiconductor channels. The HfSe2 layer was transferred onto the channel materials and fully oxidised at an oxidation rate of ≈ 2.1 nm/min under pre-investigated oxygen plasma conditions (see details in the Methods section and Supplementary Figs. 2–4). In this manner, only HfSe2 was fully converted into the HfO2 dielectric while sustaining the atomically flat vdW interface, thereby preserving the underlying channel properties (Supplementary Figs. 5–9). The detailed mechanism of the vdW interface-terminated oxidation process is discussed in the following section.

This universal approach was implemented to fabricate both HfO2/MoS2 and HfO2/WSe2 gate stacks, which exhibited atomically smooth vdW interfaces (Fig. 1b, c). Notably, the pristine vdW gap of the HfSe2/TMD (MoS2, WSe2) heterostructure remained intact after oxidation, maintaining the integrity of the clean vdW interface in the HfO2/TMD (MoS2, WSe2) heterostructures. The high-resolution STEM images in Fig. 1d, e further indicate that HfO2 formation is limited to the vdW gaps above the channels, sustaining the channel crystallinity. The observed interfacial gap (≈ 0.3 nm) between HfO2/TMD (MoS2, WSe2) is comparable to the physical vdW gap (defined as the chalcogen-to-chalcogen distance) between MoS2 and WSe2 (Fig. 1d, e). Furthermore, uniform coverage with consistently high vdW interface quality was observed in individual samples, and reproducible morphological results were obtained across multiple samples (Supplementary Fig. 10 and 11), demonstrating the robustness of the proposed vdW interface approach and its potential for broad applicability in various 2D semiconductor device platforms. The robust vdW interface maintained throughout thermal cycling further demonstrates its thermal stability (Supplementary Fig. 22). The scalability of this methodology toward wafer-scale integration will be further investigated in our future work through the combination with large-area 2D precursor formation approaches.

Mechanism of the formation of vdW HfO2/TMD interfaces
To clarify the mechanisms underlying the universal formation of atomically clean HfO2/TMD vdW interfaces via the oxygen plasma oxidation of HfSe2, we performed AIMD simulations within the DFT framework. While extensive AIMD simulations have been performed for the Si oxidation44,45, to our knowledge, the corresponding AIMD simulation study for HfSe2 or is non-existent25,46. Based on extensive testing, we initially established an AIMD protocol that simulates the oxygen plasma HfSe2 oxidation process (Fig. 2a). Briefly, it consists of (1) the introduction of several randomly distributed singlet O (1D) atoms dropping onto the HfSe2 surface with normal-direction velocities assigned according to the Maxwell-Boltzman distribution, (2) a multiple picosecond (ps) NVE-ensemble oxidation MD run that captures the incorporation of O atoms into HfSe2 and the resulting migration and cluster formation of extracted Se atoms, (3) the removal of free-floating Se atoms or clusters, (4) a 1 ps NVT-ensemble quenching MD run with a Nosé-Hoover thermostat, and (5) the repetitive applications of steps (1)–(4) for the progressively oxidising HfSe2 (HfSexOy) model (Supplementary Figs. 12–14). Throughout MD simulations, reflecting the low-temperature plasma experimental condition, we adopted a temperature of 500 K.

Applying the alternating NVE-NVT AIMD scheme to a HfSe2 monolayer modelled by a (3 × 4) supercell (Supplementary Fig. 12) and introducing four impinging O atoms, we first analysed the key atomistic features in the HfSe2 oxidation process (Fig. 2a and Supplementary Fig. 14). Next, as shown in Fig. 2b, we continued the AIMD simulations with an interface model prepared by placing a partially oxidised Hf24Se28O36 (O36) on top of a HfSe2 monolayer (Supplementary Fig. 12) and studied the mechanisms of the layer-by-layer HfSe2 oxidation process. Based on DFT-based energetic analyses, we previously showed that the facile HfSe2-to-HfO2 conversion is allowed because O atoms can replace Se atoms on a HfSe2 surface without a substitution energy barrier25. Through AIMD simulations, we could additionally observe that, upon reacting with HfSe2, impinging O atoms release significant heat (≈ 7 eV per O atom) and, due to thermal vibrations and strong Hf-O interactions, they rapidly (within a few ps) diffuse to Se sites (Supplementary Fig. 13). As the oxidation proceeds and the number of neighbouring O atoms increases in the top HfSexOy layer, Hf atoms that were initially placed planarly began to reconfigure vertically. This results in the formation of voids within the HfSexOy layer, which should act as pathways for the insertion (extraction) of O (Se) atoms into (out of) the deep HfO2/TMD interfacial regions. At the same time, the displaced Se atoms free floated on the HfSexOy surface and upon meeting other Se atoms formed Se clusters. We then observed that these mobile Se atoms remaining at the HfSexOy/HfSe2 interface play an important role in the layer-by-layer oxidation process by preserving the vdW gap until the full HfSexOy-to-HfO2 conversion is completed25.

To examine whether WSe2 and MoS2 behave differently from HfSe2 in forming clean HfO2/TMD vdW interfaces, we next considered a slightly non-ideal O excess condition that will lead to the breakdown of the layer-by-layer oxidation process for HfSe2. Specifically, as shown in Fig. 2c, we prepared the corresponding O36 HfSexOy/MoS2 and HfSexOy/WSe2 interface models (see also Supplementary Fig. 12) and (rather than dropping from the top) introduced four energetic O atoms into the HfSexOy/TMD interfacial region and repeated AIMD simulations. For the HfSexOy/HfSe2 case, we first confirmed that the second bottom HfSe2 layer begins to oxidise in the NVE run as in the first top HfSe2 layer (Fig. 2c top panel). On the other hand, for the HfSexOy/MoS2 and HfSexOy/WSe2 cases, we found that the O atoms cannot oxidise the top surface of MoS2 or WSe2 and continue oxidising the bottom side of HfSexOy (Fig. 2c middle and bottom panel). This difference indicates that compared with HfSe2, which requires precise control of the layer-by-layer process, achieving clean HfO2/TMD vdW interfaces based on plasma oxidation should be easier with MoS2 or WSe2 (Supplementary Figs. 15 and 16). This is in fact consistent with our experimental observations, indirectly validating our AIMD simulations.

Electrical performance of vdW interface-integrated FETs
Figure 3a shows a schematic of the FETs fabricated with the vdW interface-integrated HfO2/MoS2 and HfO2/WSe2 gate stacks, thereby integrating the MoS2 nFET and WSe2 pFET (see the Methods and Supplementary Fig. 1). Optical images and the output characteristics of these devices are shown in Supplementary Fig. 19. The quality of the vdW interfaces between the HfO2 and TMD channels was investigated using multi-frequency C−V measurements (Fig. 3b). The extracted interface trap densities (Dit) for HfO2/MoS2 and HfO2/WSe2 were suppressed to ≈ 7.1 × 1010 and ≈ 8.4 × 1010 cm−2 eV−1, respectively, aligning with the structural and theoretical clarifications discussed above (see details of the measurements and analysis in Supplementary Fig. 17). A high dielectric constant (κ = ≈ 23; see Supplementary Fig. 17) and low gate leakage current were consistently achieved in EOT ranges of 0.5–2.5 nm (Supplementary Fig. 18), indicating high-quality dielectric characteristics. The suppressed leakage current, compared with the crystalline phase, further underscores the intrinsic advantage of maintaining the amorphous phase to ensure low-power device integrity (Supplementary Fig. 19). Notably, the fabricated MoS2 nFET and WSe2 pFET exhibited near-ideal SS values of 61 and 63 mV/dec (over four orders of IDS) at room temperature (300 K), along with a high on-off ratio of ≈ 108 and low gate leakage current of ≈ 10-6 A/cm2. (Fig. 3c). This superior device performance was primarily attributed to the seamless formation of HfO2 on the TMD channels with a well-preserved vdW interface, which suppressed defect formation. The reproducibility of the vdW interface-integrated FETs was demonstrated by the consistent results observed in 40 MoS2 and WSe2 FETs, all fabricated using the same process (Fig. 3c and Supplementary Fig. 23). The stability and reliability of the fabricated FETs were further corroborated by time-dependent electrical performance and bias–temperature stress durability (Supplementary Figs. 24 and 25).

Gate hysteresis is another critical device parameter closely related to the interface quality and defects within the dielectric layer47,48. The hysteresis of the MoS2 nFET and WSe2 pFET was evaluated under varying gate sweeping rates from 0.01 to 0.1 V/s (Fig. 3d). The negligible hysteresis (≈ 3 mV) indicates that the trap states at the vdW interface and within the HfO2 dielectric were suppressed (Fig. 3e, f). This performance demonstrates an improvement over recently reported vdW interface-integrated high-κ dielectrics on a 2D semiconductor, including GdOCl/MoS2 (≈ 5 mV), HfO2/MoS2 (≈ 10 mV), Al2O3/MoS2 (≈ 10 mV), and Ga2O3/MoS2 (≈ 60 mV)37,43,49,50. Furthermore, both the MoS2 nFET and WSe2 pFET demonstrated SS values approaching the Boltzmann limit across all sweep rates without degradation over four orders of IDS. Similar results were observed for various gate-sweeping ranges (Fig. 3g–i). Device simulations incorporating various process nodes were also conducted to investigate the SS and on–off ratio variations of the proposed FETs with respect to the different Dit values (Supplementary Table 3 and Supplementary Figs. 26a and 27). These findings confirm that the proposed vdW integration offers a universal and scalable approach for delivering consistent and predictable performances in 2D semiconductor-based electronics, underscoring its potential for the construction of future low-power complementary logic gates.

3D integrated CFET inverter
Recent advancements, including innovative approaches that leverage monolithic 3D integration, have highlighted the feasibility of 2D semiconductor-based vertical CMOS technology51–58. However, the interfacial degradation associated with integrating conventional high-κ dielectrics and 2D semiconductors remains a critical challenge, limiting the performance of future 3D CMOS integrated circuits. In this study, we demonstrate the feasibility of CFETs by sequentially stacking vdW interface-integrated FETs. A schematic of the 3D structure of the proposed CFET, where the top MoS2 nFET and bottom WSe2 pFET are vertically interconnected, is shown in Fig. 4a (see Supplementary Figs. 1, 28 and 29 for details). In this configuration, the MoS2 nFET and WSe2 pFET share a common gate, and the sources are connected to the same metal pad to form a 3D integrated CMOS inverter. The common gate functions as the input voltage (VIN), whereas the connected drains of the nFET and pFET serve as the output voltage (VOUT). Importantly, in the proposed vdW integration system with a high-κ dielectric, the voltage transfer characteristics of the CFET show highly sharp voltage transitions at different supply voltages (VDD) ranging from 0.5 to 2.0 V (Fig. 4b). VOUT is high (logic ‘1’) when VIN is low (logic ‘0’), and VOUT is reduced to a low level (logic ‘0’) when VIN increases (logic ‘1’), demonstrating an ideal logic functionality. The high VOUT near VDD and low VOUT of ≈ 0.1 mV indicate a well-matched voltage between the two FETs and their low leakage current, as discussed in the previous section. The voltage gain is boosted with the increase of VDD and reaches a peak value of ≈ 115 at VDD = 2.0 V (Fig. 4c). In particular, acceptable voltage gains at a scaled VDD of 0.5 V satisfied the minimum requirement for ultralow-power logic applications1,59–62. Furthermore, the proposed CFET exhibited superior gain and a low-voltage operation capability compared to previously reported CFETs (Fig. 4d). The inverter gain of the fabricated CFET at various supply voltages is among the highest values reported for comparable architectures to date, including conventional Si channels63,64, 2D-Si hybrid channels65,66, and all 2D configurations53,54,67–70 (also in Supplementary Table 1). The demonstrated voltage gain is essential for signal transmission and logic operations in 3D integrated circuits. Similar results were consistently obtained for 10 CFETs integrated using the same fabrication process (Supplementary Fig. 30). The noise margin is another crucial parameter related to stable inverter operation and desirable circuit performance, and it defines the tolerance of the output signal to the signal interference at the input. The enhanced noise margin derived from the sharp and narrow transition in the voltage transfer characteristics was demonstrated (Fig. 4e). The input voltage is defined as logic high (‘1’) when VIN < VIH and logic low (‘0’) when VIN > VIL, indicating the clear and distinct output logic level in the proposed CFET operation. VOH and VOL represent the ideal logic high and logic low levels of the CFET, respectively. Consequently, the high noise margin (NMH) and low noise margin (NML) were calculated by NMH = VOH - VIH and NML = VIL - VOL, resulting in NMH = 0.975 V (97.5% of 1/2VDD) and NML = 0.985 V (98.5% of 1/2VDD), respectively. Both values approached the ideal noise margin (1/2VDD), indicating the high noise tolerance of the vdW interface-integrated CFET. Moreover, all noise margins exceeded 90% at various supply voltages, further indicating the robustness of the proposed CFETs for multistage operation (Supplementary Fig. 31). The static power consumption of the CFET as a function of VDD is shown in Fig. 4f. Notably, a low peak static power of ≈ 19 pW at VDD = 0.5 V was demonstrated, which is the most important characteristic of low-power CMOS logic circuits. The proposed CFET demonstrated significantly reduced static power dissipation compared to currently reported CMOS technologies, including both vertical and planar architectures utilising various channel materials (2D channels, 2D/Si hybrid channels, organic channels, and GaN) with enhanced energy efficiency (Fig. 4g and Supplementary Table 1)65–74. Device simulations based on the proposed structure demonstrated compatibility with current process nodes1, highlighting its potential for energy-efficient, low-power applications in 3D integrated circuits (Supplementary Table 4 and Supplementary Figs. 26b and 32).

RO integrated with CFETs
Here, we present CFET-integrated ROs, demonstrating a 3D CMOS architecture incorporating 2D semiconductors with the potential for low-power and high-performance computing. A schematic and the corresponding circuit diagram of the five-stage RO are shown in Fig. 5a. The RO was realised by cascading five CFET inverters in a closed-loop configuration. An additional inverter stage served as a readout buffer to isolate the oscillator operation from the measurement setup, ensuring accurate signal extraction without interference. The same configuration applies to the three-stage RO (see Methods and Supplementary Figs. 1 and 33 for details). Figure 5b shows the output oscillation signals of the three- and five-stage ROs measured at VDD = 2.0 V. Both configurations exhibited stable and periodic oscillation with suppressed signal loss. Furthermore, consistent results were also achieved under various supply voltages varying from 0.5 to 2.0 V (Fig. 5c and Supplementary Fig. 34). This is attributed to high-quality vdW interface-integrated FETs and their seamless extension into vertically interconnected high-performance CFET architectures. The corresponding propagation delay time per stage, defined as τpd = 1/2Nf (where N is the number of RO stages and f is the oscillation frequency) at VDD = 2.0 V was ≈ 1.83 and ≈ 1.85 ns for the three- and five-stage ROs, respectively. The similar τpd values of these ROs further indicate their stability and robustness. Moreover, the fabricated ROs demonstrated a competitive advantage with low driving voltages and fast propagation stage delay times compared to previously reported ROs fabricated with various 2D semiconductors, organic materials, CNT, oxides, and Si/GaN channels (Fig. 5d and Supplementary Table 2), outperforming the reported experimental results63,67,73–82. Further optimisation, including the suppression of parasitic capacitances, reduction of contact resistance, and aggressive gate-length scaling is expected to further enhance the signal delivery and overall performance, achieving levels comparable to those of advanced technology nodes (Supplementary Fig. 35).

Methods
Fabrication of the HfO2/TMD heterostructure
The exfoliation and transfer processes were performed in a glove box in a controlled environment to prevent external perturbations (where both the O2 and H2O concentrations were < 0.1 ppm). The thickness of the material was first identified using an optical microscope, and then accurately determined using an atomic force microscope. MoS2 and WSe2 were first transferred onto a SiO2/Si substrate, followed by transferring HfSe2. Then, O2 plasma oxidation was performed under fixed conditions (a power of 10 W, flow rate of 5 sccm, and pressure of 470 mTorr) for HfO2 formation as a high-κ gate dielectric with an atomically flat vdW interface. The polymethylmethacrylate (PMMA) layers were spin-coated at 2000 rpm for 5 s and 4000 rpm for 35 s. Each layer was baked at 180 °C for 2 min on a hot plate. Electron-beam lithography (EBL) and electron-beam deposition were used to form source/drain and top-gate electrodes with Au in a high-vacuum chamber (5 × 10−7 Torr).

Fabrication of FET
MoS2 and WSe2 flakes (≈ 5 nm) were exfoliated using Scotch tape and subsequently dry-transferred onto a SiO2/Si substrate. Source and drain electrodes were defined using standard EBL, followed by the deposition of 10-nm Au metal. After lifting off the metal in acetone, HfSe2 (≈ 25 nm) was dry-transferred and oxidised for 5 min to form HfO2 layers (≈ 10 nm) under the given plasma conditions. The top gate was patterned, and a 30-nm Au layer was deposited to serve as the top gate electrode.

Fabrication of CFET and RO
For the CFET, the bottom WSe2 pFET was fabricated using the same procedure as the FET described above. The fabricated HfO2/MoS2 heterostructure was then transferred onto the top gate of the WSe2 pFET via an advanced transfer method using PMMA-coated PDMS considering adhesion and annealed for 30 min to release the HfO2/MoS2 heterostructure via the full decomposition of the PMMA layer. Au source and drain electrodes were then patterned and deposited. In this configuration, the common gate functions as VIN, whereas the connected drains serve as VOUT. These sources act as VDD and GND, respectively. For the ROs, the single-stage fabrication process was identical to that used for the CFETs in both the three- and five-stage designs. To connect each stage, the VOUT of each stage was connected to the VIN of the next stage, and all VDD and GND systems were linked using the same metal pad. Additionally, to reduce the interference between the closed loop and measurement setup, VOUT was connected to an additional readout buffer stage.

Sample characterisation
OM (Olympus, BX51M) and FE-SEM (JEOL, JSM7500F) were used to observe the sizes and colours of the prepared samples and fabricated devices. Raman spectroscopy at an excitation wavelength of 523 nm was used to characterise MoS2, WSe2, and the fully converted HfO2. The thickness of the flakes was determined using an atomic force microscope (Park Systems Corp., NX-10) in the non-contact mode with PPP-NCHR probe tips (nanosensors). The cross-sections were observed using transmission electron microscopy (TEM, JEOL, TEM2100F) at an accelerating voltage of 200 kV.

Electrical characterisation
All the electrical measurements were performed in a probe station (MSTECH) with a vacuum pressure of 10-6 Torr using a semiconductor analyser (Keithley 4200) and an oscilloscope (Tektronix TBS1154). A Keithley 4200 instrument was used to provide the supply voltage to all the devices in this study. A Tektronix TBS1154 instrument was used to measure the output waveforms of the vdW interface-integrated ROs.

Computational details
DFT calculations were performed using the VASP package with the projected augmented wave method83. Many-electron exchange-correlation interactions were treated within the Perdew-Burke-Ernzerhof form of generalised gradient approximation84. The weak long-range dispersion interactions were described within the Grimme’s DFT-D3 method85. The kinetic energy cut-off for the plane wave basis was set at 500 eV, and the 2 × 4 × 1 Monkhorst–Pack k-point samplings were used in the structural relaxation for 2D planar structures of TMDs. The atomic structures were optimised until the total energy and the Hellmann-Feynman forces on each atom reached the 10-4 eV and 0.01 eV/Å levels, respectively. AIMD simulations were performed by iterative NVE-NVT dynamics. NVE ensemble dynamics runs a few ps (less than 5 ps) until local configuration of oxygen does not change and NVT ensemble dynamics runs for 1 ps with a Nosé–Hoover thermostat to quench the system to 500 K. Throughout the AIMD procedure, a timestep of 1 fs was used, and Brillouin zone sampling was restricted to the Γ-point.

TCAD simulations
Device analysis was performed using Synopsys Sentaurus (Synopsys Inc., Mountain View, CA, USA), a 3D technology computer-aided design (TCAD) software package.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This study demonstrates the integration of high-k dielectrics with n- and p-type 2D semiconductors through dry transfer and plasma oxidation techniques, achieving high-quality van der Waals interfaces. The fabricated devices exhibit low interface trap density, negligible hysteresis, high on/off ratios, and steep sub-threshold swings. Furthermore, this work pioneers the experimental integration of 2D semiconductors into CFET via ring oscillators. This approach provides a significant technical pathway for implementing 2D materials and high-k dielectrics in semiconductor applications, facilitating the translation of related research toward practical implementation. There are many concerns that require attention:\n1. It seems that this strategy based on transfer method can’t be scalable. How to improve it to fabricate a large area (such as cm-scale) device integration? And some simple and scalable evaporation processes reported can achieve these results.\n2. Supplementary Figure 3(ii) EELS Data: Could an oxygen elemental line profile across the vertical interface or an elemental mapping near the interfacial region be provided? This would allow for a more intuitive assessment of the impact of oxygen plasma oxidation on the underlying TMDs layer.\n3. Oxygen Plasma Power: The comparative experiments at 10W, 20W, and 30W show that 10W yields the best results. However, as 10W is the lowest tested power, could a lower power control group (e.g., 5W) be considered? It would be valuable to know whether interface quality and device performance might be further improved at powers below 10W.\n4. Figure 4(b), (c), (e), (f) Visualization: Would it be possible to present these panels in color? The grayscale format makes it difficult to distinguish between the different datasets during reading.\n5. HfSe₂ Thickness Dependence: Does the pre-transfer thickness of HfSe₂ affect device performance, and if so, how? Could an excessively thin HfSe₂ layer lead to oxidation of the underlying semiconductor during plasma oxidation? Conversely, could an excessively thick HfSe₂ layer result in incomplete oxidation of HfSe₂, thereby affecting hysteresis improvement?\n6. Method Generalizability & Functionalization: Regarding the extensibility of the experimental method: Could this approach be applied to oxidation-prone 2D semiconductor materials? Additionally, could post-processing be used to crystallize the formed amorphous HfO₂ and possess the memory performances?\n7. Supplementary Table 1: There appears to be a spelling error in the abbreviation for 'Demonstrations', it is typically abbreviated as \"demos\" rather than \"demons\".\nBased on these concerns, it is recommended that the manuscript can’t be published in Nature Communications.", "reviewer_2": "The authors demonstrate a universal method for integrating high-κ dielectrics by converting dry-transferred HfSe₂ into HfO₂ via oxygen plasma oxidation. This process yields high-quality vdW interfaces on both n-type (MoS₂) and p-type (WSe₂) 2D semiconductors. The resulting HfO₂/TMD gate stacks exhibit excellent electrical properties, enabling the fabrication of high-performance vdW FETs. With this method, the authors successfully fabricated and vertically interconnected complementary field-effect transistors (CFETs) comprising MoS₂ nFETs and WSe₂ pFETs, showcasing promising potential for future 3D logic applications. While the research holds scientific merit, the following concerns should be addressed:\n1. The abstract should more explicitly articulate the scientific problem addressed and the core innovation. The claim of \"first experimental integration\" of CFET-based ring oscillators, while notable, may inadvertently overshadow the study's more fundamental innovation. Emphasizing universal high-κ integration methodological advance would provide clearer focus on the primary scientific contribution.\n2. The reported constant oxidation rate (~2.1 nm/min) across thicknesses appears inconsistent with conventional understanding, where surface oxide layers typically impede further oxidation (e.g., as observed in aluminum oxidation to Al₂O₃, Nature 632, 788–794 (2024)). Please provide a mechanistic explanation for this observed behavior. Furthermore, clarify if this linear rate is expected to hold for significantly thicker layers (e.g., approaching the cm scale) or if limitations exist.\n3. Could heat accumulation during prolonged plasma exposure lead to temperature increases that significantly alter the oxidation rate? Please discuss potential thermal effects inherent to the plasma process and their possible influence on reaction kinetics and uniformity.\n4. Regarding the layer-by-layer oxidation mechanism: (1) Is it feasible to optimize conditions to achieve layered crystalline HfO₂ instead of amorphous HfO₂? (2) What is the minimum achievable HfO₂ thickness using this method? Please elaborate on these aspects.\n5. The uniformity of the 40 n-type and p-type devices shown in Fig. 3c appears relatively poor. What are the primary factors contributing to this performance variation? Is the non-uniformity primarily attributed to variations in the HfO₂ layer itself, or are other process steps?\n6. Formatting and presentation issues:\n(1) When referring to multiple figures, use \"Figs.\" (e.g., \"Figs. 1a and 2b\" instead of \"Fig. 1a and Fig. 2b\").\n(2) Some scientific notations use the letter \"x\" instead of the proper multiplication symbol \"×\"(e.g. page 3, line 10). It is need to review this article carefully and correct them.\n(3) At page 6, line 15, \"an 1 ps NVT-ensemble\" should be corrected to \"a 1 ps NVT-ensemble\".\n(4) The arrows (e.g. length, width, head shape, and color) in Fig.2 require standardization.\n(5) The color schemes employed in (b), (c), (e), and (f) of Figure 4 exhibit poor visual harmony with adjacent charts, significantly reducing readability.", "reviewer_3": "This manuscript presents a significant advancement in 2D semiconductor technology by demonstrating universal high-κ dielectric integration using vdW interfaces. The authors develop a scalable approach where HfSe2 precursors are transferred onto both n-type MoS2 and p-type WSe2 channels, followed by controlled plasma oxidation to convert HfSe2 into HfO2 while preserving atomically clean vdW interfaces. The work achieves suppressed interface trap densities and demonstrates near-ideal subthreshold slopes. A complementary field-effect transistor (CFET) and ring oscillators (ROs) are also been successfully achieved. Prior to the possible publication, the following concerns should be addressed:\n1. The plasma oxidation process appears critical for success. What is the process window for the oxidation parameters (power, pressure, time)? How sensitive is the interface quality to variations in these parameters, and what quality control metrics would be necessary for manufacturing?\n2. In Figure 3, as hysteresis is highly sensitive to sweep rate, bias range, and temperature, the claimed ~3 mV hysteresis requires more comprehensive validation beyond the limited conditions shown. Please provide systematic characterization across wider temperature ranges and broader sweep rates.\n3. What are the specific device dimensions (channel length, width, and area) for the FETs characterized in Figure 3? The transfer characteristics should be presented as current density rather than absolute current values to enable proper benchmarking against literature and industry standards.\n4. The manuscript lacks comprehensive thermal stability analysis. Given that the vdW interface is maintained through weak interactions, how does the HfO2/TMD interface behave under thermal cycling conditions relevant to practical applications? What is the long-term reliability of these interfaces under bias-temperature stress?\n5. Regarding Figure 5, while the CFET ring oscillator demonstration is impressive, the achieved frequency (~91 MHz) remains below the record 2.65 GHz (https://doi.org/10.1038/s41928-023-01052-5). Could the authors provide a critical analysis of the limiting factors (parasitic capacitances, contact resistance, channel mobility, etc.) and discuss the roadmap for achieving competitive frequencies? What are the fundamental and engineering challenges that need to be addressed to reach GHz-level performance comparable to advanced silicon technologies?\n6. Line 89 correction, “..the minimum EOT is limited to ~1.5 nm ...” should be \"~0.77 nm\" as claimed in reference 35."}, "author_response": "Response to Reviewer #1\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in red.\nComments:\nThis study demonstrates the integration of high-κ dielectrics with n- and p-type 2D\nsemiconductors through dry transfer and plasma oxidation techniques, achieving high-quality\nvan der Waals interfaces. The fabricated devices exhibit low interface trap density, negligible\nhysteresis, high on/off ratios, and steep sub-threshold swings. Furthermore, this work pioneers\nthe experimental integration of 2D semiconductors into CFET via ring oscillators. This\napproach provides a significant technical pathway for implementing 2D materials and high-κ\ndielectrics in semiconductor applications, facilitating the translation of related research toward\npractical implementation. There are many concerns that require attention: Based on these\nconcerns, it is recommended that the manuscript can’t be published in Nature Communications.\n1. It seems that this strategy based on transfer method can’t be scalable. How to improve it to\nfabricate a large area (such as cm-scale) device integration? And some simple and scalable\nevaporation processes reported can achieve these results.\n (Approaches for large-area integration) We acknowledge the reviewer’s concern and\nagree that complementary strategies are essential to fully realise large-area integration. In\nthis regard, we are actively investigating two scalable approaches for large-area 2D\nprecursor formation and oxidation directly on MoS and WSe channels. One promising\n2 2\nroute involves the vdW heteroepitaxy of 2D precursors such as HfSe via a CVD process—\n2\nwhose large-area growth has recently been demonstrated [R1,2]— followed by controlled\noxidation to form HfO (left panel of Fig. R1a and Fig. R1b). In parallel, we are also\n2\nexploring the large-area formation of 2D precursors via printing processing [R3,4],\nfollowed by plasma oxidation to convert them into high-κ dielectrics (right panel of Fig.\nR1a and Fig. R1b). Importantly, while channel applications require high crystalline\nquality, in our case the 2D precursor is intentionally oxidised into an amorphous phase,\nmaking the initial crystalline quality less critical and thus providing a more straightforward\npathway for large-area integration.\nIn fact, recent advances have established large-area transfer methods as one of the viable\napproaches for mass production of 2D semiconductor-based electronics, including the dry\ntransfer of ultrathin ALD-grown dielectrics [R5], the lamination of prefabricated Y O\n2 3\ngate stacks [R6], wafer-scale vdW contact integration on CVD-grown MoS [R7], mass\n2\ntransfer printing of over one million MoS arrays [R8]. Furthermore, key industrial players\n2\nsuch as Samsung Electronics have already demonstrated 200-mm wafer-scale integration\nof polycrystalline MoS TFTs using MOCVD growth combined with automated transfer\n2\nin an industrial standard 200-mm fab facility [R9]. These reports collectively highlight\nthat large-area transfer is being seriously evaluated in both academia and industry as one\nof the practical routes toward mass production of 2D semiconductor electronics.\nIn summary, in line with the reviewer’s comment, we are actively pursuing large-area\nprecursor formation and oxidation strategies—including CVD growth and printing-based\napproaches—as complementary routes towards universal and scalable vdW integration,\nwhich will be systematically investigated in our future work.\nFigure R1. Scalable approaches for wafer-scale 2D precursor formation. a, Possible\npathways for large-area 2D precursor formation, including vdW heteroepitaxy (left panel)\nand printing process (right panel). b, Schematic illustration of the 2D precursor-to-\ndielectric conversion process for wafer-scale integration, highlighting the transformation\nof 2D precursor into high-κ dielectrics and their incorporation into scalable device\nplatforms.\nTo indicate to readers the potential extension towards large-area integration, the revised\nmanuscript briefly includes the following description:\n“…… 2D semiconductor device platforms. The scalability of this methodology toward\nwafer-scale integration will be further investigated in our future work through the\ncombination with large-area 2D precursor formation approaches.”\n(revised Manuscript, page 6)\nReferences\n[R1] Chu, W. et al. Stable alkali halide vapor assisted chemical vapor deposition of 2D HfSe₂\ntemplates and controllable oxidation of its heterostructures. Front. Phys. 19, 33212 (2024).\n[R2] Huang, J. et al. Van der Waals epitaxy of high-quality transition metal dichalcogenides\non single-crystal hexagonal boron nitride. Small Methods 9, 2401296 (2024).\n[R3] Kim, M. et al. Sub-stoichiometric zirconium oxide as a solution-processed dielectric for\nreconfigurable electronics. Nat. Commun. 16, 1210 (2025).\n[R4] Kim, J., Rhee, D., Song, O. et al. All-Solution-Processed Van der Waals Heterostructures\nfor Wafer-Scale Electronics. Adv. Mater. 34, 2106110 (2022).\n[R5] Lu, N. et al. Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals\nintegration. Nat. Commun. 14, 1014 (2023)\n[R6] Wang, L. et al. A general one-step plug-and-probe approach to top-gated transistors for\nrapidly probing delicate electronic materials. Nat. Nanotechnol. 17, 1206–1213 (2022).\n[R7] Yang, P. et al. Highly reproducible van der Waals integration of two-dimensional\nelectronics on the wafer scale. Nat. Nanotechnol. 18, 471–478 (2023).\n[R8] Liu, L. et al. A mass transfer technology for high-density two-dimensional device\nintegration. Nat. Electron. (2025).\n[R9] Kwon, J. et al. 200-mm-wafer-scale integration of polycrystalline molybdenum disulfide\ntransistors. Nat. Electron. (2024).\n2. Supplementary Figure 3(ii) EELS Data: Could an oxygen elemental line profile across the\nvertical interface or an elemental mapping near the interfacial region be provided? This would\nallow for a more intuitive assessment of the impact of oxygen plasma oxidation on the\nunderlying TMDs layer.\n (EELS line-scan analysis of HfO 2 /TMD) Following the reviewer’s suggestion, the O–K\nedge spectra have been provided as a function of vertical distance in the revised\nSupplementary Fig. 3c. In this EELS analysis, the O–K edge intensity was acquired along\na vertical line scan across the red dotted square region, starting from the HfO surface and\n2\nextending down to the channel (denoted as the depth from the surface), thus covering the\noxidised HfO layer, the vdW interface, and the underlying TMD channels (MoS or\n2 2\nWSe ). The sharp decay of the O–K signal at the HfO /TMD channel interface indicates\n2 2\nthat the channel remains intact after oxidation, with no evidence of oxygen-induced\nreactions, thereby reaffirming the robustness of the proposed methodology. The inset of\nthe revised Supplementary Fig. 3c presents the corresponding O–K signal collected at an\nenergy loss of 523 eV for each region.\n (Detailed analytical protocol for ensuring result reliability) For quantitatively reliable\nsignal collection, the O–K edge signal was carefully extracted after subtracting the\nbackground scattering contribution, and subsequently corrected for the local specimen\nthickness to eliminate artificial variations arising from thickness differences across the\nlamella [R1]. Since the EELS signal intensity is proportional to the number of atoms\nencountered along the electron path, regions of greater thickness inherently yield stronger\nO–K edge signals even at identical oxygen concentrations. Without such correction,\napparent variations in the O–K intensity would simply reflect differences in lamella\nthickness rather than true changes in oxygen concentration [R2]. After correction for the\nlocal thickness (t/λ), we ensured that the extracted O–K profile represents genuine\ncompositional variations rather than geometrical artefacts. To minimize additional\nartefacts, low-dose acquisition and short dwell times were used, and no progressive\nincrease in the oxygen signal was observed in repeated scans [R3].\nIt has been incorporated into the revised Supplementary Information as follows:\nSupplementary Figure 3. Structural analysis of the HfO /TMD (MoS , WSe )\n2 2 2\nheterostructure. a, Cross-sectional STEM images of the HfSe /TMD (MoS , WSe )\n2 2 2\nheterostructure (i) and HfO / TMD (MoS , WSe ) heterostructure after 5 min of plasma\n2 2 2\noxidation (ii), clearly showing the complete oxidation of the top-stacked HfSe layer with the\n2\natomically flat vdW interface with a given O plasma oxidation condition (10 W, 5 sccm, and\n2\n470 mTorr). The insets in the right panel show the FFT patterns of the fully converted HfO\n2\nand the underlying channel materials. b, Corresponding thickness profiles of the structures\nshown in Supplementary Fig. 3a. c, EELS spectra collected along the yellow-arrowed vertical\nline scan across the HfO /TMD (MoS , WSe ) heterostructure within the red dotted square\n2 2 2\nregion, traversing the oxidised HfO₂, the vdW interface, and the underlying TMD channels\n(normalised to the maximum O–K intensity in the HfO ). Within the detection limit of ~1–2\n2\nat.% oxygen, the O–K signal exhibits a sharp decay at the vdW boundary, with no detectable\nsignal inside the TMD. This confirms that oxygen plasma oxidation is confined to the HfSe -\n2\nderived HfO layer and does not measurably oxidise the underlying channel, thereby preserving\n2\nits properties after the oxidation process. The inset shows the O–K edge intensity as a function\nof energy loss.\n(revised Supplementary Information, page 9)\nReferences\n[R1] Iakoubovskii, K. et al. Thickness measurements with electron energy loss spectroscopy.\nMicrosc. Res. Tech. 71, 626–631 (2008).\n[R2] Egerton, R. F. Electron energy-loss spectroscopy in the electron microscope.\n[R3] Valencia et al. Induced damage during STEM-EELS analyses on acrylic-based materials.\nUltramicroscopy 234, 113557 (2022).\n3. Oxygen Plasma Power: The comparative experiments at 10W, 20W, and 30W show that 10W\nyields the best results. However, as 10W is the lowest tested power, could a lower power control\ngroup (e.g., 5W) be considered? It would be valuable to know whether interface quality and\ndevice performance might be further improved at powers below 10W.\n As the reviewer commented, we previously examined the oxidation characteristics under\nlower plasma power conditions to explore the possibility of further optimised oxidation,\nand the corresponding findings are provided here for clarity. Approximately 25 nm of\nHfSe samples were oxidised under the lowest accessible power of our system (5 W, 5\n2\nsccm, 470 mTorr), yielding ~10 nm-thick HfO layers. Cross-sectional STEM imaging\n2\n(Fig. R2a) reveals locally unconverted HfSe domains embedded within the HfO layer,\n2 2\nsignifying incomplete oxidation under reduced plasma power. To quantitatively examine\nthe residual Se atoms, XPS depth profiling was further conducted (Fig. R2b). For this\nanalysis, the HfO samples were sequentially thinned by ~2.5 nm at a sputtering rate of\n2\n0.5 nm/min, and the XPS spectra were collected after each thinning step. In contrast to the\n2\nsignal was detected, distinct Se 3d peaks were observed under the lower-power condition.\nThis finding is consistent with the locally unconverted HfSe region in the cross-sectional\nImportantly, we respectfully note that the device characteristics achieved under the 10 W\ncondition already approach the Boltzmann limit (~60 mV/dec at room temperature).\nTherefore, even if further lowering of plasma power were experimentally feasible, it would\nbe unlikely to yield any meaningful improvement in interface quality or device\nperformance. On this basis, we consider 10 W to represent the optimised condition,\nbalancing complete oxidation of HfSe with preservation of the atomically flat vdW\n2\ninterface integrity.\nFigure R2. Characterisation of HfO converted under lower plasma power condition.\n2\na, Cross-sectional STEM image of HfO formed from HfSe under reduced plasma power\n2 2\n(5 W, 5 sccm, 470 mTorr). b, XPS depth profiling of the converted HfO layer. The O 1s\n2\nand Se 3d peak ratios were monitored from the top surface of the ~10 nm HfO down to\n2\nthe bottom through sequential thinning steps at a sputtering rate of 0.5 nm/min. The\ndetection of the Se 3d signal at a depth of ~5 nm indicates the presence of locally\nunconverted HfSe . These results indicates that such low-power plasma conditions are\n2\ninsufficient to ensure complete oxidation of HfSe into HfO .\n2 2\nSupplementary Figure 4. Characterisation of fully converted HfO . a, Cross-sectional\n2\ncondition (10 W, 5 sccm, and 470 mTorr). No noticeable selenium atoms were detected in\nthe atomic distribution. b, Raman spectra of 12 fully converted HfO samples prepared\n2\nusing the same plasma oxidation process. In most samples, negligible peaks were observed,\nsuggesting the amorphous nature and full conversion of HfO . c, XPS depth profiling of\n2\nfully converted HfO . XPS peak detection ratio of O 1s and Se 3d from the top surface of\n2\nthe 10 nm HfO to the bottom obtained through sequential thinning steps with a sputtering\n2\nrate of 0.5 nm/min. The unnoticeable detection of the Se 3d spectra from the top surface\nto the bottom further suggests that the entire HfSe layer was fully oxidised. These results\n2\nindicate the full conversion of HfO .\n2\n4. Figure 4(b), (c), (e), (f) Visualization: Would it be possible to present these panels in color?\nThe grayscale format makes it difficult to distinguish between the different datasets during\nreading.\n Following the reviewer’s suggestion, the color schemes of Figure 4 panels (b), (c), (e), and\n(f) have been adjusted to improve visual harmony, and the revisions have been reflected\nin the revised Manuscript as follows:\nFigure 4. Vertically stacked CFET fabricated with vdW interface-integrated MoS nFET\n2\nand WSe pFET. a, Structural schematic of the CFET. GND, V , V and V represent\nground, input voltage, supply voltage and output voltage for the CFET, respectively. b,c,\nVoltage transfer characteristics and corresponding voltage gain as a function of V .\nDD\nd, The\nvoltage gain comparison of the CFETs fabricated with 2D semiconductor/Si hybrid channel,\n2D semiconductor channel, and Si channel, including proposed vdW interface-integrated\nCFET55,56,65,66,67,68,69,70,71,72. e, Voltage transfer characteristic and its mirror reflection at V =\nDD\n2.0 V. The V , V , V , and V represent the minimum high output voltage, maximum low\nOH OL IL IH\noutput voltage, maximum low input voltage, and minimum high input voltage, respectively.\nThe noise margin is determined by nesting the largest square (grey shading). The dashed lines\n(black) are auxiliary lines for extracting the value of V , V , V , and V .\nf, Static power\nOH OL IL IH\nconsumption of the proposed CFET as a function of V .\nDD\ng, Comparison of static power\nconsumption at various V with literature reports67,68,69,70,71,72,73,74,75,76.\nDD\n(revised Manuscript, page 27)\n5. HfSe Thickness Dependence: Does the pre-transfer thickness of HfSe affect device\n2 2\nperformance, and if so, how? Could an excessively thin HfSe layer lead to oxidation of the\n2\nunderlying semiconductor during plasma oxidation? Conversely, could an excessively thick\nHfSe layer result in incomplete oxidation of HfSe , thereby affecting hysteresis improvement?\n2 2\n (Impact of excessively thin HfSe 2 thickness on channel integrity after oxidation) To\naddress the reviewer’s concern regarding the oxidation of excessively thin HfSe , we\n2\ninvestigated the case of monolayer HfSe (~0.65 nm), which represents the minimum\n2\nthickness of the 2D precursor in the proposed methodology. Cross-sectional STEM\nanalysis confirmed the formation of an ultrathin HfO layer with a thickness of ~0.3 nm,\n2\nconsistent with the expected volume ratio of ~1:2.3 between HfO and HfSe (Fig. R3a\n2 2\nand b). Importantly, the crystallinity of the underlying channels was preserved under this\nextreme condition, suggesting the retention of intact channel properties and the formation\nof an atomically flat vdW interface. Under such extreme scaling, clear pinholes were\nobserved, where excessive thinning induces morphological discontinuities and potential\nleakage paths. This observation aligns with our theoretical model of the oxidation pathway,\nin which local voids/holes are transiently generated and subsequently recovered with the\noxidation of the second HfSe layer (Supplementary Fig. 14). In the ultrathin regime, this\n2\nrecovery remains incomplete, leading to morphological discontinuities. Notably, once the\nconverted HfO thickness exceeded ~2 nm, such pinhole features were no longer observed,\n2\nand the films became morphologically uniform and continuous with the atomically flat\nvdW interface integrity (Fig. R3c,d).\nFigure R3. Integrity of HfO converted from thin HfSe a,b, Cross-sectional STEM\n2 2.\nimages of HfO /MoS and HfO /WSe heterostructures formed by transferring and\n2 2 2 2\noxidising monolayer HfSe Despite the excessive thinning of the HfO layer (~0.3 nm),\n2. 2\nthe underlying channel crystallinity remains intact after the oxidation process with\natomically flat vdW interface. c,d, Cross-sectional STEM images of HfO /MoS and\n2 2\nHfO /WSe heterostructures showing the formation of a uniform HfO layer once the\n2 2 2\nconverted thickness exceeds ~2 nm. In this case as well, the integrity of the atomically flat\nvdW interface is maintained.\n (Influence of excessively thick HfSe 2 on the complete oxidation process) The oxidation\nbehaviour of excessively thick HfSe was also examined. HfSe samples with a uniformly\n2 2\nattainable maximum thickness of ~120 nm were oxidised under plasma conditions of 10\nW, 5 sccm, 470 mTorr, and 25 min, yielding an ~50 nm-thick HfO layer. Cross-sectional\n2\nanalysis revealed no detectable Se atoms in the EDS mapping, indicating complete\nconversion of the pristine ~120 nm HfSe into HfO (Fig. R4a). To further quantify any\n2 2\npotential residual Se atoms, XPS depth profiling was performed (Fig. R4b). For this\nanalysis, the HfO samples were sequentially thinned by ~2.5 nm at a sputtering rate of\n2\n0.5 nm/min, and XPS spectra were collected after each thinning step. The absence of\ndetectable Se 3d signals from the top surface to the bottom further confirms that the entire\n~120 nm HfSe was fully oxidised. These results demonstrate the complete conversion of\n2\nexcessively thick HfSe into HfO .\n2 2\nFigure R4. Complete oxidation of HfO converted from thick HfSe a, Cross-sectional\n2 2.\nSTEM image and corresponding elemental mapping of an ~50 nm HfO layer converted\n2\nfrom ~120 nm thick HfSe . b, XPS depth profiling of the converted HfO layer. The O 1s\n2 2\nand Se 3d peaks were monitored from the top surface of the HfO down to the bottom\n2\nthrough sequential thinning steps at a sputtering rate of 0.5 nm/min. The absence of\ndetectable Se 3d signals throughout the overall depth profile indicates the full conversion\nof the pristine ~120 nm HfSe . These results demonstrate that relatively thick HfSe can\n2 2\nbe fully converted into HfO under the given plasma conditions (10 W, 5 sccm, 470 mTorr)\n2\nemployed in this study.\nSupplementary Figure 14. Alternating NVE-NVT protocol AIMD simulations for the\nplasma HfSe oxidation. We repeated the alternating NVE-NVT AIMD simulations (filled\n2\nlight green boxes). Each NVE oxidation MD step begins with oxygen insertion and ends with\nspontaneous oxidation and structural rearrangement; its final configuration, after removing\nfloating Se atoms (highlighted by black circles), serves as the initial state for the subsequent\nNVT quenching MD step. Upon completing each NVE MD run, detached Se atoms were\nremoved, and the system is equilibrated to 500 K using NVT MD simulations for 1 ps. This\nNVE-NVT sequence continues until the partially oxidised model (Hf Se O referred to as\n24 28 36\nO ) is obtained. As oxidation progresses, three-dimensional Hf-O coordination develops,\n36\nforming a porous structure with voids appearing in the 2D lattice, indicated by black circle in\nthe final snapshot. AIMDs for the generation of O\n6\nmodel (Hf\n6\n) and O\n36\n(Hf\n36\n)\nare provided in Supplementary Video 1,2.\n6. Method Generalizability & Functionalization: Regarding the extensibility of the\nexperimental method: Could this approach be applied to oxidation-prone 2D semiconductor\nmaterials? Additionally, could post-processing be used to crystallize the formed amorphous\nHfO₂ and possess the memory performances?\n (Applicability to oxidation-prone 2D semiconductor) Please note that this important\npoint has been carefully considered throughout our initial studies I [Nanoscale 10, 18758–\n18766 (2018)] and II [Adv. Mater. 36, 2312747 (2024)] in addition to this submission III\n(Fig. 2a–c and Supplementary Figs. 12–16). Out of the four 2D semiconductors considered\nin Refs. I, II, and III, HfS , HfSe , MoS , and WSe , while MoS and WSe represent the\n2 2 2 2 2 2\noxidation-resistant 2D semiconductors, HfS and HfSe represent the most oxidation-\n2 2\nprone 2D semiconductors. Please also note that, as emphasised in II, HfSe can be more\n2\neasily oxidised than HfS . Importantly, we have demonstrated in II the layer-by-layer\n2\noxidation is possible even for HfSe and explained its mechanism based on energetics and\n2\nvia ab initio molecular dynamics simulations in II and III, respectively. This then implies\nthat the approach to achieve the high quality HfO interface with 2D semiconductors\n2\nreported in this submission III is generally applicable to oxidate-prone 2D semiconductors.\n (Post-processing for crystallisation) To assess the possibility of crystallising HfO 2 via\npost-processing, we performed a rapid thermal annealing process. Approximately 25 nm-\nthick HfSe samples were prepared and subsequently oxidised under the specified plasma\n2\nconditions (O gas, 10 W, 5 sccm, 470 mTorr, 5 min), yielding ~10 nm amorphous HfO\n2 2\nlayers. The resulting HfO samples were then annealed under Ar atmosphere (30 sccm, 6\n2\nmTorr) at 800 °C for 3h—the maximum temperature allowable in our system. The post-\nannealed HfO samples exhibited a clear polycrystalline phase, with distinct lattice fringes\n2\nand grain boundaries visible in the cross-sectional STEM images, confirming the\ncrystallisation of the initially amorphous HfO (revised Supplementary Fig. 19a). However,\n2\nas shown in the revised Supplementary Fig. 19b and consistently reproduced across 10\nindependently measured devices (revised Supplementary Fig. 19c), the polycrystalline\nHfO exhibits increased leakage current compared to the amorphous counterparts at the\n2\nsame physical thickness (10 nm). Such behaviour is generally attributed to grain-\nboundary–mediated leakage pathways, accompanied by enhanced trap-assisted tunnelling\nand Poole–Frenkel conduction, as the grain boundaries provide defect-rich regions that\nfacilitate carrier transport under bias [R1,2]. For this reason, the semiconductor industry\ncontinues to favour amorphous high-κ dielectrics for gate-stack integration, prioritising\nleakage suppression and long-term reliability.\nAdditionally, even if a single-crystalline dielectric could, in principle, be stabilised through\nhigher-temperature or more stringent processing, such conditions are impractical for 2D\nchannels and incompatible with BEOL thermal budgets (< 400 °C). In accodance with this\nconstraint, several recent reports investigating crystalline dielectrics have adopted ex situ\nformation followed by transfer onto the channel, rather than direct crystallisation on the\nactive device region [R3–6].\nTaken together, these results support our choice of plasma-converted amorphous HfO ,\n2\nwhich can be realised under a low thermal budget while preserving the vdW interface\nintegrity essential for high-quality 2D gate dielectrics.\nDetailed characterisation procedures and measurement results have been added in the\nrevised Supplementary Information and the relevant descriptions are briefly mentioned in\nthe revised manuscript as follows:\n“………..indicating excellent dielectric characteristics. The suppressed leakage current,\ncompared with the crystalline phase, further underscores the intrinsic advantage of\nmaintaining the amorphous phase to ensure low-power device integrity (Supplementary\nFig. 19). Notably, the fabricated MoS nFET and WSe pFET exhibited near-ideal SS\n2 2\nvalues………………...”\n(revised Manuscript, page 8)\nSupplementary Figure 19. Structural and electrical analysis of polycrystalline HfO .\n2\na, Cross-sectional STEM images of polycrystalline HfO samples obtained after rapid\n2\nthermal annealing at 800 °C for 3 h. b, Comparison of leakage current characteristics of\npolycrystalline and amorphous HfO at the same physical thickness of 10 nm as a function\n2\nof applied voltage (inset: schematic of the MIM structure used for the evaluation, active\narea: 9 μm2). c, Leakage current characteristics obtained from ten polycrystalline HfO\n2\nsamples (~10 nm).\n“To assess the possibility of crystallising HfO via post-processing, we further performed\n2\nrapid thermal annealing process. Approximately 25 nm HfSe samples were prepared and\n2\nsubsequently oxidised under the specified plasma conditions (O gas, 10 W, 5 sccm, 470\n2\nmTorr, 5 min), yielding ~10 nm amorphous HfO layers. The resulting HfO samples were\n2 2\nthen annealed under Ar atmosphere (30 sccm, 6 mTorr) at 800 °C for 3 h—maximum\ntemperature allowable in our system. The post-annealed HfO samples exhibited clear\n2\npolycrystalline phase, with distinct lattice fringes and grain boundaries visible in cross-\nsectional STEM images, confirming the crystallisation of the initially amorphous HfO\n2\n(Supplementary Fig. 19a). However, as shown in Fig. 19b and consistently reproduced\nacross ten independently measured devices (Supplementary Fig. 19c), the polycrystalline\nHfO exhibits increased leakage current compared to the amorphous counterparts at the\n2\nsame physical thickness (10 nm). Such behaviour is generally attributed to grain-\nboundary–mediated leakage pathways, accompanied by enhanced trap-assisted tunnelling\nand Poole–Frenkel conduction, as the grain boundaries provide defect-rich regions that\nfacilitate carrier transport under bias41,42.”\n(revised Supplementary Information, page 27)\nSupplementary references\n[41] McKenna, K. et al. Grain boundary mediated leakage current in polycrystalline HfO\n2\nfilms. Microelectron. Eng. 88, 1272–1275 (2011).\n[42] Bersuker, G. et al. Grain boundary–driven leakage path formation in HfO dielectrics.\n (Memory performance) Achieving the specific crystalline phase required for\nferroelectric memory functionality remains particularly challenging. In HfO ,\n2\nferroelectricity arises only when the metastable orthorhombic (Pca2₁) phase is stabilised,\nas this phase alone exhibits switchable polarization suitable for non-volatile operation. The\nformation of this metastable phase inherently requires a substantial thermal budget, and to\nfurther stabilise it, even higher annealing temperatures over 700 °C are typically needed\n[R7-10]. However, such conditions are fundamentally incompatible with 2D channels,\nwhich are highly sensitive to elevated temperatures. Specifically, MoS undergoes sulfur\n2\nloss and pronounced oxidation beginning at ~350–400 °C in air or oxidising environments\n[R11,12], while WSe has been reported to oxidise from its edges at temperatures as low\n2\nas ~300 °C [R13]. Therefore, applying the thermal budget required for ferroelectric\ncrystallisation of HfO would inevitably induce severe channel degradation, lattice\n2\ndisorder, and phase instability. More fundamentally, such high-temperature processing is\nincompatible with industry-adopted BEOL processes, where the thermal budget is strictly\nlimited to below ~400 °C. Although it may be theoretically possible to crystallise oxidised\nHfO via an ex situ crystallisation-and-transfer route at extremely high temperatures to\n2\nrealise ferroelectric oxides with memory functionality, we regard this strategy as highly\nimpractical in terms of scalability and process compatibility.\nReferences\n[R1] McKenna, K. et al. Grain boundary mediated leakage current in polycrystalline HfO\n2\nfilms. Microelectron. Eng. 88, 1272–1275 (2011).\n[R2] Bersuker, G. et al. Grain boundary–driven leakage path formation in HfO dielectrics.\n[R3] Xu, W. et al. Single-crystalline high-κ GdOCl dielectric for two-dimensional field-effect\ntransistors. Nat. Commun. 15, 9469 (2024).\n[R4] Cheng, R. et al. Magnesium niobate as a high-κ gate dielectric for two-dimensional\nelectronics. Nat. Electron. 7, 455–463 (2024).\n[R5] Yin, L. et al. High-κ monocrystalline dielectrics for low-power two-dimensional\nelectronics. Nat. Mater. (2024).\n[R6] Yin, L. et al. Integration of freestanding hafnium zirconium oxide membranes into two-\ndimensional transistors as a high-κ ferroelectric dielectric. Nat. Electron. (2025).\n[R7] Müller, J. et al. Ferroelectricity in simple binary ZrO and HfO . Nano Lett. 12, 4318–\n2 2\n4323 (2012).\n[R8] Böscke, T. S., Müller, J., Bräuhaus, D., Schröder, U. & Böttger, U. Ferroelectricity in\nhafnium oxide thin films. Appl. Phys. Lett. 99, 102903 (2011).\n[R9] Starschich, S. & Böttger, U. Evidence for wake-up in ferroelectric Y-doped HfO₂ thin\nfilms. Appl. Phys. Lett. 108, 032903 (2016).\n[R10] Hoffmann, M. et al. Stabilizing the ferroelectric phase in doped hafnium oxide. J. Appl.\nPhys. 118, 072006 (2015).\n[R11] Kang, K. et al. Oxidation dynamics of MoS monolayers. Nano Lett. 15, 161–168 (2015).\n2\n[R12] Cho, S. et al. Atomic-level investigation of sulfur loss in MoS under thermal annealing.\n[R13] Zhang, W. et al. Oxidation resistance of WSe nanosheets. Nat. Commun. 11, 5631\n2\n(2020).\n7. Supplementary Table 1: There appears to be a spelling error in the abbreviation for\n'Demonstrations', it is typically abbreviated as \"demos\" rather than \"demons\".\n It has been corrected in the revised Supplementary Information as follows:\nStructure Channel\nDielectric Dit VDD\nGain\nStatic power Demos.\nRef.\n(method) (cm-2 eV-1) (V) (W) RO\n(revised Supplementary Information, Supplementary Table 1, page 4)\nResponse to Reviewer #2\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in red.\nComments:\nThe authors demonstrate a universal method for integrating high-κ dielectrics by converting\ndry-transferred HfSe into HfO via oxygen plasma oxidation. This process yields high-quality\n2 2\nvdW interfaces on both n-type (MoS ) and p-type (WSe ) 2D semiconductors. The resulting\n2 2\nHfO /TMD gate stacks exhibit excellent electrical properties, enabling the fabrication of high-\n2\nperformance vdW FETs. With this method, the authors successfully fabricated and vertically\ninterconnected complementary field-effect transistors (CFETs) comprising MoS nFETs and\n2\nresearch holds scientific merit, the following concerns should be addressed:\n1. The abstract should more explicitly articulate the scientific problem addressed and the core\ninnovation. The claim of \"first experimental integration\" of CFET-based ring oscillators, while\nnotable, may inadvertently overshadow the study's more fundamental innovation. Emphasizing\nuniversal high-κ integration methodological advance would provide clearer focus on the\nprimary scientific contribution.\n Following the reviewer’s suggestion, the abstract has been rewritten in the revised\nManuscript to emphasise the core innovation of this work, as follows:\n“The integration of high-κ dielectrics with two-dimensional (2D) semiconductors has long\nremained a challenge due to the intrinsically low nucleation reactivity of their dangling\nbond-free surfaces, interfacial disorder, and limited scalability of conventional deposition\ntechniques. Here, we report van der Waals (vdW) interface-integrated high-κ/2D\nsemiconductor (n-, p-type) gate stacks. HfSe , a high-κ precursor, is dry-transferred onto\n2 2\nwhile undergoing being completely converted into amorphous HfO via plasma oxidation,\n2\nthereby integrating HfO /MoS and HfO /WSe gate stacks. This universal approach\n2 2 2 2\nenables seamless integration of HfO on MoS and WSe with suppressed interface charge\n2 2 2\ntrap density (D = 7.1 × 1010 and 8.4 × 1010 cm-2 eV-1, respectively) and high dielectric\nit\nconstant (κ = ~23). Using this scalable approach, we fabricate MoS n-type and WSe p-\n2 2\ntype field-effect transistors (MoS nFET and WSe pFET, respectively), which\n2 2\ndemonstrate nearly ideal subthreshold slopes of 61 and 63 mV/dec (over four orders of I )\nDS\nat room temperature (300 K), along with negligible hysteresis (~3 mV), a high on–offratio\n(~108), and a low gate leakage current density (~10-6 A/cm2). First-principles molecular\ndynamics simulations elucidate the layer-by-layer oxidation mechanism of HfSe and\n2\nreveal that, due to the higher energy cost for their surface oxidation, MoS and WSe can\n2 2\nfacilitates clean vdW interface formation with HfO than HfSe . Building on this\n2 2\nmethodology, vertically interconnected MoS nFETs and WSe pFETs were further\n2 2\nintegrated into complementary field-effect transistor (CFET) inverter, demonstrating an\nexcellent inverter gain (~115) and noise margin (NM , NM ~98% of 1/2V ). Ring\nL H DD\noscillators incorporating the proposed CFETs are also realised, demonstrating the broader\napplicability of our integration strategy to three-dimensional complementary logic circuits.”\n(revised Manuscript, Abstract)\n2. The reported constant oxidation rate (~2.1 nm/min) across thicknesses appears inconsistent\nwith conventional understanding, where surface oxide layers typically impede further\noxidation (e.g., as observed in aluminum oxidation to Al O , Nature 632, 788–794 (2024)).\n2 3\nPlease provide a mechanistic explanation for this observed behavior. Furthermore, clarify if\nthis linear rate is expected to hold for significantly thicker layers (e.g., approaching the cm\nscale) or if limitations exist.\n Please first note that a unique characteristic of our oxygen plasma-based HfSe 2 oxidation\napproach is its capability for layer-by-layer oxidation. This makes the oxidation feature in\nour case very different from that of, for example, Al O . We presented the mechanism in\n2 3\nour earlier studies I [Nanoscale 10, 18758–18766 (2018)] and II [Adv. Mater. 36, 2312747\n(2024)] as well as in the present submission III.\nTo further address the reviewer’s concern regarding the oxidation rate of thick HfSe layer,\n2\nwe prepared new samples with a uniformly attainable maximum thickness of ~120 nm\n(Fig. R6) using the method described in Supplementary Fig. 2 and conducted oxidation\nexperiments. After the initiation of oxidation in the ~120 nm HfSe sample, its thickness\n2\nwas monitored at 5 min intervals, and after ~25 min the sample was fully converted into\nan ~52 nm HfO layer (Fig. R6a). An oxidation rate of ~2.08 nm/min, consistent with that\n2\nobserved across various thicknesses in Supplementary Fig. 2g, was obtained (Fig. R6b).\nEven at the significantly thicker layers, oxidation proceeded linearly, demonstrating the\nrobustness of the linear oxidation behaviour. Since we believe that further increasing the\nthickness beyond this point would not yield meaningful insights for practical device\napplications, we did not investigate thicker samples, as ~52 nm of HfO , equivalent to an\nFigure R6. Extraction of the oxidation rate from thicker HfSe precursors. a, Total\n2\nthickness of the HfSe and the converted HfO thickness as a function of the plasma\n2 2\noxidation time. b, Extracted oxidation rate of HfO from HfSe under the given plasma\n2 2\nconditions (power of 10 W, flow rate of 5 sccm, and pressure of 470 mTorr).\n3. Could heat accumulation during prolonged plasma exposure lead to temperature increases\nthat significantly alter the oxidation rate? Please discuss potential thermal effects inherent to\nthe plasma process and their possible influence on reaction kinetics and uniformity.\n First, please note that the oxygen plasma method which we used to achieve the HfSe 2 -\nHfO conversion typically involves the gas temperature range of approximately 30–300 °C,\n2\nwhich is significantly lower than the 800–1000 °C range of conventional thermal oxidation.\nThe oxidation rate and quality of the oxide are primarily determined by the plasma power,\nwhich, under the low-power plasma condition we have employed is proportional to the\nflux density of neutral radicals such as O(³P), O(¹D), O₂(a¹Δg) that dominate the oxidation\nprocess.\nTo address the reviewer’s concern regarding possible heat accumulation during prolonged\nplasma exposure, we monitored the chamber temperature using thermal tape (THERMAX)\nplaced inside the plasma reactor. Under the conditions applied in this work (O gas, 10 W,\n2\n5 sccm, 470 mTorr), the chamber temperature was measured after 1, 2, 3, 4, and 5 min of\nplasma operation, covering the entire time window required for the complete oxidation of\n~25 nm HfSe precursors (Supplementary Fig. 2e,f). Throughout this period, the\n2\ntemperature remained constant at ~50 °C (Fig. R7). Please note that the substrate\ntemperature, which is self-heated by the plasma, is known to be higher than the chamber\nwall temperature by approximately 50–200 K. Therefore, we expect that the substrate\ntemperature will be higher than ~50 °C and adopted 500 K as the representative\ntemperature in our ab initio MD simulations.\nThis low-thermal-budget environment confirms that heat accumulation does not play any\nsignificant role in modifying the oxidation kinetics under the applied conditions.\nImportantly, the temperature stability persisted even after 30 min of plasma exposure,\nwhich corresponds to the maximum duration required for the oxidation of thicker HfSe\n2\nlayers, shown in Supplementary Fig. 2g. These observations indicate that our plasma-\nconversion methodology intrinsically operates within a low-thermal-budget environment\n(<400 °C) across all process durations. Moreover, the negligible thermal impact ensures\nthat the underlying 2D semiconductor channel experiences no significant thermal burden,\nthereby preserving the integrity of the vdW interface.\nFigure R7. Investigation of plasma reactor temperature at various plasma durations.\na–e, Monitored plasma chamber temperature after plasma exposure for 1, 2, 3, 4, and 5\nmin. f, Plasma chamber temperature after plasma exposure for 30 min. Even under this\nrelatively long duration, which encompasses the entire process window for HfSe\n2\noxidation with various thicknesses, the low-thermal-budget condition was preserved.\n4. Regarding the layer-by-layer oxidation mechanism: (1) Is it feasible to optimize conditions\nto achieve layered crystalline HfO instead of amorphous HfO ? (2) What is the minimum\n2 2\nachievable HfO thickness using this method? Please elaborate on these aspects.\n2\n (Layered crystalline HfO 2 layer) In line with our initial work, plasma oxidation of HfSe₂\nnaturally yields amorphous HfO , since the diffusivity of Hf/O species and the adatom\n2\nmobility under low-temperature plasma conditions are insufficient to drive long-range\nordering. Consequently, the system minimises its free energy by forming a continuous\nrandom network, consistent with the thermodynamic preference for amorphous phases at\nreduced thermal budgets.\nFrom a crystallographic perspective, HfO does not possess a van der Waals–type layered\n2\nequilibrium phase. Instead, it stabilises in the monoclinic (m) structure at room\ntemperature, transforms into the tetragonal (t) phase at elevated temperatures, and only\nbecomes cubic (c) at even higher temperatures. The orthorhombic (o, Pca2₁) phase, which\nhas attracted attention for its ferroelectricity, is metastable and generally requires extrinsic\nstabilisation such as dopants, stress, or electric-field cycling. None of these polymorphs\nprovide van der Waals gaps or lamellar stacking compatible with 2D semiconductors.\nStructurally, Hf–O forms a 3D network of distorted HfO /HfO polyhedra rather than\n6 7\nquasi-2D sheets.\nFurthermore, the topotactic transformation from layered HfSe (CdI -type, octahedral Se\n2 2\ncoordination) to HfO is intrinsically reconstructive: Se removal and O incorporation alter\n2\nboth the chemical composition and Hf coordination (increasing to 7–8), accompanied by\nsubstantial local rearrangements. This process inevitably disrupts the original van der\nWaals stacking, such that any crystallinity that develops does so in the form of randomly\noriented polycrystalline grains rather than a layered oxide. Achieving a truly layered\ncrystalline order would, in principle, require epitaxial growth under lattice-matched\nconditions at elevated temperatures to provide sufficient diffusion lengths for atomic\nordering. In practice, this would necessitate high-temperature epitaxy (≥ 500–700 °C) on\ncrystalline oxide substrates—conditions incompatible with both the thermal stability of\n2D channels and BEOL process budgets (<400 °C).\nNevertheless, to experimentally examine this possibility, we annealed plasma-converted\n~10 nm HfO films. As shown in Fig. R8a, the annealed samples transformed into\n2\npolycrystalline HfO , confirmed by lattice fringes and grain boundaries in the STEM\n2\nimages. However, this crystallisation degraded electrical performance: the polycrystalline\nfilms exhibited higher leakage currents compared with their amorphous counterparts of\nthe same thickness, a trend consistently reproduced across ten devices (Fig. R8b, c). This\nbehaviour is well explained by grain-boundary–mediated leakage, enhanced trap-assisted\ntunnelling, and Poole–Frenkel conduction in defect-rich boundary regions [R1,2]. While\none may speculate that further optimisation or epitaxial protocols could stabilise single-\ncrystalline HfO , such approaches inherently require high processing temperatures and\n2\nstrict lattice-matching conditions. These requirements are fundamentally incompatible\nwith both 2D channel stability and BEOL thermal budgets. Indeed, recent reports\nexploring crystalline dielectrics have instead adopted ex situ crystal growth followed by\ntransfer onto the channel, rather than direct crystallisation on the active device region (Fig.\nR9) [R3–6].\nBased on the overall results, our work has therefore focused on plasma-conversion–\nderived amorphous dielectrics that can be realised under a low thermal budget, while\nsimultaneously establishing an integrated strategy to preserve the van der Waals interface\nintegrity essential for 2D semiconductor gate dielectrics.\nFigure R8. Structural and electrical analysis of poly-crystalline HfO . a, Cross-\n2\nsectional STEM images of poly-crystalline HfO obtained after rapid thermal annealing at\n2\n900 °C for 3 h. b, Comparison of leakage current characteristics of poly-crystalline and\namorphous HfO as a function of applied voltage (Inset: MIM structure, active area: 9\n2\nμm2). c, Leakage current characteristics obtained from 10 poly-crystalline HfO samples\n2\n(~10 nm).\nFigure R9. Recent reports in the Nature Portfolio on ex situ grown single-crystalline\ndielectrics transferred onto 2D semiconductors for top-gate integration. a, CVD-\ngrown GdOCl/MoS structure [R3]. b, Buffer-controlled epitaxial grown MgNb O /MoS\n2 2 6 2\nstructure[R4]. c, CVD-grown Gd O /MoS structure[R5]. d, PLD-grown HZO/MoS\n2 5 2 2\nstructure[R6].\n (Minimum achievable HfO 2 thickness) To probe the minimum achievable HfO 2\nthickness attainable by this method, we investigated the case of monolayer HfSe (~0.65\n2\nnm), the thinnest 2D precursor for this methodology. Cross-sectional STEM analysis\nconfirmed the formation of an ultrathin HfO layer with a thickness of ~0.3 nm, which is\n2\nagreement with the calculated volume ratio (Fig. R10a, b). Importantly, the crystallinity of\nthe underlying channels was preserved under this extreme scaling condition, suggesting\nthe retention of intact channel properties and the formation of an atomically flat vdW\ninterface. Under such extreme scaling, clear pinholes were observed, where excessive\nthinning induces morphological discontinuities and potential leakage paths. This\nobservation aligns with our theoretical model of the oxidation pathway, which predicts\ntransient formation and recovery of local voids (Supplementary Fig. 14). In the ultrathin\nregime, this recovery remains incomplete, leading to morphological discontinuities.\nNotably, once the converted HfO thickness exceeded ~2 nm, such pinhole features were\n2\nno longer observed, and the films became morphologically uniform and continuous with\nthe atomically flat vdW interface integrity (Fig. R10c, d).\nThe above discussions and observations suggest that the practically attainable minimum\nthickness ensuring uniformity and continuity is ~2 nm. Below this threshold, incomplete\nvoid recovery inevitably compromises gate-dielectric integrity, precluding reliable device\nimplementation.\nFigure R10. Structural analysis of HfO /TMD heterostructures integrated with\n2\nultrathin HfO . a,b, Cross-sectional STEM images of HfO /MoS and HfO /WSe\n2 2 2 2 2\nheterostructures formed by transferring and oxidising monolayer HfSe Despite the\n2.\nexcessive thinning of the HfO layer (~0.3 nm), the underlying channel crystallinity\n2\nremains intact after the oxidation process with atomically flat vdW interface. c,d,\nCross-\nsectional STEM images of HfO /MoS and HfO /WSe heterostructures showing the\n2 2 2 2\nformation of a uniform HfO layer once the converted thickness exceeds ~2 nm. In this\n2\ncase as well, the integrity of the atomically flat vdW interface is maintained.\nSupplementary Figure 14. Alternating NVE-NVT protocol AIMD simulations for the\nplasma HfSe oxidation. We repeated the alternating NVE-NVT AIMD simulations (filled\n2\nlight green boxes). Each NVE oxidation MD step begins with oxygen insertion and ends with\nspontaneous oxidation and structural rearrangement; its final configuration, after removing\nfloating Se atoms (highlighted by black circles), serves as the initial state for the subsequent\nNVT quenching MD step. Upon completing each NVE MD run, detached Se atoms were\nremoved, and the system is equilibrated to 500 K using NVT MD simulations for 1 ps. This\nNVE-NVT sequence continues until the partially oxidised model (Hf Se O referred to as\n24 28 36\nO ) is obtained. As oxidation progresses, three-dimensional Hf-O coordination develops,\n36\nforming a porous structure with voids appearing in the 2D lattice, indicated by black circle in\nthe final snapshot. AIMDs for the generation of O\n6\nmodel (Hf\n6\n) and O\n36\n(Hf\n36\n)\nare provided in Supplementary Video 1,2.\nReferences\n[R1] McKenna, K. et al. Grain boundary mediated leakage current in polycrystalline HfO\n2\nfilms. Microelectron. Eng. 88, 1272–1275 (2011).\n[R2] Bersuker, G. et al. Grain boundary–driven leakage path formation in HfO dielectrics.\n[R3] Xu, W. et al. Single-crystalline high-κ GdOCl dielectric for two-dimensional field-effect\ntransistors. Nat. Commun. 15, 9469 (2024).\n[R4] Cheng, R. et al. Magnesium niobate as a high-κ gate dielectric for two-dimensional\nelectronics. Nat. Electron. 7, 455–463 (2024).\n[R5] Yin, L. et al. High-κ monocrystalline dielectrics for low-power two-dimensional\nelectronics. Nat. Mater. (2024).\n[R6] Yin, L. et al. Integration of freestanding hafnium zirconium oxide membranes into two-\ndimensional transistors as a high-κ ferroelectric dielectric. Nat. Electron. (2025).\n5. The uniformity of the 40 n-type and p-type devices shown in Fig. 3c appears relatively poor.\nWhat are the primary factors contributing to this performance variation? Is the non-uniformity\nprimarily attributed to variations in the HfO layer itself, or are other process steps?\n2\n To quantitatively evaluate device-to-device variations, cumulative probability\ndistributions of the threshold voltage (V ), subthreshold swing (SS), and on-off ratio\nth\n(I ), extracted from the transfer curves of 40 MoS nFETs and WSe pFETs shown in\non/off 2 2\nFig. 3c, are presented in Fig. R11. Device variation was quantified using the coefficient of\nvariation (CV), which measures the dispersion of a probability distributions and is defined\nas CV = (𝜎/𝜇) × 100 (%), where 𝜎 and 𝜇 represent the standard deviation and mean\nvalue, respectively. Both V and SS exhibit narrow variations, with CV values of <3% and\nth\n<2%, respectively (Fig. R11a, b), representing improved uniformity compared with\nrecently reported Ga O /MoS (SS: CV ≈ 5%), Y O /MoS (SS: CV ≈ 20–25%),\n2 3 2 2 3 2\nMgNb O /MoS (V : CV ≈ 18%), and HZO/MoS gate stacks (V : CV ≈ 50%) (Fig. R12a–\n2 6 2 th 2 th\nd) [R1–4].\nIn contrast, the I exhibits relatively larger variability (Fig. R11c), which can be directly\non/off\ncorrelated with the broad distribution of on-currents, as observed in Fig. 3c. This\nvariability is primarily attributed to the current state of contact engineering, which has not\nyet been fully optimised, rather than to the HfO dielectric itself. This interpretation is\n2\nconsistent with previously reported results (Fig. R12e) [R5], further supporting our\nconclusion that contact resistance is the dominant factor underlying the observed variation.\nTo further substantiate this point, we fabricated additional MoS nFETs and WSe pFETs\n2 2\nand measured their gate leakage currents (Fig. R11d). All devices exhibited negligible\nvariation in leakage, confirming that the HfO layer does not contribute significantly to\n2\nthe observed variability. Therefore, we conclude that the device-to-device non-uniformity\nprimarily originates from on-current variation due to irregular contact resistance, which\ncan be improved in future through optimised contact engineering.\nImportantly, the SS values of all devices exhibit negligible CV values, underscoring the\nhigh reproducibility of the atomically flat vdW interface, further supported by the\nstructural uniformity shown in Supplementary Fig. 10.\nFigure R11. Statistical analysis of MoS nFET and WSe pFET. a-c, Device-to-device\n2 2\nvariability of 40 MoS nFETs and WSe pFETs presented as cumulative probability\n2 2\ndistributions of threshold swing, subthreshold swing, and on-off ratio, extracted from Fig.\n3c. d, Gate leakage current characteristic obtained from newly fabricated 3 MoS nFETs\n2\nand 3 WSe pFETs.\na–d, Device-to-device variability in recently reported 2D semiconductor-based gate stacks,\nincluding Ga O /MoS , Y O /MoS , MgNb O /MoS , and HZO/MoS structures[R1-4]. e,\n2 3 2 2 3 2 2 6 2 2\nComparison of on-current variation between vdW contacts and evaporated contacts in\nAl O /HfO /MoS gate stacks[R5].\n2 3 2 2\nSupplementary Figure 10. Reproducibility of the atomically flat vdW interface. a,b,\nHigh-\nresolution STEM images of three different HfO /MoS and HfO /WSe heterostructures\n2 2 2 2\nfabricated under same processing conditions. Atomically flat vdW interfaces were consistently\nobserved in three different samples, demonstrating the high reproducibility of the proposed\nvdW integration.\nReferences\n[R1] Choudhuri, I. et al. Integration of high-κ native oxides of gallium for two-dimensional\ntransistors. Nat. Commun. 14, 1196 (2023).\n[R2] Cao, Y. et al. A general one-step plug-and-probe approach to top-gated transistors for\nrapidly probing delicate electronic materials. Nat. Commun. 13, 6805 (2022).\n[R3] Zhang, H. et al. Magnesium niobate as a high-κ gate dielectric for two-dimensional\nelectronics. Nat. Commun. 14, 2592 (2023).\n[R4] Polanco, C. A. et al. Integration of freestanding hafnium zirconium oxide membranes into\ntwo-dimensional transistors as a high-κ ferroelectric dielectric. Nat. Commun. 15, 1185 (2024).\n[R5] Shen, J. et al. Highly reproducible van der Waals integration of two-dimensional\nelectronics on the wafer scale. Nat. Commun. 15, 4467 (2024).\n6. Formatting and presentation issues:\n(1) When referring to multiple figures, use \"Figs.\" (e.g., \"Figs. 1a and 2b\" instead of \"Fig. 1a\nand Fig. 2b\").\n(2) Some scientific notations use the letter \"x\" instead of the proper multiplication symbol\n\"×\"(e.g. page 3, line 10). It is need to review this article carefully and correct them.\n(3) At page 6, line 15, \"an 1 ps NVT-ensemble\" should be corrected to \"a 1 ps NVT-ensemble\".\n The corresponding corrections have been made in the revised Manuscript accordingly.\n(4) The arrows (e.g. length, width, head shape, and color) in Fig.2 require standardization.\n Figure 2 has been revised as follows.\nFigure 2. Ab-initio molecular dynamics (AIMD) simulations of HfSe and HfSe /TMD\n2 2\n(HfSe , MoS , and WSe ) interface oxidations. a, A sequence of NVE-NVT dynamics\n2 2 2\n(highlighted by the light green box) is performed to simulate the oxidation of monolayer HfSe .\n(blue box) after the removal of floating Se atoms. The striped arrow represents repeated\napplication of the NVE-NVT cycle. b, A partially oxidised HfSe (O model)/pristine HfSe\n2 36 2\nstructure undergoes further oxidation under the same NVE-NVT scheme, resulting in layer-by-\nlayer oxidation and retention of a vdW gap. c, A comparative analysis of O model/TMD\n36\ninterfaces within a single NVE dynamics step, where oxygen atoms are directed toward the\nbottom TMD layer. In HfSe (top), oxidation proceeds at the bottom layer, while in MoS\n2 2\n(middle) and WSe (bottom), oxygen atoms primarily passivate the bottom surface of the upper\n2\noxide layer. (revised Manuscript, page 23)\n(5) The color schemes employed in (b), (c), (e), and (f) of Figure 4 exhibit poor visual harmony\nwith adjacent charts, significantly reducing readability.\n Figure 4 has been revised as follows.\nFigure 4. Vertically stacked CFET fabricated with vdW interface-integrated MoS nFET\n2\nand WSe pFET. a, Structural schematic of the CFET. GND, V , V and V represent\nground, input voltage, supply voltage and output voltage for the CFET, respectively. b,c,\nVoltage transfer characteristics and corresponding voltage gain as a function of V .\nDD\nd, The\nvoltage gain comparison of the CFETs fabricated with 2D semiconductor/Si hybrid channel,\n2D semiconductor channel, and Si channel, including proposed vdW interface-integrated\nCFET55,56,65,66,67,68,69,70,71,72. e, Voltage transfer characteristic and its mirror reflection at V =\nDD\n2.0 V. The V , V , V , and V represent the minimum high output voltage, maximum low\nOH OL IL IH\noutput voltage, maximum low input voltage, and minimum high input voltage, respectively.\nThe noise margin is determined by nesting the largest square (grey shading). The dashed lines\n(black) are auxiliary lines for extracting the value of V , V , V , and V .\nf, Static power\nOH OL IL IH\nconsumption of the proposed CFET as a function of V .\nDD\ng, Comparison of static power\nconsumption at various V with literature reports67,68,69,70,71,72,73,74,75,76.\nDD\n(revised Manuscript, page 27)\nResponse to Reviewer #3\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in red.\nComments:\nThis manuscript presents a significant advancement in 2D semiconductor technology by\ndemonstrating universal high-κ dielectric integration using vdW interfaces. The authors\ndevelop a scalable approach where HfSe precursors are transferred onto both MoS and\n2\np-type WSe channels, followed by controlled plasma oxidation to convert HfSe into HfO\n2 2 2\nwhile preserving atomically clean vdW interfaces. The work achieves suppressed interface trap\ndensities and demonstrates near-ideal subthreshold slopes. A complementary field-effect\ntransistor (CFET) and ring oscillators (ROs) are also been successfully achieved. Prior to the\npossible publication, the following concerns should be addressed:\n1. The plasma oxidation process appears critical for success. What is the process window for\nthe oxidation parameters (power, pressure, time)? How sensitive is the interface quality to\nvariations in these parameters, and what quality control metrics would be necessary for\nmanufacturing.\nTo address the reviewer’s questions, we performed additional experiments to clarify the\nimpacts of the plasma oxidation process parameters (power, time, and pressure), as follows.\n (Power) Approximately 25 nm-thick HfSe 2 flakes were transferred onto the TMD\nchannels and subsequently oxidised under the lowest power accessible in our system (O\n2\ngas, 5 W, 5 sccm, 470 mTorr, 15 min), resulting in the formation of ~10 nm HfO . The\n2\nfabricated HfO /TMD heterostructures retained the atomically flat vdW interface;\n2\nhowever, unconverted HfSe layers were clearly observed within the HfO film (Fig. R13a).\n2 2\nThese results are also consistent with our previous investigation of oxidation\ncharacteristics under reduced plasma power, which was conducted to explore the\npossibility of further optimised oxidation conditions (Fig. R14a). Cross-sectional STEM\nimaging of the 10 nm HfO layer converted under a plasma power of 5 W reveals locally\n2\nunconverted HfSe domains embedded within the HfO layer, indicating incomplete\n2 2\noxidation under reduced plasma power. To quantitatively examine the residual Se atoms,\nXPS depth profiling was further conducted (Fig. R14b). For this analysis, the HfO\n2\nsamples were sequentially thinned by ~2.5 nm at a sputtering rate of 0.5 nm/min, and the\nXPS spectra were collected after each thinning step. In contrast to the 10 W condition\n(Supplementary Fig. 4), where all HfSe was fully oxidised and no Se signal was detected,\n2\ndistinct Se 3d peaks were observed under the lower-power condition. This finding is\nconsistent with the locally unconverted HfSe region in the cross-sectional STEM images.\n10–13 W, complete conversion into HfO was achieved while maintaining an atomically\n2\nflat vdW interface, as evidenced in Fig. R13b and Supplementary Fig. 4. Beyond this range\n(14–30 W), a clear collapse of the vdW interface accompanied by severe interfacial\ndisorder was observed (Fig. R13c and Supplementary Fig. 6), indicating that this method\nis no longer applicable under such conditions. Considering both vdW interface integrity\nand dielectric conversion, the process window for plasma power is summarised in Fig.\nR13d, which clearly identifies 10–13 W as the optimal range to achieve complete oxidation\nwhile preserving a clean vdW interface.\nFigure R13. Process parameter (plasma power) window for vdW interface-integrated\nHfO /TMD heterostructures. a-c, Cross-sectional STEM images of HfO /TMD\n2 2\nheterostructures fabricated under different plasma power conditions. d, Process window\nsummarised in terms of plasma power, highlighting the overlap region (red arrow) where\nboth a clean vdW interface and robust dielectric integrity are simultaneously preserved.\nFigure R14. Characterisation of HfO converted under lower plasma power condition.\n2\na, Cross-sectional STEM image of HfO formed from HfSe under reduced plasma power\n2 2\n(5 W, 5 sccm, 470 mTorr). b, XPS depth profiling of the converted HfO layer. The O 1s\n2\nand Se 3d peak ratios were monitored from the top surface of the ~10 nm HfO down to\n2\nthe bottom through sequential thinning steps at a sputtering rate of 0.5 nm/min. The\ndetection of the Se 3d signal at a depth of ~5 nm indicates the presence of locally\nunconverted HfSe . These results indicates that such low-power plasma conditions are\n2\ninsufficient to ensure complete oxidation of HfSe into HfO .\n2 2\n (Time) To assess the sensitivity of the vdW interface to plasma treatment time, additional\nanalyses were performed. As shown in Supplementary Figs. 2 and 3, an HfSe film with a\n2\nthickness of ~25 nm required ~5 min of plasma treatment to be fully converted into ~10\nnm of HfO . To further probe interfacial stability beyond this point, the plasma duration\n2\nwas extended to 20, 40, and 60 min. Cross-sectional STEM analyses revealed that the\nHfO /TMD vdW interface remained clean and abrupt after 60 min of plasma exposure,\n2\nwith no evidence of interfacial collapse or chemical reaction (Fig. R15). In parallel, plasma\nreactor temperature monitoring confirmed that the chamber temperature remained\nconstant at ~50 °C for all treatment durations (Fig. R16), thereby excluding any possible\ninfluence of heat accumulation. As this temperature is well below the threshold for thermal\ndegradation of TMDs, the preserved interface quality can be attributed to the plasma\noxidation mechanism itself. More importantly, in our methodology, the final HfO\n2\nthickness is directly determined by the initial HfSe precursor thickness. For instance, to\n2\nachieve an industry-target EOT of ~0.5 nm (at κ ≈ 23), an initial HfSe thickness of ~7 nm\n2\nis fully converted within <2 min, yielding an HfO layer of ~3 nm. Consequently,\n2\nprolonged oxidation times, such as 60 min, are unnecessary and were not considered\nfurther for device-relevant processing.\nFigure R15. Plasma duration time-independent vdW interface integrity. a-c, Cross-\nsectional STEM images of HfO /TMD heterostructures fabricated under different plasma\n2\ntime conditions of 20, 40, and 60 min, respectively.\nFigure R16. Investigation of plasma reactor temperature at various plasma durations.\na–e, Monitored plasma chamber temperature after plasma exposure for 1, 2, 3, 4, and 5\nmin. f, Plasma chamber temperature after plasma exposure for 30 min. Even under this\nrelatively long duration, which encompasses the entire process window for HfSe\n2\noxidation with various thicknesses, the low-thermal-budget condition was clearly\npreserved.\n (Pressure) In our experimental setup, the process pressure was fixed at 470 mTorr, and\ntherefore could not be varied. However, as industrial process systems typically operate at\ncomparatively higher pressures, generally in the range of several hundred mTorr to a few\nTorr, the mechanisms expected under such conditions can be anticipated as follows. First,\nthe mean free path (λ) of gas species decreases with pressure, according to the kinetic gas\nrelation: 𝜆 = 𝑘 𝑇/√2𝜋𝑑2𝑃, where 𝑘 is the Boltzmann constant, 𝑇 is the temperature,\n𝐵 𝐵\n𝑑 is the effective molecular diameter, and 𝑃 is the pressure. At elevated pressures, λ\nbecomes smaller, and ion motion through the sheath becomes increasingly collisional. This\nreduces the effective ion energy at the surface, often described as 𝐸 ≈ 𝑞𝑉/1+𝛼(𝑠/𝜆 ),\n𝑖 𝑠 𝑖\nwhere 𝑞 is the ionic charge, 𝑉 is the sheath potential, 𝑠 is the sheath thickness, 𝜆 is\n𝑠 𝑖\nthe ion mean free path, and 𝛼 is a proportionality factor. Thus, higher pressures inherently\nlower the ion bombardment energy, thereby mitigating interfacial damage. Second,\noxidation in O plasmas is primarily governed by neutral radical fluxes. The net radical\n2\n1\nflux can be expressed as 𝛤 ≈ 𝑛 (𝑣), where 𝑛 is the radical density and (𝑣) is the\n𝑟 𝑟 𝑟\n4\nmean thermal velocity. At higher pressures, the diffusion coefficients decrease 𝐷 ∝ 1/𝑃,\nreducing wall losses of radicals and consequently increasing the steady-state radical\ndensity 𝑛 . This, in turn, enhances the net radical flux 𝛤, thereby accelerating the\n𝑟 𝑟\noxidation rate. Taken together, these expectations suggest that operating under higher\nprocess pressures, as typically employed in industrial systems, could accelerate the\noxidation kinetics by enhancing radical-mediated reactions, while simultaneously\nreducing ion-induced damage at the vdW interface. Importantly, this indicates that higher-\npressure operation may shorten the process time required to achieve a target dielectric\nthickness without introducing additional interfacial degradation.\nIn summary, based on both our experimental observations and theoretical considerations,\nwe suggest that the precise control of plasma power is indispensable for achieving\nreproducible high-κ dielectric conversion with robust vdW interface integrity. Accordingly,\nplasma power should be regarded as the primary quality-control parameter for process\noptimisation and eventual manufacturing implementation of this methodology.\n2. In Figure 3, as hysteresis is highly sensitive to sweep rate, bias range, and temperature, the\nclaimed ~3 mV hysteresis requires more comprehensive validation beyond the limited\nconditions shown. Please provide systematic characterization across wider temperature ranges\nand broader sweep rates.\n (Evaluation under broader sweep rates) Following the reviewer’s suggestion, we\nperformed additional measurements of MoS nFETs and WSe pFETs over a broader\n2 2\nrange of sweep rates. At the slowest applicable sweep rate of 0.01 V/s, the devices\nexhibited negligible hysteresis of ~3 mV, underscoring the extremely low density of\ninterface states and border traps within the HfO layer of our proposed HfO /TMD\n2 2\nstructures (revised Fig. 3d–f).\nThe rationale for setting 0.01 V/s as the practical lower bound is as follows. First, the\nhysteresis typically observed in transfer characteristics is intrinsically governed by charge\ntrapping and detrapping dynamics at the dielectric/semiconductor interface, which occur\non finite time scales. At slower sweep rates, the time window is sufficiently long for trap\nstates to exchange carriers with the channel, thereby revealing the full extent of hysteresis.\nBy contrast, when the sweep rate becomes excessively fast, the probability of\ntrapping/detrapping events occurring within the sweep time frame decreases substantially.\nUnder such conditions, the measured hysteresis no longer reflects the intrinsic trap density\nbut instead the limitations imposed by the measurement speed itself. Therefore, we note\nthat exploring sweep rates much higher than those presently employed would provide\nlimited physical insight. Accordingly, we conducted measurements at sweep rates slower\nthan 0.025 V/s (the slowest condition used in the initial Fig. 3d–f) to ensure that the\nextracted hysteresis faithfully reflects the intrinsic trap dynamics rather than being\nconstrained by instrumental limitations.\nMore importantly, although our measurement system (Keithley 4200) can, in principle,\ngenerate arbitrarily slow sweep rates by combining small voltage steps with long delay\ntimes, the effective lower bound is restricted by the noise floor, thermal drift, and time-\ndependent instabilities. As a result, the practically applicable slowest sweep rate is ~0.01\nV/s, below which the signal-to-noise ratio becomes unfavourable and renders further\nreduction ineffective. Notably, this sweep rate already represents an extreme condition,\neven when compared with those employed in previously reported 2D gate stacks [R1–R3].\nFollowing the reviewer’s comments, the newly measured results, together with those\naddressing Comment #3, have been incorporated into the revised Manuscript as follows:\nFigure 3. vdW interface-integrated MoS nFET and WSe pFET. a, Schematic of\n2 2\nthe top-gated FET fabricated with the vdW interface-integrated HfO /TMD (MoS ,\n2 2\nWSe ) gate stack (~5 nm of MoS & WSe , ~10 nm HfO , Channel length and width\n2 2 2 2\nare 3 um, respectively). b, Extracted D as a function of frequency using the\nit\nconduction method from multi-frequency capacitance-voltage measurements. c,\nCumulative transfer characteristics of 40 MoS nFETs and WSe pFETs with the\n2 2\nmedian transfer curves highlighted (at V = ±0.5, respectively). Note that all the\nDS\ndevices were measured at gate voltage sweeping speed of 0.025 V/s. Both MoS nFET\n2\nand WSe pFET exhibit the near-ideal subthreshold swing (61 mV/dec and 63 mV/dec,\n2\nrespectively, at 300 K) with low gate leakage current of ~10-13 A. d-f, The full view\n(d) and enlarged view (e,f) of the dual sweep transfer curves measured at various gate\nvoltage sweeping speeds, indicating negligible hysteresis of ~3 mV (Inset: enlarged\nview of measured hysteresis under gate sweep rate of 0.01 V/s). g-i, The full view (g)\nand enlarged view (h,i) of the dual sweep transfer curves under different gate voltage\nsweeping ranges, also exhibiting small hysteresis of ~3 mV (Inset: enlarged view of\nmeasured hysteresis under gate sweep range; -0.5 V to 0.8 V, and 0.5 V to -0.8 V,\nrespectively).\n(revised Manuscript, page 25)\n (Evaluation under wider temperature ranges) In response to the reviewer’s comment,\ncharacterisation over a wider temperature range was conducted (revised Supplementary\nFig. 21). To probe the trapping and detrapping dynamics under thermally activated\nconditions, the temperature was systematically increased from 300 K to 500 K. Negligible\nhysteresis of ~3.4 mV was observed at 500 K, reinforcing that trap activity at the proposed\nvdW interface is strongly suppressed.\nThe detailed characterisation procedures and corresponding results have been included in\nthe revised Supplementary Information as follows:\nSupplementary Figure 21. Temperature-dependent electrical characteristics. a,b,\nTransfer characteristics of HfO /MoS nFETs and HfO /WSe pFETs measured at various\n2 2 2 2\ntemperature ranges. All measurements were performed at ±V = 0.5 V with a gate sweep\nDS\nrate of 0.01 V/s. The inset presents an enlarged view of the transfer curves during forward\nand reverse gate sweeps measured at 500 K. c, Temperature dependence of hysteresis\nvalues for HfO /MoS nFETs and HfO /WSe pFETs.\n2 2 2 2\n“Temperature-dependent transfer characteristics of MoS nFETs and WSe pFETs are\n2 2\nshown in Supplementary Fig. 21a,b. To probe the trapping and detrapping dynamics under\nthermally activated conditions, the temperature was systematically increased from 300 K\nto 500 K. Negligible hysteresis of ~3.4 mV was observed even at 500 K, confirming that\ntrap activity at the proposed vdW interface is strongly suppressed. The corresponding\nhysteresis values across different temperatures are summarised in Supplementary Fig. 21c.\nThe preservation of such stable electrical characteristics up to 500 K demonstrates that the\ndevices operate without noticeable degradation, while maintaining minimal hysteresis.\nThis temperature-independent behaviour further underscores the extremely low density of\ninterfacial defects achieved by our vdW integration strategy, together with the excellent\nelectrical reliability confirmed by the bias-temperature stress results.”\n(revised Supplementary Information, page 29)\nReferences\n[R1] Zhou, L., et al. Vertically grown metal nanosheets integrated with atomic-layer-deposited\ndielectrics for transistors with subnanometre capacitance-equivalent thicknesses. Nat. Electron.\n7, 662-670 (2024).\n[R2] Lu, Z., et al. Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals\nintegration. Nat. Commun. 14, 2340 (2023).\n[R3] Zhu, C-Y., et al. Magnesium niobate as a high-κ gate dielectric for two-dimensional\nelectronics. Nat. Electron. 7, 1137-1146 (2024).\n3. What are the specific device dimensions (channel length, width, and area) for the FETs\ncharacterized in Figure 3? The transfer characteristics should be presented as current density\nrather than absolute current values to enable proper benchmarking against literature and\nindustry standards.\n Both the channel length and width are 3 μm, as shown in Fig. 3.\nFollowing the reviewer’s suggestion, the transfer characteristics in Fig. 3 have been\nreplotted in terms of current density. The updated figures, together with the results\naddressing Comment #2, have been incorporated into the revised Manuscript (page 25).\n4. The manuscript lacks comprehensive thermal stability analysis. Given that the vdW interface\nis maintained through weak interactions, how does the HfO /TMD interface behave under\n2\nthermal cycling conditions relevant to practical applications? What is the long-term reliability\nof these interfaces under bias-temperature stress?\n (HfO 2 /TMD interface behaviour under thermal cycling conditions) Following the\nreviewer’s comments, the behaviour of the HfO /TMD interface under thermal cycling\n2\nconditions was investigated. In accordance with industry reliability standards [R1,2], the\ncycling conditions were defined as a temperature range from –40 °C to +125 °C, with a\nramp rate (heating/cooling) limited to ±10 °C/min and a dwell time of 2–3 min at each\ntemperature. Under this standard framework, the HfO /TMD heterostructures were\n2\nsubjected to up to 200 thermal cycles. After cycling, cross-sectional STEM analyses\nconfirmed that the HfO /TMD vdW interfaces remained clean and abrupt, with no\n2\ndetectable interfacial reaction, collapse, or delamination (revised Supplementary Fig. 22).\nIn addition, the negligible variation in SS, remaining close to the Boltzmann limit at room\ntemperature after thermal cycling, provides further evidence of the thermal stability of the\nproposed vdW interface. (Fig. R17).\nThis stability can be rationalised by several intrinsic merits of the vdW interface system.\nFirstly, the relatively small coefficient of thermal expansion (CTE) mismatch between\nHfO (CTE ≈ 5–6 × 10-6 K-1) and layered TMDs such as MoS and WSe (CTE ≈ 7–9 ×\n2 2 2\n10-6 K-1) minimises the generation of interfacial stress during –40 ↔ 125 °C cycling [R3–\n7]. Second, unlike covalently bonded interfaces that often involve chemically reactive\ninterlayers prone to stress concentration, the HfO /TMD interface is chemically inert and\n2\nfree of reaction layers, allowing thermal strain to be distributed uniformly across the\natomically flat vdW interface [R8,R9]. Third, the lamellar nature of TMDs provides\nstructural compliance through interlayer sliding, which acts as an inherent stress-relief\nmechanism under repeated heating and cooling [R10,R11]. Taken together, these results\nstrongly support that the HfO /TMD vdW interface maintains robust stability under\n2\nindustry-standard thermal cycling conditions.\nDetailed characterisation procedures and measurement results have been added in the\nrevised Supplementary Information (Supplementary Figure 22) and the relevant\ndescriptions are mentioned in the revised manuscript as follows:\n“……and its potential for broad applicability in various 2D semiconductor device\nplatforms. The robust vdW interface maintained throughout thermal cycling further\ndemonstrates its thermal stability (Supplementary Fig. 22). The scalability of this\nmethodology toward wafer-scale…”\n(revised Manuscript, page 6)\nSupplementary Figure 22 . Thermal stability of the vdW interface. a, b, Cross-\nsectional STEM images of HfO /MoS and HfO /WSe heterostructures after ~200\n2 2 2 2\nthermal cycles. \n“The thermal stability of the proposed vdW interface was evaluated by examining the\nbehaviour of the HfO /TMD interface under thermal cycling conditions. Following the\n2\nindustry reliability standards43,44, the thermal cycling range was set from –40 °C to\n+125 °C, with a ramp rate (heating/cooling) limited to ±10 °C/min and a dwell time of\n2–3 min at each temperature. Under these conditions, the HfO /TMD heterostructures\n2\nwere subjected to up to 200 thermal cycles. Cross-sectional STEM analyses after cycling\nconfirmed that the HfO /TMD vdW interfaces (Supplementary Fig. 22a,b) remained clean\n2\nand abrupt, with no detectable interfacial reaction, collapse, or delamination, thereby\ndemonstrating the robust thermal stability of the proposed vdW interface.”\n(revised Supplementary Information, page 30)\nSupplementary References\n[43] JEDEC Solid State Technology Association. JESD22-A104F.01 Temperature\nCycling (JEDEC JESD22-A104F specification), JEDEC, Arlington, VA, USA.\n[44] Automotive Electronics Council. AEC-Q100 Rev. G – Failure Mechanism Based\nStress Test Qualification for Integrated Circuits, AEC-Q100 standard, AEC Council.\nFigure R17. Electrical characteristics under thermal cycling. a, b, Transfer\ncharacteristics of MoS nFET and WSe pFET recorded every 50 thermal cycles.\n2 2\nMeasurements were performed at ±V = 0.5 V, a gate sweep rate of 0.01 V/s, and 300 K.\nDS\nThe negligible variation in SS, which remains close to the Boltzmann limit even after\nrepeated thermal cycling, highlights the robustness of the proposed vdW interface.\n (Reliability under bias-temperature stress) To further assess reliability, bias-\ntemperature stress measurements were performed on MoS nFETs and WSe pFETs. The\n2 2\ndevices were subjected to a stress bias of V = 4 V (corresponding to E = 4 MV/cm)\nstress stress\nat 300 K and 380 K for progressively increasing stress durations (revised Supplementary\nFig. 25). Following the generally implemented reliability criteria, measurements were\ncarried out over a temperature range from room temperature to 380 K. The measured |ΔV |\nth\nvalues were ~0.03 V for both MoS nFET and WSe pFET at 300 K (revised\n2 2\nSupplementary Fig. 25a-c), while under more stringent high-temperature stress conditions\nat 380 K, |ΔV | remained well controlled at 0.09 V (MoS nFET) and 0.07 V (WSe pFET)\nth 2 2\n(revised Supplementary Fig. 25d-f). Importantly, the normalised |ΔV |/E value of\nth stress\n~0.007 V/(MV/cm) demonstrates improved reliability compared with the very limited\nnumber of assessments previously reported for 2D gate stacks (revised Supplementary Fig.\n25g) [R12–21].\nThe bias–temperature stress stability observed in our devices can be understood within the\nframework of the hydrogen-release model, which is among the most widely accepted\nmechanisms in reliability modelling [R21]. Within this context, two factors are particularly\ncritical. First, in conventional ALD-grown HfO dielectrics, Hf–H bond formation\n2\noriginating from precursor chemistry is a well-known reliability concern [R21]. Under\nbias–temperature stress, hydrogen released from these bonds can diffuse into the TMD\nchannel, react with chalcogen atoms (S or Se), and generate vacancies, which subsequently\ninteract with oxide traps to accelerate degradation. By contrast, our dry transfer of the 2D\nprecursor (HfSe ) followed by plasma oxidation fundamentally suppresses Hf–H bond\n2\nformation and hydrogen incorporation, thereby eliminating a primary degradation pathway.\nSecond, our approach preserves an atomically sharp and chemically intact vdW interface\nbetween HfO and the underlying TMD channel. Unlike conventional deposition methods,\n2\nwhich disrupts the dangling-bond-free TMD surface and introduces a high density of\ninterfacial defects, our process maintains clean interfacial integrity and suppresses defect\ngeneration. This is directly supported by electrical signatures: SS values close to the\nBoltzmann limit at room temperature, negligible hysteresis (~3 mV at 0.01 V/s), narrow\nSS variability (CV < 2%), and suppressed D of 7.1 × 1010 cm-2 eV-1 (MoS ) and 8.4 ×\nit 2\n1010 cm-2 eV⁻¹ (WSe ).\nbias–temperature instability model [R22-R24], expressed as |ΔV | ~ 𝐴𝐸𝑚𝑡𝑛exp(−𝐸 /\nth 𝑎\n𝑘𝑇), where 𝐴 is a prefactor reflecting the initial trap density, 𝐸𝑚 denotes the electric-\nfield dependence, 𝑡𝑛 describes the time-dependent power law, and exp(−𝐸 /𝑘𝑇)\n𝑎\nrepresents the thermally activated contribution. The modest increase in |ΔV | when raising\nth\nthe temperature from 300 K to 380 K indicates that the number of traps or defects\ndynamically responsive to thermal activation energy is inherently very limited,\ncorresponding to a suppressed D [R25,26] and weak activation dependence. This implies\nit\nthat the bias-temperature stress behavior in our devices is governed predominantly by\ncharge exchange with a very limited number of pre-existing traps. These findings\ndemonstrate that our atomically flat vdW interface-integrated high-κ dielectric strategy\nenhances the long-term reliability of 2D semiconductor devices.\nThe bias–temperature results have been included in the revised Supplementary\nInformation (Supplementary Figure 25) and are mentioned in the revised Manuscript as\nfollows:\n“………. all fabricated using the same process (Fig. 3c and Supplementary Fig. 23). “The\nstability and reliability of the fabricated FETs were further corroborated by time-dependent\nelectrical performance and bias–temperature stress durability (Supplementary Figs. 24 and\n25).”\n(revised Manuscript, page 8)\nSupplementary Figure 25. Electrical characteristics under bias-temperature stress.\na,b, Time-evolution transfer characteristics of MoS nFETs and WSe pFETs measured\n2 2\nunder posititve- and negative-bias stress at 300 K. c, Summarized variations in V as a\nth\nfunction of the applied stress time at 300 K. d,e, Time-evolution transfer characteristics of\nMoS nFETs and WSe pFETs measured under posititve- and negative-bias stress at 380\n2 2\nK. f, Summarized variations in V as a function of the applied stress time at 380 K. g,\nth\nBenchmarking of bias-temperature–induced V shifts normalised to the dielectric electric\nth\nfield, as reported for 2D gate stacks and Si technologies45-54.\n“To further verify the reliability of the vdW interface, bias–temperature stress\nmeasurements were performed on MoS nFETs and WSe pFETs with ~10 nm HfO gate\n2 2 2\ndielectrics under a stress bias of V = 4 V (corresponding to E = 4 MV/cm),\nstress stress\nat temperatures of 300 K (Supplementary Fig. 25a,b) and 380 K (Supplementary Fig. 25d,e),\nwith progressively increasing stress durations. The measured |ΔV | values were\nth\napproximately 0.03 V for both MoS nFET and WSe pFET at 300 K (Supplementary\n2 2\nFig.25c), and 0.09 V (MoS nFET)/0.07 V (WSe pFET) under high-temperature stress of\n2 2\nth\nindicates that the density of interfacial states available to participate in trap-assisted charge\ndynamics is low in the proposed HfO /TMD structures. This result highlights that, even\n2\nwhen thermal energy is sufficient to activate trap dynamics, the vdW interface presents\nonly a very limited number of active states, thereby ensuring superior interfacial stability.\nNotably, the exceptionally low normalised |ΔV |/E value of approximately 0.007\nth stress\nV/(MV/cm) highlights the markedly enhanced reliability of the proposed vdW interface-\nintegrated HfO /TMD structure, representing a clear advancement over previously\n2\nreported 2D gate stacks 45-54.”\n(revised Supplementary Information, page 33)\nSupplementary references\n[45] Illarionov, Y. Y. et al. The role of charge trapping in MoS₂/SiO₂ and MoS₂/hBN field-effect\ntransistors. 2D Materials 3, 035004 (2016).\n[46] Illarionov, Y. Y. et al. Bias-temperature instability in single-layer MoS₂ transistors.\nApplied Physics Letters 105, 143507 (2014).\n[47] Yuan, H.-W. et al. PBTI investigation of MoS₂ n-MOSFET with Al₂O₃ gate dielectric.\nIEEE Electron Device Letters 38, 677–680 (2017).\n[48] Illarionov, Y. Y. et al. Long-term stability and reliability of black phosphorus field-effect\ntransistors. ACS Nano 10, 9543–9554 (2016).\n[49] Illarionov, Y. Y. et al. Improved hysteresis and reliability of MoS₂ transistors with high-\nquality CVD growth and Al₂O₃ encapsulation. IEEE Electron Device Letters 38, 1763–1766\n(2017).\n[50] Illarionov, Y. Y. et al. Ultrathin calcium fluoride insulators for two-dimensional field-effect\ntransistors. Nature Electronics 2, 230–236 (2019).\n[51] Grasser, T. et al. Analytic modeling of the bias temperature instability using\ncapture/emission time maps. IEDM Technical Digest 27.4.1 (2011).\n[52] O’Sullivan, B. J. et al. Overview of bias temperature instability in scaled DRAM logic for\nmemory transistors. IEEE Transactions on Device and Materials Reliability 20, 258–266\n(2020).\n[53] Yao, Z. et al. Transferrable, wet-chemistry-derived high-k amorphous metal oxide\ndielectrics for two-dimensional electronic devices. Nat. Commun. 16, 1482 (2025).\n[54] Lan, H.-Y. et al. Reliability of high-performance monolayer MoS₂ transistors on scaled\nhigh-κ HfO₂. npj 2D Materials and Applications 9, 5 (2025).\nReferences\n[R1] JEDEC Solid State Technology Association. JESD22-A104F.01 Temperature Cycling\n(JEDEC JESD22-A104F specification), JEDEC, Arlington, VA, USA.\n[R2] Automotive Electronics Council. AEC-Q100 Rev. G – Failure Mechanism Based\nStress Test Qualification for Integrated Circuits, AEC-Q100 standard, AEC Council.\n[R3] Lin, Z. et al. Thermal expansion coefficient of few-layer MoS₂ studied using temperature-\ndependent Raman spectroscopy. npj 2D Mater. Appl. 5, 55 (2021).\n[R4] Kucinski, T. M. et al. Direct measurement of the thermal expansion coefficient of 2H-\nMoS₂ and 2H-WSe₂ between 10 and 300 K. npj 2D Mater. Appl. 8, 12 (2024).\n[R5] Ding, Z. et al. First-principles calculations of the thermal conductivity and thermal\nexpansion of HfO₂ polymorphs. Materialia 13, 100834 (2020).\n[R6] GlobalSino. Thermal expansion of HfO . Available at:\n2\nhttps://www.globalsino.com/EM/page2069.html (accessed 2025).\n[R7] Kisi, E. H. & Howard, C. J. Thermal expansion of HfO and ZrO . J. Am. Ceram. Soc. 73,\n2 2\n175–177 (1990).\n[R8] Qin, H. et al. Size and temperature effect on the mechanical properties of\ngraphene/hexagonal boron nitride van der Waals heterostructure. Thin Solid Films 692, 137584\n(2021).\n[R9] Gao, Y. et al. Spontaneous curvature in two-dimensional van der Waals heterostructures.\nNat. Commun. 16, 717 (2025)\n[R10] Sliding properties of transition metal dichalcogenide bilayers. J. Chem. Phys. 163,\n084709 (2025).\n[R11] Jiang, W. et al. Anisotropic Interlayer Force Field for Heterogeneous van der Waals\nJunctions. J. Phys. Chem. C 128, 12345–12356 (2024)\n[R12] Illarionov, Y. Y. et al. The role of charge trapping in MoS₂/SiO₂ and MoS₂/hBN field-\neffect transistors. 2D Materials 3, 035004 (2016).\n[R13] Illarionov, Y. Y. et al. Bias-temperature instability in single-layer MoS₂ transistors.\nApplied Physics Letters 105, 143507 (2014).\n[R14] Yuan, H.-W. et al. PBTI investigation of MoS₂ n-MOSFET with Al₂O₃ gate dielectric.\nIEEE Electron Device Letters 38, 677–680 (2017).\n[R15] Illarionov, Y. Y. et al. Long-term stability and reliability of black phosphorus field-effect\ntransistors. ACS Nano 10, 9543–9554 (2016).\n[R16] . Illarionov, Y. Y. et al. Improved hysteresis and reliability of MoS₂ transistors with high-\nquality CVD growth and Al₂O₃ encapsulation. IEEE Electron Device Letters 38, 1763–1766\n(2017).\n[R17] Illarionov, Y. Y. et al. Ultrathin calcium fluoride insulators for two-dimensional field-\neffect transistors. Nature Electronics 2, 230–236 (2019).\n[R18] Grasser, T. et al. Analytic modeling of the bias temperature instability using\ncapture/emission time maps. IEDM Technical Digest 27.4.1 (2011).\n[R19] O’Sullivan, B. J. et al. Overview of bias temperature instability in scaled DRAM logic\nfor memory transistors. IEEE Transactions on Device and Materials Reliability 20, 258–266\n(2020).\n[R20] Panarella, L. et al. Analysis of BTI in 300 mm integrated dual-gate WS₂ FETs.\nDevice Research Conference (DRC) 2022, 55272 (2022).\n[R21] Lan, H.-Y. et al. Reliability of high-performance monolayer MoS₂ transistors on scaled\nhigh-κ HfO₂. npj 2D Materials and Applications 9, 5 (2025).\n[R22] Jeon, D. et al. Bias temperature instability of HfO₂/TiN gate stacks for advanced CMOS\napplications. IEEE Trans. Electron Devices 55, 225–232 (2008)\n[R23] Grasser, T. et al. The paradigm shift in understanding the bias temperature instability:\nFrom reaction–diffusion to switching oxide traps. IEEE Trans. Electron Devices 58, 3652–\n3666 (2011).\n[R24] Alam, M. A. & Mahapatra, S. A comprehensive model of PMOS NBTI degradation.\nMicroelectron. Reliab. 45, 71–81 (2005)\n[R25] Cho, M. et al. Improved reliability of high-κ/metal gate stacks by interface engineering.\nAppl. Phys. Lett. 92, 132902 (2008)\n[R26] Illarionov, Y. Y. et al. Reliability of state-of-the-art transition metal dichalcogenide\ntransistors: BTI and HCI perspectives. Nat. Electron. 3, 147–155 (2020)\n5. Regarding Figure 5, while the CFET ring oscillator demonstration is impressive, the\nachieved frequency (~91 MHz) remains below the record 2.65 GHz\n(https://doi.org/10.1038/s41928-023-01052-5). Could the authors provide a critical analysis of\nthe limiting factors (parasitic capacitances, contact resistance, channel mobility, etc.) and\ndiscuss the roadmap for achieving competitive frequencies? What are the fundamental and\nengineering challenges that need to be addressed to reach GHz-level performance comparable\nto advanced silicon technologies?\n To discuss the pathway toward competitive operating frequencies, we assessed the limiting\nfactors using TCAD simulations. This analysis provides a valuable roadmap,\ndemonstrating that GHz-level (1.5 GHz at V = 1.0 V) operation is attainable even at the\nDD\ncurrent device dimensions through suppressed parasitic capacitance and optimised ohmic\ncontacts, while THz-level (4 THz at V = 1.0 V) operation, comparable to that of the\nDD\nadvanced silicon technologies, becomes feasible upon further scaling to the nanometre\nregime (revised Supplementary Fig. 35a). Device analysis and circuit-level performance\nevaluation were performed using Synopsys Sentaurus (Synopsys Inc., Mountain View, CA,\nUSA), a 3D technology computer-aided design software package. For the HfO /MoS and\n2 2\nHfO /WSe gate-stack structures, the material parameters were defined based on ab initio\n2 2\nsimulation results and Supplementary Table 3 to determine their energy-band\ncharacteristics, while the dielectric properties were adopted from the experimentally\nextracted values. The electrical transport was analysed through a drift–diffusion model,\nand the mobility model included a high-field saturation model, thin layer model, and an\nE model that considered the interfacial surface roughness scattering. To describe\nnormal\ncarrier tunnelling across the HfO /TMD interfaces, a nonlocal tunnelling model was\n2\nemployed that includes both elastic and inelastic phonon-assisted processes, as well as\ntrap-assisted tunnelling contributions. To describe the gate oxide leakage current, the\nUniversity of Bologna model was used. Using these calibrated device models, the\nevaluation was performed within a sequential optimisation framework—beginning with\nparasitic capacitance suppression, followed by contact resistance reduction, and\nculminating in aggressive gate-length scaling. The detailed analytical protocol is outlined\nbelow.\nFirst, the potential enhancement in operating frequency achievable through the\nsuppression of extrinsic parasitic capacitances was evaluated. In our TCAD-simulated 3D\nCMOS structure, interconnect-related parasitics were identified as the dominant\ncontributor, accounting for ~88.4% of the total effective capacitance. Suppressing these\ninterconnect-related parasitics reduces the effective capacitance from ~185 fF/µm to ~21.5\nfF/µm, which translates into an improved operating frequency of ~0.5 GHz at V = 1 V\nDD\n(revised Supplementary Fig. 35b). The single-stage delay was calculated using the\nfollowing equation: 𝜏 = 1/(2𝑓× # stage) = R × C , where R = R + R + R , C =\neff eff eff ch c int eff\n1/(R × 𝑓).\neff\nSecond, building upon the suppression of parasitic capacitances, source/drain\ncontact optimisation was investigated. High Schottky barriers at evaporated metal/TMD\njunctions are known to currently limit the achievable on-current densities, which are\ncritical for attaining competitive operating frequencies. TCAD simulations incorporating\nohmic contact resistances of reported 116 Ω·µm and 41 Ω·µm for n- and p-type devices,\nrespectively [R1,2], indicate that the on-current can be enhanced by ~4× (n-type) and ~10×\n(p-type) (revised Supplementary Fig. 35c). Such improvement enables GHz-scale\noperation, surpassing previously reported performance even at lower supply voltages [R3].\nFinally, the single-stage frequency as a function of scaled gate length was analysed\n(revised Supplementary Fig. 35d). By applying aggressive gate-length scaling, THz-level\noperation can be anticipated. Notably, single-gate operation begins to degrade below ~30\nnm due to unbalanced n/p transport arising from short-channel effects, whereas these\neffects can be mitigated by adopting a double-gate structure, which restores electrostatic\ncontrol and enables projected frequencies up to ~4 THz. This finding further highlights the\nimportance of gate-all-around CFET architectures for future technology nodes.\nIn summary, the present frequency limitation is primarily extrinsic—arising from parasitic\ncapacitances and contact resistance—rather than fundamental. We believe that, through\nsystematic engineering optimisation, the CFET architecture possesses the intrinsic\ncapability to achieve, and potentially surpass, the performance of advanced silicon\ntechnologies in future nodes.\nThese results have been included in the revised Supplementary Information\n(Supplementary Figure 35) and are mentioned in the revised Manuscript as follows:\n“channels (Fig. 5d and Supplementary Table 2), outperforming the reported experimental\nresults65,69,75,76,77,78,79,80,81,82,83,84. “Further optimisation, including the suppression of\nparasitic capacitances, reduction of contact resistance, and aggressive gate-length scaling\nis expected to further enhance the signal delivery and overall performance, achieving\nlevels comparable to those of advanced technology nodes (Supplementary Fig. 35).”\n(revised Manuscript, page 11)\nSupplementary Fig. 35. TCAD-simulated performance boosting of single-stage. a,\nSummary of TCAD simulation results showing the roadmap toward achieving competitive\nfrequencies for advanced technology nodes (DG and SG denote the double-gate and\nsingle-gate configurations, respectively). This roadmap indicates that operating\nfrequencies comparable to those of advanced silicon nodes specified in the IRDS can be\nachieved by suppressing parasitic capacitances, reducing contact resistance, and\nimplementing aggressive dimensional scaling, enabling CFETs to reach GHz-class\nperformance at the current µm scale and extend into the THz regime at advanced nodes.\nb, TCAD-simulated frequency enhancement as a function of supply voltage with\nsuppressed parasitic capacitances. In our TCAD-simulated 3D CMOS structure,\ninterconnect-related parasitics were identified as the dominant contributor, accounting for\n~88.4% of the total effective capacitance. Suppressing these interconnect-related parasitics\nreduces the effective capacitance from ~185 fF/µm to ~21.5 fF/µm, corresponding to an\nimproved single-stage frequency of ~0.5 GHz at V = 1 V.\nDD\nc, TCAD-simulated frequency\nas a function of supply voltage with contact resistance optimisation. Simulations\nincorporating ohmic contact resistances of 116 Ω·µm and 41 Ω·µm for n- and p-type\ndevices, respectively, as reported in literature55,56, indicate that the on-current can be\nboosted by ~4× (n-type) and ~10× (p-type). Such improvement enables GHz-scale\noperation, surpassing previously reported performance even at lower supply voltages57. d,\nTCAD-simulated frequency as a function of scaled gate length (DG and SG denote double-\ngate and single-gate configurations, respectively). By applying aggressive gate-length\nscaling, THz-level operation can be anticipated. Notably, single-gate operation degrades\nbelow ~30 nm due to unbalanced n/p transport arising from short-channel effects, whereas\nthese effects can be mitigated by adopting a double-gate structure, which restores\nelectrostatic control and allows projected frequencies up to ~4 THz. This finding further\nunderscores the importance of gate-all-around CFET architectures for future technology\nnodes.\n(revised Supplementary Information, page 43)\nSupplementary references\n[55] Zhang, X. et al. Scaling MoS₂ transistors to 1 nm node. 2024 IEEE International Electron\nDevices Meeting (IEDM), 29.1–29.4 (2024).\n[56] Liu, Y. et al. Gate-driven band modulation hyperdoping for high-performance p-type 2D\nsemiconductor transistors. Science 387, 421–427 (2025).\n[57] Liu, S. et al. Two-dimensional semiconductor integrated circuits operating at gigahertz\nfrequencies. Nat. Electron. 6, 123–130 (2023).\nReferences\n[R1] Zhang, X. et al. Scaling MoS₂ transistors to 1 nm node. 2024 IEEE International Electron\nDevices Meeting (IEDM), 29.1–29.4 (2024).\n[R2] Liu, Y. et al. Gate-driven band modulation hyperdoping for high-performance p-type 2D\nsemiconductor transistors. Science 387, 421–427 (2025).\n[R3] Liu, S. et al. Two-dimensional semiconductor integrated circuits operating at gigahertz\nfrequencies. Nat. Electron. 6, 123–130 (2023).\n6. Line 89 correction, “..the minimum EOT is limited to ~1.5 nm ...” should be \"~0.77 nm\" as\nclaimed in reference 35.\n It has been corrected to “~0.77 nm” in the revised manuscript accordingly.\nResponse to Reviewer #2\nWe are grateful for this review and appreciate your insightful comments.\nPlease find below our responses (in blue) to the comments (in black) provided by the reviewers.\nIn addition, revisions to the original article are indicated in black by the editorial requests\n(Supplementary Information).\nComments:\nIn my opinion, the authors have provided sufficient data to demonstrate the integrity of the\nunderlying TMD materials after oxidation, as well as the stability of the fabricated FETs by\nbias–temperature stress durability. Although the authors have outlined potential strategies for\nlarge-area integration, such as through CVD or printing techniques, I recommend that they\nshould include more statistical device characterization to evaluate the quality of the transfer\nmethod. This would help substantiate the scalability, reliability, and overall stability of the\nproposed approach. Additionally, it would be valuable if the authors could comment on the\napplicability of this method to other material systems, to highlight its broader potential. Once\nthese points have been addressed, I would be happy to recommend publication.\n (Statistical device characterisation) Following the reviewer’s original comment #5, the\nstatistical device characterisation of 40 MoS n-type and WSe p-type FETs has been\n2 2\nincluded in the original response letter. The results exhibited a narrow variation in SS\nvalues approaching the Boltzmann limit (≈60 mV/dec) at room temperature, along with\nnegligible variation in V . These results, when compared with recently reported gate\nth\ndielectric integrations on 2D semiconductors, suggest the formation of a stable vdW\ninterface through the proposed transfer process. The findings collectively indicate the\nimproved uniformity and reproducibility of the proposed methodology, confirming the\nquality and reliability of the transfer approach. Furthermore, key industrial players such as\nSamsung Electronics have recently demonstrated 200-mm wafer-scale integration of\npolycrystalline MoS TFTs using MOCVD growth combined with automated transfer in\n2\nan industrial-standard 200-mm fabrication facility [Nat. Electron. 2024, DOI:\n10.1038/s41928-024-01158-4]. This report underscores that large-area transfer is being\nseriously considered in industry as a practical and scalable route for the mass production\nof 2D semiconductor electronics. In line with this industrial trend, we are actively\nexploring scalable, large-area integration of the proposed method as part of our ongoing\nand future studies.\nThe relevant results regarding statistical device characterisation have been incorporated\ninto the revised Supplementary Information as follows.\nSupplementary Figure 23. Statistical performance distribution of thrasfer\ncharacteristics. a–c, Histograms of key performance metrics, including V , SS, and the\nth\non–off current ratio, extracted from the transfer curves shown in Fig. 3c. The suppressed\nvariation in V , combined with the low SS (close to the Boltzmann limit) and high on–off\nth\ncurrent ratio, indicates the high reproducibility of the proposed vdW interface-integrated\nFETs. d-f, Device-to-device variability presented as cumulative probability distributions\nof V , SS, and on-off current ratio, extracted from (a-c). g, Gate leakage current\nth\ncharacteristic obtained from newly fabricated 3 MoS nFETs and 3 WSe pFETs.\n2 2\n“To quantitatively evaluate device-to-device variations, cumulative probability\ndistributions of the V , SS, and I , extracted from the transfer curves of 40 MoS nFETs\nth on/off 2\nand WSe pFETs shown in Fig. 3c, are presented in Supplementary Fig. 23d-f. Device\n2\nvariation was quantified using the coefficient of variation (CV), which measures the\ndispersion of a probability distributions and is defined as CV = (𝜎/𝜇) × 100 (%), where\n𝜎 and 𝜇 represent the standard deviation and mean value, respectively. Both V and SS\nth\nexhibit narrow variations, with CV values of <3% and <2%, respectively (Supplementary\nFig. 23d,e), representing improved uniformity compared with recently reported\nGa O /MoS (SS: CV ≈ 5%), Y O /MoS (SS: CV ≈ 20–25%), MgNb O /MoS (V : CV\n2 3 2 2 3 2 2 6 2 th\n≈ 18%), and HZO/MoS gate stacks (V : CV ≈ 50%)58-61. In contrast, the I exhibits\n2 th on/off\nrelatively larger variability (Supplementary Fig. 23f), which can be directly correlated with\nthe broad distribution of on-currents, as observed in Fig. 3c. This variability is primarily\nattributed to the current state of contact engineering, which has not yet been fully\noptimised, rather than to the HfO dielectric itself. This interpretation is consistent with\n2\npreviously reported results62, further supporting our conclusion that contact resistance is\nthe dominant factor underlying the observed variation. To further substantiate this point,\nwe fabricated additional MoS nFETs and WSe pFETs and measured their gate leakage\n2 2\ncurrents (Supplementary Fig. 23g). All devices exhibited negligible variation in leakage,\nconfirming that the HfO layer does not contribute significantly to the observed variability.\non-current variation due to irregular contact resistance, which can be improved in future\nthrough optimised contact engineering. Importantly, the SS values of all devices exhibit\nnegligible CV values, underscoring the high reproducibility of the atomically flat vdW\ninterface, further supported by the structural uniformity shown in Supplementary Fig.\n10a,b”.\n(revised Supplementary Information, page 31)\nSupplementary References\n[58] Choudhuri, I. et al. Integration of high-κ native oxides of gallium for two-dimensional\ntransistors. Nat. Commun. 14, 1196 (2023).\n[59] Cao, Y. et al. A general one-step plug-and-probe approach to top-gated transistors for\nrapidly probing delicate electronic materials. Nat. Commun. 13, 6805 (2022).\n[60] Zhang, H. et al. Magnesium niobate as a high-κ gate dielectric for two-dimensional\nelectronics. Nat. Commun. 14, 2592 (2023).\n[61] Polanco, C. A. et al. Integration of freestanding hafnium zirconium oxide membranes\ninto two-dimensional transistors as a high-κ ferroelectric dielectric. Nat. Commun. 15,\n1185 (2024).\n[62] Shen, J. et al. Highly reproducible van der Waals integration of two-dimensional\nelectronics on the wafer scale. Nat. Commun. 15, 4467 (2024).\n (Applicability of this method to other material systems) This important point has been\naddressed in our present study (Fig. 2a–c, Supplementary Figs. 12–16), and additional\ndetails are provided below. The surface oxidation behaviour of three representative\nchannel materials (MoS , WSe , and HfSe ) was systematically analysed by evaluating\n2 2 2\ntheir chemical affinities—encompassing both the adsorption-energy landscape and\nreaction energetics—through ab initio molecular-dynamics simulations, in order to\nelucidate the channel reactivity and structural stability under the oxidation process (Fig.\nR1).\nFirstly, adsorption behaviour at the channel surface (Fig. R1a) was investigated. Among\nthe studied systems, oxidation-prone 2D semiconductors, here HfSe , shows the most\n2\nfavourable oxygen adsorption. O atoms can readily insert into the lattice at the lowest\nenergetic cost, and substitution of Se by O occurs without a noticeable barrier. This leads\nto the formation of robust O–Hf bonds and a substantial exothermic release (~6.9 eV per\nO atom), corresponding to a markedly negative Gibbs free energy change (ΔG < 0). By\ncontrast, for MoS and WSe , the oxygen adsorption energies (–5.6 eV and –4.6 eV,\n2 2\nrespectively) indicate strong surface binding, but the Gibbs free energy cost for direct\nsubstitution of Mo–S or W–Se bonds is considerably higher. Thus, oxygen atoms remain\nstabilised at adsorption sites without initiating substitution, leaving the channels\nchemically intact and allowing the preservation of atomically flat HfO /TMD vdW\n2\ninterfaces.\nSecondly, reactivity at defect sites (Fig. R1b) was investigated. When vacancy sites are\nexplicitly formed, HfSe exhibits the highest reactivity, with oxygen incorporation being\n2\nenergetically favorable and highly exothermic, driving the overall oxidation process\nthermodynamically spontaneous. This implies that once activation sites appear, oxidation\nof HfSe proceeds rapidly and uncontrollably, underscoring its classification as an\n2\noxidation-prone 2D semiconductor that can only be employed under very strict conditions\nand within a narrow process window. In contrast, for MoS and WSe , the Gibbs free\n2 2\nenergy cost for substitution at vacancy sites remains substantially higher, rendering oxygen\nincorporation energetically unfavorable. Consequently, oxygen is stabilised at the\nactivation sites without destructive substitution or chemical reaction, ensuring that these\nchannels remain chemically intact and thus suitable for integrating clean HfO /TMD vdW\n2\ninterfaces. Taken together, the combined analysis of adsorption energetics and defect-\nmediated reaction pathways demonstrates a clear contrast: while stable channels such as\nMoS and WSe are compatible with our proposed methodology, oxidation-prone 2D\n2 2\nsemiconductors like HfSe are inherently vulnerable as a channel.\nthis methodology can be generally applied by combining oxidation-prone 2D\nsemiconductors (e.g., HfSe , HfS , ZrSe , ZrS ) as 2D precursors for forming oxidised\n2 2 2 2\nhigh-κ dielectrics with relatively oxidation-resistant 2D semiconductors (e.g., MoS ,\n2 2 2 2 3\ncombination provides a broadly applicable strategy for constructing vdW interface–\nintegrated high-κ gate stacks, enabling flexible implementation across both logic and\nmemory device platforms.\nFigure R1. Chemical affinity. a, Adsorption energy landscape of oxygen atoms on\ndifferent 2D semiconductors (HfSe , MoS , WSe ). Red circles denote oxygen atoms.\n2 2 2\nOxygen adsorption is most favorable on HfSe (–6.9 eV), whereas MoS (–5.6 eV) and\n2 2\nWSe (–4.6 eV) show surface stabilisation without facile substitution. b, Site formation\n2\nand reaction energetics at vacancy sites. For HfSe , oxygen readily occupies Se vacancy\n2\nsites with energetically favorable, exothermic incorporation, driving spontaneous\noxidation. In contrast, MoS and WSe exhibit much higher substitution barriers.\n2 2\nThe relevant scripts have been incorporated into the revised manuscript as follows.\n“Our findings provide a pathway toward a broadly applicable framework for integrating\nhigh-κ dielectrics with diverse 2D semiconductors through atomically defined vdW\ninterfaces. This approach can be extended to a wide range of material systems and device\narchitectures, offering a versatile platform for future 2D semiconductor–based 3D logic\nand memory technologies aimed at enhanced scalability and energy-efficient computing”.\n(revised manuscript, page 12)"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors' outstanding responses have resolved the scientific and expositional issues present in the initial version. The revised manuscript demonstrates a qualitative improvement in experimental evidence, theoretical support, and logical discourse. The work presents a universal integration method with broad application prospects, backed by solid data, making its scientific value and innovation particularly prominent.\nI believe the manuscript now meets the publication standards of Nature Communications. Therefore, I recommend Acceptance of this manuscript.", "reviewer_2": "In my opinion, the authors have provided sufficient data to demonstrate the integrity of the underlying TMD materials after oxidation, as well as the stability of the fabricated FETs by bias–temperature stress durability. Although the authors have outlined potential strategies for large-area integration, such as through CVD or printing techniques, I recommend that they should include more statistical device characterization to evaluate the quality of the transfer method. This would help substantiate the scalability, reliability, and overall stability of the proposed approach. Additionally, it would be valuable if the authors could comment on the applicability of this method to other material systems, to highlight its broader potential. Once these points have been addressed, I would be happy to recommend publication.", "reviewer_3": "The authors have addressed my concerns exceptionally well. The comprehensive revision has substantially improved the manuscript’s scientific rigor and presentation quality. I hereby recommend acceptance for publication."}, "author_response": ""}]

Decision letter