Subthreshold Schottky-barrier transistor based on monolayer molybdenum disulfide

Domain: physics
Published: 2025-12-11
Editorial outcome: minor_revision

Abstract
While the internet of things (IoT) enhances global connectivity through trillions of sensors, the sensory signals are weak and require precise amplification and rapid transmission via thin-film transistor (TFT) interfaces, which must uphold high voltage gain and wide operating frequency range. In this work, we demonstrate a source-gated transistor (SGT) architecture integrating chemical vapor deposition (CVD)-grown monolayer MoS2 with thin high-k dielectrics. This transistor achieves subthreshold operation with high intrinsic gain and wide operating frequency range, even at an 80 nm channel-length (LCH). The optimization of output resistance, transconductance and subthreshold swing yields an SGT intrinsic gain exceeding 2.4 × 103, with no degradation as LCH scales from 1000 nm down to 80 nm. Additionally, benefitting from the ultra-short 80 nm LCH, microwave measurements show a high cut-off frequency of 208 MHz in the subthreshold regime. A monolithically integrated common-source amplifier operating in the subthreshold regime exhibits a high gain of 249 V/V at low supply voltage (0.5 V) and ultra-low power (~0.17 nW), indicating a promising path toward a universal high-performance transistor solution for high gain, high frequency, and ultra-low power applications.

Introduction
The Internet of Things (IoT) has the ability to provide every human access and communication to the world in unprecedented ways, thanks to the deployment of trillions of sensors1,2. This vast network of interconnected sensors enables the collection, exchange, and analysis of data by converting physical and chemical signals, e.g., light3, pressure4, temperature5, etc., into small amplitude analog electrical signals, giving way to improved efficiency, enhanced decision-making, and innovative implementations across multiple application domains. These weak output signals generated by sensors typically need high-precision amplification coupled with high-speed transmission by thin-film transistor (TFT)-based sensor-interfaces for subsequent signal processing and conditioning6. This requires TFT interface circuits to maintain a high voltage gain and low equivalent input noise across a wide frequency range to make them suitable for IoT implementations7.

In conventional TFTs, the channel length modulation effect causes a continuous rise in current after the TFT is saturated, which lowers the output resistance (ROUT) and reduces the intrinsic gain (Ai = gm × ROUT, where gm is the transconductance)8. To address this problem, two improved TFT structures have been proposed: the source-gated transistor (SGT)9 by Shannon et al. in 2003 and the Schottky barrier thin-film transistor (SB-TFT)10 by Lee and Nathan in 2016. These architectures generally create a Schottky barrier between the source contact and the semiconductor, so that the IDS is mainly dominated by the source barrier height controlled by the gate voltage (VGS) and is almost unaffected by the drain terminal, resulting in high ROUT and high Ai. Numerous subsequent reports have demonstrated such structures using silicon11–13, indium gallium zinc oxide (IGZO)14, organic7,15 and molybdenum disulfide (MoS2)16 channel materials. They all achieved high gains.

However, most if not all demonstrated TFTs operating in subthreshold exhibit low operating frequencies (<1 kHz), primarily limited by low current17 and long channel lengths (>10 µm)14 or low channel mobility7,15. To maintain high gain over a wider operating frequency range, the critical limitation lies in achieving high gain at higher frequencies. In conventional approaches, frequency performance is enhanced by aggressively scaling the channel length or adopting self-aligned structure18,19 to minimize gate parasitic capacitance. Such approaches are limited to improving cut-off frequency, however, at the cost of sacrificing intrinsic gain due to exacerbated short-channel effects (SCEs).

As discussed earlier, both SB-TFT and SGT exhibit strong immunity to SCEs, indicating great promise for high-frequency operation. Compared to the SB-TFT, the SGT is more immune to SCEs due to the insulating layer added between the source metal and semiconductor layer. This enhances vertical gate control and improves the shielding effect of the source on the drain field. Notably, with MoS2, which offers high mobility, atomic-layer channel thickness, and strong gate control capability20–25, better SGT scaling becomes possible. In addition, the SGT can operate in the subthreshold regime to achieve low power26. Therefore, by synergistically selecting the SGT structure and MoS2 as the channel material to minimize SCEs, and incorporating channel length scaling, coupled with gate dielectric engineering and subthreshold operation, it is possible to achieve high frequency operation without compromising high gain at low power consumption.

In this article, we demonstrate an 80 nm channel-length SGT based on chemical vapor deposition (CVD) of monolayer MoS2, with high intrinsic gain, high cut-off frequency, and operating in the subthreshold region. The SGT structure lends itself to a high source barrier, and a wide channel potential barrier is formed. The MoS2 SGT exhibits pinch-off regions occurring at both source and drain, leading to high output resistance (ROUT > 1011 Ω) in the subthreshold region. In addition, transconductance (gm) is improved by systematic optimization, by virtue of high mobility monolayer MoS2, thin gate dielectric and short-channel length. The overall optimization of gm and ROUT leads to an intrinsic gain (Ai = gm × ROUT) that is over ~2.4 × 103 with no degradation when LCH is scaled from 1000 to 80 nm. In addition, the device also exhibits small subthreshold swing (SS) (~70 mV/dec), small drain-induced-barrier-lowering (DIBL) effect (~7.3 mV/V), high transconductance efficiency (gm/IDS) (~38 S/A), low leakage current (below 10−12 A/μm), and high on/off ratio (over 109) at LCH = 80 nm. Besides, microwave measurements demonstrate a cut-off frequency of 208 MHz and a maximum oscillation frequency fMAX of 211 MHz of the SGT operated in the subthreshold regime at LCH = 80 nm. Finally, we further demonstrate a common-source amplifier operating in the subthreshold regime that exhibits a high gain of 249 V/V at low-supply voltage (0.5 V) and low power (~0.17 nW). This outperforms existing technologies using silicon, organics, oxides and other 2D materials, and provides for a universal high-performance transistor solution for high gain, high frequency and low power applications.

Results
Device structure and operating mechanism of MoS2 SGT
The schematic view of the MoS2 SGT device structure is shown in Fig. 1a. Contrary to the conventional MoS2 TFT, where the source/drain contacts are ohmic, in SGTs, the Schottky source contact increases the source barrier height, and the external gate is augmented at the source to increase the source barrier width. In device fabrication, CVD atomically thin one-layer (1L) MoS2 was chosen as the channel material. Detailed material information, including atomic force microscopy (AFM), Raman spectra and Photoluminescence (PL) spectra characterizations, are shown in Supplementary Figs. 1, 2, indicating the monolayer nature of MoS2. We performed electrical tests on conventional MoS2 TFTs and mobility (μFE) extracted is 29.3 cm2 V−1 s−1 (Supplementary Fig. 3), which confirms the high quality of the MoS2. The back gate used molybdenum (Mo) grown by magnetron sputtering and was patterned by dry-etching to ensure flatness and reduce leakage current. Palladium/Gold (Pd/Au) and Nickel/Gold (Ni/Au) fabricated using electron-beam evaporation (EBE) were chosen as the source/drain contacts because of their work function matching with the MoS2 channel to form Schottky source-contact and ohmic-drain-contact, respectively. The temperature-dependent measurements and barrier-height extractions27 supporting the contact behavior analysis are presented in Supplementary Fig. 4. As for the dielectric layer, hafnium oxide (HfO2) and aluminum oxide (Al2O3) were chosen owing to their excellent dielectric properties, low gate leakage current and low-temperature atomic-layer deposition (ALD) growth process capable of precisely controlling thickness. All key lithography steps are done by electron-beam lithography (EBL). The detailed fabrication process is shown in Supplementary Fig. 5. To guarantee that the device is developed with no damage between individual layers during the fabrication process, this is confirmed by high-resolution transmission electron microscopy (HRTEM) with energy-dispersive X-ray spectroscopy (EDX) element mapping, which are shown in Fig. 1b and Supplementary Fig. 6, respectively. The TEM images indicate that the interfaces of all layers are sharp and clear, and it’s obvious that the MoS2 channel is a single layer. EDX analysis demonstrates that all elements are distributed uniformly and without interdiffusion. And the TEM image confirms the geometry of the MoS2 SGT, where the channel length (LCH) is 80 nm, and the external gate distance (d) is 50 nm.

Before further electrical investigation of the MoS2 SGT, a mechanism comparison between the SGT and conventional TFT was made to clarify that the SGT possesses better immunity to drain control. We compare the energy band diagram between SGT and conventional TFT in Fig. 1c. In the SGT, better immunity to drain electric field comes from two aspects: higher Φ and wider W, where Φ is the Schottky source barrier height and W is the channel potential barrier width without drain voltage influence, which are directly related to the source Schottky contact and source external gate, respectively. At the same drain voltage, the drain electric field will increase with the shortening of the channel length. Unlike the conventional TFT, where the channel barrier decreases dramatically due to the increase in drain field, the presence of the Schottky source and external gate in the SGT shields the effect of the drain electric field and thus better maintains the height of the channel barrier. More specifically, we analyzed the specific role of the source barrier and the external gate as VDS increases until the TFT saturates. The comparison between the proposed pinch-off mechanism and the conventional pinch-off mechanism is shown in Supplementary Fig. 7. For conventional TFTs, with increasing VDS, the carrier concentration at the drain terminal decreases until pinch-off, at which point, the IDS reaches saturation. For SGT, at small VDS, the source barrier is reversed to deplete carriers under the source, until all carriers induced by VGS are depleted, whereby the first depletion region occurs at the source, and VDSAT is defined28. As VDS increases, the excess VDS cannot affect the electric field of the depletion region under the source barrier in the presence of an external gate. But, instead expands the depletion envelope towards the drain direction and lowers the carrier density in the drain, like in the conventional TFT. Then the second depletion occurs at the drain with further increasing VDS. With both the source and drain depleted, a larger output resistance is expected in the SGT compared to the conventional TFT. TCAD (Sentaurus, Synopsys) simulations of the carrier concentration and electric field confirm the mechanism of device operation (see Supplementary Fig. 8 for details). In addition to simulation results, we compare the electrical performance of the SGT and conventional TFT (Supplementary Fig. 9). From the transfer curves in log-scale and linear-scale (Supplementary Fig. 9a, b), we can see that SGT exhibits larger VTH and lower IDS mainly due to the source barrier. The DIBL extracted from the zoom-in transfer curves in the subthreshold region shows a reduction in DIBL in SGTFT by 57% (from 16.7 to 7.3 mV/V). From the output curves in small and large VGS-VREF (Supplementary Fig. 9e, F), in which reference voltages (VREF) are chosen by the VGS at IDS = 10−10 A/μm, VGS equals 0 and −0.5 V for SGT and conventional TFT, respectively. And we can see the output curves are flatter in the SGT. More precisely, the extracted ROUT (Supplementary Fig. 9g) from Supplementary Fig. 9e is observed to be increased in SGTFT by about 25X at VGS-VREF = 0 V. Multiplied with the extracted transconductance (gm) in Supplementary Fig. 9d, the intrinsic gain as a function of VGS-VREF generated in Supplementary Fig. 9h is given by the following equation: Ai = gm × ROUT. Compared with conventional TFT, the Ai increased in SGT by about 17X at VGS-VREF = 0 V. Taken together, these experimental results also further confirm the mechanism. For SGT, the source/drain geometry asymmetry shows it can operate in two biasing configurations: the source-gated configuration and the drain-gated configuration as shown in Supplementary Fig. 10. From the comparison of the transfer curves and output curves corresponding to the two biasing configurations, we can see that in the drain-gated configuration, the device exhibit smaller output resistance, higher current and larger DIBL, which are mainly due to two aspects. On the one hand, the Schottky barrier is forward-biased to enlarge the carrier concentration under the drain. On the other hand, the drain external gate induces carriers in the region beneath the drain, which is quite different from the source external gate depleting carriers in the region beneath the source. Finally, we compare the low-frequency gain and operating frequency range (−3 dB bandwidth) performance of silicon metal oxide–semiconductor field-effect transistors (MOSFET), long channel SGT, short channel SGT, long channel TFT, and short channel TFT in Fig. 1d. We conclude that the short channel SGT is able to maintain high low-frequency gain over a wider operating frequency range, making it more favorable for its application in sensor-interface circuits.

Subthreshold performance trends with channel length scaling
To demonstrate the gain versus frequency of MoS2 SGTs operating in the subthreshold region as the channel length (LCH) decreases, we measured MoS2 SGT with different LCH from 1000 nm down to 200 nm. Figure 2a shows the corresponding transfer (IDS – VGS) characteristics, where IDS is the drain-to-source current, and VGS is the gate-source voltage. From the transfer curves, we can see that when LCH is scaled down from 1000 to 200 nm, the subthreshold characteristics of the MoS2 SGT remain almost unchanged while the on-state current slightly increases. We extracted the transconductance (gm) from the transfer curves at VGS = 0 V, which shows an increasing trend with LCH scaling, as shown in Fig. 2c. Figure 2b depicts the corresponding output (IDS – VDS) characteristics, where VDS is the drain-source voltage. The output curves are very flat in the saturation region, depicting a very large ROUT. We extracted ROUT from the output curves at VGS = 0 V. This is shown in Fig. 2d. The ROUT decreases as LCH scaled, and are all larger than 1011 Ω. Next, the intrinsic gain as a function of LCH is generated in Fig. 2e following the relation: Ai = gm × ROUT. It is observed that the Ai is maintained at a high value (about 3900) and does not degrade severely as LCH scaled. The Ai vs. LCH results prove that the SGT possesses a better immunity to short-channel effects and maintains very high output resistance (ROUT) and thus a high intrinsic gain. To comprehensively evaluate the Ai, we make a comparison of Ai vs. LCH between this work and different TFTs, including other 2D material TFTs16,29–31, metal oxide TFTs10,14,32, organic TFTs7,15,33,34 and Si MOSFET35,36 (see Supplementary Table 1 for details). It shows that the fabricated MoS2 SGT in this work has high Ai amongst the different TFTs despite the short LCH, demonstrating strong voltage amplification ability and the potential for sustained scaling. In addition to the intrinsic gain, the cut-off frequency (fT), i.e., the frequency where a TFT’s short circuit current gain drops to 1, can limit the actual gain bandwidth product of amplifiers19,29,37. To evaluate the frequency performance of the MoS2 SGT, we have conducted on-chip microwave measurements using an R&S vector network analyzer ZNL3 in the range of 5 kHz – 3 GHz. For frequency measurements, the MoS2 SGTs were fabricated on a highly resistive silicon substrate (>20 kΩ·cm) to minimize the parasitic capacitance. The small-signal current gain h21 extracted from the S-parameters measured at different LCH from 1000 nm down to 200 nm is shown in Fig. 2g. The DC bias of the VGS and VDS are 0.5 and 1.0 V, respectively, ensuring that the SGT operates in the subthreshold regime. The h21 decreases with frequency with a slope of −20 dB/decade, which is consistent with the frequency characteristics of traditional semiconductor TFTs38, and we can see that the fT increases as LCH decreases, and when LCH = 200 nm, fT equals 87 MHz. In addition to fT, the maximum oscillation frequency (fMAX), defined as the frequency at which the power gain is equal to one, is another important figure of merit defining the frequency performance of a TFT. Figure 2h illustrates the unilateral power gain U1/2 versus frequency for SGTs corresponding to Fig. 2g, and the maximum oscillation frequency (fMAX) equals 100 MHz at LCH = 200 nm. Further, by analyzing the relationship between fT and LCH, a 1/L2 dependence is observed in our devices (Fig. 2i), confirmed from the relation39,
fT = gm / (2π(Cgs + Cgd)) (1)
Here, gm is the transconductance, Cgs and Cgd are the gate-to-source and gate-to-drain capacitances, respectively. Equation (1) shows that the value of fT is proportional to gm/(Cgs + Cgd), as gm and Cgs + Cgd are proportional to W/L and W·L, respectively. Thus, fT would be independent of channel width, and the relationship between fT and L is 1/L2. We can see that when LCH is scaled down from 1000 nm to 200 nm, fT increases from 26 to 87 MHz, which is about 3.3 times larger. If we roughly estimate the frequency characteristics of SGT in a long channel (e.g., 10 μm) based on the 1/L2 correlation, it is about 2.3 MHz, which is 1/37 of that at 200 nm. This poor frequency characteristic of SGT is not conducive to high-frequency operation. Therefore, we need to shorten the LCH of the SGT in pursuit of a larger fT.

Subthreshold performance of 80 nm MoS2 SGT
Based on the above-subthreshold performance of SGTs, we observe that as the channel length decreases, the SGT can effectively suppress the short-channel effect without a significant decrease in the intrinsic gain, and we also observe that the frequency response significantly improves if the channel length is further shortened. As the next step, we further reduce the channel length of the SGT with the prospect of achieving high intrinsic gain and high frequency performance. We fabricated and measured ultra-scaled MoS2 SGT as shown in Fig. 1b with channel width/length (W/L) = 500/80 nm, and an external gate distance (d) of 50 nm. Figure 3a shows the transfer characteristics at different VDS (0.1, 0.7, and 1.0 V), and shows that the threshold voltage (VTH) is about 0.9 V based on a linear fit to the transfer curve at VDS = 0.1 V (Supplementary Fig. 11). Several interesting features were observed in the subthreshold region, including a small drain-induced-barrier-lowering (DIBL) effect. The DIBL was about 7.3 mV/V, calculated from the VREF shift from VDS = 0.1 V to VDS = 1.0 V. The subthreshold swing (SS) at VDS = 0.1 V was about 70 mV/dec, in which SS is extracted from over two decades of IDS. More importantly, a high transconductance efficiency (gm/IDS) is observed (Supplementary Fig. 12). This represents the efficiency of converting the bias current into an equivalent transconductance. In the subthreshold region, the highest gm/IDS was ~38 S/A, which approaches the theoretical limit of q/kBT (i.e., 38.7 S/A at T=300 K). Here, q is the elementary charge, kB the Boltzmann constant, and T the temperature. For analog TFT circuits, a high gm/IDS is essential for an amplifier circuit to reduce the power consumption without compromising its high-amplification performance. In addition to its good subthreshold characteristics, the ultra-scaled MoS2 SGT also exhibits low leakage current (IOFF < 10−12 A/μm), relatively large on-state current (ION > 10−4 A/μm) at VGS = 1.0 V, high on/off ratio of over 109, and a normalized gm of 171.8 μS/μm (Supplementary Fig. 12). Besides, nearly negligible hysteresis is observed, confirming the excellent interface quality (Supplementary Fig. 13). Consistent with the small DIBL in the transfer curves, we have also observed very flat saturation output curves measured at different VGS (from -0.2 V to 0.5 V, 0.1 V step) in Fig. 3b. The measured ROUT is above 108 Ω at VGS = 0.5 V. The extracted gm (black circles) and ROUT (blue circles) of the MoS2 SGT operating in the subthreshold region, are shown in Fig. 3c. The Ai calculated as a function of VGS is shown in Fig. 3d. The Ai of the MoS2 SGT remains almost bias independent when operating in the subthreshold region. Compared with TFTs of other 2D materials and oxides, and the Si-MOSFET, the Ai of the MoS2 SGT is much higher and at least two orders of magnitude higher than the Si-MOSFET at the commercial 65 nm technology node40. Further, in order to estimate the device uniformity, we measured 56 MoS2 SGTs with LCH = 80 nm (the transfer characteristics and statistical results are shown in Supplementary Fig. 14). Supplementary Fig. 14b shows that the subthreshold voltage (VTH) is uniformly distributed around 1.08 V, where VTH is extracted by linear extrapolation. Supplementary Fig. 14c shows over 96% (54 out of 56) of the devices with SS (over one decade of IDS) less than 100 mV/dec with ION of all devices over 10 μA/μm (Supplementary Fig. 14d). The above discussion clearly shows that good DC performance is achieved at LCH of 80 nm. To further evaluate the frequency performance, we measure the fT and fMAX using the aforementioned method. The small-signal current gain h21 and unilateral power gain U1/2 extracted from the S-parameters measured at different DC biases are shown in Fig. 3e, f, respectively. The DC bias of the VDS is fixed at 1.0 V, while the DC bias of VGS varies from 0.5 to 2 V in steps of 0.5 V. The relationships of fT and fMAX with VGS extracted from Fig. 3e, f are shown in Fig. 3g. We can see that in subthreshold operation (i.e., VGS = 0.5 V), the fT is 208 MHz and fMAX is 211 MHz. Although the SGT exhibits a lower fT than previously reported MoS2 transistors with comparable channel lengths that employed a top-gate structure optimized for high-frequency operation37, this behavior is inherent to its source barrier-controlled conduction mechanism and subthreshold operation of the SGT. The design intentionally prioritizes high intrinsic gain and low power consumption, as required for sensor-interface circuits in IoT applications, where weak analog signals require high-gain and low-power amplification over moderate bandwidths2. Nevertheless, future optimization, including shortening the source length, refining the gate-overlapped source region that controls the Schottky barrier injection41 (as detailed in Supplementary Fig. 15), and minimizing parasitic gate-to-source/drain overlaps without affecting the intrinsic SGT operation, could further enhance the high-frequency performance. In addition, although we can see that a better frequency response can be obtained by biasing the device in the above-subthreshold region, this obviously increases power consumption and reduces intrinsic gain. Equally important is the noise behavior since this determines the detection accuracy of the transistor amplifier circuit. We measured the noise current power spectral density of SGTs with different channel lengths operating in the subthreshold region, as shown in Fig. 3h. We find that the shorter the channel length, the higher the current noise at the same bias current (IDC = 100 nA). The extracted relation between the current noise and the channel length at a frequency of 100 Hz is shown in the inset of Fig. 3h. For the SGT with the shortest channel length (LCH = 80 nm), its current noise at different IDC in the subthreshold region (Fig. 3i) shows a relatively low current noise. This clearly favors the application of SGT in low-power amplification circuits.

High-gain and low-power amplifiers based on MoS2 SGTs
Based on the above measurement results, MoS2 SGTs operating in the subthreshold region have high intrinsic gain, excellent gm/IDS and good uniformity, indicating enormous potential for low-power, high-amplification applications. Based on this, we integrated MoS2 SGTs to realize a common-source amplifier circuit, which is known to be one of the most basic circuits in analog TFT circuits. As for n-type-only technology, there are two kinds of amplifier circuit configurations: enhancement–enhancement mode (EE) amplifier and enhancement-depletion mode (ED) amplifier. A comparison of the amplification performance of an amplifier based on these two different modes is given in Supplementary Fig. 16. The equivalent circuit diagrams are shown in Supplementary Fig. 16a and Fig. 16c, and the derived small-signal model results in Supplementary Fig. 16b, d. The small-signal voltage gain (Av = VOUT/VIN) of the enhancement-depletion mode amplifier (gm1(ROUT1 // ROUT2)) is obviously larger than that of the enhancement–enhancement mode amplifier (gm1/gm2). The experimental results in Supplementary Fig. 17 confirm this. Thus, to obtain a higher Av, the ED mode was selected for the connected configuration with MoS2 SGTFTs as the drive and load transistors to obtain higher ROUT simultaneously, and thereby higher gain. Figure 4a shows the equivalent circuit and optical image of an ED mode amplifier using two MoS2 SGTs with the same dimensions (W/L = 500/80 nm). The abrupt voltage transfer characteristic and high noise tolerance of the amplifier at VDD = 0.5 V are seen in Fig. 4b. The amplifier achieves full swing output, and its voltage transition occurs at 0.5 V with symmetric noise margin, low NML and high NMH. The total noise margin, defined as (NML + NMH)/VDD, reaches up to 80%. From the inset of Fig. 4b showing the power to ground current (IDD) at VDD = 0.5 V, and the peak IDD is ~0.34 nA. Figure 4c displays the amplifier’s gain of 249 V/V at VDD = 0.5 V, and the gain increases to 694 V/V, 1099 V/V and 1511 V/V at VDD = 1.0, 1.5, and 2.0 V, respectively (Supplementary Fig. 19). It is worth noting that in addition to high gain, this amplifier exhibits low power consumption (peak power ~0.17 nW) through the entire operation process at VDD = 0.5 V. Next, we measured amplifiers with MoS2 SGTs of different channel lengths (LCH = 200, 400, 1000 nm). We observe that they all exhibit high gain and low power consumption (<1 nW). Detailed results are presented in Supplementary Figs. 20–22. Besides, during the measurement process, we found that amplifier gain increases with decreasing the sweep step (Supplementary Fig. 23a–f). This observed increase with a smaller step size originates from the numerical differentiation process and reflects a purely mathematical convergence toward the intrinsic small-signal gain, rather than any physical trapping effect, as confirmed by the additional measurements showing that the gain is independent of the sweep speed (Supplementary Fig. 23h, i). We measured at a 0.5 mV step due to measurement noise limitation, but we suppose a higher gain can be measured with a smaller sweep step. Therefore, we attribute the high gain and low power consumption to transistors operating in the subthreshold region with relatively high gm and high ROUT, which are unique properties of MoS2 SGTs. And the gain and power comparison results between MoS2 SGTs and conventional TFTs confirm it (see Supplementary Figs. 17, 18 for details). With LCH scaling down from 1000 nm to 80 nm, the gain of the respective amplifiers at VDD = 1.0 V are summarized in Fig. 4d. We can see a slight decrease in gain as LCH decreases, although it still remains at a high level. Figure 4e benchmarks the Av as a function of channel length (LCH) for amplifiers based on 2D materials29–31,42–49, metal oxides50, Si51,52, and organics33 under VDD = 1.0 V to include more references (see Supplementary Table 2 for details). The gain outperforms the other amplifiers by at least one order of magnitude at similar LCH. With VDD scaled from 2 to 0.5 V, the gain of the corresponding amplifiers at LCH = 200 nm are summarized in Fig. 4f, and the relationship of gain with VDD is presented in Supplementary Fig. 20e. Figure 4g compares the power consumption of amplifiers based on 2D materials30,42,43,48,49,53, metal oxides10,47, Si51, and organics7,33,54 (see Supplementary Table 2). The MoS2 SGT amplifier reported here consumes lower power at smaller LCH, showing great promise for low-power applications. A comprehensive comparison with VDD, LCH, and Av (Supplementary Fig. 24), demonstrates that the results presented here achieve the optimal balance between low power consumption, high amplification gain and scalability.

Methods
Fabrication of MoS2 SGT
The fabrication process flow of MoS2 SGT is shown in Supplementary Fig. 5. Firstly, a 30 nm Mo gate metal was deposited by magnetron sputtering on 300 nm SiO2 grown on silicon substrates and then patterned by inductively coupled plasma (ICP) dry-etching process using SF6/C4F8 plasma. Then, a 6 nm HfO2 dielectric layer was deposited on the Mo gate electrode by ALD (BeneQ TFS 200) at 300 °C with tetrakis(ethylmethylamino)hafnium(IV) (TEMAH) and H2O as the Hf and O precursors, respectively. The growth rate of HfO2 at 300 °C is 0.76 Å per cycle. It was then patterned by the ICP dry-etching process using BCl3 plasma. After low-power O2-plasma treatment for 2 min, the CVD monolayer MoS2 was transferred onto the target substrate by using wet transfer methods and then patterned by reactive ion etching (RIE). Then, the drain contact was patterned by electron-beam lithography (EBL), and a bilayer metal stack of 20 nm/20 nm Ni/Au was deposited by electron-beam evaporation and lift-off. Next, a 1.6 nm Al seed layer was deposited by thermal evaporation. The Al layer was then oxidized in air to obtain a thin Al2O3 film, which promotes the nucleation of ALD Al2O3 for complete coverage of the MoS2. Subsequently, 5 nm Al2O3 was deposited by ALD process at 200 °C with trimethylaluminum (TMA) and H2O as the Al and O precursors. The growth rate of Al2O3 is 1.05 Å per cycle, and then patterned by EBL and etched by the wet-etching method using CD26 solution (alkaline developer). Finally, the source contact was patterned by EBL, and a bilayer metal stack of 20 nm/20 nm Pd/Au was deposited by electron-beam deposition and lift-off to complete fabrication of the MoS2 SGT.

Detailed monolayer MoS2 film deposition procedure
Monolayer MoS2 was purchased from SixCarbon Technology, Shenzhen. The growth of monolayer MoS2 was carried out using a typical chemical vapor deposition (CVD) process: MoO3 powder (99.999% purity) and sulfur powder (99.999% purity) as the sources of molybdenum and sulfur source, respectively. Using a dual-temperature zone tube furnace with a tube diameter of 80 mm, in which the MoO3 temperature is raised to 650 °C, the sulfur temperature is raised to 180 °C, and using argon gas as the growth carrier gas, a continuous monolayer of MoS2 on a silicon oxide substrate was achieved within 10 min sulfuration time at atmospheric pressure.

Transfer of monolayer MoS2
To fabricate the MoS2 SGT, the as-grown monolayer MoS2 film was transferred from the silicon oxide growth substrate to the HfO2/Mo/SiO2/Si substrate using a PMMA (polymethyl-methacrylate) assisted wet transfer process. Firstly, PMMA photoresist was spun onto the growth substrate at 4000 RPM for 60 s and allowed to sit overnight to ensure good PMMA/MoS2 adhesion. Second, the edges of the spin-coated film were then scratched using a razor blade and the substrate was immersed in deionized water at room temperature. The sample was then moved from the deionized water to obtain a monolayer of MoS2 with PMMA. Third, the monolayer MoS2 with PMMA was transferred to the target HfO2/Mo/SiO2/Si substrate. Finally, the PMMA photoresists were washed out in acetone and isopropanol successively.

MoS2 film characterization
Atomic force microscope (Bruker Multimode 8) is carried out for determining the thickness and roughness of a 0.8-nm monolayer MoS2 film. The measurement is performed in the “ScanAsyst in Air” mode with a scanning frequency of 0.7 Hz and the accuracy is about 512 lines/sample (scanning region is divided into 512 lines and 512 points are picked up in one line).

Device characterization
The cross-section transmission electron microscope (TEM) sample is fabricated by using an FEI Scios 2 dual-beam focused ion beam (FIB) system. A platinum layer is in situ deposited to protect the target region, and the surrounding area is then etched with a 30-kV acceleration voltage and a 7-nA ion beam to form the lamella. The lamella sample is transferred to a TEM grid in the FIB chamber. The TEM images are acquired by using a high-resolution spherical aberration correction transmission electron microscope (JEM ARM300F) with energy-dispersive X-ray spectroscopy (EDX) mappings. DC electrical characterization was carried out under a vacuum of about 1.3 × 10−3 mbar in the Lake Shore vacuum low-temperature probe station and using a Keithley 4200A Parameter Analyzer. The AC performance of our devices was analyzed in terms of S-parameters, from which the current gain (h21) and power gain (Gmax) were calculated. fT was defined as the frequency at which h21 reached unity (0 dB), while fMAX was defined as the frequency at which Gmax reached 0 dB. A probe station (Cascade Summit 1100), semiconductor analyzer (Agilent B1500), ground-signal-ground (GSG) probes, coaxial cables and vector network analyzer (Agilent N5247B) were used to measure the performance of the MoS2 SGT. First, the GSG probes and coaxial RF cables were calibrated using the off-wafer short-open-load-through (SOLT) standard procedure. The semiconductor analyzer was used to provide DC bias, including VGS and VDS for MoS2 SGT. The gate and drain were defined as ports “1” and port “2”, respectively, and then two-port S-parameters (S11, S12, S21, S22) were measured using the VNA.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "In the manuscript ‘Subthreshold Schottky-Barrier Transistor Based on Monolayer Molybdenum Disulfide’ by M. Liu, et al., CVD MoS2-based source-gated transistor is demonstrated. The device here realizes high intrinsic gain based on good saturation behavior in SGT architecture and stable subthreshold operation with minimal DIBL, showing high immunity against short-channel effect. With the SGT the authors achieved high cut-off frequency about 200 MHz and high gain amplifier. The contents in this study seems meaningful as it achieved good performance with architecture engineering on 2D materials and demonstrated several practical circuits with SGT devices, showing that the progress in the study can have significant impact in 2D electronic device area. However, there is lack of the evidences proving the operation mechanism is truly SGT one and there are several points which should be reconsidered to clarify the operation mechanism of the MoS2 SGT. Therefore, I recommend the manuscript to be published in Nature Communications after revision regarding the following questions. Q1. In the manuscript and figure S6, the authors explain the saturation mechanism in SGT. But, it is vague which the saturation voltage VDSAT is for SGT. In figure S6, VDSAT for SGT is expressed as the voltage where the second pinch-off at drain happens. Basically, the saturation mechanism in SGT is the depletion of the carriers under source region. And the actual output saturation appears when the primary pinch-off at source terminal side happens. Even with further increase in VDS doesn’t increase the drain current because the current is self-consistently maintained by the reduced carrier concentration from the extension of depletion and the increase in lateral field. In that manner, it would be more appropriate to say VDSAT as the primary pinch-off point in case of SGT. Q2. In figure S6, why there is dip in carrier concentration under source electrode, I mean, why is the carrier concentration at the source edge is higher than that inside channel? The primary pinch-off in SGT occurs near the source edge. (F. Balon and J. M. Shannon 2005 J. Electrochem. Soc. 152 G674) Q3. In the manuscript page 8 line 332, the authors mentioned the variation in the measured gain value depending on the sweep step. Here, have the authors tried varying sweep speed without change in sweep step? If it also depends on the sweep speed, it can be related to the interface trap. Then, the subthreshold swing and subthreshold voltage can be significantly affected by the sweep speed or step. In that case, the measurement condition should be constantly maintained for all measurement or should be noted. Is hysteresis not significant in transfer curve? Q4. There is typo in page 9 line 345. The relationship of gain with VDD is presented in Figure S19h, not S17h. Q5. Regarding the operation mechanism of SGT, the saturation voltage has the following VG dependence. (∆V_DSAT)/(∆V_G )=C_i/(C_i+C_s ) , where Ci and Cs are insulator and semiconductor capacitance, respectively (J. M. Shannon and E. G. Gerstner, Solid-State Electronics, 48, 7 (2004) 1155-1161). Because the device in this study is using monolayer MoS2, Cs is huge and VDSAT should be almost constant or should have only week dependence on VG. To see if it is operating as SGT, it should be checked. Is that feature observed? If not, what is the reason? In addition, different to the saturation current in conventional FET which has quadratic dependency in VG, the saturation current in SGT increases exponentially as a function of VG as it is limited by source current density with Schottky emission. Does this device also show this characteristics? The quality of the data - Very good. The level of support for the conclusions – Moderate. The potential significance of the results – Good.", "reviewer_2": "This paper presents a comprehensive analysis of a high-performance MoS₂ Schottky-gated transistor (SGT) designed for high-gain, high-frequency, and ultra-low-power applications. The study demonstrates that the proposed MoS₂ SGT exhibits high output resistance, enabling superior gain characteristics for amplifier applications. Additionally, by successfully scaling the channel length down to 80 nm, the manuscript highlights its potential for high-frequency operation. Then the authors introduce an enhancement-depletion mode amplifier that operates in the subthreshold region, achieving a combination of high gain and low power consumption. Major comments 1. Compared to conventional MoS₂-based transistors which has 90 nm channel length [1], the proposed SGT exhibits a lower cut-off frequency at the same channel length. Is this characteristic inherent to the SGT structure? If so, the manuscript should explain why the SGT has a lower cut-off frequency despite having a similar channel length. 2. High output resistance enhances the gain of an amplifier but comes with a trade-off of reduced voltage headroom. What is the voltage headroom proposed in this manuscript? 3. On page 8, line 38th and Figure S20, what is the reason for the significantly high measured amplifier gain when using a small voltage sweep step? Can the higher measured gain, obtained by minimizing the sweep step, truly be considered an intrinsic characteristic of this amplifier? Could the amplifier's characteristics be distorted due to trap charging effects as the sweep is performed more slowly? 4. There is no graphical representation illustrating the RF transistor’s GSG configuration and key device parameters such as source length, contact length, and contact width. A precise indication of its value is necessary. Including a detailed diagram would enhance understanding of the device structure. 5. According to the previous paper on SGTs, the source length (D) is a significant factor affecting cut-off frequency [2], but there is no clear specification of the RF transistors’ source length in Fig.2 and Fig 3. Was an optimization process conducted for the source length to maximize the cut-off frequency? If so, including the relevant data would enhance the clarity and completeness of the manuscript. 6. Benchmark figures, such as Fig. 2f, 3d, 4e, 4g, and S21, lack references for the benchmark data. Providing specific references next to the symbol would improve clarity. In particular, for the Si benchmark, it is essential to specify the technology node and the name of the foundry company. 7. The amplifier already demonstrates excellent performance, but the paper would be more meaningful if the advantages of the amplifier, constructed with transistors having a MHz-level cutoff frequency as proposed in the study, were visualized in a specific application unit. [1] Gao, Q. et al. Scalable high performance radio frequency electronics based on large domain bilayer MoS2. Nat Commun 9, 4778 (2018). [2] Sporea, R. A., Shannon, J. M., Silva, S. R. P., Trainor, M. J. & Young, N. D. Performance trade-offs in polysilicon source-gated transistors. in 2010 Proceedings of the European Solid State Device Research Conference 222–225 (IEEE, Sevilla, Spain, 2010). doi:10.1109/ESSDERC.2010.5618382. Minor errors 1. In Figure 1a, the unit on the left y-axis appears to be incorrect. There is a discrepancy with the right y-axis unit, and it should be expressed as A/μm. 2. On page 9, line 36, the manuscript states that the Mo etch process uses SF₆/C₃H₈ plasma. However, since C₃H₈ (propane) is not commonly used for Mo etching, could you verify if this might be a typo and should instead be C₄H₈? 3. On page 9, there are inconsistencies in the way thickness units are expressed (e.g., gate metal (30 nm Mo), 300 nm SiO₂, Ni (20 nm), Au (20 nm), source metal (20 nm Pd/20 nm Au)). For clarity and consistency, please standardize the formatting of these unit expressions. 4. In Figure S15, both the solid and dashed orange lines appear ambiguous in their purpose. If they are not essential, removing them would improve clarity. 5. In Figure S15, the abbreviations SSG and REF are not explained. Their meanings should be clarified in the figure caption for better understanding. 6. In Figure S16, the caption presents the figures in an inconsistent order, which may hinder comprehension. To improve clarity, the descriptions should follow a logical sequence. 7. Is there a specific reason why the y-axis in Fig. S9-c is labeled as (A/μm) while in Fig. S9-d it is (μA/μm)? If not, it would be better to unify the units for consistency. 8. In Fig. S9-c, d, the text “This work” appears in the figure. Since this is not a benchmark figure, the label is unnecessary and should be removed. 9. On page 2, lines 14, 15 and 21, and page 8, line 17, you labeled the output resistance as ro, but used ROUT in all subsequent notations. It would be better to use ROUT for everything. Similarly, on page 2, line 15, it would be better to use '×' instead of '·' in the expression related to Ai, and to unify the spacing between '×' and gm, ROUT in the rest of the expression. 10. On page 2, line 25, you wrote “sub-threshold” but used “subthreshold” in all subsequent notations. It would be better to use “subthreshold” throughout. Similarly, all the rest are labeled as 'cut-off frequency', but only page 9 is labeled as 'cutoff frequency'. Uniformity is needed. 11. On page 3, lines 20 and 23, and page 9, line 25, you wrote “ultralow”, but all other notations used “ultra-short”, “ultra-low”, “ultra-scaled”, and “ultra-high”. It would be better to write “ultra-low”. 12. On page 6, line 27, you used the expression '1/37th of that at 200 nm', which is not grammatically natural. Consider changing it to '1/37 of that at 200 nm'. 13. Expressions with numbers and equal/unequal signs are not uniformly spaced. The problem is found on lines 15, 26, and 27 on page 2; lines 8 and 18 on page 3; lines 2, 4 and 5 on page 5; line 6 on page 6; lines 2, 8, 13, and 44 on page 7; lines 3, 16, 23, and 34 on page 8; and lines 1, 4, and 19 on page 9. The space after the subscript is also included in the issue since it looks small. 14. On page 3, lines 24 and 25; page 4, line 8; page 5, lines 26 and 42; page 6, line 36; page 7, lines 18 and 22 and page 11, lines 13 and 16, the space after MoS2 appears to be missing because it is after a subscript. It would be nice to have a clear space. 15. On page 9, line 2, the v in AV is lowercase. The rest of the notation is all capitalized and needs to be corrected. 16. On page 2, lines 8 and 15; page 6, line 26; page 7, lines 12, 26, and 34; page 8, lines 24 and 28, numbers and units are written without space. All the rest of the notation is with spaces, so you need to change the notation to one with spaces. 17. Page 4, line 4; page 5, lines 3 and 35; page 9, lines 1, 2, 7, and 8; page 17, line 7 needs to be fixed for spacing. The format Fig. (number)(alphabet) seems appropriate. 18. Overall, the supplemental figure notation is not unified. A choice between ‘Fig. S(number) (alphabet)’ and ‘Fig. S(number)(alphabet)’ seems to be needed. 19. On page 7, line 35, “Fig. 3e and f” should be bolded; it would be better if it modifies to “Fig. 3e and Fig. 3f”. 20. Page 8, line 36, and page 9, line 8 both omit the dot after Fig. The dot after 3c on page 7, line 19 has been bolded. The figure descriptions on pages 15 and 16 have “,” after the alphabet, and the figure descriptions on pages 17 and 18 have “.” after the alphabet. All these need to be corrected and purged. 21. On page 1, line 30; page 3, line 20, and page 9, line 25, “volt” and “nanowatt” are used. V and nW are more consistent and look better. 22. On page 18, Fig. 4f is labeled LCH = 200 nm, but the corresponding description states LCH = 80 nm. Accurate descriptions and labeling are essential.", "reviewer_3": "This manuscript reports a significant advancement in the field of thin-film transistors by demonstrating a high-frequency, subthreshold-operating source-gated transistor (SGT) based on monolayer molybdenum disulfide (MoS₂).The authors have achieved an impressive cutoff frequency of 208 MHz in an 80 nm channel-length device, which is a major breakthrough considering the historical limitations of SGTs to low operating frequencies(typically in the kHz range).This achievement not only shatters previous frequency limitations but also highlights the potential of MoS₂ SGTs for high-speed applications. The reproducibility of the fabrication process is further evidenced by the consistent performance across 56 measured devices, indicating robustness and scalability. Given these outstanding results, I strongly support the publication of this manuscript in Nature Communications. With minor revisions addressing the specific questions raised below, I believe this paper is well-suited for acceptance. 1. The manuscript mentions that metal Ni and Pd form ohmic and Schottky contacts with MoS₂, respectively. It would be beneficial to include measurements of the Schottky barrier heights and contact resistances for these configurations to further validate the contact properties. 2. Hysteresis behavior is crucial for understanding the stability and reliability of the transistor. Could the authors provide detailed double-sweep transfer curve data to illustrate the hysteresis behavior of their devices? 3. Clean interfaces are vital for transistor performance. The TEM image of the transistor structure in Fig. 1 is rather blurry, which does not allow for clear observation of the interfaces. Could the authors supplement high-resolution TEM images, particularly magnified views of the Ni-MoS₂ contact, Pd-MoS₂ contact, and the interface between MoS₂ and the gate stack? 4. The measured cutoff frequency of 208 MHz is impressive for an 80 nm channel length. However, the source electrode in SGTs typically covers a portion of the channel and has significant overlap with the bottom gate, increasing parasitic capacitance. Could the authors address this issue? Would it be possible to fabricate a local top-gate transistor to achieve similar performance while mitigating this parasitic effect? 5. The concept of pinch-off, originally proposed for silicon MOSFETs, may not be directly applicable to MoS₂ SGTs, which are n-type semiconductors and do not easily transition to inversion. Could the authors provide an explanation and discussion on the applicability of this concept to their MoS₂ SGTs? 6. The gain-input voltage (AV-VIN) curve in Fig. 4 would be more intuitive if presented on a logarithmic scale for the y-axis. This would allow for a clearer judgment of the gain magnitude. Could the authors consider this change? 7. The absolute units of the y-axis variables in Fig. 3c and 3d may not be helpful for readers to judge their magnitudes. Could the authors consider normalizing these variables for better clarity? 8. In Fig. S17 and S19, there are noticeable fluctuations in the VIN-IDD and VIN-Power curves around VIN=0.15-0.2 V. Could the authors explain the reason for these fluctuations?"}, "author_response": "General Response: We greatly appreciate the reviewer’s positive and encouraging comment recognizing that our work “… realizes high intrinsic gain based on good saturation behavior … and stable subthreshold operation with minimal DIBL, showing high immunity against short-channel effect … seems meaningful as it achieved good performance with architecture engineering on 2D materials and demonstrated several practical circuits… the progress in the study can have significant impact in 2D electronic device area”. Below, we provide point-by-point responses to all the questions and concerns raised. Comment 1: In the manuscript and figure S6, the authors explain the saturation mechanism in SGT. But, it is vague which the saturation voltage VDSAT is for SGT. In figure S6, VDSAT for SGT is expressed as the voltage where the second pinch-off at drain happens. Basically, the saturation mechanism in SGT is the depletion of the carriers under source region. And the actual output saturation appears when the primary pinch-off at source terminal side happens. Even with further increase in VDS doesn’t increase the drain current because the current is self-consistently maintained by the reduced carrier concentration from the extension of depletion and the increase in lateral field. In that manner, it would be more appropriate to say VDSAT as the primary pinch-off point in case of SGT. Response 1: We greatly appreciate the reviewer’s instructive suggestion. We fully agree that the drain-current saturation in SGTs is determined by the primary pinch-off beneath the source barrier, as originally described by Shannon in the first SGT publication [R1]. Following the reviewer’s suggestion, we have redefined the V for SGT as the primary pinch- DSAT off point under source region in the Fig. S7 of the revised supplementary information and also in Fig. R1 below. In this work, for our ultra-short-channel (80 nm) MoS SGTs, this source-barrier-limited saturation 2 still governs the output characteristics. As the V increases, due to the extremely short channel and DS accompanying high drain electric field, the residual drain field cannot fully be screened by the source barrier. Consequently, the depletion envelope extends slightly toward the drain side at higher V , similar to that in conventional TFT, as clearly supported by our TCAD simulation results in DS Fig. S8. Importantly, this secondary depletion does not redefine V ; rather, it provides a more DSAT complete and realistic explanation of the saturate mechanism in short-channel SGTs. In other words, source-side pinch-off saturation remains the primary cause of saturation, while drain-side depletion represents a scaling-induced extension of the depletion region, occurring almost simultaneously in our short-channel devices and appearing as a single smooth saturation transition. TCAD simulations further confirm the coexistence of both depletion regions, verifying that the dual-depletion mechanism remains valid even though the two pinch-off processes cannot be distinctly resolved in the electrical characteristics. With both the source and drain partially depleted, the output resistance becomes larger than that of a conventional TFT, consistent with our experimental observations. Reference: [R1] Shannon, J. M. & Gerstner, E. G. Source-gated thin-film transistors. IEEE Electron Device Lett. 24, 405-407, doi:10.1109/LED.2003.813379 (2003). Revision for Comment 1: Following the reviewer’s comments, we modified the V for SGT as DSAT the primary pinch-off point under source region in the Fig. S7 of the revised supplementary information and the revised manuscript in Page 4, Line 26, which we have highlighted. Comment 2: In figure S6, why there is dip in carrier concentration under source electrode, I mean, why is the carrier concentration at the source edge is higher than that inside channel? The primary pinch-off in SGT occurs near the source edge. (F. Balon and J. M. Shannon 2005 J. Electrochem. Soc. 152 G674) Response 2: We greatly appreciate the reviewer’s insightful comment and for pointing out the reference by F. Balon and J. M. Shannon [R2]. After carefully re-examining both our simulation results (Figure S8) and the schematic illustration in Figure S7, we found that the original schematic was not accurately consistent with the simulated carrier distribution. In fact, during the primary pinch-off at the source edge, the carrier concentration near the source indeed becomes lower than that inside the channel, which agrees well with the behavior described in the cited literature. We have corrected the schematic in the above supplied Figure R1, and the corresponding Figure S7 in the supplementary information has also been updated accordingly and cited the reference (F. Balon and J. M. Shannon, J. Electrochem. Soc., 2005, 152, G674) in the revised manuscript. Revision for Comment 2: Following the reviewer’s comments, we corrected the Fig. S7 in the revised supplementary information and we cited the reference (F. Balon and J. M. Shannon, J. Electrochem. Soc., 2005, 152, G674) in the revised manuscript in Page 4, Line 26, which we have highlighted. Reference: [R2] Balon, F. & Shannon, J. M. Modeling of Source-Gated Transistors in Amorphous Silicon. Journal of The Electrochemical Society 152, G674, doi:10.1149/1.1946507 (2005). Comment 3: In the manuscript page 8 line 332, the authors mentioned the variation in the measured gain value depending on the sweep step. Here, have the authors tried varying sweep speed without change in sweep step? If it also depends on the sweep speed, it can be related to the interface trap. Then, the subthreshold swing and subthreshold voltage can be significantly affected by the sweep speed or step. In that case, the measurement condition should be constantly maintained for all measurement or should be noted. Is hysteresis not significant in transfer curve? Response 3: We appreciate the reviewer’s valuable comment. For the observed variation in the measured gain with sweep step, we have verified that the gain shows negligible dependence on sweep speed. Specifically, measurements performed at sweep rates of approximately 1, 10, and 50 mV/s (with a fixed voltage step of 1 mV) yielded nearly identical gain values (as shown in the Fig. R2a-b). In addition, the transfer characteristics exhibit negligible hysteresis (only ~46 mV, as shown in the Fig. R2c), further confirming that interface traps do not affect the extracted results. We note that all electrical measurements in this study were conducted under a constant sweep rate (~10 mV/s), while only the voltage step was varied to verify the numerical convergence of the extracted gain. Therefore, the sweep speed does not influence the behavior. The apparent increase in gain with smaller voltage steps arises from the numerical differentiation process: as ΔV → 0, the computed slope dV /dV approaches the true small- IN OUT IN signal (intrinsic) gain, whereas larger steps average over local nonlinearities and underestimate the peak slope. The use of fine voltage steps to accurately capture intrinsic gain behavior is a well-established practice in previous studies [R3, R4]. Reference: [R3] Luo, Z. et al. Sub-thermionic, ultra-high-gain organic transistors and circuits. Nature Communications 12, 1928, doi:10.1038/s41467-021-22192-2 (2021). [R4] Tang, J. et al. Low power flexible monolayer MoS2 integrated circuits. Nature Communications 14, 3633, doi:10.1038/s41467-023-39390-9 (2023). Revision for Comment 3: Following the reviewer’s comments, we have added some discussion clarifying that the amplifier gain does not depend on the sweep speed in the revised manuscript in Page 9, Line 2, and the corresponding figures are incorporated in Fig. S23 of the revised supplementary information, which we have highlighted. In addition, the discussion of the SGT hysteresis characteristic has been incorporated in the revised manuscript in Page 7, Line 12, which we have highlighted. And the hysteresis behavior has been incorporated in newly-added Fig. S13 in the revised supplementary information, which we have highlighted. Comment 4: There is typo in page 9 line 345. The relationship of gain with VDD is presented in Figure S19h, not S17h. Response 4: Thanks for the kind suggestion. We are very sorry that we made such a mistake because of our negligence. Revision for Comment 4: Following the reviewer’s comment, we have now corrected this error in Page 9, Line 22 in the manuscript, which we have highlighted. Comment 5: Regarding the operation mechanism of SGT, the saturation voltage has the following VG dependence. (∆V )/(∆V )=C/(C+C), where Ci and Cs are insulator and semiconductor capacitance, DSAT G i i s respectively (J. M. Shannon and E. G. Gerstner, Solid-State Electronics, 48, 7 (2004) 1155-1161). Because the device in this study is using monolayer MoS2, Cs is huge and VDSAT should be almost constant or should have only week dependence on VG. To see if it is operating as SGT, it should be checked. Is that feature observed? If not, what is the reason? In addition, different to the saturation current in conventional FET which has quadratic dependency in VG, the saturation current in SGT increases exponentially as a function of VG as it is limited by source current density with Schottky emission. Does this device also show this characteristics? Response 5: We greatly appreciate the reviewer’s instructive suggestion. (1). V dependence of V : According to Shannon’s model [R5], the V dependence of V G DSAT G DSAT follows: (∆V )/(∆V ) = C/(C+C ), where C and C are insulator and semiconductor capacitance, DSAT G i i S i S respectively. In an ideal SGT with a very large C , V should be nearly constant or show only S DSAT week dependence on V . G To verify this, we compared the output characteristics of the MoS SGT and a conventional MoS 2 2 TFT with 80 nm channel-length (Fig. S9 in the supplementary information), as shown in below Fig. R3. The results indicate that V in the SGT is not perfectly constant but exhibits only a weak DSAT dependence on V , in sharp contrast to the strong dependence observed in the TFT. The difference GS between the two devices is modest in the subthreshold regime but becomes pronounced in the on- state, where the SGT maintains a much lower gate-dependent V . DSAT This behavior can be explained by follows: In the subthreshold regime, the semiconductor capacitance C of monolayer MoS is relatively small due to low carrier density [R6], making it S 2 comparable to C; hence, V still shows a minor gate dependence, though weaker than in the TFT. i DSAT In the on-state, C becomes very large owing to the high carrier density, leading to a only week S dependence on V and a markedly lower V . Besides, for ultra-short-channel devices, the G DSAT stronger drain electric field can partial penetrate beneath the source deplete region and introduce slight deviation from ideal SGT behavior. Therefore, although V is not completely constant, its DSAT much weaker gate dependence and lower saturation voltage compared with the TFT confirm the SGT operation mechanism of the MoS SGT. 2 (2). V dependence of I : To verify whether the SGT device follows the exponential dependence G DSAT of the saturation current (I ) on gate voltage (V ) as expected for Schottky emission–limited DSAT GS transport, the I was extracted from the output characteristics (Fig. 3b in the manuscript) at DSAT different V values (Fig. R4 a,b). As shown in Fig. R4c, the plot of Ln (I ) versus V exhibits GS DSAT GS an excellent linear relationship (R2≈0.97), indicating that I increases exponentially with V . DSAT GS This behavior confirms that the drain-current saturation in our MoS SGT is governed by the source 2 Schottky barrier–limited emission transport, consistent with the characteristic mechanism of SGTs. General Response: We greatly appreciate the reviewer’s positive and encouraging comments on the performance and application potential of our MoS source-gated transistor for high-gain, high- 2 frequency, and low-power operation. Below, we provide point-by-point responses to all the questions and suggestions raised. Comment 1: Compared to conventional MoS₂-based transistors which has 90 nm channel length [1], the proposed SGT exhibits a lower cut-off frequency at the same channel length. Is this characteristic inherent to the SGT structure? If so, the manuscript should explain why the SGT has a lower cut-off frequency despite having a similar channel length. Response 1: We thank the reviewer for this insightful question. The relatively lower cut-off frequency (f ) observed in our device is indeed inherent to both the T source-gated transistor (SGT) architecture and its intended subthreshold operation mode. (1). Current mechanism: In an SGT, the drain current is mainly dominated by the source barrier height controlled by the gate voltage (V ), and is almost unaffected by the drain terminal, resulting GS in high output resistance (R ) and high intrinsic gain (A). In contrast, in conventional transistors, OUT i the drain current is jointly controlled by the gate-induced channel carrier density and the carrier drift driven by the drain-to-source electric field (V ). As a result, this source-barrier-controlled DS mechanism inherently results in a lower transconductance (gₘ). (2). Operating region: In addition, to achieve ultra-low-power operation, as typically required in senor interfaces applications, the proposed MoS SGT is intentionally biased in the subthreshold 2 regime, where both g and current are intrinsically smaller. This naturally results in a lower f m T compared to conventional transistors of similar channel length. (3). Design objective: Nevertheless, this trade-off is fully consistent with the design objective of the SGT, which emphasizes high intrinsic gain and ultra-low power consumption rather than extreme frequency performance. Such characteristics are particularly desirable for sensor-interface circuits in Internet-of-Things (IoT) applications, where weak analog signals require high-gain and low-power amplification over moderate bandwidths [R7]. In contrast, conventional high-frequency transistors typically enhance f through aggressive channel-length scaling or self-aligned top-gate T structures [R8, R9, R10], which degrade intrinsic gain due to aggravated short-channel effects (SCEs). Reference: [R7] Luo, Y. et al. Technology Roadmap for Flexible Sensors. ACS Nano 17, 5211-5295, doi:10.1021/acsnano.2c12606 (2023). [R8] Liao, L. et al. High-speed graphene transistors with a self-aligned nanowire gate. Nature 467, 305–308 (2010). [R9] Shi, H. et al. Radiofrequency transistors based on aligned carbon nanotube arrays. Nat. Electron. 4, 405–415 (2021). [R10] Gao, Q. et al. Scalable high performance radio frequency electronics based on large domain bilayer MoS2. Nat Commun 9, 4778 (2018). Revision for Comment 1: The explanation for why the SGT exhibits a lower cut-off frequency than conventional transistors, despite having a similar channel length, has been added in the revised version in Page 7, Line 37. Comment 2: High output resistance enhances the gain of an amplifier but comes with a trade-off of reduced voltage headroom. What is the voltage headroom proposed in this manuscript? Response 2: We appreciate the reviewer’s insightful comment. The voltage headroom is defined as the available output-voltage swing around the quiescent (Q) point, within which both the load and drive transistors remain in their saturation regions at the chosen power supply voltage (V ) [R11]. The Q-point corresponds to the DC operating point of DD the amplifier, typically chosen to maximize the small-signal gain and ensure a symmetric output swing. The trade-off between gain and voltage headroom is well recognized in conventional amplifier design, where high output resistance (R ) is typically achieved by cascoding or stacking OUT transistors [R12], which inherently limits the available voltage swing. In contrast, in the proposed SGT, a Schottky barrier is introduced between the source contact and the semiconductor, so that the drain current (I ) is primarily governed by the gate-controlled source barrier height and is almost DS independent of the drain potential. This mechanism enables high output resistance without the need for circuit-level stacking. Consequently, the required saturation voltage is significantly reduced, allowing the device to maintain a larger effective voltage headroom under the same supply voltage. Regarding the voltage headroom of the amplifier in Fig. 4b of the manuscript, the load transistor is configured with its gate shorted to source (V = 0 V), behaving as a weak current source operating GS in the subthreshold regime. In this configuration, the upper output limit is essentially defined by V -(3~4)V (≈0.1V at 300 K, where V =kT/q is the thermal voltage) [R12], which ensures that DD T T the load transistor remains in subthreshold saturation. Although this definition was originally derived for conventional Si MOSFETs, it can be reasonably applied here to estimate the upper voltage limit for the MoS subthreshold transistor operating in the saturation regime. The lower 2 output limit is determined by the V of the bottom drive transistor at the actual bias. We evaluate DSAT V at the actual amplifier bias, i.e. V = V used for gain measurements. Here, V DSAT GS,Q IN,Q GS,Q represents the quiescent operating point where the amplifier gain is maximized. Practically, V DSAT (@V ) is extracted from the I -V curve at V = V ≈ 0.3 V (Fig.R5) to obtain a rough GS,Q DS DS GS IN,Q estimate. The extracted V (@V =0.3 V) ≈ 0.17 V, leading to a voltage headroom of DSAT GS,Q approximately V - 0.1-V = 0.5 - 0.1 - 0.17 = 0.23 V. DD DSAT The wide effective headroom at ultra-low supply voltage of 0.5 V is consistent with the observed high gain and large noise margin, and shows the potential of implementing the SGT in low-power applications. Comment 3: On page 8, line 38th and Figure S20, what is the reason for the significantly high measured amplifier gain when using a small voltage sweep step? Can the higher measured gain, obtained by minimizing the sweep step, truly be considered an intrinsic characteristic of this amplifier? Could the amplifier's characteristics be distorted due to trap charging effects as the sweep is performed more slowly? Response 3: We thank the reviewer for this insightful question. The higher measured gain obtained with smaller voltage sweep steps does not originate from trap- related charging or slow transient effects but from the improved numerical precision of the differentiation process used to extract the gain. As the voltage step ΔV decreases, the computed IN slope dV /dV more closely approaches the true small-signal gain, whereas larger steps average OUT IN over local nonlinearities, leading to an apparent reduction in the extracted value. The use of fine voltage steps to ensure accurate numerical differentiation is a well-established practice in the literature for high-gain amplifier application [R3, R4]. To verify that the result is not influenced by sweep speed, we performed measurements at different sweep speeds (1, 10, and 50 mV/s) while keeping the voltage step fixed at 1 mV. As shown in Fig. R6 a,b, the extracted gain remains nearly unchanged, indicating that the device performance is independent of sweep rate and that trap-related hysteresis effects are negligible. Revision for Comment 3: Following the reviewer’s comments, we have added some discussion clarifying that the amplifier gain does not depend on the sweep speed in the revised manuscript in Page 9, Line 2, and the corresponding figures are incorporated in Fig. S23 of the revised supplementary information, which we have highlighted. Comment 4: There is no graphical representation illustrating the RF transistor’s GSG configuration and key device parameters such as source length, contact length, and contact width. A precise indication of its value is necessary. Including a detailed diagram would enhance understanding of the device structure. Response 4: We thank the reviewer for this kind suggestion. The device structure is illustrated in Fig.R7 below. Fig.R7a shows the schematic image of the MoS 2 SGT structure, where the source length and contact length are indicated. The source length (S) refers to the gate-overlapped portion of the source that controls the Schottky barrier injection [R13]. The contact length (L ) generally refers to the metal-channel overlap length along the current-flow C direction [R14], while the contact width generally refers to the metal-channel overlap width perpendicular to the current-flow direction. It should be noted that, for illustrative purposes, the schematic diagram is not necessarily drawn to scale with the actual device dimensions. Fig.R7b presents the top-view layout of the fabricated MoS SGT used for RF measurements. The RF 2 measurements were performed using a ground-signal-ground (GSG) two-port configuration, where the small-signal input was applied to the gate through port 1, and the amplified signal was measured at the drain through port 2. As an example, for the SGT with a channel length of 80 nm, the device parameters are: source length = 1.46 µm, contact length = 2.46 µm and contact width = 10 µm. In detail, the source length (S) can be approximately estimated as (L -L )/2, where gate length L = 3 µm; and the contact length (L ) G CH G C can be approximately estimated as (L - L )/2, where semiconductor length L Semiconductor CH Semiconductor = 5 µm. The above parameters may slightly deviate due to lithography alignment and process variations, but the overall estimation remains reasonable. Revision for Comment 4: Following the reviewer’s comments, a graphical representation illustrating the RF transistor’s GSG configuration and key device parameters has been added as Fig. S15 in the revised supplementary information, which has been highlighted. Comment 5: According to the previous paper on SGTs, the source length (D) is a significant factor affecting cut-off frequency [2], but there is no clear specification of the RF transistors’ source length in Fig.2 and Fig 3. Was an optimization process conducted for the source length to maximize the cut-off frequency? If so, including the relevant data would enhance the clarity and completeness of the manuscript. Response 5: We appreciate the reviewer’s insightful comment. As reported in previous works on SGTs [R13, R15, R16], including the one cited by the reviewer, the source length (denoted as D in the reviewer’s comment, corresponding to S in [R13]) refers to the gate-overlapped portion of the source that controls the Schottky barrier injection. In this study, due to the lack of an effective channel doping technique, such as that used for polysilicon in previous report [R13], the source and drain in our MoS SGT inevitably overlap with 2 the gate to ensure effective contact with the MoS channel. The device schematic is shown in Fig. 2 R8 below, where the source length (S) is highlighted in red for clarity. The original schematic was overly idealized and did not illustrate this overlap; therefore, we have replaced it with a revised version in Fig. 1a of the manuscript to more accurately represent the actual device structure. During the device fabrication process, three electron-beam lithography (EBL) steps were sequentially performed to precisely define the drain pattern, the Al O etching pattern (used for 2 3 forming the external gate), and the source pattern, thereby realizing short-channel SGT devices with channel lengths (L ) scaled down from 1 μm to 80 nm (detailed fabrication procedures are provided CH in supplementary information S5). Because the EBL process is complex and time-consuming, ultraviolet (UV) lithography was employed for gate definition, resulting in a relatively long gate length (L ) of approximately 3 μm. Therefore, the source length (S) can be approximately estimated G as (L -L )/2. Specifically, for RF SGTs with channel length of 1000 nm, 800 nm, 600 nm, 400 nm, G CH 200 nm in Fig.2, the source length (S) are approximately1000 nm, 1100 nm, 1200 nm, 1300 nm and 1400 nm, respectively. And for RF SGT with channel length of 80 nm in Fig.3, the source length (S) is about 1460 nm. In this work, source length (S) was not intentionally optimized to maximize the cut-off frequency. As the fabrication of small-scale-size SGTs involves three sequential EBL steps we mentioned above, varying source length (D) will add another EBL step, which is technically challenging and would significantly complicate the process, particularly for sub-100-nm devices. We fully acknowledge the importance of source-length optimization for improving high-frequency performance. As demonstrated in previous studies on SGTs [R13, R15], the source length plays a crucial role in determining frequency performance. Shortening the source length can effectively increase the source injection current density and thus enhance the cut-off frequency [R13]. Although our device structure and materials differ from those in previous studies, the underlying insights from these works remain highly instructive for guiding further optimization. In future work, we plan to explore source-length optimization together with process improvements—such as reducing gate-to-source/drain overlap and parasitic capacitances—to further enhance the high-frequency characteristics of the MoS SGTs. In addition, we have cited the references [R13] and added relevant 2 discussions in the revised manuscript. Revision for Comment 3: Following the reviewer’s comments, we have revised the schematic of the MoS SGT in Fig. 1a of the manuscript. The detailed source length of the RF SGTs has been 2 incorporated in the newly-added Fig. S15 in the revised supplementary information, which we have highlighted. In addition, a discussion about further optimization on frequency performance has been incorporated in the revised manuscript in Page 7, Line 43, and we cited the reference [R13], which we have highlighted. Comment 6: Benchmark figures, such as Fig. 2f, 3d, 4e, 4g, and S21, lack references for the benchmark data. Providing specific references next to the symbol would improve clarity. In particular, for the Si benchmark, it is essential to specify the technology node and the name of the foundry company. Response 6: We appreciate the reviewer’s valuable comment. For the benchmark figures (Figs. 2f, 4e, 4g, and S21), we have added specific references next to the corresponding symbols to improve clarity, as shown in the revised manuscript and in Fig. R9 below. In the case of the benchmark figure Fig. 3d, the shaded regions labeled “2D material or metal oxide TFT” and “Si-MOSFET” are intended to represent the typical range of intrinsic gain values summarized from previously reported devices with comparable channel length, rather than data from a single source. To preserve the visual clarity and consistency of the figure with previously published works [R17, R18, R19], we intentionally did not annotate references directly within the plot. The corresponding quantitative data and citations are provided in Fig. 2f and Table S1 of the supplementary information for reference. Regarding the Si MOSFET benchmark in Fig. 3d, we have now specified the technology node in the revised manuscript (rather than directly within the figure itself). Specifically, the Si benchmark data were extracted from [R20], corresponding to a 65 nm commercial technology node, which provides a fair comparison with the 80 nm channel-length SGT presented in this work. It is well established that the intrinsic gain of Si MOSFETs decreases with technology scaling, as the stronger short-channel effects lead to reduced output resistance [R21]. The name of the foundry company was not disclosed in the cited reference, possibly due to the confidentiality policies, which is common in academic publications involving commercial CMOS technologies. Revision for Comment 6: Following the reviewer’s comments, we have added specific references next to the corresponding symbols in the benchmark figures (Figs. 2f, 4e, 4g, and S21) in both the manuscript and supplementary information, which we have highlighted. In addition, for the benchmark in Fig. 3d that includes the Si reference, the technology node has now been specified in the revised manuscript in Page 7, Line 23, which we have highlighted. Comment 7: The amplifier already demonstrates excellent performance, but the paper would be more meaningful if the advantages of the amplifier, constructed with transistors having a MHz-level cutoff frequency as proposed in the study, were visualized in a specific application unit. Response 7: We fully agree the reviewer’s point and thanks for this valuable suggestion. The proposed amplifier is primarily targeted for high-gain sensor-interface applications operating in the MHz-level frequency range, where ultra-low-power operation is also essential [R7]. The present work focuses on demonstrating the feasibility and device-level potential of ultra-high gain, MHz-level cutoff frequency transistors operating in subthreshold region for such analog front-end circuits. Although full circuit integration or system-level demonstration is beyond the present scope, the achieved results effectively emulate the performance required for such sensor-interface and analog front-end circuits. In our future work, we plan to further integrate and visualize the advantages of this amplifier in specific sensing or readout units to highlight its application-level benefits. Response for the minor errors: We thank the reviewer for the careful reading and for pointing out these detailed inconsistencies and minor errors. All the noted issues, including unit corrections, figure labeling, notational consistency, spacing, and typographical errors, have been carefully checked and corrected throughout the revised manuscript and supplementary information to ensure full uniformity and clarity. Specifically: 1. The unit on the left y-axis in Fig. 2a has been corrected to A/μm for consistency. 2. The gas name in the Mo etching process has been verified and corrected from C H to C F . 3 8 3 8 3. The expression of layer thicknesses and material names has been standardized (e.g., “30 nm Mo gate metal”, “300 nm SiO dielectric”, “20 nm Ni/20 nm Au source metal”). 2 4&5 The unnecessary orange lines in Fig. S15 have been removed, and the abbreviations SGT and REF are now defined in the caption. 6. The order and notation in Fig. S16 have been revised for logical consistency. 7. The use of different y-axis units in Figs. S10c and S10d is intentional. In Fig. S10c, the drain current spans several orders of magnitude and is plotted on a logarithmic scale, so the unit (μA/m) is used to conveniently cover a wide current range. In contrast, Fig. S10d presents the linear output characteristics in the microampere range, where (μA/μm) provides clearer readability. Therefore, the unit difference is maintained for clarity and visual consistency with the data scale. This practice is also common in the literatures [R3, R17, R18]. 8. The label “This work” has been removed in Figs. S9 c-d. 9&10&11. All inconsistent symbols, notations, and spacing (e.g., rₒ vs R , “×” vs “·”, OUT “subthreshold”, “cut-off frequency”, “ultra-low”, etc.) have been standardized across the main text and Supplementary Information. 12. The expression has been corrected to “1/37 of that at 200 nm” in the revised manuscript. 13. Figure numbering, reference formatting (e.g., “Fig. 3e and Fig. 3f”), and spacing between numbers and units (e.g., 10 nm, 1 V) have also been corrected. 14. Appropriate spaces have been added after “MoS ” where missing. 2 15. The lowercase “v” in “Av” has been corrected to uppercase “V” for consistency. 16. Spaces have been added between numbers and units where missing. 17. All figure notations have been unified to the format like “Fig. 1a” without parentheses or extra spaces. 18. All supplemental figure notations have been unified to the format “Fig. S1a”. 19. “Fig. 3e and f” has been modified to “Fig. 3e and Fig. 3f” and bolded. 20. All figure labels have been standardized to the format “Fig. 1a” without additional punctuation. 21. “Volt” and “nanowatt” have been replaced with “V” and “nW” for consistency. 22. The corresponding description of Fig. 4f has been corrected to 200 nm to ensure consistency between the figure and its description. Revision for the minor errors: Following the reviewer’s comments, we have corrected all the minor errors throughout in the revised manuscript and supplementary information, which we have highlighted. General Response: We greatly appreciate the reviewer’s highly positive and encouraging evaluation of our work, recognizing it as “a significant advancement in the field of thin-film transistors by demonstrating a high-frequency, subthreshold-operating source-gated transistor (SGT) based on monolayer molybdenum disulfide (MoS )… a major breakthrough considering the 2 historical limitations of SGTs to low operating frequencies… highlighting the potential of MoS₂ SGTs for high-speed applications. The reproducibility of the fabrication process is further evidenced by the consistent performance across 56 measured devices, indicating robustness and scalability.” Below, we provide detailed point-by-point responses to all the questions and suggestions raised. Comment 1: The manuscript mentions that metal Ni and Pd form ohmic and Schottky contacts with MoS₂, respectively. It would be beneficial to include measurements of the Schottky barrier heights and contact resistances for these configurations to further validate the contact properties. Response 1: We thank the reviewer for this constructive suggestion. To further verify the contact characteristics of Ni and Pd with MoS , we have performed 2 temperature-dependent electrical measurements and extracted the corresponding Schottky barrier heights (Φ ) using the following relationship between the current and the barrier to calculate the B Schottky barrier [R22]: 𝐼 𝑞𝑷𝒉𝒊 𝑞𝑽 ln( 𝑫𝑺 )=− 𝑺𝑩 +ln(𝑨∗∗ )+ln⁡[exp( )−1] (1) 𝑻𝟐 𝒌𝑻 𝒌𝑻 where k, q, T and A∗∗ are the Boltzmann constant, electronic charge, temperature and Richardson's constant, respectively. The barrier height can be obtained from the slope of the ln (I /T2) to the 1/T DS relation curve as shown in Fig. R10 below. The extracted Φ values are approximately 71 meV for B Ni and 157 meV for Pd, respectively. The much smaller barrier of Ni indicates a near-ohmic contact, while the relatively larger barrier of Pd confirms its Schottky-type contact, consistent with our discussion in the manuscript and some previous studies [R23, R24]. This result also fulfills the intended purpose of forming a Schottky barrier at the source in the SGT, enabling a direct comparison between the SGT and conventional TFT configurations. These extracted barrier heights provide clear quantitative evidence of the distinct contact behaviors and offer consistent experimental support for the contact interpretation presented in the manuscript. Revision for Comment 1: Following the reviewer’s comments, we have added some discussion clarifying that the distinct contact behaviors of Ni (ohmic-type) and Pd (Schottky-type) with MoS 2 in the revised manuscript in Page 3, Line 38, and the corresponding figures are incorporated in Fig. S4 of the revised supplementary information, which we have highlighted. Comment 2: Hysteresis behavior is crucial for understanding the stability and reliability of the transistor. Could the authors provide detailed double-sweep transfer curve data to illustrate the hysteresis behavior of their devices? Response 2: We thank the reviewer for this constructive suggestion. To clarify the hysteresis behavior, we have provided the double-sweep transfer characteristics of the MoS SGT in Fig. R11. The forward (black) and reverse (red) sweeps were measured at V = 1 V 2 DS for a device with a channel length of 80 nm. The extracted hysteresis is approximately 46 mV, indicating the high interface quality of the fabricated device. Revision for Comment 2: The discussion about the hysteresis characteristic of the SGT has been incorporated in the revised manuscript in Page 7, Line 12, which we have highlighted. The hysteresis behavior has been incorporated in newly-added Fig. S13 in the revised supplementary information, which we have highlighted. Comment 3: Clean interfaces are vital for transistor performance. The TEM image of the transistor structure in Fig. 1 is rather blurry, which does not allow for clear observation of the interfaces. Could the authors supplement high-resolution TEM images, particularly magnified views of the Ni-MoS₂ contact, Pd-MoS₂ contact, and the interface between MoS₂ and the gate stack? Response 3: We appreciate the reviewer’s kind and valuable suggestion. As correctly pointed out, clean interfaces are indeed crucial for transistor performance. The TEM image in Fig. 1 was primarily intended to verify that the fabricated device structure conforms to our design and demonstrates the short channel length of the transistor. It also clearly reveals that the interfaces among all stacked layers are sharp and clear. For further clarity, we have provided additional EDX elemental mapping data in Fig. S6 of the Supplementary Information, where each element is presented separately. However, to maintain a concise layout, we only included a cropped device region in Fig. S6, which may have affected the apparent clarity of the interfaces. To address the reviewer’s concern more directly, the original-size TEM image and corresponding EDX elemental maps are now provided in Fig. R12 below. As shown, these maps confirm that all elements are uniformly distributed without inter-diffusion, further confirming that the interfaces are clean. Regarding the higher-resolution TEM images of the Ni–MoS and Pd–MoS contacts, as well as the 2 2 MoS /gate-stack interface, we regret that these specific regions were not captured at atomic 2 resolution in the present measurements due to the small device area and the limited exposure tolerance of monolayer MoS under electron-beam irradiation. Nevertheless, the existing TEM and 2 EDX analyses already confirm the structural integrity and cleanliness of the interfaces, ensuring that the overall device quality is sufficient to support the excellent electrical characteristics discussed in the manuscript. Revision for Comment 3: The higher-resolution TEM images and EDX mappings have been incorporated in Fig. S6 in the revised supplementary information, which we have highlighted. Comment 4: The measured cutoff frequency of 208 MHz is impressive for an 80 nm channel length. However, the source electrode in SGTs typically covers a portion of the channel and has significant overlap with the bottom gate, increasing parasitic capacitance. Could the authors address this issue? Would it be possible to fabricate a local top-gate transistor to achieve similar performance while mitigating this parasitic effect? Response 4: We thank the reviewer for this insightful question. The source–gate overlap indeed introduces additional parasitic capacitance; however, in source- gated transistors (SGTs) this overlap is a functional design element rather than a purely parasitic feature. In SGT, the gate electrode must be located above or below the source barrier so that the semiconductor region between the source and gate becomes fully depleted as the drain bias increases, fixing the electric field at the barrier and yielding current saturation that is almost independent of drain voltage. This design intrinsically provides low saturation voltage, low-power consumption, high output resistance (R ), large intrinsic gain, and strong immunity to short-channel effects OUT (SCEs). [R1] We fully agree that a local top-gate (TG) structure could, in principle, lower overlap capacitance and enhance frequency response, as commonly adopted in studies [R8, R9] primarily focused on pursuing high-frequency operation. However, implementing a local TG configuration would decouple the gate from the source barrier and revert carrier transport toward conventional channel- limited conduction, which would inevitably compromise the key merits of the SGT—its high R , OUT high intrinsic gain and strong immunity to short-channel effects (SCEs). In this work, our goal is to maintain a high voltage gain and low power consumption across a wide frequency range to make the proposed device suitable for IoT sensor interfaces [R18], rather than pursuing high cut-off frequency alone. To this end, we employ the SGT configuration to realize high gain and low-power consumption in the subthreshold regime, while further enhancing the frequency performance through the use of high-mobility monolayer MoS , thin high-k gate dielectrics and 2 ultra channel-length scaling enabled by the strong short-channel immunity of the SGT mechanism. These combined design strategies allow our 80-nm MoS SGTs to simultaneously achieve high 2 intrinsic gain and a cut-off frequency of 208 MHz in the subthreshold regime. Therefore, while reducing overlap capacitance is desirable, such optimization must preserve the gate coupling to the source barrier. Future refinements—such as introducing a selective low-k dielectric beneath the overlap region or employing self-aligned source patterning to ensure the minimal functional overlap required for barrier modulation—could further minimize parasitic capacitance without compromising the fundamental SGT operation principle. Comment 5: The concept of pinch-off, originally proposed for silicon MOSFETs, may not be directly applicable to MoS₂ SGTs, which are n-type semiconductors and do not easily transition to inversion. Could the authors provide an explanation and discussion on the applicability of this concept to their MoS₂ SGTs? Response 5: We thank the reviewer for this insightful question. The concept of “pinch-off” was originally defined for inversion-channel Si MOSFETs, where the channel near the drain end becomes depleted of inversion carriers when V exceeds V −V . This DS GS TH depletion forms a high-resistance region at the drain end, across which any additional drain voltage is dropped, limits further current increase and leading to current saturation. [R25] A similar field- induced depletion process also occurs in accumulation-mode TFTs, even though no inversion layer is formed. As the drain voltage increases, the electric field near the drain end raises the local channel potential and reduces the carrier density in that region. Once sufficiently depleted, most of the additional drain bias drops across this high-field region, and the drain current ceases to increase significantly with V . [R26] Thus, the term “pinch-off” can be generalized to describe the DS formation of a depletion-limited region that causes current saturation, independent of whether the device operates in inversion or accumulation mode. In source-gated transistors (SGTs), including our MoS SGTs, the depleted region simply shifts from 2 the drain side to beneath the source barrier. The detailed depletion process is as follows: at small V , the source barrier is reversed-biased, depleting the carriers beneath the source region; as V DS DS increases, first depletion occurs beneath the source when the whole carriers induced by V under GS the source are depleted [R1]; with further increase in V , the excess V no longer affects the DS DS depletion region under the source terminal, but instead reduces the electron density in the channel toward the drain direction, similar to the behavior in the conventional TFTs; then the second depletion region develops at the drain side, as shown in the TCAD simulation results in Fig. S8 (supplementary information) and Fig. R13 below. With both the source and drain partially depleted, the saturation behavior yields a larger output resistance than that of a conventional TFT, consistent with our experimental observations. Therefore, although the physical location differs, the underlying mechanism—formation of a depletion-limited region that fixes the drain current—is conceptually analogous to “pinch-off.” Comment 6: The gain-input voltage (AV-VIN) curve in Fig. 4 would be more intuitive if presented on a logarithmic scale for the y-axis. This would allow for a clearer judgment of the gain magnitude. Could the authors consider this change? Response 6: We appreciate the reviewer’s kind suggestion. Following the reviewer’s suggestion, we applied a logarithmic scale to the y-axis of the A -V V IN curve in Fig. 4c (bottom) and compared it with the original linear-scale plot. The two plots are shown in Fig. R14 below for comparison. As shown in the left panel, the linear scale clearly presents the actual peak gain. This is because the amplifier exhibits excellent amplification performance, and its gain is concentrated within a narrow peak region. In contrast, as shown in the right panel, under the logarithmic scale, the values in the low-gain region (below approximately 1 V/V) are stretched, and small measurement fluctuations are amplified, making the main peak less distinguishable. Moreover, although the logarithmic scale provides a wider vertical range, the main peak appears flattened, and the contrast between high- and low-gain regions becomes less pronounced, leading to poor visual clarity. Therefore, we retained the linear-scale presentation in Fig. 4 to ensure better readability and more accurate interpretation. It is also worth noting that presenting the A -V curve on a linear scale is a widely accepted practice V IN in amplifier characterization, as adopted in previous studies [R3, R4, R19]. Comment 7: The absolute units of the y-axis variables in Fig. 3c and 3d may not be helpful for readers to judge their magnitudes. Could the authors consider normalizing these variables for better clarity? Response 7: We appreciate the reviewer’s kind suggestion. Following the reviewer’s suggestion, for Fig. 3c, we scaled g and R by 1011 and 10-8, m OUT respectively, to present their relative trends on comparable scales. This adjustment improves the readability of the data by eliminating the large-scale difference between the two variables. The modified figure is shown below. As for Fig. 3d, we have kept the original absolute scale because this figure is intended to provide a direct comparison of the intrinsic gain across different device technologies (Si-MOSFETs, metal oxides, and 2D materials). Using the absolute scale allows readers to quantitatively benchmark our results against previously reported values. Revision for Comment 7: Following the reviewer’s comments, Fig. 3c has been modified in the revised manuscript with the scaled presentation of g and R by 1011 and 10-8, respectively, to m OUT improve data readability. The corresponding figure caption has been modified in the revised version, which we have highlighted. Comment 8: In Fig. S17 and S19, there are noticeable fluctuations in the VIN-IDD and VIN-Power curves around VIN=0.15-0.2 V. Could the authors explain the reason for these fluctuations? Response 8: We appreciate the reviewer’s helpful suggestion. The fluctuations observed in the V –I and V –Power curves originate from small variations in IN DD IN the measured I current. The I current represents the current flowing from V to ground through DD DD DD the amplifier (as shown in Fig. R16 below), which can be approximately regarded as the current flowing through both the load transistor and drive transistor during amplifier operation. In the V IN range of 0.15–0.2 V, the drive transistor operates in the deep subthreshold region, and the load transistor also operates in the deep subthreshold region due to its gate-source shorten configuration (V = 0 V), where the current magnitude is extremely small (below 10 pA) and thus highly sensitive GS to measurement noise. Moreover, to obtain a precise voltage gain, a very fine voltage step of 0.5 mV was used during measurement, which may make the apparent fluctuations more noticeable. In addition, the noise of the probe station may also contribute to these small variations in the measurement results. Therefore, the observed fluctuations are attributed to the inherent noise and the fine voltage step in deep-subthreshold measurements, as can also be slightly observed in Fig. 4c, Fig. S19c, and Fig. S21e. These fluctuations do not affect the normal operation or the overall performance of the amplifier. General Response: We greatly appreciate the valuable work of the reviewer. General Response: We greatly appreciate the valuable work of the reviewer. Below, we provide point-by-point responses to all the questions and suggestions raised. Comment 1: In supplementary information, abbreviation of atomic layer deposition was noted ALD, not spelled out. Response 1: We thank the reviewer for this insightful question. We have spelled out ‘atomic layer deposition (ALD)’ at its first occurrence in the Supplementary Information. Revision for Comment 1: The full term ‘atomic layer deposition’ has been added in the Supplementary Information to clarify the abbreviation ‘ALD’ in the revised version，which we have highlighted. Comment 2: On page 6, line 249 / page 10, line 419 / page 18, line 637, 638, 641, spacing is needed between number, unit, symbols and equals sign - “0.1V” / “1.0V” / “80mm” / “VDS= 1.0 V” / “f= 100 Hz” / “LCH =80 nm”. Response 2: We appreciate the reviewer’s insightful comment. The spacing between numbers, units, symbols, and equals signs has been corrected in all indicated locations in the revised version. Revision for Comment 2: The requested spacing corrections have been implemented at all indicated locations in the revised version，which we have highlighted. Comment 3: On page 11, line 446, “H21” should be standardized to “h21”. Response 3: We thank the reviewer for this insightful question. ‘H ’ has been standardized to ‘h ’ in the revised version. 21 21 Revision for Comment 3: The notation has been corrected from ‘H ’ to ‘h ’ in the revised version, 21 21 which we have highlighted. Comment 4: On page 11, lines 452 and 453, “gs” and “ds” should be written as subscripts. Response 4: We thank the reviewer for this kind suggestion. ‘gs’ and ‘ds’ have been changed to subscript format in the revised version. Revision for Comment 4: The notations have been corrected to subscript format (‘V ’ and ‘V ’) gs ds in the revised version, which we have highlighted. Comment 5: In Supplementary Figures 10a and 10b, it would be preferable to adjust the position of the “Al₂O₃” label so that it does not overlap with the figure, similar to Figure 1a. Response 5: We appreciate the reviewer’s insightful comment. The position of the ‘Al O ’ label has been adjusted to avoid overlap in Supplementary Figures 10a 2 3 and 10b, similar to Figure 1a, which has shown in the below Fig. R1. Revision for 5: Following the reviewer’s comments, we have adjusted the position of the ‘Al O ’ label in Supplementary Figures 10a and 10b to avoid overlap, which we have highlighted. 2 3 Comment 6: In Supplementary Figures 10b / Supplementary Figures 20 ~ 22, spacing is needed between number and unit - “38.7S/A” / “0.5V”. Response 6: We appreciate the reviewer’s valuable comment. The spacing between numbers and units has been corrected in Supplementary Fig. 10b and Supplementary Figs. 20–22. Revision for Comment 6: Following the reviewer’s comments, the number–unit formatting in Supplementary Fig. 10b and Supplementary Figs. 20–22 has been revised (e.g., “38.7 S/A”, “0.5 V”) to ensure appropriate spacing, which we have highlighted. General Response: We greatly appreciate the valuable work of the reviewer."}]

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