Wafer-scale high-κ HfO_2 dielectric films with sub-5-Å equivalent oxide thickness for 2D MoS_2 transistors

Domain: physics
Published: 2026-01-20
Editorial outcome: minor_revision

Abstract
High-κ gate dielectrics are indispensable in modern transistor technology and play a pivotal role in efficient capacitive gating and suppression of leakage currents. However, the realization of industry-compatible high-κ gate dielectrics at a sub-5-Å equivalent oxide thickness (EOT) remains challenging. Here we report the realization of 1.3-nm thick hafnium oxide (HfO2) dielectrics via an industry-compatible multiple oxidation atomic layer deposition process at 200°C. A low EOT down to 2.5 Å is demonstrated for 1.3-nm thick HfO2 dielectrics on metal gates with a low leakage current of 10−6 A/cm2 and a robust breakdown electric field of ~22.3 MV/cm. Remarkably, such low EOT high-κ/metal gates can be directly implanted into emerging two-dimensional (2D) transistors and low-power logic circuits on 8-inch wafer scale to showcase their potentials. The as-fabricated molybdenum disulfide (MoS2) transistors exhibit a large on-state current density of 260 µA/µm at source-drain bias of 0.5 V, a high on/off ratio of 108, an average subthreshold slope (SS) of 75 mV/dec, and small capacitance equivalent thickness (CET) values of 0.34 nm for gate-first transistors and 0.50 nm for gate-last transistors. Our ultra-scaled dielectrics hold significant promise for advanced semiconductor fabrication processes towards the angstrom era.

Introduction
The evolution of semiconductor technology is closely associated with the development of high-κ gate dielectrics, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and zirconium oxide (ZrO2)1–4. In 2007, Intel Corporation announced the adoption of hafnium-based high-κ metal gate (HKMG) in its 45 nm technology node. This technological innovation marked a significant paradigm shift away from traditional silicon dioxide (SiO2) dielectrics and poly-Si gate, quickly becoming a standard in the semiconductor industry. In order to further advance semiconductor technology nodes for more compact, fast, and energy-efficient integrated circuits (ICs)5–8, it is pivotal to continue the equivalent oxide thickness (EOT) scaling of high-κ dielectrics in transistors. EOT of a high-κ dielectric refers to the equivalent thickness of a SiO2 film having the same specific capacitance with the high-κ dielectric film, while capacitance equivalent thickness (CET) reflects the actual physical gate controllability in devices. The former is more commonly used to evaluate the dielectric performance of one material. In the process of EOT reduction, using high-κ materials can effectively suppress the leakage current. EOT within silicon transistors at the 3-nm technology node has already been reduced to 9.5 Å9. Recently, high-κ dielectrics of HfO2-ZrO2 superlattice or Sb2O3/HfO2 with EOT of 6–8 Å has been demonstrated in prototype transistors10,11. According to the 2022 International Roadmap for Devices and Systems (IRDS), the outlined EOT for emerging logic devices requires to be <5 Å12. Such aggressive EOT values are challenging to achieve in conventional HfO2- or ZrO2-based high-κ dielectrics10–14. Over the past five years, many emerging high-κ dielectrics, including perovskite SrTiO3, ion crystal CaF2, molecular crystal Sb2O3, and two-dimensional (2D) Bi2SeO5/Bi2SiO5, have been developed for further EOT scaling down to ~4.1 Å15–19. Yet promising, these materials are incompatible with the standard manufacturing process line due to high-temperature processes, small-scale limitations, and specific channel necessities, etc.20. Besides, these emerging high-κ dielectrics also exhibit large gate leakage currents at 10−1–10−3 A/cm2 level, which are away from the low-power application of 10−5 A/cm2 11,13,14. Thus, developing a high-κ gate dielectric with sub-5-Å EOT, low gate leakage currents of <10−5 A/cm2, and implementable to standard semiconductor manufacturing process as well persists as an essential yet elusive challenge.

In this work, we develop a multiple oxidation atomic layer deposition (MOALD) approach for high-quality ultrathin HfO2 dielectrics at an 8-inch wafer scale. The deposition is performed at a relatively low temperature of 200°C, rendering it compatible not only with commercial Si complementary metal-oxide-semiconductor (CMOS) technology but also with emerging two-dimensional semiconductor-based field-effect transistors (2DFETs). Notably, we report the realization of the 1.3-nm-thick HfO2 dielectric layer with a small EOT of 2.5 Å. As-achieved HfO2 films exhibit an exceedingly low leakage current below 10−6 A/cm2 at 1 V gate voltage and showcase a robust breakdown electric field of ~22.3 MV/cm. The application of such a low-EOT high-κ layer in cutting-edge 2D gate-first and gate-last FETs based on monolayer molybdenum disulfide (MoS2) is demonstrated to evaluate its practicality and efficacy in gate control. Remarkably, 100-nm-channel devices feature an on-state current density of ~260 µA/µm, a high on/off ratio of ~108, and an average subthreshold slope (SS) of ~75 mV/dec at the source-drain bias of 0.5 V. We further fabricate 8-inch wafer-scale logic gates and memory devices such as inverters, logic gates (e.g., AND, NAND, and NOR) and five-stage ring oscillators (ROs) with correct functions. Such ultimately scaled EOT not only transcends the goal of IRDS for 2037, but also holds substantial implications for the forthcoming advanced semiconductor processes towards the ångström era.

Results
Realization of the 2.5-Å-EOT HfO2 films
In the conventional ALD process for HfO2 employing only one oxidation step, a wealth of oxygen vacancies (Ov) is often found in the as-deposited films. In contrast, our optimized HfO2 deposition is performed via a MOALD process, including two steps of oxidation by ozone and oxygen plasma accordingly. Please refer to Materials and Methods for more details. As illustrated in Fig. 1a, this MOALD process is effective in reducing oxygen vacancy concentrations (V_O) and significantly enhancing the quality of HfO2 films, as confirmed from the X-ray photoelectron spectroscopy (XPS) spectra (Fig. 1b). From the XPS characterizations, it can be clearly seen that V_O reduces from 25.7% for one-step-oxidation ALD to nearly negligible levels for MOALD21. As a result, when applying in MoS2 FETs, hysteresis in the transfer curve is expected to be greatly suppressed with MOALD HfO2 dielectric, compared with that using normal ALD HfO2 dielectrics. (Supplementary Fig. 1).

We further elucidate the merit of the reduced defect concentration in HfO2 film through first-principles calculations (Supplementary Fig. 2). V_O is defined as:

V_O = n_v / N × 100%

where N equals to 320, representing the total number of oxygen atoms; and n_v is the number of Ov. Here, we consider several different V_O varying from 0 to 15.6% (Supplementary Fig. 3). Five amorphous structures for each V_O are generated and optimized with fixed lattice parameters (Supplementary Fig. 3). The densities of states at each V_O are calculated and shown in Supplementary Fig. 4. The Fig. 1c, d show results from two typical V_O, i.e., 0 and 15.6%, respectively. Due to the presence of structural disorder, the electrical conductivities of the systems are assessed through the mobility bandgap, which is identified using the inverse participation ratio22–24 (see Supplementary Notes 1, 2 and Supplementary Fig. 5) The mobility bandgaps are summarized in Supplementary Tables 1–6. The average mobility bandgap at each V_O is presented in Fig. 1e, which shows a shrinking trend with the increase of V_O. With the mobility bandgap reducing at the presence of oxygen vacancies, a reduced breakdown strength of HfO2 is expected. Moreover, as V_O increases, in-gap localized defect states become more prominent (Fig. 1d and Supplementary Fig. 4). These defective states are expected to provide additional channels, like trap assisted tunneling (TAT), for electron tunneling thus further reduces the breakdown strength of HfO2. Therefore, reducing the Ov concentration is expected to restore the breakdown strength of HfO2 thin film and enhance its dielectric performance.

In order to fabricate metal/high-κ stacks, we first deposit 10-nm Au at a low rate of 0.01 Å/s by the electron-beam evaporation then HfO2 by the MOALD. At least 10 ALD cycles are necessary to realize continuous HfO2 films with a minimum thickness of 1.3 nm. Figure 1f and Supplementary Fig. 6 show the cross-sectional transmission electron microscopy (CS-TEM) images of an Au/HfO2/MoS2 stack, demonstrating the continuity and uniformity of the 1.3-nm HfO2 film. A zoomed-in image is shown in Fig. 1g with two stacked layers of monolayer MoS2 and HfO2 clearly seen. The layer thickness of MoS2 and HfO2 are 0.7 and 1.3 nm, respectively. Besides, the stacked structure of Au/HfO2/MoS2 is further confirmed from the elemental mapping of Au, Mo, Hf (Fig. 1h). Atomic force microscopy (AFM) images on the surface of gate metal before and after deposition of 1.3-nm-HfO2 layer are also shown in Fig. 1i, indicating an excellent surface smoothness, integrity, and uniformity. The surface roughness of the metal gate and dielectric are 241 and 239 pm, respectively, as illustrated in the height histogram (Fig. 1j and Supplementary Fig. 7).

Dielectric properties of MOALD ultrathin HfO2 films
The dielectric properties of MOALD HfO2 dielectrics are characterized electrically in a metal-insulator-metal (MIM) cell, in which employing Au as top and bottom electrode. (Fig. 2a, b) The C-V and leakage-current measurements are performed for 1.3-, 2.6- and 3.9-nm thick HfO2 films (Fig. 2c and Supplementary Fig. 8a). Our results indicate that κ is ~31.0 for 3.9-nm-HfO2 films; and it gradually reduces with the decreasing layer thickness but still maintains at 19.8 for 1.3-nm-HfO2 dielectrics (Fig. 2d). As EOT = 3.9 * t / κ, where t denotes the dielectric thickness, we also plot the corresponding EOT for different HfO2 thickness in Fig. 2d. Notably, an EOT of 2.5 Å is achieved for 1.3-nm-HfO2 dielectrics.

The dielectric breakdown characteristics of as-deposited HfO2 layers are also investigated based on the MIM structure (Fig. 2e and Supplementary Fig. 8b). Figure 2e shows leakage currents as a function of applied bias voltages for three typical dielectric thicknesses, i.e., 1.3, 2.6, and 3.9 nm. Note that both Fowler–Nordheim (FN) tunneling and direct tunneling could contribute to the leakage currents in MIM structure. The experimentally observed suppression of leakage current is consistent with the large bandgap of the dielectric with minimal oxygen vacancies and the oxygen-rich surface, which effectively reduces wavefunction overlap at the contact–dielectric interface. In contrast, similar measurements on the 1.3-nm-HfO2 deposited via a conventional one-step-oxidation ALD process exhibit a direct tunneling behavior even under small bias voltages at ~mV scale (Supplementary Fig. 9). The hard breakdown voltage for the 1.3-nm-HfO2 deposited via MOALD is 2.9 V, corresponding to an electrical breakdown field of ~22.3 MV/cm. Note that the leakage current of all samples consistently remains a level below the low-power threshold of 0.015 A/cm2 till breakdown. This compelling observation underscores the robust performance and reliability of our samples, highlighting their suitability for various applications particularly in the low-power scheme. In case of 1.3-nm-HfO2 dielectrics, the leakage at 4 MV/cm gating maintains <10−6 A/cm2 (approaching detection limit), a value significantly approaching the dynamic random-access memory (DRAM) limit15,25,26 (Fig. 2f). The current-time curves of the 1.3-nm-HfO2 dielectric (Supplementary Fig. 10) also demonstrate electrical stability. These results suggest the substantial advantages of ultrathin HfO2 dielectrics in gate-first technology for low-power applications.

Based on the above results, we benchmark the performance of our HfO2 dielectrics in comparison with existing up-to-date EOT dielectrics such as HfO2, SrTiO3, CaF2, and Bi2SiO5 (Fig. 2g and Supplementary Table 7)10,13–19,27–33. It can be seen that MOALD ultrathin HfO2 dielectrics exhibit one of the highest dielectric constants at the same scale of dielectric physical thickness. In Fig. 2h, It also show one of the lowest recorded EOT and electrical breakdown field strengths among all reported dielectric films1,34. Therefore, our MOALD ultrathin HfO2 dielectrics are promising for advanced transistors to achieve heightened carrier densities under equivalent effective gate voltages while simultaneously maintaining minimal current leakages.

2D FETs employing with 1.3-nm-HfO2 gate dielectrics
2D FETs are considered a promising solution to future chips in the post-Moore era and usher in the ångström technology node4,8,35,36. Aiming for such 2D FETs, both channels and high-κ dielectrics are required to be ultimately scaled. In this work, we further investigate such possibilities by implementing the 2.5-Å EOT high-κ dielectrics into the 2D transistor technology. Transferred monolayer MoS2 is employed as the channel and the device fabrications are accomplished by gate-first technology in this part (Fig. 3a, Materials and methods). Gate-first MoS2 FETs are fabricated with varied HfO2 thicknesses but same channel width/length (W/L) of 5/2 µm (Supplementary Fig. 11). As shown in Fig. 3b, a reduction in the HfO2 thickness leads to decreasing gate control voltage, suggesting an enhancement in gate controllability for thinner dielectrics. Figure 3c and Supplementary Fig. 12 show the transfer curve of a typical 2.5-Å-EOT 2D FET with a 2-µm channel length, featuring with a fundamental thermionic limit of the subthreshold slope (SS) of 70 mV/dec (Fig. 3e), a substantial on-off ratio of ~108 and a negligible hysteresis (~1 mV) at a sweep rate of 0.1 V/s, just as expected. The output characteristics are shown in Fig. 3d, and the on-state current density (Ion) exceeds 58 µA/µm at gate voltage (Vgs) = 1 V and a source-drain bias of 0.5 V. The transfer curves of 105 MoS2 FETs are shown in Fig. 3f. These devices exhibit small device-to-device variations and superior performance in terms of SS, on/off ratio, and Ion (Fig. 3f). The average SS is ~72 mV/dec, meeting the requirement of the 2037 criteria for future FETs (2022 IRDS). Moreover, these devices show a high average on/off ratio of 4 × 108 and a high Ion of 18 µA/µm at 0.1 V source-drain bias. These excellent device performances highlight the effectiveness of the high-κ dielectrics on gate controllability.

Note that, due to the effect of vdW gap, quantum capacitance, and contact resistance, the effective capacitance in transistors is little less than the oxide capacitance. Thus, we re-estimated the transistor capacitance and CET to confirm this judgment, as shown in the Fig. 3h–k and Supplementary Figs. 13–15. From these measurements, we report an average CET of 0.34 ± 0.01 nm for 1.3-nm HfO2 dielectrics, 0.47 ± 0.03 nm for 2.6-nm HfO2 dielectrics, 0.66 ± 0.03 nm for 3.9-nm HfO2 dielectrics, respectively. Short-channel transistors at L = 100 nm are fabricated. Remarkably, the gate leakage at Vch = 1 V remains below 10−5 µA/µm, which is comparable to those previous state-of-the-art devices15,17,18. The sweeping measurements (Fig. 3l) also indicate an exceedingly small hysteresis (<10 mV) and low SS value (70 mV/dec, Supplementary Fig. 16). A high Ion of 260 µA/µm at 0.5 V source-drain voltage and 1 V gate voltage, which exceeds the most of MoS2 FETs with advanced dielectrics. (Fig. 3m)

We also summarize the key performance metrics in 2D FETs incorporated with sub-3.5-nm-EOT dielectrics in Fig. 3n, with respect to the on-state current, on/off ratio, and SS which are pivotal indicators for the operational efficiency and device applicability. From this benchmark analysis, our 2D FETs exhibit obvious performance superiority in terms of the aforementioned metrics. Such performance superiority underscores the potential of 2.5-Å EOT dielectrics to not only the current silicon-based semiconductor technology but also a variety of new post-Moore technologies.

Gate-last 2D MoS2 transistors for sub-1-V operation
For all transistors, including silicon-based CMOS and thin-film transistors (TFTs), gate-last or gate-all-around architectures are commonly adopted. Therefore, it is necessary to evaluate gate-last 2D MoS2 transistors with ultrathin MOALD HfO2 dielectrics4,5. Due to the lack of dangling bonds in the MoS2 surface, it is generally difficult to deposit ultrathin HfO2 film by ALD (Supplementary Fig. 17). Here, we adopt an alternative approach. Firstly, a 1-nm-thick antimony (Sb) film is deposited on the MoS2 surface through electron-beam evaporation as the seeding layer. Such a thin Sb film will be oxidized to SbOx after 10 h of exposure to the air. Then we can deposit MOALD ultrathin HfO2 film (Fig. 4a). The quality of MoS2 after deposition is not degraded, as shown in the Raman and PL spectra (Supplementary Fig. 18). AFM is also conducted to measure the surface of every step (Fig. 4b). The schematic illustration and optical photos of the obtained gate-last MoS2 transistors is shown in the Fig. 4c, d. The total thickness of the device is only ~3 nm, including 0.7 nm MoS2, 1 nm SbOx seeding layer and 1.3 nm HfO2, which is confirmed with CS-TEM and STEM-EDS mapping (Fig. 4e, f).

Figure 4g shows the transfer curve of an as-fabricated gate-last MoS2 transistor, revealing a high on/off ratio of 108 and average SS of 71 mV/dec. The drain current saturates at gate voltage of ~0.7 V, which is closer to the requirement of IRDS 2024. Note that the Vth is more positive in gate-last transistors than that in gate-first transistors. We attribute this shift primarily to the incorporation of oxygen doping within the MoS2 channel during the fabrication of the gate-last stacks. This doping introduces n-type carriers, which effectively shifts the turn-on voltage in the positive direction7. The output curves of this device is shown in Supplementary Fig. 19, illustrating a high current density of 15 µA/µm at 0.5 V source bias, which is slightly smaller than that in gate-first transistors. The reason may come from the small contact resistance variation37 or gate controllability difference between 0.34 nm CET for gate-first devices and 0.50 nm CET for gate-last devices.

40 FETs with high uniformity are shown in the Fig. 4i. Compared with reported dielectrics for gate-last 2D transistors, our MOALD ultrathin HfO2 shows some of the one of the best SS of 70 mV/dec and on/off ratio of 108 (Fig. 4i)10,14,17,19,28,30–33,38,39. The effective CET in ultrathin gate-last MoS2 transistors with ultrathin 1 nm SbOx and 1.3 nm HfO2 dielectrics is also measured (Supplementary Fig. 20), demonstrating a small CET value of 0.50 nm and corresponding dielectric constant of 17.9. Comparing the EOT in the MIM structure and the CET in the MIS gate-first devices, the CET in gate-last devices is slightly larger (Fig. 4j), while still fulfilling the requirement of dielectrics in the future advanced transistors and chips.

8-inch wafer-scale 2D circuits with 1.3-nm-HfO2
To validate the scalability of the MOALD ultrathin HfO2 dielectrics, we deposit 1.3-nm-HfO2 dielectric layer on the 8-inch SiO2/Si wafer. The film thickness is accessed by ellipsometer (Fig. 5a), confirming the good uniformity with a minimal margin of error of 200 pm. Compared with previously reported sub-1-nm-EOT dielectrics of SrTiO3, Bi2SeO5, Bi2SiO5, Sb2O3, CaF2, and HfO2, our MOALD ultrathin HfO2 dielectrics showcase an unparalleled characteristics and superiority (Fig. 5b)14–18,29. For instance, the remarkably low process temperature, e.g., 200°C, enables seamless integration with silicon CMOS processes, in marked contrast from both perovskite (~1000°C) and 2D dielectric materials (~750°C)15,19. Moreover, the developed aggressively low-EOT dielectrics at 8-inch wafer scale significantly surpasses the limitations of other sub-1-nm-EOT dielectrics with a maximum wafer size of 4 inch. The 2.5-Å EOT HfO2 dielectrics also enable remarkable gate control capability, a high breakdown electric field, and minimal leakage current. MoS2 FETs and logic gates are fabricated via standard microfabrication processes.

We further demonstrate 8-inch wafer-scale fabrication of monolayer MoS2-based circuits with 1.3-nm-HfO2 dielectrics (Fig. 5c). More details on the fabrication process are included in Methods. Note that the 8-inch wafer-scale monolayer MoS2 is grown by our recently developed technique40 (Supplementary Fig. 21). Figure 5d shows flat tomography in nine different areas of HfO2 film. In Fig. 5e–g and Supplementary Figs. 22, 23, we present the inverter measurement in this 8-inch wafer. It shows a high gain of 40 and 205 at Vdd of 0.2 and 1.0 V, respectively. At the same time, the static power is only 22 pW at Vdd of 0.2 V. This diminutive power supply is significantly smaller than that of devices fabricated with other sub-1-nm-EOT dielectric layers, owing to the low EOT coupled with its good gate tunability. Besides, other elemental components of chips, including inverters and AND, NAND and NOR logic gates in a single pixel are fabricated, as presented in Fig. 5h, i. All AND, NAND and NOR logic gates function correctly and exhibit compatibility with the same low supply voltage of 0.2 V. Five-stage ROs could also work smoothly at Vin of 0.4 V with an output frequency of 2.35 MHz (Fig. 5k). These demonstrations further shed light on applying such ultra-low-EOT high-κ dielectrics in emerging large-scale 2D electronics targeting to further scaling down and low-power consumptions5.

Sub-5-Å-EOT HfO2 dielectric technology is developed at a maximum wafer size of 8-inch for both gate-first and gate-last technology. The achieved ultrathin HfO2 film holds an ultra-low EOT of 2.5 Å, in conjunction with a low leakage current of 10−6 A/cm2 at 1 V bias voltage, and possesses a robust breakdown electric field of ~22.3 MV/cm. We also demonstrate 8-inch wafer-scale 2D FETs and logic circuits employing 1.3-nm-HfO2 dielectrics with remarkable electrical performances. Our results not only offer valuable insights into further scaling of EOT, approaching the physical limits of dielectric thickness, but also represent a promising step towards the development of next-generation electronic devices.

Methods
Synthesis of ultrathin HfO2 film
First, we deposit 10 nm Au as the metal gate layer via E-beam evaporation on the cleaned 300 nm SiO2/Si substrate. Then, 0.5-nm-Ti is deposited on metal gates as the seeding layer for ALD of HfO2 dielectric layer. The ALD process is carried out in the Picosun R-200 Adv system. For the normal (one-step) ALD process, Tetrakis(ethylmethylamino)hafnium (TEMAH) and O3 serve as Hf sources and oxygen sources, respectively. The pulse (purge) time are 1.6 (25) s for TEMAH and 1.6 (30) s for O3. The carrier gas is pure N2 with a flow rate of 150 sccm for both TEMAH and O3. The TEMAH source is heated up to 125°C during the deposition. For the MOALD process, the deposition condition for the Hf source remains the same, while the oxygen sources are alternated between successive O3 and O2 plasmas. The pulse and purge times of O3 and O2 plasma are 1.6 and 25 s, respectively, with the O2 plasma operating at a power of 1500 W. Post-testing revealed film physical thickness of 1.3, 2.6, and 3.9 nm were achieved after 10, 20, and 30 cycles, respectively.

Sample characterizations
Raman and photoluminescence spectra are collected in Horiba Lab-Ram HR Evolution with a laser excitation wavelength of 532 nm and a power of 2 mW. Film thickness is measured by spectropic Mueller matrix ellipsometer ME-mapping. Scanning electron microscope images and cross-sectional STEM-HAADF images were obtained by Regulus 8100 and Thermo Fisher Spectra 300, respectively. AFM are performed by Oxford Instruments Asylum Research Cypher S. X-ray photoelectron spectroscopy measurements are conducted with the Thermo Fisher ESCALAB XI+.

Device fabrications and measurements
MoS2 FETs and logic gates are fabricated via standard microfabrication processes. Fabrications involve UV lithography, reactive ion etching and electron-beam evaporation to define device structures, etch MoS2 and deposit metal gate or contact, respectively. An 8-inch monolayer MoS2 film is transferred from sapphire to high-κ/metal gate by the PMMA-assisted method. For contact metal, Au/Ti/Au (3/2/30 nm) are deposited in vacuum at a base pressure of ~2 × 10−7 torr with a rate of 0.01 Å·s−1. All electrical measurements are performed in the Lake Shore probe station under 10−6 torr with a Keysight semiconductor analyzer B1500 equipped with high-resolution modules at room temperature.

Simulations
A “melt-quench” process and classical molecular dynamics (MD) are employed to generate initial amorphous structures41. Here, the initial HfO2 amorphous systems are generated using this melt-quench method with MD implemented in the LAMMPS software package42. The interatomic potential is considered as the charge-optimized many-body potential (COMB)43. The interatomic potential originally used a core-shell model with ionic charge +4 for Hf and −2 for O, respectively. The crystalline slab of HfO2 is made up of 4 × 5 × 4 supercells of P42/nmc HfO2 (a=b=3.587 Å and c=5.227 Å) with (100) plane facing upward. In this process, the crystalline systems are first heated up to 5000°C within 10 ps, held at this temperature for 50 ps, and then quenched to 300 K within 40 ps and again held for 10 ps. After getting the amorphous structures, these systems are further optimized and calculated for the electronic properties from the First-principles calculations.

First-principles calculations are mainly performed using the ABACUS package44, a DFT software based on numerical atomic orbitals (NAO)45. Generalized gradient approximation with the Perdew–Burke–Ernzerhof (PBE) functional and norm-conserving Vanderbilt (ONCV) pseudopotentials from SG15 set46,47 is employed to describe the exchange and correlation effects of the electrons. The numerical orbital sets adopt 4s2p2d2f1g for Hf and 2s2p1d for O48. For structure optimizations and densities of states calculation, the Brillouin zone is sampled with a Gamma-centered 2×3×1 mesh. The energy cutoff for the wavefunctions is set to 100 Ry.

Data availability
Relevant data supporting the key findings of this study are available within the article and the Supplementary Information file. All raw data generated during the current study are available from the corresponding authors upon request.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The authors have revised the manuscript and addressed some of the questions raised by the reviewers.\nIn general, I am good with the technical discovery of the paper. However, I am not very happy with the writing style of this paper which tries to over-claim too much. In particular, the authors mixed up the discussions of long and short channel devices. I could not find the SS for short channel FET in the paper but the authors keep emphasizing SS~ 60 that I believe that should only be the signatures of their long channel devices.\nIRDS roadmap for future devices should also refer to short-channel FET. The long channel SS ~62 is an irrelevant argument. The authors should try to clarify this in their manuscript, ensuring not misleading the readers.", "reviewer_4": "It is great that the authors have included top gated device performance in this version of the manuscript. Some questions need to be addressed before the manuscript can be recommended for publication:\n1. Figure 3 - back gated MoS2 FETs, Vt is negative, which is acceptable according to other published work. For Figure 4, how were the FET characteristics obtained? What was the voltage on the back gate Si/SiO2? Why is the Vt with top gate more positive than with back gate?\n2. Compare the current at the same Vg-Vt for back gate and top gate configurations. Seems like with top gate, the current is higher. Why? Is the MoS2 getting doped by Sb or the MOALD process?", "reviewer_5": "In the manuscript “Sub-3-A EOT High-k Dielectrics for Advanced Transistors”, the authors claim to demonstrate a gate dielectric with sub 3A EOT via an ALD process at 200C. The work is relevant, timely and highly interesting for the field of ultra-scaled nanoelectronics based on 2D materials as channels. However, there are several central points that are presented in a misleading way, which render the manuscript unsuitable for publication in its present form. A scholarly clear presentation that accurately states the key performance metrics (including statistics and error bars) and makes the work reproducible is essential. There are several major issues:\n1) The central claim of 2.5A EOT is based on capacitance-voltage measurements on Au-HfO2-Au MIM structures. However, in particular for ultra-thin gate dielectrics that should be used as gate dielectrics with van der Waals bonded 2D materials, like MoS2, the effective CET and EOT that will be measured on a MIS structure (i.e. Au-HfO2-MoS2) will be substantially different from the EOT measured on a MIM structure (i.e. Au-HfO2-Au) (see also Fig. 6a in A. Gaur et al., 2D Materials, 2019, 10.1088/2053-1583/ab20fb). However, what really matters for an ultra-scaled 2D field-effect transistor is the CET and EOT achieved in the actual gate stack, i.e. for the Au-HfO2-MoS2 system, as was also pointed out by reviewer 3. Hence, please report the following:\na) Measure capacitance(voltage) (C(V)) curves on the MIS stacks used for the back gated FETs in Fig. 3. Ideally report on the C(V) for different device areas and measure the capacitance for frequencies from kHz to MHz, for at least 5 different devices. Then please report on the average CET and EOT for these samples including error-bars.\nb) Measure C(V) curves on the MIS stacks used for the top gated FETs presented in Fig. 4. Again, report the C(V) curves for different device areas, for varying frequencies from kHz to MHz, for at least 5 different devices. Please report on the average CET and EOT for these samples.\nc) In Supplementary Fig. 13 you show a C(V) measurement. Is this for top or for back gated devices? What is the device area? Please also show the curve of capacitance (in microF) as a function of gate voltage before normalizing to the area. Are there overlap capacitances of the gate contact with source and drain contacts included? Please show an optical microscopy image where you measure the active area of the device that is used for normalization. The estimated CET is between 3.1A and 4.3A depending on the sweep frequency.\nd) Please create an overview Fig. like now presented in Fig. 2d where the CET and EOT values as measured on the MIM, and the 2 different MIS stacks (top and back gated) are compared directly (a Figure comparable to Fig. 6a in Gaur et al., 2D Materials, 10.1088/2053-1583/ab20fb).\ne) Please use in the title and consistently throughout the manuscript the EOT value that is consistently achieved for the MIS stacks in both the top gate and the back gate design. Hence, if e.g. an EOT of 0.5nm can be reached consistently, please use sub-5A EOT.\nf) Typically, the CET that is measured in a MIS stack is larger than the EOT, as there is an additional van der Waals gap between the 2D MoS2 and the HfO2. How large is the van der Waals gap between the MoS2 and the HfO2? What is the effective capacitance of the van der Waals gap Cvdw? Typically the van der Waals gap is on the order of about 0.3nm, much larger than the 0.05nm claimed in the rebuttal, see also Zhang et al., Nature Electronics 2022, 10.1038/s41928-022-00824-9.\ng) Finally, also the quantum capacitance of monolayer MoS2 limits the overall measured gate capacitance in highly scaled gate stacks, see also R. Bennett et al., Nano Letters 2023, 10.1021/acs.nanolett.2c03913. When using a MoS2 channel the gate capacitance is reduced due to the quantum capacitance. Also, I would heavily dispute the claim of the authors “CET considers more complicated conditions related to semiconductor interface and quantum capacitance.” In fact, EOT is an ideal number that refers to the dielectric constant and the physical thickness of the insulator, whereas CET reflects the actual physical gate control aimed for. Hence, CET is the number specified in the IRDS, that should be smaller than 0.9nm for advanced technology nodes (see https://irds.ieee.org/editions/2023/20-roadmap-2023-edition/130-irds%E2%84%A2-2023-more-moore).\n2) What is the thickness of the gate insulator used for the top gate configuration presented in Fig. 4? About 1nm SbOx and about 2nm HfO2? Please indicate the layer thicknesses together with the probable dielectric constants of both components of the gate stack (SbOx and HfO2) as well as the CET. The CET and EOT for the combined gate stack is certainly larger than 0.5nm - which is fine, as long as it is clearly stated.\n3) As pointed out by Reviewer 2, comment 3, the previously reported DFT calculations based on PBE functionals severely underestimated the HfO2 band gap. The authors use DFT calculations to study the impact of oxygen vacancies on the band structure. However, this methodology has one major flaw. In fact they are investigating the impact of oxygen vacancies on crystalline HfO2. In reality the HfO2 films investigated are (as most HfO2 dielectrics used) amorphous. In order to study amorphous films with DFT one needs to use packages that can handle large supercell calculations like CP2K and a melt and quench method, see for example J. Strand et al., J. Phys. Cond. Matter 2018, 10.1088/1361-648X/aac005. I do not think that the DFT calculations performed for crystalline HfO2 have any meaning for the amorphous HfO2 films investigated. Hence, please either repeat your calculations for amorphous HfO2 supercells or completely remove the paragraph about oxygen vacancies and the DFT data from the supplementary information.\n4) As pointed out by Reviewer 2, comment 4 the authors talk about FN vs direct tunneling but do not show any modeled leakage currents. Please include a calculated tunnel current based on FN tunneling, direct tunneling or a combination of both of them according to a Tsu-Esaki model, see also Tsu et al., Applied Phys, Letters 1973, 10.1063/1.1654509 or T. Knobloch et al., Nature Electronics 2021, 10.1038/s41928-020-00529-x. Please calculate the tunneling currents using a model for direct tunneling. In this way the authors will also see that the statement “The direct tunneling current is suppressed below the detection limit due to the large bandgap and high-quality of the sample.” is just plainly wrong. The direct tunnel currents depend a lot on the dielectric thickness and the effective tunnel masses (see for example F. Sacconi et al., IEEE TED 2007, 10.1109/TED.2007.908880) and will be sizable for a film of only 1.3nm thickness - even in the theoretical case without any defects, or trap assisted tunneling.\n5) In Figure 2c for evaluating the capacitance of MIM structures the C(V) curves should be shown at least up to +- 0.6V. Ideally the capacitance on at least 5 devices should be compared as well as the leakage currents on 5 MIM structures in a range from +- 0.6V.\n6) As pointed out by Reviewer 2, comment 12, please show a cross section of your devices, including all the dimensions. The Fig 3a in the new manuscript includes an artistic representation but I am still missing many important device dimensions, i.e. contact length, overall gated area, BG Au thickness, HfO2 thickness used for devices, source/drain dimensions (i.e. width, length, thickness), overlap areas of contacts with back gate etc. Please include an optical microscopy image and/or a simple 2D schematic including all important dimensions.\n7) The subthreshold swing that the authors report should be averaged over at least 2 decades of current, see also Z. Cheng et al. Nature Electronics 2022, doi:10.1038/s41928-022-00798-8. Taking the minimum value of SS at a small drain current of 1e-4 uA/um is meaningless. Please average over 2-3 decades in Fig. 3e and update Fig. 3g accordingly.\n8) I do not see any evidence presented for the allegedly negligible hysteresis. Please show a double-sweep IdVg for a range of different sweep frequencies. Also the hysteresis is typically evaluated close to the threshold voltage. As the hysteresis depends strongly on the sweep frequency a small hysteresis at one frequency cannot give a meaningful conclusion about the hysteresis further away. Please evaluate the hysteresis width as a function of the sweep frequency spanning at least 2 orders of magnitude in sweep frequency, see for example Illarionov et al., npj 2D Mater. Appl. 2024, 10.1038/s41699-024-00445-0.\nAnd a few minor issues:\n9) When responding to reviewer 2, question 7, the authors included in the rebuttal FigR12 c and d. In particular Fig. R12d should be included either in the main manuscript or the supplementary including a scale bar. What is the width and length of the devices used for the circuits? What is the active area covered by the back gate and the MoS2?\n10) The optical images shown in Fig. 5e, 5h and 5j are taken with a large magnification. It would be much more relevant to use a magnification where one can see one cell of an inverter, one cell of an AND logic gate etc., hence please zoom in more and include these images instead."}, "author_response": "We thank the referee for their critical feedback. We have corrected some exaggerated statements in the revised manuscript, such as SS is 60 mV/dec. According to the referee’s suggestion, we have also included the SS data in short channel devices, as shown in the below Fig. R1. In this device, the channel length is 100 nm. From 10-4 µA/µm to 10-2 µA/µm, The SS value is ~70 mV/dec as shown in the Fig. R1 and Supplementary Fig. 16 in line 29, page 7 in revised manuscript: “The sweeping measurements (Fig. 3h) also indicate an exceedingly small hysteresis (<10 mV) and low SS value (70 mV/dec, Supplementary Fig. 16).”\n\nWe thank the referee for their positive comment on the inclusion of the top-gated device data. We have addressed all the specific questions raised below point-by-point in the revised manuscript and believe these changes have further improved the quality of our work.\n1. Figure 3 - back gated MoS FETs, V is negative, which is acceptable according to other published work. For Figure 4, how were the FET characteristics obtained? What was the voltage on the back gate Si/SiO ? Why is the V with top gate more positive than with back gate?\nResponse: We thank the referee for these insightful questions. Regarding the measurement configuration for the top-gated FETs in Figure 4, the device characteristics were obtained by applying a voltage solely to the top gate (Au), with the SbOₓ/HfO₂ bilayer serving as the gate dielectric. The back gate Si/SiO was electrically floated (i.e., no voltage was applied) during these measurements to ensure that the recorded performance reflects the electrostatic control of the top gate only.\nThe observed positive shift in the Vₜ for the top-gated device, compared to the back-gated one, is a key finding. We attribute this shift primarily to the incorporation of oxygen doping within the MoS channel during the fabrication of the top-gate stack. This intentional doping introduces n-type carriers, which effectively shifts the turn-on voltage in the positive direction. This method of threshold voltage modulation via channel doping is well-established, as supported by prior literature (e.g., Small 16, 2004276 (2020)).\n2. Compare the current at the same V -V for back gate and top gate configurations. Seems like with top gate, the current is higher. Why? Is the MoS getting doped by Sb or the MOALD process?\nResponse: We thank the referee for their comment. Output curves for back and top-gated transistors in Fig. 3d and Fig. 4h show that the current for back-gate transistors (25 µA/µm) is larger than that for top-gated transistors (15 µA/µm) under the same 0.5 V source voltage and 1 V V -V. The reason may come from the small contact resistance variation (Nature 613, 274–279 (2023)) or gate controllability difference (0.34 nm CET for back-gated devices and 0.50 nm CET for top-gated devices).\n\nThank the referee for highlighting the need for greater clarity and precision in our manuscript. We sincerely apologize for any misleading impressions in our original presentation. We have thoroughly revised the manuscript to address these concerns with utmost seriousness.\n1) The central claim of 2.5Å EOT is based on capacitance-voltage measurements on Au-HfO -Au MIM structures. However, in particular for ultra-thin gate dielectrics that should be used as gate dielectrics with van der Waals bonded 2D materials, like MoS , the effective CET and EOT that will be measured on a MIS structure (i.e. Au-HfO -MoS ) will be substantially different from the EOT measured on a MIM structure (i.e. Au-HfO -Au) (see also Fig. 6a in A. Gaur et al., 2D Materials, 2019, 10.1088/2053-1583/ab20fb). However, what really matters for an ultra-scaled 2D field-effect transistor is the CET and EOT achieved in the actual gate stack, i.e. for the Au-HfO -MoS system, as was also pointed out by reviewer 3. Hence, please report the following:\nResponse: We acknowledge careful review by the referee. We totally agree that the CET and EOT achieved in the actual gate is that really matters.\na) Measure capacitance(voltage) (C(V)) curves on the MIS stacks used for the back gated FETs in Fig. 3. Ideally report on the C(V) for different device areas and measure the capacitance for frequencies from kHz to MHz, for at least 5 different devices. Then please report on the average CET and EOT for these samples including error-bars.\nResponse: We thank the referee for this insightful and constructive suggestion. We agree that a detailed characterization of the MIS (Metal-Insulator-Semiconductor) capacitor stacks is crucial for a complete understanding of the device performance presented in Fig. 3. According to the referee's suggestion, we have performed comprehensive Capacitance-Voltage (C-V) measurements on these structures.\nThe C-V measurements were performed on MIS capacitor structures. The voltage was swept from accumulation to inversion (from 0 V to 1 V for MoS FETs with 1.3 nm HfO dielectrics; from 0 V to 1.5 V for MoS FETs with 2.6 nm HfO dielectrics; from 0 V to 2 V for MoS FETs with 3.9 nm HfO dielectrics). Measurements were conducted on 5 devices with varying areas (from 40 μm2 to 200 μm2 depending on devices) at multiple frequencies ranging from 5 kHz to 1 MHz. The representative C-V characteristics are presented in Fig. R1~R3 and Supplementary Fig. 13-15 in the revised Supplementary Materials.\nFrom the accumulation capacitance (C ) measured at 1 MHz, we calculated the CET using the formula for a parallel plate capacitor: CET=C ϵ /A. The extracted CET values for 5 representative devices are summarized in Table R1. These measurements show an average CET of 0.34 ± 0.01 nm for 1.3 nm HfO dielectrics, 0.47± 0.03 nm for 2.6 nm HfO dielectrics, 0.66± 0.03 nm for 3.9 nm HfO dielectrics. The small standard deviation across multiple devices highlights the uniformity and reproducibility of our dielectric deposition process. We believe these additional data and analyses substantially strengthen the paper by providing a quantitative evaluation of the gate stack, which directly supports the high-performance FET characteristics presented. We once again thank the referee for their valuable advice.\nb) Measure C(V) curves on the MIS stacks used for the top gated FETs presented in Fig. 4. Again, report the C(V) curves for different device areas, for varying frequencies from kHz to MHz, for at least 5 different devices. Please report on the average CET and EOT for these samples.\nResponse: We thank the referee for their continued diligence and for the excellent suggestion to characterize the top-gated MIS stacks. This provides a direct assessment of the gate module quality for the devices presented in Fig. 4. In response, we have conducted the requested C-V measurements on the top-gated structures at five devices with different areas, sweeping the frequency from 5 kHz to 1 MHz as shown in the following Fig. R4 and Supplementary Fig. 15 in the revised Supplementary Materials. Based on these results, the average CET for the top-gated stack is 0.50 ± 0.01 nm. The consistent values obtained across the wafer underscore the robustness of our fabrication process. We are confident that this additional characterization provides a more complete and robust validation of our device quality. We thank the referee for pushing for this higher standard of evidence.\nc) In Supplementary Fig. 13 you show a C(V) measurement. Is this for top or for back gated devices? What is the device area? Please also show the curve of capacitance (in microF) as a function of gate voltage before normalizing to the area. Are there overlap capacitances of the gate contact with source and drain contacts included? Please show an optical microscopy image where you measure the active area of the device that is used for normalization. The estimated CET is between 3.1Å and 4.3Å depending on the sweep frequency.\nResponse: We thank the referee for these insightful and detailed questions regarding the C-V characterizations. The C-V measurement in the former Supplementary Fig. 13 was indeed performed on a complete gate-first FET structure. As the referee noted, and as confirmed by the optical image in Fig. R5, this device configuration includes significant gate-to-source/drain overlap. We fully agree that the parasitic capacitance introduced by this overlap leads to an artificially inflated total capacitance measurement and, consequently, an underestimation of the true CET. To address this critical point and accurately determine the intrinsic properties of our gate dielectric, we have fabricated and characterized new MIS capacitor test structures that are free from any overlap. The complete and rigorous characterization of these new devices is now presented in the revised manuscript and the above Figs. R1-R4.\nd) Please create an overview Fig. like now presented in Fig. 2d where the CET and EOT values as measured on the MIM, and the 2 different MIS stacks (top and back gated) are compared directly (a Figure comparable to Fig. 6a in Gaur et al., 2D Materials, 10.1088/2053-1583/ab20fb).\nResponse: Per the referee's recommendation, we have created a new overview figure (Fig. R6), which has been added to the revised Supplementary Materials as Supplementary Fig.20.\ne) Please use in the title and consistently throughout the manuscript the EOT value that is consistently achieved for the MIS stacks in both the top gate and the back gate design. Hence, if e.g. an EOT of 0.5nm can be reached consistently, please use sub-5Å EOT.\nResponse: We thank the referee for this excellent suggestion to improve the consistency and impact of our manuscript. Based on the comprehensive C-V analysis presented for both our top-gated and back-gated MIS stacks, we can confirm that an EOT of approximately 0.5 nm is consistently achieved. Following the referee's valuable guidance, we have adopted the \"sub-5Å EOT\" metric to describe this key achievement.\nf) Typically, the CET that is measured in a MIS stack is larger than the EOT, as there is an additional van der Waals gap between the 2D MoS and the HfO . How large is the van der Waals gap between the MoS and the HfO ? What is the effective capacitance of the van der Waals gap C ? Typically the van der Waals gap is on the order of about 0.3nm, much larger than the 0.05nm claimed in the rebuttal, see also Zhang et al., Nature Electronics 2022, 10.1038/s41928-022-00824-9.\nResponse: We sincerely thank the referee for the expertise on this critical topic and for pointing out the important role of the van der Waals (vdW) gap. The referee is correct that the physical van der Waals (vdW) gap is typically on the order of 0.3 to 0.35 nm (3.0 to 3.5 Å). Assuming the vdW gap is essentially a vacuum, its dielectric constant (k ) is ≈ 1. We can then calculate its capacitance per unit area (C /A) and its contribution to the EOT (EOT ). This analysis shows that the vdW gap makes a very significant contribution of ~1.17 nm to the total measured EOT. However, for accurate electrostatic and capacitance calculations, one must use the electrical-equivalent gap, which is significantly smaller. As demonstrated by Vaidya et al., the tails of the ionic potentials from the 2D material protrude into the interlayer gap, greatly reducing the effective electrical separation compared to the physical one (Phys. Rev. Applied 10, 034070). The paper shows that a physical separation of 3.0 Å (0.3 nm) corresponds to an electrical-equivalent separation of just 0.6 Å (0.06 nm). This also explains why in some literature reports, despite the existence of vdW gap, CET is still less than 1nm. (Nat. Electron. 7, 1126–1136 (2024), and Nature 605, 262–267 (2022).)\ng) Finally, also the quantum capacitance of monolayer MoS limits the overall measured gate capacitance in highly scaled gate stacks, see also R. Bennett et al., Nano Letters 2023, 10.1021/acs.nanolett.2c03913. When using a MoS channel the gate capacitance is reduced due to the quantum capacitance. Also, I would heavily dispute the claim of the authors “CET considers more complicated conditions related to semiconductor interface and quantum capacitance.” In fact, EOT is an ideal number that refers to the dielectric constant and the physical thickness of the insulator, whereas CET reflects the actual physical gate control aimed for. Hence, CET is the number specified in the IRDS, that should be smaller than 0.9nm for advanced technology nodes (see https://irds.ieee.org/editions/2023/20-roadmap-2023-edition/130-irds%E2%84%A2-2023-more-moore).\nResponse: We thank the referee for their comment. In line 10, page 2 in revised manuscript, we have modified the sentence as “EOT of a high-κ dielectric refers to the equivalent thickness of a SiO film having the same specific capacitance with the high-κ dielectric film, while capacitance equivalent thickness (CET) reflects the actual physical gate controllability in devices.”\n2) What is the thickness of the gate insulator used for the top gate configuration presented in Fig. 4? About 1nm SbO and about 2nm HfO ? Please indicate the layer thicknesses together with the probable dielectric constants of both components of the gate stack (SbO and HfO ) as well as the CET. The CET and EOT for the combined gate stack is certainly larger than 0.5nm - which is fine, as long as it is clearly stated.\nResponse: We thank the referee for this question. As shown in the line 11, page 8, we have demonstrated the vertical structure of the top-gated devices as “The total thickness of the device is only ~3 nm, including 0.7 nm MoS , 1 nm SbO seeding layer and 1.3 nm HfO , which is confirmed with CS-TEM and STEM-EDS mapping (Fig. 4e and 4f).” The CET is measured as ~ 0.50 nm and presented in the above Fig. R4. The dielectric constant is ~17.9.\n3) As pointed out by Reviewer 2, comment 3, the previously reported DFT calculations based on PBE functionals severely underestimated the HfO band gap. The authors use DFT calculations to study the impact of oxygen vacancies on the band structure. However, this methodology has one major flaw. In fact they are investigating the impact of oxygen vacancies on crystalline HfO . In reality the HfO films investigated are (as most HfO dielectrics used) amorphous. In order to study amorphous films with DFT one needs to use packages that can handle large supercell calculations like CP2K and a melt and quench method, see for example J. Strand et al., J. Phys. Cond. Matter 2018, 10.1088/1361-648X/aac005. I do not think that the DFT calculations performed for crystalline HfO have any meaning for the amorphous HfO films investigated. Hence, please either repeat your calculations for amorphous HfO supercells or completely remove the paragraph about oxygen vacancies and the DFT data from the supplementary information.\nResponse: Thanks for the reviewer’s comments. HfO serves as a high dielectric layer in CMOS and MIM systems. It was often studied in amorphous form. So, we recalculate the bandgaps and densities of states (DOS) of HfO under amorphous structures. In previous results, we have compared the effects of HSE and PBE functionals to bandgaps in HfO . So here we directly use PBE functional to calculate the electronic properties. We find that the measured bandgaps keep the same variation law, which validates the reliability of the changes of bandgaps when increasing O vacancies concentrations. The bandgaps were measured with the help of inverse participation ratio (IPR) of densities of states, which can reflect the localization degree of densities of states (DOS). In amorphous structures, due to the disorder, the band edges often show localized electronic states. Compared with crystalline structure, the bandgap (E ) becomes mobility bandgap (ME ), and the valence band maximum and conduction band minimum are switched as valence band mobility edge (VBME) and conduction band mobility edge (CBME). Thus, here we use IPR to analyze the band edge of amorphous structure. In our analysis, the mid-energy points of the IPR within the valence and conduction bands were designated as the valence band mobility edge (VBME) and conduction band mobility edge (CBME), respectively. Consequently, the resulting mobility band edges and mobility bandgap, which were found to decrease systematically with increasing oxygen vacancy concentration. The original conclusion in the part remains unchanged in revised manuscript.\n4) As pointed out by Reviewer 2, comment 4 the authors talk about FN vs direct tunneling but do not show any modeled leakage currents. Please include a calculated tunnel current based on FN tunneling, direct tunneling or a combination of both of them according to a Tsu-Esaki model, see also Tsu et al., Applied Phys, Letters 1973, 10.1063/1.1654509 or T. Knobloch et al., Nature Electronics 2021, 10.1038/s41928-020-00529-x. Please calculate the tunneling currents using a model for direct tunneling. In this way the authors will also see that the statement “The direct tunneling current is suppressed below the detection limit due to the large bandgap and high-quality of the sample.” is just plainly wrong. The direct tunnel currents depend a lot on the dielectric thickness and the effective tunnel masses (see for example F. Sacconi et al., IEEE TED 2007, 10.1109/TED.2007.908880) and will be sizable for a film of only 1.3nm thickness - even in the theoretical case without any defects, or trap assisted tunneling.\nResponse: We thank the reviewer for these insightful and constructive comments. We fully agree that the leakage current depends on multiple factors beyond the bandgap, including the effective tunneling mass, barrier height, and dielectric thickness. Based on our previous experience, we found that the WKB or Tsu–Esaki tunneling models are most reliable for relatively thick dielectric layers, where transport is dominated by bulk-like barrier transmission. In the present case with an ultrathin dielectric layer of ~1.3 nm, the tunneling process is strongly influenced by interfacial atomic configurations and the overlap between the electronic wavefunctions of the contact and dielectric layers. Such effects cannot be accurately captured by simple analytical models with homogeneous barrier parameters, which are typically calibrated for thicker systems. A rigorous and quantitative description of tunneling in this ultrathin regime would require atomistic-level transport simulations (for example, first-principles nonequilibrium Green’s function calculations) that explicitly include the contact–dielectric interfaces. These simulations are highly computationally demanding and beyond the current scope of this work, which primarily focuses on the experimental demonstration and characterization of the dielectric properties. Nevertheless, we fully recognize the importance of such modeling and plan to pursue detailed atomistic simulations in our future studies to further understand the interface-dependent tunneling mechanisms. In the present work, the experimentally observed suppression of leakage current is consistent with the large bandgap of the dielectric with minimal oxygen vacancies and the oxygen-rich surface, which effectively reduces wavefunction overlap at the contact–dielectric interface. We have clarified these points in the revised manuscript.\n5) In Figure 2c for evaluating the capacitance of MIM structures the C(V) curves should be shown at least up to +- 0.6V. Ideally the capacitance on at least 5 devices should be compared as well as the leakage currents on 5 MIM structures in a range from +- 0.6V.\nResponse: We thank the referee for this valuable feedback, which will certainly help improve the clarity and completeness of our results. We agree that providing a wider voltage range and a statistical analysis of device performance is essential. As shown in Fig. R11, Fig. 2c and Supplementary Fig. 8a in the revised manuscript, we have re-measured the MIM capacitance and leakages.\n6) As pointed out by Reviewer 2, comment 12, please show a cross section of your devices, including all the dimensions. The Fig 3a in the new manuscript includes an artistic representation but I am still missing many important device dimensions, i.e. contact length, overall gated area, BG Au thickness, HfO thickness used for devices, source/drain dimensions (i.e. width, length, thickness), overlap areas of contacts with back gate etc. Please include an optical microscopy image and/or a simple 2D schematic including all important dimensions.\nResponse: We thank the referee for this comment. We have added dimensions in revised device schematic illustration. Optical image is also shown in Fig. R12 and Supplementary Fig. 11 revised Supplementary materials.\n7) The subthreshold swing that the authors report should be averaged over at least 2 decades of current, see also Z. Cheng et al. Nature Electronics 2022, doi:10.1038/s41928-022-00798-8. Taking the minimum value of SS at a small drain current of 1e-4 uA/um is meaningless. Please average over 2-3 decades in Fig. 3e and update Fig. 3g accordingly.\nResponse: We have re-estimated and updated the SS value as shown in Fig. R13 and updated Fig. 3g in revised manuscript.\n8) I do not see any evidence presented for the allegedly negligible hysteresis. Please show a double-sweep I V for a range of different sweep frequencies. Also the hysteresis is typically evaluated close to the threshold voltage. As the hysteresis depends strongly on the sweep frequency a small hysteresis at one frequency cannot give a meaningful conclusion about the hysteresis further away. Please evaluate the hysteresis width as a function of the sweep frequency spanning at least 2 orders of magnitude in sweep frequency, see for example Illarionov et al., npj 2D Mater. Appl. 2024, 10.1038/s41699-024-00445-0.\nResponse: Thank you for these valuable suggestions. We have included the hysteresis data under sweep frequency of 0.01 V/s, 0.01 V/s and 0.1 V/s, as shown in Fig. R14 and Supplementary Fig. 12 in revised manuscript. A small hysteresis of 11 mV, 9 mV and 11 mV are obtained at current of 1nA, which is slightly dependent on the sweeping frequency.\nAnd a few minor issues:\n9) When responding to reviewer 2, question 7, the authors included in the rebuttal FigR12 c and d. In particular Fig. R12d should be included either in the main manuscript or the supplementary including a scale bar. What is the width and length of the devices used for the circuits? What is the active area covered by the back gate and the MoS ?\nResponse: We acknowledge the referee’s feedback. We have added former Fig. R12c and R12d into Supplementary Fig. 22 in revised manuscript (Fig. R15 below). The width and length of the devices for circuits are 10 µm and 30 µm, respectively. Back gate covered all active area and MoS , around 600 µm2.\n10) The optical images shown in Fig. 5e, 5h and 5j are taken with a large magnification. It would be much more relevant to use a magnification where one can see one cell of an inverter, one cell of an AND logic gate etc., hence please zoom in more and include these images instead.\nResponse: We thank the referee’s suggestions. We have added enlarging optical images in Fig. 5e, 5h and 5j in Fig. R16 and updated Fig. 5 the revised manuscript."}, {"round": 2, "reviewer_comments": {"reviewer_5": "In the manuscript “Sub-5-Å EOT High-κ Dielectrics for Advanced Transistors” the authors present an extremely scaled gate dielectric. During the previous review round, the authors provided comprehensive additional C(V) measurement data to improve the reproducibility of this very relevant and timely study. In general, I think that the study improved considerably by the revisions made. However, I agree with the other reviewers that still I am not happy with the language and the metrics used to present the paper. I think the authors are unnecessarily overselling the performance of their devices, thereby misleading the readers. In particular, please address the following issues:\n1) As mentioned by reviewer 1 the long channel minimum subthreshold slope of ~62mV/dec is irrelevant. The relevant metric is the averaged subthreshold slope over at least 2 orders of magnitude (better 5 or more) for the short channel devices, see the IRDS Roadmap (https://irds.ieee.org/editions), which is about 110mV/dec based on the data shown in Fig. 16. Please remove the claim of 60mV/dec. from the abstract. (p1, line 37). The same holds true for Fig. 4k - please compare instead of the minimum subthreshold slope, the average subthreshold slope, as this is the relevant and well reproducible metric. Please also remove the ideal SS claim from line 272 and instead give the average SS.\n2) Can you please briefly comment on the more positive Vt for the top gated FETs in comparison to back gated FETs and the comparable albeit slightly smaller on current level for top gated FETs in the main text? I think the answers to the points raised by Referee 4 are accurate and sufficient but should be briefly, ie. in one sentence each be reflected in the main text.\n3) I think that all the C(V) data reported now in the Supplementary in response to the previous review round is a major improvement of the manuscript. However, these changes are mostly presented in the Supplementary, I would suggest the following changes in the main manuscript. Please include as additional figures in Fig. 2 the C(V) data, for example, please add Supplementary Fig. 13 a and f as well as Supp. Fig. 20. As stated before, the CET value is much more relevant than the small EOT. As the small CET/EOT is one of the main achievements of the work presented, I would argue that supplementary Fig. 20 is from my perspective one of the most important figures of the whole manuscript and should be presented alongside some of the raw C(V) curves that were evaluated to create this Figure in the main manuscript."}, "author_response": "We sincerely thank the reviewer for acknowledging the improvements made in the previous round. We take your concerns regarding the language, metrics, and the presentation of our results very seriously. We realize that our previous enthusiasm for the results may have led to subjective phrasing that detracted from the scientific objectivity of the study.\nIn this revision, we have thoroughly rewritten the manuscript to adhere to a strictly objective tone. We have removed subjective qualifiers and \"overselling\" claims. Point-by-point responses are listed below.\n1) As mentioned by reviewer 1 the long channel minimum subthreshold slope of ~62mV/dec is irrelevant. The relevant metric is the averaged subthreshold slope over at least 2 orders of magnitude (better 5 or more) for the short channel devices, see the IRDS Roadmap (https://irds.ieee.org/editions), which is about 110 mV/dec based on the data shown in Fig. 16. Please remove the claim of 60 mV/dec. from the abstract. (p1, line 37). The same holds true for Fig. 4k - please compare instead of the minimum subthreshold slope, the average subthreshold slope, as this is the relevant and well reproducible metric. Please also remove the ideal SS claim from line 272 and instead give the average SS.\nResponse: We acknowledge that for short-channel devices, the minimum subthreshold slope (SS ) does not adequately represent the device's switching performance. We agree that the average subthreshold slope (SS ), extracted over several decades of drain current, is the scientifically rigorous metric, consistent with the benchmarks set by the IRDS Roadmap. To address this, we have revised the manuscript to strictly report SS instead of SS for our short-channel devices. Specifically: 1. Abstract (Page 1, Line 38): We have removed the claim of 62 mV/dec (which corresponded to the minimum value). We now state the SS value of 75 mV/dec, which represents the average slope over 3 decades of current. 2. Figure 4i Revision: We have redrawn Figure 4i. Instead of comparing the \"best-case\" SS , we now benchmark our device against the state-of-the-art using SS (71 mV/dec) as the metric. This provides a fair and reproducible comparison. 3. Line 221 Revision: We have deleted the phrase \"ideal SS\". The text now reads: \" Fig. 4g shows the transfer curve of an as-fabricated gate-last MoS transistor, revealing a high on/off ratio of 108 and average SS of 71 mV/dec\". We believe these changes eliminate the ambiguity and \"overselling\" concerns, providing a transparent view of the device physics and performance.\n2) Can you please briefly comment on the more positive Vt for the top gated FETs in comparison to back gated FETs and the comparable albeit slightly smaller on current level for top gated FETs in the main text? I think the answers to the points raised by Referee 4 are accurate and sufficient but should be briefly, ie. in one sentence each be reflected in the main text.\nResponse: As suggested, we have incorporated the explanations provided in our previous response to Referee 4 directly into the main text. We have added two concise sentences to the revised manuscript in Line 223 to clarify the physical origins of the positive V shift and the slightly reduced I in the gate-last configuration: “Note that the V is more positive in gate-last transistors than that in gate-first transistors. We attribute this shift primarily to the incorporation of oxygen doping within the MoS channel during the fabrication of the gate-last stacks. This doping introduces n-type carriers, which effectively shifts the turn-on voltage in the positive direction7. The output curves of this device is shown in Supplementary Fig. 19, illustrating a high current density of 15 µA/µm at 0.5 V source bias, which is slightly smaller than that in gate-first transistors. The reason may come from the small contact resistance variation38 or gate controllability difference between 0.34 nm CET for gate-first devices and 0.50 nm CET for gate-last devices.”\n3) I think that all the C(V) data reported now in the Supplementary in response to the previous review round is a major improvement of the manuscript. However, these changes are mostly presented in the Supplementary, I would suggest the following changes in the main manuscript. Please include as additional figures in Fig. 2 the C(V) data, for example, please add Supplementary Fig. 13 a and f as well as Supp. Fig. 20. As stated before, the CET value is much more relevant than the small EOT. As the small CET/EOT is one of the main achievements of the work presented, I would argue that supplementary Fig. 20 is from my perspective one of the most important figures of the whole manuscript and should be presented alongside some of the raw C(V) curves that were evaluated to create this Figure in the main manuscript.\nResponse: We appreciate this suggestion and fully agree. We recognize that the aggressive scaling of the dielectric (sub-5 Å EOT) is the central achievement of this work, and the supporting C-V measurements are indeed the most critical evidence. Per your recommendation, we have significantly restructured Figs. 3 and 4 in the main manuscript to include the key C-V characterization data: 1. Raw C-V Data: We have moved the representative raw C-V curves (previously Supplementary Figs. 13c, 13f, 14d and 15a) into the main text as Figs. 3h~3k. This allows readers to directly assess the quality and frequency dispersion of the dielectric capacitance. 2. CET Scaling Trend: We agree that the Capacitance Equivalent Thickness (CET) is the more direct and robust metric compared to the derived EOT. We have moved the CET vs. Thickness plot (previously Supplementary Fig. 20) to Fig. 4j. This figure now clearly demonstrates the scaling trend and validates the sub-5 Å EOT extraction alongside the measured CET values. By moving these figures to the main text, we believe the manuscript now provides a much more compelling and transparent demonstration of the dielectric performance."}]

Decision letter