Decoding correlated errors in quantum LDPC codes

Domain: physics
Published: 2026-03-14
Editorial outcome: minor_revision

Abstract
We introduce a decoding framework for correlated errors in quantum LDPC codes under circuit-level noise. Our approach is a graph augmentation and rewiring for inference (GARI) method, which modifies the correlated detector error model by eliminating 4-cycles involving Y-type errors, while preserving the equivalence of the decoding problem. A normalized min-sum decoder with a hybrid serial-layered schedule is applied on the transformed graph, achieving high accuracy with low latency. Performance is further enhanced (on par with XYZ-Relay-BP) through ensemble decoding, where 24 randomized normalized min-sum decoders run in parallel on the transformed graph. For the distance 12 Bivariate Bicycle code the logical error rate of (6.70±1.93)×10−9 is achieved at a physical error rate of 10−3. Furthermore, preliminary FPGA implementation results show that such high accuracy can be achieved in real time, with a per-round average decoding latency of 273ns and sub-microsecond latency in 99.99% of the decoding instances.

Introduction
Quantum low-density parity-check (QLDPC) codes have recently emerged at the forefront of quantum error correction (QEC) research. Early interest was driven by the demonstration of constant-overhead fault tolerance using QLDPC codes [1], which spurred the search for code families that surpass the limitations of previous constructions defined by geometrically local stabilizers [2]. These efforts have progressively advanced QLDPC code constructions [3–9], resulting in asymptotically good families [10–12] (i.e., with non-vanishing rate and linear minimum distance), as well as practically implementable codes tailored to the constraints of specific quantum technologies [13, 14].

However, beyond code parameters and compatibility with quantum technology constraints, the merit of a QEC code also hinges on its practical decodability. At first glance, this may seem like good news for QLDPC codes, since decoding is what drove the remarkable success of their classical counterparts [15]. Unfortunately, message-passing (MP) decoding algorithms – a class of lightweight iterative algorithms with linear time complexity per iteration – that are effective for classical codes fail in the quantum setting. Indeed, for classical LDPC codes, both the theoretical and the practical significance of MP algorithms stems from their ability to perform optimal inference on cycle-free factor graphs (bipartite graphs representing the factorization of a joint probability distribution), where marginal probabilities and max-marginals can be computed via belief-propagation (BP) and min-sum (MS) algorithms, respectively [16] (note that BP is also known as sum-product). In decoding terms, maximum a posteriori (MAP) decoding is realized via BP, while maximum likelihood (ML) decoding is realized via MS [17]. And even though practical LDPC codes are defined by graphs with cycles, they locally resemble cycle-free graphs: their girth (the length of the shortest cycle) grows at the optimal rate Θ(logn), where n is the code length. For QLDPC codes, the situation is markedly different: their low-weight stabilizers – the very property that makes them suitable for fault-tolerance – typically lead to graphs with girth of Θ(1), causing MP decoders to fail at producing sufficiently accurate inference [18].

Previous works have explored various strategies to improve MP decoding performance, particularly through combinations with post-processing techniques such as ordered-statistics decoding (OSD) [6]. This approach is usually referred to in the literature as BPOSD rather than MPOSD, even though BP decoding is rarely used and the best performance is typically achieved with normalized MS decoding [6, 19, 20]. Several subsequent works have continued to use the BP terminology in the more general sense of “propagating belief messages” – that is, message passing – regardless of whether the underlying inference would, in the cycle-free case, correspond to marginal probabilities or max-marginals. In deference to the original works and to avoid any possible confusion, we adopt the same terminology as that used in the original papers whenever referring to previous literature.

BPOSD quickly established itself as an almost universal solution [20], capable of decoding both code-capacity and circuit-level noise models, with an accuracy that remained the benchmark for some time. However, it relies on Gaussian elimination to produce the error estimate, which limits both parallelization and scalability for real-time applications, even on dedicated hardware [21, 22]. This has prompted the development of alternative approaches, which can be broadly classified into the following three categories: (1) Simplified post-processing methods, building upon or refining inversion-based or clustering approaches: e.g., localized statistics decoding [23], ordered Tanner forest decoding [24], closed branch decoding [25], ambiguity clustering [26]; (2) Heuristic methods for improving the MP decoding performance by modifying the decoding rules: e.g., guided decimation guessing [27], collaborative check removal [28], symmetry-breaking techniques [29], refined or memory BP [30, 31], MP decoders with past influence [32]; (3) Diversity or ensemble-decoding techniques, which combine multiple decoders to improve overall performance and mitigate individual decoder failures: e.g., automorphism ensemble decoding [33] or Relay-BP [34]. Some approaches span multiple categories, e.g., stabilizer inactivation [19], check-agnosia [21], or speculative decoding [35], which are simplified post-processing methods, where the post-processing is based on ensemble MP-decoding.

These methods still face major limitations, including high resource demands and reduced performance when decoding correlated errors (i.e., correlations between X, Y, and Z errors). For instance, Ref. [36] shows that BPOSD is limited by its inability to decode correlated errors, as BP struggles with short cycles in the correlated detector error model, providing misleading information to the OSD post-processor. The XYZ-Relay-BP decoder [34] efficiently handles correlated errors, significantly outperforming BPOSD, by employing an ensemble decoding approach that uses a large number of BP decoders sequentially. Nevertheless, while the approach can be regarded as a lightweight MP decoder, its sequential nature may result in increased latency.

Graph-search-based decoders such as Tesseract [36] and decision-tree decoders [37] have emerged as promising solutions, providing the most accurate decoding of correlated errors reported so far. However, this comes at the cost of increased complexity, which may preclude their use in large-scale applications.

Short cycles (the shortest and most harmful being the 4-cycle) can lead to early error floors, where the decoder becomes trapped on certain error patterns [36, 38], causing a shallower – potentially nearly flat – decline in the logical error rate as the physical error rate decreases. This has motivated various approaches to enhance MP decoding performance, including heuristics to improve convergence and accuracy, post-processing techniques, and diversity or ensemble-based decoding methods (see related works, below). In contrast, our approach focuses on modifying the decoding graph rather than the MP decoding algorithm itself, while enabling “vanilla” MP decoders to perform their intended inference task more accurately.

Besides accuracy, the challenge of QLDPC decoding is further compounded by (1) circuit-level errors, captured by the detector error model, (2) the presence of correlations between X, Y, and Z errors [36], and (3) the requirement for real-time decoding, as timely error correction is essential to prevent backlog issues and maintain fault tolerance in quantum computation [39, 40]. Our approach tackles these challenges and sets new benchmarks in decoding performance, achieving high accuracy and low latency for the bivariate bicycle (BB) codes of distance 6 to 12 from [13].

In this work, we focus on MP decoding of correlated errors under the circuit-level noise model. The starting observation is that the inefficiency of MP decoding in performing the intended inference stems from the structural properties of the underlying decoding graph. Accordingly, our contributions center on modifying the decoding graph to improve its suitability for MP decoding, and on exploiting the new structure via an expert selection of MP decoding parameters.

Considering the correlated detector error model, the decoding graph is a bipartite graph involving error nodes and check nodes. Error nodes correspond to X, Y, or Z errors propagating from different locations in the syndrome measurement circuit (possibly merging multiple locations if they produce the same syndrome), while check nodes correspond to either X or Z detectors (we assume CSS codes).

Results
The core of our approach is a graph augmentation and rewiring technique that transforms the original detector error model graph into a new graph representing an equivalent decoding problem, while eliminating 4-cycles passing through Y-type error nodes. Eliminating 4-cycles is intended to facilitate MP inference; thus, we refer to the proposed graph transformation as graph augmentation and rewiring for inference (abrv. GARI).

We then perform MP decoding on the new graph obtained after applying GARI. Our MP decoding consists of a normalized MS (NMS) algorithm with a hybrid serial-layered message schedule, chosen to optimize the decoding accuracy while also reducing the overall latency. For the tested BB codes, this results in a logical error rate matching that of the best-performing BPOSD, with OSD of order-zero.

To further improve the decoding performance, we employ an ensemble decoding approach, running multiple MP decoders in parallel on our augmented and rewired decoding graph. To this end, we leverage the randomization in the serial part of the hybrid serial-layered schedule, using a modest-sized ensemble of MP decoders with different randomization seeds. This approach achieves decoding accuracy on par with XYZ-Relay-BP-5 (see Fig. 1). Moreover, preliminary hardware implementation results for the [[144,12,12]] BB code show that each decoder of the ensemble can run in real-time on a single VU19P FPGA device. For instance, at a physical error rate of 10−3, the average decoding latency is 273ns, and in 99.99% of instances the decoding completes within 1µs per round.

Graph Augmentation and Rewiring for Inference

A decoding problem can typically be formulated as a linear system, where the decoder’s task is to identify the most likely solution given the prior probability distributions of the errors (variables of the system). The linear system is defined by a matrix, which we call the decoding matrix. For MP decoders, the decoding matrix can be conveniently represented as a decoding graph: a bipartite graph whose adjacency matrix is the decoding matrix, with vertices referred to as error nodes and check nodes, corresponding to the columns and rows of the matrix, respectively (we use the term error node instead of the variable node or data node terminology commonly used in the literature, to explicitly indicate that these nodes represent Pauli errors). We describe the GARI method in terms of both the decoding matrix and the decoding graph. The first description, based on the decoding matrix, focuses on the correlated detector error model and provides a simple linear-algebra procedure to construct the GARI matrix. The second description, based on the decoding graph, applies to more general graph models, and can be used for further optimization and refinement of our approach.

The Decoding Matrix Perspective: We assume Calderbank–Shor–Steane (CSS) codes. Thus, in the correlated detector error model [41, 42], the decoding matrix is a binary matrix that takes the following form:

D XYZ = (D_X 0 D'_X; 0 D_Z D'_Z) (1)

The matrix is partitioned into three block columns: the left block corresponds to Z errors, the middle block to X errors, and the right block to Y errors. The corresponding errors are denoted by e_Z, e_X, and e_Y. Similarly, the rows are divided into two blocks: the top block corresponds to X-type detectors, and the bottom block to Z-type detectors. The corresponding syndromes are denoted by s_X and s_Z.

For given syndromes s_X and s_Z, the role of the decoder is to estimate the most likely error vector (e_Z, e_X, e_Y), such that (we always treat vectors as column vectors in equations; however, error vectors e_Z, e_X and e_Y should be interpreted as row vectors when used to label the columns of the decoding matrix):

D_XYZ (e_Z, e_X, e_Y)^T = (s_X, s_Z)^T (2)

Note that matrices D_X and D_Z are those obtained when considering only one type of detectors, that is, either X or Z detectors, which detect Z or X errors, respectively. The notation D_XYZ for the correlated detector error model is somewhat abusive, since there are no Y-typedetectors. Since our focus is on correlated errors, we will assume that any circuit location where a Y error may occur can also experience X and Z errors. Therefore, matrices D_X and D'_X satisfy the following properties, and analogous properties hold for D_Z and D'_Z as well:

• D_X has no repeating columns,
• every column of D'_X is equal to a column of D_X; however, D'_X may contain repeated columns, meaning the same column of D_X may appear multiple times in D'_X.

The fact that D_X has no repeating columns follows directly from the definition of the detector error model: Z errors occurring at different locations but producing the same syndrome are merged into a single column. For the second property, we observe that a Y-error and a Z-error occurring at the same location produce the same X-syndrome. This explains why every column of D'_X is equal to a column of D_X. However, D'_X may contain repeated columns, corresponding to Y-errors at different locations that produce the same X-syndrome but different Z-syndromes. In this case, the corresponding columns are not merged in [D'_X; D'_Z], resulting in column repetitions in D'_X (where we use the semicolon to denote vertical stacking of matrices). These properties imply the existence of matrices U and V, such that D'_X = D_X U and D'_Z = D_Z V, which can be explicitly determined as follows:

• each column of U has exactly one 1, and
• the ith row of U has 1’s in columns j_1, ..., j_k if and only if the ith column of D_X equals the columns j_1, ..., j_k in D'_X.
• Similar statements hold for V.

We use matrices U and V to perform a change of variables in Eq. (2). Precisely, we define

e_bar_Z = e_Z + U e_Y and e_bar_X = e_X + V e_Y (3)

so that Eq. (2) rewrites as

D_X e_bar_X = s_X and D_Z e_bar_Z = s_Z (4)

Independent decoders operating on D_X and D_Z provide independent estimations of e_bar_X and e_bar_Z satisfying Eq. (4). To account for correlations between X, Y, and Z errors, a decoder must jointly estimate e_bar_X and e_bar_Z satisfying Eq. (4) along with the variable change in Eq. (3). Precisely, this corresponds to defining a new decoding matrix

D_XYZ = (D_X 0 0 0 0; 0 0 0 0 D_Z; I 0 U I 0; 0 I V 0 I) (5)

so that Eq. (4) and Eq. (3) can be rewritten as

D_XYZ (e_Z, e_X, e_Y, e_bar_Z, e_bar_X)^T = (s_X, s_Z, 0, 0)^T (6)

Note that Eq. (6) depends on an augmented variable set, consisting of (e_Z, e_X, e_Y, e_bar_Z, e_bar_X). We refer to D_XYZ, which defines an equivalent decoding problem, as the GARI matrix. Importantly, a GARI decoder – i.e., one using the decoding matrix D_XYZ – produces an estimate of the error vector (e_Z, e_X, e_Y, e_bar_Z, e_bar_X). In practice, however, we are typically interested in only one type of error, depending on the type of the logical observables protected by the decoder. Assuming we protect logical-Z observables, we are only interested in decoding X errors, including contributions from Y errors, that is e_bar_X. This is precisely the error that would be estimated using the Z-type detector error model alone; however, in that case, the decoder cannot exploit correlations between the Pauli errors.

The Decoding Graph Perspective: Let us first consider an arbitrary decoding graph that contains 4-cycles (the connection with the previous section will be made later), which we aim to eliminate to enable more effective MP inference. This necessarily involves modifying the decoding graph, while ensuring that the resulting graph corresponds to a decoding problem equivalent to the original one. Moreover, since 4-cycles can combine to form bicliques – i.e., complete bipartite subgraphs of the decoding graph – these are precisely the types of structures we aim to eliminate. A 4-cycle is illustrated in Fig. 2(a), and a biclique is shown in Fig. 2(b). Any two error nodes and any two check nodes participating in the biclique determine a 4-cycle. Note that a biclique is necessarily an induced subgraph, formed from one subset of error nodes and one subset of check nodes, along with all edges from the decoding graph connecting pairs of nodes in these subsets. In terms of the decoding matrix, a biclique corresponds to a submatrix with all entries equal to 1.

The GARI procedure is illustrated in Fig. 2(c), and it is applied to maximal bicliques in the decoding graph – i.e., bicliques that cannot be extended by adding any additional error or check nodes. We modify the decoding graph by adding a new error node (in blue), representing the sum of all error nodes in the biclique. We enforce this last condition by also introducing a new check node (in blue) connected to the error nodes in the biclique and the newly added one, with its syndrome value set to zero. Finally, for each check node in the biclique, we replace its corresponding incident edges with a single edge connecting it to the newly added error node. We note that the above procedure was previously developed, but applied only to 4-cycles, in [43, 44] for decoding some families of classical linear block codes under belief propagation.

Clearly, the above procedure eliminates all 4-cycles forming the biclique. While new 4-cycles may appear involving the nodes introduced by GARI, it can be easily seen that their number is reduced. Thus, recursively applying the procedure will eventually eliminate all 4-cycles in the graph.

We also note that, although the above procedure augments the decoding graph with additional error and check nodes, it increases the number of edges by only one when applied to a 4-cycle, preserves the number of edges when applied to a 5-node biclique, and strictly reduces the number of edges in all other cases. This can be easily seen by comparing the number of edges in Fig. 2(b) and Fig. 2(c). Consequently, the augmented graph may contain fewer edges than the original graph, implying that an MP decoder operating on the augmented graph may incur a reduced computational load (i.e., performs fewer message updates per iteration) compared to the same decoder operating on the original graph. This is typically the case for correlated detector error model matrices D_XYZ, due to the generally large size of the maximal bicliques (see also the BB code examples below).

We now claim that, for the correlated detector error model discussed in the previous section, the GARI matrix D_XYZ is the adjacency matrix of the graph produced by one possible application of the GARI transform to the decoding graph with adjacency matrix D_XYZ. To see this, we first note that any column of D_X or D_Z that is repeated one or more times in D'_X or D'_Z, respectively, determines a biclique in D_XYZ. For instance, assuming that the ith column of D_X equals the columns j_1 and j_2 in D'_X, we obtain a biclique with three error nodes as in Fig. 2(b): the three error nodes correspond to these columns, while the check nodes (left unlabeled in the figure) correspond to the rows containing 1 entries in them. Upon application of GARI, the newly introduced error and check nodes (depicted in blue in Fig. 2(c)) correspond, respectively, to the ith column within the e_bar_Z column block and the ith row within the third row block of D_XYZ. The edges connecting the newly added check nodes to the error nodes j_1 and j_2 correspond to 1 entries in the U matrix, while the edges connecting it to the white and blue error nodes labeled i correspond to the 1 entries in the two identity matrices on the left and right sides of U. The edges connecting the newly added error node to the four check nodes from the original graph reproduce the corresponding D_X column.

Summarizing, upon applying GARI, the added error nodes correspond to columns e_bar_Z and e_bar_X in (5), while the added check nodes correspond to the bottom part of D_XYZ, containing the I’s, U and V submatrices. D_X and D_Z submatrices in the top part of D_XYZ are reproduced by the new edges added between the original check nodes and the newly introduced error nodes, and they contain the only remaining 4-cycles in the new graph. See Table 1 for a quantitative summary of the size, average row weight, and number of 4-cycles in D_X, D_Z, D_XYZ, and D_XYZ for various BB codes. The number of non-zero entries in each matrix can be computed as the product of the number of rows and the average row weight. For instance, for the [[144, 12, 12]] code, the D_XYZ matrix has 1728×226.46 = 391323 non-zero entries, while the D_XYZ matrix (including D_X, D_Z, and the bottom part) has 792×34.18+936×32.77+16704×8.11 = 193213 non-zero entries, which is less than half the number of non-zero entries in D_XYZ.

As discussed above, the GARI transform can be applied recursively to further eliminate the remaining 4-cycles. However, for the tested BB codes, the achieved performance was on par with or exceeded that of significantly more complex state-of-the-art decoders, and at the time of writing this paper, we did not pursue further optimization.

We also note that removing only the cycles through Y-type error nodes enables a more accurate treatment of correlations, without optimizing the decoding of a single error type. Indeed, a closer examination of the GARI decoding matrix in (5), reveals that a GARI MP decoder can be interpreted as two decoders operating on the single-detector-type matrices D_X and D_Z, which exchange information through the bottom part of D_XYZ. This information exchange allows the decoder to account for correlations between X, Y, and Z errors. Such a decoder architecture is further discussed and illustrated in a subsequent section.

Randomized Scheduling based Ensemble Decoding

Now that we have a graph enabling improved MP inference, we can apply MP decoding on it. It is to be expected that any MP decoder will perform better on the GARI graph than on the original one. However, optimizing accuracy and speed requires a judicious choice of the MP decoder, encompassing both the message update rules and the message update schedule. We refer to the Methods section for a discussion on different message-update schedules (flooding, serial, layered) and, in the following, discuss the choice of MP decoding for GARI and the ensemble decoding approach.

MP Decoding on GARI: We consider the normalized variant of the MS decoder (NMS), in which a scaling (normalization) factor is applied to check node messages to improve the accuracy of inference on loopy graphs [45]. It is also the preferred choice for hardware implementations, owing to its simple arithmetic and robustness when messages are quantized with a small number of bits. Lowering the bit-width of the exchanged messages is important both for reducing footprint and for increasing speed [46]. We also employ a horizontal hybrid serial-layered schedule, as explained in the next paragraph. Horizontal schedules are often the de facto choice in hardware implementations due to their efficiency in resource allocation and straightforward integration into processing pipelines [47]. We note, however, that we also experimented with various vertical schedules, which proved less effective than horizontal ones in terms of decoding accuracy and speed. In the following, all schedules are horizontal.

Hybrid schedule: We consider the GARI decoding matrix D_XYZ given in Eq. (5). For the top part of D_XYZ, consisting of the rows corresponding to the D_X and D_Z blocks, we use a randomized serial schedule. For the bottom part, consisting of the remaining rows, we use a layered schedule with two layers: the first layer contains the rows corresponding to the U matrix, and the second contains those corresponding to the V matrix.

For the top part, since the only non-zero entries lie within the D_X and D_Z matrices, which do not share any rows or columns, we can equivalently use two MP decoders running in parallel – one for D_X and one for D_Z – each employing a randomized serial schedule. At each iteration, these decoders exchange information via the processing performed in the bottom part of the D_XYZ. For the bottom part, the fact that the layers are well defined (i.e., rows within each layer do not intersect) follows from the fact that U and V have column weight 1. Since there are only two layers and processing the same layer twice in succession (without processing the other layer in between) would not change the outgoing messages, randomization is not possible. Thus, we simply process the layers in their natural order. Note that a serial schedule processing the rows of the bottom matrix in their natural order would perform exactly the same computations (i.e., produce the same messages). Thus, layered scheduling is used in the bottom matrix not to improve accuracy, but merely to reduce latency.

Prior probabilities: The MP decoder is initialized with a prior probability value for each column of D_XYZ (i.e., each error node, in graph terminology). For the e_Z, e_X, and e_Y columns in (5), we use the prior probabilities obtained from the detector error model (as done for D_XYZ in (1)). For columns e_bar_Z and e_bar_X, corresponding to new error nodes added by GARI, no prior knowledge is available, so their prior probabilities are set to 0.5 (corresponding to a log-likelihood ratio of 0). One might object that prior probabilities could be obtained from Eq. (3). However, this is precisely what the MP decoder does after the first decoding iteration. Manually setting prior probabilities is not only unnecessary but may be detrimental, as it duplicates the information obtained through MP inference. Finally, since e_bar_Z and e_bar_X columns have no prior knowledge, we start the decoder by processing the bottom part of D_XYZ first, followed by the top part (starting with the top would simply waste the first iteration on that part).

Early stopping: Let us consider a memory experiment, in which we protect logical-Z observables (i.e., the protected logical state is a tensor product of eigenstates of the logical-Z operators). In the detector error model, the physical qubits are measured in the Z basis at the end, which allows us to detect logical-X errors, manifested as changes in the protected logical observables. Although our decoder exploits correlations and effectively estimates the error vector (e_Z, e_X, e_Y, e_bar_Z, e_bar_X), we can actually only assess the accuracy of the X error estimation, including contributions from Y errors – that is e_bar_X. Thus, for early stopping of our MP decoder, we only check whether the Z-type syndrome is satisfied, that is, D_Z e_bar_X = s_Z. This is checked after each decoding iteration, and the MP decoder stops when the Z-type syndrome is satisfied or when a maximum number of iterations is reached. Similarly, for the X-memory experiment, one would implement the early stopping on D_X instead.

As an aside, we note that we also experimented with a different early stopping criterion, checking both Z and X syndromes, that is D_Z e_bar_X = s_Z and D_X e_bar_Z = s_X (while, of course, we could estimate only the logical-X error rate, based on the decoded e_bar_X). This yielded a similar logical-X error rate but increased the average number of decoding iterations by approximately a factor of two, since the decoder needs to converge on both D_Z and D_X before it stops. Also, convergence on D_Z generally occurs faster, aided by the final measurements of physical qubits in Z basis. Importantly, such a stopping criterion could be used in experiments in which both X and Z logical operators must be preserved. However, our focus is on memory experiments involving the preservation of a single type of logical operator (in line with current practice in the literature), and we aim to show how its preservation can be enhanced by effectively exploiting correlations among X, Y, and Z errors.

Ensemble Decoding Approach: The benefits of randomization in scheduling can be further leveraged through an ensemble decoding approach. This method involves running multiple MP decoder instances in parallel, each decoding the GARI matrix but using a distinct randomization seed for the serial part of the hybrid serial-layered schedule.

Early ensemble stopping: Since our decoders run in parallel and may converge after different numbers of iterations, we also need a global strategy to stop the entire ensemble. We adopt a latency-minimizing strategy, in which all MP decoder instances stop as soon as one of them converges. If several MP decoders converge simultaneously (i.e., after the same number of decoding iterations), we select the most likely error among those estimated by these decoders, where the likelihood of an error is determined according to the prior probabilities. However, recall that the MP decoder stops when the Z-type syndrome is satisfied, D_Z e_bar_X = s_Z, and that no prior probabilities for e_bar_X has been provided to the decoder. Fortunately, as mentioned earlier, we can use Eq. (3) to compute prior probabilities for e_bar_X (which are identical to those obtained from the Z-type only detector error model). While these probabilities are not needed by the decoder (see earlier discussion), we use them to compute the likelihood of each estimated error and then select the most likely one.

Hardware Architecture

The GARI MP decoder features a hardware-efficient architecture, which we discuss in this section. The architecture is illustrated in Fig. 3, and consists of three distinct processing units. The D_X and D_Z units implement MP decoding on the D_X and D_Z submatrices, respectively, and they exchange information through a third processing unit that implements MP decoding on the bottom part of D_XYZ. We note that this high-level architecture is generic and can accommodate different MP decoders, including different message update rules and scheduling strategies. Below, we examine in detail the benefits of the hybrid serial–layered schedule discussed in the previous section.

Resource efficiency: Serial schedules are implemented in hardware using a single check node processor, which is reused to sequentially process all the checks (rows) of the decoding matrix. Thus, implementing D_X and D_Z units requires a single check-node processor for each. Considering an ensemble decoding approach, the number of check-node processors per D_X or D_Z unit equal to the size of the ensemble. Even in this case, the number of check-node processors remains significantly lower than that required for the parallel implementation of a single MP decoder on either D_X or D_Z, which equal the number of rows of the corresponding matrix. This is particularly important as the code distance and thus the size of the decoding matrix increase (see, for instance, Table 1). While such an increase does not affect the resource usage of D_X and D_Z units in our architecture, it can hinder the implementation of a fully parallel schedule due to the limited resources available on FPGAs.

The most resource-intensive part of our architecture is the implementation of the bottom-part unit, which requires a number of check-node processors equal to the maximum layer size (i.e., the maximum number of rows between the first and second layers). However, the weights of the rows in the bottom part of D_XYZ are considerably smaller than those of the D_X and D_Z rows (see Table 1). Thus, check node processors in the bottom-part unit require fewer resources than in the D_X and D_Z units, so increasing their number is less of a concern.

Low latency: The serial architecture of D_X and D_Z units reduces routing complexity, since a single check node processor is connected to a single bank of registers and memory. Such an architecture can operate at high clock frequencies, thereby compensating for the inherent latency induced by the sequential nature of the serial schedule. Moreover, the horizontal serial schedule considered in our architecture provides a significant speedup compared to the vertical schedule, due to the ratio between the number of rows and columns in the D_X and D_Z matrices (at least ninefold speedup for the BB codes, see Table 1). By way of comparison, it is worth noting that a parallel implementation would require multiple wiring connections (proportional to the edges of the graph), which could cause routing congestion and contribute significantly to the critical path delay in FPGAs that have fixed routing lines.

The layered schedule in the bottom part unit may reduce the operating clock frequency, due to the increased footprint and routing complexity. However, this effect is mitigated by the reduced logic depth of the check-node processors, while the inherent parallelism of the schedule enables a significant latency reduction.

Finally, we note that processing units can employ pipelining to reduce the critical path and increase the maximum achievable clock frequency. The pipelined implementation also supports hardware sharing, allowing resources to be reused across different decoding runs, thereby further improving resource efficiency. Resource sharing across decoding runs was not implemented in the present work, but could be explored in future research.

Numerical Results on Decoding Accuracy

We consider memory experiments, in which all logical qubits are initialized in an eigenstate of their corresponding logical-Z operators. To benchmark our method, we consider the BB codes with parameters [[72,12,6]], [[90,8,10]] and [[144,12,12]] from [13]. For a code of distance d, we consider the circuit obtained by repeating the syndrome measurement d times, followed by a final measurement of the data qubits in Z basis. The corresponding detector error model is constructed and simulated for a given noise model using Stim [48]. Note that detector circuits may not be distance preserving (i.e., the circuit level distance may be less than d), but we will systematically refer to them using the [[n,k,d]] notation of the corresponding code.

We consider various decoders operating on different decoding matrices, namely D_Z, D_XYZ, and D_XYZ (i.e., the GARI matrix). The goal is to provide a comparison of our method with BPOSD decoder, as well as with more recent, higher-accuracy decoders such as Relay-BP and Tesseract. We discuss below the hyperparameters used in our simulations, where decoder names are prefixed with the decoding matrix they operate on (using GARI for D_XYZ).

GARI-NMS: NMS decoder with hybrid serial-layered schedule, operating on the D_XYZ matrix. The serial round schedule is randomized and the maximum number of iterations is set to 400. The NMS normalization factor is set to either 0.96875 or 0.9921875, chosen to optimize accuracy while facilitating hardware implementation using bit shifts and adders. The GARI-NMS-ensemble decoders employ either 24 or 48 GARI-NMS decoders in parallel for the uniform depolarizing noise and SI1000 noise models, respectively (discussed below). We denote these decoders as GARI-NMS-×s, where s is the size of the ensemble. Ensemble decoding is only used for BB codes with distances 10 and 12.

(D_Z/D_XYZ)-NMS: For comparison purposes, we also consider an NMS decoder with a randomized serial schedule, using a maximum number of 400 decoding iterations and normalization factor of 0.96875, but operating on either D_Z or D_XYZ matrix.

(D_Z/D_XYZ)-BPOSD: We use the open-source library [20, 49] to simulate the order-zero BPOSD decoder. We fine-tune BPOSD decoders on both D_Z and D_XYZ using different NMS normalization factors, schedules and number of iterations, and then use the best resulting decoder for comparison with our method (see Methods for details). We obtain the best performance when combining OSD post-processing with an NMS decoder operating on D_XYZ for distance d=6, but on D_Z for distances d=10 and d=12, using a normalization factor of 0.625, randomized serial scheduling, and a maximum number of 30 iterations (a larger number of iterations degrades performance at low physical error rates due to erratic behavior of the MP decoder). We note that the NMS decoder in BPOSD library [49] uses a vertical serial schedule (in contrast to horizontal schedules used in our implementation of the NMS).

D_XYZ-Relay-BP: We use the open-source library [50], associated with the paper [34], to simulate Relay-BP, using the hyperparameters specified in the library. We compare our results with the XYZ-Relay-BP-5 (operating on D_XYZ) decoder, which handles correlated errors and has been shown to outperform BPOSD. It uses 301 DMem-BP decoders in series with up to 18080 decoding iterations. The decoder searches for five different solutions (thus the suffix 5 in the notation) and returns the one with the lowest weight. We note that the simulation results in [34] use 601 DMem-BP decoders in series, instead of 301, which is the default value in the library. We noticed this rather late and ran several simulations with 601 DMem-BP decoders, but they were too slow to produce meaningful results, especially at low physical error rates.

Logical error rates: We determine the logical error rate as the ratio of decoding failures (i.e., either the decoder did not converge, or at least one logical observable is flipped by the decoded error) to the total number of decoded runs, i.e., LER = decoding failures / number of samples. The logical error rate per syndrome measurement round (in short, per-round) is obtained by [36],

LER = (1 - (1 - 2 * LER)^(1/r)) / 2. (7)

Unless otherwise stated, all reported logical error rates are per-round. Error bars in all plots indicate 99% confidence intervals, calculated from at least 100 decoding failures, except for the Relay-BP and Tesseract (discussed later) decoders, for which the number of decoding failures is about 40 at low physical error rates.

Uniform depolarizing noise: Fig. 4 presents the per-round logical error rate results under the circuit-level uniform depolarizing noise model. The detector error model is instantiated using the Stim circuits from [27] for Figs. 4(a)–4(c), and the Stim circuit from the Relay-BP library [50] for Fig. 4(d).

First, we observe that the D_XYZ-NMS decoder performs significantly worse than D_Z-NMS. This degradation is due to the large number of 4-cycles in D_XYZ introduced by Y-type errors, which hinder the NMS decoder’s ability to handle correlations between Pauli errors. Table 1 lists the number of 4-cycles in these matrices, as well as the average check degree, for all the codes considered. It is worth noticing that the bottom part of the GARI matrix contains no 4-cycles and has a smaller average check degree compared to D_XYZ, making it more suitable for MP decoding. As a result, the GARI-NMS decoder not only outperforms D_Z-NMS, but it is already on par with BPOSD for BB codes of distance d=10 and d=12, while being significantly more lightweight and faster. Moreover, for the smaller distance d=6 code, GARI-NMS outperforms BPOSD, achieving performance similar to that of the D_XYZ-Relay-BP-5 decoder.

We now consider the GARI-NMS-×24 ensemble decoder, and report its decoding performance for the BB codes of distance d=10 and d=12. Let us note that for the BB code of distance d=6, the ensemble decoder does not further improve performance. For distances d = 10 and d = 12, we can observe that GARI-NMS-×24 and D_XYZ-Relay-BP-5 decoders achieve similar performance, with the former performing slightly better at high physical error rates or when using the Stim circuit from the Relay-BP library, as shown in Fig. 4(d).

While we prioritized minimizing latency, the GARI-NMS-ensemble performance could potentially be improved by waiting for multiple decoders to converge, and then selecting the most likely (e.g., lowest weight) solution. This echoes the idea of Relay-BP-5, which stops after five decoders have converged. However, while both approaches rely on ensemble decoding, it is worth noting that they differ in a key aspect. Our method runs all decoders in the ensemble in parallel, with each operating independently. In contrast, Relay-BP executes the decoders sequentially, relaying information from one decoder to the next. This serial operation increases decoding latency and limits the ability to exploit the parallel processing capabilities of CPUs and FPGAs.

Finally, for completeness of the comparison, we also discuss the case of the D_Z-NMS-ensemble decoder (not shown in Fig. 4 to maintain clarity), where the randomized-scheduled ensemble decoding approach is applied to D_Z-NMS rather than the GARI-NMS decoder. For distance d = 12 and physical error rate 10−3, the D_Z-NMS-×24 decoder achieves a logical error rate of 1.6×10−7, on par with BPOSD. This highlights that it is the combination of GARI and randomized-scheduled ensemble decoding that achieves the best accuracy.

SI1000 noise model and Tesseract: For comparison with Tesseract, we use the data provided by the authors of [36]. The simulations in that work employ the SI1000 noise model and a different gate set (CZ-H-MZ) for BB code circuits. Accordingly, we simulate our decoder under the same noise conditions and on the same circuits, which are available in the open-source library associated with [36].

In this setting, the GARI-NMS-ensemble decoder achieves an accuracy within an order of magnitude of Tesseract, as shown in Fig. 5. However, Tesseract is a graph search–based decoder that searches through a graph of all error subsets to find the lowest-cost subset consistent with the input syndrome. Although the search can be made more efficient using the A* algorithm and pruning heuristics (since the search graph is exponentially large), its complexity remains considerably higher than that of MP decoders. To the best of our knowledge, no other MP-based decoding solution has been reported to achieve a comparable level of decoding performance in this setting.

Real-Time Decoding Implementation

We report implementation results obtained for the Virtex UltraScale+ VU19P (16nm), currently the highest-capacity FPGA in production by AMD. The code under test is the [[144,12,12]] BB code. The cores for the D_X, D_Z, and bottom-part units were implemented independently using Vivado 2021.2.

The serial D_X and D_Z processing units employ 10 pipeline stages and operate at a maximum clock frequency of 357MHz. This corresponds to a clock period of 2.8ns, with 60% of the delay due to routing and 40% to logic gates. Consequently, the per-iteration delay is 2.22µs for D_X and 2.62µs for D_Z. For the bottom part processing unit, the maximum clock frequency is over 20 times lower than that of the serial units, due to the high degree of parallelism and the absence of pipelining. The total delay for processing both layers is 272ns, with 80% of the delay due to the routing. The total delay per iteration for the GARI MP architecture is the sum of the maximum delay of D_X and D_Z units (which run concurrently), and the delay of the layered bottom part unit. This results in a total per-iteration delay of 2.9µs. We note that, in practice, a fully integrated design with proper clock-domain crossing is expected to achieve similar decoding latency, with only negligible overhead due to synchronization. In addition, if multi-FPGA is required, high-speed transceivers such as GTY included in V19P, with 4.5 Tb/s of bandwidth and tens of nanoseconds of latency in raw mode can be used to preserve the timing behaviour of the independently implemented modules.

Assuming a time budget of 1µs per syndrome measurement round [40], and given that decoding is performed across a number of rounds equal to the code distance, the resulting time budget for decoding the BB code under test is 12µs. Hence, on average, slightly more than four decoding iterations can be accommodated within the given time budget. According to the average number of decoding iterations reported in Table 2, the GARI MP ensemble decoder operates in real-time (i.e., within the specified time budget) for physical error rates below 0.003.

We also define the per-round decoding latency as the decoding latency (i.e., number of iterations multiplied by the per-iteration latency) divided by the number of syndrome measurement rounds. For a physical error rate of 0.001, considering the average number of decoding iterations reported in Table 2, the resulting per-round average decoding latency is 1.13×2900/12 = 273ns. Moreover, Fig. 6 shows that, at the same physical error rate, more than 99.99% of decoding runs complete within the 1µs per-round time budget.

We also note that our decoder has a worst-case latency corresponding to the situation in which it reaches the maximum of 400 decoding iterations, which occurs with a probability approximately equal to the logical error rate (it is also possible for the decoder to converge on the very last iteration, but this is rare, as suggested by Fig. 6). However, we did not attempt to optimize the maximum number of iterations, and similar accuracy could likely be achieved with a much lower maximum number of decoding iterations (Fig. 6 again provides some supporting evidence for this). Moreover, for decoders with variable latency, it has been shown in Ref. [51] (see also the analysis in Ref. [52]) that even when the worst-case latency exceeds the available time budget, the backlog problem [39, 40] can be avoided, provided that the decoding latency tail is not too long and occurs with sufficiently low probability.

If even lower latency is desired in an FPGA implementation, different optimizations can be explored. Firstly, the latency in our architecture is primarily limited by the D_X and D_Z units, due to the sequential updates imposed by the serial schedule. One possible approach to reduce this latency is to divide the D_X and D_Z submatrices into layers, allowing more checks to be updated in parallel without compromising accuracy. This approach requires a careful balance between the FPGA’s logic and memory resources, the desired speedup, and scalability with the code distance. In addition, quantization improvements could be explored to reduce the number of bits used to represent the exchanged messages in serial and layered decoders, which is currently set to 12 bits to achieve accuracy close to that of a floating-point implementation. Also, compression techniques applied to the exchanged messages [53] or simplifications on the check node [54, 55] can be explored to reduce the delay derived from routing or logic, respectively.

Finally, we note that, using the same 16nm technology for ASIC, it is reasonable to expect, with the same design and without any further optimization, at least a three times speedup [56].

Methods
Message Update Schedules

Besides the update rules used to compute the exchanged messages, a key component of the MP decoder is the message update schedule, which specifies the order in which exchanged messages are updated and passed to their neighbors. While the time complexity of a single MP decoding iteration is linear in the size of the decoding graph, regardless of the message update schedule, the choice of the schedule can affect the parallelization of message updates and the convergence speed, thus playing an important role in the achievable latency.

In the flooding (or parallel) schedule, all nodes of the same type update their outgoing messages in parallel, alternating between error nodes and check nodes at each demi-iteration. The flooding schedule matches fully parallel implementations, enabling high speed but requiring substantial hardware resources and potentially facing routing and interconnect congestion issues [47].

In the serial schedule, message updates are performed sequentially over a given type of nodes. The serial schedule can be vertical, when updates are sequentialized over error nodes (i.e., column-wise), or horizontal, when updates are sequentialized over check nodes (i.e., row-wise). The serial schedule corresponds to a fully serial implementation, minimizing hardware resources but increasing decoding latency.

The layered schedule updates messages layer by layer (see below), combining parallelism within each layer with sequential updates across layers. Depending on the vertical or horizontal variant, a layer consists of a set of error nodes (columns) or check nodes (rows) that do not share common neighbors (i.e., are non-intersecting), enabling efficient parallelization of message updates within the layer. By combining parallelism and sequential updates, the layered schedule is the natural choice for a partly parallel implementation, offering a balance between speed and hardware complexity [47].

For classical LDPC codes, the flooding schedule generally achieves the same accuracy as the serial and layered schedules but requires roughly twice as many iterations to converge [67]. For QLDPC codes, however, the flooding schedule may fall well short of the decoding accuracy of the serial or layered schedules, even with significantly more iterations [19, 63]. Additionally, serial and layered schedules may be randomized, further improving the decoding performance [63, 68]. In a randomized serial (or layered) schedule, message updates are performed sequentially over the nodes (or layers) in an order randomly chosen at each decoding iteration. The asymmetry introduced by such randomization may help the decoder break the symmetry or cyclic dependencies that trap it in persistent or repetitive error patterns, thus improving convergence and overall decoding performance.

BPOSD Tuning

Here, we discuss simulation results for the order-zero BPOSD operating on the D_Z and D_XYZ matrices.

For the distance-6 BB code, when the parallel (flooded) scheduling is used for the underlying MP decoder, it was observed in [36, Appendix A] that uncorrelated BPOSD is significantly more accurate than correlated BPOSD, that is BPOSD performs better when operating on D_Z than D_XYZ. We reproduce these results in Fig. 7(a), and provide similar results for BB codes with distances 10 and 12 in Fig. 7(b)-(c) – see orange curves, corresponding to parallel scheduling.

Additionally, we perform simulations using a randomized serial scheduling (blue curves), and observe a significant improvement in the BPOSD performance, for both D_Z and D_XYZ matrices.

Interestingly, for the distance-6 BB code, BPOSD with randomized serial scheduling performs significantly better on D_XYZ than on D_Z. Thus, accuracy results included in the main text for comparison purposes correspond to the dashed blue curve in Fig. 7(a).

For BB codes with distances 10 and 12, BPOSD with serial scheduling outperforms parallel scheduling at higher physical error rates. However, the performance gap diminishes, and may even reverse, at lower physical error rates, as shown in Fig. 7(b) and (c). As BPOSD with randomized serial scheduling on D_Z achieves the best performance and exhibits a steeper slope in the low-error-rate regime, we adopt this variant of the decoder as a baseline for comparison with our method in the main text, for BB codes with distances 10 and 12.

Finally, we note that all simulation results in Fig. 7 use an NMS decoder, with the normalization factor optimized for the best performance under the considered scheduling. Specifically, we use a normalization factor of 1.0 for parallel scheduling and 0.625 for serial scheduling. The maximum number of decoding iterations is set to 30, as we observed that a larger number of iterations degrades performance at low physical error rates due to the erratic behavior of the NMS decoder in case of non-convergence.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The paper presents a promising decoding strategy for bivariate bicycle code memory circuits under circuit-level noise. By\njointly using X and Z syndromes to address Y-type errors, the authors propose an alternative graph formulation together with\nan ensemble of random permutation schedules for Min-Sum belief propagation over a Tanner graph incorporating X, Z, and\nY detectors. The method demonstrates accuracy comparable to or exceeding previous techniques, and the accompanying\nFPGA implementation helps validate the practicality and efficiency of the approach.\nThe work is interesting and timely, but I think there are some points that need to be addressed.\n1. The authors call the new representation for the parity check matrices GARI. The technique introduces a new row and\ncolumn to eliminate specific 4-cycles. This technique was previously developed for classical decoding in 'Generating Code\nRepresentations Suitable for Belief Propagation Decoding' by J. Yedidia, J. Chen and M. Fossorier and 'Polar Codes: Graph\nRepresentation and Duality' by M. Fossorier, both of which works are not cited when the method is introduced.\n2. The modified representation increases the number of rows, columns, and non-zero entries of the matrix. Some discussion\non whether this leads to additional computational overhead during message passing, and how this compares to the benefits\nin decoding performance, would add clarity on the tradeoffs.\n3. The stopping condition for the decoder relies on convergence of only one syndrome type (specifically, satisfaction of the Z\nsyndrome). This aligns well with the specific memory setting where preserving a single basis is the objective. How would the\nmethod might generalize to experiments where both logical generators must be maintained, such as arbitrary state\npreservation experiments?\n4. The numerical results employ a maximum of 400 decoding iterations, whereas the FPGA implementation appears to\noperate within only 10 or fewer. Where is this discrepancy between simulations and implementation attributed to? It would\nbe valuable to know the logical error rate achievable when limiting simulations to 10 iterations, and whether restricting both\nsimulation and hardware runs to, for example, 4 or 5 iterations might provide a fair and practically relevant comparison.\n5. The latency and throughput results are strong, but it seems that the worst-case latency remains the main limitation with\nrespect to real-time constraints. Discussion on possible mitigation strategies, even if they involve tradeoffs in accuracy,\nwould be useful for understanding and comparing.\n6. Finally, releasing a CPU based implementation, even in a simplified form, would greatly support reproducibility and allow\nothers to benchmark or build upon this work.\nOverall, this paper presents a compelling decoder design backed by solid experimental results, and the FPGA\nimplementation meaningfully demonstrates the potential and practical challenges associated with real-time quantum error\ncorrection.", "reviewer_2": "A _Tanner graph_ is the incidence graph of the parity check matrix of an error correcting code.\nFor low-density parity check codes this graph is sparse, so decoding algorithms which pass messages along its edges can\nin principle be implemented efficiently in hardware.\nMessage passing decoders work well for classical codes, but not straightforwardly for quantum codes.\nOne problem is degeneracy: the existence of small errors with no syndrome or logical effect means that there are many\nplausible error strings with any given syndrome, and a message passing algorithm can get torn between these.\nA second problem is that in the quantum setting there are almost universally cycles of length 4 in the Tanner graph.\nThese can lead to poor numerical behaviour as messages echo round them.\nRecently Müller et al. published the Relay decoder which greatly improves the performance of message passing decoding\nby adding large random perturbations in the form of a varying memory effect.\nThe authors of the present submission achieve similar accuracy by more directly tackling the problem of 4-cycles arising, in\nthe first instance, from the fact that any given X- or Z-error will, in a CSS-code, look the same as multiple Y-errors, so any two\nchecks on a single X- or Z-error lead to a large number of 4-cycles in the Tanner graph.\nThey name their approach GARI.\nOne approach to eliminating these cycles is to delete half of the checks entirely (say the X-checks if we are mostly interested\nin Z-logical information), after which the Y-error nodes will merge into their equivalent X-errors.\nFor the most simple message passing decoders this improves performance even though we are throwing half of our\ninformation away.\nFrom a first perspective, GARI takes the two smaller decoding problems obtained by deleting the X- or Z-checks and add\nback a new linking structure combining them into a single Tanner graph different from the original Tanner graph.\nFrom a second perspective, they add new error nodes encoding the error state of combinations of error nodes and use these\nlike a cache to avoid multiple computations of the same sum, eliminating complete bipartite subgraphs (which are lousy with\n4-cycles) from the Tanner graph.\nThe authors remark that this second perspective could be applied beyond eliminating the 4-cycles arising from Y-errors, but\nin this work they only implement the Y-error version.\nThis is already sufficient to obtain essentially state of the art decoding performance for qLDPC codes by running your\nfavourite message passing algorithm on the GARI-transformed Tanner graph.\nThe authors also describe hardware implementation techniques and FPGA resource counts for each component of the\ndecoder, although they do not make a complete integrated FPGA implementation.\nThe accuracy and cycle count data in the paper is obtained by software simulation.\nThis is an outstanding contribution to the field of practical quantum error correction and should certainly be published.\nThe remainder of this report contains comments to help the authors with revision of their paper.\n- There are some inconsistent usages througout\n- inference (which I think is intended) vs interference\n- BP-OSD vs BPOSD\n- page 1, second column: I agree that qLDPC codes typically have short cycles (in fact 4-cycles) but are low-weight\nstabilisers specifically the reason for this?\n- next para: \"no longer significantly improve\" presumably means something like a shallower gradient but still a decrease with\ndecreasing physical error rate\n- page 2, fig 1 caption\n- 18080 is a strange number. Perhaps explain that this is 80 + three hundred 60s, not one big undifferentiated budget\n- You explain much later that you didn't ensemble for distance 6 because it didn't make a noticeable difference, but perhaps\nit's worth mentioning here.\n- page 3, second column: I can imagine a situation where a Y error is possible with no corresponding X or Z error, but the\ndescription is easily patched up in that case.\n- page 4, first column: \"Similar statements holds\"\n- page 5, top of first column: \"(using the fact that the procedure is applied to maximal bicliques).\" I agree with the statement\nthis is in support of but don't think this is the most helpful hint.\n- \"it results in a reduced number of edges\" This is false if the biclique is a 4-cycle, which is transformed to a graph with 5\nedges. You're at least break even for any larger clique though.\n- next para, \"_the_ GARI transform\" There are a large number of possible GARI transform steps which could be applied, not\na unique sensible choice.\n- final para, \"is (5)\" -> in (5)?\n- page 6, second column: \"all schedules are assumed to be\" Isn't this something you decided?\n- \"Note that a serial schedule processing the rows of the bottom matrix in their natural order would perform exactly the same\ncomputations...\" Is this still true given possible intervening updates from the top part of the matrix?\n- page 8, second column: maybe give the dyadic fractions for the decimals?\n- page 10: \"Finally, for completeness ...\" At what physical error rate was 1.6e-7 the observed logical error rate?\n- Real-time decoding section: does the fact that the components were implemented independently and in particular at\ndifferent operating frequencies affect how confident we can be in the performance of a full FPGA implementation?\n- page 11: \"which is currently set to 12 bits to mimic floating-point accuracy\" What does this mean?"}, "author_response": "Response to the Reviewers’ Comments\nDear Reviewers,\nWe sincerely thank the Reviewers for their careful\nevaluation and insightful comments. In accordance with the requests, we have prepared and submitted a revised\nversion of the manuscript, together with this response letter, which provides a point-by-point reply to all comments.\nFor clarity, the principal revisions in the manuscript are marked in red.\nThe revised paper has also been reorganized to comply with formatting requirements, including in particular\nthe addition or slight reformulation of transition sentences (however, such changes are not highlighted in red). Some\nreferencesfromtheinitialsubmissionhavebeenremovedtocomplywiththereferencelimitspecifiedintheformatting\ninstructions.\nRESPONSE TO THE COMMENTS OF REVIEWER 1\nWe thank the Reviewer for the positive assessment of our work. We appreciate the recognition of our approach in\nimproving both the practicality and accuracy of decoding correlated errors in QLDPC codes, as well as the value of\nthe FPGA implementation in demonstrating feasibility. We also acknowledge that several points require clarification,\nand we address each of them in detail below.\nComment: TheauthorscallthenewrepresentationfortheparitycheckmatricesGARI.Thetechniqueintroducesa\nnewrowandcolumntoeliminatespecific4-cycles. Thistechniquewaspreviouslydevelopedforclassicaldecoding\nin “Generating Code Representations Suitable for Belief Propagation Decoding” by J. Yedidia, J. Chen and M.\nFossorier and “Polar Codes: Graph Representation and Duality” by M. Fossorier, both of which works are not\ncited when the method is introduced.\nResponse: Thank you for pointing out these references! We have cited them in the revised paper when intro-\nducing the decoding graph perspective of GARI:\n“Wenotethattheaboveprocedurewaspreviouslydeveloped,butappliedonlyto4-cycles,in[43,44]fordecoding\nsome families of classical linear block codes under belief propagation.”\nComment: The modified representation increases the number of rows, columns, and non-zero entries of the matrix.\nSome discussion on whether this leads to additional computational overhead during message passing, and how\nthis compares to the benefits in decoding performance, would add clarity on the tradeoffs.\nResponse: Thank you for pointing this out. Although the modified representation increases the number of rows\nand columns, it actually significantly decreases the number of non-zero entries, and consequently the computa-\ntional load during message passing. This was insufficiently discussed in the original submission, and we have\nadded the following clarifications in the revised manuscript on page 5:\n“We also note that, although the above procedure augments the decoding graph with additional error and check\nnodes, it increases the number of edges by only one when applied to a 4-cycle, preserves the number of edges\nwhen applied to a 5-node biclique, and strictly reduces the number of edges in all other cases. This can be easily\nseen by comparing the number of edges in Fig. 2b and Fig. 2c. Consequently, the augmented graph may contain\nfewer edges than the original graph, implying that an MP decoder operating on the augmented graph may incur\nareducedcomputationalload(i.e., performsfewermessageupdatesperiteration)comparedtothesamedecoder\noperating on the original graph. This is typically the case for correlated detector error model matrices D ,\nXYZ\ndue to the generally large size of the maximal bicliques (see also the BB code examples below).\n[...]\nSee Table I for a quantitative summary of the size, average row weight, and number of 4-cycles in D , D ,\nX Z\nD , and D for various BB codes. The number of non-zero entries in each matrix can be computed as the\nXYZ XYZ\nproduct of the number of rows and the average row weight. For instance, for the [[144, 12, 12]] code, the D\nXYZ\nmatrixhas1728×226.46=391323non-zeroentries,whiletheD matrix(includingD ,D ,andthebottom\nXYZ X Z\npart) has 792×34.18+936×32.77+16704×8.11=193213 non-zero entries, which is less than half the number\nof non-zero entries in D .”\nXYZ\nsatisfactionoftheZsyndrome). Thisalignswellwiththespecificmemorysettingwherepreservingasinglebasis\nis the objective. How would the method might generalize to experiments where both logical generators must be\nmaintained, such as arbitrary state preservation experiments?\nResponse: Our method naturally applies to experiments in which both X and Z logical operators must be\npreserved. This was discussed in the following paragraph of the original submission (page 5), with text in red\nadded in the revised version for further clarification.\n“As an aside, we note that we also experimented with a different early stopping criterion, checking both Z and\nX syndromes, that is D e¯ =s and D e¯ =s (while, of course, we could estimate only the X-logical error\nZ X Z X Z X\nrate, based on the decoded e¯ ). This yielded a similar X-logical error rate but increased the average number of\nX\ndecoding iterations by approximately a factor of two, since the decoder needs to converge on both D and D\nZ X\nbefore it stops. Also, convergence on D generally occurs faster, aided by the final measurements of physical\nZ\nqubits in Z basis. Importantly, such a stopping criterion could be used in experiments in which both X and Z\nlogical operators must be preserved. However, our focus is on memory experiments involving the preservation\nof a single type of logical operator (in line with current practice in the literature), and we aim to show how its\npreservation can be enhanced by effectively exploiting correlations among X, Y, and Z errors.”\nComment: Thenumericalresultsemployamaximumof400decodingiterations,whereastheFPGAimplementation\nappears to operate within only 10 or fewer. Where is this discrepancy between simulations and implementation\nattributed to? It would be valuable to know the logical error rate achievable when limiting simulations to 10\niterations, and whether restricting both simulation and hardware runs to, for example, 4 or 5 iterations might\nprovide a fair and practically relevant comparison.\nResponse: We consistently use a maximum of 400 iterations in all simulations. The confusion likely arose from\nFig. 6, where we only show the percentage of decoding runs that converge at iteration i, for i = 1,...,10. The\nfollowing clarification has been added to the caption of Fig. 6 in the revised version:\n“Percentageofdecodingruns(y-axis)convergingatagiveniterationnumber(x-axis)fortheBBcode[[144,12,12]]\nat a physical error rate of 10−3. On the x-axis, only the first 10 iterations out of 400 are shown for clarity. The\nvertical dashed line shows the cut-off iteration number (4 iterations) to stay within the per-round time budget\nof 1µs. The figure shows that in 99.992% of decoding runs complete within the considered time budget.”\nComment: The latency and throughput results are strong, but it seems that the worst-case latency remains the\nmain limitation with respect to real-time constraints. Discussion on possible mitigation strategies, even if they\ninvolve tradeoffs in accuracy, would be useful for understanding and comparing.\nResponse: We agree that the worst-case latency is an important aspect of variable-latency decoders that has\nnot been discussed in the original submission. We have included the following discussion in the “Real Time\nDecoding” section of the revised version:\n“We also note that our decoder has a worst-case latency corresponding to the situation in which it reaches the\nmaximum of 400 decoding iterations, which occurs with a probability approximately equal to the logical error\nrate (it is also possible for the decoder to converge on the very last iteration, but this is rare, as suggested by\nFig. 6). However, we did not attempt to optimize the maximum number of iterations, and similar accuracy\ncould likely be achieved with a much lower maximum number of decoding iterations (Fig. 6 again provides some\nsupportingevidenceforthis). Moreover,fordecoderswithvariablelatency,ithasbeenshowninRef.[51](seealso\nthe analysis in Ref. [52]) that even when the worst-case latency exceeds the available time budget, the backlog\nproblem can be avoided, provided that the decoding latency tail is not too long and occurs with sufficiently low\nprobability.”\nComment: Finally, releasing a CPU based implementation, even in a simplified form, would greatly support repro-\nducibility and allow others to benchmark or build upon this work.\nResponse: We have included a Code Availability statement in the paper, providing a link to an open-access\nrepository containing the source code used for our simulations.\nWe thank the Reviewer for the positive assessment of our work. We are delighted that the Reviewer finds our GARI\napproach, including its treatment of 4-cycles and its ability to achieve state-of-the-art decoding performance, to be\nan outstanding contribution to practical quantum error correction. We also appreciate the recognition of our FPGA\nimplementation and the accompanying analysis. We have carefully considered the additional comments provided and\naddress each of them in detail below.\nComment: There are some inconsistent usages throughout: inference (which I think is intended) vs interference,\nBP-OSD vs BPOSD.\nResponse: Thank you for pointing this out. We have corrected this in the revised manuscript.\nComment: Page 1, second column: I agree that qLDPC codes typically have short cycles (in fact 4-cycles) but are\nlow-weight stabilisers specifically the reason for this?\nResponse: The comment refers to the following sentence from the paper: “For QLDPC codes, the situation is\nmarkedly different: their low-weight stabilizers – the very property that makes them suitable for fault-tolerance\n– imply that their graphs have a girth of Θ(1), causing MP decoders to fail at producing sufficiently accurate\ninference [18]”.\nIt is true that the non-binary graph associated with any stabilizer code necessarily contains 4-cycles, due to the\ncommutation property of the stabilizer generators (checks). However, our sentence is meant to emphasize that\nshort cycles also occur when decoding X and Z errors separately, for example, in the binary bipartite graphs\ncorrespondingtothematricesH andH ofaCSSQLDPCcode. Thesegraphsmayhavegirthsstrictlygreater\nX Z\nthan 4. However, because any row of H is a codeword of H , the girth of the graph associated with H is\nZ X X\nupper-boundedbytwicetheminimumweightoftherowsofH (and,ofcourse,thereversealsoholds). Ingeneral\nZ\nthisisalooseupperbound,thoughitmaybetightinsomecases–forinstance,forthesurfacecode,thegenerator\nweightis4, whilethegirthofH andH (consideredasbipartitegraphs)is8. Butthemainobservationisthat\nX Z\nlow (constant) weight stabilizers imply that the classical minimum distance is Θ(1), and consequently, the girth\nofanygraphrepresentationofthecodeisalsoΘ(1). ThiscontrastswiththeclassicalLDPCcasediscussedearlier\nin the same paragraph. In the revised version, reference [18] has been added to clarify the intended meaning.\nComment: Nextparagraph: “nolongersignificantlyimprove”presumablymeanssomethinglikeashallowergradient,\nbut still a decrease with decreasing physical error rate.\nResponse:OuroriginalsentencewasindeedintendedtoconveyexactlywhattheReviewerdescribes: ashallower\ndecline in the logical error rate with decreasing physical error rate, rather than a complete plateau. To clarify\nthis and avoid potential ambiguity, we have rephrased the sentence in the revised manuscript as follows:\n“Short cycles (the shortest and most harmful being the 4-cycle) can lead to early error floors, where the decoder\nbecomes trapped on certain error patterns [19, 20], causing a shallower – potentially nearly flat – decline in the\nlogical error rate as the physical error rate decreases.”.\nComment: Page 2, fig 1 caption:\n• 18080isastrangenumber. Perhapsexplainthatthisis80+threehundred60s,notonebigundifferentiated\nbudget\n• Youexplainmuchlaterthatyoudidn’tensemblefordistance6becauseitdidn’tmakeanoticeabledifference,\nbut perhaps it’s worth mentioning here\nResponse: We have corrected this in the revised manuscript: “The XYZ-Relay-BP-5 decoder uses 301 DMem-\nBP decoders in series with up to 300×60+80= 18080 decoding iterations...”, and later “For distance 6, only a\nsingle GARI-NMS decoder is used, as employing multiple decoders does not further improve performance.”\nComment: Page 3, second column: I can imagine a situation where a Y error is possible with no corresponding X\nor Z error, but the description is easily patched up in that case.\nResponse:WeagreewiththeReviewer. However,ourfocusisoncorrelatederrors,i.e.,correlationsarisingfrom\nerrorsthattaketheformof“pure”Y errorsorcombinationsofX andZ errors. Thefollowingsentencehasbeen\naddedintherevisedmanuscript,immediatelybeforethestatementofthepropertiesoftheD andD′ matrices:\nX X\n4\n“Since our focus is on correlated errors, we will assume that any circuit location where a Y error may occur can\nalso experience X and Z errors. Therefore, matrices D and D′ satisfy the following properties, ...”\nX X\nComment: Page 4, first column: “Similar statements holds”.\nResponse: Thank you! Corrected.\nComment: Page5,topoffirstcolumn: “(usingthefactthattheprocedureisappliedtomaximalbicliques).” Iagree\nwith the statement this is in support of but don’t think this is the most helpful hint.\nResponse: We agree that the hint in parentheses is unnecessary and have removed it in the revised version.\nComment: “it results in a reduced number of edges” This is false if the biclique is a 4-cycle, which is transformed\nto a graph with 5 edges. You’re at least break even for any larger clique though.\nResponse: Thank you for pointing this out. We have revised the manuscript as follows:\n“We also note that, although the above procedure augments the decoding graph with additional error and check\nnodes, it increases the number of edges by only one when applied to a 4-cycle, preserves the number of edges\nwhen applied to a 5-node biclique, and strictly reduces the number of edges in all other cases. This can be easily\nseen by comparing the number of edges in Fig. 2b and Fig. 2c. Consequently, the augmented graph may contain\nfewer edges than the original graph, implying that an MP decoder operating on the augmented graph may incur\nareducedcomputationalload(i.e., performsfewermessageupdatesperiteration)comparedtothesamedecoder\noperating on the original graph. This is typically the case for correlated detector error model matrices D ,\nXYZ\ndue to the generally large size of the maximal bicliques (see also the BB code examples below).”\nAnd later in the same section:\n“See Table I for a quantitative summary of the size, average row weight, and number of 4-cycles in D , D ,\nX Z\nD , and D for various BB codes. The number of non-zero entries in each matrix can be computed as\nXYZ XYZ\nthe product of the number of rows and the average row weight. For instance, for the [[144, 12, 12]] code, the\nD matrix has 1728×226.46=391323 non-zero entries, while the D matrix (including D , D , and the\nXYZ XYZ X Z\nbottom part) has 792×34.18+936×32.77+16704×8.11=193213 non-zero entries, which is less than halft the\nnumber of non-zero entries in D .”\nXYZ\nwhich could be applied, not a unique sensible choice.\nResponse:Werephrasedas: “... theGARImatrixD istheadjacencymatrixofthegraphproducedbyone\nXYZ\npossible application of the GARI transform to the decoding graph with adjacency matrix D ”\nXYZ\nComment: final paragraph, ”is (5)” → in (5)?\nResponse: Thank you! Corrected.\nComment: Page 6, second column: “all schedules are assumed to be” Isn’t this something you decided?.\nResponse: Modified as: “In the following, all schedules are horizontal.”\nComment: “Note that a serial schedule processing the rows of the bottom matrix in their natural order would\nperform exactly the same computations...” Is this still true given possible intervening updates from the top part\nof the matrix?.\nResponse: Yes, this is indeed true in general for layered schedules. In a layered decoder, layers are processed\nsequentiallyinagivenorder. Theorderinwhichthelayersareprocessedaffectsthecomputedmessages. However,\nwithin each layer, the order in which rows (checks) are processed – whether in parallel or sequentially – does not\naffect the computed messages, but it does, of course, affect the decoding latency. This also applies in our case,\nasthedecodercanbeviewedasalayereddecoderovertheentirematrix, withlayerscomposedofasinglerowin\nthetoppartandmuchlargerlayersinthebottompart(thesizeofthelayerisirrelevanttotheabovediscussion).\nResponse: Modified as: “The NMS normalization factor is set to either (cid:80)5 1/2i = 0.96875 or (cid:80)7 1/2i =\ni=1 i=1\n0.9921875, chosen to optimize accuracy while facilitating hardware implementation using bit shifts and adders.”\nComment: Page 10: “Finally, for completeness ...” At what physical error rate was 1.6e-7 the observed logical error\nrate?\nResponse: Modified as: For distance d=12 and physical error rate 10−3, the D -NMS-×24 decoder achieves a\nZ\nlogical error rate of 1.6×10−7, on par with BPOSD.\nComment: Real-time decoding section: does the fact that the components were implemented independently and in\nparticular at different operating frequencies affect how confident we can be in the performance of a full FPGA\nimplementation?\nResponse: While the independent implementations do not capture all interactions that may occur in a fully\nintegrated system, the performance metrics obtained from the separate modules provide a reliable estimate for\ndecoding throughput and resource usage. Communication between modules running at different frequencies can\nbe managed using standard techniques such as dual-clock FIFOs or synchronizer registers, which are commonly\nusedinFPGAdesigns. Ifamulti-FPGAarchitectureisrequiredduetoareaconstraints,modernFPGAssuchas\nthe Virtex VU19P employed in this work integrate a large number of high-speed GTY transceivers, providing an\naggregatedfull-duplexbandwidthofupto4.5Tb/s. Theselinkssupporthigh-densityinter-FPGAcommunication\nusingemerginginterfacestandardsandprotocols,introducingafixed,deterministiclatencytypicallyontheorder\nof hundreds of nanoseconds or tens of nanoseconds when used as raw transceivers without high-level protocols,\nwhich preserves the timing behavior of independently implemented modules. The following sentence has been\nadded in the revised manuscript:\n“[...] This results in a total per-iteration delay of 2.9µs. We note that, in practice, a fully integrated design\nwith proper clock-domain crossing is expected to achieve similar decoding latency, with only negligible overhead\ndue to synchronization. In addition, if multi-FPGA is required, high-speed transceivers such as GTY included\nin V19P, with 4.5 Tb/s of bandwidth and tens of nanoseconds of latency in raw mode can be used to preserve\nthe timing behaviour of the independently implemented modules. ”\nComment: Page 11: “which is currently set to 12 bits to mimic floating-point accuracy” What does this mean?\nResponse: Changed to “to achieve accuracy close to that of a floating-point implementation.”"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The paper presents a promising decoding strategy for bivariate bicycle code memory circuits under circuit-level noise. By\njointly using X and Z syndromes to address Y-type errors, the authors propose an alternative graph formulation together with\nan ensemble of random permutation schedules for Min-Sum belief propagation over a large Tanner graph incorporating X\nand Z detectors. The method demonstrates accuracy comparable to or exceeding previous techniques, and the\naccompanying FPGA implementation helps validate the practicality and efficiency of the approach.\nThe methods and plots are well explained, although it would be helpful to provide a plot that includes the tail of the\ndistribution of decoding iterations in figure 6 as well as the resources of the fpga used by the new method.\nOverall, this paper presents a compelling decoder design backed by solid experimental results, and the FPGA\nimplementation meaningfully demonstrates its potential and practical challenges associated with real-time quantum error\ncorrection.\n(Remarks on code availability)\nThe code is readable and the results are reproducible.", "reviewer_2": "The authors have diligently revised the paper in response to the referee reports. I have two remaining comments.\nOn serial versus layered updates in the bottom part of the matrix: I'd been thinking about serialising the full set of bottom part\nupdates (or further, mixing them with the top part updates), but these would be large architectural changes with significant\nimpacts on implementation size and latency. I have no objections to the text as it stands.\nOn low-weight stabilisers implying low girth: the authors' additional reference clarifies that the argument factors through a\nclaim that an associated classical code has distance O(1), and that all such classical codes have Tanner graphs with girth\nO(1). However, this is false: if you take many disjoint copies of the repetition code you will have bounded distance but a\nTanner graph which is a forest. This code is degenerate in various ways, but it remains unclear to me on what result the\nauthors are basing this claim.\n(Remarks on code availability)\nI was able to compile and run the software by following the instructions in the README. Running the sample script\nlaunched sinter and produced a csv data file as expected.\nI have looked at, but not read in detail, the underlying C implementation, the binding code, and the experiment python script.\nIt will certainly be useful, both to those who may with to run the decoder themselves, and those who wish to inspect the\ndetails of the implementation -- for example, we can see from the code that in the case where no element of the ensemble\nconverges the decoder returns the zero correction.\nThe code in `build_circuit.py` is taken from the repo https://github.com/gongaa/SlidingWindowDecoder. This code is MIT\nlicensed so reuse is fine, and there is a comment giving the source of the copied code, but strictly speaking the MIT license\ntext and copyright attribution should be retained.\nI've just seen the link above labelled \"private link\". My comments above are based on the public github referenced from the\nrevised article. A quick inspection suggests the contents are the same, with the addition of an Apache license file to the\nversion at the private link."}, "author_response": "Response to the Reviewers’ Comments\nDear Reviewers,\nWe sincerely thank the Reviewers for their careful evaluation and insightful comments. In accordance with\nthe requests, we have prepared and submitted a revised version of the manuscript, together with this response\nletter, which provides a point-by-point reply to all comments. For clarity, the principal revisions in the\nmanuscript are marked in red.\nThe revised paper has also been reorganized to comply with formatting and author checklist requirements.\nRESPONSE TO THE COMMENTS OF REVIEWER 1\nWe thank the Reviewer for the positive assessment of our work. We appreciate the recognition of our approach in\nimproving both the practicality and accuracy of decoding correlated errors in QLDPC codes, as well as the value\nof the FPGA implementation in demonstrating feasibility. We have carefully considered the additional comments\nprovided and address each of them in detail below.\nComment: The methods and plots are well explained, although it would be helpful to provide a plot that includes\nthe tail of the distribution of decoding iterations in figure 6 as well as the resources of the FPGA used by the\nnew method.\nResponse: Thank you for the comment. For the first part, we have included a supplementary file with the plot\nshowing the tail of the distribution of decoding iterations and the corresponding discussion in the caption of the\nfigure.\nForthesecondpartofthecomment,asdiscussedonpage10andinthepreviousroundofreviews,amulti-FPGA\nimplementation is required in its current form. One device (V19P) will implement the decoders for the top part\n(D and D ), while another device (V19P) will implement the layered architecture of the bottom part (U and\nX Z\nV). The two devices will communicate through high-speed transceivers. Optimization of resource usage and\nfurther design improvements to reduce the overall footprint of the complete decoder to a single device will be\naddressed in future work.\nComment: Remarks on code availability: The code is readable and the results are reproducible.\nResponse: Thank you for testing and verifying the code!\nRESPONSE TO THE COMMENTS OF REVIEWER 2\nWethanktheReviewerforthepositiveassessmentofourwork. Wehavecarefullyconsideredtheadditionalcomments\nprovided and address each of them in detail below.\nComment: On serial versus layered updates in the bottom part of the matrix: I’d been thinking about serialising\nthefullsetofbottompartupdates(orfurther,mixingthemwiththetoppartupdates),butthesewouldbelarge\narchitectural changes with significant impacts on implementation size and latency. I have no objections to the\ntext as it stands.\nResponse: Thank you for the insight. We did test these variants during our simulations. For the bottom part:\nsincethemaximumvariabledegreeisonlytwo,thefullserialrandomizationoftherowsdoesnotresultinfurther\nimprovement in accuracy and thus layered is the natural approach. We also tested random serialisation of the\nfull matrix and the accuracy was less than this current method of controlled randomisation where we go over\nfirst the bottom part (collect the correlations) and then the top part.\nComment: Onlow-weightstabilisersimplyinglowgirth: theauthors’additionalreferenceclarifiesthattheargument\nfactorsthroughaclaimthatanassociatedclassicalcodehasdistanceO(1), andthatallsuchclassicalcodeshave\nwill have bounded distance but a Tanner graph which is a forest. This code is degenerate in various ways, but it\nremains unclear to me on what result the authors are basing this claim.\nResponse: Thank you for pointing this out. The reviewer is right that this is not a universal case. However,\nsince the statement appeared in the introduction, specifying the cases that do not satisfy this condition would\nrequire defining the graph variables at that stage. We have therefore rewritten the sentence to clarify that this is\na typical case (with edge degree greater than two) rather than a general one. Introducing further detail on this\npoint would not meaningfully affect the contribution of the paper and would add unnecessary complexity at the\nintroductory stage.\n“For QLDPC codes, the situation is markedly different: their low-weight stabilizers – the very property that\nmakesthemsuitableforfault-tolerance–typicallyleadtographswithgirthofΘ(1), causingMPdecoderstofail\nat producing sufficiently accurate inference[18].”\nComment: Remarks on code availability: The code in build_circuit.py is taken from the repo https://github.\ncom/gongaa/SlidingWindowDecoder. This code is MIT licensed so reuse is fine, and there is a comment giving\nthe source of the copied code, but strictly speaking the MIT license text and copyright attribution should be\nretained. I’vejustseenthelinkabovelabelled”privatelink”. Mycommentsabovearebasedonthepublicgithub\nreferenced from the revised article. A quick inspection suggests the contents are the same, with the addition of\nan Apache license file to the version at the private link.\nResponse: Thank you for verifying the code in detail and pointing out about the license. We have added the\nMIT license in the build_cicuit.py for the used function and Apache license of rest of the files. We have\nupdated the GitHub repository (https://github.com/astra-decoders/gari-nms) to address the changes."}]

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