Capacitive piezotronics

Domain: physics
Published: 2026-03-26
Editorial outcome: major_revision

Abstract
Interface engineering by polarization derives a plethora of distinctive phenomena. Most of them focus on modulation of barrier height for controlling carrier transport of direct-current electronics. However, modulating interface width under alternating-current settings and its resultant effects have not been explored. Here, we report the capacitive piezotronics, which utilizes piezoelectric polarization to control the interface width of heterostructures and modulate junction capacitance at high frequency. The built-in electric potential and the interface width can be reversibly tuned with amplitude as high as 0.11 V and 10.5 nm, which presents a high strain sensitivity (> 110 fF/mbar), and surpasses that of commercial capacitive pressure sensors (~0.1-0.7 fF/mbar). It possesses a capacity of mechanically tuning transmission signal of communication systems with an amplitude > 11 kHz, and substantially improving the filtering characteristics particularly for high frequency noise (> 300 kHz). The strain-tuned alternating-current electronics offer a distinctive approach for high quality communication.

Introduction
Interfaces of materials and heterostructures lie at the heart of the laws in condensed-matter physics1. Manipulation of interfaces allows emergent effects and functionalities2, which is critical for designing the post-Moore’s devices. Recently, interface engineering, that utilizes piezoelectric3-6, pyroelectric7,8, ferroelectric9, or flexoelectric10-12 effect to induce polarization in semiconductors, has inspired emerging fields such as resistive piezotronic effect13-15, pyro-phototronic effect16-18, ferroelectronic effect19-21, flexoelectronic effect22-24 and flexo-photovoltaic effect25,26, making great progress towards next-generation electronics/optoelectronics, advanced communications and artificial intelligence. It provides an ideal platform for exploring the fundamental couplings between polarization and intriguing physical processes27. Among these couplings, the resistive piezotronic effect is a typical and important phenomenon of interface engineering by piezoelectric polarization28. Its core concept is that the strain-induced piezoelectric polarization at semiconductor interface can effectively regulate the barrier height, so as to control the carrier transport of direct-current (DC) electronics, resulting in a substantial change of resistance (Fig. 1a). As an inherent effect in non-centrosymmetric semiconductors, this resistive piezotronic effect has made a profound impact on the design and fabrication of DC electronics for mechanosensation29,30, human-machine interfacing31,32 and robotics33-35. The key to achieving resistive piezotronic effect is to tune interface barrier height by using piezoelectric polarization, which has also been the focus of interface engineering by polarization in recent years.

In addition, the interface width of heterostructures, referring to the width of the region where the potential energy is higher than that in the surrounding space, also plays a critical role in semiconductor devices2,36, especially those regarding communication applications such as high-frequency transport37-39 and high-cutoff-frequency radio-frequency diode40,41. It is closely associated with the distribution of built-in electric field and the band structure near the interface, which controls the processes of charge carrier separation, transport, relaxation or recombination within the interface region1. Actually, key properties such as junction capacitance and carrier dynamics under high frequency alternating-current (AC) settings can be effectively controlled through modulating the interface width2, providing a possible scheme for advanced performance of AC electronics/optoelectronics. Particularly, with the wide use of sub-10 nm (even sub-5 nm) materials and development of device miniaturization in present-day technology, the interface width becomes more and more important to device performance. Generally, it can be designed by traditional methods such as atomic-level construction with precision growth equipment, material optimization (with different work functions or dielectric properties), elemental doping, etc., but keeps completely fixed and cannot be modulated further once it is constructed. Some preliminary attempts have been made to modulate the interface width using external stimuli, such as mechanical or optical stimuli42. However, most of these prior works have not provided systematic experiments and clear mechanism explanations. Thus, achieving dynamic manipulation of the interface width without changing the constructed device structure, and exploring the resultant effect are urgently needed, especially for AC electronics/optoelectronics.

Here, we proposed the capacitive piezotronics, demonstrating that polarization potential in piezoelectric semiconductor can be used as a gate signal to reversibly tune the interface width of heterostructures, so as to control the junction capacitance under high frequency AC settings (~kHz-MHz). A substantial capacitive piezotronic effect was discovered in both single and dual Schottky junctions, in which the interface width can be reversibly tuned as high as 10.5 nm and 5.1 nm, respectively. It demonstrates a high sensitivity (ΔC/p > 110 fF/mbar in single Schottky junction) in tuning the junction capacitance, largely outperforming that of commercial MEMS-based capacitive pressure sensors (~0.1-0.7 fF/mbar43,44). Specifically, it can be also used to mechanically tune the oscillation frequency of a typical resonant circuit with a frequency shift > 11 kHz, and substantially increase the cutoff frequency of a filtering circuit. This work provides an in-depth understanding of the discovered capacitive piezotronics towards next-generation AC electronics, demonstrating its huge potential in high-quality communication.

Results
Mechanism of the capacitive piezotronics
Fig. 1b illustrates the main principle of the capacitive piezotronics. The amount of charged donors or acceptors within the depletion region can be modulated by an external voltage. Under AC settings, the applied AC voltage (V_AC) results in a periodic migration of free carriers at the interface, thereby inducing a fluctuation in the amount of charged atoms within in the depletion region. This dynamic behavior resembles a charge-discharge process in a conventional capacitor. Notably, a charge-discharge process has a typical time constant, finally resulting in a substantial phase shift. Thus, a Schottky junction manifests a measurable capacitive characteristic under AC settings, and this capacitance is directly governed by the amount of charged atoms within the depletion region.

In a typical Schottky junction, the interface width (W) specifically refers to the width of the depletion layer at Schottky interface, where the potential energy is higher than that in the surrounding space. The interface width (W) is inversely proportional to the junction capacitance (C) 2:
C = \epsilon_j * S / W, (1)
where S is the area of interface and \epsilon represents the dielectric constant of the semiconductor. On this basis, the interface width could act as the key factor for the capacitive piezotronics.

When a strain or stress is applied on a piezoelectric semiconductor in a Schottky junction, a piezoelectric polarization field is generated at the Schottky interface due to the piezoelectric effect, which significantly influences the migration and redistribution of carriers at the interface, so as to change the interface width (Fig. 1b(ii))45. Taking a metal/n-semiconductor Schottky junction as an example, the negative piezoelectric polarization charges induced by compressive strain will repel electrons away from the interface, resulting in an increase in the amount of the charged donor atoms in the depletion layer. Thus, the interface width increases while the junction capacitance decreases (Fig. 1b(ii-2)). Conversely, the tensile strain/stress-induced positive piezoelectric polarization charges attract electrons near the interface, leading to a decrease in the amount of the charged donor atoms and the interface width, and an increase in the junction capacitance (Fig. 1b(ii-3)). Thus, the strain-induced piezoelectric polarization can effectively modulate the interface width, so as to control the junction capacitance under AC settings. This is the capacitive piezotronic effect, which differs from the previous resistive piezotronic effect that uses piezopotential to control the charge carrier transport of DC electronic devices. The use of inner-crystal piezoelectric polarization potential as a controlling signal, to modify the interface width and achieve precise control of junction capacitance under AC settings, especially at high-frequency systems, is the basis of capacitive piezotronics. The modulation mechanism largely extends the realm of piezotronics to AC applications from a distinctive perspective, and provides a strategy for developing mechanical-stimulation-controlled devices in high-frequency communications (Fig. 1b(iv)).

Relationship between capacitive piezotronics, resistive piezotronics and traditional capacitive effect
The capacitive piezotronics is an extension of the previous resistive piezotronics, but shows significant divergence in both basic principle and application scope. The fundamental nature of capacitive and resistive piezotronics are both interface effects, which asymmetrically modulate local contacts at different terminals of a device using piezoelectric polarization. This piezotronic modification on the terminals can modify its electrical properties, thereby changing the impedance (Z) of the whole device, which can be described as:
Z = R + X = R + i(\omega L – 1/(\omega C)), (2)
where R, X, L and C represent resistance, reactance, inductance and capacitance of the device, respectively, \omega is the angular frequency of AC signal, and i is the imaginary unit. The previous resistive piezotronic effect is primarily characterized under DC conditions (\omega = 0), thus the piezotronic modification is reflected by the resistance (R) of the semiconductor device, which is closely related to its interface barrier height. In contrast, the capacitive piezotronics actually aims at studying the piezotronic modification on semiconductor devices under AC conditions (\omega > 0), where the reactance (X), particularly its capacitive component (C), becomes a critical parameter.

In semiconductor heterostructures, such as p-n junctions, Schottky junctions and tunnelling junctions, this capacitive component is intrinsically associated with the junction capacitances, which is determined by the corresponding interface widths. Thus, the capacitive piezotronic effect focuses primarily on the interfacial electric properties under AC conditions, distinguishing it from the resistive piezotronic effect. As inherent effects in non-centrosymmetric semiconductors, the resistive piezotronics has made a profound impact on the design and fabrication of DC electronics for mechanosensation, while the capacitive piezotronics shows exceptional prospects in AC electronics, such as high-frequency transport and communications.

Furthermore, the capacitive piezotronics significantly differs from but still has some relation with the traditional capacitive effect (Supplementary Note 7). Although both of these two effects ultimately modulate the capacitance of the device, the mechanism is completely different. The capacitive effect realizes variation in capacitance by changing the gap between two electrodes, which is a volume effect that regulates the capacitance without polarity. While, the capacitive piezotronics uses piezoelectric polarization to asymmetrically modulate the interface width at two terminates of Schottky junctions, which is an interface effect that enables substantial modulation of junction capacitance in semiconductor devices. The sensor based on the capacitive piezotronic effect therefore is a distinctive kind of capacitive device, which is well-suited for micro-nano structural integration, with high sensitivity and much miniaturization.

Capacitive piezotronics in single Schottky junction
1. Theoretical simulations of capacitive piezotronic effect
To demonstrate the principle of the capacitive piezotronic effect, we performed Finite Element Analysis (FEA) on a Schottky junction based on Ga-polar (0001) n-GaN at zero bias, where the intrinsic piezoelectric c-axis of n-GaN is oriented perpendicular to the interface (Method). As the compressive strain increases, negative piezoelectric polarization charges will be produced at the interface, resulting in a reduction of the electric potential near the interface (Fig. 2a and Supplementary Fig. 1). This modification in electric potential induced by piezoelectric polarization will in turn increase the conduction band energy level near the interface, and hence raise the built-in potential (V_bi) of the Schottky junction. It is noted that the interface width is proportional with the square root of V_bi at zero reverse bias (V_R = 0)2,
W = \sqrt{2\epsilon_s(V_bi + V_R) / qN_d} = \sqrt{2\epsilon_s V_bi / qN_d}, (3)
where q is the elementary charge, and N_d is carrier concentration. Accordingly, the interface width also exhibits an increment (\Delta W) with the increased compressive strain (Fig. 2b). Generally, the polarization field can increase the conduction band energy level, repelling the electrons away while attracting the holes towards the Schottky interface (Fig. 2c). As a result, the electron concentration decreases while the hole concentration increases near the interface. Since electrons are the majority carrier of n-GaN, the decreased electron concentration near the Schottky interface will induce more charged donor atoms in the depletion layer, resulting in an increased interface width. Specifically, with the compressive strain changed from 0% to 3%, the interface width is increased by ~3.1 nm and the corresponding junction capacitance is decreased by ~0.04 mF/m2 (Fig. 2d). These results show that redistribution of carriers by inner-crystal piezoelectric polarization can modulate the interface width and hence the junction capacitance, strongly demonstrating the possibility of capacitive piezotronics in Schottky junction. It should be worth noting that the piezotronic modifications on the interface width and the junction capacitance have often been ignored in the past DC electronics, but is crucial in AC settings.

2. Interface width engineering in single Schottky junction via piezoelectric polarization
To verify the above theoretical simulations, we fabricated two-terminal devices consisting of a single Schottky junction and an Ohmic contact on a piezoelectric n-GaN single crystal with low carrier concentration (Supplementary Fig. 2). Fig. 3a illustrates the electrical measurement system that uses a DC voltage to apply a bias to the single Schottky junction and simultaneously uses a 2 kHz AC signal (V_AC) to conduct the capacitance measurements under such bias condition. Then, we characterized the capacitance versus bias (C-V) curves and the corresponding (1/C)2-V curves in Fig. 3b. As the reverse bias increases, the junction capacitance gradually decreases and finally tends to a constant value, indicating that the interface width increases until the Schottky junction is completely depleted. While as the forward bias increases, the interface width decreases and thus the junction capacitance increases. As the applied bias gets close to the flat band voltage, the capacitance tends to infinity rapidly. The linear (1/C)2-V dependence at reverse bias also indicates the successful construction of the single Schottky junction, according to the formula of Schottky junction capacitance2,
(1/C)^2 = (W/S)^2 = 2(V_bi + V_R) / (q\epsilon_s N_d S^2). (4)
External loading forces were then applied to the Schottky junction along the polarization c-axis of piezoelectric n-GaN, which were controlled by the displacement of a translation stage (Supplementary Fig. 3). As expected, when the loading force gradually increases, the interface width increases and simultaneously the junction capacitance decreases at the same bias (Fig. 3b, c). The change of junction capacitance reaches a maximum value of ~0.44 nF and correspondingly the interface width is increased by ~10.5 nm at a critical pressure of 0.73 MPa. The strain sensitivity (\Delta C/p) of the devices is measured in our experiments to quantitatively analyze the capacitive piezotronic modulation, which reaches the maximum of ~110 fF/mbar, and largely outperforms than that of commercial capacitive pressure sensors (~0.1-0.7 fF/mbar43,44, Supplementary Note 1). Fig. 3d shows the detailed modulation process in an n-GaN based single Schottky junction. Under loading force, the negative piezoelectric polarization charges generated at the interface will repel electrons away from the interface and effectively enhance the built-in electric potential, which is demonstrated in Fig. 3e. According to formula (3), the enhancement in built-in electric potential further leads to an increase in the interface width, consequently reducing the junction capacitance. Besides, it should be noted that the bias has an influence on the capacitive piezotronic effect (Fig. 3c, f). To be specific, a high reverse bias makes the Schottky junction completely depleted with its interface width and junction capacitance almost unchanged, thus degrading the influence of capacitive piezotronic effect on junction capacitance (Supplementary Note 3). Therefore, the devices exhibit stronger capacitive piezotronic modulation at low reverse bias, showing great potential in AC electronics with low power consumption and long lifetime.

Capacitive piezotronics in dual Schottky junctions
To in-depth understand the capacitive piezotronic effect, we further investigated the force-dependent C-V characteristics of dual Schottky junctions by fabricating a two-terminal device based on back-to-back Schottky junctions (Supplementary Fig. 2). The electrical measurement system in this experiment utilizes a DC voltage to apply bias between junction L and R, which is respectively reverse-biased (L) and forward-biased (R) at negative DC voltage, while overturned at positive DC voltage, and simultaneously utilizes a V_AC signal to conduct capacitance measurements under such bias conditions. As shown in Fig. 4a, the force-induced piezoelectric polarization charges at one junction will increase its interface width, thereby decreasing its capacitance. The piezotronic polarization is spatially confined to the stressed junction (Supplementary Fig. 4). This will lead to an asymmetric modulation on the dual Schottky junction width via the capacitive piezotronic effect.

Firstly, we measured the C-V curves of dual Schottky junctions without loading force (Fig. 4b), and found two peaks (one around –0.5 V and the other around 0.5 V) at low-frequency (< 5 kHz), while only one peak (around 0 V) at high-frequency (≥ 5 kHz). It can be seen that the two peaks at low-frequency are slightly different, resulting from the fabrication induced non-idealities of the dual Schottky junctions (e.g., local variations in effective doping concentration or slightly different metal pad areas). As the frequency increases, the junction resistances have a diminishing effect on the equivalent capacitance of dual Schottky junctions, so that the two peaks decrease until they degenerate into one peak (Supplementary Note 2). Under a force located at the junction L, one of the dual peaks at low-frequency gradually increases while the other decreases, and the C-V curve at low bias region (approximately from –0.5 V to 0.5 V) exhibits a positive offset of 0.11 V with a decrease in the valley point (Fig. 4c). Moreover, an asymmetric phenomenon is also observed at high-frequency condition. The peak value of C-V curve increases steadily and the curve shifts toward positive bias (Fig. 4d). Next, we turned to apply the loading forces on the other Schottky junction, and observed completely overturned asymmetric modulation (Fig. 4f, g). These results further indicate that the asymmetric C-V modulations indeed come from the strain-induced piezoelectric polarization. Furthermore, because the valley point occurs when the dual junctions are balanced, the valley capacitance could reflect the variation of each junction. Accordingly, we can obtain the changes of interface width of dual Schottky junctions from the change in the valley capacitance (Supplementary Note 4), which respectively reaches 5.1 nm (Fig. 4e) and 0.6 nm (Fig. 4h) at 2.42 MPa. The smaller variation in the interface width with force on junction R could be attributed to the higher initial doping concentration near junction R. In order to quantitatively analyze the performance of the capacitive piezotronic device, we calculated the strain sensitivity (\Delta C/p) and found it as high as 9.0 fF/mbar at –0.5 V, which is much larger than that (~0.1-0.7 fF/mbar43,44) of commercial MEMS capacitive pressure sensors (Supplementary Note 1).

The force-dependent variation in C-V curves arises from the asymmetric modulation on dual Schottky junctions via the capacitive piezotronic effect. In the absence of an external loading force, both the low-frequency and high-frequency C-V curves of the dual Schottky junctions are centered at near-zero bias region. When a loading force is applied to only one of the Schottky junctions, the strain-induced negative piezoelectric polarization charges increase both of the built-in electric potential and the interface width of the stressed junction. This asymmetric stimulation requires an additional bias to compensate for the difference in built-in electric potentials, resulting in an obvious shift of the C-V curves. Under low frequencies, taking junction L under loading force as an example, the entire C-V curve shifts toward the positive direction to compensate for the asymmetric potential (Fig. 4c). Consequently, the peak in the negative bias region shifts closer to zero bias. Note that the peak capacitance of C-V curve in low-frequency is primarily dominated by the interface width of the reverse-biased junction (junction L in the negative voltage region and junction R in the positive region). Thus, the peak shifting closer to zero bias is dominated by junction L. An anomalous phenomenon is observed that this peak capacitance increases rather than deceases as the junction L is stressed, which can be attributed to two mechanisms. On the one hand, although the negative polarization charges increase the interface width of the stressed junction, the peak moves to a lower bias owing to the shift of C-V curve, and the lower bias will simultaneously decrease the interface width and hence compensate for the capacitance reduction. On the other hand, the changed effective carrier concentration near the interface enables interfacial electrostatic equilibrium (Fermi Level alignment) to be sustained within a narrower interface width, which also makes a contribution to the increasing capacitance (Supplementary Note 4). For the other peak of C-V curve in the positive bias, the interface width of the unstressed junction R becomes the dominant factor. Since the piezotronic polarization is spatially confined to the stressed junction L, the interface width of the junction R is only influenced by the external bias. As this peak shifts to a higher bias region, the increased bias expands its interface width, and thus decreases the peak capacitance. Conversely, when the force is applied to junction R, the peak value in the negative bias decreases while the other peak value increases (Fig. 4f). This is a unique asymmetric capacitance modulation induced by the capacitive piezotronic effect (Supplementary Figs. 5, 6).

Under high-frequency settings, the capacitance of the peak at near-zero bias is dominated by both of the dual Schottky junctions. The interface widths of dual Schottky junctions exhibit opposing variations with one of the junctions stressed: the stressed junction widens, whereas the unstressed junction narrows. The experimental results further suggest that the narrowed junction may play a dominant role (Fig. 4d, g and Supplementary Fig. 7), leading to an increase in peak capacitance under loading forces. Furthermore, this increase is also ascribed to the variation in the effective carrier concentration near the stressed junction (Supplementary Note 5). These results show the strong modulation of capacitive piezotronic effect on dual Schottky junctions, demonstrating significant potential for mechanically controlled high-frequency AC electronics.

Universal nature of capacitive piezotronics in other piezoelectric semiconductors
In practice, the presence of free carriers in piezoelectric semiconductor will generate an electrostatic screening effect on the produced piezoelectric polarization28. Nevertheless, we still observed remarkable capacitive piezotronic effect in low-carrier-concentration GaN based devices due to the partial screening of piezoelectric polarization. However, the screening effect of free carriers will be substantial in heavy-doped piezoelectric semiconductor. The proposed mechanism of capacitive piezotronics shown in above may therefore be invalid. We conducted the same experiments on dual Schottky junctions using heavy-doped GaN (Supplementary Note 6 and Supplementary Figs. 24, 25). Completely different with the phenomenon of low-carrier-concentration GaN, excess capacitance is generated in C-V characteristics due to the presence of interfacial traps46. No matter which junction the loading force is applied on, the excess capacitance is enhanced gradually without asymmetrical characteristics. This phenomenon mainly arises from the strain-induced bandgap tuning of semiconductor that reduces the Schottky barrier height of the stressed junction.

To show that the capacitive piezotronic effect widely presents in piezoelectric semiconductors, a series of similar experiments were performed in single crystal of ZnO, which is an ideal material with high piezoelectricity and semiconducting properties. Supplementary Fig. 8 shows the C-V characteristics of the ZnO micro-wire based devices under tensile and compressive strain respectively, exhibiting a same trend as those of GaN with low carrier concentration (Fig. 4c). The C-V curve presents a consistent shift towards negative bias and an increasing extremum under tensile strain, while shows a consistent shift towards positive bias and a decreasing extremum with the increased compressive strain. Moreover, the magnitude of tuning in ZnO micro-wire based devices by capacitive piezotronic effect seems to be more effective than that of bulk GaN. This is possibly owing to the fact that more effective piezoelectric polarization is generated within ZnO micro-wire resulted from a much larger strain as well as a higher piezoelectric constant. These results further demonstrate the effectiveness and universality of the capacitive piezotronic effect in piezoelectric semiconductors, which is promising for future mechanically tunable AC electronics and wide range applications.

Capacitive piezotronics for communication systems
The junction capacitance of semiconductor devices (e.g., MS junction, MIS junction, p-n junction) plays a crucial role in high-frequency transport and communications. Utilizing the capacitive piezotronic effect, external mechanical stimuli can precisely tune the junction capacitance, and hence enable frequency modulation and filtering of electrical signal during antenna transductions (Fig. 5a). The equivalent circuit of frequency modulation is schematically shown in Fig. 5b, comprising a resonant circuit made of an inductor (L) and a capacitive piezotronic device with dual Schottky junctions (serving as a tunable capacitor C′). The resonant frequency f of this circuit is governed by:
f = 1 / (2\pi\sqrt{LC'}). (5)
Repetitive measurements on oscillation signals of the circuit were performed under force free and a loading force of 2.42 MPa on the capacitive piezotronic device (Supplementary Fig. 9). Upon loading force, the junction capacitance of the capacitive piezotronic device is enlarged, and hence extends the oscillation period from 3.68 \mu s to 3.86 \mu s, corresponding to an oscillation frequency shift of 11 kHz (Fig. 5c, d). This strain-induced frequency modulation verifies a possible approach based on the capacitive piezotronic effect for signal processing in communication systems.

To further investigate the capacitive piezotronic effect for electrical signal filtering, we designed a low-pass filtering circuit (LPFC): a 10 kHz sinusoidal wave signal was first rectified by a commercial Schottky diode, and then was filtered by the capacitive piezotronic device (serving as a tunable capacitor) (Fig. 5e). The filtered signals of LPFC were systematically carried out under force free condition and a loading force of 2.42 MPa (data reproducibility are presented in Supplementary Fig. 10). Our results show that the sinusoidal wave signal can be partially filtered by the capacitive piezotronic device without external loading force, but there is still some high-frequency noise. When the loading force was applied, the change in junction capacitance of the capacitive piezotronic device resulted in a reduction in its cutoff frequency, and a progressive degradation of high-frequency noise (Fig. 5f). These observations were also verified by the Fast Fourier Transform (FFT) spectrum: the low-frequency signal (≤ 300 kHz) remains preserved, while the high-frequency noise (> 300 kHz) can be completely filtered out by the device under loading force (Fig. 5g and Supplementary Figs. 11, 12). This phenomenon demonstrates the excellent performance of capacitive piezotronics on electrical signal filtering, providing a possibility for unconventional mechanical switching AC devices through dynamic tunning on junction capacitance.

Methods
Materials. The [0001]-oriented single crystal GaN epitaxial wafers were purchased from Suzhou Nanowin Science and Technology Co., Ltd., which were grown on c-plane single crystal sapphire substrates via metalorganic chemical vapor deposition (MOCVD). The specific parameters of GaN epitaxial wafers (provided by Suzhou Nanowin Science and Technology Co., Ltd.) were as follows, dimensions: diameter: 50.8 mm ± 0.2 mm; thickness ≈ 4.5 \mu m; conduction type: n-type; resistivity (300 K) < 0.5 \Omega\cdot cm (carrier concentration ≤ 2\times 10^17 cm–3) and < 0.05 \Omega\cdot cm (carrier concentration > 1\times 10^18 cm–3);

Fabrication of capacitive piezotronic devices. The GaN epitaxial wafers were all cut into 1.0 cm × 1.0 cm squares. The sample pretreatment procedure consisted of sequential ultrasonic degreasing in acetone, absolute ethanol and distilled water (each for 15 mins), followed by surface oxide layer removal using diluted hydrochloric acid (HCl) and drying under nitrogen atmosphere. High-vacuum E-beam, magnetron sputtering and thermal evaporation (Kurt J. Lesker PRO Line PVD 75 and Denton Explorer 14) were used for electrode fabrication. Ti/Al/Ni/Au composite layers were deposited for Ohmic contacts and Pt were deposited to construct Schottky barrier. Circular electrodes with diameter of 1 mm were formed using lithography mask technology. The connection between copper lead wires and electrodes employed high-conductivity silver paste, and the thermal curing was completed in a vacuum environment (60 ℃, –100 kPa).

Capacitive piezotronic measurements. The capacitive piezotronic modification on the devices was performed using a semiconductor device parameter analyzer (Keysight B1500A) equipped with Multi Frequency Capacitance Measurement Unit (MFCMU) module. In MFCMU module, a small V_AC with an amplitude of 200 mV and a frequency ranging from 1 to 10 kHz was applied to the capacitive piezotronic devices. Simultaneously, a sweeping DC voltage with a step size of 6 mV was used to apply a bias on the devices. The equivalent parallel circuit model (C_p) was adopted to obtain the capacitance of these devices. External forces were applied via a high-resolution (10 \mu m) translation stage, with the force-displacement relationship quantitatively monitored in situ using a calibrated pressure sensor.

Signal modulation measurements. For frequency modulation measurements, arbitrary function generator (Tektronix AFG31000) was used to provide charges for resonant circuit, which includes a capacitive piezotronic device and a 680 \mu H inductor. The resonance signal of this circuit was measured by a mixed domain oscilloscope (Tektronix MDO3024). For filtering circuit, a 10 kHz sinusoidal wave signal was also provided by the arbitrary function generator and then half-wave rectified by a commercial Schottky diode. The half-wave rectified signal was filtered by a capacitive piezotronic device and the filtered signal was also measured by the mixed domain oscilloscope.

Theoretical Calculations. The calculation on force-induced deformation in devices was performed with the solid module of COMSOL program. The Young’s modulus of GaN film and Sapphire is 324 GPa and 335 GPa, respectively. The Poisson’s ratio of GaN film and Sapphire is 0.20 and 0.25, respectively. The calculation on capacitive piezotronics was performed with the AC/DC and Semiconductor module of COMSOL program package through a 3D model of 200 nm wurtzite Ga-polar (0001) n-GaN. The top endpoint was set as Schottky contact while the bottom endpoint was set as Ohmic contact and grounded. The intrinsic piezoelectric c-axis points to the Schottky interface and the force is applied along the c-axis. The constants of GaN for numerical simulation were the relative dielectric constant \epsilon_r = 8.9, the mobility of electrons \mu_n = 1000 cm^2V–1s–1, and the mobility of holes \mu_p = 200 cm^2V–1s–1. The electron affinity \chi adopted here was 4.1 eV and the band gap E_g was 3.39 eV. All the material coefficients above are available in COMSOL Multiphysics material library. The temperature was 293.15 K and the carrier concentration is about 8\times 10^16 cm–3. The piezotronic effect was considered with the assumption that the piezoelectric charge was distributed uniformly within a very thin width of W_piezo. With these conditions applied, sweeps of strain were conducted at zero bias using stationary solver with a normal physical-control mesh to demonstrate the potential distribution, conduction band energy and carrier concentration distribution. With the above conditions, change of interface width and capacitance with increasing strain could be calculated.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The article is devoted to the study of a new phenomenon called the capacitive piezotronic effect that occurs at\nsemiconductor-piezoelectric / metal interface under pressuer and voltage application.. Although the magnitudes of these\neffects are relatively small, their practical application holds promise for enhancing the performance of devices where\npressure sensitivity is crucial, such as stress sensors.\nHowever, there are several issues that makes difficult understanding of the presented results and the text.\n1. The terminology and physical principles underlying this work are the first key questions.\n1.1. The authors use the term \"interface width.\" This term is used in physics and electronics, but can mean anything: it can\nambiguously refer to structural, chemical, or electrical characteristics at the junction. In electronics, it typically refers to the\nroughness or length of the transition between two different materials in a heterostructure, or the atomic or chemical\nabruptness at the heterojunction or heterointerface (i.e., how many monolayers the transition from one material to another\noccurs over).\nThe authors do not provide a clear definition of the term in question. Furthermore, the interface width for the unperturbed\ntransition is only indicated in Figure 8 of the Supplementary Information, where it is 68 nm at zero pressure. The\nSupplementary Information further states:\nLine 65 “….. The piezotronic effect was considered with the assumption that the piezoelectric charge was distributed\nuniformly within a width of Wpiezo.”\nWhat is Wpiezo? This term is mentioned only once in the manuscript. In all relevant figures (e.g., Figs. 3d and 4a in the main\ntext), it is represented as a single atomic layer or at least significantly narrower than the overall interface width. If Wpiezo\nindeed corresponds to a single atomic layer, the question arises as to how piezoelectric charge can be uniformly distributed\nover such a thin region. Clear and precise definitions of terms such as Wpiezo and interface width are crucial. Incorrect use\nor ambiguity of these definitions can fundamentally alter the underlying models and, consequently, the results presented in\nthe paper.\n1.2. The term \"capacitive piezotronics\" is quite beautiful. However, although it appears in the title and the first sentences of\nthe abstract, the authors only provide a full explanation starting on line 109. Consequently, readers of the preceding 108\nlines may not understand the precise meaning and scope of the concept being discussed.\nFurthermore, this term is not entirely new. Commercial devices based on \"capacitive piezotronics,\" such as the PCB3801\naccelerometers, appeared on the market as early as 2005. Although these early devices were based on different materials, it\nis worth mentioning this historical context to clarify the relationship of this work to earlier ones.\n1.3 From the very beginning of the manuscript, it should be clearly stated that the study is devoted to piezoelectric\nsemiconductors. In the current version, this fundamental definition appears only in line 122.\n1.4. Care must be taken to ensure that all variables described in the descriptive sections of the text (voltage, for instance) are\nconsistently and accurately related to the precise physical quantities and notations used in the formulas and figures.\n2. The second key questions are devoted to presenting description of experimental results and experiment.\n2.1 I believe the manuscript lacks a clear physical representation of the device under study. In addition to schematic\ndiagrams, it would be helpful to include a more specific illustration or description demonstrating realistic pressure application\nto the device. Furthermore, I would appreciate a photograph or visual representation clearly demonstrating:\nSupplementary, Line 49: “External forces were applied via a high-resolution translation stage, with the force-displacement\nrelationship quantitatively monitored in situ using a calibrated pressure sensor”\n2.2. The supplementary materials contain numerous virtually identical experimental curves (capacitance versus voltage),\nmaking them difficult to understand. Furthermore, frequent references to 20 figures in the main text significantly complicate\nreading and disrupt the flow. I propose reorganizing the article so that the main text remains self-contained and easily\nunderstandable. Instead of citing supplementary materials multiple times on each page of the main article, it would be more\neffective to structure the supplementary materials so as to clearly indicate which sections or figures provide additional\nexplanations or confirm specific parts of the main text.\n2.3 What is the statistics of the results? How many samples were studied?\n2.4. The manuscript contains several examples of the use of non-technical or indefinite adjectives:\nSupplementary:\nLine 48 …. a precisely controlled DC bias …\nLine 50 … high-resolution translation stage…\nLine 145 …. we can get the low-frequency (ω-low) and high-frequency 146 (ω-high) capacitance…\nLine 242 …as the frequency increases, the excess capacitance response should be weakened because the carrier\ncapture/release rate is too slow to keep up with the high-frequency signals…\nMain text\nLine 95 …to precisely control the junction capacitance under high frequency AC settings\nLine 174 … can be precisely controlled by the displacement …\n…..\nAnd more….\nIt is important that these qualitative terms be accompanied by specific numerical values.\n2.5. Error bars should be discussed for experimental results.\n3. The use of the specific words.\n3.1. Quite often the authors use the words, that in principle may mean what maybe they mean, but in context of the paper\nthey are confusing:\nLine 114 “This dynamic hysteresis phenomenon is fundamentally equivalent to the capacitive reactance (XC) inherent in MS\njunction, resembling a charge-discharge process in a conventional capacitor.”\nPhenomenon (if consider dynamic hysteresis as a processes can be equivalent to the another process – charging-\ndischarging). But it cannot not be equivalent to the value, such as capacitive reactance (XC).\nLine 150 “… potential (Vbi) of the Schottky junction. It is noted that…” Who noted that?\nLine 177 “…The linear correlation of (1/C)2-V curve …”.. must be changed by :” The linear (1/C)2-V dependence…”\nLine 195 “… built-in electric potential, which is intuitively demonstrated by the experimental results…”. What means\n“intuitively” in the context of experimental demonstration?\nLine 335 “…For the capacitive piezotronics, reactance (X) is applied to further describe the effect …“. How the measurable\nvalue (X) can be applied… to describe?\n3.2. Quite often the adverbs are used instead of adjectives:\nLine 85: “… Particularly, with widely use of… materials…\nAnd more…\n4. It is also necessary to carefully review and correct the grammar throughout the manuscript.\nIn conclusion,\nI need additional evidence which support the result (see #1 and #2 in my report).\nIt requires better data presentation and more logic and accuracy in the text.\nThe work demonstrates significant results and deserves publication after significant revision.", "reviewer_2": "General Assessment\nThe authors present a comprehensive investigation into how strain-induced polarization in piezoelectric semiconductors can\nbe exploited as an interface engineering mechanism to modulate the interface width and the junction capacitance under AC\noperation in Schottky-diodes structures. The study combines finite element simulations and experimental measurements on\nsingle and dual GaN-based Schottky diodes to explore how controlled compressive strain affects the built-in potential,\ninterface width, and capacitance, reporting strain sensitivities exceeding those of commercial capacitive pressure sensors.\nFurthermore, the authors illustrate the potential of these mechanisms in practical applications by demonstrating\nimplementations in communication circuits such as frequency modulators and filtering systems.\nThe manuscript provides a substantial amount of material supporting the main claims, including\nphysical descriptions, finite element simulations, and a broad set of experimental results. The\nmechanisms are interpreted with an appropriate level of detail, and the inclusion of practical\napplications and comparative analyses strengthens the overall study. Nevertheless, several aspects of\nthe work would benefit from clarification and refinement to further improve its rigor and readability\nbefore it can be considered for publication.\nGeneral Revisions\nIt should be noted that capacitance variation in piezoelectric and piezotronic devices under mechanical stress has been\nreported previously; for instance, in bulk ceramics (Cho et al., JJAP, 1995 10.1143/JJAP.34.1591) and in ZnO-based\nSchottky structures (Zhang et al., Sensors 2021, 21(6), 2253; https://doi.org/10.3390/s21062253).In this respect, the present\nmanuscript goes beyond those studies and offers a conceptual and practical advance.\nNevertheless, in light of the existing literature, the authors are encouraged to cite and briefly discuss these and others prior\nworks, either in the Introduction or main text, and to compare their findings and underlying mechanisms where appropriate.\nIn addition, they are encouraged to balance some novelty statements to ensure that the contribution is presented in a\nbalanced and accurate way. Such refinements would further enhance the credibility of the manuscript and draw clearer\nattention to its genuine advances.\nAbstract Revision\nThe abstract does not clearly specify the type of investigation conducted, whether the reported results are\ntheoretical/simulative or experimental, nor does it explain how the numerical values were obtained. The authors should\nexplicitly state that the study combines finite element simulations and experimental measurements, and that the reported\nnumerical results refer to single and dual GaN-based Schottky devices. This clarification would provide a more accurate and\ntransparent representation of the work.\nManuscript Revisions\n1. In the caption of Figure 1a, please specify that “P” denotes the polarization vector.\n2. In Figure 1b (ii-1, ii-2, ii-3), both compressive and tensile strains are illustrated as acting along the same direction of the c-\naxis. Since tensile and compressive strain correspond to opposite deformation directions, leading to opposite polarization\nvectors, showing both with arrows in the same direction is misleading. The schematic should be revised to accurately depict\nstrain directions relative to the c-axis and the corresponding polarization orientations.\n3. The authors indicate the parameters used in the simulations, but should clarify which crystallographic polarity (Ga-face or\nN-face) is considered and under what bias conditions the simulations were performed.\n4. In addition to the schematics, an optical image of both the single and dual Schottky diodes should be provided. The\nauthors should also specify which capacitor area “S” is used in equation (3).\n5. Since the junction capacitance is analyzed across various bias ranges, including an I–V curve of the Schottky diode under\nstrain-free conditions would provide a more complete picture of the device behavior.\n6. The C–V measurements of the single Schottky diode under compressive strain are reported without indicating the\nfrequency of the AC signal. The authors should specify the frequency used, justify their choice, and clarify whether the\ncapacitance variation depends on frequency, as was done for the dual-Schottky configuration. This might be useful to better\nunderstand the dual-Schottky junction case.\n7. Supplementary Figure 3 should be corrected, as it currently shows the same strain direction for both compressive and\ntensile loading.\n8. In the section “Capacitive piezotronics in dual Schottky junctions”, the authors should specify on which junction the bias is\napplied and explain why they expect that loading one junction does not affect the interface width of the other (line 210-212).\nThey should add a reference to this sentence.\n9. To improve readability, the color scheme of Figure 4b should differ from the subsequent figures. In reference to the\nsentence at line 217 the authors could also specify the parameters (junction area,..) that make the two Schottky junctions\ndifferent and explain how these differences lead to asymmetric C–V peaks. The two Schotkky barriers, indeed, are\nconsidered symmetrical over the manuscript. Additionally, there appears to be an inconsistency: in Figure 4b the left peak is\nhigher than the right one, while the opposite occurs in subsequent figures.\n10. Figures 4c and 4f are not self-explanatory. It is unclear which curve corresponds to the strain-free case. The referee\nsuggests replacing them with Supplementary Figures 8a and 8c, which are clearer. The authors should also indicate,\nat least in the caption, the low and high frequencies used for the strain-dependent measurements. Moreover, the rightward shift\nof the C–V curve under strain is evident near the valley point; the arrows should be repositioned accordingly.\n11. Figure 4c shows that at low bias the C–V curve valley shifts to the right when the left junction is under strain. What do\nthey associate with the leftward shift observed at higher bias?\n12. Just for clarity, the authors could specify why a smaller capacitance variation is observed when the right junction is\nloaded at low frequency, in Figure 4f.\n13. Supplementary Figure 9 does not seem consistent with the description provided in the manuscript. Why is the barrier\nheight of the left junction in reverse mode and under strain (i) lower than in the strain-free condition? Why is the depletion\nwidth in that case smaller than in the strain-free configuration? When the strain is applied to the right junction, why is the left-\njunction barrier height higher than in the other two cases?\nOne would expect the strained junction in reverse mode to exhibit a higher barrier and wider depletion region. If these plots\nrepresent a different potential distribution rather than local barrier heights, the authors should clarify this explicitly. In that\ncase, the statement around lines 210–212 regarding the independence of each junction under strain may need\nreconsideration.\n14. The explanation of the asymmetric strain-induced modulation of the C–V peaks needs clarification. One would expect\nthe strained junction in reverse bias to show lower capacitance than the strain-free case, since its depletion region widens.\nHowever, the observed peak shows higher capacitance. While the shift of the peak to lower negative biases the authors\nrefer to in line 245-248 compensates for the widened barrier, it does not fully explain the higher capacitance compared to the\nstrain-free situation. A more explicit discussion of the interaction between the two junction might be needed to explain\nwhy the capacitance increases despite the widened barrier.\n14. In Supplementary Note 4, the role of Rs in the theoretical model should be clarified.\n15. In Supplementary Note 5, the derivation of Equation (17) is not clear and a reference should be added.\n16. The clarity of the manuscript could be further improved by adding additional details on the device fabrication,\nexperimental procedures, and physical mechanisms directly within the main text, rather than leaving them mainly in the\nSupplementary Information.\n17. The last section of the manuscript “ Relationship between capacitive piezotronics, resistive piezotronics and traditional\ncapacitive effect “ could be summarized and added in the introduction or in the ‘ mechanism of the capacitive piezotronics’,\nsince the main claims have already been introduced."}, "author_response": "Point-to-Point Response to Reviewers’ comments:\nWe would like to thank the reviewers for their in-depth reviews and constructive suggestions\nregarding our manuscript. In the pages that follow, we have provided our responses to each of the\nreviewer’s questions.\nReviewer #1 (Remarks to the Author):\nThe article is devoted to the study of a new phenomenon called the capacitive piezotronic effect that\noccurs at semiconductor-piezoelectric/metal interface under pressure and voltage application.\nAlthough the magnitudes of these effects are relatively small, their practical application holds\npromise for enhancing the performance of devices where pressure sensitivity is crucial, such as stress\nsensors.\nHowever, there are several issues that makes difficult understanding of the presented results and\nthe text.\nResponse:\nWe thank the reviewer for acknowledging the importance of our work. And we also thank the\nreviewer’s detailed and responsible reviewing of our work.\nQuestion #1\nThe terminology and physical principles underlying this work are the first key questions.\nResponse #1:\nThanks for the reviewer’s constructive comment. A clear description of the terminology and physical\nprinciples is indeed crucial for understanding our work. We have made comprehensive revisions to\nthe manuscript and supplementary materials in response to your subsequent Questions #1.1-1.4.\nQuestion #1.1\nThe authors use the term “interface width.” This term is used in physics and electronics, but can\nmean anything: it can ambiguously refer to structural, chemical, or electrical characteristics at the\njunction. In electronics, it typically refers to the roughness or length of the transition between two\ndifferent materials in a heterostructure, or the atomic or chemical abruptness at the heterojunction\nor heterointerface (i.e., how many monolayers the transition from one material to another occurs\nover).\nThe authors do not provide a clear definition of the term in question. Furthermore, the interface\nwidth for the unperturbed transition is only indicated in Figure 8 of the Supplementary Information,\nwhere it is 68 nm at zero pressure. The Supplementary Information further states:\nLine 65 “…The piezotronic effect was considered with the assumption that the piezoelectric\ncharge was distributed uniformly within a width of W .”\npiezo\nWhat is W ? This term is mentioned only once in the manuscript. In all relevant figures (e.g.,\npiezo\nFigs. 3d and 4a in the main text), it is represented as a single atomic layer or at least significantly\nnarrower than the overall interface width. If W indeed corresponds to a single atomic layer, the\npiezo\nquestion arises as to how piezoelectric charge can be uniformly distributed over such a thin region.\nClear and precise definitions of terms such as W and interface width are crucial. Incorrect use\npiezo\nor ambiguity of these definitions can fundamentally alter the underlying models and, consequently, the\nresults presented in the paper.\nResponse #1.1:\nThanks for the reviewer’s insightful comment. We are sorry that our descriptions are not clear. We\nhave now provided precise descriptions of the terminology and revised them in manuscript and\nsupplementary materials as follows.\n(1) The authors use the term “interface width”. This term is used in physics and electronics, but can\nmean anything: it can ambiguously refer to structural, chemical, or electrical characteristics at the\njunction. In electronics, it typically refers to the roughness or length of the transition between two\ndifferent materials in a heterostructure, or the atomic or chemical abruptness at the heterojunction\nor heterointerface (i.e., how many monolayers the transition from one material to another occurs\nover). The authors do not provide a clear definition of the term in question.\nAs is well known, the potential energy within the region near the interface (e.g., in p-n junctions,\nSchottky junctions or tunnel junctions) is higher than that of the surrounding space, forming an\n“energy barrier” region. Ideally, the interface width could be defined as the width of this region,\nwhile the interface barrier height is the energy required for electrons to cross the region.\nPrevious studies about piezotronics mainly focus on regulating the interface barrier height\nutilizing piezoelectric polarization, so as to control the carrier transport and thus change the\n“resistance” of DC devices. It can be concluded as “resistive piezotronics”. In fact, piezoelectric\npolarization could also simultaneously modulate interface width, which is closely associated with\njunction capacitance, the core of capacitive piezotronics proposed in our work.\nIn our experiments, the term “interface width (W)” specifically refers to the width of depletion\nlayer (W ) at Schottky interface, which is a well-established concept in semiconductor physics (Sze,\nde\nS. M. et al. Physics of Semiconductor Devices. John Wiley & Sons, 2021), denoting the width of a\nregion where the mobile charged carriers are completely depleted. This parameter directly affects the\njunction capacitance (C) through the relationship\n𝐶 𝜀S\nwhere S is the area of interface and ε repre=sents t,he dielectric constant of the semicon(Rdu−cto1r).\nS 𝑆 𝑊de\nModulation on the depletion layer width and thus the junction capacitance plays a critical role in\nsemiconductor device, especially for communication applications such as high-frequency transport\nand high-cutoff-frequency radio frequency diode.\nThe term “interface width” instead of “depletion layer width” is adopted in our work, as it\nprovides a more proper and comprehensive description. Theoretically, the interface width includes\nnot only depletion layer width but also the width of insulator/dielectric layer in MIS structures, the\nwidth of functional layer in some composite structures and so on. Also, the traditional theory about\ndepletion layer may become invalid in low-dimensional materials such as nanowires and\ntwo-dimensional materials. Therefore, the term “interface width” is more universal in different\ndevice structures and materials, providing better insight into the mechanism of the capacitive\npiezotronics.\nTo provide a clear and precise description of “interface width”, we have revised the manuscript\nas follows:\n In line 78-80: “In addition, the interface width of heterostructures, referring to the width of the\nregion where the potential energy is higher than that in the surrounding space, also plays a\ncritical role in semiconductor devices…”\n In line 120-122 in section “Mechanism of the capacitive piezotronics”: “In a typical Schottky\njunction, the interface width (W) specifically refers to the width of the depletion layer at\nSchottky interface, where the potential energy is higher than that in the surrounding space…”\n(2) Furthermore, the interface width for the unperturbed transition is only indicated in Figure 8 of the\nSupplementary Information, where it is 68 nm at zero pressure.\nThank the reviewer for this comment. The following revisions are aimed at clarifying the\ninterface width without strain in manuscript:\n In the caption of Figure 3d (line 481-482): “…W represents the initial interface width without\n0\nforce (81 nm at zero bias) and ΔW represents the change of interface width under loading\nforce…”\n In the caption of Figure 4a (line 490-491): “…W represents the initial interface width without\n0\nforce (68 nm at zero bias) and ΔW represents the change of interface width under loading\nforce...”\n(3) The Supplementary Information further states: Line 65 “…The piezotronic effect was considered\nwith the assumption that the piezoelectric charge was distributed uniformly within a width of\nW .” What is W ? This term is mentioned only once in the manuscript.\npiezo piezo\nGenerally speaking, W is the width of the region in which we hypothesis the piezoelectric\npiezo\ncharge uniformly distributes. The piezoelectric polarization induces opposite net charges respectively\ndistributed at the two surfaces of the material. These net charges refer to piezoelectric polarization\ncharges, which are non-mobile ionic charges adjacent to the interface. In simulations, the\npiezoelectric polarization charges are often assumed to be distributed uniformly within a very thin\nwidth, which is denoted as “W ”. Since it is merely an assumption utilized in theoretical\npiezo\nsimulation, we have placed it only in section “theoretical calculations” of “Methods”.\n(4) In all relevant figures (e.g., Figs. 3d and 4a in the main text), it is represented as a single atomic\nlayer or at least significantly narrower than the overall interface width. If W indeed\npiezo\ncorresponds to a single atomic layer, the question arises as to how piezoelectric charge can be\nuniformly distributed over such a thin region. Clear and precise definitions of terms such as\nW and interface width are crucial. Incorrect use or ambiguity of these definitions can\npiezo\nfundamentally alter the underlying models and, consequently, the results presented in the paper.\nFirstly, we would like to clarify that the “W ” doesn’t corresponds to only a single atomic\npiezo\nlayer. The piezoelectric polarization charges in all relevant figures are schematic presentations,\nintended only to clarify the direction of polarization at the interface. Similar presentations have also\nbeen applied in previous works on piezotronics (Liu, S. et al. Adv. Mater., 2019, 31, 1905436; Yu Q.\net al. Nat. Commun., 2022, 13, 778).\nIn fact, “W ” is indeed significantly narrower than the overall interface width. This is because\npiezo\nthat piezo-semiconductor also shows screening effect (though poor than conductor), thus the positive\nand negative charges tend to distribute within a small depth from the surface to get a lower electric\npotential energy. In nanodevices or even microdevices, the assumption that the polarization charge\nwas distributed uniformly within a very thin W has also been proved effective in simulations and\npiezo\ncalculations (Zhang Y. et al. Adv. Mater., 2011, 23, 3004).\nNotably, although W is significantly narrower than the interface width, the polarization\npiezo\ncharges can still effectively modulate the interface characteristics. This is already confirmed by\nprevious studies on “resistive piezotronics”, which have demonstrated that the strain-induced\npolarization charges have a huge impact on the migration and redistribution of carriers at the\ninterface (Liu, S. et al. Adv. Mater., 2019, 31, 1905436; Yu Q. et al. Nat. Commun., 2022, 13, 778).\nTo be specific, negative polarization charges can attract the holes to the interface while keep the\nelectrons away, leading to the enhancement in interface barrier height and width. On the contrary,\npositive polarization charges induce completely overturned changes. In this way, the junction\nresistance and capacitance can be modulated, which is the “resistive piezotronics” in previous works\nand “capacitive piezotronics” of this work, respectively.\nWe have provided a precise description of “interface width” and “W ” and we hope that these\npiezo\nrevisions have resolved the ambiguity in terminology and strengthened the foundation of our\nphysical model.\nQuestion #1.2\nThe term “capacitive piezotronics” is quite beautiful. However, although it appears in the title and\nthe first sentences of the abstract, the authors only provide a full explanation starting on line 109.\nConsequently, readers of the preceding 108 lines may not understand the precise meaning and scope\nof the concept being discussed.\nFurthermore, this term is not entirely new. Commercial devices based on “capacitive\npiezotronics,” such as the PCB3801 accelerometers, appeared on the market as early as 2005.\nAlthough these early devices were based on different materials, it is worth mentioning this\nhistorical context to clarify the relationship of this work to earlier ones.\nResponse #1.2:\nThanks for the reviewer’s constructive and important suggestions.\n(1) The term “capacitive piezotronics” is quite beautiful. However, although it appears in the title\nand the first sentences of the abstract, the authors only provide a full explanation starting on line\n109. Consequently, readers of the preceding 108 lines may not understand the precise meaning\nand scope of the concept being discussed.\nThanks for the reviewer’s praise on the term “capacitive piezotronics” and we agree that its full\nexplanation should be referred at a proper position in the manuscript. Although we highly respect the\nreviewer’s opinion, we would like to clarify that the explanation of “capacitive piezotronics” has\nbeen already presented before line 109 for several times:\n In the abstract of the original manuscript: “…It utilizes the strain-induced piezoelectric\npolarization to precisely control the interface width of heterostructures and hence modulate the\njunction capacitance at a high frequency…”\n In line 93-95 of the original manuscript: “Here, we report the first study of capacitive\npiezotronics, showing that the inner crystal piezoelectric polarization can be used as a “gate”\nsignal to reversibly tune the interface width of heterostructures, so as to precisely control the\njunction capacitance under high frequency AC settings…”.\nWe recognize that these two explanations are underemphasized in our original manuscript and\nwe have revised them to give the emphasis they deserve:\n In line 41-45 in the abstract: “…Here, we report the capacitive piezotronics, which utilizes the\nstrain-induced piezoelectric polarization to precisely control the interface width of\nheterostructures and hence modulate the junction capacitance at a high frequency. It is a\ndistinctive regulation mechanism that is widely present in piezoelectric semiconductors (ZnO,\nGaN, etc.)...”. We highlight the core definition of the capacitive piezotronics to give more\nemphasis on the precise meaning and scope of the concept.\n In line 98-101: “Here, we report the first study of capacitive piezotronics, demonstrating that\npolarization potential in piezoelectric semiconductor can be used as a “gate” signal to\nreversibly tune the interface width of heterostructures, so as to control the junction\ncapacitance under high frequency AC settings…”. We added the “piezoelectric semiconductor”\nin the sentence to further clarify the meaning and scope of the concept.\nMoreover, we would like to provide a brief summary to help the reviewer understand our\nthought about introducing the concept of “capacitive piezotronics”. As the capacitive piezotronics is\nan expansion to the piezotronic effect, we think it would be more readable to introduce from the\ntraditional resistive piezotronics and then propose the new effect by indicating the differences. Based\non this aspect, we firstly introduce the context of polarization-driven interface engineering in\nsemiconductors, highlighting the well-established resistive piezotronic effect that modulates interface\nbarrier height and thus control the current/resistance of DC devices. After that, we demonstrate the\ncritical role of interface barrier width in high-frequency AC electronics, and emphasizes the urgent\nneed for achieving dynamic manipulation of the interface width. Accordingly, we change the focus of\npiezotronic effect from modulation on interface barrier height to that on interface barrier width.\nBased on these foundations, we could claim our core concept “capacitive piezotronics” reasonably.\n(2) Furthermore, this term is not entirely new. Commercial devices based on “capacitive\npiezotronics,” such as the PCB3801 accelerometers, appeared on the market as early as 2005.\nAlthough these early devices were based on different materials, it is worth mentioning this\nhistorical context to clarify the relationship of this work to earlier ones.\nWe thank the reviewer for careful consideration on the historical context of our work. We would\nlike to clarify that the terms “capacitive piezotronics” and “capacitive piezotronic effect” have not\nbeen proposed before. The commercial devices mentioned by the reviewer may be based on the\npiezoelectric effect and capacitive effect, rather than the capacitive piezotronic effect. The\nrelationship between them has been illustrated as follows:\nFirstly, we would like to emphasize the definition of the capacitive piezotronic effect in our\nwork (line 136-139): “Thus, the strain-induced piezoelectric polarization can effectively modulate\nthe interface width, so as to control the junction capacitance under AC settings. This is the\ncapacitive piezotronic effect, which differs from the previous resistive piezotronic effect that uses\npiezopotential to control the charge carrier transport of DC electronic devices.” The capacitive\npiezotronic effect we proposed here is an interfacing modulation effect coupling the piezoelectricity\nand semiconductor properties.\nThe reviewer introduced the PCB3801 accelerometers as a “capacitive piezotronics” based\ndevice. Unfortunately, the detailed information of PCB3801 accelerometers mentioned by the\nreviewer is no longer accessible given its age. But we believe that its basic mechanism may be\nsimilar as the new devices made by “PCB Piezotronics”. Actually, we have already known about the\nPCB Piezotronics Co. Ltd. and their “capacitive” accelerometer devices. However, these “capacitive”\naccelerometers are not based on the “capacitive piezotronics”. According to the PCB Piezotronics\nwebsite, their accelerometers are mostly ICP or MEMS accelerometers. For ICP devices, “under\nacceleration, the seismic mass causes stress on the sensing crystals which results in a proportional\nelectrical output.” And for MEMS devices, “this configuration forms two air gap capacitors\nbetween the proof mass and upper and lower plates.” Thus, we could summarize that the PCB\nPiezotronics accelerometers are actually based on the piezoelectric effect or capacitive effect (by\ntuning the thickness of dielectric layer or bulk dielectric properties), rather than an interfacial\nmodulation in the “capacitive piezotronics”. On the contrary, a typical capacitive piezotronic device\naims at regulating the interface width of the heterostructure, so as to change the junction\ncapacitance. Therefore, we believe that the capacitive piezotronic devices are different from the\ncommercial devices mentioned by the reviewer.\n(3) Although these early devices were based on different materials, it is worth mentioning this\nhistorical context to clarify the relationship of this work to earlier ones.\nThanks for the reviewer’s suggestion. We think that the relationship between our work and the\nearlier ones should be claimed earlier and more explicitly, and a more detailed distinction among all\nof the common force or acceleration sensing mechanisms is also needed. Thus, we added\nSupplementary Note 7 to clarify the piezoelectric effect, capacitive effect and resistive effect based\ndevices. Meanwhile, we reorganized the original “Relationship between capacitive piezotronics,\nresistive piezotronics and traditional capacitive effect” section, which was marked in red, and moved\nit to follow the mechanism section.\nWe are grateful for the reviewer’s suggestions and guidance for our work and we hope our\nresponse would address the reviewer’s question.\nQuestion #1.3\nFrom the very beginning of the manuscript, it should be clearly stated that the study is devoted to\npiezoelectric semiconductors. In the current version, this fundamental definition appears only in line\n122.\nResponse #1.3:\nThanks for the reviewer’s valuable suggestions and we agree that the materials—piezoelectric\nsemiconductor—used in our work should be clearly clarified at the beginning of the manuscript. We\nhave revised the related parts in the manuscript.\n In line 98-100 in the main text: “Here, we report the first study of capacitive piezotronics,\ndemonstrating that polarization potential in piezoelectric semiconductor can be used as a “gate”\nsignal to reversibly tune the interface width of heterostructures, so as to control the junction\ncapacitance under high frequency AC settings...”.\nHere we would also clarify that we actually have mentioned these statements before line 122 for\nseveral times in our original manuscript. The related descriptions are listed as follows:\n At the fourth sentence in abstract of the original manuscript: “…Here we report the capacitive\npiezotronics, a distinctive regulation mechanism that is widely present in piezoelectric\nsemiconductors (ZnO, GaN, etc.)...”. This sentence have been revised in our new manuscript as\n“…It is a distinctive regulation mechanism that is widely present in piezoelectric\nsemiconductors (ZnO, GaN, etc.)...” (line 43-44)\n At the last sentence in abstract of the original manuscipt: “…This study gives a brand-new\nstrain-tuned AC electronics based on piezoelectric semiconductors…”\nWe thank the reviewers for these suggestions. And we hope that these revisions could help the\nreaders to understand the scope and context of our work from the very beginning.\nQuestion #1.4\nCare must be taken to ensure that all variables described in the descriptive sections of the text\n(voltage, for instance) are consistently and accurately related to the precise physical quantities and\nnotations used in the formulas and figures.\nResponse #1.4:\nWe sincerely thank the reviewer for this valuable suggestion. In response, we have conducted a\nthorough, line-by-line check of the entire manuscript and supplementary information to ensure all\nvariables are perfectly aligned with their representations in formulas and figures. The main revisions\ninclude:\n(1) The applied direct and alternating voltage have been all denoted as “V ” and “V ”,\nDC AC\nrespectively, in Figure 1. Also, revisions include:\n In line 113-115 in section “Mechanism of the capacitive piezotronics”: “…Under AC settings,\nthe applied alternating voltage (V ) results in the periodic migration of free carriers at the\nAC\ninterface, thereby inducing a fluctuation in the amount of charged atoms within the depletion\nregion…”\n In line 212-214 in section “Interface width engineering in single Schottky junction via\npiezoelectric polarization”: “…the electrical measurement system that uses a DC voltage to\napply a bias to the single Schottky junction and simultaneously uses a 2 kHz AC signal (V ) to\nAC\nconduct the capacitance measurements...”\n In line 415-416 in “Methods”: “…a small V with an amplitude of 200 mV and a frequency\nAC\nranging from 1 to 10 kHz was applied to the capacitive piezotronic devices…”\n(2) The bias applied in measurements have been all denoted as “(DC)Bias” in Figure 3, Figure 4,\nSupplementary Figures 2, 5, 7, 8, 14, 17-27, 29, 30. Also, revisions include:\n In line 193 in Supplementary Note 3.2: “…It is due to the nonlinear dependence between the\njunction capacitance and the bias…”\n In line 318-320 in Supplementary Note 6.1: “…Note that the junction L is forward-biased under\npositive bias, while the junction R is forward-biased under negative bias...”\n In line 333-335 in Supplementary Note 6.2: “…the junction L is forward-biased at positive bias\nand thus the corresponding excess capacitance occurs at positive bias; while the interface traps\nlocated at junction R induces the excess capacitance at negative bias…”\n(3) The output signals in frequency modulation or filtering circuit have been all denoted as “Output\nsignal” in Figure 5 and Supplementary Figures 9-12.\n(4) The elementary charge has been denoted as “q” in Figure 2 and Supplementary Figure 17, in\nformulas (3), (4), (S-18) to (S-22), (S-26) to (S-33), (S-35) to (S-36) and (S-38) to (S-39). Also,\nrevisions include:\n In line 194 in section “Theoretical simulations of capacitive piezotronics effect”: “…where q is\nthe elementary charge…”\n In line 464 in the caption of Figure 2b: “…q represents the elementary charge…”\n In line 140 in Supplementary Note 2.2: “…q is the elementary charge…”\n(5) The interface barrier height has been all denoted as “φ” in Figure 1, in formula (S-23), (S-26),\n(S-32) and (S-33). Also, revisions include:\n In line 457-458 in the caption of Figure 1b: “…W is the initial interface width of Schottky\n0\njunction, Δφ and ΔW represent the change of the interface barrier height and width,\nrespectively...”\n In line 144-145 in Supplementary Note 2.2: “…φ and φ are the interface barrier heights of the\n1 2\nSchottky junctions L and R…”\n In line 157-158 in Supplementary Note 3.1: “…the interface barrier height (φ) and width (W)\nare closely related to it…”\n In line 232-234 in Supplementary Note 4.2: “…which also represents the interface barrier\nheights are equal here (φ = φ ). Specifically, when the configuration of dual Schottky junctions\n1 2\nis perfectly symmetric (φ = φ at zero bias)…”\n1 2\n In line 244 in Supplementary Note 4.2: “…and thus V > V , φ > φ …”\nbi1 bi2 1 2\n In line 301-302 in Supplementary Note 5: “…when the configuration of dual Schottky junctions\nis perfectly symmetric (φ = φ at zero bias)…”\n1 2\n In line 572-573 in the caption of Supplementary Figure 20b, c: “…The asymmetry in dual\nSchottky junctions is set by the differences between interface barrier heights (ΔBH = φ – φ ).”\n2 1\n In line 595 in the caption of Supplementary Figure 23a, b: “…(ΔBH = φ – φ )…”\n2 1\n(6) The ratio of the junction resistances has been denoted as “r” in formula (S-15), (S-16), (S-22),\n(S-24), (S-25). Also, revisions include:\n In line 120 in Supplementary Note 2.2: “…where r is the ratio of the junction resistances R and\n1\n In line 204-205 in Supplementary Note 4.1: “…the low-frequency C-V characteristics exhibit an\nevident dependence on the ratio of junction resistances (r)…”\nOther detailed revisions include:\n The word “Resistor” has been replaced by “Resistance” in Figure 1a.\n The formula of resistance and capacitance have been replaced by “ ” and “ ”\n𝑞𝜑 1\nin Figure 1a, b. 𝑅 ∝ exp(𝑘𝑇) 𝐶 ∝ 𝑊\n The term “junction width” has been replaced by “interface width” in Figure 1b and 4a.\n The notations in equivalent circuit in Figure 4b, “C ” “R ” “C ” “R ”, have been replaced by\n1 1 2 2\n“C ” “R ” “C ” “R ”, respectively.\nL L R R\n The change in built-in electric potential induced by piezoelectric polarization, “V ”, has been\npiezo\nreplaced by “ΔV ” and the built-in potential after being regulated by polarization, “V ”, has\nbi bi\nbeen replaced by “V ′” in Supplementary Figure 18.\nbi\nThe manuscript has been significantly improved by this process, and we are grateful for the\nreviewer’s suggestions and guidance for our work.\nQuestion #2\nThe second key questions are devoted to presenting description of experimental results and\nexperiment.\nResponse #2:\nThanks for the reviewer’s constructive comment. A clear description of experimental results and\nexperiment is indeed crucial for understanding our work. We have made comprehensive revisions to\nthe manuscript and supplementary materials in response to your subsequent Questions #2.1-2.5.\nQuestion #2.1\nI believe the manuscript lacks a clear physical representation of the device under study. In addition to\nschematic diagrams, it would be helpful to include a more specific illustration or description\ndemonstrating realistic pressure application to the device. Furthermore, I would appreciate a\nphotograph or visual representation clearly demonstrating:\nSupplementary, Line 49: “External forces were applied via a high-resolution translation stage, with the force-displacement\nrelationship quantitatively monitored in situ using a calibrated pressure sensor”\nResponse #2.1:\nThank you for this constructive suggestion. Here we have provided Figure R1 to show the optical\nimages of the single and dual Schottky junctions. And a photograph demonstrating realistic pressure\napplication to the device is included in Figure R2, where “External forces were applied via a\nhigh-resolution translation stage, with the force-displacement relationship quantitatively monitored\nin situ using a calibrated pressure sensor”.\nIn revisions, these figures have been added into Supplementary Figure 2 and Supplementary\nFigure 3 to further improve our work.\nFigure R1 | Capacitive piezotronic devices. a, The device based on dual Schottky junctions. b, The\ndevice based on single Schottky junction. c, The optical image of the Schottky contact (Pt/n-GaN).\nForce is applied on the circular area and the lead wires are connected to the strip area. The interface\narea S = 0.8296 mm2. d, The optical image of the Ohmic contact (Ti/Al/Ni/Au/n-GaN).\nFigure R2 | Measuring system. a, A total view of the measuring system. b, Force application and\nsensing module, containing an intender, a sensor and a translation stage. c, The intender. d, The\nsoftware for data collection and processing.\nQuestion #2.2\nThe supplementary materials contain numerous virtually identical experimental curves (capacitance\nversus voltage), making them difficult to understand. Furthermore, frequent references to 20 figures\nin the main text significantly complicate reading and disrupt the flow. I propose reorganizing the\narticle so that the main text remains self-contained and easily understandable. Instead of citing\nsupplementary materials multiple times on each page of the main article, it would be more effective\nto structure the supplementary materials so as to clearly indicate which sections or figures provide\nadditional explanations or confirm specific parts of the main text.\nResponse #2.2:\nThank the reviewer’s suggestion. We have reorganized both of the main text and the supplementary\ninformation.\n(1) The detailed descriptions on device fabrication, experimental procedures and physical\nmechanisms are now added into the main text to make it self-contained. Nevertheless, due to\nspace constraints, we still have to use some references to the supplementary information in the\nmain text. We have endeavored to ensure that readers can grasp the core meaning of the main\ntext without needing to consult the supplementary information. Revisions include:\n In line 248-252 in section “Capacitive piezotronics in dual Schottky junctions”: “…The\nelectrical measurement system in this experiment utilizes a DC voltage to apply bias between\njunction L and R, which is respectively reverse-biased (L) and forward-biased (R) at negative\nDC voltage, while overturned at positive DC voltage, and simultaneously utilizes a V signal to\nAC\nconduct capacitance measurements under such bias conditions…”\n In line 271-276 in section “Capacitive piezotronics in dual Schottky junctions”: “…Furthermore,\nbecause the valley point occurs when the dual junctions are balanced, the valley capacitance\ncould reflect the variation of each junction. Accordingly, we can obtain the changes of interface\nwidth of dual Schottky junctions from the change in the valley capacitance (Supplementary Note\n4), which respectively reaches 5.1 nm (Fig. 4e) and 0.6 nm (Fig. 4h) at 2.42 MPa. The smaller\nvariation in the interface width with force on junction R could be attributed to the higher initial\ndoping concentration near junction R...”\n In line 280-315 in section “Capacitive piezotronics in dual Schottky junctions”:\n“The force-dependent variation in C-V curves arises from the asymmetric modulation on dual\nSchottky junctions via the capacitive piezotronic effect. In the absence of an external loading\nforce, both the band structure and carrier distribution of the dual Schottky junctions remain\nsymmetric, resulting in C-V curves centered at zero bias. When a loading force is applied to only\none of the Schottky junctions, the strain-induced negative piezoelectric polarization charges\nincrease both of the built-in electric potential and the interface width of the stressed junction.\nThis asymmetric stimulation requires an additional bias to compensate for the difference in\nbuilt-in electric potentials, resulting in an obvious shift of the C-V curves. Under low\nfrequencies, taking junction L under loading force as an example, the entire C-V curve shifts\ntoward the positive direction to compensate for the asymmetric potential (Fig. 4c). Consequently,\nthe peak in the negative bias region shifts closer to zero bias. Note that the peak capacitance of\nC-V curve in low-frequency is primarily dominated by the interface width of the reverse-biased\njunction (junction L in the negative voltage region and junction R in the positive region). Thus,\nthe peak shifting closer to zero bias is dominated by junction L. An abnormal phenomenon is\nobserved that this peak capacitance increases rather than deceases as the junction L is stressed,\nwhich can be attributed to two mechanisms. On the one hand, although the negative polarization\ncharges increase the interface width of the stressed junction, the peak moves to a lower bias\nowing to the shift of C-V curve, and the lower bias will simultaneously decrease the interface\nwidth and hence compensate for the capacitance reduction. On the other hand, the changed\neffective carrier concentration near the interface also makes a contribution to the increasing\ncapacitance (Supplementary Note 4). For the other peak of C-V curve in the positive bias, the\ninterface width of the unstressed junction R becomes the dominant factor. Since the piezotronic\npolarization is spatially confined to the stressed junction L, the interface width of the junction R\nis only influenced by the external bias. As this peak shifts to a higher bias region, the increased\nbias expands its interface width, and thus decreases the peak capacitance. Conversely, when the\nforce is applied to junction R, the peak value in the negative bias decreases while the other peak\nvalue increases (Fig. 4f). This is a unique asymmetric capacitance modulation induced by the\ncapacitive piezotronic effect (Supplementary Figs. 5, 6). Under high-frequency settings, the\ncapacitance of the peak at near-zero bias is dominated by both of the dual Schottky junctions.\nThe interface widths of dual Schottky junctions exhibit opposing variations with one of the\njunctions stressed: the stressed junction widens, whereas the unstressed junction narrows. The\nexperimental results further suggest that the narrowed junction may play a dominant role (Fig.\n4d, g and Supplementary Fig. 7), leading to an increase in peak capacitance under loading\nforces. Furthermore, this increase is also ascribed to the variation in the effective carrier\nconcentration near the stressed junction (Supplementary Note 5). These results show the strong\nmodulation of capacitive piezotronic effect on dual Schottky junctions, demonstrating significant\npotential for mechanically controlled high-frequency AC electronics.”\n The section “Methods” has been added to the end of the revised manuscript, which includes\ndetailed device fabrication and experimental procedures.\n(2) The supplementary notes have been integrated to fewer parts and rearranged to be more logical\nand readable:\n The original Supplementary Note 4 has been moved to Supplementary Note 2 in the revised\nversion, and simultaneously more comprehensive descriptions have been added;\n The original Supplementary Note 2 and 3 have been merged into Supplementary Note 3 in the\nrevised version;\n The original Supplementary Note 5 and 6 have been merged into Supplementary Note 4 in the\nrevised version, and simultaneously more comprehensive descriptions have been added;\n The original Supplementary Note 7 has been moved to Supplementary Note 5 in the revised\nversion;\n The original Supplementary Note 8 and 9 have been merged into Supplementary Note 6 in the\nrevised version;\n Supplementary Note 7 has been added into the revised version.\nThanks again for the reviewer’s guidance for our work.\nQuestion #2.3\nWhat is the statistics of the results? How many samples were studied?\nResponse #2.3:\nThanks for the reviewer’s comments. We have performed a series of additional experiments, and\nthe measured data of three independent devices with single Schottky junction and three independent\ndevices with dual Schottky junctions are shown in Figure R3. The qualitative behaviors remain\nconsistent across all tested devices, indicating that the underlying physical mechanisms is universally\nvalid, which could further confirm our conclusions. Furthermore, the repeatedly results of the\ndevices have been discussed in Response #2.5, indicating a highly stable and reproducible\nmodulation behavior. We have added them in Supplementary Figure 29 and 30.\nFigure R3 | Force-dependent C-V characteristics of multiple independent devices. a,\nForce-dependent C-V characteristics of devices 1-3 based on single Schottky junctions. b,\nForce-dependent low-frequency (1 kHz) C-V characteristics of devices 4-6 based on dual Schottky\njunctions. c, Force-dependent high-frequency (10 kHz) C-V characteristics of devices 4-6 based on\ndual Schottky junctions.\nQuestion #2.4\nThe manuscript contains several examples of the use of non-technical or indefinite adjectives:\nSupplementary:\n Line 48 …a precisely controlled DC bias…\n Line 50 …high-resolution translation stage…\n Line 145 …we can get the low-frequency (ω-low) and high-frequency 146 (ω-high)\ncapacitance…\n Line 242 …as the frequency increases, the excess capacitance response should be weakened\nbecause the carrier capture/release rate is too slow to keep up with the high-frequency signals…\nMain text：\n Line 95 …to precisely control the junction capacitance under high frequency AC settings\n Line 174 …can be precisely controlled by the displacement…\n …. \nAnd more….\nIt is important that these qualitative terms be accompanied by specific numerical values.\nResponse #2.4:\nThank you for pointing out these non-technical or indefinite adjectives in our text. Revisions have\nbeen made as follows:\n(1) Line 48 …a precisely controlled DC bias…\nThe revised sentence in line 416-417 in section “Capacitive piezotronic measurements” in\n“Methods” is: “…a sweeping DC voltage with a step size of 6 mV was used to apply a bias on the\ndevices…”\n(2) Line 50 …high-resolution translation stage…\nThe revised sentence in line 418-419 in section “Capacitive piezotronic measurements” in\nMethods is: “…External forces were applied via a high-resolution (10 μm) translation stage…”\n(3) Line 145 …we can get the low-frequency (ω-low) and high-frequency 146 (ω-high) capacitance…\nHere, we would clarify that the “low-frequency” and “high-frequency” are the limit condition of\nformula (S-15) when frequency tends to zero (low-frequency limit) and infinity (high-frequency\nlimit), but not an inaccurate qualitative description. To clearly show that, we have made revision in\nline 126-128 in Supplementary Note 2.2: “…we can get the equivalent capacitance of dual Schottky\njunctions at low-frequency limit (C , ω tends to zero) and its equivalent capacitance at\nω-low\nhigh-frequency limit (C , ω tends to infinity)…”\nω-high\n(4) Line 242 …as the frequency increases, the excess capacitance response should be weakened\nbecause the carrier capture/release rate is too slow to keep up with the high-frequency signals…\nHere, we have estimated the time constant (τ ~800 ms) of the carrier capture/release process at\nthe deep-level traps in n-GaN, according to (Chattopadhyay, P. Solid-State Electron. 1993, 36, 605):\n1 𝑞𝜓𝑆\nwhere σ is the capture cross-section of 𝜏th=e\n𝑣\ni\nt\nn\nh\nt\n𝜎\ne\n𝑁\nrf\nD\naceex ps t(at\n𝑘\ne\n𝑇\ns,) ν\nt h\ni s t h e t h e r m a l v e l o c i t y o f t h e c(aRrr−ier2s),\nN is the carrier concentration, q is the elementary charge, ψ is the interface barrier height, k is the\nD S\nBoltzmann constant and T is the temperature.\nObviously, the dynamic behavior with a such large time constant around 800 ms could not keep\nup with the high-frequency (> 10 kHz) signals.\nWe have made revision to clarify this issue more clearly in line 320-323 in Supplementary Note\n6.1: “…as the frequency increases, the excess capacitance response should be weakened. This is\nbecause the time constant of the carrier capture/release process is too large (~ several hundred ms)\nto keep up with the high-frequency signals (> 10 kHz)…”\n(5) Line 95 …to precisely control the junction capacitance under high frequency AC settings\nWe would clarify that this sentence is a qualitative summarizing statement, but the word\n“precisely” is not quite accurate. We have deleted this inaccurate word in the third paragraph of the\nmain text, “…so as to control the junction capacitance under high frequency AC settings…” (line\n100-101), and a quantitative description is performed later in the same paragraph: “…It demonstrates\na high sensitivity (ΔC/p > 110 fF/mbar in single Schottky junction) in tuning the junction\ncapacitance…” (line 103-104)\n(6) Line 174 …can be precisely controlled by the displacement…\nSince the force-displacement relation is nonlinear, its sensitivity cannot be summarized as a\nconstant value. We have measured the force-displacement relation in Supplementary Figure 3 to\nprovide a further data support.\nWe have made a revision in line 224-226 in section “Interface width engineering in single\nSchottky junction via piezoelectric polarization”: “External loading forces were then applied to the\nSchottky junction along the polarization c-axis of piezoelectric n-GaN, which were controlled by the\ndisplacement of a translation stage (Supplementary Fig. 3)…”\n(7) And more….\n In the Figure 4 caption: “…The C-V characteristics of dual Schottky junctions based device\nunder 1 kHz (c) and 10 kHz (d) AC settings with forces applied to junction L…show the C-V\ncharacteristics of dual Schottky junctions based device under 1 kHz (f) and 10 kHz (g) AC\nsettings…” (line 493-496)\n In the Figure 3a caption: “…2 kHz V and DC bias are simultaneously applied on the\nAC\nelectrodes…” (line 476-477)\nQuestion #2.5\nError bars should be discussed for experimental results.\nResponse #2.5:\nThanks for the reviewer’s suggestion. We have performed additional repeated experiments, and\nadded the experimental data with error bars. Figure R4a-c and R5a-c show the measured C-V curves,\nand Figure R4d and R5d show the force-induced changes in capacitance under different bias of\nsingle and dual junction devices, respectively. These results show consistent results as our original\nmanuscript, further confirming the validation of the modulation effect and the underlying mechanism.\nRelated description and figures have been added to Supplementary Figure 30.\nFigure R4 | Repeat C-V measurements on single Schottky junction based device (a-c) and the\nforce-induced change of capacitance under different bias (d).\nFigure R5 | Repeat C-V measurements on dual Schottky junction based device (a-c) and the\nforce-induced change of capacitance under different bias (d).\nQuestion #3\nThe use of the specific words.\nResponse #3:\nThanks for the reviewer’s constructive comment. We have made comprehensive revisions in\nresponse to your subsequent Questions #3.1-3.2.\nQuestion #3.1\nQuite often the authors use the words, that in principle may mean what maybe they mean, but in\ncontext of the paper they are confusing:\n Line 114 “This dynamic hysteresis phenomenon is fundamentally equivalent to the capacitive\nreactance (X ) inherent in MS junction, resembling a charge-discharge process in a conventional\nC\ncapacitor.”\nPhenomenon (if consider dynamic hysteresis as a processes can be equivalent to the\nanother process – charging-discharging). But it cannot not be equivalent to the value, such as\ncapacitive reactance (X ).\nC\n Line 150 “…potential (V ) of the Schottky junction. It is noted that…” Who noted that?\nbi\n Line 177 “…The linear correlation of (1/C)2-V curve …” must be changed by: “The linear\n(1/C)2-V dependence…”\n Line 195 “…built-in electric potential, which is intuitively demonstrated by the experimental\nresults…”. What means “intuitively” in the context of experimental demonstration?\n Line 335 “…For the capacitive piezotronics, reactance (X) is applied to further describe the\neffect…”. How the measurable value (X) can be applied to describe?\nResponse #3.1:\nWe thank the reviewer for pointing out these confusing words. And, we have addressed each of them\nwith clearer explanations and revisions as follows:\n(1) Line 114 “This dynamic hysteresis phenomenon is fundamentally equivalent to the capacitive\nreactance (X ) inherent in MS junction, resembling a charge-discharge process in a conventional\nC\ncapacitor.” Phenomenon (if consider dynamic hysteresis as a processes can be equivalent to the\nanother process – charging-discharging). But it cannot not be equivalent to the value, such as\ncapacitive reactance (X ).\nC\nWe acknowledge that our description on the capacitive characteristics of MS junction is\nconfusing here and have provided a revision for clearer explanations in line 112-119 in section\n“Mechanism of the capacitive piezotronics”: “Figure 1b illustrates the main principle of the\ncapacitive piezotronics. The amount of charged donors or acceptors within the depletion region can\nbe modulated by an external voltage. Under AC settings, the applied alternating voltage (V ) results\nAC\nin the periodic migration of free carriers at the interface, thereby inducing a fluctuation in the\namount of charged atoms within in the depletion region. This dynamic behavior resembles a\ncharge-discharge process in a conventional capacitor. Notably, a charge-discharge process has a\ntypical time constant, finally resulting in a substantial phase shift. Thus, a Schottky junction\nmanifests a measurable capacitive characteristic under AC settings, and this capacitance is directly\ngoverned by the amount of charged atoms within the depletion region.”\n(2) Line 150 “…potential (V ) of the Schottky junction. It is noted that…” Who noted that?\nbi\nA proper reference to formula (2) has been added in line 191-192 in section “Theoretical\nsimulations of capacitive piezotronic effect”: “…It is noted that the interface width is proportional\nwith the square root of V at zero reverse bias (V = 0)2…” (Sze, S. M. et al. Physics of\nbi R\nSemiconductor Devices. John Wiley & Sons, 2021)\n(3) Line 177 “…The linear correlation of (1/C)2-V curve…” must be changed by: “The linear\n(1/C)2-V dependence…”\nWe thank the reviewer for pointing out our impropriate usage of “…The linear correlation of\n(1/C)2-V curve…” and we have revised it in line 220-221 in section “Interface width engineering in\nsingle Schottky junction via piezoelectric polarization”: “…The linear (1/C)2-V dependence at\nreverse bias also indicates the successful construction of the single Schottky junction…”\n(4) Line 195 “…built-in electric potential, which is intuitively demonstrated by the experimental\nresults…”. What means “intuitively” in the context of experimental demonstration?\nThank you for pointing that out and we agree that the word “intuitively” is not quite suitable for\ndemonstrating the variation in built-in electric potential. Here we have revised it in line 233-236 in\nsection “Interface width engineering in single Schottky junction via piezoelectric polarization” as\nfollows: “…Under loading force, the negative piezoelectric polarization charges generated at the\ninterface will repel electrons away from the interface and effectively enhance the built-in electric\npotential, which is demonstrated in Figure 3e…”.\n(5) Line 335 “…For the capacitive piezotronics, reactance (X) is applied to further describe the\neffect…”. How the measurable value (X) can be applied to describe?\nWe agree that the usage of measurable value (X) is not suitable here and have made revisions on\nit in line 160-162 in section “Relationship between capacitive piezotronics, resistive piezotronics and\ntraditional capacitive effect”: “…In contrast, the capacitive piezotronics actually aims at studying the\npiezotronic modification on semiconductor devices under AC conditions (ω > 0), where the\nreactance (X), particularly its capacitive component (C), becomes a critical parameter...”\nThe manuscript has been significantly improved by these revisions, and we are grateful for the\nreviewer’s suggestions and guidance for our work.\nQuestion #3.2\nQuite often the adverbs are used instead of adjectives:\n Line 85: “…Particularly, with widely use of…materials…”\nAnd more…\nResponse #3.2:\nWe sincerely thank the reviewer for their attention to the grammatical details of our manuscript.\nWe apologize for the improper use of adverbs in the original text and have revised them as follows:\n(1) Line 85: “…Particularly, with widely use of…materials…”\nRevision has been made in line 87 in the main text: “…Particularly, with the wide use of sub-10\nnm (even sub-5 nm) materials…”\n(2) Other revisions on the improper usage of adverbs, which is not referred by the reviewer:\n In line 259-261 in section “Capacitive piezotronics in dual Schottky junctions”: “…It can be\nseen that the two peaks at low-frequency are slightly different, resulting from the slight\ndifference of the two initially fabricated Schottky junctions…”\n In line 383-384 in section “Summary and outlook”: “…which enables mechanical tuning of\ncommunication systems including signal transmission and filtering…”\nWe are grateful for the reviewer’s guidance for our work.\nQuestion #4\nIt is also necessary to carefully review and correct the grammar throughout the manuscript.\nResponse #4:\nWe thank the reviewer for this valuable suggestion and apologize for the grammatical errors in our\noriginal text. To address this, we have checked the entire manuscript and supplementary materials.\n(1) Revisions on the use of punctuations:\nIn the abstract:\n “…and substantially improving the filtering characteristics particularly for high-frequency\nnoise…” (line 51-52)\n “…offering a distinctive approach for high-quality communication via mechanical stimuli.”\n(line 53-54)\nIn the main text:\n “…Particularly, with the wide use of sub-10 nm (even sub-5 nm) materials and development\nof device miniaturization in present-day technology…” (line 87-88)\n “…This work provides an in-depth understanding of the discovered capacitive piezotronics\ntowards next-generation AC electronics, demonstrating its huge potential in high-quality\ncommunication.” (line 107-109)\n “…and provides a new strategy for developing mechanical-stimulation-controlled devices in\nhigh-frequency communications. (line 144-145)\n(2) Revisions on use of verbs:\nIn the main text:\n “Interfaces of materials and heterostructures lie at the heart of the laws in condensed-matter\nphysics…” (line 60)\n “…Recently, interface engineering, that utilizes piezoelectric3-6, pyroelectric7,8, ferroelectric9,\nor flexoelectric10-12 effect to induce polarization in semiconductors, has inspired emerging\nfields…” (line 62-63)\n “…Highly sensitive capacitive piezotronics for junction capacitance tuning has been\nachieved, of which the sensitivity largely outperforms that of commercial capacitive pressure\nsensors…” (line 379-381)\n “…the capacitive piezotronics is widespread in noncentrosymmetric semiconductors\nincluding not only wurtzite structured ZnO and GaN, but also two-dimensional van der\nWaals materials (MoS , In Se etc.) and perovskite materials…” (line 385-387)\n2 2 3\nIn Supplementary Note 6.2:\n “…the investigation into strain-induced band modulation further provides a more\ncomprehensive understanding of capacitive piezotronics…” (line 342-343)\n(3) Revisions on tense consistency:\nIn the main text:\n “…which has also been the focus of interface engineering by polarization in recent years.”\n(line 76-77)\n “…According to formula (3), the enhancement in built-in electric potential further leads to\nan increase in the interface width, consequently reducing the junction capacitance...” (line\n236-237)\n(4) Revisions on prepositions and prepositional phrases:\nIn the abstract:\n “…More excitingly, the new effect possesses a capacity of mechanically tuning the\ntransmission signal in communication systems with a frequency shift > 11 kHz…” (line\n49-51)\nIn the main text:\n “…providing a possible scheme for advanced performance of alternating current (AC)\nelectronics/optoelectronics…” (line 86-87)\n(5) Revisions on the use of nouns:\nIn the main text:\n “…Manipulation of interfaces allows emergent effects and functionalities…” (line 61)\n “…which controls the processes of charge carrier separation, transport, relaxation or\nrecombination within the interface region…” (line 83-84)\n “…The equivalent circuit of frequency modulation is schematically shown in Figure 5b,\ncomprising a resonant circuit made of an inductor (L) and a capacitive piezotronic device\nwith dual Schottky junctions (serving as a tunable capacitor C′)…” (line 350-352)\n “…Thus, our findings open up a new avenue for mechanically tunable AC electronics in\nsemiconductors, which are promising for the new kinds of AC electronic devices and\nelectromechanical applications…” (line 388-390)\n(6) Revisions on the use of articles:\nIn the main text:\n “…and substantially increase the cutoff frequency of a filtering circuit…” (line 106-107)\n “…This work provides an in-depth understanding of the discovered capacitive piezotronics...”\n(line 107-108)\n “…a piezoelectric polarization field can be generated…” (line 127-128)\n “…Figure 3d shows the detailed modulation process in an n-GaN based single Schottky\njunction...” (line 233)\n(7) Revisions on other kinds of grammatical errors:\nIn the second paragraph of main text:\n “…especially those regarding communication applications such as high-frequency\ntransport37-39 and high-cutoff-frequency radio-frequency diode…” (line 80-81)\n “To verify the above theoretical simulations, we fabricated two-terminal devices consisting\nof a single Schottky junction and an Ohmic contact on a piezoelectric n-GaN single crystal\nwith low carrier concentration…” (line 210-212)\n “…Figure 3d shows the detailed modulation process in an n-GaN based single Schottky\njunction...” (line 233)\n “In practice, the presence of free carriers in piezoelectric semiconductor will generate an\nelectrostatic screening effect on the produced piezoelectric polarization…” (line 318-319)\nWe sincerely thank the reviewer for this constructive suggestion again.\nIn conclusion, I need additional evidence which support the result (see #1 and #2 in my report). It\nrequires better data presentation and more logic and accuracy in the text. The work demonstrates\nsignificant results and deserves publication after significant revision.\nResponse:\nWe gratefully thank the reviewer for the comments on our work as “significant results”. We have\nconducted a thorough and comprehensive revision to address the reviewer’s questions. We hope that\nour point-to-point responses, combined with the revised text, can provide strong evidence to support\nour results and can fully addressed all the reviewer’s concerns.\nReviewer #2 (Remarks to the Author):\nGeneral Assessment\nThe authors present a comprehensive investigation into how strain-induced polarization in\npiezoelectric semiconductors can be exploited as an interface engineering mechanism to modulate\nthe interface width and the junction capacitance under AC operation in Schottky-diodes structures.\nThe study combines finite element simulations and experimental measurements on single and dual\nGaN-based Schottky diodes to explore how controlled compressive strain affects the built-in\npotential, interface width, and capacitance, reporting strain sensitivities exceeding those of\ncommercial capacitive pressure sensors. Furthermore, the authors illustrate the potential of these\nmechanisms in practical applications by demonstrating implementations in communication circuits\nsuch as frequency modulators and filtering systems.\nThe manuscript provides a substantial amount of material supporting the main claims, including\nphysical descriptions, finite element simulations, and a broad set of experimental results. The\nmechanisms are interpreted with an appropriate level of detail, and the inclusion of practical\napplications and comparative analyses strengthens the overall study. Nevertheless, several aspects of\nthe work would benefit from clarification and refinement to further improve its rigor and readability\nbefore it can be considered for publication.\nResponse:\nWe sincerely thank the reviewer for acknowledging the importance of our work. And we also thank\nthe reviewer’s detailed and responsible reviewing of our work.\nGeneral Revisions\nIt should be noted that capacitance variation in piezoelectric and piezotronic devices under\nmechanical stress has been reported previously; for instance, in bulk ceramics (Cho et al., JJAP,\n1995 10.1143/JJAP.34.1591) and in ZnO-based Schottky structures (Zhang et al., Sensors 2021,\n21(6), 2253; https://doi.org/10.3390/s21062253). In this respect, the present manuscript goes beyond\nthose studies and offers a conceptual and practical advance.\nNevertheless, in light of the existing literature, the authors are encouraged to cite and briefly\ndiscuss these and others prior works, either in the Introduction or main text, and to compare their\nfindings and underlying mechanisms where appropriate. In addition, they are encouraged to balance\nsome novelty statements to ensure that the contribution is presented in a balanced and accurate way.\nSuch refinements would further enhance the credibility of the manuscript and draw clearer attention\nto its genuine advances.\nResponse to General Revision:\nThanks very much for the reviewer’s suggestions. We have carefully read the prior works mentioned\nby the reviewer. These works are related to our study, which propose capacitance modulation\nmethods with piezoelectric effect, but the mechanisms are different from capacitive piezotronics in\nthis work. We have cited these works and made a brief description in the revised manuscript.\nSpecifically, the definition of the capacitive piezotronic effect in our work is “Thus, the\nstrain-induced piezoelectric polarization can effectively modulate the interface width, so as to\ncontrol the junction capacitance under AC settings. (line 136-138 in the main text)\nNevertheless, the “capacitance variation in piezoelectric devices” (Cho, Y. et al. Jpn. J. Appl.\nPhys. 1995, 34, 1591) describes another different effect: the force-induced polarization in the\ntraditional piezoelectric device is utilized to induce bound charges on the piezoelectric layer, so as to\ncontrol its equivalent capacitance. This is actually a traditional piezoelectric device based on a\nmetal-insulator-metal (MIM) structure, while a typical capacitive piezotronic device mainly apply\nsemiconductor heterostructures, such MS junction, MIS junction and p-n junction. And for the work\nreported the “capacitance variation in piezotronic device” (Raoul, J. et al. Sensors 2021, 21, 2253),\nthe authors do have found a force-induced variation in C-V characteristics of Pt/ZnO/Pt dual\nSchottky junctions. However, this reported phenomenon was observed only under illumination, and\nremained many unsolved questions without explanations.\nHere, we would like to emphasize our breakthroughs compared to the prior works:\n(1) By introducing the core concept of interface width and emphasizing its importance, a significant\nprogress has been achieved in the theoretical model to explain the polarization-induced variation\nin junction capacitance; The theoretical model has been further refined in Schottky interface by\nestablishing a correlation between built-in potential and interface width;\n(2) Utilizing Finite Element Method, simulations on the distribution of electric potential and the\ncarrier transport have been achieved, clarifying the inner mechanism of the variation in interface\nwidth and junction capacitance under external force;\n(3) Systematic characterizations and detailed analysis in both single Schottky interface and dual\nSchottky interfaces have been carried out; the changes in built-in potential, interface barrier\nheight and width have all been calculated. Moreover, the universal nature has been proved by\nconducting same experiments on devices with different materials and structures;\n(4) Comparative experiments in materials with high carrier density and low carrier density have\nbeen conducted to further clarify the influence of piezoelectric polarization charges, excluding\nthe influence of piezoresistive effect, capacitive effect and so on, which have not been done in\nmost of the prior works.\n(5) The applications of this effect in frequency modulation and signal filtering have been presented,\ndemonstrating the potential of this effect in communication engineering;\nDespite of the discussion above, these prior works do make up some of the background of our\nworks, thus we have added the description about these works into the manuscript and supplementary\nmaterials, and also cited them in the references, as well as balanced some novelty statements:\n In the abstract: “…However, modulating the interface width and its resultant effects under AC\nsettings have not been deeply explored…” (line 40-41)\n In line 92-95 in the main text: “…Some preliminary attempts have been made to modulate the\ninterface width using external stimuli, such as mechanical or optical stimuli42. However, most of\nthese prior works have not provided systematic experiments and clear mechanism\nexplanations…” (Raoul, J. et al. Sensors 2021, 21, 2253)\n In line 95-97 in the main text: “…Thus, achieving dynamic manipulation of the interface width\nwithout changing the constructed device structure, and exploring the resultant effect are\nurgently needed, especially for AC electronics/optoelectronics.” Here we deleted the “…but it\nhas not been done.”\n A new Supplementary Note 7 has been added to compare the underlying mechanisms of these\nprior works and our work.\nWe sincerely thank the reviewer for this constructive suggestion and we hope that our revisions\nwill improve the quality of our work.\nAbstract Revision\nThe abstract does not clearly specify the type of investigation conducted, whether the reported results\nare theoretical/simulative or experimental, nor does it explain how the numerical values were\nobtained. The authors should explicitly state that the study combines finite element simulations and\nexperimental measurements, and that the reported numerical results refer to single and dual\nGaN-based Schottky devices. This clarification would provide a more accurate and transparent\nrepresentation of the work.\nResponse to Abstract Revision:\nThanks for the reviewer’s valuable suggestions. We are sorry that our descriptions are not clear in\nabstract and we have made the revision as follows (the type of investigation and the source of\nnumerical values have been explicitly clarified by the bold sentences):\n“Interface engineering by ionic polarization is vitally important in condensed-matter physics,\nderiving a plethora of distinctive phenomena, such as resistive piezotronics, pyroelectrics,\nferroelectrics, flexoelectronics and many more. Most of them focus on the polarization modulated\nbarrier height for effectively controlling carrier transport of DC electronics. However, modulating\nthe interface width and its resultant effects under AC settings have not been deeply explored. Here,\nwe report the capacitive piezotronics, which utilizes the strain-induced piezoelectric polarization to\nprecisely control the interface width of heterostructures and hence modulate the junction capacitance\nat a high frequency. It is a distinctive regulation mechanism that is widely present in piezoelectric\nsemiconductors (ZnO, GaN, etc.). Combining theoretical analysis and experiments, our results\nshow that the interface width can be reversibly tuned with amplitudes as high as 10.5 nm in single\nSchottky junction and 5.1 nm in dual Schottky junctions, respectively, which presents a high\nstrain sensitivity (ΔC/p > 110 fF/mbar in single Schottky junction) and surpasses that of\ncommercial capacitive pressure sensors (~0.1-0.7 fF/mbar). More excitingly, the new effect\npossesses a capacity of mechanically tuning the transmission signal in communication systems with\na frequency shift > 11 kHz, and substantially improving the filtering characteristics particularly for\nhigh-frequency noise. This study gives a brand-new strain-tuned AC electronics based on\npiezoelectric semiconductors, offering a distinctive approach for high-quality communication via\nmechanical stimuli.”\nThanks again for the reviewer’s suggestions and guidance for our work and we hope our\nresponse would address the reviewer’s question.\nManuscript Revisions\nQuestion #1\nIn the caption of Figure 1a, please specify that “P” denotes the polarization vector.\nResponse #1:\nThanks for the reviewer’s suggestion and we are sorry that our incomplete annotations hinder the\nreadability of our work. Here we directly replace the “P” by “polarization” in Figure 1a to avoid\nmisunderstanding, and attach the revised figure along with the following Response #2.\nQuestion #2\nIn Figure 1b (ii-1, ii-2, ii-3), both compressive and tensile strains are illustrated as acting along the\nsame direction of the c-axis. Since tensile and compressive strain correspond to opposite deformation\ndirections, leading to opposite polarization vectors, showing both with arrows in the same direction\nis misleading. The schematic should be revised to accurately depict strain directions relative to the\nc-axis and the corresponding polarization orientations.\nResponse #2:\nWe sincerely thank the reviewer for pointing out the inappropriate usage of the arrows in Figure 1\nand we are sorry about this unclear annotation. Revisions on Figure 1 are as follows:\nFig. 1 | Mechanism of the capacitive piezotronics.\nQuestion #3\nThe authors indicate the parameters used in the simulations, but should clarify which\ncrystallographic polarity (Ga-face or N-face) is considered and under what bias conditions the\nsimulations were performed.\nResponse #3:\nWe thank the reviewer’s suggestion. Our simulations were performed on Ga-polar (0001) n-GaN at\nzero bias. To further clarify these parameters in manuscript, we have made revisions as follows:\n In line 184-186 in section “Theoretical simulations of capacitive piezotronic effect”: “To\ndemonstrate the principle of the capacitive piezotronic effect, we performed Finite Element\nAnalysis (FEA) on a Schottky junction based on Ga-polar (0001) n-GaN at zero bias, where the\nintrinsic piezoelectric c-axis of n-GaN is oriented perpendicular to the interface (Method)…”\n In the section “Theoretical Calculations” in “Methods”:\n“The calculation on capacitive piezotronics was performed with the semiconductor module of\nCOMSOL program package through a 3D model of 200 nm wurtzite Ga-polar (0001) n-GaN...”\n(line 431-433)\n“…sweeps of strain were conducted at zero bias using stationary solver with a normal\nphysical-control mesh to demonstrate the potential distribution, conduction band energy and\ncarrier concentration distribution…” (line 441-443)\nQuestion #4\nIn addition to the schematics, an optical image of both the single and dual Schottky diodes should be\nprovided. The authors should also specify which capacitor area “S” is used in equation (3).\nResponse #4:\nThanks for the reviewer’s suggestions. Here we have provided the optical images of the single and\ndual Schottky junctions in Figure R1, and marked the capacitor area “S” in it. These optical images\nare all added into Supplementary Figure 2, and have been referred in the revised manuscript to\nfurther specify the capacitor area “S” in equation:\n In line 210-212 in section “Interface width engineering in single Schottky junction via\npiezoelectric polarization”: “…we fabricated two-terminal devices consisting of a single\nSchottky junction and an Ohmic contact on a piezoelectric n-GaN single crystal with low carrier\nconcentration (Supplementary Fig. 2)…”\n In line 246-248 in section “Capacitive piezotronics in dual Schottky junctions”: “…we further\ninvestigated the force-dependent C-V characteristics of dual Schottky junctions by fabricating a\ntwo-terminal device based on back-to-back Schottky junctions (Supplementary Fig. 2)…”\nFigure R1 | Capacitive piezotronic devices. a, The device based on dual Schottky junctions. b, The\ndevice based on single Schottky junction. c, The optical image of the Schottky contact (Pt/n-GaN).\nForce is applied on the circular area and the lead wires are connected to the strip area. The interface\narea S = 0.8296 mm2. d, The optical image of the Ohmic contact (Ti/Al/Ni/Au/n-GaN).\nQuestion #5\nSince the junction capacitance is analyzed across various bias ranges, including an I–V curve of the\nSchottky diode under strain-free conditions would provide a more complete picture of the device\nbehavior.\nResponse #5:\nWe thank the reviewer for this insightful suggestion. Here, I-V characteristics of the devices under\nstrain-free condition has been provided in Figure R2.\nThe I-V characteristic in Figure R2a is based on the device with single Schottky junction\nfabricated on low-carrier-concentration GaN. It fits well with the current expression in thermionic\nemission theory:\n∗ 2 −𝑞𝜑 𝑞𝑉\nwhere the J is the current pa𝐽ss=ing[𝐴 th𝑇roeuxgph (the s)in]g[elex pS(chot)tk−y 1j]u,n c t i o n , A * i s t h e e (fRfec−ti1ve)\n𝑘𝑇 𝑘𝑇\nRichardson constant, T is the temperature, q is the elementary charge, φ is the interface barrier height,\nk is the Boltzmann constant and V is the bias applied to the single Schottky junction. The interface\nbarrier height is ~0.66 eV obtained by curve fitting.\nThe I-V characteristics in Figure R2b, c are based on the devices with dual Schottky junctions\nfabricated on low-carrier-concentration GaN and high-carrier-concentration GaN, respectively. Both\nof them exhibit approximately symmetrical I-V characteristics, indicating the symmetry in device\nstructure. Besides, the current measured in GaN with high carrier concentration is much higher than\nthat measured in GaN with low carrier concentration, which is owing to the enhanced conductivity in\nhigh-carrier-concentration materials.\nIn revisions, we have added the I-V characteristics into Supplementary Figure 2. We hope that\nthese results can strengthen the support for our claims and thank the reviewer for prompting this\ninvestigation.\nFigure R2 | I-V characteristics of the devices under strain-free condition. a, The I-V\ncharacteristic of single Schottky junction fabricated on low-carrier-concentration GaN. The\nexperimental results fit well with the theoretical results in thermionic emission theory and the\nobtained interface barrier height is ~0.66 eV. b, The I-V characteristic of dual Schottky junctions\nfabricated on low-carrier-concentration GaN. c, The I-V characteristic of dual Schottky junctions\nfabricated on high-carrier-concentration GaN.\nQuestion #6\nThe C-V measurements of the single Schottky diode under compressive strain are reported without\nindicating the frequency of the AC signal. The authors should specify the frequency used, justify\ntheir choice, and clarify whether the capacitance variation depends on frequency, as was done for the\ndual-Schottky configuration. This might be useful to better understand the dual-Schottky junction\ncase.\nResponse #6:\nWe thank the reviewer for this valuable and significant suggestion. In Figure 3b, a 2 kHz AC signal\nwas applied during C-V measurements of the single Schottky diode under compressive strain. The\nmeasured capacitance of a single Schottky junction is theoretically independent on frequency, and\nsimilar method with frequencies ranging from 1 kHz to 10 kHz has also been adopted in many other\nliteratures (Table R1), which further prove the rationality of our test conditions. Thus, we believe\nthat 2 kHz is a valid choice for our experiments. The reason why the capacitance is independent on\nfrequency is derived as follows:\nAs shown in Figure R3, a single Schottky junction is described as a combination of junction\ncapacitance (C), junction resistance (R) and series resistance (R ). The corresponding impedance\nj j S\n(Z ) is:\nsingle\n𝑅j\n𝑍single = +𝑅S, (R−2)\nwhere ω is the angular frequency of AC signal, a\n1\nn\n+\nd i\n𝑖 𝜔\nis\n𝐶\ntjh\n𝑅\ne jimaginary unit. In our experiments, the\nfrequency of AC signal is 2 kHz, and the single junction capacitance ranges approximately from 0.3\nnF to 5 nF. Note that the junction resistance exhibits a strong dependence on the applied bias:\ngenerally, in the ~MΩ order under reverse bias while in the ~Ω order under forward bias (Korkut, H.\nNano-Micro Lett. 2013, 5, 34; Anderson, W. A. et al. Proc. IEEE 1975, 63, 206; Cohen, L. D. Proc.\nIEEE 1971, 59, 288). The influence of junction resistance cannot be neglected since (R) ≈ 1/ωC\nj max j.\nHowever, the influence of series resistance (generally in the ~Ω order) can be overlooked under\nreverse bias due to the fact that it is much smaller than the junction resistance at this bias. Thus, the\nsingle Schottky junction under reverse bias can be regarded as a single parallel connection of a\nresistor R and a capacitor C. The simplified impedance (Z ) is:\nj j re\n𝑅j\n𝑍re = , (R−3)\nHowever, the influence of series resistance must b\n1\ne\n+\nta\n𝑖\nk\n𝜔\nen\n𝐶\nji n\n𝑅\ntjo account under forward bias, and thus\nthe equivalent circuit of a single Schottky junction under forward bias still maintains a complex\nstructure. The corresponding impedance (Z ) is:\nfor\n𝑅j\n𝑍for = +𝑅S. (R−4)\nNote that the equivalent parallel circuit mo\n1\nd\n+\nel,\n𝑖 𝜔\nw h\n𝐶\nijc\\𝑅\nhj regards the entire circuit as a parallel\nconnection of a capacitor (C ) and a resistor (R ), is applied in our measurements. The\nparallel parallel\nmeasured equivalent capacitance (C ) of a single Schottky junction thus satisfies:\nparallel\n1 1\n= 𝑖𝜔𝐶parallel−re + (R−5)\n𝑍re 𝑅parallel-re\n1 1\n𝑜𝑟 = 𝑖𝜔𝐶parallel−for + . (R−6)\nTherefore, according to formula (R-\n𝑍\n3f)o rand (R-5), the equiv\n𝑅\nalpeanratl lecl-afporacitance of a single Schottky\njunction under reverse bias measured by equivalent parallel circuit model is:\nand according to formula (R-4) and (R-6), the e\n𝐶\nqpuariavllaell-erent\n=\nca\n𝐶\npj, a c i t a n c e o f a s i n g l e S c h o t t k y j\n(\nu\nR\nc\n−\ntio\n7\nn\n)\nunder forward bias measured by equivalent parallel circuit model is:\n2\n𝐶j𝑅𝑗\n𝐶parallel-for = 2 2 2 2 2. (R−8)\nObviously, the measured capacitance under reve\n(\nr\n𝑅\nsej\n+\nbi\n𝑅\naSs\n)\nvi\n+\na\nω\nequ\n𝐶\nijv\n𝑅\nalje\n𝑅\nnSt parallel circuit model is\nexactly the single Schottky junction capacitance, showing independence on frequency, junction\nresistance and series resistance. Results measured under such conditions are quite suitable for\nstudying the influence of capacitive piezotronic effect on interface width and junction capacitance.\nTherefore, discussion and analysis in our Figure 3 are all based on the data measured under reverse\nbias via equivalent parallel circuit model.\nFurthermore, the above derivation can also be extended to the case of dual Schottky junctions\nand the corresponding equivalent capacitance has been shown as formula (S-15) in Supplementary\nNote 2.2, clearly showing dependence on frequency. Therefore, it is necessary to investigate the C-V\ncharacteristics of dual Schottky junction under different AC frequencies, as in Figure 4. The detailed\nderivation of equivalent capacitance of both single Schottky junction and dual Schottky junctions\nhave been added in Supplementary Note 2.\nIn summary, the frequency selection theoretically has no impact on the measured capacitance of\nthe single Schottky junction shown in Figure 3b. To further clarify the test conditions, we have made\nthe revision in the section “Capacitive piezotronic measurements” in “Methods”: “…The equivalent\nparallel circuit model (C ) was adopted to obtain the capacitance of these devices…”\np\nFigure R3 | Equivalent circuit of a single Schottky junction. a, Schematic illustration of a single\nSchottky junction. b, Equivalent circuit of a single Schottky junction under forward bias. c,\nEquivalent circuit of a single Schottky junction under reverse bias.\nTable R1 | Frequency settings for Schottky junction capacitance measurements\nReferences Devices Frequency\nNat. Energy 8, 504-514 (2023) CdTe/V-In S 4 kHz\n2 3\nEnergy Environ. Sci. 16, 4620 (2023) Pt/p-Si 10 kHz\nNat. Energy 6, 63-71 (2021) FTO/3D(SIG-2D)/spiro-OMeTAD/Au 10 kHz\nNat. Commun. 16, 8523 (2025) GDYO/Pt 1-1.732 kHz\nAdv. Energy Mater. 9, 1803243 (2019) Cs SnI /electrolyte 1 kHz\n2 6\n3D Perovskite\nEnergy Environ. Sci. 17, 6234 (2024) 3D Perovskite/SIG-I 10 kHz\n3D Perovskite/SIG-Br\nQuestion #7\nSupplementary Figure 3 should be corrected, as it currently shows the same strain direction for both\ncompressive and tensile loading.\nResponse #7:\nThank the reviewer for the suggestion. We are sorry for the annotation mistake in the origin\nSupplementary Figure 3 (Supplementary Figure 16 after revision) and have revised the figure in\nsupplementary materials.\nSupplementary Figure 3 (Supplementary Figure 16 after revision) | Modulation mechanism of\npiezoelectric polarization on the built-in potential of Schottky junction at compressive strain\n(a), strain free (b) and tensile strain (c) conditions.\nQuestion #8\nIn the section “Capacitive piezotronics in dual Schottky junctions”, the authors should specify on\nwhich junction the bias is applied and explain why they expect that loading one junction does not\naffect the interface width of the other (line 210-212). They should add a reference to this sentence.\nResponse #8:\nThanks for the reviewer’s constructive suggestions.\n(1) Which junction the bias is applied?\nWe would like to clarify that, during the C-V characterizations of dual Schottky junctions, the\nDC voltage aims at applying bias between junction L and R rather than separately to one of the\njunctions. Owing to the symmetric structure of this device, the applied voltage between the two\njunctions leads to the different bias conditions on each junction. For example, under a negative\nvoltage, junction L is reversed-biased while junction R is forward-biased. For clarity, revisions have\nbeen added in line 248-252 in section “Capacitive piezotronics in dual Schottky junctions”: “…The\nelectrical measurement system in this experiment utilizes a DC voltage to apply bias between\njunction L and R, which is respectively reverse-biased (L) and forward-biased (R) at negative\nDC voltage, while overturned at positive DC voltage, and simultaneously utilizes a V signal to\nAC\nconduct capacitance measurements under such bias conditions…”\n(2) Why they expect that loading one junction does not affect the interface width of the other (line\n210-212).\nWe are sorry for the misunderstanding. This misread is because our previous expression “…has\nno influence on the other junction…” was ambiguous. Our real meaning is that the external force and\nthe piezoelectric polarization is spatially localized only in the stressed junction (but of course, the\nunstressed junction is also influenced due to voltage division). This conclusion is further confirmed\nby a finite element simulation (Figure R4). And, it has been also reflected in literatures which use\npiezotronic effect to realize pressure imaging (Liu, S. et al. Adv. Mater., 2019, 31, 1905436). We\nhave revised this sentence in line 253-254 in section “Capacitive piezotronics in dual Schottky\njunctions”: “…The piezotronic polarization is spatially confined to the stressed junction…”\nWe hope that this revision has resolved the ambiguities, and we thank the reviewer’s help in\nimproving the quality of our work.\nFigure R4 | Analysis of the deformation of two-terminal devices under loading force. a,\nDeformation of the two-terminal device with 2 MPa pressure applied on one of the junctions. The\ndeformed area is concentrated within a range of ~1 mm near the stressed junction. b, The\ndeformation distribution along x-axis (y = 5 mm) at the top surface of GaN. Area near the unstressed\njunction (x ranges from 7 to 8 mm) has almost no change. c, The deformation distribution along\ny-axis (x = 2.5 mm) at the top surface of GaN.\nQuestion #9\nTo improve readability, the color scheme of Figure 4b should differ from the subsequent figures. In\nreference to the sentence at line 217 the authors could also specify the parameters (junction area,..) that make the two Schottky junctions\ndifferent and explain how these differences lead to asymmetric C–V peaks. The two Schottky barriers, indeed, are\nconsidered symmetrical over the manuscript. Additionally, there appears to be an inconsistency: in Figure 4b the left peak is\nhigher than the right one, while the opposite occurs in subsequent figures.\nResponse #9:\nThank the reviewer for the suggestions. We have changed the color scheme in Figure 4b to\ndistinguish it clearly from subsequent figures (Figure. 4c–h). The revised Figure 4 has been\nprovided in the following Response #10.\nActually, the two Schottky junctions are designed to be symmetric in geometry with the same\nmaterials (Pt/n-GaN), same junction areas (as illustrated in Response #4), same preparation\nprocesses, etc.. However, due to the limitation of preparation processes, the GaN layer in our device\nis not perfectly uniform, and the MS contacts are not ideally symmetric.\nThe asymmetric C–V peaks observed without loading force could be attributed to the relative\nhigher initial doping concentration near the junction R. A higher doping concentration leads to a\nnarrower interface width and thus a higher capacitance. This hypothesis is further confirmed by the\ndifference in the modulation performance with each junction stressed, which is further discussed in\nResponse #12. And we have carefully checked our original data of Figure 4b. We found that we\nhave made a mistake that the x-axis was labeled into the opposite direction. We have made revision\nin the manuscript, and we sincerely thank again for the reviewer’s careful observation, and apologize\nfor the confusion caused by the mistake.\nQuestion #10\nFigures 4c and 4f are not self-explanatory. It is unclear which curve corresponds to the strain-free\ncase. The referee suggests replacing them with Supplementary Figures 8a and 8c, which are clearer.\nThe authors should also indicate, at least in the caption, the low and high frequencies used for the\nstrain-dependent measurements. Moreover, the rightward shift of the C–V curve under strain is\nevident near the valley point; the arrows should be repositioned accordingly.\nResponse #10:\nThanks for the reviewer’s suggestion for improving the presentation of our work. We have made\nrevisions in Figure 4c, f referring to the style of the original Supplementary Figure 8a, c\n(Supplementary Figure 21 after revision). And, the arrow has been moved to the valley point to\npresent the evident shift of C-V curve, making the curves under different pressure conditions easier\nto distinguish. The revised Figure 4 has been provided at the end of this response.\nThe low and high frequencies of AC signals used in measuring C-V curves of dual Schottky\njunctions are 1 kHz and 10 kHz, respectively. Revisions have been made in the caption of Figure 4:\n “…The C-V characteristics of dual Schottky junctions based device under 1 kHz (c) and 10 kHz\n(d) AC settings with forces applied to junction L...” (line 493-494)\n “…Respectively, f, g show the C-V characteristics of dual Schottky junctions based device under\n1 kHz (f) and 10 kHz (g) AC settings, with forces applied to junction R...” (line 495-496)\nWe sincerely thank the reviewer again for prompting these important advices, which has\nsignificantly improved our work.\nFig. 4 | Capacitive piezotronics in dual Schottky junctions. a, Schematics of dual Schottky\njunctions and mechanism of piezoelectric polarization to modify the interface width in dual Schottky\njunctions. W represents the initial interface width without force (68 nm at zero bias) and ΔW\n0\nrepresents the change of interface width under loading force. b, Dispersive behavior of C-V\ncharacteristics in dual Schottky junctions. The inset presents the equivalent circuit of the dual\nSchottky junctions. c, d, The C-V characteristics of dual Schottky junctions based device under 1\nkHz (c) and 10 kHz (d) AC settings with forces applied to junction L. e, The variation of interface\nwidth versus pressure corresponding to (c). Respectively, f, g show the C-V characteristics of dual\nSchottky junctions based device under 1 kHz (f) and 10 kHz (g) AC settings, with forces applied to\njunction R. h, The variation of interface width versus pressure corresponding to (f).\nQuestion #11\nFigure 4c shows that at low bias the C–V curve valley shifts to the right when the left junction is\nunder strain. What do they associate with the leftward shift observed at higher bias?\nResponse #11:\nWe are grateful for the reviewer’s attention to the curve shift, which is actually a core phenomenon\nand key evidence for the capacitive piezotronics. In Figure 4c, the whole C–V curve indeed shifts to\nthe right at low bias. The “leftward shift” of the C-V curve at higher bias is in fact a visual illusion\ninduced by the variation of the peak values, that the left peak value increases and the right peak value\ndecreases. In fact, the curve at higher bias do not shift to left. A detailed explanation for the variation\nin value peak has been provided in Response #13-14. We hope our response can address your\nquestion.\nQuestion #12\nJust for clarity, the authors could specify why a smaller capacitance variation is observed when the\nright junction is loaded at low frequency, in Figure 4f.\nResponse #12:\nThank the reviewer for this suggestion. The smaller capacitance variation observed when the right\njunction is loaded could be attributed to the higher initial doping concentration near the right junction,\nwhich is an intrinsic problem in the GaN we purchased.\nAs shown in Figure 4, the right peak (dominated by the junction R) is initially a little higher\nthan the left peak in the C-V curves without loading force. This phenomenon indicates a higher\ndoping carrier concentration near the junction R. Note that the interface widths of junction L (W )\n1\nand junction R (W ) at zero bias are:\n2\n2𝜀S𝑉bi1\n𝑊1 = √ , (R−9)\n𝑞𝑁1\n2𝜀S𝑉bi2\n𝑊2 = √ , (R−10)\nwhere ε is the dielectric constant of the semiconduc𝑞to𝑁r2, V and V are the built-in electric potential\nS bi1 bi2\nof junction L and junction R, respectively, N and N are the doping concentration of junction L and\n1 2\nR, respectively. Since N > N , the polarization-induced interface width increment in junction R\n2 1\nwould be smaller under the same loading force. This leads to a smaller capacitance variation when\nthe right junction is loaded at low frequency.\nWe have added this explanation in line 275-276 in section “Capacitive piezotronics in dual\nSchottky junctions”: “…The smaller variation in the interface width with force on junction R could\nbe attributed to the higher initial doping concentration near junction R…”\nQuestion #13\nSupplementary Figure 9 does not seem consistent with the description provided in the manuscript.\nWhy is the barrier height of the left junction in reverse mode and under strain (i) lower than in the\nstrain-free condition? Why is the depletion width in that case smaller than in the strain-free\nconfiguration? When the strain is applied to the right junction, why is the left-junction barrier height\nhigher than in the other two cases?\nOne would expect the strained junction in reverse mode to exhibit a higher barrier and wider\ndepletion region. If these plots represent a different potential distribution rather than local barrier\nheights, the authors should clarify this explicitly. In that case, the statement around lines 210–212\nregarding the independence of each junction under strain may need reconsideration.\nResponse #13:\nThanks for the reviewer’s insightful comment. We are sorry that our explanations are not clear\nenough. The original Supplementary Figure 9 (Supplementary Figure 5 after revision) shows the\ninterface widths of the dual junctions at the peak position, while the peak position does not remain\nsteadily but shifts under external force. Thus, the core mechanism for these questions is actually the\nsame: the interface width is not only modulated by the piezoelectric polarization charges, but also the\nexternal bias where the peak occurs. We have revised the description and made revisions in the\nmanuscript.\n(1) Why is the barrier height of the left junction in reverse mode and under strain (i) lower than in\nthe strain-free condition? Why is the depletion width in that case smaller than in the strain-free\nconfiguration?\nHere the interface barrier height and width are actually coupled and have the same variation\nbehavior, thus we take the interface width as an example for the following explanation:\nFor junction L, its interface width is modulated by both of the piezoelectric polarization charges\nand the external bias: a higher negative bias would increase its interface width, while a lower\nnegative bias would decrease it. Notably, the C-V curve would shift towards positive bias when the\njunction L is stressed, thus the peak in the negative bias region shifts closer to zero bias. As a result,\nat this peak position, the lower negative bias decreases the interface width of junction L as well as its\ninterface barrier height, compensating for the increase induced by the polarization charges.\nRevisions have been made in the section “Capacitive piezotronics in dual Schottky junctions”:\n“…An abnormal phenomenon is observed that this peak capacitance increases rather than deceases\nas the junction L is stressed, which can be attributed to two mechanisms. On the one hand, although\nthe negative polarization charges increase the interface width of the stressed junction, the peak\nmoves to a lower bias owing to the shift of C-V curve, and the lower bias will simultaneously\ndecrease the interface width and hence compensate for the capacitance reduction…” (line 293-297)\nActually, the real interface barrier height was not shown in Supplementary Figure 9. We are\nsorry for the misunderstanding, and we have revised it in the revised Supplementary information\n(Supplementary Figure 5 after revision) to avoid possible misunderstanding.\n(2) When the strain is applied to the right junction, why is the left-junction barrier height higher\nthan in the other two cases?\nAs mentioned above, the interface barrier height is not shown in Supplementary Figure 9\n(Supplementary Figure 5 after revision), but have the same variation behavior as the interface\nwidth. Thus, we will also use the interface width for the following explanation:\nThe interface width is influenced by both the polarization charges and the external bias. Because\nthe piezoelectric polarization is localized at the stressed junction R and the distance between the two\njunctions is far enough, there are actually no polarization charges distributing near the unstressed\njunction L (Response #8 and Figure R4). Thus, for the unstressed junction L, the only factor\nmodulating its interface properties is the external bias. Based on the mechanism mentioned above, as\njunction R is stressed, the peak at negative bias region shifts away from zero bias. Thus, the higher\nnegative bias increases the interface width and barrier height of junction L.\n(3) If these plots represent a different potential distribution rather than local barrier heights, the\nauthors should clarify this explicitly.\nAs we discussed just above, our original Supplementary Figure 9 (Supplementary Figure 5\nafter revision) actually shows the interface width rather than interface height at the peak position.\nWe are sorry for our unclear description. We have revised the original Supplementary Figure 9a\n(Supplementary Figure 5a after revision) and renamed the title of the figure as: “Interface width of\ndual Schottky junctions at peak position”.\n(4) In that case, the statement around lines 210–212 regarding the independence of each junction\nunder strain may need reconsideration.\nWe are sorry that the previous expression “…has no influence on the other junction…” was\nambiguous, and we have made revision in section “Capacitive piezotronics in dual Schottky\njunctions”: “…The piezotronic polarization is spatially confined to the stressed junction…” (line\n253-254)\nWe hope that our response will address your question and improve the readability of our work.\nQuestion #14\nThe explanation of the asymmetric strain-induced modulation of the C–V peaks needs clarification.\nOne would expect the strained junction in reverse bias to show lower capacitance than the strain-free\ncase, since its depletion region widens. However, the observed peak shows higher capacitance. While\nthe shift of the peak to lower negative biases the authors refer to in line 245-248 compensates for the\nwidened barrier, it does not fully explain the higher capacitance compared to the strain-free situation.\nA more explicit discussion of the interaction between the two junctions might be needed to explain\nwhy the capacitance increases despite the widened barrier.\nResponse #14:\nThanks for the reviewer’s insightful comment. We sincerely apologize for our unclear explanations\nfor the rising of C-V peak value in the low frequency occasions. Here, the main factors that resulting\nin the rising of C-V peak are the variation in the external bias and the effective charge concentration.\nWe have provided a clearer description and an explicit numerical simulation to confirm our\nmechanism.\n(1) The effect of the external bias\nThe peak with an increased capacitance is dominated by the stressed junction. As we stated in\nResponse #13, the interface width of the stressed junction is modulated by both of the piezoelectric\npolarization charges and the external bias. Although the negative polarization charges increase its\ninterface width, the shift of C-V curve moves the peak to a lower bias region and the lower bias\nsimultaneously decreases the interface width, thereby making a compensation for the reduced\ncapacitance.\nWe have revised the third paragraph of section “Capacitive piezotronics in dual Schottky\njunctions”: “…Note that the peak capacitance of C-V curve in low-frequency is primarily dominated\nby the interface width of the reverse-biased junction (junction L in the negative voltage region and\njunction R in the positive region). Thus, the peak shifting closer to zero bias is dominated by junction\nL. An abnormal phenomenon is observed that this peak capacitance increases rather than deceases\nas the junction L is stressed, which can be attributed to two mechanisms. On the one hand,\nalthough the negative polarization charges increase the interface width of the stressed junction,\nthe peak moves to a lower bias owing to the shift of C-V curve, and the lower bias will\nsimultaneously decrease the interface width and hence compensate for the capacitance reduction.\nOn the other hand, the changed effective carrier concentration near the interface also makes a\ncontribution to the increasing capacitance (Supplementary Note 4). For the other peak of C-V curve in\nthe positive bias, the interface width of the unstressed junction R becomes the dominant factor.\nSince the piezotronic polarization is spatially confined to the stressed junction L, the interface width\nof the junction R is only influenced by the external bias. As this peak shifts to a higher bias region,\nthe increased bias expands its interface width, and thus decreases the peak capacitance. Conversely,\nwhen the force is applied to junction R, the peak value in the negative bias decreases while the other peak\nvalue increases (Fig. 4f). This is a unique asymmetric capacitance modulation induced by the\ncapacitive piezotronic effect…” (line 290-306)\n(2) The effect of the effective charge concentration\nBeginning with an ideal model (zeroth-order approximation), we supposed that the change in\nbuilt-in electric potential (V ) and interface width (W) perfectly follows a steady relationship:\nbi\n2𝜀S𝑉bi\n𝑊 = √ , (R−11)\nwhere V is the built-in electric potential and N is 𝑞th𝑁ed doping concentration. This relation is derived\nbi d\nfrom the 1D Poisson’s equation:\n2\nd 𝜓(𝑥) 1\nwhere ψ(x) is the electric potential distribu\nd\nti\n𝑥\no2n a=lo\n𝜀\nnSg[ 𝑞t𝑁he d ] x - a x i s , a s s h o w n i n F i g u r e R 5 a . (NRo−tab1l2y),\nthe validation of formula (R-11) requires that the curvature of ψ(x) does not change, so that the\nchange in built-in electric potential and interface width could be perfectly “matched” under an\nexternal stress. To meet this requirement, we actually set a hypothesis that the piezoelectric charges\ndistribute normally in a very thin layer and have little influence on the potential curvature. This\nhypothesis is valid as we explain the single junction model, but not enough in the dual junction\nmodel.\nThe reality is that, as the force increases, the piezoelectric polarization charges change the\ndistribution of free carriers and donors (first order approximation), simultaneously influences the\neffective charge concentration (N ):\neff\n2\nd 𝜓(𝑥) 𝑞 𝑞\nwhere ΔN is the variation in the concentr\nd\na\n𝑥\nti2on.= In\n𝜀\nSt[h𝑁is D +waΔy𝑁, ]th=e\n𝜀\ncSu𝑁r e v ff a t u r e o f ψ ( x ) i n c r e a s e s( Ran−d 1th3e)\nband bending becomes much steeper. Consequently, the depletion region essentially “narrows” to\naccommodate the sharp potential drop, even though the total barrier is larger (Figure R5a). This\n“narrowed” depletion regions results in the “mismatch” between built-in electric potential and\ninterface width, leading to a narrower interface width under same conditions.\nBased on this mechanism, we have induced this “mismatch” between built-in electric potential\nand interface width into our simulations (Figure R5b). Results show that the peak shifting closer to\nzero bias shows an increment, and the other peak shows a reduction, which is consistent with our\nexperiments. This mechanism further explains why the capacitance increases despite the widened\nbarrier.\nWe have added this analysis in Supplementary Note 4.3 and referred it in line 297-299 in\n“Capacitive piezotronics in dual Schottky junctions”: “…On the other hand, the changed effective\ncarrier concentration near the interface also makes a contribution to the increasing capacitance\n(Supplementary Note 4)…”. And, we hope that our revised explanations and the added\nsupplementary materials have made our description clearer.\nFigure R5 | Correction on the theoretical model of dual Schottky junctions. a, Under strain free\ncondition, the interface width has a positive relation with built-in electric potential at zero bias (i). As\nthe force increases, zeroth order correction, that the built-in electric potential is enhanced, is applied\nto represent the influence of polarization charges (i). The first order correction, that the effective\ncarrier concentration is also changed, is applied to further explain the increase of the peak value in\nlow-frequency C-V curves (ii). b, The simulated low-frequency C-V curves of dual Schottky\njunctions under situations of strain free (dashed line), zeroth correction (blue line) and first\ncorrection (red line).\nQuestion #15\nIn Supplementary Note 4, the role of R in the theoretical model should be clarified.\nS\nResponse #15:\nThanks for the reviewer’s comment. In fact, the series resistance is regarded as zero in the derivation\nsince its value is too small compared to junction resistance (R) at reverse bias:\nj\nAs is demonstrated in Response #6, a single Schottky junction is described as a combination of\njunction resistance (R), junction capacitance (C) and series resistance (R ). Note that junction\nj j s\nresistance is in the ~MΩ order under reverse bias. On the contrary, the series resistance is generally\nin the ~Ω order (Korkut, H. Nano-Micro Lett. 2013, 5, 34; Anderson, W. A. et al. Proc. IEEE 1975,\n63, 206; Cohen, L. D. Proc. IEEE 1971, 59, 288), and hence can be overlooked under reverse bias\nbecause it is much smaller. Since our investigation on single Schottky junction are carried out under\nreverse bias, the influence of series resistance can be neglected in our experiments.\nTo further prove this, we have provided Figure R6, which compares the equivalent capacitances\nof single Schottky junction with (C ) and without (C ) the influence of series resistance.\noriginal simplified\nThe used parameters are basically consistent with those applied in our experiments. Results show\nthat the two equivalent capacitances tend to be consistent when the junction resistance is much larger\nthan the series resistance. Thus, the neglect of series resistance under this condition is reasonable in\nour experiments.\nAdditionally, dual Schottky junctions is composed of two single Schottky junctions (L and R),\nwhich are connected in series. Here, the series resistance in the circuit is also overlooked (R = 0 Ω),\ns\nsince dual Schottky junctions always exhibits a much higher junction resistance than series resistance\nwhether under forward or reverse bias. On this basis, the impedance and equivalent capacitance of\ndual Schottky junctions are independent on series resistance.\nWe have added these detailed descriptions on the role of R in line 58-62 in Supplementary\ns\nNote 2.1: “…Note that the junction resistance exhibits a strong dependence on the applied bias:\ngenerally, in the ~MΩ order under reverse bias while in the ~Ω order under forward bias3-5. The\ninfluence of junction resistance cannot be neglected since (R) ≈ 1/ωC\nj max j.\nHowever, the influence of\nseries resistance (generally in the ~Ω order3-5) can be overlooked under reverse bias because it is\nmuch smaller than the junction resistance…”\nFigure R6 | Comparation on equivalent capacitances of single Schottky junction with (C )\noriginal\nand without (C ) the influence of series resistance. The two equivalent capacitances tend to\nsimplified\nbe consistent when the junction resistance is much larger than series resistance. So, the series\nresistance can be neglected under this condition. The parameters used in simulations are basically\nconsistent with those applied in our experiments.\nQuestion #16\nIn Supplementary Note 5, the derivation of Equation (17) is not clear and a reference should be\nadded.\nResponse #16:\nThanks for the reviewer’s comment. We have added the full derivation of the Equation (17) in the\noriginal supplementary materials (formula (S-37) after revision) (Van Opdorp, C. et al. Solid-State\nElectron. 1967, 10, 401).\nIn an ideal symmetric structure of dual Schottky junctions, the interface widths of junction L\n(W ) and R (W ) at zero bias satisfy:\n1 2\n2𝜀S𝑉bi1\n𝑊1 = √ , (R−14)\n𝑞𝑁d\n2𝜀S𝑉bi2\n𝑊2 = √ , (R−15)\nSuppose the junction L is stressed and the junctio𝑞n 𝑁Rd is unstressed, the piezoelectric polarization\ncharges will increase the built-in potential of junction L and thus V > V . Under this condition, the\nbi1 bi2\nlow-frequency C-V curve of dual Schottky junctions will exhibit a shift in valley, which occurs only\nwhen the interface barrier heights of the dual Schottky junctions are equal. The bias where the valley\noccurs (V ) thus satisfies:\nvalley\n𝜑1 −𝜑2\nwhere φ and φ are the interface 𝑉b v a a r ll r e i y er= heights of =th e𝑉 b S i c 1 h−ott𝑉k b y i2 j,unctions L and R. Under( tRhi−s b1i6a)s\n1 2 𝑞\ncondition, the voltage drops over junction L (V ) and R (V ) are equal:\n1-valley 2-valley\n𝑉2−valley 𝑅2−valley φ2 −φ1 𝑞𝑉valley\n= = exp( )exp( ) = 1, (R−17)\n𝑉1−valley 𝑅1−valley 𝑘𝑇 𝑘𝑇\n𝑉valley 𝑉bi1 −𝑉bi2\nwhere R and R 𝑉a1re− vtahlele yju=nc𝑉ti2o−nv arellseiyst=ances of =the Schottky ,j u n c t i o n s L a n d R a t t(hRe −va1ll8ey)\n1-valley 2-valley\n2 2\npoint, k is Boltzmann constant and T is the temperature. In this way, the interface widths of junction\nL (W ) and R (W ) at valley point are:\n1-valley 2-valley\n2ε𝑆(𝑉bi1−𝑉valley) ε𝑆(𝑉bi1+𝑉bi2)\n𝑊1-valley = √ = √ , (R−19)\n𝑞𝑁d 𝑞𝑁d\n2𝜀𝑆(𝑉bi2 +𝑉valley) 𝜀𝑆(𝑉bi1+𝑉bi2)\n𝑊2-valley = √ = √ . (R−20)\nHere, we define W\n1-valley\n= W\n2-valley\n= W\nvalley\n.𝑞 A𝑁dccording formulas 𝑞(R𝑁-d14), (R-15), (R-19), (R-20), the\nEquation (17) in original supplementary materials can be derived:\n2 2\n𝑊1 +𝑊2 2\nSimilar derivation can be conducted under the case tha=t t𝑊hev ajlulenyc. t i o n L i s u n s t r e s s e d a n d t h e ( Rjun−ct2io1n)\nQuestion #17\nThe clarity of the manuscript could be further improved by adding additional details on the device\nfabrication, experimental procedures, and physical mechanisms directly within the main text, rather\nthan leaving them mainly in the Supplementary Information.\nResponse #17:\nThanks for the reviewer’s suggestions. We have added the device fabrication, experimental\nprocedures, and physical mechanisms parts into the manuscript:\n In line 248-252 in section: “Capacitive piezotronics in dual Schottky junctions”: “…The\nelectrical measurement system in this experiment utilizes a DC voltage to apply bias between\njunction L and R, which is respectively reverse-biased (L) and forward-biased (R) at negative\nDC voltage, while overturned at positive DC voltage, and simultaneously utilizes a V signal to\nAC\nconduct capacitance measurements under such bias conditions…”\n In line 271-276 section “Capacitive piezotronics in dual Schottky junctions”: “…Furthermore,\nbecause the valley point occurs when the dual junctions are balanced, the valley capacitance\ncould reflect the variation of each junction. Accordingly, we can obtain the changes of interface\nwidth of dual Schottky junctions from the change in the valley capacitance (Supplementary Note\n4), which respectively reaches 5.1 nm (Fig. 4e) and 0.6 nm (Fig. 4h) at 2.42 MPa. The smaller\nvariation in the interface width with force on junction R could be attributed to the higher initial\ndoping concentration near junction R...”\n In line 290-313 in section “Capacitive piezotronics in dual Schottky junctions”: “…Note that the\npeak capacitance of C-V curve in low-frequency is primarily dominated by the interface width of\nthe reverse-biased junction (junction L in the negative voltage region and junction R in the\npositive region). Thus, the peak shifting closer to zero bias is dominated by junction L. An\nabnormal phenomenon is observed that this peak capacitance increases rather than deceases as\nthe junction L is stressed, which can be attributed to two mechanisms. On the one hand,\nalthough the negative polarization charges increase the interface width of the stressed junction,\nthe peak moves to a lower bias owing to the shift of C-V curve, and the lower bias will\nsimultaneously decrease the interface width and hence compensate for the capacitance\nreduction. On the other hand, the changed effective carrier concentration near the interface also\nmakes a contribution to the increasing capacitance (Supplementary Note 4). For the other peak\nof C-V curve in the positive bias, the interface width of the unstressed junction R becomes the\ndominant factor. Since the piezotronic polarization is spatially confined to the stressed junction\nL, the interface width of the junction R is only influenced by the external bias. As this peak shifts\nto a higher bias region, the increased bias expands its interface width, and thus decreases the\npeak capacitance. Conversely, when the force is applied to junction R, the peak value in the\nnegative bias decreases while the other peak value increases (Fig. 4f). This is a unique\nasymmetric capacitance modulation induced by the capacitive piezotronic effect (Supplementary\nFigs. 5, 6). Under high-frequency settings, the capacitance of the peak at near-zero bias is\ndominated by both of the dual Schottky junctions. The interface widths of dual Schottky\njunctions exhibit opposing variations with one of the junctions stressed: the stressed junction\nwidens, whereas the unstressed junction narrows. The experimental results further suggest that\nthe narrowed junction may play a dominant role (Fig. 4d, g and Supplementary Fig. 7), leading\nto an increase in peak capacitance under loading forces. Furthermore, this increase is also\nascribed to the variation in the effective carrier concentration near the stressed junction\n(Supplementary Note 5).…”\n The section “Methods” has been added to the end of the revised manuscript, which includes\ndetailed device fabrication and experimental procedures.\nWe are grateful for the reviewer’s guidance, which has been invaluable in strengthening this\nwork.\nQuestion #18\nThe last section of the manuscript “Relationship between capacitive piezotronics, resistive\npiezotronics and traditional capacitive effect” could be summarized and added in the introduction or\nin the ‘mechanism of the capacitive piezotronics’, since the main claims have already been\nintroduced.\nResponse #18:\nThanks for the reviewer’s suggestion. We have reorganized the section of “Relationship between\ncapacitive piezotronics, resistive piezotronics and traditional capacitive effect”, and moved this part\nto follow the mechanism in the revised manuscript and marked this section in red.\nFinally, we appreciate the reviewers’ suggestions and guidance for our work again. Based on the\ndetails discussed above, we have revised the manuscript and the supplementary materials.\nPoint-to-Point Response to Reviewers’ comments:\nWe are grateful to the reviewers for their constructive and insightful comments on our revised\nmanuscript and supplementary materials. In the pages that follow, we have provided our responses to\neach of the reviewers’ questions\nReviewer #1 (Remarks to the Author):\nAll comments have been taken into account in the new version, and the quality of the article has been\nsignificantly improved. I believe it can be published in its current form.\nResponse:\nThanks for the reviewer’s positive assessment of our work. We are delighted to learn that all of the\nreviewer’s comments have been satisfactorily addressed and we sincerely thank the reviewer for the\ndetailed and responsible reviewing of our work.\nReviewer #2 (Remarks to the Author):\nThe authors have responded thoroughly to the reviewer’s comments. They have referred to prior\nliterature, improved the clarity of several figures, added the requested derivations and theoretical\nmodels, and provided additional details in the main text. In particular, the physical interpretation of the\nC–V curves shape, the observed shift, and the asymmetric capacitance behavior is now clearer and\nbetter motivated. Overall, the manuscript has significantly improved. A few points, however, would\nstill benefit from further clarification before publication.\nResponse:\nWe sincerely thank the reviewer for the encouraging feedback and for acknowledging that our previous\nrevisions have significantly improved the quality of the manuscript. And we also thank the reviewer’s\ndetailed and responsible reviewing of our revised manuscript and supplementary materials. In response\nto the remaining points, we have provided further clarifications and made comprehensive revisions to\nthe manuscript and supplementary materials.\nAbstract revision\nWhile the revised abstract more clearly states that both theoretical analysis and experimental\ninvestigations are involved, it remains unclear how the reported quantitative values are obtained and\nto which specific devices they refer. The authors are encouraged to explicitly state that finite-element\nsimulations and experimental measurements were carried out on GaN-based (and subsequently ZnO-\nbased) Schottky diodes, and to clarify which results are experimentally measured and which are\nsupported by simulations. Phrases such as “Experimental measurements on GaN-based Schottky\ndiodes show that…” and “Finite-element simulations confirm that…” could be considered.\nMoreover, when referring to “high frequency” operation, the authors should provide indicative\nfrequency ranges (e.g., kHz regime) in order to better contextualize the practical applicability of the\ndevices.\nResponse to Abstract Revision:\nThanks for the reviewer’s valuable suggestions and guidance. In response to these questions, we have\nmade revisions on the abstract and the relevant sections in the main text.\n1. While the revised abstract more clearly states that both theoretical analysis and experimental\ninvestigations are involved, it remains unclear how the reported quantitative values are obtained\nand to which specific devices they refer.\nWe are sorry for the unclear description in our abstract. We would like to clarify that the finite-\nelement analysis in our work mainly aims at revealing and verifying the underlying mechanism of\ncapacitive piezotronics. And, the reported quantitative values, such as the change in interface width\nand the strain sensitivity, are all based on our experimental results. To further clarify the research\nmethods, we have revised the abstract as follows (bold sentences):\n“Interface engineering by ionic polarization is vitally important in condensed-matter physics,\nderiving a plethora of distinctive phenomena, such as resistive piezotronics, pyroelectrics,\nferroelectrics, flexoelectronics and many more. Most of them focus on the polarization modulated\nbarrier height for effectively controlling carrier transport of DC electronics. However, modulating\nthe interface width and its resultant effects under AC settings have not been deeply explored. Here,\nwe report the capacitive piezotronics, which utilizes the strain-induced piezoelectric polarization\nto precisely control the interface width of heterostructures and hence modulate the junction\ncapacitance at a high frequency (~kHz-MHz). It is a distinctive regulation mechanism that is widely\npresent in piezoelectric semiconductors (ZnO, GaN, etc.). This mechanism was rigorously verified\nby a combination of finite element analysis and experimental measurements in GaN-based\nSchottky contacts. Our experimental results show that the interface width can be reversibly\ntuned with amplitudes as high as 10.5 nm in GaN-based single Schottky junction and 5.1 nm in\nGaN-based dual Schottky junctions, which presents a high strain sensitivity (ΔC/p > 110\nfF/mbar in single Schottky junction) and surpasses that of commercial capacitive pressure\nsensors (~0.1-0.7 fF/mbar). More excitingly, the new effect possesses a capacity of mechanically\ntuning the transmission signal in communication systems with a frequency shift > 11 kHz, and\nsubstantially improving the filtering characteristics particularly for high-frequency noise (> 300\nkHz). This study gives a brand-new strain-tuned AC electronics based on piezoelectric\nsemiconductors, offering a distinctive approach for high-quality communication via mechanical\nstimuli.”\n2. Moreover, when referring to “high frequency” operation, the authors should provide indicative\nfrequency ranges (e.g., kHz regime) in order to better contextualize the practical applicability of\nthe devices.\nWe thank the reviewer for raising this important point. In response, we have carefully reviewed all\ninstances of “high frequency” in the abstract and main text. Regarding those referring to a specific\nfrequency range, we have revised them according to our test conditions:\n In the fourth sentence of the abstract: “…and hence modulate the junction capacitance at a\nhigh frequency (~kHz-MHz)…”. This frequency range is determined by the test environment\nin Figures 3-4 (1-10 kHz) and the signal frequency in Figure 5 (~300 kHz).\n In the eighth sentence of the abstract: “…and substantially improving the filtering\ncharacteristics particularly for high-frequency noise (> 300 kHz)…”. This range is determined\nby the frequency of noise in Figure 5.\n In the third paragraph of the main text: “…so as to control the junction capacitance under high\nfrequency AC settings (~kHz-MHz)…”\n In the first paragraph of the section “Summary and outlook”: “…in which the interface width\nand hence the junction capacitance at high-frequency AC settings (~kHz-MHz) can be\ndynamically modulated by strain-induced piezoelectric polarization…”\n In the section “Capacitive piezotronics in dual Schottky junctions”, the high-frequency\ncondition refers to the frequency range ≥ 5 kHz and it has been clarified at a proper position:\n“…and found two peaks (one around –0.5 V and the other around 0.5 V) at low-frequency (<\n5 kHz), while only one peak (around 0 V) at high-frequency (≥ 5 kHz)…”\nNote that, in a few instances, the term “high frequency” is used in a more general, introductory\ncontext, where specifying a particular frequency range would be unsuitable. So, we would like to\nkeep them in their original form, such as:\n In the second paragraph of the main text: “…especially those regarding communication\napplications such as high-frequency transport…”\n In the third paragraph of the section “Mechanism of the capacitive piezotronics”: “…especially\nat high-frequency systems…”\n ……\nWe hope that these revisions could improve the quality of our work and we sincerely thank the reviewer\nagain for prompting these important advices.\nSpecific comments to the authors' responses\nR1. Although the symbol “P” has been replaced with “polarization” in Fig. 1a, it is still used elsewhere\nwithout definition. For consistency, it should be explicitly defined or replaced throughout the\nmanuscript.\nResponse #1:\nThanks for pointing that out. We have carefully checked the entire manuscript and supplementary\nmaterials, and have ensured that the symbol “P” is either explicitly defined or replaced with the full\nterm “polarization”. The revised Figure 3 and Supplementary Figure 16 have been provided at the\nend of this response:\nSupplementary Figure 16 | Modulation mechanism of piezoelectric polarization on the built-in\npotential of Schottky junction at compressive strain (a), strain free (b) and tensile strain (c)\nconditions.\nFigure 3 | Capacitive piezotronics in single Schottky junction.\nR6. The authors have provided a convincing theoretical justification for the choice of measurement\nfrequency and for the frequency-independent behavior of a single Schottky junction under reverse bias.\nWhile an explicit experimental verification of the absence of frequency dispersion would have been\nappreciated, the present explanation is sufficient and consistent with established literature.\nResponse #6:\nThanks for the reviewer’s comment. In response, we have provided the C-V characteristics of a single\nSchottky junction under different frequencies in Figure R1. Experimental results show that the\ncapacitance measured at reverse bias remains almost unchanged as the frequency changes, while the\ncapacitance measured at forward bias exhibit a significant change. These results provide a verification\nof our theoretical justification, and are also consistent with the previous works (such as Supplementary\nFigure 10 in Ref.: Georgiadou, D. G. et al. Nat. Electron., 2020, 3, 718-725).\nFigure R1| The C-V characteristics of a single Schottky junction under different frequencies.\nR8. The clarification of the measurement setup and the demonstration that strain effects are spatially\nlocalized in the stressed junction are appreciated. However, in the low-frequency C–V characteristics\nof the dual Schottky junction (Figs. 4c and 4f), the reported zero-strain curves exhibit noticeably\ndifferent peak asymmetries. The authors are encouraged to clarify whether these strain-free curves\nwere acquired under identical measurement and normalization conditions, and whether factors such as\nmechanical boundary conditions, contact resistance, or low-frequency drift/hysteresis could account\nfor these differences.\nResponse #8:\nWe sincerely thank the reviewer for acknowledging our revised manuscript and providing further\nvaluable suggestions.\nIn response to the reviewer’s questions on Figure 4c, f, we have carefully checked our\nexperimental results. We would like to clarify that, these two zero-strain curves were acquired under\nthe same measurement and normalization conditions, and are consistent with each other within\nexperimental precision. To clearly clarify this, we have emphasized these zero-strain curves with the\nblack lines in Figure R2, and it can be seen that the two lines exhibit no significant difference. We\nhave revised the caption of Figure 4:\n“…These results were acquired under identical test conditions and normalization conditions.”\nWe are sorry for this misunderstanding and we hope that our response would address your\nquestions.\nFigure R2 | The force-dependent C-V characteristics of dual Schottky junctions based device. a,\nForce on junction L. b, Force on junction R. These results are acquired under identical test conditions\nand normalization conditions. The zero-strain curves are all emphasized in black.\nR9. The explanation of the asymmetric C–V peaks in terms of fabrication-related non-idealities (e.g.,\nlocal variations in effective doping concentration or slightly different metal pad areas) is physically\nreasonable. The authors are encouraged to state this more explicitly in the main text, for instance by\nrevising the sentence: “It can be seen that the two peaks at low frequency are slightly different,\nresulting from…” or by referring to this point in the Methods section.\nResponse #9:\nThanks for the reviewer’s constructive suggestions. As suggested, we have revised the sentence in the\nsecond paragraph of the section “Capacitive piezotronics in dual Schottky junctions” to more explicitly\nstate the explanation of the asymmetric C-V peaks:\n“…It can be seen that the two peaks at low-frequency are slightly different, resulting from the\nfabrication induced non-idealities of the dual Schottky junctions (e.g., local variations in effective\ndoping concentration or slightly different metal pad areas)…”\nR14. The revised description of the increase in the capacitance peak is clearer. The authors are\nencouraged to elaborate slightly more in the main text on the role of the effective charge concentration,\nwhile keeping the full quantitative details in the Supplementary Information. This would help convey\na more complete physical picture within the manuscript.\nResponse #14:\nThanks for the reviewer’s insightful comment. To more explicitly demonstrate the role of the effective\ncharge concentration, we have revised the related parts in the third paragraph of the section “Capacitive\npiezotronics in dual Schottky junctions” as follows:\n“…On the other hand, the changed effective carrier concentration near the interface enables\ninterfacial electrostatic equilibrium (Fermi Level alignment) to be sustained within a narrower\ninterface width, which also makes a contribution to the increasing capacitance (Supplementary Note\n4)…”\nThis revision provides a more detailed qualitative description on the role of the effective carrier\nconcentration and how its variation affects the peak capacitance. We hope that this response could\naddress your question and improve the quality of our work.\nFurthermore, although the valley in low-frequency measurements and the peak in high-frequency\nmeasurements are experimentally observed at zero bias (Figure 4), statements such as “the valley\noccurs only when R =R ” (Supplementary Note 4.2) or “the peak locates at zero bias when the\n1 2\njunctions are perfectly symmetric” (Supplementary Note 5) may be misleading in the presence of\nfabrication-induced asymmetries. It would be clearer to specify that the condition R =R is satisfied at\n1 2\na specific bias point (which may coincide with zero bias), rather than implying perfect structural\nsymmetry.\nResponse:\nThanks for the constructive suggestion, and we have revised the relevant content as follows:\n In the third paragraph of the section “Capacitive piezotronics in dual Schottky junctions”: “…In\nthe absence of an external loading force, both the low-frequency and high-frequency C-V curves\nof the dual Schottky junctions are centered at near-zero bias region…”\n In the first paragraph of Supplementary Note 4.2: “Based on analysis above, the valley in low-\nfrequency C–V curve occurs only at the bias where the resistances of the dual Schottky junctions\nare equal (R = R ), which also represents the interface barrier heights are equal here (φ = φ ).\n1 2 1 2\nGenerally, this symmetry condition R = R /φ = φ can be satisfied at a specific bias (which may\n1 2 1 2\ncoincide with zero bias if the configuration of dual Schottky junctions is almost symmetric). When\nthe force applied on one of the junctions, the induced negative polarization charges will increase\nits interface barrier height and width and the specific bias that satisfying the symmetry condition\nwill change, with the valley shifts and a variation in C–V curve being induced (Supplementary\nFig. 20a)…”\n In the first paragraph of Supplementary Note 5: “…Similar to the case under low-frequency\nsettings, the peak locates at a specific bias (which may coincide with zero bias if the configuration\nof dual Schottky junctions is almost symmetric) under zero-strain condition, while exhibits a shift\nwhen the configuration of dual Schottky junctions is modified by the force-induced piezoelectric\npolarization potential…”\nThanks for the reviewer’s guidance again and we hope that our revision could improve our work.\nFinally, the authors are encouraged to further refine the language and avoid overly strong expressions\nsuch as “abnormal phenomenon”, “huge impact”, or “unexpectedly giant effect”, in order to maintain\na balanced scientific tone.\nResponse:\nThanks for the in-depth reviews to help us improve the manuscript. We have conducted a careful check\non our manuscript and supplementary materials and have revised the relevant contents as follows:\n In the third paragraph of the section “Mechanism of the capacitive piezotronics”: “…which\nsignificantly influences the migration and redistribution of carriers at the interface, so as to\nchange the interface width…”\n In the third paragraph of the main text: “…A substantial capacitive piezotronic effect was\ndiscovered in both single and dual Schottky junctions…”\n In the third paragraph of the section “Capacitive piezotronics in dual Schottky junctions”: “…An\nanomalous phenomenon is observed that this peak capacitance increases rather than deceases as\nthe junction L is stressed…”\n In the first paragraph of the section “Summary and outlook”: “…This effect reveals a seldom\nrecognized coupling between piezoelectric polarization and high-frequency AC electronics…”\nFinally, we thank the reviewer for the deep patience and effort in reviewing our manuscript. We\nare particularly grateful for the detailed logic, linguistic and stylistic suggestions. These insightful\nsuggestions have significantly refined the presentation of our work and improved the overall\nreadability of the manuscript.\nReviewer #2 (Remarks to the Author):\nThe authors have adequately addressed all the comments in the revised manuscript. In\nmy opinion, the paper can be accepted for publication in its current version.\nResponse:\nThanks for the reviewer’s positive assessment of our work. We are delighted to learn\nthat all of the reviewer’s comments have been adequately addressed and we sincerely\nthank the reviewer for the detailed and responsible reviewing of our work.\nFinally, we sincerely thank the editor and the reviewers for spending so much time and\neffect on improving the quality of our paper. These constructive and professional\nsuggestions are very helpful for us to upgrade our understandings and investigations\nand promote us to one step further. Thank you very much!"}, {"round": 2, "reviewer_comments": {"reviewer_1": "All comments have been taken into account in the new version, and the quality of the article has been significantly improved.\nI believe it can be published in its current form.", "reviewer_2": "The authors have responded thoroughly to the reviewer’s comments. They have referred to prior literature, improved the clarity of several figures, added the requested derivations and theoretical models, and provided additional details in the main text. In particular, the physical interpretation of the C–V curves shape, the observed shift, and the asymmetric capacitance behavior is now clearer and better motivated. Overall, the manuscript has significantly improved. A few points, however, would still benefit from further clarification before publication."}, "author_response": "Point-to-Point Response to Reviewers’ comments:\nWe are grateful to the reviewers for their constructive and insightful comments on our revised\nmanuscript and supplementary materials. In the pages that follow, we have provided our responses to\neach of the reviewers’ questions\nReviewer #1 (Remarks to the Author):\nAll comments have been taken into account in the new version, and the quality of the article has been\nsignificantly improved. I believe it can be published in its current form.\nResponse:\nThanks for the reviewer’s positive assessment of our work. We are delighted to learn that all of the\nreviewer’s comments have been satisfactorily addressed and we sincerely thank the reviewer for the\ndetailed and responsible reviewing of our work.\nReviewer #2 (Remarks to the Author):\nThe authors have responded thoroughly to the reviewer’s comments. They have referred to prior\nliterature, improved the clarity of several figures, added the requested derivations and theoretical\nmodels, and provided additional details in the main text. In particular, the physical interpretation of the\nC–V curves shape, the observed shift, and the asymmetric capacitance behavior is now clearer and\nbetter motivated. Overall, the manuscript has significantly improved. A few points, however, would\nstill benefit from further clarification before publication.\nResponse:\nWe sincerely thank the reviewer for the encouraging feedback and for acknowledging that our previous\nrevisions have significantly improved the quality of the manuscript. And we also thank the reviewer’s\ndetailed and responsible reviewing of our revised manuscript and supplementary materials. In response\nto the remaining points, we have provided further clarifications and made comprehensive revisions to\nthe manuscript and supplementary materials.\nAbstract revision\nWhile the revised abstract more clearly states that both theoretical analysis and experimental\ninvestigations are involved, it remains unclear how the reported quantitative values are obtained and\nto which specific devices they refer. The authors are encouraged to explicitly state that finite-element\nsimulations and experimental measurements were carried out on GaN-based (and subsequently ZnO-\nbased) Schottky diodes, and to clarify which results are experimentally measured and which are\nsupported by simulations. Phrases such as “Experimental measurements on GaN-based Schottky\ndiodes show that…” and “Finite-element simulations confirm that…” could be considered.\nMoreover, when referring to “high frequency” operation, the authors should provide indicative\nfrequency ranges (e.g., kHz regime) in order to better contextualize the practical applicability of the\ndevices.\nResponse to Abstract Revision:\nThanks for the reviewer’s valuable suggestions and guidance. In response to these questions, we have\nmade revisions on the abstract and the relevant sections in the main text.\n1. While the revised abstract more clearly states that both theoretical analysis and experimental\ninvestigations are involved, it remains unclear how the reported quantitative values are obtained\nand to which specific devices they refer.\nWe are sorry for the unclear description in our abstract. We would like to clarify that the finite-\nelement analysis in our work mainly aims at revealing and verifying the underlying mechanism of\ncapacitive piezotronics. And, the reported quantitative values, such as the change in interface width\nand the strain sensitivity, are all based on our experimental results. To further clarify the research\nmethods, we have revised the abstract as follows (bold sentences):\n“Interface engineering by ionic polarization is vitally important in condensed-matter physics,\nderiving a plethora of distinctive phenomena, such as resistive piezotronics, pyroelectrics,\nferroelectrics, flexoelectronics and many more. Most of them focus on the polarization modulated\nbarrier height for effectively controlling carrier transport of DC electronics. However, modulating\nthe interface width and its resultant effects under AC settings have not been deeply explored. Here,\nwe report the capacitive piezotronics, which utilizes the strain-induced piezoelectric polarization\nto precisely control the interface width of heterostructures and hence modulate the junction\ncapacitance at a high frequency (~kHz-MHz). It is a distinctive regulation mechanism that is widely\npresent in piezoelectric semiconductors (ZnO, GaN, etc.). This mechanism was rigorously verified\nby a combination of finite element analysis and experimental measurements in GaN-based\nSchottky contacts. Our experimental results show that the interface width can be reversibly\ntuned with amplitudes as high as 10.5 nm in GaN-based single Schottky junction and 5.1 nm in\nGaN-based dual Schottky junctions, which presents a high strain sensitivity (ΔC/p > 110\nfF/mbar in single Schottky junction) and surpasses that of commercial capacitive pressure\nsensors (~0.1-0.7 fF/mbar). More excitingly, the new effect possesses a capacity of mechanically\ntuning the transmission signal in communication systems with a frequency shift > 11 kHz, and\nsubstantially improving the filtering characteristics particularly for high-frequency noise (> 300\nkHz). This study gives a brand-new strain-tuned AC electronics based on piezoelectric\nsemiconductors, offering a distinctive approach for high-quality communication via mechanical\nstimuli.”\n2. Moreover, when referring to “high frequency” operation, the authors should provide indicative\nfrequency ranges (e.g., kHz regime) in order to better contextualize the practical applicability of\nthe devices.\nWe thank the reviewer for raising this important point. In response, we have carefully reviewed all\ninstances of “high frequency” in the abstract and main text. Regarding those referring to a specific\nfrequency range, we have revised them according to our test conditions:\n In the fourth sentence of the abstract: “…and hence modulate the junction capacitance at a\nhigh frequency (~kHz-MHz)…”. This frequency range is determined by the test environment\nin Figures 3-4 (1-10 kHz) and the signal frequency in Figure 5 (~300 kHz).\n In the eighth sentence of the abstract: “…and substantially improving the filtering\ncharacteristics particularly for high-frequency noise (> 300 kHz)…”. This range is determined\nby the frequency of noise in Figure 5.\n In the third paragraph of the main text: “…so as to control the junction capacitance under high\nfrequency AC settings (~kHz-MHz)…”\n In the first paragraph of the section “Summary and outlook”: “…in which the interface width\nand hence the junction capacitance at high-frequency AC settings (~kHz-MHz) can be\ndynamically modulated by strain-induced piezoelectric polarization…”\n In the section “Capacitive piezotronics in dual Schottky junctions”, the high-frequency\ncondition refers to the frequency range ≥ 5 kHz and it has been clarified at a proper position:\n“…and found two peaks (one around –0.5 V and the other around 0.5 V) at low-frequency (<\n5 kHz), while only one peak (around 0 V) at high-frequency (≥ 5 kHz)…”\nNote that, in a few instances, the term “high frequency” is used in a more general, introductory\ncontext, where specifying a particular frequency range would be unsuitable. So, we would like to\nkeep them in their original form, such as:\n In the second paragraph of the main text: “…especially those regarding communication\napplications such as high-frequency transport…”\n In the third paragraph of the section “Mechanism of the capacitive piezotronics”: “…especially\nat high-frequency systems…”\n ……\nWe hope that these revisions could improve the quality of our work and we sincerely thank the reviewer\nagain for prompting these important advices.\nSpecific comments to the authors' responses\nR1. Although the symbol “P” has been replaced with “polarization” in Fig. 1a, it is still used elsewhere\nwithout definition. For consistency, it should be explicitly defined or replaced throughout the\nmanuscript.\nResponse #1:\nThanks for pointing that out. We have carefully checked the entire manuscript and supplementary\nmaterials, and have ensured that the symbol “P” is either explicitly defined or replaced with the full\nterm “polarization”. The revised Figure 3 and Supplementary Figure 16 have been provided at the\nend of this response:\nSupplementary Figure 16 | Modulation mechanism of piezoelectric polarization on the built-in\npotential of Schottky junction at compressive strain (a), strain free (b) and tensile strain (c)\nconditions.\nFigure 3 | Capacitive piezotronics in single Schottky junction.\nR6. The authors have provided a convincing theoretical justification for the choice of measurement\nfrequency and for the frequency-independent behavior of a single Schottky junction under reverse bias.\nWhile an explicit experimental verification of the absence of frequency dispersion would have been\nappreciated, the present explanation is sufficient and consistent with established literature.\nResponse #6:\nThanks for the reviewer’s comment. In response, we have provided the C-V characteristics of a single\nSchottky junction under different frequencies in Figure R1. Experimental results show that the\ncapacitance measured at reverse bias remains almost unchanged as the frequency changes, while the\ncapacitance measured at forward bias exhibit a significant change. These results provide a verification\nof our theoretical justification, and are also consistent with the previous works (such as Supplementary\nFigure 10 in Ref.: Georgiadou, D. G. et al. Nat. Electron., 2020, 3, 718-725).\nFigure R1| The C-V characteristics of a single Schottky junction under different frequencies.\nR8. The clarification of the measurement setup and the demonstration that strain effects are spatially\nlocalized in the stressed junction are appreciated. However, in the low-frequency C–V characteristics\nof the dual Schottky junction (Figs. 4c and 4f), the reported zero-strain curves exhibit noticeably\ndifferent peak asymmetries. The authors are encouraged to clarify whether these strain-free curves\nwere acquired under identical measurement and normalization conditions, and whether factors such as\nmechanical boundary conditions, contact resistance, or low-frequency drift/hysteresis could account\nfor these differences.\nResponse #8:\nWe sincerely thank the reviewer for acknowledging our revised manuscript and providing further\nvaluable suggestions.\nIn response to the reviewer’s questions on Figure 4c, f, we have carefully checked our\nexperimental results. We would like to clarify that, these two zero-strain curves were acquired under\nthe same measurement and normalization conditions, and are consistent with each other within\nexperimental precision. To clearly clarify this, we have emphasized these zero-strain curves with the\nblack lines in Figure R2, and it can be seen that the two lines exhibit no significant difference. We\nhave revised the caption of Figure 4:\n“…These results were acquired under identical test conditions and normalization conditions.”\nWe are sorry for this misunderstanding and we hope that our response would address your\nquestions.\nFigure R2 | The force-dependent C-V characteristics of dual Schottky junctions based device. a,\nForce on junction L. b, Force on junction R. These results are acquired under identical test conditions\nand normalization conditions. The zero-strain curves are all emphasized in black.\nR9. The explanation of the asymmetric C–V peaks in terms of fabrication-related non-idealities (e.g.,\nlocal variations in effective doping concentration or slightly different metal pad areas) is physically\nreasonable. The authors are encouraged to state this more explicitly in the main text, for instance by\nrevising the sentence: “It can be seen that the two peaks at low frequency are slightly different,\nresulting from…” or by referring to this point in the Methods section.\nResponse #9:\nThanks for the reviewer’s constructive suggestions. As suggested, we have revised the sentence in the\nsecond paragraph of the section “Capacitive piezotronics in dual Schottky junctions” to more explicitly\nstate the explanation of the asymmetric C-V peaks:\n“…It can be seen that the two peaks at low-frequency are slightly different, resulting from the\nfabrication induced non-idealities of the dual Schottky junctions (e.g., local variations in effective\ndoping concentration or slightly different metal pad areas)…”\nR14. The revised description of the increase in the capacitance peak is clearer. The authors are\nencouraged to elaborate slightly more in the main text on the role of the effective charge concentration,\nwhile keeping the full quantitative details in the Supplementary Information. This would help convey\na more complete physical picture within the manuscript.\nResponse #14:\nThanks for the reviewer’s insightful comment. To more explicitly demonstrate the role of the effective\ncharge concentration, we have revised the related parts in the third paragraph of the section “Capacitive\npiezotronics in dual Schottky junctions” as follows:\n“…On the other hand, the changed effective carrier concentration near the interface enables\ninterfacial electrostatic equilibrium (Fermi Level alignment) to be sustained within a narrower\ninterface width, which also makes a contribution to the increasing capacitance (Supplementary Note\n4)…”\nThis revision provides a more detailed qualitative description on the role of the effective carrier\nconcentration and how its variation affects the peak capacitance. We hope that this response could\naddress your question and improve the quality of our work.\nFurthermore, although the valley in low-frequency measurements and the peak in high-frequency\nmeasurements are experimentally observed at zero bias (Figure 4), statements such as “the valley\noccurs only when R =R ” (Supplementary Note 4.2) or “the peak locates at zero bias when the\n1 2\njunctions are perfectly symmetric” (Supplementary Note 5) may be misleading in the presence of\nfabrication-induced asymmetries. It would be clearer to specify that the condition R =R is satisfied at\n1 2\na specific bias point (which may coincide with zero bias), rather than implying perfect structural\nsymmetry.\nResponse:\nThanks for the constructive suggestion, and we have revised the relevant content as follows:\n In the third paragraph of the section “Capacitive piezotronics in dual Schottky junctions”: “…In\nthe absence of an external loading force, both the low-frequency and high-frequency C-V curves\nof the dual Schottky junctions are centered at near-zero bias region…”\n In the first paragraph of Supplementary Note 4.2: “Based on analysis above, the valley in low-\nfrequency C–V curve occurs only at the bias where the resistances of the dual Schottky junctions\nare equal (R = R ), which also represents the interface barrier heights are equal here (φ = φ ).\n1 2 1 2\nGenerally, this symmetry condition R = R /φ = φ can be satisfied at a specific bias (which may\n1 2 1 2\ncoincide with zero bias if the configuration of dual Schottky junctions is almost symmetric). When\nthe force applied on one of the junctions, the induced negative polarization charges will increase\nits interface barrier height and width and the specific bias that satisfying the symmetry condition\nwill change, with the valley shifts and a variation in C–V curve being induced (Supplementary\nFig. 20a)…”\n In the first paragraph of Supplementary Note 5: “…Similar to the case under low-frequency\nsettings, the peak locates at a specific bias (which may coincide with zero bias if the configuration\nof dual Schottky junctions is almost symmetric) under zero-strain condition, while exhibits a shift\nwhen the configuration of dual Schottky junctions is modified by the force-induced piezoelectric\npolarization potential…”\nThanks for the reviewer’s guidance again and we hope that our revision could improve our work.\nFinally, the authors are encouraged to further refine the language and avoid overly strong expressions\nsuch as “abnormal phenomenon”, “huge impact”, or “unexpectedly giant effect”, in order to maintain\na balanced scientific tone.\nResponse:\nThanks for the in-depth reviews to help us improve the manuscript. We have conducted a careful check\non our manuscript and supplementary materials and have revised the relevant contents as follows:\n In the third paragraph of the section “Mechanism of the capacitive piezotronics”: “…which\nsignificantly influences the migration and redistribution of carriers at the interface, so as to\nchange the interface width…”\n In the third paragraph of the main text: “…A substantial capacitive piezotronic effect was\ndiscovered in both single and dual Schottky junctions…”\n In the third paragraph of the section “Capacitive piezotronics in dual Schottky junctions”: “…An\nanomalous phenomenon is observed that this peak capacitance increases rather than deceases as\nthe junction L is stressed…”\n In the first paragraph of the section “Summary and outlook”: “…This effect reveals a seldom\nrecognized coupling between piezoelectric polarization and high-frequency AC electronics…”\nFinally, we thank the reviewer for the deep patience and effort in reviewing our manuscript. We\nare particularly grateful for the detailed logic, linguistic and stylistic suggestions. These insightful\nsuggestions have significantly refined the presentation of our work and improved the overall\nreadability of the manuscript.\nReviewer #2 (Remarks to the Author):\nThe authors have adequately addressed all the comments in the revised manuscript. In\nmy opinion, the paper can be accepted for publication in its current version.\nResponse:\nThanks for the reviewer’s positive assessment of our work. We are delighted to learn\nthat all of the reviewer’s comments have been adequately addressed and we sincerely\nthank the reviewer for the detailed and responsible reviewing of our work.\nFinally, we sincerely thank the editor and the reviewers for spending so much time and\neffect on improving the quality of our paper. These constructive and professional\nsuggestions are very helpful for us to upgrade our understandings and investigations\nand promote us to one step further. Thank you very much!"}, {"round": 3, "reviewer_comments": {"reviewer_2": "The authors have adequately addressed all the comments in the revised manuscript. In my opinion, the paper can be accepted for publication in its current version."}, "author_response": ""}]

Decision letter