Domain wall motion-driven magnetic convolutional accelerator

Domain: physics
Published: 2026-01-14
Editorial outcome: major_revision

Abstract
Modern computing powers applications from data analysis to artificial intelligence but now faces limitations. The slowdown of device scaling and the bottleneck between memory and processors motivate architectures that unify computation and data storage. Convolution is a core operation in learning, vision, and signal processing, yet its conventional implementation incurs high energy, high latency, and limited scalability. Magnetic systems that host spin textures, such as domain walls, offer dynamic behaviors that enable computation beyond traditional logic. Here we introduce a compute-in-memory platform that performs convolution by sequentially shifting magnetic domains and sensing the resulting signals. Information is written directly into domain patterns, processed through controlled motion, and read electrically, forming a nonvolatile structure suited for convolution tasks. This approach supports applications including Fourier analysis, neural networks, and image processing, achieving 103 to 105 improvements in area, energy, and throughput over existing technologies, marking a concrete advance in spintronic computing.

Introduction
Modern computing underpins transformative advances in artificial intelligence, data analytics, and signal processing. However, it now faces critical challenges. The continued scaling of CMOS technology has encountered severe limitations, signaling the breakdown of Moore’s Law, while the separation of memory and processing in the Von Neumann architecture introduces latency and energy bottlenecks. These issues are especially pronounced in workloads with high data movement and computational intensity, such as convolutional operations.

Convolution serves as a cornerstone of modern computing, enabling tasks such as deep learning, image recognition, and frequency-domain signal analysis by extracting spatial and temporal features across hierarchical representations1–4. Conventional hardware architectures accelerate convolution through CPUs, GPUs, and TPUs5,6, utilizing parallelized algorithms to enhance throughput. Yet, these systems remain constrained by the Boolean logic framework, which struggles to support multi-state and sequential operations efficiently7. Moreover, the underlying memory hierarchy—spanning registers, caches, RAM, and nonvolatile storage—introduces delays and energy costs associated with frequent data shuttling8. These cumulative inefficiencies motivate the search for generalized computing approaches that move beyond Boolean logic and exploit novel physical substrates for both memory and computation.

To address these limitations, emerging technologies are being explored to perform computation via intrinsic physical phenomena, giving rise to compute-in-memory (CIM) paradigms and architectures based on unconventional systems. Among these, spintronic systems based on magnetic solitons—particularly magnetic domain walls (DWs) and skyrmions—exhibit rich dynamic behaviors such as oscillation, motion, and mutual interactions9–17. These phenomena can be directly mapped to computational primitives, opening pathways toward low-power, high-speed, and nonvolatile computing architectures. Pioneering studies have demonstrated the immense potential of spintronic phenomena for computation: coupled nanomagnet oscillators have been shown to emulate neural networks18, spin-wave amplitudes have been used to encode information19, and DW motion has been harnessed to perform Boolean logic operations20. However, no prior work has demonstrated a platform that enables convolutional acceleration while simultaneously integrating memory and computation through spintronic mechanisms.

In this work, we present the Magnetic Convolutional Accelerator (MCA)—a spintronic hardware platform that leverages magnetic DW motion to perform convolution directly within memory. In the MCA, input data are physically encoded as magnetic domains, and computation is realized via sequential DW motion and anomalous Hall effect (AHE) readout, forming a nonvolatile, physical realization of convolution. This approach exploits the analogies between domain shifting and sliding-window operations, enabling the MCA to execute data processing tasks including short-time Fourier transform (STFT), convolutional neural networks (CNNs), and image processing. The system performance can be further enhanced by selecting alternative material systems. For example, systems with large Dzyaloshinskii–Moriya interaction (DMI) offer exceptional scalability (domain sizes down to sub-10 nm21); low-roughness systems provide significantly higher energy efficiency (DW motion energy ~27 aJ22); and heavy-metal/ferrimagnet systems enable much higher operation speeds (DW velocities exceeding 1000 m/s23 and dynamic frequencies reaching the THz regime24). Importantly, all these systems retain the key advantage of nonvolatility25.

While a fully general-purpose computer based on emerging technologies and CIM remains a long-term vision—limited today by incomplete algorithm-hardware codesign, device-level maturity, and CMOS integration barriers—our MCA represents a concrete advancement in this direction. It achieves CIM functionality and is particularly suited to edge computing scenarios, where fast, localized, and energy-efficient data processing is critical. Compared to 28 nm CMOS technology, our MCA platform achieves 3 to 5 orders of magnitude improvements in combined area, throughput, and energy efficiency, highlighting its promise as a scalable and sustainable alternative to conventional architectures.

Results
MCA architecture and convolution mechanism
Following the introduction of the MCA, we now detail its hardware structure and operating principles, as illustrated in Fig. 1a. The MCA implements convolutional operations using a streamlined and highly integrable architecture based on serially connected magnetic computing unit cells.

Each unit cell consists of a magnetic domain segment overlapped by AHE readout electrodes (Fig. 1b). The magnetic domains are encoded as regions with opposite magnetization: red rectangles represent magnetic moments aligned along the –z direction, and blue rectangles represent moments along the +z direction. Gold-colored strips and pads define the AHE electrodes, which sense the net out-of-plane magnetization within their coverage area.

The Hall voltage (VH) output of a single unit cell is governed by the relation:

VH = \alpha I H 2L D \cdot L P W P (1)

Where \alpha is a device- and material-dependent constant, IH is the applied current flowing along the +x axis of the device, and LD is the domain length in the x direction with the domain magnetization aligned along the –z direction, LP is the electrode contact length, and WP is the lateral spacing between the electrode pairs. This relation captures the combined contributions of domain configuration and electrode geometry to the electrical signal. For a detailed derivation, see “Methods”.

In our MCA implementation, we fix \alpha, LP, and IH during operation, enabling a simplified form:

V H = c 1 + c 2 W P L D (2)

Where c1 and c2 are device-specific constants determined by fabrication. This linear dependence allows the Hall voltage to directly encode the product of domain length and electrode spacing—the two physical quantities mapped to the convolution input and kernel, respectively.

By serially connecting multiple unit cells together, the MCA (Fig. 1a) sums the outputs from each unit cell to form the total Hall voltage:

V H,TOTAL = c 1 + c 2 \sum_{n=1}^{N} W P (n)L D (n) (3)

Where N is the number of unit cells. Critically, in each clock cycle, the domains are shifted by one unit cell length, enabling dynamic convolution across the input data. In each computing cycle, we shift the domains by one unit cell. After k cycles of domain displacement, the total Hall voltage evolves to:

V H,TOTAL (k) = c 1 + c 2 \sum_{n=1}^{N} W P (n)L D (n-k) (4)

This sequential shift-and-readout operation physically implements the convolution W P * L D [k] in real time. The domain lengths LD encode the input signal, while the electrode spacings WP define the convolution coefficients.

The working principle, W P * L D [k] = \sum_{n=1}^{N} W P (n)L D (n-k), is illustrated schematically in Fig. 1c. The first row shows the discrete input domains (blue dots) corresponding to varying LD values. The second row represent the convolutional coefficients (red dots) corresponding to variations in WP, with a gray arrow indicating the shifting direction of the convolution kernel. The device-level cartoon (third row) depicts the magnetic domains, Hall electrodes, and the domain shifting direction (gray arrow). As the domains move sequentially under stationary electrodes, the resulting Hall voltages cumulatively realize the convolution, as shown in the final row.

The domain shifting is enabled by spin-orbit torque (SOT), as depicted in Fig. 1d. A charge current j flowing along the x-axis generates a transverse spin current js via the spin Hall effect, exerting a torque on the DWs26. This spin torque induces coherent DW motion at velocity v, governed by the interplay between spin-orbit effects and DMI9,15. As a result, the magnetic domains translate uniformly along the conduit, enabling real-time, clocked convolution operations. Further experimental details of domain control are provided in “Methods” and Supplementary Fig. 1.

Experimental realization of the MCA
The experimental implementation of the MCA can be categorized into three key stages: (1) generation and control of domain lengths (LD) to encode the input signal, (2) DW motion induced by SOT to shift the domains sequentially, and (3) convolution signal readout via the AHE.

Figure 2a schematically illustrates the domain nucleation process. A current-induced Oersted field is applied using an orthogonal conducting or microwave stripline overlaid on the magnetic conduit. Within the magnetic material, gray-shaded regions denote smoothly rotating DW magnetization, transitioning between +z-oriented (blue) and –z-oriented (red) domains. By injecting a short current pulse I into the stripline, a localized Oersted field H is generated, nucleating a +z-magnetized domain (blue). The domain length LD can be finely controlled by tuning the polarity, magnitude, and duration of the current pulse, allowing flexible input encoding. Once nucleated, the domains are shifted collectively by moving their associated DWs, as depicted in Fig. 2b. The DW velocity (VDW) is driven by the applied current j and propagates along the conduit in the current direction, enabling synchronized displacement of multiple domains.

A microscope image of a fabricated MCA device is shown in Fig. 2c, highlighting key functional regions for domain generation, shifting, and readout. Details regarding material characterization and device fabrication are provided in Supplementary Figs. 2 and 3.

Figure 2d–h presents experimental demonstrations corresponding to the three operational stages introduced earlier.

(1) Domain generation and control: Fig. 2di illustrates the application of a 200 mA, 1 ms current pulse (Igen) into the left Oersted Channel to nucleate a +z magnetized domain (blue) within the Domain Channel. As shown in Fig. 2dii, this process produces a domain of ~32 μm length at the left side of the conduit. By varying the polarity and magnitude of Igen, different domain lengths (LD) are achieved. Specifically, current pulses of –80 mA, –90 mA, and –100 mA (each 1 ms duration) yield LD values of 14 μm, 11 μm, and 6 μm, respectively, as displayed in Fig. 2diii. To further refine the domain size control, we performed COMSOL simulations to estimate the spatial distribution and energy consumption of the Oersted field based on device geometry, detailed in Supplementary Fig. 4.

(2) Domain shifting via SOT: Fig. 2e presents the demonstration of sequential domain shifting. The operation is performed by injecting SOT pulses (Ishift) through the Shifting and Domain Channel (Fig. 2ei). Four magnetic domains, initially spaced at 20 μm intervals (matching the Hall Channel pitch), are sequentially shifted. The corresponding domain-shifting velocity and thermal effects induced by the SOT pulses are experimentally characterized and discussed in Supplementary Note 1 and Note 2, respectively.

As shown in Fig. 2eii, the first domain appears at the right side of the Domain Channel, while the remaining three domains lie outside the field of view. Each SOT pulse displaces the domain sequence by 20 μm toward the left. Figure 2eiii–vi shows the progressive movement of domains into the Hall Channel region. Additional pulses continue the stepwise displacement of the domains, as shown in Fig. 2evii, progressively shifting the domain sequence across the Hall Channel region and completing the full convolution operation.

During the shifting process, small fluctuations in domain length are observed, attributed to domain-wall pinning and imperfect synchronization between neighboring walls. This effect, referred to as the domain-wall synchronization problem, is systematically analyzed in Supplementary Note 3. Complementary micromagnetic simulations further examine the impact of domain-wall pinning in downscaled devices, as shown in Supplementary Note 4.

(3) Convolution signal readout via AHE: When the domains are positioned beneath the Hall electrodes, the convolution signal (VAHE) is recorded according to the physical convolution mapping introduced in Eq. (4). Here, the convolution coefficients (kernels) are encoded in the electrode spacings (WP), while the input values are mapped to domain lengths (LD). The granularity of the readout—represented by ΔVAHE ≈ ΔWP ΔLD —is experimentally characterized as a function of both WP and LD, as shown in Fig. 2f, g.

In Fig. 2f, varying WP from 2 μm to 20 μm while keeping LD = 14 μm fixed results in a linear increase of VAHE from approximately 0.9 mV to 4.8 mV. Conversely, in Fig. 2g, LD is varied from 0 μm to 14 μm with a fixed WP = 8 μm, yielding a linear change in VAHE from 0 to 2 mV. Additional tests of VAHE versus LD for various WP values exhibit similar linearity, five examples of which are shown in Fig. 2h. Minor deviations from perfect linearity are attributed to fabrication-induced pinning sites and material imperfections. Further characterization of the current dependence of VAHE is provided in Supplementary Fig. 5 and refer to “Methods” for AHE reading details.

With the successful demonstration of domain generation, shifting, and convolution readout, the complete operational cycle of the MCA is realized. For practical deployment, however, the three functional stages must operate simultaneously and repeatedly with high stability and reproducibility. This requirement raises considerations of device yield and endurance, which directly affect large-scale integration and long-term reliability. To evaluate these aspects, we performed systematic tests of fabrication yield and cycling endurance, with the results summarized in Supplementary Note 5 and Note 6, respectively.

Algorithm demonstrations on the MCA platform
Building on the physical convolution capability of the MCA, we implement a range of algorithms, including the STFT, CNNs, and image processing tasks. Devices are specifically designed to accommodate these algorithmic requirements. Details of device design and fabrication are provided in “Methods” and Supplementary Fig. 6. In this demonstration, the raw experimental data from Fig. 2f is used as the convolutional coefficients, while linearized input data, extracted from Fig. 2h and presented in Supplementary Fig. 7, is employed as the input signals.

The STFT is a widely utilized signal processing technique for analyzing non-stationary signals whose frequency content evolves over time. It represents the most prevalent form of the discrete Fourier transform (DFT) applied to segmented time-domain signals and serves as a foundational operation in frequency-domain analysis.

As schematically illustrated in Fig. 3a, the STFT process involves segmenting an input signal into overlapping windows, each of which undergoes a DFT. The DFT of a windowed signal is given by: Xk = e−iπ N k2 \sum_{n=0}^{N-1} (xn \cdot e−iπ N n2)(eiπ(k−n)2), where xn is the nth input signal sample, Xk is the kth Fourier-transformed component, and N is the segment length. By defining auxiliary variables an = xn \cdot e−iπ N n2 and bn = eiπ N n2, the DFT expression can be recast into a convolutional form:

Xk = b*k * \sum_{n=0}^{N-1} an bn−k (5)

Where b*k is the complex conjugate of bk. This reformulation highlights that the DFT computation can be interpreted as a convolution between an and bk−n, enabling its direct implementation using the MCA platform. Specifically, input signals an are mapped to domain lengths (LD), while the convolution kernel coefficients bk−n are mapped to the electrode spacings (WP).

To experimentally demonstrate this capability, we perform a 4-point STFT using a 7-Hall-pad MCA device. The input signals consisting of four domains (LD = a0, a1, a2, a3) are shifted across a kernel of seven Hall electrodes programmed with spacings corresponding to (WP = b3, b2, b1, b0, b−1, b−2, b−3). Each shift operation advances the domain sequence by one unit, and the Fourier-transformed outputs (X0, X1, X2, X3) are obtained by summing the AHE voltages across the corresponding electrode configurations. Additional details regarding the STFT mathematical derivation and device implementation are provided in “Methods” and Supplementary Fig. 8.

Following this 4-point STFT configuration (Fig. 3b), we fabricate a 7-Hall-pad MCA device, shown in Fig. 3c. As test signals, we prepare two synthetic time-varying functions: f(t) = t/200 [cos(4πt) + 1], representing a signal with increasing amplitude, and g(t) = 0.5 − t/200 [cos(2πt) + 1], representing a signal with decreasing amplitude. Both signals are sampled at intervals of 0.25 s.

Figures 3di and 3dii display zoomed-in segments of f(t) and g(t), respectively, highlighting their amplitude variations over time. Figure 3diii shows the superposition of f(t) + g(t), which is segmented and input into the MCA device. A snapshot of the domain segment shifting across the 7-Hall-pad structure during operation is captured in Fig. 3c. After completing the sequential shifting and Hall voltage readout processes, the recorded AHE signals are post-processed (scaled in computer) to construct the STFT result, as shown in Fig. 3div. This result clearly resolves the temporal evolution of the individual frequency components associated with f(t) and g(t).

Finally, as discussed earlier, the fabricated electrode spacings WP are mapped to the convolution kernel. Variations in WP can therefore influence the accuracy of the STFT output. This effect is systematically investigated and discussed in Supplementary Note 7.

Additionally, to demonstrate scalability, we implement an 8-point STFT using a 15-Hall-pad MCA device, as presented in Supplementary Fig. 9. By expanding the number of Hall electrodes, the MCA architecture supports longer segmentation windows and higher-resolution STFT calculations, showcasing the potential for scaling the platform toward more complex signal processing tasks.

CNNs are foundational in computer vision, enabling applications such as object detection, image segmentation, and facial recognition. Their versatility extends across diverse fields, including natural language processing, medical imaging, and strategic decision-making tasks. To improve computational efficiency, CNNs frequently rely on specialized hardware accelerators.

The MCA platform is designed to support this role by accelerating convolutional operations with fixed weights. Unlike hardware platforms aimed at training, our devices specifically target inference tasks where pre-trained convolutional layers remain unchanged. This design aligns naturally with the widespread use of transfer learning in contemporary AI workflows.

In standard AI pipelines, transfer learning involves initializing models with pre-trained weights derived from large, diverse datasets. These pre-trained networks extract generalized features applicable across many domains. Fine-tuning is then performed on smaller, task-specific datasets, typically by freezing the early convolutional layers responsible for basic feature extraction (e.g., edges, textures) and retraining only the later layers to specialize the model. This hierarchical training strategy significantly reduces computational overhead, accelerates deployment, and minimizes the size of required datasets.

For example, in large language models like GPT-derived architectures used for code assistance, fine-tuning typically modifies only a small portion of the network—adding a task-specific head—while the majority of the network remains unchanged. In computer vision, a typical application involves adding a recognition head onto a pre-trained backbone such as MobileNetV2. As documented by Google27, this approach reduces the number of trainable parameters from 2,257,984 to just 1281, cutting training time and energy by over an order of magnitude.

Transfer learning has been shown to consistently outperform training from scratch when working with limited data28,29, and underpins many state-of-the-art models, including Llama30 and BERT31. It is now the dominant paradigm across AI applications.

Our MCA device is ideally suited for accelerating the fixed convolutional layers that dominate deep neural networks in terms of area, energy consumption, and computation time—often accounting for over 90% of network resources27. By offloading these computationally intensive, fixed-weight layers to the MCA platform, overall system performance can be significantly enhanced, reducing the computational footprint, latency, and energy demand compared to traditional CMOS implementations.

For the adaptable, trainable layers toward the end of the network, conventional hardware such as GPUs or application-specific integrated circuits can be employed. This creates a hybrid system architecture that leverages the strengths of both spintronic and CMOS technologies—speed and efficiency from MCA, and flexibility from conventional digital hardware.

To demonstrate the MCA’s effectiveness in accelerating CNNs, we apply the platform to a practical task: recognizing MNIST handwritten digits. The system flow diagram is shown in Fig. 3e, where input images undergo a typical CNN pipeline including convolutional, max pooling, flattening, fully connected, and output layers. Additional algorithmic details are provided in “Methods” and Supplementary Fig. 10a.

In our experimental setup, the pre-trained convolutional layers are physically implemented using the MCA device, while the subsequent layers (pooling, fully connected, classification) are executed in silico. As illustrated in Fig. 3f, the convolutional layer is realized by mapping pixel intensity values to domain lengths (LD) and kernel weights to Hall electrode spacings (WP).

Due to the one-dimensional nature of domain shifting, a 3×3 convolutional kernel must be partitioned into three parallel 1×3 kernels. These are assigned to three separate MCA devices to perform two-dimensional scanning. In Fig. 3f, three MCA devices are shown, each with three pairs of Hall electrodes (marked by gray dots) forming the 1×3 kernel structure. As domains representing pixel values are shifted across the devices, AHE voltages are sequentially read and summed to complete the convolution operation. Additional filters can be appended by cascading MCA devices.

Recognition tests were conducted on 10,000 MNIST handwritten digit samples. An average classification accuracy of 98% was achieved, as summarized in the confusion matrix shown in Fig. 3g. The plot is presented on a logarithmic scale to highlight misclassification rates below 1%. Detailed accuracy results are further provided in Supplementary Fig. 10b.

To further assess the practicality and generalization of the MCA platform, a more advanced image-classification task using the CIFAR-10 dataset was also implemented (Supplementary Note 8). In addition, variations in electrode spacing (WP) and domain length (LD)—which introduces light deviations from ideal linearity—could affect convolution accuracy and, consequently, the overall algorithmic performance. These effects are systematically examined and discussed in Supplementary Note 9.

Convolution is a fundamental operation in image processing, forming the basis for tasks such as edge detection, sharpening, blurring, and averaging. Leveraging the MCA platform’s convolutional capabilities, we demonstrate these key image processing functions experimentally.

For the input, we select the standard 256×256-pixel, 8-bit greyscale ‘Cameraman’ image, shown in the left panel of Fig. 3h. This image is represented as a greyscale pixel matrix, where each pixel has an intensity value between 0 and 255. As an illustration, the right panel of Fig. 3h displays the greyscale intensity profile along a single line cut through the image.

Analogous to the CNN demonstration, each pixel value is mapped to a corresponding domain length (LD) within the MCA device. To perform different convolutional operations, distinct processing kernels are encoded by setting specific spacings between pairs of Hall electrodes (WP).

Figure 3i captures a snapshot during the edge detection experiment. Here, the greyscale values of three adjacent pixels are mapped to three magnetic domains with corresponding LD values. These domains are shifted sequentially across a kernel designed for edge detection, consisting of three Hall electrode pairs representing the coefficients [1, 0, –1]. In this setup, positive coefficients are connected with standard polarity, negative coefficients are connected with reversed polarity, and zero coefficients are left unconnected.

The resulting edge-detected image, generated using the MCA platform, is shown in Fig. 3j. Additional image processing functions, including sharpening, Gaussian blurring, and averaging, are implemented by programming different kernel configurations into the device. The corresponding results are presented in Supplementary Fig. 11.

Toward two-dimensional architectures and benchmarking against CMOS
As discussed previously, our one-dimensional (1D) Hall-based MCA platform supports the majority of convolution operations required for pre-trained AI networks and signal processing tasks. However, in scenarios where dynamic coefficient updates are necessary—such as during AI training—more flexible architectures are desirable.

To address this limitation, we propose a two-dimensional (2D) extension of the MCA platform by integrating crossing arrays of magnetic tunnel junctions (MTJs), resulting in a 2D MTJ-MCA architecture (Fig. 4ai, ii). In this design, convolutional inputs and weights are mapped to domain lengths along the bottom and top magnetic strips, respectively. The procedures for weight programming and independent control of the upper and lower magnetic domains are described in Supplementary Note 10 and Note 11, respectively. As illustrated schematically in Fig. 4aiii, the x- and y-direction magnetic strips contain domains with lengths LD,X and LD,Y, while W denotes the lateral dimension of the junction overlap region. Additional details and analysis of the domain configuration of Fig. 4aiiia are discussed in Supplementary Note 12.

The readout function for a device with N junctions is formulated by considering an x-directed bottom strip overlapped by N y-directed top strips. When a bias voltage V is applied across the MTJs, the total current through the bottom strip is given by:

I(k) = c3 VN + c4 V \sum_{n=1}^{N} W−1 LD,Y[n] W−1 LD,X[n−k] (6)

where c3 and c4 are device-dependent constants, and k denotes the clock cycle corresponding to domain shifting. As shown in Eq. (6), the output current naturally results from a convolution operation, with both the input and kernel coefficients being tunable via domain length modulation. A detailed derivation of this readout mechanism is provided in “Methods”.

We next present a comprehensive benchmarking analysis comparing the MCA platform against standard CMOS technology, using experimental parameters or experimentally derived estimates. The evaluation focuses on three key metrics—area, throughput, and energy consumption—for an 8-bit, 1024-point convolution task, targeting a 28 nm process node.

The results are summarized in Fig. 4b, with detailed calculations provided in the Supplementary Note 13.

The sampling and summation circuits for the MCA were synthesized using a commercial 28 nm process design kit (PDK), and their area and energy consumption were extracted accordingly. Notably, in the MCA architecture, the overall area is dominated by the sampling circuitry (comprising five transistors per cell), accounting for ~70% of the total footprint. For the CMOS benchmark, a full synthesis application-specific integrated circuit (ASIC) targeting an equivalent convolutional operation was performed using the same PDK. Details of the CMOS circuit design and benchmarking methodology are provided in the Supplementary Note 14.

Benchmarking results (Fig. 4b) reveal that the MCA platform offers substantial improvements in both area and throughput compared to CMOS. This advantage arises from the highly compact physical implementation of the shifting and multiply–accumulate (MAC) operations, which would otherwise require hundreds of transistors per unit in CMOS.

On the other hand, as shown in Fig. 4b, the current energy consumption per operation in the 1D Hall-based MCA is slightly higher than that of CMOS, primarily due to the large current densities required to drive high-speed domain wall motion. However, previous studies22 indicate that optimizing material growth and minimizing pinning sites can significantly reduce the required shift current, thereby enhancing the energy efficiency of future 2D MTJ-based designs. Compared with optical systems for physical-convolution computing32,33, the MCA exhibits a comparable level of energy consumption but higher latency, primarily due to the lower speed of domain-wall motion. Nonetheless, its area footprint is orders of magnitude smaller, offering clear advantages for large-scale integration and on-chip deployment. The crosstalk behavior of the MCA in large-scale array configurations is also investigated to assess integration feasibility, as discussed in Supplementary Note 15.

Considering the figure of merit (FOM), defined as:

FOM = Throughput(T) / Area(A) × Energy(E) (FOM = T / AE) (7)

The MCA platform demonstrates a 3–5 orders of magnitude improvement compared to CMOS technology at the same process node, as highlighted in Fig. 4b.

Methods
Thin film deposition and device fabrication
Thin films composed of Ta(5 nm)/Co40Fe40B20(1 nm)/MgO(2 nm)/Ta(2 nm) were deposited onto semi-insulating silicon substrates covered with a 100 nm thermal oxide layer. Deposition was performed at room temperature using both direct current (DC) and radio-frequency (RF) magnetron sputtering in an AJA sputtering system. The base pressure during deposition was maintained below 1×10−8 torr, with an argon working pressure of 3 mtorr. Post-deposition, the films underwent vacuum annealing at 250°C for 30 min to enhance perpendicular magnetic anisotropy (PMA), as confirmed in Supplementary Fig. 2. Exposure to ambient conditions naturally oxidized the top 2 nm Ta layer into TaOx, providing environmental protection. Device patterning was achieved through a combination of photolithography, dry etching, wet etching, and metal evaporation processes. While the overall fabrication flow resembled that of a conventional Hall bar device, modifications were introduced to integrate an Oersted-field generating microwave strip for domain nucleation and a Hall pad–Via structure for precise control of the Hall pad separation distance (WP).

The detailed fabrication sequence is illustrated in Supplementary Fig. 3.

MOKE microscopy characterization
Wide-field Magneto-Optic Kerr Effect (MOKE) imaging was performed using a custom-designed MOKE microscope setup, providing spatial resolution of ~360 nm and temporal resolution of 20 ms. An external magnetic field was generated by a GMW-5201 Helmholtz coil system, powered through a Kepco BOP 5-20D power supply. Initially, the sample was saturated under a strong negative out-of-plane magnetic field (−Hz), and a reference background image was recorded. Subsequent magnetic images were obtained by subtracting this background, enabling clear magnetic domain contrast. To prepare the initial domain configurations used in Fig. 2d, e, the MCA devices were first saturated under a large −Hz. After removing the field, the magnetic layer retained a uniform negative out-of-plane magnetization (−mz). MOKE imaging sequences were then captured during the processes of domain nucleation and subsequent domain wall motion.

Domain nucleation, domain motion, and AHE voltage detection
After initializing the MCA device into a uniform −mz magnetization state, domain nucleation was triggered by sending a current pulse through the Oersted field line, sourced from a Keithley 2636A SourceMeter. The generated +mz domain length (LD) was controllably adjusted by tuning the pulse parameters, including amplitude, polarity, and duration. Following nucleation, domains were displaced to designated locations to reserve space for the creation of additional domains. This domain shifting process was driven by applying a series of current pulses (1 mA) to the Shifting channel using an Agilent 33250A arbitrary waveform generator. Successive domains were similarly created and spaced to align precisely with the intended Hall sensing regions. After forming the desired domain array, all domains were shifted simultaneously into the Hall detection region. AHE measurements were carried out sequentially, corresponding to the convolution operation order, as demonstrated in Fig. 2e. Specifically, the transverse Hall voltage (VAHE) was measured whenever a domain resided within the Hall sensing channel. The typical measurement configuration is present in Supplementary Fig. 2b, with a constant current I(0.1 mA) applied along the device and VAHE monitored across the transverse electrodes.

All experiments were conducted at ambient room temperature.

Analytical derivation of Hall-MCA convolution operation
The MCA device is structured such that the AHE voltage (VH) can be expressed as:

VH = \alpha0 \cdot Mz \cdot I H \cdot WP / W (8)

Here, \alpha0 represents a material-dependent constant, Mz is the net out-of-plane magnetization within the sensing region between a pair of Hall electrodes, IH is the applied current along the +x direction, WP is the separation between the two Hall electrodes, and W is the total device width.

The net magnetization Mz is described by:

Mz = (1 − 2 LD / LP) Ms (9)

where Ms denotes the saturation magnetization, LD is the length of the reversed (−z) magnetic domain, and LP corresponds to the contact length of the Hall electrodes.

Initially, the Hall sensing area is uniformly magnetized along the +z direction. When a reversed domain of length LD enters the region, the net Mz decreases linearly with LD. As \alpha0, Ms, and W are intrinsic material and device constants, they can be consolidated into a single coefficient \alpha for simplicity.

Substituting the expression for Mz into the VH formula yields:

VH = \alpha IH 2LD − LP WP (10)

This result corresponds to Eq. (1) presented in the main text.

Fundamental operating principles of the MCA
The realization of the MCA relies on four fundamental components: (1) Establishment of PMA, ensuring the preferential alignment of magnetization along the z-axis; (2) Fine control over domain length, critical for accurate input encoding; (3) DW displacement driven by SOT, necessary for sequential domain shifting; and (4) Electrical readout of the convolution signal via AHE voltage measurements.

All these elements are implemented in a well-established material system comprising a Heavy Metal/Ferromagnet/Insulator heterostructure—specifically, Ta/CoFeB/MgO—as depicted in Supplementary Fig. 1 and Supplementary Fig. 2.

For (1), PMA is achieved through interfacial effects between the CoFeB and MgO layers36, as verified experimentally (Supplementary Fig. 2).

For (2), domain and DW formation is accomplished through Oersted fields generated by a transverse conducting stripline (Supplementary Fig. 1a). In this schematic, blue and red regions denote +mz and −mz magnetization, respectively, while the white area represents the DW transition zone. By injecting a short current pulse along the +y-axis into the strip, a localized Oersted (B) field (green arrows) is produced, nucleating a −mz domain. The domain length (LD) can be tuned by adjusting the current pulse parameters—with a positive (negative) current increasing (decreasing) LD.

For (3), DW motion is induced by SOTs generated through spin Hall effects9,26 within the Ta underlayer. When a current j flows along the +x-direction (Supplementary Fig. 1b), spin accumulations (σ+y and σ−y) build up at the top and bottom surfaces of the Ta layer, as shown in the right-hand schematic. These spins act as effective z-directed fields on the DW moments m and exert a torque described by:

HZ SOT = m × σ+y (11)

Due to the right-handed DMI15,16,37 at the Ta/CoFeB interface9,15, the DWs possess chiral structures that respond differently to σ+y. The effective fields HZ SOT act oppositely on the two DWs (since the angle between m and σ+y is ±90°), satisfying:

HZ SOT = sin(±90°) · ±z (12)

As a result, SOTs drive both DWs coherently along the +x-direction with velocity V9,15—a mechanism commonly referred to as SOT-driven DW motion.

For (4), the AHE readout leverages the intrinsic properties of ferromagnetic metals such as CoFe and CoFeB. In the Ta/CoFeB/MgO structure, the AHE resistance RAHE is typically around 1 Ω9, as demonstrated in Supplementary Fig. 2. This AHE voltage provides a direct and efficient means of electrically sensing the domain configurations necessary for convolution operations.

Simulation and optimization of the Oersted field channel using COMSOL
To optimize the performance of the gold striplines (Oersted field channels) and reduce energy consumption, a COMSOL Multiphysics simulation study was conducted. The target was to generate an out-of-plane magnetic field of 50 Oe—matching the coercivity of the material—at a distance of 75 nm from the sample boundary, in accordance with device constraints. The study involved tuning three main control parameters: stripline thickness, width, and applied current. By carefully adjusting these variables, we aimed to achieve the required magnetic field strength while minimizing power dissipation. The optimization targeted two wire lengths, l=346 nm and l=75 nm, which reflect practical design constraints (Supplementary Fig. 4a). The optimization process employed the Nelder-Mead algorithm within the Magnetic and Electric Fields module of COMSOL. The objective function was set to minimize the volumetric loss density (expressed in watts). Initial conditions for the optimization were chosen as: wire width w=1 nm, thickness t=1 nm, and starting current i0 = 0.2 mA. Control parameter boundaries were defined between 1 nm and 300 nm for both width and thickness, and between 0.05 mA and 5 mA for current. Upon convergence, the optimal parameters for the 346 nm-long wire were determined to be a thickness of 156 nm, width of 104 nm, and applied current of 3.8 mA, resulting in a total power consumption of less than 7 μW. For the 75 nm-long wire, the optimal configuration was a thickness of 38.5 nm, width of 108 nm, and current of 2.9 mA, with energy dissipation reduced to below 4 μW. The magnetic field spatial distribution and the optimization progression (power loss versus iteration number) for the 346 nm wire are presented in Supplementary Fig. 4b, while corresponding results for the 75 nm case are shown in Supplementary Fig. 4c.

Device design and dimensioning for MCA functions
The MCA device architecture was engineered to support different convolution operations — including Gaussian blurring, image averaging, sharpening, and STFT—as detailed in Supplementary Fig. 6. The starting point of the design involved defining the spacing between adjacent Hall electrodes (WP) according to the intended convolution kernel. For example, in the Gaussian blurring function, the sequence of WP values was set to 3–12–18–12–3 μm, providing an approximation of a Gaussian curve. The Hall electrode contact length (LP) was selected to be either 14 μm or 20 μm, balancing the need for fine domain length control with fabrication feasibility. A Hall pad width (WH) of 6 μm was chosen to maximize successful Via fabrication rates. To maintain reliable photolithographic patterning, Hall pads were positioned 3 μm inward from the magnetic strip edge. Based on these considerations, the overall magnetic strip width (WM) was determined as WM = 18 + 6×2 + 3×2 = 36 μm. For domain nucleation, the Oersted field channel width (WO) was designed at 15 μm. This allows for the formation of a magnetic domain under a 50 Oe coercive field when applying a 200 mA pulse. Further tuning of WO can be performed if higher field magnitudes are required. Similar design strategies were applied to devices optimized for averaging, sharpening, and STFT functionalities. Dimension details for these kernels are summarized in Supplementary Fig. 6.

STFT formulation and realization with MCA devices
The DFT is a mathematical operation that converts a sequence of time-domain samples into a corresponding set of complex-valued frequency-domain coefficients. It can be expressed in a convolution-like form, enabling its hardware implementation via sequential domain shifting in the MCA device.

The DFT is formally defined as:

Xk = \sum_{n=0}^{N-1} xn \cdot e−i2πkn / N (13)

Where xn are the input time-domain samples and Xk are the resulting frequency-domain outputs.

This equation can be algebraically rearranged into a form that resembles a convolution:

Xk = e−iπ N k2 \sum_{n=0}^{N-1} xn \cdot e−iπ N n2 eiπ(k−n)2 (14)

By introducing the substitutions an = xn \cdot e−iπ N n2 and bn = eiπ N n2, the expression becomes:

Xk = b*k * \sum_{n=0}^{N-1} an bn−k (15)

This transformation highlights a convolution structure involving a fixed kernel bk−n. Importantly, “fixed kernel” implies that the coefficients bk−n are independent of the input signal xn and remain unchanged. In the MCA device, this feature is leveraged by encoding these fixed weights through predefined electrode spacings (WP) during fabrication.

Since DFT outputs are complex-valued, the convolution must be separated into real and imaginary components. The input signal, pre-multiplied by the complex phase factor e−iπ N n2, is first decomposed into real and imaginary parts. Each part is then individually mapped to the domain lengths (LD) in separate MCA devices. The real and imaginary parts of the convolution kernel bk−n are similarly mapped to dedicated devices. Convolution operations proceed independently within these MCA devices by sequential domain shifting and AHE readout. After completing the convolution across four MCA devices (two for the input real/imaginary parts and two for the kernel real/imaginary parts), the results are recombined by post-multiplying by b*k. The final calculated values Xk reveal the amplitude and phase information across different frequency components, as depicted in Supplementary Fig. 8.

Implementation of CNN inference using MCA devices
To assess the performance of the MCA-based CNN under varying input and weight precision constraints, we conducted the following experimental procedure: The original MNIST handwritten digit dataset, consisting of 28×28-pixel 8-bit grayscale images, was first quantized according to the specified input precision (e.g., n-bit resolution). Each pixel value was rescaled to the nearest quantization level between 0 and 1 corresponding to the chosen bit depth. A CNN architecture comprising two convolutional layers, two fully connected layers, and two max-pooling layers (shown schematically in Fig. 3e) was trained on the training set using the ADAM optimizer for 10 epochs. Full-precision (floating-point) weights were used during initial training to establish baseline performance on the test set. For network quantization, each layer’s weights were mapped into discrete steps determined by the weight precision constraint: the 1st and 99th percentile values of the trained weights were identified, and the range between them was divided evenly according to the number of quantization steps. Each original weight was then projected onto its closest discrete value, and the resulting quantized model was evaluated on the test set to determine the ideal n-bit weight accuracy. To simulate hardware-based inference, we constructed a model where each convolutional operation was replaced by experimental data collected from the MCA devices. The filter (kernel) coefficients were taken from the experimental measurements shown in Fig. 2f. The inputs were mapped using the linearized AHE voltage responses (VAHE) obtained in Supplementary Fig. 7 to account for real device behavior. The full evaluation workflow for this MCA-based CNN implementation is summarized in the flowchart in Supplementary Fig. 10a. The final recognition accuracy results are summarized in Supplementary Fig. 10b.

Derivation of convolution operation for MTJ-based MCA devices
In a single MTJ unit, the parallel (P) and antiparallel (AP) alignments of the magnetic layers yield tunneling resistances of R and 2R, respectively, due to the tunneling magnetoresistance (TMR) effect. When two magnetic domains, with respective lengths LD,X and LD,Y, overlap at the junction area (of total width W) as depicted in Fig. 4a(iii), the structure can be modeled as four parallel-connected sub-junctions with effective areas:

• A1 = LD,X × LD,Y (P) (P-aligned region)
• A2 = (W − LD,X) × LD,Y (AP) (AP-aligned region)
• A3 = LD,X × (W − LD,Y) (AP) (AP-aligned region)
• A4 = (W − LD,X) × (W − LD,Y) (P) (P-aligned region)

The overall conductance (G) of the junction can thus be expressed as the sum of the conductances of these four regions:

G = G1 + G2 + G3 + G4 = 1/RW2 (A1 + A4) + 1/2RW2 (A2 + A3) (16)

Substituting the expressions for the areas and simplifying yields:

G = 1/RW2 (W−LD,X W−LD,Y + 3/4 W2) (17)

This can be further written as:

G = c3 + c4 W−LD,X W−LD,Y (18)

where c3 and c4 are constants that depend on the device parameters.

To extend this model to a full device containing N MTJ junctions, consider a structure where a horizontal (x-direction) bottom magnetic strip overlaps with N vertical (y-direction) top strips. Applying a bias voltage V across the device results in a total current Ik along the bottom strip, which is the cumulative contribution from each junction. The current readout for such an N-junction device is formulated as:

I(k) = c3 VN + c4 V \sum_{n=1}^{N} W−1 LD,Y[n] W−1 LD,X[n−k] (19)

This corresponds to Eq. (6) presented in the Main Text.

Data availability
All data needed to evaluate the conclusions in the paper are available within the article and its Supplementary Information files. All data generated during the current study are available from the corresponding author upon request.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "In this paper, Dai et al designed a magnetic convolutional accelerator (MCA) device based on current-driven domain-wall motion. They fabricated several μm-scale MCA devices and demonstrated the basic performance of domain-wall sensing and convolution computing. During the operation, the information is encoded in domain patterns and read via Hall voltages with various geometric parameters. The manuscript is generally well written and the concept of convolutional computing using DW motion is interesting. However, I have several concerns regarding the feasibility of such domain-wall MCA devices, which must be addressed before the manuscript can be considered for Nature Communications.:\n1. The performance of current-induced domain-wall displacement seems too idealistic. The authors encode the input signal in the domain length. But the domains are prone to getting deformed due to the presence of pinning sites. Especially, the Hall channel may act as the geometric pinning sites. Since input variations can affect the functionalities, the domain-wall pinning may significantly degrade the performance of MCA devices. The authors should present the stability test of domain size when transferring through the racetrack channel and estimate the influence of domain-wall pinning in downscaled devices. They should also provide a MOKE video to show the smooth domain-wall movement in MCA devices.\n2. Though the velocity of current-driven domain-wall motion can be fast, the detection of Hall voltage is through DC measurement in this work, which slows down the operation speed. The author should demonstrate a fast way to read the Hall signal to match the fast domain-wall velocity. In addition, how is the domain-wall velocity in this work? They should measure the domain-wall velocity as a function of current density.\nBesides, some other issues need to be addressed:\n1. The device used by the authors is based on the ferromagnet CoFeB. The velocity of ferromagnetic DW motion is usually limited to a few hundred meters per second. The authors should provide more experimental evidence to support the expected operating speed of THz. Moreover, the size of the domain wall in ferromagnets is usually tens of nanometers. The authors should provide more evidence to support the expected domain size of 1 nm.\n2. They applied a high current to displace the domain wall, which may induce significant Joule heating, particularly when operating at a high frequency. The authors should consider this in their modelling and estimate the device temperature due to Joule heating.\n3. There have been several reports using physical systems for convolution computing. The author should compare with other systems and clarify the advantages of MCA devices.\n4. The convolutional algorithm relies on the fact that the Hall voltage is linear with respect to the length of domains, whereas there are nonlinear deviations in the real devices (Fig. 2f and 2h). The author should analyze how this affects the algorithm.\n5. The authors designed several MCA devices for different kernel functionalities. What is the principle for designing the MCA devices? How does the influence of the Hall probe number?\n6. It is not clear to me how they perform the handwritten digit recognition and image edge detection tasks. Which results were performed in physical devices and which results were performed in computers? They should provide more details, such as how to encode the grey scale value into domain length, how to choose the current density and how to correct the offset Hall voltage.", "reviewer_2": "Authors proposed a nice idea having the weights mapped as spacing between electrode pairs during fabrication, which mean weights are fixed at that stage. The inputs, however are applied as domain lengths that can be dynamically controlled and changed at runtime. However, only this part of the device has been experimentally validated. At this stage, the work has multiple practical issues, which are not resolved or discussed. Furthermore, there are theoretical ideas which are not validated in depth, such as, 2D version where both the weights and inputs can be dynamically programmed.\nThe critical points are highlighted below.\nThe manuscript acknowledges that the current 1D Hall-based MCA requires relatively high current densities to drive domain wall motion, leading to energy per operation that is slightly higher than CMOS. While the authors suggest this can be mitigated by material optimization, this is left as future work.\nThe device relies on precise domain nucleation, length control, and synchronized wall motion. The paper shows impressive lab-scale control but does not address large-array scaling. Scalability and uniformity are critical for any practical accelerator.\nWhile a 2D MTJ-MCA extension is proposed, it is theoretical. Can the authors clarify whether any test structures for the 2D MTJ-MCA have been fabricated?\nAHE voltage readout relies on linear mapping of domain length and electrode spacing, but fabrication imperfections introduce nonlinearity. Readout fidelity is fundamental to inference accuracy. Can the authors provide quantitative measurements of deviation from ideal linearity? How does readout noise impact classification accuracy in their CNN demonstration?\nThe device requires precise deposition of Ta/CoFeB/MgO stacks with PMA, fine Hall electrode spacing, and integration of Oersted nucleation lines. Scalable production is necessary for any hardware accelerator. What is the measured yield of fabricated devices? How sensitive is performance to lithographic variations?\nWhile small-scale devices are demonstrated, large-scale arrays needed for real AI workloads are not. Demonstrating a few cells is valuable, but deployment requires large arrays. How does domain wall synchronization degrade over distance? What strategies exist to handle crosstalk or variation in large arrays?\nCan the authors clarify what CMOS baseline design was used? Have they benchmarked against state-of-the-art low-power MAC implementations?\nThe main application demonstrated is MNIST digit classification (28×28 images). A simple dataset can overstate practical readiness.\nThe 2D extension is presented analytically, but no experimental validation is shown. Proposing a 2D solution is important, but feasibility is unclear. What is the plan for fabricating test 2D MTJ cells? How will the authors address alignment, yield, and TMR variation across large junction arrays? What is the estimated energy/area/throughput of such 2D designs versus 1D Hall MCA?\nAny practical use will require integration with CMOS for control, ADC/DAC, and post-processing. Have the authors analyzed the latency and energy of these conversions? How does this impact the claimed system-level advantage?\nReliability is critical for deployment. High-current pulses may cause electromigration or heating. Have the authors measured temperature rise during operation? What is the estimated lifetime under continuous cycling? Are there mitigation strategies (e.g., duty cycling, material changes)?", "reviewer_3": "Dai et al present a spintronic convolutional computing platform that exploits DW motion to perform both computation and data storage, realized through Magnetic Convolutional Accelerator (MCA). They demonstrate a concrete advance toward the vision of a general-purpose computing platform or full CIM realization, enabling applications such as short-time Fourier transforms, convolutional neural networks, and image processing. The demonstrated MCA pioneered in convolutional acceleration while simultaneously integrating memory and computation through spintronic mechanisms. Realization of data processing tasks rely on analogies between domain shifting and sliding-window operations, which offers exceptional scalability, energy efficiency, operation speeds and nonvolatility. I recommend publication if authors can address the following concerns.\n1. Is the 1D MCA convolution kernel multiplication and Fourier transform implemented through peripheral circuits? How is it realized?\n2. The accumulated errors during multiple domain wall movements were not addressed. Such errors pose a significant challenge in physical hardware implementations of multiply-accumulate (MAC) operations.\n3. In a 2D MTJ-based MCA architecture, are the magnetic domain regions in the strips used as convolution kernel coefficients continuously generated in a certain time sequence, or are they fixed within the MTJ region? If they are generated dynamically, how is the simultaneous appearance of magnetic domains in the upper and lower strips within the MTJ region controlled? If they are fixed, how can the corresponding magnetic domain widths be modified for different cases? Does the read current used to measure the MTJ magnetoresistance have any effect on the magnetization direction of the magnetic domains?\n4. The fixed-weight approach is only suitable for inference, not for the computationally intensive and diverse training phase. Additionally, the 2D architecture lacks experimental validation.\n5. ln line 104 and 105, the authors depict ‘I_H is the applied current flowing along the +x axis, L_D is the domain length aligned along the –z direction’. It seems not the case as illustrated in Fig. 1b.\n6. In Equation 1, the length of the domain wall is not taken into consideration. Will the DW length influence the final convolutional result?\n7. Since the domain motion is driven by SOT of the underlying heavy metal，will the external magnetic field used for AHE signal read out affect the domain motion?\n8. In Fig. 2f, the y-intercept of V_AHE versus W_P seems not zero (about 0.5 mV). What is the reason and can it be adjusted or eliminated?\n9. In Fig. 2h, the legend of the picture is incomplete with the absence of corresponding symbol or color.\n10. In Fig. 3c, the distinction of fabricated W_P is not evident. Will it influence the mapping to convolutional kernel?\n11. In Fig. 4aiii, the red, blue and purple squares can coexist simultaneously in the crossing area or is just a phenological illustration of all possible cases?\n12. As claimed in line 362 and 363, energy consumption per operation in the 1D Hall-based MCA is primarily due to the large current densities required to drive high-speed domain wall motion. Will adoption of magnetic solitons like skyrmions or driving method like spin wave in insulators facilitate reduction of energy consumption?"}, "author_response": "We sincerely thank the reviewer for the careful evaluation and constructive feedback, which have greatly improved the rigor and clarity of our manuscript. In response to the reviewer’s comments, we have conducted additional experiments, micromagnetic simulations, and algorithmic validations to strengthen the technical foundation and address the key feasibility concerns. These new results further confirm the robustness and practicality of the proposed MCA concept. We have extensively revised the Main Text and Supplementary Materials to integrate these new results and enhance the overall clarity and coherence of the manuscript.\nDetailed point-by-point responses are provided below:\n1. The performance of current-induced domain-wall displacement seems too idealistic. The authors encode the input signal in the domain length. But the domains are prone to getting deformed due to the presence of pinning sites. Especially, the Hall channel may act as the geometric pinning sites. Since input variations can affect the functionalities, the domain-wall pinning may significantly degrade the performance of MCA devices. The authors should present the stability test of domain size when transferring through the racetrack channel and estimate the influence of domain-wall pinning in downscaled devices. They should also provide a MOKE video to show the smooth domain-wall movement in MCA devices.\nReply:\nWe thank the reviewer for this insightful comment. Our response is divided into two sections:\n1. Stability test of domain size during domain transfer and MOKE video of smooth motion\n2. Influence of domain-wall pinning in downscaled devices\nStability test of domain size during domain transfer and MOKE video of smooth motion\n(a) Quantification of domain size\nTo examine domain-size stability during propagation, we used MOKE microscopy to directly quantify the domain length as the domains moved along the racetrack channel. The domain size is defined as length × width; since the width is fixed by the channel geometry, only the domain length can vary. Thus, we focused on analyzing variations in domain length during transfer.\n1 | Pa ge\nWe experimentally prepared two representative cases: a wide domain and a narrow domain. The results are shown in Fig. R1. For wide-domain propagation, the measured domain lengths exhibit a standard deviation of 0.15 µm (1.9%), and for narrow domains, 0.10 µm (2.1%). These results confirm the high stability of domain-wall motion.\nFig. R1 | Domain size stability test. (a), Wide (Top) and narrow (Bottom) domain propagation across MCA device. (b), Domain length vs. Travel Distance.\nRevisions:\nThis section is added into the Supplementary Fig. S3, highlighted in yellow.\nA description is added into the Main Text: From Line 188 to 191, highlighted in yellow.\n(b) MOKE video of smooth movement\nThe MOKE video is provided in the Supplementary Data file. It shows smooth domain propagation across the MCA device, with minimal influence from the Hall channels or other pinning sites.\nWe note that slight shape distortions occur during motion; however, the net domain area (size) remains nearly conserved. As a result, the encoded input value remains stable with only minor variations. These small variations have a negligible impact on the AI inference performance — the system still achieves 98.94% accuracy in handwritten digit recognition. A detailed analysis of this aspect is provided in Comment 4.\nInfluence of domain-wall pinning in downscaled devices\nWe performed additional micromagnetic simulations on devices with dimensions of 256 × 64 × 1 nm³ and 1024 × 256 × 1 nm³ (Fig. R2ai). Following established methods [1,2], pinning was modeled by introducing grains, as shown in Fig. R2aii. The grain size and associated material parameters—including perpendicular magnetic anisotropy, saturation magnetization, and 2 | Pa ge\nDzyaloshinskii–Moriya interaction—were assigned Gaussian distributions to emulate realistic disorder.\nWe then examined SOT-driven domain-wall motion under varying current densities. The influence of pinning is reflected in the velocity–current density (v–J) characteristics (Fig. R2b). In both device sizes, we observe depinning and creep regimes—hallmarks of pinning-limited motion. The smaller device exhibits a higher depinning threshold current, indicating stronger pinning effects due to the reduced dimensions. Once the depinning transition is surpassed, the motion enters the flow regime, where the dynamics become largely independent of pinning [3]. This flow regime represents the desirable operational state for domain-wall motion devices.\nIn conclusion, device downscaling increases the required current density to achieve a given domain-wall velocity.\nFig. R2 | Influence of domain-wall pinning in downscaled devices. (ai), Domain wall motion device. Black: -Mz, White: +Mz, Red: Domain Wall region. (aii), The device is divided into grains with Gaussian distributed size and material properties. Different color represents different perpendicular magnetic anisotropy values. (b), Velocity vs. Current Density plot.\nReference\n[1] Moretti, S., Voto, M. and Martinez, E., 2017. Dynamical depinning of chiral domain walls. Physical Review B, 96(5), p.054433.\n[2] Herranen, T. and Laurson, L., 2019. Barkhausen noise from precessional domain wall motion. Physical review letters, 122(11), p.117205.\n[3] Metaxas, P.J., Jamet, J.P., Mougin, A., Cormier, M., Ferré, J., Baltz, V., Rodmacq, B., Dieny, B. and Stamps, R.L., 2007. Creep and Flow Regimes of Magnetic Domain-Wall Motion in Ultrathin Pt/Co/Pt Films with Perpendicular Anisotropy. Physical review letters, 99(21), p.217208.\nRevisions:\nThis section is added into the Supplementary Fig. S4.\nA description is added into the Main Text: From Line 191 to 192.\n3 | Pa ge\n2. Though the velocity of current-driven domain-wall motion can be fast, the detection of Hall voltage is through DC measurement in this work, which slows down the operation speed. The author should demonstrate a fast way to read the Hall signal to match the fast domain-wall velocity. In addition, how is the domain-wall velocity in this work? They should measure the domain-wall velocity as a function of current density.\nReply:\nWe thank the reviewer for this valuable suggestion. We have developed a fast Hall measurement technique and experimentally determined the domain-wall velocity.\nIn our setup, the Hall voltage is recorded using a high-speed oscilloscope with a detection bandwidth in the MHz range, allowing real-time tracking of sub-10 m/s domain-wall motion. For higher velocities (on the order of hundreds of m/s), GHz-level detection would be required, which can be achieved by integrating a high-frequency detection circuit, as demonstrated in Reference [1]. Due to time constraints, this GHz-range implementation was not pursued in the current study but remains an extension of our setup.\nThe measurement principle is detailed as follows. It relies on the linear dependence of the Hall voltage ( ) on the domain length ( ) within the Hall channel. As illustrated in Fig. R3a, is expressed as:\n𝑉𝑉 𝐿𝐿𝐷𝐷 𝑉𝑉\n𝐿𝐿𝐷𝐷\n𝑉𝑉 = 𝑉𝑉𝐴𝐴𝐴𝐴𝐴𝐴(2 −1) (1)\nwhere is the Hall channel length, and is\n𝐿𝐿\nt𝑃𝑃he saturated anomalous Hall effect (AHE)\nvoltage.\n𝐿𝐿𝑃𝑃 𝑉𝑉𝐴𝐴𝐴𝐴𝐴𝐴\nWhen a current drives the domain wall, evolves with time as , giving:\n𝐿𝐿𝐷𝐷 𝐿𝐿𝐷𝐷 = 𝑣𝑣𝐷𝐷𝐷𝐷 ×𝑡𝑡\n𝑣𝑣𝐷𝐷𝐷𝐷 ∙𝑡𝑡\n𝑉𝑉 = 𝑉𝑉𝐴𝐴𝐴𝐴𝐴𝐴(2 −1) (2)\nHence, the domain-wall velocity ( ) can be extra\n𝐿𝐿\nc𝑃𝑃ted from the slope of the curve.\nUsing this method, we measured\n𝑣𝑣\nth𝐷𝐷e𝐷𝐷 domain-wall velocity in our MCA devic\n𝑉𝑉\ne\n−\n(F\n𝑡𝑡\nig. R3b). The\nreal-time Hall Voltage vs. Time curve is shown in Fig. R3c (right Y-axis), and the corresponding domain length ( ) derived from Eq. (1) is plotted on the left Y-axis. Linear fitting of\nyields a slope of 0.0625 m/s, representing the domain-wall velocity. The dependence of velocity\non current densit𝐿𝐿y 𝐷𝐷 is summarized in Fig. R3d. 𝐿𝐿𝐷𝐷 −𝑡𝑡\nReference\n[1] Sala, G., Krizakova, V., Grimaldi, E. et al. Real-time Hall-effect detection of current-induced magnetization dynamics in ferrimagnets. Nat Commun 12, 656 (2021).\nRevisions:\nThis section is added into the Supplementary Fig. S1.\nA description is added into the Main Text: From Line 179 to 181.\n4 | Pa ge\nFig. R3 | Domain wall motion speed measurement. (a), Blue rectangle represents the domain, red the + domain, and grey the Hall channel. : Hall channel length. : Length of the domain inside the Hall channel. A current is applied to drive the domain wall mo−tio𝑀𝑀n 𝑧𝑧 . The voltage of t𝑀𝑀he 𝑧𝑧 Hall channel is measured in real tim𝐿𝐿e 𝑃𝑃 . Top left picture illustr𝐿𝐿a 𝐷𝐷 tes the ideal\nVolt−ag𝑀𝑀e 𝑧𝑧 vs. Time plot for the domain wall motion. (b𝑗𝑗), Current-driven domain wall motion in the\nMCA device𝑉𝑉. Horizontal rectangle is the magnetic strip. Black color is the domain, and\ngrey the domain. Pairs of vertical strips are Hall channels. (c), and Hall Voltage vs. Time\nplot measured in the rightmost Hall channel. The velocity is obtained by l−in𝑀𝑀ea 𝑧𝑧 r fitting. (d),\nDomain-+w𝑀𝑀all 𝑧𝑧 velocity as a function of current density. 𝐿𝐿𝐷𝐷\nBesides, some other issues need to be addressed:\n1. The device used by the authors is based on the ferromagnet CoFeB. The velocity of ferromagnetic DW motion is usually limited to a few hundred meters per second. The authors should provide more experimental evidence to support the expected operating speed of THz. Moreover, the size of the domain wall in ferromagnets is usually tens of nanometers. The authors should provide more evidence to support the expected domain size of 1 nm.\nReply:\nWe thank the reviewer for raising this important point and apologize for the lack of clarity in our original description. We have revised the manuscript to explicitly state that the THz operation\n5 | Pa ge\nspeed and fast domain-wall motion refer to ferrimagnetic systems, not the CoFeB-based ferromagnetic device used in this work. In addition, we clarified that the domain size discussed in the manuscript is sub-10 nm, rather than 1 nm, and is achievable in systems with large Dzyaloshinskii–Moriya interaction (DMI).\nThe revisions are shown below for your review; related references are also updated.\nFrom Line 79 to 85 of the Main Text:\nThe system performance can be further enhanced by selecting alternative material systems. For example, systems with large Dzyaloshinskii–Moriya interaction offer exceptional scalability (domain sizes down to sub-10 nm21); low-roughness systems provide significantly higher energy efficiency (domain-wall motion energy ~27 aJ22); and heavy-metal/ferrimagnet systems enable much higher operation speeds (domain-wall velocities exceeding 1000 m/s23 and dynamic frequencies reaching the THz regime24). Importantly, all these systems retain the key advantage of nonvolatility25.\nFrom Line 427 to 430 of the Main Text:\nFurthermore, leveraging diverse material systems could enable scaling domain sizes down to sub-10 nm21, maintaining high on–off ratios34, and boosting operational speeds up to ~1 THz24. Pinning optimization could substantially reduce the domain wall driving energy to ~27 aJ22.\nTHz speed\nFerrimagnet exhibit THz-range dynamics. Several experimental studies are shown below:\nMaterial Switching Speed Reference\nGdFeCo 1.5 picosecond [1]\nPt/Co/Gd 100 femtosecond [2]\nMn\nx\nGa 2 picosecond [3]\nIn these systems, typical domain-wall motion velocities exceed 1000 m/s, as summarized by experimental results below:\nMaterial Max Speed Driving Method Reference\nGdFeCo 1500 m/s Magnetic field [4]\nPt/GdFeCo 1300 m/s Spin-orbit torque [5]\nPt/BiYIG Over 4300 m/s Spin-orbit torque [6]\nThe Pt/GdFeCo system can serve as an alternative to our Ta/CoFeB/MgO structure, as it provides a large anomalous Hall signal (Convolution Kernel and Reading) [7,8], supports perpendicular multidomain states (Convolution Input), and enables spin–orbit-torque-driven domain-wall motion (Convolution Shifting) [5], fulfilling the essential requirements for convolution operation. Therefore, in the revised manuscript, we describe this as an alternative system.\nSub-10 nm domain size\nSystems with large DMI can support small domain sizes. As shown in Fig. R4 (adapted from Reference [3]), the combined domain and domain-wall region (circled in red) measures\n6 | Pa ge\napproximately 5 × 2 nm². Accordingly, we have revised the manuscript to clarify that the domain size is sub-10 nm, rather than 1 nm.\nThis system, consisting of a Pd/Fe bilayer on an Ir(111) single crystal, can also serve as an alternative to our Ta/CoFeB/MgO structure, as both fulfill the essential requirements for convolution operation. Therefore, in the revised manuscript, we refer to this as an alternative system.\n[FIGURE REDACTED]\nFig. R4 | Sub-10 nm domain. Spin-polarized scanning tunneling microscopy image of a Pd/Fe island on Ir(111) showing the multi-domain state. Differential conductance (dI/dU) map gives the magnetic contrast of the out-of-plane ( ) direction. Figures adapted from Reference [9].\n𝑧𝑧\nReference\n1. Radu, I., Vahaplar, K., Stamm, C., Kachel, T., Pontius, N., Dürr, H.A., Ostler, T.A., Barker, J., Evans, R.F.L., Chantrell, R.W. and Tsukamoto, A., 2011. Transient ferromagnetic-like state mediating ultrafast reversal of antiferromagnetically coupled spins. Nature, 472(7342), pp.205-208.\n2. Lalieu, M.L.M., Peeters, M.J.G., Haenen, S.R.R., Lavrijsen, R. and Koopmans, B., 2017. Deterministic all-optical switching of synthetic ferrimagnets using single femtosecond laser pulses. Physical review B, 96(22), p.220411.\n3. Banerjee, C., Teichert, N., Siewierska, K.E., Gercsi, Z., Atcheson, G.Y.P., Stamenov, P., Rode, K., Coey, J.M.D. and Besbas, J., 2020. Single pulse all-optical toggle switching of magnetization without gadolinium in the ferrimagnet Mn2RuxGa. Nature communications, 11(1), p.4444.\n4. Kim, Kab-Jin, et al. \"Fast domain wall motion in the vicinity of the angular momentum compensation temperature of ferrimagnets.\" Nature materials 16.12 (2017): 1187-1192.\n5. Caretta, Lucas, et al. \"Fast current-driven domain walls and small skyrmions in a compensated ferrimagnet.\" Nature nanotechnology 13.12 (2018): 1154-1160.\n6. Caretta, L., Oh, S.H., Fakhrul, T., Lee, D.K., Lee, B.H., Kim, S.K., Ross, C.A., Lee, K.J. and Beach, G.S., 2020. Relativistic kinematics of a magnetic soliton. Science, 370(6523), pp.1438-1442.\n7. Roschewsky, N., Matsumura, T., Cheema, S., Hellman, F., Kato, T., Iwata, S. and Salahuddin, S., 2016. Spin-orbit torques in ferrimagnetic GdFeCo alloys. Applied Physics Letters, 109(11).\n8. Seung Ham, W., Kim, S., Kim, D.H., Kim, K.J., Okuno, T., Yoshikawa, H., Tsukamoto, A., Moriyama, T. and Ono, T., 2017. Temperature dependence of spin-orbit effective fields in Pt/GdFeCo bilayers. Applied Physics Letters, 110(24).\n9. Spethmann, J., Vedmedenko, E.Y., Wiesendanger, R., Kubetzka, A. and von Bergmann, K., 2022. Zero-field skyrmionic states and in-field edge-skyrmions induced by boundary tuning. Communications Physics, 5(1), p.19.\n10. Romming, N., Kubetzka, A., Hanneken, C., von Bergmann, K. and Wiesendanger, R., 2015. Field-dependent size and shape of single magnetic skyrmions. Physical review letters, 114(17), p.177203.\n7 | Pa ge\n2. They applied a high current to displace the domain wall, which may induce significant Joule heating, particularly when operating at a high frequency. The authors should consider this in their modelling and estimate the device temperature due to Joule heating.\nReply:\nWe thank the reviewer for this valuable suggestion. We performed additional experiments to characterize the heating effect.\nFirst, we measured the Rₓₓ–T curve (device longitudinal resistance vs. temperature) for the same devices used in the manuscript. The setup is shown in Fig. R5a. A 1 μA reading current (chosen to minimize self-heating) was applied to the current-shifting channel, and the voltage was measured across the two Hall channels using the standard four-probe method. The resulting Rₓₓ–T curve (Fig. R5b) shows a resistance of 349.72 Ω at 300 K with a slope of –0.069 Ω/K, which serves as our calibration reference. The temperature rise (ΔT) associated with Joule heating during domain shifting can be obtained from the measured change in longitudinal resistance (ΔRₓₓ) using:\n1K\nTo quantify th∆e𝑇𝑇 he=at−ing0. 0e6f9fΩec∆t,𝑅𝑅 w𝑥𝑥. 𝑥𝑥e applied DC currents ranging from 1 μA to 1 mA and measured the equilibrium Rₓₓ (Fig. R5c). For a 1 mA current—the shifting current used in the manuscript—we obtain:\n1K 1K\nThis indicates that the device temperature increases from 300 K to approximately 320 K\n∆𝑇𝑇 = 0.069Ω∆𝑅𝑅𝑥𝑥𝑥𝑥 → ∆𝑇𝑇 = −0.069Ω×(348.33Ω−349.72Ω) ≈ 20 𝐾𝐾.\nduring 1mA DC current application.\nA temperature rise of ~20 K is modest in magnetic device applications and is unlikely to cause irreversible changes in magnetic properties. Larger temperature change is commonly observed in spin-orbit torque and domain-wall motion studies, without performance degradation.\nMoreover, in practical operation, the device is driven by pulse with a 50% duty cycle (or lower), which further reduces the effective heating. Therefore, Joule heating is not expected to notably affect the reliability or reproducibility of our device.\nRevisions:\nThis section is added into the Supplementary Fig. S2.\nA description is added into the Main Text: From Line 179 to 181.\n8 | Pa ge\nFig. R5 | Heating effect during Shifting operation. (a), Measurement setup. (b), vs. curve. (c), as a function of DC current amplitude. Each current is applied for 4 hours, and measurements are performed at room temperature. 𝑅𝑅𝑥𝑥𝑥𝑥 𝑇𝑇\n𝑅𝑅𝑥𝑥𝑥𝑥\n3. There have been several reports using physical systems for convolution computing. The author should compare with other systems and clarify the advantages of MCA devices.\nReply:\nWe thank the reviewer for this valuable question. We identify the multiply-and-accumulate (MAC) function as the fundamental operation in physical convolution computing. Based on this, we conducted a literature survey and identified relevant optical implementations for benchmarking. The comparative results are summarized below:\nBenchmarks Our Device Ref. [1] Ref. [2]\nEnergy 4.75fJ to 1.01pJ per MAC 0.53pJ per MAC 25fJ per MAC\nLatency 4.03ns 1ns 0.25ps\nArea 133um2 to 103um2 1cm2 1mm2\nBenchmarking energies are per MAC operation. Accordingly, we used the values from Main Text Fig. 4b (4.86pJ and 1.03nJ) and divided them by 1024, as they are for 1024-point convolution.\nCompared with Refs. [1,2], our device exhibits comparable energy efficiency and higher latency but offers a dramatically smaller area footprint, which is critical for large-scale on-chip integration.\nIt is also important to note that the estimations of photonic convolution systems (Refs. [1,2]) are typically based on device-level metrics and do not include system-level overheads such as optical-to-electrical conversion via photodiodes, which introduce additional latency and energy consumption.\nIn contrast, our benchmarking accounts for the energy/latency/area cost from all peripheral and interfacing components, including CMOS integration for control, ADCs, and post-processing. Specifically, we include the contributions from voltage drivers, switching capacitors, ADCs, and both electric–magnetic and magnetic–electric conversion lines, providing a more comprehensive and realistic estimate of practical system performance. More details can be found in Comment 10 from Reviewer 2.\nAt present, we have identified only these two representative physical convolution studies. We remain open to benchmarking against any other existing physical convolution systems if further comparisons are requested.\nReference\n[1] Amiri, S. and Miri, M., 2025. All-optical convolutional neural network based on phase change materials in silicon photonics platform. Scientific Reports, 15(1), p.22055.\n9 | Pa ge\n[2] Fan, L., Wang, K., Wang, H., Dutt, A. and Fan, S., 2023. Experimental realization of convolution processing in photonic synthetic frequency dimensions. Science Advances, 9(32), p.eadi4956.\nRevisions:\nA discussion is added in the Main Text from Line 398 to 401; the references are also updated:\nCompared with optical systems for physical-convolution computing32,33, the MCA exhibits a comparable level of energy consumption but higher latency, primarily due to the lower speed of domain-wall motion. Nonetheless, its area footprint is orders of magnitude smaller, offering clear advantages for large-scale integration and on-chip deployment.\n4. The convolutional algorithm relies on the fact that the Hall voltage is linear with respect to the length of domains, whereas there are nonlinear deviations in the real devices (Fig. 2f and 2h). The author should analyze how this affects the algorithm.\nReply:\nWe thank the reviewer for raising the important question regarding the effect of nonlinearity on the convolution algorithm. To address this, we use handwritten digit recognition as a representative example and perform experiments using the device’s raw data that inherently include the nonlinear deviations. The response is divided into two parts:\n1. Nonlinear deviations from experiment\n2. Algorithm performance with nonlinear deviations included\nNonlinear deviations from experiment\nIn our experimental setup, the nonlinear deviations mainly come from two sources: (1) variations in the domain length (input variation) and (2) variations in the Hall pad width (weight variation).\nThe nonlinear deviations of these two factors are presented in Main Text Figs. 2f and 2h, and reproduced in Fig. R6 for reference. Quantitatively, the average deviation in Hall pad width is approximately 7%, while the variation in domain length is about 2%.\n10 | Pa ge\nFig. R6 | Main Text Fig. 2f & 2h. Left figure: Fig. 2f, weight variation. Right figure: Fig. 2h, input variation.\nAlgorithm performance with nonlinear deviations included\n(a) Input variation\nWe compared the input data using the raw experimental results from Fig. 2h with the ideal case.\nAs shown in Fig. R7, the handwritten digit datasets with and without domain-length deviations are visually indistinguishable, as the experimental variation in domain length is only about 2%. This small deviation preserves the fundamental image features necessary for accurate handwritten-digit recognition. Consequently, the recognition accuracy remains 98.94%, demonstrating that input nonlinearity has a negligible effect on the algorithm’s performance.\n11 | Pa ge\nFig. R7 | Input with and without deviation. Left: MNIST image without incorporating domain variation. Right: MNIST image with domain length variation. Both images show a clear digit shape and the difference is negligible.\n(b) Weight variation\nIn the original manuscript, we already accounted for variations in the weights by directly using the raw V readouts from different Hall channels as the weight values.\nAHE\nAs discussed in the manuscript, the training process was performed in software, whereas the MCA device is designed for inference with fixed weights. Accordingly, the kernel values derived from the training results are approximated using the nearest experimental V values, as\nAHE\nillustrated below:\nIdeal convolution kernel (training):\n0.1399 -0.289 0.172\n0.489 0.251 -0.521\n0.2173 -0.299 -0.452\nRaw V approximation (experiment):\nAHE\n0.1400 -0.271 0.184\n0.490 0.239 -0.524\n0.2208 -0.305 -0.478\nWe then performed inference using both experimental input and weight variations (raw V\nAHE\nvalues incorporating domain-length and Hall-pad deviations). The resulting recognition accuracy remains high at 98.80%, confirming that the observed nonlinearities do not significantly impact the algorithm’s performance.\nRevisions:\nThis section is added into the Supplementary Fig. S10.\nA description is added into the Main Text: From Line 327 to 330.\n5. The authors designed several MCA devices for different kernel functionalities. What is the principle for designing the MCA devices? How does the influence of the Hall probe number?\nReply:\nWe thank the reviewer for asking about the design principle of the MCA devices.\nThe design of the MCA device is fundamentally based on the convolution operation. Any functionality that can be expressed by a convolution kernel can, in principle, be realized through an MCA by tailoring the device geometry accordingly. In this framework, the convolution input is encoded by the domain lengths, while the kernel is defined by the spacing (Wₚ) and number of the Hall probes, which determine the convolution weights.\n12 | Pa ge\nFor example, in the case of a Gaussian blurring kernel commonly used in image processing, the kernel coefficients follow a Gaussian distribution. We translate this distribution into Hall-pad spacing, using a sequence of Wₚ = 3–12–18–12–3 µm, which approximates the Gaussian curve. This design employs five Hall probes, as shown in Fig. R8 (left). Increasing the number of Hall probes (e.g., to seven or nine) improves the resolution of the Gaussian approximation.\nSimilarly, for edge detection, the kernel follows the function (1, 0, –1), which measures the intensity difference between neighboring pixels (see Comment 6 for details). The corresponding device uses Wₚ = 8–8–8 µm, reflecting the equal magnitude of the coefficients +1 and –1. The opposite signs are implemented by reversing the connection polarity of the first and third Hall channels, while the 0 coefficient is realized by leaving the middle Hall channel unconnected. Although Fig. R8 (right) shows five equally spaced Hall pads (8–8–8–8–8 µm), only three are active for edge detection, while all five are utilized for the averaging function.\nIn summary, the design principle of the MCA device is determined by the target convolution kernel, where the number and spacing of Hall probes (Wₚ) directly correspond to the kernel’s elements and their relative magnitudes. Further details are provided in the Methods section of the manuscript.\nFig. R8 | MCA device photo-litho mask. Left: For Gaussian blurring, W values of 3–12–18–\nP\n12–3 µm. Right: For edge detection and average, W values of 8–8–8–8–8 µm. Details of other\nP\ndimensions, such as W and W , can be found in Method.\nO H\n6. It is not clear to me how they perform the handwritten digit recognition and image edge detection tasks. Which results were performed in physical devices and which results were performed in computers? They should provide more details, such as how to encode the grey scale value into domain length, how to choose the current density and how to correct the offset Hall voltage.\n13 | Pa ge\nReply:\nWe thank the reviewer for asking about the detailed implementation of the MCA device. We realize that our original description may not have been sufficiently clear. The details are clarified below in the following order:\n1. Encoding grey scale value, Choice of current density, and Correction of offset Hall voltage\n2. Image edge detection\n3. Handwritten digit recognition\nEncoding grey scale values\nAs shown in Fig. R9a, each image is composed of pixels with grayscale values ranging from 0 to 255. An example of pixel grayscale variation from pixel No. 100 to No. 150 is shown in Fig. R9b. The corresponding V –domain-length dependence is measured experimentally (Fig.\nAHE\nR9c), establishing a one-to-one linear mapping between grayscale value and domain length through V : Grey scale (Computer) → V (Device)→ Domain length. This mapping allows\nAHE AHE\neach pixel’s intensity to be physically represented by a domain of proportional length in the MCA device.\nIn summary, the grayscale values (from the original image) are obtained in the computer, while the corresponding V values are measured experimentally in the MCA device.\nAHE\n[FIGURE REDACTED]\nFig. R9 | Encoding grey scale value to domain length. (a), Grey scale image. (b), Grey scale value of pixel No. 100 to No. 150. (c), V as a function of domain length.\nAHE\nChoice of current density\nIn our current implementation, a fixed driving current of 1 mA is used for domain-wall motion, corresponding to a current density of 8.33 × 10⁹ A/m². The choice of current density is determined by the device geometry and the temporal resolution of the pulse generator. Since the pulser used in our experiments provides reliable control in the μs-range, we selected a domain-wall velocity of approximately 0.5 m/s, corresponding to a 40μs displacement time for a 20μm Hall-electrode spacing.\nCorrection of offset Hall voltage\n14 | Pa ge\nThe offset Hall voltage arises primarily from slight misalignment of Hall pads during fabrication (see also Comment 8, Reviewer 3). At the current stage, this offset is corrected computationally in computer. Experimentally, it can be minimized using high-resolution lithography, as demonstrated in Fig. R10, where the offset is nearly eliminated.\nAlternatively, offset compensation can be achieved using a simple peripheral differential amplifier or offset-cancellation circuit. The offset can be effectively subtracted in real time using standard readout electronics commonly employed in Hall sensors and magnetic memory devices [1,2]. Such circuits require only a modest number of transistors and consume microwatt-level power, negligible compared with the total device array, while operating well within the readout bandwidth of magnetic devices [3].\nFig. R10 | AHE measurement of device with improved fabrication. The alignment is improved and the offset is nearly zero.\nReference\n[1] Ramsden, E., 2011. Hall-effect sensors: theory and application. Elsevier.\n[2] Popovic, R.S., 2003. Hall effect devices. CRC Press.\n[3] Carusone, T.C., Johns, D.A. and Martin, K.W., 2011. Analog integrated circuit design. John Wiley & Sons.\nImage edge detection\nWe first briefly discuss the principle of edge detection, as illustrated in Fig. R11a. Consider a one-dimensional line of pixels, where the edge corresponds to the region with the largest change in grayscale value—for example, between 1 and –1 in the sequence. In flat regions (e.g., 1 1 1 or –1 –1 –1), no change occurs. To detect the edge, we use a convolution kernel of (1, 0, –1) and slide it along the pixel line. In flat regions, the convolution output remains 0, while at the edge, it becomes nonzero (2 in this example). Consequently, only the edge appears bright (grayscale = 2), and all other regions remain dark (grayscale = 0).\n15 | Pa ge\nThus, the edge-detection process follows the standard convolution operation, consisting of shift and multiplication steps. The shift is achieved through SOT-driven domain-wall motion, while multiplication is realized by combining the input and kernel values. The input grayscale image is encoded as the domain length (L ), and the kernel values are encoded as the spacing between\nD\npairs of Hall pads (W ). These two parameters produce a Hall voltage proportional to V ~ L\nP AHE D\n× W . The resulting multiplication outputs (V ) are then summed in the computer to\nP AHE\nreconstruct the edge-detected image. The overall flow is shown in Fig. R11b. In the future, this summation can be fully implemented in hardware using a simple switched-capacitor circuit, as illustrated in Fig. R11c, enabling a completely integrated operation.\nFig. R11 | Edge detection. (a), Principle. (b), Flow diagram. (c), Switch capacitor circuit.\nHandwritten digit recognition\nThe handwritten-digit recognition task is implemented using a convolutional neural network, as shown in Fig. R12a. Only the convolutional layers (Conv) are physically realized using the MCA device, while the subsequent layers—max pooling, flattening, and fully connected layers— are executed on a computer. As discussed in the manuscript, convolution layers account for over 90% of the total computation cost; thus, implementing them in our MCA hardware significantly reduces energy consumption and area footprint.\nThe physical implementation of the convolution layer follows the same principle as the edge-detection operation, differing only in the kernel size and values. For instance, the grayscale image matrix is convolved with a 3 × 3 kernel (Fig. R12b). Each 3 × 3 block of the image is multiplied element-wise by the kernel matrix and summed to yield the first element of the output feature map. The kernel is then shifted across the entire image matrix to complete the convolution.\nSimilar to every convolution operation performed by our MCA device, here the pixel value (input) is encoded as domain length, the kernel (weight) is encoded as the spacing between Hall pads (Fig. R12c), and the shift and multiplication are done physically.\n16 | Pa ge\nFig. R12 | Handwritten digit recognition. (a), Flow diagram. MCA device is used to reduce the energy and area of the Conv layers. (b), Principle of the convolution layer. (c), Physical implementation of convolution.\n17 | Pa ge\nReviewer #2 (Remarks to the Author):\nAuthors proposed a nice idea having the weights mapped as spacing between electrode pairs during fabrication, which mean weights are fixed at that stage. The inputs, however are applied as domain lengths that can be dynamically controlled and changed at runtime. However, only this part of the device has been experimentally validated. At this stage, the work has multiple practical issues, which are not resolved or discussed. Furthermore, there are theoretical ideas which are not validated in depth, such as, 2D version where both the weights and inputs can be dynamically programmed.\nReply:\nWe sincerely thank the reviewer for the thorough and constructive feedback, which has greatly improved the practical relevance, scientific rigor, and overall impact of our work. In response, we have performed additional experiments, calculations, and algorithmic validations to address the reviewer’s concerns and to further substantiate both the experimentally demonstrated and theoretically proposed aspects of the device. Moreover, we have substantially revised the Main Text and Supplementary Information to incorporate these new results and enhance the overall clarity and coherence of the manuscript\nA detailed point-by-point response to each comment is provided below:\nThe critical points are highlighted below.\n1. The manuscript acknowledges that the current 1D Hall-based MCA requires relatively high current densities to drive domain wall motion, leading to energy per operation that is slightly higher than CMOS. While the authors suggest this can be mitigated by material optimization, this is left as future work.\nReply:\nWe thank the reviewer for this insightful comment. In response, we conducted additional experiments to reduce the energy required for domain-wall motion through material optimization.\nOur material stack is Ta (5) / CoFeB (1) / MgO (2), with thicknesses in nanometers. Motivated by Reference [1], we optimized the growth pressure of the heavy-metal Ta layer, which strongly influences defect density and interfacial quality. Specifically, we prepared three batches of samples with Ta growth pressures of 2.0, 2.5, and 3.0 mTorr and characterized their domain-wall motion velocities. As reported in Reference [1], a lower growth pressure typically reduces pinning-site density, thereby decreasing the energy required for domain-wall motion. Our measurements confirm a similar trend, as shown in Fig. R1a.\nFor the 2.0mTorr condition, a domain-wall velocity of 2.5 m/s is achieved under a current density of 2.1 × 10⁹ A/m². In contrast, before optimization, the same velocity required a current density of approximately 11.5 × 10⁹ A/m² (Fig. R1b). This corresponds to an ~30-fold reduction in energy consumption per operation.\n18 | Pa ge\nFig. R1 | Domain wall motion after pinning optimization. (ai), Snapshots of domain wall motion. White (grey) color denotes +Mz (-Mz). V denotes domain wall motion velocity, and represent time stamps. (aii), Domain wall motion velocity vs. Current density plot. (b), Domain wall motion velocity vs. Current density plot before material optimization.\n𝑡𝑡0,1,2\nReference\n[1] Kumar, Durgesh, et al. \"Ultralow energy domain wall device for spin-based neuromorphic computing.\" ACS nano 17.7 (2023): 6261-6274.\n2. The device relies on precise domain nucleation, length control, and synchronized wall motion. The paper shows impressive lab-scale control but does not address large-array scaling. Scalability and uniformity are critical for any practical accelerator.\nReply:\nWe thank the reviewer for this insightful feedback. The scalability and uniformity concerns are indeed critical for practical accelerator implementation and are collectively addressed through our detailed responses to other specific comments.\nThe scalability issue is addressed by:\n1. Domain wall synchronization measurement over large distance and methods for handling crosstalk or variation in large arrays (Comment 6)\n2. Method for handling alignment, yield, and TMR variation across large arrays (Comment 9)\nThe uniformity issue is addressed by:\n1. Quantitative measurements of deviation from ideal case (Comment 4)\n2. Measured yield of fabrication (Comment 5)\n3. Method for handling alignment, yield, and TMR variation across large arrays (Comment 9)\n19 | Pa ge\n3. While a 2D MTJ-MCA extension is proposed, it is theoretical. Can the authors clarify whether any test structures for the 2D MTJ-MCA have been fabricated?\nReply:\nWe thank the reviewer for this valuable comment. In response, we clarify that we have fabricated test structures for the 2D MTJ-MCA and experimentally verified all key convolutional operations—namely Read, Write, Shift, and Tunable Weight. The results are presented in two parts:\n1. Fabrication of MTJ-MCA devices on an industry-grade full-MTJ material stack (8-inch wafer)\n2. Experimental demonstration of Read, Write, Shift, and Tunable Weight operations\nFabrication of MTJ-MCA devices on an industry-grade full-MTJ material stack (8-inch\nwafer)\nIn collaboration with a semiconductor foundry, we developed an industry-grade full-MTJ material stack on an 8-inch wafer. The wafer photograph and corresponding material stack are shown in Fig. R2a and Fig. R2b, respectively. Using this stack, we fabricated test MTJ-MCA devices, as shown in the optical micrograph in Fig. R2c. Each device consists of a magnetic strip (the Shifting Channel), a MTJ readout region (the Reading Junction, highlighted by the red dashed box), and two Oersted-field writing lines (the Writing Channel). The schematic on the right of Fig. R2c illustrates the detailed structure within the red dashed box.\n20 | Pa ge\nFig. R2 | Industry-grade full-MTJ material stack 8-inch wafer and MTJ-MCA device.\n(a), A photo of the 8-inch wafer. (b), Magnetic tunneling junction material stack. The layer thicknesses are not provided for confidential reasons. (c), MTJ-MCA device. The structure inside the red dashed box is illustrated in the right schematic. Red: -Mz domain. Blue: +Mz domain.\nExperimental demonstration of Read, Write, Shift, and Tunable Weight operations\n(a) Write:\nWriting is performed using the Oersted field, same method as the Hall-MCA device.\nRepresentative MOKE snapshots are shown in Fig. R3a.\n(b) Read:\nReading is performed using tunneling magnetoresistance (TMR), which, analogous to the anomalous Hall effect, is proportional to the net Mz. The measured TMR loop of the MTJ-MCA device is shown in Fig. R3b. The zoomed-in region (right panel) reveals distinct resistance steps, each corresponding to a convolution input value, with several hundred inputs achieved across the full loop.\n(c) Shift:\nShifting is realized through spin–orbit torque (SOT)-driven domain-wall motion, employing the same mechanism as in the Hall-MCA. MOKE snapshots are provided in Fig. R3c.\n21 | Pa ge\nFig. R3 | Demonstration of Read, Write, and Shift and tunable weight in the MTJ-MCA\ndevice. (a), MOKE images of the Domain Writing process. Green shade: Oersted field channel.\nYellow arrow: Applied current direction. A current is applied, and a +z domain is created,\nlocation mark by the blue arrow. (b), TMR loop. Each step corresponds to a convolution input.\nRight figure: Zoom-in plot of the red box region. (c), MOKE images of domain wall motion.\nYellow shade: Reading junction. t1 to t6 represent the time stamps. Black arrow denotes the\nmotion direction. d(i), TMR loops by applying different junction voltages. Weight is obtained\nby ( ). d(ii), Plot summarizing the measured and at different applied voltages.\n𝑅𝑅𝑎𝑎𝑎𝑎−𝑅𝑅𝑎𝑎\nInset: w𝑅𝑅𝑎𝑎eight values ( ). Currently, 15 different w𝑅𝑅e𝑝𝑝ights 𝑅𝑅ar𝑎𝑎e𝑝𝑝 obtained.\n𝑅𝑅𝑎𝑎𝑎𝑎−𝑅𝑅𝑎𝑎\n(d) Tunable weights: 𝑅𝑅𝑎𝑎\nIn the Hall-MCA, the convolution weights are fixed by the geometric width between pairs of\nHall pads. In contrast, the MTJ-MCA enables tunable weights, achieved by modulating the TMR\nratio, defined as , where denote the resistances corresponding to parallel and\n𝑅𝑅𝑎𝑎𝑎𝑎−𝑅𝑅𝑎𝑎\nantiparallel alignmen\n𝑅𝑅𝑎𝑎\nts of the top\n𝑅𝑅\na𝑝𝑝n d\n( 𝑅𝑅\nb𝑎𝑎o𝑝𝑝tt\n)\nom CoFeB layers, respectively.\nBy applying different junction voltages, the TMR loops can be rescaled. As shown in Fig. R3d(i), each junction voltage produces a distinct TMR loop that differs only in its TMR ratio. In other words, these loops can be transformed into one another by a multiplicative factor—\ncorresponding to the definition of a weight.\nAs discussed in the (b) Read section, each point on the TMR loop represents a convolution input\nvalue. By adjusting the TMR ratio, the multiplicative factor (weight) of each input can thus be\ntuned. For instance, Point 1 at 50 mV transforms into Point 2 at 500 mV, effectively multiplying\nthe input by a scaling factor (weight). Measurements under multiple junction voltages yielded a\nwide range of tunable weights, summarized in Fig. R3d(ii).\nThe underlying mechanism is that increasing the junction voltage (and thus the electric field)\nallows deeper, un-spin-polarized electronic states to contribute to tunneling, thereby reducing the\nTMR ratio. We note that this voltage-controlled method is simpler than the originally proposed\nscheme in the Main Text, where the weights are tuned by varying the magnetization of the top\nCoFeB layer. However, the voltage-controlled range is limited, as higher voltages may induce\nbarrier breakdown. Therefore, the magnetization-based approach remains the preferred and more\nscalable method for future implementations.\nIn summary, we have experimentally verified the MTJ-MCA architecture.\n4. AHE voltage readout relies on linear mapping of domain length and electrode spacing, but\nfabrication imperfections introduce nonlinearity. Readout fidelity is fundamental to inference\naccuracy. Can the authors provide quantitative measurements of deviation from ideal linearity?\nHow does readout noise impact classification accuracy in their CNN demonstration?\nReply:\nWe thank the reviewer for this valuable suggestion. Our response is divided into two sections:\n1. Quantitative measurements of deviation from linearity\n2. Readout noise and classification accuracy of CNN demonstration\nQuantitative measurements of deviation from linearity\nIn our experimental setup, the nonlinear deviations mainly come from two sources: (1) variations\nin the domain length (input variation) and (2) variations in the Hall pad width (weight variation).\nThe nonlinear deviations of these two factors are presented in Main Text Figs. 2f and 2h, and\nreproduced in Fig. R4 for reference. Quantitatively, the average deviation in Hall pad width is\napproximately 7%, while the variation in domain length is about 2%.\n22 | Pa ge\nFig. R4 | Main Text Fig. 2f & 2h. Left figure: Fig. 2f, weight variation. Right figure: Fig. 2h, input variation.\nReadout noise and classification accuracy of CNN demonstration\n(a) Domain length (input) variation\nWe compared the input data using the raw experimental results from Fig. 2h with the ideal case.\nAs shown in Fig. R5, the handwritten digit datasets with and without domain-length deviations\nare visually indistinguishable, as the experimental variation in domain length is only about 2%.\nThis small deviation preserves the fundamental image features necessary for accurate\nhandwritten-digit recognition. Consequently, the recognition accuracy remains 98.94%,\ndemonstrating that input nonlinearity has a negligible effect on the algorithm’s performance.\n23 | Pa ge\nFig. R5 | Input with and without deviation. Left: MNIST image without incorporating\ndomain length variation. Right: MNIST image with domain length variation. Both images\nshow a clear digit shape and the difference is negligible.\n(b) Hall electrode spacing (weight) variation\nIn the original manuscript, we already accounted for variations in the weights by directly using\nthe raw V readouts from different Hall channels as the weight values.\nAHE\nAs discussed in the manuscript, the training process was performed in software, whereas the\nMCA device is designed for inference with fixed weights. Accordingly, the kernel values derived\nfrom the training results are approximated using the nearest experimental V values, as\nAHE\nillustrated below:\nIdeal convolution kernel (training):\n0.1399 -0.289 0.172\n0.489 0.251 -0.521\n0.2173 -0.299 -0.452\nRaw V approximation (experiment):\nAHE\n0.1400 -0.271 0.184\n0.490 0.239 -0.524\n0.2208 -0.305 -0.478\nWe then performed inference using both experimental input and weight variations (raw V\nAHE\nvalues incorporating domain-length and Hall-pad deviations). The resulting recognition accuracy\nremains high at 98.80%, confirming that the observed nonlinearities do not significantly impact\nthe algorithm’s performance.\n24 | Pa ge\nRevisions:\nThis section is added into the Supplementary Fig. S10, highlighted in yellow.\nA description is added into the Main Text: From Line 327 to 330, highlighted in yellow.\n5. The device requires precise deposition of Ta/CoFeB/MgO stacks with PMA, fine Hall\nelectrode spacing, and integration of Oersted nucleation lines. Scalable production is necessary\nfor any hardware accelerator. What is the measured yield of fabricated devices? How sensitive is\nperformance to lithographic variations?\nReply:\nWe thank the reviewer for this important question regarding device yield and sensitivity to\nlithographic variations. Our response is divided into two sections:\n1. Measured device yield\n2. Performance sensitivity to lithographic variations\nMeasured device yield\nAn optical image of the fabricated sample is shown in Fig. R6a, containing 354 MCA devices. A\nmagnified view of the top block and a single representative device are shown in Figs. R6b and\nR6c, respectively.\nTo qualify as functional, a device must successfully perform the Write, Shift, and Read\noperations. Across the entire project, we have measured 64 MCA devices, of which 58 were fully\noperational, corresponding to a yield of ~90.6%, primarily limited by the Shift operation.\nFig. R6 | Sample and device. (a), An actual fabricated sample. (b), A block of the sample. (c), A single\nMCA device from (b).\n(a) Write\n25 | Pa ge\nDomain nucleation and length control are achieved using an Oersted-field line, as described in\nthe manuscript. The mechanism and fabrication requirements are both simple and robust. The\nwriting lines are tens of micrometers in width, easily handled by standard lithography. No\nfailures were observed in the Write operation, giving a 100% yield.\n(b) Shift\nThe main source of yield loss arises from local fabrication defects that hinder domain-wall\nmotion. A representative defective device is shown in Fig. R7a, with the magnified region in Fig.\nR7b highlighting structural imperfections. Such defects reduce domain-wall velocity, requiring\nhigher current densities to achieve the same speed and thereby increasing energy consumption.\nFor quantitative evaluation, we measured domain-wall velocities in all 64 devices under the same\ndriving current density of 8.33 × 10⁹ A/m² (the value used in the manuscript). The results,\nsummarized in Fig. R7c, show that typical devices exhibit velocities around 0.5 m/s, while\ndefective ones fall below 0.4 m/s. We therefore define devices with v < 0.4m/s as non-functional.\nThe resulting yield is 58/64 (~90.6%).\nFig. R7 | Device yield from the shifting operation. (a), Microscope image of an MCA device with\ndefects. (b), Zoom-in image of (a) showing the shape defect in magnetic strip. (c), Device variation in\ndomain motion velocity.\n(c) Read\nThe Read operation relies on detecting the anomalous Hall effect (AHE), which scales linearly\nwith the width W . AHE sensing is highly robust, with only small deviations from ideal linearity\nP\ndue to fabrication non-idealities. As demonstrated in Comment 4, the readout quality remains\nsufficient for algorithmic implementation. Thus, the Read operation also shows a 100% yield.\nIn summary, the domain-wall motion (Shift) stage represents the primary yield bottleneck.\nAmong 64 tested devices, 58 functioned correctly, yielding ~90.6% overall.\nYield Write Success Rate Shift Success Rate Read Success Rate\n90.6% 100% 90.6% 100%\nRevisions:\nThis section is added into the Supplementary Fig. S5 & S6.\nA description is added into the Main Text: From Line 208 to 214.\n26 | Pa ge\nPerformance sensitivity to lithographic variations\nThe lithographic variation in our lab-scale fabrication is approximately 1–2 μm, primarily\nlimited by the instrument resolution (for example, Karl Suss MA-6 contact aligner). These\nvariations result in two types of imperfections: (i) shape defects, and (ii) pattern misalignment.\nShape defects mainly affect the Shift operation by introducing pinning sites that reduce domain-\nwall velocity, as discussed in the previous section. In contrast, pattern misalignment laterally\noffsets device features by about 1 μm, but has negligible impact on all three operations (Write,\nShift, and Read). This insensitivity arises because we intentionally included 3 μm design margins\nin the photomask layout, providing sufficient spatial tolerance.\nAn exemplary mask design is shown in Fig. R8a, where the 3 μm margin is highlighted. A\nrepresentative optical micrograph of a fabricated device is shown in Fig. R8b. From the\nobserved dimensions, it is clear that a 1 μm misalignment remains well within the designed\ntolerance and does not affect device functionality.\nFig. R8 | Exemplary Mask design and a typical device. (a), Design margin of the MCA mask. (b),\nMicroscope image of a typical MCA device.\n6. While small-scale devices are demonstrated, large-scale arrays needed for real AI workloads\nare not. Demonstrating a few cells is valuable, but deployment requires large arrays. How does\ndomain wall synchronization degrade over distance? What strategies exist to handle crosstalk or\nvariation in large arrays?\nReply:\nWe thank the reviewer for this valuable comment. Our response is divided into three sections:\n27 | Pa ge\n1. Domain wall synchronization measurement over distance\n2. Handling of crosstalk\n3. Handling of variations\nDomain wall synchronization measurement over distance\nWe used MOKE imaging to quantitatively assess domain-wall synchronization during\npropagation. As illustrated in Fig. R9a, a domain is bounded by two domain walls (DWs), and\ntheir spacing—the domain length (L )—may fluctuate during motion. Thus, the degree of\nD\nsynchronization can be evaluated by measuring the variation in L as the domain moves along\nD\nthe track.\nWe experimentally prepared two representative cases: a wide domain and a narrow domain. The\nresult is shown in Figs. R9b & c. For wide-domain propagation, the measured domain lengths\nexhibit a standard deviation of 0.15 µm (1.9%), and for narrow domains, 0.10 µm (2.1%).\nThese results confirm the high stability of domain-wall motion.\nFig. R9 | Domain wall synchronization test. (a), MOKE image of a domain. It consists of two\ndomain walls, DW 1 and DW 2. (b), Wide (Top) and narrow (Bottom) domain propagation\nacross MCA device. (c), Domain length vs. Travel Distance.\nRevisions:\nThis section is added into the Supplementary Fig. S3.\nA description is added into the Main Text: From Line 188 to 191.\nHanding of crosstalk\n28 | Pa ge\nIn large arrays, crosstalk may occur when neighboring MCA devices are placed too close\ntogether. The primary source of crosstalk is the dipolar (stray) field generated by the magnetic\nlayer of adjacent devices.\nTo quantify this effect, we calculated the stray-field distribution based on the actual device\ndimensions: the magnetic layer (Domain Channel) measures 200 μm × 20 μm × 1 nm, with a\nsaturation magnetization Ms=1000 emu/cc. The results are summarized in Fig. R10. Fig. R10a\nshows the device geometry, and Fig. R10b maps the out-of-plane field component (Bz) near the\ndevice. The detailed dependence of stray-field magnitude on distance from the device edge is\npresented in Figs. R10c and R10d (short and long edges, respectively), with zoomed-in views\nfrom 100 nm to 1000 nm shown in Figs. R10e and R10f.\nThe stray field magnitudes at characteristic lengths are summarized below:\n• At 10 nm from the device edge:\nBz ≈ 19–20 mT; the tangential in-plane component is ≈ 3 mT (that’s By at a long edge or\nBx at a short edge)\n• ∣ At 1 ∣ 00 nm: ∣ ∣\n∣Bz∣ ≈ 2.0 mT; tangential in-plane ≈ 0.03 mT (30 µT).\n• At 1 µm:\n∣Bz∣ ≈ 0.19 mT; tangential in-plane ≈ 0.0003 mT (0.3 µT).\nFor comparison, the coercivity of our magnetic layer is ~5 mT. Therefore, a 1 µm lateral spacing\n∣ ∣\nensures that the maximum stray field (~0.19 mT) remains well below the coercivity, effectively\nsuppressing magnetic crosstalk between adjacent devices.\nTo further increase device density, 100 nm or smaller spacing can be adopted if the\nperpendicular magnetic anisotropy (PMA) is enhanced. This can be achieved, for example, by\nreducing the CoFeB thickness or by switching to material systems such as Pt/CoFeB/MgO or\nPt/Co/AlOx, which exhibit coercivities exceeding 100 mT. Under such conditions, stray-field\ninteractions would be negligible.\nWe note that this estimation represents the worst-case crosstalk scenario, assuming a uniformly\nmagnetized single-domain state. In practical devices, however, the magnetization alternates\nacross domains, producing flux closure and substantial field cancellation. Consequently, the\nactual magnetic crosstalk in large arrays is expected to be significantly weaker than this upper\nbound.\nRevisions:\nThis section is added into the Supplementary Fig. S15.\nA description is added into the Main Text: From Line 401 to 403.\n29 | Pa ge\nFig. R10 | Stray field from the magnetic layer. (a), Device dimensions. (b), Stray field color map. (c),\nStray field distribution from the short edge. (d), Stray field distribution from the long edge. (e), Zoom-in\nof (c) from 100nm to 1000nm. (f), Zoom-in of (d) from 100nm to 1000nm.\nHandling of variations\nAs discussed in Comment 5, our current devices exhibit a yield of approximately 90.6%,\nprimarily limited by the Shift operation. The yield loss arises from shape defects introduced\nduring fabrication using lab-scale instruments, which impose limits on lithographic resolution\nand uniformity.\nTo mitigate these variations, two practical strategies can be employed:\n1. Foundry collaboration: Partnering with a semiconductor foundry would significantly\nimprove fabrication quality, as industry-standard tools provide much higher patterning\nprecision and process yield. Given the simplicity of our device geometry, a 180 nm\ntechnology node is sufficient to realize large-scale arrays with minimal variation.\n30 | Pa ge\n2. High-resolution e-beam lithography: Alternatively, employing electron-beam\nlithography—with achievable resolutions of 20 nm or finer—would effectively eliminate the\nedge roughness and shape defects responsible for domain-wall velocity variation.\nBoth approaches ensure high uniformity and reproducibility, thereby addressing the observed\nvariability in domain-wall motion and enabling scalable array fabrication.\n7. Can the authors clarify what CMOS baseline design was used? Have they benchmarked\nagainst state-of-the-art low-power MAC implementations?\nReply:\nWe thank the reviewer for this important question regarding the CMOS benchmarking baseline.\nWe apologize for not clearly stating these details in the original manuscript. Our response is\norganized into two sections:\n1. Details of the CMOS benchmarking baseline\n2. Benchmarking against state-of-the-art Multiplication-Accumulation (MAC)\nDetails of the CMOS benchmarking baseline\nTo enable a fair comparison, a dedicated CMOS application-specific integrated circuit (ASIC)\nwas designed to replicate the exact same functionality of our device—specifically, performing 8-\nbit, 1024-point convolutions. The architecture is illustrated in Fig. R11.\nThe CMOS baseline consists of:\n• 8-bit shift registers for sequential input data shifting,\n• 8-bit fixed-weight registers for storing convolution kernels,\n• Parallel 8-bit multipliers to compute the input–weight products,\n• An 8-bit adder tree to sum the partial products.\n31 | Pa ge\nFig. R11 | CMOS baseline. CMOS circuit architecture used for benchmarking. (This figure\nis a schematic of the design, the actual circuit layout is significantly larger and is not shown\nhere for brevity.)\nThis is provided in Supplementary Fig. S14.\nBenchmarking against the state-of-the-art Multiplication-Accumulation (MAC)\nEach circuit component shown in Fig. R11 was synthesized using a standard digital cell library\nprovided by the TSMC semiconductor foundry. The library offers state-of-the-art specifications\nfor each cell, including physical layout information, delay characteristics, leakage properties, and\nenergy consumption metrics, some exemplary specifications are shown in Fig. R12. These\nspecifications ensure the CMOS benchmark has a state-of-the-art low-power, high-speed,\nand small-area MAC implementation.\nThe CMOS benchmarking was established as follows:\n• Area Estimation: The reported area reflects the fully synthesized layout, accounting for both\nthe active components and routing overheads.\n• Energy Estimation: The reported energy consumption corresponds to the dynamic (active)\nenergy during computation.\n• Throughput Estimation: The path delay extracted from synthesis results was used to\ndetermine the operating throughput of the benchmark CMOS hardware.\n32 | Pa ge\nFig. R12 | Standard digital cell library from TSMC. The metrics ensures the state-of-the-\nart low-power, high-speed, and small-area MAC performance.\n8. The main application demonstrated is MNIST digit classification (28×28 images). A simple\ndataset can overstate practical readiness.\nReply:\nWe thank the reviewer for this insightful comment. To further validate the practical potential of\nour device, we extended our evaluation beyond the MNIST dataset to the more challenging\nCIFAR-10 image classification task. Compared with MNIST, CIFAR-10 images have a higher\ndimensionality (32 × 32 × 3) and involve convolutional layers with approximately 20× more\nkernel weights, thereby providing a more stringent benchmark for computational performance.\nIn our experiments, we incorporated readout deviations originating from both domain length and\nweight variability. Representative CIFAR-10 images with and without domain-length deviation\nare shown in Fig. R13a, illustrating that the induced variation has a negligible visual impact—an\nimportant prerequisite for maintaining correct classification performance.\nThe classification results obtained from our MCA device are presented in Fig. R13b. The\nachieved recognition accuracy is approximately 80%, which is comparable to state-of-the-art\nCIFAR-10 baselines (see Ref. [1], Fig. R13c). These results confirm that our MCA device\nsustains robust performance even for more complex datasets beyond MNIST.\nWe note that the current accuracy limit (~80%) primarily arises from the simplified neural\nnetwork architecture used for this demonstration rather than any intrinsic device limitation.\nFurther improvements can be expected by employing more advanced network structures—such\nas ResNet—which are beyond the scope of the present work.\n33 | Pa ge\n[FIGURE REDACTED]\nFig. R13 | CIFAR-10. (a), CIFAR-10 image without and with domain length deviations. (b),\nCIFAR-10 recognition matrix from our device. For example, when input is an Automobile\nimage, we have 91.4% chance to recognize it as an Automobile. An average of ~80% accuracy is\nachieved. (c), CIFAR-10 and MNIST accuracy of the state-of-the-art result. Adapted from Ref\n[1].\nReference\n[1] Shridhar, K., Laumann, F. and Liwicki, M., 2019. A comprehensive guide to bayesian convolutional\nneural network with variational inference. arXiv:1901.02731.\nRevisions:\nThis section is added into the Supplementary Fig. S9.\nA description is added into the Main Text: From Line 325 to 327.\n34 | Pa ge\n9. The 2D extension is presented analytically, but no experimental validation is shown.\nProposing a 2D solution is important, but feasibility is unclear. What is the plan for fabricating\ntest 2D MTJ cells? How will the authors address alignment, yield, and TMR variation across\nlarge junction arrays? What is the estimated energy/area/throughput of such 2D designs versus\n1D Hall MCA?\nReply:\nWe thank the reviewer for this valuable comment. Our response is divided into three sections:\n1. Fabrication plan for CMOS-integrated 2D MTJ cells\n2. Addressing fabrication challenges in large arrays\n3. Performance estimation of 2D versus 1D design\nFabrication plan for CMOS-integrated 2D MTJ cells\nOur preliminary experimental validation of the 2D MTJ-MCA concept was presented in\nComment 3, where we demonstrated all essential functions:\n• Write: Oersted-field–based domain nucleation\n• Shift: Spin–orbit torque (SOT)-driven domain-wall motion\n• Read: Tunneling magnetoresistance (TMR)-based readout\n• Tunable weights\nBuilding on this foundation, our next steps—conducted in collaboration with the foundry—will\nfocus on three progressive stages: (a) device scaling, (b) array fabrication, and (c) CMOS\nintegration.\n(a) Device scaling\nThe current MTJ-MCA devices are on the micrometer scale. We plan to downscale them using\nelectron-beam lithography, which provides ~20 nm patterning resolution. The target MTJ\njunction diameter is 100 nm, corresponding to a geometric scaling factor of 100 nm / 20 µm ≈\n0.005. The layout of the scaled-down MTJ-MCA design is shown in Fig. R14a.\n(b) Array fabrication\nWe have completed the first version of the mask and layout design for array-level testing. In\ncollaboration with the foundry, we will fabricate 8×8 MTJ-MCA arrays, with the contact layout\nexample shown in Fig. R14b. These arrays will serve to evaluate yield, uniformity, and inter-cell\ninterference across multiple MTJ elements.\n(c) CMOS integration\nFor CMOS integration, the MTJ material stack will be sputter-deposited on an 8-inch 28 nm\nCMOS wafer at room temperature. The critical MTJ junctions (100 nm diameter) will be\n35 | Pa ge\npatterned using e-beam lithography. M1–M5 back-end-of-line (BEOL) interconnect processing\nwill be implemented.\nThe integration architecture is as follows:\n• The MTJ-MCA device will be built atop VIA56.\n• The source line (SL) of each read/write/shift column connects to the MTJ’s fixed layer (top\nlayer) through VIA56, bottom and top electrodes (BE, TECT, TE).\n• The bit line (BL) connects to the MTJ free layer (bottom layer) through VIA56 and BE.\n• On-chip routing is arranged as SL on M1, WL on M4, and BL on M5.\nThe full integration flow is illustrated in Fig. R14c.\nIn summary, the CMOS front-end and M1–M5 BEOL will be fabricated by the foundry, followed\nby MTJ stack deposition and patterning in our lab. The final product will be a functional CMOS-\nintegrated MTJ-MCA chip capable of performing convolution operations.\nFig. R14 | Fabrication plan for scale-down, large-array, CMOS-integrated MTJ-MCA. (a), Device\npattern of MCA with 100nm MTJ. (b), Large-array of MCA devices. The contact layout is shown here.\n(c), CMOS-integration flow.\nAddressing fabrication challenges in large arrays\n(a) Alignment variation\nTo ensure alignment accuracy during array fabrication, we will adopt e-beam lithography with\nhigh-precision alignment marks and employ step-and-repeat exposure to maintain <10 nm\noverlay accuracy across the array. For wafer-scale implementation, we will collaborate with a\nfoundry to leverage advanced stepper lithography and automated overlay correction techniques\nalready established in standard MRAM production lines, which routinely achieve alignment\ntolerances below 5 nm.\n36 | Pa ge\n(b) Yield variation\nYield optimization will be addressed through redundant test structures and in-situ process\ncalibration to monitor layer-thickness uniformity and etch-endpoint control across the wafer.\nStatistical process control (SPC) will be applied during sputtering, patterning, and lift-off to\nensure uniformity of the magnetic and tunnel-barrier properties over large areas. As discussed in\nComment 5, the primary yield bottleneck arises from device-shape variation, which affects\ndomain motion. To mitigate this, special emphasis will be placed on maintaining sidewall\nsmoothness through optimized ion-beam etching and hard-mask engineering. Uniformity in\nfeature dimensions will be verified using high-resolution SEM and MFM imaging across\nrepresentative dies. Additionally, redundant sub-arrays and isolated test cells will be included on\neach wafer to statistically test the yield, enabling iterative feedback for process refinement. These\ncombined steps are expected to maintain domain-wall motion consistency and ensure high-yield\nfabrication across large arrays.\n(c) TMR variation\nRegarding TMR variation, we will employ post-deposition annealing and MgO-barrier thickness\ntuning to minimize junction-to-junction variability. The TMR uniformity achieved in state-of-\nthe-art MTJ arrays fabricated with similar methods is typically within ±5–10 %, which is\nadequate for AI algorithm applications, where small resistance fluctuations can be tolerated.\nIn summary, lithographic alignment will be ensured through precision e-beam and stepper\noverlay; yield will be enhanced through process control, device-shape optimization, and\nredundancy; and TMR variation will be minimized through material and thermal optimization\nconsistent with foundry-qualified MRAM standards.\nPerformance estimation of 2D versus 1D design\nThe performance estimation for the 2D design is summarized in Main Text Fig. 4b, with full\ndetails provided in the Supplementary Information. A concise summary is presented below.\n(a) Area\nCompared with the 1D design, the 2D MTJ-MCA occupies a smaller footprint because the\nweights are encoded by domain width, eliminating the need for the pair of anomalous Hall (AHE)\ncontacts used in the 1D version. Consequently, the total area is reduced from 133 μm² (1D) to\n103 μm² (2D).\n(b) Energy\nThe 2D design also exhibits significantly lower energy consumption, primarily due to the\nreduced shifting energy, while the write and read energies remain the same for both architectures.\nBy optimizing material pinning, the required current density for domain-wall motion can be\nreduced by several orders of magnitude.\nIn the current estimation, the shifting energy decreases from 1.024 nJ (1D) to 0.61 pJ (2D). This\nis based on a recent experimental report [1], where optimized pinning in a W/CoFeB/MgO\nheterostructure resulted in domain-wall displacement energies as low as 0.4 fJ for 18.6 μm\nmotion. Scaling this to our ~200 μm device corresponds to an energy of ~4 fJ—roughly five\n37 | Pa ge\norders of magnitude lower than the 1D design. To remain conservative, we adopted their worst-\ncase condition, yielding the 0.61 pJ value used in our estimation.\nIt is worth noting that the material system in Ref. [1]—W/CoFeB/MgO—is nearly identical to\nours (Ta/CoFeB/MgO), and Ta can be directly substituted by W, confirming the practical\nfeasibility of this improvement.\n(c) Throughput\nThroughput in both 1D and 2D architectures is determined by the domain-wall velocity, which\nremains identical in both cases. As a result, the throughput is ~248 MHz for both designs.\nReference\n[1] Kumar, Durgesh, et al. \"Ultralow energy domain wall device for spin-based neuromorphic\ncomputing.\" ACS nano 17.7 (2023): 6261-6274.\n10. Any practical use will require integration with CMOS for control, ADC/DAC, and post-\nprocessing. Have the authors analyzed the latency and energy of these conversions? How does\nthis impact the claimed system-level advantage?\nReply:\nWe thank the reviewer for this insightful question. Our response is divided into two sections:\n1. Latency and energy associated with CMOS conversions\n2. Impact on the system-level advantage\nLatency and energy associated with CMOS conversions\nTo ensure realistic benchmarking, our performance estimation explicitly includes the overhead\nfrom all peripheral CMOS circuitry. We apologize that this was not made sufficiently clear in the\noriginal manuscript.\nAdditional details are provided below and summarized schematically in Fig. R15, which\nillustrates the system integration components—drivers, control circuits, ADC, and the electrical–\nmagnetic interfaces. All components were modeled using 28 nm process design kits (PDKs) from\nTSMC, ensuring accurate estimation of latency, energy, and area, including routing and layout\noverhead.\n• Reading and Summation Circuitry: Accounting for approximately 80% of the total area,\nthe summation circuitry handles the addition of the weighted inputs and contributes\nsignificantly to the total area and energy metrics.\n• Analog-to-Digital Conversion (ADC) and Domain Writing/Shifting Circuitry: These\ncomponents have lower area and energy overhead as they are shared across the entire MCA.\n38 | Pa ge\nFig. R15 | The architecture of the evaluated MCA that includes all peripheral components. This\nfigure is an illustration of the design, the actual circuit layout is significantly larger and is not shown\nhere for brevity.\nMore details of Fig. R15 are provided below.\n• Domain Writing: The domains are written using a driver that generates a control voltage and\ndrives a current through a metal wire to create a magnetic field, establishing the interface\nfrom electrical to magnetic domains.\n• Domain Shifting: This is achieved via spin-orbit torque (SOT), where a driver generates a\ncontrol voltage and drives a current through the strip (comprising Heavy Metal/Ferromagnet\nlayers of the convolution device) to shift the magnetic domains within the device, forming\nthe interface from electrical to magnetic domains.\n• Readout: The anomalous Hall effect (AHE) converts magnetic signals into voltage signals,\ncreating the interface from magnetic to electrical domains.\n• Summation and ADC: Both summation and ADC operations are fully implemented in the electrical domain. Following reviewer’s suggestion, we further add an ADC such that the\noutput is not only electrical, but also digitized.\nWe adopt the ADC specifications from Reference [1], which has the same 8-bit precision and\n28nm technology as our evaluation. The ADC increases the total area by ~200%, but has\nnegligible effect on energy and latency overhead as it is shared across the entire MCA and\nprocess in real-time. The corresponding details are discussed below.\nWe evaluate the AHE readout for an 8-bit resolution, 1024-point convolution operation at\nGigahertz (GHz) frequencies, which is suitable for most AI and signal processing applications:\n• In our experiment, the range of the AHE signal is ( ) for a reading\ncurrent for a single convolution unit (a single Hall device). For a 1024-point convolution, the\noutput voltage range would be 0.4𝑚𝑚𝑉𝑉 +− an0d.2 𝑚𝑚the𝑉𝑉 variatio0n.1 f𝑚𝑚or𝑚𝑚 an 8-bit\nprecision would be , which can be readout by most circuits.\n0.4𝑚𝑚𝑉𝑉 ×1024 = 409.6 𝑚𝑚𝑉𝑉\n409.6 𝑚𝑚𝑚𝑚\n• To achieve the targe 82- 8 bit p=re1ci.6si o𝑚𝑚n𝑉𝑉, we should compare the voltage range with that of the\nsupply. Since our range ( ) is similar to the ( ), no\nadditional voltage amplification or range conversion is necessary.\n28 𝑛𝑛𝑚𝑚 409.6 𝑚𝑚𝑉𝑉 28 𝑛𝑛𝑚𝑚 𝑉𝑉𝐷𝐷𝐷𝐷 0.9 𝑉𝑉\n39 | Pa ge\n• Based on our device’s operational frequency ( , as estimated in the manuscript) and\noutput characteristics (8-bit precision), we require an 8-bit ADC capable of operating at\nto match the high-speed requiremen2t4s.8 I f𝑀𝑀 th𝑀𝑀e𝑧𝑧 ADC throughput is below ,\nmultiple ADC instances would be required for each 1024-point convolution engin>e.\n2C5o0n v𝑀𝑀er𝑀𝑀s/e𝑠𝑠ly, if the ADC throughput exceeds this requirement, a single ADC can 2b5e0 s 𝑀𝑀ha𝑀𝑀r/ed𝑠𝑠\namong multiple MCA devices.\nImpact on the system-level advantage\nGiven the aforementioned specifications, we have added a ADC to our benchmarking.\nThe ADC [1] is in area, has an 8-bit precision and operates at , fitting the\nabove requirements and i2s capable of supporting a larg2e 8a 𝑛𝑛m𝑚𝑚ount of MCA devices. The\nspecification can 0b.e0 0fo9u 𝑚𝑚nd𝑚𝑚 in Reference [1]. 10 𝐺𝐺𝑀𝑀/𝑠𝑠\nThe benchmarking performance is updated accordingly: The total energy is increased by\n(ADC conversion energy), the area is increased by . The\n58.9 𝑓𝑓𝑓𝑓\ninclusion of the ADC has negligible effect in energy 24 8 (f 𝑀𝑀 ro 𝐴𝐴 m 𝑧𝑧 to 2 2 ) but\n10 𝐺𝐺𝐴𝐴𝑧𝑧 ×0.009 𝑚𝑚𝑚𝑚 = 223.2 𝜇𝜇𝑚𝑚\nresults in an approximate increase in area (from to ).\n𝟏𝟏.𝟎𝟎𝟎𝟎 𝒏𝒏𝒏𝒏 𝟏𝟏.𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎 𝒏𝒏𝒏𝒏\n𝟐𝟐 𝟐𝟐\nWe have updated the benchmarking results based on the revisions made here. The updated\n2× 𝟏𝟏𝟎𝟎𝟎𝟎 𝝁𝝁𝝁𝝁 𝟎𝟎𝟎𝟎𝟑𝟑.𝟐𝟐 𝝁𝝁𝝁𝝁\nbenchmarking figure is shown in Fig. R16 below, which is also updated in the Main Text Fig. 4b.\nFig. R16 | Updated performance comparison of 1D Hall- and 2D MTJ-MCA against CMOS\non the same node. The plot is in log scale. Figure of merit (FOM) is defined as the Throughput\n( ) divided by the product of Area ( ) and Energy Efficiency ( ) ( ).\nR𝑇𝑇eference 𝑚𝑚 𝐸𝐸 𝐹𝐹𝐹𝐹𝑀𝑀 ≡ 𝑇𝑇/(𝑚𝑚𝐸𝐸)\n40 | Pa ge\n[1] Chen, Qian, et al. \"17.8 A Single-Channel 10GS/s 8b> 36.4 d8 SNDR Time-Domain ADC Featuring\nLoop-Unrolled Asynchronous Successive Approximation in 28nm CMOS.\" 2023 IEEE International\nSolid-State Circuits Conference (ISSCC). IEEE, 2023.\n11. Reliability is critical for deployment. High-current pulses may cause electromigration or\nheating. Have the authors measured temperature rise during operation? What is the estimated\nlifetime under continuous cycling? Are there mitigation strategies (e.g., duty cycling, material\nchanges)?\nReply:\nWe thank the reviewer for this important question regarding device reliability and potential\nheating effects. Our response is divided into three sections:\n1. Additional experiments on temperature rise\n2. Additional experiments on lifetime under continuous cycling\n3. Mitigation strategies\nAdditional experiments on temperature rise\nThe primary sources of heating are high-current pulse for domain motion. To characterize this\neffect, we performed additional experiments.\nFirst, we measured the Rₓₓ–T curve (device longitudinal resistance vs. temperature) for the same\ndevices used in the manuscript. The setup is shown in Fig. R17a. A 1 μA reading current (chosen\nto minimize self-heating) was applied to the current-shifting channel, and the voltage was\nmeasured across the two Hall channels using the standard four-probe method. The resulting Rₓₓ–\nT curve (Fig. R17b) shows a resistance of 349.72 Ω at 300 K with a slope of –0.069 Ω/K, which\nserves as our calibration reference. The temperature rise (ΔT) associated with Joule heating\nduring domain shifting can be obtained from the measured change in longitudinal resistance\n(ΔRₓₓ) using:\n1K\nTo quantify th∆e𝑇𝑇 he=at−ing0. 0e6f9fΩec∆t,𝑅𝑅 w𝑥𝑥. 𝑥𝑥e applied DC currents ranging from 1 μA to 1 mA and measured\nthe equilibrium Rₓₓ (Fig. R17c). For a 1 mA current—the shifting current used in the\nmanuscript—we obtain:\n1K 1K\nThis indicates that the device temperature increases from 300 K to approximately 320 K\n∆𝑇𝑇 = 0.069Ω∆𝑅𝑅𝑥𝑥𝑥𝑥 → ∆𝑇𝑇 = −0.069Ω×(348.33Ω−349.72Ω) ≈ 20 𝐾𝐾.\nduring 1mA DC current application.\nA temperature rise of ~20 K is modest in magnetic device applications and is unlikely to cause\nirreversible changes in magnetic properties. Larger temperature change is commonly observed in\nspin-orbit torque and domain-wall motion studies, without performance degradation.\nMoreover, in practical operation, the device is driven by pulse with a 50% duty cycle (or lower),\nwhich further reduces the effective heating. Therefore, Joule heating is not expected to notably\naffect the reliability or reproducibility of our device.\n41 | Pa ge\nFig. R17 | Heating effect during Shifting operation. (a), Measurement setup. (b), vs. curve. (c),\nas a function of DC current amplitude. Each current is applied for 4 hours, and measurements are\nperformed at room temperature. 𝑅𝑅𝑥𝑥𝑥𝑥 𝑇𝑇\n𝑅𝑅𝑥𝑥𝑥𝑥\nRevisions:\nThis section is added into the Supplementary Fig. S2.\nA description is added into the Main Text: From Line 179 to 181.\nAdditional experiments on lifetime under continuous cycling\nThe lifetime (endurance) can be divided into two parts, magnetic and non-magnetic.\nThe magnetic endurance is essentially unlimited, since magnetization reversal itself is inherently\nnon-destructive, it has no wear-out mechanism — as emphasized in fundamental reviews of\nspintronics and MRAM technology [1–3]. The non-magnetic endurance (mostly electric\nendurance) — including tunnel barrier reliability, interface degradation, dielectric breakdown,\nand electrical stress — has been experimentally demonstrated to exceed 10^14 switching cycles\nat 90% duty cycle without degradation [4,5].\nTo experimentally assess our own device stability, we monitored the anomalous Hall effect\n(AHE) signal under continuous operation. Using the same device from the temperature-rise test,\nwe applied a 1 mA DC current (domain-motion current) and repeatedly measured the AHE loops\nover five days. More than 1000 AHE loops were recorded (Fig. R18a). All curves overlap nearly\nperfectly, indicating no measurable change in either magnetic (AHE resistance, PMA, DMI, Ms)\nor electrical (longitudinal resistance, contact resistance) properties.\nAssuming a 2 ns operation pulse and 50% duty cycle, this corresponds to a projected endurance\nof 2.16 10^14 operation, which is sufficient for most AI and signal-processing workloads. A\nlonger test duration would likely confirm even higher endurance, but was not pursued due to\ntime co×nstraints. A zoom-in of the coercive-field region (Fig. R18b) shows minor fluctuations\n(~0.3 Oe), attributable to expected thermal noise near coercivity.\n42 | Pa ge\nFig. R18 | Endurance test for the MCA device. (a), 5-day AHE measurement. Offset in Hz is due to the\nremanence field of the electro-magnet. (b), Zoom-in plot of the red box region of (a), at the coercivity.\nReference\n[1] Chappert, C., Fert, A. & Van Dau, F. The emergence of spin electronics in data storage. Nature Mater\n6, 813–823 (2007).\n[2] Everspin Technologies Whitepaper. Fast Read/Write • Non-Volatile • Infinite Endurance. (Everspin\nTechnologies, 2016).\n[3] Kent, A., Worledge, D. A new spin on magnetic memories. Nature Nanotech 10, 187–191 (2015).\n[4] Kan, J.J., Park, C., Ching, C., Ahn, J., Xue, L., Wang, R., Kontos, A., Liang, S., Bangar, M., Chen, H.\nand Hassan, S., 2016, December. Systematic validation of 2x nm diameter perpendicular MTJ arrays and\nMgO barrier for sub-10 nm embedded STT-MRAM with practically unlimited endurance. In 2016 IEEE\nInternational Electron Devices Meeting (IEDM) (pp. 27-4). IEEE.\n[5] Kan, J.J., Park, C., Ching, C., Ahn, J., Xie, Y., Pakala, M. and Kang, S.H., 2017. A study on practically\nunlimited endurance of STT-MRAM. IEEE Transactions on Electron Devices, 64(9), pp.3639-3646.\nRevisions:\nThis section is added into the Supplementary Fig. S7.\nA description is added into the Main Text: From Line 208 to 214.\nMitigation strategies\nIn practical systems, several established strategies can be employed to further mitigate potential\nreliability concerns such as electromigration, localized heating, or dielectric degradation —\nmany of which are already adopted in commercial MRAM technologies.\n(a) Duty-cycle optimization and current-pulse engineering\nBy operating in pulsed mode with low duty cycles (typically <10%), the average thermal load\nand cumulative electromigration stress are significantly reduced, as demonstrated in STT-\nMRAM and SOT-MRAM devices. Shorter pulse widths (sub-nanosecond) and optimized rise/fall\ntimes further suppress transient temperature spikes.\n(b) Material and stack engineering\n43 | Pa ge\nThese can enhance robustness. The use of high-melting-point heavy metals (e.g., W) as spin-\norbit layers and thermally stable interfaces (e.g., CoFeB/MgO with optimized annealing)\nimproves electromigration resistance and thermal endurance. These design principles are\nstandard in advanced MRAM fabrication lines, where devices routinely sustain >1013 switching\ncycles without degradation.\n(c) Thermal management\nThis can be further improved through heat-spreading metallic underlayers such as Cu or Ru,\nwhich distribute local heat more evenly and improve overall temperature stability.\nTogether, these strategies — already validated in commercial MRAM and SOT-MRAM\nplatforms — are directly transferrable to our MCA devices, providing a strong foundation for\nlong-term endurance and reliable large-scale integration.\n44 | Pa ge\nReviewer #3 (Remarks to the Author):\nDai et al present a spintronic convolutional computing platform that exploits DW motion to\nperform both computation and data storage, realized through Magnetic Convolutional\nAccelerator (MCA). They demonstrate a concrete advance toward the vision of a general-\npurpose computing platform or full CIM realization, enabling applications such as short-time\nFourier transforms, convolutional neural networks, and image processing. The demonstrated\nMCA pioneered in convolutional acceleration while simultaneously integrating memory and\ncomputation through spintronic mechanisms. Realization of data processing tasks rely on\nanalogies between domain shifting and sliding-window operations, which offers exceptional\nscalability, energy efficiency, operation speeds and nonvolatility. I recommend publication if\nauthors can address the following concerns.\nReply:\nWe sincerely thank the reviewer for the thorough evaluation and constructive feedback, which\nhave greatly improved the rigor, clarity, and overall impact of our manuscript. In response to the\nreviewer’s comments, we have conducted additional experiments, algorithmic validations, and\nprovided further explanations to strengthen both the physical and computational aspects of the\nwork. We have also extensively revised the Main Text and Supplementary Materials to\nincorporate these updates and enhance the manuscript’s clarity and scientific rigor.\nA detailed point-by-point response to each comment is provided below:\n1. Is the 1D MCA convolution kernel multiplication and Fourier transform implemented through\nperipheral circuits? How is it realized?\nReply:\nWe thank the reviewer for this insightful question and apologize for not making this sufficiently\nclear in the original manuscript. To clarify, we provide additional explanations below. Our\nresponse is divided into two sections:\n1. 1D MCA convolution kernel multiplication\n2. Fourier transform implementation\n1D MCA convolution kernel multiplication\nThe multiplication is directly implemented at the device level through the anomalous Hall effect\n(AHE). Specifically, this is achieved by assigning the convolution input as domain length L and\nD\nthe kernel coefficient as the spacing between the Hall electrode pair W , as discussed in the\nP\nmanuscript. Detailed derivation is provided in (c).\nThe multiplication is based on two key physical relationships, illustrated in Fig. R1:\n(a) V W\nAHE P\nThe AHE voltage (V ) is proportional to the effective current amplitude within the pair of Hall\n∝ AHE\nelectrodes. This arises from the current shunting effect: for a fixed read current (I ), the fraction\nH\n45 | Pa ge\nof current passing through the Hall electrode pair scales with W , the spacing between the\nP\nelectrodes.\n(b) V L\nAHE D\nThe AHE voltage is also proportional to the net magnetization within the Hall sensing region,\n∝\nwhich depends on the magnetic domain area. For a fixed device width (W), the magnetized area\n— and thus the net magnetization — scales linearly with the domain length L .\nD\nCombine these two, V W L , which directly implements the multiplication\nAHE P D\nfunction at the device level.\n∝ ×\nFig. R1 | The convolution device. V : AHE voltage. I : Reading current. W: Device width. L :\nH H D\nDomain length. W : Spacing between the Hall electrode pair. L : Hall electrode length. Upper\nP P\npicture: A single unit. Lower picture: Different L\nD\nand W\nP\n.\n(c) Detailed derivation\nThe MCA device is structured such that the AHE voltage ( ) can be expressed as:\n𝑉𝑉𝐴𝐴\n′ 𝑊𝑊𝑃𝑃\nHere, represents a material-depen𝑉𝑉d 𝐴𝐴 en=t 𝛼𝛼con∙𝑀𝑀sta 𝑧𝑧 n∙t,𝐼𝐼 𝐴𝐴 ∙ is the net out-of-plane magnetization\n𝑊𝑊\nwithin th′e sensing region between a pair of Hall electrodes, is the applied current along the +x\ndirectio𝛼𝛼n, is the separation between the two Hall e𝑀𝑀lec 𝑧𝑧 trodes, and is the total device width.\n𝐼𝐼𝐴𝐴\nThe net ma\n𝑊𝑊\ng𝑃𝑃netization is described by:\n𝑊𝑊\n𝑀𝑀𝑧𝑧\n46 | Pa ge\n𝐿𝐿𝐷𝐷\nwhere denotes the saturation magnetization, is the length of the reversed (-z) magnetic\n𝑀𝑀𝑧𝑧 = −2𝐿𝐿𝑃𝑃 +1𝑀𝑀𝑠𝑠\ndomain, and corresponds to the contact length of the Hall electrodes.\n𝑀𝑀𝑠𝑠 𝐿𝐿𝐷𝐷\nInitially, the H 𝐿𝐿𝑃𝑃all sensing area is uniformly magnetized along the +z direction. When a reversed\ndomain of length enters the region, the net decreases linearly with . As , , and\nare intrinsic material and device constants, they can be consolidated into a single ′coefficient\nfor simplicity. 𝐿𝐿𝐷𝐷 𝑀𝑀𝑧𝑧 𝐿𝐿𝐷𝐷 𝛼𝛼 𝑀𝑀𝑠𝑠 𝑊𝑊\n𝛼𝛼\nSubstituting the expression for into the formula yields:\n𝑀𝑀𝑧𝑧 𝑉𝑉𝐴𝐴\nIn our implementation, we fix , ,\n𝑉𝑉\na𝐴𝐴nd\n= 𝛼𝛼 𝐼𝐼\nd𝐴𝐴u\n(\n2\n𝐿𝐿\n𝐷𝐷\n−\n𝐿𝐿\n𝑃𝑃\n)\n𝑊𝑊\nrin𝑃𝑃g\n(\n1\n)\nop\n𝐿𝐿\ne𝑃𝑃r\na\ntio𝑃𝑃n , enabling a simplified form:\n𝛼𝛼 𝐿𝐿𝑃𝑃 𝐼𝐼𝐴𝐴\nWhere and are device-specific co\n𝑽𝑽\nn𝑯𝑯sta\n=\nnt\n𝒄𝒄\ns 𝟏𝟏d\n+\nete\n𝒄𝒄\nr𝟐𝟐m\n𝑾𝑾\nin𝑷𝑷e\n𝑳𝑳\nd𝑫𝑫 by fabrication.\nThis lin\n𝑐𝑐\ne1ar dep\n𝑐𝑐\ne2ndence allows the Hall voltage to directly encode the product of domain length\nL and electrode spacing W — the two physical quantities mapped to the convolution input and\nD P\nkernel, respectively— enabling on-device multiplication without the need for peripheral circuits.\nFourier transform implementation\nThe Fourier transform is jointly implemented by the MCA device and computer post-processing.\nThe MCA device performs the physical convolution operation, while the computer performs the\nfinal scaling to complete the Fourier transform. Detailed implementation is provided in (c).\n(a) The MCA device part\nThe Fourier transform begins with the convolution of the input signal, which is physically\nexecuted by the MCA device. The input signal is encoded as the magnetic domain length (L ).\nD\nThe convolution process consists of three steps: multiplication, shifting, and readout. The\nmultiplication mechanism is described in the previous section. The shifting is achieved through\ndomain-wall motion, and the readout is performed by measuring the anomalous Hall voltage\n(V ), which represents the convolution result.\nAHE\n(b) The computer part\nAt the current stage, the final scaling of the AHE voltage to complete the Fourier transform is\nperformed digitally. This step is straightforward, as the MCA already outputs an analog signal\nproportional to the convolution result, and the computer simply applies a multiplicative factor to\nobtain the Fourier result.\nIn the future, this operation could be fully migrated into hardware by integrating low-overhead\nanalog peripheral circuits, such as transconductance amplifiers or programmable gain stages [1],\ndirectly adjacent to the MCA array. These circuits would perform the necessary scaling in real\ntime, eliminating the need for computer-side post-processing and enabling an entirely on-chip\nFourier transform. Importantly, such circuits require only a negligible amount of chip area and\n47 | Pa ge\nenergy, and because the scaling is executed in real time, they do not introduce additional latency\nor reduce throughput [2]. This integration is consistent with standard mixed-signal design\npractices in neuromorphic and in-memory computing systems [3, 4].\nReference\n[1] Razavi, B. Design of Analog CMOS Integrated Circuits, 2nd ed.; McGraw-Hill, 2016.\n[2] Baker, R.J., 2019. CMOS: circuit design, layout, and simulation. John Wiley & Sons.\n[3] Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. et al. Memory devices and applications for in-\nmemory computing. Nat. Nanotechnol. 15, 529–544 (2020).\n[4] Ambrogio, S., Narayanan, P., Tsai, H. et al. Equivalent-accuracy accelerated neural-network training\nusing analogue memory. Nature 558, 60–67 (2018).\n(c) Detailed implementation\nThe Discrete Fourier Transform (DFT) is a mathematical operation that converts a sequence of\ntime-domain samples into a corresponding set of complex-valued frequency-domain coefficients.\nIt can be expressed in a convolution form, enabling its hardware implementation in the MCA\ndevice.\nThe DFT is formally defined as:\n𝑁𝑁−1\n𝑖𝑖2𝜋𝜋\n− 𝑘𝑘𝑛𝑛\n𝑁𝑁\n𝑋𝑋𝑘𝑘 = 𝑥𝑥𝑛𝑛 ∙𝑒𝑒\nWhere are the input time-domain sample𝑛𝑛s= a0nd are the resulting frequency-domain outputs.\nThis eq\n𝑥𝑥\nu𝑛𝑛ation can be algebraically rearranged into\n𝑋𝑋\na𝑘𝑘 form that resembles a convolution:\n𝑖𝑖𝑖𝑖𝑘𝑘2 𝑖𝑖𝑖𝑖𝑛𝑛2 𝑖𝑖𝑖𝑖(𝑘𝑘−𝑛𝑛)2\n− 𝑁𝑁 𝑁𝑁−1 − 𝑁𝑁 𝑁𝑁\nBy introducing the substitu𝑋𝑋t 𝑘𝑘 io=ns 𝑒𝑒 ∑𝑛𝑛=0𝑥𝑥𝑛𝑛 ∙ a𝑒𝑒nd 𝑒𝑒 , the e xpression becomes:\n𝑖𝑖𝑖𝑖𝑛𝑛2 𝑖𝑖𝑖𝑖𝑛𝑛2\n− 𝑁𝑁 𝑁𝑁\n𝑎𝑎𝑛𝑛 = 𝑥𝑥𝑛𝑛 ∙𝑒𝑒 𝑏𝑏𝑛𝑛 = 𝑒𝑒\nThis transformation highlights a convolution ∗stru𝑁𝑁c−tu1re involving a fixed kernel . Importantly,\n\"fixed kernel\" implies that the coe𝑋𝑋ff 𝑘𝑘 ic=ien𝑏𝑏t 𝑘𝑘 s ∑𝑛𝑛=0 a𝑎𝑎r 𝑛𝑛 e 𝑏𝑏i 𝑘𝑘 n − d 𝑛𝑛 e pendent of the input signal and\nremain unchanged. In the MCA device, this feature is leveraged by encoding th𝑏𝑏e 𝑘𝑘 s − e 𝑛𝑛 fixed weights\nthrough predefined electrode spacings ( ) du𝑏𝑏r 𝑘𝑘 in − g 𝑛𝑛 fabrication. 𝑥𝑥𝑛𝑛\nSince DFT outputs are complex-valu\n𝑊𝑊\ned𝑃𝑃, the convolution must be separated into real and\nimaginary components. The input signal, pre-multiplied by the complex phase factor , is\n𝑖𝑖𝑖𝑖𝑛𝑛2\nfirst decomposed into real and imaginary parts. Each part is then individually mappe−d t\n𝑁𝑁\no the\ndomain lengths ( ) in separate MCA devices. The real and imaginary parts of the co𝑒𝑒nvolution\nkernel are similarly mapped to dedicated devices. Convolution operations proceed\nindependently wi𝐿𝐿th 𝐷𝐷 in these MCA devices by sequential domain shifting and AHE readout. After\ncomplet𝑏𝑏in 𝑘𝑘− g 𝑛𝑛 the convolution across MCA devices (the input real/imaginary parts and the kernel\nreal/imaginary parts), the results are recombined by post-multiplying by . The final calculated\nvalues reveal the amplitude and phase information across different frequ∗ency components, as\ndepicted in Fig. R2.\n𝑏𝑏𝑘𝑘\n𝑋𝑋𝑘𝑘\n48 | Pa ge\nWe have revised the Main Text: Line 257 to 259, highlighted in yellow.\nThese two descriptions are provided in the Main Text.\n1. Convolution multiplication: Line 505 to 521.\n2. Fourier transform implementation: Line 594 to 619.\nFig. R2 (Extended Data Fig. 8) | Mapping of DFT to the MCA device. Complex number\nprocessing is performed by decomposing the input signal into real and imaginary parts, each\nhandled by separate MCA devices. Four MCA devices are used in total to process both\ncomponents. The combined output is then post-multiplied by to yield the Fourier-\ntransformed signal . ∗\n𝑏𝑏𝑘𝑘\n𝑋𝑋𝑘𝑘\n2. The accumulated errors during multiple domain wall movements were not addressed. Such\nerrors pose a significant challenge in physical hardware implementations of multiply-accumulate\n(MAC) operations.\nReply:\nWe thank the reviewer for this insightful comment. Our response is divided into three sections:\n1. Accumulated errors during domain-wall movements\n2. Errors in multiply-accumulate (MAC) operations\n3. Effect on algorithm accuracy\nAccumulated errors during domain-wall movements\nThe primary source of error arises from domain-wall pinning, which can cause de-\nsynchronization of domain walls during motion and potentially affect MAC precision.\nWe used MOKE imaging to quantitatively assess domain-wall synchronization during\npropagation. As illustrated in Fig. R3a, a domain is bounded by two domain walls (DWs), and\n49 | Pa ge\ntheir spacing—the domain length (L )—may fluctuate during motion. Thus, the degree of\nD\nsynchronization can be evaluated by measuring the variation in L as the domain moves along\nD\nthe track.\nWe experimentally prepared two representative cases: a wide domain and a narrow domain. The\nresult is shown in Figs. R3b & c. For wide-domain propagation, the measured domain lengths\nexhibit a standard deviation of 0.15 µm (1.9%), and for narrow domains, 0.10 µm (2.1%).\nThese results confirm that the accumulated errors are small.\nFig. R3 | Domain wall synchronization test. (a), MOKE image of a domain. It consists of two\ndomain walls, DW 1 and DW 2. (b), Wide (Top) and narrow (Bottom) domain propagation\nacross MCA device. (c), Domain length vs. Travel Distance.\nRevisions:\nThis section is added into the Supplementary Fig. S3, highlighted in yellow.\nA description is added into the Main Text: From Line 188 to 191, highlighted in yellow.\nErrors in multiply-accumulate (MAC) operations\nThe anomalous Hall voltage (V ) is proportional to the domain length (L ) and the spacing\nAHE D\nbetween pairs of Hall pads (W ), i.e., V L W , which serves as the basis of the physical\nP AHE D P\nMAC operation.\n∝ ×\nIn our experiments, the primary error sources arise from two factors: (i) deviations from the ideal\ndomain length (input variation) and (ii) deviations from the ideal Hall pad spacing (weight\nvariation). The corresponding variations are shown in Figs. 2g and 2h of the Main Text and\n50 | Pa ge\nreproduced in Fig. R4 below. Quantitatively, the average variation in Hall pad spacing is\napproximately 7%, while that in domain length is approximately 2%.\nFig. R4 | Main Text Fig. 2f & 2h. Left figure: Fig. 2f, weight variation. Right figure: Fig. 2h, input variation.\nEffect on algorithm accuracy\nThe observed variations introduce small errors in the MAC function, which could translate into\nalgorithmic deviations. To evaluate their impact, we performed additional experiments as\ndescribed below.\n(a) Input variation\nWe first examined the effect of input variation by comparing the handwritten-digit dataset\nprocessed using the raw experimental data from Fig. 2h (which includes domain-length\ndeviations) with the ideal case. As shown in Fig. R5, the images with and without domain-length\nvariation appear visually identical, as the experimental domain-length fluctuation is only ~2%.\nThis confirms that the essential image features required for accurate recognition are well\npreserved.\nThe corresponding handwritten-digit recognition task, incorporating these nonlinear deviations,\nachieves an accuracy of 98.94%, demonstrating that domain-length variation has a negligible\neffect on the algorithm’s performance.\n51 | Pa ge\nFig. R5 | Input with and without deviation. Left: MNIST image without incorporating\ndomain variation. Right: MNIST image with domain length variation. Both images show a\nclear digit shape and the difference is negligible.\n(b) Weight variation\nIn the original manuscript, we already accounted for variations in the weights by directly using\nthe raw V readouts from different Hall channels as the weight values.\nAHE\nAs discussed in the manuscript, the training process was performed in software, whereas the\nMCA device is designed for inference with fixed weights. Accordingly, the kernel values derived\nfrom the training results are approximated using the nearest experimental V values, as\nAHE\nillustrated below:\nIdeal convolution kernel (training):\n0.1399 -0.289 0.172\n0.489 0.251 -0.521\n0.2173 -0.299 -0.452\nRaw V approximation (experiment):\nAHE\n0.1400 -0.271 0.184\n0.490 0.239 -0.524\n0.2208 -0.305 -0.478\nWe then performed inference using both experimental input and weight variations (raw V\nAHE\nvalues incorporating domain-length and Hall-pad deviations). The resulting recognition accuracy\nremains high at 98.80%, confirming that the errors in MAC operations do not significantly\nimpact the algorithm’s performance.\nRevisions:\nThis section is added into the Supplementary Fig. S10.\nA description is added into the Main Text: From Line 327 to 330.\n52 | Pa ge\n3. In a 2D MTJ-based MCA architecture, are the magnetic domain regions in the strips used as\nconvolution kernel coefficients continuously generated in a certain time sequence, or are they\nfixed within the MTJ region? If they are generated dynamically, how is the simultaneous\nappearance of magnetic domains in the upper and lower strips within the MTJ region controlled?\nIf they are fixed, how can the corresponding magnetic domain widths be modified for different\ncases? Does the read current used to measure the MTJ magnetoresistance have any effect on the\nmagnetization direction of the magnetic domains?\nReply:\nWe thank the reviewer for these thoughtful questions. Our response is divided into three sections:\n1. Dynamical generation and control of kernel coefficients\n2. Simultaneous control of upper and lower magnetic domains\n3. Effect of read current on the magnetization direction\nDynamical generation and control of kernel coefficients\nWe apologize for not making this point clear in the original manuscript. The kernel coefficients\nare dynamically generated and tunable in a defined time sequence.\nAs illustrated in Fig. R6, the kernel coefficients are encoded in the upper magnetic strip. Similar\nto the domain generation method used in the Hall-based MCA, the magnetic domains are\nnucleated and tuned using current-induced Oersted fields generated by a local Oersted channel.\nThe sequence proceeds as follows: the first domain is generated and its width (corresponding to\nthe coefficient value) is adjusted (Fig. R6a); it is then shifted to the first MTJ junction region\n(Fig. R6b). The second domain is subsequently generated (Fig. R6c), after which both domains\nare shifted together into their designated MTJ junctions, and the third domain is generated (Fig.\nR6d). This process continues until all kernel-coefficient domains are deployed. When a new set\nof kernel coefficients is required, the same procedure can be repeated to redefine the domain\npattern.\nThus, the kernel domains are generated sequentially, and they remain tunable and movable\nwithin the MTJ array.\nRevision:\nWe have added this section into Supplementary Fig. S11.\nA description is added into the Main Text: From line 361 to 363.\n53 | Pa ge\nFig. R6 | Kernel coefficient domain generation process. a, The first domain is created and tune\nby Oersted field. b, The first domain is shifted to the MTJ junction region. c, The second domain\nis generated and tuned. d, The first and second domain is shifted to the MTJ junction region.\nAfter this, the third domain is generated.\nSimultaneous control of upper and lower magnetic domains\nThe magnetic domains in the upper (kernel) and lower (input) strips can be controlled\nindependently, as illustrated in Fig. R7. The upper-strip domains are generated as described\nabove, while the lower-strip domains (input data) are produced using the same sequential\ndomain-generation and shifting approach. Independent Oersted field lines and current channels\nallow precise temporal and spatial control of both layers, ensuring synchronized alignment of\ninput and kernel domains within each MTJ junction.\nRevision:\nWe have added this section into Supplementary Fig. S12.\nA description is added into the Main Text: From line 361 to 363.\n54 | Pa ge\nFig. R7 | Simultaneous control of upper and lower magnetic domains.\nEffect of read current on the magnetization direction\nIn the MTJ structure, the read and write currents share the same vertical conduction path through\nthe junction. This current can, in principle, influence the magnetization direction of the free layer\nvia the spin-transfer torque (STT) mechanism, which is the fundamental operation principle of\nSTT-MRAM.\nHowever, the critical current density required for STT-induced switching is approximately 3.9 ×\n10¹⁰ A/m², as reported in the landmark study on perpendicular MTJs [1]. In practice, the read\ncurrent is chosen to be sufficiently large to produce a measurable voltage signal but at least two\norders of magnitude smaller than the critical switching current to prevent any disturbance of the\nmagnetization state.\nTo verify this experimentally, we used our MTJ stack (Fig. R8a) to fabricate MTJ-MCA devices\n(Fig. R8b). Additional details on the MTJ-MCA structure are provided in Comment 4. A read\nvoltage of 20 mV typically provides a clear TMR signal. To examine whether higher read\ncurrents influence the magnetization, we applied read voltages of ±200 mV, corresponding to\ncurrents of approximately ±3.1 mA (current densities of ±7.7 × 10⁶ A/m²). As shown in Fig. R8c,\nno noticeable change is observed in the TMR loops for these two cases.\nAlthough ±STT could, in principle, act as an effective ±z-directional field and shift the TMR\nloops, the nearly perfect overlap of the two loops in Fig. R8c confirms that the read current does\nnot influence the domain magnetization.\nIn conclusion, the applied read current is sufficient to resolve the TMR signal while remaining\nwell below the threshold for disturbing the magnetization direction of the magnetic domains.\n55 | Pa ge\nFig. R8 | Reading current test. (a), MTJ material stack. (b), MTJ-MCA device. (c), TMR loop\nmeasured by high reading voltages (currents).\nReference\n1. Ikeda, S., Miura, K., Yamamoto, H. et al. A perpendicular-anisotropy CoFeB–MgO magnetic tunnel\njunction. Nature Mater 9, 721–724 (2010).\n4. The fixed-weight approach is only suitable for inference, not for the computationally intensive\nand diverse training phase. Additionally, the 2D architecture lacks experimental validation.\nReply:\nWe thank the reviewer for this valuable comment. We fully agree that while the fixed-weight\nMCA device provides substantial advantages for inference, it is not suitable for the training stage,\nwhich requires tunable weights. Therefore, the 2D MTJ-MCA architecture with programmable\nweights is essential for enabling on-chip training.\nTo address this, we have experimentally validated the 2D MTJ-MCA architecture and\ndemonstrated tunable-weight operation suitable for training. The results are presented in two\nparts:\n56 | Pa ge\n1. Fabrication of MTJ-MCA devices on an industry-grade full-MTJ material stack (8-inch wafer)\n2. Experimental demonstration of Read, Write, Shift, and Tunable Weight operations\nFabrication of MTJ-MCA devices on an industry-grade full-MTJ material stack (8-inch\nwafer)\nIn collaboration with a semiconductor foundry, we developed an industry-grade full-MTJ\nmaterial stack on an 8-inch wafer. The wafer photograph and corresponding material stack are\nshown in Fig. R9a and Fig. R9b, respectively. Using this stack, we fabricated test MTJ-MCA\ndevices, as shown in the optical micrograph in Fig. R9c. Each device consists of a magnetic strip\n(the Shifting Channel), a MTJ readout region (the Reading Junction, highlighted by the red\ndashed box), and two Oersted-field writing lines (the Writing Channel). The schematic on the\nright of Fig. R9c illustrates the detailed structure within the red dashed box.\nFig. R9 | Industry-grade full-MTJ material stack 8-inch wafer and MTJ-MCA device. (a),\nA photo of the 8-inch wafer. (b), Magnetic tunneling junction material stack. The layer\nthicknesses are not provided for confidential reasons. (c), MTJ-MCA device. The structure\ninside the red dashed box is illustrated in the right schematic. Red: -Mz domain. Blue: +Mz\n57 | Pa ge\ndomain.\nExperimental demonstration of Read, Write, Shift, and Tunable Weight operations\n(a) Write:\nWriting is performed using the Oersted field, same method as the Hall-MCA device.\nRepresentative MOKE snapshots are shown in Fig. R10a.\n(b) Read:\nReading is performed using tunneling magnetoresistance (TMR), which, analogous to the\nanomalous Hall effect, is proportional to the net Mz. The measured TMR loop of the MTJ-MCA\ndevice is shown in Fig. R10b. The zoomed-in region (right panel) reveals distinct resistance\nsteps, each corresponding to a convolution input value, with several hundred inputs achieved\nacross the full loop.\n(c) Shift:\nShifting is realized through spin–orbit torque (SOT)-driven domain-wall motion, employing the\nsame mechanism as in the Hall-MCA. MOKE snapshots are provided in Fig. R10c.\nFig. R10 | Demonstration of Read, Write, and Shift and tunable weight in the MTJ-MCA\ndevice. (a), MOKE images of the Domain Writing process. Green shade: Oersted field channel.\nYellow arrow: Applied current direction. A current is applied, and a +z domain is created,\nlocation mark by the blue arrow. (b), TMR loop. Each step corresponds to a convolution input.\n58 | Pa ge\nRight figure: Zoom-in plot of the red box region. (c), MOKE images of domain wall motion.\nYellow shade: Reading junction. t1 to t6 represent the time stamps. Black arrow denotes the\nmotion direction. d(i), TMR loops by applying different junction voltages. Weight is obtained\nby ( ). d(ii), Plot summarizing the measured and at different applied voltages.\n𝑅𝑅𝑎𝑎𝑎𝑎−𝑅𝑅𝑎𝑎\nInset: w𝑅𝑅𝑎𝑎eight values ( ). Currently, 15 different w𝑅𝑅e𝑝𝑝ights 𝑅𝑅ar𝑎𝑎e𝑝𝑝 obtained.\n𝑅𝑅𝑎𝑎𝑎𝑎−𝑅𝑅𝑎𝑎\n(d) Tunable weights: 𝑅𝑅𝑎𝑎\nIn the Hall-MCA, the convolution weights are fixed by the geometric width between pairs of\nHall pads. In contrast, the MTJ-MCA enables tunable weights, achieved by modulating the TMR\nratio, defined as , where denote the resistances corresponding to parallel and\n𝑅𝑅𝑎𝑎𝑎𝑎−𝑅𝑅𝑎𝑎\nantiparallel alignmen\n𝑅𝑅𝑎𝑎\nts of the top\n𝑅𝑅\na𝑝𝑝n d\n( 𝑅𝑅\nb𝑎𝑎o𝑝𝑝tt\n)\nom CoFeB layers, respectively.\nBy applying different junction voltages, the TMR loops can be rescaled. As shown in Fig.\nR10d(i), each junction voltage produces a distinct TMR loop that differs only in its TMR ratio.\nIn other words, these loops can be transformed into one another by a multiplicative factor—\ncorresponding to the definition of a weight.\nAs discussed in the (b) Read section, each point on the TMR loop represents a convolution input\nvalue. By adjusting the TMR ratio, the multiplicative factor (weight) of each input can thus be\ntuned. For instance, Point 1 at 50 mV transforms into Point 2 at 500 mV, effectively multiplying\nthe input by a scaling factor (weight). Measurements under multiple junction voltages yielded a\nwide range of tunable weights, summarized in Fig. R10d(ii).\nThe underlying mechanism is that increasing the junction voltage (and thus the electric field)\nallows deeper, un-spin-polarized electronic states to contribute to tunneling, thereby reducing the\nTMR ratio. We note that this voltage-controlled method is simpler than the originally proposed\nscheme in the Main Text, where the weights are tuned by varying the magnetization of the top\nCoFeB layer. However, the voltage-controlled range is limited, as higher voltages may induce\nbarrier breakdown. Therefore, the magnetization-based approach remains the preferred and more\nscalable method for future implementations.\nIn summary, we have experimentally validated the 2D MTJ-MCA architecture.\n5. ln line 104 and 105, the authors depict ‘I_H is the applied current flowing along the +x axis,\nL_D is the domain length aligned along the –z direction’. It seems not the case as illustrated in\nFig. 1b.\nReply:\nWe thank the reviewer for pointing out this issue and apologize for the confusion.\nThe clarification is as follows:\nIn Fig. 1b, the schematic shows I appearing to flow along the –x direction; however, the current\nH\npath forms a loop, and within the device channel, I indeed flows along the +x direction.\nH\n59 | Pa ge\nThe parameter L represents the domain length measured along the x-axis, with the domain\nD\nmagnetization oriented along the –z direction.\nWe have revised the text to read:\n“I is the applied current flowing along the +x axis of the device, and L is the domain length in\nH D\nthe x direction with the domain magnetization aligned along the –z direction.”\nThis correction has been updated in Lines 107 to 109 of the Main Text.\nFig. R11 | Fig. 1b in the manuscript.\n6. In Equation 1, the length of the domain wall is not taken into consideration. Will the DW\nlength influence the final convolutional result?\nReply:\nWe thank the reviewer for this insightful question. The length of the domain wall (DW) does not\ninfluence the final convolution result. The reasons are as follows:\nThe convolution operation is based on the anomalous Hall effect (AHE). As described in the\nmanuscript, Equation (1) expresses the relationship between the domain length (L ) and the AHE\nD\nvoltage:\nAs the reviewer noted, the DW leng 𝑉𝑉𝐴𝐴th𝐴𝐴 𝐴𝐴is\n=\nno\n𝛼𝛼\nt\n𝐼𝐼\ni𝐴𝐴n\n(\n2\n𝐿𝐿\n𝐷𝐷\n−\n𝐿𝐿\n𝑃𝑃\n)\n𝑊𝑊\ntlu𝑃𝑃de\nd\nin\nt\nhe\nequation. This is because the A\n(\nH\n)\nsignal is proportional to the net out-of-plane magnetization (Mz).\nAccording to Reference [1], the anomalous Hall resistivity ( ) is related to Mz by\n𝜌𝜌𝐴𝐴𝐴𝐴𝐴𝐴\nWhere is a material-dependent constan\n𝜌𝜌\nt.𝐴𝐴 T𝐴𝐴h𝐴𝐴e\n=\nref\n𝑅𝑅\no𝑠𝑠r\n𝑀𝑀\ne, 𝑧𝑧a zero Mz gives rise to a zero AHE signal.\nWithin\n𝑅𝑅\nth𝑠𝑠e DW, the local magnetization continuously rotates from +z to –z (or vice versa),\nresulting in a net Mz of zero, as illustrated in Fig. R12. Consequently, the DW does not\ncontribute to the AHE signal and therefore has no influence on the convolution results.\n60 | Pa ge\n[FIGURE REDACTED]\nFig. R12 | Domain wall magnetic moment. Figure adapted from [2]\nReference\n[1] Nagaosa, N., Sinova, J., Onoda, S., MacDonald, A.H. and Ong, N.P., 2010. Anomalous hall effect.\nReviews of modern physics, 82(2), pp.1539-1592.\n[2] Kézsmárki, I., Bordács, S., Milde, P. et al. Néel-type skyrmion lattice with confined orientation in the\npolar magnetic semiconductor GaV4S8. Nature Mater 14, 1116–1122 (2015).\n7. Since the domain motion is driven by SOT of the underlying heavy metal，will the external\nmagnetic field used for AHE signal read out affect the domain motion?\nReply:\nWe thank the reviewer for this important question and apologize for any confusion caused by our\nearlier description. The experimental procedure consists of three sequential stages:\n1. Domain creation: Magnetic domains are generated using the current-induced Oersted field.\n2. Domain shifting: The domains are then displaced by spin–orbit torque (SOT).\n3. AHE signal readout: The anomalous Hall voltage is measured after the domain displacement.\nImportantly, no external magnetic field is applied during either the domain motion or AHE\nreadout stages.\nThe AHE signal measurement does not require a magnetic field, as it is directly proportional to\nthe net out-of-plane magnetization according to (discussed in the last comment).\n𝜌𝜌𝐴𝐴𝐴𝐴𝐴𝐴 = 𝑅𝑅𝑠𝑠𝑀𝑀𝑧𝑧\n8. In Fig. 2f, the y-intercept of V_AHE versus W_P seems not zero (about 0.5 mV). What is the\nreason and can it be adjusted or eliminated?\nReply:\nWe thank the reviewer for this careful observation. The non-zero y-intercept of V versus W\nAHE P\narises from slight misalignment of the Hall pads during fabrication. We clarify the origin and\ndescribe possible mitigation methods below. Our response is divided into two sections:\n1. Misalignment and non-zero y-intercept of V\nAHE\n2. Mitigation methods\n61 | Pa ge\nMisalignment and non-zero y-intercept of V\nAHE\nAs shown in Fig. R13a, during readout, a longitudinal current is applied and the transverse\nvoltage is measured. In an ideally aligned configuration, only the transverse electric field (Ey)\nfrom the anomalous Hall effect contributes to the signal.\nHowever, if the Hall pads are slightly misaligned, the voltmeter also detects a small component\nof the longitudinal electric field (Ex) generated by the read current. This mixing introduces an\noffset in the measured V . An example is shown in Fig. R13b, where the offset exceeds 2 mV.\nAHE\nIn the ideal case, the V loop would be centered at V=0.\nAHE\nFig. R13 | Aligned and mis-aligned Hall pads and offset of V . (a), AHE measurement. A\nAHE\nlongitudinal current is applied and the transverse voltage is measured. Only Ey is measured for\naligned Hall pads. An additional Ex is measured for the mis-aligned one, which creates an offset\nof in the V . (b), An example of the V loop from the mis-aligned device.\nAHE AHE\nMitigation methods\n62 | Pa ge\nTo mitigate or eliminate this offset, we employed higher-resolution lithography for defining the\nHall pad pattern, as shown in Fig. R14, where the offset is nearly removed.\nFurther improvement can be achieved through foundry-level fabrication, where advanced stepper\nlithography and automated overlay correction routinely achieve alignment tolerances below 5 nm,\neffectively eliminating such offsets.\nFig. R14 | AHE measurement of device with improved fabrication. The alignment is\nimproved and the offset is nearly zero.\nEven without fabrication upgrades, this offset can be electronically compensated using a\ndifferential amplifier or offset-cancellation circuit. For example, if 1000 Hall pad pairs each\nexhibit an average offset of ~0.5 mV, the total accumulated offset would be ~0.5 V. A simple\ndifferential circuit can subtract this voltage in real time. Such offset-cancellation techniques are\nstandard in Hall sensors and magnetic memory readout systems [1, 2], requiring only minimal\npower (microwatts) and transistor count, and they operate well within the bandwidth of magnetic\ndevice readout [3].\nReference\n[1] Ramsden, E., 2011. Hall-effect sensors: theory and application. Elsevier.\n[2] Popovic, R.S., 2003. Hall effect devices. CRC Press.\n[3] Carusone, T.C., Johns, D.A. and Martin, K.W., 2011. Analog integrated circuit design. John Wiley &\nSons.\n9. In Fig. 2h, the legend of the picture is incomplete with the absence of corresponding symbol or\ncolor.\nReply:\nWe thank the reviewer for the careful review and for helping improve the quality of our\nmanuscript.\n63 | Pa ge\nThe missing legend in Fig. 2h has been added. The revised figure is provided below as Fig. R15\nfor the reviewer’s reference and has also been updated in the Main Text.\nFig. R15 | Revised Fig. 2h to include the complete legend. All colors are labeled.\n10. In Fig. 3c, the distinction of fabricated W_P is not evident. Will it influence the mapping to\nconvolutional kernel?\nReply:\nWe thank the reviewer for the careful examination of our manuscript. The distinction in the\nfabricated W values is sufficient for accurate mapping to the convolution kernel.\nP\nIn Fig. 3c, the device is used to perform the short-time Fourier transform (STFT). The designed\nW sequence for this device is 6–8–6–8–6–8–6 μm, as labeled in Fig. R16a(i). The\nP\ncorresponding measured V values are shown in Fig. R16a(ii). The V – W dependence\nAHE AHE P\nconfirms the intended mapping between W and the convolution kernel coefficients.\nP\nAlthough small variations exist among the measured V values, this level of precision is\nAHE\nsufficient for algorithmic implementation. As demonstrated in Fig. 3 of the manuscript, the\nFourier transform was performed using the raw data from Fig. R16a(ii), yielding accurate\nreconstruction of the Fourier amplitudes (Fig. R16b(i); corresponding to Fig. 3c(iv) in the Main\nText). A zoomed-in view of the boxed region [Fig. R16b(ii)] shows only small fluctuations due\nto fabrication variations in W , which do not affect the overall transform accuracy.\nP\nRevision:\nWe have added this section into Supplementary Fig. S8.\nA description is added into the Main Text: From Line 261 to 263.\n64 | Pa ge\nFig. R16 | Mapping of convolution kernel and Fourier transform result. (ai), Fig. 3c device\nmicroscope image. This device is designed to have two W , 6 μm and 8 μm. (aii), Measured\nP\nV of the 7 W . (bi), Fourier transformed result. (bii), Zoom-in plot of the black box region in\nAHE P\n(bi).\n11. In Fig. 4aiii, the red, blue and purple squares can coexist simultaneously in the crossing area\nor is just a phenological illustration of all possible cases?\nReply:\nWe thank the reviewer for the careful review and apologize for not making this point sufficiently\nclear in the original manuscript. The red, blue, and purple squares in Fig. 4aiii can indeed coexist\nsimultaneously in the crossing area. To clarify this, we have redrawn Fig. 4aiii as Fig. R17,\nfollowing the same color code and the definitions of L , L , and W.\nDX DY\nThe top and bottom magnetic strips overlap in the junction region (crossing area), as illustrated\nin Fig. R17a(i). Within this region, each magnetic layer contains two domains, represented by\nred and blue rectangles in Fig. R17a(ii). As shown in Fig. R17b, four possible domain\nconfigurations can exist in the overlapping area:\n1. Region : Top:-z, Bottom:-z\n①\n65 | Pa ge\n2. Region : Top:+z, Bottom:-z\n3. Region : Top:+z, Bottom:+z\n②\n4. Region : Top:-z, Bottom:+z\n③\nHere, the re④d squares correspond to overlapping (–z, –z) domains (region ), the blue squares\nto overlapping (+z, +z) domains (region ), and the purple squares to (+z, –z) or (–z, +z)\ndomains (region ). ①\n③\nIn summary, the red, blue, and purple regions represent the coexisting domain configurations of\n②④\nthe top and bottom layers within the crossing area. They collectively describe one possible\nmagnetic state; different configurations can occur if the domain positions or lengths (L , L )\nDX DY\nare varied—for example, when the top domain becomes entirely –z in the overlapping region.\nRevision:\nWe have added this section into Supplementary Fig. S13.\nA description is added into the Main Text: From line 365 to 366.\nFig. R17 | Schematic of the MTJ-MCA. (ai), The MTJ-MCA schematic. Blue: +z domain. Red:\n-z domain. Yellow: Junction region (crossing area). Strip width: W. Top -z domain length: .\nBottom -z domain length: . (aii), Top and bottom domain configuration at the crossing area.\n𝐿𝐿𝐷𝐷,𝑋𝑋\n(b), Detailed view of the crossing area. It can be divided into four regions. Red square (region\n: Top:-z Bottom:-z; Pu𝐿𝐿rp 𝐷𝐷 l ,𝑌𝑌 e square (region : Top:+z Bottom:-z; Blue square (region :\nTop:+z Bottom:+z; Purple square (region : Top:-z Bottom:+z. The corresponding 3D view\na①re) shown. ②) ③)\n④)\n12. As claimed in line 362 and 363, energy consumption per operation in the 1D Hall-based\nMCA is primarily due to the large current densities required to drive high-speed domain wall\n66 | Pa ge\nmotion. Will adoption of magnetic solitons like skyrmions or driving method like spin wave in\ninsulators facilitate reduction of energy consumption?\nReply:\nWe thank the reviewer for this insightful question. Our response is divided into two sections:\n1. Adoption of magnetic solitons such as skyrmions\n2. Adoption of driving methods such as spin waves in insulators\nAdoption of magnetic solitons such as skyrmions\nMagnetic solitons, such as skyrmions, are typically much smaller than domain walls—down to a\nfew nanometers in diameter, as experimentally demonstrated in Reference [1]. Their topological\nspin texture also makes them significantly less sensitive to pinning, allowing them to bypass\ndefects [2,3] or move smoothly along grain boundaries [4,5].\nAs a result, skyrmions can be driven with minimum current densities of ~10² A cm⁻², which are\n3–6 orders of magnitude lower than those required for domain-wall motion (10⁵–10⁸ A cm⁻²) [6–\n10].\nIn summary, the use of magnetic solitons such as skyrmions could substantially reduce energy\nconsumption due to their smaller size, lower pinning sensitivity, and dramatically lower drive\ncurrent density.\nAdoption of driving method such as spin wave in insulators\nWe consider two cases:\n(a) Ferromagnetic (FM) insulator\nIn a purely FM insulator, domain walls or other spin textures can be driven by spin waves.\nHowever, FM insulators generally lack a strong electrical readout mechanism compared to\nmetallic ferromagnets such as CoFeB, which exhibit pronounced anomalous Hall and tunneling\nmagnetoresistance signals. This limits the ability to electrically detect or read out the resulting\nstates.\n(b) FM insulator as layer below CoFeB\nAlternatively, a hybrid stack such as FM insulator/CoFeB/MgO (e.g., YIG or TmIG as the\ninsulator) can be used. In this case, spin waves generated in the insulator can transfer angular\nmomentum across the interface and drive domain walls or skyrmions in the CoFeB layer. Since\nmagnons carry spin angular momentum of ħ, compared to ħ/2 for electrons, this mechanism is\nintrinsically more efficient.\nExperimentally, magnon-driven domain-wall motion has been demonstrated in Bi-doped YIG,\nwith an upper-bound energy consumption of ≈ 4 pJ to move a domain wall by 15 μm [11]. In\ncomparison, our current device requires ≈ 143 pJ for the same displacement, indicating that spin-\nwave-based driving can indeed reduce energy consumption.\nHowever, this high efficiency is achieved when the spin wave and domain wall coexist in the\nsame FM insulator. In a bilayer system (FM insulator/CoFeB), the spin wave must transmit\n67 | Pa ge\nthrough the interface to exert torque on the CoFeB, reducing overall efficiency. To our\nknowledge, such interfacial magnon-driven motion has not yet been experimentally quantified,\nthough it is reasonable to expect improved energy efficiency relative to current-driven domain-\nwall motion.\nIn summary, both approaches—using magnetic solitons such as skyrmions and adopting spin-\nwave-based driving in magnetic insulators—offer promising routes to reduce the energy\nconsumption required for high-speed domain-wall motion in future MCA devices.\nReference\n[1] 10. Romming, N., Kubetzka, A., Hanneken, C., von Bergmann, K. and Wiesendanger, R., 2015.\nField-dependent size and shape of single magnetic skyrmions. Physical review letters, 114(17), p.177203.\n[2] C. Reichhardt, D. Ray, and C. J. Olson Reichhardt, Collective Transport Properties of Driven\nSkyrmions with Random Disorder, Phys. Rev. Lett. 114, 217202 (2015).\n[3] J. Iwasaki, M. Mochizuki, and N. Nagaosa, Current induced skyrmion dynamics in constricted\ngeometries, Nat. Nanotechnol. 8, 742 (2013).\n[4] A. Salimath, A. Abbout, A. Brataas, and A. Manchon, Current-driven skyrmion depinning in magnetic\ngranular films, Phys. Rev. B 99, 104416 (2019).\n[5] X. Gong, H. Y. Yuan, and X. R. Wang, Current-driven skyrmion motion in granular films, Phys. Rev.\nB 101, 064421 (2020).\n[6] Jonietz, F. et al. Spin transfer torques in MnSi at ultralow current densities. Science 330, 1648–1651\n(2010).\n[7] Yu, X., Kanazawa, N., Zhang, W. et al. Skyrmion flow near room temperature in an ultralow current\ndensity. Nat Commun 3, 988 (2012).\n[8] Yamanouchi, M., Chiba, D., Matsukura, F. & Ohno, H. Current-induced domain-wall switching in a\nferromagnetic semiconductor structure. Nature 428, 539–542 (2004).\n[9] Thomas, L., Moriya, R., Rettner, C. & Parkin, S. Dynamics of magnetic domain walls under their own\ninertia. Science 330, 1810–1813 (2010).\n[10] Togawa, Y. et al. Current-excited magnetization dynamics in narrow ferromagnetic wires. J. Appl.\nPhys. 45, L683–L685 (2006).\n[11] Fan, Y., Gross, M.J., Fakhrul, T. et al. Coherent magnon-induced domain-wall motion in a magnetic\ninsulator channel. Nat. Nanotechnol. 18, 1000–1004 (2023).\n68 | Pa ge"}, {"round": 2, "reviewer_comments": {"reviewer_1": "Overall, the authors have carefully addressed my major concerns and strengthened the work with new data, making the revised manuscript more rigorous. The work highlights the potential of MCA for convolutional computing, especially in energy and area efficiency, contributing to emerging computing paradigms. While most issues are resolved, I have a few minor questions for further clarification or refinement:\n1. While the authors correctly note that advanced material systems (e.g., ferrimagnets, SOC materials) could enhance performance, the challenges of integrating these into a functional MCA platform, such as interface engineering and read/write compatibility, are not clearly addressed. A brief acknowledgement of these integration challenges as a direction for future work would strengthen the discussion and enhance its rigor.\n2. The conclusion section primarily highlights the benefits and potential research directions of the MCA, but provides limited discussion on its inherent limitations (e.g., energy consumption, constraints of the 1D design, stochastic DW motion). Could a short discussion be added to the discussion or conclusion addressing the current or potential limitations and the challenges that need to be overcome for using MCA as a compute-in-memory device?\n3. Some figure captions (for example, Fig. 1c) appear quite lengthy and largely restate content already covered in the main text. Could these captions be rephrased or more concise?", "reviewer_2": "Authors have successfully addressed the prior review comments. I am glad with the current version of the manuscript and recommend acceptance.", "reviewer_3": "The authors have adequately addressed the points raised by the referees. I therefore recommend acceptance of the manuscript in its current form."}, "author_response": "We sincerely thank the reviewer for the positive assessment and the constructive suggestions. We have carefully addressed each point in the detailed responses below and revised the manuscript accordingly.\nDetailed point-by-point responses are provided below:\n1. While the authors correctly note that advanced material systems (e.g., ferrimagnets, SOC materials) could enhance performance, the challenges of integrating these into a functional MCA platform, such as interface engineering and read/write compatibility, are not clearly addressed. A brief acknowledgement of these integration challenges as a direction for future work would strengthen the discussion and enhance its rigor.\n2. The conclusion section primarily highlights the benefits and potential research directions of the MCA, but provides limited discussion on its inherent limitations (e.g., energy consumption, constraints of the 1D design, stochastic DW motion). Could a short discussion be added to the discussion or conclusion addressing the current or potential limitations and the challenges that need to be overcome for using MCA as a compute-in-memory device?\nReply:\nWe thank the reviewer for these valuable suggestions. We have substantially revised the\nDiscussion and Conclusion section to address both the material integration challenges and the\nlimitations and challenges of the MCA platform. For clarity, the added discussion is shown in red\nfont below.\n1 | Pa ge\nDiscussion and Conclusion\nIn conclusion, we demonstrate a hardware platform capable of performing convolution through\nsequential magnetic DW motion, with applications spanning deep learning, computer vision, and\nsignal and image processing. Benchmarking results reveal performance enhancements of three to\nfive orders of magnitude over 28 nm CMOS technology. By directly mapping magnetic-domain\ndynamics onto convolutional operations, the MCA unifies data storage (via magnetic domains)\nand computation (via DW motion and Hall-voltage readout) within a nonvolatile physical\nframework, establishing a spintronic compute-in-memory architecture. The experimental\nrealization of convolution—a core building block of modern machine learning and signal\nprocessing—thus represents a concrete step toward general-purpose computing platforms beyond\nBoolean logic.\nDespite these advancements, the present MCA prototype exhibits several limitations that define\nkey directions for future development. Pinning-induced variations lead to relatively high energy\nconsumption and occasional stochasticity in DW motion, underscoring the need for improved\nmaterial uniformity and engineered pinning profiles. The current one-dimensional, fixed-weight\ndesign restricts kernel programmability; implementing a two-dimensional array with electrically\ntunable MTJ weights will be essential for general-purpose compute-in-memory functions. As\ndevice density increases, additional system-level challenges—including inter-track crosstalk,\nmodest Hall-signal margins, TMR variability across MTJ arrays, and fabrication-yield\nconstraints—must also be addressed to achieve large-scale integration.\nLooking ahead, two natural directions emerge. First, the MCA architecture will need to scale in\nboth dimension and functionality to accommodate larger training datasets and more complex\nworkloads, such as those required by models like ChatGPT³⁴. Extending the design into a two-\ndimensional MTJ-MCA array with programmable weights provides a logical pathway toward\nversatile convolutional kernels and on-chip learning, and the MCA’s simple DW-based racetrack\ngeometry³⁵ facilitates integration atop existing CMOS platforms.\nSecond, advanced material systems offer promising opportunities to enhance performance.\nStrong-DMI multilayers²¹ and ferrimagnets²⁴ could enable sub-10 nm domain scaling²¹ and\noperational speeds approaching ~1 THz²⁴, while optimization of pinning landscapes may further\nreduce DW driving energies to the attojoule regime²². However, realizing these benefits requires\novercoming nontrivial materials-integration challenges. In ferrimagnets, the angular-momentum\ncompensation point is highly sensitive to composition and temperature²⁴, and deviations can\nsuppress DW velocity and degrade writing efficiency. In strong-DMI multilayers²¹, large DMI\nmay stabilize skyrmion textures4,5,6 rather than the alternating-domain configuration required for\nMCA operation, necessitating careful tuning of anisotropy, DMI, exchange, and dipolar energies.\nMoreover, compatibility with MTJ stacks and CMOS back-end-of-line processes imposes\nstringent constraints on interface engineering, thermal management, and interconnect routing to\npreserve high TMR readout and robust sensing. Addressing these material, device, and\nintegration challenges will be essential for translating the performance potential of advanced\nstacks into practical MCA hardware.\nTogether, these results establish the MCA as a promising pathway toward scalable, energy-\nefficient spintronic computing, offering a solid foundation for future advances in compute-in-\nmemory hardware.\n2 | Pa ge\n3. Some figure captions (for example, Fig. 1c) appear quite lengthy and largely restate content\nalready covered in the main text. Could these captions be rephrased or more concise?\nReply:\nWe thank the reviewer for this valuable suggestion. We have refined all figure captions to\nimprove conciseness and clarity, and the revised captions are provided below for the reviewer’s\nreference.\na b\nc d\nFig. 1 | Operating principles of the MCA. (a) MCA architecture comprising serially connected magnetic\nunit cells. (b) Structure of a single unit cell. Red and blue rectangles denote domains with –z and +z\nmagnetization. Gold strips and pads indicate AHE readout electrodes. The domain length is , the\nelectrode contact length is , and the spacing between Hall-electrode pairs is . During readout, a\ncurrent flows along the conduit and the transverse Hall voltage is measured. (c) Schem𝐿𝐿a 𝐷𝐷 tic of\nMCA-based convolution. Th𝐿𝐿e 𝑃𝑃 input domains (top) and kernel coefficients (second r𝑊𝑊ow 𝑃𝑃 ) are represented by\ndiscrete 𝐼𝐼𝐻𝐻 values of and . The device-level cartoon (third row) il𝑉𝑉lu 𝐻𝐻 strates stationary electrodes and\nsequential domain shifting. The resulting Hall-voltage sequence (bottom) corresponds to the convolution\noutput. (d) DW sh𝐿𝐿if 𝐷𝐷 ting d𝑊𝑊riv 𝑃𝑃 en by SOT. A charge current generates a transverse spin current , which\napplies a torque on the DWs and translates the domains along the track.\n𝑗𝑗 𝑗𝑗𝑠𝑠\n3 | Pa ge\na d f\n(i)\n(ii)\nb\ng\n(iii)\ne\nc\n(i)\nh\n(ii) (iii) (iv)\n(v) (vi) (vii)\nFig. 2 | Experimental realization of the MCA. (a) Schematic of domain nucleation using current-\ninduced Oersted fields. (b) Schematic of SOT-driven DW shifting. (c) Optical micrograph of a fabricated\nMCA device. (d) Experimental demonstration of domain nucleation and size control. (i) Setup for\ngenerating domains. (ii) Creation of a 32 µm +z domain using a 200 mA, 1 ms pulse. (iii) Domain-length\ntuning: pulses of –80 mA, –90 mA, and –100 mA (1 ms) yield =14, 11, and 6 µm, respectively. Scale\nbar: 20 µm. (e) Experimental demonstration of sequential domain shifting. (i) Setup for applying SOT-\ndriven shifting pulses. (ii) Initial domain position. (iii–vi) St𝐿𝐿e 𝐷𝐷 pwise 20 µm displacement per pulse,\nshifting domains into the Hall-channels. (vii) Continued pulses translate the full domain sequence across\nthe Hall-channels. Scale bar: 20 µm. (f) AHE-based convolution granularity versus at fixed =14\nµm. Shaded color bands indicate error bars. Insets: device region with varying and measurement\nsetup. Scale bar: 14 µm. (g) AHE-based convolution granularity versus at fixed 𝑊𝑊𝑃𝑃 =8 µm. 𝐿𝐿In 𝐷𝐷 sets:\nmeasurement setup and snapshots of domains with different . Scale bar: 20 µm. (𝑊𝑊h) 𝑃𝑃 Linear dependence\nof on for various electrode spacings (10, 8, 7, 6, and 3 µm).\n𝐿𝐿𝐷𝐷 𝑊𝑊𝑃𝑃\n𝐿𝐿𝐷𝐷\n𝑉𝑉𝐴𝐴𝐻𝐻𝐴𝐴 𝐿𝐿𝐷𝐷 𝑊𝑊𝑝𝑝\n4 | Pa ge\na b c\nd\n(i) (iii)\n(ii) (iv)\ne\nf g\nh i j\nFig. 3 | Algorithm implementation on the MCA. (a) Conceptual illustration of the STFT. The input\nsignal is segmented and Fourier-transformed. (b) Schematic of 4-point STFT using a 7-Hall-pad MCA\ndevice. Input values map to , and kernel coefficients to . Sequential domain shifting and\nAHE readout yield Fourier components . (c) Magnetic-domain snapshot as domains shift across the 7-\nHall-pad device. Scal𝑎𝑎e 𝑛𝑛 bar: 14 µ𝐿𝐿m 𝐷𝐷 . (d) Experimental STFT d𝑏𝑏e 𝑘𝑘 m − o 𝑛𝑛 nstr𝑊𝑊at 𝑃𝑃 ion. (i) Initial segment of . (ii)\nFinal segment of . (iii) Combined in𝑋𝑋p 𝑛𝑛 ut . (iv) MCA-generated STFT output showing the\ntemporal evolution of both components. (e) CNN flow diagram for MNIST handwritten digit reco𝑓𝑓g(𝑡𝑡n)ition.\n(f) Implementatio𝑔𝑔n (o𝑡𝑡f) a 3×3 convolutional k𝑓𝑓er(n𝑡𝑡e)l +us 𝑔𝑔in(g𝑡𝑡 )three MCA devices, each encoding a 1×3 kernel\nvia configurations (grey dots). Pixel intensities map to . Scale bar: 20 µm. (g) Confusion matrix for\nthe MNIST task, showing 98% average accuracy. (h) Left: 256×256 greyscale ‘Cameraman’ image.\nRigh𝑊𝑊t: 𝑃𝑃 Intensity profile along a line cut; x-axis denotes p𝐿𝐿ix 𝐷𝐷 el position. (i) Experimental setup for edge\ndetection using the kernel [1, 0, –1] encoded via , with pixel intensities mapped to . Scale bar: 20\nµm. (j) Edge-detected image produced using the MCA.\n𝑊𝑊𝑃𝑃 𝐿𝐿𝐷𝐷\n5 | Pa ge\na\n(i) (ii\n(iii) b\nFig. 4 | Two-dimensional MTJ-based MCA architecture and benchmarking against CMOS. (a)\nSchematic of the 2D MTJ-based MCA (MTJ-MCA). (i) Conceptual design using crossing arrays of MTJs.\nGrey arrows indicate domain-shifting currents; yellow arrows denote vertical readout through the MTJs.\n(ii) Schematic of a single MTJ junction. (iii) Top view of an MTJ junction and overlapping magnetic\nstrips. Red and blue regions represent –z and +z magnetizations, with domain lengths and\nalong the y- and x-directed strips and junction width . Overlap regions highlight different domain\ncombinations. (b) Benchmarking comparison between the 1D Hall-based MCA, the 2D M 𝐿𝐿T 𝐷𝐷 J , - 𝑌𝑌 MCA, 𝐿𝐿 a 𝐷𝐷 n ,𝑋𝑋 d\nCMOS (28 nm). The plot uses a logarithmic scale. The fig𝑊𝑊ure of merit is defined as FOM=T/(AE).\nReviewer #2 (Remarks to the Author):\nAuthors have successfully addressed the prior review comments. I am glad with the current\nversion of the manuscript and recommend acceptance.\nReply:\nWe sincerely thank the reviewer for the positive assessment and for recommending acceptance.\nWe appreciate your time and valuable feedback throughout the review process.\n6 | Pa ge\nReviewer #3 (Remarks to the Author):\nThe authors have adequately addressed the points raised by the referees. I therefore recommend\nacceptance of the manuscript in its current form.\nReply:\nWe sincerely thank the reviewer for the positive assessment and for recommending acceptance.\nWe appreciate your time and valuable feedback throughout the review process.\n7 | Pa ge"}, {"round": 3, "reviewer_comments": {"reviewer_1": "The authors have answered my questions. I am happy to recommend its publication in Nature Communications."}, "author_response": ""}]

Decision letter