Pruning random resistive memory for optimizing analog AI

Domain: neuroscience
Published: 2026-01-10
Editorial outcome: major_revision

Abstract
The rapid expansion of AI models has intensified concerns over energy consumption. Analog in-memory computing with resistive memory offers a promising, energy-efficient alternative, yet its practical deployment is hindered by programming challenges and device non-idealities. Here, we propose a software-hardware co-design that trains randomly weighted resistive-memory neural networks via edge-pruning topology optimization. Software-wise, we tailor the network topology to extract high-performing sub-networks without precise weight tuning, enhancing robustness to device variations and reducing programming overhead. Hardware-wise, we harness the intrinsic stochasticity of resistive-memory electroforming to generate large-scale, low-cost random weights. Implemented on a 40 nm resistive memory chip, our co-design yields accuracy improvements of 17.3% and 19.9% on Fashion-MNIST and Spoken Digit, respectively, and a 9.8% precision-recall AUC improvement on DRIVE, while reducing energy consumption by 78.3%, 67.9%, and 99.7%. We further demonstrate broad applicability across analog memory technologies and scalability to ResNet-50 on ImageNet-100.

Introduction
Recent advances in artificial intelligence (AI), particularly deep learning, have revolutionized natural language and image processing, enabling capabilities that increasingly rival human intelligence1,2. However, the trajectory toward larger, more sophisticated models necessitates immense computational resources, raising significant concerns regarding energy consumption and environmental sustainability3,4.

Revisiting analog computing—a technique predating digital architectures-presents a compelling solution5. By harnessing emerging analog devices such as resistive memory6–10, analog computing processes informative analog signals directly, enhancing energy efficiency in three fundamental ways11–17. First, traditional digital systems physically separate memory and processing units, incurring substantial latency and energy overheads due to frequent data shuttling-the so-called von Neumann bottleneck18–23. In contrast, analog resistive memory collocates storage and processing within the same physical device24–27. Second, as complementary metal-oxide-semiconductor (CMOS) transistors approach physical scaling limits, the pace of Moore’s law is slowing28–31. Unlike CMOS, analog resistive memory offers high scalability and stackability12,32–36. Third, while standard digital memory (e.g., dynamic random access memory, DRAM) is volatile, non-volatile analog resistive memory retains data without a continuous power supply37–45.

Despite these advantages, emerging analog computing systems face persistent hurdles: programming non-idealities and high programming costs. Analog resistive memory exhibits inherent stochasticity and nonlinearity during programming46–53. Furthermore, the energy and time overheads associated with programming these devices are substantially higher than those of their digital counterparts54–56. Consequently, harnessing the efficiency of analog computing while mitigating these programming drawbacks remains a major open challenge for the AI hardware and electronics communities.

To address these challenges, we introduce a software-hardware co-design framework based on edge-pruning topology optimization for randomly weighted resistive memory neural networks. Inspired by clipped Hebbian-rule-based structural plasticity57, this approach emulates the brain’s postnatal development: synaptic overproduction, consolidation of functional synapses, and the elimination of redundant ones following extended learning58,59. In contrast to conventional weight optimization methods that rely on precise tuning of resistive memory conductance12,14,15,42,60–62, our strategy directly engineers the topology of a randomly initialized network by selectively “turning off" insignificant weights while preserving the rest. Moreover, we leverage the intrinsic electroforming stochasticity of resistive memory to generate large-scale, low-cost hardware random weights, thereby transforming programming variability into a functional asset. Building on the theory by Ramanujan et al.63-which posits that a sub-network pruned from a sufficiently large, randomly weighted network can match the accuracy of a fully optimized one-we physically reset (or set) resistive memory to prune (or reinstate) network edges. By avoiding precise programming, our approach is inherently robust to device non-idealities and eliminates the laborious conductance tuning and verification required in traditional optimization.

We validate our co-design on three representative tasks-image classification, audio classification, and image segmentation-using a hybrid analog-digital system featuring a 40 nm, 256 K resistive memory-based in-memory computing core. With identical network architectures and parameter counts, our approach achieves accuracy improvements of 17.3% and 19.9% on the Fashion-MNIST and Spoken Digit datasets, respectively, while reducing programming operations by 99.94% and 99.93% compared to hardware-in-the-loop weight optimization. The corresponding scaled inference energy per sample is reduced by 78.3% and 67.9% relative to state-of-the-art GPUs. Additionally, simulations of U-Net segmentation on the DRIVE dataset yield an area under the precision-recall curve (PR-AUC) of 0.91 and a receiver operating characteristic (ROC) AUC of 0.97 (improvements of 9.8% and 2.0% over GPUs), accompanied by a 99.7% reduction in inference energy enabled by in-memory computing and sparsity. To further demonstrate scalability, we simulate our co-design with ResNet-50 on ImageNet-100, achieving an average Top-1 accuracy of 87.6% alongside 99.3% energy savings. This work offers a universal solution for AI leveraging analog computing with emerging resistive memory (see Supplementary Figs. 13, 14 and Supplementary Tables 11, 12 for Llama 364,65 LoRA66 fine-tuning using edge-pruning topology optimization).

Results
Software-hardware co-design: edge-pruning topology optimization for randomly weighted resistive memory neural networks

Figure 1 schematically illustrates the proposed software-hardware co-design, featuring edge-pruning topology optimization applied to a randomly weighted resistive memory neural network.

From a software perspective, our bio-inspired edge-pruning topology optimization emulates the human brain’s postnatal development, characterized by synaptic overproduction, the consolidation of functional synapses, and the elimination of redundant ones following extended learning (Fig. 1, upper left). In contrast to conventional weight optimization methods that fine-tune weights to minimize loss, this approach engineers the network architecture to uncover an effective sub-network without altering weight values. This methodology is grounded in a corollary to the Lottery Ticket Hypothesis63, which posits that pruned sub-networks derived from overparameterized neural networks can achieve accuracy competitive with that of the original, fully optimized networks. As depicted in the second panel of Fig. 1, the process initiates with the random initialization of the resistive memory network via electroforming stochasticity. Each edge is assigned a fixed random weight and a corresponding importance score. During the forward pass, edges with low scores in each layer-identified as redundant-are pruned to define the sub-network structure; if a neuron’s connections are heavily pruned, the neuron itself may be subsequently eliminated (see Supplementary Table 8). In the backward pass, scores are updated, and select edges are reinstated (replaced) to refine the sub-network topology and minimize training error (see “Methods” and Supplementary Table 1 for algorithmic details).

In terms of hardware implementation, the proposed optimization is realized on a hybrid analog-digital computing system comprising two main components: an analog core based on a 40 nm, 256 K resistive memory in-memory computing macro, which generates random weights, accelerates computation-intensive matrix multiplications, and executes edge pruning; and a digital core utilizing a Xilinx System-on-Chip (SoC) (see “Methods”). By collocating weight storage and computation, the analog core significantly mitigates data movement between memory and processing units, thereby offering superior energy efficiency and parallelism compared to conventional digital architectures (see Supplementary Fig. 15 for details on the fully integrated resistive memory chip). Prior to training, the resistive memory array is partitioned into positive and negative conductance sub-arrays (G+ and G−), which encode the weight matrix via differential conductance (Fig. 1, right). Initially insulating, the as-deposited cells display a narrow weight distribution centered near zero. Subsequent electroforming induces random analog weights within the G+ and G− arrays, resulting in differential-pair conductances that follow a mixture of two quasi-normal distributions. This process leverages electroforming stochasticity as an intrinsic entropy source, providing large-scale, low-cost true random weights for the overparameterized network (see Supplementary Table 3 for randomness analysis). During training, unnecessary edges are physically pruned by resetting the corresponding resistive memory differential pair, a process that ruptures the conductive filaments and zeros the conductance. Conversely, to reinstate a previously pruned but critical connection, the pair is set back to a conducting state, restoring the filament (see Methods for reset/set operations). Upon completion of training, the high-performing sub-network is frozen, yielding a conductance distribution characterized by a mixture of three quasi-normal distributions. Unlike conventional pruning strategies that primarily seek to sparsify networks to reduce computational complexity, our topology optimization introduces a training scheme specifically tailored for online learning in CIM edge systems, effectively circumventing weight optimization. This approach successfully mitigates key challenges associated with resistive memory, notably programming non-idealities and high programming costs (see Supplementary Fig. 10 for the impact of programming non-idealities).

Physical origin of resistive memory array programming stochasticity

Resistive memory cells were fabricated at the nanoscale and electroformed under identical conditions. The programmed cells were then sliced using a focused ion beam (FIB) before being examined by a high-resolution transmission electron microscope (TEM) to elucidate the microstructural origin of the programming stochasticity.

Figure 2a shows an optical photo of the resistive memory in-memory computing macro. This monolithically integrated 256K macro adopts a crossbar structure, with resistive memory cells in each row sharing bottom electrodes and those in each column sharing top electrodes. The cells are integrated with CMOS on a 40 nm standard logic platform between the metal 4 and metal 5 layers via a back-end-of-line process, as revealed by high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) (Fig. 2b). Figure 2c highlights clear differences in cross-sectional HAADF-STEM images between pristine and electroformed cells. In the pristine cell (left), the tantalum and tantalum oxide (Ta/TaOx) resistive layer shows uniform structure (e.g., green-boxed area), whereas electroformed cells (middle and right) display brighter contrast regions (e.g., red-boxed areas) between electrodes, indicating structural variations likely due to conducting channels. To analyze composition, energy-dispersive X-ray spectroscopy (EDS) line scans were performed, revealing that brighter regions (red arrow) have a lower oxygen-to-tantalum ratio than darker regions (green arrow), confirming the presence of conducting channels46,47,67. The red line profiles of the two cells also differ markedly, aligning with the electroforming stochasticity observed in Fig. 2h, i. Complementary low-energy electron energy loss spectroscopy (EELS) plane scans and center-point spectra (Fig. 2d, e) of electroformed cells further demonstrate variations in oxygen-vacancy concentrations and valence between dark (Area1) and bright (Area2) regions. Losses in Area1 (25.2 and 25.1 eV) resemble the plasmon peak of insulating TaO2 (25.7 eV), while those in Area2 (24.6 and 24.4 eV) match metallic TaO (24.5 eV), indicating oxygen-vacancy migration during electroforming67,68-consistent with EDS findings. Additionally, EELS low-loss peak maps visualize the conductive channels, showing oxygen-vacancy-rich TaOx clusters spanning nearly all of Area2, with no complete channels in Area1 (Fig. 2f). The varied patterns of these channels and corresponding EELS-peak distributions (Fig. 2g) underscore the inherent stochasticity of electroforming, driven by thin-film inhomogeneity and random oxygen-ion motion, enabling low-cost, scalable random conductance for physically implementing randomly weighted neural networks.

The intrinsic stochasticity of electroforming is harnessed to physically implement randomly weighted neural networks for the proposed edge pruning topology optimization. Figure 2h illustrates the random weight generation process using the resistive memory array. Initially, electroforming voltages are sampled from a small-scale sub-array, defined as the minimum voltage switching cell resistance from ~30 MΩ to below 300 KΩ. Based on the cumulative probability, a uniform 3.4 V pulse (10 ms width) is applied to the G+ (G−) array at 120°C, yielding a random conductance matrix with approximately half the cells electroformed and the rest insulating (sparsity of 0.5). High-temperature forming enhances cell retention and Ron/Roff uniformity (see Supplementary Fig. 3). Finally, each cell in the G− array is electroformed to a complementary state relative to G+ (see Supplementary Table 5 for impacts of random weight distributions). During training, weights are pruned by resetting corresponding resistive memory differential pairs. As shown in Fig. 2i, analog hardware weights follow a mixture of three quasi-normal distributions, with pruned pairs exhibiting a mean conductance of ~0.07 μS and low variance (see Supplementary Figs. 5–7 and Notes for robustness studies). Figure 2j demonstrates data retention in resistive memory cells, with minimal conductance fluctuation over 10,000 read cycles (0.1 V amplitude, 2 s width), which mitigates overfitting during training as discussed later (see Supplementary Fig. 2 for 150°C baking retention tests).

Image classification of Fashion MNIST using the co-design

The co-design was evaluated on a 4-layer convolutional neural network (CNN)69—a standard vision model-for classifying the Fashion MNIST dataset (simulations were also performed with ConvMixer70 on CIFAR-10 and ResNet-5071 on ImageNet100 to further demonstrate applicability; see Supplementary Figs. 11–12 and Supplementary Table 7).

Figure 3a illustrates example feature maps in garment classification using edge pruning topology optimization on the hybrid analog-digital system. The Fashion MNIST dataset comprises 70,000 frontal images across 10 garment categories. Test images are down-sampled to 14×14, quantized to 4 bits, and input to a randomly weighted 4-layer CNN with two convolutional and two fully connected layers (see “Methods” for CNN details). Initialized with 62K random weights (124K resistive memory cells), the model shows differential conductance heatmaps after electroforming and topology optimization in the upper schematic. Figure 3b depicts the corresponding distributions: post-electroforming weights follow a mixture of two quasi-normal distributions with means of −27.1 μS and 27.2 μS; after optimization, half the pairs are pruned (sparsity of 0.5), adding a third distribution with a mean of −0.05 μS (see Supplementary Fig. 6 for CNN hyperparameter studies). Figure 3c visualizes 3D principal component analysis (PCA) of embedded features for the classification head before and after edge pruning topology optimization, with points color-coded by garment category. Topology optimization transforms overlapping embeddings into distinct clusters, yielding discriminative features.

As shown in Fig. 3d, the experimental edge pruning topology optimization (hardware TO) achieves a classification accuracy of 87.4% compared with 79.7% of hardware weight optimization (hardware WO) with free updates, as the latter is affected by programming noise. This corresponds to a 0.4% accuracy difference compared to the software weight optimization (software WO) baseline on GPU. The edge pruning topology optimization also exhibits higher learning efficiency, showing a 17.3% accuracy margin over weight optimization with gradient threshold under the same budget of weight updates (see Methods for weight optimization details). Additionally, hardware-in-the-loop TO improves accuracy by 0.9% over software TO on GPU, mainly by mitigating overfitting via RM read noise (see Supplementary Fig. 9 for read noise impacts). This accuracy is confirmed by the predominantly diagonal confusion matrix in Fig. 3e. Figure 3f compares training complexity: TO reduces hardware weight updates in convolutional and fully connected layers by 99.74% and 99.98% on average (for fair comparison, protocols are initialized with similar parameter sizes and terminated at comparable accuracy; see Methods and Supplementary Data 1). Figure 3g contrasts single-image inference energy between the hybrid system (~3.67 μJ) and GPU (~5.76 μJ). Scaling the 40 nm design to 5 nm (matching GPU node) reduces hybrid energy to ~1.25 μJ, yielding 78.3% savings. The right panel highlights TO’s sparsity benefit, cutting RM forward-pass energy to ~12.94 nJ versus ~18.65 nJ for WO, demonstrating 30.6% energy saving (see Supplementary Tables 4, 9–10, Supplementary Note 1, and Supplementary Data 4 for energy estimation details).

Audio classification for Spoken Digit with the co-design

In the second experiment, the co-design was applied to audio classification using a convolutional recurrent neural network (CRNN)72—a standard model for extracting spatial and temporal audio features via convolutional and recurrent layers. The Spoken Digit dataset73 was used, which includes 3000 recordings from 6 speakers sampled at 8 kHz.

Figure 4a illustrates experimental forward-pass feature maps on the hybrid analog-digital system. Spoken digits are transformed to the frequency domain and converted into 23×15 acoustic feature maps, then fed into a randomly weighted 5-layer CRNN with 2 convolutional layers, 1 recurrent layer, and 2 fully connected layers (see “Methods” for CRNN details). The model incorporates 68.5K stochastic weights, realized via 137K randomly initialized resistive memory cells. Hardware weight heatmaps after electroforming and edge pruning are shown in the upper schematic. After electroforming, weights in convolutional, recurrent, and fully connected layers follow a mixture of two quasi-normal distributions with means of −27.3 μS and 27.1 μS (Fig. 4b, left). During topology optimization, half the differential pairs (sparsity of 0.5) are reset to near-zero conductance, with remaining cells fixed, resulting in three quasi-normal distributions (Fig. 4b, right). Figure 4c visualizes 3D PCA of classification-head embeddings after electroforming and topology optimization, with points color-coded by digit category. Similar to image classification, initially overlapping embeddings form distinct clusters post-optimization, indicating discriminative features.

As shown in Fig. 4d, hardware edge pruning topology optimization achieves 98.1% accuracy versus 90.8% for hardware-in-the-loop weight optimization, affected by programming stochasticity-revealing a 0.2% difference relative to the software baseline. Like the image task, hardware topology optimization mitigates overfitting using inherent RM read noise (see Supplementary Fig. 7 for CRNN hyperparameter studies). Performance is confirmed by the confusion matrix in Fig. 4e, featuring prominent diagonals. Figure 4f shows that topology optimization reduces hardware weight updates versus unrestricted weight optimization, with average reductions of 99.64%, 99.97%, and 99.96% in convolutional, recurrent, and fully connected layers, respectively. In Fig. 4g, the energy per spoken-digit inference is ~2.02 μJ on the hybrid system (scaling to ~0.68 μJ at 5 nm) versus ~2.15 μJ on a GPU, corresponding to a 67.9% reduction. The right panel further highlights sparsity benefits, with topology optimization consuming ~4.79 nJ compared to ~6.46 nJ for weight optimization (a 25.9% reduction).

Image segmentation of DRIVE with the co-design

In addition to classification, edge pruning was evaluated on biomedical image segmentation using a U-Net74,75 for the DRIVE76 dataset. DRIVE contains 40 retinal fundus images (565×584) for blood vessel segmentation, including 7 images with pathological cases. As illustrated in Fig. 5a, each 584×565 image is first partitioned into 96×96 patches, which are then processed by a U-Net comprising 2 convolutional layers (input and output), 4 contracting layers (D1-D4), and 4 expansive layers (U1-U4). The network outputs segmented patches of the same size, which are concatenated to form the final segmentation. Figure 5b shows the 768×768 simulated weights of the D4 layer after electroforming and pruning. Initial weights are sampled from the measured conductance distribution of electroformed resistive-memory differential pairs. Following topology optimization, 50% of the weights are pruned according to a predefined sparsity of 0.5 (white pixels), while the remaining weights are drawn from the conducting-state distribution. Representative segmentation results are shown in Fig. 5c, where the simulated probability maps, binary predictions, and ground truth (from left to right) exhibit close agreement, delineating major vessels and fine capillaries (see Supplementary Fig. 8 for U-Net hyperparameter studies). Figure 5d, e compares the precision-recall (PR) and ROC curves for software and simulated WO versus simulated edge-pruning TO. The simulated TO achieves PR-AUC and ROC-AUC of 0.91 and 0.97, respectively-only 0.01 below the software WO baseline, yet yielding 9.8% and 2.0% improvements over simulated WO, owing to its robustness to programming stochasticity. The corresponding F1-score (F1) and AUC evolution during training are plotted in Fig. 5f, where simulated TO gradually converges toward the software WO baselines. The confusion matrix in Fig. 5g further validates performance: the simulated U-Net with the co-design attains 97% background and 83% vessel pixel accuracy, closely matching the software WO baseline of 98% and 80% (see Methods for PR, AUC, F1, and accuracy definitions). Figure 5h shows the estimated energy consumption of the GPU computing unit and the RM core for inferring a single image. The energy consumption for the RM core is approximately 3.5 μJ while that of the GPU computing unit is approximately 1339.5 μJ, resulting in a 99.7% energy saving enabled by the co-design.

Methods
Fabrication of resistive memory chip
Under the 40 nm technology node, the fabricated resistive memory chip integrates a 512×512 crossbar array, with cells formed between the metal-4 and metal-5 layers using a backend-of-line process. Each cell consists of bottom and top electrodes (BE and TE) and a transition-metal-oxide dielectric layer. The BE via (60 nm diameter) is defined by photolithography and etching, filled with TaN by physical vapor deposition, and capped with a 10 nm TaN buffer layer. A 5 nm Ta layer is then deposited and oxidized to form an 8 nm TaOx dielectric layer. The TE is realized by sequential PVD deposition of 3 nm Ta and 40 nm TiN. After cell formation, the remaining interconnect metals are completed using a standard logic process. Cells in the same row share a common BE line, whereas cells in the same column share a common TE line. Following a 30-min post-anneal at 400°C in vacuum, the 40 nm resistive memory chip exhibits excellent properties, including high yield and robust endurance (see Supplementary Figs. 1, 2 for detailed device characteristics).

Hybrid analog-digital hardware system
The hybrid analog-digital hardware system (see Supplementary Fig. 4) comprises a 40 nm resistive memory chip and a Xilinx ZYNQ SoC, which integrates a field-programmable gate array (FPGA) and an ARM processor on a printed circuit board (PCB). The resistive memory chip operates in three modes under the edge-pruning topology optimization scheme: an electroform mode for generating random conductance weights, a reset mode for pruning selected weights, and a multiplication mode for vector-matrix operations. In electroform mode, dielectric breakdown is induced in the resistive memory array to form random conductance matrices: all source lines (SLs) are biased to a fixed programming voltage supplied by an eight-channel 16-bit analog-to-digital converter (DAC, DAC80508, Texas Instruments), while bit lines (BLs) are grounded and word lines (WLs) are biased by the DAC to enforce a compliance current and prevent hard breakdown. The SL voltage amplitude and pulse width tune the post-breakdown conductance distribution and sparsity. In reset mode, selected cells are returned to the off state: the target BL is biased by the DAC, the corresponding SL is grounded, and the remaining SLs are left floating. In multiplication mode, a 4-channel analog multiplexer (CD4051B, Texas Instruments) controlled by an 8-bit shift register (SN74HC595, Texas Instruments) applies DC voltages to the BLs. During each training step, the resistive memory chip is read, and the vector-matrix products, encoded in the SL currents, are converted to voltages by transimpedance amplifiers (OPA4322-Q1, Texas Instruments) and digitized by 14-bit ADCs (ADS8324, Texas Instruments). The resulting data are transferred to the Xilinx SoC for further processing. The FPGA implements the control logic for driving the resistive memory and exchanges data with the ARM processor via direct memory access to DRAM. It also accelerates selected neural network operations in hardware, such as activation and pooling.

Multi-Bit vector-matrix multiplications
To perform vector-matrix multiplication, the analog input vector is first converted into an m-bit binary vector. In this process, each input element is encoded as a binary number with m bits, where m equals 4 for CNN, 3 for CRNN, and 6 for U-Net. The analog multiplication is thus approximated by m successive multiplications using binary input vectors at different significance levels. In each step, a row is biased to a small fixed voltage (e.g., 0.1 V) if the corresponding bit is “1”, and is grounded if the bit is “0”. The resulting column currents are sequentially read out through a column multiplexer. Finally, these currents are scaled by their respective bit significance and summed in the digital domain.

Reset and set operations
Edge pruning topology optimization. The weight pruning process is physically implemented by driving the corresponding resistive-memory differential pairs into the off state via reset operations, while reinstatement is achieved by returning these cells to their conducting states via set operations. The set operation is realized by applying identical pulses with a 3.3 V amplitude and 300 ns width to the BLs of the resistive-memory array, thereby switching pruned cells back to the conducting state and reinserting them into the sub-network. The reset operation is implemented by applying identical pulses with a 2.6 V amplitude and 400 ns width to the SLs, annihilating the conductive filaments and driving the cells into the off state. Importantly, there is a large margin between the off state and the conducting state, so precise conductance programming is unnecessary.

Weight optimization. For weight optimization, identical pulses with a 1.5 V amplitude and 500 ns width are used to program the resistive-memory cells. The programming current is limited by the transistor gate voltage on the WL to control the conductance distribution. Each cell in a differential pair is tuned to its target conductance using a closed-loop write scheme78, followed by write-verify steps that ensure an approximate 10% conductance error margin.

Edge pruning topology optimization algorithm
The edge-pruning topology optimization algorithm consists of forward and backward steps. First, a randomly weighted neural network is initialized on the analog resistive-memory chip, where each weight value also serves as the score of the corresponding edge. In the forward pass, a sub-network is selected by pruning hardware weights whose scores fall below a threshold determined by a predefined sparsity (e.g., a sparsity of 0.5 corresponds to pruning 50% of the weights). The inputs are then fed through this sub-network for forward propagation and loss evaluation. In the backward pass, a general-purpose digital processor computes the gradients of the loss function to update the edge scores while keeping the weight values fixed. The scores are updated using a straight-through gradient estimator63,79:

es ij=s ij − η ∂L / ∂I j * w ij * Z i, (1)
where s ij and es ij denote the edge scores between the hidden nodes i and j before and after the update, respectively, η is the learning rate, ∂L / ∂I j is the partial derivative of the loss L with respect to the input of node j (I j), and w ij * Z i is the weighted output of node i. These processes are repeated until a well-performing sub-network is selected from the randomly initialized neural network.

Threshold learning rule
To improve the energy and time efficiency during the training process, we follow Yao’s work80 and use the same threshold learning rule to reduce unnecessary programming of resistive memory.

Edge pruning topology optimization.
Δs= Δs, if |Δs|≥T s (t), (2)
0, otherwise,
where Δs is the edge-score update, and T s (t) is the dynamic threshold updated by the following rule:

T s (t)= T s init − (T s init − T s end) * t / t max, (3)
where T s init, T s end, and α represent the pre-designed initial threshold, end threshold, and update step, respectively. When a new best accuracy is achieved, the value of t is increased by 1. This decaying threshold speeds up model convergence and is inspired by the learning-rate decay technique81.

Weight optimization.
Δw= Δw, if |Δw|≥T w, (4)
0, otherwise,
where Δw represents the weight update, and T w denotes the pre-designed threshold constant used to ascertain whether a particular cell requires programming. When T w equals zero, each cell is programmed during every training step, corresponding to weight optimization with free updates. By increasing the value of T w, the frequency of cell programming decreases, and weight optimization with limited updates is obtained when its programming count is similar to that in the edge pruning topology optimization.

Details of the experimental neural networks
When running randomly weighted neural networks, the analog resistive-memory in-memory computing chip accelerates the most computationally intensive vector-matrix multiplications, while the remaining max-pooling, normalization, and activation operations are executed on the Xilinx SoC. Training hyperparameters are summarized in Supplementary Data 1–3.

CNN backbone. As shown in Fig. 3a, the 4-layer CNN consists of 2 convolutional (C) layers and 2 fully connected (F) layers. The C1 layer uses kernels of size 64 × 1 × 3 × 3 (out channels × in channels × width × height) and produces 64 × 12 × 12 feature maps. The C2 layer uses kernels of size 16 × 64 × 3 × 3 and generates 16 × 10 × 10 feature maps. These maps are then down-sampled by a max-pooling layer with a 2 × 2 kernel and stride 2. The resulting 16 × 5 × 5 feature maps are flattened into a 400-element vector and fed into the F1 layer. F1 has a weight matrix of size 128 × 400 and reduces the input to a 128-element vector. Finally, this vector is passed to the F2 layer with size 10 × 128 to produce 10 output probabilities corresponding to the image labels.

CRNN backbone. Spoken digits are first transformed into the frequency domain using mel-frequency cepstral coefficients (MFCCs)72, yielding cepstral feature maps suitable for recognition and classification. As shown in Fig. 4a, these 23×15 feature maps are then fed into a 5-layer CRNN comprising 2 convolutional layers, 1 recurrent (R) layer, and 2 fully connected layers. The C1 layer uses kernels of size 64 × 1 × 3 × 2, followed by a max-pooling layer that produces 64 × 11 × 14 feature maps. The C2 layer uses kernels of size 32 × 64 × 3 × 2, followed by a max pooling layer that outputs 32 × 2 × 8 feature maps. These maps are then passed to the R1 layer:

h(t)= tanh(w ih * x t + w hh * h(t−1)), (5)
where t, h(t), w ih, and w hh denote the timestep, hidden state, input-hidden weights (128 × 32), and hidden-hidden recurrent weights (128 × 128), respectively. The timestep increases as the model iterates, and when it reaches 4, the final output of the R1 layer is obtained by the 128-element hidden state. Subsequently, the output is fed into the F1 (256×128) and F2 (10×256) layers to obtain the 10 probability outputs that determine the label of the input spoken digit.

U-Net backbone. As shown in Fig. 5a, the U-Net architecture consists of two main parts: a contracting path (down-sampling layers, D) and an expansive path (up-sampling layers, U). Each down-sampling layer applies two 3 × 3 convolutions, each followed by a rectified linear unit (ReLU) activation, and a 2 × 2 max-pooling operation. This progressively extracts higher-level features from the input, enabling the network to capture critical structures and patterns. Each up-sampling layer consists of a bilinear interpolation step, concatenation with the corresponding cropped feature maps from the contracting path, and two subsequent 3 × 3 convolutions, each followed by ReLU. This design facilitates precise localization and accurate segmentation of objects within the image.

During simulations, retinal blood vessel images of size 584×565 pixels are first split into 26,400 overlapping 96×96 patches. From these, 6400 patches are randomly selected for training, and the remaining 20,000 patches are used for testing. Each patch is fed into an input convolutional layer with kernel size 32 × 1 × 3 × 3 for initial feature extraction, and the resulting feature maps are processed by four down-sampling layers (D1–D4) and four up-sampling layers (U1–U4) for vessel segmentation. The input channel numbers for D1–D4 are 32, 64, 128, and 256, respectively, and for U1–U4 are 256, 128, 64, and 32. An output convolutional layer with kernel size 2 × 32 × 1 × 1 finally maps the U4 feature maps to segmentation probability maps for each patch. The full segmented image is then reconstructed by concatenating all processed patches.

Image segmentation indicators. To demonstrate the performance of U-Net in the DRIVE image segmentation task, several indicators are evaluated, including true positive rate (TPR), false positive rate (FPR), recall, precision, F1 score (F1), and accuracy, as follows:

TPR=Recall= TP / (TP+FN), (7)
FPR= FP / (TN+FP), (8)
Precision= TP / (TP+FP), (9)
F1=2× (Precision×Recall) / (Precision+Recall), (10)
Accuracy= (TP+TN) / (TP+FP+TN+FN), (11)
Here, Recall, Precision, F1, and Accuracy are widely used performance metrics for evaluating image segmentation tasks. Recall evaluates the U-Net’s ability to identify all relevant instances, Precision measures the correctness of positive predictions, F1 provides a balanced score ranging from 0 to 1, with higher values representing better classification performance, and Accuracy indicates the proportion of correct predictions made out of the total number of predictions. These metrics help assess classification performance accurately.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The manuscript entitled “Pruning Random Resistive Memory for Optimizing Analog AI” by Y. Li et al demonstrated pruning based network optimization method for analog hardware memory array. It is interesting that the authors utilized the intrinsic randomness from the forming process with topological pruning algorithm to achieve an optimal network. The proposed method leads to higher accuracy as compared to standard training method and better energy efficiency as compared to its GPU implementation. Although the proposed co-optimization method is interesting and promising, there are several points need to be clarified and further explained to become appropriate to be published on a distinguished journal like Nature Communications.\nComment 1: The authors mentioned that the cycle-to-cycle conductance variation leads to the prevention of overfitting. If it is the case, the accuracy should increase at a certain noise % for both CNN (SI Fig. 5 d) and CRNN (SI Fig. 6d). However, the accuracy at 0 % or noise is always same or higher than non-zero % of noise cases. Can the authors provide more detailed explanations on the prevention of overfitting with hardware?\nComment 2: For both FashionMNIST dataset and Spoken Digit dataset, the size of the analog memory arrays has to be about two times larger to achieve its optimal network after pruning since the sparsity of 0.5 is the optimal sparsity for the CNN and CRNN to achieve the highest accuracy as shown in Fig. 5b and 6b. For smaller datasets such as FashionMNIST and Spoken Digit dataset, having two times larger hardware array might be feasible. However, for the larger datasets such as ImageNet, it will be hard to have two times larger array size in hardware. Is there any way to circumvent this hardware constraint (i.e. limited array size) while still utilizing the proposed pruning method?\nComment 3: The energy consumption of the hardware system with the proposed pruning method is compared with GPU case. I wonder if the proposed pruning method is more energy efficient that the standard method (i.e. a network trained with a standard gradient descent back propagation) on the hardware system. If the proposed method is more energy efficient that the conventional method on the same hardware system, it will emphasize the energy efficient improvement solely from the proposed pruning method.\nComment 4: As also shown in the Table 7, the most of energy consumption is coming from the peripheral circuits of the synaptic arrays (i.e. MUX, DEC, and ADC etc.). However, the proposed pruning methods only considered the pruning of synaptic weights. Can the proposed method be expanded to pruning neurons (e.g. disable a column including its periphery if the total score on the column is below limit)?\nComment 5: Is there any reason that the electro forming for the data shown in Fig. 2h is performed at the elevated temperature (i.e. 120 C)? Is it to increase the stochasticity during the electro forming? Are the electroforming processes for FashinMNIST and Spoken Digit Dataset study also done at the elevated temperature?\nComment 6: The pruning algorithm is the main topic of the manuscript. However, the main text only conceptually explains the algorithm. Proper detailed explanation should be added to the main text to provide better understanding to readers.\nComment 7: The read cycle is only given with the number read pulses (Fig. S2h) or read cycles (Fig. 2j). How does the number of read pulses or read cycles corresponds to the time? Can the states after electroforming reach 10 yr of retention at 85C?\nComment 8: In addition to Comment 3, the proposed pruning method still need electro forming and programming to optimize the network similar to the gradient descent back propagation method. The number of programming with the proposed pruning method and the conventional training method should be also provided.", "reviewer_2": "This work proposed a resistive based processing-in-memory architecture and chip designs with an edge pruning topology. The design was applied and evaluated on multiple neural networks and better performance was gained. Resistive memory-based processing-in-memory designs have been widely explored in hardware and hardware-software co-design level and it is a promising technology. The proposed research is solid and the paper is well written. Some concerns are listed as below.\n1. The work proposed an edge pruning methodology, while its novelty is limited or it should be better addressed. From my knowledge and understanding, the proposed edge pruning that employing pruning while learning is the same as fundamental pruning approaches in many deep learning works.\n2. As this work has chip designs and the proposed work has been applied to several applications, I would expect to see more circuit design details, e.g., the neuron circuits design, how to implement the activation function, backpropagation, pooling, etc.\n3. From my understanding, the neural networks were pruned randomly, my question is how the crossbar array would be? Are the pruned ones on the array just be set to 0? If so, the benefit from the pruning could be limited.\n4. Will the online pruning cause device defects? Some devices may stuck in fault after many times programming. I would like to see discussions on this.\n5. In Figure 2 j, why there are no conductance locate to 10-25us?\n6. I would expect to see performance comparisons with other resistive memory based processing-in-memory designs, instead of not only GPU.", "reviewer_3": "This work is motivated to tackle the weight programming issue in analog in-memory computing by edge prunning. It is inspired by the Lottery Ticket Hypothesis to prune sub-networks from an overparameterized neural network to achieve competitive accuracy compared to the original neural network with well-optimized weights. Experimental results were shown on a 40nm 256K resistive memory macro, observing 17.3% and 19.9% accuracy improvements in FashionMNIST and Spoken Digit datasets.\nDespite the good amount of effort, it would be great if the authors could address the following points:\n1) How does the proposed edge pruning work, or could be effective, in underparameterized, or highly distilled networks? The main application of analog in-memory computing is for edge devices, and nowadays there are many modern networks that are optimized for extremely low number of parameters, or few-bit precision, to easily fit on digital solutions. How proposed solution can have an edge on them?\nIn a somewhat related note, the reviewer cannot see the edge pruning (which is a pure software technique) as an orthogonal solution to the conventional weight optimization method. If a highly parameter-optimized network is given (that may or may not be based on the Lottery Ticket Hypothesis), what this paper has to do with its accurate, efficient, or robust implementation on analog in-memory computing?\n2) Paper is motivated by LLMs and the large computational demand imposed by them, while reported experiments are for toy FashionMNIST and Spoken Digit datasets. It would be great to see how the “software” part of this co-design work, namely edge pruning, can remain effective in the parameter optimized LLMs such as LLaMA-3? Note that earlier LLMs were heavily undertrained see Chinchilla Scaling Laws."}, "author_response": "Responses to Review Comments on the manuscript entitled \"Pruning Random Resistive Memory for Optimizing Analog AI\" (Manuscript ID NCOMMS-24-17776) Yi Li†, Songqi Wang†, Yaping Zhao, Shaocong Wang, Bo Wang, Woyu Zhang, Yangu He, Ning Lin, Binbin Cui, Xi Chen, Shiming Zhang, Hao Jiang, Peng Lin, Xumeng Zhang, Feng Zhang, Xiaojuan Qi, Zhongrui Wang*, Xiaoxin Xu*, Dashan Shang*, Qi Liu, Kwang-Ting Cheng, and Ming Liu Jan, 2025 We would like to thank \"Nature Communications\" for this opportunity to revise our manuscript. We thank all the reviewers for their constructive suggestions, insightful questions and interest in our work. We have addressed their comments point-by-point as listed below and revised the manuscript accordingly. We hope the revised manuscript meets the criteria of the journal. Once again, we appreciate the time of the reviewers and hope to have their concerns addressed. All modifications are marked in orange color in the revised manuscript.The responses to the reviewers’ comments are as follows (with comments marked in blue).\n[... Author rebuttal text for Round 1 ...]"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors addressed the most of my comments adequately with full of details. However, there are several concerns that still need to be addressed before the manuscript is being published.\nComment #1:\nThe terminologies are mixed up; Read noise and write noise (or cycle-to-cycle variation). In the author’s answer to comment 1, the authors mentioned that “programming variation presents an obstacle to model performance.” However, the added text on the manuscript mention that “… optimization improves the accuracy by 0.9 % … primarily due to the mitigation of overfitting by cycle-to-cycle conductance variance”. The authors probably meant ‘read noise’ with cycle-to-cycle conductance variation. However, cycle-to-cycle variation usually means the variation on conductance between write cycles as compared to device-to-device variation (which represent process induced variations between devices). The terminology should be clarified to prevent any confusion.\nComment #2:\nWhat I meant “two times larger hardware array” on Comment #2 is for the case when the pruned network is deployed to a memory array for inference. When a network is pruned, the matrix of parameters becomes sparse following the pruning rate (Fig. R3). If we do not consider the zero valued parameters as parameters, the memory size required for the network will be reduced following the pruning rate. However, when the network is saved on a memory array, the zero valued parameters still need to be saved as zero on the memory array. If the authors can provide a mapping method that can leverage the sparsity of parameter array and combine it with the proposed pruning method, the advantages coming from the proposed pruning method will be maximized. An example of the mapping method for sparse networks is J. Lin et. al., “Learning the sparsity for ReRAM: Mapping and pruning sparse neural network for ReRAM based accelerator”, ASPDAC 2019.\nComment #3:\nTable 13 in the revised supplementary information is very helpful to understand the advantages of the proposed pruning method at a glance. The author might consider moving the table to main text if the space allows.\nComment #4:\nSome of insets has labels with very small fonts. The authors might consider enlarging the font size for the labels. Moreover, some of schematic sub figures can be reduced in size to provide more space for data figures (e.g., Fig. 3a, Fig. 4a, and Fig. 5c).\nComment #5:\nFigure 2 is distractive as it provides too much of details on the memory devices. The main focus of the manuscript is the co- design method that utilize the intrinsic variations on the devices. On that regard, Fig. 2c-g is non-necessary details. The authors might consider moving them to supplementary and provide more details on the pruning algorithm (e.g. a concise version of Supplementary Table 1).\nComment #6:\nFigure 1 is a good introductory figure that explains the advantages of the proposed co-design method. However, the figure is little bit busy and de-emphasize the main point (i.e. the pruning method and its advantages). The authors might consider removing some of minor details to emphasize the main idea they want to focus.", "reviewer_4": "In this manuscript, the authors propose a software-hardware co-design approach inspired by structural plasticity, applying edge pruning to optimize the topology of a randomly initialized analog resistive memory neural network. The noteworthy contribution is that the pruning algorithm suites for training neural networks in analog hardware, making use of noisy weights. It is beneficial to training neural networks on analog memristive compute-in-memory (ACIM) hardware with less weight programming, alleviating the endurance requirement. It also benefits training and inference accuracy.\nOn the hardware side, ACIM has been explored extensively in the literature. In this work, while leveraging the intrinsic device physics for computation is compelling, several concerns arise regarding the effectiveness of the proposed method:\n1. In computational neuroscience, structural plasticity typically refers to the dynamic rewiring of sparse networks through both pruning and neurogenesis—not merely pruning a dense, overparameterized network to identify subnetworks. The former approach can significantly reduce on-chip memory usage during learning and improve memory efficiency. In contrast, the latter does not offer these benefits in hardware for on-chip learning. As the results indicate, the proposed method does not reduce the on-chip memory footprint. The benefit of deploying sparse neural networks on the dense crossbars is saving a small part of the power consumption from the pruned weights (by reseting them to LCS). Is it likely that the dense crossbar architecture is ill-suited for sparse networks? A rethinking at the architectural level is necessary to fully realize the benefits of pruning-based sparsity. Please discuss and comment on this.\n2. In Figures 3g and 4g, what about adding a blue bar which shows the Hardware WO hybrid system inference energy on the left part? Though I suppose that there is no big difference on the values of such a blue bar versue the red bar. The authors compare the GPU (software WO) with the hybrid system (Hardware TO) which includes the algorithmic optimization of TO, so logically, the benefits of 82.1% and 51.2% energy saving is not solely from in-memory computing. The energy saving due to in-memory computing should be evaluated using the same algorithm.\n3. Unfair Comparison with GPU: In Figures 3g, 4g, and 5g, the authors compare the inference energy of their hybrid system to that of a GPU and claim substantial improvements. However, this comparison suffers from two major issues:\n1) Misleading Memory Assumptions and Incomplete System-Level Energy Accounting: According to the supplementary information on calculating the energy consumption of using NVIDIA GeForce RTX 4090 GPU, the authors use an average energy per operation including data access from DRAM (I suppose that the 450 W is the average power of the whole GPU system which includes DRAM). In addition, the calculation on the energy of the proposed “Hybrid System” only includes the CIM array and peripheries. It excludes key contributors such as FPGA-based processing, activation function computations, chip-to-chip communication, etc., —components that could dominate the total energy. In contrast, the GPU executes the full end-to-end computation.\nTherefore, the authors are comparing a stand alone accelerator with a capable large system (GPU + DRAM), and claim that the stand alone accelerator do not suffer von Neumann bottleneck, which is obvious. How to confirm that the energy benefit is from in-memory computing rather than from getting rid of DRAM? The comparison is not fair (at least not sufficiently clear), and the 82.1% and 51.2% energy gains are likely to be too optimistic. The weight parameters of the tested neural network are around 60K which can be fully stored on-chip. Assuming that these weight are mapped on the cache of the GPU, avoiding external DRAM accesses, where the DRAM bottleneck is eliminated, the green bars will drop. Please discuss and comment on this.\nDoes the proposed hybrid system still relies on off-chip memory? For example, during training, do we need to first read and buffer the weight matrix Wo before calculating the transpose of the weight matrix WoT for each training iteration? Where to store the transpose of the weight matrix?\n2) Comparing the proposed system to a GPU is not ideal. A more meaningful comparison would involve other state-of-the-art computing-in-memory (CIM) chips or/and digital machine learning accelerators.\n4. Limited System-Level Impact of Energy Gains: In Figures 3g and 4g, the authors compare the inference energy of topology optimization with that of weight optimization, reporting improvements of 30.6% and 25.9%, respectively. However, these gains translate to less than a 1% improvement at the system level (a couple of nJ vs uJ), based on the authors' own calculated/reported values. Therefore, in terms of hardware advancement - proposed pruning mechanism in dense crossbar architectures - does not meaningfully improve inference energy efficiency at the system level for CIM inference.", "reviewer_5": "I co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature Communications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career Researchers who co-review manuscripts."}, "author_response": "Responses to review comments on the manuscript entitled ”Pruning Random Resistive Memory for Optimizing Analog AI” (Manuscript ID: NCOMMS-24-17776) Yi Li†, Songqi Wang†, Yaping Zhao, Shaocong Wang, Bo Wang, Woyu Zhang, Yangu He, Ning Lin, Binbin Cui, Xi Chen, Shiming Zhang, Hao Jiang, Peng Lin, Xumeng Zhang, Feng Zhang, Xiaojuan Qi, Zhongrui Wang*, Xiaoxin Xu*, Dashan Shang*, Qi Liu, Han Wang, Kwang-Ting Cheng, and Ming Liu Wewouldliketothank”NatureCommunications”forthisopportunitytoreviseourmanuscript. We thank all the reviewers for their constructive suggestions, insightful questions, and interest in our work. We have addressed their comments point-by-point as listed below and revised the manuscript accordingly. We hope the revised manuscript meets the journal’s criteria. Once again, we appreciate the time of the reviewers and hope to have their concerns addressed. All modifications are marked in orange color in the revised manuscript. The responses to the reviewers’ comments are as follows (with comments marked in blue).\n[... Author rebuttal text for Round 2 ...]"}, {"round": 3, "reviewer_comments": {"reviewer_1": "The manuscript has been revised, and it is in a better shape. However, there are few minor concerns better to be addressed before the manuscript is published in Nature Communications.\nComment #1: The labels and texts in the figures are still too small to read. They will not be readable at all if the manuscript is printed out either in A4 or Letter papers.\nComment #2: It will be great if the authors can provide the details on the electrical measurement procedures used for this work (e.g. the high-temperature electroforming and device programming) in the methods section.\nComment #3: The statement for code availability is not included in the manuscript."}, "author_response": "Responses to review comments on the manuscript entitled ”Pruning Random Resistive Memory for Optimizing Analog AI” (Manuscript ID: NCOMMS-24-17776) Yi Li†, Songqi Wang†, Yaping Zhao, Shaocong Wang, Bo Wang, Woyu Zhang, Yangu He, Ning Lin, Binbin Cui, Xi Chen, Shiming Zhang, Hao Jiang, Peng Lin, Xumeng Zhang, Feng Zhang, Xiaojuan Qi, Zhongrui Wang*, Xiaoxin Xu*, Dashan Shang*, Qi Liu, Han Wang, Kwang-Ting Cheng, and Ming Liu Wewouldliketothank”NatureCommunications”forthisopportunitytoreviseourmanuscript. We thank all the reviewers for their constructive suggestions, insightful questions, and interest in our work. We have addressed their comments point-by-point as listed below and revised the manuscript accordingly. We hope the revised manuscript meets the journal’s criteria. Once again, we appreciate the time of the reviewers and hope to have their concerns addressed. The responses to the reviewers’ comments are as follows (with comments marked in blue).\n[... Author rebuttal text for Round 3 ...]"}]

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