Computing-in-memory architecture for Kolmogorov-Arnold networks based on tunable Gaussian-like memory cells

Domain: chemistry
Published: 2026-02-20
Editorial outcome: major_revision

Abstract
Inspired by the Kolmogorov-Arnold Representation Theorem, the Kolmogorov-Arnold networks serve as promising alternatives to multilayer perceptrons. Kolmogorov-Arnold networks utilize a superposition of finite basis functions to implement variable continuous univariate activation functions, offering greater flexibility and adaptability. However, the hardware implementation of its basis functions remains costly, making it challenging to achieve complex computations with minimal equipment. Here, we designed the device defined as Gaussian-like memory cell, composed of a Gaussian transistor and a memristor, to ensure the tunable Gaussian-like current-voltage responses. Furthermore, we constructed the circuits based on Gaussian-like memory cells to accommodate the parallel inference computation of Kolmogorov-Arnold networks. This study demonstrates that the proposed architecture based on Gaussian-like memory cells can effectively maintain the algorithmic advantages across various tasks containing one-dimensional function regression, image recognition, partial differential equation solving, and time-series forecasting. Notably, the proposed architecture achieves significant improvements in energy efficiency. The results provide a promising avenue for computing-in-memory architecture for Kolmogorov-Arnold networks, and expand the flexibility and efficiency of the neuromorphic computing paradigm.

Introduction
With the rapid advancement of AI, from AlphaGo1 to ChatGPT-4o2,3, deep neural networks (DNNs) are evolving at an incredible pace, and it has a wide range of applications in various fields, including speech recognition, visual detection, and other fields such as protein structure prediction4,5. Multilayer perceptrons (MLPs)6,7 are regarded as the default frameworks for implementing nonlinear regressors in DNNs (Fig. 1a), the importance of which can never be overstated. DNNs have evolved to contain tens to hundreds of billions of parameters8, the demand for computational resources for MLPs are also growing rapidly. Notably, the typical computation process of MLPs involves a large number of vector-matrix multiplication (VMM) operations. However, due to the separation of memory and computational units, the von Neumann architecture, results in substantial energy consumption and high latency for data shuffling between units for implementing VMM9, severely limiting the computational efficiency of MLPs. In contrast, neuromorphic computing based on memristive devices with multilevel tunable resistance states offers a promising non-von Neumann computing paradigm10, where the network parameters are stored directly, eliminating the cost of data transfer. By directly using Ohm’s law for multiplication and Kirchhoff’s law for accumulation, they can build parallel computing-in-memory (CIM) units that support VMM11, improving the speed and energy efficiency of analog memory computing12,13. Such hardware implementations extend the integration density and computing efficiency of MLPs in utilizing huge computational resources14.

Recently, inspired by Kolmogorov-Arnold (K-A) theorem, Liu et al. proposed the Kolmogorov-Arnold Networks (KANs) as powerful alternatives to MLPs15. KANs replace linear weights with learnable activation functions, which are computed by combining multiple adjustable basis functions (Fig. 1b). This change offers several advantages, typically including flexibility and adaptability, allowing for the dynamic adjustment of activation functions and the ability to adapt to different data patterns16. Furthermore, KANs exhibit faster neural scaling laws15, meaning that performance improves faster as the model parameters increase. More uniquely, each basis function introduces the local plasticity similar to that of human brains17,18, enabling models to avoid catastrophic forgetting15,16. However, due to the demand for a large number of function superpositions, KANs incur higher complexity on conventional computing machines. In particular, the original KANs use third-order B-splines as the basis functions, which means that even a single B-spline must undergo three complex recursive operations15,19. In complementary metal-oxide-semiconductor (CMOS) technologies, this requires a large number of amplifiers, transistors, and chip area for operations, resulting in substantial hardware costs in the implementation for KANs.20 Specifically, due to the inherently complex mathematical design of KANs, which relies entirely on combinations of nonlinear parameterized basis functions (such as Gaussian kernels), traditional Von Neumann architectures struggle to handle such high-density computations. For instance, graphics processing units (GPUs) achieve high computational density by efficiently parallelizing simple and regular tasks, such as general matrix multiplications (GEMMs) in MLPs.21,22 In contrast, KANs’ intricate computation process and their inability to process data in batches require multiple kernel executions per forward pass, significantly increasing the CPU-GPU offloading23 pressure and reducing resource utilization.15 Moreover, memory bandwidth limitations and the overhead from data transfer further exacerbate power consumption and hardware resource demands,24 highlighting that KANs struggle to efficiently utilize resources within conventional architectures (the detailed explanation can be found in Supplementary Note 1).

Even for the near-memory implementations, such as ASICs based on look-up tables (LUTs)25 or piecewise linear (PWL) approximation26, incur significant hardware resource consumption due to the complexity of producing a single Gaussian kernel, requiring extensive circuits containing multipliers (MPLs), adders (ADDs), and comparators (COMPs). While conventional hardware can approximate Gaussian-like functions, this introduces overhead from address generation and memory access.25 Moreover, approaches like PWL approximation face bottlenecks with inflexibility and lack of support for dynamically learnable activation functions, as pre-stored parameters become invalid when the function updates, making such implementations unsuitable for KAN’s training and one-shot MAC computation27,28. Furthermore, on the analog side, while Gaussian-like functions can be emulated using transistors,29 these implementations require continuous and precise control of voltage and current. Meanwhile, such devices are volatile and easily lose stored information upon power loss, making them unsustainable for integrated arrays, especially in low-power edge computing scenarios where long-term computation is essential.

The aforementioned facts have demonstrated that traditional hardware implementations impede the full potential of emerging algorithmic architectures like KANs. The fundamental solution lies in developing computing-in-memory devices that not only overcome the issues outlined above but also inherently align with the computational attributes of KANs. Here, each Gaussian-like memory cell (GMC) is fabricated by combining an anti-ambipolar transistor (AAT)30 and a memristor to implement tunable Gaussian-like basis functions at the analog level, serving as a replacement for B-spline basis functions and enhancing KAN’s computation performance.15,31 This design naturally aligns with the fundamental requirements of KANs, enabling the integrated arrays to learn complex features with greater flexibility while supporting continual learning32,33. In electrical design, integrating GMECs into the crossbar arrays enables parallel in-memory computing tailored to KANs. Fig. 2 provides an intuitive summary, presenting the details of various device properties in developmental order. In addition, these implementations are thoroughly analyzed along two aspects—reference object and benchmark metrics—and documented in Supplementary Table 1.

Given this background, the performance of GMC-based KAN (G-KAN) architecture can be validated on multiple tasks across different domains. Specifically, given that KANs have demonstrated significantly superior continual learning capabilities compared to MLPs,15,16 this study verifies that the G-KAN architecture also successfully inherits the algorithmic advantages of KANs in various AI tasks. Under this premise, the CIM advantages of G-KAN in terms of parallel computation and energy efficiency are validated, thereby demonstrating the feasibility of the architecture.

Results
Structure of tunable Gaussian-like memory cells. The schematic diagram of integrating a Gaussian transistor in series with a Graphene/CuInP S (CIPS)/Graphene memristor to construct tunable GMC is shown in Fig. 1c. In detail, we constructed Gaussian transistors using MoS₂ (N-type semiconductor) and MoTe₂ (P-type semiconductor). By controlling the gate voltage to modulate the transition between the dominant operating states of different semiconductor types, then a Gaussian-like current distribution is generated (Fig. 1d). The memristor here modulates the voltage across the Gaussian transistor through voltage division, thereby tuning the variation of a Gaussian feature, as illustrated in Fig. 1e. To verify the device performance, we first characterized the electrical transport properties of the individual MoS and MoTe channels. The results, as shown in Fig. 3a, reveal electron and hole-dominated transport behaviors observed in MoS and MoTe , respectively, which are crucial for the formation of p-n junctions and Gaussian transistors.

Next, we study the single-gate operation mode of the heterojunction device by independently biasing the gate of the Gaussian transistors. Fig. 3b presents the transfer characteristics of the heterojunction under gate control. The device exhibits a typical Gaussian-like bipolar response relative to the control gate terminal. The V controlled transfer curve of the junction can be divided into four regions depending on the charge accumulation profiles while changing the electric fields. Supplementary Fig. 1 schematically illustrates the band alignment capturing the doping characteristics of these four regions. In Region I, due to its p-type dominant bipolar nature, holes accumulate in the MoTe channel, while the complete depletion of the n-type MoS channel fully turns off the heterojunction, resulting in the lowest junction current. As the gate voltage increases, the Fermi level gradually moves upward into the bandgap, leading to a moderate decrease in hole concentration in MoTe , while the electron doping level in MoS rapidly increases, enhancing the overall junction current (Region II). Region III refers to the stage where the depletion of the hole channel in MoTe occurs faster than the accumulation of electrons in MoS , resulting in a decrease in junction current until the heterojunction is turned off (region IV). In addition, as shown in Supplementary Fig. 2, varying the drain voltage (V ) still reveals that the current of the Gaussian transistors’ electrical transfer characteristics conforms to a Gaussian-like distribution34.

By using the memristor as a voltage divider structure, the characteristics of the GMC can be controlled. Supplementary Fig. 3 illustrates the I-V curves of three cycles of independent CIPS device, showing significant hysteresis characteristics. Under the influence of the applied electric field, Cu⁺ ions move out of the lattice and migrate in the direction of the electric field, accumulating near the cathode electrode, which continuously affects the conductivity of device35,36. When we stimulate the CIPS memristor with different write pulse counts (Fig. 3c), it can be reset to its initial state after each write pulse test, indicating the reconfigurable migration of copper ions induced by the applied electric field.

Subsequently, the electrical characteristics of the tunable GMCs are tested. In detail, Fig. 3d shows the changes in the current of the electrical transfer characteristics of the GMC under a fixed source-drain voltage after stimulated with different write pulses. As the number of write pulses increases, the peak current (I ) of the Gaussian curve also increases linearly, while both V and  only appear slight variations. The Gaussian-like distribution of current is modeled by the following equation:

I = I exp[−((V −V )/ )^2] (1)

where the I and V respectively represent the amplitude and mean of the Gaussian-like function, while  denotes a fitting parameter modeling I when V <= V , and  models I when V > V . Strong correlation between the experimental measurement data and the fitted curve is observed (Supplementary Fig. 4). These results clearly demonstrate that simple programming operations on the GMC can achieve controllable changes in the Gaussian-like distribution of the transfer characteristic current. To investigate the stability and reliability of GMCs, retention property37 and endurance38 evaluations are conducted. With applying two programming pulses to induce significant changes in the current, the transfer characteristic curves at 20 s, 40 s, 60 s, 80 s, and 100 s after programming illustrate virtually no changes compared to those observed immediately after programming (Fig. 3e). Fig. 3f displays the distribution of characterization parameters ( I and  ) in the Gaussian-like transfer characteristics of GMC devices under 1000 cycles test (Supplementary Fig. 5), with all results demonstrating relatively small coefficients of variation (CV). Moreover, the device-to-device uniformity is further corroborated (Supplementary Fig. 6). To further verify the learnability of GMCs, a 1×2 array is fabricated based on the characteristics of GMCs described above to represent the activation functions with continuously tunable characteristics. By applying 2, 4 and 6 pulses to each GMC, the weighted states are modulated accordingly, thereby being able to precisely control the shape of the output curve (Supplementary Fig. 7).

Circuit design for GMC-based hardware architecture. Inspired by the network topology of KANs (Fig. 4a), this work proposes a crossbar-compatible design of GMC arrays (Fig. 4b and 4c). For ease of reference, ‘GMC-based KAN’ is termed ‘G-KAN’ in this paper. Such the architecture enables the inference operations of KANs to be processed in parallel at the network level. Specifically, the G-KAN’s circuit integrates GMCs following the standard crossbar configuration13,14,39. As shown in Fig. 4b, electrical signals are conducted through densely arranged source lines (SLs), bit lines (BLs), and word lines (WLs). During computation, a constant voltage (V ) is applied to all WL rows to power the devices, while each BL row delivers the gate voltage ( V ) encoding the input signals (Supplementary Note 2). Subsequently, the GMCs located on the same SL column accumulate currents according to Kirchoff’s current law (KCL)40. To ensure that negative weight coefficients can be encoded while expanding the number of effective weights (i.e., device-encoded discrete weights), the differential-pair approach is adopted.14 Notably, the output current along the SL is first converted into a voltage by a transimpedance amplifier (TIA). Subsequently, the two output voltages of the differential pair are processed by an operational amplifier (op-amp) in the ‘Subtractor Configuration’ to generate the final amplified output voltage (Fig. 4c, Methods). Since each edge of the KAN (i.e., the learnable activation function) is essentially realized as a linear combination of multiple basis functions (Fig. 4d), each input variable (x) must be propagated to multiple Gaussian-like functions. Based on the property of function translation and the mathematical relationship between the input variable and the gate voltage (Methods), the voltage amplitude to be applied to each BL can be explicitly determined (Fig. 4e). In addition, as a complementary component of the integrated circuit analysis, the scalability of the fabricated devices within crossbar arrays is further evaluated, following the fabrication theories of self-rectifying devices and employing a half-biased read scheme, as detailed in Supplementary Note 3 and Supplementary Fig. 8.

Furthermore, in terms of topological scalability, a KAN can be extended beyond the combination of basis functions by additionally configuring a residual activation (b(x)).15 Since b(x) is entirely computed in the form of synapses, it can be developed in hardware by expanding with an additional memristor array (Supplementary Fig. 9). The output vector of the GMC array and the b(x) array are then superimposed along the corresponding dimensions to obtain the total output of the residual-enhanced G-KAN. This extension effectively addresses the vanishing and exploding gradient problems in deep neural networks, enabling more stable training and enhanced representational capacity.41 Notably, it should be emphasized that the residual connection serves only as an auxiliary component designed to further enhance training performance, rather than a replacement for the GMC array (see Supplementary Note 4 and Supplementary Fig. 12 for details).

To understand the potential of this neuromorphic architecture, we tested whether the G-KAN architecture can retain the algorithmic KAN’s inherent to overcome catastrophic forgetting15,16 using a toy example of the 1D function regression task with 5 Gaussian peaks. Simply put, catastrophic forgetting poses a significant challenge in machine learning, which occurs when a neural network is trained on task 1 and then switches to be trained on task 2, causing it quickly to forget how to perform task 115,42,43. Specifically, each Gaussian peak (f(x), x  [ − 1 , 1 ]) is independently train the G-KANs (in the size of [1,1]) using 1,000 data points, based on 100 basis functions per edge. During feedforward propagation, 5,000 input signals evenly spaced from -1 to 1 are transmitted into network successively, and then G-KANs output the fitted results (denoted as G-KAN(x)). Upon learning a new peak, the model remains capable of fitting the previous peaks. After training on the final Gaussian peak, the root mean square error (RMSE) between G-KAN(x) and the 5 peaks of the label data is merely 0.017 (Fig. 4e). Moreover, the above model is constructed and tested as a complete circuit on the Simscape Electrical platform, with detailed information provided in Supplementary Note 2 and Supplementary Fig. 13. Clearly, the G-KAN architecture can retain the algorithmic property to resist catastrophic forgetting15,16 during the continual learning process of representing functions. Furthermore, to eliminate the concern that the continual learning capability may stem from task correlation due to overlapping training samples rather than from the network’s inherent properties, the identical G-KAN mentioned above was tested on three additional non-overlapping function datasets. These evaluations eliminate the interference of task relevance and confirm the cross-functional universality of the G-KAN architecture in maintaining the continual learning capability of KANs (Supplementary Note 5 and Supplementary Fig. 14).

In terms of hardware execution efficiency, G-KANs significantly improve computational performance and reduces hardware overhead compared to conventional KAN architectures based on B-spline basis functions, which are typically implemented using CMOS technology20,44 (see Supplementary Note 6 and Supplementary Fig. 15). Meanwhile, Supplementary Note 7 and Supplementary Fig. 16 demonstrate the strong robustness of G-KANs across different domains. Furthermore, it is critical to emphasize the hardware benchmark comparison with CMOS architectures for evaluating the systematic performance of CIM architectures. This study conducted a comparison between the GMC-based system and two NVIDIA GPUs. Thanks to the inherent low power consumption of GMCs and the in-situ mechanism for parallel one-shot parameterized Gaussian kernel computation and accumulation, the GMC-based system can achieve two orders of magnitude greater energy efficiency compared to GPUs. The details of the hardware benchmark statistics, GPU product models, and comparison data can be found in Supplementary Note 8.

Further performance validation of G-KANs in various AI scenarios. Since KAN and MLP are considered fundamental building blocks supporting the skyscraper of modern deep neural networks, comparing their performance across different scenarios holds significant research value. To further explore the hardware portability of the algorithmic advantages, the G-KAN and the memristor-based MLP (M-MLP) are simultaneously trained on the same function dataset utilized in Fig. 4f to verify whether the G-KAN can retain the relative algorithmic advantages of KANs. Specifically, Supplementary Fig. 17 presents the performance of these two frameworks in the 1D function regression scenario, where the M-MLP proves to be incapable of handling the task. Even when the depth and model size of the M-MLP are substantially increased, it can at best fit the newly introduced peak while completely forgetting all previously learned peaks. Further details of this experiment can be found in Supplementary Note 5.

Function regression serves only as a basic evaluation perspective for KANs. For different input types (e.g., sequential data or image data), KANs have also validated to exhibit strong performance in tasks such as image classification45, PDE solving 46, and time-series forecasting47 (Fig. 5a). Especially, performance on pattern recognition tasks serves as an important reference for evaluating deep neural networks. When handling pattern recognition tasks, the dimension of G-KANs is extended as a fully connected (FC) deep neural network overall. Each input image is encoded into an unfolded sequence of pixels, with each pixel intensity (i.e., input signal (x)) assigning the corresponding gate voltages to a GMC array in the form illustrated in Fig. 4e. Herein, the size of G-KAN is set to [784, 100, 10], with a grid size (n ) of 4 for basis functions. After nearly 50 epochs (containing 60,000 images per epoch), the networks almost converge. Since the peak currents determine the shape of Gaussian-like functions, the overall state of the G-KAN is represented by the peak current heatmap of the GMC array. In this work, the peak current matrix and its variation in the final FC layer is shown in Fig. 5b, where the 4 rows represent 4 Gaussian-like functions, and the 1000 columns are derived from this layer containing 1000 edges. To compare the performance of KANs with MLPs on MNIST dataset48, the M-MLP is preset with the identical number of training parameters for fair evaluation. The configuration mechanism for parameter count alignment is explained in detail in Methods section. As shown in Fig. 5c, the converged recognition accuracy of G-KAN is comparable to that of M-MLP, which demonstrates the effectiveness of G-KAN architecture in performing pattern recognition at the hardware level. Meanwhile, due to the reduced number of intermediate-layer nodes, G-KAN allows the crossbar array to significantly reduce the number of configured SLs—by several folds—while maintaining the same count of neuromorphic devices. Taking the differential pair encoding scenario as an example, each output node essentially computes the result through double SLs.12,40 Furthermore, additional simulation results further confirm that the G-KAN architectures successfully replicate the faster neural scaling laws which have been verified on KANs15. (Supplementary Fig. 18).

Moreover, to validate whether the G-KAN architecture can maintain the continual learning advantage of KANs in pattern recognition scenarios, the experiment is executed by training G-KAN [784, 100, 10] (n = 4 ) and M-MLP [784, 500, 10] on task 1 (the MNIST dataset) for the first 10 epochs, and then continued to train them on task 2 (FMNIST dataset50) for another 10 epochs. The results demonstrate that G-KANs experience less than 0.1 times the descent of accuracy compared to M-MLPs’ due to the resistance to catastrophic forgetting (Fig. 5d). This indicates that the G-KAN architecture can replicate the KANs’ capability in continual learning even for pattern recognition tasks. In addition, the G-KAN and M-MLP frameworks are further evaluated their performance on PDE solving and time-series forecasting tasks, with details provided in the Supplementary Note 9. On the one hand, the first task involves solving a Poisson equation with zero Dirichlet boundary conditions15. As shown in Fig. 5e, the L2-norm error of G-KAN is substantially lower than those of the two M-MLP architectures, even when using the same or a smaller network size. On the other hand, both frameworks are evaluated on a time-series forecasting task (on the Mackey-Glass time-series system49), as illustrated in Fig. 5f. It is worth noting that the outputs of G-KAN closely match the ground truth in both the training and testing stages, achieving a RMSE of only 0.071. In contrast, the M-MLP models, even with deeper architectures, exhibit good fitting performance during training but suffer from poor generalization in the testing stage. Further experimental results on the time-series forecasting task can be found in Supplementary Fig. 19. In summary, the G-KAN architectures are capable to retain the cross-scenario performance advantages of KANs in hardware deployment.

To investigate whether G-KANs both demonstrate robustness in AI tasks involving sequential data or image data, G-KANs with sizes [1,1] (n = 100 ) and [784,64,10] ( n = 4 ) are tested on function regression and image classification, respectively. To more clearly highlight the anti-interference capability, the tests are conducted under intrinsic characteristic perturbations doubled in magnitude. Here, q denotes the amplification factor of the CV for each characteristic parameter. When q = 1 , the system operates under the intrinsic characteristic perturbations of GMCs; when q > 1 , it reflects the combined effects of external disturbances, thereby producing more severe perturbations.38 During normal array operation, considering the drift of the sensing circuits, q is expected to be only slightly greater than 1.40 As shown in Fig. 5g, G-KANs exhibit strong robustness, which is particularly important for the scalability of array integration50. In addition, for the correspondence between error statistics and the actual effect on GMC arrays, the detailed analysis can be found in Supplementary Note 10.

Methods
Fabrication and Measurement of GMCs. The memory cell was achieved by a dry transfer method. Graphene, hexagonal boron nitride (h-BN), MoTe , MoS , and CIPS flakes were mechanically exfoliated onto a silicon wafer coated with 285 nm SiO . For the Gaussian transistor, using optical microscope in combination with transfer stage at temperatures of 70-90 °C, graphene, h-BN, MoS , and MoTe were sequentially picked up with PDMS covered in polycarbonate and then placed on a blank silicon wafer at 180°C. The wafer was subsequently soaked in chloroform overnight to remove the polycarbonate layer. For the Gr/CIPS/Gr memristor, the same transfer method was used to sandwich the CIPS flake between two graphene flakes. Metal electrodes (Cr 8 nm/Au 50 nm) were then introduced onto the two parts through photolithography and electron beam evaporation. Finally, the two modules were connected using an ultrasonic wire bonder. The electric measurement of the cell was conducted using a EFS-Pro 380 semiconductor parameter analyzer. In the Gauss transistor test, MoS ends are grounded and voltage is applied from MoTe . For the GMCs test, one end of the memristor is grounded. Voltage is applied from MoTe . When the Gaussian-like current is regulated, a voltage is applied to the gate of the Gaussian transistor to the ON state.

Learnable coefficients encoded by the modulable Gaussian-like transfer characteristics of GMCs. Given G ( x ) e x p [ − ( ( x − V ) /  )^2 ] based on the co-center transfer characteristics, the GMC essentially outputs a scaled factor of G ( x ) (i.e., I G ( x ) ). Within a limited peak current range [I ,I ], the quantized Gaussian-like function becomes c G ( x ) . Notably, the c = (I - I ) / (I - I )  [ − 1 , 1 ], where the I+ and I− represent the minuend and subtrahend in a differential pair, respectively. Overall, this paradigm supports differential operations based on Gaussian-like functions at a hardware level.

Principle of MAC operations in G-KANs. Each b(x)-row is composed of a row of Gr/CIPS/Gr memristor differential pairs, and the synaptic weights are mapped onto the conductance of memristors. To facilitate electronic architecture, the Sigmoid linear unit ( SiLU ( x ) )15 in b(x) is replaced with the rectified linear unit (ReLU(x))15 (further details can be found in Supplementary Note 11, Supplementary Fig. 20 and 21). Therefore, the MAC operation of the G-KAN with extended residual connections can be expressed by the following equation:

y =  w ReLU(x) +   c G (x) (2)

Herein, x represents the any neuron in a layer, where the first term in the summation is  b ( x ), and the second term denotes the learnable activation functions (  ( x ) ) determined by the coefficients (c ). Then the neuron ( y ) in the next layer can be computed based on the MAC operation.

Simulation and configuration of G-KANs. The simulation in this work is conducted based on the Python framework and Simscape Electrical platform (Supplementary Note 2). Supplementary Note 12 provides the preset configurations for model training. In addition, the training parameters updated at each iteration are mapped to the physical states of the devices (i.e., peak currents for GMCs and conductance for memristors).

For parameter count alignment, since each edge in a KAN carries n additional training parameters compared to M-MLP, the number of parameters in G-KAN and M-MLP should satisfy the given equation:

P = ( 1 + n ) P (3)

Herein, P represents the number of training parameters in a network. Therefore, given that G-KAN is configured with a network architecture of [784, 100, 10] ( n = 4 ), the M-MLP with the same number of training parameters is configured as [784, 500, 10].

Data availability. All data that support the findings of this study are available within the article and its Supplementary Information files. The MNIST dataset utilized in this work are publicly available at https://pytorch.org/vision/main/generated/torchvision.datasets.MNIST.html, while the Fashion-MNIST (FMNIST) dataset utilized in this work is also publicly available at https://pytorch.org/vision/0.19/generated/torchvision.datasets.FashionMNIST.html.

Code availability. Code for the simulations is publicly available at Github (https://github.com/VennUeSTC-NeuroComput/GMCSimu).

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The paper proposed a computing-in-memory (CIM) implementation for Kolmogorov-Arnold Networks (KANs), to address KANs' efficiency issue. In place of cubic splines, the authors use Gaussian-like basis functions to parameterize univariate learnable activation functions. The Gaussian-like basis function can be achieved by a Gaussian-like memory cell (GMC), composed of a Gaussian transistor and a memristor (voltage divider structure). GMC-based KANs exhibit good performance and can avoid catastrophic forgetting in 1D function fitting and image classification. The compute-in-memory implementation is more efficient than previous KAN implementations and memristor-based multilayer perceptrons (MLPs). This paper addresses an urgent problem in AI: efficient hardware implementation of KANs. KAN is a new type of neural network proposed in early 2024. Despite its recency, it has been cited over 500 times due to its promising algorithmic abilities (accurate, interpretable, avoiding catastrophic forgetting). However, a major limitation of KANs is the lack of efficient hardware implementation. The MAC (multiply-accumulate) calculations in KANs are different from normal VMM (vector-matrix-multiplication) computations in MLPs. GPUs are designed to speed up VMM but not MAC, so KANs call for new hardware architectures that can support efficient MAC computations. This paper, to the best of my knowledge, is the first work to design KAN hardwares. Besides KANs, the proposed hardware is expected to have wide applications -- it can apply to many algorithms involving learnable activation functions or Gaussian kernels. However, I acknowledge that my main expertise is in software (algorithms), so I am unable to evaluate the novelty of GMC in the literature of electronics. The paper's claims are well supported by their evidence. It is satisfying to see that many algorithmic advantages of KANs are demonstrated: (1) neural scaling laws (Supplementary Figure 7); (2) continual learning (Figure 3); (3) scalability to images (Figure 4). However, there are a few algorithmic choices that seem somewhat arbitrary and should be better clarified: (1) In the 1D function fitting task, why is MAE loss used instead of the MSE loss? (2) For image classification, when switching from MNIST to Fashion MNIST, the optimizer is changed from Adam to SGD. What will happen if Adam is used for the second stage as well? (3) The comparison between KAN and MLP is subtle (this is a problem in the original KAN paper by Liu et al.), because when the network shape is kept the same, KANs may have more parameters than MLPs because of grid sizes. Figure 4c may not be a fair comparison since G-KANs have more parameters than M-MLPs. Supplementary Figure 7 is fairer since hyperparameters are swept, reflecting the performance-efficiency tradeoff. Figure 4d is fair since performance is fixed (90% accuracy). However, I did not find the corresponding shapes of KAN and MLP in Figure 4d. Also, it would be nice to have a mathematical formula, indicating how many GMCs and memristors are needed for a KAN with a given shape and a certain grid size, to show how the number of devices scales against the size of the KAN network. Minor comments: (1) in the abstract, 'a combination of finite basis functions', do you mean 'finite element'? (2) 'variable univariate activation functions', 'variable' is redundant? (3) I think 'symbolic regression' is not a correct word (symbolic regression means extracting out symbolic formulas of numeric data), instead using 'function fitting', 'function regression', 'supervised learning' or 'curve fitting', etc.", "reviewer_2": "While the manuscript proposes a hardware implementation of Kolmogorov-Arnold Networks (KANs) using Gaussian-like memory cells (GMCs), there are several significant concerns that, in my opinion, prevent it from being accepted for publication in Nature Communications. 1. The performance (higher accuracy and overcoming catastrophic forgetting) demonstrated in the manuscript primarily stems from the advantages of implementing neural networks using KAN. However, the manuscript does not sufficiently highlight the benefits of using GMC to implement KAN. 2. The manuscript lacks a comparative analysis between the proposed GMC-based KAN and a conventional CMOS-based KAN implemented on electronic computers, particularly in terms of key performance metrics such as energy consumption, device volume, and data throughput. 3. While simulations are used to illustrate the advantages of the proposed approach, they cannot serve as strong evidence, especially for a physical hardware system. There is often a significant gap between simulations and physical experiments, making the reliance on simulations insufficient to support the claims. 4. The manuscript does not sufficiently address whether the scalability and stability of the GMC array can support a larger KAN for more complex intelligence tasks. A further theoretical analysis of the scalability limits of the GMC array would be valuable. 5. The physical experiments presented in the manuscript focus solely on the performance of a single device. However, the manuscript does not discuss whether the proposed GMC array relies on consistency between different units and whether this could lead to additional hardware overhead. There is a lack of relevant discussion regarding the robustness of the proposed structure. 6. The GMC-based KAN proposed in the manuscript is based on real-world analog devices. However, any analog device inevitably introduces errors, especially in large-scale arrays, where the impact of errors becomes more significant. The manuscript lacks a discussion and analysis of these errors, which raises doubts about the feasibility of the proposed architecture. 7. In the experiment validating the continual learning capability of the GMC-based KAN, the presented 1D symbolic regression task does not provide strong evidence. Factors such as task correlation and potential parameter redundancy may interfere with the conclusions. The study lacks comparative experiments or continual learning experiments across different 1D regression tasks to make the conclusion more convincing. 8. In the comparison between KAN and MLP, the parameter counts corresponding to the same network size (764-64-10) for KAN and MLP are not comparable (KAN has more parameters). The specific details of the network configurations are not presented to demonstrate the fairness of the comparison. To ensure a fair comparison, more details about the network structures and parameter settings should be provided. 9. In the MNIST handwritten digit classification task, as shown in the training curves (Fig. 4c and 4e), it appears that neither the GAN nor the MLP training process has fully converged. Therefore, such results cannot rigorously demonstrate the performance differences between the two methods. 10. The symbol regression and MNIST image classification tasks presented in the manuscript have shown the basic intelligence computing capacity for the GMC-based KAN. However, these tasks could also be well-handled by conventional MLP or CNN networks. To proof the advances of the proposed physical KAN, extra tests on more complex tasks e.g., CIFAR or ImageNet tasks will be appreciated. In conclusion, the unclear advantages of the proposed method and the lack of sufficient experimental validation significantly limit its potential to make a meaningful contribution to the field. Therefore, I do not recommend its publication in NC.", "reviewer_3": "The manuscript proposes a Gaussian-like memory cell (GMC), consisting of a Gaussian transistor and a memristor, as the basis function for Kolmogorov-Arnold Networks (KAN), an emerging neural network algorithm. While exploring efficient hardware implementations of KAN is an important topic, this manuscript only scratches the surface, relying on pure simulation data and very limited experimental results from a single cell. Further analysis and more comprehensive studies are necessary for this manuscript to be considered for publication. Detailed comments are as follows: 1. The core contribution of this work is the development of the GMC. However, the manuscript only provides minimal experimental data, such as the transfer curve of the memory cell in Fig. 2. Additional device characterization, such as endurance testing etc., is recommended to demonstrate the reliability and learning capability of the proposed memory cell. In other words, what are the full suite of device properties that are required to run the KAN algorithm? 2. The circuit design presented in Fig. 3 is more of a functional block representation than a detailed circuit implementation. To adequately demonstrate the circuit-level design, the manuscript should include explicit circuit diagrams for the key blocks rather than just describing their functions. More importantly, a circuit capable of running the KAN should be experimentally built and tested. 3. Are the results shown in Fig. 3e from experimental setups or pure simulations? If they are based on experimental setups, a photo of the memory cell array should be included to support the findings. The manuscript should provide clear details on the simulation setup and parameters if they are from simulations. 4. The claim regarding “continual learning resilience against catastrophic forgetting” in Fig. 3 appears to be an inherent benefit of the KAN rather than the GMC. To substantiate this claim, a comparative analysis should be conducted by evaluating the performance of the same KAN structure using the GMC versus other basis functions. Otherwise, this claim only reiterates the advantages of KAN without demonstrating the specific contributions of the GMC. 5. Similarly, beyond simply demonstrating that G-KAN can perform classification tasks like KAN, the manuscript should include studies on the trade-offs introduced using the GMC. Specifically, the impact of computing noise from the analog device on the performance of G-KAN should be evaluated, as well as its generalization capability to other tasks when using only a Gaussian-like function as the basis function."}, "author_response": "Point-to-point response to reviewer’s comments\nResponse to Reviewer 1's comments\nGeneral comment: The paper proposed a computing-in-memory (CIM) implementation for Kolmogorov-Arnold Networks (KANs), to address KANs' efficiency issue. In place of cubic splines, the authors use Gaussian-like basis functions to parameterize univariate learnable activation functions. The Gaussian-like basis function can be achieved by a Gaussian-like memory cell (GMC), composed of a Gaussian transistor and a memristor (voltage divider structure). GMC-based KANs exhibit good performance and can avoid catastrophic forgetting in 1D function fitting and image classification. The compute-in-memory implementation is more efficient than previous KAN implementations and memristor-based multilayer perceptrons (MLPs).\nThis paper addresses an urgent problem in AI: efficient hardware implementation of KANs. KAN is a new type of neural network proposed in early 2024. Despite its recency, it has been cited over 500 times due to its promising algorithmic abilities (accurate, interpretable, avoiding catastrophic forgetting). However, a major limitation of KANs is the lack of efficient hardware implementation. The MAC (multiply-accumulate) calculations in KANs are different from normal VMM (vector-matrix-multiplication) computations in MLPs. GPUs are designed to speed up VMM but not MAC, so KANs call for new hardware architectures that can support efficient MAC computations. This paper, to the best of my knowledge, is the first work to design KAN hardwares. Besides KANs, the proposed hardware is expected to have wide applications -- it can apply to many algorithms involving learnable activation functions or Gaussian kernels. However, I acknowledge that my main expertise is in software (algorithms), so I am unable to evaluate the novelty of GMC in the literature of electronics.\nThe paper's claims are well supported by their evidence. It is satisfying to see that many algorithmic advantages of KANs are demonstrated: (1) neural scaling laws (Supplementary Figure 7); (2) continual learning (Figure 3); (3) scalability to images (Figure 4).\nResponse: We sincerely thank you for your constructive comments on our manuscript and are very pleased that the work has made a positive impression. In particular, your insights regarding the architectural challenges and the broader relevance of the proposed solution have deeply inspired us. We have carefully revised the manuscript in accordance with your suggestions, including conducting more experiments, enhancing the quantitative analysis, and presenting clearer comparative results. We hope these improvements further demonstrate the potential of the GMC-based KAN framework.\nComment 1-1: In the 1D function fitting task, why is MAE loss used instead of the MSE loss?\nResponse 1-1: Thank you for your insightful comments. We have compared the performance of MSE and MAE losses during training process using the root mean squared error (RMSE, the standard evaluation metric for function fitting) as the evaluation metric (arXiv: 2404. 19756 (2024)). Experimental results demonstrated that utilizing MAE loss yields slightly better fitting performance. In contrast, MSE loss tends to cause more pronounced local oscillations at the junctions between Gaussian peaks (Fig. R1).\nThe unstable convergence behavior of MSE stems from its mathematical formulation (MSE is the mean of the sum of squared errors): as prediction errors approach zero (Fig. R2), the squaring operation causes gradients to diminish rapidly, potentially leading to vanishing gradients and training instability (PeerJ Comput. Sci. 7, e623 (2021)). In contrast, MAE provides a constant, non-zero gradient almost everywhere (except at zero error) (Fig. R3), promoting more stable optimization where the errors close to zero between Gaussian peaks.\nFigure R1 | Function fitting performance of G-KAN with MSE and MAE loss functions.\nFigure R2 | Visualization of the absolute errors (Abs. Errors) between the KAN outputs and the label data for each segment in the Gaussian peak dataset scenario. The red vertical lines indicate the junctions between adjacent peaks, while the cyan boxes highlight regions where the prediction error is very small (error ≈ 0).\nFigure R3 | Visualization of the MSE and MAE loss functions. The point where each curve touches (for MSE curve) or intersects (for MAE curve) the line (error = 0) corresponds to distinct gradient behaviors for the respective loss functions.\nComment 1-2: The comparison between KAN and MLP is subtle (this is a problem in the original KAN paper by Liu et al.), because when the network shape is kept the same, KANs may have more parameters than MLPs because of grid sizes. Figure 4c may not be a fair comparison since G-KANs have more parameters than M-MLPs. Supplementary Figure 7 is fairer since hyperparameters are swept, reflecting the performance-efficiency tradeoff.\nResponse 1-2: Thank you for your valuable comment regarding the fair comparison between KAN and MLP. For parameter count alignment, since each edge in a KAN carries n additional training parameters compared to MLP (arXiv: 2404. 19756 (2024)), c the number of training parameters in G-KAN and M-MLP should satisfy the given equation:\nP (1n )P (R1)\nKAN c MLP\nHerein, P represents the number of training parameters in a network, and n is the c number of Gaussian-like basis functions contained in each edge of the KAN (i.e., the grid size).\nGiven that G-KAN is configured with a network architecture of [784, 100, 10] (n  4), and M-MLP with the same number of training parameters is configured as c [784, 500, 10]. Based on these presets, as shown in Fig. R4, the converged recognition accuracy of G-KAN is comparable to that of M-MLP, which demonstrates the effectiveness of G-KAN as a novel AI framework at the hardware level. Excitingly, due to the reduced number of intermediate-layer nodes, G-KAN allows the crossbar array to significantly reduce the number of configured source lines (SLs)—by several folds—while maintaining the same number of neuromorphic devices. Taking the differential pair encoding scenario as an example, each output node essentially computes the result through two SLs (Nature 577(7792), 641-646 (2020); Nat. Commun. 9, 2385 (2018)). This demonstrates that G-KAN can substantially reduce the footprint of neuromorphic computing chips. The combination with our proposed hardware foundation—implementing KANs in analog CIM systems—opens new potential for advancing the practical capabilities of this promising architecture. To further explore the advantageous applications of G-KANs, we compared the performance of G-KANs and M-MLPs in additional scenarios. Specifically, we successfully validated the advantages of G-KANs on PDE and time-series tasks. Detailed information can be found in the response to Comment 2-10.\nFigure R4 | The learning performance of G-KAN ([784, 100, 10], n = 4 ) is c comparable to that of M-MLP [784, 500, 10] (equal training parameters) on image classification task.\nWe have added this discussion to the revised main text (on page 12 and 17). Fig. R4 has been included as Fig. 4c in the revised main text.\nComment 1-3: For image classification, when switching from MNIST to Fashion MNIST, the optimizer is changed from Adam to SGD. What will happen if Adam is used for the second stage as well?\nResponse 1-3: We appreciate your attention to this detail. To clarify, there was no optimizer switching when transitioning from MNIST to Fashion-MNIST in our experiments. The confusion may have arisen from the original phrasing in the Supplementary Information, which we have revised for clarity.\nYour question motivated us to conduct additional experiments using the AdamW optimizer for both datasets under settings with identical training parameter counts. Specifically, we compared G-KAN ([784, 100, 10], n = 4) and M-MLP ([784, 500, c 10]) trained with SGD or AdamW in continual learning scenarios. When using AdamW as the optimizer, G-KAN showed little impairment in accuracies on task 1 after task switching, but failed to learn the data from task 2—the accuracy remained at 10%, without showing any improvement during training (see the lower panel of task 2 in Fig. R5). Meanwhile, M-MLP achieved over 60% accuracy on task 2, yet its performance on task 1 plummeted to 10% accuracy after switching tasks, indicating severe catastrophic forgetting.\nAbove results indicate that AdamW is not suitable as an optimizer for continual learning in these frameworks, and further support the choice of using SGD in this scenario.\nFigure R5 | Comparison of continual learning performance for pattern recognition from MNIST (during first 10 epochs) to FMNIST (during subsequent 10 epochs) between G-KAN ([784, 100, 10], n = 4) and M-MLP [784, 500, 10] with AdamW optimizer. c\nComment 1-4: Figure 4d is fair since performance is fixed (90% accuracy). However, I did not find the corresponding shapes of KAN and MLP in Figure 4d.\nResponse 1-4: We appreciate your attention to details, and your feedback helps us to improve the quality and clarity of our work. For Fig. 4d in original manuscript, the required size for G-KAN is [784, 22, 10], while the required size for M-MLP is [784, 144, 10]. The specific calculation and corresponding model shapes are provided in Fig. R6.\nFigure R6 | Mathematical relationship between the number of devices and the network topology.\nComment 1-5: Also, it would be nice to have a mathematical formula, indicating how many GMCs and memristors are needed for a KAN with a given shape and a certain grid size, to show how the number of devices scales against the size of the KAN network.\nResponse 1-5: Thank you for raising this important point, and we elaborate more about this detail. Specifically, the size of G-KAN has the following relationship with the number of consumed devices:\nC C C 2(1n )S (R2)\ndevice GMC memristor c\nHerein, S denotes the total amount of edges in the G-KAN, while C device represents the cost of devices in total. Notably, C = 2n S and C = 2S denote GMC c MEM the costs of GMCs and memristors, respectively. The factor ‘2’ comes from the use of differential pairs—each learnable parameter is implemented using 2 physical devices.\nWe have added the both contents in response to Comment 1-4 and 1-5 to Supplementary Note 7 and Supplementary Fig. 17. And also referenced it on page 12 to the revised main text.\nComments 1-6: Minor comments: (i) in the abstract, 'a combination of finite basis functions', do you mean 'finite element'? (ii) 'variable univariate activation functions', 'variable' is redundant? (iii) I think 'symbolic regression' is not a correct word (symbolic regression means extracting out symbolic formulas of numeric data), instead using 'function fitting', 'function regression', 'supervised learning' or 'curve fitting', etc.\nResponse 1-6: We appreciate your detailed comments and address them point by point below:\n(i) These two concepts differ significantly in both mathematics and application. ‘A combination of a finite number of basis functions’ stems from the Kolmogorov-Arnold representation theorem (KART), which states that any multivariate function can be expressed as a superposition of a finite number of continuous univariate functions (arXiv: 2407.11075 (2024)). This contrasts fundamentally with finite element methods, as KART’s finite basis requirement ensures feasibility for hardware implementation, whereas infinite bases are impractical. Thus, the term ‘finite’ here highlights the practicality of implementing KANs in hardware.\n(ii) The term 'variable' here is not redundant but serves to emphasize the contrast with fixed activation functions in MLPs. In KANs, since the coefficients of basis functions are trainable, the resulting activation functions can theoretically approximate any shape. This inherent flexibility distinguishes KANs from MLPs.\n(iii) We appreciate your valuable suggestion. After discussion, we have modified ‘symbolic regression’ to ‘function regression’ throughout the revised main text and Supplementary Information.\nResponse to Reviewer 2's comments\nGeneral comment: While the manuscript proposes a hardware implementation of Kolmogorov-Arnold Networks (KANs) using Gaussian-like memory cells (GMCs), there are several significant concerns that, in my opinion, prevent it from being accepted for publication in Nature Communications.\nResponse: We sincerely thank the reviewer for the assessment and for pointing out several important concerns. We understand the high standards of Nature Communications, and we acknowledge that rigorous evaluation is essential to ensure the scientific robustness and impact of published work. In response to the reviewer’s concerns, we have carefully revised the manuscript and addressed each issue point-by-point (see detailed responses below). Specifically, we have strengthened the experimental evidence supporting the stability of the proposed cells. In addition, based on further simulations with varying levels of physical noise arising from non-ideal variability, we analyzed the impact of device variability on robustness. We believe these additions significantly enhance the clarity, depth, and overall scientific contribution of our work.\nThere is no doubt that exploring efficient hardware implementations of KANs is a critical and urgent challenge in AI, as noted by the other two reviewers. However, this area is still in its early stages of development. Therefore, our proposed architecture—based on programmable memristors—represents a significant step forward. It offers notable advantages in terms of power efficiency, robustness, and error tolerance. We hope these revisions and clarifications help address the reviewer’s concerns and effectively demonstrate the potential of our hardware-based KAN implementation to make a meaningful contribution to the field.\nComment 2-1: The performance (higher accuracy and overcoming catastrophic forgetting) demonstrated in the manuscript primarily stems from the advantages of implementing neural networks using KAN. However, the manuscript does not sufficiently highlight the benefits of using GMC to implement KAN.\nResponse 2-1: Thank you for your valuable suggestion, as it gives us an opportunity to further elaborate on the novelty of using GMCs to implement KAN. Currently, parallel hardware accelerators, such as GPUs, are not optimized for the spline function computations central to KAN, limiting its scalability and practical deployment. To fully unlock KAN’s potential for improved accuracy and resistance to catastrophic forgetting, a hardware-software co-design approach is essential. To this end, we leveraged the learnability of memristors to propose a solution that utilizes GMCs for efficient hardware acceleration of physical KAN.\nThe original KAN employs B-spline basis functions, which require third-order Cox-De Boor recursive computations (arXiv: 2404.19756 (2024)), resulting in high computational and energy costs. In contrast, GMC directly generates Gaussian-like basis functions (serving as a faster alternative basis function to B-spline for computation), greatly reducing computational complexity. Moreover, replacing B-splines with Gaussians at the same model size can significantly improve forward propagation efficiency. In 1D function regression and pattern recognition tasks, this substitution achieved a speedup of 2.073× and 2.166×, respectively, as shown in Fig. R7.\nAlthough previous studies have proposed using lookup tables (LUTs) in digital circuits to approximate B-spline functions and reduced recursive operations (Proceedings of the 30th Asia and South Pacific Design Automation Conference 693-699 (2025); 2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW) 110-116 (2024)), LUTs suffer from severe scalability limitations. Their size increases exponentially with the number of classes, causing a sharp increase in the required number of transistors, and severely limiting the scalability of physical KAN. Although implementing B-spline functions with analog circuits offers certain advantages in resource utilization and potential scalability (arXiv: 2502.01489 (2025)), both analog and digital designs generally rely on physically separated computing and memory architectures, fundamentally limiting computational efficiency.\nIn comparison, GMCs inherently generate Gaussian-like functions, reducing the complexity of generating basis functions, while enabling computing in memory. More importantly, GMC’s inherent programmability and in-situ computation capabilities, are well-suited for physical KAN’s implementations. Table R1 provides a direct comparison of hardware resources, clearly demonstrating that employing GMCs in building efficient physical KAN systems allow to significantly reduce hardware usage and energy consumption.\nFigure R7 | Statistics on the time consumption of basis functions based on GMCs or B-splines in KANs.\nTable R1 | Comparison of different ways to implement spline functions\nAmp. Num. of Area Power\nRef. Mode function Memory\nadjustability devices (mm2) (μW)\nNakashima\ndigital B-Spline No No LUTs* (96) - -\net al.\nYu et al. digital B-Spline No No LUTs* (96) - -\nLozano\ndigital B-Spline No No - 9.111 266.735\nDuarte et al.\nLozano\nanalog B-Spline No No 42 0.073 238.5\nDuarte et al.\nThis work analog Gaussian Yes Yes 2 2.2×10-4 ~ 10-3\n* The transistor count estimation for each 4-input LUT (4-LUT) is based on the architecture of Xilinx Virtex-4 FPGAs, where each 4-LUT can be configured as a 16-bit distributed RAM. Assuming each SRAM bit cell comprises six transistors, the total transistor count per 4-LUT can be approximated by multiplying the number of SRAM cells (16) by six, resulting in approximately 96 transistors per LUT.\nThis discussion has been added to the revised main text on page 10, Supplementary Note 5, and Fig. R7 has been included as Supplementary Fig. 13c in the revised Supplementary Information. Table R1 has been included as the Supplementary Table 2.\nComment 2-2: The manuscript lacks a comparative analysis between the proposed GMC-based KAN and a conventional CMOS-based KAN implemented on electronic computers, particularly in terms of key performance metrics such as energy consumption, device volume, and data throughput.\nResponse 2-2: Thank you for raising this important point. We have identified three prior studies on the CMOS-based hardware implementation of KAN, which are summarized in Comment 2-1 and Table R1. All of these prior studies, regardless of whether they are based on digital or analog CMOS design, rely on a memory–computation separated architecture to implement spline functions, which introduces significant data movement overhead and thus fundamentally limits the efficiency of physical KAN implementations.\nLozano Duarte et al. reported that the digital CMOS implementation consumed 266.735 μW of power and occupied an area of 9.111 mm², whereas the analog CMOS version consumed 238.5 μW and required 0.073 mm² (arXiv: 2502.01489 (2025)). In contrast, our proposed GMC achieves a significantly lower power consumption on the order of nanowatts (calculated as operating multiplication of voltage and current), with an area of only 2.2×10⁻⁴ mm², thereby demonstrating advantages in both energy efficiency and area.\nThis discussion has been added to the revised main text on page 10 and Supplementary Note 5 in the revised Supplementary Information.\nComment 2-3: While simulations are used to illustrate the advantages of the proposed approach, they cannot serve as strong evidence, especially for a physical hardware system. There is often a significant gap between simulations and physical experiments, making the reliance on simulations insufficient to support the claims.\nResponse 2-3: We appreciate your valuable feedback regarding the need for experimental validation, and we fully agree that there is a gap between simulations and physical experiments. While physical verification is essential in circuit design, simulation remains an indispensable tool for demonstrating theoretical feasibility and guiding future hardware development. In this work, we aim to present a hardware-software co-design framework that can motivate further experimental studies.\nFor the hardware implementation of G-KAN, we have conducted comprehensive device verification and mechanism analysis (Fig. 2, revised manuscript), and further illustrated the circuit design (Supplementary Note 1 and Fig. 8 and 10, revised Supplementary Information). Those have proven the feasibility of realizing Gaussian-like functions and in-memory computing. However, fabricating fully integrated physical arrays remains prohibitively expensive for most academic laboratories, a common challenge across the industry. As a result, investigating individual devices and validating the proposed architecture through simulations represent a critical and practical approach (Nat. Electron. 6, 870-878 (2023); Nat. Electron. 7, 705-713 (2024); Nat. Commun. 14, 468 (2023)).\nOur simulation experiments, based on realistic GMC device properties, not only offer important reference data, but also provide practical solutions for hardware system design and optimization. Through these strategies, we've determined key parameter requirements, optimized the architecture, and reduced the simulation-to-physical gap by introducing random noise. These efforts confirm G-KAN's feasibility, lay a solid theoretical and design foundation for future chip manufacturing, and mitigate risks and costs in subsequent physical implementation.\nThis discussion has been also added to the revised main text on page 10 and Supplementary Note 5 in the revised Supplementary Information.\nComment 2-4: The manuscript does not sufficiently address whether the scalability and stability of the GMC array can support a larger KAN for more complex intelligence tasks. A further theoretical analysis of the scalability limits of the GMC array would be valuable.\nResponse 2-4: We thank the reviewer for the insightful comments. It is indeed very important to take measures to verify the stability of GMCs. Experimental characterization of individual GMC devices constructed on 2D materials demonstrates robust and reproducible Gaussian-like conductance profiles, indicating that each cell can operate reliably. This device-level stability supports the feasibility of constructing large-scale arrays. Moreover, preliminary tests on a prototype composed of two GMC units show tunable and gradually varying activation functions, indicating the potential for learning capability, as shown in Fig. R8.\nRegarding the theoretical analysis of scalability limits, we agree that this is an important direction. One promising approach is to develop a modeling framework that accounts for device variability and analyzes how key performance metrics—such as accuracy or robustness—change with network scale. We decided to extend our existing simulation models by incorporating non-idealities originated from real devices to quantify performance at larger scales. In Response 2-6, we have provided an analysis based on these modeling results.\nFigure R8 | Endurance performance and programmable activation function construction using parallel GMC units. a 1000-cycle endurance tests. b A parallel circuit of two GMCs. c Curves of current versus gate input voltage for two parallel GMC units after applying 2, 4, and 6 pulses to individual GMCs, and the constructed activation functions (colored).\nThis discussion has been added to the revised main text on page 7, Fig. R8a has been included as Fig. 2f to the revised main text. Fig. R8b and c have been included as Supplementary Fig. 7.\nComment 2-5: The physical experiments presented in the manuscript focus solely on the performance of a single device. However, the manuscript does not discuss whether the proposed GMC array relies on consistency between different units and whether this could lead to additional hardware overhead. There is a lack of relevant discussion regarding the robustness of the proposed structure.\nResponse 2-5: Thank you for your insightful comment. To validate the feasibility of our proposed GMC-based KAN architecture and provide realistic device characteristics for further application simulation, our experiments primarily focus on evaluating the basic functionality and performance of actual GMCs. This allows the weighted coefficients of these cells to be dynamically adjusted during training to automatically compensate for effects such as current drift caused by device variations (Nature 577, 641-646 (2020); Nat. Commun. 9, 2385 (2018)). Such adaptability significantly reduces the reliance on device uniformity and eliminates the need for additional calibration circuits.\nTo assess the robustness of our proposed structure, we added additional experiments to evaluate the robustness of the KAN implementation based on GMC under device-to-device (D2D) variability. Considering that the computational error caused by D2D variability, as well as the errors induced by noise in analog devices, are both due to non-idealities in the cell output. Thus, the corresponding results and analyses are discussed in detail in our unified response to Comment 2-6. The results show that although increased device variability introduces some performance degradation, the decline is gradual and remains within an acceptable range.\nIn conclusion, the impact of GMCs’ variability can be automatically compensated during in-situ training, without significantly affecting the performance of G-KAN. Therefore, no additional hardware overhead is required to enforce perfect consistency.\nComment 2-6: The GMC-based KAN proposed in the manuscript is based on real-world analog devices. However, any analog device inevitably introduces errors, especially in large-scale arrays, where the impact of errors becomes more significant. The manuscript lacks a discussion and analysis of these errors, which raises doubts about the feasibility of the proposed architecture.\nComment 2-6: We sincerely thank the reviewer for this insightful and constructive comment regarding the potential impact of analog device errors on the proposed GMC-based KAN architecture. As with any analog computing system, real-world implementation inevitably exists non-idealities, especially in large-scale arrays. Against this background, a central advantage of the proposed architecture lies in its use of programmable memristors, enabling each GMC’s learnable coefficient to adaptively compensate for non-ideal effects—such as current drift induced by device variability—during the training process (Nature 577, 641-646 (2020); Nat. Commun. 9, 2385 (2018)). This intrinsic adaptability substantially mitigates the influence of analog device imperfections on system performance.\nIn addition, in our proposed architecture, the observed errors can be attributed primarily to two sources: (1) device variability, including both device-to-device and cycle-to-cycle variations; and (2) external disturbances that introduce random fluctuations. Both types of errors manifest as non-idealities in the Gaussian-like output of the GMC and can be modeled by introducing the coefficient of variation (C ) (Nat. V Commun. 15(1), 129 (2024)) into the amplitude, σ , and σ of realistic GMC devices + - (Fig. R9a-c). This strategy allowed us to simulate a series of Gaussian-like activation functions with computational noise (Fig. R9d), which derives from the non-idealities of realistic devices.\nTo evaluate the impact of errors on the performance of G-KANs, we conducted two typical task types: regression and classification tasks. In the 1D function regression task, despite the injected noise, the G-KAN maintained a high level of fitting precision, indicating minimal performance degradation after in-situ learning. To further evaluate the robustness of the G-KAN’s model, the C values were scaled by a factor q (denoted V as q×C, which refers to scaling these C s to q times their original values) to simulate V different levels of non-idealities. Note that C denotes the set of C , i.e., {C , C , V amp σ- C }. When q 1 , it indicates that only the intrinsic variability of the device is σ+ considered, whereas q 1 implies the presence of additional external disturbances. As shown in Fig. R10a, the RMSE gradually increases with the factor q from 1 to 50 on the 1D function regression task. Even under the noise levels increased up to 50 times the intrinsic case, the RMSE on this task remained below 0.4, demonstrating the robustness of the G-KAN architecture under severe variation conditions. Furthermore, we also evaluated noisy G-KAN’s performance in pattern classification task. As illustrated in Fig. R10b, the learning curves under different noise presets show that the classification performance also remained robust under realistic noise conditions introduced by GMCs’ variability and external disturbances. On the other hand, in response to Comment 2-4, when incorporating the intrinsic non-idealities of GMCs, the G-KAN was evaluated on a more complex classification task by enlarging the architectural scale. The results demonstrate that systematic performance was scarcely affected, as illustrated in Fig. R10c.\nFigure R9 | Non-idealities of GMCs and the generated Gaussian-like curves. Fitting statistics for 1000-cycle endurance tests. a I , b   and c   . d Visualization of the peak     Gaussian-like functions generated by the GMCs after incorporating analog noise.\nFigure R10 | Robustness evaluation of the G-KAN under device non-idealities and increasing architectural scalability. a 1D function regression performance under variable coefficients of variation. b Performance of G-KAN ([784, 64, 10], n = 4) on c the pattern recognition task (MNIST) with various C s of device inconsistency V introduced. c Learning curves recorded under the incorporation of GMC non-idealities as scalability increases (on FMNIST dataset).\nThe contents in response to Comment 2-5 and 2-6 have been added to the revised main text (page 7 and 10). Fig. R9a-c have been included as Supplementary Fig. 6, and Fig. R9d has been included as Supplementary Fig. 14a. Fig. R10 has been included as Supplementary Fig. 14b-d.\nComment 2-7: In the experiment validating the continual learning capability of the GMC-based KAN, the presented 1D symbolic regression task does not provide strong evidence. Factors such as task correlation and potential parameter redundancy may interfere with the conclusions. The study lacks comparative experiments or continual learning experiments across different 1D regression tasks to make the conclusion more convincing.\nResponse 2-7: Thanks for your profound comments, which are crucial for the rigor and scientific validity of this study. We have added additional experiments in two aspects: parameter redundancy and task correlation to alleviate readers' concerns in these regards:\n(1) Parameter redundancy\nG-KAN has more parameters than M-MLP in the same network architecture (arXiv: 2404.19756 (2024)). Therefore, if M-MLP, even with the same or even more parameters, still fails to achieve continual learning like KANs, this would help rule out the concern about parameter redundancy. As depicted in Fig. R11a, since the G-KAN was configured with 100 basis functions, the M-MLP initially preset a size of [1, 100, 1] to match the parameter count of both models. However, as clearly observed in Fig. R11b, the M-MLP failed to achieve even basic fitting, let alone continual learning.\nAdditionally, after expanding the depth of the M-MLP sufficiently, the well-formed fitting Gaussian functions can be finally observed. Regrettably, each time the model learned a new Gaussian peak, it forgot all previous peaks, demonstrating that the M-MLP completely lacks the capability for continual learning in 1D function regression scenarios (Fig. R11c). These results further solidify the recognition that KANs, with their local activation capabilities, inherently possess continual learning as a functional attribute, in contrast to MLPs, which rely on global activation.\nFigure R11 | The continual learning capability validations of the G-KAN and M-MLP on 1D function regression. a Fitting results of G-KAN ([1, 1], n = 100). b Fitting results c of M-MLP [1, 100, 1], showing no successful fitting. c Fitting results of M-MLP [1, 50, 50, 50, 200, 1], exhibiting very severe catastrophic forgetting.\n(2) Task correlation\nIn previous experiments, each function period in a dataset was obtained via translation, and all periods consisted entirely of Gaussian functions. To mitigate potential concerns regarding task correlation, we ensured that the data within different periods of the dataset did not completely overlap, and also introduced datasets generated by other functions. Based on this approach, function regression performed on this basis can validate whether the continual learning capability of G-KANs is independent of task correlation. This scenario encompasses three cases: non-Gaussian periodic, non-periodic, and piecewise functions.\nSpecifically, Fig. R12a presents a periodic function, but since each half wave is treated as a separate subset, the training samples in each period do not completely overlap. In contrast, Fig. R12b presents a non-periodic function, under which G-KAN continues to exhibit strong continual learning capability. Fig. R12c represents a more challenging case, in which the G-KAN is trained on a piecewise function with intentionally introduced discontinuities between segments to minimize task correlation. As illustrated in this subplot, even when presented with unrelated sequential data, the G-KAN still demonstrates effective continual learning performance. Apart from a slight impact near the discontinuous boundaries, no significant catastrophic forgetting can be observed throughout the whole process. From the three subplots in Fig. R12, it is clearly observed that whether the dataset consist of periodic, non-periodic, or piecewise functions, G-KANs can perfectly fit the ideal function curves. This set of experiments demonstrated that, the capability of G-KANs to achieve continual learning is not a result of task correlation.\nBased on the experimental results mentioned above, the continual learning capability of G-KANs is independent of parameter redundancy and task correlation.\nFigure R12 | Fitting performance of the G-KAN on non-repetitive function datasets. Models are trained by a single non-Gaussian periodic function (a), a non-periodic function (b), and a piecewise discontinuous function (c).\nThis discussion has been added to the revised main text (page 10 and 11) and Supplementary Note 3. Fig. R11 has been included as Supplementary Fig. 15, and Fig. R12 has been included as Supplementary Fig. 11 to the revised Supplementary Information.\nComment 2-8: In the comparison between KAN and MLP, the parameter counts corresponding to the same network size (784-64-10) for KAN and MLP are not comparable (KAN has more parameters). The specific details of the network configurations are not presented to demonstrate the fairness of the comparison. To ensure a fair comparison, more details about the network structures and parameter settings should be provided.\nResponse 2-8: Thank you for your insightful comment. Our original intention was to ensure fairness in the comparison by aligning the network structures, meaning that KAN have the same number of layers and neurons as M-MLP. We also acknowledge that under this configuration, G-KAN have more parameters due to its architectural design.\nTo ensure a more comprehensive comparison, we conducted additional experiments that allowed us to evaluate G-KAN and M-MLP under an identical parameter budget. Specifically, we redesigned the network architectures as G-KAN [784, 100, 10] (n 4) and M-MLP [784, 500, 10], ensuring both models have the c same count of parameters. As shown in Fig. R4, G-KAN achieves classification accuracy comparable to that of M-MLP.\nHowever, we would like to emphasize that beyond pattern recognition tasks, G-KAN shows clear advantages over M-MLP in more scenarios, such as 1D function regression, partial differential equation (PDE) solving, and time-series forecasting. These tasks demand that the computing system generate continuous and accurate numerical outputs with a high dynamic range, such as floating-point (FP) numbers (Nat. Electron. 8, 276–287 (2025)), where G-KAN’s architectural design offers tangible benefits. In addition, the corresponding research content can be found in detail in response to Comment 2-10.\nIt is also worth noting that conventional computing hardware is not yet optimized for the KAN architecture. Therefore, the main contribution of our work lies in proposing a hardware-efficient implementation tailored specifically for KAN, which we believe will help unlock its full potential in future applications.\nFigure R4 | The learning performance of G-KAN ([784, 100, 10], n = 4 ) is c comparable to that of M-MLP [784, 500, 10] (equal training parameters) on image classification task. (Copied from response to Comment 1-2)\nComment 2-9: In the MNIST handwritten digit classification task, as shown in the training curves (Fig. 4c and 4e), it appears that neither the KAN nor the MLP training process has fully converged. Therefore, such results cannot rigorously demonstrate the performance differences between the two methods.\nResponse 2-9: Thanks for the suggestion. We have increased the training epochs in the MNIST handwritten digit classification task from 10 to 50. Under the same number of parameters in M-MLP as in G-KAN, the performance of the two models became comparable. We discussed it in detail in response to Comment 2-8. To further explore the advantageous applications of G-KANs, we compared the performance of G-KANs and M-MLPs in additional scenarios. Specifically, we successfully validated the advantages of G-KANs on PDE and time-series tasks. Detailed information can be found in the response to Comment 2-10.\nWe have added the discussion in response to Comment 2-8 and 2-9 to the revised main text (on page 12 and 13). Fig. R4 has been included as Fig. 4c in the revised main text.\nComment 2-10: The symbol regression and MNIST image classification tasks presented in the manuscript have shown the basic intelligence computing capacity for the GMC-based KAN. However, these tasks could also be well-handled by conventional MLP or CNN networks. To proof the advances of the proposed physical KAN, extra tests on more complex tasks e.g., CIFAR or ImageNet tasks will be appreciated.\nResponse 2-10: We thank the reviewer for the valuable suggestions. We evaluated both M-MLP and G-KAN on the CIFAR-10 dataset (Nat. Commun. 16, 702 (2025)) and found that neither model performed satisfactorily (Fig. R13a). This situation has already been demonstrated in previous literature as well (arXiv:2407.16674 (2024)), and this problem can be addressed by extending these foundational frameworks—for instance, by incorporating residual blocks to handle such complex image datasets (arXiv:2410.05500 (2024)). However, this lies beyond the scope of this work, and we plan to explore it more thoroughly in future studies. To better demonstrate the advancements of our proposed GMC-based KAN, we designed two more challenging computational tasks: partial differential equation (PDE) solving and time-series forecasting.\nOn the one hand, for the PDE task, we considered Poisson equation with zero Dirichlet boundary conditions data. For a space detailed as [1,1]2:\nu u  f in,\n xx yy (R3)\nu 0, on\nConsidering the data f(x,y)22sin(x)sin(y)for which the exact solution is u sin(x)sin(y) . Using the framework of physics-informed neural networks (PINNs) to solve this PDE, with the loss function given by:\nlossloss loss  1  n i u (z)u (z) f(z ) 2  1  n b u2 (R4)\ni b n xx i yy i i n\ni i1 b b1\nwhere lossᵢ is the interior loss, discretized and evaluated by a uniform sampling of n i points z (x,y ) inside the domain, and similarly loss is the boundary loss\nb\ni i i evaluated at n uniformly sampled points on the boundary. The parameter α balances\nb\nthe two loss components. We compared G-KAN with two different M-MLP architectures using the same hyperparameters (nᵢ = 51, n = 51, α = 0.01). As shown in\nb\nFig. R13b, G-KAN achieves a significantly lower L2 norm error while using a smaller network size and fewer parameters. Specifically, G-KAN attains an L2 norm error of 0.0121, which is much lower than that of M-MLP, which is 1.0121 and 0.2215, respectively.\nOn the other hand, for the time-series forecasting task, we used a chaotic system as benchmark test. It is inherently very challenging due to the positive Lyapunov exponent (Transp. Res. Rec. 1897, 9-17 (2004)), which leads to exponential growth of separation of close trajectories so that even small errors in prediction can quickly lead to divergence of the prediction from the ground truth. We tested the system using the Mackey-Glass time series (Nat. Electron. 2, 480-487 (2019); Science, 197, 287-289 (1977)):\ndx x(t)\n x(t) (R5)\ndt 1(x(t))n\nHerein, the parameters were set to β = 0.2, γ = 0.1, τ = 18, and n = 10, respectively. G-KAN and M-MLP were trained to predict the next time step based on the previous 20 time steps. Fig. R13c presents the results, G-KAN's predictions demonstrate strong agreement with the ground truth, with a root mean square error (RMSE) of 0.0691. In contrast, even with increased network depth and width, the RMSE of M-MLP consistently remained above 0.6, indicating its difficulty in accurately forecasting chaotic systems.\nFigure R13 | Performance evaluation on other typical complex tasks. a Performance comparison between G-KAN and M-MLP on the CIFAR-10 dataset. b PDE example: the squared L2 loss between the predicted solution and the ground truth. G-KAN achieves much lower error compared to M-MLP. c Time-series forecasting example: training (blue) and forecasting (pink) results of G-KAN and M-MLP.\nThis discussion has been added to the revised main text (page 13), and Supplementary Note 8. Fig. R13 has been included as Fig. 4 in revised main text, and Supplementary Fig. 18.\nResponse to Reviewer 3's comments\nGeneral comment: The manuscript proposes a Gaussian-like memory cell (GMC), consisting of a Gaussian transistor and a memristor, as the basis function for Kolmogorov-Arnold Networks (KAN), an emerging neural network algorithm. While exploring efficient hardware implementations of KAN is an important topic, this manuscript only scratches the surface, relying on pure simulation data and very limited experimental results from a single cell. Further analysis and more comprehensive studies are necessary for this manuscript to be considered for publication.\nResponse: We sincerely appreciate your insightful comments and constructive feedback on our manuscript. In response to your concerns regarding the limited experimental validation and simulation depth, we have expanded both the experimental and simulation components of this work. Specifically, we have conducted additional device-level measurements on multiple fabricated GMCs to evaluate performance consistency and reliability, performed comprehensive simulations to demonstrate the feasibility of the proposed GMC-based KAN architecture in real-world applications, and added stability and noise analysis to validate the robustness of the design under practical operating conditions. We believe these improvements will address your concerns and provide a more complete and rigorous evaluation of the proposed approach.\nComment 3-1: The core contribution of this work is the development of the GMC. However, the manuscript only provides minimal experimental data, such as the transfer curve of the memory cell in Fig. 2. Additional device characterization, such as endurance testing etc., is recommended to demonstrate the reliability and learning capability of the proposed memory cell. In other words, what are the full suite of device properties that are required to run the KAN algorithm?\nResponse 3-1: We are grateful to the reviewer for the insightful comment, which is crucial for us to elaborate on the electrical performance of the GMC and how to utilize GMCs to construct the core of KANs - the variable activation function.\nTo implement the KAN’s algorithm on hardware based on GMC, each cell must satisfy several key requirements, including realization of Gaussian-like curve, multistate storage capability, stable retention characteristics, and high endurance. The weighted linear superposition of Gaussian-like curves is critical to KAN's implementation as it can approximate any activation function. As shown in Fig. 2d in the original manuscript, the GMC can have satisfied Gaussian-like curves with tunable weighting coefficients. Furthermore, the retention characteristics and endurance are essential for KAN's hardware implementation to ensure hardware stability and reliability. In the revised manuscript, we have provided tests about the GMC’s retention in 100 seconds and endurance in 1000 cycles (Fig. R14). Through fitting and statistical analysis of the endurance test, we found that the coefficient of variation (Nat. Commun. 15(1), 129 (2024)) (C ) for the maximum current, μ, and σ of the GMC are all within V ± 0.075. To demonstrate GMCs’ feasibility in a whole integrated architecture, we have incorporated random noise testing in simulation, and the results shown that the performance of G-KAN remained stable without significant degradation within this C V range.\nMoreover, to intuitively demonstrate the learning ability of the GMC array, we fabricated a 1×2 device array to implement activation functions with continuously tunable characteristics. This array configuration serves as the minimal complete unit required for approximating arbitrary activation functions in G-KAN, providing the essential functional building blocks for constructing any nonlinear mapping. By applying 2, 4, and 6 pulses to each GMC, we modulated their weighted states, enabling precise control over the shape of the activation functions. The evolution of the output functions is illustrated in Fig. R15. The results verified the feasibility of approximating any activation function through the linear combination of multiple GMCs.\nFigure R14 | Endurance tests. a Results of the endurance test in 1000 cycles. Fitting statistics for endurance tests in 1000 cycles: b I , c σ , and d σ.\npeak + -\nFigure R15 | 1×2 GMC array achieving a learnable activation function. a A parallel circuit of two GMCs. b Curves of current versus gate input voltage for two parallel GMC units after applying 2, 4, and 6 pulses to individual GMCs (grey), and the constructed activation functions (colored).\nWe added this discussion to the revised main text (page 7). Fig. R14a has been included as Fig. 2f in the revised main text, and Fig. R14b-d have been included as Supplementary Fig. 6. Fig. R15 has been included as Supplementary Fig. 7. In addition, the original Fig. 2e has been relocated to Supplementary Fig. 4, while the newly added cycle-to-cycle characteristics have been presented in the revised Fig. 2.\nComment 3-2: The circuit design presented in Fig. 3 is more of a functional block representation than a detailed circuit implementation. To adequately demonstrate the circuit-level design, the manuscript should include explicit circuit diagrams for the key blocks rather than just describing their functions. More importantly, a circuit capable of running the KAN should be experimentally built and tested.\nResponse 3-2: Thank you for the suggestion, which is helpful in improving this work. In Fig. 3a-d of the manuscript, the circuit of the G-KAN was presented in a modular form. This type of illustration may obscure some of the more detailed designs. To provide a clearer illustration of the circuit details, a complete array design is presented in Fig. R18. The following content gives detailed explanation about the working principle of the circuit from input to output in sequence for the entire workflow.\nFirstly, the translation module provides Gaussian-like basis functions with evenly spaced center positions. The principle relies on translating the input signal to induce a corresponding translation in the function. Based on this mechanism, the sequence of translation terms can be derived through function construction and translation properties, as detailed below.\nGiven that the device transfer characteristic is described by the function\n(V )2\nf(V )exp( g ) , and assuming the target basis function is expressed as\ng 2\n(u)2\ng(u)exp( ) . Herein, k=L/4 (L is the grid size, and the value ‘4’\n(/k)2\noriginates from the transfer characteristic of the GMC), since the GMC intrinsically corresponds to a grid size of 4, ensuring that the width of each grid cell exactly matches the parameter . Therefore, equating f(V ) g(u) yields:\ng\nV ku(k1) (R6)\ng\nk2x2 k2(xx2)\nDefine h(x)exp( ). It is evident that h(xx)exp( ). Let\n2 2\ng(u)h(xx) , then the result follows that u  xx . Therefore,\nV k(xx). Since the translated centers of h(x) are evenly distributed across L\ng\npoints within the interval [-1,1], the set of x can be calculated as:\n2\nx{1,1,12,,12,1,1}( ) (R7)\nL1\nIn summary, the voltage sequence applied to the gates of different GMCs, according to the input signal (x), is given by that:\nV {k(x1),k(x1),,k(x1),k(x1)} (R8)\ng\nMoreover, in Fig. R16, each original input signal ( ) enters along the red path and is distributed equipotentially across parallel GMC columns. For the independent memristor column, the non-negative input signal, i.e., ReLU(x), is applied through a multiplexer (MUX). In addition, each one-transistor-one-resistive-memory (1T1R) unit contains a pair of amplification gains of -A and A, respectively. Herein,\nIGMC IGMC\nA max min , which serves as a normalization factor. The alternating\nImemristor Imemristor\nmax min\nplacement of gains is designed to match the polarity of the output lines in the GMC array.\nFor the signal routing, equipotential paths including VBL, VWL, VSL, INPUT, and GND, are employed with configurable interface switches to specify the desired connection combinations. For example, during the forward propagation, the potential on the VWL is set to V , supplying power through the drain of GMC. On the other hand,\nd\nduring backpropagation, the potentials coordinate with the selected cells and the write voltage pulses to determine the target cell locations and the polarity of the pulses (SET or RESET). In array techniques, signal routing can be configured utilizing field-programmable gate arrays (FPGAs) in conjunction with peripheral circuits (Nature 2020, 577(7792), 641-646).\nFigure R16 | The complete circuit design of a G-KAN.\nBased on the above design, a modular system comprising the translation module, b(x)-row module, and the GMC array was constructed on the Simulink platform (Fig. R17a). Additionally, Fig. R17b presents the oscilloscope image of the linear input signal (x) from -1 V to 1 V, while the output waveform of the array is shown in Fig. R17c.\nFigure R17 | Modular systematic architecture and testing results of the G-KAN (with a size of [1,1], and the n = 100) in Simulink. a Diagram of the architecture. b c\nOscilloscope image of the input signal x(t) from -1 to 1 (V). c Oscilloscope waveform of the output signal G-KAN(x(t)).\nWe added this discussion to the revised main text (page 8 and 9), and Supplementary Note 1. Fig. R16 and Fig. R17 have been included as Supplementary Fig. 8 and 10 in the revised Supplementary Information, respectively.\nComment 3-3: Are the results shown in Fig. 3e from experimental setups or pure simulations? If they are based on experimental setups, a photo of the memory cell array should be included to support the findings. The manuscript should provide clear details on the simulation setup and parameters if they are from simulations.\nResponse 3-3: Thank you for your attention to this information. The data in Fig. 3e was sourced from simulations, which we have validated both in Python and using the Simulink platform based on very high-speed hardware description language (VHDL). Notably, the simulations were entirely based on the polymorphic results obtained from the actual measurements of GMCs and CIPS memristors. There are the additional details regarding the execution of the simulations below.\nIn the 1D function regression task, since the grid size is expanded to 100 (i.e., expanded 25 times). Accordingly, in the translation module, k = 100/4 = 25 . Specifically, the training dataset consists of five segments of Gaussian peaks ( f (x)exp[300(xc)2](i1,2,3,4,5) , where the f (x) and c represent the i i i i function and the center of the i-th Gaussian peak), with each segment containing 1,000 data points. The G-KAN was trained for 1,000 iterations on the data from each segment of the Gaussian peaks using the L1 loss function and AdamW optimizer with a learning rate of 0.02 and weight decay of 0.0001. During this process, all learnable coefficients (c) were encoded by the differential pairs of GMCs, while the weights (w ) were b encoded by the differential pairs of CIPS memristors. Furthermore, in Simulink, the translation module receives a scanning signal ranging from -1 V to 1 V generated by a signal generator and distributes the processed signals to each row of GMC pairs. The device responses are accumulated along the differential columns and the output can be read out via an oscilloscope.\nComment 3-4: The claim regarding “continual learning resilience against catastrophic forgetting” in Fig. 3 appears to be an inherent benefit of the KAN rather than the GMC. To substantiate this claim, a comparative analysis should be conducted by evaluating the performance of the same KAN structure using the GMC versus other basis functions. Otherwise, this claim only reiterates the advantages of KAN without demonstrating the specific contributions of the GMC.\nResponse 3-4: Thank you for your valuable comments. Indeed, the catastrophic forgetting resistance is inherent advantage of KANs. However, our work main emphases are on how GMCs enable the hardware efficient implementation of KANs at the analog level, while simultaneously enabling parallel computing in memory (CIM). Moreover, we have included experimental comparisons between B-splines and GMC-based implementations in a 1D function regression task to evaluate their performance. Both scenarios were evaluated under identical conditions with the same loss function, optimizer, and hyperparameters. The performance of the G-KAN was almost identical to that under the B-spline functions (Fig. R18). It is worth noting that, at the physical level, GMCs can serve as basis functions that are more straightforward and hardware-friendly to implement on analog platforms. In contrast, B-splines rely on the recursive Cox-De Boor formulation, which requires considerable hardware resources for implementation (see Table R1). Moreover, G-KAN is specifically designed based on a CIM architecture, allowing KANs to operate efficiently in both the analog signal domain and memory-centric computation frameworks. Specifically, the comparison of time consumption between using GMCs or B-splines is illustrated in Fig. R7.\nFigure R18 | The performance comparison of KANs with different basis functions. a The performance of a KAN when using B-splines. b The performance of a G-KAN based on GMCs.\nFigure R7 | Statistics on the time consumption of basis functions based on GMCs or B-splines in KANs. (Copied from the response to Comment 2-1)\nTable R1 | Comparison of different ways to implement spline functions.\nAmp. Num. of Area Power\nRef. Mode function Memory\nadjustability devices (mm2) (μW)\nNakashima\ndigital B-Spline No No LUTs* (96) - -\net al.\nYu et al. digital B-Spline No No LUTs* (96) - -\nLozano\ndigital B-Spline No No - 9.111 266.735\nDuarte et al.\nLozano\nanalog B-Spline No No 42 0.073 238.5\nDuarte et al.\nThis work analog Gaussian Yes Yes 2 2.2×10-4 ~ 10-3\n* The transistor count estimation for each 4-input LUT (4-LUT) is based on the architecture of Xilinx Virtex-4 FPGAs, where each 4-LUT can be configured as a 16-bit distributed RAM. Assuming each SRAM bit cell comprises six transistors, the total transistor count per 4-LUT can be approximated by multiplying the number of SRAM cells (16) by six, resulting in approximately 96 transistors per LUT.\nWe added this discussion to the revised main text (page 10). Fig. R7 and Fig. R18 have been included together as Supplementary Fig. 13.\nComment 3-5: Similarly, beyond simply demonstrating that G-KAN can perform classification tasks like KAN, the manuscript should include studies on the trade-offs introduced using the GMC. Specifically, the impact of computing noise from the analog device on the performance of G-KAN should be evaluated, as well as its generalization capability to other tasks when using only a Gaussian-like function as the basis function.\nResponse 3-5: We appreciate the reviewer’s constructive comments. In practical applications, computational noise is inevitable due to external interference and non-ideal variability inherent in analog devices, which can affect hardware performance. Hence, we introduced perturbations at the output of the GMC to simulate the effects of external interference and device-level variability, with the aim of quantitatively assessing the influence of computational noise on the G-KAN performance. As computational noise from external interference generally follows a Gaussian distribution and can be compounded with device-level variability, the latter was used as a representative factor to account for both effects in our analysis. In detail, we measured the coefficients of variation (C ) of GMCs, as shown in Fig. R9 a-c. Based V on this measurement, the Gaussian-like functions generated by GMCs exhibited non-ideal states, as illustrated in Fig. R9d. After introducing computational noise, the G-KAN still exhibited relatively strong robustness and tolerance in the 1D function regression task. Note that C denotes the set of C V , i.e., {C amp , C σ- , C σ+ }, and q×C refers to scaling these C s to q times their original values. As shown in Fig. R10a, the RMSE gradually increases with the factor q from 1 to 50 on the 1D function regression task. Even under the noise levels increased up to 50 times the intrinsic case, the RMSE on this task remained below 0.4, demonstrating the robustness of the G-KAN architecture under severe variation conditions. The robustness of the G-KAN was also evaluated in pattern recognition tasks, addressing the same concern raised by Reviewer #2, as illustrated in Fig. R10b and c referenced earlier. The analysis shows that under noise conditions induced by C within 10C, the accuracy degradation of the G-KAN remains relatively minor.\nThe above supplementary experiments are provided to further support the effectiveness and advantages of G-KAN.\nFigure R9 | The output of GMC is not an ideal Gaussian-like curve. Fitting statistics for 1000-cycle endurance tests. a I , b   and c   . d Visualization of the Gaussian-peak     like functions generated by the GMC after incorporating analog noise. (Copied from the response to Comment 2-6)\nFigure R10 | Robustness evaluation of the G-KAN under device non-idealities and increasing architectural scalability. a 1D function regression performance under variable coefficients of variation. b Performance of G-KAN ([784, 64, 10], n = 4) on c the pattern recognition task (MNIST) with various C s of device inconsistency V introduced. c Learning curves recorded under the incorporation of GMCs’ non-idealities as scalability increases (on FMNIST dataset). (Copied from the response to Comment 2-6)\nThis discussion has been added to the revised main text (page 7 and 10). Fig. R9a-c has been included as Supplementary Fig. 6, and Fig. R9d has been included as Supplementary Fig. 14a. Fig. R10 has been included as Supplementary Fig. 14b-d.\nReviewer #1 (Remarks to the Author):\nI'm glad to see that authors have addressed all my concerns.\nResponse: We sincerely appreciate the reviewer’s positive feedback and pleased that we were able to address your concerns. We also truly appreciate the reviewer’s constructive comments and suggestions throughout the previous review process, which have been highly valuable in improving the clarity, rigor, and overall quality of our work.\nReviewer #2 (Remarks to the Author):\nThe revised manuscript provides more comprehensive details regarding the implementation of the proposed G-KAN and addresses several of my previous concerns. However, there are still some important issues that need to be addressed.\nResponse: We sincerely thank the reviewers for these constructive comments on our revised manuscript. We are delighted that the previous improvements have already received positive responses. Reviewer's comments have been valuable in helping us further clarify the key contributions of this work and strengthen its overall presentation. We carried out a more detailed revision process, carefully addressing each suggestion point by point. We conducted additional experiments to enhance the rigor of our work and ensure that the narrative can more clearly convey the significance of our findings. We hope these improvements further demonstrate the potential of the GMC-based KAN framework.\n1. While the response includes a comparison between G-KAN and M-MLP to demonstrate performance advantages, these benefits appear to stem largely from the inherent characteristics of the KAN architecture itself. The revised manuscript still provides limited discussion on the specific advantages of the GMC-based implementation. More thorough discussion and comparative visual evidence are required to underscore the contribution of the proposed GMC implementation.\nResponse 2-1: We sincerely appreciate the insightful comments provided by the reviewer, which have offered a valuable opportunity to further clarify and enhance the significance of our research. In the revised manuscript, we have included a comparative analysis of typical hardware implementation approaches to highlight the significant and adaptability advantages of GMCs in executing KAN-type networks.\nAs Gaussian kernels constitute the most underlying computational units in KANs, the key factor in determining whether KANs can be effectively hardware-implemented lies in how effectively the Gaussian kernels’ computation and training can be realized through devices or circuits. However, existing hardware architectures (von Neumann and near-memory architectures) face significant bottlenecks, both in implementing the Gaussian kernels and in training, which ultimately hinder the full potential of KANs. The proposed GMCs are specifically introduced to overcome the challenges that current devices and architectures cannot address (Fig. R1). To fully highlight the significance of GMC-based implementation for hardware KANs, the following section will present real-world cases to demonstrate why conventional hardware architectures are unsuitable for implementing KANs, thus contrasting the advantages of G-KANs.\n(1) Dilemmas of von Neumann architecture (corresponding to Dilemma 1-3 in Fig. R1b)\nIn the von Neumann architecture, the physical separation of the processor and memory requires continuous data and instruction transfer between them during execution. Since memory bandwidth is much lower than the processing throughput, processing cores often remain underutilized while waiting for data.1 Moreover, accessing memory incurs significant time and energy costs, with much of the energy spent on data transfer rather than computing (Dilemma 1 and 2).1,2 Additionally, the graphics processing unit (GPU) is a representative example of optimized computing design. GPUs have become prevalent for their remarkable acceleration in general matrix multiplication (GEMM)3. In neural network computations, GPUs can perform linear transformations with high computational density by exploiting highly regular operations and contiguous memory access4, while the central processing unit (CPU) only needs to initiate a single scheduling process, minimizing offloading overhead.5 However, these capabilities are not fully leveraged in KANs’ computation. Taking Gaussian kernels as the basis functions, the inference process involves sequential operations, which contain squaring ((xa)2), scaling multiplication ( (xa)2), nonlinear exponential transformation (exp()), weighted multiplication (c exp()), and accumulation ( ). These operations cannot be directly handled by GEMM, requiring frequent kernel launches per feedforward processing (each scheduled by the CPU), significantly increasing CPU-GPU offloading overhead (Dilemma 3). Worse yet, KAN’s complex computational components consume more hardware resources and power compared to MLPs, even with the same number of parameters.2,6\n(2) Dilemmas of near-memory implementations (corresponding to Dilemma 4-6 in Fig. R1b)\nThe evidence above confirms the incompatibility of KANs with the von Neumann architecture. Therefore, it is crucial to implement KANs on hardware platforms with higher computational and memory density. In this context, researchers have attempted to alleviate the dilemmas of von Neumann architecture through near-memory computing7. For KAN-related applications, typical examples include lookup table (LUT)8 and piecewise linear (PWL)9 circuit designs. Although LUT-based circuits can directly output Gaussian kernels at the hardware level, this strategy inevitably introduces significant computational complexity and storage address overhead. For instance, implementing a single Gaussian kernel requires 452 LUTs.8 When scaled to a network level, for highly densely integrated architectures like KANs, the resulting operational costs become unbearable (Dilemma 4).\nMoreover, a recent study have employed CMOS integration technology based on PWL to directly approximate the activation functions (connections) in KANs.9 However, this strategy has several inherent bottlenecks: first, the PWL function requires predefined breakpoint ( X ), slope ( M ) and intercept ( Y ) of each segment (X  X  X ), which must be stored in peripheral memories; second, the hardware architecture must integrate massive comparators (COMPs) and sensing circuits to determine which segment the input signal belongs to, then retrieve the corresponding slope and intercept from the buffers and pass these parameters to the MAC circuits to complete the linear operation (F(X)M *X Y ). Therefore, even for simple and few target operations, this approach still suffers from heavy hardware resource overhead (Dilemma 5).\nOverall evaluation of these two strategies reveals that they not only require significant hardware resources such as multipliers (MPLs), adders (ADDs), and COMPs to execute Gaussian kernel computations, but also, due to their hardwired electrical architecture, are physically incapable of implementing parameter update functionality (Dilemma 6). Therefore, although both aim to alleviate the von Neumann bottleneck, LUT-based and PWL-based implementations ultimately suffer from a fundamental flaw due to their inability to endow the neural network with trainable characteristics.\nIn the context given above, the limitations of existing CMOS-based implementations have led to the exploration of dedicated KAN-type computing-in-memory (CIM) architectures. Clearly, memristors alone cannot achieve in-memory computation for nonlinear functions such as Gaussian kernels. The following content will specifically elaborate on how the GMCs and the array design proposed in this work effectively address the aforementioned challenges.\n(3) Solutions relying on GMC-based implementation (corresponding to the Solution 1-5 in Fig. R1b).\nThe transfer characteristics of GMCs can directly generate stable and parameterized Gaussian kernels, naturally representing the mathematical behavior of Gaussian kernels in the analog domain. In addition, by adjusting the conductance of memristors through write voltages, the peak height of the Gaussian kernel can be flexibly controlled, enabling electrical programming of the learnable coefficients. At the architectural level, the one-transistor-one-memristor structure of GMCs facilitates easy integration into crossbar arrays.10 According to the KCL, the output currents of all GMCs in the same column can be physically accumulated on the source line, directly performing the linear combination of Gaussian kernels in a KAN. Therefore, the GMC-based implementation can complete the full computation from input to output within the analog domain (Solution 1).\nFurthermore, the Dilemma 2 in conventional CMOS-based implementations arises from the physical separation between processor and memory.1 The GMC-based implementation fundamentally reshapes this paradigm through the CIM approach. The core mechanism lies in synchronizing computation and data storage at the same physical location, thus completely avoiding the frequent data transfers between memory and processing units. As a result, the conflict between memory bandwidth and processing throughput is eliminated, with energy consumption focused on computation (Solution 2). Meanwhile, the in-situ CIM working mode also entirely avoids the offloading overhead inherent in von Neumann architecture (Solution 3).\nTo address the hardware catastrophe scaling problem (Dilemma 4) faced by CMOS-based implementations—an inherent bottleneck where the growth in the number of basis functions triggers a nonlinear explosion in hardware resource consumption—the GMCs proposed in this study offers a fundamental solution through a linear hardware scaling paradigm. Specifically, under the differential-pair encoding rule, each Gaussian kernel requires only a fixed pair of GMCs. This ensures that the hardware scale expands strictly linearly with the number of Gaussian kernels, which is equivalent to the network scale of a KAN. As a result, this approach fundamentally prevents uncontrollable resource consumption at the hardware level, ensuring that the hardware scale of a G-KAN remains predictable and manageable throughout (Solution 4).\nOf equal significance, the GMC-based paradigm circumvents the complex and segmented operations that characterize near-memory computing implementations (Dilemma 5 and 6). Within the GMC arrays, an input vector is loaded in parallel across all rows, enabling each cell to perform in-situ Gaussian-like mapping and MAC operations simultaneously. By leveraging the native physics of the crossbar array and KCL, the complete matrix transformation is executed in one step, thereby obviating the need for piecewise function evaluation, parameter retrieval from memory, and data shuttling. This one-shot process fundamentally eliminates the timing and control overhead associated with multi-step operations in CMOS-based implementations, achieving a drastic reduction in computational complexity (Solution 5).\nThe primary dilemmas confronting the aforementioned CMOS-based implementations and their corresponding solutions enabled by the GMC-based implementations are graphically summarized in Fig. R1. Furthermore, a detailed comparison of the key attributes discussed for the reference objects is provided in Table R1.\nFig. R1 | Overview of KAN’s hardware implementation strategies. a Reference object and benchmark metrics for the hardware implementation of KAN. b The bottlenecks encountered by the von Neumann and near-memory architectures in processing the computations of KAN, while the GMC-based implementation provides a reliable solution at the in-memory computing level. c The GMC ingeniously combines the Gaussian kernel provided by AAT with the parameterization capability of memristors, integrating the necessary physical foundation for the in-memory computing required by KAN.\nFurthermore, in order to more systematically highlight the advantages of GMC in implementing KAN and the basis functions (i.e., Gaussian kernels) for each activation connection, we compare different implementation paths with their reference objects and benchmark metrics. Table R1 present a complete summary across several comparative dimensions as below.\nTable R1 Comparison for implementing KAN across different benchmarks.\nReference objects/ Von Neumann Near-Memory GMC-based\nbenchmarks Architecture Architecture Crossbar Array\n1. hardware 1. memory-bound; physically\ndependance: 2. Separation of in-device\nDSPs/GPUs/FFs/ parameterization generation\nRAMs/LUTs6,11-13; and kernel\n2. Muti-step computation;\npointwise operators 3. Non-adjustable\n(squaring→ functions\nParameterized multiplication→ (hardwired);\nGaussian kernel exp()→ 4. Reliance on a\nimplementation multiplication); large number of\n3. memory- computational\nbound;14,15 modules8,9\n4. frequent\nmemory\naccessing16\n☹ ☹  \nif one-shot? No No Yes\nComputing in NOT partial complete\nmemory\n☹ ☹  \nif one-shot? No No Yes\n1. Data loading and (LUT-based)8 analog MAC\nscheduling ADC→multi-bit implemented on\ninitialization (CPU input (address)→ the crossbar array\nside); multi-bit output→\n↓ DAC;\n2. Multi-step chain (PWL-based)9\nPipeline of pointwise binary encoding→\noperators; breakpoint detection\n↓ →accessing\n3. Weighted slope/intercept\naccumulation; memory\n↓ →parameter\n4. Memory copy fetching→digital\nMAC→DAC\n☹ ☹  \nif one-shot? No No Yes\n(partially parallel (partially parallel)9 (completely\non GPUs) 1. memory-bound; parallel)\n1. memory- 2. massive 1. access-free\nbound;17 computational memory;\n2. high overhead of modules; 2. offloading-\ndata movement;18 3. intricated control free;\n3. significant CPU- flow (PWL-based 3. one-shot\nComputational GPU offloading scene); parallel VMM\nparallelism latency and energy 4. redundancy in and MAC\nconsumption;19 address (LUT-based process;\n4. high overhead of scene) or parameter 4. simple control\nscheduling and (PWL-based scene) mechanism\nsynchronization20,21 access (voltage-pulse\ndirect drive)\n☹ ☹  \n1. memory and 1. memory and 1. device count\ncomputation computation demand increases\ndemand grows demand grows linearly with\nsuperlinearly with superlinearly with computational\nthe number of the number of scale (one basis\nparameters; parameters function is\n2. exponentially implemented by a\nincreasing memory pair of GMCs)\nHardware copy latency;*\noverhead change 3. memory\nbandwidth\nbottleneck\namplifies with\nincreasing\ncomputational\nscale22\n☹ ☹  \nIn-situ training -- NO (hardwired) YES\n☹  \n* https://developer.nvidia.com/gdrcopy\nWe have included the response in Supplementary Note 1 of the latest revision of the manuscript. Additionally, Fig. R1 is presented as Fig. 2 in the latest main text, while Table R1 is shown as Supplementary Table 1 in the latest Supplementary Information.\n2. The experiment involving two GMC units in the revised manuscript only demonstrates the functional feasibility. However, it does not analyze the potential errors or scalability issues that may arise when integrating multiple units. As such, it is insufficient to convincingly support the practical feasibility and scalability of a full GMC array. Further experimental results and in-depth analysis are necessary to substantiate this claim.\nResponse 2-2: We appreciate the reviewer’s insightful comment regarding the practical feasibility and scalability of the multiple GMC integrations. We acknowledge that our experiment mainly demonstrates functional feasibility, while a deeper analysis of the potential errors or scalability issues arising when integrating a larger number of units has not yet been fully addressed. Considering that array-level performance ultimately determines whether such devices can support large-scale CIM architectures in real-world applications, a quantitative evaluation of integration scalability is indeed essential.\nAs shown in Fig. R2a, given the intrinsic self-rectifying characteristics of the GMC devices, we employ the read margin as the key metric to characterize the scalability of the GMC array23. The read margin reflects the ability of a memory array to accurately retrieve stored information under realistic conditions, including noise and sneak path currents. Therefore, it is a widely accepted and fundamental indicator for evaluating the scalability of self-rectifying memristive crossbar arrays.23 Additionally the read voltage scheme during array operation has a significant impact on the sneak path current. The V /2 bias scheme is employed for current readout in this analysis (V 1.7V).\nread read\nUnder this scheme, only the fully selected GMCs (with a read voltage of V , as read indicated by pink dots in Fig. R2a) will have current, while the partially selected (with a read voltage of V /2, as indicated by green dots in Fig. R2a) and unselected GMCs read (with a read voltage of 0, as indicated by blue dots in Fig. R2a) will have no current, effectively suppressing sneak-path currents.\nNotably, the read margin typically decreases with integrated array size, and a margin below 10% is generally considered the practical scalability limit.24 Experimentally, we evaluate the read margin using a single bit-line pull-up strategy, which is defined by the following relationships:25\nV  1 1 \nRead Margin   R    (R1)\nV pu R R R R \npu  1 pu 2 pu \n 2R R\nR  pos  neg\n\nsneak n1 n12\n\n\n  R \nR  R  sneak  (R2)\n  LRS sneak \n\n R \nR  R  sneak \n 2 HRS R R\n  HRS sneak \nHerein, V refers to the difference between the input voltages of the selected cell at low-resistance state (LRS) and high-resistance state (HRS). V denotes the pull-up pu voltage applied to the selected BL, which is represented by V in this experiment. read R is the pull-up resistance, and R is the resistance along the sneak paths. In pu sneak addition, R and R refer to the resistance of a cell that is half selected in this pos neg experiment as well as a cell that is not selected at all, respectively. n represents the number of SLs or BLs in a whole crossbar array. As illustrated in Fig. R2b, with read margin as the sole parameter for evaluating the scalability of the proposed GMC array, the array in this work can be scaled up to approximately 59×59 (3.48 Kb) operated at a read voltage of 1.7 V. This indicates that the GMC units proposed in this work can reliably perform read operations, demonstrating feasibility at the array level.\nFurthermore, the scalability of the GMC array could be further improved by increasing the self-rectifying ratio, for example, by increasing the read voltage or replacing other self-rectifying memristors with higher rectification ratios.23,24 It should be noted that the main goal of this work is to propose a potential hardware implementation of KAN, and future efforts will focus on further advancing the practical realization of hardware KAN.\nFig. R2 | Analysis of the array scalability. a Self-rectifying I-V characteristics of GMCs. b Scalability analysis based on the proposed GMCs with over 3.48 kb scale.\nWe have included the response in the latest Supplementary Note 3 and referenced it in the ‘Circuit design for GMC-based implementation of KANs’ section of the ‘Results’ in the latest main text. Correspondingly, Fig. R2 is presented as Supplementary Fig. 8.\n3. The response includes an error modeling of device variability and analyzes its impact on task performance. However, it remains unclear whether the modeling aligns with actual physical behavior. To justify the validity of this approach, experimental validation using measured device variability is necessary.\nResponse 2-3: We are grateful for the reviewer’s comment on the consistency between the previously adopted error modeling and the actual physical behavior of the GMCs, which is crucial for ensuring the reliability of the proposed physical G-KAN. The primary sources of errors in GMC units arise from device-to-device (D2D) variations (Fig. R3a) and cycle-to-cycle (C2C) variations within the same device (Fig. R3b). D2D variations are mainly caused by fluctuations in material defect density and channel area due to fabrication limitations26,27, whereas C2C variations result from external random perturbations. Both types of errors manifest as non-idealities and inconsistencies in the quasi-Gaussian output of the GMC units.\nTo investigate the causes and nature of the random perturbations in the Gaussian-like transfer characteristic curve, a statistical analysis is required. Given that the Gaussian-like function is described by characteristic parameters such as the peak value,  and  , error analysis can be conducted on the perturbations introduced in these   parameters. Mathematically, these parameters can be defined as a class of variables that satisfy the following equation:\nP*  P(1KZ) (R3)\nwhere the P* denotes the experimentally measured value, Z is a random variable following a standard normal distribution (i.e., Z ~ N (0,1)), and K is defined as the characteristic perturbation constant.28 As an illustration, Fig. R3c shows the effect when K 0.1.\nBased on the above premise, to validate that the utilization of the coefficient of variation (CV) to quantify the parameter perturbation behavior is reasonable, it is sufficient to demonstrate that the CV is a variable explicitly related to the coefficient K in Eq. (R3). Through rigorous mathematical derivation, we have proved that the previously adopted error modeling based on the coefficient of variation (CV) is in fact equivalent to the above perturbation model. The detailed proof process is presented as follows.\nLet P be the intrinsic value of a certain characteristic parameter, and let P i ( i1,2,3, ) denote the measured value (random variable) of P at the i-th measurement. According to the perturbation model:\nP  P(1KZ)，Z ~ N (0,1) (R4)\ni\nDenote by E(P) and Var(P) the exception and variance of P, respectively. By exploiting the properties of the normal distribution, the following derivation is obtained:\nE(P) E(P)KE(Z) P (R5)\ni\nVar(P) P2Var(1KZ) P2\n\nE1KZ2E1KZ\n2\n(R6)\ni    \nSince\nE1KZ2  E  12KZ K2Z2 1K2E  Z2 1K2\n\nVar(Z)EZ\n2\n1K2\n   \n, and E1KZ1. Equation (R6) follows that,\nVarP K2P2 (R7)\ni\nFor the GMCs prepared in this work, P 0. Therefore,\nVarP\ni  K，(K 0) (R8)\nE(P)\ni\nAccording to the definition of the CV—the ratio of the standard deviation to the exception—the constant K is equivalent to CV. In summary, the previous error modeling based on CV is equivalent to the characterization perturbation model of GMCs. In combination with the laws of large numbers29, the intrinsic value\n1 n\nPE(P) P . Hence, this equivalence establishes a direct theoretical link i n i\ni1\nbetween the error modeling framework and the statistical description of experimentally observed device variability. It is worth noting that, in the previously revised manuscript, to ensure the rationality of the perturbation simulation, each device model in a G-KAN was independently assigned its own characterization perturbation random variables, and the outcome was obtained through forward propagation at the network level, thereby reflecting the cumulative effect of the perturbations.\nFig. R3 | Device variability. a The transfer characteristic curves with 8 different GMCs. b Test of the transfer characteristic curve for 1000 cycles of the same GMC unit, among which the wine red color represents the output of the 500th cycle. c Random perturbations considered on the modeled GMC curve to emulate the impact of device variability.\nWe have included the data in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text. Correspondingly, Fig. R3 is presented as Supplementary Fig. 5 and Supplementary Fig. 6.\n4. The revised manuscript states that the RMSE of G-KAN remains below 0.4 when the factor $q$ reaches 50. However, it is not evident what level of physical error this corresponds to in practice. Is such a quantization level sufficient in a real-world hardware scenario? A more detailed explanation is needed to substantiate the robustness of G-KAN under practical conditions.\nResponse 2-4: We sincerely thank the reviewer for raising this important comment regarding the physical significance of the factor q and correspondence to the error statistics in practical hardware scenarios.\nIn the previous version of the revised manuscript, q was introduced as a hypothetical scaling factor to magnify the intrinsic variability of the device by q -fold. This setting was applied to emulate the situation in which the intrinsic device variability is further amplified when the array operates under the influence of external noise sources. Specifically, the expression ‘ qC ’ refers to multiplying the CV of each characterization parameter. To avoid ambiguity, in the latest revised manuscript, we have clarified this description as “multiplying each intrinsic perturbation constant by q ”, which more clearly conveys the experimental details.\nRegarding whether a q -fold perturbation level is sufficient for real-world hardware, we refer to the study by Li et al30. In practice, in addition to the intrinsic device variability, array-level operation also suffers from perturbations introduced by peripheral circuits, such as sensing drift in the transimpedance amplifier (TIA).30 The standard deviation of such drift has been reported to be approximately 0.3, which is still far below the case of 50-fold intrinsic variability (corresponding to\nP* ~ N (P,2500(KP)2)). Notably, when q 50, the RMSE approximately reaches as high as 0.4. Although this represents a considerable error level for a 1D function regression task, it should be emphasized that such performance arises under extremely amplified perturbations—50 times the intrinsic device variation. The motivation for presenting this stress-test scenario was to benchmark against a M-MLP model with 15,250 weights (i.e., 152.5× larger than G-KAN with n 100). However, this M- c MLP exhibited an RMSE as high as 1.311 even under ideal conditions. Hence, such extreme test was previously adopted to demonstrate that G-KAN could achieve much lower error than M-MLP under ideal conditions, even when subjected to such an extremely adverse testing premise. In realistic settings, GMC arrays operate under normal device-to-device interactions, where the perturbation factor q is expected to be close to 1. Even when q2 —already far beyond the typical operational conditions—the RMSE increases only by 0.0168, demonstrating that the system maintains strong robustness under practical circumstances.\nFollowing the reasoning of Li et al.30, if the network maintains robust performance (measured by AI benchmark metrics) even under artificially magnified error conditions (e.g., q2 , which significantly exceeds the expected real-world variability), this strongly substantiates the reliability of the G-KAN in practical operation. Moreover, the underlying mechanism of neural network for classification is probabilistic decision-making, where the label with the highest probability is selected as the output.31 Under this principle, even if the predicted probabilities are affected by internal errors, the final classification outcome does not vary continuously as RMSE does in regression tasks, but instead exhibits a certain degree of tolerance. Consequently, classification accuracy is less sensitive to perturbations. As shown in Fig. R4, even when q5, the accuracy decreases by only 0.453%. Therefore, G-KAN demonstrates strong robustness in both regression and classification tasks.\nFig. R4 | Robustness evaluation of G-KAN. The left panel presents the evaluation on the function regression task, while the right panel shows the evaluation on the image classification task.\nWe have included the response in latest Supplementary Note 7 and 9 and referenced it in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text. Correspondingly, Fig. R4 is presented as Fig. 5g in the latest main text.\n5. The response mentions methods that allow the weighted coefficients of cells to be dynamically adjusted during training to compensate for effects such as current drift caused by device variations. However, these methods are designed primarily for conventional CNN or MLP architectures, which are fundamentally different from the proposed G-KAN. Whether such techniques are applicable to G-KAN requires further clarification.\nResponse 2-5: We sincerely appreciate the reviewer’s insightful comments and acknowledge that a more in-depth discussion of this concern will help confirm the feasibility of the method within the architecture proposed in this work. Specifically, the method refers to in-situ training in neuromorphic computing architectures.30,32\nTherefore, we first clarify the working mechanism of in-situ training in well-established systems such as MLPs and CNNs, as well as the details of how this method overcome device non-idealities. On this basis, we then analyze whether in-situ training remains feasible for G-KAN by considering the electrical write/erase mechanism of GMCs.\nIn-situ training is widely applied in various neuromorphic architectures that utilize memristors to store trainable parameters and operate on crossbar arrays. Examples include spiking neural networks (SNNs)33, reservoir computing34-36, long short-term memory (LSTM) networks37,38, and even hardware implementations of fast Fourier transforms (FFT)39 and discrete Fourier transforms (DFT)40. In these architectures, the trainable parameters are fundamentally stored in the conductance states of memristors, and the training process is accomplished by modulating these conductance values.41\nUpon analyzing the GMC structure, which is composed of an anti-ambipolar transistor (AAT)42 in series with a memristor, the AAT solely provides the Gaussian-like transfer characteristics, while the memristor stores and modulate the trainable parameter of the Gaussian kernel. Similar to purely memristor-based networks, the in-situ training of G-KAN is also achieved by applying programming pulse sequences to adjust the memristor conductance. Moreover, the GMC is physically compatible with the crossbar array. Therefore, as a hardware-level optimization mechanism, in-situ training does not depend on specific network architectures, and the KAN-type networks constructed with GMCs also inherently inherit the capability of in-situ training to overcome hardware non-idealities.\nSecondly, regarding the role of in-situ training in overcoming current drift, further clarification is necessary. In fact, in-situ training not only effectively addresses current drift but also adaptively compensates for other various hardware non-idealities. Non-ideal factors such as current drift, write nonlinearity, device-to-device variation, wire resistance, and asymmetries in peripheral circuits typically affect the weight programming process.32 Moreover, in-situ training directly performs computation at the location where the neural network parameters are stored. This allows in-situ training to capture and compensate for these unavoidable device defects in real-time.30\nSpecifically, in-situ training with backpropagation can adaptively adjust network parameters to minimize the impact of unavoidable hardware non-idealities without the need for any hardware prior knowledge. Therefore, in-situ training has the capability to automatically adjust weights and compensate for hardware defects.30 In deeper networks, the adaptive ability of in-situ training is particularly pronounced because the hidden neurons can minimize the impact of hardware defects on network performance.30 Experimental results from Li et al. have shown that in-situ training can effectively tolerate defects in other hardware components (e.g., transistors, peripheral circuits, and current sensing drift), further validating its robustness.30 Especially in large-scale arrays, where some devices may fail to respond due to manufacturing or usage defects, in-situ training can continue to update the effective units without significantly affecting the overall performance of the network. Even with 11% of devices being stuck and unresponsive, in-situ training maintains high performance, demonstrating its adaptive ability in the presence of hardware defects.30 In summary, in-situ training is not merely a solution to current drift specific to MLPs and CNNs, but rather a device- and circuit-level strategy which is broadly feasible to the hardware compatible with crossbar array integration. This method enables neuromorphic circuits to effectively overcome various hardware non-idealities, thereby enhancing the performance and robustness of neural networks in actual hardware environments.\nWe have already included the explanations regarding the error analysis in Supplementary Note 9 and referenced this content in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text.\nReviewer #3 (Remarks to the Author):\nThe authors have conducted additional experiments and simulations that partially address my initial concerns regarding device measurements. However, the circuit designs presented in this manuscript remain underdeveloped and are insufficient to support even a design-level demonstration of computing-in-memory (CIM) for Kolmogorov–Arnold Networks (KAN), let alone an implementation of CIM-based KAN. Several significant concerns remain, even after the revisions, and the manuscript does not meet the standards required for publication in Nature Communications.\nResponse: We sincerely appreciate the reviewer for providing valuable feedback on the shortcomings in the circuit design and result presentation in the previous manuscript. The original manuscript indeed oversimplified some of the schematic details, which compromised the technical rigor. In response, we have invited a professor with extensive expertise in memristor chip design and fabrication to join the discussion. Through in-depth collaboration and multiple rounds of revisions, we have comprehensively and carefully improved the manuscript to effectively address the issues raised in the reviewer’s comments. In detail, (1) we recognized that the initial circuit illustrations were adopted from overly simplified representations in several prior works10,43-45 and therefore lacked sufficient components; (2) we have now reconstructed the circuit schematics by referring to detailed circuit presentations in established neuromorphic computing literatures,10,30,46,47 and re-implemented the presentations on a professional electronic simulation platform to ensure accuracy and credibility; and (3) we decomposed the previously identified design limitations into distinct sub-problems and proposed targeted solutions for each. Collectively, these efforts elevate professional circuit design which is adequate to support a computing-in-memory (CIM) demonstration for KANs.\n1. The circuit designs presented in this manuscript are difficult to understand and appear unrealistic, which significantly undermines the authors’ claim of implementing KAN using a CIM approach. The poor quality of the circuit design raises serious concerns about the credibility of the simulation results. Below are several fundamental questions that support this assessment:\nResponse 3-1:\n1) What do the triangle symbols represent in inputs and outputs of Fig. 3a? What are their functions?\nWe appreciate the reviewer’s attention to Fig. 3a. The triangle symbols were originally used as a simplified representation of differential operational amplifier stages, omitting the power supply pins and feedback paths. This simplification, which follows the convention adopted in some reports about memristive neural network, was intended to maintain clarity within the limited schematic space.10,45,48\nHowever, we acknowledge that such a representation may be easily confused with the comparator symbol commonly used in analog electronics. In response to the reviewer’s comment, we have revised the figure to align with the standard depiction of output stages in memristive crossbar arrays. Specifically, the column currents from the array are first converted into voltage signals via a transimpedance amplifier (TIA), which enables subsequent operations (Fig. R5). Since the non-inverting terminal is grounded, the virtual short property of the negative-feedback operational amplifier ensures that the potential of the entire SL column is maintained at zero.10 Then, the amplified differential signals can then be fed into a dedicated differential amplifier stage or a specialized processor for further processing. The specifics of these peripheral circuits are provided in the figure captions for clarity, as the ensuing discussion will focus on the core GMC array architecture.\nFig. R5 | Transimpedance amplifier (TIA).\n2) What are the triangle symbols in Fig. 3b? Are they the same components as those in Fig. 3a?\nIn the Fig. 3b of original manuscript, the triangular symbols serve the same purpose as in the reviewer’s Question (1) – to simplify the representation in the block diagram. These symbols indicate differential operation, where “+” and “-” denote the non-inverting and inverting input terminals, respectively. To address the previous non-standard depiction, we have revised the figure and adopted the widely utilized TIA as the essential element at the MAC current output stage.\nWe sincerely apologize for the insufficient explanations and non-standard notations in our original submission, which may have caused confusion. Thank you again for pointing out these issues, which have helped us significantly improve the rigor and readability of the manuscript.\n3) Fig. 1c shows that a GMC consists of a Gaussian transistor and a memristor. However, in Fig. 3b, memristors appear as independent devices when forming differential pairs. How is this structural change justified? What are the characteristics of these independent memristor differential pairs?\nIn the Fig. 3b of original manuscript, the standalone memristors (highlighted in gray) correspond to the synaptic weights of the residual connections in the KAN. These connections serve as additional pathways in the network structure, enabling the direct transmission of input information (Fig. R6).49 In hardware implementation, these connections adopt exactly the same differential-pair encoding format for weights as conventional memristors. Through this design, the network can achieve more stable training and enhanced representational capability.49\nFig. R6 | Information transfer between nodes—residual connection (b(x)) can be added on the basis function combination (c f (x)).\ni i\ni\nThis response is presented in Supplementary Note 4 and referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the main text. Correspondingly, Fig. R6 is combined and presented as Supplementary Fig. 12.\n4) In Fig. 3c, what are the triangles with one terminal connected to x? Where are the other terminals connected?\nThe triangle symbols used here represent a simplified version of the differential circuit as well, which was originally intended to achieve a horizontal translation of the function. In the previously revised manuscript, the other terminals were connected to external bias sources used to implement function translation, as illustrated in Fig. R7. Since a horizontal translation of the function is equivalent to a biasing of the independent variable (x), we utilized this translation property in differential form to achieve the effect shown in Fig. R8. Specifically, the transfer characteristics of the GMC are mapped to a laterally translated Gaussian-like function (Fig. R8a), which requires establishing a bias relationship between the input (x) and the gate voltage (v ).\ng\nIn scenarios requiring higher fitting precision, such as the approximation of complex one-dimensional continuous functions, it is further necessary to contract the basis functions to form a finer grid (Fig. R8b). However, function contraction can be achieved simply by introducing a gain factor of k to the independent variable. In general, all these operations rely on addition/subtraction and subsequent amplification of x, which can be processed via operational circuits. Therefore, in the previously presented triangular symbols, the port other than the one connected to x represents the bias term. The other input of the triangle symbol corresponds to the applied bias term.\nIn the original manuscript, the bias terms were not explicitly labeled in the block diagram to avoid overcrowding the figure. Following the reviewer’s suggestion, we recognize that the original design may be confusing and lacks hardware-friendliness. As a result, we have re-evaluated and modified the configuration of the input terminals. Specifically, as shown in Fig. R8c, the contraction and translation of the Gaussian-like function essentially result from a fixed computational mode of linear encoding applied to the input variable. This operation can be realized simply by generating the gate voltages fed into the GMC array according to v k(xa)V , which is inherently a g  peripheral process. Consequently, we eliminated the translation module in the original design, which unnecessarily increases hardware complexity, thereby optimizing the circuit design. The reconstructed figure can be found in Fig. R11.\nFig. R7 | Schematic illustration of the computational scheme for handling translation and scaling operations with external bias.\nFig. R8 | Function translation and device mapping. a Function translation induced by variable bias. b Function contraction induced by gain on the independent variable for finer-grid adaption. c The input signal (x) is embedded in the voltage applied to the gate electrode, and the mapped functional relationship is established through the output\n  xa 2\ncharacteristics of the GMC: f(x)exp\n \n.\n    \nThis response is mentioned in the latest Supplementary Note 2 and referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text. Correspondingly, Fig. R8 is presented as Supplementary Fig. 10 in the latest Supplementary Information.\n5) In Supplementary Fig. 8, what is the 1T1R architecture, and is it the same as a GMC cell? The diagram includes numerous switches, what are their specific functions? Moreover, what is the difference between these switches and the MUXes, given that they are typically considered equivalent in circuit design?\nIn the Supplementary Fig. 8 of original manuscript, the specifically highlighted 1T1R structure represents the memristor differential pairs used for implementing the residual connection, distinguishing this design from the GMC configuration. In detail, in typical hardware implementations, a memristor-based crossbar array requires additional transistors to select specific rows or columns.10 This is because, in the absence of transistors, unintended operations may occur on unselected units within the two-dimensional arrays. Through the switching control of transistors, the 1T1R structure effectively prevents crosstalk between multiple memristor units, especially half-select interference. This is the main challenge in achieving high-precision tuning in passive integrated circuits.45\nIn addition, the multiple switches shown in Supplementary Fig. 8 of the original manuscript function similarly to MUXes. This representation is referred to previously reported studies.50 Specifically, these switches are utilized to select and connect different signal lines (VWL/VBL/VSL/GND) in various modes to alter the potential difference across the selected unit. For example, during feedforward progress, SLs are connected to GND, providing a zero-potential reference point. During backpropagation, if the selected unit requires a negative voltage, thence BLs are connected to GND while SLs are connected to VSL. The switching of WLs between VWL and GND are used to select the row and column of the target unit. Additionally, the MUXes shown in original Supplementary Fig. 8 are used to implement the ReLU activation function. In the original Simulink module, these MUXes were implemented using the ‘Switch’ blocks (Fig. R9).\nWe sincerely apologize that, in the original design, directly paralleling the memristor component connected through the operational amplifier with other GMCs is inappropriate. This is because that, the operational amplifier forces the output potential V to R i (where R is the feedback resistor and i is the current flowing out F F through the memristor), which contradicts the condition that the operational amplifier at the array’s total output enforces the SL column potential to be zero through the virtual short principle. Therefore, we correct the schematic, and the updated version is shown in Fig. R10. Specifically, since the memristor array and the GMC array adopt different electrical encoding schemes, they need to be allocated into two independent arrays. The corresponding output vectors from each array can then be summed to compute the residual-connected form of G-KAN, as illustrated in Fig. R10 and Fig. R11.\nFig. R9 | The ‘Switch’ block utilized in Simulink module to implement the ReLU function. When the ‘Input Signal’ is greater than zero, the block directly outputs the input; otherwise, this block outputs a ground signal (zero potential).\nFig. R10 | Hardware implementation of the G-KAN. a, d Topology of KAN. Unlike MLPs, each edge is not merely a simple synapse but can be expanded into an activation function represented by a combination of Gaussian-like basis functions (Gaussian-like kernels), as illustrated in d. b GMCs serve as the fundamental electrical units for implementing tunable Gaussian-like basis functions, and are compatible with crossbar array architectures to realize analog in-memory VMM and MAC operations. c Schematic of G-KAN. e Demonstration of function-level parallelism in a G-KAN during inference operations (m input nodes, p output nodes, with n basis functions between input-output node pair). f Basic performance evaluation of the G-KAN (with 100 basis functions), using a 1D function regression task as a representative example.\nFig. R11 | Schematic diagram of the extended G-KAN architecture with residual connections. a GMC array part. Each green block represents the combination of n c Gaussian-like basis functions expanded from an input variable (x ). b A 1T1R-standard integrated memristor array is employed to process the additional operations of the residual-connection part. c The GMC array and the b(x) array are directly superimposed element-wise along the output vector to generate the final output.\nIn the schematics above, the ‘Subtractor Configuration’ contains the peripheral circuits utilized to handle the differential operation of the output voltages, which can be implemented using an operational amplifier (op-amp) (Fig. R12). Specifically, two TIAs as a differential pair convert the current representing the MAC operation result on the SL column into voltage, and then perform the differential calculation through an op-amp. The electrical principles in Fig. R12 can be found in following description.\nFor the non-inverting terminal, according to the op-amp’s virtual open and KCL, the result follows that:\nV V V 0 V\n2    V  2 (R9)\nR R  R\n1 2 1 1\nR\nR\nV  1V\nV V V V 1 R o\n1    o V  2 (R10)\nR R  R\n1 2 1 1\nR\noperation: V  R 2V V .\no R 2 1\nThe response is presented in Supplementary Note 2 of the latest revised manuscript and is referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the main text. Correspondingly, Fig. R10 is presented as Fig. 4 in the main text, Fig. R11 as Supplementary Fig. 9, and Fig. R12 as Supplementary Fig. 11.\n6) In Supplementary Fig. 9, a ReLU function cannot be implemented with only a single analog switch. How is the comparison operation (i.e., determining whether x < 0 or x > 0) realized in the analog domain?\nThank you for your in-depth review and valuable comments on this detail. Indeed, it is not feasible to implement the rectification output of the ReLU function using only a single switch in the analog domain. The single switch symbol in the previous illustration was intended to facilitate the understanding of the basic function of a ReLU-like electronic switch. However, since this form lacks the ability to determine the polarity of the input voltage, a detailed demonstration of the ReLU activation function is provided here.\nFirstly, to provide a more intuitive comparison of the hardware implementation complexity between the SiLU and ReLU nonlinear activation functions, we present the complete circuit schematics of both the SiLU51 and ReLU designs (Fig. R13). Specifically, the construction of the SiLU circuit51 is relatively challenging, as this circuit involves an exponential circuit (highlighted in the orange box), an external constant current source (1 A), two operational amplifiers, and a division circuit. In particular, the exponential circuit additionally requires a constant current source supplying the reference current and two operational amplifiers.51 Under these conditions, configuring such a complex circuit merely to generate the output of a single SiLU(x) function is highly impractical for large-scale network integration.\nOn the other hand, the ReLU function ( ReLU(V)max{0,V} ) can be implemented through a combination of the feedback amplifiers and diodes to achieve analog-level transformation (Fig. R14a). This circuit has been validated through Simscape electrical simulations, and the ReLU operation is well-supported by the simulation result (Fig. R14b and c). This approach is designed to transmit the voltage in the ReLU form and effectively determine the polarity of the input signals.\nFig. R13 | Hardware implementation of SiLU and ReLU functions. a Graph of SiLU(x). b Graph of ReLU(x). c Schematic of SiLU circuit. d Schematic of ReLU circuit.\nFig. R14 | Rectifying linear unit (ReLU) circuit. a Circuit schematic. V and V i o represent the input and output voltages of the ReLU function circuit module, respectively. b Circuit built within the Simscape electrical simulation platform. For the configuration, V is swept from -1 V to 1 V using a controlled voltage source, and the i V is measured using a voltage sensor. c V -V characteristic curve, which is o o i consistent with the numerical simulation of ReLU.\nAdditionally, considering that the ReLU function at the input side processes the given analog signals rather than performing computations within the network, a simpler approach is to directly utilize a signal function generator (included in the input buffer50) to generate the required signals. However, this part pertains to the peripheral configuration for generating input signals, rather than the processing element (PE) chip52 responsible for processing within the neural network.53 Therefore, such peripheral configuration falls outside the scope of this study. The specific simplified approach to be used can be chosen based on the actual PE board design.\nThe response is mentioned in Supplementary Note 10 of the latest revised manuscript and is referenced in the 'Principle of MAC Operations in G-KANs' section of the 'Methods' in the main text. Correspondingly, Fig. R13 is presented as Supplementary Fig. 20, and Fig. R14 as Supplementary Fig. 21.\n7) Simulink is generally used for system-level simulations, and VHDL is designed for modeling digital circuits at the behavioral level. Since the proposed CIM framework targets fully analog circuits, the simulation results shown in Supplementary Fig. 10 are not representative of analog behavior and are therefore unconvincing.\nWe sincerely appreciate the reviewer’s critical insight regarding the appropriateness of simulation tools used in Supplementary Fig. 10 of the original manuscript. We acknowledge that the earlier description may have caused misunderstanding, and we regret any confusion this may have caused.\nTo clarify, the previously mentioned reference to ‘VHDL’ stemmed from the optional settings under ‘HDL Code Generation > Set Basic Options’ within Simulink. It was not our intention to suggest that VHDL was directly involved in the simulation or modeling process. The actual model presented in the previous Supplementary Fig. 10 was constructed entirely using the ‘Commonly Used Blocks’ library in Simulink. Notably, each GMC was encapsulated as a self-contained functional module, with input-output behavior designed to reflect experimentally measured I - V d g characteristics of the fabricated devices in this work.\nTo address the reviewer’s concern about analog-level validation, we have revised the simulation methodology in the current version. Specifically, we reconstructed the full array of 200 GMCs in the Simscape Electrical platform (‘Foundation Library > Electrical’) to ensure more rigorous physical-level modeling. As illustrated in Fig. R15a, a single GMC unit—composed of an AAT and a memristor in series—cannot be instantiated directly from standard Simscape library components. However, based on GMC’s characteristic behavior, each GMC branch can be accurately modeled as a voltage-controlled current source (VCCS). Subsequently, following Kirchoff’s current law (KCL), the current output from a parallel array of GMCs (Fig. R15b) equals the algebraic sum of all individual branch currents. This cumulative current inherently performs the MAC operation across all basis functions in the analog domain, fully capturing the kernel computation of the KAN architecture. The resulting current is then converted to an analog voltage via a transimpedance amplifier (TIA). Such a configuration utilizes the negative feedback of the operational amplifier to form a virtual ground, thereby clamping the source line voltage to a stable ground level and minimizing readout errors.10 Finally, the differential operation is performed by an op-amp (Fig. R15c). Notably, the entire forward computation process—covering input application, weighted current generation, voltage readout, and differential-pair subtraction—is completed entirely in the analog domain within the full array (Fig. R15d). In addition, Fig. R16 displays the oscilloscope waveform captured during the operation of this circuit.\nFig. R15 | GMC array constructed in the Simscape Electrical platform. a VCCS equivalent of the GMC branch and the parallel equivalent circuit of the GMC array. b Partial view of the crossbar circuit of GMCs. c TIAs used for voltage-mode output ( R 1 ), while the op-amp for differential operation with R I I  and 1 M m R 1 . Here, I and I represent the values of the GMC current peak, 2 M m respectively. d Demonstration of the GMC array with 100 basis functions (200 GMCs). Furthermore, the output voltages of a pair of TIAs are processed through an op-amp to II perform an amplified differential operation to produce the final output (V  ) o I I M m of the G-KAN’s network computation. The output waveform is then observed using a ‘Voltage Sensor’ and a ‘Scope’ block.\nFig. R16 | The oscilloscope waveform of the output voltage sweep for the circuit corresponding to Fig. R15. This measurement used a sampling period of 0.02 seconds, collecting a total of 5000 output signals via a voltage sensor. The horizontal axis represents time (in seconds), and the vertical axis represents voltage (in volts).\nIn summary, these enhancements not only strengthen the physical fidelity of the simulation but also more accurately reflect the analog behavior of the proposed CIM framework. We thank the reviewer again for this valuable suggestion, which has led to a significant improvement in the rigor and clarify of our work.\nThe response is mentioned in Supplementary Note 2 of the latest revised manuscript and is referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the main text. Correspondingly, Fig. R15 is presented as Supplementary Fig. 13.\nResponse 3-2:\n(2.1) The claimed advantages of implementing KANs using GMC-based CIM are not supported by solid evidence. The algorithm-level benefits highlighted by the authors are inherent to the KAN architecture itself and are not specific to the proposed hardware implementation.\nWe sincerely thank the reviewer for the valuable insights into the integration advantages of KAN and GMCs. This issue is fundamental to the core intent to this research. We note that Reviewer 2 has independently addressed this central point, which further convinces us that providing a detailed explanation of this aspect is crucial to highlighting the value of our work. Therefore, we offer this comprehensive response to substantiate the key contributions of this research.\nAs Gaussian kernels (i.e., the simplified description of ‘Gaussian-like basis functions’) are the fundamental computational elements in KANs, the effectiveness of KAN’s hardware implementation largely depends on how efficiently the computation and training of these kernels can be realized through devices or circuits. Existing hardware architectures, including von Neumann and near-memory systems, encounter significant limitations both in executing Gaussian kernels and in performing training, which restricts the full potential of KANs. The proposed GMCs are introduced specifically to address the shortcomings that current devices and architectures cannot overcome (Fig. R1). To emphasize the transformative impact of GMC-based implementation on hardware KANs, the following content will provide real-world examples that illustrate why traditional hardware architectures are inadequate for KAN’s implementation, thereby highlighting the advantages of G-KANs.\n(1) Dilemmas of von Neumann architecture (corresponding to Dilemma 1-3 in Fig. R1b)\nIn von Neumann architectures, the physical separation between the processor and memory leads to the continuous transfer of data and instructions between them during computation due to the disparity between memory bandwidth and awaiting data.1 Moreover, memory access introduces significant time and energy overhead, with much of the energy being consumed during data transfer rather than computation (Dilemma 1 and 2).1,2 The graphics processing unit (GPU), a prime example of optimized computing design, is widely used due to its exceptional performance in general matrix multiplication (GEMM)3. GPUs excel in neural network computations, efficiently performing linear transformations with high computational density by utilizing regular operations and contiguous memory access4, while the central processing unit (CPU) merely initiates scheduling, minimizing offloading overhead.5 However, these capabilities are not fully realized in KAN’s computations. Using Gaussian kernels as basis functions, the inference of a KAN requires sequential operations such as squaring ( (xa)2 ), scaling (  (xa)2 ), exponential transformation ( exp() ), weighted multiplication ( c exp() ), and accumulation (  ). These operations cannot be directly handled by GEMM, necessitating frequent kernel launches during each feedforward pass, with each launch scheduled by the CPU, thus significantly increasing the CPU-GPU offloading overhead (Dilemma 3). Even more concerning, KAN’s more complex computational elements require more hardware resources and power than MLPs, even when the number of parameters is the same.2,6\n(2) Dilemmas of near-memory implementations (corresponding to Dilemma 4-6 in Fig. R1b)\nThe previous evidence highlights the incompatibility of KANs with the von Neumann architecture. As a result, it is essential to implement KANs on hardware platforms with greater computational and memory density. In this context, researchers have sought to overcome the limitations of the von Neumann architecture through near-memory computing.7 For KAN-related applications, typical approaches include lookup table (LUT)8 and piecewise linear (PWL)9 circuit designs. Although LUT-based circuits can output Gaussian kernels directly at the hardware level, this approach introduces considerable computational complexity and storage overhead. For instance, implementing a single Gaussian kernel requires 452 LUTs.8 When extended to network-level implementations, particularly in densely integrated architectures like KANs, the resulting operational costs become unsustainable (Dilemma 4).\nFurthermore, recent research has applied CMOS integration technology based on PWL approximation to model activation functions in KANs.9 However, this approach presents several fundamental limitations: First, the PWL function requires predefined breakpoints (X ), slopes (M ), and intercepts (Y ) for each segment (X  X  X ), which must be stored in external memory. Second, the hardware architecture must incorporate numerous comparators (COMPs) and sensing circuits to determine the segment corresponding to the input signal, retrieve the associated parameters (M and n Y ) from memory, and pass them to the MAC circuits to complete the linear computation. As such, even for simple operations, this method still incurs significant hardware resource overhead (Dilemma 5).\nAn overall assessment of both LUT-based and PWL-based strategies reveals that not only do they demand considerable hardware resources—such as multipliers (MPLs), adders (ADDs), and comparators (COMPs)—for executing Gaussian kernel computations, but also, due to their hardwired architecture, they are incapable of performing parameter updates (Dilemma 6). Although both strategies attempt to mitigate the von Neumann bottleneck, they ultimately fall short due to their inability to incorporate trainable characteristics into the neural networks.\nGiven these limitations in existing CMOS-based implementations, there has been a shift towards the exploration of dedicated KAN-type CIM architectures. Clearly, memristors alone are insufficient to perform in-memory computation for nonlinear functions like Gaussian kernels. The following section will specifically discuss how the GMCs and array design introduced in this work effectively address these challenges.\n(3) Solutions leveraging GMC-based implementation (corresponding to Solution 1-5 in Fig. R1b)\nThe transfer characteristics of GMCs enable the direct generation of stable, parameterized Gaussian kernels, effectively capturing the mathematical behavior of Gaussian-like functions within the analog domain. Additionally, by adjusting the memristor conductance via write voltages, the peak of the Gaussian kernel can be flexibly controlled, allowing electrical programming of the learnable coefficients. On the architectural side, the one-transistor-one-memristor structure of GMCs facilitates seamless integration into crossbar arrays.10 According to KCL, the output currents from all GMCs in the same column can be physically summed on the source line, directly performing the linear combination of Gaussian kernels in a KAN. Consequently, the GMC-based implementation enables the full computation from input to output to be completed within the analog domain (Solution 1).\nMoreover, the traditional dilemma in CMOS-based implementations (Dilemma 2) arises from the physical separation of processor and memory.1 The GMC-based solution fundamentally alters this model by adopting the CIM paradigm. The core advantage of this approach is that computation and data storage are synchronized at the same physical location, eliminating the need for frequent data transfers between memory and processing units. This removes the conflict between memory bandwidth and processing throughput, and concentrates energy consumption on computation (Solution 2). At the same time, the in-situ CIM operation mode completely avoids the offloading overhead intrinsic to the von Neumann architecture (Solution 3).\nTo address the hardware scaling challenge (Dilemma 4) faced by CMOS-based systems—where increasing the number of basis functions leads to a nonlinear explosion in hardware resource consumption—the GMCs introduced in this study provide a straightforward solution through linear scaling approach. Specifically, under the differential-pair encoding scheme, each Gaussian kernel requires only a fixed pair of GMCs. This ensures that hardware scaling grows linearly with the effectively prevents unmanageable resource consumption, keeping the hardware scale of a G-KAN predictable and scalable (Solution 4).\nEqually important, the GMC-based approach avoids the complex and segmented operations typical of near-memory computing solutions (Dilemma 5 and 6). Within GMC arrays, an input vector is loaded in parallel across all rows, enabling each cell to simultaneously perform in-situ Gaussian-like mapping and MAC operations. By utilizing the native physics of the crossbar array and KCL, the entire matrix transformation is executed in one step, eliminating the need for piecewise function evaluation, memory-based parameter retrieval, and data transfer. This one-step operation completely removes the timing and control overhead associated with multi-step processes in CMOS-based implementations, significantly reducing computational complexity (Solution 5).\nThe main dilemmas faced by the CMOS-based implementations, along with their corresponding solutions provided by the GMC-based approach, are visually summarized in Fig. R1. In addition, a comprehensive comparison of the key features of the reference objects is presented in Table R1.\nFig. R1 | Overview of KAN’s hardware implementation strategies. a Reference object and benchmark metrics for the hardware implementation of KAN. b The dilemmas encountered by the von Neumann and near-memory architectures in processing the computations of KAN, while the GMC-based implementation provides a reliable solution at the in-memory computing level. c The GMC ingeniously combines the Gaussian kernel provided by AAT with the parameterization capability of memristors, integrating the necessary physical foundation for the in-memory computing required by KAN.\nFurthermore, to systematically underscore the advantages of GMCs in implementing KAN and in representing the basis functions (i.e., Gaussian kernels) associated with each activation link, we provide a comparative analysis against alternative implementation routes along with their corresponding reference objects and benchmark metrics. Table R1 offers a comprehensive summary across multiple dimensions of comparison, as outlined below.\nTable R1 Comparison for implementing KAN across different benchmarks.\nReference objects Von Neumann Near-Memory GMC-based\nArchitecture Architecture Crossbar Array\n1. hardware 1. memory-bound; physically\ndependance: 2. Separation of in-device\nDSPs/GPUs/FFs/ parameterization generation\nRAMs/LUTs6,11-13; and kernel\n2. Muti-step computation;\npointwise operators 3. Non-adjustable\n(squaring→ functions\nParameterized multiplication→ (hardwired);\nGaussian kernel exp()→ 4. Reliance on a\nimplementation multiplication); large number of\n3. memory- computational\nbound;14,15 modules8,9\n4. frequent\nmemory\naccessing16\n☹ ☹  \nif one-shot? No No Yes\nComputing in NOT partial complete\nmemory\n☹ ☹  \nif one-shot? No No Yes\n1. Data loading and (LUT-based)8 analog MAC\nscheduling ADC→multi-bit implemented on\ninitialization (CPU input (address)→ the crossbar array\nside); multi-bit output→\n↓ DAC;\n2. Multi-step chain (PWL-based)9\nPipeline of pointwise binary encoding→\noperators; breakpoint detection\n↓ →accessing\n3. Weighted slope/intercept\naccumulation; memory\n↓ →parameter\n4. Memory copy fetching→digital\nMAC→DAC\n☹ ☹  \nif one-shot? No No Yes\n(partially parallel (partially parallel)9 (completely\non GPUs) 1. memory-bound; parallel)\n1. memory- 2. massive 1. access-free\nbound;17 computational memory;\n2. high overhead of modules; 2. offloading-\ndata movement;18 3. intricated control free;\n3. significant CPU- flow (PWL-based 3. one-shot\nComputational GPU offloading scene); parallel VMM\nparallelism latency and energy 4. redundancy in and MAC\nconsumption;19 address (LUT-based process;\n4. high overhead of scene) or parameter 4. simple control\nscheduling and (PWL-based scene) mechanism\nsynchronization20,21 access (voltage-pulse\ndirect drive)\n☹ ☹  \n1. memory and 1. memory and 1. device count\ncomputation computation demand increases\ndemand grows demand grows linearly with\nsuperlinearly with superlinearly with computational\nthe number of the number of scale (one basis\nparameters; parameters function is\n2. exponentially implemented by a\nincreasing memory pair of GMCs)\nHardware copy latency;*\noverhead change 3. memory\nbandwidth\nbottleneck\namplifies with\nincreasing\ncomputational\nscale22\n☹ ☹  \nNO (hardwired) YES\nIn-situ training --\n☹  \n* https://developer.nvidia.com/gdrcopy\nWe have included the response in Supplementary Note 1 of the latest revision of the manuscript. Additionally, Fig. R1 is presented as Fig. 2 in the latest main text, while Table R1 is shown as Supplementary Table 1 in the latest Supplementary Information.\n(2.2) At the hardware level, the claim of reduced device count compared to MLPs is based on an unfair comparison: the authors only consider the number of memristor devices required for KANs versus MLPs, while overlooking the significantly higher circuit complexity associated with implementing KANs using GMCs. This undermines the validity of the claimed hardware efficiency.\nThanks for the reviewer’s critical observation. We have discussed about the reviewer’s comment regarding the comparison of device counts. Since a complete hardware system involves numerous components, and the peripheral design methodologies of MLPs and KANs differ in ways that make their device counts hard to quantify directly, a simple comparison based solely on memory devices would be unfair. We sincerely appreciate the reviewer for highlighting this critical point, and we have accordingly removed this experiment from the manuscript to ensure the overall rigor of this work.\nReference\nREVIEWER COMMENTS\nReviewer #2 (Remarks to the Author):\nI appreciate the authors' comprehensive responses, which have satisfactorily addressed all my previous concerns. Therefore, I recommend the manuscript for publication.\nWe sincerely appreciate your recognition of this research and the revisions. The critical comments you previously provided played a key role in refining the logic and enhancing the rigor of this paper. We are very pleased that the revisions have met your approval, and we deeply appreciate the time and effort you dedicated to the entire review process!\nReviewer #3 (Remarks to the Author):\nThe authors have thoroughly revised both the manuscript and the supplementary information, addressing most of my previous concerns regarding peripheral circuit designs. While the manuscript has improved in technical details, I still have concerns about the presented comparisons and several major claims. As I understand it, the primary contributions of this work are the fabrication and characterization of the GMC cell, along with circuit design and simulation demonstrating the feasibility of using the GMC cell for hardware implementation of KAN.\nResponse:\nWe appreciate your recognition of the revisions made to the proposed circuit design. Under your guidance, we have addressed key weakness in the previous version, thereby significantly enhancing the scientific rigor of this research. Meanwhile, we fully understand the reviewer’s cautious stance on the current technical details and main conclusions. In accordance with your suggestions, we have further revised the manuscript and included analysis of relevant hardware benchmark metrics to more robustly support the conclusions of this study regarding hardware advantages.\n1. The authors claim that the GMC-based KAN exhibits “strong learning capabilities” and “excellent continual learning capability.” These properties are inherent to the KAN architecture and would be expected regardless of whether the GMC cell is used. I therefore recommend that the authors clearly distinguish algorithmic capabilities from device-level contributions. In particular, the manuscript should emphasize the advantages introduced by the GMC cell, such as improved energy efficiency and computational speed enabled by in-memory computing, rather than implying that these learning capabilities originate from the GMC cells.\nResponse to 3-1:\nWe appreciate your constructive comments regarding the appropriateness of the conclusion statements. Following your suggestions, we have revised the relevant sections in the main text, including the Abstract, Introduction, Results, Discussion, as well as related statements in Supplementary Information (marked in red). These revisions aim to clearly state that the simulation results of the architecture proposed in this work is intended to validate the inheritance to KAN’s advantages (which is the prerequisite for the system’s feasibility), rather than relying on GMCs themselves to achieve these algorithmic advantages. In addition, the revised phrasing aims to avoid any overclaimed expressions regarding the contributions of this study. Furthermore, regarding the parallel computing advantages and energy efficiency improvements brought by the computing-in-memory architecture, we have provided a detailed explanation and quantitative study in the response to next question.\n2. The performance comparison between G-KAN and M-MLP in Fig. 5 is not directly relevant to the main contributions of the work. As I understand it, a comparison between KAN and MLP would yield similar trends, since the observed performance differences are attributable to the underlying network architectures rather than the use of the GMC cell. Therefore, the advantages shown in Fig. 5 do not arise from the proposed device or circuit designs. Instead, I would expect quantitative comparisons that directly demonstrate the benefits of the GMC-based in-memory computing architecture, such as improvements in energy efficiency and computational throughput, compared to a CMOS-based implementation, in order to substantiate the advantages presented in Fig. 2.\nResponse to 3-2:\nWe sincerely appreciate the reviewer’s insightful comments. The issue regarding the comparison of performance between G-KAN and M-MLP in Figure 5 is crucial for enhancing the rigor and clarity of the contribution in this paper.\nFirst, we fully understand the reviewer’s concern. The performance differences between software-level algorithms (KAN and MLP) are supported by related studies. The reviewer’s comments highlighted that the original phrasing might have led to a misinterpretation of Figure 5, suggesting it demonstrated \"AI performance advantages brought by GMCs.\" We have revised the manuscript (marked in red) to clarify that the comparison aims to verify the hardware platform's ability to preserve algorithmic advantages, shifting the focus to the core contribution—performance benefits of the GMC-based in-memory computing architecture.\nNext, in accordance with the reviewer’s suggestion, we conducted the study on the energy efficiency of the GMC-based architecture.1-5 Specifically, we compared the GMC-based system with two recently launched NVIDIA graphics processing units (GPUs).\nThe experiment was conducted on a predefined scale of the KAN [784,100,10] (grid size = 4), combining the corresponding GMC array and peripheral circuits. The inference latency was set to 300 ns, and the average power consumption of each GMC device was measured to be 16.6345 nW. The total system energy consumption consists of the energy of the array (E ) and that of the peripheral circuits (E ), with the array perip latter primarily driven by neurons using the differential-pair mechanism, each output neuron equipped with three high-bandwidth and low-power operation amplifiers6,7. The specific formulas for energy consumption calculation are as follows:\nn 7841001001042635200 (R1)\ndevice\nn 100103330 (R2)\nopa\nE 63520016.6345nW300ns=3.17nJ (R3)\narray\nE 3300.34mW300ns33.66nJ (R4)\nperip\nE  E E 36.83nJ (R5)\ntotal array perip\nHere, n represents the total number of devices in the GMC array, and n device opa denotes the total number of operational amplifiers used to implement the neurons.\nMoreover, according to the definition of energy efficiency1-3,7, the computational workload must first be quantified. Since the GMC array performs the parameterized\n  x 2\nGaussian transformation and accumulation (Aexp\n \n) operation in one\n    \nstep, such the operations need to be equated to the corresponding number of operations\n  x 2\nin CMOS architectures. In computer electronics, the operation Aexp   \n    \nx  x 2  x 2   x 2\nis executed step by step: x→ →   →   →exp   \n           \n  x 2   x 2\n→ Aexp    → Aexp    . Among these steps, the\n         \ntranscendental function exp in double precision calculations involves 29 operations in floating-point architectures based on the reduction-approximation-  x 2\nreconstruction principle.8 Therefore, the Aexp    operation in\n    \ncomputer hardware is equivalent to 35 operations in total. Based on this, the energy efficiency of the GMC-based system can be calculated as follows:\n63520035operations\nEE  603.64TOPS/W (R6)\n36.83nJ\nTable R1 presents the comparison results of energy efficiency, where the energy efficiency of the GPU is calculated based on the ratio of its peak throughput to thermal design power (TDP)7.\nTable R1 Comparison of hardware energy efficiency\nEnergy Efficiency\nArchitecture\n(TOPS/W)\nRTX PRO 2000 Blackwell *1 7.79\nRTX 2000 Ada Generation *2 2.74\nThis work 603.64\n*1: https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-2000/workstation-datasheet-blackwell-rtx-pro-2000-nvidia-us-4016661.pdf\n*2: https://www.nvidia.com/en-us/products/workstations/rtx-2000/\nThe CIM architecture and the ability to execute one-shot transcendental functions by GMCs provide the GMC-based system with parallel computation and low power consumption, which contributes to the high energy efficiency demonstrated in Table R1.\nIn addition, the comparison of hardware benchmark metrics has been submitted with the Supplementary Note in the revised Supplementary Information.\nWe would like to once again express our sincere gratitude to the reviewer for the valuable comments and detailed guidance provided during this round of review. The reviewer’s suggestions have significantly enhanced the rigor and clarity of the contribution in this paper, and the related revisions have effectively improved the final presentation of the manuscript.\n3. The manuscript primarily focuses on single-device-level experiments and circuit-level design and simulations. I therefore suggest that the authors avoid using the term “implementation” in the title and clearly clarify in the main text that the proposed G-KAN has not been “implemented” at the system level to prevent overclaim of the experimental scope and ensure that the statements accurately reflect the demonstrated results.\nResponse to 3-3:\nWe sincerely thank the reviewer for this insightful suggestion. We completely agree with your concern and have revised the title accordingly. Specifically, we have replaced “Implementation” with “Architecture,” resulting in the updated title: “Computing-in-Memory Architecture for Kolmogorov–Arnold Networks Based on Tunable Gaussian-Like Memory Cells”.\nMoreover, in both the main text and Supplementary Information, we have revised certain statements (marked in red), removing the expression that could lead to misinterpretation or over-interpretation, in order to ensure the rigor of the content and present the research more objectively. Thank you again for helping us present our work with appropriate precision.\nReferences\nREVIEWER COMMENTS\nReviewer #3 (Remarks to the Author):\nThe authors have addressed my previous concerns. One additional comment is that the authors should clearly state that the energy-efficiency estimation added in the revised manuscript is based on idealized assumptions, as the analysis considers only the G-KAN implementation, whereas the GPUs are general-purpose computing platforms.\nResponse:\nWe are very happy to hear that you acknowledge our previous revision as effectively addressing your concerns, which also means that we have successfully refined an important detail in this study. Meanwhile, regarding your suggestion for additional clarification, we fully agree and have added the corresponding statement in the latest version of the Supplementary Note, emphasizing that the energy efficiency results are estimated based on idealized assumptions. Once again, we sincerely appreciate your valuable guidance and contribution in this work!"}, {"round": 2, "reviewer_comments": {"reviewer_2": "I appreciate the authors' comprehensive responses, which have satisfactorily addressed all my previous concerns. Therefore, I recommend the manuscript for publication.", "reviewer_3": "The authors have thoroughly revised both the manuscript and the supplementary information, addressing most of my previous concerns regarding peripheral circuit designs. While the manuscript has improved in technical details, I still have concerns about the presented comparisons and several major claims. As I understand it, the primary contributions of this work are the fabrication and characterization of the GMC cell, along with circuit design and simulation demonstrating the feasibility of using the GMC cell for hardware implementation of KAN. However, the manuscript attributes certain learning capabilities, inherent to the KAN architecture itself, to the GMC cell. This attribution is not well justified and, in my view, overstates the role of the device. Some detailed comments are as follows: 1. The authors claim that the GMC-based KAN exhibits “strong learning capabilities” and “excellent continual learning capability.” These properties are inherent to the KAN architecture and would be expected regardless of whether the GMC cell is used. I therefore recommend that the authors clearly distinguish algorithmic capabilities from device-level contributions. In particular, the manuscript should emphasize the advantages introduced by the GMC cell, such as improved energy efficiency and computational speed enabled by in-memory computing, rather than implying that these learning capabilities originate from the GMC cells. 2. The performance comparison between G-KAN and M-MLP in Fig. 5 is not directly relevant to the main contributions of the work. As I understand it, a comparison between KAN and MLP would yield similar trends, since the observed performance differences are attributable to the underlying network architectures rather than the use of the GMC cell. Therefore, the advantages shown in Fig. 5 do not arise from the proposed device or circuit designs. Instead, I would expect quantitative comparisons that directly demonstrate the benefits of the GMC-based in-memory computing architecture, such as improvements in energy efficiency and computational throughput, compared to a CMOS-based implementation, in order to substantiate the advantages presented in Fig. 2. 3. The manuscript primarily focuses on single-device–level experiments and circuit-level design and simulations. I therefore suggest that the authors avoid using the term “implementation” in the title and clearly clarify in the main text that the proposed G-KAN has not been “implemented” at the system level to prevent overclaim of the experimental scope and ensure that the statements accurately reflect the demonstrated results."}, "author_response": "Reviewer #2 (Remarks to the Author):\nThe revised manuscript provides more comprehensive details regarding the implementation of the proposed G-KAN and addresses several of my previous concerns. However, there are still some important issues that need to be addressed.\nResponse: We sincerely thank the reviewers for these constructive comments on our revised manuscript. We are delighted that the previous improvements have already received positive responses. Reviewer's comments have been valuable in helping us further clarify the key contributions of this work and strengthen its overall presentation. We carried out a more detailed revision process, carefully addressing each suggestion point by point. We conducted additional experiments to enhance the rigor of our work and ensure that the narrative can more clearly convey the significance of our findings. We hope these improvements further demonstrate the potential of the GMC-based KAN framework.\n1. While the response includes a comparison between G-KAN and M-MLP to demonstrate performance advantages, these benefits appear to stem largely from the inherent characteristics of the KAN architecture itself. The revised manuscript still provides limited discussion on the specific advantages of the GMC-based implementation. More thorough discussion and comparative visual evidence are required to underscore the contribution of the proposed GMC implementation.\nResponse 2-1: We sincerely appreciate the insightful comments provided by the reviewer, which have offered a valuable opportunity to further clarify and enhance the significance of our research. In the revised manuscript, we have included a comparative analysis of typical hardware implementation approaches to highlight the significant and adaptability advantages of GMCs in executing KAN-type networks.\nAs Gaussian kernels constitute the most underlying computational units in KANs, the key factor in determining whether KANs can be effectively hardware-implemented lies in how effectively the Gaussian kernels’ computation and training can be realized through devices or circuits. However, existing hardware architectures (von Neumann and near-memory architectures) face significant bottlenecks, both in implementing the Gaussian kernels and in training, which ultimately hinder the full potential of KANs. The proposed GMCs are specifically introduced to overcome the challenges that current devices and architectures cannot address (Fig. R1). To fully highlight the significance of GMC-based implementation for hardware KANs, the following section will present real-world cases to demonstrate why conventional hardware architectures are unsuitable for implementing KANs, thus contrasting the advantages of G-KANs.\n(1) Dilemmas of von Neumann architecture (corresponding to Dilemma 1-3 in Fig. R1b)\nIn the von Neumann architecture, the physical separation of the processor and memory requires continuous data and instruction transfer between them during execution. Since memory bandwidth is much lower than the processing throughput, processing cores often remain underutilized while waiting for data.1 Moreover, accessing memory incurs significant time and energy costs, with much of the energy spent on data transfer rather than computing (Dilemma 1 and 2).1,2 Additionally, the graphics processing unit (GPU) is a representative example of optimized computing design. GPUs have become prevalent for their remarkable acceleration in general matrix multiplication (GEMM)3. In neural network computations, GPUs can perform linear transformations with high computational density by exploiting highly regular operations and contiguous memory access4, while the central processing unit (CPU) only needs to initiate a single scheduling process, minimizing offloading overhead.5 However, these capabilities are not fully leveraged in KANs’ computation. Taking Gaussian kernels as the basis functions, the inference process involves sequential operations, which contain squaring ((xa)2), scaling multiplication ( (xa)2), nonlinear exponential transformation (exp()), weighted multiplication (c exp()), and accumulation ( ). These operations cannot be directly handled by GEMM, requiring frequent kernel launches per feedforward processing (each scheduled by the CPU), significantly increasing CPU-GPU offloading overhead (Dilemma 3). Worse yet, KAN’s complex computational components consume more hardware resources and power compared to MLPs, even with the same number of parameters.2,6\n(2) Dilemmas of near-memory implementations (corresponding to Dilemma 4-6 in Fig. R1b)\nThe evidence above confirms the incompatibility of KANs with the von Neumann architecture. Therefore, it is crucial to implement KANs on hardware platforms with higher computational and memory density. In this context, researchers have attempted to alleviate the dilemmas of von Neumann architecture through near-memory computing7. For KAN-related applications, typical examples include lookup table (LUT)8 and piecewise linear (PWL)9 circuit designs. Although LUT-based circuits can directly output Gaussian kernels at the hardware level, this strategy inevitably introduces significant computational complexity and storage address overhead. For instance, implementing a single Gaussian kernel requires 452 LUTs.8 When scaled to a network level, for highly densely integrated architectures like KANs, the resulting operational costs become unbearable (Dilemma 4).\nMoreover, a recent study have employed CMOS integration technology based on PWL to directly approximate the activation functions (connections) in KANs.9 However, this strategy has several inherent bottlenecks: first, the PWL function requires predefined breakpoint ( X ), slope ( M ) and intercept ( Y ) of each segment (X  X  X ), which must be stored in peripheral memories; second, the hardware architecture must integrate massive comparators (COMPs) and sensing circuits to determine which segment the input signal belongs to, then retrieve the corresponding slope and intercept from the buffers and pass these parameters to the MAC circuits to complete the linear operation (F(X)M *X Y ). Therefore, even for simple and few target operations, this approach still suffers from heavy hardware resource overhead (Dilemma 5).\nOverall evaluation of these two strategies reveals that they not only require significant hardware resources such as multipliers (MPLs), adders (ADDs), and COMPs to execute Gaussian kernel computations, but also, due to their hardwired electrical architecture, are physically incapable of implementing parameter update functionality (Dilemma 6). Therefore, although both aim to alleviate the von Neumann bottleneck, LUT-based and PWL-based implementations ultimately suffer from a fundamental flaw due to their inability to endow the neural network with trainable characteristics.\nIn the context given above, the limitations of existing CMOS-based implementations have led to the exploration of dedicated KAN-type computing-in-memory (CIM) architectures. Clearly, memristors alone cannot achieve in-memory computation for nonlinear functions such as Gaussian kernels. The following content will specifically elaborate on how the GMCs and the array design proposed in this work effectively address the aforementioned challenges.\n(3) Solutions relying on GMC-based implementation (corresponding to the Solution 1-5 in Fig. R1b).\nThe transfer characteristics of GMCs can directly generate stable and parameterized Gaussian kernels, naturally representing the mathematical behavior of Gaussian kernels in the analog domain. In addition, by adjusting the conductance of memristors through write voltages, the peak height of the Gaussian kernel can be flexibly controlled, enabling electrical programming of the learnable coefficients. At the architectural level, the one-transistor-one-memristor structure of GMCs facilitates easy integration into crossbar arrays.10 According to the KCL, the output currents of all GMCs in the same column can be physically accumulated on the source line, directly performing the linear combination of Gaussian kernels in a KAN. Therefore, the GMC-based implementation can complete the full computation from input to output within the analog domain (Solution 1).\nFurthermore, the Dilemma 2 in conventional CMOS-based implementations arises from the physical separation between processor and memory.1 The GMC-based implementation fundamentally reshapes this paradigm through the CIM approach. The core mechanism lies in synchronizing computation and data storage at the same physical location, thus completely avoiding the frequent data transfers between memory and processing units. As a result, the conflict between memory bandwidth and processing throughput is eliminated, with energy consumption focused on computation (Solution 2). Meanwhile, the in-situ CIM working mode also entirely avoids the offloading overhead inherent in von Neumann architecture (Solution 3).\nTo address the hardware catastrophe scaling problem (Dilemma 4) faced by CMOS-based implementations—an inherent bottleneck where the growth in the number of basis functions triggers a nonlinear explosion in hardware resource consumption—the GMCs proposed in this study offers a fundamental solution through a linear hardware scaling paradigm. Specifically, under the differential-pair encoding rule, each Gaussian kernel requires only a fixed pair of GMCs. This ensures that the hardware scale expands strictly linearly with the number of Gaussian kernels, which is equivalent to the network scale of a KAN. As a result, this approach fundamentally prevents uncontrollable resource consumption at the hardware level, ensuring that the hardware scale of a G-KAN remains predictable and manageable throughout (Solution 4).\nOf equal significance, the GMC-based paradigm circumvents the complex and segmented operations that characterize near-memory computing implementations (Dilemma 5 and 6). Within the GMC arrays, an input vector is loaded in parallel across all rows, enabling each cell to perform in-situ Gaussian-like mapping and MAC operations simultaneously. By leveraging the native physics of the crossbar array and KCL, the complete matrix transformation is executed in one step, thereby obviating the need for piecewise function evaluation, parameter retrieval from memory, and data shuttling. This one-shot process fundamentally eliminates the timing and control overhead associated with multi-step operations in CMOS-based implementations, achieving a drastic reduction in computational complexity (Solution 5).\nThe primary dilemmas confronting the aforementioned CMOS-based implementations and their corresponding solutions enabled by the GMC-based implementations are graphically summarized in Fig. R1. Furthermore, a detailed comparison of the key attributes discussed for the reference objects is provided in Table R1.\nFig. R1 | Overview of KAN’s hardware implementation strategies. a Reference object and benchmark metrics for the hardware implementation of KAN. b The bottlenecks encountered by the von Neumann and near-memory architectures in processing the computations of KAN, while the GMC-based implementation provides a reliable solution at the in-memory computing level. c The GMC ingeniously combines the Gaussian kernel provided by AAT with the parameterization capability of memristors, integrating the necessary physical foundation for the in-memory computing required by KAN.\nFurthermore, in order to more systematically highlight the advantages of GMC in implementing KAN and the basis functions (i.e., Gaussian kernels) for each activation connection, we compare different implementation paths with their reference objects and benchmark metrics. Table R1 present a complete summary across several comparative dimensions as below.\nTable R1 Comparison for implementing KAN across different benchmarks.\nReference objects/ Von Neumann Near-Memory GMC-based\nbenchmarks Architecture Architecture Crossbar Array\n1. hardware 1. memory-bound; physically\ndependance: 2. Separation of in-device\nDSPs/GPUs/FFs/ parameterization generation\nRAMs/LUTs6,11-13; and kernel\n2. Muti-step computation;\npointwise operators 3. Non-adjustable\n(squaring→ functions\nParameterized multiplication→ (hardwired);\nGaussian kernel exp()→ 4. Reliance on a\nimplementation multiplication); large number of\n3. memory- computational\nbound;14,15 modules8,9\n4. frequent\nmemory\naccessing16\n☹ ☹  \nif one-shot? No No Yes\nComputing in NOT partial complete\nmemory\n☹ ☹  \nif one-shot? No No Yes\n1. Data loading and (LUT-based)8 analog MAC\nscheduling ADC→multi-bit implemented on\ninitialization (CPU input (address)→ the crossbar array\nside); multi-bit output→\n↓ DAC;\n2. Multi-step chain (PWL-based)9\nPipeline of pointwise binary encoding→\noperators; breakpoint detection\n↓ →accessing\n3. Weighted slope/intercept\naccumulation; memory\n↓ →parameter\n4. Memory copy fetching→digital\nMAC→DAC\n☹ ☹  \nif one-shot? No No Yes\n(partially parallel (partially parallel)9 (completely\non GPUs) 1. memory-bound; parallel)\n1. memory- 2. massive 1. access-free\nbound;17 computational memory;\n2. high overhead of modules; 2. offloading-\ndata movement;18 3. intricated control free;\n3. significant CPU- flow (PWL-based 3. one-shot\nComputational GPU offloading scene); parallel VMM\nparallelism latency and energy 4. redundancy in and MAC\nconsumption;19 address (LUT-based process;\n4. high overhead of scene) or parameter 4. simple control\nscheduling and (PWL-based scene) mechanism\nsynchronization20,21 access (voltage-pulse\ndirect drive)\n☹ ☹  \n1. memory and 1. memory and 1. device count\ncomputation computation demand increases\ndemand grows demand grows linearly with\nsuperlinearly with superlinearly with computational\nthe number of the number of scale (one basis\nparameters; parameters function is\n2. exponentially implemented by a\nincreasing memory pair of GMCs)\nHardware copy latency;*\noverhead change 3. memory\nbandwidth\nbottleneck\namplifies with\nincreasing\ncomputational\nscale22\n☹ ☹  \nIn-situ training -- NO (hardwired) YES\n☹  \n* https://developer.nvidia.com/gdrcopy\nWe have included the response in Supplementary Note 1 of the latest revision of the manuscript. Additionally, Fig. R1 is presented as Fig. 2 in the latest main text, while Table R1 is shown as Supplementary Table 1 in the latest Supplementary Information.\n2. The experiment involving two GMC units in the revised manuscript only demonstrates the functional feasibility. However, it does not analyze the potential errors or scalability issues that may arise when integrating multiple units. As such, it is insufficient to convincingly support the practical feasibility and scalability of a full GMC array. Further experimental results and in-depth analysis are necessary to substantiate this claim.\nResponse 2-2: We appreciate the reviewer’s insightful comment regarding the practical feasibility and scalability of the multiple GMC integrations. We acknowledge that our experiment mainly demonstrates functional feasibility, while a deeper analysis of the potential errors or scalability issues arising when integrating a larger number of units has not yet been fully addressed. Considering that array-level performance ultimately determines whether such devices can support large-scale CIM architectures in real-world applications, a quantitative evaluation of integration scalability is indeed essential.\nAs shown in Fig. R2a, given the intrinsic self-rectifying characteristics of the GMC devices, we employ the read margin as the key metric to characterize the scalability of the GMC array23. The read margin reflects the ability of a memory array to accurately retrieve stored information under realistic conditions, including noise and sneak path currents. Therefore, it is a widely accepted and fundamental indicator for evaluating the scalability of self-rectifying memristive crossbar arrays.23 Additionally the read voltage scheme during array operation has a significant impact on the sneak path current. The V /2 bias scheme is employed for current readout in this analysis (V 1.7V).\nread read\nUnder this scheme, only the fully selected GMCs (with a read voltage of V , as read indicated by pink dots in Fig. R2a) will have current, while the partially selected (with a read voltage of V /2, as indicated by green dots in Fig. R2a) and unselected GMCs read (with a read voltage of 0, as indicated by blue dots in Fig. R2a) will have no current, effectively suppressing sneak-path currents.\nNotably, the read margin typically decreases with integrated array size, and a margin below 10% is generally considered the practical scalability limit.24 Experimentally, we evaluate the read margin using a single bit-line pull-up strategy, which is defined by the following relationships:25\nV  1 1 \nRead Margin   R    (R1)\nV pu R R R R \npu  1 pu 2 pu \n 2R R\nR  pos  neg\n\nsneak n1 n12\n\n\n  R \nR  R  sneak  (R2)\n  LRS sneak \n\n R \nR  R  sneak \n 2 HRS R R\n  HRS sneak \nHerein, V refers to the difference between the input voltages of the selected cell at low-resistance state (LRS) and high-resistance state (HRS). V denotes the pull-up pu voltage applied to the selected BL, which is represented by V in this experiment. read R is the pull-up resistance, and R is the resistance along the sneak paths. In pu sneak addition, R and R refer to the resistance of a cell that is half selected in this pos neg experiment as well as a cell that is not selected at all, respectively. n represents the number of SLs or BLs in a whole crossbar array. As illustrated in Fig. R2b, with read margin as the sole parameter for evaluating the scalability of the proposed GMC array, the array in this work can be scaled up to approximately 59×59 (3.48 Kb) operated at a read voltage of 1.7 V. This indicates that the GMC units proposed in this work can reliably perform read operations, demonstrating feasibility at the array level.\nFurthermore, the scalability of the GMC array could be further improved by increasing the self-rectifying ratio, for example, by increasing the read voltage or replacing other self-rectifying memristors with higher rectification ratios.23,24 It should be noted that the main goal of this work is to propose a potential hardware implementation of KAN, and future efforts will focus on further advancing the practical realization of hardware KAN.\nFig. R2 | Analysis of the array scalability. a Self-rectifying I-V characteristics of GMCs. b Scalability analysis based on the proposed GMCs with over 3.48 kb scale.\nWe have included the response in the latest Supplementary Note 3 and referenced it in the ‘Circuit design for GMC-based implementation of KANs’ section of the ‘Results’ in the latest main text. Correspondingly, Fig. R2 is presented as Supplementary Fig. 8.\n3. The response includes an error modeling of device variability and analyzes its impact on task performance. However, it remains unclear whether the modeling aligns with actual physical behavior. To justify the validity of this approach, experimental validation using measured device variability is necessary.\nResponse 2-3: We are grateful for the reviewer’s comment on the consistency between the previously adopted error modeling and the actual physical behavior of the GMCs, which is crucial for ensuring the reliability of the proposed physical G-KAN. The primary sources of errors in GMC units arise from device-to-device (D2D) variations (Fig. R3a) and cycle-to-cycle (C2C) variations within the same device (Fig. R3b). D2D variations are mainly caused by fluctuations in material defect density and channel area due to fabrication limitations26,27, whereas C2C variations result from external random perturbations. Both types of errors manifest as non-idealities and inconsistencies in the quasi-Gaussian output of the GMC units.\nTo investigate the causes and nature of the random perturbations in the Gaussian-like transfer characteristic curve, a statistical analysis is required. Given that the Gaussian-like function is described by characteristic parameters such as the peak value,  and  , error analysis can be conducted on the perturbations introduced in these   parameters. Mathematically, these parameters can be defined as a class of variables that satisfy the following equation:\nP*  P(1KZ) (R3)\nwhere the P* denotes the experimentally measured value, Z is a random variable following a standard normal distribution (i.e., Z ~ N (0,1)), and K is defined as the characteristic perturbation constant.28 As an illustration, Fig. R3c shows the effect when K 0.1.\nBased on the above premise, to validate that the utilization of the coefficient of variation (CV) to quantify the parameter perturbation behavior is reasonable, it is sufficient to demonstrate that the CV is a variable explicitly related to the coefficient K in Eq. (R3). Through rigorous mathematical derivation, we have proved that the previously adopted error modeling based on the coefficient of variation (CV) is in fact equivalent to the above perturbation model. The detailed proof process is presented as follows.\nLet P be the intrinsic value of a certain characteristic parameter, and let P i ( i1,2,3, ) denote the measured value (random variable) of P at the i-th measurement. According to the perturbation model:\nP  P(1KZ)，Z ~ N (0,1) (R4)\ni\nDenote by E(P) and Var(P) the exception and variance of P, respectively. By exploiting the properties of the normal distribution, the following derivation is obtained:\nE(P) E(P)KE(Z) P (R5)\ni\nVar(P) P2Var(1KZ) P2\n\nE1KZ2E1KZ\n2\n(R6)\ni    \nSince\nE1KZ2  E  12KZ K2Z2 1K2E  Z2 1K2\n\nVar(Z)EZ\n2\n1K2\n   \n, and E1KZ1. Equation (R6) follows that,\nVarP K2P2 (R7)\ni\nFor the GMCs prepared in this work, P 0. Therefore,\nVarP\ni  K，(K 0) (R8)\nE(P)\ni\nAccording to the definition of the CV—the ratio of the standard deviation to the exception—the constant K is equivalent to CV. In summary, the previous error modeling based on CV is equivalent to the characterization perturbation model of GMCs. In combination with the laws of large numbers29, the intrinsic value\n1 n\nPE(P) P . Hence, this equivalence establishes a direct theoretical link i n i\ni1\nbetween the error modeling framework and the statistical description of experimentally observed device variability. It is worth noting that, in the previously revised manuscript, to ensure the rationality of the perturbation simulation, each device model in a G-KAN was independently assigned its own characterization perturbation random variables, and the outcome was obtained through forward propagation at the network level, thereby reflecting the cumulative effect of the perturbations.\nFig. R3 | Device variability. a The transfer characteristic curves with 8 different GMCs. b Test of the transfer characteristic curve for 1000 cycles of the same GMC unit, among which the wine red color represents the output of the 500th cycle. c Random perturbations considered on the modeled GMC curve to emulate the impact of device variability.\nWe have included the data in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text. Correspondingly, Fig. R3 is presented as Supplementary Fig. 5 and Supplementary Fig. 6.\n4. The revised manuscript states that the RMSE of G-KAN remains below 0.4 when the factor $q$ reaches 50. However, it is not evident what level of physical error this corresponds to in practice. Is such a quantization level sufficient in a real-world hardware scenario? A more detailed explanation is needed to substantiate the robustness of G-KAN under practical conditions.\nResponse 2-4: We sincerely thank the reviewer for raising this important comment regarding the physical significance of the factor q and correspondence to the error statistics in practical hardware scenarios.\nIn the previous version of the revised manuscript, q was introduced as a hypothetical scaling factor to magnify the intrinsic variability of the device by q -fold. This setting was applied to emulate the situation in which the intrinsic device variability is further amplified when the array operates under the influence of external noise sources. Specifically, the expression ‘ qC ’ refers to multiplying the CV of each characterization parameter. To avoid ambiguity, in the latest revised manuscript, we have clarified this description as “multiplying each intrinsic perturbation constant by q ”, which more clearly conveys the experimental details.\nRegarding whether a q -fold perturbation level is sufficient for real-world hardware, we refer to the study by Li et al30. In practice, in addition to the intrinsic device variability, array-level operation also suffers from perturbations introduced by peripheral circuits, such as sensing drift in the transimpedance amplifier (TIA).30 The standard deviation of such drift has been reported to be approximately 0.3, which is still far below the case of 50-fold intrinsic variability (corresponding to\nP* ~ N (P,2500(KP)2)). Notably, when q 50, the RMSE approximately reaches as high as 0.4. Although this represents a considerable error level for a 1D function regression task, it should be emphasized that such performance arises under extremely amplified perturbations—50 times the intrinsic device variation. The motivation for presenting this stress-test scenario was to benchmark against a M-MLP model with 15,250 weights (i.e., 152.5× larger than G-KAN with n 100). However, this M- c MLP exhibited an RMSE as high as 1.311 even under ideal conditions. Hence, such extreme test was previously adopted to demonstrate that G-KAN could achieve much lower error than M-MLP under ideal conditions, even when subjected to such an extremely adverse testing premise. In realistic settings, GMC arrays operate under normal device-to-device interactions, where the perturbation factor q is expected to be close to 1. Even when q2 —already far beyond the typical operational conditions—the RMSE increases only by 0.0168, demonstrating that the system maintains strong robustness under practical circumstances.\nFollowing the reasoning of Li et al.30, if the network maintains robust performance (measured by AI benchmark metrics) even under artificially magnified error conditions (e.g., q2 , which significantly exceeds the expected real-world variability), this strongly substantiates the reliability of the G-KAN in practical operation. Moreover, the underlying mechanism of neural network for classification is probabilistic decision-making, where the label with the highest probability is selected as the output.31 Under this principle, even if the predicted probabilities are affected by internal errors, the final classification outcome does not vary continuously as RMSE does in regression tasks, but instead exhibits a certain degree of tolerance. Consequently, classification accuracy is less sensitive to perturbations. As shown in Fig. R4, even when q5, the accuracy decreases by only 0.453%. Therefore, G-KAN demonstrates strong robustness in both regression and classification tasks.\nFig. R4 | Robustness evaluation of G-KAN. The left panel presents the evaluation on the function regression task, while the right panel shows the evaluation on the image classification task.\nWe have included the response in latest Supplementary Note 7 and 9 and referenced it in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text. Correspondingly, Fig. R4 is presented as Fig. 5g in the latest main text.\n5. The response mentions methods that allow the weighted coefficients of cells to be dynamically adjusted during training to compensate for effects such as current drift caused by device variations. However, these methods are designed primarily for conventional CNN or MLP architectures, which are fundamentally different from the proposed G-KAN. Whether such techniques are applicable to G-KAN requires further clarification.\nResponse 2-5: We sincerely appreciate the reviewer’s insightful comments and acknowledge that a more in-depth discussion of this concern will help confirm the feasibility of the method within the architecture proposed in this work. Specifically, the method refers to in-situ training in neuromorphic computing architectures.30,32\nTherefore, we first clarify the working mechanism of in-situ training in well-established systems such as MLPs and CNNs, as well as the details of how this method overcome device non-idealities. On this basis, we then analyze whether in-situ training remains feasible for G-KAN by considering the electrical write/erase mechanism of GMCs.\nIn-situ training is widely applied in various neuromorphic architectures that utilize memristors to store trainable parameters and operate on crossbar arrays. Examples include spiking neural networks (SNNs)33, reservoir computing34-36, long short-term memory (LSTM) networks37,38, and even hardware implementations of fast Fourier transforms (FFT)39 and discrete Fourier transforms (DFT)40. In these architectures, the trainable parameters are fundamentally stored in the conductance states of memristors, and the training process is accomplished by modulating these conductance values.41\nUpon analyzing the GMC structure, which is composed of an anti-ambipolar transistor (AAT)42 in series with a memristor, the AAT solely provides the Gaussian-like transfer characteristics, while the memristor stores and modulate the trainable parameter of the Gaussian kernel. Similar to purely memristor-based networks, the in-situ training of G-KAN is also achieved by applying programming pulse sequences to adjust the memristor conductance. Moreover, the GMC is physically compatible with the crossbar array. Therefore, as a hardware-level optimization mechanism, in-situ training does not depend on specific network architectures, and the KAN-type networks constructed with GMCs also inherently inherit the capability of in-situ training to overcome hardware non-idealities.\nSecondly, regarding the role of in-situ training in overcoming current drift, further clarification is necessary. In fact, in-situ training not only effectively addresses current drift but also adaptively compensates for other various hardware non-idealities. Non-ideal factors such as current drift, write nonlinearity, device-to-device variation, wire resistance, and asymmetries in peripheral circuits typically affect the weight programming process.32 Moreover, in-situ training directly performs computation at the location where the neural network parameters are stored. This allows in-situ training to capture and compensate for these unavoidable device defects in real-time.30\nSpecifically, in-situ training with backpropagation can adaptively adjust network parameters to minimize the impact of unavoidable hardware non-idealities without the need for any hardware prior knowledge. Therefore, in-situ training has the capability to automatically adjust weights and compensate for hardware defects.30 In deeper networks, the adaptive ability of in-situ training is particularly pronounced because the hidden neurons can minimize the impact of hardware defects on network performance.30 Experimental results from Li et al. have shown that in-situ training can effectively tolerate defects in other hardware components (e.g., transistors, peripheral circuits, and current sensing drift), further validating its robustness.30 Especially in large-scale arrays, where some devices may fail to respond due to manufacturing or usage defects, in-situ training can continue to update the effective units without significantly affecting the overall performance of the network. Even with 11% of devices being stuck and unresponsive, in-situ training maintains high performance, demonstrating its adaptive ability in the presence of hardware defects.30 In summary, in-situ training is not merely a solution to current drift specific to MLPs and CNNs, but rather a device- and circuit-level strategy which is broadly feasible to the hardware compatible with crossbar array integration. This method enables neuromorphic circuits to effectively overcome various hardware non-idealities, thereby enhancing the performance and robustness of neural networks in actual hardware environments.\nWe have already included the explanations regarding the error analysis in Supplementary Note 9 and referenced this content in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text.\nReviewer #3 (Remarks to the Author):\nThe authors have conducted additional experiments and simulations that partially address my initial concerns regarding device measurements. However, the circuit designs presented in this manuscript remain underdeveloped and are insufficient to support even a design-level demonstration of computing-in-memory (CIM) for Kolmogorov–Arnold Networks (KAN), let alone an implementation of CIM-based KAN. Several significant concerns remain, even after the revisions, and the manuscript does not meet the standards required for publication in Nature Communications.\nResponse: We sincerely appreciate the reviewer for providing valuable feedback on the shortcomings in the circuit design and result presentation in the previous manuscript. The original manuscript indeed oversimplified some of the schematic details, which compromised the technical rigor. In response, we have invited a professor with extensive expertise in memristor chip design and fabrication to join the discussion. Through in-depth collaboration and multiple rounds of revisions, we have comprehensively and carefully improved the manuscript to effectively address the issues raised in the reviewer’s comments. In detail, (1) we recognized that the initial circuit illustrations were adopted from overly simplified representations in several prior works10,43-45 and therefore lacked sufficient components; (2) we have now reconstructed the circuit schematics by referring to detailed circuit presentations in established neuromorphic computing literatures,10,30,46,47 and re-implemented the presentations on a professional electronic simulation platform to ensure accuracy and credibility; and (3) we decomposed the previously identified design limitations into distinct sub-problems and proposed targeted solutions for each. Collectively, these efforts elevate professional circuit design which is adequate to support a computing-in-memory (CIM) demonstration for KANs.\n1. The circuit designs presented in this manuscript are difficult to understand and appear unrealistic, which significantly undermines the authors’ claim of implementing KAN using a CIM approach. The poor quality of the circuit design raises serious concerns about the credibility of the simulation results. Below are several fundamental questions that support this assessment:\nResponse 3-1:\n1) What do the triangle symbols represent in inputs and outputs of Fig. 3a? What are their functions?\nWe appreciate the reviewer’s attention to Fig. 3a. The triangle symbols were originally used as a simplified representation of differential operational amplifier stages, omitting the power supply pins and feedback paths. This simplification, which follows the convention adopted in some reports about memristive neural network, was intended to maintain clarity within the limited schematic space.10,45,48\nHowever, we acknowledge that such a representation may be easily confused with the comparator symbol commonly used in analog electronics. In response to the reviewer’s comment, we have revised the figure to align with the standard depiction of output stages in memristive crossbar arrays. Specifically, the column currents from the array are first converted into voltage signals via a transimpedance amplifier (TIA), which enables subsequent operations (Fig. R5). Since the non-inverting terminal is grounded, the virtual short property of the negative-feedback operational amplifier ensures that the potential of the entire SL column is maintained at zero.10 Then, the amplified differential signals can then be fed into a dedicated differential amplifier stage or a specialized processor for further processing. The specifics of these peripheral circuits are provided in the figure captions for clarity, as the ensuing discussion will focus on the core GMC array architecture.\nFig. R5 | Transimpedance amplifier (TIA).\n2) What are the triangle symbols in Fig. 3b? Are they the same components as those in Fig. 3a?\nIn the Fig. 3b of original manuscript, the triangular symbols serve the same purpose as in the reviewer’s Question (1) – to simplify the representation in the block diagram. These symbols indicate differential operation, where “+” and “-” denote the non-inverting and inverting input terminals, respectively. To address the previous non-standard depiction, we have revised the figure and adopted the widely utilized TIA as the essential element at the MAC current output stage.\nWe sincerely apologize for the insufficient explanations and non-standard notations in our original submission, which may have caused confusion. Thank you again for pointing out these issues, which have helped us significantly improve the rigor and readability of the manuscript.\n3) Fig. 1c shows that a GMC consists of a Gaussian transistor and a memristor. However, in Fig. 3b, memristors appear as independent devices when forming differential pairs. How is this structural change justified? What are the characteristics of these independent memristor differential pairs?\nIn the Fig. 3b of original manuscript, the standalone memristors (highlighted in gray) correspond to the synaptic weights of the residual connections in the KAN. These connections serve as additional pathways in the network structure, enabling the direct transmission of input information (Fig. R6).49 In hardware implementation, these connections adopt exactly the same differential-pair encoding format for weights as conventional memristors. Through this design, the network can achieve more stable training and enhanced representational capability.49\nFig. R6 | Information transfer between nodes—residual connection (b(x)) can be added on the basis function combination (c f (x)).\ni i\ni\nThis response is presented in Supplementary Note 4 and referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the main text. Correspondingly, Fig. R6 is combined and presented as Supplementary Fig. 12.\n4) In Fig. 3c, what are the triangles with one terminal connected to x? Where are the other terminals connected?\nThe triangle symbols used here represent a simplified version of the differential circuit as well, which was originally intended to achieve a horizontal translation of the function. In the previously revised manuscript, the other terminals were connected to external bias sources used to implement function translation, as illustrated in Fig. R7. Since a horizontal translation of the function is equivalent to a biasing of the independent variable (x), we utilized this translation property in differential form to achieve the effect shown in Fig. R8. Specifically, the transfer characteristics of the GMC are mapped to a laterally translated Gaussian-like function (Fig. R8a), which requires establishing a bias relationship between the input (x) and the gate voltage (v ).\ng\nIn scenarios requiring higher fitting precision, such as the approximation of complex one-dimensional continuous functions, it is further necessary to contract the basis functions to form a finer grid (Fig. R8b). However, function contraction can be achieved simply by introducing a gain factor of k to the independent variable. In general, all these operations rely on addition/subtraction and subsequent amplification of x, which can be processed via operational circuits. Therefore, in the previously presented triangular symbols, the port other than the one connected to x represents the bias term. The other input of the triangle symbol corresponds to the applied bias term.\nIn the original manuscript, the bias terms were not explicitly labeled in the block diagram to avoid overcrowding the figure. Following the reviewer’s suggestion, we recognize that the original design may be confusing and lacks hardware-friendliness. As a result, we have re-evaluated and modified the configuration of the input terminals. Specifically, as shown in Fig. R8c, the contraction and translation of the Gaussian-like function essentially result from a fixed computational mode of linear encoding applied to the input variable. This operation can be realized simply by generating the gate voltages fed into the GMC array according to v k(xa)V , which is inherently a g  peripheral process. Consequently, we eliminated the translation module in the original design, which unnecessarily increases hardware complexity, thereby optimizing the circuit design. The reconstructed figure can be found in Fig. R11.\nFig. R7 | Schematic illustration of the computational scheme for handling translation and scaling operations with external bias.\nFig. R8 | Function translation and device mapping. a Function translation induced by variable bias. b Function contraction induced by gain on the independent variable for finer-grid adaption. c The input signal (x) is embedded in the voltage applied to the gate electrode, and the mapped functional relationship is established through the output\n  xa 2\ncharacteristics of the GMC: f(x)exp\n \n.\n    \nThis response is mentioned in the latest Supplementary Note 2 and referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the latest main text. Correspondingly, Fig. R8 is presented as Supplementary Fig. 10 in the latest Supplementary Information.\n5) In Supplementary Fig. 8, what is the 1T1R architecture, and is it the same as a GMC cell? The diagram includes numerous switches, what are their specific functions? Moreover, what is the difference between these switches and the MUXes, given that they are typically considered equivalent in circuit design?\nIn the Supplementary Fig. 8 of original manuscript, the specifically highlighted 1T1R structure represents the memristor differential pairs used for implementing the residual connection, distinguishing this design from the GMC configuration. In detail, in typical hardware implementations, a memristor-based crossbar array requires additional transistors to select specific rows or columns.10 This is because, in the absence of transistors, unintended operations may occur on unselected units within the two-dimensional arrays. Through the switching control of transistors, the 1T1R structure effectively prevents crosstalk between multiple memristor units, especially half-select interference. This is the main challenge in achieving high-precision tuning in passive integrated circuits.45\nIn addition, the multiple switches shown in Supplementary Fig. 8 of the original manuscript function similarly to MUXes. This representation is referred to previously reported studies.50 Specifically, these switches are utilized to select and connect different signal lines (VWL/VBL/VSL/GND) in various modes to alter the potential difference across the selected unit. For example, during feedforward progress, SLs are connected to GND, providing a zero-potential reference point. During backpropagation, if the selected unit requires a negative voltage, thence BLs are connected to GND while SLs are connected to VSL. The switching of WLs between VWL and GND are used to select the row and column of the target unit. Additionally, the MUXes shown in original Supplementary Fig. 8 are used to implement the ReLU activation function. In the original Simulink module, these MUXes were implemented using the ‘Switch’ blocks (Fig. R9).\nWe sincerely apologize that, in the original design, directly paralleling the memristor component connected through the operational amplifier with other GMCs is inappropriate. This is because that, the operational amplifier forces the output potential V to R i (where R is the feedback resistor and i is the current flowing out F F through the memristor), which contradicts the condition that the operational amplifier at the array’s total output enforces the SL column potential to be zero through the virtual short principle. Therefore, we correct the schematic, and the updated version is shown in Fig. R10. Specifically, since the memristor array and the GMC array adopt different electrical encoding schemes, they need to be allocated into two independent arrays. The corresponding output vectors from each array can then be summed to compute the residual-connected form of G-KAN, as illustrated in Fig. R10 and Fig. R11.\nFig. R9 | The ‘Switch’ block utilized in Simulink module to implement the ReLU function. When the ‘Input Signal’ is greater than zero, the block directly outputs the input; otherwise, this block outputs a ground signal (zero potential).\nFig. R10 | Hardware implementation of the G-KAN. a, d Topology of KAN. Unlike MLPs, each edge is not merely a simple synapse but can be expanded into an activation function represented by a combination of Gaussian-like basis functions (Gaussian-like kernels), as illustrated in d. b GMCs serve as the fundamental electrical units for implementing tunable Gaussian-like basis functions, and are compatible with crossbar array architectures to realize analog in-memory VMM and MAC operations. c Schematic of G-KAN. e Demonstration of function-level parallelism in a G-KAN during inference operations (m input nodes, p output nodes, with n basis functions between input-output node pair). f Basic performance evaluation of the G-KAN (with 100 basis functions), using a 1D function regression task as a representative example.\nFig. R11 | Schematic diagram of the extended G-KAN architecture with residual connections. a GMC array part. Each green block represents the combination of n c Gaussian-like basis functions expanded from an input variable (x ). b A 1T1R-standard integrated memristor array is employed to process the additional operations of the residual-connection part. c The GMC array and the b(x) array are directly superimposed element-wise along the output vector to generate the final output.\nIn the schematics above, the ‘Subtractor Configuration’ contains the peripheral circuits utilized to handle the differential operation of the output voltages, which can be implemented using an operational amplifier (op-amp) (Fig. R12). Specifically, two TIAs as a differential pair convert the current representing the MAC operation result on the SL column into voltage, and then perform the differential calculation through an op-amp. The electrical principles in Fig. R12 can be found in following description.\nFor the non-inverting terminal, according to the op-amp’s virtual open and KCL, the result follows that:\nV V V 0 V\n2    V  2 (R9)\nR R  R\n1 2 1 1\nR\nR\nV  1V\nV V V V 1 R o\n1    o V  2 (R10)\nR R  R\n1 2 1 1\nR\noperation: V  R 2V V .\no R 2 1\nThe response is presented in Supplementary Note 2 of the latest revised manuscript and is referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the main text. Correspondingly, Fig. R10 is presented as Fig. 4 in the main text, Fig. R11 as Supplementary Fig. 9, and Fig. R12 as Supplementary Fig. 11.\n6) In Supplementary Fig. 9, a ReLU function cannot be implemented with only a single analog switch. How is the comparison operation (i.e., determining whether x < 0 or x > 0) realized in the analog domain?\nThank you for your in-depth review and valuable comments on this detail. Indeed, it is not feasible to implement the rectification output of the ReLU function using only a single switch in the analog domain. The single switch symbol in the previous illustration was intended to facilitate the understanding of the basic function of a ReLU-like electronic switch. However, since this form lacks the ability to determine the polarity of the input voltage, a detailed demonstration of the ReLU activation function is provided here.\nFirstly, to provide a more intuitive comparison of the hardware implementation complexity between the SiLU and ReLU nonlinear activation functions, we present the complete circuit schematics of both the SiLU51 and ReLU designs (Fig. R13). Specifically, the construction of the SiLU circuit51 is relatively challenging, as this circuit involves an exponential circuit (highlighted in the orange box), an external constant current source (1 A), two operational amplifiers, and a division circuit. In particular, the exponential circuit additionally requires a constant current source supplying the reference current and two operational amplifiers.51 Under these conditions, configuring such a complex circuit merely to generate the output of a single SiLU(x) function is highly impractical for large-scale network integration.\nOn the other hand, the ReLU function ( ReLU(V)max{0,V} ) can be implemented through a combination of the feedback amplifiers and diodes to achieve analog-level transformation (Fig. R14a). This circuit has been validated through Simscape electrical simulations, and the ReLU operation is well-supported by the simulation result (Fig. R14b and c). This approach is designed to transmit the voltage in the ReLU form and effectively determine the polarity of the input signals.\nFig. R13 | Hardware implementation of SiLU and ReLU functions. a Graph of SiLU(x). b Graph of ReLU(x). c Schematic of SiLU circuit. d Schematic of ReLU circuit.\nFig. R14 | Rectifying linear unit (ReLU) circuit. a Circuit schematic. V and V i o represent the input and output voltages of the ReLU function circuit module, respectively. b Circuit built within the Simscape electrical simulation platform. For the configuration, V is swept from -1 V to 1 V using a controlled voltage source, and the i V is measured using a voltage sensor. c V -V characteristic curve, which is o o i consistent with the numerical simulation of ReLU.\nAdditionally, considering that the ReLU function at the input side processes the given analog signals rather than performing computations within the network, a simpler approach is to directly utilize a signal function generator (included in the input buffer50) to generate the required signals. However, this part pertains to the peripheral configuration for generating input signals, rather than the processing element (PE) chip52 responsible for processing within the neural network.53 Therefore, such peripheral configuration falls outside the scope of this study. The specific simplified approach to be used can be chosen based on the actual PE board design.\nThe response is mentioned in Supplementary Note 10 of the latest revised manuscript and is referenced in the 'Principle of MAC Operations in G-KANs' section of the 'Methods' in the main text. Correspondingly, Fig. R13 is presented as Supplementary Fig. 20, and Fig. R14 as Supplementary Fig. 21.\n7) Simulink is generally used for system-level simulations, and VHDL is designed for modeling digital circuits at the behavioral level. Since the proposed CIM framework targets fully analog circuits, the simulation results shown in Supplementary Fig. 10 are not representative of analog behavior and are therefore unconvincing.\nWe sincerely appreciate the reviewer’s critical insight regarding the appropriateness of simulation tools used in Supplementary Fig. 10 of the original manuscript. We acknowledge that the earlier description may have caused misunderstanding, and we regret any confusion this may have caused.\nTo clarify, the previously mentioned reference to ‘VHDL’ stemmed from the optional settings under ‘HDL Code Generation > Set Basic Options’ within Simulink. It was not our intention to suggest that VHDL was directly involved in the simulation or modeling process. The actual model presented in the previous Supplementary Fig. 10 was constructed entirely using the ‘Commonly Used Blocks’ library in Simulink. Notably, each GMC was encapsulated as a self-contained functional module, with input-output behavior designed to reflect experimentally measured I - V d g characteristics of the fabricated devices in this work.\nTo address the reviewer’s concern about analog-level validation, we have revised the simulation methodology in the current version. Specifically, we reconstructed the full array of 200 GMCs in the Simscape Electrical platform (‘Foundation Library > Electrical’) to ensure more rigorous physical-level modeling. As illustrated in Fig. R15a, a single GMC unit—composed of an AAT and a memristor in series—cannot be instantiated directly from standard Simscape library components. However, based on GMC’s characteristic behavior, each GMC branch can be accurately modeled as a voltage-controlled current source (VCCS). Subsequently, following Kirchoff’s current law (KCL), the current output from a parallel array of GMCs (Fig. R15b) equals the algebraic sum of all individual branch currents. This cumulative current inherently performs the MAC operation across all basis functions in the analog domain, fully capturing the kernel computation of the KAN architecture. The resulting current is then converted to an analog voltage via a transimpedance amplifier (TIA). Such a configuration utilizes the negative feedback of the operational amplifier to form a virtual ground, thereby clamping the source line voltage to a stable ground level and minimizing readout errors.10 Finally, the differential operation is performed by an op-amp (Fig. R15c). Notably, the entire forward computation process—covering input application, weighted current generation, voltage readout, and differential-pair subtraction—is completed entirely in the analog domain within the full array (Fig. R15d). In addition, Fig. R16 displays the oscilloscope waveform captured during the operation of this circuit.\nFig. R15 | GMC array constructed in the Simscape Electrical platform. a VCCS equivalent of the GMC branch and the parallel equivalent circuit of the GMC array. b Partial view of the crossbar circuit of GMCs. c TIAs used for voltage-mode output ( R 1 ), while the op-amp for differential operation with R I I  and 1 M m R 1 . Here, I and I represent the values of the GMC current peak, 2 M m respectively. d Demonstration of the GMC array with 100 basis functions (200 GMCs). Furthermore, the output voltages of a pair of TIAs are processed through an op-amp to II perform an amplified differential operation to produce the final output (V  ) o I I M m of the G-KAN’s network computation. The output waveform is then observed using a ‘Voltage Sensor’ and a ‘Scope’ block.\nFig. R16 | The oscilloscope waveform of the output voltage sweep for the circuit corresponding to Fig. R15. This measurement used a sampling period of 0.02 seconds, collecting a total of 5000 output signals via a voltage sensor. The horizontal axis represents time (in seconds), and the vertical axis represents voltage (in volts).\nIn summary, these enhancements not only strengthen the physical fidelity of the simulation but also more accurately reflect the analog behavior of the proposed CIM framework. We thank the reviewer again for this valuable suggestion, which has led to a significant improvement in the rigor and clarify of our work.\nThe response is mentioned in Supplementary Note 2 of the latest revised manuscript and is referenced in the 'Circuit Design for GMC-based Implementation of KANs' section of the 'Results' in the main text. Correspondingly, Fig. R15 is presented as Supplementary Fig. 13.\nResponse 3-2:\n(2.1) The claimed advantages of implementing KANs using GMC-based CIM are not supported by solid evidence. The algorithm-level benefits highlighted by the authors are inherent to the KAN architecture itself and are not specific to the proposed hardware implementation.\nWe sincerely thank the reviewer for the valuable insights into the integration advantages of KAN and GMCs. This issue is fundamental to the core intent to this research. We note that Reviewer 2 has independently addressed this central point, which further convinces us that providing a detailed explanation of this aspect is crucial to highlighting the value of our work. Therefore, we offer this comprehensive response to substantiate the key contributions of this research.\nAs Gaussian kernels (i.e., the simplified description of ‘Gaussian-like basis functions’) are the fundamental computational elements in KANs, the effectiveness of KAN’s hardware implementation largely depends on how efficiently the computation and training of these kernels can be realized through devices or circuits. Existing hardware architectures, including von Neumann and near-memory systems, encounter significant limitations both in executing Gaussian kernels and in performing training, which restricts the full potential of KANs. The proposed GMCs are introduced specifically to address the shortcomings that current devices and architectures cannot overcome (Fig. R1). To emphasize the transformative impact of GMC-based implementation on hardware KANs, the following content will provide real-world examples that illustrate why traditional hardware architectures are inadequate for KAN’s implementation, thereby highlighting the advantages of G-KANs.\n(1) Dilemmas of von Neumann architecture (corresponding to Dilemma 1-3 in Fig. R1b)\nIn von Neumann architectures, the physical separation between the processor and memory leads to the continuous transfer of data and instructions between them during computation due to the disparity between memory bandwidth and awaiting data.1 Moreover, memory access introduces significant time and energy overhead, with much of the energy being consumed during data transfer rather than computation (Dilemma 1 and 2).1,2 The graphics processing unit (GPU), a prime example of optimized computing design, is widely used due to its exceptional performance in general matrix multiplication (GEMM)3. GPUs excel in neural network computations, efficiently performing linear transformations with high computational density by utilizing regular operations and contiguous memory access4, while the central processing unit (CPU) merely initiates scheduling, minimizing offloading overhead.5 However, these capabilities are not fully realized in KAN’s computations. Using Gaussian kernels as basis functions, the inference of a KAN requires sequential operations such as squaring ( (xa)2 ), scaling (  (xa)2 ), exponential transformation ( exp() ), weighted multiplication ( c exp() ), and accumulation (  ). These operations cannot be directly handled by GEMM, necessitating frequent kernel launches during each feedforward pass, with each launch scheduled by the CPU, thus significantly increasing the CPU-GPU offloading overhead (Dilemma 3). Even more concerning, KAN’s more complex computational elements require more hardware resources and power than MLPs, even when the number of parameters is the same.2,6\n(2) Dilemmas of near-memory implementations (corresponding to Dilemma 4-6 in Fig. R1b)\nThe previous evidence highlights the incompatibility of KANs with the von Neumann architecture. As a result, it is essential to implement KANs on hardware platforms with greater computational and memory density. In this context, researchers have sought to overcome the limitations of the von Neumann architecture through near-memory computing.7 For KAN-related applications, typical approaches include lookup table (LUT)8 and piecewise linear (PWL)9 circuit designs. Although LUT-based circuits can output Gaussian kernels directly at the hardware level, this approach introduces considerable computational complexity and storage overhead. For instance, implementing a single Gaussian kernel requires 452 LUTs.8 When extended to network-level implementations, particularly in densely integrated architectures like KANs, the resulting operational costs become unsustainable (Dilemma 4).\nFurthermore, recent research has applied CMOS integration technology based on PWL approximation to model activation functions in KANs.9 However, this approach presents several fundamental limitations: First, the PWL function requires predefined breakpoints (X ), slopes (M ), and intercepts (Y ) for each segment (X  X  X ), n n n n n+1 which must be stored in external memory. Second, the hardware architecture must incorporate numerous comparators (COMPs) and sensing circuits to determine the segment corresponding to the input signal, retrieve the associated parameters (M and n Y ) from memory, and pass them to the MAC circuits to complete the linear computation. As such, even for simple operations, this method still incurs significant hardware resource overhead (Dilemma 5).\nAn overall assessment of both LUT-based and PWL-based strategies reveals that not only do they demand considerable hardware resources—such as multipliers (MPLs), adders (ADDs), and comparators (COMPs)—for executing Gaussian kernel computations, but also, due to their hardwired architecture, they are incapable of performing parameter updates (Dilemma 6). Although both strategies attempt to mitigate the von Neumann bottleneck, they ultimately fall short due to their inability to incorporate trainable characteristics into the neural networks.\nGiven these limitations in existing CMOS-based implementations, there has been a shift towards the exploration of dedicated KAN-type CIM architectures. Clearly, memristors alone are insufficient to perform in-memory computation for nonlinear functions like Gaussian kernels. The following section will specifically discuss how the GMCs and array design introduced in this work effectively address these challenges.\n(3) Solutions leveraging GMC-based implementation (corresponding to Solution 1-5 in Fig. R1b)\nThe transfer characteristics of GMCs enable the direct generation of stable, parameterized Gaussian kernels, effectively capturing the mathematical behavior of Gaussian-like functions within the analog domain. Additionally, by adjusting the memristor conductance via write voltages, the peak of the Gaussian kernel can be flexibly controlled, allowing electrical programming of the learnable coefficients. On the architectural side, the one-transistor-one-memristor structure of GMCs facilitates seamless integration into crossbar arrays.10 According to KCL, the output currents from all GMCs in the same column can be physically summed on the source line, directly performing the linear combination of Gaussian kernels in a KAN. Consequently, the GMC-based implementation enables the full computation from input to output to be completed within the analog domain (Solution 1).\nMoreover, the traditional dilemma in CMOS-based implementations (Dilemma 2) arises from the physical separation of processor and memory.1 The GMC-based solution fundamentally alters this model by adopting the CIM paradigm. The core advantage of this approach is that computation and data storage are synchronized at the same physical location, eliminating the need for frequent data transfers between memory and processing units. This removes the conflict between memory bandwidth and processing throughput, and concentrates energy consumption on computation (Solution 2). At the same time, the in-situ CIM operation mode completely avoids the offloading overhead intrinsic to the von Neumann architecture (Solution 3).\nTo address the hardware scaling challenge (Dilemma 4) faced by CMOS-based systems—where increasing the number of basis functions leads to a nonlinear explosion in hardware resource consumption—the GMCs introduced in this study provide a straightforward solution through linear scaling approach. Specifically, under the differential-pair encoding scheme, each Gaussian kernel requires only a fixed pair of GMCs. This ensures that hardware scaling grows linearly with the effectively prevents unmanageable resource consumption, keeping the hardware scale of a G-KAN predictable and scalable (Solution 4).\nEqually important, the GMC-based approach avoids the complex and segmented operations typical of near-memory computing solutions (Dilemma 5 and 6). Within GMC arrays, an input vector is loaded in parallel across all rows, enabling each cell to simultaneously perform in-situ Gaussian-like mapping and MAC operations. By utilizing the native physics of the crossbar array and KCL, the entire matrix transformation is executed in one step, eliminating the need for piecewise function evaluation, memory-based parameter retrieval, and data transfer. This one-step operation completely removes the timing and control overhead associated with multi-step processes in CMOS-based implementations, significantly reducing computational complexity (Solution 5).\nThe main dilemmas faced by the CMOS-based implementations, along with their corresponding solutions provided by the GMC-based approach, are visually summarized in Fig. R1. In addition, a comprehensive comparison of the key features of the reference objects is presented in Table R1.\nFig. R1 | Overview of KAN’s hardware implementation strategies. a Reference object and benchmark metrics for the hardware implementation of KAN. b The dilemmas encountered by the von Neumann and near-memory architectures in processing the computations of KAN, while the GMC-based implementation provides a reliable solution at the in-memory computing level. c The GMC ingeniously combines the Gaussian kernel provided by AAT with the parameterization capability of memristors, integrating the necessary physical foundation for the in-memory computing required by KAN.\nFurthermore, to systematically underscore the advantages of GMCs in implementing KAN and in representing the basis functions (i.e., Gaussian kernels) associated with each activation link, we provide a comparative analysis against alternative implementation routes along with their corresponding reference objects and benchmark metrics. Table R1 offers a comprehensive summary across multiple dimensions of comparison, as outlined below.\nTable R1 Comparison for implementing KAN across different benchmarks.\nReference objects Von Neumann Near-Memory GMC-based\nArchitecture Architecture Crossbar Array\n1. hardware 1. memory-bound; physically\ndependance: 2. Separation of in-device\nDSPs/GPUs/FFs/ parameterization generation\nRAMs/LUTs6,11-13; and kernel\n2. Muti-step computation;\npointwise operators 3. Non-adjustable\n(squaring→ functions\nParameterized multiplication→ (hardwired);\nGaussian kernel exp()→ 4. Reliance on a\nimplementation multiplication); large number of\n3. memory- computational\nbound;14,15 modules8,9\n4. frequent\nmemory\naccessing16\n☹ ☹  \nif one-shot? No No Yes\nComputing in NOT partial complete\nmemory\n☹ ☹  \nif one-shot? No No Yes\n1. Data loading and (LUT-based)8 analog MAC\nscheduling ADC→multi-bit implemented on\ninitialization (CPU input (address)→ the crossbar array\nside); multi-bit output→\n↓ DAC;\n2. Multi-step chain (PWL-based)9\nPipeline of pointwise binary encoding→\noperators; breakpoint detection\n↓ →accessing\n3. Weighted slope/intercept\naccumulation; memory\n↓ →parameter\n4. Memory copy fetching→digital\nMAC→DAC\n☹ ☹  \nif one-shot? No No Yes\n(partially parallel (partially parallel)9 (completely\non GPUs) 1. memory-bound; parallel)\n1. memory- 2. massive 1. access-free\nbound;17 computational memory;\n2. high overhead of modules; 2. offloading-\ndata movement;18 3. intricated control free;\n3. significant CPU- flow (PWL-based 3. one-shot\nComputational GPU offloading scene); parallel VMM\nparallelism latency and energy 4. redundancy in and MAC\nconsumption;19 address (LUT-based process;\n4. high overhead of scene) or parameter 4. simple control\nscheduling and (PWL-based scene) mechanism\nsynchronization20,21 access (voltage-pulse\ndirect drive)\n☹ ☹  \n1. memory and 1. memory and 1. device count\ncomputation computation demand increases\ndemand grows demand grows linearly with\nsuperlinearly with superlinearly with computational\nthe number of the number of scale (one basis\nparameters; parameters function is\n2. exponentially implemented by a\nincreasing memory pair of GMCs)\nHardware copy latency;*\noverhead change 3. memory\nbandwidth\nbottleneck\namplifies with\nincreasing\ncomputational\nscale22\n☹ ☹  \nNO (hardwired) YES\nIn-situ training --\n☹  \n* https://developer.nvidia.com/gdrcopy\nWe have included the response in Supplementary Note 1 of the latest revision of the manuscript. Additionally, Fig. R1 is presented as Fig. 2 in the latest main text, while Table R1 is shown as Supplementary Table 1 in the latest Supplementary Information.\n(2.2) At the hardware level, the claim of reduced device count compared to MLPs is based on an unfair comparison: the authors only consider the number of memristor devices required for KANs versus MLPs, while overlooking the significantly higher circuit complexity associated with implementing KANs using GMCs. This undermines the validity of the claimed hardware efficiency.\nThanks for the reviewer’s critical observation. We have discussed about the reviewer’s comment regarding the comparison of device counts. Since a complete hardware system involves numerous components, and the peripheral design methodologies of MLPs and KANs differ in ways that make their device counts hard to quantify directly, a simple comparison based solely on memory devices would be unfair. We sincerely appreciate the reviewer for highlighting this critical point, and we have accordingly removed this experiment from the manuscript to ensure the overall rigor of this work.\nReference\nREVIEWER COMMENTS\nReviewer #2 (Remarks to the Author):\nI appreciate the authors' comprehensive responses, which have satisfactorily addressed all my previous concerns. Therefore, I recommend the manuscript for publication.\nWe sincerely appreciate your recognition of this research and the revisions. The critical comments you previously provided played a key role in refining the logic and enhancing the rigor of this paper. We are very pleased that the revisions have met your approval, and we deeply appreciate the time and effort you dedicated to the entire review process!\nReviewer #3 (Remarks to the Author):\nThe authors have thoroughly revised both the manuscript and the supplementary information, addressing most of my previous concerns regarding peripheral circuit designs. While the manuscript has improved in technical details, I still have concerns about the presented comparisons and several major claims. As I understand it, the primary contributions of this work are the fabrication and characterization of the GMC cell, along with circuit design and simulation demonstrating the feasibility of using the GMC cell for hardware implementation of KAN.\nResponse:\nWe appreciate your recognition of the revisions made to the proposed circuit design. Under your guidance, we have addressed key weakness in the previous version, thereby significantly enhancing the scientific rigor of this research. Meanwhile, we fully understand the reviewer’s cautious stance on the current technical details and main conclusions. In accordance with your suggestions, we have further revised the manuscript and included analysis of relevant hardware benchmark metrics to more robustly support the conclusions of this study regarding hardware advantages.\n1. The authors claim that the GMC-based KAN exhibits “strong learning capabilities” and “excellent continual learning capability.” These properties are inherent to the KAN architecture and would be expected regardless of whether the GMC cell is used. I therefore recommend that the authors clearly distinguish algorithmic capabilities from device-level contributions. In particular, the manuscript should emphasize the advantages introduced by the GMC cell, such as improved energy efficiency and computational speed enabled by in-memory computing, rather than implying that these learning capabilities originate from the GMC cells.\nResponse to 3-1:\nWe appreciate your constructive comments regarding the appropriateness of the conclusion statements. Following your suggestions, we have revised the relevant sections in the main text, including the Abstract, Introduction, Results, Discussion, as well as related statements in Supplementary Information (marked in red). These revisions aim to clearly state that the simulation results of the architecture proposed in this work is intended to validate the inheritance to KAN’s advantages (which is the prerequisite for the system’s feasibility), rather than relying on GMCs themselves to achieve these algorithmic advantages. In addition, the revised phrasing aims to avoid any overclaimed expressions regarding the contributions of this study. Furthermore, regarding the parallel computing advantages and energy efficiency improvements brought by the computing-in-memory architecture, we have provided a detailed explanation and quantitative study in the response to next question.\n2. The performance comparison between G-KAN and M-MLP in Fig. 5 is not directly relevant to the main contributions of the work. As I understand it, a comparison between KAN and MLP would yield similar trends, since the observed performance differences are attributable to the underlying network architectures rather than the use of the GMC cell. Therefore, the advantages shown in Fig. 5 do not arise from the proposed device or circuit designs. Instead, I would expect quantitative comparisons that directly demonstrate the benefits of the GMC-based in-memory computing architecture, such as improvements in energy efficiency and computational throughput, compared to a CMOS-based implementation, in order to substantiate the advantages presented in Fig. 2.\nResponse to 3-2:\nWe sincerely appreciate the reviewer’s insightful comments. The issue regarding the comparison of performance between G-KAN and M-MLP in Figure 5 is crucial for enhancing the rigor and clarity of the contribution in this paper.\nFirst, we fully understand the reviewer’s concern. The performance differences between software-level algorithms (KAN and MLP) are supported by related studies. The reviewer’s comments highlighted that the original phrasing might have led to a misinterpretation of Figure 5, suggesting it demonstrated \"AI performance advantages brought by GMCs.\" We have revised the manuscript (marked in red) to clarify that the comparison aims to verify the hardware platform's ability to preserve algorithmic advantages, shifting the focus to the core contribution—performance benefits of the GMC-based in-memory computing architecture.\nNext, in accordance with the reviewer’s suggestion, we conducted the study on the energy efficiency of the GMC-based architecture.1-5 Specifically, we compared the GMC-based system with two recently launched NVIDIA graphics processing units (GPUs).\nThe experiment was conducted on a predefined scale of the KAN [784,100,10] (grid size = 4), combining the corresponding GMC array and peripheral circuits. The inference latency was set to 300 ns, and the average power consumption of each GMC device was measured to be 16.6345 nW. The total system energy consumption consists of the energy of the array (E ) and that of the peripheral circuits (E ), with the array perip latter primarily driven by neurons using the differential-pair mechanism, each output neuron equipped with three high-bandwidth and low-power operation amplifiers6,7. The specific formulas for energy consumption calculation are as follows:\nn 7841001001042635200 (R1)\ndevice\nn 100103330 (R2)\nopa\nE 63520016.6345nW300ns=3.17nJ (R3)\narray\nE 3300.34mW300ns33.66nJ (R4)\nperip\nE  E E 36.83nJ (R5)\ntotal array perip\nHere, n represents the total number of devices in the GMC array, and n device opa denotes the total number of operational amplifiers used to implement the neurons.\nMoreover, according to the definition of energy efficiency1-3,7, the computational workload must first be quantified. Since the GMC array performs the parameterized\n  x 2\nGaussian transformation and accumulation (Aexp\n \n) operation in one\n    \nstep, such the operations need to be equated to the corresponding number of operations\n  x 2\nin CMOS architectures. In computer electronics, the operation Aexp   \n    \nx  x 2  x 2   x 2\nis executed step by step: x→ →   →   →exp   \n           \n  x 2   x 2\n→ Aexp    → Aexp    . Among these steps, the\n         \ntranscendental function exp in double precision calculations involves 29 operations in floating-point architectures based on the reduction-approximation-  x 2\nreconstruction principle.8 Therefore, the Aexp    operation in\n    \ncomputer hardware is equivalent to 35 operations in total. Based on this, the energy efficiency of the GMC-based system can be calculated as follows:\n63520035operations\nEE  603.64TOPS/W (R6)\n36.83nJ\nTable R1 presents the comparison results of energy efficiency, where the energy efficiency of the GPU is calculated based on the ratio of its peak throughput to thermal design power (TDP)7.\nTable R1 Comparison of hardware energy efficiency\nEnergy Efficiency\nArchitecture\n(TOPS/W)\nRTX PRO 2000 Blackwell *1 7.79\nRTX 2000 Ada Generation *2 2.74\nThis work 603.64\n*1: https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-2000/workstation-datasheet-blackwell-rtx-pro-2000-nvidia-us-4016661.pdf\n*2: https://www.nvidia.com/en-us/products/workstations/rtx-2000/\nThe CIM architecture and the ability to execute one-shot transcendental functions by GMCs provide the GMC-based system with parallel computation and low power consumption, which contributes to the high energy efficiency demonstrated in Table R1.\nIn addition, the comparison of hardware benchmark metrics has been submitted with the Supplementary Note in the revised Supplementary Information.\nWe would like to once again express our sincere gratitude to the reviewer for the valuable comments and detailed guidance provided during this round of review. The reviewer’s suggestions have significantly enhanced the rigor and clarity of the contribution in this paper, and the related revisions have effectively improved the final presentation of the manuscript.\n3. The manuscript primarily focuses on single-device-level experiments and circuit-level design and simulations. I therefore suggest that the authors avoid using the term “implementation” in the title and clearly clarify in the main text that the proposed G-KAN has not been “implemented” at the system level to prevent overclaim of the experimental scope and ensure that the statements accurately reflect the demonstrated results.\nResponse to 3-3:\nWe sincerely thank the reviewer for this insightful suggestion. We completely agree with your concern and have revised the title accordingly. Specifically, we have replaced “Implementation” with “Architecture,” resulting in the updated title: “Computing-in-Memory Architecture for Kolmogorov–Arnold Networks Based on Tunable Gaussian-Like Memory Cells”.\nMoreover, in both the main text and Supplementary Information, we have revised certain statements (marked in red), removing the expression that could lead to misinterpretation or over-interpretation, in order to ensure the rigor of the content and present the research more objectively. Thank you again for helping us present our work with appropriate precision.\nReferences\nREVIEWER COMMENTS\nReviewer #3 (Remarks to the Author):\nThe authors have addressed my previous concerns. One additional comment is that the authors should clearly state that the energy-efficiency estimation added in the revised manuscript is based on idealized assumptions, as the analysis considers only the G-KAN implementation, whereas the GPUs are general-purpose computing platforms.\nResponse:\nWe are very happy to hear that you acknowledge our previous revision as effectively addressing your concerns, which also means that we have successfully refined an important detail in this study. Meanwhile, regarding your suggestion for additional clarification, we fully agree and have added the corresponding statement in the latest version of the Supplementary Note, emphasizing that the energy efficiency results are estimated based on idealized assumptions. Once again, we sincerely appreciate your valuable guidance and contribution in this work!"}, {"round": 3, "reviewer_comments": {"reviewer_3": "The authors have addressed my previous concerns. One additional comment is that the authors should clearly state that the energy-efficiency estimation added in the revised manuscript is based on idealized assumptions, as the analysis considers only the G-KAN implementation, whereas the GPUs are general-purpose computing platforms."}, "author_response": "We are very happy to hear that you acknowledge our previous revision as effectively addressing your concerns, which also means that we have successfully refined an important detail in this study. Meanwhile, regarding your suggestion for additional clarification, we fully agree and have added the corresponding statement in the latest version of the Supplementary Note, emphasizing that the energy efficiency results are estimated based on idealized assumptions. Once again, we sincerely appreciate your valuable guidance and contribution in this work!"}]

Decision letter