Flexible monolithic 3D complementary circuits based on 2D semiconductor inks

Domain: chemistry
Published: 2025-12-22
Editorial outcome: major_revision

Abstract
Emerging flexible and wearable electronic systems require high-density, low-power circuits that can seamlessly integrate with soft substrates. Monolithic 3D (M3D) integration using 2D semiconductors offers a compelling route in fulfilling these requirements by enabling vertical stacking without compromising mechanical compliance. However, current M3D approaches utilizing 2D semiconductors often require high-temperature processing or transfer steps that hinder their scalability on flexible substrates. Herein, we present a low-temperature M3D integration strategy based on 2D semiconductor inks, which is enabled by a tailored anion-cation doping approach for precise carrier control in n- and p-type devices. Our methodology yields vertically assembled complementary metal-oxide-semiconductor circuits – including inverters, logic, and photosensor-integrated gates, and ring oscillators (ROs) – fabricated entirely at ≤150 °C. Notably, the inverters exhibit a voltage gain up to 462 at a supply voltage of 4 V, and the 5-stage ROs can operate at a maximum oscillation frequency of 13.5 kHz. Beyond their electrical performances, the circuits display robust mechanical stabilities, conforming to curved surfaces, and excellent skin compatibilities. This study reports a scalable, low-temperature platform for the fabrication of M3D electronics in wearable low-power neuromorphic computing systems and bio-integrated electronics.

Introduction
The rapid evolution of flexible and wearable electronics propels the development of miniaturized, highly integrated, energy-efficient systems for application in health monitoring, human-machine interfaces, and soft robotics. To satisfy the demands of these next-generation devices, realizing high-density multilayer/3D integration, minimal power consumption, and a robust mechanical durability under deformation is imperative. Monolithic 3D (M3D) integration using 2D materials has emerged as a promising alternative in realizing such dense 3D architectures. This is due to the ultrathin nature, superior levels of electrostatic control, and inherent scalability of 2D materials that enable the aggressive downscaling of the device dimensions.

Early demonstrations of M3D integration predominantly employed mechanical exfoliation and transfer techniques, which, although instrumental in establishing proof-of-concept stacked transistor architectures, encountered significant scalability limitations. Subsequent approaches utilizing chemical vapor deposition (CVD) combined with layer transfer improved the film uniformity, but they introduced complexities related to transfer-induced contamination and alignment inaccuracies. More recently, the direct CVD growth of 2D materials on prefabricated layers was advanced, offering an in-situ fabrication strategy that mitigated process-induced damage. Nevertheless, these conventional methods still require high processing temperatures, thus constraining their applicability to flexible substrates and underscoring the need for alternative, low-temperature fabrication strategies.

Solution-processed 2D material inks provide a scalable, cost-effective route in preparing large-area electronics by enabling the direct deposition of atomically thin semiconductors without complex transfer steps. Unlike vapor-phase techniques, solution processing supports low-temperature fabrication, flexible substrate integration, and precise control over the film thickness. Recent advances in 2D monolayer inks and nanoscale films enhanced their levels of charge transport while preserving their intrinsic properties. Moreover, establishing broad-area plane-to-plane van der Waals (vdWs) contacts within these films endow them with exceptional levels of mechanical flexibility and stretchability, rendering them particularly well-suited for flexible and wearable electronic applications. Nevertheless, precisely controlling the carrier concentration remains a significant challenge, particularly those of p-type transistor materials, such as WSe2, where robust solution-processable doping techniques are still lacking. Although various molecular approaches have been explored to modulate the carrier density of n-type MoS2 at low temperatures, the limited understanding of their underlying mechanisms hinders the reliable tuning of the electrical performance. While the M3D integration of 2D semiconductors has been demonstrated via CVD or exfoliation methods, a solution-processed M3D integration strategy has yet to be realized, highlighting the need for innovative fabrication approaches.

In this study, we establish a solution-phase anion-cation co-doping strategy to precisely modulate the carrier concentrations within solution-processed n-type MoS2 and p-type WSe2 thin-film transistors, which is a critical prerequisite for high-performance M3D complementary logic integration. The carriers within both materials are modulated via tailored dopant chemistry, as supported by density functional theory (DFT) calculations. Anions introduce acceptor-like states close to the valence band, enabling electron depletion or hole accumulation, whereas cations preferentially occupy defect sites, effectively suppressing hysteresis and enhancing stability. Thus, we demonstrate the solution-processed M3D integration of complementary 2D semiconductor circuits, including inverters, NOR and NAND gates, photosensor-in-logic circuits, and a ring oscillator (RO), entirely at ≤150 °C, without high-temperature or transfer steps. The M3D inverter realizes a voltage gain of 462 at 4 V, whereas the 5-stage RO reaches a maximum frequency of 13.5 kHz. The flexible circuits maintain stable performance under deformation, highlighting their suitability in wearable skin-compatible electronics.

Results
Fabrication of the flexible M3D system
Figure 1a presents the solution-processed semiconducting MoS2 and WSe2 inks, as confirmed by the ultraviolet–visible absorption spectrum (Supplementary Fig. 1), which enable the scalable fabrication of M3D complementary metal-oxide-semiconductor (CMOS) circuits by integrating the n- and p-type materials. Figure 1b illustrates the M3D CMOS structure, wherein the n-type MoS2 and p-type WSe2 transistors in the bottom and top tiers, respectively, are vertically stacked and separated by an interlayer dielectric (Supplementary Figs. 2 and 3 detail the fabrication process; see “Methods” section). Figure 1c demonstrates the wafer-scale M3D CMOS circuit, confirming the scalability of solution processing in high-density integration, and Fig. 1d shows the flexible M3D circuit on human skin, highlighting its mechanical robustness. The vdWs-bonded stacking enables strain relaxation, ensuring stability under bending. Compared to CVD-based growth or mechanical transfer approaches, solution processing offers a lower-temperature, more scalable, and transfer-free route toward flexible and large-area M3D integration. Successful M3D integration is confirmed using high-resolution transmission electron microscopy (Fig. 1e), revealing the vertically stacked p-type WSe2 and n-type MoS2 layers, each with a thickness of approximately 5 nm, formed via the self-assembly of solution-processed nanoflakes. The SU-8/Al2O3 interlayer dielectric provides electrical isolation while maintaining flexibility. Energy-dispersive X-ray spectroscopy elemental mapping (Fig. 1f) further verifies the presence of Mo, S, W, Se, Al, and Ni, confirming the layered structure and uniform material distributions with precise alignments.

Electrical properties of n-type MoS2 and p-type WSe2 transistors
Precise carrier concentration control is crucial in preparing stable, low-temperature, high-performance complementary logic circuits. We developed an in-solution strategy by incorporating anion-cation pairs directly into the 2D semiconductor inks prior to deposition. Conventional post-treatment methods involve doping after film formation and often restrict dopant interaction to only the exposed surface of the nanoflakes, requiring elevated temperatures or multistep processing. In contrast, our in-solution doping approach enables uniform carrier modulation across both the surface and buried layers of the nanoflakes during film formation. This incorporation not only yields superior device metrics, including reduced hysteresis and low subthreshold swing (SS), owing to the maximum treatment across the entire semiconductor film, but also enhances compatibility with ultra-flexible or wearable substrates and facilitates scalable large-area processing.

The electrical performances of the solution-processed transistors are characterized from the transfer characteristics of the n-type MoS2 and p-type WSe2 devices (Fig. 1g–i), respectively. The median SS for n-type MoS2 and p-type WSe2 were 133 mV/dec and 193 mV/dec, respectively. The MoS2 transistor achieved an on/off ratio of >108 and a minimum SS of 88 mV/dec at VDS = 1 V, while the WSe2 transistor exhibited an SS of 119 mV/dec at VDS = –1 V with an on/off ratio of >108. These values are comparable to those of CVD-grown 2D transistors (Supplementary Fig. 4 and Supplementary Table 1). Further improvements in the dielectric engineering and the film quality could reduce the SS toward the thermionic limit of 60 mV/dec, underscoring the potential of solution processing for high-performance logic applications. The consistent electrical characteristics across the wafer confirm the reproducibility and scalability of our low-temperature, solution-processed transistors (Supplementary Fig. 5).

Carrier concentration modulation
The proposed doping mechanism is schematically shown in Fig. 2a, b. Electron-withdrawing anions, such as bis(trifluoromethanesulfonyl)imide (TFSI−) or trifluoromethanesulfonate (OTf−), reduce the excess carriers within intrinsically highly doped n-type 2D materials or induce effective p-doping to increase their hole concentrations (nh). Meanwhile, small cations (e.g., H+ or Li+) may passivate the defect states and suppress trap-mediated hysteresis. To evaluate the individual roles of anions and cations in tuning transistor performance, we systematically investigated MoS2 transistors treated with various TFSI− and OTf− salts. Applying those anion species significantly alters the electron concentration (ne) from 1.8 × 1013 to 5 × 1012 cm−2 and enhances the on/off current ratio from 10 to >107 (Fig. 2c and Supplementary Fig. 6). Hence, electron-withdrawing anions are primarily responsible for carrier suppression. To isolate the role of cations, we further examined devices treated with Li⁺-containing salts. The transfer characteristics result in a marked reduction in hysteresis (10 mV), and an almost overlapping forward and reverse sweeps (Supplementary Figs. 7 and 8), which is comparable to those reported for MoS2 transistors fabricated using CVD or exfoliated flakes. This improvement is attributed to cation-induced surface passivation, which mitigates charge trapping. Therefore, decoupled anion-cation modulation enables the fabrication of high-quality, low-hysteresis n-type MoS2 transistors.

We further evaluated the p-doping behaviors of solution-processed WSe2 thin films to enable robust p-type transistor operation. As shown in Fig. 2d and Supplementary Fig. 9, treatment with the TFSI− and OTf− salts significantly increases the nh from 3 × 1011 to 8 × 1011 cm−2 and improves the on/off current ratio from 103 to >107. Hence, the anions are the dominant contributors to effective p-type doping. Beyond the carrier concentration tunability, the doped p-WSe2 and n-MoS2 transistors exhibit strong thermal stabilities, maintaining their electrical performances after annealing at 150 °C (Fig. 2e and Supplementary Fig. 10), and thus, they are compatible with downstream processes, such as the atomic layer deposition (ALD) of a dielectric.

Moreover, both the p-WSe2 and n-MoS2 transistors exhibit excellent air stability, showing minimal degradation after one month of ambient storage under controlled low humidity (relative humidity ≈ 5%, Supplementary Fig. 11), without requiring encapsulation. The observed air stability can be attributed to two key factors: the intrinsic oxygen inertness of dopants such as TFSI−, which remain unaffected even under aggressive oxidative conditions, and the buried dopant formed during film formation, where overlapping nanoflakes encapsulate a portion of these dopants beneath the surface, thereby sustaining doping efficacy and mitigating ambient degradation.

To elucidate the mechanism of doping within the solution-processed 2D semiconductor, we performed DFT calculations using TFSI as a representative anion alongside various cationic alkali dopants in MoS2 and WSe2 (Fig. 2f). Density of states (DOS) analysis indicates that TFSI induces doping by introducing molecular states close to the valence band edge, which serve as charge-accepting sites. This facilitates electron transfer from the 2D semiconductor to the acceptor levels of TFSI, effectively lowering the ne within MoS2 or enhancing the hole density within WSe2. On the other hand, in MoS2, hydrogen preferentially occupies sulfur vacancies within MoS2 and acts as an acceptor under S-poor conditions with excess electrons, while Li⁺, though a donor in interstitial form, passivating traps and reducing electron concentration (Supplementary Fig. 12a). Similarly, Na⁺ and K⁺ tend to form substitutional deep acceptors rather than interstitial donors under n-type conditions, further weakening the n-type behavior. In WSe2, hydrogen (from HTFSI and HOTf) forms interstitial defects, which have a limited doping efficiency due to the deep transition level, supporting p-type doping via anion (Fig. 2i). In contrast, Li⁺, Na⁺, and K⁺ act as shallow donors in the form of interstitials, partially compensating for anion-induced p-doping and causing a lower nh and on-state current (Supplementary Fig. 12b). These results confirm that tunable carrier modulation arises from the synergistic effects of anion-induced doping and cation-mediated defect passivation. Importantly, this molecular doping framework – based on tailored anion-cation combinations – can be generalized to a broad class of ionic dopants and 2D semiconductors.

Fabricated M3D complementary circuits
With the established control over the electrical performances of the solution-processed pMOS and nMOS transistors, we have constructed M3D logic functions on a rigid SiO2/Si substrate. For circuit fabrication, a 60 nm ALD-grown Al2O3 dielectric was employed on both rigid and flexible substrates to ensure low leakage current, mechanical robustness, and high uniformity during multistep stacking and peel-off processes, thereby preserving the dielectric against processing-induced damage. Figure 3a shows the M3D-stacked inverter fabricated using the solution-processed MoS2 (n-type, bottom) and WSe2 (p-type, top) thin films. The voltage transfer characteristics at different supply voltages (VDD, Fig. 3b) exhibit sharp transitions, switching with a voltage gain exceeding 462 at VDD = 4 V. Meanwhile, the inverter remains functional at an ultra-low VDD = 0.1 V, confirming its potential in ultra-low-power electronics. At VDD = 3 V, it realizes a noise margin of 90.3% (Supplementary Fig. 13), ensuring robust logic operation. The device operates with sub-nanowatt power consumption, with a static power of ~18.5 pW at VDD = 0.3 V corresponding to a normalized power density of ~18.5 fW/µm (Supplementary Fig. 14), which is comparable to state-of-the-art values. Such ultra-low-power operation is attributed to the steep subthreshold characteristics of the MoS2 and WSe2 transistors, enabling sharp transitions. Figure 3c benchmarks the voltage gain of our solution-processed M3D inverter against those of CVD-grown and exfoliated 2D inverters, indicating a comparable or superior performance, even at 0.1 V. Compared to those of the Si-on-insulator-MoS2 stacking inverter, our inverter realizes a higher gain, with the peak power consumption decreased almost 10-fold, underscoring its energy efficiency in low-power applications. Moreover, Supplementary Fig. 15 presents the voltage transfer characteristics of ~30 inverters, exhibiting an average gain exceeding 150 V/V and an average noise margin above 90%, highlighting their excellent uniformity and ensuring reliable circuit operation.

M3D integration enables the realization of multifunctional logic circuits, such as a NOR gate with an embedded photosensing capability (Fig. 3d). The optical image (left) and schematic (right) depict the vertically stacked MoS2/WSe2 CMOS structure, where the top-tier p-type transistor is exposed to light, enabling direct light-modulated logic operations. The input-output characteristics (Fig. 3e and Supplementary Fig. 16) confirm the NOR logic functionality, with distinct output voltage levels for all input combinations. Figure 3f shows the photosensor-in-logic operation, where the output voltage dynamically responds to on/off light cycles. When exposed to light, the top WSe2 transistor shifts its threshold voltage, altering the photoresponse and enabling light-controllable logic functions. The successful integration of logic and sensing within a single M3D circuit eliminates the need for separate photodetectors, reducing system complexity, which is particularly promising for compact optoelectronic applications. This photosensor-in-logic architecture provides a platform for reconfigurable and stimulus-selective logic arrays, with potential applications in neuromorphic vision. With further spectral tuning and heterostructure design, it may enable multi-channel optical logic photocomputing.

To further validate the potential of solution-processed M3D integration in dynamic logic applications, a 5-stage RO was fabricated (Fig. 3g). The optical image (top) and circuit diagram (bottom) display the vertically stacked structure. The output waveforms of the 5-stage ROs under different VDD values are presented in Fig. 3h, exhibiting stable oscillations with increasing frequency as VDD is increased. The oscillation frequency can be adjusted from 5.1 to 13.5 kHz as VDD increases from 5 to 12 V (Fig. 3i). The frequency increases with supply voltage before gradually saturating beyond ~12 V, which we attribute to intrinsic delays in the circuit. The limited oscillation frequency and high operation voltage primarily arise from a large delay per stage (τ), where the τ = Reff · Cload reflects the effective resistance (Reff) and total capacitive load (Cload). The large gate area of the transistors leads to high gate capacitance, while the gate–electrode overlap and the interlayer dielectric between stacked metal layers introduces significant parasitic capacitance both within and between tiers. Furthermore, the moderate mobility of solution-processed MoS2 and WSe2 could contribute to high Reff. These factors collectively limit switching speed, though future optimization in device geometry, dielectric design, and mobility could substantially improve frequency performance.

Flexible M3D integrated circuits
The mechanical adaptability of solution-processed M3D circuits leverages the vdWs interaction between the stacked 2D layers, enabling strain accommodation without compromising their performance. The bond-free interfaces within vdW thin films enable flexibility, stretchability, and structural integrity, rendering them ideal in bio-integrated electronics. Figure 4a (top) illustrates this vdWs-enabled deformation mechanism, where adjacent nanosheets slide to absorb the bending stress while maintaining charge transport across the vdWs contacts, ensuring a stable electrical performance, even under mechanical deformation. The optical images (bottom) show an M3D circuit conformally attached to human skin, demonstrating its ultrathin, flexible nature. The wrist exhibits similar bending and releasing motions, highlighting the ability to conform to dynamic surfaces without performance degradation.

The mechanical robustness of the solution-processed M3D inverter was demonstrated (Fig. 4b–d). Figure 4b shows the voltage transfer characteristics and voltage gain, with the maximum voltage gain reaching 61 at a VDD of 9 V. Figure 4c further shows the transfer characteristics under bending and release states with a bending radius of 9.5 mm, revealing minimal shifts in the threshold voltage, ensuring a consistent logic functionality. This result indicates that the device maintains its switching behavior and amplification capability under strain. Figure 4d assesses the long-term mechanical stability upon subjecting the inverter to 100 bending cycles, with the voltage transfer characteristics and voltage gain remaining nearly unchanged.

The mechanical robustness of flexible M3D logic circuits extends to the NOR and NAND gates and ROs. Figure 4e, f shows the stable input-output characteristics of the NOR and NAND gates, respectively, before and after bending, confirming reliable logic operation under strain. Figure 4g presents an optical image of a flexible M3D-stacked 3-stage RO with via-hole interconnections. Figure 4h demonstrates the stable output waveforms of the RO at different VDD values, with a maximum frequency of 6 kHz at 12 V (Supplementary Fig. 17). We evaluated five independent flexible 3-stage RO (15 M3D-stacked inverters), all exhibiting stable output with frequencies ranging from 1.31 kHz to 2.37 kHz (Supplementary Fig. 18), confirming the reproducibility and uniformity of the integrated logic devices. The flexible 3-stage RO retained stable output before and after bending (Supplementary Fig. 19), implying mechanical robustness and suitability for wearable applications. We note that flexible devices exhibit reduced inverter gain and oscillation frequency compared to their rigid counterparts, primarily due to mechanical challenges introduced during the peel-and-transfer process. Although a 60 nm ALD-grown Al2O3 layer is deposited on the 2 µm-thick parylene film to reduce surface roughness, the flexible stack remains prone to strain and deformation during transfer and thermal release (Supplementary Fig. 3 and Supplementary Fig. 20). Nevertheless, these results distinguish solution-processed flexible M3D circuits from previously reported circuits, establishing them as promising candidates in wearable and low-power electronics (Supplementary Table 2).

Methods
Ink preparation
Intercalation was conducted in a two-electrode system with tetraheptylammonium bromide (98%, Tokyo Chemical Industry, Tokyo, Japan) as the electrolyte. A MoS2 or WSe2 crystal was attached to a Cu plate with conductive Cu tape as the cathode, while a graphite rod served as the anode. As the electrolyte, tetraheptylammonium bromide was dissolved in acetonitrile at a concentration of 5 mg/mL. During intercalation, a voltage of approximately 15 V was applied to the cathode for 1 h. Subsequently, the expanded transition metal dichalcogenide (TMD) crystals were sonicated in 40 mL of a polyvinylpyrrolidone/dimethylformamide solution at a concentration of 8 mg/mL for 30 min. We employed iterative centrifugation cascades to remove the intercalated molecules and large flakes. The dispersion was centrifuged at 110, 440, and 990 × g for 30 min each (Centrifuge 1736R, LABOGENE), and the precipitates were discarded. The sediment was collected at a centrifugation speed of 2750 × g and dispersed in isopropyl alcohol (IPA). TFSI− or OTf−-based molecules were dissolved in IPA at a concentration of 10 mg/mL and mixed with the 2D semiconductor ink in a volumetric ratio of 1:10. The relative and absolute concentrations of the 2D semiconductor inks and TFSI may be modified and optimized for best results. WSe2 crystals for electrochemical intercalation were purchased from 2D Semiconductors, USA, and MoS2 crystals obtained from SPI Supplies were used as received.

Thin-film transistor fabrication
First, the SU-8 photoresist was prepared on an Al2O3 (18 nm)/Si substrate using conventional photolithography to form the desired patterns, and the Al2O3 dielectric layer was deposited via ALD. The treated 2D semiconductor inks were drop-cast onto the patterned photoresist to confine the formation of the 2D thin film. The substrate was covered with a Petri dish to slow the solvent evaporation and obtain a well-stacked thin film. After the solvent evaporated, the photoresist was removed with chloroform to yield highly aligned 2D TMD thin-film arrays. The substrate with the 2D thin-film arrays was then annealed on a hot plate in a N2-filled glovebox at 150 °C for 1 h. The Ni (40 nm) electrodes were thermally evaporated and patterned via photolithography. To realize a p-type WSe2 transistor with the optimal performance, the WSe2 device was further annealed in a HTFSI or HOTf solution at 120 °C for 15 min.

DFT calculations
We performed first-principles density functional theory calculations to investigate the doping properties of MoS2 and WSe2. We used the generalized gradient approximation parameterized by Perdew, Burke, and Ernzerhof and the projector-augmented wave method, implemented in the Vienna ab initio simulation package code. For a better description of the dispersion interaction, the DFT-D3 method with Becke-Johnson damping function was used. The correction scheme suggested by Freysoldt, Neugebauer, and Van de Walle was used for charged defect calculations. The plane waves were expanded up to 340 eV. The chemical potential of the Mo-rich and S-poor (W-poor and Se-rich) condition was determined by body-centered cubic (BCC) Mo (orthorhombic Se consisting of Se8 rings). The chemical potential of H, Li, Na, and K was obtained from the H2 molecule, BCC Li, BCC Na, and BCC K, respectively.

M3D-stacked CMOS fabrication
Fabricating the M3D-stacked CMOS structure begins with substrate preparation on a Si wafer coated with a sacrificial layer. The sacrificial layer used in flexible device fabrication was a 2 wt% aqueous solution of Micro-90, spin-coated at 1000 rpm for 60 s and baked at 90 °C for 5 min. A 2 μm-thick parylene film was subsequently deposited onto the sacrificial layer using a parylene coating system (OBT-PC300, Obang Technology) via standard chemical vapor deposition. A parylene film (2 μm) was used as the flexible substrate, followed by the ALD of Al2O3 (60 nm), which functioned as a buffering layer to enhance adhesion and structural stability. Fabricating the first-tier transistor followed a standard photolithography and deposition sequence. Ni was patterned as the gate electrode, and then Al2O3 was deposited as a dielectric. The n-type MoS2 active layer was defined via a lift-off process, and the Ni electrode contacts were formed on top to complete the transistor. To facilitate vertical integration, an SU-8 photoresist layer was spin-coated as the interlayer dielectric and crosslinked via ultraviolet exposure, followed by the ALD of an additional Al2O3 buffering layer to prepare for the deposition of the second tier. Fabricating the second-tier p-type transistor followed an identical process to that used in preparing the first-tier n-type transistor. Once both transistor layers were fabricated, thermal release tape was applied to the entire structure, and the wafer was immersed in deionized H2O to dissolve the sacrificial layer, enabling the flexible device to detach. The device, now attached to the tape, was transferred onto the target substrate and annealed on a hot plate to release the tape and complete integration. Vertical electrical interconnections between the two stacked layers were established by via-hole formation at each pixel using pulsed laser ablation, followed by filling with Ag ink to ensure interconnection. All fabrication processes were conducted at ≤150 °C, rendering the protocol compatible with flexible and stretchable substrates.

Characterizations
A sample for use in cross-sectional transmission electron microscopy was prepared using a focused ion beam (Helios Nanolab 650, FEI) and measured using a JEOL JEM-2100F (JEOL, Tokyo, Japan). The electrical characteristics of the transistors and M3D circuits were measured using a Keithley 4200 parameter analyzer in an N2-filled glovebox. ne and nh were extracted using n = (I_DS L)/(q W V_DS μ), where L is the channel length, W is the channel width, μ is the field-effect mobility, and q is the electron charge. The carrier concentration was calculated at VGS = 0 V.

Flexible demonstration experiments
All wearable demonstration procedures involving human participation complied with the institutional ethical guidelines of POSTECH (Pohang University of Science and Technology). A healthy adult volunteer (female, age 34) participated in the experiments shown in Figs. 1d and 4 to demonstrate the conformal adhesion and flexibility of the fabricated devices. The devices were only attached to the skin surface without any electrical stimulation, sensing, or physiological measurement, and thus posed no physical or psychological risk. The participant provided informed consent for participation.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The manuscript by Zou et al. reported interesting progress in solution-processed MoS2 and WSe2 transistors. A modified molecular doping strategy can now result in improved transistor behavior with smaller SS and gate voltage. Integrated logic gates in a three-dimensional vertically stacking structure were demonstrated on both rigid silicon and flexible plastic substrates. Overall, these results have shown clear advancements and may be of significance to the field of solution-processed 2D semiconductors and devices. And I have a few technical questions.\n1. Solution-processed MoS2 films with TFSI were previously reported in several publications. Could the authors elaborate more on why the MoS2 transistor in this work shows much better SS and hysteresis (Fig. 1g) than the relevant reports?\n2. In Fig. 1e, the Al2O3 gate dielectric thickness is about 60 nm. Although the gate capacitance is only half of the regular 30 nm-thick Al2O3, a very small gate voltage (-1 V to 5 V) can already turn the transistor on and off. It seems to be a great improvement over the previous results. Could the authors add more explanations on how such an improvement was realized? Also, 5 V is far smaller than the expected breakdown voltage of the 60 nm-thick Al2O3. If the gate voltage is further increased to +/-10 V or even +/-20 V, does the transistor's behavior change? Like mobility, off-current, and hysteresis.\n3. The WSe2 transistor exhibited excellent air stability in air for 6 days (Fig. 2g). However, previous reports on WSe2 usually suggest prominent current decay upon exposure to air for just several hours. What is the reason for the greatly enhanced air stability here (e.g., oxygen, water, etc.)?\n4. The mobility value is important for evaluating the quality of semiconductor. So, the authors are suggested to provide the mobility values for the MoS2 and WSe2 treated with various cations and anions (Fig. 2c,e)? It would help readers to better understand the effect of these molecular treatments.\n5. The authors are suggested to add more details in the experimental section so that other researchers in the field can better reproduce these results. For example, in the “Ink preparation”, what is the molar concentration of WSe2/IPA used for mixing with TFSI/IPA? Currently, there is only a volumetric ratio between these two materials. In “M3D-Stacked CMOS Fabrication”, what exactly is the “sacrificial layer” and how was it prepared? How was the parylene film deposited? Similarly, other experimental details require expanded explanations.", "reviewer_2": "Zou et al. developed a low-temperature M3D integration approach employing solution-processable MoS2 and WSe2 semiconductor inks to fabricate flexible devices. While the work is innovative, the data presented are somewhat lacking in persuasiveness. The following points should be addressed to strengthen the manuscript:\n1. Mobility is a critical device parameter. The authors should provide mobility measurements for a comprehensive evaluation of device performance.\n2. Only single FET device performance is reported, without large-area statistical analysis. Comparisons with literature based on a single device are not meaningful. The authors should fabricate and characterize a statistically significant number of devices (at least 400) to report key parameters such as mobility, on/off ratio, SS, and threshold voltage……\n3. Similarly, logic devices (e.g., inverters) should be evaluated with large-area statistics to enhance reliability.\n4. The input states (0,0) and (1,1) are not clearly explained in Figure 3f. The authors should specify how these inputs are applied.\n5. The photoresponse speed in Figure 3f appears relatively slow. Can this be improved? Additionally, the practical utility of the \"photosensor-in-logic\" concept should be discussed in greater depth.\n6. The reported oscillation frequency seems rather low. Can the device structure be optimized to achieve higher frequencies? Alternatively, the authors should explain the reasons for the limited frequency.\n7. No bending test data are provided for the flexible ring oscillator. This should be supplemented to demonstrate mechanical robustness.\n8. The 6-day stability measurement is insufficient. At least one month of data should be provided to convincingly assess air stability.\n9. The on/off ratio of only 10 for undoped MoS2 is unexpectedly low. Is this truly MoS2? TEM or other characterization techniques should be employed to verify the material identity.\n10. The use of Ni as both gate and source/drain electrodes for both MoS2 and WSe2 devices is questionable. Given the work function mismatch, this may degrade electrical performance. The authors should justify their choice or consider alternative electrodes.\n11. The flexible devices exhibit significantly poorer performance compared to rigid substrates. What is the underlying reason? Additionally, the thickness of the Al2O3 insulating layer in flexible devices is not specified—is it identical to that in rigid devices?\n12. The data processing in this work is somewhat inconsistent and lacks rigor. For example, WSe2 devices are tested for temperature and temporal stability, while MoS2 devices are not; MoS2 devices show hysteresis data, but WSe2 devices do not. These omissions should be addressed for consistency", "reviewer_3": "This work by Taoyu Zou et al. introduces a low-temperature, solution-processed monolithic 3D integration strategy for complementary circuits using solution-processed 2D semiconductor inks, including MoS2 (n-type) and WSe2 (p-type). By leveraging a tailored anion–cation co-doping strategy, the authors achieve carrier modulation and scalable integration of vertically stacked CMOS circuits on both rigid and flexible substrates, all processed at temperatures below 150 °C without requiring transfer steps. However, while the concept and integration strategy are compelling, the manuscript requires further revisions, particularly regarding the data quality and the consistency of performance reporting, before I can recommend publication.\nBelow are my detailed comments and suggestions for revision:\n1. Although the inverter is reported to operate at an ultra-low supply voltage of 0.1 V with a power consumption of ~8.8 pW, this claim is not well supported. From the output characteristics shown in the inset of Fig. 3b, the inverter’s transition point is around 0.2–0.3 V, indicating limited switching capability at 0.1 V. Moreover, neither the logic gates nor the 5-stage ring oscillators (5-ROs) are demonstrated to function at this voltage. Therefore, the claimed power consumption of 8.8 pW at 0.1 V appears unrealistic and should be reconsidered.\n2. For a meaningful comparison of power consumption with other works, the authors should report the device details (such as channel length and width). Power should be normalized accordingly and compared under equivalent operating conditions.\n3. The SS values appear to be extracted from a single data point rather than from the linear region of the log-scale current over several decades, as is standard in the field. The SS comparison in Fig. 1i is therefore unreliable. Please recalculate the SS using proper extraction methods.\n4. Although individual devices show promising performance, the manuscript lacks statistical data on device-to-device variability, circuit yield, or reproducibility across the integrated arrays. These metrics are essential to validate the scalability and robustness of the proposed 3D integration scheme.\n5. While SS and on/off ratios are emphasized for individual devices, other critical parameters, such as carrier mobility and current density normalized by device geometry, are not reported. These are essential for benchmarking and understanding the logic performance.\n6. The air stability of doped p-WSe2 devices is reported (6 days), but the environmental stability of n-type MoS2 devices is not mentioned. Please include comparable stability data for both types.\n7. The manuscript presents performance metrics from different devices under varied conditions, making it difficult to assess true device behavior. For instance, the inverter’s power consumption ~8.8 pW is reported at VDD = 0.1 V, while gain is highlighted at VDD = 4 V. Such mixing of device parameters is misleading and should be corrected.\n8. Inverters are shown to operate from 0.1 V to 4 V, but 5-ROs are only demonstrated at higher voltages (6–10 V) on rigid substrates. The manuscript should explain why no 5-ROs data are presented below 5 V, particularly given the high inverter performance at low VDD. Similarly, the difference in inverter/5-ROs behavior between rigid and flexible substrates (Figs. 3–4) needs clarification.\n9. The optical image in Fig. 3a is not sufficiently clear to illustrate the device structure. Please provide a cleaner schematic to assist reading.\n10. The Al2O3 layer above the Ni gate appears to exceed 50 nm in the cross-sectional TEM image (Fig. 1e), yet SS and gate voltages are surprisingly low (±5 V in Fig. 1g, h). Meanwhile, Fig. 2g and Supplementary Figs. 3–4 show gate voltages as high as 60 V. This discrepancy should be addressed. Please specify the actual dielectric thickness and clarify the variation in operating voltages across the figures.\nOverall Recommendation:\nWhile the manuscript introduces a significant advancement, the monolithic 3D integration of complementary circuits using solution-processed 2D semiconductor inks, the reported device performance is inconsistently presented and, at times, misleading. The main value of this work lies in the integration strategy, not in setting new benchmarks for device performance (far below the literature works by exfoliated or CVD ones). It is recommended that the manuscript be reorganized to emphasize this key contribution, tone down inflated performance claims, and include comprehensive, consistent performance data to support the conclusions."}, "author_response": "Response: We thank you for your positive assessment of our molecular‑doping approach and 3D‑stacked logic demonstrations on rigid and flexible substrates. We have addressed your technical questions and updated the manuscript and Supplementary Information accordingly.\n1. Solution-processed MoS2 films with TFSI were previously reported in several publications. Could the authors elaborate more on why the MoS2 transistor in this work shows much better SS and hysteresis (Fig. 1g) than the relevant reports?\nResponse R1Q1: Thank you for highlighting this point. In previous reports, a continuous thin film was first formed using TFSI-untreated MoS flakes. The resulting MoS film was then immersed in a TFSI solution, followed by rinsing and annealing. This subsequent surface‐only treatment mainly passivates traps at the topmost layers, leaving subsurface and inter-flake sites largely untreated. (Figure R1-1)\nBy contrast, our strategy directly adds TFSI to the MoS ink, allowing each flake to interact with the dispersed dopant in solution. After film formation, a mild anneal removes any residues and fully activates the passivation. This solution-based doping approach uniformly treats all flakes and interfaces, resulting in a much steeper subthreshold swing and virtually no hysteresis. (Figure R1-2)\nFigure R1-1. a. Conventional post-treatment methods involve doping after film formation. b, Electrical transfer characteristics of TFTs with a pristine MoS film, after TFSI treatment and after TFSI treatment and thermal annealing. (Ref: Nat Electron 6, 443–450 (2023).)\nFigure R1-2. Our approach mixes the dopant directly into the semiconductor ink, enabling interaction throughout the entire film.\nWe have included the following discussion in the revised manuscript:\nOur revision on Page 2:\n“Conventional post-treatment methods involve doping after film formation and often restrict dopant interaction to only the exposed surface of the nanoflakes, requiring elevated temperatures or multistep processing 27. In contrast, our in-solution doping approach enables uniform carrier modulation across both the surface and buried layers of the nanoflakes during film formation. This incorporation not only yields superior device metrics, including reduced hysteresis and low subthreshold swing (SS), owing to the maximum treatment across the entire semiconductor film, but also enhances compatibility with ultra-flexible or wearable substrates and facilitates scalable large-area processing.”\n2. In Fig. 1e, the Al2O3 gate dielectric thickness is about 60 nm. Although the gate capacitance is only half of the regular 30 nm-thick Al2O3, a very small gate voltage (-1 V to 5 V) can already turn the transistor on and off. It seems to be a great improvement over the previous results. Could the authors add more explanations on how such an improvement was realized? Also, 5 V is far smaller than the expected breakdown voltage of the 60 nm-thick Al2O3. If the gate voltage is further increased to +/-10 V or even +/-20 V, does the transistor's behavior change? Like mobility, off-current, and hysteresis.\nResponse R1Q2: We apologize for the confusion caused by the dielectric description. For circuit fabrication, we employed a 60 nm Al O dielectric deposited by ALD to ensure low leakage current, mechanical robustness, and high uniformity during multi-step stacking and peel-off processes. However, for detailed electrical performance studies, a thinner high-κ dielectric stack of Al O (18 nm) was used to achieve strong gate control, as we aimed to investigate the intrinsic device behavior and performance limits under optimized electrostatics. This dielectric provides a safe operating voltage below 5 V, with transfer characteristics confirming that off-current and hysteresis remain largely unchanged at different sweeping gate voltages. We have clarified the dielectric thickness in the revised manuscript to avoid confusion.\nThe observed improvement in switching behavior arises primarily from the unique in-ink doping strategy. Unlike conventional post-treatment methods, which only modify the top surface of deposited films, our approach mixes the dopant directly into the semiconductor ink, enabling molecular-level interaction throughout the entire film. As a result, both the surface and buried layers of the nanoflakes are effectively doped, leading to enhanced carrier modulation and superior electrostatic control. The combination of this uniform in-depth doping and optimized thin high-κ dielectric design allows us to probe the intrinsic performance limits of the solution-processed devices, thereby demonstrating reliable low-voltage operation and highlighting the potential of our M3D integration strategy.\nOur revision on Page 2:\n“Conventional post-treatment methods involve doping after film formation and often restrict dopant interaction to only the exposed surface of the nanoflakes, requiring elevated temperatures or multistep processing 27. In contrast, our in-solution doping approach enables uniform carrier modulation across both the surface and buried layers of the nanoflakes during film formation. This incorporation not only yields superior device metrics, including reduced hysteresis and low subthreshold swing (SS), owing to the maximum treatment across the entire semiconductor film, but also enhances compatibility with ultra-flexible or wearable substrates and facilitates scalable large-area processing.”\nFigure R1-3. Transfer characteristics of a solution-processed MoS transistor measured under different gate voltage range.\n3. The WSe2 transistor exhibited excellent air stability in air for 6 days (Fig. 2g). However, previous reports on WSe2 usually suggest prominent current decay upon exposure to air for just several hours. What is the reason for the greatly enhanced air stability here (e.g., oxygen, water, etc.)?\nResponse R1Q3: We thank you for highlighting the remarkable air stability of our p‑WSe 2 transistors. Unlike prior reports where unpassivated WSe films lose a significant fraction of their current within hours due to oxygen and moisture adsorption at defect sites, our devices maintain >95 % of their on‑current even after one month in ambient air (≤5 % RH). This enhanced stability arises from the three factors:\n1. Intrinsic oxygen stability of TFSI. The bis(trifluoromethanesulfonyl)imide anion features strong S–N and S–O bonds along with multiple C–F linkages, which confer remarkable chemical inertness to molecular oxygen and reactive oxygen species. For example, Zor et al. (DOI: 10.1039/D4EE02176B) demonstrated that TFSI- showed no measurable degradation when exposed to singlet oxygen under aggressive photochemical generation conditions. This means that the dopant layer remains intact and continues to block oxygen ingress without itself oxidizing or leaching out.\n2. Uniform in-ink TFSI passivation with buried dopants beneath nanoflakes. Unlike surface-only treatments, introducing dopants such as TFSI⁻ directly into the WSe ink 2 enables interaction with every flake in the solution. During film formation, overlapping flakes encapsulate a portion of these anions beneath the surface, providing subsurface doping that protects against ambient species.\nThis method allows p‑WSe transistors to operate stably in air for a month without any encapsulation.\nOur revision on Page 4:\n“The observed air stability can be attributed to two key factors: the intrinsic oxygen inertness of dopants such as TFSI⁻, which remain unaffected even under aggressive oxidative conditions40, and the buried dopant formed during film formation, where overlapping nanoflakes encapsulate a portion of these dopants beneath the surface, thereby sustaining doping efficacy and mitigating ambient degradation.”\n4. The mobility value is important for evaluating the quality of semiconductor. So, the authors are suggested to provide the mobility values for the MoS2 and WSe2 treated with various cations and anions (Fig. 2c,e)? It would help readers to better understand the effect of these molecular treatments.\nResponse R1Q4: We thank you for this comment and agree that field‑effect mobility (μ ) is FE important for evaluating device performance. We have extracted μ from the linear regime FE (V = 1 V) of our transfer curves for both MoS n‑FETs and WSe p‑FETs under each dopant DS 2 2 treatment. For MoS , the untreated devices exhibit electron μ ≈ 7 cm2 V-1 s-1, while HTFSI, 2 FE LiTFSI, NaTFSI, KTFSI, and HOTf treatments yield μ of ≈ 2.7, 1.5, 1.0, 1.3, and 3.1 cm2 V- FE 1 s-1, respectively (with LiOTf, NaOTf, and KOTf giving 0.25 to 0.48 cm2 V-1 s-1).\nFor WSe , untreated films show small hole μ (<0.001 cm2 V-1 s-1), whereas HTFSI and HOTf 2 FE treatments dramatically enhance mobility to 7.2 and 5.3 cm2 V-1 s-1, with LiTFSI, NaTFSI, and KTFSI giving intermediate values (0.5 to 0.3 cm² V⁻¹ s⁻¹). These results, now included in the Supplementary Information.\nFigure R1-4. Transfer characteristics of the solution-processed n-type MoS treated with and 2 without different TFSI⁻ and OTf⁻ based molecular dopants treatment.\nFigure R1-5. Transfer characteristics of the solution-processed p-type WSe treated with and 2 without different TFSI⁻ and OTf⁻ based molecular dopants treatment.\n5. The authors are suggested to add more details in the experimental section so that other researchers in the field can better reproduce these results. For example, in the “Ink preparation”, what is the molar concentration of WSe2/IPA used for mixing with TFSI/IPA? Currently, there is only a volumetric ratio between these two materials. In “M3D-Stacked CMOS Fabrication”, what exactly is the “sacrificial layer” and how was it prepared? How was the parylene film deposited? Similarly, other experimental details require expanded explanations.\nResponse R1Q5: We appreciate your suggestion to improve the clarity and reproducibility of our experimental procedures. We have now revised the Methods section to include additional details. Specifically, the concentration of MoS and WSe in the IPA-based mother ink was 2 2 adjusted to approximately 2 mg/mL before mixing with the dopant solution. The sacrificial layer used in flexible device fabrication was a 2 wt% aqueous solution of Micro-90, spin-coated at 1000 rpm for 60 s and baked at 90 °C for 5 minutes. A 2 μm-thick parylene film was subsequently deposited onto the sacrificial layer using a parylene coating system (OBT-PC300, Obang Technology) via standard chemical vapor deposition. Additional experimental details have also been added throughout the Methods section to facilitate reproducibility.\nResponse R2: We sincerely thank you for recognizing the innovation of our low-temperature M3D integration strategy using solution-processed MoS and WSe inks for flexible device 2 2 fabrication. We appreciate your constructive feedback and have carefully revised the manuscript to address the concerns raised. In particular, we have added additional data, clarified experimental procedures, and strengthened technical justifications to enhance the overall persuasiveness and reproducibility of the work. Detailed point-by-point responses are provided below.\n1. Mobility is a critical device parameter. The authors should provide mobility measurements for a comprehensive evaluation of device performance.\nResponse R2Q1: We thank you for this comment and agree that field‑effect mobility (μ ) is FE important for evaluating device performance. We have extracted μ from the linear regime FE (V = 1 V) of our transfer curves for both MoS n‑FETs and WSe p‑FETs under each dopant DS 2 2 treatment. For MoS , the untreated devices exhibit electron μ ≈ 7 cm2 V-1 s-1, while HTFSI, 2 FE LiTFSI, NaTFSI, KTFSI, and HOTf treatments yield μ of ≈ 2.7, 1.5, 1.0, 1.3, and 3.1 cm2 V- FE 1 s-1, respectively (with LiOTf, NaOTf, and KOTf giving 0.25 to 0.48 cm2 V-1 s-1).\nFor WSe , untreated films show small hole μ (<0.001 cm2 V-1 s-1), whereas HTFSI and HOTf 2 FE treatments dramatically enhance mobility to 7.2 and 5.3 cm2 V-1 s-1, with LiTFSI, NaTFSI, and KTFSI giving intermediate values (0.5 to 0.3 cm² V⁻¹ s⁻¹). These results, now included in the Supplementary Information.\nFigure R2-1. Transfer characteristics of the solution-processed n-type MoS treated with and 2 without different TFSI⁻ and OTf⁻ based molecular dopants treatment.\nFigure R2-2. Transfer characteristics of the solution-processed p-type WSe treated with and 2 without different TFSI⁻ and OTf⁻ based molecular dopants treatment.\n2. Only single FET device performance is reported, without large-area statistical analysis. Comparisons with literature based on a single device are not meaningful. The authors should fabricate and characterize a statistically significant number of devices (at least 400) to report key parameters such as mobility, on/off ratio, SS, and threshold voltage……\nResponse R2Q3: We appreciate this important suggestion. In the revised manuscript, we have fabricated and characterized a statistically significant number of devices, comprising 200 n-type MoS and 200 p-type WSe transistors. The electrical performance of these devices is 2 2 summarized in Fig. 1g–i.\nSpecifically, the statistical analysis shows that the median SS values are 133 mV/dec for MoS 2 and 193 mV/dec for WSe . The best-performing MoS transistor achieves a minimum SS of 88 2 2 mV/dec at V = 1 V, while the WSe transistor exhibits an SS of 119 mV/dec. These values DS 2 are comparable to those reported for CVD-grown 2D transistors. The histograms and scatter distributions provided in Fig. 1h–i further confirm the reproducibility and uniformity of the device performance across large-area statistics.\nOur revision on Page 3:\n“The electrical performances of the solution-processed transistors are characterized from the transfer characteristics of the 200 n-type MoS and 200 p-type WSe devices (Fig. 1g-i). 2 2 respectively. The median SS for n-type MoS and p-type WSe were 133 mV/dec and 193 mV/dec, 2 2 respectively. The MoS transistor achieved an on/off ratio of >108 and a minimum SS of 88 2 mV/dec at V = 1 V, while the WSe transistor exhibited an SS of 119 mV/dec at V = –1 V DS 2 DS with an on/off ratio of >108. These values are comparable to those of CVD-grown 2D transistors14,28-38 (Supplementary Fig. 4 and Supplementary Table 1). Further improvements in the dielectric engineering and the film quality could reduce the SS toward the thermionic limit of 60 mV/dec underscoring the potential of solution processing for high-performance logic applications.”\nFigure R2-2. g, Transfer characteristics of the solution-processed 200 n-type MoS and 200 p- 2 type WSe transistors with 18 nm Al O dielectric. Scatter plots of on/off current ratios and SS 2 2 3 values, and statistical histogram of SS for h, n-type MoS and i, p-type WSe transistors. 2 2\n3. Similarly, logic devices (e.g., inverters) should be evaluated with large-area statistics to enhance reliability.\nResponse R2Q3: We thank you for the valuable suggestion. To assess the reproducibility and statistical robustness of our logic devices, we fabricated and characterized five independent flexible 3-stage ring oscillators (ROs), corresponding to a total of 15 inverters. All ROs exhibit stable oscillations with frequencies ranging from 1.31 kHz to 2.37 kHz under the same operating conditions (V = 6 V). This narrow distribution demonstrates the consistent DD performance of our inverters and the reliability of the M3D integration process using solution-processed 2D semiconductors. These results strengthen the reproducibility of the logic components in our platform.\nOur revision on Page 6:\n“We evaluated five independent flexible 3-stage RO (15 M3D-stacked inverters), all exhibiting stable output with frequencies ranging from 1.31 kHz to 2.37 kHz (Supplementary Fig. 16), confirming the reproducibility and uniformity of the integrated logic devices.”\nRO-1 2.30 kHz\nRO-2 2.08 kHz\nt RO-3 u p 1.31 kHz t u O RO-4 1.70 kHz\nRO-5 2.37 kHz\n-4 -2 0 2 4 Time (ms)\nFigure R2-4. Output waveforms of five independent 3-stage ring oscillators. Each ring oscillator (RO-1 to RO-5) exhibits stable and periodic output with oscillation frequencies ranging from 1.31 kHz to 2.37 kHz, demonstrating device-to-device uniformity and reliable operation across multiple integrated circuits.\n4. The input states (0,0) and (1,1) are not clearly explained in Figure 3f. The authors should specify how these inputs are applied.\nResponse R2Q6: We appreciate your comment. In Figure 3f, the logic input states (0,0) and (1,1) are applied by setting both input terminals simultaneously to (0 V, 0 V) (logic low) or (0.3 V, 0.3 V) (logic high), respectively, using synchronized voltage sources. Additionally, a light source was applied uniformly to the device area during measurement for photoresponse testing under logic operation. This illumination modulates the output voltage under specific input conditions. We have clarified the input configuration and illumination conditions in the Figure 3f caption.\nOur revision in the Figure 3f caption:\n“Logic inputs (0,0) and (1,1) are applied as (0 V, 0 V) and (0.3 V, 0.3 V) using synchronized sources. A light source is used during measurement to evaluate photoresponse, which modulates the output under certain logic conditions.”\n5. The photoresponse speed in Figure 3f appears relatively slow. Can this be improved? Additionally, the practical utility of the \"photosensor-in-logic\" concept should be discussed in greater depth.\nResponse R2Q5: We thank you for highlighting the photoresponse speed shown in Fig. 3f. The observed response time is primarily limited by the intrinsic nature of the device structure, which operates as a phototransistor-based logic gate. In our design, the NOR gate consists of a vertically stacked WSe /MoS heterostructure, where the top WSe transistor exhibits 2 2 2 photoresponsivity. Unlike photodiodes or MSM photodetectors, phototransistors inherently exhibit longer response times due to carrier trapping and release processes during illumination cycles. This effect is further pronounced in solution-processed 2D semiconductors, where defect and trap states are more prevalent. As a result, the photoresponse time is on the order of seconds—consistent with previous reports such as ACS Nano 2023, 17, 530–538.\nAlthough this implementation is not optimized for speed, it successfully demonstrates an integrated photosensor-in-logic architecture, where optical signals directly modulate circuit-level logic without external photodetectors. We believe that this approach offers significant potential for compact, flexible, and multifunctional electronics. Future work will focus on enhancing response speed through interface passivation, material quality improvement, and device scaling.\nFor the practical utility of the “photosensor-in-logic” concept:\n1. Compact optoelectronic integration\nThe \"photosensor-in-logic\" concept demonstrated in our work represents a functionally compact integration of sensing and computation within the M3D circuit framework. Unlike conventional architectures that rely on separate photodetectors, amplifiers, and logic units, our approach allows optical stimuli to directly control logic states through intrinsic photosensing in WSe -based transistors. This eliminates the need for external signal transduction, power 2 consumption, and footprint. Thus, it offers scalability for high-density, flexible optoelectronic systems.\n2. System-level potential and emerging applications:\nFrom a system design perspective, such integration enables distributed, event-driven optical processing where computation is localized near the sensing interface. This is especially beneficial for applications in, such as, neuromorphic vision systems, where energy efficiency, physical density, and input-selective logic behavior are essential.\nFuture iterations may exploit heterojunction engineering and spectral selectivity to implement multi-channel optical logic and in-memory photocomputing, enabling more sophisticated sensory–logic functions. Moreover, the inherent scalability of solution-processed 2D materials and 3D stacking offers the potential to construct dense photosensor-in-logic arrays, enabling parallel optical processing and reconfigurable vision systems within ultrathin form factors.\nOur revision on Page 5:\n“The successful integration of logic and sensing within a single M3D circuit eliminates the need for separate photodetectors, reducing system complexity, which is particularly promising for compact optoelectronic applications. This photosensor-in-logic architecture provides a scalable platform for reconfigurable and stimulus-selective logic arrays, with potential applications in neuromorphic vision. With further spectral tuning and heterostructure design, it may enable multi-channel optical logic photocomputing.”\n6. The reported oscillation frequency seems rather low. Can the device structure be optimized to achieve higher frequencies? Alternatively, the authors should explain the reasons for the limited frequency.\nResponse R2Q6: We thank you for this important observation. The relatively low oscillation frequency primarily results from the large signal propagation delay per stage (𝜏) in our 5-stage ring oscillator. The frequency is approximately given by: f = (1/2⋅N⋅τ), where N=5 is the number of inverter stages, and 𝜏 = R ⋅C is determined by the effective resistance and total eff load capacitive load. Several aspects of our current device structure contribute to the large time constant:\nLarge gate capacitance arises from the wide and long gate area of transistors used to ensure high yield and fabrication uniformity. The resulting large gate area increases intrinsic capacitance and slows signal transitions.\nParasitic capacitance due to gate–electrode overlap introduces capacitive loading within tiers. Overlap between gate and source/drain electrodes, especially in interdigitated layouts, increases C and reduces switching speed. load\nVertical parasitic capacitance originates from the ~1.5 µm-thick conformal interlayer dielectric. This dielectric creates capacitive coupling between stacked metal layers, particularly between bottom-tier source/drain and top-tier gate electrodes, further loading inverter outputs.\nHigh effective resistance, mainly from the moderate mobility of solution-processed MoS and 2 WSe , increases R and delays signal propagation. 2 eff\nWhile frequency optimization was not the primary focus of this study, future improvements could include optimizing the device geometry, reducing gate dimensions, minimizing metal overlap, using thinner or lower-κ interlayer dielectrics, and improving transistor mobility.\nThese explanations have been added to the revised manuscript to clarify the origin of the frequency limitation and to suggest paths for enhancement.\nOur revision on Page 6:\n“The limited oscillation frequency and high operation voltage primarily arise from a large delay per stage (τ), where the τ = R ⋅ C reflects the effective resistance (R ) and total eff load eff capacitive load (C ). The large gate area of the transistors leads to high gate capacitance, load while gate–electrode overlap and the interlayer dielectric between stacked metal layers introduce significant parasitic capacitance both within and between tiers. Additionally, the moderate mobility of solution-processed MoS and WSe contributes to high R . These factors 2 2 eff collectively limit switching speed, though future optimization in device geometry, dielectric design, and mobility could substantially improve frequency performance.”\n7. No bending test data are provided for the flexible ring oscillator. This should be supplemented to demonstrate mechanical robustness.\nResponse R2Q7: We thank you for this valuable suggestion. To address this point, we have now included bending test data for a flexible 3-stage ring oscillator. The oscillator exhibits stable output signals before and after bending, with no observable degradation in oscillation amplitude or frequency. These results demonstrate the mechanical robustness and reliable electrical performance of our monolithically integrated flexible circuits under mechanical deformation. We have revised the manuscript accordingly.\nOur revision on Page 6:\n“The flexible 3-stage RO retained stable output before and after bending (Supplementary Fig. 17), confirming mechanical robustness and suitability for wearable applications.”\nAfter 1.75 kHz\n) V ( t u p t u O Before 1.87 kHz\n-4 -2 0 2 4 Time (ms)\nFigure R2-5. Output waveforms of the flexible 3-stage ring oscillator before and after bending.\n8. The 6-day stability measurement is insufficient. At least one month of data should be provided to convincingly assess air stability.\nResponse R2Q8: We appreciate your suggestion regarding stability measurements. In response, we have extended the ambient stability test of WSe transistors to over one month. The devices 2 exhibited negligible changes, demonstrating excellent long-term air stability without encapsulation. This result further confirms the robustness of our solution-processed WSe 2 devices.\n100 100 a MoS b WSe 2 2 10-2 10-2 ) ) m 10-4 m 10-4 m m / / A A m m ( 10-6 ( 10-6 S S D 0 day D 0 day I I 2 days 2 days 10-8 10-8 6 days 6 days 1 month 1 month 10-10 10-10 -60 -30 0 30 60 -60 -30 0 30 60 V (V) V (V) GS GS\nFigure R2-6. Air stability of the of the n-MoS (a) and p-WSe (b) transistors over one 2 2 month.\n9. The on/off ratio of only 10 for undoped MoS2 is unexpectedly low. Is this truly MoS2? TEM or other characterization techniques should be employed to verify the material identity.\nResponse R2Q9: We appreciate your concern. To verify the identity and semiconducting nature of our materials, we performed UV–vis absorption spectroscopy. The MoS spectrum 2 clearly exhibits the characteristic A, B, and C excitonic peaks, while the WSe spectrum shows 2 A, B, A′, and B′ features—both in agreement with reported values for 2H-phase semiconducting TMDs (Nature 562, 254–258 (2018).). This confirms the correct identity of the materials.\nThe low on/off ratio observed in undoped MoS is attributed to a high density of sulfur 2 vacancies and unintentional doping, which are commonly observed in solution-processed MoS and lead to degenerate-like transport with weak gate modulation. This behavior has also 2 been documented in prior reports, including Nat Electron 8, 235–243 (2025) and Nat Electron 6, 443–450 (2023).\nMoS WSe 2 B' 2 C ) ) . . u u A' . . a a ( ( e e c c n n B a a b b A r r o o s B s b b A A A 400 600 800 400 600 800 Wavelength (nm) Wavelength (nm)\nFigure R2-6. UV–vis absorption spectra of MoS and WSe inks. These spectral features 2 2 confirm the semiconducting 2H phase of the solution-processed MoS and WSe nanosheets. 2 2\n10. The use of Ni as both gate and source/drain electrodes for both MoS2 and WSe2 devices is questionable. Given the work function mismatch, this may degrade electrical performance. The authors should justify their choice or consider alternative electrodes.\nResponse R2Q10: We appreciate your thoughtful comment regarding the electrode material. Nickel (Ni) was selected as a universal metal for both gate and source/drain electrodes primarily due to its excellent adhesion to dielectric surfaces, as well as its robust chemical and mechanical stability during processing. These properties are particularly important in our solution-based fabrication flow, which involves multiple wet chemical steps, including sonication and lift-off. Ni consistently maintains pattern integrity under these conditions, unlike softer or more reactive metals such as Au or Ag.\nIn addition, the influence of the metal-semiconductor work function difference is less pronounced in our system compared to exfoliated or CVD-grown 2D materials. In our case, solution-processed MoS typically exhibits a high background carrier concentration due to 2 sulfur vacancies and unintentional n-doping, resulting in high intrinsic conductivity and low contact resistance, even with mid-gap metals like Ni. Similarly, treated WSe shows strong p- 2 type behavior, and the doping mitigates Schottky barrier effects at the contact interface. As a result, despite the inherent mismatch in work function, the Ni/WSe contact becomes 2 sufficiently conductive for reliable transistor operation.\nMoreover, using a single metal stack simplifies the overall fabrication of vertically integrated devices, ensuring compatibility across multiple layers and reducing alignment complexity. This uniformity is crucial for scalable M3D circuit assembly.\n11. The flexible devices exhibit significantly poorer performance compared to rigid substrates. What is the underlying reason? Additionally, the thickness of the Al2O3 insulating layer in flexible devices is not specified—is it identical to that in rigid devices?\nResponse R2Q11: We thank you for this question. The reduced performance of flexible devices primarily stems from mechanical and process-related challenges introduced during fabrication and transfer. To minimize surface roughness and more closely match the SiO /Si substrate, we 2 first deposit a 60 nm ALD Al O layer onto a 2 µm-thick parylene film, which serves as the 2 3 flexible substrate. Devices are then fabricated directly on this Al O /parylene stack, supported 2 3 by a sacrificial layer on a rigid Si wafer. After completing both transistor tiers—including the interlayer—thermal release tape is applied, and the stack is detached by dissolving the sacrificial layer in deionized water. The flexible device, now supported by tape, is then transferred onto the final target substrate and thermally annealed to release the tape. Despite efforts to reduce roughness, the thin and mechanically soft parylene substrate is more prone to strain, wrinkling, and deformation during transfer, which can affect contact quality, alignment, and channel mobility. These factors—rather than differences in device architecture—lead to lower inverter gain and reduced ring oscillator frequency compared to devices fabricated directly on rigid SiO /Si substrates. 2\nThe Al O insulating layer used in flexible devices has a thickness of 60 nm, which is identical 2 3 to that used in devices on rigid substrates. Using the same dielectric thickness facilitates a direct comparison of device performance between flexible and rigid platforms and more clearly isolates the underlying causes of performance differences between the two. This information has been clarified in the revised manuscript.\nOur revision on Page 6:\n“We note that flexible devices exhibit reduced inverter gain and oscillation frequency compared to their rigid counterparts, primarily due to mechanical challenges introduced during the peel- and-transfer process. Although a 60 nm ALD-grown Al O layer is deposited on the 2 µm-thick 2 3 parylene film to reduce surface roughness, the flexible stack remains prone to strain and deformation during transfer and thermal release (Supplementary Fig. 3).”\nFigure R2-7. Schematic illustration of device fabrication on rigid SiO /Si substrates (a) and 2 flexible substrates (b). Flexible devices are prepared on parylene/Al O films with a sacrificial 2 3 layer, followed by peel-off using thermal tape and transfer to target substrates for integration.\n12. The data processing in this work is somewhat inconsistent and lacks rigor. For example, WSe2 devices are tested for temperature and temporal stability, while MoS2 devices are not; MoS2 devices show hysteresis data, but WSe2 devices do not. These omissions should be addressed for consistency\nResponse R2Q11: We appreciate your suggestion regarding consistency in device characterization. In this work, we reported a tailored anion-cation doping approach for precise carrier control in n- and p-type WSe and MoS transistors, where stability tests (temperature 2 2 and temporal) were prioritized for WSe owing to its known sensitivity to ambient conditions, 2 while hysteresis analysis was emphasized for MoS to highlight the benefit of our in-solution 2 doping strategy.\nTo address the concern, we have now included additional stability measurements for MoS 2 devices as well as hysteresis data for WSe transistors. These additions provide a consistent 2 comparison across both material systems.\nFigure R2-8. Hysteresis of WSe and MoS transistors measured under different gate voltage 2 2 range.\n. Figure R2-9. Transfer characteristics of MoS and WSe transistors annealed at different 2 2 temperatures in N -filled glovebox. 2\n100 100 a MoS b WSe 2 2 10-2 10-2 ) ) m 10-4 m 10-4 m m / / A A m m ( 10-6 ( 10-6 S S D 0 day D 0 day I I 2 days 2 days 10-8 10-8 6 days 6 days 1 month 1 month 10-10 10-10 -60 -30 0 30 60 -60 -30 0 30 60 V (V) V (V) GS GS\nFigure R2-9. Air stability of the n-MoS and p-WSe transistor over one month. 2 2\nResponse: We sincerely thank you for the thoughtful evaluation of our work and for recognizing the novelty of our low-temperature, solution-processed M3D integration strategy. We appreciate the comments regarding data quality and performance consistency. In response, we have substantially revised the manuscript to clarify key performance metrics, improve the consistency of reporting across figures, and incorporate additional data and schematics where necessary. We believe these revisions have significantly strengthened the clarity and impact of the work.\nBelow are my detailed comments and suggestions for revision:\n1. Although the inverter is reported to operate at an ultra-low supply voltage of 0.1 V with a power consumption of ~8.8 pW, this claim is not well supported. From the output characteristics shown in the inset of Fig. 3b, the inverter’s transition point is around 0.2–0.3 V, indicating limited switching capability at 0.1 V. Moreover, neither the logic gates nor the 5-stage ring oscillators (5-ROs) are demonstrated to function at this voltage. Therefore, the claimed power consumption of 8.8 pW at 0.1 V appears unrealistic and should be reconsidered.\nResponse R3Q1: We thank you for this important point. While our initial report highlighted an 8.8 pW static leakage at V = 0.1 V, we agree that the inverter’s transition voltage (~0.2– DD 0.3 V, Fig. 3b inset) and limited output swing make logic operation unreliable at this low bias. To support the feasibility of low-voltage logic operation, we now include a NOR gate measurement demonstrating correct logic switching at V = 0.3 V. This confirms that our 3D DD inverter design supports logic functionality down to 0.3 V. We have now revised the manuscript to clarify that a static power consumption of ~18.5 pW is measured at V = 0.3 V as this DD voltage represents the lowest point at which logic gates (e.g., NOR) still function.\nOur revision on Page 5:\n“The device operates with sub-nanowatt power consumption, with a static power of ~18.5 pW at 𝑉 = 0.3 V corresponding to a normalized power density of ~18.5 fW/µm.” DD\nFigure R3-1. Input-output characteristics of the NOR gate at V = 0.3, 0.5, and 1 V. DD\n2. For a meaningful comparison of power consumption with other works, the authors should report the device details (such as channel length and width). Power should be normalized accordingly and compared under equivalent operating conditions.\nResponse R3Q2: We thank you for this suggestion. We have added the channel dimensions of the inverter used in the power measurements—channel length = 10 µm and channel width = 1000 µm—to the manuscript. The reported static power consumption of ~18.5 pW at V = 0.3 V corresponds to a normalized power density of ~18.5 fW µm⁻¹ (based on channel DD width). These details have been added to the revised manuscript to facilitate fair benchmarking with prior work.\nOur revision on Page 5:\n“The device operates with sub-nanowatt power consumption, with a static power of ~18.5 pW at 𝑉 = 0.3 V corresponding to a normalized power density of ~18.5 fW/µm” DD\n3. The SS values appear to be extracted from a single data point rather than from the linear region of the log-scale current over several decades, as is standard in the field. The SS comparison in Fig. 1i is therefore unreliable. Please recalculate the SS using proper extraction methods.\nResponse R3Q3: We thank you for pointing this out. As suggested, we have recalculated the subthreshold swing (SS) values using the standard extraction method—based on the slope of the linear region of the log(I )–V transfer characteristics over multiple decades of current. D GS The corrected SS values are now 88 mV/dec for MoS and 119 mV/dec for WSe . 2 2\nOur revision on Page 5:\n“The electrical performances of the solution-processed transistors are characterized from the transfer characteristics of the 200 n-type MoS and 200 p-type WSe devices (Fig. 1g–i). 2 2 respectively. The median SS for n-type MoS and p-type WSe were 133 mV/dec and 193 mV/dec, 2 2 respectively. The MoS transistor achieved an on/off ratio of >108 and a minimum SS of 88 2 mV/dec at V = 1 V, while the WSe transistor exhibited an SS of 119 mV/dec at V = –1 V DS 2 DS with an on/off ratio of >108. These values are comparable to those of CVD-grown 2D transistors14,28-38 (Supplementary Fig. 4 and Supplementary Table 1). Further improvements in the dielectric engineering and the film quality could reduce the SS toward the thermionic limit of 60 mV/dec underscoring the potential of solution processing for high-performance logic applications.”\nFigure R3-2. Transfer characteristics of the solution-processed (a) n-type MoS and (b) p-type 2 WSe transistors. 2\nFigure R3-3. g, Transfer characteristics of the solution-processed 200 n-type MoS and 200 p- 2 type WSe transistors with 18 nm Al O dielectric. Scatter plots of on/off current ratios and SS 2 2 3 values, and statistical histogram of SS for h, n-type MoS and i, p-type WSe transistors. 2 2\n4. Although individual devices show promising performance, the manuscript lacks statistical data on device-to-device variability, circuit yield, or reproducibility across the integrated arrays. These metrics are essential to validate the scalability and robustness of the proposed 3D integration scheme.\nResponse R3Q4: We appreciate your comment. To address concerns about device-to-device variability and reproducibility, we emphasize that integrated circuit demonstrations—such as ring oscillators (ROs)—are effective indicators of system-level reliability. Therefore, we further fabricated and measured five independent 3-stage ROs, which collectively include 15 inverters. All five ROs exhibit stable oscillation with consistent frequencies ranging from 1.31 kHz to 2.37 kHz, confirming good reproducibility and uniformity across devices. This statistical assessment highlights the robustness of our low-temperature M3D integration process and its scalability toward larger integrated systems.\nOur revision on Page 6:\n“We evaluated five independent flexible 3-stage RO (15 inverters total), all exhibiting stable output with frequencies ranging from 1.31 kHz to 2.37 kHz (Supplementary Fig. xxx), confirming the reproducibility and uniformity of the integrated logic devices.”\nRO-1 2.30 kHz\nRO-2 2.08 kHz\nt RO-3 u p 1.31 kHz t u O RO-4 1.70 kHz\nRO-5 2.37 kHz\n-4 -2 0 2 4 Time (ms)\nFigure R3-4. Output waveforms of five independent 3-stage ring oscillators. Each ring oscillator (RO-1 to RO-5) exhibits stable and periodic output with oscillation frequencies ranging from 1.31 kHz to 2.37 kHz, demonstrating device-to-device uniformity and reliable operation across multiple integrated circuits.\n5. While SS and on/off ratios are emphasized for individual devices, other critical parameters, such as carrier mobility and current density normalized by device geometry, are not reported. These are essential for benchmarking and understanding the logic performance.\nResponse R3Q5: We thank you for this comment and agree that field‑effect mobility (μ ) is FE critical for evaluating device performance. The current density is around 10-1 μA/μm, as shown in Fig. 1g and h. We have further extracted μ from the linear regime (V = 1 V) of our transfer FE DS curves for both MoS n‑FETs and WSe p‑FETs under each dopant treatment. For MoS , the 2 2 2 untreated devices exhibit electron μ ≈ 7 cm2 V-1 s-1, while HTFSI, LiTFSI, NaTFSI, KTFSI, FE and HOTf treatments yield μ of ≈ 2.7, 1.5, 1.0, 1.3, and 3.1 cm2 V-1 s-1, respectively (with FE LiOTf, NaOTf, and KOTf giving 0.25 to 0.48 cm2 V-1 s-1). For WSe , untreated films show 2 small hole μ (<0.001 cm2 V-1 s-1), whereas HTFSI and HOTf treatments dramatically enhance FE mobility to 7.2 and 5.3 cm2 V-1 s-1, with LiTFSI, NaTFSI, and KTFSI giving intermediate values (0.5 to 0.3 cm² V⁻¹ s⁻¹). These results, now included in the Supplementary Information.\nFigure R3-5. Transfer characteristics of the solution-processed n-type MoS treated with and 2 without different TFSI⁻ and OTf⁻ based molecular dopants treatment.\nFigure R3-6. Transfer characteristics of the solution-processed p-type WSe treated with and 2 without different TFSI⁻ and OTf⁻ based molecular dopants treatment.\n6. The air stability of doped p-WSe2 devices is reported (6 days), but the environmental stability of n-type MoS2 devices is not mentioned. Please include comparable stability data for both types.\nResponse R3Q6: We appreciate your suggestion regarding consistency in device characterization. We have now included additional stability measurements for MoS devices as 2 well as hysteresis data for WSe transistors. These additions provide a consistent comparison 2 across both material systems. Both the p-WSe and n-MoS transistors exhibit excellent air 2 2 stability, showing minimal degradation after one month of ambient storage under low controlled humidity, without requiring encapsulation.\n100 100 a MoS b WSe 2 2 10-2 10-2 ) ) m 10-4 m 10-4 m m / / A A m m ( 10-6 ( 10-6 S S D 0 day D 0 day I I 2 days 2 days 10-8 10-8 6 days 6 days 1 month 1 month 10-10 10-10 -60 -30 0 30 60 -60 -30 0 30 60 V (V) V (V) GS GS\nFigure R3-7. Air stability of the of the n-MoS (a) and p-WSe (b) transistors over one 2 2 month.\n7. The manuscript presents performance metrics from different devices under varied conditions, making it difficult to assess true device behavior. For instance, the inverter’s power consumption ~8.8 pW is reported at VDD = 0.1 V, while gain is highlighted at VDD = 4 V. Such mixing of device parameters is misleading and should be corrected.\nResponse R3Q7: We thank you for highlighting the inconsistent presentation of inverter metrics. To eliminate any confusion, we have revised the manuscript so that the abstract and conclusion now report only the peak voltage gain, while all discussion of power consumption is confined to the Results Section under a single, clearly stated supply voltage. This separation ensures that readers can compare gain and power metrics without mixing bias conditions.\n8. Inverters are shown to operate from 0.1 V to 4 V, but 5-ROs are only demonstrated at higher voltages (6–10 V) on rigid substrates. The manuscript should explain why no 5-ROs data are presented below 5 V, particularly given the high inverter performance at low VDD. Similarly, the difference in inverter/5-ROs behavior between rigid and flexible substrates (Figs. 3–4) needs clarification.\nResponse R3Q8: We thank you for this important question. While our inverters exhibit high voltage gain and full logic swing at low supply voltages (down to 0.1 V), 5-stage ring oscillators (5-ROs) only function reliably at higher voltages (≥5 V). This difference originates from the fundamentally distinct operating principles and performance thresholds between a single-stage inverter and a multi-stage feedback oscillator.\nA single inverter operates in a static regime, where the input–output relationship is defined by the DC voltage transfer characteristics. As long as the transistors provide sufficient gain and output swing, correct logic levels can be maintained even under low V conditions. This DD allows isolated inverters or logic gates to operate effectively with ultra-low power consumption. In contrast, a ring oscillator is a dynamic circuit that relies on continuous signal propagation and regeneration across multiple inverter stages. The oscillation frequency is given by:\nf= 1/2Nτ, with τ=R ⋅C ,\neff load\nwhere N is the number of stages, R is the effective output resistance, and C is the total eff load capacitive load per stage. In multi-stage configurations, even a modest increase in stage delay (τ) is amplified across the loop, making the system more sensitive to device resistance, capacitive load, and signal attenuation.\nImportantly, R increases significantly as V decreases. Since R ≈V /I , lower drive eff DD eff out D current at small V results in larger resistance and slower output transitions. This voltage DD dependence is particularly pronounced in solution-processed 2D semiconductors with moderate field-effect mobility. Consequently, although static logic operation is retained at low V , dynamic performance in RO circuits becomes severely limited. DD\nMoreover, parasitic capacitance contributes substantially to C , including gate–electrode load overlap and vertical coupling through the interlayer between tiers. These parasitics, while tolerable in isolated inverters, become performance-limiting in oscillators due to their cumulative impact on delay and signal integrity.\nIn our work, we focus on demonstrating reliable 5-RO behavior with simple inverter chains based on solution-processed 2D semiconductors. We thus present data above 6 V, where the drive strength and signal margins are sufficient for stable oscillation. In future work, we plan to explore device- and circuit-level strategies to enable low-voltage RO operation, including compact device geometries and dielectric engineering to reduce parasitic capacitance. In addition, SPICE-level circuit simulations will be conducted to analyze signal attenuation and optimize stage delay. These explanations have been added to the revised manuscript to clarify the origin of the frequency limitation and to suggest paths for enhancement.\nOur revision on Page 6:\n“The limited oscillation frequency and high operation voltage primarily arise from a large delay per stage (τ), where the τ = R ⋅ C reflects the effective resistance (R ) and total eff load eff capacitive load (C ). The large gate area of the transistors leads to high gate capacitance, load while gate–electrode overlap and the interlayer dielectric between stacked metal layers introduce significant parasitic capacitance both within and between tiers. Additionally, the moderate mobility of solution-processed MoS and WSe contributes to high R . These factors 2 2 eff collectively limit switching speed, though future optimization in device geometry, dielectric design, and mobility could substantially improve frequency performance.”\nWe also thank you for this question regarding the difference in inverter/5-ROs behavior between rigid and flexible substrates. The reduced performance of flexible devices primarily stems from mechanical and process-related challenges introduced during fabrication and transfer. To minimize surface roughness and more closely match the SiO /Si substrate, we first 2 deposit a 60 nm ALD Al2O3 layer onto a 2 µm-thick parylene film, which serves as the flexible substrate. Devices are then fabricated directly on this Al O /parylene stack, supported by a 2 3 sacrificial layer on a rigid Si wafer. After completing both transistor tiers—including the interlayer—thermal release tape is applied, and the stack is detached by dissolving the sacrificial layer in deionized water. The flexible device, now supported by tape, is then transferred onto the final target substrate and thermally annealed to release the tape. Despite efforts to reduce roughness, the thin and mechanically soft parylene substrate is more prone to strain, wrinkling, and deformation during transfer, which can affect contact quality, alignment, and channel mobility. These factors—rather than differences in device architecture—lead to lower inverter gain and reduced ring oscillator frequency compared to devices fabricated directly on rigid SiO /Si substrates. 2\nOur revision on Page 6:\n“We note that flexible devices exhibit reduced inverter gain and oscillation frequency compared to their rigid counterparts, primarily due to mechanical challenges introduced during the peel- and-transfer process. Although a 60 nm ALD-grown Al O layer is deposited on the 2 µm-thick 2 3 parylene film to reduce surface roughness, the flexible stack remains prone to strain and deformation during transfer and thermal release (Supplementary Fig. 3).”\nFigure R3-8. Schematic illustration of device fabrication on rigid SiO /Si substrates (a) and 2 flexible substrates (b). Flexible devices are prepared on parylene/Al O films with a sacrificial 2 3 layer, followed by peel-off using thermal tape and transfer to target substrates for integration.\n9. The optical image in Fig. 3a is not sufficiently clear to illustrate the device structure. Please provide a cleaner schematic to assist reading.\nResponse R3Q9: We thank you for this suggestion and have added a clean schematic illustration in Figure 1b that clearly delineates the device structure of the two transistor tiers, interlayer insulator, vertical connection, and source/drain and gate electrodes. All key layers are now color‑coded and labeled.\nFigure R3-9. Schematic of the M3D-stacked complementary metal-oxide-semiconductor (CMOS) inverter structure.\n10. The Al2O3 layer above the Ni gate appears to exceed 50 nm in the cross-sectional TEM image (Fig. 1e), yet SS and gate voltages are surprisingly low (±5 V in Fig. 1g, h). Meanwhile, Fig. 2g and Supplementary Figs. 3–4 show gate voltages as high as 60 V. This discrepancy should be addressed. Please specify the actual dielectric thickness and clarify the variation in operating voltages across the figures.\nResponse R3Q10: We thank you for pointing out this important observation. The observed variation in operating voltages stems from these different dielectrics. In Fig. 1e, the Al2O3 layer deposited by ALD is 60 nm thick, consistent with our fabrication protocol for M3D integration. This dielectric thickness was chosen to ensure low leakage current and high uniformity during device stacking.\nFor comparative electrical studies in the previous version of Fig. 2g and Supplementary Fig. 3– 4, we used conventional 100 nm SiO on Si substrates as the gate dielectric. This choice of 2 100 nm SiO on Si substrates aligns with standard benchmarking practices in the 2D materials 2 community and facilitates meaningful comparison with other literature. We have clarified this distinction in the revised manuscript to avoid confusion and ensure consistency in data interpretation.\nOverall Recommendation:\nWhile the manuscript introduces a significant advancement, the monolithic 3D integration of complementary circuits using solution-processed 2D semiconductor inks, the reported device performance is inconsistently presented and, at times, misleading. The main value of this work lies in the integration strategy, not in setting new benchmarks for device performance (far below the literature works by exfoliated or CVD ones). It is recommended that the manuscript be reorganized to emphasize this key contribution, tone down inflated performance claims, and include comprehensive, consistent performance data to support the conclusions.\nResponse: We appreciate your suggestions. We agree that the primary significance of this work lies in the low-temperature, solution-processed M3D integration strategy, rather than in setting new performance benchmarks against exfoliated or CVD-grown devices. To reflect this, we have reorganized the manuscript to place stronger emphasis on the integration methodology and its implications for scalable, flexible electronics, while moderating claims related to absolute device metrics. For instance, Figure 1i (benchmarking of on/off ratios and subthreshold swing values against CVD-grown devices) has been removed to avoid misleading comparisons.\nFurthermore, we have strengthened the presentation of consistent performance data across both MoS (n-type) and WSe (p-type) transistors. In the revised manuscript, we now report 2 2 hysteresis, thermal stability, and long-term ambient stability for both semiconductors, ensuring a balanced and rigorous assessment. These additions provide more reliable results of device reproducibility, aligning with your recommendation for a comprehensive evaluation.\n………… end of the response letter."}, {"round": 2, "reviewer_comments": {"reviewer_2": "Here are the major concerns that require the authors' thorough response and substantial revision:\n1) My previous request for statistical data on individual inverters has not been adequately addressed. The characterization of 5 single ring oscillator comprising 15 inverters is insufficient to represent the performance distribution across the wafer. Comprehensive statistics on key inverter metrics, such as voltage transfer characteristics, gain, and noise margins, are essential and currently missing.\n2) The presented transistor data saturates at a gate voltage of only ~5 V. Given the use of an 18 nm Al2O3 dielectric layer, which should theoretically sustain a much higher gate bias (e.g., ~10 V), this early saturation is unexpected and unexplained. Please clarify if the presented data is the full voltage sweep and provide a physical explanation for this observation. Are there issues with gate leakage, interface quality, or contact resistance that limit the performance?\n3) The statistical data from 200 n-type and p-type devices, while helpful, does not convincingly demonstrate wafer-scale uniformity. This is a critical point raised by both reviewers, and the authors have circumvented it in their response. A map showing the distribution of key parameters (e.g., mobility, threshold voltage, on/off ratio) across the entire wafer is necessary to prove the scalability and reproducibility of their process.\n4) The core advantage of complementary integration is the reduction of static power consumption and the enhancement of operating speed. Therefore, it is imperative to demonstrate the high-frequency performance of the fundamental logic devices, such as the maximum operating frequency of inverters or ring oscillators. Furthermore, the manuscript claims benefits from 3D integration but does not address the potential drawback of increased parasitic capacitance, which could severely limit circuit speed. An analysis or measurement related to this parasitic capacitance is required.\n5) The W/L data for the transistors are not provided anywhere in the manuscript. The optical micrographs suggest that the devices remain at a large scale (~500 μm), which fails to demonstrate the potential for high-density integration. To claim relevance for advanced integration, data from scaled-down, short-channel devices must be provided to show how the performance evolves with critical dimensions.\n6) The reported carrier mobility values are severely limited and fall far below the medium performance level. Numerous prior studies demonstrating wafer-scale synthesis have reported significantly higher mobility values. The authors must therefore more clearly articulate what the novel contribution and practical advantage of their work is, given this level of performance. What is the specific advancement that compensates for the inferior electrical properties and makes this work stand out?\n7) In your 3D integration process, what effect does the introduction of the interlayer have on the underlying bottom-layer MoS2 n-FETs? Specifically, does it induce any doping-like effects or lead to performance degradation in these pre-fabricated devices?\n8) The FET characterizations provided appear to be primarily from individual, isolated monolayer devices. It is crucial to clarify how the entire 3D integration process flow, particularly the deposition of the top-layer Al2O3 dielectric for the p-FETs, affects the performance of the underlying n-FETs. Does this step introduce doping, cause contamination, or result in any measurable performance degradation in the bottom layer?\n9) The thermal release tape transfer process inherently involves stress application and release. Please discuss whether this specific step induces any detrimental effects (e.g., cracking, strain, reduced mobility) on the electrical performance of the final 3D stack.\n10) Although bending test data are provided for the flexible ring oscillator, neither the magnitude of the applied strain nor the number of bending cycles is specified.", "reviewer_3": "I have carefully reviewed the revised manuscript along with the authors’ response letter. They have conducted the additional experiments I requested and have made appropriate revisions to the main claims and figures that previously raised concerns. Overall, the manuscript has been substantially improved.\nI have also examined their responses to referee #1, and I find that those concerns have been satisfactorily addressed as well. I therefore recommend acceptance of the manuscript."}, "author_response": "Response R2Q1: We thank you for this suggestion. For more comprehensive statistical data of the inverters, we have significantly expanded our inverter characterization to include 30 individual inverters across the wafer. The voltage transfer characteristics (VTC), voltage gain, and noise margin of these devices are presented. The results demonstrate excellent device uniformity, with an average voltage gain exceeding 150 V/V and an average noise margin above 90%, highlighting the reproducibility and scalability of our solution-processed M3D fabrication approach.\nOur revision on page 5:\n“Moreover, Supplementary Fig. 13 presents the voltage transfer characteristics of ~30 inverters, exhibiting an average gain exceeding 150 V/V and an average noise margin above 90%, highlighting their excellent uniformity and ensuring reliable circuit operation.”\nFigure R1. Characterization of 30 solution-processed M3D-stacked inverters fabricated on a 2-inch wafer.\n2) The presented transistor data saturates at a gate voltage of only ~5 V. Given the use of an 18 nm Al2O3 dielectric layer, which should theoretically sustain a much higher gate bias (e.g., ~10 V), this early saturation is unexpected and unexplained. Please clarify if the presented data is the full voltage sweep and provide a physical explanation for this observation. Are there issues with gate leakage, interface quality, or contact resistance that limit the performance?\nResponse R2Q2: We appreciate your comment. We have now included the corresponding gate leakage current (I ). The I indeed begins to increase when the gate bias exceeds ~5 V. To avoid g g extrinsic leakage effects, we restricted our transistor characterization within ±5 V. Importantly, in this safe operating regime, I is several orders of magnitude lower than the channel current, g confirming that the observed early saturation of transfer curves is not caused by leakage. Instead, the rapid turn-on arises from the strong electrostatic coupling of the thin high-κ dielectric combined with our in-solution doping approach. This results in efficient channel control at low gate voltages, enabling MoS and WSe transistors to reach full accumulation or 2 2 depletion by ~5 V. Additionally, the quality of the ALD-grown Al O dielectric is also 2 3 determined by the deposition process and equipment. Further optimization of the deposition process could enable a low-voltage operation and low leakage current.\nFigure R2. Transfer characteristics of the solution-processed (a) n-type MoS and (b) p-type 2 WSe transistors. 2\n3) The statistical data from 200 n-type and p-type devices, while helpful, does not convincingly demonstrate wafer-scale uniformity. This is a critical point raised by both reviewers, and the authors have circumvented it in their response. A map showing the distribution of key parameters (e.g., mobility, threshold voltage, on/off ratio) across the entire wafer is necessary to prove the scalability and reproducibility of their process.\nResponse R2Q3: We thank you for emphasizing the importance of wafer-scale uniformity. To address this, we have shown spatial mapping of 100 MoS (n-type) and WSe (p-type) 2 2 transistors across a 2-inch wafer in a 10 × 10 array configuration (Fig. R3). The parameter maps of field-effect mobility, threshold voltage (V ), and on/off ratio exhibit spatial uniformity, with TH average mobilities of 3.03 cm2 V-1 s-1 for MoS2 and 3.82 cm² V⁻¹ s⁻¹ for WSe . The consistent 2 electrical characteristics across the wafer confirm the reproducibility and scalability of our low- temperature, solution-processed M3D fabrication process.\nOur revision on page 4:\n“The consistent electrical characteristics across the wafer confirm the reproducibility and scalability of our low-temperature, solution-processed transistors (Supplementary Fig. 5).”\nFigure R3. Wafer-scale uniformity of solution-processed transistors. Spatial maps of mobility, threshold voltage, and on/off ratio for (a–c) MoS and (d–f) WSe transistors across a 2-inch 2 2 wafer (10 × 10 array).\n4) The core advantage of complementary integration is the reduction of static power consumption and the enhancement of operating speed. Therefore, it is imperative to demonstrate the high-frequency performance of the fundamental logic devices, such as the maximum operating frequency of inverters or ring oscillators. Furthermore, the manuscript claims benefits from 3D integration but does not address the potential drawback of increased parasitic capacitance, which could severely limit circuit speed. An analysis or measurement related to this parasitic capacitance is required.\nResponse R2Q4: We appreciate your insightful comment. The oscillation frequency characterization of the 5-stage ring oscillator, as shown in Figure R4, exhibits a maximum frequency of ~13.5 kHz at V =12 V. The frequency increases with supply voltage before DD gradually saturating beyond ~12 V, which we attribute to intrinsic RC delays in the circuit. Specifically, the oscillation frequency of a ring oscillator follows f ≈ 1/(2Nτ), where N is the number of stages and τ=R C is the stage delay. At higher V , R reduction becomes less eff load DD eff significant, while C (dominated by gate capacitance and interconnect capacitance) remains load constant, leading to frequency saturation.\nWe also thank you for highlighting the importance of parasitic capacitance in determining circuit speed. As reported by Fan et al. (Nat. Electron. 6, 879–887, 2023), parasitic capacitance — particularly gate–source/drain overlap capacitance and interlayer coupling capacitance — is a primary factor limiting the high-frequency performance of 2D devices and circuits. Our present work adopts a fully back-gated configuration, which maximizes electrostatic coupling and current drive but inherently introduces larger parasitic capacitance compared with locally back-gated or air-gap designs. This trade-off is evident in Figure R5 of Fan et al.: while the fully back-gated architecture achieves the highest normalized I , it also exhibits the largest on gate capacitance C and C V /I , which directly influence the delay time τ=R C and gg gg dd on eff load limit the oscillation frequency.\nFor example, a locally back-gated structure can effectively reduce C and interfacial gg capacitance by minimizing the overlap region, thereby lowering gate delay. In our work, we prioritize demonstrating M3D complementary integration with strong channel control and reliable operation, hence the choice of the fully back-gated dielectric design. Future optimization efforts will target capacitance-driven delay reduction by engineering shorter gate overlaps, thinning the inter-tier dielectric, and refining interconnect geometries, which will collectively help push the oscillation frequency beyond the current limit toward the MHz regime. We have cited the paper in our revised manuscript.\nOur revision on page 4:\n“The frequency increases with supply voltage before gradually saturating beyond ~12 V, which we attribute to intrinsic delays in the circuit.”\nFigure R4. Frequency response of the 5-stage RO as a function of supply voltages.\nFigure R5. Comparison of simulated I values, C values and gate delays for Different device on gg designs: classical MOSFET, air-gap device, locally back-gated device and fully back-gated device. [Nat Electron 6, 879–887 (2023).]\n5) The W/L data for the transistors are not provided anywhere in the manuscript. The optical micrographs suggest that the devices remain at a large scale (~500 μm), which fails to demonstrate the potential for high-density integration. To claim relevance for advanced integration, data from scaled-down, short-channel devices must be provided to show how the performance evolves with critical dimensions.\nResponse R2Q5: We thank you for raising this important point. The channel length (50 μm) and width (750 μm) of the transistors in Figure 1 g-h are now explicitly provided in the revised manuscript.\nWe acknowledge that scaling down to short-channel devices is indeed crucial for demonstrating the ultimate potential of high-density integration. In this work, our focus has been on establishing the feasibility of low-temperature, solution-processed M3D integration, rather than optimizing device scaling. On the other hand, due to equipment limitations, we were not able to fabricate sub-micron channel devices at this stage. Nonetheless, the current 10 µm channel length devices successfully demonstrate reliable CMOS operation and circuit integration, thereby validating the integration strategy.\nIn the future, we plan to pursue device scaling in future work by introducing advanced lithography and etching processes. This will allow us to study the performance evolution of short-channel devices and further enhance circuit density, bridging the gap toward practical high-density 2D semiconductor integration.\n6) The reported carrier mobility values are severely limited and fall far below the medium performance level. Numerous prior studies demonstrating wafer-scale synthesis have reported significantly higher mobility values. The authors must therefore more clearly articulate what the novel contribution and practical advantage of their work is, given this level of performance. What is the specific advancement that compensates for the inferior electrical properties and makes this work stand out?\nResponse R2Q6: We acknowledge your concern regarding the carrier mobility values. It is important to emphasize that the mobilities reported in this work are consistent with recent reports of CVD-based studies of M3D integration using 2D materials. For example, Pendurthi et al. (Nat. Nanotechnol. 19, 970–977 (2024)) demonstrated M3D integration using CVD- grown materials, where the extracted mobilities were also moderate (~4 cm2 V-1 s-1). Similar to their findings, our results indicate that while exfoliated or isolated CVD devices may reach higher intrinsic mobilities, the values observed in integrated circuits are inherently reduced. Thus, the mobility values in our study are not anomalous but reflect the current state of M3D integration platforms.\nThe novelty and practical significance of our work lie in the integration strategy rather than pushing the mobility benchmark of individual devices. As summarized in Table R1, our solution-processed approach uniquely achieves low-temperature (<150 °C), transfer-free fabrication of vertically stacked CMOS circuits, with competitive inverter gain, low power consumption, and functional ring oscillators on both rigid and flexible substrates. Unlike high- temperature CVD or transfer-based methods, our approach offers mechanical robustness and compatibility with polymeric and wearable platforms, representing a significant advancement in manufacturable 3D circuit integration. These system-level advantages compensate for the moderate mobility values and underscore the unique contribution of our solution-based M3D strategy.\nTable R1. Comparison of different fabrication methods for M3D integration using 2D materials, highlighting key device functionalities.\nInverter CMOS Process Power RO Flexibility Method gain References type temperature consumption frequency demonstration (V ) DD\n110 pW Solution- 462 V/V CMOS ≤ 150 °C (110 fW/µm) 13.5 kHz High This work process (4 V) (0.3 V, Peak) 18.5 pW (18.5 fW/µm) (0.3 V, Static)\n~ 518 pW Mechanical Ref. 13 23 V/V (1 V, Peak) Exfoliation CMOS / / / Nature 630, 346- (7 V) ~ 30 pW /Transfer 352, (2024). (1 V, Static)\nRef. 8 1000 °C 79 V/V CVD/Transfer CMOS / / / Nat. Nanotechnol. (CVD) (3 V) 19, 970-977, (2024).\n~2 pW Ref. 12 18 V/V CVD/Transfer CMOS / (0.25 V, / / 2022 IEDM. (3 V) Static) 20.26.21-20.26.24. 850 °C\nRef. 14 (CVD) 96 V/V CVD/Transfer NMOS / / / Nature 630, 340- 150 °C (5 V) 345, (2024). (ALD)\nRef. 15 650 °C 7 V/V CVD/Transfer CMOS / / / Small 18, 2107650, (CVD) (4V) (2022).\nRef. 16 485 °C and CVD direct ~ 13 V/V Nature 636, 615- CMOS 350 °C / / / growth (1.5 V) 621, (CVD) (2024).\n7) In your 3D integration process, what effect does the introduction of the interlayer have on the underlying bottom-layer MoS2 n-FETs? Specifically, does it induce any doping-like effects or lead to performance degradation in these pre-fabricated devices?\n8) The FET characterizations provided appear to be primarily from individual, isolated monolayer devices. It is crucial to clarify how the entire 3D integration process flow, particularly the deposition of the top-layer Al2O3 dielectric for the p-FETs, affects the performance of the underlying n-FETs. Does this step introduce doping, cause contamination, or result in any measurable performance degradation in the bottom layer?\n9) The thermal release tape transfer process inherently involves stress application and release. Please discuss whether this specific step induces any detrimental effects (e.g., cracking, strain, reduced mobility) on the electrical performance of the final 3D stack.\nResponse R2Q7-Q9: We thank you for these insightful questions regarding possible degradation pathways in our 3D integration process. To directly address these concerns, we performed systematic device measurements at multiple stages of the integration flow.\nEffect of the SU-8/Al2O3 interlayer (Q7-Q8):\nThe transfer characteristics of the bottom‐layer MoS2 n-FETs were carefully evaluated before and after the deposition of the SU-8 and ALD-grown Al O interlayer. The results show that 2 3 the electrical characteristics remain stable, with negligible changes in threshold voltage and on-state current. This indicates that the interlayer does not induce unintended doping or measurable degradation of the underlying channel. Moreover, the measured transfer curves confirm that this step does not introduce doping‐like effects or contamination that compromise device performance. The robustness of the SU-8/Al O encapsulation could further effectively 2 3 protects the MoS transistor during subsequent WSe transistor fabrication. 2 2\nEffect of thermal release tape transfer (Q9):\nWe acknowledge that the peel-and-transfer process using thermal release tape introduces some degree of performance reduction in the bottom-layer MoS devices. After transfer, the 2 transistors exhibit slightly lower on-current and positively shifted V compared to their pre- th transfer state. This degradation is attributed to the mechanical stress and strain imposed during peeling and thermal release (Nat. Electron. 3, 711-717.). Nonetheless, the overall device functionality remains intact, and the integrated circuits operate reliably, demonstrating that our process is robust enough to sustain 3D stacking on flexible substrates despite the modest reduction in performance.\nWe have added the result in our revised manuscript.\nMoS 2 0.06 As-fabricated After SU-8/Al O 2 3 ) After transferring m m / A m ( S D I 0.04 0.02 0.00 -5 0 5 10 15 V (V) GS\nFigure R6. Transfer characteristics of the as-fabricated MoS transistors, after SU-8/Al O 2 2 3 interlayer, and after transferring to a flexible substrate.\n10) Although bending test data are provided for the flexible ring oscillator, neither the magnitude of the applied strain nor the number of bending cycles is specified.\nResponse R2Q10: We thank you for this suggestion. In the revised manuscript, we now specify the bending conditions for the flexible three-stage ring oscillator. The devices were subjected to a bending with a radius of 9.5 mm, corresponding to a tensile strain of ~0.02%.\nMeasurements were taken before bending and after 50 bending cycles, with negligible change in oscillation frequency or output stability.\nResponse R3: We sincerely thank you for the careful re-evaluation of our revised manuscript and for recognizing the substantial improvements made in response to the previous round of comments. We also greatly appreciate your confirmation that the concerns raised by Reviewer #1 have been adequately resolved."}, {"round": 3, "reviewer_comments": {"reviewer_2": "The authors have adequately addressed all my concerns through the additional experiments and revisions. The manuscript is now much improved and suitable for publication. I recommend acceptance and have no further feedback."}, "author_response": ""}]

Decision letter