Micro-LED/van der Waals heterointegration for in-pixel processing display architecture

Domain: chemistry
Published: 2026-02-21
Editorial outcome: major_revision

Abstract
The rapid evolution of intelligent display technologies is driving the development of next-generation edge smart systems, yet conventional off-pixel processing architectures suffer from severe display latency and energy bottlenecks. Embedding in-memory computing features into pixel-level active drivers presents a promising strategy for co-locating image processing and display. In this work, we provide an in-pixel processed display-driven architecture that integrates micro-LEDs with MoS2 in-memory transistors into a 16 × 16 active display array. Our in-pixel processing design exhibits high luminance (>3 × 105 cd·m⁻2), high-speed operation (5000 Hz), and compact dimensions of 20 × 35 μm per pixel. Crucially, leveraging the segmented voltage-luminance response and the non-volatile multilevel conductance update characteristics of the design devices, we demonstrate in-situ image reconstruction and real-time display using in-pixel processed micro-LED arrays. The image reconstruction capability of the proposed design is validated through a neural network-based image recognition task, where the inference process is implemented directly on the pixel array by deploying the trained weights via non-volatile conductance modulation. The reconstructed images achieved a significantly higher accuracy of 99.29% compared to the original inputs (79.81%). These results highlight the significance of the in-pixel processed display architecture as a promising approach to realize high-performance intelligent display technologies.

Introduction
The rapid advancement of intelligent display technologies is revolutionizing interactive experiences and enabling next-generation Internet of Things applications1–3. Specifically, relying on typical silicon-based complementary metal oxide semiconductor (CMOS) driving circuits, transistor-capacitor cell design, and precise alignment bonding processes, micro-LEDs with high luminance and high resolution display features are propelling the blooming of intelligent display products4–7. However, with the increasing complexity and ever-growing loading for edge data processing escalating, conventional display-driving architectures relying on off-pixel processors are suffering from high data-shuttling latency and energy consumption8–10. This becomes a critical bottleneck for meeting high-performance display requirements in high-frame-rate imaging (120 Hz) and high-dynamic-range rendering11,12, necessitating a fundamental innovation in display driving design towards energy-efficient operation with integrated in-situ processing capabilities.

Image reconstruction, such as contrast and enhancement, as a pivotal stage in display pipelines, typically depends on discrete processing units (e.g., GPUs/ASICs) and complicated peripheral circuits13–16. Recent progress in in-memory computing architectures that empower low latency and parallel processing operations, offering a disruptive alternative for in-situ efficient display technology by embedding computational capabilities within active drivers17–21. For instance, emerging nonvolatile devices, such as floating-gate transistors, with analog switching behaviors can jointly drive micro-LEDs and perform in-situ processing22,23. Particularly, the linear voltage-luminance modulation enables low-level contrast calibration, while multistate charge storage facilitates high-level tasks like denoising and super-resolution reconstruction24–26. The original in-situ processed display concept was demonstrated in an electrolyte-gated synaptic transistor-driven quantum-dot light-emitting diode cell, achieving a luminance memory behavior, akin to the classical transistor-capacitor (e.g., 1T1C) driving design27. This scenario is subsequently extended to more compact light-emitting devices via an embedded conductance tuning layer, aiming to boost integration density and explore in-situ synaptic weight-dominated luminance modulation28,29. Despite these advances, current research on this aspect primarily focuses on either low-resolution low-luminance organic light emitting diode components or silicon-based driving circuits with fussy circuit design, low-yield bonding alignment, and high operating voltages. As the demand for ultra-high-resolution and reliable driving continues to rise, efficient intelligent display architectures call for collaborative optimization in driving configurations and mechanisms beyond silicon CMOS and oxide thin-film transistors.

The emergence of van der Waals (vdW)-based neuromorphic electronic devices, combining non-volatile memory and parallel processing characteristics, offers a high-density integrated driving platform ideally suited for micro-LED-based computational displays. Initial proof-of-concept studies, such as the monolithic integration of MoS2 field-effect transistors driving micro-LEDs for high-luminance displays, have validated the potential of vdW devices in display driving areas22,30,31. To fully unlock the potential of vdW material for intelligent micro-LED displays, we pioneer an innovative in-pixel processed display-driven micro-LED display (IPPMLED) design with integrated in-situ processing capabilities. The proposed IPPMLED architecture integrates micro-LEDs with 16 × 16 MoS2 synaptic transistor arrays as the pixel-level active drivers, achieving high luminance (>3 × 105 cd m⁻2), a small pixel footprint (20 × 35 μm), fast operating speed (5000 Hz), and operating reliability (106 cycles @ 120 Hz). Benefiting from the non-volatile, multilevel conductance update characteristics of the driver transistors, the flexibly modulated and temporarily stored luminance can be achieved in the integrated pixel devices, underlying their in-situ image processing and real-time display capabilities. Specifically, the piecewise linear voltage–luminance characteristics that closely align with pixel remapping schemes allow the implementation of the contrast stretching in the fabricated IPPMLED array, realizing the in-situ image enhancement display for noisy input letter images. By exploiting the pixel-level weight programmability of the IPPMLEDs, the trained neural network weights for image recognition can be deployed directly onto the IPPMLED arrays for hardware-accelerated inference. Consequently, the in-situ processed images achieve a recognition accuracy of 99.29%, significantly outperforming unprocessed inputs (79.81%). The integrated display approach in this work delivers a closed-loop solution that unifies image optimization and display within a compact, highly efficient pixel cell, advancing in-pixel image processing for next-generation intelligent display technologies.

Results
The structural design and device integration of IPPMLED
In contrast to traditional active-matrix micro-LED driver systems, where driver transistors merely function as current regulators for pixel switching and luminance control32, the proposed IPPMLED design endows each driver transistor with parallel memory and processing capabilities, enabling efficient image reconstruction and real-time display. As illustrated in Fig. 1a, the IPPMLED architecture unifies the dual capabilities of in-situ image enhancement and on-chip weight updating for image recognition under a unified hardware platform. Specifically, by leveraging its gate-tunable luminescence properties, the device enables real-time contrast stretching (Fig. 1a(i)). This process dynamically remaps input pixel distributions for instantaneous data display. Simultaneously, the nonvolatile memory characteristics allow for the persistent retention of synaptic weights, thereby supporting the in-situ inference tasks required for robust image recognition via multiply-accumulate (MAC) operations within the IPPMLED-based pixel array (Fig. 1a(ii)).

Figure 1b shows the structural schematics of the designed IPPMLED display array and the corresponding manufacturing procedure. Each pixel unit comprises a vdW synaptic transistor and a micro-LED, forming a point-to-point modulation scheme via one-transistor-one-diode (1T1D) integration. Considering the high-resolution and high-yield requirements of future intelligent display technologies, a low-temperature-compatible maskless lithography process route is adopted in this study33. As illustrated in Fig. 1b, the main procedures include the precise patterning of the microscale electrodes, the definition of the monolayer vdW material MoS2 active channels, the fabrication of the self-aligned bonding interfaces, and the low-temperature thermo-compression bonding (TCB) (<200 °C), leading to the vertical interconnection between the micro-LEDs and the driver transistor array. Specifically, the bottom contact configuration of the MoS2-driver transistor enables rich modulation of the IPPMLED devices, which will be described in detail below. Note that 300 nm SiO2 is employed as the gate dielectric during the early-stage exploration and validation of the proposed display architecture, owing to its advantages in better color contrast for transferred vdW materials and hence improving the processing reliability. Figure 1c provides the optical micrograph of the fabricated IPPMLED array, where each 1T1D cell integrates at the intersection of the gate and data lines to enable individual pixel addressing. The array features a pixel pitch of 84.75 μm, corresponding to an integration density of 300 pixels per inch (PPI). The clear surface image of an individual 1T1D pixel reveals the high fabrication quality of the designed processing route. Cross-sectional transmission electron microscopy (TEM) characterization with energy-dispersive X-ray spectroscopy (EDS) analysis examines the uniform interfaces and material composition of the vdW-driver transistors (Fig. 1d and Fig. S1a). Raman spectroscopy is further employed to confirm the crystalline property of the monolayer MoS2 channels after TCB step, with typical E1 2g and A1g peaks observed at 383 cm−1 and 408 cm−1, respectively (Fig. S1b).

Driving characteristics of IPPMLED
The electrical characteristics of the vdW-driver transistors serve as the critical determinant of pixel modulation in the IPPMLED array, directly impacting key display metrics such as luminance uniformity and stability. Figure 2a, b present the transfer and output characteristics of a representative MoS2 driver transistor, respectively. It exhibits n-type behavior with good ohmic contact features34. The on/off current ratio exceeds 106 orders ensures efficient current modulation and high display contrast. Notably, the observed clockwise hysteresis in the transfer curves manifests controllable charge-trapping dynamics during the carrier transport process35, underlying the achievement of programmable luminance profiles in micro-LEDs through driving history manipulation.

Based on the efficient driving capability of the MoS2 driver transistor, we further examine the electrical and luminescent characteristics of the integrated IPPMLED devices. As shown in Fig. 2c, the device-to-device variation is analyzed across 100 randomly selected IPPMLED pixels, for which the overlapped transfer characteristic curves with a variation of 11.98% recall the n-type conducting behavior of MoS2 transistors in Fig. 2a. More statistical analysis of the threshold voltage (Vth), on-current (Ion), and off-current (Ioff) is presented in Fig. 2e. Notably, variations among integrated units remain minimal with an average Ion of 2.6 × 10−6 A and Ioff of 5.5 × 10−13 A. Figure 2d shows the output characteristic of the IPPMLED pixel, along with the corresponding light-emitting feature (red dashed curve). The turn-on data voltage (Vdata) of IPPMLED can be identified as around 2.3 V, at which the micro-LED begins to emit visible blue light and then exhibits an exponential rise in luminance with respect to the Vdata.

The blue-emitting micro-LED devices in this architecture are fabricated on the mature gallium nitride (GaN) platform (Supplementary Note 1 and Fig. S2), which offers significant advantages in material stability, electro-optical efficiency, and operational lifetime36,37. The micro-LED cell exhibits remarkable luminescence performance, achieving a peak external quantum efficiency (EQE) of 32.46% at a current of 0.29 mA, and a luminance of 3.13 × 106 cd m−2 at a current density of 2.4 × 105 mA cm−2 (Fig. S3). Fig. S4 provides the electroluminescence (EL) characteristics of the micro-LED under various driving currents. The observed narrowband emission peaks and absence of spectral shift confirm the color purity and stable emission characteristics38. Such high-performance emission can be stably maintained over 2 h under a fixed driving voltage (Fig. 2f), and exhibits negligible luminance degradation over a 5-week duration (Fig. S5).

To evaluate the switching reliability of the integrated device, a pair of driving voltages is applied to alternately switch the IPPMLED pixels between the on state and the off state under a fixed Vdata of 3 V. The recorded current exhibits long-term endurance, maintaining stable and repeatable switching behavior over 106 cycles at both 60 Hz and 120 Hz standard speed (Fig. 2g and Fig. S6), meeting the critical merits of device reliability and operational stability under continuous-use conditions. Furthermore, the IPPMLED also demonstrates consistent switching behavior over 10,000 cycles at a high frequency of 5000 Hz without obvious degradation (Fig. 2h and Fig. S7). Based on the obtained device performance, we further perform benchmark tests with existing active-driving display technologies, including luminance, pixel size, integration density, and switching characteristics (Supplementary Table 1). Figure 2i provides a clear comparison with the key metrics in the modern display fields22,29,31,39. Our IPPMLED design demonstrates a well-balanced display performance, particularly excelling in integrating in-pixel processing capabilities with practical applications. This integration underscores its potential for high-resolution and compact display implementations.

Multilevel luminescence tuning of IPPMLEDs
Typical in-situ image presentation in display terminals, including image contrast and local pixel calibration, closely relies on controllable luminescence characteristics40,41. For example, the driving voltage-dependent luminescence behaviors dominate the contrast stretching principles. Thus, the driving voltage-dependent luminescence characteristics of the proposed IPPMLED devices are systematically investigated. Figure 3a exhibits the relationship between driving current and luminance of the IPPMLED pixel, revealing a strong linear evolution. This result indicates the luminance behavior is highly predictable, reducing the need for luminance compensation12. As the primary control parameter, gate voltage manipulates the emitted luminance behavior by regulating the injection current of the micro-LEDs. As shown in Fig. 3b, the gate voltage-luminance dependency can be assigned as three phases: a non-emissive region at low gate voltages, a saturation region at high gate voltages, and a quasi-linear modulation region in the middle, where luminance can be precisely and predictably controlled. This segmented luminance modulation characteristic provides a fundamental principle for contrast enhancement in display systems, enabling per-pixel luminance remapping through gate voltage encoding.

Besides, higher-quality image presentation necessitates advanced high-level image reconstruction, where embedded intelligent calibration at the display pixel terminals is expected42–45. In this context, IPPMLED devices serve as pixel-level weight updating units for neural network–based image processing, physically embodied by the programmable and nonvolatile conductance states. This necessitates an in-depth investigation into the weight plasticity dynamics for shaping the pixel-level in-situ processing capability. We first review the uniform charge-trapping transport behavior in Fig. 2a, for which the uniform charge-trapping transport behavior is critical in shaping synaptic plasticity. Its physical origin can be understood by the bottom-contact fabrication procedures in Fig. 3c, during which the patterning of source/drain electrodes is followed by the channel transfer process. This scenario, compared to the typical top-contact configuration (Fig. S8), would provide a broader space, i.e., vdW gaps, for residual adsorbates (such as H2O and oxygen) to be trapped at the interface of the active channel and the substrate (Fig. 3d)46,47.

Furthermore, both microscopic observation and holistic dynamic electrical characterizations are performed to validate this hypothesis. A high-resolution cross-sectional TEM image reveals the suspended structure between MoS2 and SiO2, in good agreement with the measured electrical characteristics (Fig. S9). Low-frequency noise analysis for two devices with top and bottom configurations further allows us to visualize the dynamic charge trapping-detrapping mechanisms by diagnosing the carrier transport fluctuations48,49. The measured power spectral density (PSD) of the current fluctuations (S) for both devices exhibits an ideal 1/f behavior, indicating the uniform distribution of charge fluctuations (Fig. S10). Figure 3e shows the PSD as a function of drain-source current (Ids) of bottom-contact device. The PSD scales quadratically with Ids across frequencies, confirming 1/f noise generation governed by carrier-number fluctuations in the channel. Subsequently, the normalized PSDs (S I/I2 ds) of both bottom-contact and top-contact devices are analyzed at different drain-source voltage (Vds) values, as presented in Fig. 3f. Following the semi empirical equation of S I/I2 ds=A/f, a critical parameter of noise amplitude (A) can be extracted, which marks the level of the charge fluctuation behaviors. As expected, bottom-contact devices exhibit significantly higher A values, confirming the critical role of heterogeneous interfacial defects in carrier modulation under the bottom-contact process (Fig. 3g).

The elucidated physical mechanism of the charge transport behavior in driver transistors propels us to explore the weight-update-dominated luminance characteristics for achieving the in-situ processing capability in the IPPMLED devices. As shown in Fig. 4a, we probe synaptic-shaped display luminance evolution in individual pixels by applying different polarities of the gate-voltage pulse in the driver transistor. Specifically, under a positive pulse, electron accumulation occurs on the surface of the active channel, causing the energy levels to bend downward and enabling trap states below the Fermi level to be filled. While under a negative pulse, the trapped carriers are released, making the traps empty50. Thus, the recorded excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) behavior reshape the light emission of the micro-LED, giving rise to long memory luminescence and transient quenching behaviors in the IPPMLED cell, named excitatory postsynaptic luminance (EPSL) and inhibitory postsynaptic luminance (IPSL), respectively. The insets of Fig. 4a present the complete temporal luminescence profile of EPSL and IPSL phenomena. Notably, the memory luminescence characteristics of EPSL provide a solution for eliminating the inherent blanking intervals in refresh cycles, effectively replacing the pixel-refresh circuitry used in traditional active matrix displays—such as the 1T1C design for maintaining the pixel-driving voltage across the storage capacitor component. This capability critically addresses the need for enhanced visual smoothness in modern intelligent display technologies.

To systematically investigate the multilevel modulation behavior of pixel-level weight updating, a diverse range of driving situations is considered. As illustrated in Fig. 4b, the recorded EPSC curves following the increase in pulse width correspond to a multilevel memory function, which is visualized by the luminance density duration of micro-LEDs. Figure 4c depicts the extracted evolution of EPSC and the corresponding luminance modulation trajectories of micro-LED under varying pulse widths. The characteristic multilevel luminance dynamics, initiated from a dark state, reaching maximum luminance, and subsequently undergoing gradual dimming, clearly demonstrate the pronounced influence of pulse widths on the conductance-dependent luminance characteristics. This scenario can be reproduced under varying pulse amplitudes (Fig. S11), indicating precise electrical modulation of device weights.

The conductance-dependent luminance modulation behavior under diverse driving conditions is further examined. For example, paired-pulse facilitation luminance, akin to the typical feature of short-term synaptic plasticity, is emulated by applying successive driving gate spikes (Fig. S12). It is found that the PPF index decreases gradually with increasing interval time (Δt), following a double exponential function. Given that the refresh frequency is a critical metric for display technologies, driving frequency-dependent EPSL behavior is further investigated. Figure 4d shows that the EPSC and EPSL of the device as a function of driving frequency increase steadily from 5 to 20 Hz. The extracted EPSC gain can reach above 110% at 20 Hz, with the EPSL demonstrating a comparable gain level (Fig. 4e). Figure 4f demonstrates the learning–experience characteristics of the integrated IPPMLED cell under a stimulation protocol of 30 consecutive electrical pulses followed by a 150-s recovery period. Specifically, the EPSC response is shown to increase, surpassing the previous baseline levels, as evidenced by the progressively intensifying light output in the inset image. In summary, the IPPMLED device exhibits diverse conductance plasticity characteristics under different pulse conditions, enabling versatile display operating modes.

On the other hand, to meet the stringent power constraints of edge computing applications, we systematically explored the potential of high-κ dielectrics in replacing SiO2 gate insulator for power consumption optimization51,52. HfO2, as a widely adopted high-κ dielectric material, exhibits good insulating properties and favorable interface characteristics, which are compatible with the designed fabrication process flow of the IPPMLEDs. Figure 5a shows the successfully fabricated 16 × 16 HfO2-based IPPMLED arrays with an increased pixel density of 336 PPI by reducing the pixel pitch. The detailed process optimization for large-scale array integration is provided in Fig. S13 and Fig. S14, showcasing refined methods for large-area vdW material transfer and micro-LED bonding techniques. As expected, the IPPMLED device with dielectric engineering exhibits a notable reduction in the driving voltage, while maintaining good device-to-device uniformity in both Vth and on/off-state across 100 devices (Cv=9.9%) (Fig. S15). Correspondingly, the inherently low power consumption of the synaptic transistor translates into a great energy efficiency advantage for the integrated LED device over current display technologies (Fig. S16 and Supplementary Table 2).

Similarly, ideal nonlinear or triplet-stage voltage-dependent luminance characteristics along with non-volatile memory behavior can be reproduced in the IPPMLED device with HfO2 dielectric engineering. As illustrated in Fig. S17a, when the gate voltage is swept from −4 to +4 V, the device exhibits three well-defined emission regions, characterized by a non-emissive dead zone below 0 V, an approximately linear response regime, and finally a saturation region at intermediate to higher voltages (above 3 V). Furthermore, under programming pulses within a low voltage window of ± 4 V, the device exhibits controllable conductance modulation, mirroring the versatile synaptic plasticity essential for in-memory computing (Fig. S17b–e). Specifically, the conductance state demonstrates non-volatile conductance retention lasting over 150 s with wider-pulse stimulus, highlighting its potential for neural network weight deployment applications. In contrast, the device achieves instantaneous refresh responses under short pulse widths, such as at frequencies of 60 Hz, 120 Hz, and 240 Hz, emphasizing its capability for display refreshing (Fig. S18). Moreover, the HfO2-based IPPMLED demonstrates robust endurance, maintaining stable operation over 104 cycles (Fig. S19). This reliable cycling endurance is critical for subsequent practical in-situ display applications that require long-term device stability.

IPPMLED-enabled in-situ display processing design
The blooming of intelligent edge technologies, especially for edge-oriented visual platforms, demands stringent requirements on efficient and in-situ image data processing capabilities. Conventional display architectures, however, typically offload a variety of tasks—ranging from low-level image processing (e.g., contrast stretching, gamma correction) to high-level functions (e.g., recognition, deblurring)—to external processors53. This physical separation between the processor and the display terminal leads to significant reconstruction latency and extra energy waste, generally causing noticeable visual dizziness54,55. In this work, the IPPMLED features gate-tunable luminance response and in-memory computing capability, offering significant advantages for in-situ display processing. To fully harness the advantages of the proposed devices, both contrast stretching and image recognition are taken as classic examples to exhibit how the IPPMLED array provides a processing platform towards an optimal balance between in-pixel processing and off-chip management.

To comprehensively assess the capability of the proposed IPPMLED in reshaping the intelligent in-situ display landscape, a synchronized display processing pipeline capable of handling representative multi-level tasks has been designed. As shown in Fig. 5b, the input image pixels are first converted into driving voltages according to the device-specific voltage–luminance characteristic, which intrinsically aligns with the contrast-stretching algorithm. In this scheme, low pixel values are mapped to the sub-threshold voltage region (no emission), high values to the saturation region, and intermediate values to the linearly stretched operating region, respectively, thereby enabling immediate contrast-enhanced display. To further optimize the display output, an in-pixel recognition function is proposed. Specifically, the IPPMLED array, serving as the neural network accelerator, enables efficient hardware inference by executing batched weight deployment and in-situ MAC operations. The system subsequently determines whether to trigger MCU-assisted image deblurring according to the obtained recognition results. For instance, if the obtained recognition accuracy falls below a predefined threshold, an advanced deblurring procedure would be activated with the assistance of the MCU (STM32F103RCT6) and back-end processors. Conversely, a higher recognition accuracy would bypass high-level processing to achieve the high-quality display.

In-situ display processing tasks with IPPMLED arrays
To demonstrate the practical in-situ image processing and display capability of the designed IPPMLED, we have established a hardware platform that integrates the IPPMLED array with peripheral circuits to perform in-pixel processing and real-time image display, following the synchronized display processing pipeline (Fig. S20). In specific, each pixel in the IPPMELD array is equipped with independently addressable data and gate lines to enable precise control over input and output terminals (Fig. 5c). The successful operation of the wire-bonded array on a custom-designed printed circuit board (PCB) is demonstrated in Fig. S21, which exhibits uniform pixel illumination across the array.

First of all, the fundamental contrast stretching capability of the fabricated IPPMLED array is investigated. The demonstration employs letter patterns S, H, and U with noticeable noise pixels as the original input images. Specifically, the pixel values of the input image are converted to corresponding voltage signals spanning from −4 to 4 V and injected into the IPPMLED array. The detailed pixel-to-voltage mapping during the contrast stretching procedure is provided in Supplementary Note 2 and Fig. S22. Each pixel element autonomously processes its input voltage based on intrinsic voltage-dependent luminance characteristics, providing real-time optical feedback. Distinctly, with the device-specific contrast stretching, the input images are enhanced by the IPPMLED array that suppresses noise pixels and boosts feature pixels, effectively yielding clear images and operating steadily (Fig. 5d).

The quantitative assessment is further considered to validate the contrast stretching operation, providing better guidance for subsequent refinement of the display architecture. We demonstrate an in-pixel image recognition using an IPPMLED-based feedforward neural network, applied to both original noisy letter images and their IPPMLED-enhanced counterparts (Fig. 5e). As shown in Fig. 5f, the weights obtained from ex-situ software training are extracted, quantized, and then programmed onto the IPPMLED array via non-volatile conductive states, achieving a complete correspondence with the target weight matrix. Subsequently, the letter images (5 × 5 pixels) are transformed into voltage vectors to serve as inputs, where parallel MAC operations are performed with the deployed weights, enabling highly parallel, low-power analog computing and in-situ execution of the inference process within the IPPMLED. Figure 5g illustrates a representative current summation process across the array during this operation. The resulting MAC values are temporarily stored in the readout circuit and buffer registers, after which weight refreshing and array reuse enable the processing of subsequent batches, ultimately yielding the recognition result. As expected, the IPPMLED-enhanced images demonstrated a high inference accuracy of 99.29%, outperforming the unprocessed images (79.81%) (Fig. 5h and Fig. S23), enabling high-quality display output while eliminating the need for further processing. Notably, the hardware inference accuracies exhibit only a minor degradation of 0.1–0.9% compared to their software counterparts (Fig. S24), which strongly validate the functional reliability of the IPPMLED-based in-situ image display system.

Methods
Device fabrication
The GaN-based blue LEDs are fabricated beginning with the metal-organic chemical vapor deposition (CVD) growth of n-GaN, InGaN/GaN multiple quantum well, and p-GaN epitaxial layers on sapphire substrates. The mesa structure is then defined by inductively coupled plasma etching to expose the n-GaN layer, followed by sputtering and patterning of an indium tin oxide current spreading layer. An Ag reflective layer is subsequently deposited via electron-beam evaporation to enhance light extraction efficiency. Device isolation is achieved through plasma-enhanced CVD of a SiO2 layer with via openings formed by dry etching. Finally, patterned metal electrodes are fabricated by electron-beam evaporation to complete the pixel array. A detailed flowchart of the fabrication process is provided in Fig. S2.

To fabricate the IPPMLED array, local gate terminals are first patterned using a laser direct writing (LDW) lithography system. Ti/Au gate metals with thicknesses of 5/30 nm are then deposited via electron-beam evaporation, where Ti serves as an adhesion layer to improve Au-substrate bonding and form ohmic contact with the semiconductor channel. A SiO2 dielectric layer with a thickness of 300 nm is subsequently fabricated by CVD. Then, bottom-contact source and drain electrodes are fabricated, followed by the location of a MoS2 film (Six Carbon Technology) and channel patterning via a wet-transfer technique and plasma etching. The indium (In) electrode pattern is then defined by LDW, and a low-pressure e-beam evaporation process is used to deposit the In layer (1.6 μm), forming a self-aligned interface for subsequent micro-LED integration. Finally, TCB is employed to precisely bond micro-LEDs onto the In bumps, completing the flip-chip bonding process. Furthermore, this fabrication scheme is successfully extended to fabricate IPPMLED arrays featuring an HfO2 dielectric layer. A uniform 20 nm HfO2 film was deposited by atomic layer deposition, a technique selected owing to its great conformality and precise thickness control at the atomic scale.

Structural analysis and electrical characterization
The surface morphology of the samples is captured using a Focused Ion Beam-Field Emission Electron Microscope (FIB–FESEM, Helios G4 UX), which is also used for sample preparation for TEM. High-resolution imaging and element analysis are performed on the samples using a High-Resolution Transmission Electron Microscope (JEM-2100F) coupled with an Energy Dispersive X-ray Spectroscopy (EDS) system. Electrical performance testing of the devices is conducted using a Semiconductor Parameter Analyzer (Keysight B1500A equipped with a WGFMU). For Raman spectroscopy, a continuous-wave laser (MSL-U-532, 532 nm) is used as the excitation source, and a Raman spectroscopy system is setup with an HRS300 spectrometer and an 1800 lines/mm diffraction grating to collect and analyze the Raman signals from the samples. The optical performance of the micro-LEDs is further characterized by measuring the luminance with a COLOR VISIONS V-2000 optical testing system and the EQE with an EVERFINE AIS-2_0.5 m integrating sphere, respectively.

Training and inference of the IPPMLED-based neural network
A multilayer perceptron is developed for character classification using a custom dataset of 5 × 5 grayscale letter images. The model adopts a three-layer, fully connected architecture, which includes two hidden layers with 128 neurons each and an output layer corresponding to the 26 character categories. The total number of trainable parameters of the entire neural network amounts to 23194. A Rectified Linear Unit activation function follows each hidden layer to enhance the model’s nonlinear representational capacity. The network is trained for 250 epochs using the AdamW optimizer, with the cross-entropy loss serving as the optimization objective. To evaluate generalization performance, the dataset is divided into separate training and validation subsets, and validation accuracy is recorded after each epoch. The dataset comprises 26,000 grayscale images across 26 classes (A–Z), with 1000 samples per class. Each character is represented as a 5 × 5 pixel array. To improve robustness against input perturbations, controlled-amplitude random noise is applied for data augmentation. All image samples are normalized prior to being fed into the network.

For hardware-accelerated neural network inference, an integrated system comprising an HfO2-based IPPMLED array, peripheral electronics (INA226A ADC, DAC7311 DAC), and a microcontroller unit (MCU, STM32F103RCT6) is developed. The HfO2-based IPPMLED array is configured in a matrix layout and wire-bonded onto a PCB (ASM Pacific Technology, IHAWK AERO). Programming voltages within the range of ± 4 V are supplied by an NI-PXI 4163 modular instrumentation system, integrated with a 24-channel PXI-2532B multiplexer for row and column addressing. During inference, the trained synaptic weights are deployed onto the IPPMLED array via non-volatile conductance modulation. Each input image (5 × 5 pixels) is flattened into a 25 × 1 vector, divided into five sub-vectors, and sequentially encoded into voltage signals proportional to pixel intensity for in-situ MAC operations with the mapped 5 × 5 weights on the array. The resulting output currents are then amplified and converted by peripheral readout circuitry, with the processed signals being temporarily stored in buffer registers. Following this, the array undergoes weight refreshing and is reused to process subsequent image batches, ultimately generating the final recognition result.

Data availability
Relevant data supporting the key findings of this study are available within the article and the Supplementary Information file. All raw data generated during the current study are available from the corresponding authors upon request.

Code availability
The codes used for simulation and data plotting are available from the corresponding authors upon request.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This study introduces an in-pixel processed micro-LED display (IPPMLED) architecture that integrates MoS₂-based synaptic transistors with micro-LEDs for combined pixel driving and memory-related functionality. The system demonstrates luminance levels above 3×10⁵ cd/m², integration density of 14,000 units/cm², and operation up to 5000 Hz, with reported cycling stability. Using voltage-luminance modulation and multilevel conductance characteristics, the device is applied to image enhancement and MCU-assisted deblurring. A proof-of-concept 5×5 matrix is presented, showing noise suppression and image reconstruction, with recognition accuracy on the Fashion-MNIST dataset improving from 83.79% to 96.31%. While these results suggest the potential of combining display and processing functions within individual pixels, the demonstrations are limited in scale, and further work is needed to verify scalability, power efficiency, and stability in practical contexts. The concept is of interest, but revisions are necessary to clarify the scope of the hardware contribution and address methodological issues. The detailed comments are as follows:\n1. The devices operate at relatively high gate voltages due to the use of a 300 nm SiO₂ dielectric, which raises concerns regarding energy efficiency for the portable applications (e.g., AR/VR systems). Although the supplementary information briefly mentions HfO₂ as a possible replacement to lower the operating voltage, the manuscript does not provide a systematic analysis of overall power consumption. For targeting edge computing applications, such quantitative evaluation is essential to support the claimed applicability.\n2. In Figure 4f, the authors demonstrate potentiation behavior through output current changes under repeated pulses, illustrating a learning-forgetting-relearning cycle. While this result confirms short-term synaptic plasticity, the analysis is limited to tens of seconds. For establishing robust memory functionality, additional data on long-term retention and potentiation–depression characteristics (linearity, symmetry) are necessary.\n3. A central claim of the manuscript is that the device enables hardware-level contrast stretching by exploiting its piecewise voltage-luminance response. However, the detailed explanation of this process, including the mapping relationship and supporting histograms, is presented only in the Supplementary Information. Given its importance to the overall contribution, this description should be included in the main text to substantiate the in-situ processing claims. Otherwise, the role of hardware in the contrast stretching demonstration remains unclear.\n4. The description of the deblurring demonstration lacks sufficient detail. Although the manuscript states that the process is “MCU-assisted,” it does not clearly explain which parts are carried out by the device and which by the MCU. Moreover, the algorithmic details are missing. It is not specified whether a neural network was used, what network architecture or parameters were adopted, or how the computation was divided between the MCU and the device. Without this information, it is difficult to determine whether the demonstration truly reflects in-pixel processing or is largely dependent on external computation. A clearer and more rigorous explanation of the deblurring methodology is therefore essential.\n5. Across the demonstrations, it is unclear whether true in-situ processing was actually carried out at the hardware level using MoS₂ synaptic transistors. The descriptions of contrast stretching and MCU-assisted deblurring do not provide sufficient evidence that these functions were intrinsically realized within the device rather than externally emulated. For the central claim to be convincing, the authors should present a more precise explanation of how in-situ processing was implemented, along with clear experimental evidence demonstrating that the computation indeed occurred in the hardware.\n6. Figure 1a is described simply as a “schematic diagram of the IPPMLED architectures and functional implementation,” but the caption lacks sufficient detail to help readers interpret the figure. the right-hand side shows an image processing part that is only described as “functional implementation” in the caption. However, it is unclear how image processing operations are mapped onto the pixel-level hardware. Also, the label “ADMLED” appears, but this abbreviation is never defined in the manuscript. Since this schematic diagram is crucial to illustrate the computational aspect of architecture, the authors should provide a clearer explanation of the processing pathway and its correspondence with the device functions.\n7. In Figure 2e, the average I_on is described in the text as ~2.6×10⁻⁶A, but the figure label appears to indicate I_on(x10⁶A), which is misleading. Similar typographical errors (e.g., fig.3b, “matrixes” instead of “matrices”) are present. Careful revision is needed to avoid confusion.", "reviewer_2": "This manuscript presents a novel in-pixel processed display-driven micro-LED display (IPPMLED) architecture that integrates micro-LEDs with molybdenum disulfide (MoS2) in-memory computing transistors. The goal of this architecture is to overcome the latency and energy consumption bottlenecks of conventional off-pixel processing by co-locating image processing and display at the pixel level. The authors fabricated a 5x5 IPPMLED matrix and demonstrated its capabilities in both low-level and high-level image processing.\nThe reviewer believes that the following revisions will help improve the quality of the manuscript.\nComment #1: The authors’ claims about “high-resolution display” are ambitious given that the hardware demonstration is limited to a 5 x 5 matrix. Wafer-scale, high-uniformity MoS2 TFT backplanes remain challenging (many processes still rely on flake transfer or small-area CVD growth), whereas micro-LEDs are already proven at very high pixel densities. This creates a scalability tension between the transistor backplane and the emitter array. While the reported pixel density of 300 PPI is notable, please provide a credible scaling roadmap and demonstrate a larger matrix to validate the claim.\nComment #2: The current array performs contrast enhancement task, but practical image processing pipelines also require low-level (e.g., color correction, gamma correction), mid-level (e.g., segmentation, feature extraction), and high-level (e.g., recognition) processing. Please clarify how these additional functions would be handled by the in-pixel architecture versus off chip.\nComment #3: The main limitation of trap-based synaptic devices is slow processing, which may cause image ghosting. In Fig. 4a-c, the postsynaptic current appears to stabilize over tens of seconds, which conflicts with high refresh rate operation. Please report the relevant time constants at the operating point and demonstrate video-rate updates without image persistence. If the display mode does not rely on slow synaptic effects, please state this explicitly and provide measurements that confirm millisecond scale settling suitable for typical display rates of 60 to 240 Hz.\nComment #4: Please expand the micro-LED section to include fabrication flow and key device metrics such as luminance, current density, and EQE to clarify emitter performance.\nComment #5: In Figure 2e, the variation of threshold voltage appears large for display-class uniformity, which could limit high-resolution operation. Please describe compensation methods and pathways to enhance the uniformity.\nComment #6: Only blue micro-LED devices are demonstrated. Please discuss how the in-pixel processing systems scale to multi-color RGB displays.\nComment #7: In Fig. 3b, it seems that the required gate voltages are quite high. Is this common, and realistic for actual display operation? If not, are there ways/roadmaps to reduce this?\nComment #8: The demonstrated pixel density of ~300 PPI is insufficient for microdisplays which typically require much higher PPIs (>2000) to reduce screen door effects. Therefore, the references to microdisplays in the abstract and introduction seem a bit misleading.\nComment #9: In Table S1, I think it could be better to also display the integration density in PPIs since it’s more commonly used for displays than units/cm2.\nComment #10: The authors should provide a more thorough analysis of the device's power consumption, comparing that of IPPMLED to conventional off-pixel display system. This would provide a more complete picture of the energy efficiency benefits.", "reviewer_3": "I co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature Communications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career Researchers who co-review manuscripts."}, "author_response": "The authors deeply thank Reviewer #1 very much for carefully reviewing our manuscript and providing us with professional and constructive comments, which have been valuable in enhancing the quality and stringency of our work. Also, we sincerely appreciate that such positive feedback on its significance can be obtained from Reviewer #1. In response to Reviewer #1’s suggestions, additional array fabrication experiments, rigorous thinking of the hardware contribution, systematic literature survey, practical hardware implementation, and corresponding modifications have been made, including: (1) Exploration of device scaling pathways and supplemental experiments for fabricating larger IPPMLED array (16×16), achieved through the optimization of large-area material transfer and micro-LED bonding processes (Figure R1). (2) Reduction of operating voltage and power consumption via dielectric layer engineering, coupled with a systematic literature review to benchmark the power efficiency of the IPPMLED against current display systems (Table R1). (3) Reorganization of the IPPMLED-based display system architecture and revision of the corresponding figures, providing a clearer delineation of processing roles and a refined balance between in-pixel and off-chip computing (Figure R4 and Figure R8). (4) Hardware implementation of image display enhancement and neural network deployment to solidify the hardware contribution of the work (Figure R3, Figure R5, Figure R6, and Figure R7). All revisions have been carefully incorporated into the manuscript, with detailed point-by-point responses to Reviewer #1’s comments provided in the revised version, where corresponding modifications are clearly highlighted.\n[... (omitted for brevity, contains detailed responses to all 10 comments from Reviewer 2 and 7 comments from Reviewer 1)]"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The revised manuscript addresses many of the earlier concerns, with improvements in overall organization, clearer figure annotations, and added benchmarking context. Nonetheless, several critical points remain unresolved and currently preclude a clear assessment of the hardware contribution and system-level viability.\nComment#1\nWhile the HfO2 gate lowers the threshold for read/display operation, the conductance programming for in-memory computing still relies on high amplitude pulses ( −30V to −35V), leaving open questions about true low-power operation. The required programming voltages also raise concerns about device lifetime. Providing endurance data under these conditions (e.g., cycles-to-failure or stability over 10^3 - 10^4 cycles) would help assess reliability.\nComment#2\nFig. 4b and Fig. S17 do not report the essential write/read pulse parameters (amplitude, width, inter-pulse interval, and related settings), leaving the methodology unclear and preventing meaningful energy or latency estimates.\nComment#3\nPlease define “post-training” and “post-development” explicitly in both the main text and the Fig. 5f caption and clarify whether the weights were obtained ex-situ (software training/simulation) and subsequently programmed into hardware. Also, since the input vector is 25×1 (from a 5×5 image) whereas the weight map is shown as 5×5, a short explanation of how the 25×1 input corresponds to the 5×5 weight visualization would improve interpretability. (In Fig. 5f)\nComment#4\nThe manuscript does not clearly describe the neural network architecture (layers, activations, parameter count), the training dataset (type/size) and split, or software-hardware accuracy comparisons. Without these, reproducibility is limited and the hardware claim is difficult to interpret.", "reviewer_2": "I have carefully reviewed the authors’ rebuttal and the revised manuscript describing the IPPMLED architecture. The authors have adequately addressed all the major concerns raised in the initial review. In particular, the transition from a 5×5 proof-of-concept to a 16×16 IPPMLED array demonstrates the scalability of the design and is supported by appropriate statistical analysis of device-to-device uniformity. Furthermore, the integration of high-ĸ HfO2 dielectrics effectively reduces the driving gate voltages to a more practical range of -4 V to +4 V, successfully addressing the concern regarding high operating voltage and energy efficiency.\nThe revised manuscript also provides thorough technical validation for the system’s high-speed operational capabilities. By exploiting the short-term plasticity of the synaptic transistors, the authors demonstrate stable image refreshing at standard rates of 60 Hz, 120 Hz, and 240 Hz, which clarify how the device maintains display performance alongside its in-memory computing functions. The inclusion of detailed fabrication flowcharts and comprehensive micro-LED characterization metrics further enhances the technical rigor of the manuscript. Given these substantial improvements and the successful experimental validation of the proposed architecture, I believe the revised manuscript now meets the standards for publication in Nature communications.", "reviewer_3": "I co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature Communications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career Researchers who co-review manuscripts."}, "author_response": "The authors would like to express their sincere gratitude to Reviewer #1 for carefully reviewing our manuscript and providing us with valuable feedback and constructive suggestions, which have greatly enhanced the quality of this work. In response to Reviewer #1’s insightful comments, additional explanations have been provided regarding conductance programming in practical image processing applications, the deployment of input vectors and weights, and details of the neural network architecture. Furthermore, we have supplemented the experimental data with endurance characteristics on different IPPMLED configurations (Figure R1) and software-hardware inference accuracy comparisons (Figure R2). All revisions have been carefully incorporated into the manuscript, with detailed point-by-point responses to Reviewer #1’s comments provided in the revised version, where corresponding modifications are highlighted.\n[... (omitted for brevity, contains detailed responses to all 4 comments from Reviewer 1)]"}, {"round": 3, "reviewer_comments": {"reviewer_1": "The second revision provides the additional data and clarifications needed to address the outstanding concerns from earlier rounds. The organization is improved, figure annotations are clearer, and the new methodological details allow a fair assessment of the hardware contribution and system feasibility. With the current revisions, the manuscript is suitable for publication in Nature Communications."}, "author_response": ""}]

Decision letter