High-κ samarium oxysulfate dielectric for two-dimensional electronics with enhanced gate coupling

Domain: chemistry
Published: 2025-12-29
Editorial outcome: major_revision

Abstract
Layered dielectric materials and their van der Waals (vdW) heterostructures offer high potential for next-generation two-dimensional (2D) electronic devices, but materials that combine a wide band gap and high dielectric constant are rare. Here, we present the controllable synthesis of quasi-vdW layered samarium oxysulfate (Sm2O2SO4) single crystals via a molten-salt-assisted chemical vapor deposition (CVD) method. These atomically thin crystals exhibit remarkable dielectric properties, including a wide band gap (~5.54 eV), high dielectric constant (~18), robust breakdown voltage (>12 MV cm-1) and good thermal reliability. By integrating ultrathin Sm2O2SO4 nanoplates with 2D molybdenum disulfide (MoS2) via vdW forces, we fabricate field-effect transistors (FETs) showing a subthreshold swing down to 65.2 mV dec-1, hysteresis down to 5.4 mV, on/off current ratios of ~109, and gate leakage currents down to around 7×10-7 A cm-2. Furthermore, a high gate coupling ratio (GCR ~0.83) non-volatile memory device was developed based on the MoS2/h-BN/MLG/Sm2O2SO4/MLG heterostructure. The flash memory achieves ultrafast (~50 ns) programming/erasing operations, robust endurance (>2000 cycles) and long-term retention (>10 years). This work shows promising results for the integration of Sm2O2SO4 as a high-κ dielectric in future 2D devices, with implications for low-power, high-performance electronics.

Introduction
Two-dimensional (2D) semiconductors, with high carrier mobility, tunable band gaps, and atomic-scale thickness, are widely regarded as ideal channel materials for future technologies that aim to surpass silicon-based integrated circuits and memory computing architectures1–3. In recent years, floating-gate field-effect transistors (FGFETs) based on 2D materials have gained widespread attention4–13. 2D materials such as MoS2, ReSe2, HfS2, and MoTe2 demonstrate excellent electric field control, effectively reduce parasitic defect capture, and facilitate the scaling of memory and computing systems, thereby showing significant advantages in high-density integration14,15. However, the lack of high-quality blocking dielectric materials limits further improvements in low-power and ultrafast FGFET performance. Dielectrics must not only exhibit excellent electrical properties but also achieve low operating voltage, low leakage current, and stable thermal and electrical characteristics16,17.

Conventional high-κ oxides (HfO2, ZrO2, Ta2O5) enhance electrostatic control but are limited by atomic layer deposition (ALD) processes, which cause crystallization at the nanoscale and introduce interface defects, reducing device reliability18–21. Additionally, in-situ deposition may induce interface trap states, increase charge scattering, degrade carrier mobility, and elevate leakage current, restricting their applicability in 2D devices. Meanwhile, silicon-based floating-gate memory suffers from high tunneling barriers at the Si/SiO2 interface and dangling bonds, leading to a low gate coupling ratio (GCR), high power consumption, and short data retention times22–24. High-quality single crystal dielectric materials such as h-BN, Gd2O3, MgNb2O6, Eu2SO4, and Mn2O3, due to their excellent interface quality, have been widely used in 2D electronic devices as vdW dielectric materials, preserving the intrinsic properties of 2D semiconductors25–30. Recently, all-2D floating-gate memory utilizing h-BN as a blocking layer has been demonstrated, achieving atomically sharp interfaces and enabling miniaturization for high-density integration8. However, its low dielectric constant (κ = 2–4) limits electrostatic control, preventing further scaling of the equivalent oxide thickness (EOT), and constrains GCR improvement, ultimately affecting storage efficiency. Furthermore, an ideal gate dielectric should possess a wide band gap to suppress leakage current, reduce interface state density, and enhance breakdown strength. For example, perovskite strontium titanate (SrTiO3) has an ultrahigh dielectric constant and holds promise for sub-1 nm EOT applications, but its relatively narrow band gap (~3.2 eV < 5 eV) leads to excessive leakage current, limiting its potential for future 2D CMOS applications31,32. Therefore, there is an urgent need to develop new dielectric materials with high GCR, a high dielectric constant, low leakage current, and stable interfaces to advance 2D electronics and storage technologies.

In this study, we report the successful synthesis of atomically thin samarium oxysulfate (Sm2O2SO4) dielectric single crystals using a molten-salt-assisted chemical vapor deposition (CVD) method. This quasi-vdW layered Sm2O2SO4 single crystal exhibits remarkable potential as a gate dielectric for 2D heterostructure devices due to its high dielectric constant (~18), wide band gap (~5.54 eV), high breakdown field strength (>12 MV cm−1), and excellent thermal and electrical stability. Molybdenum disulfide (MoS2) with Sm2O2SO4 gate dielectrics operates with minimal hysteresis of 5.4 mV, a subthreshold slope (SS) of 65.2 mV dec−1, an on/off current ratio of 109, a low top-gate leakage current of 7×10−7 A cm−2, and high operational reliability at 500 K. Furthermore, leveraging the wide band gap and high dielectric performance of Sm2O2SO4, we constructed a low-power (2.97 pJ) all-2D floating-gate memory device based on a MoS2/h-BN/MLG/Sm2O2SO4/MLG vdW heterostructure (here h-BN stands for hexagonal boron nitride and MLG stands for multilayer graphene), where Sm2O2SO4 was employed as a blocking layer. The resulting FG device exhibits outstanding non-volatile memory performance, including a low-voltage storage window (<3 V), high on/off ratio (>107), long data retention (>10 years), stable endurance (>2000 cycles) and fast (~50 ns) programming/erasing operations. These characteristics stem from its high-κ properties, which enhance GCR (~0.83), and the atomically sharp vdW interface. These findings highlight the potential of Sm2O2SO4 as a promising high-κ layered dielectric material for 2D nanoelectronics and high-GCR floating-gate memory devices.

Results
Controlled growth and structural characterization of Sm2O2SO4
As shown in Fig. 1a, europium oxysulfate Sm2O2SO4 crystallizes in the tetragonal lattice with an I42m space group, and it possesses a quasi-vdW layered structure with a covalently saturated surface in the [001] direction. From the side view of the Sm2O2SO4 structure, the crystal structure consists of alternating [SmO]+ cationic layers and [SO4]2− anionic layers via electrostatic forces instead of vdW attractions. From the top view, the structure appears as consisting of multiple [SmO] units, where the Sm atoms form the framework and the O atoms occupy the central positions, with each Sm atom coordinated to two O atoms, creating a [SmO] subunit. Additionally, the [SO4] group is symmetrically placed around the [SmO] units, with the S atom at the center and the four O atoms positioned around it in a tetrahedral arrangement.

High-quality ultrathin Sm2O2SO4 nanoplates were synthesized using the molten-salt-assisted chemical vapor deposition (CVD) system, employing mica as growth substrate, Sm2(SO4)3·xH2O as the growth precursor and KI as eutectic melt (Fig. 1b and Supplementary Fig. 1 for details). During the melting process, molten salts promote the dissolution of precursors, ion diffusion, and the assembly of basic units, with nucleation and growth primarily occurring in the lateral direction based on the reaction process as follows: Sm2(SO4)3·xH2O + 2H2 + KI → Sm2O2SO4 + 2SO2 + (2+x)H2O + KI. Optical microscopy (OM) images confirm that the Sm2O2SO4 nanoplates exhibit a transparent rhombic-like shape and atomically thin nature, with maximum lateral sizes of 50 μm (Fig. 1c and Supplementary Fig. 2a). Supplementary Fig. 2c shows the atomic force microscope (AFM) image of a typical Sm2O2SO4 nanoplate, which features atomically smooth surface and ultrathin thickness of ~5.2 nm. The crystal size and thickness can be commendably controlled by modulating the growth parameters (Supplementary Fig. 3). The statistical results, as shown in Supplementary Fig. 3c, f, and i, indicate that the lateral crystal sizes are mainly distributed in the range of 20-60 μm, with a concentration around 40 μm. Besides, the as-synthesized Sm2O2SO4 nanoplates are prone to wrinkling when washing residual salts, indicating a weak adhesion force between nanoplate and mica substrate, originating from the vdW epitaxy mechanism (Supplementary Fig. 4)29. Therefore, ultrathin Sm2O2SO4 nanoplates can be easily released from the growth substrate and transferred onto other target substrates or constructing artificial heterostructures. Density functional theory (DFT) calculations are performed to investigate the electronic band structure of layered Sm2O2SO4. As plotted in Fig. 1d, Sm2O2SO4 displays a large indirect band gap of ~5.67 eV, with the conduction band minimum (CBM) and valence band maximum (VBM) both located at the Γ and near the X points of the 2D Brillouin zone, respectively. The conduction band is made up hybridized Sm p and S p states associated with the empty O 1s lone pair, while the valence band consists mainly of S p states. Furthermore, we analysed the optical band gap from the absorption spectrum using ultraviolet-visible spectroscopy and found that the band gap of ultrathin Sm2O2SO4 nanoplates is ~5.54 eV, which is higher than that of the most crystalline high-κ dielectrics such as SrTiO3 (3.2 eV)32, Bi2SeO5 (3.9 eV)33, Sb2O3 (4.06 eV)34 and Bi2SiO5 (3.79 eV)35. To study the chemical structure and crystallinity of Sm2O2SO4, Raman and Photoluminescence (PL) spectra measurements were conducted. As shown in Fig. 1e, the Sm2O2SO4 crystal exhibits four vibrational modes (ν1, ν2, ν3 and ν4) corresponding to the free [SO4]2− ions with Td symmetry, and two prominent peaks at 333.4 and 418.8 cm−1, which are attributed to the Sm-O fundamental modes, consistent with previous experimental Raman results36. We systematically performed Raman spectroscopy on Sm2O2SO4 crystals of different thicknesses (Supplementary Fig. 5). As the thickness decreases, the peaks (ν1, ν2, ν3 and ν4) become less pronounced, which can be attributed to the weaker intensities of four vibrational modes in few-layer Sm2O2SO4 nanoplates. PL spectra of the bulk Sm2O2SO4 crystal is recorded using excitation wavelength 532 nm in Supplementary Fig. 6a. Four peaks can be observed at 562 nm, 608 nm, 644 nm, and 658 nm, corresponding to the characteristic luminescent bands of the Sm3+ ions, arising from the transitions of the 4G5/2 state to the 6H5/2, 6H7/2 and 6H9/2 multiplets, respectively. However, as the thickness decreases, the three peaks at 608 nm, 644 nm, and 658 nm become less pronounced, which can be attributed to the reduced luminous efficiency in few-layer Sm2O2SO4 nanoplates due to enhanced surface effects and non-radiative recombination pathways37,38. Supplementary Fig. 6b shows the cathodoluminescence (CL) spectra of ultrathin Sm2O2SO4 nanoplates transferred onto a SiO2/Si substrate. Two distinct peaks are observed at 606 nm and 652 nm, which correspond to the electronic transitions labeled 6H7/2 and 6H9/2 due to the f-f transitions of Sm3+ ions. Additionally, the chemical states of ultrathin Sm2O2SO4 nanoplates were analyzed using X-ray photoelectron spectroscopy (XPS) (Fig. 1f and Supplementary Fig. 7). The binding energies of 1083.5 and 1110.4 eV confirm the presence of Sm3+ 3d5/2 and Sm3+ 3d3/2, respectively. The O 1s binding energies of 529.2 and 532.1 eV are attributed to Sm-O and [SO4]2− species, while the S 2p binding energies of 168.9 and 170.1 eV are assigned to Sm-S.

Scanning transmission electron microscopy (STEM) studies are used to investigate more information about the crystal structure of the transferred ultrathin Sm2O2SO4 nanoplates (Supplementary Fig. 8a). The typical high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) images of the rhombic Sm2O2SO4 crystal (Fig. 1g and Supplementary Fig. 8b) along the [001] zone axis is shown in Fig. 1h and Supplementary Fig. 9a, b. The intuitive plan-view STEM images reveal a highly-crystallized tetragonal crystal structure with no atomic vacancies or lattice deformation. The lattice spacings are estimated to be ~4.15 and ~2.93 Å, as verified by the enlarged HAADF-STEM image (Fig. 1i), matching well with the structure of (100) and (110) plane of the tetragonal phase Sm2O2SO4 crystal. Besides, the selected-area electron diffraction (SAED) pattern along the [001] zone axis shows the corresponding tetragonal structure. The energy dispersive X-ray spectroscopy (EDS) elemental mapping confirms the uniform distribution of Sm, S and O throughout the entire nanoplate (Supplementary Fig. 9c). To identify the layered characteristic in Sm2O2SO4 single crystal, a nanoplate was cut using a focused ion beam (Supplementary Fig. 10), followed by atomic-resolution cross-sectional HAADF-STEM imaging. Figure 2j, k and Supplementary Fig. 11 show atomic-resolution STEM imaging along three-zone axes ([100], [130], and [110]) with a regular layered arrangement, as well as corresponding atomic models of Sm2O2SO4. The alternative stacking of [Sm2O2]2+ and [SO4]2− layers with a layer space of 7.4 Å is observed, and the measured lattice fringes of 4.15, 2.93, and 1.72 Å can be attributed to the lattice planes of (010), (110), and (310), respectively. These results indicate the successful fabrications of the 2D quasi-vdW layered Sm2O2SO4 single crystal.

Dielectric properties of Sm2O2SO4
Dielectric constant, and breakdown field strength are key parameters that determine the performance of dielectric materials. To evaluate the dielectric properties of layered Sm2O2SO4 single crystals, dual-gate graphene FETs were fabricated by integrating graphene channels with ultrathin Sm2O2SO4 nanoplates on a p-Si substrate with a 285 nm SiO2 capping layer (Fig. 2a). The thicknesses of Sm2O2SO4 (15 nm) and graphene (single layer) were determined by AFM and Raman spectroscopy, respectively (Fig. 2a and Supplementary Fig. 12). In this setup, Sm2O2SO4 and SiO2 serve as the top- and back-gate dielectrics, respectively. The charge carriers in the graphene channel can be controlled simultaneously by applying top- and back-gate voltages28,30,39,40. The top-gate Dirac point voltage (VDirac, tg) can be modulated by the back-gate voltage (Vbg), as shown in Fig. 2b. Using a parallel plate capacitor model for the top- and back-gate, the slope of VDirac, tg with respect to Vbg corresponds to the ratio of the back-gate capacitance to the top-gate capacitance (C SiO2/C Sm2O2SO4), as expressed in the following equation:

C SiO2 / C Sm2O2SO4 = ε SiO2 t Sm2O2SO4 / ε Sm2O2SO4 t SiO2 (1)

where ε Sm2O2SO4 and ε SiO2 (3.9) are the dielectric constants of Sm2O2SO4 and SiO2, respectively, and t Sm2O2SO4 and t SiO2 are their respectively thicknesses, we obtain the dielectric constant of 16.9 for 15-nm-thick Sm2O2SO4 from this device (Fig. 2c). To obtain the effective dielectric constant of Sm2O2SO4 more precisely, more dual-gate graphene FETs are fabricated using Sm2O2SO4 with various thicknesses as the top-gate dielectric (Supplementary Fig. 13). Additionally, the parallel-plate capacitor device with vertical metal-insulator-metal (MIM) structure were also constructed to characterize the dielectric properties of Sm2O2SO4 (Supplementary Fig. 14a). In this setup, the Sm2O2SO4 layer was sandwiched between two vertically stacked Cr/Au electrodes on a quartz substrate. The corresponding capacitance–voltage (C-V) measurements at various frequencies (f) are shown in Supplementary Fig. 14b. The effective permittivity (εeff) can be calculated calculated using the following equation:

Ceff = Aε0 εeff / t (2)

in which Ceff is the measured capacitance, A is the effective area, t is the thickness of the Sm2O2SO4 layer, and ε0 is the vacuum permittivity. Thus, the Sm2O2SO4 nanoplate with a thickness of 14.6 nm demonstrated a high εeff of 17.8, which is much higher than that of 2D hexagonal boron nitride (h-BN) (~5)25 and comparable with that of traditional high-κ oxide dielectrics such as HfO241, ZrO242 and Al2O343. As shown in Fig. 2d and Supplementary Fig. 15, the capacitance exhibited a significant dependence on the thickness of the Sm2O2SO4 nanoplates. Correspondingly, the εeff of Sm2O2SO4 with different thicknesses is plotted in Fig. 2e, which shows a decreasing trend as the thickness reduces and can be well described by the typical ‘dead layer’ model due to the existence of interfacial capacitance (Supplementary Fig. 16)44,45. The corresponding EOT for Sm2O2SO4 can be calculated by the following equation:

EOT = 3.9 t / εeff (3)

where 3.9 is the dielectric constant of silicon oxide. Notably, the EOT shows a near-linear relationship with the Sm2O2SO4 thickness, implying that a 1.7 nm EOT can be achieved with a thickness of 6.5 nm nanoplate (Fig. 2e).

Beyond the dielectric constant, a low leakage current and high breakdown strength (Ebd) of dielectric materials are also important performance parameters for reducing device power consumption46–48. The Sm2O2SO4 nanoplates sandwiched between Cr/Au electrodes demonstrate the large Ebd in the range 12-15 MV cm−1 (Fig. 2f), almost triple that of perovskite SrTiO3 membranes32, which are significantly higher than the required by the International Technology Roadmap for Semiconductors (ITRS)49. The thermal stability and electrical reliability of Sm2O2SO4 nanoplates were also evaluated, as these properties are critical for ensuring their performance in device applications. To ensure the reliability of the breakdown field strength results, we performed at least three independent measurements on different samples, as shown in Supplementary Fig. 17. All experimental results indicate that the breakdown field strength exceeds 10 MV/cm for samples of different thicknesses. Thanks to its high crystallinity and wide band gap, the Sm2O2SO4 nanoplates maintain a high breakdown field strength of up to 10 MV/cm even at a high testing temperature of 500 K, demonstrating the robust breakdown performance of Sm2O2SO4 at various thicknesses. They exhibited a low leakage current of the order of 10−2 A cm−2 under 7.5 MV cm−1 (Fig. 2g). Low leakage current can be attributed to the well-defined vdW gap, which primarily improves leakage and stability by introducing an additional barrier at the interface to extend the carrier tunneling path, suppressing the interference of interfacial defects with charge transport, and alleviating stress concentration induced by lattice or thermal mismatch. To further confirm the potential of Sm2O2SO4 as a dielectric, the relationship between the breakdown field strength and corresponding dielectric constant of currently reported dielectrics was summarized in Fig. 2h. Given the superior dielectric properties of crystalline Sm2O2SO4 nanoplate, it is a promising insulating candidate for integration into high-performance FETs with 2D semiconductor channels.

High-performance 2D FETs with Sm2O2SO4 as gate insulator
To investigate the dielectric modulation effect of Sm2O2SO4, MoS2 FETs with Sm2O2SO4 as the top-gate dielectric were fabricated using the mechanical stacking method. (Supplementary Fig. 18). The device structure is shown schematically in Fig. 3a. The Sm2O2SO4/MoS2 top-gate FET was fabricated on a SiO2/Si substrate, utilizing Cr/Au as the source and drain electrodes. To ensure that Cr/Au exhibits a low contact resistance, we extracted the contact resistance of 0.97 kΩ·μm (see Supplementary Note 1 and Supplementary Fig. 19). It is important to emphasize that the focus of this work is not on the scaling of contact resistance. The output curves of the Sm2O2SO4/MoS2 FET show excellent gate control, as evidenced by the linear Ids-Vds curve at low Vds and saturation at high Vds, and exhibit a good ohmic contact between the electrodes and MoS2 (Fig. 3b). The corresponding transfer curves demonstrates a high on/off ratio of 107 and low gate leakage currents as low as 7×10−7 A cm−2 across a Vtg sweep from −1.0 to 1.0 V (Fig. 3c). There was a sharp increase in drain current in the subthreshold region, with an average subthreshold slope (SS) of ~65.2 mV dec−1 and a low drain-induced barrier lowering (DIBL) value of ~21 mV/V (Supplementary Fig. 20). Particularly, remains close to 60 mV dec−1 across more than two orders of magnitude of the drain-source current and stays below 100 mV dec−1 over three orders of magnitude of Ids (Fig. 3d). More importantly, we also investigated the thermal stability and electrical reliability of the Sm2O2SO4/MoS2 FETs. For a typical MoS2 FET device, the on/off current states could be well maintained even after being stored in air for 1 month, with an insignificant shift in threshold voltage (Supplementary Fig. 21). Benefitting from the high-quality interface with the low interfacial defect density between the Sm2O2SO4 and MoS2, the devices had a negligible hysteresis as low as 5.4 mV in the Ids-Vtg curve (Fig. 3e), ensuring the operational stability. The thermal stability of the dielectric properties in single-crystalline Sm2O2SO4 allowed the MoS2 FET device to maintain consistent performance without noticeable degradation even at a testing temperature of 500 K, exhibiting a small hysteresis width ΔVtg of no more than 24.4 mV (Fig. 3e, Supplementary Fig. 22).

To further validate the performance of the Sm2O2SO4-based top-gate FET devices, we fabricated MoS2 transistors with higher on-state currents. Using high-quality MoS2 single crystals (as shown in Supplementary Fig. 23), we have fabricated MoS2 FETs that achieve a switching ratio of up to 109. We further extracted the transconductance and mobility of the devices, with a maximum transconductance of approximately 38 μS/μm and a maximum mobility of around 81 cm2 V-1 s-1. These results confirm that, under conditions of lower defect density and higher crystal quality, the MoS2 FET devices with Sm2O2SO4 as the gate dielectric demonstrate good electrical performance, further validating the positive impact of material and process optimization on device performance. When the channel length of MoS2 FETs is reduced to 100 nm, Sm2O2SO4 demonstrates good electrical performance as a gate dielectric (Supplementary Fig. 24). Electrical statistics show that all devices exhibit steep subthreshold slopes (Supplementary Fig. 25), with the on/off ratio and field-effect mobility following a Gaussian distribution, averaging 7×106 and 48.6 cm2·V-1·s-1, respectively. The key parameters for transistors, such as on/off ratio, SS, hysteresis, EOT and Ebd, listed in Supplementary Table 1, highlight the great potential of Sm2O2SO4 single crystals for application in 2D electronics. These results demonstrate that the MoS2 FETs gated with Sm2O2SO4 dielectrics exhibit excellent thermal stability and electrical reliability.

In the microelectronics industry, traditional amorphous oxide dielectrics are typically integrated with semiconducting channels using ALD method, which often induces a substantial density of defects at the dielectric/semiconductor interface due to uncontrolled chemical bonding. These defects lead to the formation of border traps, which capture charge during device operation, resulting in increased subthreshold swing, wider hysteresis, and threshold voltage shift. The interfacial microstructure of top-gated MoS2 FET was analyzed by cross-sectional STEM image and EDS mapping. Figure 3f and Supplementary Fig. 26, the Sm2O2SO4/MoS2 shows a uniform layer thickness and clean, flat surfaces with a typical vdW gap. Atomic-resolution HAADF-STEM image in Fig. 3g exhibits a vdW gap of ~5.6 Å without any structural disorder, indicating a perfect interface with low carrier tunneling probability. The interface trap density (Dit) was extracted based on the following equation:

SS = ln(10) (kBT/q) [1 + (qDit / CG)] (4)

where kB is Boltzmann constant, T is absolute temperature, q is the elementary charge and CG is the gate capacitance. A low Dit value of 4.87×1011 cm-2 eV-1 can be achieved, which demonstrates its superiority compared to previously reported 2D MoS2 FETs with conventional oxides (Supplementary Table 2). To investigate the vdW interface between the Sm2O2SO4 dielectric and the MoS2 channel, a differential charge density calculation was carried out on the Sm2O2SO4/MoS2 heterostructure using DFT calculations. As shown in Fig. 3h, there is no charge accumulation at the Sm2O2SO4/MoS2 interface, indicating the absence of bonding interactions between Sm2O2SO4 and MoS2. Additionally, from the planar-averaged electron density difference curve, the average vdW gap is 5.2 Å, which is consistent with the cross-sectional atomic-resolution HAADF-STEM data. This value is significantly larger than the combined covalent radii of both O and S atoms, further supporting the existence of a vdW contact.

Non-volatile FG memory based on MoS2/h-BN/MLG/Sm2O2SO4/MLG
Floating gate (FG) memory, as a classic non-volatile storage technology, has been a research focus due to its high storage density, low power consumption, and excellent data retention capabilities17. However, conventional silicon-based FG memory suffers from high tunneling barriers and dangling bond issues at the Si/SiO2 interface, leading to slow operation, increased power consumption, and limited data retention5,50–52. 2D layered atomic-scale sharp high-κ dielectric materials, with their outstanding electrical properties and high stability, have emerged as promising alternatives to SiO2. They can effectively enhance the GCR of FG memory while enabling miniaturized integration6,8,10. A high GCR translates to faster programming, a larger memory window, lower power consumption, extended data retention, and low-voltage operation. We have leveraged the high dielectric constant and wide band gap characteristics of Sm2O2SO4 to successfully fabricate a high-GCR FG memory device based on a MoS2/h-BN/MLG/Sm2O2SO4/MLG vdW heterostructure, where the channel material MoS2, tunneling h-BN, floating gate MLG, blocking Sm2O2SO4 and control gate MLG from top to bottom, respectively (Fig. 4a and Supplementary Fig. 27, 28). The corresponding OM image of the FG memory device is provided in Fig. 4b. With this configuration, our fully 2D memory device achieves a GCR as high as ~0.83 (further explained in the Supplementary Note 2), significantly exceeding that of silicon-based flash memory (0.49-0.57) and the state-of-the-art FGFET using h-BN as the blocking layer (0.6)6,8,10. Figure 4c exhibits the transfer curves obtained by scanning the control gate voltage (Vcg) from negative to positive values and then back to negative values, under a drain-source bias maintained at 0.1 V. A significant clockwise memory window (ΔV) increases almost linearly with the maximum Vcg (Supplementary Fig. 29), where ΔV is defined as the difference between the positive and negative Vcg offsets. Notably, even at Vth < 3 V, a memory window exceeding 3.4 V is achieved, attributed to the high-κ Sm2O2SO4 enhancing GCR and effectively increasing the tunneling field in the h-BN layer. The output curves at different control voltages are shown in Fig. 4d. The output characteristic curve of the FG memory device (purple curve, fresh state) under no control gate voltage pulse exhibits a typical on-state with symmetric current due to initial doping of MoS2, also indicating a good ohmic contact at Cr/Au and MoS2 interfaces. When a positive voltage pulse (+20 V, 1 s width) is applied to the MLG control gate, the electrons are injected from the MoS2 channel into the floating-gate MLG through the tunneling layer h-BN and are blocked by the blocking Sm2O2SO4 layer. This causes a redistribution of the charge in the top MoS2 layer, leading to the device entering the off-state. On the contrary, when a negative control gate voltage pulse is applied, the holes are injected into the floating-gate MLG, causing a change in the floating gate charge, which modulates the electrical properties of the top MoS2 layer. As a result, the device enters the on-state, exhibiting higher conductivity.

More importantly, our devices operated with excellent long-term memory stability and electrical reliability. The endurance performance of FG memory device is validated by repeatedly programming and erasing the MoS2/h-BN/MLG/Sm2O2SO4/MLG vdW heterostructure (Fig. 4e), which shows that the on and off states of the current could be well maintained even after operating for more than 1000 cycles. Additionally, after 1.0 year, the repeated programming and erasing of the FG memory device for another 1000 cycles reveals no apparent change in either the program and erase states, demonstrating excellent durability and stability. Figure 4f shows an enlarged real-time memory state, indicating a stable transition between high and low current states. To verify the reliability of Sm2O2SO4 as a blocking dielectric, the maximum allowable voltage of 20 V was used as the operating voltage. After writing (+20 V) and erasing (-20 V) with a pulse duration of 1 s, the on/off ratio remained ~106 after 6000 s under a fixed Vds of 0.1 V at Vcg = 0 V (Fig. 4g), indicating a low back-tunneling probability by using Sm2O2SO4 as the blocking layer. Even after 1.0 year, the two current states characteristics of FG memory device show almost no changes. Additionally, we further evaluated the device’s fast programming/erasing performance (Supplementary Fig. 30). The results demonstrate that the device is capable of performing programming and erasing operations within nanosecond timescales (55.9 ns for erasing and 54.2 ns for programming), showing clear and stable state transitions. We further evaluated its energy efficiency, and the calculation results show that the energy consumption per pulse is 2.97 pJ (detailed in Supplementary Note 3). To further validate the long-term stability of the Sm2O2SO4-based floating-gate memory, we conducted testing using the Arrhenius method6. The results indicate that the memory exhibits over 10 years of stability, with a characteristic temperature of 179.2 °C and an activation energy of 2.03 eV (Supplementary Fig. 31 and Supplementary Note 4). Figure 4h illustrates the writing and erasing mechanisms of the device. When a positive pulse (Vcg > 0 V) is applied, electrons primarily tunnel from the MoS2 channel into the MLG floating gate via Fowler–Nordheim (FN) tunneling. The Sm2O2SO4 blocking layer effectively shields the control gate electric field, facilitating electron accumulation and stable storage. Conversely, when a negative pulse (Vcg < 0 V) is applied, the electrons in the floating gate tunnel back to the MoS2 channel through FN tunneling, restoring the erased state. As shown in Supplementary Table 3, we compared the key performance of our device with other advanced 2D floating-gate memory devices. Our results demonstrate that the fully 2D high-GCR FG FET structure based on high-κ Sm2O2SO4 can overcome the low-power and low-GCR integration bottlenecks of conventional flash memory, holding potential for the development of next-generation low-power, fast non-volatile memory technologies.

In summary, we have shown that 2D crystalline high-κ Sm2O2SO4 dielectric can be synthesized via a molten-salt-assisted CVD method on a mica substrate. The ultrathin Sm2O2SO4 nanoplates have atomically flat surfaces, wide band gap, high dielectric constants, and large breakdown strength, which could make it a potential dielectric for 2D FETs and other storage devices. Top-gated MoS2 FETs using Sm2O2SO4 as the dielectric exhibited an Ion/Ioff ratio of 109, a negligible hysteresis of 5.4 mV, a steep SS of 65.2 mV dec−1, and a low top-gate leakage current of 7×10−7 A/cm2. Furthermore, we demonstrated the use of Sm2O2SO4 dielectric as a blocking layer in FG memory, verifying the feasibility of miniaturized integration and low power consumption in 2D high-GCR FG devices. The dielectric properties of ultrathin crystalline Sm2O2SO4 nanosheets provide potential opportunities for developing low-power, fast electronic devices using the vdW integration strategy.

Methods
Synthesis and transfer of ultrathin Sm2O2SO4 nanoplates
2D Sm2O2SO4 single crystals were obtained by a molten-salt-assisted CVD system, which equipped with a 2-inch diameter quartz tube. Sm2(SO4)3·xH2O powders (purity 99.9%, Aladdin) and KI powders (purity 99.9%, Aladdin) were dispersed on fluorophlogopite mica (KMg3(AlSi3O10)F2) substrate and placed in the center of the furnace as the reactant and solvent. Prior to the growth process, the furnace was purged with ultra-high purity argon (Ar) gas at a flow rate of 500 sccm for 10 minutes to eliminate residual oxygen. Then, the system was heated from room temperature to 680 °C in 15 min and maintained for 10 min for ultrathin nanoplates growth at the Ar/H2 carrier gas with the flow rate of 80/20 sccm. After growth, the ultrathin nanoplates were transferred onto a target substrate via the polystyrene (PS) assisted transfer method, as shown in Supplementary Fig. 7. Firstly, PS solution was spin-coated on the mica with grown ultrathin nanoplates, followed by drying at 80 °C for 5 minutes. Then, the PS-capped substrate was placed in deionized water and then the PS film with ultrathin nanoplates was carefully lifted off the mica. Subsequently, the film was attached onto the target substrates (such as copper grid and silicon substrate). Finally, after drying on a hot plate with 80 °C for 2 min, the PS layer was removed by hot acetone (70 °C for 10 min), completing the transfer of the ultrathin nanoplates.

Material characterization
The morphology and thickness characteristics of the ultrathin nanoplates were characterized by OM (Nikon instrument ECLIPSE LV150N) and AFM (Bruker Dimension Icon), respectively. Raman and PL spectra were recorded using a micro-Raman spectrometer (LabRAM HORIBA) with a 532 nm excitation laser source. The chemical composition and crystal microstructure were investigated through XPS (250Xi ESCALAB), TEM (JEM-ARM200F, JEOL), STEM (FEI-Titan Cubed Themis G2 300). The band gap of ultrathin nanoplates was characterized by the ultraviolet-visible absorption spectrometer (Mstarter ABS).

Density functional theory calculations
All DFT calculations were conducted using the Vienna ab initio simulation package (VASP). The exchange-correlation interactions were described using the Perdew–Burke–Ernzerhof (PBE) form of the generalized gradient approximation (GGA). The interactions between ion cores and valence electrons were treated using the projector augmented wave (PAW) method. A plane-wave cutoff energy of 500 eV was set to ensure convergence and accuracy. For geometry optimization, a Γ-centered 3×3×1 Monkhorst-Pack k-point grid was used, and all structures were fully relaxed until the residual forces on each atom were below 0.01 eV/Å. To prevent spurious interactions between periodic images in the vertical direction, a vacuum layer larger than 20 Å was introduced. After structural relaxation, the band gap was calculated using a denser 6×6×3 k-point mesh.

Device fabrication and measurements
To fabricate the metal-insulator-metal (MIM) capacitors, bottom electrodes (5/50 nm Cr/Au) were first patterned on quartz substrates via electron beam lithography (EBL) followed by electron beam evaporation. Subsequently, Sm2O2SO4 nanoplates were transferred onto the patterned bottom electrodes using a PS and polydimethylsiloxane (PDMS)-assisted transfer technique on a 2D material transfer platform. Finally, top electrodes composed of Cr/Au (5/50 nm) were defined through a second EBL patterning and electron beam evaporation process.

For the Gr/MoS2 FETs, mechanically exfoliated Gr and MoS2 flakes were transferred onto a SiO2/Si substrate, followed by the transfer of grown Sm2O2SO4 nanoplates onto the Gr and MoS2 flakes, respectively. After that, Cr/Au (5/50 nm) electrodes were deposited using standard EBL and electron beam evaporation. The fabrication process for the FG memory devices, apart from the use of graphene as the bottom-gate electrode, was largely identical to that of the FETs. Specifically, the graphene stripes through mechanical exfoliation from bulk graphite crystals are firstly transferred on a SiO2/Si substrate as a bottom-gate electrode. Then, Sm2O2SO4, graphene, BN, and MoS2 layers were sequentially transferred onto the back-gate electrode using a 2D material transfer platform. Finally, the Cr/Au source-drain electrodes were fabricated on it by EBL and electron beam evaporation process.

Electrical characterizations of the MIM capacitors, FETs, and FG memory devices were carried out using a semiconductor parameter analyzer (Keithley 4200) equipped with capacitance-voltage measurement modules, in a vacuum probe station (TTPX, Lake Shore) with a base pressure of approximately 10-4 Torr. All electrical measurements were performed at room temperature unless otherwise stated.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This manuscript reports the synthesis and application of quasi-van der Waals layered Sm₂O₂SO₄ as a high-κ dielectric material for 2D electronics. The study presents notable progress in the development of 2D gate dielectrics and non-volatile memory. The combination of a wide bandgap, high dielectric constant, strong breakdown field, and successful device integration highlights the potential relevance of this work. However, to align more closely with the publication standards of Nature Communications, the authors are encouraged to address the following points.\n1.The molten salt CVD growth process requires a more detailed mechanistic explanation. What is the specific role of KI in layered versus bulk growth? How does this differ from typical CVD/flux growth methods? The authors should provide statistical data on sample growth thickness uniformity or flake size distribution.\n2.The claim of a \"quasi-vdW structure\" needs to be further clarified by contrasting it with the structure of typical vdW-layered materials.\n3.The C-V analysis and dielectric constant extraction are well-conducted; however, the manuscript would benefit from a clearer description of the quantitative fitting process of the \"dead layer\" model. Specifically, the parameters used in the fitting and their physical significance should be more explicitly presented.\n4.To provide a more comprehensive evaluation of the performance of Sm2O2SO4, the authors should include a comparison table with current state-of-the-art dielectric materials, detailing key dielectric parameters and device performance.\n5.The authors should consider providing additional data on high-temperature stability and threshold voltage shifts to more thoroughly support the reliability of the device. Furthermore, to further strengthen the reliability assessment of the device, the discussion could be enhanced by elaborating on the significance of the approximately 5.6 Å van der Waals gap at the Sm2O2SO4/MoS2 interface, particularly in terms of its effectiveness in suppressing tunneling pathways and reducing leakage current.\n6.Sm₂O₂SO₄ is utilized as a blocking layer in floating-gate non-volatile memory, showing a high gate coupling ratio (~0.83) and good data retention characteristics. However, the current validation of memory performance appears limited. Although the manuscript reports stability over 1000 program/erase cycles, further evaluation of endurance beyond this range, as well as reliability under high-temperature conditions, would strengthen the claims. Moreover, the dynamic performance of the memory device, including programming and erase speeds under different operating conditions, has not been discussed. These metrics are important for a comprehensive assessment of the material’s suitability for practical memory applications.\n7.I suggest the author list more the recent publication of the 2D gate dielectrics to show the rapid development on this field.", "reviewer_2": "Liang et al. have reported on the the controllable synthesis of quasi-vdW layered samarium oxysulfate (Sm2O2SO4) single crystals via a molten-salt-assisted chemical vapour deposition (CVD) method. These atomically thin crystals exhibit exceptional dielectric properties, including a wide bandgap (~5.54 eV), high dielectric constant (~18), robust breakdown voltage (>12 MV cm-1) and good thermal reliability. However, the details provided could be insufficient to support the significance of this work. Additionally, I have several concerns which I outline below:\n1.What’s the mobility of top-gated MoS2 transistors? Please provide the gm curves.\n2.What’s the electrical performance of short channel device?\n3.What’s the contact resistance? The fitting should contain long channel (> 1 um) and short channel devices (< 200 nm). (Please refer to Nature Electronics, 5, 416 (2022)).\n4.What’s the thickness of MoS2 in this work?\n5.What’s the low frequency noise of top-gated MoS2 transistors?\n6.Please provide the output curves of MoS2 transistors at 300-500 K.\n7.What’s the advantages of Sm2O2SO4 compared with BN in Fig. 4? There are many works on floating memory using 2D materials. Please provide the benchmark on memory window, endurance, and retention to demonstrate the memory performance.", "reviewer_3": "Liu et al. reported the controllable synthesis of quasi-van der Waals layered Sm2O2SO4 single crystals by using a molten-salt-assisted CVD method. The material exhibits wide bandgap (~5.54 eV), high dielectric constant (~18), and excellent thermal and electrical reliability. By integrating Sm2O2SO4 with MoS₂-based FET and floating-gate memory structures, the authors demonstrated promising device-level performance, including low subthreshold swing, minimal hysteresis, high on/off ratios, and stable memory characteristics. However, this manuscript is below the average compared to other work published in Nature Communications in this field. Below are detailed comments.\n1. The introduction section would benefit from the inclusion of recent literature related to two-dimensional floating-gate memory devices, which are currently lacking and essential for contextualizing the significance of this work.\n2. In Figure 1c, the OM image of the Sm2O2SO4 crystal exhibits unclear edge definition. The authors should provide reasonable explanation for this point. Furthermore, the reported crystal size of 50 μm is relatively modest; can the authors achieve the growth of larger-area 2D Sm2O2SO4 crystals? It is also recommended to include a statistical distribution of lateral crystal sizes.\n3. In Figure 1e, the x-axis of Raman spectrum is labeled as “wavelength”, which should be corrected. Additionally, the authors should clarify what thickness is denoted by “few-layer.” Raman spectra from multiple samples with varying thicknesses should be provided to validate the thickness-dependent vibrational modes.\n4. For XPS, the binding energy should be plotted from high to low value, namely, reverse the direction of horizontal axis, in Figure 1f.\n5. STEM analysis, the plane distances are wrongly described as bonding length of Sm-Sm atoms.\n6. Figure 2f presents leakage current and breakdown characteristics for Sm2O2SO4 of different thicknesses. However, only single measurements are shown for each thickness. To ensure the reliability and reproducibility of the results, it is recommended to perform and present at least five measurements per thickness.\n7. In the dielectric performance comparison shown in Figure 2h, data for MgNb2O6 are missing, despite it being included in the caption. Moreover, several recently reported 2D gate dielectrics, such as Ga2O3 and CaNb2O6, are not included. Incorporating data for these materials would provide a more comprehensive and up-to-date performance benchmark.\n8. Figure 3f, why there is no oxygen element?\n9. The authors fabricated Sm2O2SO4/MoS₂ top-gate FETs, however, a key performance parameter—carrier mobility—is not reported. Since mobility is critical for evaluating FET performance, its inclusion is necessary. Furthermore, in order to highlight the advantages of Sm2O2SO4, a comparative analysis with state-of-the-art high-k 2D dielectrics (e.g., Dit, SS, etc.) should be conducted.\n10. The manuscript describes the development of an ultrafast floating-gate nonvolatile memory. However, in Figure 4c, the gate voltage sweep rate is not specified. If sweep rate may significantly influence the memory window, the authors should provide this information and discuss its impact.\n11. While the manuscript claims low-power operation for the floating-gate device, no quantitative value for power consumption is provided. The authors should explicitly state the power consumption of the memory device to substantiate this claim.\n12. The term “ultrafast” is used to describe the floating-gate memory device, but no clear evidence is provided to justify this designation. For comparison, prior work has demonstrated programming/erasing speeds as fast as 20 ns (https://doi.org/10.1002/adma.202311652). Can the authors achieve similar speeds with their device? A comparative analysis of key performance metrics is necessary to clearly illustrate the role and advantage of Sm2O2SO4 in floating-gate nonvolatile memory applications.\n13. English should be further improved. For example, Raman spectrums-> spectra; XPS patterns -> XPS spectra."}, "author_response": "Note: [All newly added experimental images and revised content in the manuscript are\nmarked in red font. All newly added experimental images and related content, except\nfor those with titles starting with Fig. R, have been marked in red in the manuscript and\nsupplementary materials.]\nReviewer #1 (Remarks to the Author):\nThis manuscript reports the synthesis and application of quasi-van der Waals layered\nSm O SO as a high-κ dielectric material for 2D electronics. The study presents notable\n2 2 4\nprogress in the development of 2D gate dielectrics and non-volatile memory. The\ncombination of a wide bandgap, high dielectric constant, strong breakdown field, and\nsuccessful device integration highlights the potential relevance of this work. However,\nto align more closely with the publication standards of Nature Communications, the\nauthors are encouraged to address the following points.\nComment 1: The molten salt CVD growth process requires a more detailed mechanistic\nexplanation. What is the specific role of KI in layered versus bulk growth? How does\nthis differ from typical CVD/flux growth methods? The authors should provide\nstatistical data on sample growth thickness uniformity or flake size distribution.\nResponse 1: We sincerely appreciate the reviewer’s valuable comments on the molten-\nsalt CVD growth mechanism and the role of KI. Our clarifications are provided as\nfollows:\n(1) Melting point advantage\nKI has a melting point of ~681 °C, which is lower than that of NaCl (801 °C) and KCl\n(770 °C). Since our growth temperature (~680 °C) is close to the melting point of KI,\nit can undergo partial melting, thereby facilitating precursor dissolution and ion\ntransport without requiring excessively high temperatures.\n(2) Avoiding SO 2- structural degradation\n4\nwhich leads to the formation of secondary phases. Using NaCl or KCl typically requires\nhigher growth temperatures, which can damage SO 2- groups and hinder the ordered\n4\nlayered growth of Sm O SO .\n2 2 4\n(3) Flexible ionic environment and volatility\nThe high polarizability and chemical inertness of I⁻ ions provide a flexible ionic\nenvironment that promotes the preferential epitaxial stacking of Sm-O-S layers along\nthe [001] direction, while effectively suppressing vertical grain coarsening to achieve\nunidirectional layered epitaxy. Meanwhile, the volatile nature of I⁻ ions allow them to\ngradually escape from the system during the later growth stage, avoiding residual\ninterference with the crystal structure. In contrast, NaCl/KCl molten salts exert stronger\nionic fields under higher temperatures, which often induce multidirectional bulk\ncrystallization.\n(4) Selective ionic coordination\nI⁻ ions do not undergo side reactions with Sm3+ or SO 2-, which helps maintain the\n4\nchemical cleanliness and stability of the growth environment.\nTo provide a comprehensive statistical overview of the crystal size distribution,\nwe have conducted detailed analysis and included a corresponding histogram as\nSupplementary Fig. 3c, f and i. The statistical results demonstrate that the lateral sizes\nof the crystals predominantly range from 20 to 60 μm, with a notable concentration\naround 40 μm.\nSupplementary Fig. 3 | OM images of Sm 2 O 2 SO 4 nanoplates and statistical\ndistribution of lateral crystal sizes with increasing substrate temperature from\n640 ℃ (a-c) to 680 ℃ (d-f) and 720 ℃ (g-i). Scale bar: 40 µm.\nComment 2: The claim of a \"quasi-vdW structure\" needs to be further clarified by\ncontrasting it with the structure of typical vdW-layered materials.\nResponse 2: We appreciate the reviewer’s insightful suggestion regarding the\nclarification of the term “quasi-van der Waals structure.” In this work, Sm O SO is\n2 2 4\ncategorized as a quasi-van der Waals structure, a term used to capture its unique\ninterlayer interaction characteristics. While not identical to conventional two-\ndimensional van der Waals (vdW) materials, it exhibits similarly weak interlayer\ncoupling and pronounced layered growth behavior.\nStructurally, Sm O SO belongs to the Bi O X (X = S, Se, SO₄) family. Its crystal\n2 2 4 2 2\nstructure consists of alternating, highly stable [Sm O ]2+ bilayers and SO 2- anionic\n2 2 4\nlayers (see Fig. 1a and Fig. R1), giving rise to a well-defined layered architecture.\nThe [Sm O ]2+ layers adopt an Aurivillius-type oxide framework, while the interlayers are\n2 2\npredominantly stabilized by electrostatic interactions and limited hydrogen bonding,\nrather than strong covalent or ionic linkages.\nIn contrast, typical vdW materials such as MoS and h-BN are composed of\n2\natomically thin layers held together exclusively by vdW forces, resulting in extremely\nlow exfoliation energies and intrinsic cleavability. Although the interlayer coupling in\nSm O SO is not purely vdW in nature, its relatively low binding energy is sufficient to\n2 2 4\nsupport preferential two-dimensional epitaxial growth. Accordingly, the term quasi-van\nder Waals structure is employed to emphasize its weak interlayer interactions, robust\nin-plane stability, and close structural analogy to related layered compounds such as\nBi O Se and Bi O S. This classification is well supported by both physical rationale\n2 2 2 2\nand literature precedent (e.g., Nat. Mater. 2017, 16, 940; Adv. Mater. 2019, 31,\n1806020).\nFig. 1 | Structure and characterization of quasi-vdW layered Sm O SO single\n2 2 4\ncrystals.\nFig. R1 | Structure and characterization of vdW layered Bi SeO single crystals.\n2 5\n（Nat. Mater. 2017, 16, 940）\nWe have revised the description in the main text as follows: Compared with typical\nvan der Waals materials (e.g., MoS , h-BN), where atomic layers are connected by\n2\ncovalent bonds and stacked purely via van der Waals forces, Sm O SO features\n2 2 4\n[Sm O ]2+ layers coupled with SO 2- layers through weak electrostatic interactions. The\n2 2 4\ninterlayer binding energy is on the same order of magnitude as that of “quasi–van der\nWaals” materials such as Bi O Se, thereby endowing Sm O SO with van der Waals–\n2 2 2 2 4\nlike characteristics in its layered structural behavior.\nComment 3: The C-V analysis and dielectric constant extraction are well-conducted;\nhowever, the manuscript would benefit from a clearer description of the quantitative\nfitting process of the \"dead layer\" model. Specifically, the parameters used in the fitting\nand their physical significance should be more explicitly presented.\nResponse 3: We thank the reviewer for the positive feedback on our C–V analysis and\ndielectric constant extraction. Regarding the “dead layer” model, we will further\nsupplement the revised manuscript with a detailed description of the quantitative fitting.\nSpecifically, we will explicitly present the fitting formula and parameters used (such as\nthe thicknesses of the interfacial low-κ layers, tᵢ₁ and tᵢ₂, and their corresponding\ndielectric constants, εᵢ), and explain their physical significance. These parameters\nrepresent the fixed weakening effect of low-κ interfacial regions on the overall\nequivalent dielectric constant.\nIn high-κ materials, the interface regions often exhibit a lower dielectric constant,\nwhich forms the \"dead layer\" (Fig. S16). Specifically, low permittivity layers at the\ninterface (C , C ) are in series with the bulk capacitance (C ), thereby reducing the\ni1 i2 bulk\noverall effective dielectric constant. The relationship can be expressed as follows:\n1 1 1\n= + +\nC C C\neff bulk i1\n1\n(1)\nC\ni2\nFurthermore, assuming that the depths of the interfacial low permittivity layers (t , t )\ni1 i2\nare independent of the total thickness, the effective dielectric constant can be related as:\n1 t-(t + t ) t\ni1 i2 i1\n= + +\nε ε ε\neff bulk i1\nt\ni2\n(2)\nε\ni2\nwhere ε , ε , and ε represent effective, bulk, and interfacial dielectric constants,\neff bulk i\nrespectively. The rear two terms relate to interfacial dead layer and can be treated as\ninvariable, which is substituted by a constant D:\nt\n=\nε\neff\nt\n+ D (3)\nε\nbulk\nComment 4: To provide a more comprehensive evaluation of the performance of\nSm2O2SO4, the authors should include a comparison table with current state-of-the-\nart dielectric materials, detailing key dielectric parameters and device performance.\nResponse 4: We would like to thank the reviewer for their valuable suggestions. Based\non the reviewer's comments, we have added a comparative Supplementary Table 1 in\nthe revised manuscript, which systematically compares Sm O SO with the current\n2 2 4\nstate-of-the-art high-κ dielectric materials. Supplementary Table 1 details key dielectric\nparameters (such as κ value, EOT, hysteresis) and device performance metrics,\nproviding readers with a clear and intuitive understanding of the advantages and\nlimitations of Sm O SO . We believe this comparative table will further highlight the\n2 2 4\nsignificance and reference value of the work presented in this manuscript.\nSupplementary Table 1. Integration of high-κ dielectrics on 2D semiconductors via\nvan der Waals (vdW) assembly.\nt E Hystere EOT SS\nbd\nκ I /I ref.\non off\n(nm) (MV/cm) sis (mV) (nm) (mV/dec)\nSb O 40 2.7 11.5 500 N/A 64 108 4\n2 3\nHfO 16 8 11 800 N/A 78 108 5\n2 3\nZrO (ZrS ) 1.4 7.22 19 N/A 0.29 90 105 8\n2 2\nY O 20 N/A 17-20 N/A 4.2 70 105 9\n2 3\nHfO /Sb O 4/1 19.3 17.5 N/A 0.67 60 109 10\n2 2 3\nHfO (HfS ) 3 9.33 ~10 10 N/A 63.1 108 11\nx 2\nBi SeO 20 16 21 N/A 0.9 75 105 12\n2 5\n22~10\nSrTiO 4~32 6.3 N/A 1 71.5 107 13\n3\n2\n23.8~3\nLaOCl 11.3 10.8 0~30 N/A N/A 105 15\n9.3\nGd O 8.5 15.7 25.5 N/A <1 61.5 108 16\n2 5\nCCTO 8 N/A 42.9 2.4 0.9 67 106 17\nGa O 2.7 11 30 N/A 0.4 60 108 18\n2 3\nMgNb O 15 16 20 0.9 1 62 107 19\n2 6\nSr Nb O 57 N/A 24.6 N/A N/A 88 106 20\n2 3 10\nGdOX\n（X=Cl, 16 13.5 18.9 12 N/A 155 109 21\nBr）\nEu SO 12-14 >10 23.4 5.3 1 63.5 108 22\n2 x\nMn O 39 13.2 237 5 0.57 84 108 23\n3 4\nCaNb O 2.9 12 16 10 0.7 61 107 24\n2 6\nThis\nSm O SO 14.6 >12 17.8 5.4 1.7 65.2 107\n2 2 4\nwork\nComment 5: The authors should consider providing additional data on high-\ntemperature stability and threshold voltage shifts to more thoroughly support the\nreliability of the device. Furthermore, to further strengthen the reliability assessment of\nthe device, the discussion could be enhanced by elaborating on the significance of the\napproximately 5.6 Å van der Waals gap at the Sm O SO /MoS interface, particularly\n2 2 4 2\nin terms of its effectiveness in suppressing tunneling pathways and reducing leakage\ncurrent.\nResponse 5: We thank the reviewer for their valuable suggestions. In Fig. 2 and Fig. 3\nof the main text, we have already confirmed the issue of high-temperature stability and\nprovided a detailed evaluation of the device's reliability. Additionally, we agree that the\nvan der Waals gap of approximately 5.6 Å at the Sm O SO /MoS interface plays a\n2 2 4 2\ncritical role in device reliability. We have further elaborated on this in the discussion\nsection of the revised manuscript. Specifically:\n(1) Suppression of tunneling paths: This van der Waals gap acts as an atomic-scale\nphysical barrier, effectively extending the tunneling path for carriers from MoS₂ to the\ngate, thus significantly reducing the probability of direct tunneling. Compared to\nconventional oxide/semiconductor interfaces with tight coupling, this additional vdW\ngap reduces leakage currents caused by quantum tunneling while maintaining good\nelectrostatic control.\n(2) Reduction of interface defect sensitivity: The van der Waals gap prevents strong\ncovalent or dangling bonds between interface atoms, greatly alleviating the scattering\nand trapping effects of interface defect states on carriers. This not only improves the\nsubthreshold swing but also enhances the long-term electrical stability of the device.\n(3) Stress buffering and structural stability: The vdW gap at the interface also acts\nas a stress buffer, preventing the introduction of defects caused by lattice mismatch or\ndifferences in thermal expansion coefficients, thereby enhancing the structural stability\nof the dielectric layer and channel material.\nIn the main text, we have added a sentence summarizing these mechanisms:\n“This can be attributed to the well-defined vdW gap, which primarily improves leakage\nand stability by introducing an additional barrier at the interface to extend the carrier\ntunneling path, suppressing the interference of interfacial defects with charge transport,\nand alleviating stress concentration induced by lattice or thermal mismatch.”。\nComment 6: Sm O SO is utilized as a blocking layer in floating-gate non-volatile\n2 2 4\nmemory, showing a high gate coupling ratio (~0.83) and good data retention\ncharacteristics. However, the current validation of memory performance appears\nlimited. Although the manuscript reports stability over 1000 program/erase cycles, further evaluation of endurance beyond this range, as well\nas reliability under high-temperature conditions, would strengthen the claims. Moreover,\nthe dynamic performance of the memory device, including programming and erase\nspeeds under different operating conditions, has not been discussed. These metrics are\nimportant for a comprehensive assessment of the material’s suitability for practical\nmemory applications.\nResponse 6: We thank the reviewer for the valuable comments. To further evaluate the\nhigh-temperature stability as well as the programming and erasing speeds of the\nmemory device, we have conducted additional detailed experiments.\nTo accurately evaluate the retention lifetime and high-temperature stability of the\nmemory cell, we employed the commercial standard retention time test method, namely\nthe Arrhenius plot method. In the experiments, the threshold voltage (𝑉 ) of the\nth\nmemory cell was measured over time after programming and erasing to analyze the\naccelerated effects at different temperatures. The test temperatures were set at 100, 200,\nand 300 ℃. Supplementary Figure 30a shows the time evolution of 𝑉 at different\nth\ntemperatures, while Supplementary Figure 30b presents the corresponding threshold\nvoltage difference (Δ𝑉 ) as a function of time.\nth\nThe retention lifetime of the non-volatile memory is determined by the degradation\nof the threshold voltage, i.e., the time when the threshold voltage difference decays to\n50% of its initial value. Supplementary Figure 30c shows the time points corresponding\nto 50% retention failure at different temperatures. The experimental data were fitted\nusing the Arrhenius equation, yielding an activation energy 𝐸 =2.03 eV:\na\nt = \nT\nE\na\nt exp (− ) (13)\nR kT\nwhere t is the retention lifetime at the test temperature, t is the reference retention\nT R\ntime at infinite temperature, k is Boltzmann’s constant, and T is the test temperature.\nFrom the fitted curve, the critical temperature for a 10-year retention lifetime was\ncalculated to be 179.2 ℃, as shown in Supplementary Figure 30d. These results indicate\nthat the memory cell exhibits excellent non-volatile retention performance under high-\ntemperature acceleration, and the 50% retention failure analysis provides a reliable\nreference for long-term room-temperature data retention.\nSupplementary Fig. 30 | Electrical characteristics and temperature dependence of\nthe floating-gate memory device. (a) Evolution of the threshold voltage (V ) over\nth\ntime under +22.5 V/54.2 ns programming and -22.4 V/55.9 ns erasing pulses at\ndifferent temperatures (100, 200, and 300 °C). Red, blue, and purple curves correspond\nto different initial states. (b) Retention of the threshold voltage difference (ΔV ) as a\nth\nfunction of time at various temperatures. (c) Time-dependent retention failure rate of\nthe device after baking at 100, 200, and 300 °C. (d) Arrhenius analysis and\nextrapolation of retention time. Dashed lines indicate linear fitting, extrapolated to a\n10-year lifetime. The critical temperature is 179.2 °C, with an activation energy E = \na\n2.03 eV.\nWe thank the reviewer for the valuable comments regarding the dynamic\nperformance of the device. To further evaluate the programming and erasing speed of\nthe Sm O SO -based floating-gate device, we performed additional experiments, as\n2 2 4\nshown in Supplementary Fig. 29. Supplementary Fig. 29a presents the current response\n(I ) of the device after a single program (black) and erase (red) operation, clearly\nds\ndemonstrating well-distinguished program and erase states, indicating reliable state\nswitching in a single operation. Supplementary Fig. 29b shows the control gate voltage\n(V ) waveforms measured by the Keithley 4200 system, where the left panel\ncg\ncorresponds to a -22.4 V erase pulse (red, full width at half maximum, FWHM = 55.9\nns) and the right panel corresponds to a +22.5 V program pulse (black, FWHM = 54.2\nns). These results indicate that the device can complete programming and erasing\noperations within nanoseconds, demonstrating both stable memory states and high-\nspeed operation, which are essential for high-performance non-volatile memory\napplications.\nSupplementary Fig. 29 | Fast program/erase characteristics of the Sm O SO -\n2 2 4\nbased floating-gate device. (a) Current response (I ) of the device after applying a\nds\nsingle program operation (black) and an erase operation (red), clearly showing well-\ndistinguished program and erase states. (b) Output voltage waveforms (V ) generated\ncg\nby a Keithley 4200 system: the left panel corresponds to the -22.4 V erase pulse (red,\nfull width at half maximum, FWHM = 55.9 ns), and the right panel corresponds to the\n+22.5 V program pulse (black, FWHM = 54.2 ns).\nComment 7: I suggest the author list more the recent publication of the 2D gate\ndielectrics to show the rapid development on this field.\nResponse 7: We would like to thank the reviewer for their valuable suggestion. As per\nthe request, we have included more recent progress in the field of 2D high-k dielectrics\nin our manuscript. Specifically, we have added the following:\n(1) Introduction Section: The sentence \"High-quality single crystal dielectric\nmaterials such as h-BN, Gd O , MgNb O , Eu SO , and Mn O , due to their\n2 5 2 6 2 x 3 4\nexcellent interface quality, have been widely used in 2D electronic devices as\nvdW dielectric materials, preserving the intrinsic properties of 2D\nsemiconductors\" has been added to highlight the significance of recent\ndevelopments.\n(2) Figure 2h: In this figure, we have further elaborated on additional relevant\nstudies related to 2D high-k dielectrics, showing their integration with 2D\nsemiconductors and their impact on device performance.\n(3) Supplementary Table 1: We have also included a comprehensive table\n(Supplementary Table 1), which summarizes recent advancements in high-k\ndielectrics for 2D materials, offering further references to relevant works in the\nfield.\nWe believe these additions provide a broader perspective on the current progress\nand strengthen the context of our study in relation to the state-of-the-art research.\nFig. 2 | Dielectric properties of quasi-vdW layered Sm O SO single crystal.\n2 2 4\nSupplementary Table 1. Integration of high-κ dielectrics on 2D semiconductors via\nvan der Waals (vdW) assembly.\nt E Hystere EOT SS\nbd\nκ I /I ref.\non off\n(nm) (MV/cm) sis (mV) (nm) (mV/dec)\nSb O 40 2.7 11.5 500 N/A 64 108 4\n2 3\nHfO 16 8 11 800 N/A 78 108 5\n2 3\nZrO (ZrS ) 1.4 7.22 19 N/A 0.29 90 105 8\n2 2\nY O 20 N/A 17-20 N/A 4.2 70 105 9\n2 3\nHfO /Sb O 4/1 19.3 17.5 N/A 0.67 60 109 10\n2 2 3\nHfO (HfS ) 3 9.33 ~10 10 N/A 63.1 108 11\nx 2\nBi SeO 20 16 21 N/A 0.9 75 105 12\n2 5\n22~10\nSrTiO 4~32 6.3 N/A 1 71.5 107 13\n3\n2\n23.8~3\nLaOCl 11.3 10.8 0~30 N/A N/A 105 15\n9.3\nGd O 8.5 15.7 25.5 N/A <1 61.5 108 16\n2 5\nCCTO 8 N/A 42.9 2.4 0.9 67 106 17\nGa O 2.7 11 30 N/A 0.4 60 108 18\n2 3\nMgNb O 15 16 20 0.9 1 62 107 19\n2 6\nSr Nb O 57 N/A 24.6 N/A N/A 88 106 20\n2 3 10\nGdOX\n（X=Cl, 16 13.5 18.9 12 N/A 155 109 21\nBr）\nEu SO 12-14 >10 23.4 5.3 1 63.5 108 22\n2 x\nMn O 39 13.2 237 5 0.57 84 108 23\n3 4\nCaNb O 2.9 12 16 10 0.7 61 107 24\n2 6\nThis\nSm O SO 14.6 >12 17.8 5.4 1.7 65.2 107\n2 2 4\nwork\nReviewer #2 (Remarks to the Author):\nLiu et al. have reported on the controllable synthesis of quasi-vdW layered samarium\noxysulfate (Sm O SO ) single crystals via a molten-salt-assisted chemical vapour\n2 2 4\ndeposition (CVD) method. These atomically thin crystals exhibit exceptional dielectric\nproperties, including a wide bandgap (~5.54 eV), high dielectric constant (~18), robust\nbreakdown voltage (>12 MV cm-1) and good thermal reliability. However, the details\nprovided could be insufficient to support the significance of this work. Additionally, I\nhave several concerns which I outline below:\nComment 1: What’s the mobility of top-gated MoS transistors? Please provide the gm\n2\ncurves.\nResponse 1: We appreciate the reviewer’s valuable comments. In the revised\nmanuscript, we have provided further explanations and clarifications. It is important to\nemphasize that the field-effect mobility is typically extracted from the transconductance\n𝐺 , and the magnitude of 𝐺 is physically closely related to the on-state current of the\nm m\nchannel. For thin-channel MoS devices, if the material quality is limited and the defect\n2\ndensity is high, the on-state current may be insufficient, leading to a reduced\ntransconductance and consequently a limited extracted mobility.\nIn the early experiments of this study, we used MoS crystals mechanically\n2\nexfoliated from natural molybdenite. Such natural materials generally contain a\nrelatively high density of point defects and impurities, resulting in strong scattering that\nlimits the electron mobility. Consequently, both the on-state current and mobility of\nthese devices were relatively low. To obtain more representative device performance,\nwe further introduced high-quality bulk MoS₂ single crystals grown by the chemical\nvapor transport (CVT) method and prepared top-gate devices via mechanical\nexfoliation. Benefiting from the lower defect density and higher crystal quality, the\nchannel on-state current was significantly enhanced, reaching a magnitude of over 10-5\nA, which markedly improves the observability of the transconductance signal.\nIn the newly added Supplementary Fig. 23, we systematically present the structure\nand electrical characteristics of these devices: (a) optical microscopy image showing a\nclearly defined channel region; (b) and (c) AFM morphology and height profile,\nconfirming a MoS thickness of ~2.3 nm and Sm O SO dielectric thickness of ~15 nm;\n2 2 2 4\n(d) transfer characteristics at 𝑉 =1.0 V, exhibiting typical field-effect modulation; (e)\nds\ntransconductance versus overdrive voltage extracted from the transfer curve, with a\nmaximum 𝐺 of ~21 μS/μm; (f) field-effect mobility as a function of on-state current\nm\ndensity calculated from the transconductance, with a maximum mobility 𝜇max of ~70\ncm2 V-1 s-1.\nIt should be noted that this performance approaches the reported optimum values\nfor top-gate devices fabricated from high-quality exfoliated MoS and is significantly\n2\nhigher than that obtained from devices based on natural MoS₂. This clearly\ndemonstrates the decisive influence of channel material quality on transconductance\nand mobility. More importantly, this work further validates that Sm O SO , as a high-\n2 2 4\nquality gate dielectric layer in top-gate structures, effectively modulates the MoS\n2\nchannel, ensuring excellent device electrical performance.\nSupplementary Fig. 23 | Structure and electrical characteristics of the\nMoS /Sm O SO FET. (a) Optical micrograph of the device with a Sm O SO\n2 2 2 4 2 2 4\nthickness of ~15 nm. scale bar: 2 µm. (b) Atomic force microscopy (AFM) image\nshowing the MoS /Sm O SO heterostructure. scale bar: 0.5 µm. (c) AFM height\n2 2 2 4\nprofile along the line in panel b, confirming a MoS thickness of ~2.3 nm. (d) Transfer\n2\ncharacteristics (I -V ) measured at V = 1.0 V. (e) Transconductance characteristics\nds ov ds\n(G -V ) extracted from the transfer curve at V = 1.0 V. (f) Field-effect mobility (μ)\nm ov ds\nextracted from transconductance as a function of on-state current density (I ), showing\non\na peak mobility μ of ~70 cm2·V-1·s-1.\nmax\nComment 2: What’s the electrical performance of short channel device?\nResponse 2: Thank you for the reviewer’s question. To evaluate the performance of\nSm O SO as the gate dielectric material in short-channel MoS₂ FETs, we fabricated\n2 2 4\nback-gated MoS₂ FETs with a channel length of 100 nm and conducted detailed\nelectrical measurements of the device.\nFirst, from the transfer characteristics shown in Supplementary Fig. 24a, the short-\nchannel MoS FET exhibits a switching ratio of approximately 106, and a subthreshold\n2\nswing (SS) of 72 mV/decade, indicating that the device retains good switching\ncharacteristics at low power operation. Additionally, the device demonstrates stable\nperformance and exhibits a linear transfer characteristic at different drain-source\nvoltages (V = 0.1 V, 0.5 V, and 1.0 V), confirming the effectiveness of Sm O SO as\nds 2 2 4\nthe gate dielectric in short-channel devices. In terms of output characteristics\n(Supplementary Fig. 24b), we observed significant gate control over the drain-source\ncurrent (I ) with varying drain-source voltages (V ) at different back-gate voltages\nds ds\n(V ). Especially as the back-gate voltage changes from -4.0 V to 4.0 V, the excellent\nbg\ncurrent modulation indicates the effective gate control capability of the Sm O SO\n2 2 4\nmaterial in short-channel devices.\nIn conclusion, Sm O SO , as the gate dielectric material, has shown outstanding\n2 2 4\nperformance in short-channel MoS FETs. It effectively enhances the gate control\n2\ncapability and suppresses short-channel effects, providing strong support for the\nrealization of high-performance, low-power electronic devices.\nSupplementary Fig. 24 | Transfer and output characteristics of the back-gated\nshort-channel MoS FET. (a) Transfer characteristics of the short-channel MoS FET,\n2 2\nshowing a switching ratio of approximately 105 and a subthreshold swing (SS) of 87.3\nmV/decade, measured at different drain-source voltages (V = 0.1 V, 0.5 V, and 1.0 V).\nds\nThe inset shows the scanning electron microscope (SEM) image of the device with a\nchannel length (L ) of approximately 100 nm, scale bar: 400 nm. (b) Output\nch\ncharacteristics showing the variation of drain-source current (I ) with different back-\nds\ngate voltages (V ) from -4.0 V to 4.0 V, measured with a step of 0.8 V.\nbg\nComment 3: What’s the contact resistance? The fitting should contain long channel (>\n1 um) and short channel devices (< 200 nm). (Please refer to Nature Electronics, 5, 416\n(2022)).\nResponse 3: Thank you for the reviewer’s detailed review and valuable suggestions. In\nthis study, we used the Transmission Line Model (TLM) method to extract the contact\nresistance (𝑅 ) of short-channel MoS FETs. The TLM method has been widely applied\nc 2\nin semiconductor devices and can effectively separate the contact resistance (𝑅 ) and\nc\nchannel resistance (R ). Specifically, by measuring the total resistance (𝑅 ) as a\nch tot\nfunction of the channel length (L ), the contact resistance (𝑅 ) can be extracted as\nch c\nfollows:\nR = 2R\ntot c\n+L R (4)\nch ch\nwhere 𝑅 is the total resistance, 𝑅 is the contact resistance, R is the channel resistance,\ntot c ch\nand L is the channel length. In this study, we used ns=1.0×1013 cm-2 as the normalized\nch\ncarrier density to eliminate the resistance variations caused by different carrier densities.\nTo ensure the accuracy of the experimental results, we chose a small drain-source\nvoltage (V = 0.1 V) to avoid the interference of nonlinear effects from larger currents,\nds\nensuring that the contact resistance dominated the device’s current response, allowing\nfor more precise extraction of the contact resistance. From Supplementary Fig. 19a, we\nobserve that as the channel length (L ) increases from 0.1 μm to 1.5 μm, the transfer\nch\ncharacteristics of the devices show typical FET behavior, with the switching\ncharacteristics weakening as the channel length increases. The short-channel devices\n(L = 0.1 μm and 0.15 μm) turn on at lower gate voltages and exhibit higher on/off\nch\nratios, indicating that the contact resistance has a significant impact on the current\ncontrol in short-channel devices. In contrast, for longer channel lengths (L = 1.0 μm\nch\nand 1.5 μm), the current response is more gradual, and the influence of contact\nresistance becomes less significant, with channel resistance becoming dominant. This\ntrend validates that in short-channel MoS FETs, the contact resistance plays a much\n2\nlarger role in controlling the current compared to long-channel devices. In\nSupplementary Fig. 19b, we present the relationship between the total resistance (𝑅 )\ntot\nand channel length (L ). As shown, the contact resistance (𝑅 ) increases significantly\nch c\nwith decreasing channel length, demonstrating a typical linear trend. The contact\nresistance (𝑅 ) extracted using the TLM method is 0.97 kΩ·μm, and the normalized\nc\ncontact resistance (2𝑅 ) is 1.94 kΩ·μm. These results align well with the experimental\nc\ndata, further confirming the validity of the TLM method for measuring contact\nresistance in short-channel MoS₂ FETs.\nThrough repeated measurements of devices with different channel lengths and\nstandardization using the carrier density (n ), we ensured the reliability and accuracy of\ns\nthe data. The standardized TLM method effectively eliminates the resistance variations\ncaused by different carrier densities, ensuring the precise extraction of the contact\nresistance. It is important to emphasize that the focus of this work is not on the scaling\nof contact resistance.\nWe would like to express our sincere gratitude to the reviewer for their valuable\nsuggestions, which have significantly helped improve the scientific quality and\naccuracy of the manuscript.\nSupplementary Fig. 19 | Transfer and resistance characteristics of short-channel\nMoS FETs with varying channel lengths. (a) Transfer characteristics of MoS FETs\n2 2\nwith channel lengths (L ) ranging from 0.1 μm to 1.5 μm, measured at a drain-source\nch\nvoltage (V ) of 0.1 V. The inset shows the scanning electron microscope (SEM) image\nds\nof the devices with different channel lengths, scale bar: 5 μm. (b) The total resistance\n(R ) as a function of channel length (L ), showing the trend of contact resistance (R )\ntot ch c\nvariation with channel length. The contact resistance (R ) is extracted using the TLM\nc\nmethod and normalized to a carrier density (nₛ) of 1.0×1013 cm-2. Based on the\nextraction results, 2R is 1.94 kΩ·μm, and the contact resistance (R ) is 0.97 kΩ·μm.\nc c\nComment 4: What’s the thickness of MoS in this work?\nof MoS₂ in this study, we have provided the AFM measurement results, which show\nthat the thickness of MoS is approximately 3.1 nm, as shown in Fig. R2 below. This\n2\nhas been added to the manuscript with a red annotation. Your feedback has been\ninstrumental in improving the manuscript and clarifying the details. Once again, thank\nyou!\nFig. R2 | AFM thickness measurement of MoS in Fig. 3c, with a thickness of\n2\napproximately 3.1 nm.\nComment 5: What’s the low frequency noise of top-gated MoS transistors?\nof our MoS₂ transistors. As shown in Fig. R3, we measured the normalized current noise\nspectral density (S /I 2) of monolayer MoS FETs with Sm O SO gate dielectrics over\nid d 2 2 2 4\na wide frequency range from 1 Hz to 105 Hz. The spectra clearly exhibit a 1/f -like\ndependence without additional Lorentzian humps or random telegraph noise, indicating\na low and uniformly distributed trap density at the dielectric/semiconductor interface.\nQuantitatively, the normalized noise spectral density is on the order of 10-9-10-10 Hz-1\nat 10 Hz and further decreases to ~10-12 Hz-1 at higher frequencies (103-104 Hz), which\nis comparable to or better than state-of-the-art MoS₂ FETs reported in the literature.\nMoreover, the noise level decreases slightly as V increases from 0 V to 2 V, which is\ntg\nconsistent with the carrier number fluctuation (CNF) model, where higher carrier\ndensities effectively screen the influence of trapping/detrapping events. This result\nconfirms that our devices are dominated by number fluctuation noise rather than\nmobility fluctuation noise, reflecting the clean interface and stable electrical\ncharacteristics provided by the high-κ Sm O SO dielectric. Taken together, these\n2 2 4\nresults demonstrate that our MoS FETs achieve low S /I 2, robust 1/f behavior, and\n2 id d\nfavorable gate-bias dependence, placing their low-frequency noise performance among\nthe best in the field of 2D FETs.\nFig. R3 | 1/f noise characterization of MoS FETs with Sm O SO gate dielectric.\n2 2 2 4\nThe measured 1/f noise of monolayer MoS FETs with Sm O SO gate dielectrics as a\n2 2 2 4\nfunction of frequency, with V swept from 0 V to 2 V.\ntg\nComment 6: Please provide the output curves of MoS transistors at 300-500 K.\nFig. 22 below, we have provided the output characteristics of MoS₂ transistors in the\ntemperature range of 300-500 K.\nSupplementary Fig. 22 | Output characteristics of MoS FETs in Fig. 3c. This figure\n2\nshows the output characteristics of MoS FETs based on Sm O SO as the gate\n2 2 2 4\ndielectric, with curves measured at different gate voltages (V ) and drain-source\ntg\nvoltages (V ) ranging from 0 to 3 V.\nds\nComment 7: What’s the advantages of Sm O SO compared with BN in Fig. 4? There\n2 2 4\nare many works on floating memory using 2D materials. Please provide the benchmark\non memory window, endurance, and retention to demonstrate the memory performance.\nResponse 7: Thank you for the reviewer’s valuable feedback. We greatly appreciate\nyour insightful comments regarding the use of Sm O SO as a blocking layer, and we\n2 2 4\nwould like to further clarify the background of our study and its innovative advantages.\nIn the following, we will discuss the significance of this work from three aspects:\n(1) Theoretical Model and Design Optimization of Fully 2D Floating Gate\nMemory Based on Sm O SO Dielectric\n2 2 4\nIn a fully two-dimensional floating gate memory, the ability of the control gate to\nregulate the floating gate directly determines the programming and erasing efficiency\nof the device. The gate coupling ratio (GCR) is a key parameter for evaluating this\ncapability. Compared to traditional SiO and low-κ h-BN as the blocking layer, this\n2\nstudy, for the first time, employs a novel high-κ dielectric, Sm O SO (SmOS), as the\n2 2 4\nblocking layer and evaluates its impact on the memory’s electric field distribution and\nGCR. To accurately describe how the control gate voltage is distributed across the\ntunneling and blocking layers, we derive the electric field calculation formula based on\nthe charge conservation principle:\nε 𝑆 𝐸\nBN BN BN\n−ε 𝑆 𝐸 = Q(t)∙𝑆 (5)\nSmOS SmOS SmOS 1\n𝐸 𝑑\nBN BN\n+𝐸 𝑑 = V (6)\nSmOS SmOS\nwhere ε (~4) an ε (~15) are the dielectric constants of h-BN and Sm O SO ,\nBN SmOS 2 2 4\nrespectively; d (~12 nm) and d (~23 nm) represent their thicknesses; S (~16\nBN SmOS BN\nμm2) and S (~40 μm2) denote their contact areas. and are the electric fields within\nSmOS\nthe respective layers, while V is the applied voltage on the control gate, and Q(t)\nrepresents the charge density per unit area passing through the h-BN layer. To further\nquantify the impact of Sm O SO as a blocking layer on the performance of floating\n2 2 4\ngate memory, we computed its gate coupling ratio (GCR):\nGCR = \nC\nSmOS-MLG\n(7)\nC +C\nSmOS-MLG BN-MoS2\nThe capacitance of each layer is calculated as follows:\nC = \nSmOS-MLG\nε 𝑆\nSmOS SmOS\n(8)\nd\nSmOS\nC = \nBN-MoS2\nε 𝑆\nBN BN-MoS2\n(9)\nd\nBN\nUnder the experimental parameters, the calculated GCR reaches as high as 0.83.\nCompared to the state-of-the-art fully 2D floating gate memory using h-BN as the\nblocking layer, which exhibits a GCR of 0.6, the Sm O SO FG FET further enhances\n2 2 4\nthe coupling between the floating gate and the control gate3. This demonstrates that\nSm O SO , when used as the blocking layer, effectively strengthens the electrostatic\n2 2 4\ncoupling between the floating gate and the control gate, thereby improving memory\ncontrol efficiency. As a result, the required control gate voltage for programming is\nreduced, while the stability of the memory window is enhanced. Furthermore, based on\nEquations (5), (6), (8), and (9), the tunneling electric field equation for the h-BN\ntunneling layer is derived as:\n𝑉/d\nBN\n𝐸 = \nBN 1+C /C\nBN SmOS\nQ(t)∙𝑆 /d\n+ (10)\nC +C\nBN SmOS\nIt can be observed that the use of the high-κ blocking layer Sm O SO increases C ,\n2 2 4 SmOS\nwhich in turn enhances the electric field E in the h-BN layer. As a result, a higher\nBN\ntunneling electric field can be achieved under the same control gate voltage. Our\nmemory device achieves nearly 80% of the memory window at a low operating voltage\nof 3 V, which is attributed to the high-κ Sm O SO blocking layer. This layer provides\n2 2 4\nexcellent GCR and an enhanced E , significantly reducing power consumption and\nBN\nimproving the reliability of the memory device.\n(2) Performance comparison analysis\nWe compared the performance metrics of the latest floating-gate memory\ndevices and compiled the following table. Based on the data in the table, the\nSm₂O₂SO₄-based floating-gate memory device demonstrates significant advantages in\nterms of memory window, low operating voltage, high programming/erasing speed,\nand other performance aspects. Specifically:\n Memory Window: The memory window of the Sm 2 O 2 SO 4 -based memory\ndevice is below 3 V, providing higher storage capacity and better stability\ncompared to other materials at low voltages.\n Programming/Erasing Voltage: This device enables efficient\nprogramming/erasing operations at a low voltage of 3 V, significantly\nreducing power consumption.\n Programming/Erasing Speed: The programming/erasing speed of the\nSm O SO -based memory device reaches 55.9/54.2 ns, placing it among the\n2 2 4\nleaders in storage speed, demonstrating faster operational performance.\n On/Off Ratio: The Sm 2 O 2 SO 4 -based floating-gate memory device has an\non/off ratio of 3×10⁷, indicating its potential for high-speed storage\napplications.\n Endurance: The device exhibits more than 2000 cycles of endurance,\nensuring long-term stable usage.\nIn conclusion, the Sm O SO -based floating-gate memory device ranks among\n2 2 4\nthe top in the field of 2D memory, particularly excelling in low voltage, high-speed\nprogramming/erasing operations, and large memory window, showcasing its\nsignificant potential for future memory applications.\n(3) Supplementary Table 3. Comparison of the performance of our floating-gate\nmemory devices based on all-2D materials with other devices partially based\non 2D materials\nWrite/erase Retention Endurance Memory\nDevice structure Voltage I /I ref.\non off\npluse performance Performance Window\nMoS /hBN/MLG/hBN/MLG\n2\n(All 2D Materials)\nMoS /Al O /Pt/SiO /Si 3 V 109 ~5 μs ~104 s 105 cycles 78% 27\n2 2 3 2\nMoS /hBN/MLG/SiO /Si 15 V 109 10-100 ns >104 s >106 cycles 56% 28\n2 2\nReSe /hBN/Gr/SiO /Si 12 V >104 4 ms >103 s >3000 cycles >70% 29\n2 2\nMoS /HfO /HfS /HfO /Au 5 V 107 1 ms >105 s >1000 cycles 56% 30\n2 x 2 x\nMoTe /hBN/Gr/SiO /Si 17 V 104 4 ms 103 s 1000 cycles 65% 31\n2 2\nInSe (MoS )/hBN/MLG\n2\n/SiO /Si\n2 2\nMoS /hBN/MLG/Sm O SO / -22.4/22.5 This\n2 2 2 4\n107 55.9/54.2 ns ~104 s ~2000 cycles 75%\nMLG V work\n(4) Potential and future directions of research\nDue to limitations in our experimental equipment, we have not yet been able to\nmeasure the programming/erasing speed on the sub-nanosecond (sub-ns) timescale.\nHowever, we have already demonstrated the potential of Sm O SO as a blocking layer\n2 2 4\nin enhancing memory performance. In the future, our research will focus on further\noptimizing the programming/erasing speed of the memory device and achieving sub-\nnanosecond (sub-ns) operation speeds. By improving the experimental equipment and\nfurther optimizing the performance of Sm O SO , we expect to accelerate the operation\n2 2 4\nspeed of the memory, providing support for higher-performance 2D memory devices.\nReviewer #3 (Remarks to the Author):\nLiu et al. reported the controllable synthesis of quasi-van der Waals layered Sm O SO\n2 2 4\nsingle crystals by using a molten-salt-assisted CVD method. The material exhibits wide\nbandgap (~5.54 eV), high dielectric constant (~18), and excellent thermal and electrical\nreliability. By integrating Sm O SO with MoS₂-based FET and floating-gate memory\n2 2 4\nstructures, the authors demonstrated promising device-level performance, including\nlow subthreshold swing, minimal hysteresis, high on/off ratios, and stable memory\ncharacteristics. However, this manuscript is below the average compared to other work\npublished in Nature Communications in this field. Below are detailed comments.\nComment 1: The introduction section would benefit from the inclusion of recent\nliterature related to two-dimensional floating-gate memory devices, which are currently\nlacking and essential for contextualizing the significance of this work.\nResponse 1: We would like to express our gratitude to the reviewer for their insightful\ncomments. As per the suggestion, we have included recent research progress on 2D\nfloating-gate field-effect transistors (FGFETs) in the references and cited several high-\nquality studies from the relevant field to further clarify the background and significance\nof our work. Additionally, we have added Supplementary Table 3 to further highlight\nthe contributions of our research. The revised manuscript now includes the following\ncontent:\n\" In recent years, floating-gate field-effect transistors (FGFETs) based on 2D\nmaterials have gained widespread attention4-13. 2D materials such as MoS , ReSe , HfS ,\n2 2 2\nand MoTe demonstrate excellent electric field control, effectively reduce parasitic\n2\ndefect capture, and facilitate the scaling of memory and computing systems, thereby\nshowing significant advantages in high-density integration14,15. \"\nThese additional references and content help to highlight the contribution of our\nresearch in the field of 2D floating-gate memory devices and closely align it with\nexisting related studies.\nSupplementary Table 3. Comparison of the performance of our floating-gate\nmemory devices based on all-2D materials with other devices partially based on\n2D materials\nWrite/erase Retention Endurance Memory\nDevice structure Voltage I /I ref.\non off\npluse performance Performance Window\nMoS /hBN/MLG/hBN/MLG\n2\n(All 2D Materials)\nMoS /Al O /Pt/SiO /Si 3 V 109 ~5 μs ~104 s 105 cycles 78% 27\n2 2 3 2\nMoS /hBN/MLG/SiO /Si 15 V 109 10-100 ns >104 s >106 cycles 56% 28\n2 2\nReSe /hBN/Gr/SiO /Si 12 V >104 4 ms >103 s >3000 cycles >70% 29\n2 2\nMoS /HfO /HfS /HfO /Au 5 V 107 1 ms >105 s >1000 cycles 56% 30\n2 x 2 x\nMoTe /hBN/Gr/SiO /Si 17 V 104 4 ms 103 s 1000 cycles 65% 31\n2 2\nInSe (MoS )/hBN/MLG\n2\n/SiO /Si\n2 2\nMoS /hBN/MLG/Sm O SO / -22.4/22.5 This\n2 2 2 4\n107 55.9/54.2 ns ~104 s ~2000 cycles 75%\nMLG V work\nComment 2: In Figure 1c, the OM image of the Sm O SO crystal exhibits unclear edge\n2 2 4\ndefinition. The authors should provide reasonable explanation for this point.\nFurthermore, the reported crystal size of 50 μm is relatively modest; can the authors\nachieve the growth of larger-area 2D Sm O SO crystals? It is also recommended to\n2 2 4\ninclude a statistical distribution of lateral crystal sizes.\nResponse 2: We sincerely thank the reviewer for their careful observation and valuable\ncomments regarding the OM image of the Sm O SO crystals in Fig. 1c and their size.\n2 2 4\nOn the \" unclear edge definition\" of the crystals: The reviewer's observation\nregarding the somewhat blurred edges of the crystals in the optical micrograph is\nabsolutely valid. We appreciate this comment and would like to clarify that this effect\nis not due to poor crystallinity, but is primarily a result of the high transparency of the\nSm O SO crystals. This high transparency causes incident light to transmit through the\n2 2 4\ncrystals and scatter at their edges, making the precise boundary between the crystal and\nthe substrate appear less distinct under optical microscopy. To thoroughly address any\npotential concerns from the reviewers, we have provided additional characterization\ndata using TEM and HAADF-STEM (Supplementary Fig. 7b and Fig. 1h). This\ntechnique effectively circumvents the limitations of optical scattering by employing\nelectron beam imaging, thereby enabling clear visualization of the true crystal\nmorphology. As shown in Supplementary Fig. 3, the Sm O SO crystals exhibit intact\n2 2 4\nand sharp edge profiles along with well-defined crystallographic angles, which\nunambiguously confirms their excellent structural integrity and high crystallinity.\nSupplementary Fig. 3 | OM images of Sm O SO nanoplates and statistical\n2 2 4\ndistribution of lateral crystal sizes with increasing substrate temperature from\n640 °C (a-c) to 680 °C (d-f) and 720 °C (g-i). Scale bar: 40 µm.\nOn the crystal size and potential for larger-area growth: We agree with the\nreviewer that achieving larger lateral dimensions is highly desirable for practical\napplications. The ~50 μm size reported represents a typical and reliable size obtained\nfrom our current optimized chemical vapor deposition growth method. The growth of\nlarge-sized, high-quality 2D Sm O SO crystals is inherently challenging, as it requires\n2 2 4\na delicate balance between thermodynamic and kinetic conditions to promote lateral\nexpansion while simultaneously suppressing nucleation density. Under our optimized\ngrowth protocol, we have successfully obtained crystals with a maximum lateral\ndimension of up to 80 μm in following Fig. R4. To provide a comprehensive statistical\noverview of the crystal size distribution, we have conducted detailed analysis and\nincluded a corresponding histogram as Supplementary Fig. 3c, f and i. The statistical\nresults demonstrate that the lateral sizes of the crystals predominantly range from 20 to\n60 μm, with a notable concentration around 40 μm.\nFig. R4 | OM images of Sm O SO nanoplates.\n2 2 4\nComment 3: In Figure 1e, the x-axis of Raman spectrum is labeled as “wavelength”,\nwhich should be corrected. Additionally, the authors should clarify what thickness is\ndenoted by “few-layer.” Raman spectra from multiple samples with varying thicknesses\nshould be provided to validate the thickness-dependent vibrational modes.\nResponse 3: We sincerely thank the reviewer for their thorough review. We would first\nlike to offer our sincere apologies for an error in our previous response. Upon re-\nexamination, we recognized that Fig. 1e should present PL spectra, and we mistakenly\nreferred to it as a Raman spectrum in our earlier description. We have now replaced the\nrelevant data with corrected Raman spectra (Fig. 1e). Furthermore, to properly address\nthe reviewer's request regarding the specific definition of \"few-layer\" and the thickness\ndependence of the Raman vibrational modes, we systematically performed Raman\nspectroscopy on Sm O SO crystals of different thicknesses (Supplementary Fig. 5). As\n2 2 4\nthe thickness decreases, the peaks (ν , ν , ν , and ν ) become less pronounced, which\n1 2 3 4\ncan be attributed to the weaker intensities of four vibrational modes in few-layer\nSm O SO nanoplates.\n2 2 4\nFig. 1 | Structure and characterization of quasi-vdW layered Sm O SO single\n2 2 4\ncrystals. a The crystal structure of Sm O SO . Blue, yellow and red spheres represent\n2 2 4\nSm, S and O atoms, respectively. b Schematic of the strategy for the growth of layered\nSm O SO single crystals. c OM image of Sm O SO nanoplates. Scale bars: 10 µm. d\n2 2 4 2 2 4\nOptical bandgap of ultrathin Sm O SO nanoplates identified by the ultraviolet-visible\n2 2 4\nabsorption spectroscopy, α, h and ν are the absorption coefficient, Planck constant and\nlight frequency, respectively. Inset: calculated electronic band structure of Sm O SO .\n2 2 4\ne Typical Raman spectrums of ultrathin Sm O SO nanoplates transferred onto SiO /Si\n2 2 4 2\nsubstrate acquired at room temperature. f XPS patterns of Sm 3d orbitals. g STEM-\nEDS elemental mapping images of Sm O SO nanoplate. Scale bars: 0.5 µm. h An in-\n2 2 4\nplane atomic-resolution HAADF-STEM image of Sm O SO . Scale bars: 2 nm. i The\n2 2 4\nhigh-magnification HAADF-STEM image (top) and SAED pattern (bottom) of\nSm O SO nanoplate. Scale bars: 0.5 nm and 5 nm-1. j,k Cross-sectional atomic-\n2 2 4\nresolution HAADF-STEM images and corresponding atomic models of ultrathin\nSm O SO nanoplate taken along the zone axes of j [100], and k [1̅30]. Scale bars: 1\n2 2 4\nnm.\nSupplementary Fig. 5 | Raman spectra. (a, b) The Raman spectra and corresponding\n2D plot of the Sm O SO layer-dependent Raman spectrum, where the color reflects\n2 2 4\nthe relative intensity of the Raman vibration.\nComment 4: For XPS, the binding energy should be plotted from high to low value,\nnamely, reverse the direction of horizontal axis, in Figure 1f.\nResponse 4: Thank you for your valuable suggestion. We have adjusted the orientation\nof the x-axis in Fig. 1f (it has now been reversed) and updated the figure in the revised\nmanuscript accordingly.\nComment 5: STEM analysis, the plane distances are wrongly described as bonding\nlength of Sm-Sm atoms.\nResponse 5: We thank the reviewer for pointing out this imprecise terminology. The\nreviewer is absolutely correct that the distance measured directly from the STEM image\nis the interplanar spacing (d-spacing between Sm atomic columns) rather than the direct\natomic bond length. We have thoroughly revised the manuscript and replaced all\ninaccurate instances of “bond length” with the precise term “the interatomic spacing of\nSm-Sm”.\nComment 6: Figure 2f presents leakage current and breakdown characteristics for\nSm O SO of different thicknesses. However, only single measurements are shown for\n2 2 4\neach thickness. To ensure the reliability and reproducibility of the results, it is\nrecommended to perform and present at least five measurements per thickness.\nResponse 6: Thank you for the reviewer’s valuable comments regarding the leakage\ncurrent and breakdown characteristics of Sm O SO at different thicknesses presented\n2 2 4\nin Fig. 2f. We fully agree with the reviewer’s suggestion that ensuring the reliability\nand reproducibility of the results is essential. In response, we have performed at least\nfive independent measurements for each thickness in the revised experiments, as shown\nin Supplementary Fig. 17. All experimental results show consistent leakage current and\nbreakdown characteristics for different thicknesses of Sm O SO , which further\n2 2 4\nconfirm the reliability of the initially obtained data. Moreover, the experimental data\nindicate that for all thicknesses—8 nm, 10 nm, 17 nm, and 23 nm—the breakdown field\nstrength exceeds 10 MV/cm, demonstrating the excellent breakdown performance of\nSm O SO at varying thicknesses.\n2 2 4\nWe believe that these repeated experimental results significantly enhance the\nreliability and robustness of the data and conclusions presented in our work, providing\nfurther solid support for our findings. We have duly included these experimental data\nin the revised manuscript to ensure the comprehensiveness and reliability of the results.\nWe sincerely appreciate the reviewer’s suggestions, which have greatly contributed to\nthe improvement of our manuscript.\nSupplementary Fig. 17 | Breakdown characteristics and data of Sm O SO -based\n2 2 4\nMIM devices with different thicknesses. This figure shows the breakdown\ncharacteristics of Sm O SO -based metal-insulator-metal (MIM) devices with different\n2 2 4\nthicknesses: (a) 8 nm, (b) 10 nm, (c) 17 nm, and (d) 23 nm. The current-voltage (I-V)\ncurves demonstrate clear breakdown behavior under varying applied voltages, with the\ninset showing the schematic of the MIM structure. All devices exhibit a breakdown\nfield strength exceeding 10 MV/cm.\nComment 7: In the dielectric performance comparison shown in Figure 2h, data for\nMgNb O are missing, despite it being included in the caption. Moreover, several\n2 6\nrecently reported 2D gate dielectrics, such as Ga O and CaNb O , are not included.\n2 3 2 6\nIncorporating data for these materials would provide a more comprehensive and up-to-\ndate performance benchmark.\nResponse 7: Thank you for the reviewer’s valuable comment regarding the dielectric\nperformance comparison in Fig. 2h. We noticed that the data for MgNb₂O₆ was missing\nin the figure, and recently reported 2D gate dielectrics such as Ga₂O₃ and CaNb₂O₆ were\nalso not included. In the revised version, we have added the data for these materials to\nFig. 2h and updated the comparison analysis. We appreciate the reviewer’s suggestion,\nwhich has helped improve the figure.\nFig. 2 | Dielectric properties of quasi-vdW layered Sm O SO single crystal. a\n2 2 4\nSchematic (top) and OM image (right bottom) and Raman spectroscopy (left bottom)\nof the double-gate graphene (Gr) FET with the Sm O SO top-gate dielectric on SiO /Si\n2 2 4 2\nsubstrate. Scale bars: 5 µm. b Total resistance of a typical dual-gate graphene FET as\nthe function of top-gate voltages (V ) at different back-gate voltages (V ). c V -\ntg bg bg\ndependent top-gate Dirac point voltages of the dual-gate graphene FET. d Thickness-\ndependent C-V measurements of Sm O SO nanoplates at measurement frequency of\n2 2 4\n100 kHz. e Thickness-dependent dielectric constant of Sm O SO measured by the C-\n2 2 4\nV method. Inset: thickness dependent EOT of Sm O SO . f Current leakage and\n2 2 4\nbreakdown characteristics of Sm O SO nanoplates measured by MIM devices with\n2 2 4\nthicknesses ranging from 6.5 to 22.3 nm. g The breakdown field of Sm O SO at\n2 2 4\ndifferent temperatures. Inset: OM image of the MIM device. Scale bars: 5 µm. h\nBreakdown field versus effective dielectric constant of ultrathin Sm O SO , compared\n2 2 4\nwith various dielectric materials18,20,26,27,32-35,41-46.\nComment 8: Figure 3f, why there is no oxygen element?\nResponse 8: We thank the reviewer for the valuable comment. The oxygen elemental\nmap has been provided in the supplementary information (Supplementary Fig. 25),\nwhile Fig. 3f mainly presents the distribution of the key elements (Sm, Mo, and S).\nSupplementary Fig. 25 | Cross-sectional STEM image of an Sm O SO /MoS\n2 2 4 2\nheterointerface. (a, b) The atomic schematic and corresponding low-magnification\ncross-sectional HAADF-STEM image. Scale bar: 10 nm.\nComment 9: The authors fabricated Sm O SO /MoS top-gate FETs, however, a key\n2 2 4 2\nperformance parameter—carrier mobility—is not reported. Since mobility is critical for\nevaluating FET performance, its inclusion is necessary. Furthermore, in order to\nhighlight the advantages of Sm O SO , a comparative analysis with state-of-the-art\n2 2 4\nhigh-κ 2D dielectrics (e.g., D , SS, etc.) should be conducted.\nit\nResponse 9: We appreciate the reviewer’s valuable comments. In response to the\nquestion regarding carrier mobility, we have provided further explanations and\nclarifications in the revised manuscript. It is important to emphasize that field-effect\nmobility is typically extracted from transconductance 𝐺 , and the magnitude of 𝐺 is\n𝑚 𝑚\nphysically closely related to the on-state current of the channel. For thin-channel MoS\n2\ndevices, if the material quality is limited and the defect density is high, the on-state\ncurrent may be insufficient, leading to a reduced transconductance and consequently a\nlimited extracted mobility.\nIn the early experiments of this study, we used MoS crystals mechanically\n2\nexfoliated from natural molybdenite. These natural materials generally contain a\nrelatively high density of point defects and impurities, leading to strong scattering that\nlimits carrier mobility. As a result, both the on-state current and mobility of these\ndevices were relatively low. To obtain more representative device performance, we\nfurther introduced high-quality bulk MoS₂ single crystals grown by the chemical vapor\ntransport (CVT) method and prepared top-gate devices via mechanical exfoliation.\nBenefiting from the lower defect density and higher crystal quality, the channel on-state\ncurrent was significantly enhanced, reaching a magnitude of over 10-5 A, which\nmarkedly improves the observability of the transconductance signal.\nIn the newly added Supplementary Fig. 23, we systematically present the structure\nand electrical characteristics of these devices: (a) optical microscopy image showing a\nclearly defined channel region; (b) and (c) AFM morphology and height profile,\nconfirming a MoS₂ thickness of ~2.3 nm and Sm O SO dielectric thickness of ~15 nm;\n2 2 4\n(d) transfer characteristics at V =1.0 V, exhibiting typical field-effect modulation; (e)\nds\ntransconductance versus overdrive voltage extracted from the transfer curve, with a\nmaximum G of ~21 μS/μm; (f) field-effect mobility as a function of on-state current\nm\ndensity calculated from the transconductance, with a maximum mobility μmax of ~70\ncm² V⁻¹ s⁻¹. It should be noted that this performance approaches the reported optimum\nvalues for top-gate devices fabricated from high-quality exfoliated MoS and is\n2\nsignificantly higher than that obtained from devices based on natural MoS . This clearly\n2\ndemonstrates the decisive influence of channel material quality on transconductance\nand mobility. More importantly, this work further validates that Sm O SO , as a high-\n2 2 4\nquality gate dielectric layer in top-gate structures, effectively modulates the MoS\n2\nchannel, ensuring excellent device electrical performance.\nSupplementary Fig. 23 | Structure and electrical characteristics of the\nMoS /Sm O SO FET. (a) Optical micrograph of the device with a Sm O SO\n2 2 2 4 2 2 4\nthickness of ~15 nm. scale bar: 2 µm. (b) Atomic force microscopy (AFM) image\nshowing the MoS /Sm O SO heterostructure. scale bar: 0.5 µm. (c) AFM height\n2 2 2 4\nprofile along the line in panel b, confirming a MoS thickness of ~2.3 nm. (d) Transfer\n2\ncharacteristics (I -V ) measured at V = 1.0 V. (e) Transconductance characteristics\nds ov ds\n(G -V ) extracted from the transfer curve at V = 1.0 V. (f) Field-effect mobility (μ)\nm ov ds\nextracted from transconductance as a function of on-state current density (I ), showing\non\na peak mobility μ of ~70 cm2·V-1·s-1.\nmax\nIn addition, to better highlight the advantages of Sm O SO , we have included a\n2 2 4\ncomparative analysis with the most advanced high-κ 2D dielectric materials in the\nrevised manuscript. We have provided two tables, compared the interface state density\n(D ) and key dielectric parameters such as dielectric constant (𝜅), equivalent oxide\nit\nthickness (EOT), and hysteresis, and systematically compared Sm O SO with other\n2 2 4\nhigh-κ materials. These comparisons in the tables clearly present the key dielectric\nproperties and device performance metrics of each material, helping readers gain a\nclearer and more intuitive understanding of the advantages and potential limitations of\nSm O SO in these critical parameters.\n2 2 4\nFurthermore, we particularly emphasize the balance of dielectric constant and\nbandgap in Sm O SO . Compared to other high-κ materials, Sm O SO maintains a\n2 2 4 2 2 4\nrelatively high dielectric constant while possessing a wide bandgap, further enhancing\nthe device performance. At the same time, Sm O SO excels in subthreshold swing (SS),\n2 2 4\nequivalent oxide thickness (EOT), and hysteresis, ranking among the leading 2D\ndielectric materials. These advantages make Sm O SO a promising material for low-\n2 2 4\npower, high-performance applications.\nSupplementary Table 2. List of D values achieved by MoS FETs with various gate\nit 2\ndielectrics.\nDielectrics Dit (1012 cm-2 eV-1) Ref\nSm O SO 0.487 This work\n2 2 4\nCaF 10 14\n2 5\nMgNb O 0.4 19\n2 6\nGa O 0.4 18\n2 3\nGd O 2.2 16\n2 5\nGdOCl 0.781 21\nSupplementary Table 1. Integration of high-κ dielectrics on 2D semiconductors via\nvan der Waals (vdW) assembly.\nt E Hystere EOT SS\nbd\nκ I /I ref.\non off\n(nm) (MV/cm) sis (mV) (nm) (mV/dec)\nSb O 40 2.7 11.5 500 N/A 64 108 4\n2 3\nHfO 16 8 11 800 N/A 78 108 5\n2 3\nZrO (ZrS ) 1.4 7.22 19 N/A 0.29 90 105 8\n2 2\nY O 20 N/A 17-20 N/A 4.2 70 105 9\n2 3\nHfO /Sb O 4/1 19.3 17.5 N/A 0.67 60 109 10\n2 2 3\nHfO (HfS ) 3 9.33 ~10 10 N/A 63.1 108 11\nx 2\nBi SeO 20 16 21 N/A 0.9 75 105 12\n2 5\n22~10\nSrTiO 4~32 6.3 N/A 1 71.5 107 13\n3\n2\n23.8~3\nLaOCl 11.3 10.8 0~30 N/A N/A 105 15\n9.3\nGd O 8.5 15.7 25.5 N/A <1 61.5 108 16\n2 5\nCCTO 8 N/A 42.9 2.4 0.9 67 106 17\nGa O 2.7 11 30 N/A 0.4 60 108 18\n2 3\nMgNb O 15 16 20 0.9 1 62 107 19\n2 6\nSr Nb O 57 N/A 24.6 N/A N/A 88 106 20\n2 3 10\nGdOX\n（X=Cl, 16 13.5 18.9 12 N/A 155 109 21\nBr）\nEu SO 12-14 >10 23.4 5.3 1 63.5 108 22\n2 x\nMn O 39 13.2 237 5 0.57 84 108 23\n3 4\nCaNb O 2.9 12 16 10 0.7 61 107 24\n2 6\nThis\nSm O SO 14.6 >12 17.8 5.4 1.7 65.2 107\n2 2 4\nwork\nComment 10: The manuscript describes the development of an ultrafast floating-gate\nnonvolatile memory. However, in Figure 4c, the gate voltage sweep rate is not specified.\nIf sweep rate may significantly influence the memory window, the authors should\nprovide this information and discuss its impact.\nResponse 10: We appreciate the reviewer’s valuable feedback. Regarding the effect of\ngate voltage scan rate on the memory window, we conducted experiments and present\nthe results in Fig. R5. By comparing the memory window curves at different scan rates\n(S = 400 mV/s, 200 mV/s, and 100 mV/s), we observed that the memory window (ΔV)\nsize remains approximately 31 V with varying scan rates, indicating that the gate\nvoltage scan rate does not have a significant impact on the memory window.\nFig. R5 | Effect of gate voltage scan rate on the current-gate voltage characteristics\nof the floating-gate memory.\nComment 11: While the manuscript claims low-power operation for the floating-gate\ndevice, no quantitative value for power consumption is provided. The authors should\nexplicitly state the power consumption of the memory device to substantiate this claim.\nResponse 11: We would like to thank the reviewer for their valuable comments on the\npower consumption calculations in our work. Based on the reviewer's suggestions, we\nhave further analyzed the power consumption of the floating-gate memory and\nperformed the necessary calculations. To clearly demonstrate the low-power\ncharacteristics of the floating-gate memory, we have added a detailed explanation of\nthe power consumption calculation process in the revised manuscript. Below are the\nresults of our analysis:\nPower Consumption Calculation Overview\nIn our power consumption calculations, we focused on two main contributions: gate\ncapacitance power consumption and leakage current power consumption.\nGate Capacitance Power Consumption\nThe gate capacitance power consumption is determined by the gate capacitance and\nthe operating frequency. The formula is as follows:\nW= P ·𝑡= C ·𝑉 2f·𝑡 (1)\nload load 𝐷𝐷\nwhere:\n C load is the gate capacitance,\n V DD is the gate voltage,\n f is the operating frequency.\n t is the pulse time\nLeakage Current Power Consumption\nThe leakage current power consumption is straightforward to calculate using the\nformula:\nW= P ·𝑡= I ·𝑉 ·𝑡 (2)\nleak leak 𝐷𝐷\nwhere I is the leakage current.\nleak\nSummary of Power Consumption\nBased on the above formulas, the power consumption of the floating-gate memory\ncan be summarized as follows:\n Gate capacitance power consumption: approximately 2.97 pJ.\n Leakage current power consumption: approximately 5.5 × 10-23 J.\nOverall, the power consumption per pulse is mainly due to dynamic power, with\nan energy of approximately 2.97 pJ, while static power consumption is negligible.\nComment 12: The term “ultrafast” is used to describe the floating-gate memory device,\nbut no clear evidence is provided to justify this designation. For comparison, prior work\nhas demonstrated programming/erasing speeds as fast as 20 ns\n(https://doi.org/10.1002/adma.202311652). Can the authors achieve similar speeds with\ntheir device? A comparative analysis of key performance metrics is necessary to clearly\nillustrate the role and advantage of Sm O SO in floating-gate nonvolatile memory\n2 2 4\napplications.\nResponse 12: We appreciate the reviewer’s valuable comments regarding the dynamic\nperformance of the device. In response to your concern about the \"ultrafast\" description,\nwe have provided further clarification in the revised manuscript. We have presented\nadditional experimental data to demonstrate the programming/erasing speed of the\nSm₂O₂SO₄-based floating-gate memory device. Supplementary Fig. 29a shows the\ncurrent response (I ) of the device after a single program (black) and erase (red)\nds\noperation, clearly demonstrating well-distinguished program and erase states,\nindicating reliable state switching in a single operation. Supplementary Fig. 29b\npresents the control gate voltage (V ) waveforms, where the left panel corresponds to\ncg\na -22.4 V erase pulse (red, full width at half maximum, FWHM = 55.9 ns) and the right\npanel corresponds to a +22.5 V program pulse (black, FWHM = 54.2 ns). These results\nindicate that the device can complete programming and erasing operations within\nnanoseconds, demonstrating both stable memory states and high-speed operation,\nwhich are essential for high-performance non-volatile memory applications.\nAlthough some previous studies have reported programming/erasing speeds as fast\nas 20 ns (e.g., https://doi.org/10.1002/adma.202311652), our device exhibits\nperformance close to this level, with programming/erasing speeds of 55.9 ns and 54.2\nns, respectively. Due to limitations in the experimental equipment, we have not yet been\nable to test the device at sub-nanosecond (sub-ns) speeds. However, our future research\nwill focus on further optimizing the programming/erasing speed and achieving sub-\nnanosecond operation speeds. By improving the experimental setup and optimizing the\nperformance of Sm₂O₂SO₄, we expect to enhance the device's speed and drive the\nprogress of 2D memory technology.\nSupplementary Fig. 29 | Fast program/erase characteristics of the Sm O SO -\n2 2 4\nbased floating-gate device. (a) Current response (I ) of the device after applying a\nds\nsingle program operation (black) and an erase operation (red), clearly showing well-\ndistinguished program and erase states. (b) Output voltage waveforms (V ) generated\ncg\nby a Keithley 4200 system: the left panel corresponds to the -22.4 V erase pulse (red,\nfull width at half maximum, FWHM = 55.9 ns), and the right panel corresponds to the\n+22.5 V program pulse (black, FWHM = 54.2 ns).\nTo better demonstrate the role and advantages of Sm₂O₂SO₄ in floating-gate non-\nvolatile memory applications, we compared the performance metrics of the latest\nfloating-gate memory devices and compiled the following Supplementary Table 3.\nBased on the data in the Supplementary Table 3, the Sm₂O₂SO₄-based floating-gate\nmemory device shows significant advantages in terms of memory window, low\noperating voltage, high programming/erasing speed, and other performance aspects.\nSpecifically:\n(1) Memory Window: The memory window of the Sm O SO -based memory device\n2 2 4\nis below 3 V, providing higher storage capacity and better stability compared to\nother materials at low voltages.\n(2) Programming/Erasing Voltage: The device enables efficient\nprogramming/erasing operations at a low voltage of 3 V, significantly reducing\npower consumption.\n(3) Programming/Erasing Speed: The programming/erasing speed of the Sm O SO -\n2 2 4\nbased memory device reaches 55.9 ns and 54.2 ns, placing it among the leaders in\nstorage speed, demonstrating faster operational performance.\n(4) On/Off Ratio: The Sm O SO -based floating-gate memory device has an on/off\n2 2 4\nratio of 10⁷, indicating its potential for high-speed storage applications.\n(5) Endurance: The device exhibits more than 2000 cycles of endurance, ensuring\nlong-term stable usage.\nIn conclusion, the Sm O SO -based floating-gate memory device ranks among the\n2 2 4\ntop in the field of 2D memory, particularly excelling in low voltage, high-speed\nprogramming/erasing operations, and large memory window, showcasing its significant\npotential for future memory applications. Through this comparison of key performance\nmetrics, we clearly demonstrate the role and advantages of Sm O SO in floating-gate\n2 2 4\nnon-volatile memory devices and confirm its promising future in memory technology.\nSupplementary Table 3. Comparison of the performance of our floating-gate\nmemory devices based on all-2D materials with other devices partially based on\n2D materials\nWrite/erase Retention Endurance Memory\nDevice structure Voltage I /I ref.\non off\npluse performance Performance Window\nMoS /hBN/MLG/hBN/MLG\n2\n(All 2D Materials)\nMoS /Al O /Pt/SiO /Si 3 V 109 ~5 μs ~104 s 105 cycles 78% 27\n2 2 3 2\nMoS /hBN/MLG/SiO /Si 15 V 109 10-100 ns >104 s >106 cycles 56% 28\n2 2\nReSe /hBN/Gr/SiO /Si 12 V >104 4 ms >103 s >3000 cycles >70% 29\n2 2\nMoS /HfO /HfS /HfO /Au 5 V 107 1 ms >105 s >1000 cycles 56% 30\n2 x 2 x\nMoTe /hBN/Gr/SiO /Si 17 V 104 4 ms 103 s 1000 cycles 65% 31\n2 2\nInSe (MoS )/hBN/MLG\n2\n/SiO /Si\n2 2\nMoS /hBN/MLG/Sm O SO / -22.4/22.5 This\n2 2 2 4\n107 55.9/54.2 ns ~104 s ~2000 cycles 75%\nMLG V work\nComment 13: English should be further improved. For example, Raman spectrums->\nspectra; XPS patterns -> XPS spectra.\nResponse 13: We appreciate the reviewer’s suggestion. The expressions such as\n“Raman spectrums” and “XPS patterns” have been corrected to “Raman spectra” and\n“XPS spectra” in the revised manuscript."}, {"round": 2, "reviewer_comments": {"reviewer_1": "Judging from the feedback of the response letters, my concerns have already been addressed.I suggest the acceptance of this revised manuscript in terms of considering other responsive questions.", "reviewer_2": "1.Field-effect mobility (μ) is usually extracted from transfer curve in linear region at small Vds. Therefore, it is wrong to use high Vds of 1V for Fig. S23.\n2.In Fig. S23d, why the author use Vov instead of Vgs? The thickness of dielectrics is 15 nm and the breakdown voltage is very high. Why the range of gate voltage is so small? It also didn’t show off-state and saturation regions. What’s the output curves? The on/off ratio is also much less than the back gate. Why?\n3.In Fig. S23f, why the X axis is Ion? This is hard to understand and not a common plot way in the literature.\n4.What’s mobility of MoS2 in Fig. 3c? Rc of 0.97 kΩ·μm is a good value. But why the drain current is so low in Fig. S24b?\n5.In Fig. S19a, the drain current for Lch= 100 nm is ~32uA/um at Vd = 0.1 V, which is much higher than that in Fig. S24b.\nPlease provide the detailed reasons. The SEM image is also difficult to understand. Please add annotation.", "reviewer_3": "The authors have mostly addressed previous reviewer comments with substantial supplementary data, greatly strengthening the manuscript's validity and impact. The work is now highly mature and reliable. For final acceptance, there are a few points that require attention:\n1. The molten-salt-assisted CVD approach is elegantly demonstrated. However, given the multi-component nature of the precursor (Sm, O, S), could the authors provide insights into how they ensured the phase purity of Sm2O2SO4 and avoided the formation of other competing phases, such as Sm2O3 or Sm2(SO4)3?\n2. The uniformity of device performance is critical for future electronics. As a fundamental component, the assessment of transistors necessitates more devices and a statistical analysis of key figures of merit, such as mobility and on/off current ratio."}, "author_response": "REVIEWER COMMENTS AND RESPOSNSES\nNote: [All newly added experimental images and revised content in the manuscript are\nmarked in red font. All newly added experimental images and related content, except\nfor those with titles starting with Fig. R, have been marked in red in the manuscript and\nsupplementary materials.]\nReviewer #1 (Remarks to the Author):\nJudging from the feedback of the response letters, my concerns have already been\naddressed. I suggest the acceptance of this revised manuscript in terms of considering\nother responsive questions.\nResponse: We sincerely appreciate the reviewer for the thorough review of my\nmanuscript and for providing valuable comments and suggestions. Your expert\nfeedback has not only helped me improve the paper but has also enhanced the quality\nof the research.\nReviewer #2 (Remarks to the Author):\nComment 1: Field-effect mobility (μ) is usually extracted from transfer curve in linear\nregion at small V . Therefore, it is wrong to use high V of 1V for Fig. S23.\nds ds\nResponse 1: We thank the reviewer for highlighting the improper use of a high drain-\nsource voltage (V =1.0 V) for extracting the field-effect mobility in Fig. S23. We fully\nds\nagree that mobility should be extracted from the transfer characteristics measured in the\nlinear regime under a small V , so that the obtained μ reliably reflects the intrinsic\nds\nchannel transport rather than high-bias effects. Using V =1.0 V is therefore\nds\ninappropriate.\nIn response, we have re-measured and included the transfer curves at V = 0.1 V in the\nds\nrevised Fig. S23. The field-effect mobility has been recalculated based on these low-\nbias measurements, and all related mobility values in the figure have been corrected\naccordingly. This modification ensures that the extracted μ is accurate and consistent\nwith standard extraction procedures.\nSupplementary Fig. 23 | Structure and electrical characteristics of the\nMoS /Sm O SO FET. (a) Optical micrograph of the device with a Sm O SO\n2 2 2 4 2 2 4\nthickness of ~15 nm. scale bar: 2 µm. (b) Atomic force microscopy (AFM) image\nshowing the MoS /Sm O SO heterostructure. AFM height profile along the line in\n2 2 2 4\npanel b, confirming a MoS thickness of ~2.3 nm. scale bar: 0.5 µm. (c) Output\n2\ncharacteristics showing the variation of drain-source current (I ) with different top-gate\nds\nvoltages (V ) from -2.0 V to 2.0 V, measured with a step of 0.1 V. (d) Transfer\nbg\ncharacteristics (I -V ) measured at V = 0.1 V and V = 1.0 V. (e) Transconductance\nds g ds ds\ncharacteristics (G -V ) extracted from the transfer curve at V = 1.0 V. (f) The field-\nm g ds\neffect mobility (μ) extracted from panel d as a function of gate voltage (V ), showing a\ng\npeak mobility μ of approximately 81 cm2·V-1·s-1.\nmax\nComment 2: In Fig. S23d, why the author use V instead of V ? The thickness of\nov gs\ndielectrics is 15 nm and the breakdown voltage is very high. Why the range of gate\nvoltage is so small? It also didn’t show off-state and saturation regions. What’s the\noutput curves? The on/off ratio is also much less than the back gate. Why?\nResponse 2: We thank the reviewer for the insightful questions. Our detailed responses\nare provided below.\n1. Regarding the use of V instead of V ：In the original Fig. S23d, we used the\nov gs\noverdrive voltage V =V -V to more directly represent the effective gate modulation\nov gs th\nafter removing the threshold voltage offset. However, we agree that using V is more\ngs\nconventional and facilitates clearer comparison with other device configurations.\nFollowing the reviewer’s suggestion, we have revised Fig. S23 and now present the\ncurves as a function of V on the x-axis. This ensures consistency with standard\ngs\nreporting practices.\n2. Regarding the limited gate-voltage range, and the lack of off-state and\nsaturation regions: The previous version focused mainly on the on-state\ncharacteristics, which resulted in a narrower V window and did not fully display the\ng\noff-state, transition, and saturation regions. In the revised manuscript, we have\nexpanded the V sweep to cover the entire operating range of the 15-nm dielectric and\ng\nhave re-plotted both the complete transfer curves and output characteristics. The\nupdated Fig. S23c now clearly shows the off-state region, the transition to conduction,\nand the on-state saturation behavior. The full output characteristics under different V\ngs\nvalues are also included.\n3. Regarding the on/off ratio being smaller than that of the back-gate\nconfiguration: After re-plotting the data with the corrected V range, the transfer\ngs\ncharacteristics indicate that the device exhibits an on/off ratio exceeding 10⁹ under\nproper gating conditions. This value is comparable to, and in some cases even higher\nthan, that obtained in the back-gate configuration. The updated data and corresponding\nplots in Fig. S23 confirm that there is no issue of reduced switching ratio.\nSupplementary Fig. 23 | Structure and electrical characteristics of the\nMoS /Sm O SO FET. (a) Optical micrograph of the device with a Sm O SO\n2 2 2 4 2 2 4\nthickness of ~15 nm. scale bar: 2 µm. (b) Atomic force microscopy (AFM) image\nshowing the MoS /Sm O SO heterostructure. AFM height profile along the line in\n2 2 2 4\npanel b, confirming a MoS thickness of ~2.3 nm. scale bar: 0.5 µm. (c) Output\n2\ncharacteristics showing the variation of drain-source current (I ) with different top-gate\nds\nvoltages (V ) from -2.0 V to 2.0 V, measured with a step of 0.1 V. (d) Transfer\nbg\ncharacteristics (I -V ) measured at V = 0.1 V and V = 1.0 V. (e) Transconductance\nds g ds ds\ncharacteristics (G -V ) extracted from the transfer curve at V = 1.0 V. (f) The field-\nm g ds\neffect mobility (μ) extracted from panel d as a function of gate voltage (V ), showing a\ng\npeak mobility μ of approximately 81 cm2·V-1·s-1.\nmax\nComment 3: In Fig. S23f, why the X axis is I ? This is hard to understand and not a\non\ncommon plot way in the literature.\nResponse 3: We thank the reviewer for pointing out this issue. We agree that using I\non\nas the X-axis is unconventional and may cause confusion, as it is not a standard way of\npresenting mobility-related plots in the field. In response to the reviewer’s suggestion,\nwe have revised Fig. S23f by replacing the X-axis with V . This modification makes\ng\nthe figure more intuitive and consistent with common practice in the literature, and it\nmore clearly presents the intended mobility-related trend.\nSupplementary Fig. 23 | Structure and electrical characteristics of the\nMoS /Sm O SO FET. (a) Optical micrograph of the device with a Sm O SO\n2 2 2 4 2 2 4\nthickness of ~15 nm. scale bar: 2 µm. (b) Atomic force microscopy (AFM) image\nshowing the MoS /Sm O SO heterostructure. AFM height profile along the line in\n2 2 2 4\npanel b, confirming a MoS thickness of ~2.3 nm. scale bar: 0.5 µm. (c) Output\n2\ncharacteristics showing the variation of drain-source current (I ) with different top-gate\nds\nvoltages (V ) from -2.0 V to 2.0 V, measured with a step of 0.1 V. (d) Transfer\nbg\ncharacteristics (I -V ) measured at V = 0.1 V and V = 1.0 V. (e) Transconductance\nds g ds ds\ncharacteristics (G -V ) extracted from the transfer curve at V = 1.0 V. (f) The field-\nm g ds\neffect mobility (μ) extracted from panel d as a function of gate voltage (V ), showing a\ng\npeak mobility μ of approximately 81 cm2·V-1·s-1.\nmax\nComment 4: What’s mobility of MoS in Fig. 3c? Rc of 0.97 kΩ·μm is a good value.\nResponse 4: Thank you for the reviewer’s question. Our detailed response is as follows:\n1. Regarding the mobility of MoS in Fig. 3c: We calculated the mobility of MoS\n2 2\nin Fig. 3c, and as shown in Fig. R1, the mobility (μ) of the MoS device is\n2\napproximately 2.6 cm2·V-1·s-1. This value represents the peak mobility extracted\nas a function of the gate voltage (V ) at V = 0.1 V, reflecting the conductive\ng ds\ncharacteristics of the device.\n2. Regarding the low leakage current in Fig. S24b: The short-channel devices\ndisplayed in Fig. S24 were fabricated during the early stage of developing our\nnanofabrication process. At that time, we primarily used MoS₂ flakes mechanically\nexfoliated from natural molybdenite, which typically contains a relatively high\ndensity of point defects, sulfur vacancies, and unintentional impurities. These\nintrinsic defects strongly enhance carrier scattering and significantly limit the\ncarrier mobility. Consequently, the resulting short-channel devices exhibit lower\non-state current and mobility, which is consistent with the reduced drain currents\nobserved in Fig. 3c and Fig. S24b.\nAs our short-channel fabrication process was further optimized, we introduced\ncommercially purchased high-purity MoS single crystals with much lower defect\n2\ndensities. Using these improved crystal sources, we were able to build high-quality\nshort-channel FETs, as shown in Supplementary Fig. S19. These later-stage\ndevices exhibited a substantially higher channel current, often exceeding 10-5A,\nand also demonstrated more stable transfer and output characteristics. The\nextracted contact resistance (Rc ≈ 0.97 kΩ·μm) from these high-quality devices is\ntherefore representative of the performance achievable with optimized materials\nand processing.\nOverall, the lower current in Fig. S24b originates from defect-limited mobility of\nthe early-stage natural MoS flakes, rather than from contact issues. The improved\n2\ndevices fabricated with high-quality crystals, which is presented in Fig. S19\nshowing significantly enhanced performance and reconcile the apparent\ndiscrepancy.\nFig. R1 | The field-effect mobility (μ) extracted from Figure 3c as a function of gate\nvoltage (V ), showing a peak mobility μ of approximately 2.6 cm2·V-1·s-1.\ng max\nSupplementary Fig. 24 | Transfer and output characteristics of the back-gated\nshort-channel MoS FET. (a) Transfer characteristics of the short-channel MoS FET,\n2 2\nshowing a switching ratio of approximately 106 and a subthreshold swing (SS) of 72\nmV/decade, measured at different drain-source voltages (V = 0.1 V, 0.5 V, and 1.0 V).\nds\nThe inset shows the scanning electron microscope (SEM) image of the device with a\nchannel length (L ) of approximately 100 nm, scale bar: 400 nm. (b) Output\nch\ncharacteristics showing the variation of drain-source current (I ) with different back-\nds\ngate voltages (V ) from -4.0 V to 4.0 V, measured with a step of 0.8 V.\nbg\nSupplementary Fig. 19 | Transfer and resistance characteristics of short-channel\nMoS FETs with varying channel lengths. (a) Transfer characteristics of MoS FETs\n2 2\nwith channel lengths (L ) ranging from 0.1 μm to 1.5 μm, measured at a drain-source\nch\nvoltage (V ) of 0.1 V. The inset shows the scanning electron microscope (SEM) image\nds\nof the devices with different channel lengths, where the golden area represents the\nsource and drain electrodes made of Au, and the green area represents MoS , scale bar:\n2\n5 μm. (b) The total resistance (R ) as a function of channel length (L ), showing the\ntot ch\ntrend of contact resistance (R ) variation with channel length. The contact resistance\nc\n(R ) is extracted using the TLM method and normalized to a carrier density (nₛ) of\nc\n1.0×1013 cm-2. Based on the extraction results, 2R is 1.94 kΩ·μm, and the contact\nc\nresistance (R ) is 0.97 kΩ·μm.\nc\nComment 5: In Fig. S19a, the drain current for L = 100 nm is ~32uA/um at V = 0.1\nch d\nV, which is much higher than that in Fig. S24b. Please provide the detailed reasons. The\nSEM image is also difficult to understand. Please add annotation.\nResponse 5: We thank the reviewer for these constructive comments. Our detailed\nexplanations are provided below.\nThe discrepancy between the drain current in Supplementary Fig. S19a (e.g., ~32\nµA/µm at 𝐿 =100 nm and V =0.1 V) and that in Supplementary Fig. S24b originates\nch ds\nfrom the different crystal qualities and fabrication stages associated with the two sets\nof devices. The devices shown in Fig. S24 were fabricated at the initial stage of our\nshort-channel process development. At that time, MoS flakes were mechanically\n2\nexfoliated from natural molybdenite, which typically contains a high density of sulfur\nvacancies, point defects, and unintentional impurities. These defects strongly enhance\nelectron scattering and therefore suppress mobility and on-state current, leading to the\nrelatively low drain currents observed in Fig. 3c and Fig. S24b.\nAs our fabrication process improved, we transitioned to using commercial high-quality\nMoS₂ single crystals with substantially lower defect densities. With these higher-quality\nmaterials and refined lithography/etching processes, we were able to fabricate\nrepresentative short-channel devices with significantly improved electronic\nperformance, as presented in Supplementary Fig. S19. These optimized devices exhibit\nmuch higher channel conduction currents (exceeding 10-5A) and much more stable\noutput behavior, which accounts for the higher drain current seen in the 100-nm-\nchannel device of Fig. S19a.\nTo improve clarity, we have added explicit annotations to the SEM images in\nSupplementary Fig. S19, marking the MoS₂ channel region, source/drain electrodes,\nand channel length. Additional explanations have also been included in the revised\nfigure caption to ensure that the device geometry is easy to understand.\nSupplementary Fig. 19 | Transfer and resistance characteristics of short-channel\nMoS FETs with varying channel lengths. (a) Transfer characteristics of MoS FETs\n2 2\nwith channel lengths (L ) ranging from 0.1 μm to 1.5 μm, measured at a drain-source\nch\nvoltage (V ) of 0.1 V. The inset shows the scanning electron microscope (SEM) image\nds\nof the devices with different channel lengths, where the golden area represents the\nsource and drain electrodes made of Au, and the green area represents MoS , scale bar:\n2\n5 μm. (b) The total resistance (R ) as a function of channel length (L ), showing the\ntot ch\ntrend of contact resistance (R ) variation with channel length. The contact resistance\nc\n(R ) is extracted using the TLM method and normalized to a carrier density (nₛ) of\nc\n1.0×1013 cm-2. Based on the extraction results, 2R is 1.94 kΩ·μm, and the contact\nc\nresistance (R ) is 0.97 kΩ·μm.\nc\nReviewer #3 (Remarks to the Author):\nThe authors have mostly addressed previous reviewer comments with substantial\nsupplementary data, greatly strengthening the manuscript's validity and impact. The\nwork is now highly mature and reliable. For final acceptance, there are a few points that\nrequire attention:\nComment 1: The molten-salt-assisted CVD approach is elegantly demonstrated.\nHowever, given the multi-component nature of the precursor (Sm, O, S), could the\nauthors provide insights into how they ensured the phase purity of Sm O SO and\n2 2 4\navoided the formation of other competing phases, such as Sm O or Sm (SO ) ?\n2 3 2 4 3\nResponse 1: Thank you for the reviewer’s question. We employed the molten salt-\nassisted chemical vapor deposition (CVD) method to ensure the phase purity of\nSm2O2SO4 during the growth process, avoiding the formation of other competing\nphases, primarily through the following factors:\n1. Avoiding the formation of Sm O : Sulfate (SO₄²⁻) tends to decompose and rearrange\n2 3\nabove 700 °C, leading to the formation of phases like Sm O , which typically requires\n2 3\nhigh temperatures (>800 °C) for growth. However, our growth temperature is around\n680 °C, which is close to the melting point of KI (~681 °C), allowing partial melting of\nKI to assist in precursor dissolution and ion transport without requiring excessively\nhigh temperatures. Because the growth temperature is relatively low, far below the high\ntemperature of 800 °C, we effectively avoid the decomposition of sulfate, thus\nsuppressing the formation of Sm O .\n2 3\n2. Avoiding the formation of Sm (SO ) : Regarding the formation of Sm (SO ) ,\n2 4 3 2 4 3\nwe\nbelieve that at the appropriate growth temperature, the KI molten salt provides a\nrelatively stable environment. At the lower temperature of approximately 680 °C, the\nhigh polarization and chemical inertness of KI offer a flexible ionic environment that\npromotes the preferential epitaxial stacking of the Sm-O-S layers, without excessively\npromoting the decomposition or rearrangement of SO₄²⁻ groups. Although SO₄²⁻ is\nprone to decomposition or rearrangement at higher temperatures, the KI molten salt\nenvironment effectively suppresses this phenomenon, ensuring that only the pure phase\nof Sm O SO is formed in this growth window and preventing the formation of by-\n2 2 4\nproducts such as Sm (SO ) .\n2 4 3\n3. Selective ion coordination and flexible ionic environment: The high polarization and\nchemical inertness of I⁻ ions provide a flexible ionic environment that effectively\nsuppresses vertical grain coarsening and ensures the unidirectional layered epitaxial\ngrowth of Sm O SO . Additionally, the volatility of I⁻ ions allow them to gradually\n2 2 4\nescape from the system during the later stages of growth, avoiding residual interference\nwith the crystal structure, thus ensuring the phase purity of Sm O SO .\n2 2 4\nIn summary, by controlling the growth temperature and utilizing the unique\nproperties of KI molten salt, we successfully suppressed the formation of competing\nphases such as Sm O and Sm (SO ) , ensuring the phase purity of Sm O SO .\n2 3 2 4 3 2 2 4\nSpecifically, at the lower growth temperature (~680 °C), we effectively avoided the\nformation of Sm O , as temperatures above 800 °C are required for its formation.\n2 3\nComment 2: The uniformity of device performance is critical for future electronics. As\na fundamental component, the assessment of transistors necessitates more devices and\na statistical analysis of key figures of merit, such as mobility and on/off current ratio.\nResponse 2: Thank you for the reviewer’s valuable comments. We fully agree that the\nuniformity of device performance is crucial for the future of electronic devices. As a\nfundamental component, transistor performance evaluation indeed requires testing a\nlarger number of devices and performing statistical analysis of key performance\nindicators such as mobility and on/off current ratio. To this end, we present the I -V\nds tg\ncharacteristics of 10 MoS top-gated FET devices in Supplementary Fig. 25 and have\n2\nconducted a detailed electrical statistical analysis. The results show that all devices\nexhibit steep subthreshold slopes, and both the on/off ratio and field-effect mobility\nfollow a Gaussian distribution, with average values of 7×106 and 48.6 cm2·V-1·s-1,\nrespectively. These statistical data demonstrate the consistency and stability of the\ndevices, thereby validating the excellent performance and wide application potential of\nMoS top-gated FETs.\nds tg 2"}, {"round": 3, "reviewer_comments": {"reviewer_2": "For final acceptance, there are a few points that require attention:\n1.The unit in Fig. S23c is wrong.\n2. The author needs to use Vtg or Vbg to distinguish between different devices, as using Vg may mislead readers. At the same time, the thickness of MoS2 must be clearly indicated for all the devices.\n3. The IdVd curves of Supplementary Fig. 25 should be provided.", "reviewer_3": "I suggest the acceptance of the revised manuscript in present form. No further revision is requested."}, "author_response": "REVIEWER COMMENTS AND RESPOSNSES\nReviewer #2 (Remarks to the Author):\nComment 1: The unit in Fig. S23c is wrong.\nResponse: Thank you for the thorough review. Your comment is absolutely correct; the\nunit label in Fig. S23c was indeed erroneous. We have corrected it in the revised\nmanuscript.\nSupplementary Fig. 23 | Structure and electrical characteristics of the\nMoS /Sm O SO FET. (a) Optical micrograph of the device with a Sm O SO\n2 2 2 4 2 2 4\nthickness of ~15 nm. scale bar: 2 µm. (b) Atomic force microscopy (AFM) image\nshowing the MoS /Sm O SO heterostructure. AFM height profile along the line in\n2 2 2 4\npanel b, confirming a MoS thickness of ~2.3 nm. scale bar: 0.5 µm. (c) Output\n2\ncharacteristics showing the variation of drain-source current (I ) with different top-gate\nds\nvoltages (V ) from -2.0 V to 2.0 V, measured with a step of 0.1 V. (d) Transfer\nbg\ncharacteristics (I -V ) measured at V = 0.1 V and V = 1.0 V. (e) Transconductance\nds g ds ds\ncharacteristics (G -V ) extracted from the transfer curve at V = 1.0 V. (f) The field-\nm g ds\neffect mobility (μ) extracted from panel d as a function of gate voltage (V ), showing a\ng\npeak mobility μ of approximately 81 cm2·V-1·s-1.\nmax\ntg bg\nas using V may mislead readers. At the same time, the thickness of MoS must be\ng 2\nclearly indicated for all the devices.\nResponse: Thank you for your valuable comments. You are absolutely correct in\npointing out the potential ambiguity caused by using \"V \" To accurately distinguish\ng\nbetween the gate structures of different devices, we have uniformly revised all relevant\nfigures, formulas, and textual descriptions.\nComment 2: The I -V curves of Supplementary Fig. 25 should be provided.\nd d\nResponse: We have added the relevant data in the Supplementary Figure 25 and made\ncorresponding updates to the main text.\nSupplementary Fig. 25 | Electrical characteristics of the top-gated MoS FET\n2\narray. (a) I -V curves of all 10 devices in the array (MoS thickness: 1.96 nm). Inset:\nds tg 2\ncorresponding scatter distribution of the extracted mobilities and on/off ratios. (b) I -\nds\nV output characteristics measured under varying top-gate voltage.\nds"}]

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