Ferroelectricity-modulated asymmetric van der Waals heterostructure for ultralow-power neuromorphic synapse and logic-in-memory operations

Domain: chemistry
Published: 2026-03-14
Editorial outcome: minor_revision

Abstract
Vertical integration of two-dimensional materials holds tremendous potential for integrated
sensing, memory and computing applications, yet it still confronts challenges such as single device
functionality, limited in-memory logic capability and high power consumption. To address these
issues, we propose an asymmetric van der Waals integration strategy based on an
In₂Se₃/MoOₓ/MoS₂/graphene heterojunction, which integrates five reconfigurable logic gates
(AND, OR, NOT, NOR, and NAND), dual-mode photodetection (~10 fA dark current, a high
responsivity of 89.3 mA/W and a specific detectivity of 1.4 × 10¹¹ Jones), and low-power
neurosynaptic functions (7-bit conductance states, subfemtojoule energy consumption) into a
single device. By virtue of these characteristics, the device enables high-precision image
recognition, simulation of classical Pavlovian conditioning and single-pixel dual-band optical
imaging. This work paves a feasible path for the development of multifunctionally integrated
sensor-memory-computing devices.

Introduction
In recent years, the rapid advancement of the Internet of Things (IoT) and artificial
intelligence (AI) has placed huge demands on the data processing capabilities of terminal devices1-
8. The traditional von Neumann architecture, characterizEed by its separation of memory and
computing9-12, faces challenges such as the "memRory wall" bottleneck and high power
consumption when processing massive sensory
data1P3-15.
Inspired by the highly efficient and low-
power perception and information processinNg mechanisms in biological systems16-18, the
development of sensing-memory-computinIg integrated devices has become crucial for
overcoming the limitations of convEentional computing and advancing next-generation
neuromorphic computing and artificiaLl vision systems19-21.
Among various candidate mIaterials, 2D layered materials have emerged as an ideal platform
for building next-generation optoelectronic devices due to their electrical and optical properties,
atomic-scale thickness, and exceptional integration potential in the post-Moore era22-26. Notably,
in-memory logic computing devices constructed from 2D heterostructures enable high-speed and
high-precision information processing27-29; photodetectors are capable of mimicking artificial
visual perception, showing significant potential in target recognition and imaging applications30-
32; while photonic synaptic devices can directly convert incident optical signals into synaptic
weight updates, offering a highly attractive in-sensor computing solution for the efficient
integration of visual perception and neuromorphic computing33-36. Although these devices show
great potential within their respective domains, integrating multiple functions into a single device
remains a major challenge.
To address these issues, researchers have begun exploring the use of intrinsic physical
properties of materials (such as ferroelectricity) for functionality control37-39. Among these, 2D
ferroelectric materials (such as α-In₂Se₃) leverage their non-volatile polarization states to
effectively modulate carrier transport behavior and alter the band structure of heterojunctions40-44,
thereby opening new pathways for designing low-power, multifunctional optoelectronic devices25.
Recent theoretical predictions suggest that α-In₂Se₃ and MoS₂ form two type-II band-aligned
heterostructure45, wherein the ferroelectric polarization field of α-In₂Se₃ can effectively tune the
interface barrier and channel conductance, offering flexibility for designing photodetection and
synaptic devices. More importantly, large-scale growth processes for both MoS₂ and α-In₂Se₃ thin
films have been successively demonstrated by relevant research groups, highlighting the
substantial potential of these two materials for practical applications42, 46.
Herein, we develop a dual-terminal In₂Se₃/MoOₓ/MoS₂/Gra heterojunction device that
integrates multiple functions, including five classic Boolean logic-in-memory operations, broad-
spectrum photoelectric synaptic plasticity, and photodetection. By leveraging the polarization
modulation of In₂Se₃ to tailor the band alignment at the In₂Se₃/MSoOₓ/MoS₂ interface, the device
exhibits electrically tunable positive and negative photorespSonses, successfully emulating five
fundamental Boolean logic operations—AND, OR, NOTE, NOR, and NAND—within a single
device. Furthermore, through the synergy between In₂Se₃ ferroelectric polarization and defect
engineering in MoOₓ/MoS₂, the device demonstrates dual-mode operation (photoelectric synaptic
and photodetection) across a broad spectrumN from ultraviolet to near-infrared. Under the
photoelectric synaptic mode (low voltage), defect levels in the MoOₓ/MoS₂ channel are activated,
enabling charge trapping/detrapping beEhavior. Combined with polarization modulation from
In₂Se₃, the device achieves over 128 (7-bit) continuous conductance states, operates at a voltage
as low as 1 mV, and consumes only 0.03 fJ per electrical synaptic event and 0.37 fJ per optical
synaptic event. In photodetecTtion mode (0 V bias), benefiting from the interfacial control via In₂Se₃
polarization, the dark current is suppressed to sub-fA levels, while the responsivity reaches 89.3
mA/W at 375 nm and the specific detectivity attains 1.4×10¹¹ Jones at 373 nm. Finally, we
successfully demonstrate that the device achieves high-precision image recognition based on
parallel computing of five reconfigurable logic gates coupled with optoelectronic synapses,
emulates classical Pavlovian associative learning, and enables single-pixel dual-band (visible to
near-infrared) optical imaging. In summary, this work not only presents a multifunctional
integrated device with simple structure, rich functionality, and ultralow power consumption, but
also offers a design strategy leveraging intrinsic properties of 2D ferroelectric materials for in-
sensor computing.

Results
Device characterization and analysis

Fig. 1a shows the schematic diagram of the device structure. During fabrication, graphene
and MoS₂ are sequentially stacked on a SiO₂/Si substrate via mechanical transfer, followed by
annealing the heterostructure at 300 ℃ for 2 hours to introduce controlled defects into MoS₂ for
stabilizing its memristive characteristics. After annealing, the In₂Se₃ layer is transferred onto the
graphene/MoS₂ stack. Finally, Cr/Au (5/20 nm) electrodes are fabricated on graphene and In₂Se₃
via thermal evaporation. AFM measurements (Figs. 1b-1c) reveal thicknesses of approximately 16
nm for graphene, 27 nm for MoS₂, and 46 nm for In₂Se₃. The cross-sectional STEM image (Fig.
1d) clearly demonstrates the layered structure of the device. The interfacial elemental distribution
is further confirmed by EDS mapping (Fig. 1e). Raman spectroscopy (Fig. 1f) shows characteristic
peaks of MoS₂ at 386 and 404 cm⁻¹, corresponding to the E₂g and A₁g modes, respectively; peaks
at 108, 178, and 207 cm⁻¹ are assigned to the A₁(LO+TO), A₁(TO), and A₁(LO) vibrational modes
of α-In₂Se₃, consistent with previous reports47. The XPS spectra in Supplementary Fig. 1 confirm
the presence of a MoOₓ phase in MoS₂ after annealing, where the unsaturated bonds between MoOₓ
and MoS₂ facilitate the formation of interfacial sulfur vacancies 48. Fig. 1g presents the PFM phase
hysteresis loop and amplitude butterfly loop of α-In₂Se₃, indicating that nanosheets with a
thickness close to 46 nm exhibit coercive fields of approximately –2 V and +1.5 V. Moreover, the
spontaneous ferroelectric domains (Supplementary Fig. 2) also confirm the strong ferroelectricity
of In₂Se₃. Fig. 1h,i show the band structure projections of MoS₂/In₂Se₃ and MoS₂/MoOₓ/In₂Se₃ van
der Waals heterostructures under downward-oriented poRlarization (P
down
), calculated based on first
principles. Supplementary Fig. 3 presents the Pband structure projections of the same
heterostructures under upward-oriented polarization (P ). The figures reveal a type-II band
up
alignment in MoS₂/In₂Se₃, and highlight the strong influence of defect-induced impurity levels in
the treated MoS₂ on the band structure.

Evaluation of electrical performance

Memristive properties play a pivotal role in realizing synaptic functions in devices. Figs. 2a,b
exhibit the hysteresis loops of the device under voltage sweeps from 0 to +1 V and 0 to -1 V,
respectively. The stable memory window confirms robust memristive behavior after high-
temperature annealing, whereas the unannealed device (Supplementary Fig. 4) shows a negligible
hysteresis window. The intrinsic mechanism is further elucidated in Supplementary Fig. 5-7. Fig.
2c demonstrates that the device maintains high/low resistance states (HRS/LRS) for over 5000
seconds under +3/-3 V pulse modulation. Supplementary Fig. 8 reveals that the device remains
stable after 3000 consecutive resistance switching cycles. As shown in Fig. 2d, under continuous
stimulation with +1.5 V and -1.5 V pulses, the device successfully emulates the excitation and
inhibition functions of biological synapses. Paired-pulse facilitation (PPF), a key mechanism for
brain information processing and temporal filtering, can be calculated using the formula PPF = (I -
2
I )/I , while the exponential decay trend of the PPF index can be determined by the following
1 2
equation53:
PPF index = 𝐶 +𝐶 e-Δt/τ1 +𝐶 e-Δt/τ2 (1)
0 1 2
Where C₀, C₁(C₂), and Δt represent the initial facilitation amplitude, facilitation constants,
and pulse interval, respectively. τ₁(τ₂) denotes the characteristic relaxation time for fast (slow)
decay. The results in Fig. 2d show that the PPF index decays rapidly with increasing time interval
and eventually stabilizes, indicating that the memory effect weakens as the time between two
pulses increases. Fig. 2e shows that as the intensity of the electrical pulses increases, the
conductance retention level of the device improves, demonstrating its excellent plasticity under
varying electrical pulse intensities. Similarly, Fig. 2f aPlso reveals the device's synaptic plasticity in
response to different electrical pulse widths. The e nergy efficiency of the device is crucial for its
application in low-power neuromorphic computing. Fig. 2g specifically evaluates the minimum
energy consumption of the device at a w orking voltage of 1 mV. The energy consumption
calculation formula is38:
𝐸 = 𝑉 ×𝐼 ×𝑡 (2)
DS DS spike
Here, 𝐼 and 𝑡 represent the amplitude of the excitatory postsynaptic current (ΔEPSC)
DS sApike
and the pulse width, respectively, while 𝑉 denotes the operating voltage of the device. As a
DS
result, the energy consumption is as low as 0.03 fJ, which aligns well with the energy range of
biological synapses (1–10 fJ). As shown in Fig. 2h, the energy efficiency of this device remains
highly competitive even when compared with recently reported works.

Emulation of five Boolean logic gates

As illustrated in Fig. 3b, the device can be nonvolatilely switched to positive/negative
conductance states upon the application of electrical pulses with different polarities (+3 V and −3
V). This behavior originates from the ferroelectric polarization switching characteristics of the
In₂Se₃ layer (detailed mechanism analysis is shown in Supplementary Fig. 5): positive and negative
pulses induce two stable polarization states, Pₒᵤₜ and Pᵢₙ, respectively. These two polarization states
modulate the interfacial band alignment of the In₂Se₃–MoS₂ heterojunction, ultimately enabling
the device to exhibit distinct positive and negative electrical responses (the bipolar plasticity
modulation of the device is demonstrated in Supplementary Fig. 9). Based on this characteristic,
we dynamically implement five Boolean logic operations (AND, OR, NAND, NOR, NOT) on a
single device.
In the left region Fig. 3a, for inputs A and B, “0” and “1” represent the off and on states of +3
V pulses, respectively. The output Y is defined by the instantaneous polarity: "0" represents a
negative current, while "1" corresponds to a positive current. Supplementary Fig. 10 demonstrates
the consistent logic current output of the device over 5000 cycling tests. Supplementary Fig. 11
further presents the signal-to-noise ratio (SNR) evaluation to assess the stability of the logic output.
In this configuration, a read voltage V = −0.01 V or −0.02 V is applied, introducing a negative
read
conductance effect (corresponding to logic “0”) that competes with the positive current response
(logic “1”) induced by positive pulses. Taking the OR gate as an example (Fig. 3c), as long as one
input is “1” (e.g., in the “10” or “01” states), the positive conductance response dominates,
resulting in an output of “1”. In the AND gate configuration (Fig. 3d), V = −0.02 V is used to
read
enhance the negative conductance effect. In this case, a single input of “1” (“10” or “01”) is
insufficient to reverse the current polarity; only when both inputs are “1” (“11”) can the positive
conductance response overcome the competition, yielding an output of “1”.Correspondingly, the
right region in Fig. 3a illustrates the negative pulse inpRut mode: for inputs A and B, “0” and “1”
represent the absence or presence of a −3 V pulse, rPespectively. The output Y still distinguishes
logic states based on current polarity. In this mode, V = 0.01 V or 0.02 V provides a positive
Nread
conductance effect, competing with the negative polarity response induced by negative pulses. By
appropriately configuring this competing relationship, the device successfully realizes the NOT,
NOR, and NAND functions, as showLn in Figs. 3e–g. Supplementary Fig. 12 demonstrates the
consistency in logic output acrossC different devices. Moreover, as shown in Supplementary Fig.
13 and 14, the device exhibits stable outputs for all five logic functions across a wide temperature
range (10–300 K) and undRer different bias voltages, demonstrating its high operational stability in
varied environments.

Optical performance evaluation of the device

Under laser excitation, the device exhibits switchable dual-mode optoelectronic
characteristics, enabling dynamic transition between photodetection and synaptic functionalities.
Fig. 4a illustrates the operational mode schematic. As shown in Fig. 4b, at zero bias (0 V), the
device demonstrates broad-spectrum photoresponse from ultraviolet to near-infrared, operating in
photodetection mode. When a bias of 0.1 V is applied, defect energy levels in the MoS₂ layer are
activated, leading to persistent photoconductance and enabling wide-spectrum optoelectronic
synaptic behavior. This mode-switching capability arises from the synergistic effect between
ferroelectric polarization modulation in the In₂Se₃ layer and activation of deep defect levels in
MoS₂, with detailed mechanisms provided in Supplementary Fig. 5. Fig. 4c shows the I-V
characteristics of the device under 670 nm laser illumination as a function of optical power density.
Supplementary Fig. 15 further shows the I–V responses under fixed optical power but different
excitation wavelengths. Owing to the polarization modulation of the In₂Se₃ layer, the dark current
is effectively suppressed to approximately 10 fA, significantly outperforming the pristine MoS₂
device without an In₂Se₃ interlayer (Supplementary Fig. 16). Supplementary Fig. 17 shows the
power-dependent photoelectric response characteristics of the device under different laser
excitations. Fig. 4d displays the responsivity (R) and specific detectivity (D*) as functions of
optical power under different laser excitations, calculated using the following equations54:
𝑅 = 𝐼ph / 𝑃in
𝐷∗ = 𝐴^1/2𝑅 / (2𝑞𝐼d)^1/2
Here, 𝐼 refers to the photocurrent (𝐼 = I – I ), and 𝑃 denotes the incident optical
ph ph dark in
power. In Equation 4, A is the illuminated d evice area, and 𝐼 is the dark current. Under 375 nm
d
laser excitation, the device achieves a maximum responsivity of 89.3 mA/W and a specific
detectivity of 1.4×1011 Jones. In thCe optoelectronic synaptic mode, the device exhibits frequency-
dependent plasticity: as the pulse frequency increases, the conductivity response transitions from
short-term potentiation (STP) to long-term potentiation (LTP) (Fig. 4e). Similar synaptic behaviors
can also be modulatAed by varying the number, intensity, and duration of optical pulses
(Supplementary Fig. 18).
As shown in the paired-pulse facilitation (PPF) index fitting curve in Fig. 4f (calculated using
Equation 1), the PPF index decays rapidly with increasing pulse interval and gradually stabilizes,
demonstrating temporal dynamics highly similar to those of biological synapses. The device also
successfully emulates the "learning-forgetting-relearning" behavior observed in brain-like learning
(Supplementary Fig. 19). Under optical stimulation at 670 nm (P = 90 μW/cm2), the device exhibits
more than 128 (7-bit) continuously tunable conductance states (Fig. 4g), a feature of significant
value for neuromorphic computing applications. Furthermore, we calculate the noise for the six
conductance states using formula (5):
𝜎 = √ 1 ∑𝑛 (𝐼 −𝐼)̅ 2 (5)
𝑛−1 𝑖=1 𝑖
where σ is the noise, n is the number of measurements, and I ̅ is the average current. The
calculated values are: σ
10
=32 pA, σ
40
=35 pA, σ
60
=30 pA, σ
80
=37 pA, σ
100
=31 pA, σ
128
=34 pA. The
current differences between adjacent conductance states are about 0.1-0.15 nA, which is
significantly larger than twice the maximum noise (2σ =74 pA), confirming clear
max
distinguishability between different states. Supplementary Fig. 20 demonstrates the current
retention duration of the device across six conductance states over 3000 s. Supplementary Fig. 21
shows the conductance retention of approximately 10000 s under 128 optical pulse stimulations.
These results highlight the excellent and stable conductance retention characteristics of the device.
Supplementary Fig. 22 indicates that the synaptic weight (Aₙ/A₁ ratio) continues to increase with
the number of optical pulses, reaching 4.26 at the 25th pulse. This demonstrates the potential for
achieving high contrast in neuromorphic imaging and preprocessing applications. Finally, we
evaluate the energy consumption of the device in the optoelectronic synaptic mode using Equation
2, with the lowest energy consumption per synaptic event being 0.37 fJ (as shown in Fig. 4h).
Supplementary Fig. 23 compares the optical synaptic Renergy consumption of our device with
recent works. Supplementary Fig. 24 and 25 statisticPally illustrate the consistency of low-power
performance among different devices, and that of photodetection and optoelectronic synaptic
performance, respectively. Based on the excellent photoresponse and optoelectronic synaptic
plasticity of the device, we successfully emulate classical Pavlovian conditioning and single-pixel
dual-band optical imaging (SupplemeLntary Fig. 26).

High-precision image recognition

We construct and validate an image recognition system based on the Gra/MoS₂/MoO /In₂Se₃
x
heterojunction device. This system innovatively integrates the analog sensing capability of
photoelectric synapses with the reconfigurable digital processing functions of five Boolean logic
gates (OR, AND, NOT, NAND, NOR), enabling efficient hybrid computing. As illustrated in Fig.
5a, the system workflow is as follows: After the raw image is input, the photoelectric synaptic
layer first processes the optical signal in the analog domain, preliminarily extracting basic image
features such as contours and textures. These features are then fed in parallel into five
reconfigurable logic gate branches for specific and differentiated feature enhancement.
Specifically, the OR gate employs depthwise separable convolution to expand the receptive field,
focusing on extracting the overall contour and spatial structure of the target. The AND gate
enhances and focuses on key details and local features in the image through refined convolution
operations. The NOT gate utilizes a channel attention mechanism to achieve feature inversion and
recalibration, effectively suppressing background interference and improving foreground contrast.
The NAND gate uses dilated convolution to enlarge the rReceptive field while employing smoothing
operations to suppress noise, achieving robust featuPre representation. The NOR gate introduces
spatial attention weights to strengthen the response in the core target area, enabling adaptive focus
on the main subject. The differentiated features output by each logic gate are adaptively weighted
and integrated by an intelligent feature fusion module, ultimately forming a unified feature
representation with stronger discrimiLnative power, which is then fed into a classifier to achieve
high-accuracy and high-robustneCss image recognition. Fig. 5b visually compares the feature
extraction characteristics of the photoelectric synaptic layer and the five logic layers, using an
input cat image as an exRample. Fig. 5c further presents the hybrid feature response heatmap
generated from the outAputs of the photoelectric synaptic layer and the logic layers, demonstrating
the enhanced effect after feature fusion. Fig. 5d shows a comparison of the training recognition
accuracy curves between the single photoelectric synaptic layer and the photoelectric
synaptic/logic hybrid layer on the CIFAR-10 dataset. After 100 training epochs, the hybrid layer
achieves an accuracy of 97.28%, significantly higher than the 91.56% accuracy of the single
photoelectric synaptic layer, highlighting the performance advantage brought by the synergistic
processing of logic gates. Fig. 5e, f display the confusion matrix and accuracy distribution,
respectively, for the photoelectric synaptic/logic hybrid layer in recognizing ten types of objects
(such as airplanes, cars, cats, etc.). The average recognition accuracy remains stable at around 97%,
further verifying the system’s high accuracy and strong generalization capability in multi-category
recognition tasks.

Methods
Theoretical calculation. First-principles calculations are performed using the Vienna Ab initio
Simulation Package (VASP) based on density functional theory (DFT). The ion-electron
interactions are treated using the projector augmented wave (PAW) method. The exchange-
correlation potential is described by the generalized gradient approximation (GGA) in the scheme
of Perdew–Burke–Ernzerhof (PBE). The plane-wave energy cutoff is set to 400 eV. The geometry
optimization is allowed to proceed until the residual forces on the atoms are less than 0.05 eV/Å,
and the energy convergence criterion for the self-consistent loop is set to 10−6 eV. The Brillouin
zone integration is sampled using a Γ-centered k-point mesh with a grid density consistent with a
resolution of 0.05 Å⁻¹. The MoS₂/MoOₓ/In₂Se₃ heterostructures are modeled by stacking the
corresponding layers along the z-direction. To investigate the ferroelectric modulation mechanism,
the polarization states of α-In₂Se₃ (Pup and Pdown) are simulated by adjusting the atomic stacking
sequence. The projected band structures are calculated to identify the orbital contributions of each
layer, and the plane-averaged electrostatic potentials are computed to evaluate the band alignment
and the built-in electric field distribution across the interface.

Device fabrication. During device fabrication, 2D nanosheets are first mechanically exfoliated
from bulk crystals of graphene, MoS₂, and In₂Se₃ using polydimethylsiloxane (PDMS). The
graphene and MoS₂ nanosheets are then sequentially dry-transferred onto a 300 nm SiO₂/Si
substrate. The resulting graphene/MoS₂ heterostructure is annealed at 300 °C for 2 hours. After
cooling to room temperature, an In₂Se₃ nanosheet is transferred onto the heterostructure. To
enhance the interlayer adhesion and improve the optoelectronic performance, the entire device is
heated at 100 °C for 5 minutes. Finally, electrode patterns are defined over the heterojunction
region using a maskless UV lithography system, followed by the deposition of a 5 nm/25 nm metal
layer via thermal evaporation. The photoresist is lifted off in acetone to obtain the final device.

Sample characterization and optoelectronic measurements. TShe physicochemical properties
and morphology of the devices are characterized using X-rayS photoelectron spectroscopy (XPS,
Thermo Scientific Kα+ system) and atomic force miEcroscopy (AFM, Bruker Icon). All
optoelectronic measurements and synaptic behavior emulation are performed on a probe station
equipped with a semiconductor parameter analyzer (Keithley B1500A), using the
In₂Se₃/MoOₓ/MoS₂/Gra heterostructure devicesN. For synaptic performance testing, the devices are
optically excited by laser sources spanning 375–808 nm, with laser frequency and pulse width
modulated by a signal generator. Laser inEtensity is monitored in real time using a power meter.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "Zhi et al presented an asymmetric van der Waals heterostructure, In2Se3/MoOx/MoS2/Graphene, demonstrating multifunctional electrical operations, including Boolean logic-in-memory, broad-spectrum photoelectric synaptic plasticity, and photodetection. The device emulates classical Pavlovian conditioning and supports single-pixel dual-band optical imaging. However, although this progress is important, the underlying material platform (In2Se3 and MoS2 ) iand the general concept of van der Waals heterostructures for neuromorphic computing are well-established. Given the lack of significant material or architecture innovation and the preliminary nature of key demonstrations, the reviewer cannot recommend this for publication in a such high impact journal. Some comments are noted as follows.\n1.The ferroelectric polarization of α-In2Se3 is critical for achieving device functionality. The authors should provide additional details on the in-situ testing of ferroelectric properties of the α-InSe film. Additionally, there appears to be a serious mismatch between the figure labels and the descriptive text/captions in Fig. 1. Carefully review and revise Fig.1 and its caption to ensure a precise, one-to-one correspondence between the panels.\n2.The author mentions that the device exhibits different states before and after annealing. What is the precise mechanism responsible for the state difference before and after annealing? This requires direct, supporting evidence (e.g., XPS spectra comparing the interface before and after annealing, or TEM cross-sections). While the presence of MoOx in annealed MoS2 is noted (Fig. 1g), the authors fail to elaborate on its functional role. Given that MoOx can modify the work function, the authors must discuss how this oxidized layer tunes the band alignment at the InSe/MoS2 interface and consequently regulates device performance (e.g., affects charge transfer or the internal electric field).\n3.Reliability data is mandatory for the memory device claim. Please supplement the endurance and retention data of the van der Waals heterostructure. The statement regarding the \"working voltage of 1 mV\" is confusing and likely refers only to the read operation.\n4.Figure 1g shows an α-In2Se3 coercive voltage of approximately 5 V. However, the subsequent memory testing (Fig. 2) is performed using biases significantly lower than 5 V. Since the applied voltage is insufficient to reverse the ferroelectric polarization as determined by the authors' own data, the observed memory window in Fig. 2 cannot be solely due to ferroelectric polarization reversal.\n5.The claim of exhibiting \"more than 128 (7-bit) continuously tunable conductance states\" (Fig. 4g) is excellent, but requires more rigorous support. The authors must explicitly demonstrate the reliability and separation of these 128+ states. This typically involves plotting the distribution of the states to confirm that the noise margin is sufficient to prevent state overlap.\n6.The simultaneous demonstration of Boolean logic and analog synapse functionality in a single device is a valuable finding that should be leveraged into a compelling application scenario. The authors should propose a distinctive hybrid application that specifically utilizes the co-existence of both features.\n7.The figures must be revised to meet publication quality standards. The \"pA\" values in Fig.3b are completely illegible. These must be increased in font size and contrast to clearly display the data range. Ensure consistent font style and size across all panels.", "reviewer_2": "In this manuscript, the authors report a multi-functional device based on 2D heterostructure, which integrate electrical logic-in memory operations, broad-spectrum optoelectronic synaptic and photodetection capabilities into one device. Five classic Boolean operations have been demonstrated. Photoelectric synaptic and photodetections under broad spectrum illumination can be realized with ultralow power consumption and high responsivity/detectivity, respectively. Moreover, Pavlov classic experiment and dual-band optical imaging have been demonstrated. The topic is really hot all around the world and advances rapidly. I personally recommend to accept this manuscript to be published in NC.\nHowever, there are some issues that should be addressed before acception.\n1. Line 97-99, The caption of Figure 1 does not match the panels of Fig.1. Obviously, there are 9 panels in Fig. 1 (a-i), but there are only 6 descriptions (a-f) in the caption. Moreover, the descriptions of the caption are not accord with the pictures.\n2. Figrue 4g and line 237, The authors claim that the device exhibits more than 128 (7-bit) tunable conductance states. It should be specified that how to define a conductance state, like what the separation of neighboring states is and how it is reasonable.\n3. In the manuscript, the authors just show measurement results from one device. I would like to know how many devices that the authors have prepared and measured. And How the variation is between different devices. It is very important that the results should be reproducible in different devices. And this should be clearly stated in the manuscript.\n4. The thickness of electrodes is 5 nm/25 nm. However, the thicknesses of 2D materials are 46 nm (In2Se3), 27 nm (MoS2), and 15 nm (Gra). How to confirm the good electric contact with so big thickness difference?", "reviewer_3": "This manuscript reports an asymmetric van der Waals heterostructure (In₂Se₃/MoOₓ/MoS₂/Graphene) that integrates multiple functionalities including reconfigurable logic, ultralow-power synaptic behavior, and high-sensitivity photodetection. The key operating principle lies in the active modulation of interfacial band alignment and carrier transport through the ferroelectric polarization of α-In₂Se₃. The novelty of this work is that all three functions—(1) reconfigurable logic, (2) ultralow-power synapse, and (3) broadband photodetection—are demonstrated within a single two-terminal device. While most prior studies on 2D materials have focused on only one of these functionalities, this work achieves their coexistence and interaction within a unified heterostructure, thereby advancing toward the ultimate goal of in-sensor computing and logic-in-memory architectures. The dual-mechanism operation—combining nonvolatile ferroelectric polarization switching in In₂Se₃ with defect-assisted charge trapping/detrapping in MoS₂ introduced by thermal treatment at 300 °C—represents a distinctive and synergistic device design strategy. The results are experimentally elegant and technically intriguing. However, several aspects require further clarification and strengthening:\n1. The central operation relies on the synergy between the ferroelectric polarization of In₂Se₃ and the defect states in MoS₂, but the manuscript lacks a quantitative analysis of how these two factors interact. Specifically, it remains unclear how the polarization direction modifies the trapping/detrapping efficiency or the capture cross-section of defect states at the MoOₓ/MoS₂ interface. A more detailed physical discussion supported by band diagram simulations, temperature-dependent measurements, or capacitance-based analyses would substantially enhance the scientific rigor of the paper.\n2. All devices are fabricated by mechanical exfoliation, which, although effective for proof-of-concept studies, inherently suffers from device-to-device variation and scalability limitations. To strengthen the validity of the conclusions, statistical data from at least 5–10 devices should be presented for key parameters such as synaptic energy consumption, logic current contrast, and dark current. Furthermore, a brief discussion on the feasibility of wafer-scale or CVD-based fabrication would provide valuable perspective for potential practical implementation.\n3. For neuromorphic and memory-oriented devices, endurance (number of polarization or weight-update cycles) and data retention are crucial performance metrics. The manuscript should include endurance tests for both ferroelectric switching and synaptic weight updates, as well as retention measurements showing how long the programmed conductance states can be maintained under ambient conditions.\n4. As shown in Fig. 3, the Boolean logic operations depend on current polarity differences at the picoampere level. Such small current windows may be easily affected by noise, temperature fluctuation, or readout uncertainty. The authors should evaluate the signal-to-noise ratio (SNR) of the readout current and verify logic stability under varying bias and temperature conditions. Demonstrating consistent logic output across a range of operating environments would greatly strengthen the practical significance of the results."}, "author_response": "Manuscript ID: NCOMMS-25-74831A\nTitle: Ferroelectricity-Modulated asymmetric van der Waals heterostructure for Ultralow-Power Neuromorphic Synapse and logic-in-memory Operations\nWe thank the reviewers for their positive recommendation and valuable comments.\nYour insights have strengthened our manuscript, which we have revised accordingly.\nBelow are our point-by-point responses to each comment.\nResponse to Reviewer #1: [Full text of response to Reviewer 1 omitted for brevity, but included in full in the source document]\nResponse to Reviewer #2: [Full text of response to Reviewer 2 omitted for brevity, but included in full in the source document]\nResponse to Reviewer #3: [Full text of response to Reviewer 3 omitted for brevity, but included in full in the source document]"}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors addressed all concerns raised by the reviewers, and the answer and discussion were comprehensive to support the conclusions. The manuscript has been drastically improved after this revision. The reviewer recommends this for publication in Nature Communications without further revision.", "reviewer_2": "The authors have carefully addressed the issues that raised by reviewers. The manuscript has been improved and now is appropraite for publication in NC.", "reviewer_3": "Thank you for submitting the revised version of your manuscript and the detailed response letter.\nI carefully reviewed your point-by-point responses and the corresponding changes made in the manuscript. The revisions adequately address the concerns raised in my previous review. In particular, the additional data and expanded explanations/discussion have clarified the key issues that previously caused uncertainty, and the updated manuscript now provides sufficient support to interpret the results with confidence.\nIn my view, the revisions have effectively resolved the major concerns, and I am satisfied with the updated version."}, "author_response": ""}]

Decision letter