Brain-inspired synaptic transistors for in-situ spiking reinforcement learning with eligibility trace

Domain: chemistry
Published: 2026-02-21
Editorial outcome: major_revision

Abstract
Brain-inspired reinforcement learning is pivotal for artificial general intelligence, yet current artificial neural network-based hardware lacks critical biological mechanisms like third-terminal modulated eligibility traces and dynamic reward signaling. Emerging materials address these challenges by efficiently mimicking complex reinforcement learning dynamics. Here, we demonstrate a brain-inspired spiking neural network-based reinforcement learning computing architecture using α-In2Se3 ferroelectric semiconductor field-effect transistor. By leveraging the intrinsic in-plane and out-of-plane polarization coupling of α-In2Se3, the multi-terminal conductance modulation in the device enables reward signal modulation of reinforcement learning. The ferroelectric relaxation is utilized to implement biological eligibility trace decay, thereby enhancing the algorithm’s processing capability. autonomous driving tasks are then demonstrated with an RL neural network constructed by the α-In2Se3 transistor array, wherein in-situ reward-based weight updates and eligibility trace decay are performed without any external memory or computing units. Our solution enables a fully functional, energy-efficient, and low-overhead spiking-based reinforcement learning architecture.

Introduction
Reinforcement learning (RL) originates from brain models in the study of biological neural systems1–5, which has the potential for achieving artificial general intelligence6–11. Researchers have demonstrated hardware implementations of RL based on emerging nonvolatile memory technologies (NVMs)12–14. However, these artificial neural networks (ANNs) based RL implementations only implement a single aspect of RL functionality (such as weight updates15, feedback reward modulation13, or eligibility traces14,16) rather than the complete set, with the remaining functionalities requiring additional analog circuit computations. Therefore, novel approaches are needed to achieve complete RL functionality based on NVM, enabling efficient computation.

In contrast, brain-like spiking neural networks (SNNs) offer advantages in power consumption, processing speed, and sparse computation17–19, addressing the challenges faced by hardware acceleration for RL. Reward-modulated spike-timing-dependent plasticity (R-STDP) is a brain-inspired RL algorithm designed for SNN20, integrating dopamine modulation and eligibility trace mechanisms from biological systems (Fig. 1a–1c)3,4. Compared to conventional STDP, feedback signals in R-STDP enhance its adaptive optimization, improving performance in learning task3,20. Therefore, biologically inspired SNN-based RL holds promise for more efficient hardware implementation.

However, SNN-based RL algorithms like R-STDP usually require three hardware terminals to process reward signals (Fig. 1c)15,21, two terminals serve as the pre-synaptic and post-synaptic ports, while the third terminal is used for reward modulation, which exceeds the capabilities of most two-terminal NVM devices. Additionally, the eligibility trace (ET) in RL ensures appropriate future weight updates by decaying over time, thereby helping to achieve the optimal policy3,4,20. Implementing ET’s exponential decay using conventional complementary metal-oxide-semiconductor (CMOS) technology requires analog circuits with dozens of components22–24. NVM-based solutions like phase change memory (PCM) conductance drift need multiple parallel PCMs and additional synaptic weight units (Fig. 1b)14,16. Therefore, more efficient device implementations for SNN-based RL are urgently called for.

In this work, we demonstrate a hardware implementation of SNN-based RL algorithm with α-In2Se3 ferroelectric semiconductor field-effect transistor (FeS-FET). We utilize the intrinsic physical mechanisms of the device to emulate brain-like complex analog computations, without requiring additional computational units. The brain-inspired R-STDP algorithm is mapped onto the FeS-FET for in-situ weight updates in three steps: (1) STDP Process. Pre- and post-signals are applied through the source and drain, forming VDS pulses that modulate conductance by in-plane (IP) polarization; (2) Eligibility trace decay. Conductance decays exponentially due to ferroelectric relaxation caused by depolarization field, mapping to the ET decay in the algorithm; (3) Reward modulation. During relaxation, feedback reward signals applied through the gates act as VGS pulses that further modulate conductance by out-of-plane (OOP) polarization. Our approach achieves this three-step computation in a single device, mimicking the three-terminal synaptic behavior modulated by dopamine in biological systems. This work provides the complete hardware solution for in-situ weight updates of SNN-based RL, paving the way for hardware acceleration in RL.

Results
Brain-inspired synapse for spiking reinforcement learning
Figure 1a shows a comparison of the Hebbian rule (STDP) and R-STDP in the brain’s neural system. Unlike STDP, which learns from the timing of spikes alone, R-STDP adds feedback signals, aligning with RL principles. Compared to conventional STDP, the presence of positive and negative feedback signals enables R-STDP to possess adaptive optimization capabilities characteristic of RL, thereby achieving superior performance in learning tasks. Figure 1b illustrates the hardware efficiency advantages of α-In2Se3 FeS-FET in implementing R-STDP. Figure 1c illustrates the detailed dynamic evolution of R-STDP synapses in biological systems. Pre- and post-neurons initially generate a standard STDP effect through spike timing, but the synaptic weight does not change immediately; instead, the magnitude of the weight change is stored as an eligibility trace. The eligibility trace then decays exponentially over time, representing the strength of the learning effect. Finally, the reward signal from the third modulatory neuron is feedback, resulting in the final weight update based on the remaining magnitude of the eligibility trace. The reward signal is determined by the outcome caused by the preceding STDP event, which can be either positive or negative (Fig. 1a). The shorter the delay of the reward signal, the less the eligibility trace decays, leading to a greater amount of weight adjustment. This mechanism aligns with the principle of causality: the shorter the delay, the stronger the relationship between the event and the outcome, thereby justifying a more significant impact on weight updates3,4,20.

Figure 1d illustrates the mechanism of implementing the R-STDP synaptic dynamics with the α-In2Se3 FeS-FET. By utilizing the unique IP (for STDP and ET) and OOP (for reward signal) ferroelectric polarization coupling characteristics of α-In2Se3, the STDP and reward parts of the algorithm can be achieved by modulating IP and OOP polarization, respectively. Furthermore, the algorithm’s eligibility trace decay function is mapped to the ferroelectric polarization relaxation effect caused by the depolarization field. This approach enables in-situ spiking RL weight updates within a single transistor. Compared to existing hardware implementations, this design is simpler and achieves the complete algorithmic process computation within a single device.

Multi-terminal programmable α-In2Se3 synapses
The two-dimensional (2D) ferroelectric semiconductor α-In2Se3, with IP and OOP polarization coupling25–33, enables complex analog calculations34–40. Due to the coexistence of ferroelectric and resistive switching properties, α-In2Se3 exhibits distinct advantages and unique application scenarios compared to traditional ferroelectric and resistive switching materials (Supplementary Table 3 and 4). Furthermore, the trade-off between its ferroelectric and resistive characteristics further expands its application prospects (Supplementary Note 3). Compared to other non-volatile memory devices (e.g., FeFET and charge-trapping memories), the three-terminal modulation capability of the FeS-FET provides an additional independent control terminal. This feature can be utilized to emulate more complex biological synaptic characteristics, such as the dopamine-synapse-based R-STDP characteristics demonstrated in this work. Due to the simultaneous semiconductor and ferroelectric properties of α-In2Se3, FeS-FET using α-In2Se3 as the channel material does not require a ferroelectric gate dielectric, resulting in a simpler fabrication structure32. Figure 2a shows the cross-sectional schematic device structure of the FeS-FET. The detailed device fabrication process is described in the Methods section. Supplementary Fig. 1 illustrates the Raman spectrum of α-In2Se3 flake on a SiO2 substrate. The piezoresponse force microscopy (PFM) measurement of α-In2Se3 (Supplementary Fig. 2) demonstrates the intrinsic coupling of IP and OOP polarization.

By applying vertical and horizontal electric fields to control the IP and OOP polarization, respectively, the IDS scanning curve exhibits a significant hysteresis window (Fig. 2b and 2c), demonstrating the capability for non-volatile conductance modulation. Figure 2c shows the clockwise hysteresis consistent with the high effective oxide thickness (EOT, the EOT of 30 nm Al2O3 is 13 nm) condition of the gate dielectric thickness32. To rule out the possibility of clockwise hysteresis caused by charge trapping41,42, Supplementary Fig. 3 presents measurements down to 60 K. The minimal change in the hysteresis window suggests that ferroelectric polarization is the dominant factor. High-temperature characterization (Supplementary Fig. 3) also confirms the device’s capability to operate in elevated temperature environments. As for the resistive switching in Fig. 2b, it is attributed to the changes in the OOP polarization coupled with the IP polarization, which alters the band bending between the α-In2Se3 channel and the Au-α-In2Se3 interface36,43 (Supplementary Fig. 4).

The polarization modulation schematics for IP (Fig. 2d–2f) and OOP (Fig. 2g–2i) are shown in Fig. 2. These two modulation methods correspond to STDP and reward signals in biological systems, respectively. Figure 2e and 2h present the analog modulation of channel conductance under VDS and VGS pulses, respectively. The large hysteresis window under VGS (±5 V, ON/OFF ratio > 105) contributes to excellent conductance modulation range (Gmax/Gmin > 25) and multiple conductance states (>32). The VDS pulses can also produce analog modulation on channel conductance (Gmax/Gmin > 6, >32 states). The results of 500 cycling measurement and the analog modulation under different pulse widths/amplitudes are shown in Supplementary Fig. 5 and Supplementary Fig. 6, demonstrating excellent cycling consistency. Because the thickness (~40 nm) of α-In2Se3 is much smaller than the channel length (1 µm), the displacement field of VGS (5 V under 30 nm gate insulator is 170 V µm−1) is much higher than that of VDS (7 V under 1 µm channel length is 7 V µm−1), which leads to stronger modulation of VGS. This characteristic aligns well with the requirements of the R-STDP algorithm in biological systems, where STDP signal (VDS) modulation is weaker than reward signal (VGS) modulation3,4. This compatibility facilitates our subsequent application of FeS-FET for R-STDP synapses.

The excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) under two consecutive VDS pulses (±9 V, 20 ms. The read voltage is 0.1 V) is shown in Fig. 2f. The application of a positive VDS pulse is equivalent to an increase in the read voltage, and together with the change in ferroelectric polarization, results in a rapid increase in current. Polarization relaxation causes the current to partially decrease after the pulse is removed, while residual polarization results in a non-volatile increase of conductance. The situation is similar in the case of a negative pulse.

Figure 2i shows the current response under two consecutive VGS pulses (7 V, 15 ms. The read voltage is 0.1 V). Upon application of a positive voltage pulse, the current increases sharply due to the attraction of electrons into the channel. After the pulse is removed, the current decreases rapidly as ferroelectric polarization dominates. Simultaneously, the presence of the depolarization field causes partial polarization relaxation44, leading to a reduction in residual polarization and a subsequent increase in current. The positive VGS pulses result in IPSC, and the negative VGS pulses result in EPSC. The current relaxation caused by polarization relaxation in α-In2Se3 FeS-FET is consistent with the eligibility trace decay in RL algorithms, thereby providing an efficient hardware implementation scheme that does not require additional circuitry. Supplementary Fig. 7 illustrates the conductance retention under VGS pulses.

In addition, Supplementary Fig. 8 shows the standard STDP function via VDS pulses and the pulse scheme used for STDP measurement. Unlike existing research, where waveforms are pre-computed and then input to the transistor gate to achieve STDP15,31,35, this approach naturally realizes STDP by using the source and drain as the pre- and post-synaptic terminals, respectively, allowing STDP to occur through the superposition of pre- and post-neuron pulses. The diverse synaptic behaviors of α-In2Se3 FeS-FET illustrate its applicability as an artificial synapse in spiking-based reinforcement learning.

Reward-modulated synapses with eligibility trace
In biological R-STDP systems, reward signal (dopamine) and eligibility traces play a critical role3,4. Figure 3a shows that the eligibility trace captures the strength of the STDP effect and decays exponentially over time. When a reward signal arrives, the weight update is based on the remaining trace. This process aligns with the Markov chain in reinforcement learning45, where past and future events together influence weight updates. In R-STDP, the earlier the reward, the stronger the link between the STDP event and the reward, leading to a larger weight adjustment due to less decay in the eligibility trace (Fig. 3a). The simplified R-STDP rule is as follows3: Δw = STDP(t) ∙ E(t) ∙ R(t), Δw is the weight change, E(t) and R(t) represent the eligibility trace and reward signal, respectively (Fig. 3a). The schematic diagram of using α-In2Se3 FeS-FET to implement R-STDP in-situ update is shown in Fig. 3a: (1) VDS represents the effective pulse composed of pre- and post-synaptic pulses, indicating the STDP signal; (2) The relaxation effect of the conductance after the pulse represents the decay of the eligibility trace; (3) The delayed VGS pulse represents the delayed reward signal, a negative VGS pulse (resulting in increased conductance) corresponds to a positive reward, whereas a positive VGS pulse (resulting in decreased conductance) corresponds to a negative reward. The combined effect of VDS and VGS results in the final conductance update.

The R-STDP update formula requires that the weight not update when only one signal is present. The weight updates only when both STDP(t) and R(t) signals are present simultaneously (Supplementary Fig. 9). This requirement can be met by setting the amplitude of a single pulse near the ferroelectric threshold. The threshold test results for VDS and VGS are shown in Supplementary Fig. 10, with values of 5 V and 2.1 V. More importantly, in R-STDP, the longer the delay of the reward signal, the more the eligibility trace decays, and the smaller the final weight update value. The α-In2Se3 FeS-FET achieves this through the time interval between VDS and VGS pulses. The larger the time interval, the more pronounced the ferroelectric relaxation, resulting in a weaker modulation. Supplementary Fig. 11 shows the modulation results for different time intervals, which align with the expectations. Statistical results (Fig. 3b and 3c) indicate that the greater the delay of the reward signal, the weaker the weight modulation. The results align well with the standard R-STDP curve. This demonstrates that α-In2Se3 FeS-FET can realize the functionality of R-STDP synapses.

As a widely used concept in RL, eligibility trace can effectively improve learning efficiency and has been validated in biological systems4,46–48. However, on CMOS-based or NVMs-based computing platforms14,16,24,49, implementing decaying eligibility traces exponentially requires significant hardware overhead (For example, in Fig. 1b, multiple PCMs in parallel are required to utilize their resistance drift to achieve the eligibility trace). Furthermore, it is also difficult for FeFET and charge-trapping memories to realize a decaying trace via simple pulse modulation. While often considered a non-ideal effect, ferroelectric polarization relaxation has been successfully exploited in recent studies to enable complex functionalities such as reservoir computing36,37 and associative learning50. Rather than a detriment, relaxation serves as a valuable, controllable mechanism36,51 for neuromorphic and unconventional computing. In this work, we leverage ferroelectric relaxation to naturally achieve eligibility trace decay with tunable relaxation time. The definition of the relaxation time τ is shown in Fig. 3d. To achieve tunable τ, measurements with varying VDS pulse amplitudes and widths are performed (Supplementary Fig. 12). Figure 3d indicates that the larger the amplitude (3~7 V), the greater the τ, while the pulse width (7~15 ms) has no effect on τ. The differences observed in the hysteresis loops under different VDS demonstrate the influence of VDS on polarization and relaxation (Supplementary Fig. 13). This may be related to the sensitivity of the depolarization field to voltage51. Therefore, by increasing the amplitude and reducing the pulse width (Fig. 3e), we can achieve different eligibility trace relaxation times without altering the conductance with a single VDS pulse, in accordance with the requirements of the R-STDP formula. Figure 3f shows the R-STDP test results under three different τ values. The tunable range based on α-In2Se3 FeS-FET can reach up to 28-189 ms, which is comparable to the eligibility trace times in biological systems4. Tunable relaxation time τ of eligibility trace by electrical pulses allows the algorithm to achieve optimal performance across various scenarios, particularly in complex problems20,47.

Supplementary Table 1 summarizes the comparison of R-STDP implementation by different hardware. Compared to systems that incur higher hardware costs and only partially implement R-STDP functions (synaptic weights, eligibility traces, and reward signals), this work integrates all R-STDP functionalities into a single α-In2Se3 FeS-FET, enabling in-situ weight updates and incorporating tunable eligibility traces. Our approach reduces the hardware complexity by a factor of several times. This learning rule is realized by our FeS-FET with about 10 µm2 footprint. Furthermore, it exhibits low operating energy consumption, approximately 65 pJ per R-STDP event (Supplementary Fig. 14), demonstrating a significant advantage over comparable devices (Supplementary Table 1). Therefore, it indicates the significant predominance in area, energy, and latency of the hardware SNN system for RL. Meanwhile, the power consumption of the printed circuit board (PCB) control circuit is significantly higher than that of the device itself (Supplementary Note 1). Future improvements are expected to achieve much higher energy efficiency through custom on-chip integration52,53 or novel memristor-based ADC54. Supplementary Table 2 summarizes α-In2Se3-based synaptic devices. The R-STDP synapse presented in this work exhibits distinct advantages in terms of joint IP and OOP modulation, conductance range, and energy consumption.

Spiking reinforcement learning neural network
RL has gained widespread application in areas such as autonomous driving, gaming, and robotic control due to its ability to handle open-ended tasks effectively. To demonstrate the application of In2Se3 FeS-FET-based R-STDP synaptic reinforcement learning, we set up an autonomous driving scenario as shown in Fig. 4a. Supplementary Fig. 15 illustrates the detailed simulation scenario. The lane scene captured by the vehicle’s camera is compressed into a 3 × 6 pixels format55, where each pixel is encoded by pulse count to generate 18 pulse sequences that are separately input to 18 input neurons of the spiking RL neural network connected by R-STDP synapses.

A 6×8 In2Se3 FeS-FET array and a corresponding PCB circuit operating system are fabricated to accomplish the autonomous driving task (Fig. 4b and Supplementary Fig. 16). The measured pulse output from the PCB writing circuitry in Supplementary Fig. 17 demonstrates that the circuit system exhibits extremely low noise. An analysis of the circuit system’s power consumption is presented in Supplementary Note 1. Figure 4c present the R-STDP curve of the 36 devices in the array, with detailed curves presented in Supplementary Fig. 18. The ID-VG (OOP polarization) and ID-VD (IP polarization) curves also demonstrate good consistency (Supplementary Fig. 19 and Supplementary Fig. 20). Supplementary Fig. 21 presents the statistical information of the on-off ratio. The process of writing weights to three individual devices via the PCB circuit system, along with the corresponding writing results, is illustrated in Supplementary Fig. 22. The weight distribution pre-trained by the software is shown in Supplementary Fig. 23. The actual weight distribution, written into the array according to the required weights based on the R-STDP curve, is shown in Fig. 4d. Figure 4e present that the performance of the experimental array with written weights is largely consistent with the performance of the weights pre-trained by software in the autonomous driving task. Supplementary Fig. 24 shows the weight distribution at 300 seconds and 800 seconds after array writing, along with the corresponding performance. Even in the presence of a certain degree of Device-to-Device (D2D) variation or noise variation, the network remains capable of successful convergence, exhibiting a slight reduction in convergence speed (Supplementary Figs. 25 and 26). This demonstrates the strong redundancy capability of the In2Se3 FeS-FET-based RL neural network. This is attributed to the closed-loop nature of in-situ training, where the iterative weight updates dynamically compensate for static device errors. Consequently, the algorithm automatically adjusts the number of update steps to reach the target conductance, effectively mitigating the impact of individual device variability56–61.

As mentioned earlier, eligibility trace is a key concept in RL and can significantly improve algorithm performance. The adjustable eligibility trace decay constant ensures optimal performance across different tasks. In2Se3-based synapses can easily adjust the decay constant through different pulses (Fig. 3e, f). To validate the effect of eligibility trace, Fig. 4f shows the performance of the training process with different decay time constants. The details of weight evolution during training are shown in Supplementary Fig. 27. The results indicate that as the decay time constant increases, the convergence speed initially rises and then falls, reaching its peak at 130 ms. Additionally, the convergence speed decreases without eligibility traces. More data on convergence speed and time constants are presented in the inset of Fig. 4f. This result indicates that an adjustable eligibility trace time constant significantly impacts algorithm performance. R-STDP synapses based on In2Se3 FeS-FET effectively enhance the algorithm’s processing capability through relaxation time constants (28–189 ms) adjustable by pulse amplitude.

Methods
Device fabrication
The transistor was fabricated on Al2O3/p-Si (30 nm/500 µm) substrate by transferring α-In2Se3 thin flakes using polydimethylsiloxane-assisted exfoliation and transfer methods. Then the source and drain electrode regions (with 1 µm between them) were patterned by electron beam lithography. Cr/Au (10/50 nm) electrodes were deposited through e-beam evaporation followed by a lift-off process. Finally, 5 nm of Al2O3 was covered by atomic layer deposition technology as a passivation layer.

As for the α-In2Se3 FeS-FET array, the local bottom gate electrodes (Cr/Au, 5 nm/25 nm) were patterned by electron beam lithography on SiO2/p-Si (300 nm/500 µm) substrate. Then, 30 nm Al2O3 is deposited as the gate insulation layer by atomic layer deposition. The α-In2Se3 synthesized by Flux-assisted growth is transferred to the gate electrode via polyvinyl alcohol assisted transfer. The α-In2Se3 is patterned by electron beam lithography, then the channel region is formed by inductively coupled plasma etching (Cl2+SF6). Finally, top source and drain electrodes (Cr/Au, 10 nm/50 nm) were patterned.

Device characterization
Room-temperature electrical measurements were carried out using a Lakeshore probe station equipped with an Agilent B1500A and B1530 semiconductor parameter analyzer. The high/low-temperature measurements were carried out in a Lakeshore cryogenic probe station in vacuum conditions, equipped with an Agilent B1500A semiconductor parameter analyzer.

Raman spectra of the exfoliated α-In2Se3 flakes on the SiO2 substrate were obtained using a Raman imaging microscope (Horiba LabRAM Odyssey) with an excitation laser of 532 nm. Scanning electron microscopy (SEM) images were obtained using a field emission scanning electron microscope (JSM-7900F). PFM measurements were performed using a multimode AFM device (Bruker Dimension Icon).

Reinforcement learning based spiking neural network
The autonomous driving environment setup is simulated by Python based on the reported model62. We constructed a spiking neural network with a scale of 18 × 2 to process an autonomous driving task, where 18 input neurons represent the 3 × 6 input image information, and two output neurons correspond to left and right turns. The parameters of the simulation environment are listed in Table 1. The synaptic weight update behaviors are based on the R-STDP characteristics of the α-In2Se3 synaptic cell. The neuron mode is based on the leaky integrate and fire neuron (LIF neuron). Based on the spiking output and the reward signal, the synaptic conductance is then updated based on the R-STDP characteristics. The specific weight update method is as follows.

The STDP as a function of the time difference between pre- and postsynaptic spikes is defined as:

Δt = tpost − tpre (1)

W(Δt) = A+ e−Δt/τ+ , Δt ≥ 0
−A− eΔt/τ− , Δt < 0 (2)

Δw = W(Δt) (3)

where w is the synaptic weight. Δw is the change of the synaptic weight. tpre and tpost stand for the timing of the firing spike from pre-neuron and post-neuron. A+ and A− represent positive constants scaling the strength of potentiation and depression, respectively. τ+ and τ− are positive time constants defining the width of the positive and negative learning window.

In the R-STDP, the synaptic weight w changes with the reward signal R. The eligibility trace of a synapse can be defined as:

c(t) = c(t) / τc + W(Δt)δ(t − tpre=post) (4)

where c is an eligibility trace. tpre=post means the time of a pre or postsynaptic spikes. C1 is a constant coefficient. τc is a time constant of the eligibility trace. δ is the Dirac delta function.

w(t) = R(t) × c(t) (5)

where R(t) is the reward signal. More details on the R-STDP mechanism can be found in the paper3,63.

Data availability
The data that support the plots within this paper and other findings of this study are available from the corresponding author upon request. Source data are provided with this paper.

Code availability
The code for the SNN with the scheme is available from the corresponding author with detailed explanations upon request.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "This paper shows in-situ spiking reinforcement learning with eligibility trace by In2Se3 FeS-FET technology. Specially, hardware implementation of spiking reinforcement learning neural network is demonstrated by A 6×8 In2Se3 FeS-FET array to accomplish the autonomous driving task. Overall, this is a timely work and deserve publishing in this journal. The detailed comments are shown below.\n1. In the current version of the manuscript, the need to use In2Se3 FeS-FET is not clearly described. How is the proposed In2Se3 FeS-FET technology compared to other NVM memory technologies like FeFET and charge-trapping memory?\n2. For the hardware implementation of spiking RL neural network with a 6×8 In2Se3 FeS-FET array, the authors only show the results of FeS-FET array. How are the peripherals such as sensing circuit, MUX, etc.? The authors should clarify more details about the hardware system not just the array.\n3. Since the authors use In2Se3 FeS-FET array, the operating conditions (e.g., inhibition) for the array configuration during the spiking reinforcement learning process need to be systematically confirmed.\n4. In addition, the paper lacks analysis of the system's power consumption and accuracy for a practical setting.\n5. How is the effect of noise in the device/circuit/system quantified?\n6. According to Fig. 4 (c), devices in an array show large device-to-device variation. How does the variation affect the accuracy of the proposed hardware system?", "reviewer_2": "This study demonstrates a brain-inspired spiking neural network (SNN)-based reinforcement learning (RL) computing architecture utilizing α-In2Se3 ferroelectric semiconductor field-effect transistors (FeS-FETs). Specifically, an autonomous driving task is implemented using an RL neural network constructed from an α-In2Se3 FeS-FET array. While the integration of α-In2Se3 FeS-FETs into an RL framework is conceptually intriguing, the manuscript suffers from insufficient novelty, inadequate mechanistic explanations, and unresolved practical challenges in device uniformity and system-level implementation. Consequently, the conclusions drawn appear premature, necessitating further extensive research to validate the practical applicability and value of artificial neurons with spatiotemporal specificity. For these reasons, the reviewer does not recommend publishing this manuscript in Nature Communications, as outlined by the major critiques below (though not exhaustively).\nMajor Concerns:\n1、The manuscript fails to demonstrate significant innovation. The utilization of α-In2Se3's in-plane (IP) and out-of-plane (OOP) ferroelectric polarization coupling for third-terminal synaptic plasticity and reward-modulated spiking reinforcement learning (RL) has been extensively reported in prior studies (e.g., ACS Nano 2025, 19, 13, 13287–13299). The proposed physical mechanisms and application scenarios (e.g., autonomous driving) largely overlap with existing literature, without introducing new insights or methodologies. Furthermore, the synaptic device performance (e.g., conductance modulation range, cycling endurance) shows no breakthrough compared to state-of-the-art ferroelectric transistors.\n2、Eligibility Trace (ET) Implementation: The authors attribute ET decay to ferroelectric polarization relaxation caused by depolarization fields. However, depolarization-induced relaxation is typically an undesirable property in ferroelectric devices, and its controllability/consistency remains unproven. The manuscript merely states that \"current relaxation aligns with ET decay\" without clarifying the quantitative correlation between polarization dynamics and algorithmic parameters (e.g., decay time constants, causality principles). Additional evidence, such as direct measurements of polarization relaxation kinetics and their mathematical mapping to ET decay, is required.\n3、R-STDP Uniformity: The R-STDP curves in Fig. 4c exhibit poor uniformity, with weight changes ranging from 12% to 26% at a 50 ms time interval. This raises concerns about the feasibility of reliable in-situ training in a 36-device array (Supplementary Fig. 16), where significant variations in threshold voltages, memory windows, and IDVD、IDVG characteristics are observed.\n4、Neural Network Implementation: The autonomous driving task (Fig. 4a) lacks critical details. For instance:\nHow are the 18 input neurons interfaced with the 3×6 pixel grid?\nHow are reward signals selectively applied to specific synapses without unintended weight updates in adjacent devices (e.g., column-wise crosstalk during VGS modulation)?\nThe absence of crossbar addressing schemes (e.g., read/write voltages, line resistance effects) in the 6×8 array (Fig. 4b) undermines the practical viability of the proposed architecture.\n5、PFM Data Quality: The piezoresponse force microscopy (PFM) phase and amplitude images (Supplementary Fig. 2c,d) lack sufficient resolution and quantitative analysis, casting doubt on the claimed IP/OOP polarization coupling.\n6、Relaxation Time Variability: The tunable relaxation time constants (28–189 ms) in Fig. 3e-f are attributed to depolarization field sensitivity, but no direct evidence (e.g., field simulations, polarization hysteresis loops under varying VDS conditions) supports this claim.\nMinor Concerns:\nPage 6, Line 1: \"The hysteresis window is caused by IP and OOP polarization, respectively\" → Ambiguous phrasing.\nSpecify which hysteresis corresponds to IP/OOP polarization.\nPage 9, Last line: \"the later the delayed reward signal\" → Replace \"later\" with \"longer delay of the reward signal\" for clarity.\nFigure 4e: The y-axis label (\"distance from the lane center\") requires units.", "reviewer_3": "This manuscript presents an interesting and original contribution, demonstrating a hardware implementation of a spiking neural network (SNN)-based reinforcement learning (RL) algorithm using α-In₂Se₃ ferroelectric semiconductor field-effect transistors (FeS-FETs) that exhibit both in-plane (IP) and out-of-plane (OOP) polarization coupling. The demonstration of three key brain-inspired functions—spike-timing-dependent plasticity (STDP), eligibility traces, and reward modulation—adds significant novelty and depth to the study. The experimental results are convincing and well-structured.\nThe manuscript merits consideration for publication after addressing the following points of clarification:\nQuestion1: Material Thickness and Scalability: The devices are fabricated using exfoliated α-In₂Se₃ flakes with a relatively large thickness (~40 nm), which enables the observation of ferroelectric hysteresis and resistive switching effects attributed to the interplay between OOP and IP polarizations.\n(i) Have the authors systematically investigated how these two properties vary with flake thickness? A comparative analysis or discussion on thickness-dependent behavior would enhance the understanding of the underlying mechanisms.\n(ii) Given that mechanical exfoliation is not scalable for large-scale integration, the authors should comment on the feasibility of synthesizing α-In₂Se₃ via wafer-scale techniques such as chemical vapor deposition (CVD), and address potential constraints related to integration on standard silicon substrates.\nQuestion 2: Trade-offs Between Ferroelectricity and Resistive Switching: Is there an intrinsic trade-off between enhancing the ferroelectric polarization and optimizing the resistive switching behavior in this material system? A discussion, possibly supported by a simplified physical or phenomenological model, would be valuable to assess whether the coexistence of both functionalities could result in compromised individual performance compared to dedicated ferroelectric or resistive-switching materials. Please compare the performance with state of the art high-k ferroelectric and resistive-switching materials.\nQuestion 3: Voltage Requirements and Material Engineering: The operational voltages reported in Figures 2b and 2c, particularly for resistive switching, remain relatively high. This is a significant concern given that state-of-the-art resistive memory devices typically operate below 1 V. The authors are requested to discuss the prospects for reducing operating voltages in α-In₂Se₃ FeS-FETs. Beyond geometric scaling, are there material engineering strategies (e.g., doping, strain, interface engineering) that could further tailor the polarization and switching characteristics?\nQuestion 4: Thermal Stability and Temperature Range: In Supplementary Figure 3, the authors present hysteresis loops measured from room temperature down to 90 K, supporting the attribution to OOP ferroelectric switching. Have the devices also been characterized at elevated temperatures (e.g., up to 85°C or 100°C)? Assessing thermal stability is essential for realistic deployment in neuromorphic hardware operating under varying environmental conditions.\nQuestion 5: Device Variability and Yield: The ID–VG characteristics from an array of 36 devices exhibit substantial variability, with many devices showing incomplete or non-saturated polarization switching and also highly variable characteristics of resistive switching. The authors should provide a detailed analysis of the sources of this variability — e.g., flake quality, interface states, contact resistance, or fabrication-induced disorder — and outline potential strategies for variability mitigation. Furthermore, how is this variability tolerated or compensated for in the reported neuromorphic applications?"}, "author_response": "Point-by-point Response\nWe thank all the reviewers for their precious time and constructive comments on our\nmanuscript. We are delighted that the 1st and 3rd reviewers speak highly of our work\nand recommend the publication of this paper after proper revisions. The 2nd reviewer\nconcerns the novelty of this work. In this revision, we have addressed all the concerns\nraised. A summary of the major revisions is provided at the end.\nIn the following point-to-point response, the original reviewers’ comments are in blue\ncolored italic font, our responses are in black fonts. Changes in the revised main text\nand SI are highlighted in yellow, with the revised content presented in black italic font.\nResponse to Reviewers' comments:\nReviewer #1 (Remarks to the Author):\nThis paper shows in-situ spiking reinforcement learning with eligibility trace by In Se\n2 3\nFeS-FET technology. Specially, hardware implementation of spiking reinforcement\nlearning neural network is demonstrated by A 6×8 In Se FeS-FET array to accomplish\n2 3\nthe autonomous driving task. Overall, this is a timely work and deserve publishing in\nthis journal. The detailed comments are shown below.\nResponse: We thank the reviewer for the positive comments and recommendation.\n1. In the current version of the manuscript, the need to use In Se FeS-FET is not clearly\n2 3\ndescribed. How is the proposed In Se FeS-FET technology compared to other NVM\n2 3\nmemory technologies like FeFET and charge-trapping memory?\nResponse: We thank the reviewer for this comment. We chose the In₂Se₃ FeS-FET\nbecause it possesses both in-plane (IP) and out-of-plane (OOP) polarization modes,\nenabling three-terminal conductance modulation via both V and V . This feature\nds gs\naligns well with the requirements of our reinforcement learning algorithm based on\nreward-modulated spike-timing-dependent plasticity (R-STDP), as illustrated in Fig.\n1c. In biological systems, R-STDP is typically implemented through three-terminal\nsynapses, where STDP is governed by pre- and post-synaptic spikes, and the reward\nsignal is delivered through a third pathway mediated by dopamine. In our\nimplementation, V modulates the conductance via IP polarization to emulate the STDP\nds\ncomponent, while V modulates the conductance via OOP polarization to represent the\ngs\nreward signal.\nIn contrast, other non-volatile memory technologies such as FeFET and charge-trapping\nmemories, although capable of memory retention, lack the ability for multi-terminal\nmodulation, typically allowing only V based control, thus making them unsuitable for\ngs\nimplementing R-STDP based reinforcement learning.\nFurthermore, we introduce a novel mechanism by leveraging the intrinsic ferroelectric\nrelaxation behavior of the OOP polarization to physically emulate the decay of the\neligibility trace (ET). The temporal relaxation of polarization-induced current in the\nFeS-FET follows an exponential form that matches the mathematical formulation of ET\ndecay used in reinforcement learning models. This physical alignment enables a\nhardware-efficient, device-level realization of the eligibility trace without additional\ncircuitry, representing a key innovation of our work.\nOn the other side, regarding the emulation of ET, some recent research demonstrated\ninteresting ET behavior by utilizing the temporal decay of phase-change material (PCM)\nconductanceR1. However, since they are usually two-terminal, PCM devices could\nhardly be utilized to emulate the complexed R-STDP behavior. Furthermore, realizing\nthe eligibility trace also requires multiple PCMs connected in parallel. As for charge-\ntrapping memories and FeFET, there are currently no reports demonstrating the\nrealization of tunable eligibility traces using these devices. More critically, they are\nincapable of achieving multi-terminal modulation. Therefore, the emulating of both\nmultiple-terminal tuning and the eligibility trace requested by R-STDP learning rules\noutlines the innovation of our developed devices and circuitry.\nTo make this point clearer, we made the following revisions in the revised main text.\n1. In page 4, we added:\n“The two-dimensional (2D) ferroelectric semiconductor α-In Se , with IP and\n2 3\nOOP polarization coupling25-33, enables complex analog calculations34-40. Compared\nto other non-volatile memory devices (e.g., FeFET and charge-trapping memories),\nthe three-terminal modulation capability of the FeS-FET provides an additional\nindependent control terminal. This feature can be utilized to emulate more complex\nbiological synaptic characteristics, such as the dopamine-synapse-based R-STDP\ncharacteristics demonstrated in this work.”\n2. In page 10, we added:\n“However, on CMOS-based or NVMs-based computing platforms14, 16, 24, 49,\nimplementing exponentially decaying eligibility traces requires significant hardware\noverhead (For example, in Fig. 1b, multiple PCMs in parallel are required to utilize\ntheir resistance drift to achieve the eligibility trace). Furthermore, it is also difficult for\nFeFET and charge-trapping memories to realize a decaying trace via simple pulse\nmodulation. In this work, we leverage ferroelectric relaxation to naturally achieve\neligibility trace decay with tunable relaxation time.”\nReferences:\nR1 Lu, Yingming, et al. \"In‐memory realization of eligibility traces based on conductance drift of phase\nchange memory for energy‐efficient reinforcement learning.\" Advanced Materials 34.6 (2022): 2107811.\n2. For the hardware implementation of spiking RL neural network with a 6×8 In Se\n2 3\nFeS-FET array, the authors only show the results of FeS-FET array. How are the\nperipherals such as sensing circuit, MUX, etc.? The authors should clarify more\ndetails about the hardware system not just the array.\nResponse: We thank the reviewer for the useful suggestions. We have added a\nphotograph of the PCB and its corresponding block diagram as Supplementary Fig.\n16, the write operations of three typical devices using the PCB circuit system as\nSupplementary Fig. 22 in the revised SI.\nSupplementary Fig. 16. Circuit system of array operation. (a) Photograph of the PCB and (b) its\ncorresponding modular block diagram. The figure details the microcontroller unit (MCU), the power\nsupply module, the read/write circuitry, the FeS-FET array, and the switch matrix for device selection,\nas well as the signal flow and control relationships among these functional modules. Specifically, the\nMCU is responsible for the centralized control of the read/write circuitry and the logic control circuitry.\nThe MCU provides one ADC port and two DAC ports to the read/write circuitry. It also provides multiple\nports to control the logic circuitry, which are primarily used to control the pulses output from the\nread/write circuitry, ensuring they are applied to the corresponding devices via the switch matrix. The\nwrite circuitry module is responsible for receiving DAC signals from the MCU, which are subsequently\namplified by internal circuitry to generate write voltage pulses. The pulse width is precisely controlled\nby the MCU (down to the microsecond level). The three switch matrices correspond respectively to the\ngate, source, and drain of the devices within the array. The MCU controls the switches of the selected\nchannels in these matrices, thereby ensuring that the pulses output from the write circuitry are correctly\napplied to the gate/drain of the targeted device to complete the write operation. The read operation is\nanalogous: the read circuitry samples the voltage signal from the source, and after amplification by the\nread circuitry, the signal is transmitted to the ADC port of the MCU for sampling and conversion.\nSupplementary Fig. 22 Read/write operations of the PCB circuit system. (a), (b) and (c): conductance\nevolution of three devices during read/write operations. (d), a write-verify scheme was adopted.\nAdditionally, we have also added the following description of the array operation\ncircuitry to the revised main text in page 12:\n“A 6×8 In\nwas fabricated to accomplish the autonomous driving task (Fig. 4b and Supplementary\nFig. 16). The measured pulse output from the PCB writing circuitry in Supplementary\nFig. 17 demonstrates that the circuit system exhibits extremely low noise. Fig. 4c\npresents the R-STDP curve of the 36 devices in the array, with detailed curves presented\nin Supplementary Fig. 14. The I\nD\n-V\nG\n(OOP polarization) and I\nD\n-V\nD\n(IP polarization)\ncurves also demonstrate good consistency (Supplementary Fig. 15 and 16).\nSupplementary Fig. 17 presents the statistical information of the on-off ratio. The\nprocess of writing weights to three individual devices via the PCB circuit system, along\nwith the corresponding writing results, is illustrated in Supplementary Fig. 22”\nAnd this work focuses on the hardware implementation of synapses for reinforcement\nlearning neural networks, while the fabrication of the vision sensor itself is beyond the\nscope of this study. The visual signals utilized in this work can be acquired using\nestablished dynamic vision sensors (DVS).\n3. Since the authors use In Se FeS-FET array, the operating conditions (e.g., inhibition)\n2 3\nfor the array configuration during the spiking reinforcement learning process need to\nbe systematically confirmed.\nResponse: We thank the reviewer for suggestion on further explaining array operations.\nFor details on device selection and the read/write operations within the array, please\nrefer to our detailed Response to Comment 2 and Supplementary Fig. 16. Here, we\nelaborate on the specific process of the weight update procedure.\nFor weight potentiation (positive reward), a positive reward signal from the\nenvironment is applied to the device's gate, corresponding to a negative pulse (a\nnegative gate pulse increases the channel conductance). This occurs while the channel\nconductance is already in the process of decaying following an initial increase caused\nby the STDP signal (as depicted in the top-right inset of Fig. 3b, where the first rising\npulse is due to STDP, and the subsequent brief conductance decay corresponds to the\ndecay of the eligibility trace). At this moment, the effect of the negative pulse, which\nincreases conductance, is superimposed onto this decaying trace (corresponding to the\nsecond rising pulse in the Fig. 3b inset). The synergistic action of these two effects\npotentiates (strengthens) the conductance (weight).\nFor weight depression (negative reward/inhibition), a negative reward signal from the\nenvironment is applied to the device's gate, corresponding to a positive pulse (a positive\ngate pulse decreases the channel conductance). This also occurs while the conductance\nis in the STDP-induced post-enhancement decay phase. In this case, the modulation\neffect of the positive gate pulse overcomes the STDP-induced trace effect, resulting in\nthe suppression (depression) of the conductance (weight) (as shown in the top-right\ninset of Fig. 3c).\nOn page 8 of the revised main text, we have made the following adjustments to make\nthe point clearer:\n“The delayed V pulse represents the delayed reward signal, a negative V pulse\nGS GS\n(resulting in increased conductance) corresponds to a positive reward, whereas a\npositive V pulse (resulting in decreased conductance) corresponds to a negative\nGS\nreward.”\n4. In addition, the paper lacks analysis of the system's power consumption and accuracy\nfor a practical setting.\nResponse: We thank the reviewer for the valuable suggestions regarding the system's\npower consumption and accuracy. Firstly, system power consumption is a highly\nrelevant issue. We will address this by discussing the power consumption of the FeS-\nFET and the PCB operational circuitry separately.\nRegarding the FeS-FET 's power consumption, we have added Supplementary Fig. 14\nto the revised SI for analysis.\nSupplementary Fig. 16. Current and energy consumption analysis for FeS-FET operation. This\nillustrates the FeS-FET's current response during an R-STDP event, where the two sequential pulses are\nV and V , respectively. Accordingly, the power consumption of a single synaptic event can be\nDS GS\ncalculated using the following formula: E = V × I ×t + V × I × t , where V = 6.5 V,\nDS DS DS DS_read DS_read GS DS\nI = 6.7 nA, and t = 1.5 ms are the amplitude of the V pulse, the channel current, and the V pulse\nDS DS DS DS\nwidth, respectively; and V = 0.1 V, I = 5.7 nA, and t = 1 ms are the amplitude of the V\nDS_read DS_read GS GS\npulse, the channel current, and the V pulse width, respectively. Therefore, the energy consumption is E\nGS\n≈ 65 pJ.\nConcurrently, we have added the following description regarding power consumption\nto the revised main text on page 11:\n“This learning rule is realized by our FeS-FET with about 10 µm2 footprint.\nFurthermore, it exhibits low operating energy consumption, approximately 65 pJ per\nR-STDP event (Supplementary Fig. 14), demonstrating a significant advantage over\ncomparable devices (Supplementary Table 1).”\nRegarding the power consumption of the PCB, we have added the following analysis\nin Supplementary Note 1 of the revised SI.\n“Supplementary Note 1: Power consumption of the PCB system. The power\nestimation for each module is explained as follows, based on a system-wide supply\nvoltage of V = 3.3 V. For the microcontroller unit (MCU), the power consumption\nS\nconsists of two parts: static and dynamic. The static power is calculated as P =\nMCU_S\nV × I = 3.3 V × 1 mA = 3.3 mW, where the static current (I ) is 1mA. The\nS MCU_S MCU_S\naverage dynamic power for operations is P = V × I × t × f = 3.3 V × 25\nMCU_D S MCU_D r s\nmA × 1ms × 100 Hz = 8.25 mW, where the dynamic current (I ) is 25 mA, operation\nMCU_D\nduration (t = 1 ms), and operation frequency (f = 100 Hz) are determined by the\nr s\nsystem's workload. because this work employs an SNN, the signals possess inherent\nsparsity, thus resulting in a relatively low frequency. Therefore, the total power for the\nMCU is P = P + P = 11.55 mW. For the amplifier module, which\nMCU_D MCU_S MCU_D\ncontains the read/write circuitry, the total current for the module is I = I\nAMP_total AMP_single\n× N = 100 μA × 8 = 800 μA, where I is the current of a single amplifier chip\nAMP AMP_single\n(100 μA) and N is the number of amplifiers used (NAMP = 8). The total power\nAMP\nconsumption of the amplifier module can be calculated as P = V × I = 3.3\nAMP S AMP_total\nV × 800 μA = 2.64 mW. For the switch matrix module, power consumption consists of\ntwo parts. The static power is P = V × I × N = 3.3 V × 0.1 μA × 3 = 0.99\nSM_S S SM_S SM\nμW, where I is the static current per chip (0.1 μA) and N is the number of matrix\nSM_S SM\nchips (N = 3). The average dynamic power is P = V × I ×N × t × f = 3.3\nSM SM_D S SM_D SM r s\nV × 2 μA × 3 × 1ms × 100 Hz = 1.98 μW, where I is the dynamic current per active\nSM_D\ngate (2 μA). Therefore, the total power of the switch matrix module is P = P +\nSM SM_S\nP = 2.97 μW. Finally, the total estimated power consumption of the system is the\nSM_D\nsum of these modules, P = P + P + P = 11.5 mW + 2.64 mW + 2.97 μW ≈\nTotal MCU AMP SM\n14.19 mW.”\nConcurrently, we have added a corresponding description of the power consumption on\npage 12 of the revised main text.\n“The measured pulse output from the PCB writing circuitry in Supplementary\nFig. 17 demonstrates that the circuit system exhibits extremely low noise. An analysis\nof the circuit system's power consumption is presented in Supplementary Note 1.”\nWe fully agree that evaluating the system’s performance in a practical setting is of\ncritical importance. The reviewer mentioned accuracy, and we would like to clarify that\nsince this work evaluates a RL task, rather than a Supervised Learning task,\n“classification accuracy” is not used as the performance metric. In RL, the key metrics\nused to evaluate performance are the “Average Cumulative Reward” or “Convergence\nSpeed”. These metrics quantitatively evaluate how well the agent performs its policy\nand its learning speed over its lifecycle. This performance is demonstrated in Figure 4f.\nFurthermore, the hardware implementation for RL proposed in this work was also\nvalidated on the RL classic “cart-pole” benchmark. The Fig. R1. illustrates the\n“convergence speed” under different eligibility trace relaxation time constants. The y-\naxis represents the “average cumulative reward”, where a higher value indicates better\nperformance.\nFig. R1. Convergence speed in the cart-pole task under different eligibility trace relaxation time\nconstants. The x-axis represents the training epoch, and the y-axis represents the normalized average\nreward.\n5. How is the effect of noise in the device/circuit/system quantified?\nResponse: The noise of the circuit system can be characterized by examining the actual\noutput pulses. We have added Supplementary Fig. 17 to the revised SI to evaluate this\nnoise. Supplementary Fig. 17 displays a pulse configured with an amplitude of 6 V\nand a duration of 5 ms. The actual output, measured using an oscilloscope, exhibits a\nmean amplitude of 6.024 V, a variance of 0.0005 V, and rise/fall times of 100 μs,\ndemonstrating extremely low noise levels. Consequently, the minimal noise generated\nby the circuit system will have a negligible impact on the device performance.\nSupplementary Fig. 17. Noise characterization of the PCB circuit system. For a pulse configured with\nan amplitude of 6 V and a duration of 5 ms, the output exhibited a mean amplitude of 6.024 V, a variance\nof 0.0005 V, and rise/fall times of 100 μs, demonstrating extremely low noise levels.\nWe have also made the following additions to page 12 of the revised main text:\n“A 6×8 In\nwas fabricated to accomplish the autonomous driving task (Fig. 4b and Supplementary\nFig. 16). The measured pulse output from the PCB writing circuitry in Supplementary\nFig. 17 demonstrates that the circuit system exhibits extremely low noise.”\nDevice-induced noise can be uniformly treated as write noise. We have added\nSupplementary Fig. 26 to the revised SI to evaluate the impact of this write noise.\nConsidering the noise, the weight update formula is given by Δw = Δw + α\nideal noise,\nwhere Δw represents the ideal update value, Δw denotes the actual update value, and\nideal\nα corresponds to the noise introduced during each write update operation, with α\nnoise noise\nfollowing a gaussian distribution: α\nnoise\n~ N (μ = 0, σ = σ\nnoise\n). The results indicate that\ntraining can be successfully completed within a noise variation σ range of 0 nS to 0.5\nnS (As a reference for the applied noise level, the conductance of the devices within\nthe array ranges from approximately 0.6 nS to 12 nS.), with the only notable difference\nbeing a slight decrease in convergence speed.\nSupplementary Fig. 17. Evaluation of the device noise on performance. (a) The number of steps\nrequired for convergence under different noise variation σ, calculated as the average of five training\nruns. (b) The normalized reciprocal of the convergence steps, which serves as a proxy for training\nconvergence speed. (c) The inference (testing) performance using weights converged under different\nnoise variation σ. The results indicate that training can be successfully completed within a noise variation\nσ range of 0 nS to 0.5 nS (As a reference for the applied noise level, the conductance of the devices within\nthe array ranges from approximately 0.6 nS to 12 nS.), with the only notable difference being a slight\ndecrease in convergence speed. The device variation is defined as follows: the weight update formula is\ngiven by Δw = Δw + α , where Δw represents the ideal update quantity, Δw is the actual update\nideal noise ideal\nquantity, and α denotes the deviation introduced by noise variation. Here, α follows a gaussian\nnoise noise\ndistribution: α ~ N (μ = 0, σ = σ ).\nnoise noise\nWe have made the following additions regarding noise variation to the revised main\ntext in page 13:\n“Even in the presence of a certain degree of D2D variation or noise variation, the\nnetwork remains capable of successful convergence, exhibiting a slight reduction in\nconvergence speed (Supplementary Fig. 25 and Supplementary Fig. 26). This\ndemonstrates the strong redundancy capability of In Se FeS-FET based RL neural\n2 3\nnetwork. This is attributed to the closed-loop nature of in-situ training, where the\niterative weight updates dynamically compensate for static device errors. Consequently,\nthe algorithm automatically adjusts the number of update steps to reach the target\nconductance, effectively mitigating the impact of individual device variability53-58.”\n6. According to Fig. 4 (c), devices in an array show large device-to-device variation.\nHow does the variation affect the accuracy of the proposed hardware system?\nResponse: We thank the reviewer for their suggestion regarding the evaluation of\ndevice-to-device (D2D) variation. We have added Supplementary Fig. 25 to the\nrevised SI to evaluate the impact of D2D variation. The results indicate that within a\nD2D variation σ range of 0 to 0.5, the training process converges successfully, and the\ninference performance remains virtually unchanged. The primary effect of D2D\nvariation is a slight reduction in convergence speed. Given that the calculated average\nvariation for all curves presented in Fig. 4 c is σ = 0.36, we conclude that this level of\nvariation does not compromise the learning efficacy.\nPrevious studies have established that in-situ training schemes possess an inherent\nresilience to device non-idealities R1, R2. Unlike ex-situ weight mapping, where device\nvariations lead to direct inference errors, the iterative nature of on-line learning allows\nthe system to compensate for static D2D variation by dynamically adjusting the number\nof update stepsR3, R4. Specifically, Querlioz et al. and Ly et al. demonstrated that SNNs\ntrained with STDP can tolerate parameter variability as high as 50% without significant\nperformance degradationR5, R6, which aligns with our experimental observations.\nSupplementary Fig. 25. Evaluation of the impact of device-to-device (D2D) variation on performance.\n(a) The number of steps required for convergence under different D2D variation σ, calculated as the\naverage of five training runs. (b) The normalized reciprocal of the convergence steps, which serves as a\nproxy for training convergence speed. (c) The inference (testing) performance using weights converged\nunder different D2D variation σ. The results indicate that training can be successfully completed within\na D2D variation σ range of 0 to 0.5, with the only notable difference being a slight decrease in\nconvergence speed. The D2D variation is defined as follows: the weight update formula is given by Δw\n= Δw × α , where Δw represents the ideal update quantity, Δw is the actual update quantity, and\nideal D2D ideal\nα denotes the deviation introduced by D2D variation. Here, α follows a gaussian distribution: α\nD2D D2D D2D\n~ N (μ = 1, σ = σ ).\nD2D\nWe have made the following additions regarding D2D variation to the revised main text\nin page 13:\n“Even in the presence of a certain degree of D2D variation or noise variation, the\nnetwork remains capable of successful convergence, exhibiting a slight reduction in\nconvergence speed (Supplementary Fig. 25 and Supplementary Fig. 26). This\ndemonstrates the strong redundancy capability of In Se FeS-FET based RL neural\n2 3\nnetwork. This is attributed to the closed-loop nature of in-situ training, where the\niterative weight updates dynamically compensate for static device errors. Consequently,\nthe algorithm automatically adjusts the number of update steps to reach the target\nconductance, effectively mitigating the impact of individual device variability53-58.”\nReferences:\nR1 Burr, Geoffrey W., et al. \"Neuromorphic computing using non-volatile memory.\" Advances in Physics:\nX 2.1 (2017): 89-124.\nR2 Ambrogio, Stefano, et al. \"Equivalent-accuracy accelerated neural-network training using analogue\nmemory.\" Nature 558.7708 (2018): 60-67.\nR3 Yao, Peng, et al. \"Face classification using electronic synapses.\" Nature communications 8.1 (2017):\n15199.\nR4 Li, Can, et al. \"Efficient and self-adaptive in-situ learning in multilayer memristor neural\nnetworks.\" Nature communications 9.1 (2018): 2385.\nR5 Querlioz, Damien, et al. \"Immunity to device variations in a spiking neural network with memristive\nnanodevices.\" IEEE transactions on nanotechnology 12.3 (2013): 288-295.\nR6 Ly, Denys RB, et al. \"Role of synaptic variability in resistive memory-based spiking neural networks\nwith unsupervised learning.\" Journal of Physics D: Applied Physics 51.44 (2018): 444002.\nReviewer #2 (Remarks to the Author):\nThis study demonstrates a brain-inspired spiking neural network (SNN)-based\nreinforcement learning (RL) computing architecture utilizing α-In Se ferroelectric\n2 3\nsemiconductor field-effect transistors (FeS-FETs). Specifically, an autonomous\ndriving task is implemented using an RL neural network constructed from an α-In Se\n2 3\narray. While the integration of α-In Se FeS-FETs into an RL framework is conceptually\n2 3\nintriguing, the manuscript suffers from insufficient novelty, inadequate mechanistic\nexplanations, and unresolved practical challenges in device uniformity and system-\nlevel implementation.\nResponse: We appreciate the reviewer’s time in reviewing the manuscript.\nReinforcement learning (RL) is currently a key approach for enhancing the performance\nof large language models and holds promise for achieving true artificial general\nintelligence (AGI). Mimicking biological neuronal learning strategies, this work fully\nutilizes the In Se FeS-FET's in-plane and out-of-plane polarization modulation\n2 3\ncapabilities. For the first time, it implements the complete R-STDP synaptic function\nwithin a single device, requiring no additional circuitry. This constructs an SNN-based\nspiking reinforcement learning neural network, filling a critical hardware gap for SNN-\nbased RL. Concurrently, this work uses a single transistor to achieve an eligibility trace\neffect with an adjustable decay rate, which enhances the RL algorithm's performance\nand its generalization capability; this eligibility trace scheme is also applicable to other\nRL algorithms (such as SARSA, DQN, etc.). The proposed RL synapse reduces the\nhardware overhead by tens of times compared to existing schemes.\nFurthermore, to validate the scheme's feasibility, we fabricated a 6×8 array and a\nperipheral PCB operating circuit, providing a system-level verification of the scheme's\nviability and realizing a novel neuromorphic hardware system (Please refer to the\nResponse to Comment 2 for Reviewer #1 and Supplementary Fig. 16).\nRegarding device uniformity, our evaluation demonstrates that even under a certain\ndegree of device-to-device (D2D) variation, the network successfully converges\nwithout any degradation in inference performance, exhibiting only a minor reduction\nin convergence speed (Please refer to the Response to major concerns 3 and\nSupplementary Fig. 25). This indicates that the proposed scheme possesses robustness\nagainst variation. Previous studies have established that in-situ training schemes\npossess an inherent resilience to device non-idealities R1, R2. Unlike ex-situ weight\nmapping, where device variations lead to direct inference errors, the iterative nature of\non-line learning allows the system to compensate for static D2D variation by\ndynamically adjusting the number of update stepsR3, R4. Specifically, Querlioz et al. and\nLy et al. demonstrated that SNNs trained with STDP can tolerate parameter variability\nas high as 50% without significant performance degradationR5, R6, which aligns with our\nexperimental observations.\nUndoubtedly, research into spiking RL is still in its nascent stages; therefore, achieving\na small-scale, system-level hardware solution with co-optimization between the device\nand the algorithm represents a significant advancement. Specifically, the main\ninnovations and contributions of this manuscript are as follows:\n1. In-situ weight update by couple tuning of IP and OOP polarization in. By\nleveraging the intrinsic in-plane and out-of-plane polarization coupling of α-\nIn2Se3, the multi-terminal conductance modulation in the FeS-FET enables\nreward signal modulation of RL, no feedback learning circuit required.\n2. Highly efficient biological eligibility trace implementation with tunable decay\nconstant. Ferroelectric relaxation is used to implement biological eligibility\ntrace decay, enabling tunable decay speed with a single pulse, significantly\nreducing the hardware cost of implementing eligibility trace.\n3. All-in-one-device design. The three-step complex computational processes—\nSTDP, eligibility trace decay, and reward signal modulation—are all\naccomplished through the intrinsic physical processes within the device. The\nproposed RL synapse reduces the hardware overhead by tens of times compared\nto existing schemes.\n4. Small-scale system-level hardware validation: We fabricated a 6×8 array and\ndesigned a supporting PCB circuit system to verify its feasibility. Although the\ndevices within the array exhibit a certain degree of variation, the network's\ninherent redundancy, as designed, completely mitigates this issue, having no\nimpact on its practical application performance.\nReferences:\nR1 Burr, Geoffrey W., et al. \"Neuromorphic computing using non-volatile memory.\" Advances in Physics:\nX 2.1 (2017): 89-124.\nR2 Ambrogio, Stefano, et al. \"Equivalent-accuracy accelerated neural-network training using analogue\nmemory.\" Nature 558.7708 (2018): 60-67.\nR3 Yao, Peng, et al. \"Face classification using electronic synapses.\" Nature communications 8.1 (2017):\n15199.\nR4 Li, Can, et al. \"Efficient and self-adaptive in-situ learning in multilayer memristor neural\nnetworks.\" Nature communications 9.1 (2018): 2385.\nR5 Querlioz, Damien, et al. \"Immunity to device variations in a spiking neural network with memristive\nnanodevices.\" IEEE transactions on nanotechnology 12.3 (2013): 288-295.\nR6 Ly, Denys RB, et al. \"Role of synaptic variability in resistive memory-based spiking neural networks\nwith unsupervised learning.\" Journal of Physics D: Applied Physics 51.44 (2018): 444002.\nConsequently, the conclusions drawn appear premature, necessitating further extensive\nresearch to validate the practical applicability and value of artificial neurons with\nspatiotemporal specificity. For these reasons, the reviewer does not recommend\npublishing this manuscript in Nature Communications, as outlined by the major\ncritiques below (though not exhaustively).\nResponse: We appreciate the reviewer’s valuable comment regarding the validation of\npractical applicability. Regarding the mention of 'artificial neurons,' we would like to\nrespectfully clarify that the In Se FeS-FET devices in this work are engineered to\n2 3\nfunction as artificial synapses rather than neurons. Their primary role is to emulate\nsynaptic plasticity and the associated eligibility traces (spatiotemporal synaptic\ndynamics) within the SNN architecture. We have validated the practical value of these\nsynaptic components through the system-level autonomous driving task.\nMajor Concerns:\n1、The manuscript fails to demonstrate significant innovation. The utilization of α-\nIn2Se3's in-plane (IP) and out-of-plane (OOP) ferroelectric polarization coupling for\nthird-terminal synaptic plasticity and reward-modulated spiking reinforcement\nlearning (RL) has been extensively reported in prior studies (e.g., ACS Nano 2025, 19,\n13, 13287–13299). The proposed physical mechanisms and application scenarios (e.g.,\nautonomous driving) largely overlap with existing literature, without introducing new\ninsights or methodologies. Furthermore, the synaptic device performance (e.g.,\nconductance modulation range, cycling endurance) shows no breakthrough compared\nto state-of-the-art ferroelectric transistors.\nResponse: We thank the reviewer for providing the important paper. In the revised\nmanuscript, we cite the paper (ACS Nano 2025, 19, 13, 13287–13299) as ref. 40.\nThe ref. 40 has conducted a series of studies on neuromorphic and logic computing\nusing MoS₂/In₂Se₃/h-BN transistors, demonstrating several innovation points. In\ncontrast, the present work differs from that study in multiple aspects and possesses\ndistinct and significant originality of its own. A detailed justification is provided below:\n1. Regarding the novelty of the content, we utilized a three-terminal tunable FeS-FET\nto implement a complete spiking reinforcement learning (R-STDP) algorithm. This\nrepresents a fundamental difference in innovation compared to the ref. 40 study,\nwhich did not involve reinforcement learning. The ref. 40 primarily utilizes the out-\nof-plane (OOP) polarization of In₂Se₃ to modulate the carrier distribution in MoS₂,\nthereby tuning the device conductivity. In contrast, the present work employs both\nin-plane (IP) and out-of-plane (OOP) polarizations, achieving conductivity\nmodulation through their combined effects. Moreover, while the ref. 40 study relies\non a vertically stacked heterostructure composed of MoS₂/In₂Se₃/h-BN, our work\nrealizes the full functionality using only the In₂Se₃ channel material, resulting in a\nsignificantly simpler device architecture.\n2. In terms of the utilization of physical mechanisms, the eligibility trace decay is\nimplemented through ferroelectric polarization relaxation. By modulating pulse\nschemes, the decay constant can be further tuned to optimize learning performance\nand enhance system adaptability across diverse scenarios. These critical features\nare absent in ref. 40.\nAs a widely used concept in RL, eligibility trace can effectively improve learning\nefficiency and have been validated in biological systems (ref. 4, ref. 46-48).\nHowever, on CMOS-based or NVMs-based computing platforms (ref. 14, ref. 16,\nref. 24, ref. 49), implementing exponentially decaying eligibility traces requires\nsignificant hardware overhead (For example, in Fig. 1b, multiple PCMs in parallel\nare required to utilize their resistance drift to achieve the eligibility trace).\nFurthermore, it is also difficult for charge-trapping memories to realize a decaying\ntrace via simple pulse modulation. In this work, we leverage ferroelectric relaxation\nto naturally achieve eligibility trace decay with tunable relaxation time.\n3. At the level of algorithmic and neural network applications, the ref. 40 demonstrates\napplications in fully connected neural networks (FCNNs) and classification tasks\nusing a spiking neural network (SNN) based on the spike-timing-dependent\nplasticity (STDP) algorithm, as well as emulation of sea-slug locomotion behavior\nand logic computing functionalities. In contrast, the present work focuses on\nspiking RL and, for the first time, proposes a comprehensive synaptic hardware\nframework for spiking RL—incorporating STDP behavior, reward modulation, and\neligibility trace decay mechanisms.\nAt the SNN level, the ref. 40 implements only the most basic form of unsupervised\nlearning via the STDP algorithm. Due to the limited learning capabilities of current\nunsupervised methods, the demonstrated tasks are restricted to simple clustering\nproblems (entry-level datasets such as Fisher’s Iris). In comparison, our work\nrealizes the reward-modulated STDP (R-STDP) algorithm within a spiking RL\nframework, enabling the execution of more complex and higher-level tasks such as\nautonomous driving and robotic control.\nIn terms of network scale and task complexity, the ref. 40 utilizes a 784×150×10\nFCNN (fully simulated) to perform MNIST digit recognition, whereas our\napproach achieves autonomous driving functionality with a compact 18×2 SNN\narchitecture, highlighting the efficiency and task applicability of the proposed\nsystem.\n4. At the physical mechanism level, our work fully exploits both the in-plane (IP) and\nout-of-plane (OOP) polarizations of In₂Se₃. A systematic investigation was\nconducted to evaluate the effects of IP and OOP polarization on conductance\nmodulation, both individually and in combination, through comprehensive DC and\npulsed measurements. This level of detailed and integrative analysis is lacking in\nthe existing literatureR1, R2 (including ref. 40).\nThe RL-based autonomous driving framework proposed in this work differs from most\nexisting approaches, which are predominantly based on convolutional neural networks\n(CNNs)R3, R4. Unlike supervised learning methods that rely on labeled datasets, RL does\nnot require annotated training data, thereby significantly reducing training costs.\nMoreover, due to its inherent adaptability to open-ended tasks, RL enables the model\nto optimize its behavior in real time based on environmental feedback. As a result, the\nproposed approach also offers advantages in model transferability across different\nscenarios without the need to prepare new datasets.\nOur synaptic device performance exhibits a substantial enhancement when compared\nhorizontally with synapses from other similar reinforcement learning schemes.\nRegarding the issue of state-of-the-art ferroelectric transistors, its performance is also\noptimized relative to other previously reported In₂Se₃-based synaptic devices. We have\nupdated Supplementary Table 1 and added Supplementary Table 2 to the revised SI.\nSupplementary Table 1. Comparison of R-STDP synapse implementation by different hardware.\nRef. [R5] [R6] [R7] [R8] [R9] [R10] [R11] This work\nFPGA (7 MUX+\n3 1 PCM+ 2 FeFET+ 16 MOSFET+ 8 Logic gates+ 1 FE capacitor+ 1 InSe FeS-\n2 3\nHardware 1 Adder+\nPCMs TIA 1 Selector 3 Capacitors 3 Flip-Flop 1 MOSFET FET\nR-STDP √ × √ √ √ √ × √\nEligibility\n~6 s ~300 ms × ~100 ms × × ~3 s ~28~189 ms\ntrace\nWeight\nNO 2~25 μS 0.8~26 nS N/A N/A N/A NO 0.68~17.5 nS\nrange\n2\n0.5 mm\nμm2\nTIA)\n277.5\nEnergy 860 pJ 64 pJ 2.2 nJ 1.78 μJ 351 pJ 3.75 nJ 65 pJ\npJ\nSupplementary Table 1. Comparison of In₂Se₃-based synaptic devices.\nRef. [R12] [R13] [R14] [R15] This work\nOOP √ √ × × √\nIP × × √ √ √\n0.85-2.5 μS 0.5~3.6 nS 140~290 pS 0.82-1.55 nS 0.68~17.5 nS\nWeight range\n5 bits 4 bits 3 bits 3 bits 5 bits\nOOP energy 3 pJ 8 pJ × × 0.57 pJ\nIP energy × × 607 pJ 480 pJ 65 pJ\nWe have concurrently made the following revisions to page 10 of the main text:\n“Supplementary Table 1 summarizes the comparison of R-STDP implementation\nby different hardware. Compared to systems that incur higher hardware costs and only\npartially implement R-STDP functions (synaptic weights, eligibility traces, and reward\nsignals), this work integrates all R-STDP functionalities into a single α-In Se FeS-FET,\n2 3\nenabling in-situ weight updates and incorporating tunable eligibility traces. Our\napproach reduces the hardware complexity by a factor of several times. This learning\nrule is realized by our FeS-FET with about 10 µm2 footprint. Furthermore, it exhibits\nlow operating energy consumption, approximately 65 pJ per R-STDP event (Fig. 1),\ndemonstrating a significant advantage over comparable devices (Fig. 1). Therefore, it\nindicates the significant predominance in area, energy and hardware cost of the\nhardware SNN system for RL. Supplementary Table 2 summarizes α-In Se -based\n2 3\nsynaptic devices. The R-STDP synapse presented in this work exhibits distinct\nadvantages in terms of joint IP and OOP modulation, conductance range, and energy\nconsumption.”\nReferences:\nR1 Liu, Keqin, et al. \"An optoelectronic synapse based on α-In2Se3 with controllable temporal dynamics\nfor multimode and multiscale reservoir computing.\" Nature Electronics 5.11 (2022): 761-773.\nR2 Liao, Junyi, et al. \"Van der waals ferroelectric semiconductor field effect transistor for in-memory\ncomputing.\" ACS nano 17.6 (2023): 6095-6102.\nR3 Yadav, Vivek, et al. \"Site-specific substitution in atomically precise carboranethiol-protected\nnanoclusters and concomitant changes in electronic properties.\" Nature Communications 16.1 (2025):\n1197.\nR4 Zhang, Sen, et al. \"Rational design of a vision fusion system with visible and near-infrared spectral\nintegration for improved environmental perception.\" National Science Review 12.7 (2025): nwaf204.\nR5 Demirağ, Yiğit, et al. \"PCM-trace: scalable synaptic eligibility traces with resistivity drift of phase-\nchange materials.\" 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021.\nR6 Lu, Yingming, et al. \"In‐memory realization of eligibility traces based on conductance drift of phase\nchange memory for energy‐efficient reinforcement learning.\" Advanced Materials 34.6 (2022): 2107811.\nR7 Zhou, Yue, et al. \"A reconfigurable two‐WSe2‐transistor synaptic cell for reinforcement\nlearning.\" Advanced Materials 34.48 (2022): 2107754.\nR8 Wang, Haibing, et al. \"TripleBrain: A compact neuromorphic hardware core with fast on-chip self-\norganizing and reinforcement spike-timing dependent plasticity.\" IEEE Transactions on Biomedical\nCircuits and Systems 16.4 (2022): 636-650.\nR9 Amirshahi, Alireza, and Matin Hashemi. \"ECG classification algorithm based on STDP and R-STDP\nneural networks for real-time monitoring on ultra low-power personal wearable devices.\" IEEE\ntransactions on biomedical circuits and systems 13.6 (2019): 1483-1493.\nR10 Nair, Harideep, John Paul Shen, and James E. Smith. \"A microarchitecture implementation\nframework for online learning with temporal neural networks.\" 2021 IEEE Computer Society Annual\nSymposium on VLSI (ISVLSI). IEEE, 2021.\nR11 Luo, Jin, et al. \"Energy-efficient ferroelectric-FET-based agent with memory trace for enhanced\nreinforcement learning.\" IEEE Electron Device Letters 45.2 (2023): 264-267.\nR12 Wang, Lin, et al. \"Exploring ferroelectric switching in α‐In2Se3 for neuromorphic\ncomputing.\" Advanced Functional Materials 30.45 (2020): 2004609.\nR13 Liu, Keqin, et al. \"Multilayer reservoir computing based on ferroelectric α‐In2Se3 for hierarchical\ninformation processing.\" Advanced Materials 34.48 (2022): 2108826.\nR14 Guo, Feng, et al. \"Achieving reinforcement learning in a three-active-terminal neuromorphic device\nbased on a 2D vdW ferroelectric material.\" Materials horizons 10.9 (2023): 3719-3728.\nR15 Liu, Keqin, et al. \"An optoelectronic synapse based on α-In2Se3 with controllable temporal\ndynamics for multimode and multiscale reservoir computing.\" Nature Electronics 5.11 (2022): 761-773.\n2、Eligibility Trace (ET) Implementation: The authors attribute ET decay to\nferroelectric polarization relaxation caused by depolarization fields. However,\ndepolarization-induced relaxation is typically an undesirable property in ferroelectric\ndevices, and its controllability/consistency remains unproven. The manuscript merely\nstates that \"current relaxation aligns with ET decay\" without clarifying the quantitative\ncorrelation between polarization dynamics and algorithmic parameters (e.g., decay\ntime constants, causality principles). Additional evidence, such as direct measurements\nof polarization relaxation kinetics and their mathematical mapping to ET decay,\nis required.\nResponse: We thank the reviewer for their suggestion regarding the eligibility trace\n(ET). Ferroelectric polarization relaxation is commonly regarded as an undesirable\neffect. However, in this work, it is ingeniously harnessed by drawing inspiration from\nthe biological mechanism of ET decay. By mapping ferroelectric relaxation to ET decay,\nthe system effectively enhances the performance of reinforcement learning algorithms.\nImplementing the exponential decay of ET using conventional complementary metal-\noxide-semiconductor (CMOS) technology typically requires analog circuits comprising\ndozens of componentsR1, R2, R3. Similarly, non-volatile memory (NVM)-based\napproaches, such as conductance drift in phase-change memory (PCM), often rely on\nmultiple parallel PCM devices and additional synaptic weight unitsR4, R5. In contrast,\nour work achieves the eligibility trace functionality using only a single In₂Se₃\nferroelectric semiconductor field-effect transistor (FeS-FET), offering substantial\nsimplicity and practical advantages.\nAlthough ferroelectric polarization relaxation is often considered a non-ideal effect,\nnumerous recent studies have demonstrated its utility in enabling complex\ncomputational functionalities, such as reservoir computing R6, R7 and associative\nlearningR8. In these works, polarization relaxation plays a crucial and constructive role.\nTherefore, ferroelectric relaxation should not be viewed solely as a detrimental\nphenomenon, but rather as a physical mechanism with valuable potential for\nneuromorphic and unconventional computing applications. Moreover, the\ncontrollability of ferroelectric relaxation has also been reported in the literatureR6, R9,\nfurther expanding the potential of leveraging relaxation dynamics for complex\ncomputational modeling and neuromorphic applications.\nIn order to make the point clearer, we made revisions as follows in Page 10:\n“While often considered a non-ideal effect, ferroelectric polarization relaxation\nhas been successfully exploited in recent studies to enable complex functionalities such\nas reservoir computing36, 37 and associative learning50. Rather than a detriment,\nrelaxation serves as a valuable, controllable mechanism36, 51 for neuromorphic and\nunconventional computing. In this work, we leverage ferroelectric relaxation to\nnaturally achieve eligibility trace decay with tunable relaxation time.”\nNext, Supplementary Fig.12 demonstrated the controllability of depolarization-\ninduced relaxation through electrical pulse shapes and durations. For the mathematical\nconsistency between ET decay and the ferroelectric relaxation dynamics, we have\nupdated Supplementary Fig. 12 to the revised SI. Supplementary Note 2 have\nprovided more detailed data to demonstrate that the observed current relaxation aligns\nwell with the expected ET decay behavior, along with the corresponding mathematical\nmapping to support this correlation.\nSupplementary Fig. 12. Tunable relaxation time constant. Relaxation time and the corresponding fitted\ncurve under different pulse amplitudes (a) and widths (b). Relaxation time comparison (c). The results\nshow that pulse width has no effect on relaxation time τ. The larger the pulse amplitude, the longer the\nrelaxation time.\nWe have added Supplementary Note 2 in the revised SI to provide a mathematical\nanalysis of the physical model regarding the eligibility trace and ferroelectric relaxation.\n“Supplementary Note 2：Mathematical analysis of the physical process of\nferroelectric relaxation and its mathematical mapping relationship to the eligibility\ntrace. Supplementary Fig.12 presents the current relaxation process along with the\ncorresponding fitted curve. The fitting equation is given as follows:\n(cid:3047)\n𝐼 (𝑡) =𝐼 𝑒(cid:2879) (cid:3099) (1)\n(cid:3005)(cid:3020) (cid:2868)\nWhere 𝐼 is the initial current value and 𝜏 is the relaxation time constant.\n(cid:2868)\nThe definition of eligibility trace is as followsR10, R11:\n𝑑𝑒(𝑡) 1\n= − 𝑒(𝑡)+𝑆(𝑡) (2)\n𝑑𝑡 𝜏\n(cid:3032)\nWhere 𝜏 is the decay time constant of the eligibility trace, 𝑆(𝑡) represents the input\n(cid:3032)\npulse or trigger event, assuming an input pulse occurs at time 𝑡 :\n(cid:2868)\n𝑆(𝑡) =𝛿(𝑡−𝑡 ) (3)\n(cid:2868)\nThen there is:\n(cid:2879)\n(cid:3047)(cid:2879)(cid:3047)(cid:3116)\n𝑒(𝑡) = 𝑒\n(cid:2868) \n∙𝑒 (cid:3099)(cid:3280) (4)\nTherefore, the current decay induced by ferroelectric relaxation (as described in\nEquation 1) is consistent with the decay behavior defined in the eligibility trace\n(Equation 4), enabling a direct and complete functional mapping between the two.\nThe ferroelectric polarization relaxation dynamics induced by the depolarization field\ncan be analyzed using the following equationR12, R13, R14:\n(cid:3047) (cid:3289)\n(cid:2879)(cid:4672) (cid:4673)\n𝑃(𝑡) = 𝑃\n(cid:2868) \n∙𝑒 (cid:3099)(cid:3277)(cid:3294) (5)\nwhere 𝑃 represents the value of the initial polarization before depolarizing, 𝜏 is\n(cid:2868) (cid:3029)(cid:3046)\nthe characteristic time of back switching (depolarizing), and 𝑛 is the stretched\nexponent.\nTherefore, the ferroelectric relaxation dynamics (Equation 5), the resulting current\ndecay (Equation 1), and the mathematically defined decay of eligibility trace (Equation\n4) share the same exponential form. This intrinsic consistency enables the In₂Se₃ FeS-\nFET to serve as an ideal physical substrate for implementing the eligibility trace\nfunction.”\nReferences:\nR1 Nair, Harideep, John Paul Shen, and James E. Smith. \"A microarchitecture implementation\nframework for online learning with temporal neural networks.\" 2021 IEEE Computer Society Annual\nSymposium on VLSI (ISVLSI). IEEE, 2021.\nR2 Amirshahi, Alireza, and Matin Hashemi. \"ECG classification algorithm based on STDP and R-STDP\nneural networks for real-time monitoring on ultra low-power personal wearable devices.\" IEEE\ntransactions on biomedical circuits and systems 13.6 (2019): 1483-1502.\nR3 Rubino, Arianna, Melika Payvand, and Giacomo Indiveri. \"Ultra-low power silicon neuron circuit\nfor extreme-edge neuromorphic intelligence.\" 2019 26th IEEE International Conference on Electronics,\nCircuits and Systems (ICECS). IEEE, 2019.\nR4 Lu, Yingming, et al. \"In‐memory realization of eligibility traces based on conductance drift of phase\nchange memory for energy‐efficient reinforcement learning.\" Advanced Materials 34.6 (2022): 2107811.\nR5 Demirağ, Yiğit, et al. \"PCM-trace: scalable synaptic eligibility traces with resistivity drift of phase-\nchange materials.\" 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021.\nR6 Liu, Keqin, et al. \"An optoelectronic synapse based on α-In2Se3 with controllable temporal dynamics\nfor multimode and multiscale reservoir computing.\" Nature Electronics 5.11 (2022): 761-773.\nR7 Liu, Keqin, et al. \"Multilayer reservoir computing based on ferroelectric α‐In2Se3 for hierarchical\ninformation processing.\" Advanced Materials 34.48 (2022): 2108826.\nR8 Yan, Mengge, et al. \"Ferroelectric synaptic transistor network for associative memory.\" Advanced\nElectronic Materials 7.4 (2021): 2001276.\nR9 Kim, D. J., et al. \"Polarization Relaxation Induced by a Depolarization Field<? format?> in Ultrathin\nFerroelectric BaTiO 3 Capacitors.\" Physical review letters 95.23 (2005): 237602.\nR10 Frémaux, Nicolas, and Wulfram Gerstner. \"Neuromodulated spike-timing-dependent plasticity, and\ntheory of three-factor learning rules.\" Frontiers in neural circuits 9 (2016): 85.\nR11 Florian, Răzvan V. \"Reinforcement learning through modulation of spike-timing-dependent synaptic\nplasticity.\" Neural computation 19.6 (2007): 1468-1502.\nR12 Li, X., A. Mamchik, and I-W. Chen. \"Stability of electrodeless ferroelectric domains near a\nferroelectric/dielectric interface.\" Applied Physics Letters 79.6 (2001): 809-811.\nR13 Gruverman, Alexei, et al. \"Nanoscale imaging of domain dynamics and retention in ferroelectric\nthin films.\" Applied Physics Letters 71.24 (1997): 3492-3494.\nR14 Fu, Desheng, et al. \"Dynamics of nanoscale polarization backswitching in tetragonal lead zirconate\ntitanate thin film.\" Applied physics letters 82.13 (2003): 2130-2132.\n3、R-STDP Uniformity: The R-STDP curves in Fig. 4c exhibit poor uniformity, with\nweight changes ranging from 12% to 26% at a 50 ms time interval. This raises concerns\nabout the feasibility of reliable in-situ training in a 36-device array (Supplementary\nFig. 16), where significant variations in threshold voltages, memory windows, and\nIDVD、IDVG characteristics are observed.\nResponse: We thank the reviewer for the discussion regarding device-to-device (D2D)\nvariation. We have incorporated Supplementary Fig.25 into the revised SI to evaluate\nD2D variation. The results show that the network maintains robust convergence and\ninference capabilities within a σ range of 0 to 0.5, suffering only a slight penalty in\nconvergence rate. Given that the calculated average variation in Fig. 4c is σ = 0.36, and\nthe average variability for I -V and I -V in SI is about σ = 0.39, this degree of\nD D D G\nvariation does not hinder the learning process. This indicates that the proposed scheme\npossesses robustness against variation.\nPrevious studies have established that in-situ training schemes possess an inherent\nresilience to device non-idealities R1, R2. Unlike ex-situ weight mapping, where device\nvariations lead to direct inference errors, the iterative nature of on-line learning allows\nthe system to compensate for static D2D variation by dynamically adjusting the number\nof update stepsR3, R4. Specifically, Querlioz et al. and Ly et al. demonstrated that SNNs\ntrained with STDP can tolerate parameter variability as high as 50% without significant\nperformance degradationR5, R6, which aligns with our experimental observations.\nSupplementary Fig.25. Evaluation of the impact of device-to-device (D2D) variation on performance.\n(a) The number of steps required for convergence under different D2D variation σ, calculated as the\naverage of five training runs. (b) The normalized reciprocal of the convergence steps, which serves as a\nproxy for training convergence speed. (c) The inference (testing) performance using weights converged\nunder different D2D variation σ. The results indicate that training can be successfully completed within\na D2D variation σ range of 0 to 0.5, with the only notable difference being a slight decrease in\nconvergence speed. The D2D variation is defined as follows: the weight update formula is given by Δw\n= Δw × α, where Δw represents the ideal update quantity, Δw is the actual update quantity, and α\nideal ideal\ndenotes the deviation introduced by D2D variation. Here, α follows a gaussian distribution: α ~ N (μ =\n1, σ = σ ).\nD2D\nWe have made the following additions regarding D2D variation to the revised main text\nin page 13:\n“Even in the presence of a certain degree of D2D variation or noise variation, the\nnetwork remains capable of successful convergence, exhibiting a slight reduction in\nconvergence speed (Supplementary Fig. 25 and Supplementary Fig. 26). This\ndemonstrates the strong redundancy capability of In Se FeS-FET based RL neural\n2 3\nnetwork. This is attributed to the closed-loop nature of in-situ training, where the\niterative weight updates dynamically compensate for static device errors. Consequently,\nthe algorithm automatically adjusts the number of update steps to reach the target\nconductance, effectively mitigating the impact of individual device variability53-58.”\nReferences:\nR1 Burr, Geoffrey W., et al. \"Neuromorphic computing using non-volatile memory.\" Advances in Physics:\nX 2.1 (2017): 89-124.\nR2 Ambrogio, Stefano, et al. \"Equivalent-accuracy accelerated neural-network training using analogue\nmemory.\" Nature 558.7708 (2018): 60-67.\nR3 Yao, Peng, et al. \"Face classification using electronic synapses.\" Nature communications 8.1 (2017):\n15199.\nR4 Li, Can, et al. \"Efficient and self-adaptive in-situ learning in multilayer memristor neural\nnetworks.\" Nature communications 9.1 (2018): 2385.\nR5 Querlioz, Damien, et al. \"Immunity to device variations in a spiking neural network with memristive\nnanodevices.\" IEEE transactions on nanotechnology 12.3 (2013): 288-295.\nR6 Ly, Denys RB, et al. \"Role of synaptic variability in resistive memory-based spiking neural networks\nwith unsupervised learning.\" Journal of Physics D: Applied Physics 51.44 (2018): 444002.\n4、Neural Network Implementation: The autonomous driving task (Fig. 4a) lacks\ncritical details. For instance:\nHow are the 18 input neurons interfaced with the 3×6 pixel grid?\nHow are reward signals selectively applied to specific synapses without unintended\nweight updates in adjacent devices (e.g., column-wise crosstalk during VGS\nmodulation)?\nThe absence of crossbar addressing schemes (e.g., read/write voltages, line resistance\neffects) in the 6×8 array (Fig. 4b) undermines the practical viability of the proposed\narchitecture.\nResponse: We sincerely thank the reviewer for the insightful comments regarding the\nimplementation details of the neural network. The input compressed 3×6 pixels images\n(adopted from ref. 52) are encoded into spike trains based on pulse count and then fed\ninto the corresponding 18 input neurons. Since a dynamic vision sensor (DVS) is used\nto capture the images, it responds only to changes in light intensity and remains inactive\nfor static information. As a result, the acquired images consist of three distinct states:\nunchanged intensity (represented by gray pixels), decreasing intensity (black pixels),\nand increasing intensity (white pixels). These “black-gray-white” states are ultimately\nencoded into spike trains with different pulse counts, which are then used to stimulate\nthe 18 input neurons. We have added a corresponding description on page 11 of the\nrevised main text:\n“The lane scene captured by the vehicle's camera is compressed into a 3×6 pixels\nformat 52, where each pixel is encoded by pulse count to generate 18 pulse sequences\nthat are separately input to 18 input neurons of the spiking RL neural network\nconnected by R-STDP synapses.”\nWe have also updated Fig. 4a to make it clearer:\nFig. 4. In Se FeS-FET array for spiking RL neural network and application in lane keeping task\n2 3\nof autonomous driving. a, The schematic diagram of an autonomous driving scenario. The input image\nis compressed to a 3×6 format, which is encoded by pulse count and input to 18 input neurons. Two\noutput neurons control the left and right directions, respectively. The neurons are connected through R-\nSTDP synapses.\nAs shown in Fig. R2, the 6×8 array adopts a bottom-gate layout. Each column of\ndevices shares a common gate electrode line, while each row shares a common source\nelectrode line. Each individual device has its own drain electrode. To apply a reward\nsignal (V ) to a selected device without affecting unselected ones, the target device\nGS\ncan be addressed through its corresponding row (source) and column (gate). The reward\nmodulation is achieved by applying the V signal between the selected gate and source\nGS\nlines. For other devices in the same column, since their source terminals are left floating,\nno electric field (E ) is established between gate and source, and thus no unintended\nGS\nmodulation occurs.\nFig. R2. The scanning electron microscope (SEM) image of the 6×8 array.\nWe also designed a PCB operating circuit for the 6×8 array, please refer to Response to\nComment 2 for Reviewer #1 and Supplementary Fig.16. Specifically, the cross-point\naddressing scheme is implemented via three switch matrices.\n5、PFM Data Quality: The piezoresponse force microscopy (PFM) phase and amplitude\nimages (Supplementary Fig. 2c,d) lack sufficient resolution and quantitative analysis,\ncasting doubt on the claimed IP/OOP polarization coupling.\nResponse: We thank the reviewer for their suggestion regarding image clarity. We have\nupdated Supplementary Fig.2 in the revised SI to provide clearer PFM images. Our\ncharacterization results indicate that In Se exhibits distinct in-plane and out-of-plane\n2 3\nferroelectric polarization, which is consistent with previously reported works (e.g., ref.\n36 and 37).\nSupplementary Fig.3. PFM measurement results of 𝛂-In\n3\n.The (a) topography, (b) OOP and (c) IP\nPFM phase images. Local ferroelectric switching loops of phase (d) and amplitude(e). These results show\nthe obvious OOP and IP ferroelectric polarization switching under external electric field.\n6、Relaxation Time Variability: The tunable relaxation time constants (28–189 ms) in\nFig. 3e-f are attributed to depolarization field sensitivity, but no direct evidence (e.g.,\nfield simulations, polarization hysteresis loops under varying VDS conditions) supports\nthis claim.\nResponse: We acknowledge the reviewer’s expertise and sharp observations,\nparticularly regarding the concerns on the variability of relaxation time. In this work,\nthe tunable relaxation time is achieved by applying pulses with different parameters\n(varying external electric fields), a concept that has been previously demonstrated in\nthe literature (ref. 36 and ref. 51), where the relaxation rate was shown to be modulated\nby the applied electric field. Specifically for In₂Se₃-based devices, previous studies (ref.\n36) have reported tunable relaxation behavior under different illumination and electric\nfield conditions, confirming the feasibility of controlling relaxation dynamics via\ndepolarization field variations. Therefore, the approach of achieving tunable relaxation\ntime through pulse-induced depolarization fields is well supported by prior work, and\nthe experimental results further validate its effectiveness.\nThe updated Supplementary Fig.12 in the revised SI directly demonstrates the tunable\nrelaxation speed under different pulse conditions, while Supplementary Note 2\nprovides a detailed mathematical analysis of this physical process.\nSupplementary Fig.12. Tunable relaxation time constant. Relaxation time and the corresponding fitted\ncurve under different pulse amplitudes (a) and widths (b). Relaxation time comparison (c). The results\nshow that pulse width has no effect on relaxation time τ. The larger the pulse amplitude, the longer the\nrelaxation time.\nIn order to make the point clearer, we made revisions as follows in Page 10:\n“While often considered a non-ideal effect, ferroelectric polarization relaxation\nhas been successfully exploited in recent studies to enable complex functionalities\nsuch as reservoir computing36, 37 and associative learning50. Rather than a detriment,\nrelaxation serves as a valuable, controllable mechanism36, 51 for neuromorphic and\nunconventional computing. In this work, we leverage ferroelectric relaxation to\nnaturally achieve eligibility trace decay with tunable relaxation time.”\nConcurrently, we have added hysteresis loops measured under different V voltages as\nDS\nSupplementary Fig.13 in the revised SI. The observed shifts in the hysteresis loops\nunder varying V demonstrate that V can influence the polarization hysteresis, a\nDS DS\nresult that is also consistent with previously reported literature (ref. 35 and 36).\nSupplementary Fig.12. Polarization hysteresis loops under different V .\nDS\nWe have made the following addition to the revised main text in page 12:\n“Fig. 3d indicates that the larger the amplitude (3~7 V), the greater the τ, while\nthe pulse width (7~15 ms) has no effect on τ. The differences observed in the hysteresis\nloops under different V demonstrate the influence of V on polarization and\nDS DS\nrelaxation (Supplementary Fig.13).”\nMinor Concerns:\nPage 6, Line 1: \"The hysteresis window is caused by IP and OOP polarization,\nrespectively\" → Ambiguous phrasing. Specify which hysteresis corresponds to\nIP/OOP polarization.\nResponse: Thank the reviewer for the comment. We have made the following\ncorrections to the revised main text to enhance the clarity of the description:\n“The hysteresis window is caused by IP (b) and OOP (c) polarization, respectively.”\nPage 9, Last line: \"the later the delayed reward signal\" → Replace \"later\" with\n\"longer delay of the reward signal\" for clarity.\nResponse: We thank the reviewer’s comment. We have made the following corrections\nto the revised main text to enhance the clarity of the description:\n“the longer delay of the reward signal,”\nFigure 4e: The y-axis label (\"distance from the lane center\") requires units.\nResponse: We appreciate the reviewer’s comment. The unit of the y-axis is meters, and\nwe have updated the Fig. 4e and f in the revised main text.\nReviewer #3 (Remarks to the Author):\nThis manuscript presents an interesting and original contribution, demonstrating a\nhardware implementation of a spiking neural network (SNN)-based reinforcement\nlearning (RL) algorithm using α-In₂Se₃ ferroelectric semiconductor field-effect\ntransistors (FeS-FETs) that exhibit both in-plane (IP) and out-of-plane (OOP)\npolarization coupling. The demonstration of three key brain-inspired functions—spike-\ntiming-dependent plasticity (STDP), eligibility traces, and reward modulation—adds\nsignificant novelty and depth to the study. The experimental results are convincing and\nwell-structured.\nResponse: We are grateful for the reviewer's positive assessment and recognition of\nthis work.\nThe manuscript merits consideration for publication after addressing the following\npoints of clarification:\nQuestion1: Material Thickness and Scalability: The devices are fabricated using\nexfoliated α-In₂Se₃ flakes with a relatively large thickness (~40 nm), which enables the\nobservation of ferroelectric hysteresis and resistive switching effects attributed to the\ninterplay between OOP and IP polarizations.\n(i) Have the authors systematically investigated how these two properties vary with\nflake thickness? A comparative analysis or discussion on thickness-dependent behavior\nwould enhance the understanding of the underlying mechanisms.\nResponse: We acknowledge the reviewer’s insightful comment regarding the\nscalability of material thickness. In fact, the relationship between α-In₂Se₃ thickness\nand its ferroelectric properties has been extensively studied in both theoretical and\nexperimental works. First-principles density functional theory (DFT) calculations have\npredicted the coexistence of IP and OOP ferroelectricity in monolayer α-In₂Se₃R1. On\nthe experimental side, ferroelectricity has been confirmed in monolayer α-In₂Se₃R2, R3.\nThe asymmetric bonding configuration breaks the structural symmetry of monolayer α-\nIn₂Se₃ in both IP and OOP directions, resulting in coupled ferroelectric polarization in\nthese two directions.\nIn multilayer α-In₂Se₃, the directions of the IP polarization of adjacent layers are the\nsame for the 3R stacking sequence but opposite for the 2H stacking sequence. As such,\nthe IP and OOP polarizations are preserved in multilayer α-In₂Se₃ with a 3R stacking\nsequenceR3, R4. For 2H-α-In₂Se₃, the total IP polarization depends on the number of\nlayers. Both theoretical calculations and experiments have demonstrated that odd-\nnumbered layers of the 2H phase exhibit distinct IP and OOP polarization, whereas the\npolarization in even-numbered layers is negligibleR2, R4, R5.\nThese results suggest that α-In₂Se₃ offers strong potential for scaling, maintaining\nrobust ferroelectric and resistive switching behavior down to few-layer or even\nmonolayer regimes, thus enabling further miniaturization of neuromorphic hardware.\nReferences:\nR1 Ding, Wenjun, et al. \"Prediction of intrinsic two-dimensional ferroelectrics in In2Se3 and other III2-\nVI3 van der Waals materials.\" Nature communications 8.1 (2017): 14956.\nR2 Cui, Chaojie, et al. \"Intercorrelated in-plane and out-of-plane ferroelectricity in ultrathin two-\ndimensional layered semiconductor In2Se3.\" Nano letters 18.2 (2018): 1253-1258.\nR3 Xiao, Jun, et al. \"Intrinsic two-dimensional ferroelectricity with dipole locking.\" Physical review\nletters 120.22 (2018): 227601.\nR4 Liu, Lixuan, et al. \"Atomically resolving polymorphs and crystal structures of In2Se3.\" Chemistry of\nMaterials 31.24 (2019): 10143-10149.\nR5 Lv, Baohua, et al. \"Layer-dependent ferroelectricity in 2H-stacked few-layer α-In 2 Se 3.\" Materials\nHorizons 8.5 (2021): 1472-1480.\n(ii) Given that mechanical exfoliation is not scalable for large-scale integration, the\nauthors should comment on the feasibility of synthesizing α-In₂Se₃ via wafer-scale\ntechniques such as chemical vapor deposition (CVD), and address potential constraints\nrelated to integration on standard silicon substrates.\nResponse: We agree with the reviewer’s comment regarding the importance of large-\nscale integration. Mechanical exfoliation is indeed suitable only for the preparation of\na limited number of devices, and the development of scalable, high-quality growth\ntechniques is essential for future integration and compatibility with silicon-based\nplatforms. In this work, the ~100(cid:3031)μm α-In₂Se₃ flakes used were synthesized via a flux-\nassisted growth (FAG) method, which enables relatively uniform and stable thin films.\nIn addition, recent literature has demonstrated the growth of large-area β'-In₂Se₃ films\nusing chemical vapor deposition (CVD). The metastable β' phase can be converted into\nthe more stable α phase by strain releaseR1. This approach has yielded centimeter-scale\nhigh-quality films, and with further optimization of the growth process, wafer-scale\nfabrication of α-In₂Se₃ is feasible in the future.\nCurrently, the integration of two-dimensional α-In₂Se₃ materials with silicon-based\ntechnology faces several potential limitations. These include challenges in achieving\nwafer-scale uniform growth with precise thickness control, maintaining stable\nferroelectric properties during high-temperature CMOS processing, and ensuring low-\ncontact resistance and reliable interfaces with silicon substrates. Overcoming these\nbarriers will require further advances in material synthesis, interface engineering, and\nprocess compatibility. At the same time, more mature 2D materials such as MoS₂ and\nWSe₂, which have already demonstrated a certain degree of large-scale integration and\ncompatibility with silicon-based processes, can serve as valuable references for the\nfuture development of α-In₂Se₃ integration. Leveraging insights from these materials\nmay help accelerate the advancement of scalable growth techniques and device\nfabrication strategies for α-In₂Se₃ in neuromorphic applications.\nReferences:\nR1 Han, Wei, et al. \"Phase-controllable large-area two-dimensional In2Se3 and ferroelectric heterophase\njunction.\" Nature nanotechnology 18.1 (2023): 55-63.\nQuestion 2: Trade-offs Between Ferroelectricity and Resistive Switching: Is there an\nintrinsic trade-off between enhancing the ferroelectric polarization and optimizing the\nresistive switching behavior in this material system? A discussion, possibly supported\nby a simplified physical or phenomenological model, would be valuable to assess\nwhether the coexistence of both functionalities could result in compromised individual\nperformance compared to dedicated ferroelectric or resistive-switching materials.\nPlease compare the performance with state of the art high-k ferroelectric and resistive-\nswitching materials.\nResponse: We thank the reviewer for raising an important and insightful question\nregarding the potential trade-off between ferroelectric polarization and resistive\nswitching in α-In₂Se₃. From a theoretical standpoint, we believe that these two\nfunctionalities are not mutually exclusive, but rather intrinsically coupled through the\npolarization-induced band modulation characteristic of ferroelectric semiconductors.\nWe have added the following Supplementary Note 3 to the revised SI to discuss this\ntrade-off.\n“Supplementary Note 3: Trade-off between ferroelectric and resistive switching.\nThe ferroelectric polarization 𝑃 in α-In₂Se₃ follows the Ginzburg–Landau equationR1:\n𝐸 +𝛼𝑃+𝛽𝑃(cid:2871) = 0\nHere, 𝐸 is the internal electric field, and 𝛼, 𝛽 are the Landau coefficients describing\nthe material's free energy landscape. The nonlinearity of this relation allows for\nbistable polarization states (up/down), which can be switched under an external field：\nenabling non-volatile behavior.\nIn ferroelectric semiconductors, the total displacement field in the material is:\n𝐷 = 𝜀 𝜀 𝐸+𝑃\n(cid:2868) (cid:3045)\nHere, 𝜀 varepsilon is the vacuum permittivity, 𝜀 is the relative permittivity of α-\n(cid:2868) (cid:3045)\nIn₂Se₃. This displacement field, through Poisson’s equation,\n𝛻⋅𝐷 = 𝜌 = 𝑞(𝑝−𝑛)\n(cid:3033)\ndetermines the charge distribution within the material, where 𝜌 is the free charge\n(cid:3033)\ndensity, 𝑞 is the elementary charge, 𝑛 is the electron concentration, and 𝑝 is the\nhole concentration. In α-In₂Se₃, modulation of 𝑃 shifts the conduction and valence\nband edges, thereby altering 𝑛 and 𝑝 locally.\nAssuming a dominant electron channel, the electron concentration follows the 2D\nFermi–Dirac distribution:\n2𝑚∗𝑘𝑇 𝐸 −𝐸\n(cid:3032) (cid:3007) (cid:3004)\n𝑛 = 𝑙𝑜𝑔(cid:3436)1+𝑒𝑥𝑝(cid:3436) (cid:3440)(cid:3440)\n𝜋ℏ(cid:2870) 𝑘𝑇\nIn this expression, 𝑚∗ is the electron effective mass, 𝑘 is Boltzmann’s constant, 𝑇 is\n(cid:3032)\nthe absolute temperature, ℏ is the reduced Planck constant, 𝐸 is the Fermi level,\n(cid:3007)\nand 𝐸 is the conduction band minimum. As polarization changes the internal\n(cid:3004)\nelectrostatic potential, it shifts 𝐸 relative to 𝐸 , thereby modulating the electron\n(cid:3004) (cid:3007)\nconcentration 𝑛.\nThis change in carrier density directly affects the channel conductance, and the drain-\nsource current can be approximated as:\n𝐼 ∝ 𝑛⋅𝜇⋅𝑉\n(cid:3005)(cid:3020) (cid:3005)(cid:3020)\nTherefore, rather than competing, ferroelectricity and resistive switching in α-In₂Se₃\nreinforce each other: Stronger polarization leads to deeper band bending and sharper\nmodulation of 𝑛, enhancing conductance contrast. Partial switching enables domain-\nwall states with intermediate conductance, allowing for analog-like, multi-level\nbehavior.\nThe coupled ferroelectric and semiconducting nature of α-In₂Se₃ is critical to analyze\nfor understanding the device operation of FeS-FET. For detailed analysis of the\nferroelectric and resistive switching mechanisms from the perspective of energy bands,\nplease refer to Supplementary Fig. 4.\nFeS-FET offer key advantages over conventional Fe-FET by using a ferroelectric\nsemiconductor as the channel and a stable amorphous dielectric as the gate insulator.\nThis structure reduces charge trapping and eliminates gate leakage through the\nferroelectric layer. Additionally, mobile carriers in the semiconductor effectively screen\nthe depolarization field, leading to improved retention, stability, and reliability for non-\nvolatile memory applicationsR1, R2, R3.”\nWe have added Supplementary Table 3 and 4 to the revised SI to present a\nperformance comparison between In Se devices and state-of-the-art ferroelectric and\n2 3\nresistive-switching materials.\nSupplementary Table 3. Performance comparison between In\n3\nand ferroelectric materials.\nRef. R4 R5, R6 R7, R8, R9 R10, R11, R12\nMaterial Si: HfO HZO CIPS InSe\n2 2 3\nRemnant Polarization 10 μC/cm² 13 μC/cm² 4 μC/cm−2 0.92 μC/cm−2\nThickness 5-20 nm 5-20nm 50-100 nm ∼ 1.2-50 nm\nOn/Off ratio 105 107 107 108\nSpeed 100 ns 100 ns 10–50 μs 40 ns\nEndurance\n104 108 103 104\n(cycles)\nRetention 10 years 10 years ＞104 s ＞104 s\nSupplementary Table 3. Performance comparison between In\n3\nand resistive-switching materials.\nRef. R13 R14 R15 R16 R17 R18\nDevice Pt/ZnO:Cr/ Pt/ZnO:NH/ ITO:Hf/ZrO/ Ti/TiO/ TaN/AlO/NbAlO/ Ni/InSe/\nx 2 x 2 3 2 3\nstructure IZO TiN TiN HfO/Pt AlO/Pt AlO/Ni\nx 2 3 2 3\nV (V) N/A 2.58 N/A Forming-free 4.5 Forming-free\nForming\nV /V (V) 0.89/-0.86 0.8/-0.8 1.2/-0.5 0.88/-0.89 0.8/-0.8 4/-4\nSET RESET\nOn/Off ratio 102 19 300 11.4 100 108\nEndurance\n105 107 107 100 103 106\n(cycles)\nRetention(s) ＞105 ＞104 ＞104 ＞104 ＞104 ＞104\nWe have also made the following additions to page 4 of the revised main text:\n“Due to the coexistence of ferroelectric and resistive switching properties, α-\nIn Se exhibits distinct advantages and unique application scenarios compared to\n2 3\ntraditional ferroelectric and resistive switching materials (Supplementary Table 3 and\n4). Furthermore, the trade-off between its ferroelectric and resistive characteristics\nfurther expands its application prospects (Supplementary Note 3).”\nReferences:\nR1 Si, Mengwei, et al. \"A ferroelectric semiconductor field-effect transistor.\" Nature Electronics 2.12\n(2019): 580-586.\nR2 Yurchuk, Ekaterina, et al. \"Charge-trapping phenomena in HfO2-based FeFET-type nonvolatile\nmemories.\" IEEE Transactions on Electron Devices 63.9 (2016): 3501-3507.\nR3 Ma, T. P., and Jin-Ping Han. \"Why is nonvolatile ferroelectric memory field-effect transistor still\nelusive? \" IEEE Electron Device Letters 23.7 (2002): 386-388.\nR4 Müller, Johannes, et al. \"Ferroelectricity in HfO 2 enables nonvolatile data storage in 28 nm\nHKMG.\" 2012 symposium on VLSI technology (VLSIT). IEEE, 2012.\nR5 Bae, Jong-Ho, et al. \"Highly scaled, high endurance, Ω-gate, nanowire ferroelectric FET memory\ntransistors.\" IEEE Electron Device Letters 41.11 (2020): 1637-1640.\nR6 Lin, Zehao, et al. \"Highly Robust All-Oxide Transistors Toward Vertical Logic and Memory.\" IEEE\nTransactions on Electron Devices (2024).\nR7 Wu, Jiangbin, et al. \"High tunnelling electroresistance in a ferroelectric van der Waals heterojunction\nvia giant barrier height modulation.\" Nature Electronics 3.8 (2020): 466-472.\nR8 Zhou, Shuang, et al. \"Anomalous polarization switching and permanent retention in a ferroelectric\nionic conductor.\" Materials Horizons 7.1 (2020): 263-274.\nR9 Si, Mengwei, et al. \"Ferroelectric field-effect transistors based on MoS2 and CuInP2S6 two-\ndimensional van der Waals heterostructure.\" Acs Nano 12.7 (2018): 6700-6705.\nR10 Tang, Wenhui, et al. \"A van der Waals Ferroelectric Tunnel Junction for Ultrahigh‐Temperature\nOperation Memory.\" Small Methods 6.4 (2022): 2101583.\nR11 Wang, Shuiyuan, et al. \"Two-dimensional ferroelectric channel transistors integrating ultra-fast\nmemory and neural computing.\" Nature Communications 12.1 (2021): 53.\nR12 Xue, Fei, et al. \"Room‐temperature ferroelectricity in hexagonally layered α‐In2Se3 nanoflakes\ndown to the monolayer limit.\" Advanced Functional Materials 28.50 (2018): 1803738.\nR13 Li, Sih-Sian, and Yan-Kuin Su. \"Improvement of the performance in Cr-doped ZnO memory devices\nvia control of oxygen defects.\" RSC advances 9.6 (2019): 2941-2947.\nR14 Wu, Pei-Yu, et al. \"Improvement of resistive switching characteristics in zinc oxide-based resistive\nrandom access memory by ammoniation annealing.\" IEEE Electron Device Letters 41.3 (2020): 357-360.\nR15 Li, Lei, et al. \"Variable-temperature activation energy extraction to clarify the physical and chemical\nmechanisms of the resistive switching process.\" Nanoscale 12.29 (2020): 15721-15724.\nR16 Ku, Boncheol, et al. \"Interface engineering of ALD HfO2-based RRAM with Ar plasma treatment\nfor reliable and uniform switching behaviors.\" Journal of Alloys and Compounds 735 (2018): 1181-1188.\nR17 Chen, Lin, et al. \"Highly Uniform Bipolar Resistive Switching With Al2O3 Buffer Layer in Robust\nNbAlO-Based RRAM.\" IEEE electron device letters 31.4 (2010): 356-358.\nR18 Si, Mengwei, et al. \"Asymmetric metal/α-In2Se3/Si crossbar ferroelectric semiconductor\njunction.\" ACS nano 15.3 (2021): 5689-5695.\nQuestion 3: Voltage Requirements and Material Engineering: The operational voltages\nreported in Figures 2b and 2c, particularly for resistive switching, remain relatively\nhigh. This is a significant concern given that state-of-the-art resistive memory devices\ntypically operate below 1 V. The authors are requested to discuss the prospects for\nreducing operating voltages in α-In₂Se₃ FeS-FETs. Beyond geometric scaling, are there\nmaterial engineering strategies (e.g., doping, strain, interface engineering) that could\nfurther tailor the polarization and switching characteristics?\nResponse: We thank the reviewer for the thoughtful and important comment regarding\nthe relatively high operating voltages observed in our α-In₂Se₃ FeS-FET,\nparticularly for resistive switching. We fully agree that lowering the switching voltage is essential\nfor practical deployment, especially when compared to state-of-the-art resistive\nmemory technologies that typically operate below 1(cid:3031)V. The disparity in operating\nvoltages is primarily attributed to the difference in device structures. Conventional\nresistive-switching devices typically utilize a vertical sandwich structure, whereas the\nFeS-FET employs a three-terminal transistor configuration. Notably, Ni/α-In Se /p+ Si\n2 3\ndevices, which utilize a similar vertical sandwich structure, can also achieve reduced\noperating voltages in the range of 1–2 VR1. Nevertheless, exploring strategies to reduce\nthe operating voltage of FeS-FET remains of significant importance, particularly for\noptimizing power consumption.\nIn our current device configuration, the switching voltage is primarily determined by\nthe coercive field required to reverse the out-of-plane polarization in the α-In₂Se₃\nchannel. Our device currently has a switching ratio close to 104 at 3V (Fig. 1c), but it\nstill lags behind the most advanced devices. This is influenced by both the material\nproperties and device geometry. While geometric scaling—such as reducing channel\nthickness and employing high-EOT (equivalent oxide thickness) gate dielectrics—can\ndirectly enhance the electric field across the ferroelectric channel and reduce the\nrequired gate voltage, several material engineering approaches offer further\nopportunities to reduce the operational voltage:\n(i) Doping Engineering: Controlled n-type or p-type doping of α-In₂Se₃ can modulate\nthe internal screening length and reduce the depolarization field, thus lowering the\nenergy barrier for polarization switching. In particular, introducing shallow donors may\nenhance free carrier screening, enabling more efficient polarization reversal at lower\nvoltages.\n(ii) Interface Engineering: The polarization switching dynamics and voltage threshold\nare also strongly affected by the quality of the gate dielectric/semiconductor interface.\nIntroducing a high-κ gate dielectric with a clean, well-passivated interface (e.g., HfO₂\nor Al₂O₃ with appropriate interlayers) can improve the coupling of gate electric field\ninto the ferroelectric channel, reduce charge trapping, and promote more uniform\ndomain nucleation. Such engineering may also suppress interfacial pinning effects that\notherwise raise the switching voltage.\n(iii) Layer Number Optimization: As reported in prior studies, monolayer and few-layer\nα-In₂Se₃ R2, R3 maintains robust polarization with reduced switching voltage compared\nto thicker flakes. This is consistent with reduced screening length and improved field\npenetration in thinner channels.\nWe are actively exploring these strategies in our ongoing work and are optimistic that\na combination of geometric scaling and material/interface optimization can bring the\nswitching voltage well below current levels.\nReferences:\nR1 Si, Mengwei, et al. \"Asymmetric metal/α-In2Se3/Si crossbar ferroelectric semiconductor\njunction.\" ACS nano 15.3 (2021): 5689-5695.\nR2 Cui, Chaojie, et al. \"Intercorrelated in-plane and out-of-plane ferroelectricity in ultrathin two-\ndimensional layered semiconductor In2Se3.\" Nano letters 18.2 (2018): 1253-1258.\nR3 Xiao, Jun, et al. \"Intrinsic two-dimensional ferroelectricity with dipole locking.\" Physical review\nletters 120.22 (2018): 227601.\nQuestion 4: Thermal Stability and Temperature Range: In Supplementary Figure 3, the\nauthors present hysteresis loops measured from room temperature down to 90 K,\nsupporting the attribution to OOP ferroelectric switching. Have the devices also been\ncharacterized at elevated temperatures (e.g., up to 85°C or 100°C)? Assessing thermal\nstability is essential for realistic deployment in neuromorphic hardware operating\nunder varying environmental conditions.\nResponse: We thank the reviewer for this valuable suggestion. We fully agree that\nassessing the thermal stability at elevated temperatures is essential for realistic\ndeployment in neuromorphic hardware, which often operates under varying\nenvironmental conditions. Following the reviewer's suggestion, we have now\ncharacterized the devices at elevated temperatures, specifically from 300 K up to 420\nK. The results indicate that the device maintains excellent performance in the range of\nratio. We note that this range covers the common high-temperature operating conditions\n(e.g., 85°C) for most electronic devices. As the temperature increases further to around\neffects; however, a significant switching ratio was still maintained. This high-\ntemperature characterization confirms that our device can maintain its robust\ncharacteristics in common elevated-temperature environments, supporting its potential\nfor practical deployment.\nWe have updated Supplementary Fig.3 in the revised SI.\nSupplementary Fig.3. The ID-VG under different temperatures. (a), The I -V from 90 K to 300 K.\nD G\nThe small fluctuation of the hysteresis window excludes the influence of interface traps and indicates\nthat the hysteresis is caused by ferroelectricity. (b), The I -V from 300 K to 420 K. This high-temperature\nD G\ncharacterization confirms that the device can maintain its robust characteristics in common elevated-\ntemperature environments, supporting its potential for practical deployment.\nWe have made the following additions to page 5 of the revised main text:\n“The minimal change in the hysteresis window suggests that ferroelectric\npolarization is the dominant factor. High-temperature characterization (Supplementary\nFig. 3) also confirms the device's capability to operate in elevated temperature\nenvironments.”\nQuestion 5: Device Variability and Yield: The ID–VG characteristics from an array of\n36 devices exhibit substantial variability, with many devices showing incomplete or\nnon-saturated polarization switching and also highly variable characteristics of\nresistive switching. The authors should provide a detailed analysis of the sources of this\nvariability — e.g., flake quality, interface states, contact resistance, or fabrication-\ninduced disorder — and outline potential strategies for variability mitigation.\nFurthermore, how is this variability tolerated or compensated for in the reported\nneuromorphic applications?\nResponse: We thank the reviewer for highlighting the important issue of device\nvariability and yield. We fully acknowledge that the I –V characteristics across the 36-\nD G\ndevice array exhibit noticeable variation in both polarization switching and resistive\nbehavior. This variability arises from several sources:\n(i) Interface States and Traps: Imperfect dielectric/semiconductor interfaces (e.g.,\nsurface oxidation or adsorbed residues) can introduce trap states that interfere with\ndomain switching and contribute to device-to-device non-uniformity in hysteresis and\nmemory window. (ii) Contact Resistance Fluctuations: Variability in source/drain\ncontact quality due to surface contamination or uneven metal adhesion introduces\ndifferences in current levels and on/off ratios. (iii) Fabrication-Induced Disorder:\nManual flake transfer and alignment can result in mechanical stress, interfacial voids,\nor unintended defects, which influence ferroelectric domain dynamics and charge\ntransport pathways.\nTo mitigate these sources of variability, several strategies are being pursued:\nAdopting wafer-scale synthesis techniques to improve flake uniformity and integration\nconsistency; Improving interface engineering, such as higher quality high-κ dielectrics\nand surface cleaning/passivation to reduce interface traps; Automating exfoliation and\ntransfer through deterministic placement methods to reduce mechanical damage and\ncontamination.\nEven in the presence of a certain degree of D2D variation or noise variation, the network\nremains capable of successful convergence, exhibiting a slight reduction in\nconvergence speed (Supplementary Fig. 25 and Supplementary Fig. 26). This\ndemonstrates the strong redundancy capability of In Se FeS-FET based RL neural\n2 3\nnetwork. This is attributed to the closed-loop nature of in-situ training, where the\niterative weight updates dynamically compensate for static device errors. Consequently,\nthe algorithm automatically adjusts the number of update steps to reach the target\nconductance, effectively mitigating the impact of individual device variability.\nIn the context of neuromorphic applications, some degree of device variability is not\nonly tolerable but can be exploited to introduce device-level heterogeneity, which has\nbeen shown to enhance learning robustness and generalizationR1, R2. Specifically, in our\nspiking reinforcement learning framework: Synaptic weight updates are encoded in a\nrelative manner (i.e., based on conductance change), making them resilient to absolute\nvariability; Redundant neuron-synapse mappings and reward-driven plasticity help the\nnetwork adaptively adjust to non-idealities through in-situ learning.\nReferences:\nR1 Li, Can, et al. \"Efficient and self-adaptive in-situ learning in multilayer memristor neural\nnetworks.\" Nature communications 9.1 (2018): 2385.\nR2 Yao, Peng, et al. \"Fully hardware-implemented memristor convolutional neural\nnetwork.\" Nature 577.7792 (2020): 641-646.\nThe main changes we made are summarized as follows:\n1. We have added the PCB operating circuit system designed for the 6×8 In Se\n2 3\nFeS-FET array, along with its corresponding modular logic, as shown in\nSupplementary Fig.16. Additionally, the results of read/write operations\nperformed on the In Se FeS-FET devices using this PCB circuit have been\n2 3\nincluded as shown in Supplementary Fig.22.\n2. We have added an analysis of the energy consumption for the In Se FeS-FET\n2 3\ndevice operation as Supplementary Fig.14, and a power consumption analysis\nof the PCB circuit system as Supplementary Note 1.\n3. We evaluated the noise of the PCB circuit system, which is presented as\nSupplementary Fig.17. Additionally, through neural network simulations, we\nassessed the impact of device-to-device (D2D) variation and device noise on\ntraining performance, as demonstrated in Supplementary Fig.25 and\nSupplementary Fig.26.\n4. We have updated Supplementary Table 1 to include comparisons with a\nbroader range of related works, specifically adding a comparison of energy\nconsumption. We have also added Supplementary Table 2 to provide a\nhorizontal comparison between this work and other reported In Se -based\n2 3\nsynaptic devices. Furthermore, Supplementary Table 3 and 4 have been added\nto compare the performance of In Se against state-of-the-art ferroelectric and\n2 3\nresistive-switching materials.\n5. We have updated Supplementary Fig.12 to include curve fitting information\nfor the eligibility trace. Furthermore, we have added Supplementary Note 2,\nwhich provides a mathematical analysis of the physical model regarding the\neligibility trace and ferroelectric relaxation.\n6. We have updated Supplementary Fig.2 with clearer PFM ferroelectric\ncharacterization data.\n7. We have added hysteresis loops measured under different V as\nDS\nSupplementary Fig.13 to characterize the influence of V on ferroelectric\nDS\npolarization and relaxation.\n8. We have added Supplementary Note 3 to discuss the interaction between the\nferroelectric and resistive switching physical models in In Se , and to examine\n2 3\nthe trade-off between them.\n9. We have updated Supplementary Fig.13 to include the performance\ncharacterization of In Se at elevated temperatures.\n2 3\nPoint-by-point Response\nWe thank all the reviewers for their precious time and constructive comments on our\nmanuscript. We revised both the main text and the supplementary information (SI)\naccordingly. In the following point-to-point response, the original reviewers’\ncomments are in blue colored italic font, our responses are in black fonts. Changes in\nthe revised main text and SI are highlighted in yellow, with the revised content\npresented in black italic font.\nResponse to Reviewers' comments:\nReviewer #1 (Remarks to the Author):\nThe authors have revised the manuscript in response to the reviewers’ comments.\nHowever, one concern remains.\nIn the response letter, the authors mentioned that “We chose the In2Se3 FeS-FET\nbecause it possesses both in-plane (IP) and out-of-plane (OOP) polarization modes,\nenabling three-terminal conductance modulation via both Vds and Vgs.” However,\nsimilar three-terminal conductance modulation has already been demonstrated in\nconventional Si-based FeFETs. For example, such functionality has been reported in\nAdvanced Functional Materials (DOI: 10.1002/adfm.202011077). Therefore, the use of\nIn2Se3 FeS-FET does not, by itself, convincingly demonstrate a significant innovation\nover existing Si-FeFET implementations. The authors should clarify the unique\nadvantages and novelty of the proposed device architecture beyond what has already\nbeen achieved in prior work.\nResponse: We thank the reviewer for the suggestion and the provided important\nliterature. In the revised manuscript, we cite the paper (Advanced Functional\nMaterials,DOI: 10.1002/adfm.202011077) as ref. 41. The multi-terminal modulation\nimplemented in ref. 41 differs fundamentally from our In₂Se₃ device in terms of\nphysical mechanisms and modulation degrees of freedom. Overall, ref. 41 employs the\nelectric field gradient induced by the drain voltage (V ) to spatially control the\nD\nswitching volume of a single ferroelectric polarization (out-of-plane). In contrast, our\nIn₂Se₃ device leverages the intrinsic coupling between two orthogonal polarization\nmodes, in-plane (IP) and out-of-plane (OOP), to achieve genuine multi-mechanism\nmodulation. A detailed comparative analysis is provided below:\n[FIGURE REDACTED]\nFig. R1. Schematics of domain switching in the FeFET. Switching of the out-of-plane polarization\ninduced by V (Taken from ref. 41).\nDS\n1. Fundamental Difference in Physical Mechanisms. ref. 41 relies on electric field\ngradient-controlled switching of a single polarization volume. In the reported\nHZO FeFET, a drain voltage (V ) is utilized to establish an electric field gradient\nD\nalong the channel direction (Fig. R1). By simultaneously applying V\nG\nand V\nD\n, the\npotential distribution across the gate stack is modified, thereby controlling the\nspatial volume of domain switching within the ferroelectric thin film (e.g.,\nprogressive switching propagating from the source to the drain). Fundamentally,\nthis remains a modulation of ferroelectric polarization in a single direction\n(OOP), where V serves to alter the spatial distribution of the vertical electric\nD\nfield to facilitate \"partial switching\" for multilevel storage.\nIn contrast, our work exploits the intrinsic coupling between two orthogonal\nferroelectric polarization modes, IP and OOP, inherent in In₂Se₃. The device\nutilizes V to modulate IP polarization (emulating the establishment and decay\nD\nof STDP or eligibility traces) and V to modulate OOP polarization (representing\nG\nthe modulation of the Reward signal). This is a process based on the interaction\nbetween two orthogonal physical quantities (IP and OOP), rather than merely\nchanging the magnitude of a single polarization vector.\n2. Differences in modulation degrees of freedom and functional implementation:\nIn ref. 41, the modulation degrees of freedom are dedicated to optimizing storage\ndensity. Drain modulation is employed primarily to overcome the difficulty of\n\"multilevel storage\" arising from the limited number of ferroelectric domains in\nscaled devices. Consequently, its core functionality remains static multilevel\nstorage, as both drain and gate operations ultimately control the same variable\n(the threshold voltage V ).\nTH\nConversely, the degrees of freedom in our work are designed for complex\nalgorithm mapping (R-STDP). We introduce multi-terminal modulation to\nphysically map distinct RL variables, where V and V correspond to the\nDS GS\neligibility trace and reward signal, respectively. This unique freedom allows a\nsingle device to execute complex computations requiring the synergy of temporal\ncorrelation and external feedback, going far beyond simple static weight storage.\nA brief comparison of the performance of the two devices is provided below:\nRef. ref. 41 This work\nOOP √ √\nIP × √\nOn/Off ratio 105 106\nWeight range 4 bits 5 bits\nEligibility\n× ~28~189 ms\ntrace\nReviewer #2 (Remarks to the Author):\nThe authors have made substantial efforts to address the concerns raised in the previous\nround of review. I appreciate the detailed responses, particularly the inclusion of the\nPCB circuit operating system implementation, the mathematical mapping of the\neligibility trace, and the additional characterization of device reliability. The\nmanuscript has been significantly improved in terms of system-level validation and the\nexplanation of the physical mechanisms.\nHowever, upon closer inspection of the new supplementary data (specifically the PCB\nimplementation details), critical concerns regarding the definition of \"in-situ\" learning\nand the logical consistency of the proposed R-STDP mechanism have emerged. The\nreliance on a closed-loop write scheme and the simulation-heavy defense for variation\nissues tend to undermine the central claim of \"intrinsic physical computing.\" These\nissues must be rigorously clarified before publication:\nResponse: We appreciate the reviewer’s positive evaluation of our revisions. In the\nresponse below, we have carefully addressed the new queries and provided the\nnecessary clarifications.\n1. In the abstract and introduction, the authors claim that the R-STDP function is\nimplemented by leveraging the \"intrinsic in-plane and out-of-plane polarization\ncoupling\" 1and that the three-step computational process (STDP, eligibility trace,\nreward modulation) is accomplished \"without any external memory or computing units\".\nHowever, in Supplementary Fig. 22, the authors present a weight update process via\nthe PCB circuit system that appears to function as a \"closed-loop\" writing operation.\nThe text mentions that the algorithm \"automatically adjusts the number of update steps\nto reach the target conductance\". The authors must clarify: Did the autonomous driving\nexperiment (Fig. 4) utilize this closed-loop adjustment for every synaptic update?\nIf so, the claim of \"in-situ... without external computing units\" is misleading, as the\nexternal control logic is heavily involved in calculating and correcting the weights.\nResponse: We apologize for the confusion caused by Supplementary Fig. 22 and wish\nto strictly clarify that all experiments and simulations in this manuscript were executed\nin strict adherence to the three-step computational process (STDP, eligibility trace, and\nreward modulation). The PCB serves solely as a control unit (e.g., for device port\nselection and pulse application), while the weight computation is still performed\nintrinsically within the device. Even for the SET/RESET operations shown in\nSupplementary Fig. 22, the weight updates were physically driven by this three-step\nprocess (joint modulation by V and V pulses, see Figure 3a-c). The only difference\nD G\nis that, solely for the purpose of demonstrating the feasibility and precision of our array\nand PCB control scheme, we artificially set a \"target conductance\" and performed a\nverification step after each pulse to check if the target was reached. In the actual R-\nSTDP algorithm, however, there is no such \"target conductance.\" Unlike supervised\nlearning, RL does not rely on labeled data for training; instead, it adjusts weights based\non real-time environmental feedback (reward signals, ∆w=STDP(t) ∙ E(t) ∙ R(t)), and\nthe weights converge autonomouslyR1, R2 (as shown in Supplementary Fig. 27). The\nreason we introduced a target conductance and employed a write-verify scheme in\nSupplementary Fig. 22 was to demonstrate that our PCB design is capable of precisely\nmodulating weights via the proposed three-step mechanism. If we had displayed the\nactual R-STDP process (without write-verify or targets), the weights would evolve\nstochastically based on environmental feedback and eventually converge (where ∆w ≈\n0), and without a pre-defined target value, the feasibility of our PCB solution would not\nbe fully demonstrated.\nIn summary, the write-verify scheme in Supplementary Fig. 22 was intended only to\nvalidate the feasibility of our PCB platform. Every SET/RESET step therein was strictly\nexecuted using the V + V pulse-based three-step calculation, and all experiments and\nD G\nsimulations in the manuscript strictly complied with the intrinsic three-step\ncomputational process.\nTo avoid any potential misunderstanding, we have made the following modifications to\nSupplementary Fig. 22.\nSupplementary Fig. 22 Read/write operations of the PCB circuit system. (a), (b) and (c): conductance\nevolution of three devices during read/write operations. (d), a write-verify scheme was adopted, the\nweight updates SET/RESET were physically driven by this three-step process (joint modulation by V\nD\nand V pulses, see Figure 3a-c). Here the target weights (conductance) are manually set to demonstrate\nG\nthat arbitrary weight (conductance) can be achieved within the designed range based on our three-step\nprocesses.\nReferences:\nR1 Frémaux N, Gerstner W. Neuromodulated spike-timing-dependent plasticity, and theory of three-\nfactor learning rules. Frontiers in neural circuits 2016, 9: 85.\nR2 Gerstner W, Lehmann M, Liakoni V, Corneil D, Brea J. Eligibility traces and plasticity on behavioral\ntime scales: experimental support of neohebbian three-factor learning rules. Frontiers in neural circuits\n2018, 12: 53.\n2. The authors should explicitly clarify the Training Mode used in the autonomous\ndriving demonstration. The Methods section states that the environment is \"simulated\nby Python\". The manuscript must state whether the experiment was (A) Fully In-Situ:\nwhere the FeS-FET array physically receives pre/post spikes and reward signals, and\nthe conductance updates occur naturally via the claimed polarization mechanisms; or\n(B) Hardware-in-the-Loop: where the weight updates are calculated digitally (in\nPython/MCU) and then \"written\" to the array using the closed-loop scheme mentioned\nin Source. If it is (B), the claims regarding implementing the algorithm are overstated,\nas the device is acting merely as a programmable resistor rather than a computational\nunit.\nResponse: We thank the reviewer for the suggestions. As explained in the previous\nresponse, we adopted Scenario A: the FeS-FET array physically receives pre/post\nspikes and reward signals, and the conductance updates occur naturally via the claimed\npolarization mechanisms (see the Methods section). All experiments and simulations in\nthe manuscript were completed in strict adherence to the three-step computational\nprocess (STDP, eligibility trace, and reward modulation). The neural network\nsimulation was implemented in Python, while the autonomous driving scenario was\nconstructed in CoppeliaSim and interacts with the network (Supplementary Fig. 15).\nThe PCB/MCU serves solely as a control unit responsible for tasks such as device port\nselection and pulse application. The actual calculation of the weight update is realized\nintrinsically through the ferroelectric polarization and relaxation within the device\nunder pulse stimulation (Fig. 3), rather than being computed by an external unit and\nexplicitly written into the device. The specific R-STDP computation process described\nin the manuscript is as follows (including Supplementary Fig. 22): Pre- and post-\nsynaptic pulses are applied to the drain and source, establishing an STDP effect that\ndecays over time due to ferroelectric relaxation (acting as an eligibility trace). After a\ncertain delay, a reward signal pulse is applied to the gate, which interacts with this\ndecaying state to jointly produce the final modulation of the channel conductance\n(synaptic weight).\n3. The authors claim an energy consumption of 65 pJ per R-STDP event. However, this\nis a device-level metric. As noted in Supplementary Note 1, the PCB system power is\nsignificantly higher (~14.19 mW). While the FeS-FET efficiency is notable, in this\nspecific architecture, the peripheral overhead (ADC/DAC, control logic for the closed-\nloop writing) dominates. The manuscript should transparently acknowledge that while\nthe synaptic element is efficient, the current system implementation relies heavily on\nperipheral overhead to manage the\"iterative weight updates, which compromises the\noverall system efficiency.\nResponse: We thank the reviewer for the suggestions. It is a legitimate concern that\nvarious peripherals such as A/D, D/A converters consume a major portion of the power\nused in a mixed digital-analog signal system. This is a common issue prevalent in\ncurrent mainstream energy-efficient hardware solutionsR1, R2. This is because our\ncurrent PCB platform is implemented using commercial off-the-shelf (COTS)\ncomponents, rather than a custom-designed Application-Specific Integrated Circuit\n(ASIC). High power consumption is an inherent characteristic of discrete components\nand a common issue in such prototypes. Utilizing more energy-efficient MCU and\namplifier (Ambiq Apollo, TI LPV821) is expected to reduce the circuit power\nconsumption to the microwatt (μW) range while maintaining full functionality.\nIntegrating peripheral control circuits using advanced process nodes (e.g., 28 nm) can\nfurther reduce power consumptionR3, R4.\nIn addition, although beyond the scope of this work, the future peripheral circuits are\nnot limited to CMOS technology only. For instance, recently reported energy-efficient\nhardware based on memristive ADCs/DACs is better suited for novel neuromorphic\ncomputing architecturesR5.\nTo make this point clearer, we have made the following modifications in the revised\nmanuscript in page 11:\n“Furthermore, it exhibits low operating energy consumption, approximately 65 pJ\nper R-STDP event (Supplementary Fig. 14), demonstrating a significant advantage over\ncomparable devices (Supplementary Table 1). Therefore, it indicates the significant\npredominance in area, energy and latency of the hardware SNN system for RL.\nMeanwhile, the power consumption of the PCB control circuit is significantly higher\nthan that of the device itself (Supplementary Note 1). Future improvements are expected\nto achieve much higher energy efficiency through custom on-chip integration52, 53 or\nnovel memristor-based ADC54.”\nReferences:\nR1 Li, Can, et al. \"Efficient and self-adaptive in-situ learning in multilayer memristor neural\nnetworks.\" Nature communications 9.1 (2018): 2385.\nR2 Yao, Peng, et al. \"Fully hardware-implemented memristor convolutional neural\nnetwork.\" Nature 577.7792 (2020): 641-646.\nR3 Wan, Weier, et al. \"A compute-in-memory chip based on resistive random-access\nmemory.\" Nature 608.7923 (2022): 504-512.\nR4 Verma, Naveen, et al. \"In-memory computing: Advances and prospects.\" IEEE solid-state circuits\nmagazine 11.3 (2019): 43-55.\nR5 Hong, Haiqiao, et al. \"Memristor-based adaptive analog-to-digital conversion for efficient and\naccurate compute-in-memory.\" Nature Communications 16.1 (2025): 9749.\nReviewer #3 (Remarks to the Author):\nThe authors have satisfactorily addressed the majority of the reviewer’s questions and\nhave improved the clarity of the manuscript and the discussions. The paper presents\nuseful experimental data and contains elements of novelty that may be of interest to the\ncommunity.\nHowever, important concerns remain regarding the technological scalability of the\nproposed approach. In particular, the reliance on mechanical exfoliation inherently\nlimits compatibility with large-scale integration. While the manuscript mentions the\npossibility of realizing α-In₂Se₃ through wafer-scale growth techniques and briefly\nalludes to integration on standard silicon substrates, these aspects remain largely\nconceptual and are not substantiated by a concrete process pathway.\nResponse: We thank the reviewer for recognizing the novelty of our work. We fully\nagree with the reviewer’s constructive comments concerning technological scalability\nWhile the primary objective of this work is to elucidate the intrinsic physical\nmechanism of R-STDP in ferroelectric semiconductors using high-quality single\ncrystals, we recognize that outlining a concrete path toward large-scale integration is\nessential for the practical adoption of this technology. Recent literature has already\ndemonstrated large-scale, high-quality growth processes for In Se R1. The roadmap for\n2 3\nits wafer-scale fabrication can mirror that of more mature 2D materialsR2, such as MoS .\n2 3\nintegration, following the successful trajectory of MoS\nas a methodological demonstration of the principle. We are confident that material\ngrowth challenges will be gradually addressed as the field advances.\nIn addition, device-to-device variability and control are not adequately addressed.\nWhile this limitation is likely intrinsic to the current exploratory nature of the\ntechnology and may not be fully resolvable within the present experimental framework,\nit nonetheless weakens the case for practical adoption. But I understand that these\naspects cannot be fully addressed in this more exploratory paper.\nResponse: We thank the reviewer for acknowledging our response. We also deeply\nappreciate the reviewer's understanding that this exploratory work, by its nature, cannot\nbe exhaustive in every aspect. We fully agree with the reviewer’s constructive\ncomments concerning device-to-device variability.\nIn the revision we have validated via simulation that the proposed computing scheme\npossesses a degree of tolerance towards D2D variations. Similar to the challenge of\nlarge-scale material growth discussed above, addressing this issue also relies on\nadvancements in the broader field. Large-scale, high-quality single-crystal In Se is\n2 3\nexpected to exhibit superior performance and significantly lower D2D variations. As\nan emerging ferroelectric semiconductor, the synthesis techniques for InSe are steadily\nevolving, and we are confident that future progress in the field will eventually overcome\nthis limitation.\nReferences:\nR1 Han, Wei, et al. \"Phase-controllable large-area two-dimensional In2Se3 and ferroelectric heterophase\njunction.\" Nature nanotechnology 18.1 (2023): 55-63.\nR2 Akinwande, Deji, et al. \"Graphene and two-dimensional materials for silicon\ntechnology.\" Nature 573.7775 (2019): 507-518.\nR3 Das, Saptarshi, et al. \"Transistors based on two-dimensional materials for future integrated\ncircuits.\" Nature Electronics 4.11 (2021): 786-799.\nR4 Liu, Chunsen, et al. \"Two-dimensional materials for next-generation computing\ntechnologies.\" Nature nanotechnology 15.7 (2020): 545-557."}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors have revised the manuscript in response to the reviewers’ comments. The current version is acceptable.", "reviewer_2": "Thank the author for addressing my concerns，this work has been improved for publication.", "reviewer_3": "The authors have satisfactorily addressed the majority of the reviewer’s questions and have improved the clarity of the manuscript and the discussions. The paper presents useful experimental data and contains elements of novelty that may be of interest to the community.\nHowever, important concerns remain regarding the technological scalability of the proposed approach. In particular, the reliance on mechanical exfoliation inherently limits compatibility with large-scale integration. While the manuscript mentions the possibility of realizing α-In₂Se₃ through wafer-scale growth techniques and briefly alludes to integration on standard silicon substrates, these aspects remain largely conceptual and are not substantiated by a concrete process pathway.\nIn addition, device-to-device variability and control are not adequately addressed. While this limitation is likely intrinsic to the current exploratory nature of the technology and may not be fully resolvable within the present experimental framework, it nonetheless weakens the case for practical adoption. But I understand that these aspects cannot be fully addressed in this more exploratory paper."}, "author_response": "Point-by-point Response\nWe thank all the reviewers for their precious time and constructive comments on our\nmanuscript. We revised both the main text and the supplementary information (SI)\naccordingly. In the following point-to-point response, the original reviewers’\ncomments are in blue colored italic font, our responses are in black fonts. Changes in\nthe revised main text and SI are highlighted in yellow, with the revised content\npresented in black italic font.\nResponse to Reviewers' comments:\nReviewer #1 (Remarks to the Author):\nThe authors have revised the manuscript in response to the reviewers’ comments.\nHowever, one concern remains.\nIn the response letter, the authors mentioned that “We chose the In2Se3 FeS-FET\nbecause it possesses both in-plane (IP) and out-of-plane (OOP) polarization modes,\nenabling three-terminal conductance modulation via both Vds and Vgs.” However,\nsimilar three-terminal conductance modulation has already been demonstrated in\nconventional Si-based FeFETs. For example, such functionality has been reported in\nAdvanced Functional Materials (DOI: 10.1002/adfm.202011077). Therefore, the use of\nIn2Se3 FeS-FET does not, by itself, convincingly demonstrate a significant innovation\nover existing Si-FeFET implementations. The authors should clarify the unique\nadvantages and novelty of the proposed device architecture beyond what has already\nbeen achieved in prior work.\nResponse: We thank the reviewer for the suggestion and the provided important\nliterature. In the revised manuscript, we cite the paper (Advanced Functional\nMaterials,DOI: 10.1002/adfm.202011077) as ref. 41. The multi-terminal modulation\nimplemented in ref. 41 differs fundamentally from our In₂Se₃ device in terms of\nphysical mechanisms and modulation degrees of freedom. Overall, ref. 41 employs the\nelectric field gradient induced by the drain voltage (V ) to spatially control the\nD\nswitching volume of a single ferroelectric polarization (out-of-plane). In contrast, our\nIn₂Se₃ device leverages the intrinsic coupling between two orthogonal polarization\nmodes, in-plane (IP) and out-of-plane (OOP), to achieve genuine multi-mechanism\nmodulation. A detailed comparative analysis is provided below:\n[FIGURE REDACTED]\nFig. R1. Schematics of domain switching in the FeFET. Switching of the out-of-plane polarization\ninduced by V (Taken from ref. 41).\nDS\n1. Fundamental Difference in Physical Mechanisms. ref. 41 relies on electric field\ngradient-controlled switching of a single polarization volume. In the reported\nHZO FeFET, a drain voltage (V ) is utilized to establish an electric field gradient\nD\nalong the channel direction (Fig. R1). By simultaneously applying V\nG\nand V\nD\n, the\npotential distribution across the gate stack is modified, thereby controlling the\nspatial volume of domain switching within the ferroelectric thin film (e.g.,\nprogressive switching propagating from the source to the drain). Fundamentally,\nthis remains a modulation of ferroelectric polarization in a single direction\n(OOP), where V serves to alter the spatial distribution of the vertical electric\nD\nfield to facilitate \"partial switching\" for multilevel storage.\nIn contrast, our work exploits the intrinsic coupling between two orthogonal\nferroelectric polarization modes, IP and OOP, inherent in In₂Se₃. The device\nutilizes V to modulate IP polarization (emulating the establishment and decay\nD\nof STDP or eligibility traces) and V to modulate OOP polarization (representing\nG\nthe modulation of the Reward signal). This is a process based on the interaction\nbetween two orthogonal physical quantities (IP and OOP), rather than merely\nchanging the magnitude of a single polarization vector.\n2. Differences in modulation degrees of freedom and functional implementation:\nIn ref. 41, the modulation degrees of freedom are dedicated to optimizing storage\ndensity. Drain modulation is employed primarily to overcome the difficulty of\n\"multilevel storage\" arising from the limited number of ferroelectric domains in\nscaled devices. Consequently, its core functionality remains static multilevel\nstorage, as both drain and gate operations ultimately control the same variable\n(the threshold voltage V ).\nTH\nConversely, the degrees of freedom in our work are designed for complex\nalgorithm mapping (R-STDP). We introduce multi-terminal modulation to\nphysically map distinct RL variables, where V and V correspond to the\nDS GS\neligibility trace and reward signal, respectively. This unique freedom allows a\nsingle device to execute complex computations requiring the synergy of temporal\ncorrelation and external feedback, going far beyond simple static weight storage.\nA brief comparison of the performance of the two devices is provided below:\nRef. ref. 41 This work\nOOP √ √\nIP × √\nOn/Off ratio 105 106\nWeight range 4 bits 5 bits\nEligibility\n× ~28~189 ms\ntrace\nReviewer #2 (Remarks to the Author):\nThe authors have made substantial efforts to address the concerns raised in the previous\nround of review. I appreciate the detailed responses, particularly the inclusion of the\nPCB circuit operating system implementation, the mathematical mapping of the\neligibility trace, and the additional characterization of device reliability. The\nmanuscript has been significantly improved in terms of system-level validation and the\nexplanation of the physical mechanisms.\nHowever, upon closer inspection of the new supplementary data (specifically the PCB\nimplementation details), critical concerns regarding the definition of \"in-situ\" learning\nand the logical consistency of the proposed R-STDP mechanism have emerged. The\nreliance on a closed-loop write scheme and the simulation-heavy defense for variation\nissues tend to undermine the central claim of \"intrinsic physical computing.\" These\nissues must be rigorously clarified before publication:\nResponse: We appreciate the reviewer’s positive evaluation of our revisions. In the\nresponse below, we have carefully addressed the new queries and provided the\nnecessary clarifications.\n1. In the abstract and introduction, the authors claim that the R-STDP function is\nimplemented by leveraging the \"intrinsic in-plane and out-of-plane polarization\ncoupling\" 1and that the three-step computational process (STDP, eligibility trace,\nreward modulation) is accomplished \"without any external memory or computing units\".\nHowever, in Supplementary Fig. 22, the authors present a weight update process via\nthe PCB circuit system that appears to function as a \"closed-loop\" writing operation.\nThe text mentions that the algorithm \"automatically adjusts the number of update steps\nto reach the target conductance\". The authors must clarify: Did the autonomous driving\nexperiment (Fig. 4) utilize this closed-loop adjustment for every synaptic update?\nIf so, the claim of \"in-situ... without external computing units\" is misleading, as the\nexternal control logic is heavily involved in calculating and correcting the weights.\nResponse: We apologize for the confusion caused by Supplementary Fig. 22 and wish\nto strictly clarify that all experiments and simulations in this manuscript were executed\nin strict adherence to the three-step computational process (STDP, eligibility trace, and\nreward modulation). The PCB serves solely as a control unit (e.g., for device port\nselection and pulse application), while the weight computation is still performed\nintrinsically within the device. Even for the SET/RESET operations shown in\nSupplementary Fig. 22, the weight updates were physically driven by this three-step\nprocess (joint modulation by V and V pulses, see Figure 3a-c). The only difference\nD G\nis that, solely for the purpose of demonstrating the feasibility and precision of our array\nand PCB control scheme, we artificially set a \"target conductance\" and performed a\nverification step after each pulse to check if the target was reached. In the actual R-\nSTDP algorithm, however, there is no such \"target conductance.\" Unlike supervised\nlearning, RL does not rely on labeled data for training; instead, it adjusts weights based\non real-time environmental feedback (reward signals, ∆w=STDP(t) ∙ E(t) ∙ R(t)), and\nthe weights converge autonomouslyR1, R2 (as shown in Supplementary Fig. 27). The\nreason we introduced a target conductance and employed a write-verify scheme in\nSupplementary Fig. 22 was to demonstrate that our PCB design is capable of precisely\nmodulating weights via the proposed three-step mechanism. If we had displayed the\nactual R-STDP process (without write-verify or targets), the weights would evolve\nstochastically based on environmental feedback and eventually converge (where ∆w ≈\n0), and without a pre-defined target value, the feasibility of our PCB solution would not\nbe fully demonstrated.\nIn summary, the write-verify scheme in Supplementary Fig. 22 was intended only to\nvalidate the feasibility of our PCB platform. Every SET/RESET step therein was strictly\nexecuted using the V + V pulse-based three-step calculation, and all experiments and\nD G\nsimulations in the manuscript strictly complied with the intrinsic three-step\ncomputational process.\nTo avoid any potential misunderstanding, we have made the following modifications to\nSupplementary Fig. 22.\nSupplementary Fig. 22 Read/write operations of the PCB circuit system. (a), (b) and (c): conductance\nevolution of three devices during read/write operations. (d), a write-verify scheme was adopted, the\nweight updates SET/RESET were physically driven by this three-step process (joint modulation by V\nD\nand V pulses, see Figure 3a-c). Here the target weights (conductance) are manually set to demonstrate\nG\nthat arbitrary weight (conductance) can be achieved within the designed range based on our three-step\nprocesses.\nReferences:\nR1 Frémaux N, Gerstner W. Neuromodulated spike-timing-dependent plasticity, and theory of three-\nfactor learning rules. Frontiers in neural circuits 2016, 9: 85.\nR2 Gerstner W, Lehmann M, Liakoni V, Corneil D, Brea J. Eligibility traces and plasticity on behavioral\ntime scales: experimental support of neohebbian three-factor learning rules. Frontiers in neural circuits\n2018, 12: 53.\n2. The authors should explicitly clarify the Training Mode used in the autonomous\ndriving demonstration. The Methods section states that the environment is \"simulated\nby Python\". The manuscript must state whether the experiment was (A) Fully In-Situ:\nwhere the FeS-FET array physically receives pre/post spikes and reward signals, and\nthe conductance updates occur naturally via the claimed polarization mechanisms; or\n(B) Hardware-in-the-Loop: where the weight updates are calculated digitally (in\nPython/MCU) and then \"written\" to the array using the closed-loop scheme mentioned\nin Source. If it is (B), the claims regarding implementing the algorithm are overstated,\nas the device is acting merely as a programmable resistor rather than a computational\nunit.\nResponse: We thank the reviewer for the suggestions. As explained in the previous\nresponse, we adopted Scenario A: the FeS-FET array physically receives pre/post\nspikes and reward signals, and the conductance updates occur naturally via the claimed\npolarization mechanisms (see the Methods section). All experiments and simulations in\nthe manuscript were completed in strict adherence to the three-step computational\nprocess (STDP, eligibility trace, and reward modulation). The neural network\nsimulation was implemented in Python, while the autonomous driving scenario was\nconstructed in CoppeliaSim and interacts with the network (Supplementary Fig. 15).\nThe PCB/MCU serves solely as a control unit responsible for tasks such as device port\nselection and pulse application. The actual calculation of the weight update is realized\nintrinsically through the ferroelectric polarization and relaxation within the device\nunder pulse stimulation (Fig. 3), rather than being computed by an external unit and\nexplicitly written into the device. The specific R-STDP computation process described\nin the manuscript is as follows (including Supplementary Fig. 22): Pre- and post-\nsynaptic pulses are applied to the drain and source, establishing an STDP effect that\ndecays over time due to ferroelectric relaxation (acting as an eligibility trace). After a\ncertain delay, a reward signal pulse is applied to the gate, which interacts with this\ndecaying state to jointly produce the final modulation of the channel conductance\n(synaptic weight).\n3. The authors claim an energy consumption of 65 pJ per R-STDP event. However, this\nis a device-level metric. As noted in Supplementary Note 1, the PCB system power is\nsignificantly higher (~14.19 mW). While the FeS-FET efficiency is notable, in this\nspecific architecture, the peripheral overhead (ADC/DAC, control logic for the closed-\nloop writing) dominates. The manuscript should transparently acknowledge that while\nthe synaptic element is efficient, the current system implementation relies heavily on\nperipheral overhead to manage the\"iterative weight updates, which compromises the\noverall system efficiency.\nResponse: We thank the reviewer for the suggestions. It is a legitimate concern that\nvarious peripherals such as A/D, D/A converters consume a major portion of the power\nused in a mixed digital-analog signal system. This is a common issue prevalent in\ncurrent mainstream energy-efficient hardware solutionsR1, R2. This is because our\ncurrent PCB platform is implemented using commercial off-the-shelf (COTS)\ncomponents, rather than a custom-designed Application-Specific Integrated Circuit\n(ASIC). High power consumption is an inherent characteristic of discrete components\nand a common issue in such prototypes. Utilizing more energy-efficient MCU and\namplifier (Ambiq Apollo, TI LPV821) is expected to reduce the circuit power\nconsumption to the microwatt (μW) range while maintaining full functionality.\nIntegrating peripheral control circuits using advanced process nodes (e.g., 28 nm) can\nfurther reduce power consumptionR3, R4.\nIn addition, although beyond the scope of this work, the future peripheral circuits are\nnot limited to CMOS technology only. For instance, recently reported energy-efficient\nhardware based on memristive ADCs/DACs is better suited for novel neuromorphic\ncomputing architecturesR5.\nTo make this point clearer, we have made the following modifications in the revised\nmanuscript in page 11:\n“Furthermore, it exhibits low operating energy consumption, approximately 65 pJ\nper R-STDP event (Supplementary Fig. 14), demonstrating a significant advantage over\ncomparable devices (Supplementary Table 1). Therefore, it indicates the significant\npredominance in area, energy and latency of the hardware SNN system for RL.\nMeanwhile, the power consumption of the PCB control circuit is significantly higher\nthan that of the device itself (Supplementary Note 1). Future improvements are expected\nto achieve much higher energy efficiency through custom on-chip integration52, 53 or\nnovel memristor-based ADC54.”\nReferences:\nR1 Li, Can, et al. \"Efficient and self-adaptive in-situ learning in multilayer memristor neural\nnetworks.\" Nature communications 9.1 (2018): 2385.\nR2 Yao, Peng, et al. \"Fully hardware-implemented memristor convolutional neural\nnetwork.\" Nature 577.7792 (2020): 641-646.\nR3 Wan, Weier, et al. \"A compute-in-memory chip based on resistive random-access\nmemory.\" Nature 608.7923 (2022): 504-512.\nR4 Verma, Naveen, et al. \"In-memory computing: Advances and prospects.\" IEEE solid-state circuits\nmagazine 11.3 (2019): 43-55.\nR5 Hong, Haiqiao, et al. \"Memristor-based adaptive analog-to-digital conversion for efficient and\naccurate compute-in-memory.\" Nature Communications 16.1 (2025): 9749.\nReviewer #3 (Remarks to the Author):\nThe authors have satisfactorily addressed the majority of the reviewer’s questions and\nhave improved the clarity of the manuscript and the discussions. The paper presents\nuseful experimental data and contains elements of novelty that may be of interest to the\ncommunity.\nHowever, important concerns remain regarding the technological scalability of the\nproposed approach. In particular, the reliance on mechanical exfoliation inherently\nlimits compatibility with large-scale integration. While the manuscript mentions the\npossibility of realizing α-In₂Se₃ through wafer-scale growth techniques and briefly\nalludes to integration on standard silicon substrates, these aspects remain largely\nconceptual and are not substantiated by a concrete process pathway.\nResponse: We thank the reviewer for recognizing the novelty of our work. We fully\nagree with the reviewer’s constructive comments concerning technological scalability\nWhile the primary objective of this work is to elucidate the intrinsic physical\nmechanism of R-STDP in ferroelectric semiconductors using high-quality single\ncrystals, we recognize that outlining a concrete path toward large-scale integration is\nessential for the practical adoption of this technology. Recent literature has already\ndemonstrated large-scale, high-quality growth processes for In Se R1. The roadmap for\n2 3\nits wafer-scale fabrication can mirror that of more mature 2D materialsR2, such as MoS .\n2 3\nintegration, following the successful trajectory of MoS\nas a methodological demonstration of the principle. We are confident that material\ngrowth challenges will be gradually addressed as the field advances.\nIn addition, device-to-device variability and control are not adequately addressed.\nWhile this limitation is likely intrinsic to the current exploratory nature of the\ntechnology and may not be fully resolvable within the present experimental framework,\nit nonetheless weakens the case for practical adoption. But I understand that these\naspects cannot be fully addressed in this more exploratory paper.\nResponse: We thank the reviewer for acknowledging our response. We also deeply\nappreciate the reviewer's understanding that this exploratory work, by its nature, cannot\nbe exhaustive in every aspect. We fully agree with the reviewer’s constructive\ncomments concerning device-to-device variability.\nIn the revision we have validated via simulation that the proposed computing scheme\npossesses a degree of tolerance towards D2D variations. Similar to the challenge of\nlarge-scale material growth discussed above, addressing this issue also relies on\nadvancements in the broader field. Large-scale, high-quality single-crystal In Se is\n2 3\nexpected to exhibit superior performance and significantly lower D2D variations. As\nan emerging ferroelectric semiconductor, the synthesis techniques for InSe are steadily\nevolving, and we are confident that future progress in the field will eventually overcome\nthis limitation.\nReferences:\nR1 Han, Wei, et al. \"Phase-controllable large-area two-dimensional In2Se3 and ferroelectric heterophase\njunction.\" Nature nanotechnology 18.1 (2023): 55-63.\nR2 Akinwande, Deji, et al. \"Graphene and two-dimensional materials for silicon\ntechnology.\" Nature 573.7775 (2019): 507-518.\nR3 Das, Saptarshi, et al. \"Transistors based on two-dimensional materials for future integrated\ncircuits.\" Nature Electronics 4.11 (2021): 786-799.\nR4 Liu, Chunsen, et al. \"Two-dimensional materials for next-generation computing\ntechnologies.\" Nature nanotechnology 15.7 (2020): 545-557."}]

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