Coupled polarization dynamics and charge tunneling enable reconfigurable heterojunctions

Domain: biology
Published: 2026-03-16
Editorial outcome: major_revision

Abstract
Layered CuInP₂S₆ provides robust ferroelectric polarization and strong local fields, enabling low-voltage, nonvolatile modulation, multilevel states, and analog weight updates for neuromorphic devices. However, devices driven solely by CuInP₂S₆ suffer from limited tunability and single-mechanism control inadequate for large-scale complementary logic and heterogeneous integration. In this work, we construct a ferroelectric heterostructure that simultaneously regulates ferroelectric polarization and charge tunneling, enabling nonvolatile memory operation with an on/off ratio exceeding 106, endurance up to 105 cycles, and stable retention of 16 distinct memory states for over 103 s. The distinct modulation effects of polarization and tunneling on channel transport enable controllably reconfigurable adjustment, yielding a high diode rectification ratio. By exploiting the difference between the coercive voltage and the tunneling threshold, multimode regulation of junction configurations (including nn, np, pp, and pn junctions) is realized. In addition, the device achieves logic-in-memory functionality within a single cell. Such a coupled polarization dynamics and tunneling effect enables the device to achieve high integration, energy efficiency, and multifunctionality, effectively reducing circuit complexity for next-generation intelligent computing, sensing, and edge applications.

Introduction
The rapid proliferation of memory-intensive applications has placed unprecedented demands on data processing speed and energy efficiency1-3. Constrained by Moore’s Law and the intrinsic separation of memory and processing in the von Neumann architecture, conventional CMOS-based field-effect transistors (FETs) face fundamental limits in scaling, energy efficiency, and data transfer latency4, 5. These constraints underscore the urgent need for disruptive innovations in material platforms, device architectures, and the fusion of multiple physical mechanisms to overcome integration complexity and computational inefficiencies6-8. Recently, reconfigurable FETs (RFETs) have realized polarity-programmable characteristics through physical mechanisms such as charge trapping, graded doping, and ferroelectric polarization, enabling n/p-type switching and reducing the number of transistors required for implementing conventional CMOS-based logic gates, thereby simplifying circuit complexity9-11.

Research on RFETs has made notable progress in the areas of logic circuits and neuromorphic computing12-15. However, the modulation of polarity types such as n-type and p-type in these RFETs typically requires constant gate bias for control, which leads to additional static power consumption16. Ferroelectric materials, owing to their ability to exhibit spontaneous polarization in the absence of an external electric field, have been employed to control the polarity of RFETs17, 18. Nonetheless, their implementation typically requires the use of split-gate structures to enable reconfigurable diode behavior, thereby increasing fabrication complexity. In parallel, semi-floating gate (SFG) structures can also enable logic-in-memory computing operations without relying on constant gate bias19-21. However, most of these are limited to single-mode modulation between np and pn junctions, resulting in relatively restricted reconfigurability. In addition, RFETs that modulate np or pn junctions inherently generate built-in electric fields, which potentially can enable photovoltaic and photodetection functionalities. This also allows the devices to benefit from the advantages typically associated with photovoltaic response, such as low power consumption, fast response, and low dark current, thereby further extending device multifunctionality. However, the integration of memory, logic, and photodetection within a single unit remains highly challenging.

In this work, we design a ferroelectric floating-gate reconfigurable transistor (FeFGRT) based on the molybdenum telluride/hexagonal boron nitride/copper indium phosphorus sulfide-multilayer graphene (MoTe2/hBN/CIPS-MLG), ultimately realizing an all-in-one electronic device. Relying on the characteristics of ferroelectric polarization and charge tunneling, the device exhibits highly robust memory properties, and non-volatile reconfigurable characteristics, enabling the device to demonstrate ultra-long retention, stable endurance, and multi-bit characteristics. Through the coupling of ferroelectric and floating-gate characteristics, reconfigurable behavior with controllable multi-mode modulation (including nn, np, pp, and pn junctions) is achieved, wherein the rectification ratio in the np and pn configurations exceeds 104. Under 520 nm illumination, the device demonstrates stable self-powered operation, exhibiting high responsivity (R) and detectivity (D*), thereby highlighting its strong potential for photodetection applications. By leveraging different electrical configurations, we realize multiple logic-in-memory functions within a single device, achieving significant reductions in the number of transistors compared to conventional CMOS-based logic gates. Furthermore, under an optoelectronic integrated configuration, the coupling of photovoltaic and reconfigurable characteristics enables the implementation of AND logic-in-memory operation at zero external bias. Collectively, our device serves as an all-in-one platform that integrates memory, computing, logic, and photodetection functionalities, significantly simplifying integrated circuit design while enabling advanced applications such as edge computing and secure data processing.

Results
Device structure and functional features.
Figure 1a shows an optical image of the device, which consists of vertically stacked MoTe /hBN/CIPS–MLG heterostructure on a SiO /p++ Si substrate. In this structure, MoTe serves as the channel, hBN functions as both the dielectric and tunneling layer, CIPS acts as the ferroelectric dielectric layer, MLG serves as the floating gate, and p++ Si serves as the control gate. The MoTe channel rests on hBN, which itself is divided beneath into two regions: CIPS on one side and MLG on the other, as shown in Fig. 1b. Raman spectra acquired at room temperature with a 532 nm laser (Supplementary Fig. 1) confirm the quality and characteristics of the constituent materials within the heterostructure. The Raman peaks of the above materials are consistent with previously reported results22. The Raman spectra collected from the heterostructure region show no peak shifts or omissions, confirming the successful construction and high quality of the heterostructure. Moreover, our device can also function as a ferroelectric FET (FeFET) and a floating-gate FET (FGFET), depending on the different regions of operation, as indicated by the blue dashed line and red dashed line, respectively. In addition, four electrodes (E1, E2, E3, and E4) were defined on the MoTe₂ channel, along with a floating-gate electrode (FG) on the MLG layer, using electron-beam lithography, followed by thermal evaporation of Cr/Au (5 nm/50 nm).

Figure 1c provides a schematic of the FeFET and depicts the physical mechanism governing its memory behavior under electrical pulse stimulation. After applying a negative electrical pulse to the control gate, the ferroelectric polarization in the CIPS layer is driven downward by the external electric field and remains stabilized, resulting in upward band bending in the MoTe and the formation of a hole accumulation layer. The hBN layer, inserted between the CIPS and MoTe , can address the electric loss in CIPS dielectric and restrain ion diffusion23. On the other hand, after applying a positive voltage, the ferroelectric polarization in the CIPS layer is driven upward by the external electric field and remains stabilized, resulting in downward band bending in the MoTe and the formation of an electron accumulation layer. Figure 1d presents a schematic of the FGFET structure along with its charge storage mechanism. When a positive pulse is applied to the control gate, electrons tunnel from the MoTe into the MLG under the influence of the electric field. The MLG, with its high electron affinity and large density of states, enhances charge storage capacity24. Conversely, when a negative pulse is applied to the control gate, holes tunnel from the MoTe into the MLG. We characterize the interfacial quality of the heterostructure using scanning transmission electron microscopy (STEM) and identified the individual layers through Energy-dispersive spectrometry (EDS) mapping. Figures 1e–f present the cross-sectional TEM and EDS results of the heterostructures for the FeFET and FGFET, confirming the high-quality interfaces of the constructed heterostructures. Meanwhile, Supplementary Fig. 2 shows that our device exhibits good uniformity and flatness over a large area, indicating good contact between the different constituent materials and no interference from impurities or bubbles.

Figures 1g–h illustrate that the FeFGRT exhibits non-volatile reconfigurability under electrical pulse stimulation, enabling its application in logic-in-memory circuits. The height information of the different materials is provided in Supplementary Fig. 3. In addition, the well-defined butterfly-shaped amplitude–voltage loop in Supplementary Fig. 4a and the distinct 180° phase switching observed in Supplementary Fig. 4b confirm the robust ferroelectric polarization in the CIPS nanosheets. The small coercive voltage observed in the hysteresis loop further indicates that the polarization orientation in the CIPS nanosheets can be effectively modulated by relatively low gate voltages. Based on the multifunctional characteristics described above, our FeFGRT device shows great potential for the development of integrated applications in memory, logic computing, and photodetection. Notably, due to the opposing influences of ferroelectric polarization and charge tunneling on the channel under the same pulse stimulus, a negative voltage pulse induces p-type mode in the channel region above the CIPS layer and n-type mode in the region above the MLG, resulting in the formation of a homojunction np junction without relying on a split-gate architecture, as shown in Fig.1g. Similarly, a positive pulse reverses this configuration, as illustrated in Fig. 1h. This capability of achieving non-volatile reconfigurable modulation with a single electrical pulse allows our device to implement logic-in-memory circuits. The drain–source voltage (V DS) and control gate voltage (V CG) serve as two logic inputs , while the drain–source current (I DS) functions as the logic output. Using this scheme, both XNOR and NOR in-memory logic operations can be implemented with a single transistor, reducing the number of transistors from 8 to 1 for XNOR, and from 2 to 1 for NOR, compared to conventional CMOS-based current-output logic gate circuits. When illuminated, the pn junction exhibits self-powered characteristics.

Moreover, taking advantage of the distinct threshold voltages (V th) for ferroelectric polarization (V th Fe) and charge tunneling (V th tl) — where the V th tl is usually higher25—enables independent control of the FeFET polarization. By applying a small positive/negative pulse to the device in the np/pn junction, the state can be switched to the nn/pp mode, as shown in Fig. 1i/1j. Following this scheme, a pair of voltage pulses can be applied as two logic inputs. The first pulse exceeds the V th tl, while the second falls between the V th tl and V th Fe. By assigning positive and negative voltages to logic “0” and “1,” respectively, an NAND logic operation can be implemented using only one transistor. In summary, our device demonstrates considerable potential in memory, computing, logic, and photodetection, providing a solution for simplifying integrated circuit designs and enabling logic-in-memory computing.

The robust non-volatile memory characteristics and distinct V th of FGFET and FeFET modes.
As shown in Fig. 2a, the FGFET demonstrates stable n-type and p-type memory windows under bidirectional V CG sweeps. A linear increase in both memory window sizes is observed with increasing sweep range, as depicted in Fig. 2b. To evaluate the charge storage capability of the MLG, we assessed the charge storage density based on the n-type and p-type memory windows. As calculated using the equation (n = ΔV FG−CG × C / q), the storage densities for both electrons and holes exceed 1012 cm-2, highlighting the considerable potential of our FGFET for multi-bit memory applications3. Our FGFET device exhibits robust endurance after 104 program/erase cycles, with no significant shift in the on and off states or noticeable charge leakage, as shown in Fig. 2c. Figure 2d illustrates the multi-bit and retention characteristics of the FGFET. Sixteen distinct conductance states exhibit negligible drift over a timescale of 1000 seconds, demonstrating excellent retention stability. These results reveal the advantages of our device in multi-level storage and programmable conductance, enabling the integration of memory and computing, and making it a promising candidate for neuromorphic computing applications.

Figure 2e-f illustrate the programming and erasing performance of the FGFET under pulses with different amplitudes and widths. It is noteworthy that at a pulse amplitude of ±5 V, the device fails to switch states regardless of pulse width, implying that the resulting electric field is inadequate to induce effective charge tunneling. In contrast, with increasing pulse amplitude, successful programming and erasing operations can be achieved, indicating that the higher electric field is sufficient to drive charge tunneling. Prior to equilibrium, the band alignment of the FGFET (Supplementary Fig. 5) shows that the electron tunneling barrier is substantially lower than that for holes. Therefore, complete erasure requires smaller pulse amplitude and width than full programming. To investigate the carrier tunneling process, numerical calculations and simulations were performed based on the Fowler–Nordheim (FNR) tunneling mechanism and a quantum tunneling transport model, as shown in Supplementary Fig. 6. Furthermore, ultrafast pulse measurements were carried out experimentally, demonstrating a pulse response as short as 40 ns, which highlights the device’s potential for high-speed memory applications, as shown in Supplementary Fig. 7.

Figure 2g displays a typical ferroelectric hysteresis, confirming that our device can function as a FeFET. Moreover, the nearly centrosymmetric distribution of the positive and negative ferroelectric switching currents I G indicates that the imprint effect is negligible26. Figure 2h-i show the programming and erasing operations of FeFET. Erase and program operations were successfully achieved in the FeFET device under -/+5 V, 1 ms pulses, underscoring the distinct V th characteristics between FeFET and FGFET. Generally, FeFET requires lower voltages to switch between on and off states under identical operating conditions25. As evidenced by the Supplementary Fig. 8, noticeable differences between FeFET and FGFET are also observed under scanning mode. Based on this, selective programming of the FeFET can be achieved at low voltages without affecting the properties of the FGFET, offering a novel approach for the design of multimodal, tunable programmable RFET.

The multi-modally tunable reconfigurable properties of FeFGRT enabled by the coupling between ferroelectric polarization and charge tunneling effects.
Under identical pulse conditions, ferroelectric polarization and charge tunneling exert opposite effects on the MoTe channel, leading to the formation of pn or np homojunctions under positive or negative pulse stimulation, respectively. Moreover, since the coercive voltage is significantly lower than the tunneling voltage, it is possible to selectively switch the FeFET via low-voltage programming without altering the state of the FGFET. As a result, small negative or positive pulses can be applied to the existing pn or np homojunctions to achieve pp or nn configurations, respectively. Furthermore, due to the non-volatile nature of both mechanisms, all four modes (pn, np, pp, and nn) exhibit stable retention. As shown in Fig. 3a, the output characteristics of the four configurations under a ±1.5 V sweep demonstrate distinct behaviors. Notably, the pn and np modes exhibit an ultrahigh rectification ratio exceeding 104, along with insignificant reverse currents. It is worth noting that the modulation of nn and pp modes typically requires a dual-gate architecture. However, in our design, all four modes are achieved using a single control gate, significantly simplifying the fabrication process. Figure 3b-c further demonstrate the non-volatile and multimodally reconfigurable modulation capability of our FeFGRT device. Starting from an initial np configuration, the device transitions to the nn state after applying four consecutive positive pulses (+3 V, 1 s). Conversely, four consecutive negative pulses (−3 V, 1 s) enable the transition from a pn to a pp configuration. Such multimodal tunability is not achievable in conventional SFG reconfigurable devices. To further validate the reconfigurability of our FeFGRT device, transfer characteristics were measured after applying both positive and negative gate pulses, enabling further modulation of the transistor polarity, as shown in Fig. 3d. Since the voltage sweep range is relatively small, it does not affect the charge tunneling process. A more detailed modulation process is provided in Supplementary Fig. 9.

Beyond the np-to-nn and pn-to-pp modulation modes, our FeFGRT device also enables reversible switching between np and pn states, highlighting its versatile reconfigurability. The capability of achieving flexible transitions among nn, pp, np, and pn modes within a single device greatly simplifies logic computation and reduces the design complexity of integrated circuits. As illustrated in Fig. 3e-f, the switching between pn and np configurations is achieved by varying the number of applied pulses.

The resulting output characteristic heatmaps exhibit a highly symmetric distribution, comparable to that obtained through dual-gate modulation.

To further investigate the reconfigurable operating mechanism, we analyze the field-driven band alignment configurations, as shown in Fig. 3g–j. When a large negative pulse is applied to the control gate, both ferroelectric polarization and charge tunneling occur simultaneously. In the FeFET region, the downward polarization of CIPS leads to upward band bending in MoTe , resulting in hole accumulation. Meanwhile, in the FGFET region, holes tunnel into the MLG under the electric field, inducing electron accumulation in the upper MoTe channel. Consequently, an overall np homojunction is formed in the FeFGRT device (Fig. 3g). In contrast, large positive pulses cause the MoTe₂ channel to form a pn homojunction (Fig. 3h). On the basis of the pn configuration, applying a small negative pulse induces downward polarization in the FeFET without affecting the FGFET, thereby forming a pp homojunction (Fig. 3i). Similarly, starting from an np configuration, a small positive pulse enables the transition to an nn homojunction (Fig. 3j).

Multimodal Reconfigurable Characteristics and Self-Powered Behavior of the FeFGRT.
Meanwhile, by applying a voltage to the V FG, the polarity of the channel above the MLG layer can be modulated, enabling functionality analogous to that of a SFG reconfigurable transistor. As shown in Figs. 4a–b, increasing the positive bias of V FG gradually forms an enhanced np junction (Fig. 4a), while applying the corresponding negative bias creates an enhanced pn junction (Fig. 4b), thereby providing finely tunable output characteristics. The corresponding channel currents were extracted at V DS = -1.5 V and +1.5 V for the np and pn junctions, respectively, as illustrated in Supplementary Fig. 10. This trend underscores the precise tunability and high controllability of the all two-dimensional REFT device. It should be emphasized that Figs. 4a–b are intended solely to demonstrate the multi-mode reconfigurability of the FeFGRT device. In the subsequent investigation of its photovoltaic properties, a nonvolatile pn junction defined by gate pulses is employed.

Upon withdrawal of the programming pulses, the stabilized ferroelectric polarization and charge trapping mechanisms effectively preserve the configured pn/np junction states, enabling robust non-volatile operation. Under the illumination of 520 nm with increasing power intensity (P in), a significant increase and horizontal shift in current can be observed in the pn-configured device, demonstrating pronounced photoresponse and self-powered capability (Fig. 4c). We further investigated the relationship between short-circuit current (I sc), open-circuit voltage (V oc), and incident light power. As shown in Fig. 4d, V oc exhibits a logarithmic dependence on light intensity, while I sc increases linearly with incident power, indicating that the photocurrent generation is dominated by a well-defined photovoltaic effect. Furthermore, by fitting the photocurrent data using a power-law relationship (I ph ~ P in γ), we obtained a γ value of approximately 0.98, indicating a strong linear dependence of the photocurrent on incident power. This behavior closely approaches that of an ideal photodiode, where γ tend toward 127.

Figure 4e shows a representative normalized on–off photoresponse under 520 nm illumination. The rise and decay times are approximately 3.7 ms and 4.3 ms, respectively, extracted between 10% and 90% of the maximum photocurrent. Figure 4f illustrates that the device maintains a robust self-powered response across a range of P in, confirming its stable switching characteristics and excellent reproducibility in photodetection applications. The photoresponse performance of the photodetector can be comprehensively evaluated by key figures of merit including R, D*, and external quantum efficiency (EQE), fill factor (FF), which are calculated based on equations (1-3).

I ph = I light - I dark / P in * S (1)

D* = R * √S / √2eI dark (2)

EQE = R * hc / eλ (3)

Where I light and I dark represent the current under illumination and dark current, respectively, S is the effective area of the channel, h is Planck’s constant, e is the elementary charge, λ is the incident light wavelength, and c is the speed of light. As shown in Fig. 4g–h, the FeFGRT device exhibits a R of 383 mA/W, a specific D* of 2.7 × 1012 Jones, and an EQE of 91.4% under 520 nm illumination at a P in of 0.108 mW/cm². These high values of R, D*, and EQE underscore the excellent self-powered photodetection capability of the FeFGRT. Furthermore, we benchmarked the R and D* of our device against various state-of-the-art two-dimensional photodetectors, as shown in Fig. 4i, where the superior performance metrics position our FeFGRT among the most competitive candidates in this field12, 28-34.

XNOR, NOR, and NAND logic-in-memory computing functions were successfully implemented based on the FeFGRT device.
We demonstrated the logic-in-memory computing capability of the FeFGRT device, as illustrated in Fig. 5. Notably, the XNOR gate serves as a fundamental component in decision-making and comparison circuits, playing a crucial role in address recognition and data encryption/decryption processes35. We utilized V CG and light as dual logic inputs and I DS as the output to implement the XNOR logic operation. According to Fig. 5a(i), when a positive programming pulse of +20 V is applied to the control gate, the ferroelectric layer polarizes upward, inducing electron accumulation in the MoTe channel beneath the CIPS layer. Simultaneously, electrons tunnel from the channel into the MLG and become trapped, generating a local electrostatic field. This field induces p-type doping in the MoTe channel above the MLG, forming a pn junction. Upon illumination, when V DS is set equal to V OC, the photovoltaic effect keeps the channel in the off state. Notably, due to the nonvolatile nature of both ferroelectric polarization and charge trapping in the MLG, the logic states remain stable even after the removal of the operating voltage. In contrast, when a –20 V programming pulse is applied to the control gate, the ferroelectric polarization is directed downward, inducing hole accumulation in the MoTe channel above the CIPS layer due to the electric field. Simultaneously, holes tunnel from the channel and become trapped in the MLG, generating a localized electrostatic field. This field leads to n-type doping of the MoTe channel and results in the formation of an np junction, as shown in Fig. 5a(ii). Under reverse bias, illumination leads to an increase in the reverse current due to the generation and separation of photocarriers. When only a single +20 V or −20 V gate voltage pulse is applied without illumination, the channel can be configured into a pn or np junction, respectively, corresponding to forward biased and reverse biased conditions, as shown in Fig. 5a(iii, iv). The measured absolute values of I DS (Fig. 5b) and the corresponding truth table (Fig. 5c) confirm the realization of distinguishable logic states, while also highlighting the stable retention characteristics of each output state. For XNOR logic with current output, remarkably, a single FeFGRT device can implement the logic function, reducing the number of transistors required compared to traditional CMOS-based logic circuits from 8 to 1—corresponding to an 87.5% reduction.28, 36. This significant simplification highlights the superior potential of FeFGRT devices in terms of enhancing integration density and reducing circuit complexity.

In addition, in-memory NOR logic can be further implemented by configuring two different gate voltage pulses while fixing V DS at 1 V. When two consecutive −20 V pulses are applied, the channel is configured into an np junction, and the reverse biased I DS remains in the off state (Fig. 5d(i)). When only a single −20 V pulse is applied, the channel configuration remains the same, and I DS still stays in the off state (Fig. 5d(ii)). In contrast, when a +20 V pulse is first applied to configure the channel into a pn junction, followed by a −20 V pulse that switches the channel configuration to an np junction, the channel remains in the off state (Fig. 5d(iii)). However, when only a single +20 V pulse is applied, the channel is configured into a pn junction, and the forward biased channel switches to the on state (Fig. 5d(iv)). Figures 5e-f show the output results under different configurations and the corresponding truth table, respectively. In addition, for the NAND logic-in-memory operation, Fig. 5g (i–iv) illustrates the mechanism diagrams based on V th differences. The input states “00”, “10”, “01”, and “11” correspond to four reconfigurable channel states: pn, nn, pp, and np, respectively. Under a fixed V DS = 1 V, the logic outputs of I DS are 1, 1, 1, and 0, respectively, which conform to the NAND logic-in-memory behavior and truth table, as shown in Fig. 5e–f. In addition to the advantages of logic-in-memory, for NAND logic with current output, the number of transistors is reduced from 2 to 1, yielding a 50% hardware saving 37.

By combining the reconfigurable characteristics with photovoltaic behavior, an AND logic gate operation can be realized, as demonstrated in the Supplementary Fig. 11. Here, the gate pulse and incident light act as dual inputs, while V DS is held at 0 V and I DS is considered as the logic output. Therefore, complex logic functionalities can be implemented based on a single FeFGRT unit without the need for additional control terminals or peripheral circuits, offering a feasible route toward multifunctional logic-in-memory devices. Supplementary Figure 12 shows the logic circuit diagrams for implementing XNOR and AND functions using both FeFGRT-based and conventional NMOS-based designs. Supplementary Figure 13 presents a comparison of the XOR, NOR, and NAND logic implementations under voltage output conditions. A clear reduction in circuit complexity and the number of transistors can be observed with the FeFGRT-based logic-in-memory structure.

Methods
Construction of heterostructure and fabrication of device.
Firstly, the graphene flake is exfoliated on the polydimethylsiloxane (PDMS) substrate and is transferred onto the 285 nm SiO /Si substrate by a typical dry-transfer technique. The CIPS nanosheets exfoliated from the crystal (purchased from Shanghai Onway Technology Co., Ltd.) are transferred onto the side of graphene using PDMS, and then hBN is stacked on top of the CIPS- graphene layer. The same transfer technique is used again to transfer the channel MoTe layer on top of the hBN layer. The silicon substrate with our device is spin-coated with poly (methylmethacrylate) (PMMA) 950 A4. The spin speed is 500 rpm for the first 10 s and is increased to 4000 rpm for 60 s. The sample is baked at 120 °C on a hot plate for 2 mins. Next, electron beam lithography (EBL) is used to expose the pre-designed electrode pattern, and then a typical developing process is employed. Finally, Cr/Au (5 nm/50 nm) electrodes were deposited by a thermal evaporator, followed by a lift-off process in acetone lasting for 1 hour.

Electrical characterization.
The electrical measurements of the devices were performed at room temperature and in vacuum, using the Agilent B1500A semiconductor parameter analyzer and the probe station (CRX-6.5K, Lake Shore). The ultrafast voltage pulses are applied by the B1525A (HV-SPGU) module.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The authors propose a multilevel heterostructure with ferroelectric properties based on the molybdenum telluride/hexagonal boron nitride/copper indium phosphorus sulfide-multilayer graphene (MoTe2/hBN/CIPS-MLG) material stack, within a floating gate transistor geometry (MLG is the floating gate, hBN is the gate tunnelling layer, CIPS the ferroelectric layer, and the MoTe2 the channel layer).\nAccording to the authors this device can be operated either as a FEFET or a FGFET depending on the top source-drain electrodes and gate pads (control gate or side floating gate) used.\nThe device exhibits multifunctional properties depending on the bias applied and selection of various contacts. The main argument by the authors is that their approach is simpler than split gate approaches used in other FGFET, however it seems that also their device configuration is too complex. The device has at least 4 different pads to be used as source/drain pair of contacts, and two different gates (control gate for the FEFET operation and side Floating gate for the FGFET).\nDespite this complexity that counteracts this work’s main motivation, the device can be used either as a FEFET or a FGFET using the same material stack that is an added value. The authors provide sufficient data to support their findings.\nI could suggest the publication of the manuscript upon the authors address major comments below.\n1. The title sounds a little bit confusing and lacks clarity. It should be clarified what Tunneling refers to (charge tunneling? tunneling effects in general?), and besides the terms “controllable reconfiguration” sounds as tautology.\n2. At the beginning of the abstract, the authors refer to CuInP₂S₆ , however it should be clarified if they refer to bulk materials, single crystals, thin films, layered two dimensional material form such as nanosheets etc.\n3. The terms “high rectification ratio” and “multimode regulation” again are not specified. Only later in the introduction does the reader realize that the authors refer to diodes rectification ratio and controlling junctions type such as nn, np, pp, and pn junctions.\n4. No reference to any device performance metrics is present in the abstract. What is the maximum Ion/off ratio, as well as the endurance and retention of the nonvolatile memory? Overall, the abstract and title and abstract and title and abstract should be revised accordingly in order to clearly output the key message of the paper.\n5. There is some bad wording used in the document that probably comes from bad translation to English, for example “while reducing transistor count…” the authors probably wanted to say “while reducing transistors number…”. Besides, only later in the introduction part, the reader understands what the authors wanted to express with the above sentence. Specifically, their novel device geometry can be used to implement conventional CMOS-based logic gates with lower number of required transistors as a result of their device reconfigurability. All this should be described clearly in the text.\n6. The authors describe their device geometry as para-transistor (PT) that sounds again strange with no reference provided. Besides, at the end of the introduction, the reader realizes that the device exhibits also photovoltaic behavior and photodetection functions. The introduction should be expanded in order to cover all these aspects separately, and then collectively within a multi-functional device architecture. This will help the reader realize how the present study goes beyond the state of the art.\n7. Have the authors tested reference devices without having CIPS or / and MLG in the material stack?this will help to understand the role of each component\n8. The FET configuration is back gated using a highly doped Si substrate as a bottom gate. What is the role of SiO2?did the authors tried a different dielectric layer?are they using the silicon back gate in their measurements?\n9. There are many typos found in the manuscript (i.e., page 131: “when a negative positive pulse is applied to the control gate, holes tunnel from the MoTe2 into the MLG…). A careful check and revision of the manuscript is required.\n10. The image in Fig. s2a,b probably is better to be moved to maintext. It is easier to understand the different sections of the devices rather checking only the very compact and crowed information of Figure 1.\n11. The butterfly loop of Figure s4 is taken from an isolated flake different than the layer used for electrical measurements. What is the thickness of the flake used in Figure S4?is there any thickness dependence of ferroelectric properties of CIPS films?\n12. In Figure 2 for the FGFET I-V characteristics, a very high Vg is required despite the ultra thin dielectric layer. How do the authors comment on that? Is there any hint from the FN tunneling calculations on why a huge tunnel barrier is present, and how the structure can be optimized toward lower the required switching voltages? Based on ID-VG of Figure S8 for the FGFET, a strong current tunability is achieved with few V (i.e., -3V) that contrasts with the finding of Figure 2.\n13. In many places in the manuscript, the authors claim that their approach is less complex than the split gate approach requiring only one control gate. However, their device geometry is rather quite complex requiring separate control gate for the FE-based stack and a separate control gate for the floating gate configuration of the full device making their argument less strong. Besides, they have 4 top pads used for S/D contacts depending on the different device operation mode against only 2 pads used for standard FGFETs or FEFETs.\n14. Regarding Figure 4, the focus is demonstrating device operation as a solar cell or a photodetector? If the first is the case, then a power conversion efficiency should be provided for different illumination conditions. Based on their EQE data, they authors should extract the integrate current through their device and compare its amplitude with the current measured in J-V characteristics (deviations should be less than 5%).\n15. According to the authors, a nonvolatile pn junction defined by gate pulses is employed for the photovoltaic measurements. Only in this operation mode, a PV behavior can be measured, or similar behavior can be achieved under different gate conditions and thus operation modes?", "reviewer_2": "While the manuscript presents an interesting ferroelectric heterostructure concept, in its current form it does not provide sufficient novelty or experimental evidence to justify publication. The key device claims, particularly logic-in-memory functionality and multifunctional integration, are either already demonstrated in prior works or limited by practical constraints such as high operating voltages, limited endurance, and slow switching. Therefore, I cannot recommend this manuscript for publication. Below is the detailed reasons for this decision.\n1. The manuscript claims single-transistor XNOR functionality enabled by coupled ferroelectric polarization and tunneling. However, similar demonstrations of 1T logic-in-memory functions using ferroelectric FeFETs (especially HfO₂-based devices) have already been widely reported. The authors should clearly articulate how their approach provides a significant advantage over existing FeFET logic devices, especially given that the operating voltages here are relatively high compared to hafnia-based FeFETs. Without such clarification, the novelty of the contribution may appear limited.\n2. The proposed PT device requires four channel electrodes in addition to the gate, which complicates the structure. It is therefore not straightforward to categorize this as a true “single transistor” from an integration perspective. The authors should discuss whether this architecture offers any real advantage in terms of footprint or scalability compared to conventional CMOS or other reconfigurable transistor designs.\n3. Logic-in-memory applications require very high switching speeds to be compatible with conventional logic. However, tunneling-based mechanisms are inherently slower than charge displacement in ferroelectrics, which is why NAND flash memories are unsuitable for logic-in-memory. Indeed, the data here show that proper switching is not achieved for pulses shorter than ~100 ns, which raises concerns about practical speed limitations. The authors should clarify how this device can realistically function in logic-in-memory applications given these constraints.\n4. The endurance data presented extend only to ~10⁴ cycles. By contrast, logic-level endurance is typically benchmarked at ~10¹⁵ cycles, and even state-of-the-art hafnia FeFETs report endurance up to 10⁸–10¹⁰ cycles. For the device to be positioned as a viable logic-in-memory solution, more extensive endurance characterization or at least a discussion of this limitation is needed. The current endurance window is insufficient to support the strong claims made.\n5. While the manuscript emphasizes the integration of photodetection with memory and logic, the real advantage of such multifunctionality is unclear. Most transistors exhibit some degree of photoresponse, so it is not obvious what unique benefit is achieved by coupling ferroelectric polarization with tunneling in this context. The authors should better explain what concrete advantage is offered by combining these functionalities, beyond showing that each function is separately possible.", "reviewer_3": "In the manuscript ‘Modulation Effect of Coupled Polarization Dynamics and Tunneling for Controllable Reconfiguration in Ferroelectric Heterojunction’ by C. Li, et al., the authors report the design and demonstration of a para-transistor based on a MoTe₂/hBN/CuInP₂S₆ (CIPS)-multilayer graphene (MLG) stack. The key innovation is the coupling of ferroelectric polarization and charge tunneling, which enables multi-mode, nonvolatile reconfigurable operation within a single device. In addition, the device shows good photo-response, demonstrating responsivity ~ 500 mA/W, detectivity ~ 3.1x1012 Jones, and high EQE of 120 % under 520 nm wavelength illumination.\nThe contents in this study seems meaningful as it achieved multiple of functionality based on single transistor with parallel dielectric stack, showing various logic applications such as XNOR and NOR gate and photo-response characteristics.\nHowever, there are several statements to be reconsidered and questions need to be addressed to clarify the point of this manuscript. Especially, the second demonstration of XNOR gate in Figure 5 doesn’t make sense. Therefore, I do not recommend the manuscript to be published in Nature Communications in the current status. At least major is necessary regarding the following questions.\nQ1. In the manuscript, the authors are using the term ‘para-transistor’. I haven’t seems this terminology. As far as I understood, they might use the term due to the architecture where two different stack of h-BN/CHIPS and h-BN/MLG are located in parallel. To provide sufficient information, sufficient explanation or reference should be provided for this terminology.\nQ2. The transistor seems to have quite well-balanced ambipolar characteristics for hole and electron conduction (similar on-state current for p- and n-type conduction), which is usually hard to get. How the authors achieved this balanced ambipolar characteristics with simple Cr/Au contact? The author have to provide an explanation or reference on that point as this good ambipolar characteristics enabled the reconfigurable transistor functionality.\nQ3. Although the authors argue that this device can simplify the circuit design in the sentence “In summary, our device demonstrates considerable potential in memory, computing, logic, and photodetection, providing a solution for simplifying integrated circuit designs and enabling logic-in-memory computing.”, this argument doesn’t seem practically right. First of all, the design is considerably hard to be processed in fab. To realize the device integration based on the transistor shown in this study, CIPS and multilayer graphene should be deposited or transferred and then patterned in the same layer or in parallel. Is there any possible solution to overcome this limitation?\nQ4. For the electrical voltage signal used for logic gate applications, the voltage configuration seems different from conventional logic signals. For example, VDS value of ±1 V is used in the first XNOR operation. However, in common logic gates, the VDS value have to pick only one polarity (minus or plus, depending on the transistor type) as VDD voltage is usually fixed. VDS value of ±1 V doesn’t make sense in terms of practical logic operation. And in the second XNOR operation, VDS = 0 was used. It is trivial that we get zero current at VDS = 0. If the authors’ argument is right, single floating-gate transistor should be XNOR gate as well, because floating-gate transistor have the truth table as below, which is nonsense.\nInput A (gate pulse) Input B (VDS) Output (IDS)\nProgram pulse 1 1\nProgram pulse 0 0\nErase pulse 1 0\nErase pulse 0 0\nQ5. In page 5, the statement “Using this scheme, both XNOR and NOR in-memory logic operations can be implemented with a single transistor, reducing the transistor count from 8 to 1 for XNOR, and from 2 to 1 for NOR, compared to conventional CMOS-based logic gate circuits.” is exaggerated. In the demonstration in Figure 5, the output is current, not voltage output. In the real logic gate circuit, the output should be voltage readout. In this respect, the actual logic circuit exploiting the transistor in this study will require at least one more transistor or resistor. The manuscript should be revised regarding this point.\nQ6. The band diagram in Figure 1e is wrong. The band of MLG is not Dirac cone. It is parabolic.\nQ7. For photo-switching in Figure 4f, the speed or time constant of on and off operation need to be provided.\nQ8. For calculations of responsivity, detectivity in page 10, the authors introduced a quantity S, ‘effective’ area of the channel. The way how this quantity is defined have to be clarified.\nQ9. In photo-response, the device shows EQE over 100 %. This EQE is not able to be achieved in usual photo diode. What is the underlying mechanism for this EQE over 100 %? Is it photo-gating or is there other multiplication mechanism? If not, this value can be exaggerated due to not well defined channel area.\nThe quality of the data - Moderate.\nThe level of support for the conclusions – Not good.\nThe potential significance of the results – Good."}, "author_response": "Point-by-Point Response to Reviewers’ Comments\nWe thank the reviewers for carefully reading our manuscript and for your positive\ncomments. According to the reviewers’ comments, we have revised the manuscript\npoint by point and added more detailed data to improve its readability. We have also\nsupplemented the experiments and revised the manuscript to provide sufficient\nexperimental data and evidence to support our conclusions. The responses to the\nreviewers’ comments are marked in blue, and the corresponding revisions in the\nmanuscript are marked in red.\nReviewer #1\nThe authors propose a multilevel heterostructure with ferroelectric properties based on\nthe molybdenum telluride/hexagonal boron nitride/copper indium phosphorus sulfide-\nmultilayer graphene (MoTe /hBN/CIPS-MLG) material stack, within a floating gate\n2\ntransistor geometry (MLG is the floating gate, hBN is the gate tunnelling layer, CIPS\nthe ferroelectric layer, and the MoTe the channel layer).According to the authors this\n2\ndevice can be operated either as a FEFET or a FGFET depending on the top source-\ndrain electrodes and gate pads (control gate or side floating gate) used.\nThe device exhibits multifunctional properties depending on the bias applied and\nselection of various contacts. The main argument by the authors is that their approach\nis simpler than split gate approaches used in other FGFET, however it seems that also\ntheir device configuration is too complex. The device has at least 4 different pads to be\nused as source/drain pair of contacts, and two different gates (control gate for the\nFEFET operation and side Floating gate for the FGFET).\nDespite this complexity that counteracts this work’s main motivation, the device can be\nused either as a FEFET or a FGFET using the same material stack that is an added value.\nThe authors provide sufficient data to support their findings.\nI could suggest the publication of the manuscript upon the authors address major\ncomments below.\nReply:\nWe thank the reviewer for the positive evaluation of our work. We also appreciate\nthe detailed and constructive comments, which have significantly improved the clarity\nand readability of the manuscript. Following your insightful suggestions, the\nmanuscript has been substantially improved.\nRegarding your concern about the number of pads in our device, in order to avoid\nany confusion, we would like to clarify that the E1–E2 electrodes and the E3–E4\nelectrodes are intentionally designed to directly demonstrate that the same device\ncan operate in the FeFET and FGFET modes, respectively. Importantly, all these\npads are simultaneously defined and fabricated in the top electrode layer, without the\nneed for stepwise pre-embedded gate fabrication. Even without the E2 and E3\nelectrodes, stable and controllable reconfigurable operation of the device can still\nbe achieved. The additional pads are mainly introduced to clearly demonstrate the dual-\nmode operation and to experimentally verify the differences in programming threshold\nvoltages between the two modes, as well as their distinct effects on the channel under\nidentical stimuli.\nBelow, we provide a point-by-point response to your comments, and we hope that\nour explanations can address and clarify your concerns.\nComment 1:\nThe title sounds a little bit confusing and lacks clarity. It should be clarified what\nTunneling refers to (charge tunneling? tunneling effects in general?), and besides the\nterms “controllable reconfiguration” sounds as tautology.\nReply:\nWe thank you for pointing out the ambiguity in the original title. Following your\nsuggestion, we have revised the title to explicitly clarify that the tunneling refers to\ncharge tunneling and to avoid potentially redundant wording. The revised title more\nclearly reflects the physical mechanism and the reconfigurable operation demonstrated\nin this work.\nRevision:\nThe revised title is shown below:\n“Coupled Polarization Dynamics and Charge Tunneling Enable Reconfigurable\nHeterojunctions”.\nComment 2:\nAt the beginning of the abstract, the authors refer to CuInP₂S₆ , however it should be\nclarified if they refer to bulk materials, single crystals, thin films, layered two\ndimensional material form such as nanosheets etc.\nReply:\nWe thank the reviewer for the valuable comment. The beginning of the abstract has\nbeen revised to explicitly clarify that CuInP₂S₆ refers to a layered ferroelectric material.\nRevision:\nThe revisions to the abstract are as follows:\n“Layered CuInP S provides robust ferroelectric polarization and strong local\n2 6\nfields, enabling low-voltage, nonvolatile modulation, multilevel states, and analog\nweight updates for neuromorphic devices.”\nComment 3:\nThe terms “high rectification ratio” and “multimode regulation” again are not specified.\nOnly later in the introduction does the reader realize that the authors refer to diodes\nrectification ratio and controlling junctions type such as nn, np, pp, and pn\njunctions.\nReply:\nWe thank the reviewer for this valuable comment. To improve clarity, we have\nrevised the abstract to explicitly specify that the “high rectification ratio” refers to diode\nrectification, and that “multimode regulation” corresponds to the controllable\nreconfiguration of junction types (nn, np, pp, and pn). These clarifications have been\nincorporated into the revised abstract.\nRevision:\nThe revisions to the abstract are as follows:\n“The distinct modulation effects of polarization and tunneling on channel transport\nenable controllable reconfiguration, yielding a high diode rectification ratio. By\nexploiting the difference between the coercive voltage and the tunneling threshold,\nmultimode regulation of junction configurations (including nn, np, pp, and pn junctions)\nis realized.”\nComment 4:\nNo reference to any device performance metrics is present in the abstract. What is the\nmaximum on/off ratio, as well as the endurance and retention of the nonvolatile memory?\nOverall, the abstract and title should be revised accordingly in order to clearly output\nthe key message of the paper.\nReply:\nWe thank the reviewer for this valuable suggestion. Following this comment, we\nhave revised the abstract to explicitly include key device performance metrics,\nincluding the maximum pulse-defined on/off ratio (>106), endurance up to 105 cycles,\nand stable retention of 16 distinct memory states for over 1000 s. These additions are\nintended to more clearly highlight the key device performance and core contributions\nof this work. The title and abstract have been revised accordingly to better convey the\nmain message of the manuscript.\nRevision:\nThe revisions to the abstract are as follows:\n“In this work, we construct a ferroelectric heterostructure that simultaneously\nregulates ferroelectric polarization and charge tunneling, enabling nonvolatile memory\noperation with an on/off ratio exceeding 10⁶, endurance up to 10⁵ cycles, and stable\nretention of 16 distinct memory states for over 103 s.”\nComment 5:\nThere is some bad wording used in the document that probably comes from bad\ntranslation to English, for example “while reducing transistor count…” the authors\nprobably wanted to say “while reducing transistors number…”. Besides, only later in\nthe introduction part, the reader understands what the authors wanted to express with\nthe above sentence. Specifically, their novel device geometry can be used to implement\nconventional CMOS-based logic gates with lower number of required transistors as a\nresult of their device reconfigurability. All this should be described clearly in the text.\nReply:\nWe thank the reviewer for this insightful comment. In the revised manuscript, we\nhave rephrased the relevant sentence to explicitly state that the reduction in transistor\nnumber refers to the implementation of conventional CMOS-based logic gates enabled\nby the reconfigurable nature of the proposed device. This clarification has been revised\nin the Introduction to improve readability and avoid potential misunderstanding.\nRevision:\nThe revisions to the introduction are as follows:\n“Recently, reconfigurable FETs (RFETs) have realized polarity-programmable\ncharacteristics through physical mechanisms such as charge trapping, graded doping,\nand ferroelectric polarization, enabling n/p-type switching and reducing the number of\ntransistors required for implementing conventional CMOS-based logic gates, thereby\nsimplifying circuit complexity.”\nComment 6:\nThe authors describe their device geometry as para-transistor (PT) that sounds again\nstrange with no reference provided. Besides, at the end of the introduction, the reader\nrealizes that the device exhibits also photovoltaic behavior and photodetection\nfunctions. The introduction should be expanded in order to cover all these aspects\nseparately, and then collectively within a multi-functional device architecture. This will\nhelp the reader realize how the present study goes beyond the state of the art.\nReply:\nWe sincerely thank the reviewer for the constructive comments. In response to the\nconfusion regarding the term “para-transistor (PT)”, we have removed this terminology\nin the revised manuscript and instead define our device as a ferroelectric floating-gate\nreconfigurable transistor (FeFGRT). This designation more accurately captures the\nunderlying device architecture and operating mechanisms, which integrate ferroelectric\ntransistor behavior with floating-gate charge storage, while explicitly emphasizing the\nreconfigurable functionality demonstrated in this work.\nIn response to the reviewer’s comment regarding the photovoltaic and\nphotodetection functionalities, we have revised and expanded the Introduction\naccordingly. In the revised version, we first discuss that reconfigurable transistors can,\nin principle, enable photovoltaic and photodetection functionalities through the strong\nbuilt-in electric fields formed in modulated np or pn junctions. At the same time, we\nexplicitly point out the existing limitations and challenges associated with integrating\nmemory, logic, and photodetection within a single device unit, and relevant prior studies\nhave been cited for clarification. We hope that these revisions adequately address the\nreviewer’s concerns and clarify the motivation and scope of the present work.\nRevision:\nThe revisions to the Introduction are as follows:\n“In this work, we design a ferroelectric floating-gate reconfigurable transistor\n(FeFGRT) based on the molybdenum telluride/hexagonal boron nitride/copper indium\nphosphorus sulfide-multilayer graphene (MoTe\n2\n/hBN/CIPS-MLG), ultimately\nrealizing an all-in-one electronic device.”\n“In addition, RFETs that modulate np or pn junctions inherently generate built-in\nelectric fields, which potentially can enable photovoltaic and photodetection\nfunctionalities. This also allows the devices to benefit from the advantages typically\nassociated with photovoltaic response, such as low power consumption, fast response,\nand low dark current, thereby further extending device multifunctionality. However, the\nintegration of memory, logic, and photodetection within a single unit remains highly\nchallenging.”\nComment 7:\nHave the authors tested reference devices without having CIPS or / and MLG in the\nmaterial stack?this will help to understand the role of each component.\nReply:\nWe thank the reviewer for the constructive suggestion. In general, without CIPS and\nMLG, the number of reconfigurable modes is limited: typically, only pn and n+n\ncombinations, or np and p+p combinations can be realized, while configurations\nsuch as pp and nn are not achievable1, 2. Moreover, the device performance in these\ncases differs significantly from our FeFGRT devices. We have included the relevant\ncomparison experiments, and we hope this clarifies the role of each component and\naddresses the reviewer’s concern.\nTo clarify the role of each component in the material stack, we have performed\nadditional control experiments on reference devices without CIPS and/or MLG. These\nresults have been added to the revised manuscript. We hope that these additional\nexperiments help to address the reviewer’s concerns and further improve the quality\nand clarity of the manuscript.\nFigure R1. Transfer characteristics of the device without CIPS. (a) Schematic\nillustration of the device structure without CIPS. (b) Transfer characteristics of the\ndevice under different V\nCG\nranges. (c) Measurements of V\nFG\nand I\nDS\nunder ±25 V V\nCG\nsweeps. (d) Relationship between I and V corresponding to the blue dashed region\nDS FG\nin Fig. R1c.\nWe fabricated the device shown in Fig. R1a, which does not include the CIPS layer\ncompared with our FeFGRT device. This device is essentially analogous to a semi-\nfloating-gate (SFG) structure, where the channel is defined by electrodes E1 and E2,\nand the floating-gate (FG) electrode is introduced to better investigate the device\noperating mechanism. Consistent with the FeFGRT measurements, p++ Si was used as\nthe control gate. Under repeated V sweeps within the same range as well as under\nCG\ndifferent sweep ranges, the device exhibits similar n-type memory behavior, as shown\nin Fig. R1b. This observation is consistent with previously reported results for MoTe₂-\nbased SFG devices2. As shown in Fig. R1c, a clear difference in slope can be observed\nbetween regions (1) and (2). In region (1), the variation of I with gate voltage is\nDS\nrelatively gradual, whereas in region (2) the change becomes much steeper. Since the\nV shift induced by charge stored in the floating gate through tunneling between the\nth\nchannel and the floating gate does not alter the slope of the I –V curve, the\nDS CG\npronounced slope difference indicates that an additional modulation mechanism is\ninvolved2.\nTo clarify the physical origin of the memory window difference, a more detailed\nunderstanding of the operating mechanism underlying the I –V characteristics is\nDS CG\nrequired. Therefore, we introduce simultaneous measurements of the V during the\nFG\nV sweep, as V is a key parameter that determines whether charge tunneling occurs\nCG FG\nbetween the MoTe₂ channel and the MLG through the hBN layer3. We further extracted\nthe dependence of I on V , as shown in Fig. R1d.\nDS FG\nFigure R2. Working mechanism of the device. (a) The relationship of I and V\nDS FG\nwith V . (b) Dependence of I on V . (c) Schematic illustration of the device\nCG DS FG\noperating mechanism. (d–f) Schematic illustrations of the operating mechanisms at\npositions (1), (2), and (3) in Fig. R2a.\nTo exclude possible randomness, we fabricated another device with the same\nstructure and obtained consistent results, as shown in Fig. R2a-b. It should be noted that\nthe measurement of V\nFG\nhas a negligible impact on I\nDS\n4. As V\nCG\nis swept from negative\nto positive values, V initially increases linearly with V , with a slope dV /dV\nFG CG FG CG\nclose to 1, indicating strong capacitive coupling. Once V reaches a threshold value,\nFG\ncharge tunneling and capacitive coupling jointly govern the device behavior, resulting\nin an almost constant V . A similar evolution is observed during the reverse sweep\nFG\nfrom positive to negative.\nAs shown in Fig. R2b, process (2) follows the same trend as the variation of V ,\nFG\nwhereas process (3) exhibits anomalous behavior. These observations can be explained\nby the mechanism illustrated in Fig. R2c-f, where the channel consists of two distinct\nregions: one defined by the red dashed area controlled by the FG, and the other defined\nby the blue dashed area controlled by the CG. Since the overall channel conductance is\ndetermined by the region with smaller conductance, during process (1), V remains\nFG\npositive and the FG-controlled region stays in the on state. Consequently, the channel\nconduction is dominated by the CG-controlled region, resulting in a relatively small\nchange rate of the I\nDS\n. During process (2), both the CG and the FG are positively biased,\nso the channel is turned on in both regions. However, owing to the stronger electrostatic\ncontrol of the FG, the overall channel conduction is dominated by the FG-controlled\nregion. As a result, I follows the variation of V . During process (3), as the FG\nDS FG\npotential becomes increasingly negative, the FG-controlled region of the channel is\ndriven into the p-type on state. In contrast, the weakened gate control of the CG causes\nthe CG-controlled region of the channel to gradually turn off.\nFigure R3. Memory characteristics of the device without MLG. (a) Schematic\ndiagram of the device structure without MLG. (b-c) Transfer characteristics under\nbidirectional V sweeping measured using the E1–E2 (b) and E2–E3 (c).\nCG\nIn addition, we fabricated devices without MLG (Fig. R3a) and performed transfer\ncharacteristic measurements under bidirectional V sweeping, as shown in Fig. R3b–\nCG\nc. Compared with the fully ferroelectric-controlled configuration using the E1–E2\nelectrodes, the transfer characteristics measured between the E1–E3 electrodes exhibit\nlimited memory behavior.\nFigure R4. Photovoltaic characteristics of devices without CIPS (a) and without MLG\n(b).\nFurthermore, based on the two reference device structures discussed above—\nnamely, devices without CIPS and devices without MLG—we performed\nreconfigurable programming and photovoltaic measurements. As shown in Fig. R4,\nunder dark conditions, both the devices without CIPS and without MLG exhibit\nrectification ratios of approximately 102, which are significantly lower than those\nachieved by the proposed FeFGRT device. In contrast, our FeFGRT device exhibits a\nmuch higher rectification ratio together with a significantly enhanced photovoltaic\nresponse, highlighting the critical roles of ferroelectric polarization and floating-gate\nmodulation in strengthening the built-in electric field and enabling efficient self-\npowered operation. It should be noted that, for both the devices without CIPS and\nwithout MLG, the MoTe channel is entirely located on the hBN layer. This design\n2\navoids a scenario in which the channel partially lies on hBN and partially on SiO₂,\nwhich could otherwise introduce built-in potential variations arising from differences\nin dielectric constants5.\nReference:\n[1] Wang, Z., et al. 2D programmable photodetectors based on WSe₂/h-BN/graphene\nheterojunctions. Adv. Sci. 12, 2417300 (2025).\n[2] Liu, F. et al. Self-powered programmable van der Waals photodetectors with\nnonvolatile semifloating gate. Nano Lett. 23, 11645–11654 (2023).\n[3] Sasaki, T. et al. Understanding the memory window overestimation of 2D materials–\nbased floating-gate-type memory devices by measuring floating-gate voltage. Small 16,\n2004907 (2020).\n[4] Sasaki, T.; et al. Material and device structure designs for 2D memory devices based\non the floating gate voltage trajectory. ACS Nano 15, 6658–6668 (2021).\n[5] Zhang, C. et al. Reversible diode with tunable band alignment for photoelectricity-\ninduced artificial synapse. Small 19, 2300468 (2023).\nComment 8:\nThe FET configuration is back gated using a highly doped Si substrate as a bottom gate.\nWhat is the role of SiO ? did the authors tried a different dielectric layer? are they using\n2\nthe silicon back gate in their measurements?\nReply:\nWe thank the reviewer for this insightful question. In our device configuration, the\nhighly doped Si substrate is used as a global back gate (control gate), while the SiO\n2\nlayer serves as the gate dielectric. The SiO provides electrical insulation between the\n2\nback gate and the channel, ensuring low gate leakage and reliable device operation,\nwhile simultaneously enabling stable capacitive coupling.\nUsing different dielectric materials with varying dielectric constants would indeed\nlead to different capacitive coupling strengths. Such differences are primarily reflected\nin variations of the gate coupling ratio (GCR), as described by Eq. R1.\n𝐶SiO2\nGCR = (R1)\nTo clarify the role of SiO₂ and evalu\n𝐶\naStieO t2h\n+\ne i\\𝐶\nnhflBuNence of alternative dielectrics, we\nperformed a comparative analysis based on calculations. As shown in Fig. R5, we\ncompare the GCR for SiO layers with different thicknesses, as well as for high-κ\n2\ndielectrics including Al O ( ) and HfO₂ ( ).\n2 3\nAs shown in Fig. R5a𝜀, AiIn2 Ot3h≈e a8bsence of th𝜀eH fFOG2 ≈pa1d5, high-k dielectrics can\nsignificantly enhance the GCR. The results demonstrate that higher-κ dielectrics or\nthinner dielectric layers enhance the gate coupling strength, which would directly affect\nthe programming efficiency and operating voltages of the device. However, when the\nFG pad is introduced, this difference is greatly reduced, and the GCR approaches unity\nregardless of the dielectric material (Fig. R5b). This indicates that the presence of the\nFG pad plays a dominant role in achieving a high GCR.\nFurthermore, in Fig. R6, we analyze the influence of GCR on ultrafast and high-\ndensity charge storage. When the GCR approaches unity, the device exhibits\nsignificantly enhanced capability for ultrafast programming and high-density memory\noperation. These results demonstrate that, although dielectric engineering affects gate\ncoupling, the FG pad is the key factor enabling near-ideal gate coupling and superior\nmemory performance in our device.\nFigure R5. Influence of dielectric materials and FG pad on GCR. (a) Dependence\nof GCR on dielectric thickness for SiO , Al O , and HfO without a FG pad, showing\n2 2 3 2\nenhanced GCR for high-k dielectrics. (b) Dependence of GCR on dielectric thickness\nfor the same dielectrics with a FG pad, where the GCR approaches 1 and the material\ndependence is significantly suppressed.\nFigure R6. Effect of GCR on ultrafast and high-density charge storage. (a-b)\nCalculated charge storage density as a function of pulse width for the hole tunneling\nprocess under different GCR values. (c-d) Corresponding results for the electron\ntunneling process.\nComment 9:\nThere are many typos found in the manuscript (i.e., page 131: “when a negative positive\npulse is applied to the control gate, holes tunnel from the MoTe into the MLG…). A\n2\ncareful check and revision of the manuscript is required.\nReply:\nWe thank the reviewer for pointing out this issue. In response to the reviewer’s\ncomment, we have carefully proofread the entire manuscript and corrected the\ncorresponding errors. The text has been revised to ensure accurate terminology,\nconsistent descriptions, and improved overall readability throughout the manuscript.\nRevision:\n“Conversely, when a negative pulse is applied to the control gate, holes tunnel from\nthe MoTe into the MLG.”\nThe image in Fig. s2a,b probably is better to be moved to maintext. It is easier to\nunderstand the different sections of the devices rather checking only the very compact\nand crowed information of Figure 1.\nReply:\nWe thank the reviewer for this helpful suggestion. Following the reviewer’s advice,\nwe have moved the images in Fig. S2a,b to the main text and reorganized the figure\nlayout accordingly. This modification improves the clarity of the device structure and\nfurther enhances the overall readability of the manuscript.\nRevision:\nThe revised Fig. 1 is shown below, and the corresponding descriptions related to\nthis figure in the manuscript have been updated accordingly.\nFig. 1 | Schematic illustration of the FeFGRT and its multi-functional\ncharacteristics. a, The optical image of the device. The regions outlined by orange,\nblue, black, and green dashed lines correspond to MoTe₂, hBN, graphene, and CIPS,\nrespectively. b, Schematic illustration of the multifunctional heterojunction-based\nFeFGRT. The blue and red dashed regions correspond to the FeFET and FGFET\nstructures, respectively. Importantly, the full multifunctional including memory,\nlogic, and photodetection can still be realized only using E1 and E4. The purpose of E2 and\nE3 are only intended to facilitate the independent characterization of the FeFET and\nFGFET operation modes. c, d, Structural schematics of the FeFET (c) and FGFET (d),\nalong with the polarization and tunneling band bending diagrams under electric field\nmodulation. e, Cross-sectional TEM image and the corresponding EDS mapping of the\nMoTe₂/hBN/MLG heterostructure. f, Cross-sectional TEM image and the\ncorresponding EDS mapping of the MoTe₂/hBN/CIPS heterostructure. g, h,\nReconfigurable behavior of the np (g) and pn (h) junctions under the dual coupling of\nferroelectric polarization and charge tunneling. i, j, Multimode modulation based on\nthreshold differences, where (i) corresponds to the nn mode and (j) corresponds to the\npp mode.\nComment 11:\nThe butterfly loop of Figure s4 is taken from an isolated flake different than the layer\nused for electrical measurements. What is the thickness of the flake used in Figure S4?is\nthere any thickness dependence of ferroelectric properties of CIPS films?\nReply:\nWe thank the reviewer for raising this important point. The butterfly loop shown in\nFig. S4 was measured on an isolated CIPS flake that was separately prepared for PFM\ncharacterization, rather than on the specific flake used in the electrical device\nmeasurements. It should be noted that the thickness of the CIPS flake in our device is\napproximately 80 nm, which is comparable to that of the samples used for PFM\ncharacterization in Fig. S4.\nTo further address the reviewer’s question regarding the thickness dependence of\nferroelectric properties in CIPS, we performed systematic PFM amplitude and phase\nmeasurements on exfoliated CIPS flakes with thicknesses of 170 nm, 50 nm, 30 nm,\nand 20 nm, as shown in Fig. R7. All these samples exhibit clear ferroelectric switching\nbehavior, confirming robust ferroelectricity over a wide thickness range. Consistent\nwith previous reports, thinner CIPS flakes show a larger coercive electric field[1-2].\nMoreover, prior studies have demonstrated that CIPS retains switchable\nferroelectric polarization down to thicknesses of approximately 4 nm, highlighting its\nexcellent thickness scalability and robustness as a two-dimensional ferroelectric\nmaterial. These results collectively confirm that the ferroelectric behavior observed in\nour device-relevant CIPS thickness regime is intrinsic and reliable.\nFigure R7. Ferroelectric characterization of the exfoliated CIPS flakes with\ndifferent thicknesses.\nReference:\n[1] Belianinov, A. et al. CuInP₂S₆ room-temperature layered ferroelectric. Nano Lett.\n15, 3808–3814 (2015).\n[2] Si, M. et al. Room-temperature electrocaloric effect in layered ferroelectric\nCuInP₂S₆ for solid-state refrigeration. ACS Nano 13, 8760–8765 (2019).\n[3] Liu, F. et al. Room-temperature ferroelectricity in CuInP₂S₆ ultrathin flakes. Nat.\nCommun. 7, 12357 (2016).\nComment 12:\nIn Figure 2 for the FGFET I-V characteristics, a very high Vg is required despite the\nultra thin dielectric layer. How do the authors comment on that? Is there any hint from\nthe FN tunneling calculations on why a huge tunnel barrier is present, and how the\nstructure can be optimized toward lower the required switching voltages? Based on ID-\nVG of Figure S8 for the FGFET, a strong current tunability is achieved with few V (i.e.,\n-3V) that contrasts with the finding of Figure 2.\nReply:\nWe sincerely thank the reviewer for the insightful comments regarding the\noperating voltage and tunneling barrier.\nIt should be noted that the tunneling current in FGFET-type devices exhibits an\nexponential dependence on the electric field across the hBN layer. In our FeFGRT\ndevices, an hBN thickness of approximately 10 nm was adopted, which is commonly\nused in floating-gate memories to ensure reliable tunneling behavior and device\nstability1, 2. Nevertheless, provided that a high-quality interface can be maintained,\nreducing the hBN thickness to around 5 nm can significantly lower the programming\nvoltage3, 4. In addition, several effective strategies have been reported to further reduce\nthe operating voltage of floating-gate devices, including engineering atomically sharp\ninterfaces5, increasing the GCR6, and employing phase or barrier engineering\napproaches7.\nTo address this concern, we fabricated three devices with identical structures,\nwhere the MoTe channel thickness and the MLG thickness are comparable, while the\n2\nprimary difference lies in the thickness of the hBN tunneling layer. To further\ninvestigate the FN tunneling barrier, systematic tunneling current measurements were\nperformed on these devices. Based on Eq. R2, the FN tunneling model was employed\nto fit the experimental data, from which the tunneling barriers for both electrons and\nholes were extracted,as shown in Fig.R8-10. The obtained barrier heights are consistent\nwith previously reported results and agree well with the expected band alignment of the\ndevice structure1.\n𝐼F−N 1\nIn( 2 ) = ln(𝐴1)−𝐴2 ∗ (R2)\nWhere , 𝑉 3 . 𝑉\n𝐴𝑞 3 𝑚0 8π√2𝑚 ∗ 𝜑 2 𝑑\nWhere V 𝐴 , 1 A = , 8π , ℎ q 𝜑 , 𝑑 2 𝑚 ∗, 𝐴2 = , d, an 3 d ℎ 𝑞 h are the applied voltage, the effective contact\narea, the height of the tunneli∗ng barrier, the electron charge, the mass of the free\n𝜑 𝑚0 𝑚\nelectrons, the effective mass of holes/electrons in hBN, the thickness of the tunneling\nlayer, and Planck’s constant, respectively.\nFinally, regarding the reviewer’s comment on Fig. S8a, we clarify that the ±3 V\ngate voltage sweep corresponds to a FeFET configuration, rather than an FGFET.\nThe observed memory behavior in Fig. S8a therefore originates from ferroelectric switching\ninstead of tunneling-based floating-gate operation. The results shown in Fig. S8b\noriginate from a pure capacitive coupling effect. Although the channel current can be\neffectively modulated under gate voltage sweeping, no charge tunneling occurs\nbetween the channel and the floating gate. Therefore, no nonvolatile memory behavior\nis observed in this case. This result highlights the distinct threshold voltages associated\nwith the two mechanisms, providing the foundation for achieving four functional modes\nunder a single global gate control.\nFigure R8. Tunneling current measurements and FN fitting of Device #1. (a)\nTunneling current characteristics measured across the hBN. (b) AFM height profiles of\nthe individual functional layers in the device, including MoTe , hBN, and graphene. (c–\n2\nd) FN tunneling analysis for electrons, where panel (d) shows the linear fitting extracted\nonly from the high-field regime. (e–f) FN tunneling analysis for holes, where panel (f)\nshows the linear fitting extracted only from the high-field regime.\nFigure R9. Tunneling current measurements and FN fitting of Device #2. (a)\nTunneling current characteristics measured across the hBN. (b) AFM height profiles of\nthe individual functional layers in the device, including MoTe , hBN, and graphene. (c–\n2\nd) FN tunneling analysis for electrons, where panel (d) shows the linear fitting extracted\nonly from the high-field regime. (e–f) FN tunneling analysis for holes, where panel (f)\nshows the linear fitting extracted only from the high-field regime.\nFigure R10. Tunneling current measurements and FN fitting of Device #3. (a)\nTunneling current characteristics measured across the hBN. (b) AFM height profiles of\nthe individual functional layers in the device, including MoTe , hBN, and graphene. (c–\n2\nd) FN tunneling analysis for electrons, where panel (d) shows the linear fitting extracted\nonly from the high-field regime. (e–f) FN tunneling analysis for holes, where panel (f)\nshows the linear fitting extracted only from the high-field regime.\nReference:\n[1] Sasaki, T. et al. Understanding the memory window overestimation of 2D materials\nbased floating gate type memory devices by measuring floating gate voltage. Small 16,\n2004907 (2020).\n[2] Wang, H. et al. Ultrafast non-volatile floating-gate memory based on all-2D\nmaterials. Adv. Mater. 36, 2311652 (2024).\n[3] Vu, Q. A. et al. Two-terminal floating-gate memory with van der Waals\nheterostructures for ultrahigh on/off ratio. Nat. Commun. 7, 12725 (2016).\n[4] Li, C. et al. Charge-selective 2D heterointerface-driven multifunctional floating gate\nmemory for in situ sensing-memory-computing. Nano Lett. 24, 15025–15034 (2024).\n[5] Wu, L. et al. Atomically sharp interface enabled ultrahigh-speed non-volatile\nmemory devices. Nat. Nanotechnol. 16, 882–887 (2021).\n[6] Liu, L. et al. Ultrafast non-volatile flash memory based on van der Waals\nheterostructures. Nat. Nanotechnol. 16, 874–881 (2021).\n[7] Yu, J. et al. Simultaneously ultrafast and robust two-dimensional flash memory\ndevices based on phase-engineered edge contacts. Nat. Commun. 14, 5662 (2023).\nComment 13:\nIn many places in the manuscript, the authors claim that their approach is less complex\nthan the split gate approach requiring only one control gate. However, their device\ngeometry is rather quite complex requiring separate control gate for the FE-based stack\nand a separate control gate for the floating gate configuration of the full device making\ntheir argument less strong. Besides, they have 4 top pads used for S/D contacts\ndepending on the different device operation mode against only 2 pads used for standard\nFGFETs or FEFETs.\nReply:\nWe thank the reviewer for raising this important point regarding device complexity.\nFirst, it should be clarified that the use of multiple top electrodes (E1–E2 and E3–\nE4) in this work is mainly intended to facilitate the independent characterization of the\nFeFET and FGFET operation modes and to clearly elucidate the underlying device\nphysical mechanisms. Importantly, the full multifunctional behavior of the\nproposed device—including memory, logic, and photodetection—can still be\nrealized using only two source/drain electrodes (E1 and E4). It is worth noting that\nduring the reconfigurable programming, the operation relies solely on a single global\ngate (p++ Si), with the floating-gate electrode serving only to enhance the GCR,\nfollowing standard practices in typical floating-gate designs.\nIn practical operation, by applying programming pulses with different amplitudes\nto the same control gate, the channel can be non-volatily reconfigured between np, pn,\nnn, and pp junction states. These states remain stable during readout and enable flexible\nmodulation of the channel conductance, thereby supporting multi-mode device\nfunctionality without the need for split gates.\nMoreover, although both ferroelectric switching and charge tunneling are involved\nin the device operation, they can be selectively addressed using a single control gate,\nowing to the fact that the coercive voltage of the ferroelectric layer is typically much\nsmaller than the tunneling voltage required for floating-gate programming. This allows\nindependent control of the FeFET behavior without activating the floating-gate\ntunneling process.\nTherefore, compared with split-gate architectures that require multiple\nindependently biased gate electrodes and complex lateral gate patterning, our approach\neliminates the need for lateral gate definition. Instead, it relies on heterojunction design\nengineering and control-gate voltage amplitude modulation, which significantly\nsimplifies both the gate architecture and the operation scheme.\nWe hope that this clarification adequately addresses the reviewer’s concern and\nhelps to clarify the advantages of the proposed device architecture.\nComment 14:\nRegarding Figure 4, the focus is demonstrating device operation as a solar cell or a\nphotodetector? If the first is the case, then a power conversion efficiency should be\nprovided for different illumination conditions. Based on their EQE data, they authors\nshould extract the integrate current through their device and compare its amplitude with\nthe current measured in J-V characteristics (deviations should be less than 5%).\nReply:\nWe thank the reviewer for raising this important point regarding the\ncharacterization of our device. We would like to clarify that the primary objective of\nFigure 4 is to demonstrate the device’s functionality as a high-performance self-\npowered photodetector, rather than a solar cell. In our work, the photovoltaic response\nis utilized as an internal driving mechanism that enables zero-bias photodetection. More\nimportantly, this photovoltaic behavior serves as the foundational mechanism for the\nsubsequent demonstration of in-memory logic and optoelectronic fusion logic gates,\nrather than being optimized for power generation.\nUnlike solar cells, where PCE and the quantitative consistency between EQE-\nintegrated current and J–V characteristics are key performance metrics, photodetectors\nare mainly evaluated by figures of merit such as responsivity, detectivity, and\nphotoresponse. To this end, we have revised Figure 4, replacing the electrical power\n(Pel) and fill factor (FF) with the time-resolved photoresponse (Fig. 4e), and adding a\nclear description of the effective area. This modification is intended to prevent any\npotential ambiguity regarding the device's primary functionality and ensures that its\nrole as a high-performance self-powered photodetector is accurately conveyed to the\nreaders.\nWe believe that these modifications more accurately reflect our focus on achieving\nhigh-performance self-powered photodetection, rather than showcasing the device's\nutility as a solar cell. We hope that our response and the corresponding clarifications in\nthe revised manuscript effectively address the reviewer’s concerns.\nRevision:\nThe revised Figure 4 is provided below, and the corresponding descriptions in the\nmanuscript have been updated accordingly.\nFig.4 | Multimodally Tunable Reconfigurable Features and Photovoltaic Properties of\nFeFGRT. Here, E1 and E4 represent the S and D, respectively. a, b, Multimodally tunable output\ncharacteristics. c, Logarithmic output curves under 520 nm illumination with different P . d,\nin\nExtracted I and V under various light power intensities of 520 nm. e, R esponse time of the\nsc oc\nFeFGRT under 520 nm illumination when P = 3.533 mW/cm2.\nin\nf, Photoswitching response of the\nFeFGRT under different laser powers. g, The power-dependent R and D* of the FeFGRT under 520\nnm illumination at V = 0 V.\nDS\nh, Dependence of the EQE on the laser power. The inset shows a\nschematic of the effective active area of the device (~276 μm2), indicated by the blue dashed region.\nThe white scale bar represents 10 μm. i, Comparison of R and D* of broadband photodetectors based\non advanced two-dimensional materials and their heterostructures.\nComment 15:\nAccording to the authors, a nonvolatile pn junction defined by gate pulses is employed\nfor the photovoltaic measurements. Only in this operation mode, a PV behavior can be\nmeasured, or similar behavior can be achieved under different gate conditions and thus\noperation modes?\nReply:\nWe thank the reviewer for this thoughtful question. We would like to clarify that\nthe PV measurements in this work are intentionally performed in a nonvolatile and\nreconfigurable operation mode, where a pn (or np) junction is defined by gate voltage\npulses rather than by continuously applied gate biases. After the programming pulses\nare removed, the junction configuration is retained due to the nonvolatile nature of the\ndevice, allowing stable PV measurements without the need for a sustained gate voltage,\nwhich is essential for minimizing power consumption and enabling self-powered\noperation.\nIn contrast, under constant gate bias conditions, the channel potential is\nsimultaneously influenced by both the control gate and the floating gate through\ncapacitive coupling and possible charge dynamics. This results in an unstable channel\nconduction state and fluctuating current, which is not suitable for reliable photovoltaic\ncharacterization.\nIn summary, the observed photovoltaic behavior is intrinsically linked to the\nnonvolatile, pulse-defined junction configuration, which ensures a stable built-in\nelectric field for efficient photocarrier separation while avoiding continuous gate\nbiasing and the associated energy consumption. We hope this explanation clarifies the\noperation mode and alleviates the reviewer’s concerns.\nReviewer #2\nWhile the manuscript presents an interesting ferroelectric heterostructure concept,\nin its current form it does not provide sufficient novelty or experimental evidence to\njustify publication. The key device claims, particularly logic-in-memory functionality\nand multifunctional integration, are either already demonstrated in prior works or\nlimited by practical constraints such as high operating voltages, limited endurance, and\nslow switching. Therefore, I cannot recommend this manuscript for publication. Below\nis the detailed reasons for this decision.\nReply:\nWe sincerely thank the reviewer for the constructive comments and for recognizing\nthe device architecture. We would like to emphasize that the coupled effects of\nferroelectric polarization and charge tunneling play a crucial role in our device. By\nexploiting this coupling mechanism, we achieve switchable and reconfigurable\nmodulation among four channel configurations (nn, np, pp, and pn).\nFurthermore, the two segments of the channel are modulated by electric fields with\nopposite polarities, leading to the formation of a strong built-in electric field across the\nchannel. This built-in field enables excellent photodetection performance with high\nresponsivity and detectivity, as well as stable self-powered operation.\nBuilding on this capability, the device can further realize complex in-memory logic\nfunctions under photo–electrical co-modulation. In particular, the stable pn and np\nconfigurations, together with the photovoltaic effect, demonstrate strong potential for\nlow-power sensing–computing–memory integration.\nWe hope that our point-by-point responses will address address the reviewer’s\nconcerns and help to demonstrate the novelty and significance of our work.\nComment 1:\nThe manuscript claims single-transistor XNOR functionality enabled by coupled\nferroelectric polarization and tunneling. However, similar demonstrations of 1T logic-\nin-memory functions using ferroelectric FeFETs (especially HfO₂-based devices) have\nalready been widely reported. The authors should clearly articulate how their approach\nprovides a significant advantage over existing FeFET logic devices, especially given\nthat the operating voltages here are relatively high compared to hafnia-based FeFETs.\nWithout such clarification, the novelty of the contribution may appear limited.\nReply:\nWe sincerely thank the reviewer for this insightful and constructive comment.\nBelow, we clarify the key distinctions and advantages of our approach in terms of\ndevice architecture, material choice, functional integration, and performance, which\ntogether constitute the novelty of this work.\n(1) Unique heterostructure design for multi-modal reconfigurable modulation.\nFrom a device-architecture perspective, our approach is fundamentally different\nfrom conventional FeFET logic devices. Specifically, we intentionally integrate\nferroelectric-gated FET and FGFET behaviors within a single channel and exploit the\nopposite hysteresis directions of these two mechanisms under identical gate pulse\nstimuli. As a result, the threshold voltage shifts in opposite directions after the same\nprogramming operation, enabling differential p-type and n-type modulation along the\nchannel.\nMore importantly, different segments of the channel are modulated by distinct\nlocalized electric fields: one side of the channel is dominated by the strong local\nferroelectric polarization field, while the other side is primarily governed by the\nlocalized floating-gate electric field. This asymmetric electrostatic modulation across\nthe channel gives rise to a nonvolatile pn junction with a strong built-in electric field.\nThis built-in field is a key enabler for the observed rectification, self-powered\nphotoresponse, and logic functionality.\nIn addition, since the tunneling-driven programming voltage required for floating-\ngate operation is typically larger than the coercive voltage for ferroelectric polarization\nswitching, our architecture allows decoupled and sequential control of the floating-gate\ncharge and ferroelectric polarization. As a result, our device can achieve four distinct\nreconfigurable transport modes (pp, pn, np, and nn) within a single channel, which\nremain stable and nonvolatile after the programming pulses are removed. This\nversatility is realized without relying on split-gate configurations or complex multi-gate\ngeometries, which are commonly required in conventional FeFET-based designs to\nmanage such diverse polarity states1, 2. It is worth noting that while some recent studies\nhave explored the competitive coupling between charge trapping and ferroelectric\npolarization, they typically require significantly larger switching voltages3. Overall, the\nsynergistic integration within our heterostructure design demonstrates immense\npotential for the seamless fusion of sensing, memory, computing, and logic\nfunctionalities.\n(2) High-quality atomically sharp interfaces.\nIn terms of material selection, we employ CIPS, a layered van der Waals\nferroelectric material. Compared with polycrystalline HfO₂-based ferroelectrics, CIPS\nenables atomically sharp interfaces with the channel material, effectively suppressing\ninterface trap density and interfacial disorder4.\nNotably, CIPS maintains robust ferroelectricity down to a thickness of ~4 nm,\nwhich is highly advantageous for scaling5. It is worth emphasizing that in the FeFET\noperating mode of our device, a memory window approaching 2.5 V can be achieved\nunder a relatively low gate sweep of ±3 V, demonstrating efficient charge storage and\nsignificant potential for low-voltage programming.\n(3) Integration of sensing, memory, computing, and logic functionalities.\nOwing to the strong built-in electric field, the FeFGRT device exhibits robust self-\npowered operation, a high rectification ratio, and excellent R and D*. In addition, the\ndevice can be flexibly reconfigured into four distinct operation modes. Previous studies\nhave demonstrated that stable photovoltaic characteristics can be achieved based on\nreconfigurable pn and np configurations. By using the R as a weighting factor, this\ncapability provides a promising pathway toward low-power sensing–computing\nintegrated architectures1, 2.\nFurthermore, under photo–electrical co-modulation, the FeFGRT device can\ndirectly implement logic functions such as XNOR and AND gates. Compared with\nconventional CMOS-based logic circuits, our architecture significantly reduces the\nrequired transistor count6-8. Specifically, for XNOR logic operated in the current-output\nmode, the number of transistors can be reduced from two to one when compared with\nstate-of-the-art HfO₂-based ferroelectric counterparts9. Moreover, by leveraging the\nself-powered nature of the device, the overall power consumption is substantially\nlowered. Collectively, these advantages highlight the unique capability of the FeFGRT\nplatform to integrate sensing, memory, computing, and logic functionalities within a\nsingle energy-efficient system.\n(4) Comparison with state-of-the-art reconfigurable ferroelectric devices.\nFinally, when benchmarked against representative reconfigurable ferroelectric\ndevices, our architecture shows competitive or superior performance in terms of\nmemory on/off ratio, coercive voltage, and functional versatility, while offering a\nunique pathway toward multifunctional, compact logic-in-memory systems.\nIn summary, although single-transistor logic-in-memory has been explored in\nFeFET platforms, our work introduces a distinct physical mechanism and device\nconcept based on the synergistic coupling of ferroelectric polarization and floating-gate\ntunneling within a single transistor. We suggest that this combination, together with the\ndemonstrated multifunctionality and optoelectronic logic capabilities, clearly\ndifferentiates our approach from existing FeFET-based logic devices and establishes its\nnovelty.\nWe hope that these clarifications adequately address the reviewer’s concerns.\nTable R1. Comparison table of reconfigurable devices based on ferroelectric\nmaterials.\nMemory\nDevice Program Coercive Rectificati Control archit-\nSpeed Functions on/off mode Ref.\nstructure voltage voltage on ratio ecture\nratio\npp\nGr-MoTe - memory\n2\n10 pn\nGr/ ± 35 V ±13 V sensing 104 104 split gates 1\nms nn\nP(VDF-TrFE) computing\nnp\npp\nmemory\nWSe\n2\n/\n± 20 V\n1\n±14 V sensing 107 103 split gates\npn\ncomputing\nnp\nSWCNT/ 80 memory\n± 18 V ±15 V 105 - control gate p, n 7\nAIScN ms logic\npp\nmemory pn\nWSe /hBN 10\n2 ± 12 V - logic 106 104 split gates nn 8\n/CIPS ms\nPV np\np, n\nMoS /\nx ± 4 V 1 μs ± 2.1 V 107 - control gate - 9\nTiN/HZO/ logic\nTiN\nTi/Au/ back gate\nMoS / memory (memory gate)\n2 ± 5 V 1 μs - 105 - - 10\nHZO/ logic top gate\nW (logic gate)\nmemory pp\nMoTe /\n2\ncomputing pn\nhBN/ -0.4 V This\n± 5 V 1 ms sensing 106 104 control gate nn\n(CIPS- 1.3 V work\nlogic np\nMLG)\nPV p, n\nNote: “Program voltage” and “Speed” refer to the pulse amplitude and pulse width,\nrespectively, required to switch only the ferroelectric polarization.\nReference:\n[1] Wu, G., et al. Ferroelectric-defined reconfigurable homojunctions for in-memory\nsensing and computing. Nat. Mater. 22, 1499–1506 (2023).\n[2] Dang, Z., et al. Object motion detection enabled by reconfigurable neuromorphic\nvision sensor under ferroelectric modulation. ACS Nano 18, 27727–27737 (2024).\n[3] Li, E. et al. Polarity-dependent ferroelectric modulations in two-dimensional hybrid\nperovskite heterojunction transistors. Nat. Commun. 16, 9382 (2025).\n[4] Dahan, M. M., et al. Sub-nanosecond switching of Si:HfO₂ ferroelectric field-effect\ntransistor. Nano Lett. 23, 1395–1400 (2023).\n[5] Liu, F. et al. Room-temperature ferroelectricity in CuInP₂S₆ ultrathin flakes. Nat.\nCommun. 7, 12357 (2016).\n[6] Migliato Marega, G. et al. Logic-in-memory based on an atomically thin\nsemiconductor. Nature 587, 72–77 (2020).\n[7] Rhee, D., et al. Reconfigurable single-walled carbon nanotube ferroelectric field-\neffect transistors. Nat. Commun. 16, 7655 (2025).\n[8] Ram, A., et al. Reconfigurable multifunctional van der Waals ferroelectric devices\nand logic circuits. ACS Nano 17, 21865–21877 (2023).\n[9] Lu, T., et al. Two-dimensional fully ferroelectric-gated hybrid computing-in-\nmemory hardware for high-precision and energy-efficient dynamic tracking. Sci. Adv.\n10, eadp0174 (2024).\n[10] Huang, K., et al. Hf₀.₅Zr₀.₅O₂ ferroelectric embedded dual-gate MoS₂ field-effect\ntransistors for memory-merged logic applications. IEEE Electron Device Lett. 41,\n1600–1603 (2020).\nComment 2:\nThe proposed PT device requires four channel electrodes in addition to the gate, which\ncomplicates the structure. It is therefore not straightforward to categorize this as a true\n“single transistor” from an integration perspective. The authors should discuss whether\nthis architecture offers any real advantage in terms of footprint or scalability compared\nto conventional CMOS or other reconfigurable transistor designs.\nReply:\nWe thank the reviewer for this important comment regarding the device\narchitecture. We would like to clarify the following points to address the concerns about\nintegration and footprint.\nIt should be clarified that the four top electrodes (E1–E2 and E3–E4) are\nintentionally introduced to experimentally and unambiguously demonstrate the distinct\noperating modes of the device, namely the FeFET and FGFET behaviors, and to\nfacilitate mechanism analysis. Importantly, in the reconfigurable operation mode, only\ntwo electrodes (E1 and E4) are required to realize integrated memory, logic,\ncomputing, and sensing functionalities within a single device unit. The additional\nelectrodes are therefore not essential for practical operation, but serve as\ncharacterization terminals to clearly elucidate the underlying device physics.\nIt should be noted that our FeFGRT device, designed based on 2D heterostructures,\ncan implement basic logic gates such as NAND and NOR, as well as more complex\nlogic like XNOR, within a single device unit. Compared with conventional CMOS logic\ncircuits, this significantly reduces the required number of transistors. Moreover, by\nleveraging the photovoltaic characteristics, logic functions can be realized under an\noptoelectronic co-modulation scheme. The synergistic and decoupled integration of\nferroelectric polarization and floating-gate effects enables stable, nonvolatile, and\nreconfigurable modes defined by programming pulses, providing a practical alternative\nto split-gate architectures. Compared with FeFET logic devices based on split-gate\ndesigns, this approach also reduces fabrication complexity.\nFurthermore, our platform aligns with the emerging trend of 2D/Silicon hybrid\nintegration, as recently demonstrated by the landmark 2D flash chip integrated on\nCMOS1. This synergy between the functional diversity of vdW heterostructures and\nmature CMOS technology provides a clear, scalable pathway for high-density, energy-\nefficient intelligent systems.\nIt is worth noting that achieving large-scale, high-yield integration of functional\n2D materials and their heterostructures remains a widely recognized challenge. At the\nsame time, growing efforts and recent advances have begun to address and gradually\nalleviate these limitations.With respect to material integration, significant progress has\nbeen achieved in the large-area and high-quality synthesis of graphene, hBN, and\nMoTe , including chemical vapor deposition (CVD) growth and wafer-scale transfer\n2\nprocesses, which supports the scalability of the proposed heterostructure platform2-6.\nWe acknowledge that the large-area, controllable fabrication of CIPS remains more\nchallenging at present6. However, recent studies have demonstrated promising\nstrategies, such as etching-assisted integration and device-level patterning, to scale up\nCIPS-based optoelectronic device arrays8.\nReference:\n[1] Liu, C. et al. A full-featured 2D flash chip enabled by system integration. Nature\n638, 590–597 (2025).\n[2] Chen, B. et al. Edge-feeding synchronous epitaxy of layer-controlled graphene films\non heterogeneous catalytic substrates. Nat. Commun. 16, 5490 (2025).\n[3] Wang, L. et al. Epitaxial growth of a 100-square-centimetre single-crystal hexagonal\nboron nitride monolayer on copper. Nature 570, 91–95 (2019).\n[4] Xu, X. et al. Seeded 2D epitaxy of large-area single-crystal films of the van der\nWaals semiconductor 2H-MoTe₂. Science 372, 195–200 (2021).\n[5] Fukamachi, S. et al. Large-area synthesis and transfer of multilayer hexagonal boron\nnitride for enhanced graphene device arrays. Nat. Electron. 6, 126–136 (2023).\n[6] Liu, L. et al. A mass transfer technology for high-density two-dimensional device\nintegration. Nat. Electron. 8, 135–146 (2025).\n[7] Li, M. et al. Memristors based on ferroelectric Cu-deficient copper indium\nthiophosphate for multilevel storage and neuromorphic computing. Small 21, 2412314\n(2025).\n[8] Zhong, Z. et al. Ionic–electronic photodetector for vision assistance with in-sensor\nimage processing. Nat. Commun. 16, 7096 (2025).\nComment 3:\nLogic-in-memory applications require very high switching speeds to be compatible\nwith conventional logic. However, tunneling-based mechanisms are inherently slower\nthan charge displacement in ferroelectrics, which is why NAND flash memories are\nunsuitable for logic-in-memory. Indeed, the data here show that proper switching is not\nachieved for pulses shorter than ~100 ns, which raises concerns about practical speed\nlimitations. The authors should clarify how this device can realistically function in\nlogic-in-memory applications given these constraints.\nReply:\nWe thank the reviewer for raising the important concern regarding switching speed\nand the use of tunneling mechanisms. We would like to clarify that, in our device, the\ncharge tunneling process is involved only during the programming (state-setting) stage,\nwhere a nonvolatile channel configuration is established to enable memory-logic co-\nintegration. Once the channel state is defined, logic computation and signal readout are\nperformed in a read-dominant mode governed by carrier transport and the built-in\nelectric field, without involving any tunneling process. The observed limitation that\nreliable switching is not achieved for pulses shorter than ~100 ns therefore reflects the\nprogramming speed, rather than the intrinsic speed of logic evaluation. This distinction\nis fundamental to logic-in-memory architectures, which differ from conventional high-\nfrequency CMOS logic in that the device state is programmed infrequently and\nsubsequently reused for multiple logic and sensing operations1. As a result, logic-in-\nmemory applications do not require the same write-cycle-level switching speed as\nclocked CMOS logic.\nIt is also important to note that the speed limitation of conventional silicon-based\nflash memories is not solely determined by the tunneling mechanism itself, but is\nlargely affected by charge trapping, interface states, and reliability degradation at the\nSi/SiO interface2. In contrast, our device employs atomically flat hBN as the tunneling\n2\ndielectric, which provides an ultraclean and sharp van der Waals interface with minimal\ninterfacial trap density and a well-defined tunneling barrier. This significantly\nsuppresses stochastic charge trapping and enables a more deterministic tunneling\npathway, offering intrinsic advantages for faster and more reliable programming\ncompared with conventional oxide-based flash structures.\nFor 2D flash devices, the programming speed is primarily governed by the effective\nelectric field across the tunneling dielectric, as shown in Fig. R11. Indeed, recent studies\non 2D flash memories have demonstrated programming speeds down to the picosecond\nregime, highlighting the potential of such architectures for fast state programming3.\nFurthermore, logic-in-memory operation does not necessarily require strict\nmultilevel-cell programming. When operated in a single-level-cell regime, partial\ncharge modulation can further reduce programming voltage and accelerate state\nswitching, which is advantageous for practical LIM applications4. For clarity, we have\nsummarized representative flash-based logic-in-memory architectures in Table R2 to\ncontextualize the achievable speed–endurance trade-offs.\nIn addition, by optimizing the gate coupling ratio, scaling the channel area, and\nengineering the tunneling dielectric thickness, the programming speed can be further\nimproved without fundamentally altering the device architecture5. The operation speed\nof our device can be improved to below 100 ns, as shown in Fig. R12. It can be observed\nthat, under otherwise identical conditions, the programming operation remains more\ndifficult than the erase operation. This asymmetry originates from the difference\nbetween the tunneling barriers for holes and electrons. Figures R13–R14 present the\ncorresponding programming and erasing pulse waveforms.\nFigure R11. The relationship between program/erase voltage and program/erase\ntime. (a) Program time as a function of the program voltage. (b) Erase time as a function\nof the erase voltage.\nFigure R12. Erasing (a) and programming (b) operations under pulses with\ndifferent widths and amplitudes.\nFigure R13. Obtained erasing pulse waveforms under different pulse amplitudes\nand widths.\nFigure R14. Obtained programming pulse waveforms under different pulse\namplitudes and widths.\nTable R2. Comparison table of reconfigurable logic-in-memory devices based on\nfloating-gate architectures or charge-trapping mechanisms.\nDevice Program Logic\nSpeed Endurance Retention Ref.\nstructure voltage function\nOR\nReS /hBN/Te ±60 V 2 s >1000 >104 s 6\nXNOR\nWSe /hBN/Gr ±18 V 0.3 s >800 >800 s 7\nWSe /hBN\n2 ±30 V 160 ns >250 >500 s Inverter 8\n/(Gr-Gr)\nXNOR\nXOR\nWSe /hBN NOR\n2 ±8 V 1 ms >tens >1000 s 9\n/(Gr-Gr) AND\nNAND\nOR\nAND\nOR\nhBN/ReSe - 40V NAND\n2\n0.5 s - >5000 s 10\n/hBN 80 V NOR\nXOR\nXNOR\nNOR\nMoS /HfO /Pt ±10 V 100 ms >104 10 years 1\n2 2\nNAND\nXNOR\n±10 V 10 ms\nMoTe /hBN >1000 s NOR This\n2 (50 ns/ 105\n/(CIPS-MLG) (25V/ (4-bit) NAND work\n50 ns)\n-30V) OR\nNote: “Program voltage” and “Speed” refer to the pulse amplitude and pulse width\nrequired for full programming and erasing of the floating gate.\nReference:\n[1] Migliato Marega, G. et al. Logic-in-memory based on an atomically thin\nsemiconductor. Nature 587, 72–77 (2020).\n[2] Wu, L. et al. Atomically sharp interface enabled ultrahigh-speed non-volatile\nmemory devices. Nat. Nanotechnol. 16, 882–887 (2021).\n[3] Xiang, Y. et al. Subnanosecond flash memory enabled by 2D-enhanced hot-carrier\ninjection. Nature 1-8 (2025).\n[4] Lu, T., et al. Two-dimensional fully ferroelectric-gated hybrid computing-in-\nmemory hardware for high-precision and energy-efficient dynamic tracking. Sci. Adv.\n10, eadp0174 (2024).\n[5] Liu, L. et al. Ultrafast non-volatile flash memory based on van der Waals\nheterostructures. Nat. Nanotechnol. 16, 874–881 (2021).\n[6] Bach, T. P. A. et al. 2D van der Waals heterostructure with tellurene floating-gate\nfor wide range and multi-bit optoelectronic memory. ACS Nano 18, 4131–4139 (2024).\n[7] Sheng, Z. et al. Reconfigurable logic-in-memory computing based on a polarity-\ncontrollable two-dimensional transistor. Nano Lett. 23, 5242–5249 (2023).\n[8] Jiazila, N. et al. Programmable WSe₂ 2D lateral p–n junctions controlled by dual\nfloating gates. Adv. Funct. Mater. 35, 2423196 (2025).\n[9] Sun, X. et al. Reconfigurable logic-in-memory architectures based on a two-\ndimensional van der Waals heterostructure device. Nat. Electron. 5, 752–760 (2022).\n[10] Tsai, M.-Y. et al. A reconfigurable transistor and memory based on a two-\ndimensional heterostructure and photoinduced trapping. Nat. Electron. 6, 755–764\n(2023).\nComment 4:\nThe endurance data presented extend only to ~104 cycles. By contrast, logic-level\nendurance is typically benchmarked at ~1015 cycles, and even state-of-the-art hafnia\nFeFETs report endurance up to 108–1010 cycles. For the device to be positioned as a\nviable logic-in-memory solution, more extensive endurance characterization or at least\na discussion of this limitation is needed. The current endurance window is insufficient\nto support the strong claims made.\nReply:\nWe sincerely thank the reviewer for raising the important concern regarding device\nendurance. We fully acknowledge that state-of-the-art HfO\n2\n-based FeFETs have\ndemonstrated excellent endurance performance, reaching 108–1010 cycles through\noptimized gate-stack engineering and write-pulse schemes, as reported in recent\nstudies¹˒².\nIn this regard, we have further extended the endurance characterization from ~104\ncycles reported in the original manuscript to ~105 cycles, as shown in Fig. R15.\nThroughout the cycling test, both the on and off states remain stable without noticeable\ndegradation, indicating reliable nonvolatile operation. At this stage, the achieved\nendurance is already comparable to that of advanced flash memory devices1. In addition,\na comparison with recently reported reconfigurable logic-in-memory devices based on\nfloating-gate or charge-trapping mechanisms is summarized in Table R2, where our\ndevice shows a competitive endurance level.\nIt is also worth noting that, in certain operation scenarios, full program/erase cycles\nare not always required. Partial programming or incremental state modulation can be\nemployed, which significantly reduces the required voltage stress and is expected to\nfurther improve endurance robustness3.\nMore importantly, we would like to clarify that logic-in-memory applications do\nnot necessarily require the same endurance benchmarks as high-frequency CMOS logic.\nFor many logic-in-memory schemes, the programming operation (i.e., state setting) and\nlogic evaluation are decoupled4. In our device, once the nonvolatile reconfigurable\nchannel configuration (e.g., pn or np) is defined by a programming pulse, logic\noperations are performed through read or photo-induced modulation without repeated\nreprogramming. For example, under the photovoltaic operation mode, the logical\nswitching between states can be achieved simply by light on/off conditions after a single\nprogramming event, eliminating the need for frequent program/erase cycles.\nTherefore, the effective endurance requirement for logic computation in our\narchitecture is substantially lower than the raw program/erase cycling endurance. While\nwe fully acknowledge that further endurance improvements are desirable and will be\npursued in future work, we believe the current endurance level is sufficient to support\nthe demonstrated reconfigurable logic-in-memory and multifunctional operation modes.\nFigure R15. Endurance test of the device.\nReference:\n[1] Shao, H., et al. A novel FeFET array-based PUF: Co-optimization of entropy source\nand CRP generation for enhanced robustness in IoT security. Proc. IEEE Int. Electron\nDevices Meet. 2023, 1–4 (2023).\n[2] Zhou, Y., et al. A reliable 2-bit MLC FeFET with high uniformity and 10⁹ endurance\nby gate stack and write pulse co-optimization. Proc. IEEE Eur. Solid-State Electron.\nRes. Conf. 2024, 1–4 (2024).\n[3] Jiang, Y. et al. A scalable integration process for ultrafast two-dimensional flash\nmemory. Nat. Electron. 7, 868–875 (2024).\n[4] Lu, T., et al. Two-dimensional fully ferroelectric-gated hybrid computing-in-\nmemory hardware for high-precision and energy-efficient dynamic tracking. Sci. Adv.\n10, eadp0174 (2024).\n[5] Yu, J. et al. Simultaneously ultrafast and robust two-dimensional flash memory\ndevices based on phase-engineered edge contacts. Nat. Commun. 14, 5662 (2023).\n[6] Migliato Marega, G. et al. Logic-in-memory based on an atomically thin\nsemiconductor. Nature 587, 72–77 (2020).\nComment 5:\nWhile the manuscript emphasizes the integration of photodetection with memory and\nlogic, the real advantage of such multifunctionality is unclear. Most transistors exhibit\nsome degree of photoresponse, so it is not obvious what unique benefit is achieved by\ncoupling ferroelectric polarization with tunneling in this context. The authors should\nbetter explain what concrete advantage is offered by combining these functionalities,\nbeyond showing that each function is separately possible.\nReply:\nImportantly, the proposed FeFGRT architecture is not a simple aggregation of\nindependent functions. Instead, it exploits the heterogeneous and mutually distinct\nimpacts of ferroelectric polarization and charge tunneling on the channel under the same\ngate-pulse stimulus, enabling the formation of a robust nonvolatile pn junction with a\nstrong built-in electric field. This coupling mechanism ensures that the pn junction\nis simultaneously stabilized by both mechanisms, which cannot be achieved by\nferroelectric or floating-gate control alone, highlighting the unique advantage of\nour approach.\nTo verify the robustness and universality of this mechanism, we fabricated nine\ndevices with similar structures. Under identical programming pulse conditions, all four\nchannel configurations (nn, pp, np, and pn) can be reliably and reproducibly realized,\nas shown in Fig. R16. This high consistency originates from the strong localized\nelectric fields jointly induced by the floating gate and ferroelectric polarization,\nwhich stabilize the PN junction and result in a much stronger built-in field than\nthat achievable in semi-floating-gate or purely electrostatic gating schemes.\nThe resulting strong and nonvolatile built-in electric field provides the key\nadvantage for photodetection, enabling a stable photovoltaic response without\ncontinuous external bias, which translates into low-power, self-powered operation.\nMoreover, the distinct programming voltage thresholds of ferroelectric switching and\ncharge tunneling provide additional degrees of freedom for operation-mode engineering,\nallowing independent and decoupled control in a single device. We can achieve stable\nself-powered operation and implement complex logic functions such as XNOR under\nphoto-electrical co-modulation. These operations are enabled by the heterojunction\ndesign and the synergistic coupling of the two mechanisms.\nOverall, it is the synergistic coupling of ferroelectric polarization and floating-gate\ntunneling that uniquely enables multifunctional, low-power, and reconfigurable device\nbehavior beyond what each mechanism alone could achieve, providing a clear and\ntangible advantage of our FeFGRT architecture.\nFigure R16. Reconfigurable programming of pp, pn, nn, and np configurations\nunder identical programming conditions across nine different devices.\nReviewer #3\nIn the manuscript ‘Modulation Effect of Coupled Polarization Dynamics and Tunneling\nfor Controllable Reconfiguration in Ferroelectric Heterojunction’ by C. Li, et al., the\nauthors report the design and demonstration of a para-transistor based on a\nMoTe₂/hBN/CuInP₂S₆ (CIPS)-multilayer graphene (MLG) stack. The key innovation is\nthe coupling of ferroelectric polarization and charge tunneling, which enables multi-\nmode, nonvolatile reconfigurable operation within a single device. In addition, the\ndevice shows good photo-response, demonstrating responsivity ~ 500 mA/W,\ndetectivity ~ 3.1x1012 Jones, and high EQE of 120 % under 520 nm wavelength\nillumination.\nThe contents in this study seems meaningful as it achieved multiple of functionality\nbased on single transistor with parallel dielectric stack, showing various logic applications such\nas XNOR and NOR gate and photo-response characteristics. However, there are several\nstatements to be reconsidered and questions need to be addressed to clarify the point of this\nmanuscript. Especially, the second demonstration of XNOR gate in Figure 5 doesn’t make sense.\nTherefore, I do not recommend the manuscript to be published in Nature Communications in the\ncurrent status. At least major is necessary regarding the following questions.\nReply:\nWe sincerely thank the reviewer for the careful reading of our manuscript and for\nthe positive assessment of the device concept and multifunctional integration. We\nappreciate the recognition that our para-transistor architecture enables multiple\nfunctionalities—including nonvolatile reconfigurable logic and photodetection—\nwithin a single device based on a parallel dielectric stack.\nWe also acknowledge the reviewer’s concerns regarding the clarity and correctness\nof certain statements in the manuscript, particularly the second demonstration of the\nXNOR operation in Fig. 5. We agree that the current presentation may lead to confusion\nand does not sufficiently clarify the logical definition and operational conditions of the\nXNOR function. In the revised manuscript, we have carefully re-examined this part and\nmade substantial revisions to address these issues, as detailed below.\nWe hope that the point-by-point responses and revisions presented in the following\nsections can effectively clarify the reviewer’s concerns and significantly improve the\nquality and rigor of the manuscript.\nComment 1:\nIn the manuscript, the authors are using the term ‘para-transistor’. I haven’t seems this\nterminology. As far as I understood, they might use the term due to the architecture\nwhere two different stack of h-BN/CIPS and h-BN/MLG are located in parallel. To\nprovide sufficient information, sufficient explanation or reference should be provided\nfor this terminology.\nReply:\nWe sincerely thank the reviewer for pointing out the ambiguity regarding the term\n“para-transistor”.\nIn response to this comment, we have removed the term “para-transistor (PT)”\nentirely from the revised manuscript. Instead, we now consistently refer to our device\nas a ferroelectric floating-gate reconfigurable transistor (FeFGRT). This revised\nterminology more accurately reflects both the device architecture and the underlying\nphysical mechanisms, namely the coupled modulation of the channel by ferroelectric\npolarization and floating-gate charge tunneling, as well as the resulting nonvolatile and\nreconfigurable functionalities.\nWe hope that these revisions clarify the device concept, remove ambiguity\nassociated with terminology, and more clearly convey the motivation and contributions\nof this work. We believe that these changes help to address the reviewer’s concerns and\nfurther improve the clarity and quality of the manuscript.\nRevision:\nThe revisions to the Introduction are as follows:\n“In this work, we design a ferroelectric floating-gate reconfigurable transistor\n(FeFGRT) based on the molybdenum telluride/hexagonal boron nitride/copper indium\nphosphorus sulfide-multilayer graphene (MoTe\n2\n/hBN/CIPS-MLG), ultimately\nrealizing an all-in-one electronic device.”\nComment 2:\nThe transistor seems to have quite well-balanced ambipolar characteristics for hole and\nelectron conduction (similar on-state current for p- and n-type conduction), which is\nusually hard to get. How the authors achieved this balanced ambipolar characteristics\nwith simple Cr/Au contact? The author have to provide an explanation or reference on\nthat point as this good ambipolar characteristics enabled the reconfigurable transistor\nfunctionality.\nReply:\nWe sincerely thank the reviewer for raising this important point regarding the well-\nbalanced ambipolar transport in our device, which indeed plays a critical role in\nenabling the reconfigurable transistor functionality.\nIt is well known that semiconducting TMDs can exhibit ambipolar transport under\nsufficiently strong gate modulation, regardless of their intrinsic doping levels1-3.\nHowever, in conventional FETs employing low-κ gate dielectrics such as SiO₂, the gate\ncapacitance is typically insufficient to fully induce ambipolar conduction, which limits\nthe simultaneous realization of balanced electron and hole transport4.\nFirst, we performed four-probe measurements to simultaneously monitor the\nchannel current and the floating-gate potential. As shown in Fig. R17, by sweeping the\nV , both I and V were extracted. It can be clearly observed that the p-branch and\nCG DS FG\nn-branch currents extracted from Fig. R17a and Fig. R17d closely follow the evolution\nof the floating-gate potential V . This indicates that the presence of the floating gate\nFG\nsignificantly enhances the gate coupling, enabling the channel to be strongly modulated\nby the floating-gate potential. It should be noted that the monitoring of the floating-gate\npotential does not affect the measurement of the I\nDS\n5. To further clarify the transport\nmechanism, we compared the temperature-dependent transfer characteristics of a\nconventional FET and the FGFET, as shown in Fig. R18. For the conventional FET, the\ntransfer curves exhibit strong temperature dependence, indicating that even under high\ngate bias the channel transport is still dominated by thermionic emission. In contrast,\nfor the FGFET, temperature dependence is only observed when V is in the low-\nFG\nvoltage regime, whereas in the high-voltage regime the transport is dominated by FN\ntunneling, resulting in weak temperature dependence.\nFigure R17. (a, d) I\nDS\nand V\nFG\nmeasured simultaneously as a function of V\nCG\n. (b-c, e-f) Dependence of I on V , indicating that the channel conduction is dominantly\nDS FG\ngoverned by the floating-gate potential rather than direct control-gate coupling.\nFigure R18.Temperature-dependent transport characteristics. Schematic of the\nconventional FET (a) and FGFET (b) architectures together with the measurement setup.\n(c, d) Transfer characteristics.\nTo provide a more direct comparison, we further designed low-temperature (100\nK) measurements comparing the FGFET with a semi-floating-gate (SFG) architecture,\nas shown in Fig. R19. For the FGFET, the off state current is further suppressed at low\ntemperature, while the on state current remains nearly unchanged. In contrast, for the\nSFG architecture, the on state current increases with the expanded V sweeping range.\nCG\nFigure R19. Transfer characteristics of FGFET (a) and SFG (b) under different V\nCG\nsweep ranges at 100 K.\nFigure R20. I and V measured simultaneously as a function of V . Dependence\nDS FG CG\nof I on V .\nDS FG\nFigure R21. I and V measured simultaneously as a function of V .\nDS FG CG\nThis difference can be understood by analyzing the floating-gate potential. As\nshown in Fig. R20, the transfer characteristics of the FGFET at low temperature closely\nfollow the evolution of V , confirming that the channel is dominantly governed by the\nFG\nfloating-gate potential.\nAs shown in Fig. R21, for the SFG architecture, increasing the sweep range does\nnot lead to a corresponding change in the floating-gate potential , indicating that the\nchannel conduction is primarily governed by the control gate. This behavior originates\nfrom the fact that carrier transport in the SFG device is dominated by thermionic\nemission; consequently, the on state current is strongly temperature-dependent and\nfundamentally limited at low temperatures. Furthermore, it is important to note that the\nwell-balanced ambipolar characteristics observed in the FeFET transfer curves\noriginate from a similar mechanism. During the V sweep, the strong local electric\nCG\nfield induced by the ferroelectric polarization effectively modulates the contact barriers.\nThis polarization-enhanced field facilitates the efficient injection of both electrons and\nholes, thereby promoting the symmetrical ambipolar transport observed in our devices.\nWe hope that these systematic experimental results can effectively address the\nreviewer’s concerns and further strengthen the credibility of our conclusions.\nReference:\n[1] Lezama, I. G. et al. Inducing superconductivity in a transition metal dichalcogenide\nby electrostatic gating. 2D Mater. 1, 021002 (2014).\n[2] Zhang, Y. et al. Ambipolar MoS₂ thin flake transistors. Nano Lett. 12, 1136–1140\n(2012).\n[3] Braga, D. et al. Quantitative determination of the band gap of WS₂ with ambipolar\nionic liquid–gated transistors. Nano Lett. 12, 5218–5223 (2012).\n[4] Qu, D. et al. Carrier-type modulation and ambipolar transport in graphene–MoS₂\nheterostructures. Adv. Mater. 29, 1606433 (2017).\n[5] Sasaki, T. et al. Understanding the memory window overestimation of 2D materials–\nbased floating-gate-type memory devices by measuring floating-gate voltage. Small 16,\n2004907 (2020).\nComment 3:\nAlthough the authors argue that this device can simplify the circuit design in the\nsentence “In summary, our device demonstrates considerable potential in memory,\ncomputing, logic, and photodetection, providing a solution for simplifying integrated\ncircuit designs and enabling logic-in-memory computing.”, this argument doesn’t seem\npractically right. First of all, the design is considerably hard to be processed in fab.\nTo realize the device integration based on the transistor shown in this study, CIPS and\nmultilayer graphene should be deposited or transferred and then patterned in the same\nlayer or in parallel. Is there any possible solution to overcome this limitation?\nReply:\nWe sincerely thank the reviewer for raising this important and practical concern\nregarding fabrication complexity and circuit-level simplification.\nIt should be noted that achieving large-scale, array-level multifunctional systems\nbased on 2D materials and their heterostructures remains a widely recognized\nchallenge1. International research on 2D semiconductors is still at an exploratory stage,\nand large-scale applications have yet to be realized. Nevertheless, this limitation is\ngradually being overcome, for example through the recent successful development of\nfully functional 2D–Si hybrid flash memory chips compatible with CMOS technology2.\nWe would like to clarify that the statement regarding “simplifying integrated circuit\ndesigns” refers primarily to functional and architectural simplification at the device and\ncircuit level, rather than implying that the current fabrication process is simpler than\nconventional CMOS fabrication. Specifically, our FeFGRT integrates nonvolatile\nmemory, logic, and photodetection functionalities into a single transistor unit, thereby\nreducing the number of discrete devices, interconnects, and peripheral circuits that are\ntypically required in conventional architectures.\nIt should be noted that the four channel electrodes implemented in our device are\nprimarily used to facilitate a clearer experimental verification of the ferroelectric and\nfloating-gate functionalities, as well as to distinguish their respective programming\nvoltage thresholds and operating regimes. Importantly, the presence of four electrodes\nis not a requirement for practical operation. Even with only two channel electrodes (E1\nand E4), the device is fully capable of integrating nonvolatile memory, logic,\ncomputing, and sensing functionalities within a single transistor unit. Therefore, the\nadditional electrodes serve an experimental and diagnostic purpose rather than representing an\nintrinsic increase in architectural complexity. This ensures reliable identification of the\ncoupled effects of ferroelectric polarization and charge tunneling, while preserving the\nsingle-transistor nature and multifunctional potential of the proposed architecture.\nRegarding fabrication, we acknowledge that the present device involves multiple\ntwo-dimensional materials, including CIPS and multilayer graphene, which introduces\nprocessing challenges. However, recent advances in large-area synthesis, transfer, and\netching-assisted integration of 2D materials provide feasible pathways toward scalable\nfabrication. Wafer-scale or centimeter-scale growth of graphene, hBN, and TMDs has\nbeen widely demonstrated, and etching-assisted transfer and layer-by-layer stacking\nhave been successfully used to fabricate high-density 2D device arrays3-7. Although\nlarge-area growth of CIPS remains challenging, patterning and etching-based\nmicrofabrication processes provide a promising pathway toward array-level\nimplementation and device integration8, 9. Accordingly, the proposed FeFGRT device\ncan be fabricated by first patterning the CIPS layer, followed by a transfer- and etching-\nassisted stacking process for MLG, hBN, and MoTe in a sequential manner, thereby\n2\ncompleting the overall device architecture.\nImportantly, the advantage of our architecture lies in enabling reconfigurable\nmemory, logic, and sensing functionalities within a single transistor, thereby reducing\nthe required transistor count, lowering overall energy consumption, and extending\noptoelectronic–electrical co-integration architectures. Such an approach is particularly\nattractive for in-sensor computing, edge intelligence, and low-power reconfigurable\nsystems11.\nWe hope this clarification adequately addresses the reviewer’s concern.\nReference:\n[1] Thomas, S. An industry view on two-dimensional materials in electronics. Nat.\nElectron. 4, 856–857 (2021).\n[2] Liu, C. et al. A full-featured 2D flash chip enabled by system integration. Nature\n638, 590–597 (2025).\n[3] Chen, B. et al. Edge-feeding synchronous epitaxy of layer-controlled graphene films\non heterogeneous catalytic substrates. Nat. Commun. 16, 5490 (2025).\n[4] Wang, L. et al. Epitaxial growth of a 100-square-centimetre single-crystal hexagonal\nboron nitride monolayer on copper. Nature 570, 91–95 (2019).\n[5] Xu, X. et al. Seeded 2D epitaxy of large-area single-crystal films of the van der\nWaals semiconductor 2H-MoTe₂. Science 372, 195–200 (2021).\n[6] Fukamachi, S. et al. Large-area synthesis and transfer of multilayer hexagonal boron\nnitride for enhanced graphene device arrays. Nat. Electron. 6, 126–136 (2023).\n[7] Liu, L. et al. A mass transfer technology for high-density two-dimensional device\nintegration. Nat. Electron. 8, 135–146 (2025).\n[8] Li, M. et al. Memristors based on ferroelectric Cu-deficient copper indium\nthiophosphate for multilevel storage and neuromorphic computing. Small 21, 2412314\n(2025).\n[9] Zhong, Z. et al. Ionic–electronic photodetector for vision assistance with in-sensor\nimage processing. Nat. Commun. 16, 7096 (2025).\n[10] Tsai, M.-Y. et al. A reconfigurable transistor and memory based on a two-\ndimensional heterostructure and photoinduced trapping. Nat. Electron. 6, 755–764\n(2023).\n[11] Migliato Marega, G. et al. Logic-in-memory based on an atomically thin\nsemiconductor. Nature 587, 72–77 (2020).\nComment 4:\nFor the electrical voltage signal used for logic gate applications, the voltage\nconfiguration seems different from conventional logic signals. For example, VDS value\nof ±1 V is used in the first XNOR operation. However, in common logic gates, the VDS\nvalue have to pick only one polarity (minus or plus, depending on the transistor type)\nas VDD voltage is usually fixed. VDS value of ±1 V doesn’t make sense in terms of\npractical logic operation. And in the second XNOR operation, VDS = 0 was used. It is\ntrivial that we get zero current at VDS = 0. If the authors’ argument is right, single\nfloating-gate transistor should be XNOR gate as well, because floating-gate transistor\nhave the truth table as below, which is nonsense.\nInput A (gate pulse) Input B (VDS) Output (IDS)\nProgram pulse 1 1\nProgram pulse 0 0\nErase pulse 1 0\nErase pulse 0 0\nReply:\nWe sincerely thank the reviewer for raising this important concern regarding the\nvoltage configuration used in the logic demonstrations.\nTo address this issue, we have revised the logic operation scheme in the manuscript.\nIn the updated demonstration, the control gate pulse and light illumination are explicitly\ndefined as the two logic inputs. Specifically, V\nCG\n= 20 V and -20 V correspond to logic\n“1” and logic “0”, respectively, while the absence and presence of illumination\nrepresent logic “1” and “0”. The output logic state is determined by the drain current\nI with a threshold of 1 nA, and the readout is performed at a fixed and practical drain\nDS\nvoltage of V\nDS\n= 0.3 V.\nThe operating mechanism is schematically illustrated in Fig. R22a. When a positive\nprogramming pulse is applied, the channel is non-volatily configured into a pn junction.\nUnder illumination, a strong built-in electric field induces a photovoltaic effect. Since\nthe read voltage equals the open-circuit voltage, the channel remains in the off state (i).\nIn contrast, when a negative programming pulse is applied, the channel is configured\ninto an np junction, and illumination enhances carrier separation and collection, leading\nto an on state (ii). When the light is turned off, the pn junction formed after a positive\npulse becomes forward-biased under the fixed, yielding an on state (iii), whereas the np\njunction formed after a negative pulse is reverse-biased and remains in the off state (iv).\nBased on this revised configuration, both the measured current output and the\ncorresponding truth table clearly satisfy the XNOR logic function under a fixed read\nvoltage, avoiding the use of bipolar or zero drain biases. The updated experimental\nresults and logic truth table are provided in Fig. R22b, c, which now reflect a physically\nmeaningful and practically relevant logic-in-memory operation scheme.\nIn addition to the aforementioned approach, XNOR logic functionality is also\nrealized based on the FGFET architecture. Owing to the well-demonstrated ambipolar\nbehavior of the FGFET, gate pulses with different polarities and amplitudes can be\nconfigured to enable flexible control of the channel state1, 2.\nAs illustrated in Fig. R23a-b, for a device initially in its pristine state, the\napplication of a large positive gate pulse programs the channel into a p-type on state,\nwhereas a subsequent small-amplitude negative pulse erases the programmed state,\nswitching the channel to the off state. Conversely, when a large negative gate pulse is\napplied to the initial state, the channel is programmed into an n-type on state, and a\nfollowing small-amplitude negative pulse can similarly erase the programmed state and\nreturn the channel to the off state.\nIn contrast, two consecutive positive pulses or two consecutive negative pulses do\nnot alter the channel state, allowing the device to remain in the on state. The\ncorresponding experimental results and the truth table are shown in Fig. R23c,d.\nWe believe that these revisions clarify the logic operation principle and address the\nreviewer’s concerns regarding voltage configuration and practical logic implementation.\nIn addition, the NOR logic operation was also realized through appropriate\nmodifications of the operating scheme. Specifically, NOR logic was re-demonstrated\nby sequentially applying flexibly configured gate voltage pulses while fixing V = 1 V.\nDS\nAs shown in Fig. R24a, when two consecutive −20 V pulses are applied, the\nchannel is configured into an np junction, and the reverse-biased I remains in the off\nDS\nstate (i). When only a single −20 V pulse is applied and the second pulse is omitted, the\nchannel is similarly configured into an np junction, and the reverse-biased I\nDS\nalso\nremains in the off state (ii). In contrast, when a +20 V pulse is applied first to configure\nthe channel into a pn junction, followed by a −20 V pulse that reconfigures the channel\ninto an np junction, the reverse-biased I\nDS\nagain stays in the off state (iii). However,\nwhen a +20 V pulse is applied first and no second pulse is applied, the channel remains\nconfigured as a p–n junction, and the forward-biased I\nDS\nswitches to the on state (iv).\nThe corresponding NOR logic-in-memory characteristics are presented in Fig. R24b,\nand the truth table for the NOR logic operation is summarized in Fig. R24c.\nWe hope that our response adequately addresses the reviewer’s concerns.\nFigure R22. (a) Schematic of XNOR in-memory-logic based on dual-input operation\nenabled by V and light. For the gate pulse voltage inputs, a logic “1” corresponds to\nCG\n+20 V, while a logic “0” corresponds to -20 V. For the optical input signal, logic “0” is\ndefined as the light on state, whereas logic “1” corresponds to the light off state.\nTherefore, cases (i), (ii), (iii), and (iv) correspond to input combinations “10”, “00”,\n“11”, and “01”, respectively. (b) The XNOR logic-in-memory behavior is realized by\nusing V pulses and light as logic inputs, while the I serves as the logic output.\nCG DS\n(c) Truth table for XNOR logic-in-memory computing.\nFigure R23. (a) An FGFET device in the initial state, where a large positive voltage\npulse programs the channel into a p-type on state, followed by an appropriately\nconfigured negative voltage pulse that erases the programmed state and switches the\nchannel to the off state. (b) An FGFET device in the initial state, where a large negative\nvoltage pulse programs the channel into an n-type on state, followed by an appropriately\nconfigured positive voltage pulse that erases the programmed state and switches the\nchannel to the off state. (c) The XNOR logic-in-memory behavior is realized by\napplying two appropriately configured voltage pulses. (d) Truth table for XNOR logic-\nin-memory computing.\nFigure R24. (a) Schematic of NOR in-memory-logic based on dual-input operation\nenabled by two consecutive V\nCG\npulses. For the first gate pulse voltage inputs, a logic\n“1” corresponds to -20 V, while a logic “0” corresponds to +20 V. For the second gate\npulse voltage input, logic “1” corresponds to −20 V, while logic “0” corresponds to no\napplied pulse. Therefore, cases (i), (ii), (iii), and (iv) correspond to input combinations\n“11”, “10”, “01”, and “00”, respectively. (b) The NOR logic-in-memory behavior is\nrealized by applying two appropriately configured voltage pulses. (c) Truth table for\nNOR logic-in-memory computing.\nReference:\n[1] Li, W., et al. Reconfigurable floating-gate devices with ambipolar ReSe₂ channel:\ndual-mode storage, NMOS–PMOS transformation, logic functions, synapse\nsimulations, and positive and negative photoconductive effects. Adv. Funct. Mater. 35,\n2425359 (2025).\n[2] Yao, C., et al. Reconfigurable artificial synapse based on ambipolar floating-gate\nmemory. ACS Appl. Mater. Interfaces 15, 23573–23582 (2023).\nRevision:\nFigure 5 and its corresponding description have been modified in the revised\nmanuscript.\nComment 5:\nIn page 5, the statement “Using this scheme, both XNOR and NOR in-memory logic\noperations can be implemented with a single transistor, reducing the transistor count from 8 to 1\nfor XNOR, and from 2 to 1 for NOR, compared to conventional CMOS-based logic gate\ncircuits.” is exaggerated. In the demonstration in Figure 5, the output is current, not voltage\noutput. In the real logic gate circuit, the output should be voltage readout. In this respect, the\nactual logic circuit exploiting the transistor in this study will require at least one more transistor\nor resistor. The manuscript should be revised regarding this point.\nReply:\nWe thank the reviewer for this insightful comment. We agree that the statement\ncould be potentially confusing without specifying the output mode. To address this\nconcern, we have revised the manuscript by explicitly adding the condition “for XNOR\nlogic with current output” to clearly define the comparison scope.\nIn addition, we provide a detailed discussion on transistor count and output-mode\ndependence in Supplementary Note S2 of the Supplementary Information, where both\ncurrent-output and voltage-output logic implementations are systematically compared\nwith conventional CMOS-based logic circuits. We clarify that when voltage output is\nrequired, an additional load element (such as a resistor or depletion-mode transistor) is\nindeed necessary, and this point has now been clearly stated.\nWe hope that these revisions adequately clarify the logic implementation scheme\nand eliminate any potential misunderstanding.\nRevision:\n“Using this scheme, both XNOR and NOR in-memory logic operations can be\nimplemented with a single transistor, reducing the number of transistors from 8 to 1 for\nXNOR, and from 2 to 1 for NOR, compared to conventional CMOS-based current-\noutput logic gate circuits.”\n“For XNOR logic with current output, remarkably, a single FeFGRT device can\nimplement the logic function, reducing the number of transistors required compared to\ntraditional CMOS-based logic circuits from 8 to 1—corresponding to an 87.5%\nreduction.”\n“In addition to the advantages of logic-in-memory, for NAND logic with current\noutput, the number of transistors is reduced from 2 to 1, yielding a 50% hardware\nsaving.”\nComment 6:\nThe band diagram in Figure 1e is wrong. The band of MLG is not Dirac cone. It is\nparabolic.\nReply:\nWe sincerely thank the reviewer for the valuable comments. In response to these\nconcerns, the corresponding figures and descriptions have been carefully revised and\nupdated at the appropriate locations in the manuscript.\nRevision:\nThe energy band schematics of graphene in Fig. 1 and Fig. 3 have been correspondingly\nrevised and refined in the manuscript.\nFig. 1 | Schematic illustration of the FeFGRT and its multi-functional characteristics. a, The\noptical image of the device. The regions outlined by orange, blue, black, and green dashed lines\ncorrespond to MoTe₂, hBN, graphene, and CIPS, respectively. b, Schematic illustration of the\nmultifunctional heterojunction-based FeFGRT. The blue and red dashed regions correspond to the\nFeFET and FGFET structures, respectively. Importantly, the full multifunctional including memory,\nlogic, and photodetection can still be realized only using E1 and E4. The purpose of E2 and E3 are\nonly intended to facilitate the independent characterization of the FeFET and FGFET operation\nmodes. c, d, Structural schematics of the FeFET (c) and FGFET (d), along with the polarization and\ntunneling band bending diagrams under electric field modulation. e, Cross-sectional TEM image\nand the corresponding EDS mapping of the MoTe₂/hBN/MLG heterostructure. f, Cross-sectional\nTEM image and the corresponding EDS mapping of the MoTe₂/hBN/CIPS heterostructure. g, h,\nReconfigurable behavior of the np (g) and pn (h) junctions under the dual coupling of ferroelectric\npolarization and charge tunneling. i, j, Multimode modulation based on threshold differences, where\n(i) corresponds to the nn mode and (j) corresponds to the pp mode.\nFig. 3 | Reconfigurable characteristics of FeFGRT based on the coupled effect of ferroelectric\npolarization and charge tunneling. a, The output characteristic curves of the four configurations\n(pn, np, pp, nn). Among them, the np and pn modes are defined by -/+20 V pulses, while the pp and\nnn modes are derived from the pn and np modes through subsequent switching with +5 V/-5 V\npulses. In this case, E1 and E4 correspond to the S and D, respectively. b, c, The np-to-nn mode (b)\nand pn-to-pp (c) mode transition are controlled by varying the number of applied electrical pulses.\nHere, E1 and E4 represent the S and D, respectively. d, Within a small voltage scanning range, the\ntransfer characteristics of the FGFET, enabling nonvolatile reconfigurable tuning through the\napplication of positive and negative voltage pulses. E3 and E4 serve as the S and D. e, f, The\ntransition of FeFGRT from the np to the pn mode (e) and from the pn to the np mode (f) is modulated\nby applying high-amplitude positive and negative voltage pulse sequences, respectively. E1 and E4\ncorrespond to the S and D, respectively. g-j, Schematic illustration of the reconfigurable band\nalignment of FeFGRT under electric pulse modulation, including np mode tuning by large negative\npulses (g), pn mode by large positive pulses (h), pp mode by large positive and small negative pulses\n(i), and nn mode by large negative and small positive pulses (j). E1 and E4 correspond to the S and\nD, respectively.\nComment 7:\nFor photo-switching in Figure 4f, the speed or time constant of on and off operation\nneed to be provided.\nReply:\nWe sincerely thank the reviewer for this valuable comment. The photo-switching\nspeed is indeed a critical performance metric for photodetectors. In the original\nmanuscript, Fig. 4f was primarily intended to demonstrate the stable and repeatable\nphoto-switching cycles of the device\nTo further characterize the photo-switching speed of our device, we performed\nadditional measurements using light pulses with a pulse width of 500 ms. The rise and\ndecay times were extracted by measuring the time required for the photocurrent to\nchange between 10% and 90% of the maximum photocurrent. As a result, a rise time of\n3.7 ms and a decay time of 4.3 ms were obtained, as shown in Fig. R25.\nWe hope that this clarification and the additional experimental data can address the\nreviewer’s concern and further improve the completeness and clarity of the manuscript.\nFigure R25. Response time of the device under 520 nm illumination when P\nin\n=\n3.533 mW/cm2.\nComment 8:\nFor calculations of responsivity, detectivity in page 10, the authors introduced a\nquantity S, ‘effective’ area of the channel. The way how this quantity is defined have to\nbe clarified.\nReply:\nWe thank the reviewer for raising this important question regarding the definition\nof the effective channel area S, which is indeed a key parameter for accurately\nevaluating the responsivity and detectivity of photodetectors. To improve the rigor and\nclarity of the manuscript, we have carefully reanalyzed and clarified the definition of S\nbased on classical photodetection theory and the specific characteristics of 2D devices.\nIn conventional photodetection theory, the effective area of a device is often\ndistinguished into an optical effective area (A ) and an electrical effective area (Ae)1.\nd\nThe Ae is usually introduced as a phenomenological parameter for estimating various\nnoise sources (e.g., thermal generation–recombination noise). By contrast, the A plays\nd\na more critical role in evaluating photodetector performance1. For 2D material–based\nphotodetectors, however, the definition of A is not universal and strongly depends on\nd\nthe device geometry, operation mode, and measurement configuration2.\nIn the literature, several representative scenarios have been discussed3. (1) For\nphotoconductive devices, all photogenerated electron–hole pairs created in the region\nbregion\nbetween the two electrodes can contribute to the photoconductive effect. Therefore, the\noptical effective area A should be defined as the entire area of the photoactive material\nd\ncovered between the electrodes (Fig. R26a(i)). (2) For in-plane junction devices\noperating under zero-bias or reverse-bias conditions, the spatial width of the junction is\noften difficult to estimate accurately. To avoid introducing large uncertainties, it is\nrecommended to define A as the total area of the photoactive material between the\nd\nelectrodes (Fig. R26a(ii)). (3) For vertical junction devices operating under zero-bias\nconditions, photocurrent mapping results reported in most studies indicate that the\nphotoresponse predominantly originates from the junction region. Without loss of\ngenerality, the junction area can therefore be regarded as the optical effective area A in\nd\nthis case (Fig. R26a(iii)). (4) Once a vertical junction device operates under reverse-\nbias conditions, the potential drop extends beyond the junction region. As a result, using\nthe junction area alone as the optical effective area is no longer accurate, and the entire\narea of the photoactive material between the electrodes should be taken as A (Fig.\nd\nR26a(iv)).\nFor our device, as illustrated in Fig. R26b, the red dashed region represents the\neffective channel area. It is evident that our device configuration corresponds to the\ncase shown in Fig. R26a(ii) discussed above. In our previous calculations of the\neffective area, the regions covered by the E2 and E3 metal electrodes were excluded.\nHowever, according to the literature, this treatment may underestimate the actual\noptical effective area. Specifically, although the metal electrodes (E2 and E3) are\noptically opaque, diffraction occurs at the electrode edges, allowing part of the incident\noptical field to couple into the underlying semiconductor. In addition, owing to the\natomically thin nature of two-dimensional materials, light entering the multilayer\nheterostructure can undergo lateral scattering and redistribution, further enabling\nphotogeneration in regions adjacent to or partially beneath the electrodes. These effects\nindicate that the optically active area is not strictly limited to the geometrically exposed\nchannel region.\nAs a result, our previous definition of S likely led to an underestimation of the\neffective area. To more accurately evaluate the responsivity (R), external quantum\nefficiency (EQE), and related figures of merit, we redefined the effective area S by\ntaking the region enclosed by the red dashed line as the effective area, and provided a\ndetailed discussion of this issue in the Supplementary Information.\nWe believe that this clarification adequately addresses the reviewer’s concern and\nimproves the methodological transparency and completeness of the manuscript.\nFigure R26. (a) Schematic illustrations of the effective optical area definitions for\nseveral representative photodetector configurations. (b) Definition of the effective area\nfor our device, indicated by the red dashed region.\nReference:\n[1] Rogalski, A. Infrared Detectors, 2nd edn. (CRC Press, 2010).\n[2] Piotrowski, J. et al. New generation of infrared photodetectors. Sens. Actuators A\nPhys. 67, 146–152 (1998).\n[3] Wang, F. et al. How to characterize figures of merit of two-dimensional\nphotodetectors. Nat. Commun. 14, 2224 (2023).\nComment 9:\nIn photo-response, the device shows EQE over 100 %. This EQE is not able to be\nachieved in usual photo diode. What is the underlying mechanism for this EQE over\n100 %? Is it photo-gating or is there other multiplication mechanism? If not, this value\ncan be exaggerated due to not well defined channel area.\nReply:\nWe sincerely thank the reviewer for raising this important question. In response,\nwe have carefully re-evaluated the effective area of the device. As shown in Fig. R26b,\nthe region enclosed by the red dashed line corresponds to the effective area, which is\ndetermined to be 276 μm². Based on this revised effective area, we have recalculated\nand corrected the R, D*, EQE, and other related performance metrics. As a result, the\nrevised EQE is 91.4%.\nWe hope that this clarification adequately addresses the reviewer’s concern and\nhelps improve the accuracy and completeness of the manuscript.\nPoint-by-Point Response to Reviewers’ Comments\nWe sincerely thank the reviewers for the recognition and positive evaluation of our\nmanuscript. In response to the reviewers’ comments, we have supplemented additional\nexperiments and analyses to provide sufficient data and evidence to address the\nconcerns and clarify any remaining uncertainties. The responses to the reviewers’\ncomments are marked in blue.\nReviewer #1\nThe authors have addressed all my concerns and clarified unclear points of the initial\nsubmission. I can recommend now the publication of this manuscript.\nReply:\nWe sincerely thank the reviewer for the positive comments on our manuscript.\nReviewer #2\nComment 1:\nRather than directly addressing the endurance limitation relative to logic-level\nbenchmarks, the authors redefine the operational paradigm of logic-in-memory to argue\nthat such endurance is unnecessary. A similar reframing is applied to the speed concern\nby separating programming speed from logic evaluation. While these arguments may\nbe valid for certain stateful, reconfigurable, or infrequently reprogrammed use cases,\nthey weaken the manuscript’s positioning as a general and practically viable logic-in-\nmemory solution.\nFurthermore, although Table R2 shows that slow programming speed and high\noperating voltage are common among previously reported logic-in-memory devices,\nthis comparison mainly contextualizes existing limitations in the field rather than\ndemonstrating that the proposed device overcomes them or offers a clear performance\nadvantage over prior art.\nAs a result, it remains unclear what concrete benefit the proposed approach provides\nbeyond an alternative physical realization. The present work appears to primarily\ndemonstrate a different device concept based on coupled ferroelectric polarization and\nfloating-gate tunneling, without clearly improving the key performance metrics such as\nendurance, speed, operating voltage, or scalability that currently limit the practical\nadoption of logic-in-memory technologies.\nReply:\nWe sincerely thank the reviewer for the constructive comments. We agree that\nendurance and speed are key metrics for logic computing. However, we would like to\nclarify that the endurance discussed in our manuscript refers to the memory endurance,\ni.e., the number of program/erase operations associated with charge tunneling or\nferroelectric polarization switching. In our reconfigurable scheme, this metric is not\nnecessarily the same as the number of logic operations executed.\nSpecifically, in our logic-input configuration, some operations do not require\nprogram/erase operations (i.e., they do not trigger charge tunneling or ferroelectric\npolarization switching). For example, when V =0 V is used as a logic input, no\nCG\nprogramming/erasing process is involved. In addition, certain logic inputs may program\nonly the FeFET part without affecting the FGFET part. For instance, when V\nCG\n=5 V is\napplied, the operation primarily addresses the ferroelectric-gated channel while leaving\nthe floating-gate state unchanged. Therefore, the number of logic evaluations is not\nnecessarily the same as the number of program/erase cycles.\nTo further strengthen the endurance evidence, we have extended the endurance test\nto 6×105 cycles, which demonstrates the robust cycling stability of our device. However,\nthe endurance we report is also competitive and relatively high compared with\nmany state-of-the-art flash-memory devices.[1-3] Moreover, hBN is known to undergo\na layer-by-layer breakdown behavior, which is advantageous for serving as a\ntunneling dielectric and can help mitigate catastrophic failure during repeated\nstress.[4]\nRegarding speed, we clarify that the limitation discussed here primarily\ncorresponds to the state programming speed, rather than the intrinsic speed of logic\nevaluation.\nFigure R1. Endurance test of the device.\nFigure R2. Transfer characteristic of the FeFET.\nIn addition, Tables R1–R2 indicate that high programming voltage and slow\nprogramming speed are well-known limitations across many reported reconfigurable\nand memory-based logic-in-memory devices. Importantly, the comparison also\nshows that our architecture offers competitive advantages in programming\nconditions, including lower programming voltage amplitude and shorter pulse\nwidth relative to representative state-of-the-art devices. Moreover, in conventional\nflash memories, high programming voltage is commonly enabled using charge-pump\ncircuits that boost the supply voltage to tens of volts for tunneling, and such a system-\nlevel strategy is widely adopted in practical nonvolatile memories.[5, 6] Finally, as shown\nin Fig. R2, we achieve stable ferroelectric memory behavior under a bidirectional gate\nsweep within ±2 V (with a threshold-voltage shift exceeding 1.5 V, which is sufficient\nfor memory applications)[7], directly supporting the potential for low-voltage operation.\nMost importantly, the key advantage of our coupled ferroelectric polarization–\ncharge tunneling mechanism is that it enables four stable, nonvolatile, and\nreconfigurable configurations through different pulse schemes. We further confirm the\ndevice-to-device reproducibility of these multistate configurations. This robust and\nprogrammable multi-configuration capability is essential for our demonstration\nof integrated optoelectronic sensing, memory, and computing within a single\ndevice platform. We hope that these clarifications and additional results address the\nreviewer’s concerns.\nReference:\n[1] Wang, Y. et al. 11-bit two-dimensional floating-gate memories. Nat. Commun. 16,\n9268 (2025).\n[2] Cai, Y. et al. 8-bit states in 2D floating-gate memories using gate-injection mode for\nlarge-scale convolutional neural networks. Nat. Commun. 16, 2649 (2025).\n[3] Xiang, Y. et al. Subnanosecond flash memory enabled by 2D-enhanced hot-carrier\ninjection. Nature 641, 90–97 (2025).\n[4] Hattori, Y., Taniguchi, T., Watanabe, K. & Nagashio, K. Layer-by-layer dielectric\nbreakdown of hexagonal boron nitride. ACS Nano 9, 916–921 (2015).\n[5] Rumberg, B., Graham, D. W. & Navidi, M. M. A regulated charge pump for\ntunneling floating-gate transistors. IEEE Trans. Circuits Syst. I: Regul. Pap. 64, 516–\n527 (2017).\n[6] Richard, J.-F. & Savaria, Y. High voltage charge pump using standard CMOS\ntechnology. In Proc. 2nd Annu. IEEE Northeast Workshop Circuits Syst. (NEWCAS\n2004) (Montreal, QC, Canada), 317–320 (2004).\n[7] Hong, A. J. et al. Graphene flash memory. ACS Nano 5, 7812–7817 (2011).\nComment 2:\nThe logic-in-memory demonstrations rely on a non-standard and problematic definition\nof logic inputs. Rather than employing concurrent, independently addressable electrical\ninputs, the manuscript encodes logic states through sequential gate-pulse programming\nand, in some cases, optical excitation. This temporal and modality-mixed encoding\neffectively transforms the logic operation into a state-programming-and-readout\nsequence rather than a true logic computation. Such an approach is fundamentally\nincompatible with conventional logic-in-memory concepts, as it precludes signal\ncascadability, fan-in/fan-out, and synchronous operation, thereby severely undermining\nthe claim of practical logic-in-memory functionality.\nReply:\nWe sincerely thank the reviewer for the constructive comments. We fully\nacknowledge the reviewer’s emphasis on the importance of concurrent, independently\naddressable electrical inputs in conventional logic-in-memory architectures. However,\nwe would like to clarify that in reconfigurable logic-in-memory, the logic variables are\nstored in nonvolatile states. Consequently, logic functions can be implemented through\ntime-sequenced electrical pulse operations, which may reduce the need for multiple\ngeometric input terminals while still enabling well-defined input encoding and logic\nevaluation.[1]\nTo further address the reviewer’s concern regarding “independently addressable\ninputs,” we clarify that our architecture supports reconfigurable operation using two\nindependent electrical inputs. Specifically, the floating-gate electrode and the Si back\ngate act as two separately addressable terminals: V modulates the channel region\nFG\nassociated with the FGFET component, while V controls the channel region\nCG\nassociated with the FeFET component. By applying pulse voltages to V and holding\nCG\nvoltages to V\nFG\n, we can tune distinct reconfigurable modes, as shown in Fig. R3. Similar\nschemes combining pulsed operations with held biases have also been reported in in-\nmemory computing and reconfigurable logic devices, supporting the feasibility of\nindependently addressable inputs within such stateful operation paradigms.[2]\nImportantly, the time-sequenced pulse approach adopted in our manuscript is also\nmotivated by energy considerations, as it avoids continuously applying a constant bias\nand thereby reduces static power consumption.\nRegarding the use of optical excitation, we clarify that light is introduced as an\noptoelectronic input modality to demonstrate integrated sensing–memory–\ncomputing functionality, rather than to replace electrical addressing. Notably, using\nlight (including intensity/position and temporal modulation) as logic inputs has been\nwidely explored as a viable route toward compact, energy-efficient, light-driven logic\nsystems.[3, 4]\nFigure R3. Schematic illustration of four reconfigurable configurations enabled by\nindependent V and V inputs.\nCG FG\nReference:\n[1] Li, W. et al. Reconfigurable floating-gate devices with ambipolar ReSe\n2\nchannel:\ndual-mode storage, NMOS–PMOS transformation, logic functions, synapse\nsimulations, positive and negative photoconductive effects. Adv. Funct. Mater. 35,\n2425359 (2025)\n[2] Sheng, Z. et al. Reconfigurable logic-in-memory computing based on a polarity-\ncontrollable two-dimensional transistor. Nano Lett. 23, 5242–5249 (2023).\n[3] He, T. et al. On-chip optoelectronic logic gates operating in the telecom band. Nat.\nPhoton. 18, 60–67 (2024).\n[4] Ahn, D. et al. Light-driven reconfigurable logic in a monolithic perovskite device\nvia nonlinear photoresponse switching. Adv. Mater. e09566 (2025).\nComment 3:\nIn addition, it should be noted that logic-in-memory architectures are conventionally\ndefined and evaluated based on purely electrical inputs, typically involving two or more\nvoltage-controlled signals that can be cascaded across logic stages. In this context, the\nintroduction of optical excitation as an additional logic input raises fundamental\nconcerns. Using light as a logic input departs from the standard logic-in-memory\nparadigm and significantly limits cascadability, as optical signals cannot be directly\npropagated or interfaced with subsequent electrical logic stages without additional\noptoelectronic conversion circuitry. As a result, it becomes unclear how the proposed\nlogic operations could be cascaded or integrated into larger-scale logic systems, which\nis a key requirement for practical logic-in-memory computing.\nReply:\nWe sincerely thank the reviewer for raising this important point. We agree that\nlogic-in-memory architectures are conventionally defined and evaluated with purely\nelectrical inputs and that cascadability across logic stages is a key system-level\nrequirement for large-scale logic circuits. In our work, optical excitation is introduced\nnot to redefine the standard logic-in-memory paradigm, but as an additional\noptoelectronic input modality to demonstrate integrated sensing–memory–computing\nfunctionality, where external physical stimuli can be directly mapped into\nprogrammable nonvolatile states and subsequent electrical readout.\nImportantly, using light as an input has strong precedent in optoelectronic logic and\nin-sensor computing, where the device receives optical stimuli and produces an\nelectrical output that can be interfaced with electronics.[1, 2] Moreover, introducing\noptical excitation enables a practical sensing–memory–computing co-integration\narchitecture, in which the sensory input can be processed and stored in situ at the\ndevice level.[3] This paradigm reduces unnecessary data transfer between separate\nsensing, memory, and computing units, thereby alleviating the von Neumann bottleneck\nand potentially improving the system energy efficiency for perception-oriented and\nedge computing tasks.[4] In our demonstration, light serves as a representative external\nstimulus to demonstrate how our platform can directly convert physical inputs into\nnonvolatile programmable states and electrical outputs, providing a compact route\ntoward integrated optoelectronic sensing and in-memory computation.\nReference:\n[1] He, T. et al. On-chip optoelectronic logic gates operating in the telecom band. Nat.\nPhoton. 18, 60–67 (2024).\n[2] Ahn, D. et al. Light-driven reconfigurable logic in a monolithic perovskite device\nvia nonlinear photoresponse switching. Adv. Mater. e09566 (2025).\n[3] Wu, G. et al. Ferroelectric-defined reconfigurable homojunctions for in-memory\nsensing and computing. Nat. Mater. 22, 1499–1506 (2023).\n[4] Dang, Z. et al. Object motion detection enabled by reconfigurable neuromorphic\nvision sensor under ferroelectric modulation. ACS Nano 18, 27727–27737 (2024).\nComment 4:\nThe assertion of “atomically sharp” and high-quality interfaces is largely qualitative\nand based on structural arguments. Direct electrical characterization of interface trap\ndensity would be necessary to support this claim.\nReply:\nTo quantitatively evaluate the interface trap density in our device, we employed the\nhigh–low frequency capacitance–voltage (C–V) method based on the measured C–V\ncharacteristics at low and high frequency limits.[1] The experimentally measured\ncapacitance per unit area can be expressed as:\n1\n𝐶\n−1\n1 1\n𝐶1 = ( + ) (1)\nWhere is the semicond\n𝐶\nuMcotoTre 2ca\n+\npa\n𝐶\nc𝑖i𝑡tanc\n𝐶\ne𝑔of MoTe\n2\n, is the capacitance\nof traps and is the geometric capacitance related to hBN layer and the vdW gap, all\n𝐶MoTe2 𝐶𝑖𝑡\nthe capacitance are normalized by area.\n𝐶𝑔\nBecause the interface traps can follow the AC signal at low frequency but cannot\nrespond at the high frequency limit, the interface trap density can be estimated\nfrom the difference between the low-frequency capacitance and high-frequency\n𝐷𝑖𝑡\ncapacitance as:\n𝐶𝐿𝐹\n𝐶𝐻𝐹\n−1 −1\n1 1 1 1\n𝑞𝐷𝑖𝑡 = ( − ) −( − ) (2)\nWhere is the elementa 𝐶 r𝐿y𝐹 ch 𝐶 a𝑔rge, and 𝐶 𝐻𝐹 𝐶 a𝑔nd are the measured\ncapacitances per unit area at the low- and high-frequency limits, respectively (\n𝑞 𝐶𝐿𝐹 𝐶𝐻𝐹\nand ).\n𝑓𝐿𝐹 =\nIn our structure, the geometric gate capacitance is primarily determined by the\n10 kHz 𝑓𝐻𝐹 = 1 MHz\nhBN dielectric layer, and can be approximated as: .\n𝐶𝑔\nIf an additional interfacial gap capacitance is considered, the effective\n𝐶𝑔 ≈ 𝐶ℎ𝐵𝑁\ngeometric capacitance can be expressed as:\n𝐶𝑖𝑛𝑡\n−1\n1 1\nHowever, , can b𝐶e 𝑔 w=e(ll\n𝐶\nℎa𝐵p𝑁pr+ox\n𝐶\nim𝑖𝑛a𝑡t)ed by without affecting (t3he)\nextracted .[2]\n𝐶𝑖𝑛𝑡 ≫ 𝐶ℎ𝐵𝑁 𝐶𝑔 𝐶ℎ𝐵𝑁\nThe ex\n𝐷\ntr𝑖𝑡acted exhibits a peak value of approximately 1.6×1012 cm-2eV-1 in the\ntransition region, w 𝐷 h 𝑖 i 𝑡 le in the accumulation region is reduced to around ~1×1011\ncm-2eV-1, as shown in Fig. R4. These results indicate𝐷 th𝑖𝑡at our heterostructure exhibits a\nrelatively low interface trap density compared with previously reported\nheterostructured devices.[3, 4] Moreover, prior work has suggested that when the\ninterface trap density is below ~1012 cm-2eV-1 its impact on the nonvolatile memory\nbehavior becomes negligible.[5]\nFigure R4. (a) C–V curves of the device measured at frequencies from 10 kHz to 1 MHz\nas a function of V . (b) Interface trap density extracted using the high–low\nFG\nfrequency method.\n𝐷𝑖𝑡\nTogether, these results provide quantitative electrical evidence supporting the\ninterface quality of our device, especially in the accumulation regime where device\noperation and readout are performed.\nReference:\n[1] Yu, J. et al. Simultaneously ultrafast and robust two-dimensional flash memory devices based\non phase-engineered edge contacts. Nat. Commun. 14, 5662 (2023).\n[2] Zhao, P. et al. Evaluation of border traps and interface traps in HfO /MoS gate stacks by\n2 2\ncapacitance–voltage analysis. 2D Mater. 5, 031002 (2018).\n[3] Zhao, P. et al. Probing Interface Defects in Top-Gated MoS Transistors with Impedance\n[4] Sebastian, A. et al. Benchmarking monolayer MoS and WS field-effect transistors. Nat.\n2 2\nCommun. 12, 693 (2021).\n[5] Giusi, G. M. et al. Impact of Interface Traps in Floating-Gate Memory Based on Monolayer\nMoS . IEEE Trans. Electron Devices 69, 6121–6126 (2022).\nThe authors answered all questions raised. And the point-by-point responses seem\nappropriately addresses the potential issues. Therefore, I recommend this manuscript to\nbe published in Nature Communications.\nReply:\nWe sincerely thank the reviewer for the positive comments on our manuscript."}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors have addressed all my concerns and clarified unclear points of the initial submission. i can recommend now the publication of this manuscript.", "reviewer_2": "1. Rather than directly addressing the endurance limitation relative to logic-level benchmarks, the authors redefine the operational paradigm of logic-in-memory to argue that such endurance is unnecessary. A similar reframing is applied to the speed concern by separating programming speed from logic evaluation. While these arguments may be valid for certain stateful, reconfigurable, or infrequently reprogrammed use cases, they weaken the manuscript’s positioning as a general and practically viable logic-in-memory solution.\nFurthermore, although Table R2 shows that slow programming speed and high operating voltage are common among previously reported logic-in-memory devices, this comparison mainly contextualizes existing limitations in the field rather than demonstrating that the proposed device overcomes them or offers a clear performance advantage over prior art.\nAs a result, it remains unclear what concrete benefit the proposed approach provides beyond an alternative physical realization. The present work appears to primarily demonstrate a different device concept based on coupled ferroelectric polarization and floating-gate tunneling, without clearly improving the key performance metrics such as endurance, speed, operating voltage, or scalability that currently limit the practical adoption of logic-in-memory technologies.\n2. The logic-in-memory demonstrations rely on a non-standard and problematic definition of logic inputs. Rather than employing concurrent, independently addressable electrical inputs, the manuscript encodes logic states through sequential gate-pulse programming and, in some cases, optical excitation. This temporal and modality-mixed encoding effectively transforms the logic operation into a state-programming-and-readout sequence rather than a true logic computation. Such an approach is fundamentally incompatible with conventional logic-in-memory concepts, as it precludes signal cascadability, fan-in/fan-out, and synchronous operation, thereby severely undermining the claim of practical logic-in-memory functionality.\n3. In addition, it should be noted that logic-in-memory architectures are conventionally defined and evaluated based on purely electrical inputs, typically involving two or more voltage-controlled signals that can be cascaded across logic stages. In this context, the introduction of optical excitation as an additional logic input raises fundamental concerns. Using light as a logic input departs from the standard logic-in-memory paradigm and significantly limits cascadability, as optical signals cannot be directly propagated or interfaced with subsequent electrical logic stages without additional optoelectronic conversion circuitry. As a result, it becomes unclear how the proposed logic operations could be cascaded or integrated into larger-scale logic systems, which is a key requirement for practical logic-in-memory computing.\n4. The assertion of “atomically sharp” and high-quality interfaces is largely qualitative and based on structural arguments. Direct electrical characterization of interface trap density would be necessary to support this claim.", "reviewer_3": "The authors answered all questions raised. And the point-by-point responses seem appropriately addresses the potential issues. Therefore, I recommend this manuscript to be published in Nature Communications."}, "author_response": "Point-by-Point Response to Reviewers’ Comments\nWe sincerely thank the reviewers for the recognition and positive evaluation of our\nmanuscript. In response to the reviewers’ comments, we have supplemented additional\nexperiments and analyses to provide sufficient data and evidence to address the\nconcerns and clarify any remaining uncertainties. The responses to the reviewers’\ncomments are marked in blue.\nReviewer #1\nThe authors have addressed all my concerns and clarified unclear points of the initial\nsubmission. I can recommend now the publication of this manuscript.\nReply:\nWe sincerely thank the reviewer for the positive comments on our manuscript.\nReviewer #2\nComment 1:\nRather than directly addressing the endurance limitation relative to logic-level\nbenchmarks, the authors redefine the operational paradigm of logic-in-memory to argue\nthat such endurance is unnecessary. A similar reframing is applied to the speed concern\nby separating programming speed from logic evaluation. While these arguments may\nbe valid for certain stateful, reconfigurable, or infrequently reprogrammed use cases,\nthey weaken the manuscript’s positioning as a general and practically viable logic-in-\nmemory solution.\nFurthermore, although Table R2 shows that slow programming speed and high\noperating voltage are common among previously reported logic-in-memory devices,\nthis comparison mainly contextualizes existing limitations in the field rather than\ndemonstrating that the proposed device overcomes them or offers a clear performance\nadvantage over prior art.\nAs a result, it remains unclear what concrete benefit the proposed approach provides\nbeyond an alternative physical realization. The present work appears to primarily\ndemonstrate a different device concept based on coupled ferroelectric polarization and\nfloating-gate tunneling, without clearly improving the key performance metrics such as\nendurance, speed, operating voltage, or scalability that currently limit the practical\nadoption of logic-in-memory technologies.\nReply:\nWe sincerely thank the reviewer for the constructive comments. We agree that\nendurance and speed are key metrics for logic computing. However, we would like to\nclarify that the endurance discussed in our manuscript refers to the memory endurance,\ni.e., the number of program/erase operations associated with charge tunneling or\nferroelectric polarization switching. In our reconfigurable scheme, this metric is not\nnecessarily the same as the number of logic operations executed.\nSpecifically, in our logic-input configuration, some operations do not require\nprogram/erase operations (i.e., they do not trigger charge tunneling or ferroelectric\npolarization switching). For example, when V =0 V is used as a logic input, no\nCG\nprogramming/erasing process is involved. In addition, certain logic inputs may program\nonly the FeFET part without affecting the FGFET part. For instance, when V\nCG\n=5 V is\napplied, the operation primarily addresses the ferroelectric-gated channel while leaving\nthe floating-gate state unchanged. Therefore, the number of logic evaluations is not\nnecessarily the same as the number of program/erase cycles.\nTo further strengthen the endurance evidence, we have extended the endurance test\nto 6×105 cycles, which demonstrates the robust cycling stability of our device. However,\nthe endurance we report is also competitive and relatively high compared with\nmany state-of-the-art flash-memory devices.[1-3] Moreover, hBN is known to undergo\na layer-by-layer breakdown behavior, which is advantageous for serving as a\ntunneling dielectric and can help mitigate catastrophic failure during repeated\nstress.[4]\nRegarding speed, we clarify that the limitation discussed here primarily\ncorresponds to the state programming speed, rather than the intrinsic speed of logic\nevaluation.\nFigure R1. Endurance test of the device.\nFigure R2. Transfer characteristic of the FeFET.\nIn addition, Tables R1–R2 indicate that high programming voltage and slow\nprogramming speed are well-known limitations across many reported reconfigurable\nand memory-based logic-in-memory devices. Importantly, the comparison also\nshows that our architecture offers competitive advantages in programming\nconditions, including lower programming voltage amplitude and shorter pulse\nwidth relative to representative state-of-the-art devices. Moreover, in conventional\nflash memories, high programming voltage is commonly enabled using charge-pump\ncircuits that boost the supply voltage to tens of volts for tunneling, and such a system-\nlevel strategy is widely adopted in practical nonvolatile memories.[5, 6] Finally, as shown\nin Fig. R2, we achieve stable ferroelectric memory behavior under a bidirectional gate\nsweep within ±2 V (with a threshold-voltage shift exceeding 1.5 V, which is sufficient\nfor memory applications)[7], directly supporting the potential for low-voltage operation.\nMost importantly, the key advantage of our coupled ferroelectric polarization–\ncharge tunneling mechanism is that it enables four stable, nonvolatile, and\nreconfigurable configurations through different pulse schemes. We further confirm the\ndevice-to-device reproducibility of these multistate configurations. This robust and\nprogrammable multi-configuration capability is essential for our demonstration\nof integrated optoelectronic sensing, memory, and computing within a single\ndevice platform. We hope that these clarifications and additional results address the\nreviewer’s concerns.\nReference:\n[1] Wang, Y. et al. 11-bit two-dimensional floating-gate memories. Nat. Commun. 16,\n9268 (2025).\n[2] Cai, Y. et al. 8-bit states in 2D floating-gate memories using gate-injection mode for\nlarge-scale convolutional neural networks. Nat. Commun. 16, 2649 (2025).\n[3] Xiang, Y. et al. Subnanosecond flash memory enabled by 2D-enhanced hot-carrier\ninjection. Nature 641, 90–97 (2025).\n[4] Hattori, Y., Taniguchi, T., Watanabe, K. & Nagashio, K. Layer-by-layer dielectric\nbreakdown of hexagonal boron nitride. ACS Nano 9, 916–921 (2015).\n[5] Rumberg, B., Graham, D. W. & Navidi, M. M. A regulated charge pump for\ntunneling floating-gate transistors. IEEE Trans. Circuits Syst. I: Regul. Pap. 64, 516–\n527 (2017).\n[6] Richard, J.-F. & Savaria, Y. High voltage charge pump using standard CMOS\ntechnology. In Proc. 2nd Annu. IEEE Northeast Workshop Circuits Syst. (NEWCAS\n2004) (Montreal, QC, Canada), 317–320 (2004).\n[7] Hong, A. J. et al. Graphene flash memory. ACS Nano 5, 7812–7817 (2011).\nComment 2:\nThe logic-in-memory demonstrations rely on a non-standard and problematic definition\nof logic inputs. Rather than employing concurrent, independently addressable electrical\ninputs, the manuscript encodes logic states through sequential gate-pulse programming\nand, in some cases, optical excitation. This temporal and modality-mixed encoding\neffectively transforms the logic operation into a state-programming-and-readout\nsequence rather than a true logic computation. Such an approach is fundamentally\nincompatible with conventional logic-in-memory concepts, as it precludes signal\ncascadability, fan-in/fan-out, and synchronous operation, thereby severely undermining\nthe claim of practical logic-in-memory functionality.\nReply:\nWe sincerely thank the reviewer for the constructive comments. We fully\nacknowledge the reviewer’s emphasis on the importance of concurrent, independently\naddressable electrical inputs in conventional logic-in-memory architectures. However,\nwe would like to clarify that in reconfigurable logic-in-memory, the logic variables are\nstored in nonvolatile states. Consequently, logic functions can be implemented through\ntime-sequenced electrical pulse operations, which may reduce the need for multiple\ngeometric input terminals while still enabling well-defined input encoding and logic\nevaluation.[1]\nTo further address the reviewer’s concern regarding “independently addressable\ninputs,” we clarify that our architecture supports reconfigurable operation using two\nindependent electrical inputs. Specifically, the floating-gate electrode and the Si back\ngate act as two separately addressable terminals: V modulates the channel region\nFG\nassociated with the FGFET component, while V controls the channel region\nCG\nassociated with the FeFET component. By applying pulse voltages to V and holding\nCG\nvoltages to V\nFG\n, we can tune distinct reconfigurable modes, as shown in Fig. R3. Similar\nschemes combining pulsed operations with held biases have also been reported in in-\nmemory computing and reconfigurable logic devices, supporting the feasibility of\nindependently addressable inputs within such stateful operation paradigms.[2]\nImportantly, the time-sequenced pulse approach adopted in our manuscript is also\nmotivated by energy considerations, as it avoids continuously applying a constant bias\nand thereby reduces static power consumption.\nRegarding the use of optical excitation, we clarify that light is introduced as an\noptoelectronic input modality to demonstrate integrated sensing–memory–\ncomputing functionality, rather than to replace electrical addressing. Notably, using\nlight (including intensity/position and temporal modulation) as logic inputs has been\nwidely explored as a viable route toward compact, energy-efficient, light-driven logic\nsystems.[3, 4]\nFigure R3. Schematic illustration of four reconfigurable configurations enabled by\nindependent V and V inputs.\nCG FG\nReference:\n[1] Li, W. et al. Reconfigurable floating-gate devices with ambipolar ReSe\n2\nchannel:\ndual-mode storage, NMOS–PMOS transformation, logic functions, synapse\nsimulations, positive and negative photoconductive effects. Adv. Funct. Mater. 35,\n2425359 (2025)\n[2] Sheng, Z. et al. Reconfigurable logic-in-memory computing based on a polarity-\ncontrollable two-dimensional transistor. Nano Lett. 23, 5242–5249 (2023).\n[3] He, T. et al. On-chip optoelectronic logic gates operating in the telecom band. Nat.\nPhoton. 18, 60–67 (2024).\n[4] Ahn, D. et al. Light-driven reconfigurable logic in a monolithic perovskite device\nvia nonlinear photoresponse switching. Adv. Mater. e09566 (2025).\nComment 3:\nIn addition, it should be noted that logic-in-memory architectures are conventionally\ndefined and evaluated based on purely electrical inputs, typically involving two or more\nvoltage-controlled signals that can be cascaded across logic stages. In this context, the\nintroduction of optical excitation as an additional logic input raises fundamental\nconcerns. Using light as a logic input departs from the standard logic-in-memory\nparadigm and significantly limits cascadability, as optical signals cannot be directly\npropagated or interfaced with subsequent electrical logic stages without additional\noptoelectronic conversion circuitry. As a result, it becomes unclear how the proposed\nlogic operations could be cascaded or integrated into larger-scale logic systems, which\nis a key requirement for practical logic-in-memory computing.\nReply:\nWe sincerely thank the reviewer for raising this important point. We agree that\nlogic-in-memory architectures are conventionally defined and evaluated with purely\nelectrical inputs and that cascadability across logic stages is a key system-level\nrequirement for large-scale logic circuits. In our work, optical excitation is introduced\nnot to redefine the standard logic-in-memory paradigm, but as an additional\noptoelectronic input modality to demonstrate integrated sensing–memory–computing\nfunctionality, where external physical stimuli can be directly mapped into\nprogrammable nonvolatile states and subsequent electrical readout.\nImportantly, using light as an input has strong precedent in optoelectronic logic and\nin-sensor computing, where the device receives optical stimuli and produces an\nelectrical output that can be interfaced with electronics.[1, 2] Moreover, introducing\noptical excitation enables a practical sensing–memory–computing co-integration\narchitecture, in which the sensory input can be processed and stored in situ at the\ndevice level.[3] This paradigm reduces unnecessary data transfer between separate\nsensing, memory, and computing units, thereby alleviating the von Neumann bottleneck\nand potentially improving the system energy efficiency for perception-oriented and\nedge computing tasks.[4] In our demonstration, light serves as a representative external\nstimulus to demonstrate how our platform can directly convert physical inputs into\nnonvolatile programmable states and electrical outputs, providing a compact route\ntoward integrated optoelectronic sensing and in-memory computation.\nReference:\n[1] He, T. et al. On-chip optoelectronic logic gates operating in the telecom band. Nat.\nPhoton. 18, 60–67 (2024).\n[2] Ahn, D. et al. Light-driven reconfigurable logic in a monolithic perovskite device\nvia nonlinear photoresponse switching. Adv. Mater. e09566 (2025).\n[3] Wu, G. et al. Ferroelectric-defined reconfigurable homojunctions for in-memory\nsensing and computing. Nat. Mater. 22, 1499–1506 (2023).\n[4] Dang, Z. et al. Object motion detection enabled by reconfigurable neuromorphic\nvision sensor under ferroelectric modulation. ACS Nano 18, 27727–27737 (2024).\nComment 4:\nThe assertion of “atomically sharp” and high-quality interfaces is largely qualitative\nand based on structural arguments. Direct electrical characterization of interface trap\ndensity would be necessary to support this claim.\nReply:\nTo quantitatively evaluate the interface trap density in our device, we employed the\nhigh–low frequency capacitance–voltage (C–V) method based on the measured C–V\ncharacteristics at low and high frequency limits.[1] The experimentally measured\ncapacitance per unit area can be expressed as:\n1\n𝐶\n−1\n1 1\n𝐶1 = ( + ) (1)\nWhere is the semicond\n𝐶\nuMcotoTre 2ca\n+\npa\n𝐶\nc𝑖i𝑡tanc\n𝐶\ne𝑔of MoTe\n2\n, is the capacitance\nof traps and is the geometric capacitance related to hBN layer and the vdW gap, all\n𝐶MoTe2 𝐶𝑖𝑡\nthe capacitance are normalized by area.\n𝐶𝑔\nBecause the interface traps can follow the AC signal at low frequency but cannot\nrespond at the high frequency limit, the interface trap density can be estimated\nfrom the difference between the low-frequency capacitance and high-frequency\n𝐷𝑖𝑡\ncapacitance as:\n𝐶𝐿𝐹\n𝐶𝐻𝐹\n−1 −1\n1 1 1 1\n𝑞𝐷𝑖𝑡 = ( − ) −( − ) (2)\nWhere is the elementa 𝐶 r𝐿y𝐹 ch 𝐶 a𝑔rge, and 𝐶 𝐻𝐹 𝐶 a𝑔nd are the measured\ncapacitances per unit area at the low- and high-frequency limits, respectively (\n𝑞 𝐶𝐿𝐹 𝐶𝐻𝐹\nand ).\n𝑓𝐿𝐹 =\nIn our structure, the geometric gate capacitance is primarily determined by the\n10 kHz 𝑓𝐻𝐹 = 1 MHz\nhBN dielectric layer, and can be approximated as: .\n𝐶𝑔\nIf an additional interfacial gap capacitance is considered, the effective\n𝐶𝑔 ≈ 𝐶ℎ𝐵𝑁\ngeometric capacitance can be expressed as:\n𝐶𝑖𝑛𝑡\n−1\n1 1\nHowever, , can b𝐶e 𝑔 w=e(ll\n𝐶\nℎa𝐵p𝑁pr+ox\n𝐶\nim𝑖𝑛a𝑡t)ed by without affecting (t3he)\nextracted .[2]\n𝐶𝑖𝑛𝑡 ≫ 𝐶ℎ𝐵𝑁 𝐶𝑔 𝐶ℎ𝐵𝑁\nThe ex\n𝐷\ntr𝑖𝑡acted exhibits a peak value of approximately 1.6×1012 cm-2eV-1 in the\ntransition region, w 𝐷 h 𝑖 i 𝑡 le in the accumulation region is reduced to around ~1×1011\ncm-2eV-1, as shown in Fig. R4. These results indicate𝐷 th𝑖𝑡at our heterostructure exhibits a\nrelatively low interface trap density compared with previously reported\nheterostructured devices.[3, 4] Moreover, prior work has suggested that when the\ninterface trap density is below ~1012 cm-2eV-1 its impact on the nonvolatile memory\nbehavior becomes negligible.[5]\nFigure R4. (a) C–V curves of the device measured at frequencies from 10 kHz to 1 MHz\nas a function of V . (b) Interface trap density extracted using the high–low\nFG\nfrequency method.\n𝐷𝑖𝑡\nTogether, these results provide quantitative electrical evidence supporting the\ninterface quality of our device, especially in the accumulation regime where device\noperation and readout are performed.\nReference:\n[1] Yu, J. et al. Simultaneously ultrafast and robust two-dimensional flash memory devices based\non phase-engineered edge contacts. Nat. Commun. 14, 5662 (2023).\n[2] Zhao, P. et al. Evaluation of border traps and interface traps in HfO /MoS gate stacks by\n2 2\ncapacitance–voltage analysis. 2D Mater. 5, 031002 (2018).\n[3] Zhao, P. et al. Probing Interface Defects in Top-Gated MoS Transistors with Impedance\n[4] Sebastian, A. et al. Benchmarking monolayer MoS and WS field-effect transistors. Nat.\n2 2\nCommun. 12, 693 (2021).\n[5] Giusi, G. M. et al. Impact of Interface Traps in Floating-Gate Memory Based on Monolayer\nMoS . IEEE Trans. Electron Devices 69, 6121–6126 (2022).\nThe authors answered all questions raised. And the point-by-point responses seem\nappropriately addresses the potential issues. Therefore, I recommend this manuscript to\nbe published in Nature Communications.\nReply:\nWe sincerely thank the reviewer for the positive comments on our manuscript."}, {"round": 3, "reviewer_comments": {"reviewer_2": "I appreciate the authors’ clarifications. While I remain unconvinced that the demonstrated architecture fulfills the conventional criteria of cascaded logic-in-memory systems, I recognize that the work presents a meaningful contribution in the context of reconfigurable logic and in-sensor computing. I therefore recommend publication."}, "author_response": ""}]

Decision letter