A megawatt ultra-wide bandgap semiconductor module for pulsed power electronics

Domain: biology
Published: 2026-03-30
Editorial outcome: major_revision

Abstract
Ultra-wide bandgap semiconductors exhibit advantageous electronic properties that make them promising for high-voltage, high-power electronics applications. Building on over a decade of progress in material growth and device fabrication, discrete ultra-wide bandgap devices with power-switching capacities up to the kilowatt level have been recently demonstrated. However, a packaged, multi-die ultra-wide bandgap power module – essential for further power scaling toward industrial, biomedical, grid, and aerospace applications – has yet to be realized. Here, we present a flip-chip packaged gallium oxide power module capable of 1000 A, 1000 V pulsed power switching with fast speed and minimal reverse recovery, advancing the power capacity of ultra-wide bandgap electronics by over two orders of magnitude. To address challenges posed by high electric fields and transient power surges, we employ a high-permittivity interface design enabling device-package electrothermal co-optimization. This optimization maximizes the module’s transient thermal performance and enables full exploitation of the high volumetric heat capacity of gallium oxide—a largely untapped advantage in prior device development—alongside its high-temperature stability. The optimized ultra-wide bandgap module achieves over 1.8 MW/cm2 pulsed power capacity density, outperforming silicon and wide-bandgap semiconductor counterparts and suggesting the promise of ultra-wide bandgap electronics in next-generation high-power systems.

Introduction
Power semiconductor devices, which conduct high current in the on-state, block high voltage in the off-state, and fast switch between these two states, are central components in power electronics systems in numerous applications such as consumer electronics, data centers, electric vehicles, renewable energy processing, and electric grids. The global market of power semiconductor devices and modules has exceeded US$50 billion1. In the last two decades, wide bandgap (WBG) semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC) have enabled system performance beyond the limits of conventional silicon (Si)-based devices. Recently, ultra-wide bandgap (UWBG) semiconductors, including gallium oxide (Ga2O3), aluminum nitride (AlN) and diamond, have emerged as competitive candidates for next-generation power devices. These materials promise higher critical electric field and thermal stability compared to the WBG and Si counterparts2,3. Their Baliga’s figure of merit (FOM)4, the FOM widely used to evaluate semiconductor materials for power applications, are at least 3.8 times higher than GaN or SiC and 3000 times than Si5.

Over the past decade, the development of UWBG power devices has advanced rapidly in power scaling, driven by the availability of large-diameter wafers and progress in device fabrication techniques6-10. For example, 8-inch Ga2O3 wafer and 32×31.5 mm2 diamond wafer have been recently demonstrated11,12. Fabricated UWBG devices have exhibited promising switching performance in circuit-level evaluations, with switching power capacity (PC, defined as the product of switching voltage and current) reaching the kilowatt range. For instance, Ga2O3 diodes have been tested in a buck converter delivering output power up to 2 kW, and in double pulse tests with switching voltage and current of 400 V and 15 A, respectively13. Additionally, diamond diodes have demonstrated short reverse recovery times during transitions from 2 A forward current to 100 V blocking voltage14.

However, the current power levels achieved by UWBG devices remain insufficient for the demands of industrial, biomedical, grid, and aerospace applications. For example, next-generation electric vehicle platforms support charging voltages up to 1,000 V and currents up to 1,000 A, requesting a megawatt (MW) PC for power devices15. In certain industrial and aerospace applications, such as electromagnetic forming16 and electromagnetic propulsion17, transient power levels can exceed 100 MW, with peak currents surpassing 100 kA. Traditionally, high power in Si devices is achieved by processing an entire wafer into a single, large-area device. However, this approach is not viable for WBG and UWBG materials due to intrinsic material non-uniformities, fabrication variability, and high defect densities18. These limitations often introduce a trade-off between breakdown voltage (VB) and forward current (IF). For example, in large-area Ga2O3 devices, VB typically decreases as IF increases6 (Supplementary Section S1), constraining power scaling.

As an alternative, power modules that integrate multiple devices with advanced packaging and thermal management are commonly adopted in the WBG industry19,20. However, no such power modules have yet been demonstrated for UWBG devices, primarily due to several key challenges: 1) packaging for UWBG devices must withstand very high electric fields near device edges and encapsulation interfaces; and 2) these devices must support very high power densities while maintaining a compact footprint, resulting in high heat fluxes that are difficult to manage21. These challenges are compounded by the inherently low thermal conductivity (kT) of many UWBG materials; for instance, Ga2O3 has a low kT of 11–27 W/m·K22. As a result, the power level of UWBG devices has stagnated at the kilowatt scale for nearly a decade. Additionally, the absence of a demonstrated high-power module suitable for industrial deployment continues to limit the practical application space of UWBG devices. Notably, although UWBG materials can support high-temperature operation due to their low intrinsic carrier concentrations9, this advantage remains largely unexploited because conventional packaging designs are often inadequate for such thermal environments.

This work addresses the critical limitation in power scaling of UWBG devices by introducing a Ga2O3 power module through device-package, electrothermal co-design. Building on our earlier conference report23, a high-permittivity (κ) BaTiO3 layer was employed as an interface between the device’s edge termination and the die attach of the package, inducing polarization-induced dipoles that effectively flatten the localized electric field crowding. This design further eliminates the need for the posts that are typically used in conventional flip-chip packages, improving thermal resistance by over 50%. The packaged Ga2O3 diode exhibits a high VB over 2 kV, high current capability over 100 A, low thermal resistance of 0.47 K/W, and stable operation up to 250 oC – collectively representing state-of-the-art performance among UWBG power devices reported to date.

Furthermore, the co-design enables exploration of emerging application avenues for UWBG devices – pulsed power electronics. These applications – spanning defense, biomedicine, industrial processing, scientific instrumentation, energy systems, and aerospace – rely on the generation and control of short, repetitive, high-power electrical pulses. We found that Ga2O3 power modules outperform their Si and WBG counterparts in pulse power scenarios, owing to three key factors: (a) Ga2O3’s high volumetric heat capacity (Cv), a critical property largely overlooked in prior studies; (b) the intrinsic capability of Ga2O3 device to operate at elevated temperatures; and (c) the co-designed package structure, which is optimized for transient thermal management. We demonstrated continuous pulsed switching at 1,000 V and 1,000 A – a PC level that exceeds previously reported UWBG devices by more than two orders of magnitude.

Results
Pulsed power applications and material selection
The global market size of pulsed power applications is projected to reach US$100 billion by 203224. A typical pulsed power system consists of two core stages – low power accumulation and high power output – through a pulse forming network, which delivers megawatt- to gigawatt- pulses over very short period25 (Fig. 1a). Such high-power pulse supplies are essential in diverse applications, including grid, magnetic resonance imaging (MRI), pulsed lasers, and nuclear fusion systems. For example, in grid-connected circuit breakers, devices are required to withstand a concurrence of high voltage and surge current on the microsecond timescale before the mechanism branch intervenes26,27. Compared to conventional power switching systems, pulsed power systems impose significantly higher transient power demands, making transient thermal performance far more critical than steady-state behavior28.

The performance of pulsed power systems is critically determined by the switching device connecting energy storage and pulse delivery stages, which must handle large transient currents, high voltages, fast switching speeds, and elevated transient temperatures29. Currently, pulsed power devices fall into two main categories: gas discharge devices and solid-state devices (Fig. 1b)30. Despite high power handling capabilities, gas discharge devices suffer from low repetition rates, limited lifetimes, and large physical footprints. In solid-state devices, Si bipolar devices can handle high power but exhibit slow switching speeds, high conduction loss, and limited high-temperature stability. Emerging SiC unipolar devices offer faster switching speeds, but their power handling remains constrained. Next-generation pulsed power devices, including both controlled switches (i.e., power transistors) and power diodes, are therefore in high demand. In pulsed-power systems, transistors are often used for initiating and shaping the pulse, whereas power diodes play indispensable roles in energy steering, stage isolation, rapid charge management, and transient overvoltage suppression. For instance, in inductive-load pulsed circuits, the diode must withstand and conduct large surge currents while clamping voltage spikes induced by rapid current transients (L∙di/dt), all within several micro-seconds. In high-voltage pulse generation circuits, such as Marx and Cockcroft-Walton generators, the diode is further required to reliably block kilovolt reverse voltages.

Semiconductor material selection for pulsed power devices must account for both electrical FOMs and thermal properties. For thermal considerations, during short-duration pulsed heating, the heat has insufficient time to spread spatially, and thus the temperature rise is governed primarily by the material’s Cv instead of kT. As thermal diffusion is negligible, an approximate model dictates the local temperature rise ΔT to scale with Q⁄(CvV)31, where Q is the heat generation energy, and V is the material volume. Hence, a higher Cv indicates a smaller temperature increase under the identical power loss32, offering improved thermal buffering against fast surges33. Fig. 1c compares the room-temperature Cv and Baliga’s FOM of representative power semiconductors, including Si34, GaAs35, SiC36, GaN37, Ga2O338,39, AlN40 and diamond41. Ga2O3 exhibit the largest Cv – nearly twice that of SiC – and one of the highest Baliga’s FOMs, making it optimal for pulsed switches.

Another fundamental limitation of transient power operation is the device’s high temperature operation capability, which is usually constrained by its high-temperature, high-bias blocking capability. Elevated temperatures enhance intrinsic carrier generation and activate traps, resulting in increased leakage current, localized self-heating and premature breakdown. As the intrinsic carrier density (ni) increases exponentially with decreasing material bandgap, lower leakage current is expected in UWBG devices, enabling them to sustain higher operational temperatures42. Fig. 1d compares the maximum operational temperature and blocking voltage reported for bare-die WBG43-47 and UWBG power devices48-59. Ga2O3 devices exhibit the favorable combinations of high voltage and high temperature performance, further consolidating their suitability for pulsed power applications.

Device-package electrothermal co-optimization
Fig. 1e shows the design of the packaging architecture for a single-die Ga2O3 device, which is referred to as a sub-module in this work, as well as the photography of a prototyped package. As the p-n junction enables lower leakage current and higher operational temperatures than metal-semiconductor junctions, a p-NiO/n-Ga2O3 p-n heterojunction diode (HJD) is selected for module development. Notably, this p-NiO/n-Ga2O3 p-n junction is also a common building block of various high-temperature, high-voltage Ga2O3 devices benchmarked in Fig. 1d48-55. To extract heat directly from the device junction instead of through the low-kT Ga2O3 chip, the junction-side cooling (JSC) package is employed, and the flip-chip Ga2O3 die is directly attached to the direct bond copper (DBC) plate. A molybdenum-copper (Mo-Cu) alloy post with a height similar to the Ga2O3 chip thickness is placed on the side and connected to the cathode of Ga2O3 HJD via an Ag ribbon. Benefitting from the smaller coefficient of thermal expansion (CTE) of the Mo-Cu alloy and the bend of the ribbon structure60, these designs can absorb the thermo-mechanical stress induced by cyclic temperature variations, and thereby boost the reliability and lifetime of the sub-module. Ag sintering is deployed as the primary die attach, with solder only used for connecting the Ag ribbon.

While the JSC package has been demonstrated as an effective thermal management approach for Ga2O3 devices61,62, a widely-reported adverse bi-product is a degradation in device VB63. This is usually induced by the inevitable overflow of the die attach materials — such as soldering and sintering metals – from device active region to edge area, producing additional and higher electric field peaks in device61. The optical image of overflowed sintered Ag after JSC package is shown in Supplementary Section S2. The conventional solution to this problem is adding a post with sufficient height to physically distance die attach materials from the device surface. However, the added post can introduce substantial thermal resistance, compromising the effectiveness of the JSC package in heat extraction. To address this dilemma, we replace the post with a high-κ interface inserted between the device edge termination and the overflown die attach material, which could concurrently improve the device’s electrical and thermal performance. As illustrated in Fig. 1f, owing to the large permittivity contrast between BTO and Ga2O3, the external electric field induces a polarization gradient inside the BTO layer, creating net negative bound polarization charge at the BTO/Ga2O3 interface and a corresponding positive charge beneath the metal/BTO interface64,65. This polarization dipole can shield the electric field produced by charges in the metal and enable a nearly-zero net charge to flatten the crowded electric field – similar to the legacy superjunction design in multidimensional power devices66. Fig. 1g illustrates the prototype high-κ interface for Ga2O3 HJD, and Fig. 1h shows the cross-sectional scanning electron microscopy (SEM) image. The device’s edge termination consists of multiple lightly-doped p-NiO layers with varied lengths, constructing a graded junction termination extension (JTE) that enables a graded decrease in charge density away from the main junction to spatially spread the electric field67. On top of this NiO JTE and below the overflowed Ag, a 300 nm-thick BaTiO3 layer with κ of over 155 (Supplementary Section S3) is deposited through magnetron sputtering. The detailed processes for device fabrication and packaging are illustrated in Methods section and Supplementary Sections S4 and S5.

To validate the functionality of the high-κ interface design, we fabricated two additional packages as control samples, one with the conventional SiO2 passivation layer (control sub-module A) and the other with an additional 500 µm-thick Mo-Cu post (control sub-module B); the high-κ interface submodule is referred to as sub-module C. Physics-based TCAD simulation is performed to obtain the electrical field contours of three packages at a blocking voltage of 2000 V. The physical parameters and models in simulation are detailed in Supplementary Section S6. Simulation reveals a peak electric field up to 19 MV/cm in SiO2 in the control sub-module A, which exceeds the critical electric field of SiO2 (Fig. 2a(i)). Such an electric field peak can be effectively suppressed by either a post in the control sub-module B (Fig. 2a(ii)) or the proposed high-κ interface (Fig. 2a(iii)). Fig. 2b shows the experimental reverse current-voltage (I-V) characteristics of the three packaged Ga2O3 HJDs, revealing a VB of 930 V, 1560 V and 2010 V in the sub-modules A-C. The VB enhancement verifies the effectiveness of high-κ interface for electric field management.

Fig. 2c and Fig. 2d show the temperature-dependent forward and reverse I-V characteristics of the sub-module C, respectively. The Ga2O3 sub-module exhibits an enhanced current capability due to high-level conductivity modulation as temperature (T) increases from room temperature (RT) to 200 oC68, while the differential on-resistance (RON) gradually increases from 200 oC to 300 oC, attributed to the dominance of mobility degradation over conductivity modulation. The VB increases from 2010 V to 2240 V with T from RT to 250 °C,48 exhibiting a positive temperature coefficient of ~1 V/°C, which suggests the avalanche capability. This operation temperature is among the highest reported for kilovolt, large-area UWBG devices. When the temperature is further increased to 300 oC, VB decreases to 1330 V, which is likely due to the trap-assisted preliminary breakdown possibly originating from the interface states between Ag, BTO and Ga2O3. Such a trap-assisted breakdown has been widely reported in other ultra-wide bandgap power devices and features a negative temperature coefficient69,70. As a comparison, the temperature-dependent reverse I-V characteristics of a commercial SiC power diode shows higher leakage current and significantly degraded VB when T is above 150 oC – for example, VB drops to 61% of the RT value at 200 oC (Supplementary Section S7).

Transient thermal impedance and maximum power capacity
Thermal impedance (Z) was measured to compare the junction-to-case thermal resistance (RθJC) of the conventional Ga2O3 sub-module B with post and the proposed sub-module C with high-κ interface. The measurement is based on the transient dual interface method (TDIM) – an industry standard (JEDEC 51-14) for characterizing the RθJC of packaged power devices71. This method relies on capturing transient thermal responses of the packaged devices using two thermal interface materials (TIMs). From the resulting time evolution of transient thermal impedance (Z~t curve), both transient thermal impedance and the steady-state thermal resistance can be extracted, with the latter determined from the separation point of the two Z~t curves. The experimental measurement setups are described in Methods section and Supplementary Section S8. Fig. 3a presents the measured Z~t curves of the two Ga2O3 sub-modules, each with two TIMs, revealing a steady state RθJC of 1.05 K/W and 0.47 K/W for sub-modules with the post and the high-κ interface, respectively. The comparison reveals that, in the JSC package, the elimination of post enabled by high-κ interface allows for a RθJC reduction by over 50%.

Physics-based thermal simulations in ANSYS are performed to uncover the internal temperature contours within the packaged sub-module and their time-resolved evolutions. The simulations are calibrated against the experimental case temperature (TC) of the Ga2O3 sub-module measured across three orders of magnitudes in time scales under continuous 10 A, 1000 V circuit operations. The simulated temperature evolution closely matches experimental data under two cooling schemes (natural convection and fan cooling). The simulation models and calibrations are detailed in Methods section and Supplementary Section S9. Fig. 3b shows the simulated steady-state temperature contours inside two Ga2O3 sub-modules under identical 20 W power dissipation and cooling conditions. Compared to the high-κ interface module with a nearly uniform junction temperature (Tj) of 57 oC, the sub-module with post shows a higher Tj of 74 oC and an additional peak temperature of 89 oC near the anode edge. These hot spots arise because the post contact area is smaller than the actual anode area, resulting in ineffective heat extraction at the anode edge regions.

To probe the sub-module’s transient thermal performance, we simulate temperature contours in the two sub-modules under three pulse durations (10 µs, 1 ms, and 100 ms) while maintaining a constant dissipated energy of 0.5 J. As shown in Fig. 3c, the high-κ interface module effectively suppresses hot spots at the die edge and lowers peak temperatures under all pulse conditions. Additionally, both sub-modules show higher Tj for shorter pulses, indicating greater thermal stress and suggesting the critical importance of the device’s maximum operational temperature in pulsed power applications.

The above thermal and electrical data allows for deriving the sub-module’s maximum PC density at different time scales. Based on experimental Z~t characteristics and the 250 oC maximum operational temperature of Ga2O3 sub-module determined by voltage blocking capability (see Fig. 2d), the maximum power loss at different transient time scales can be calculated. This loss, in conjunction with experimental temperature-dependent I-V (I-V-T) characteristics, allows for further derivation of maximum forward current and PC at various time scales. This analysis is illustrated in Fig. 3d and detailed in Supplementary Section S10. Based on the same approach, the maximum PC under different time scales is also derived for an industrial SiC diode (IDH02G120C5) and a Si diode (RF305BM6S) with the same differential on-resistance (which indicates similar current conduction capability) compared to the Ga2O3 HJD, using their datasheet I-V-T and Z~t characteristics and assuming a maximum operational Tj of 175 oC for SiC device and 150 oC for Si device. Fig. 3e and Fig. 3f shows the derived time-resolved junction-to-case thermal impedance and maximum PC density, respectively, for three packaged devices. The maximum PC density of Ga2O3 diode sub-module outperforms the Si and SiC counterparts with increased advantages at shorter pulses, which is attributable to the higher Cv of Ga2O3, higher blocking temperatures of Ga2O3, and the electrothermal co-optimized package structure.

Circuit demonstration of megawatt pulsed-power switching
The projected superiority of Ga2O3 sub-module is explored experimentally in practical pulsed-power switching circuits. We designed an on-board double-pulse test (DPT) circuit for high-power inductive switching with adjustable pulse width, which represents the typical power rectifier operation in various pulsed-power applications. The DPT circuit consists of power SiC MOSFETs (C3M0016120D), an inductor, and the diode under test (DUT). The inductor is first pre-charged to a target current value, acting as a current source. The SiC MOSFETs are used to control short-pulse, high-voltage, and high-current waveforms with an adjustable pulse width, these pulses are then delivered to the Ga2O3 DUT for evaluating its turn-on and turn-off characteristics. The schematic and photo of the test setup are shown in Fig. 4a and 4b, respectively, and circuit working principle is detailed in Supplementary Section S11. Under a bus bias of 1,000 V, the Ga2O3 sub-module is capable of conducting a forward current of 234 A with a pulse width of 5 μs, as shown in Fig. 4c. Time-resolved junction temperature simulations reveal that Tj peaks at 251 oC for 234 A and 297 oC for 257 A during pulsed switching (Fig. 4d). At forward current over 234 A, the high Tj starts to degrade device blocking voltage (see Fig. 2d). When the blocking voltage degrades below the bus voltage, breakdown occurs.

To further upscale the PC to reach that of industrial applications, we assemble a multi-die full module based on a symmetric arrangement of six Ga2O3 sub-modules (Fig. 4e). The module demonstrates reliable dynamic switching at 1,000 V/1,000 A under a switching frequency of 1 kHz (Fig. 4f and 4g), along with fast switching speed and minimal reverse recovery, with the turn-off time being extracted to be 23 ns. The thermal imaging results of the full module under continuous pulsed-power switching are shown in Supplementary Section S12, revealing uniform current sharing among six sub-modules. The case temperature reached 92 oC on the top and 81 oC on the bottom of each sub-module at the steady state, confirming the effective thermal management. Fig. 4h benchmarks the switching voltage and PC for the Ga2O3 sub-module and multi-die full module prototyped in this work, as well as the previously reported UWBG devices in practical circuit switching13,14,57,72-75. The PC of our Ga2O3 modules is over two orders of magnitude higher than the previous best report, validating the effectiveness of device-package co-optimization for UWBG modules.

Short-pulse surge current capability and Power cycling test
From the analysis in Fig. 4d, the device failure in the kilovolt switching is limited by the maximum junction temperature for voltage blocking instead of the device’s intrinsic thermal failure in forward current conduction. Meanwhile, in some pulse power applications (e.g., light laser detection and ranging (LiDAR) systems), devices are only required to pass high current but do not need to block a very high voltage. For these applications scenarios, surge current capability is a key metric of power rectifiers. Here we study the surge current capability of the Ga2O3 sub-module across a wide range of time spans to understand its intrinsic electrothermal limit in conduction-dominant pulsed power applications.

The schematic and photo of the surge-current evaluation circuit are shown in Fig. 5a and 5b, and the circuit working principle is detailed in Supplementary Section S13. Different from conventional surge current test circuit with a fixed pulse width (e.g., 10 ms), this test setup is tailored for pulse power applications by enabling adjustable pulse widths across four orders of magnitude down to 3.6 μs. The half-sinusoidal surge current signal is generated by adjusting the resonance circuit, and the pulse width is controlled by modulating the values of inductor and capacitor. The circuit layout is optimized to limit the diode’s maximum ringing bias in the blocking state below 100 V.

Fig. 5c shows the current and voltage waveforms in the surge current tests under a 3.6 μs pulse width and increased peak current amplitude. The Ga2O3 sub-module can withstand a maximum peak surge current of 856 A. Post-test static characterization confirms the device integrity until the last 856 A surge current test, after which the device exhibits a measurable deterioration in its reverse-blocking capability. Fig. 5d compares the surge current capabilities of the Ga2O3 sub-module under varying pulse widths. The critical peak surge current decreases from 856 A to 65 A when the pulse width increases from 3.6 μs to 10 ms. The peak critical surge currents at various pulse widths are plotted in Fig. 5e from surge current tests performed under both the room temperature and an ambient temperature of 150 oC. Under two temperatures, the Ga2O3 sub-module delivers increasing current capacity for shorter pulse applications, and its current capacity consistently outperforms a state-of-the-art industrial 1200 V-rated SiC diode with a similar differential on-resistance (IDH02G120C5), particularly under shorter pulses and elevated temperatures.

Further physical insight is obtained via transient thermal simulations. Fig. 5f and 5g present the surge power extracted from experimental waveforms, and the simulated evolutions of transient Tj under critical surge current tests with varying pulse widths, respectively. Under the critical failure condition, the peak Tj is projected to decrease from 648 oC to 478 oC with pulse width increased from 3.6 μs to 10 ms, indicating that the Ga2O3 sub-module can sustain higher Tj at short pulses. To further understand the superior performance of the Ga2O3 sub-module compared to its SiC counterpart, we also conduct transient thermal simulations on a hypothetical SiC sub-module that shares identical device and package architectures, with only the material properties substituted from Ga2O3 to SiC. The critical Tj of Ga2O3 and SiC sub-modules under various pulse widths are summarized in Fig. 5h, and the evolution of internal temperature contours of two sub-modules in a critical surge current test is presented in Supplementary Section S14. At long pulse width, the hypothetical SiC sub-module shows lower critical Tj than the Ga2O3 counterpart, primarily due to SiC’s higher kT. However, at short pulse width, the critical Tj of the Ga2O3 sub-module falls below that of the SiC sub-module, highlighting the dominant influence of Ga2O3’s higher Cv over its comparatively lower kT. This comparison further manifests the greater importance of a material’s Cv – as well as the thermal capacitance of the package – in determining transient thermal behavior during pulsed power operations.

A similar consideration is also relevant for repetitive switching under varying duty cycles, or equivalently, different repetition rates. As shown in the analysis in Supplementary Section S15, at relatively high duty cycles or repetition rates, an average junction temperature rise develops in addition to the transient pulsed temperature peaks when the generated heat cannot be fully removed between pulses. This average junction temperature rise can be suppressed through improved external cooling. In this scenario, advanced external cooling is required to fully exploit the module’s intrinsic power capacity.

Finally, we evaluate the reliability of the prototyped sub-modules. The BaTiO3 layer is fully encapsulated by silicone gel, forming a continuous dielectric barrier that suppresses humidity-induced degradation commonly observed in bulk BaTiO3 ceramics76. In addition, the BaTiO3 interface is found to improve thermo-mechanical reliability. Table S3 in Supplementary Section S16 summarizes the CTE of relevant materials. Due to the large CTE mismatch, conventional Ga2O3/SiO2/Sintered Ag stacks experience elevated thermo-mechanical stress near die edges. Replacing SiO2 with BaTiO3 significantly improves CTE matching. To validate this, we perform a switching-based power-cycling test, the widely-used method for qualifying power module reliability77. As detailed in Supplementary Section S16, the sub-module C exhibits minimal parametric shift after 10,000 power-cycling cycles, whereas sub-module A exhibits pronounced forward voltage degradation after ~1,200 cycles.

Methods
Epitaxial structure and device fabrication
The Ga2O3 wafer consists of a 10-μm Si-doped drift layer with an electron concentration of 1.5×1016 cm−3 grown by hydride vapor phase epitaxy (HVPE) on a conductive Sn-doped (001) β-Ga2O3 substrate. The schematic of device fabrication steps is shown in Supplementary Section S4. The device fabrication started with the substrate cleaning via ultrasonic treatment in acetone and alcohol soaking. Then, the Ga2O3 epi-wafers were annealed at 500 oC under the O2 ambient. A Ti/Au (20/80 nm) Ohmic contact was formed as the cathode, followed by rapid thermal annealing. Subsequently, by using a bi-layer photoresist, multi-layer NiO JTE was deposited on the Ga2O3 drift layer by RF magnetron sputtering technique at room temperature. The NiO layers have varied lengths to enable a graded decrease in effective charge density away from the main junction. The target used in magnetron sputtering was high-purity (99.99%) NiO ceramics. The thickness of each graded p-NiO JTE layer and top p+-NiO layer is 100 nm. The acceptor concentration of p-NiO and p+-NiO is 1.7×1017 cm-3 and 2×1019 cm-3, respectively, as modulated by the O2/Ar gas ratio in the sputtering process. To achieve good anode Ohmic contact on p-NiO, in situ sputtering of a metal Ni layer (100 nm) is performed in Ar ambient at room temperature utilizing high-purity Ni metal target. The device active area is 3×3 mm2.

Device packaging
Schematic of the packaging steps and optical images of three sub-modules are shown in Supplementary Section S5. For sub-modules A and C, 300 nm SiO2 and 300 nm BaTiO3 were deposited on the Ga2O3 die surface by plasma-enhanced chemical vapor deposition and magnetron sputtering, respectively. The contact window was opened by dry etch for SiO2 and by a lift-off process for BaTiO3. Then top anode and bottom cathode were further finished with an Au/Ti (200 nm) bilayer. The Ti barrier layer can avoid the diffusion of Ag atoms into electrode during the high-temperature silver sintering process. Then the device die attach on the direct bond copper (DBC) substrate and post attach on the die were formed by silver sintering. A laser-cut mask was used to stencil-print a 50-μm thick silver-sintering paste (provided by NBE Technologies) on die anode. The sintering temperature profile was from room temperature to 230 °C at a ramp rate of 6 °C/min and held at 230 °C for 1 hour, followed by air cool to room temperature.

For sub-module B with a post interface, a Mo-Cu post was sintered on the anode; then anode post was sintered on DBC. The subsequent steps, e.g., cathode and stacker-side sintering, soldering and ribbon formation, are the same for all sub-modules. In the soldering process, a solder paste (Sn-42Pb-8Bi) was used for the silver ribbon attach. Before packaging, AlN DBC substrate (provided from Rogers Corporation) was patterned. Firstly, the DBC substrate was covered by Kapton tape as a hard mask, then laser cutting was used to remove the tape outside the pattern, followed by spray etching with FeCl3 solution. The sub-module was encapsulated before thermal resistance measurement and circuit test. In the encapsulation process, a 3-D printed housing was glued to the DBC using the slow-cure epoxy resin (from Bob Smith Industries), then silicone gel (Wacker 612 A/B) was mixed and vacuumed to remove all air bubbles, which was poured into the housing to encapsulate all the components. Finally, the housing was placed on a hotplate and cured at a temperature of 150 °C for 30 minutes.

SEM characterization
The SEM image shown in Fig. 1h was captured by a ThermoScientific Helios 5 UC dual-beam workstation that combines a high-resolution scanning electron microscope (SEM) and a focused ion beam (FIB). The measured SEM images were processed with Photoshop software to add false color to highlight different layers of device structure.

Device static temperature-dependent electrical characterizations
The temperature-dependent forward and reverse I-V measurements were performed by a Keysight B1505A Power Device Analyzer. The probe station model is FormFactor Summit 11000, equipped with a thermal chuck and temperature controller, which supports high-voltage and high-current testing at temperatures from -40 oC to 300 oC. I-V sweeps were conducted using the N1265A high current and high-voltage SMU, four-wire Kelvin connection is utilized in the I-V sweep to eliminate the impact from probe-associated parasitic resistance.

TCAD device simulations
The Technology Computer-Aided Design (TCAD) device simulations were performed using Silvaco to obtain the electric field distribution. The major material parameters and physical models used in the simulation are described in Supplementary Section S6. Appropriate physical models, such as Chynoweth impact ionization model, field-dependent mobility, Shockley-Read-Hall recombination, Auger recombination, and bandgap narrowing effects, were deployed. Poisson’s equation and carrier transport equations were solved self-consistently under steady-state and transient bias conditions. Mesh refinement was applied in high-field regions and various interfaces to ensure numerical convergence.

Thermal impedance characterizations
The junction-to-case thermal impedance (Z) was measured using the transient dual interface method (TDIM), following the JEDEC 51-14 standard. In this technique, the device under test was subjected to a controlled power step, and the resulting transient temperature response was monitored. Measurements were performed using an Analysis Tech Phase 12 Semiconductor Thermal Analyzer, which provides high temporal resolution for capturing the heating and cooling transients. The thermal impedance curve was derived by deconvolution of the temperature response and applied heating power, yielding the cumulative structure function. Z was determined as the thermal resistance increment between the two test configurations: one with a high-conductivity thermal interface material (TIM) applied between the device case and the cold plate, and the other with a low-conductivity TIM. The key equation governing the transient response is: Z = (Tj(t)-Tref(t))/P, where Tj(t) is the measured instant junction temperature, Tref(t) is the reference temperature at the cold plate, and P is the applied heating power. The intersection point of the differential structure functions from both configurations defines the effective junction-to-case thermal resistance.

Circuit-level characterizations
The short-pulse power switching demonstration, surge current tests with variable pulse widths, and the dynamic switching test for simulation calibration were carried out by a customized circuit platform. Schematics of test circuits, working principle, waveforms, and thermal images of the dynamic test circuit are presented in Supplementary Section S9. Schematics of test circuit, working principle, and waveforms for short-pulse power switching are presented in Supplementary Section S11. Schematics of test circuit, working principle, and waveforms for surge current tests are presented in Supplementary Section S13.

ANSYS simulation and thermal calibration with experiments
ANSYS Workbench (2021 R1) software was used for package and module simulations in this work. The detailed material parameters, physical model, and calibration with experiments for the steady-state and transient thermal simulation in Figs. 3-5 are described in Supplementary Section S9. The 3D physical structure of the Ga2O3 packaged device was first constructed in SolidWorks and then imported into ANSYS Workbench, where SpaceClaim was used to simplify the module geometry and define Icepak-recognizable objects such as solids, heat sources, and boundaries. After preprocessing, the model was transferred into Icepak. Thermal properties, material properties, power dissipation, and convection boundary conditions were specified. To ensure accuracy, the computational mesh was refined in regions with steep thermal gradients, such as junctions and interfaces. Steady-state or transient thermal simulations were carried out, and the resulting temperature distribution inside the module structures provided insight into the module’s thermal behavior and heat dissipation capability.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The paper addresses the interesting topic of future pulsed power electronics. It mainly concerns the use of Ga2O3, an\nUWBG material addressed in numerous recent publications.\nThe presented diode Ga203 module has very good performance.\nThe originality of this paper comes from the pulsed power application and thus the major drawback of Ga2O3, its low thermal\nconduction, is less significant\nHowever, some points must be better explained for the interest of most readers.\nPage 4, concerning Fig. 1b “Pulsed power applications, material selection, as well as device and package designs.”, it is\nwritten, “Currently, pulsed power switches fall into two main categories: gas discharge switches and solid-state switches”.\nHowever, Fig 1b shows controlled devices like thyratrons or SiC MOSFETs while the paper shows the performance of a\nPower Diode Module.\nSo at least some explanations about the role of diodes and controlled devices is expected.\nParticularly, what is the application of a good power diode module based on Ga2O3, as presented in the paper if no\nequivalent controlled switched exists?\nFurthermore, Fig. 4a shows the schematic of the circuit used to test the surge power capability of the proposed Ga2O3 diode\nmodule. This circuit uses some SiC MOSFETs. So a reader could understand that SiC MOSFETs are convenient for pulsed\npower applications, even to avoid the use of power diode modules as in a synchronous converter.\nSo why a power diode module is very important for pulsed power applications ?\nPage 5, it is written :\n“As thermal diffusion is negligible, an approximate model dictates the local temperature\nrise ∆(cid:1) to scale with (cid:2) ⁄ ((cid:3)(cid:4) (cid:4)), where Q is the heat generation energy, and V is the material volume. Hence, materials with\nhigher Cv can absorb more energy with smaller temperature increases, offering superior thermal buffering against fast\nsurges”\nThis is true, and fig 2.c shows a better, about a ratio of 2, Cv for Ga2O3 than for SiC, but the build-in potential is higher in\nGa2O3 (~ 4.5 V) than in SiC (~2.8 V). So heat generation could be higher for Ga2O3. Furthermore, in pulse power\napplications, heat generation is related to the high-pulsed current.\nThis issue is no more included in the Baliga’s FOM. So the conclusion of such data is not so easy and demands further\ndiscussion.\nFig. 2a, Breakdown voltage enhancement and sub-modules’ electrical characteristics.\nThe figure seems to be related to a heterojunction but it is not mentioned in the caption. It will be clearer for most readers to\nexplicitly mention it in the caption.\nConcerning the presented result, it is written, “all simulated under a reverse bias of 2000 V”, while in Fig 2b), “Reverse I-V\ncharacteristics of three types of Ga2O3 sub-modules with different package structures” show VBR about of 930 V, 1560 V for\nstructures A and B, so this is inconsistent. That needs some explanations or corrections.\nMoreover Fig. 2a shows a higher electric field (with orange region) in case of sub-modules A and C but not in case of sub-\nmodule B. This is also inconsistent with the I-V characteristic in Fig 2b.\nSo please correct this or give an adequate explanation.\nFurthermore, on page 6 it is written, “the VB increases from 2010 V to 2240V with T from RT to 250 °C, exhibiting a positive\ntemperature coefficient of ~1 V/°C, which suggests the avalanche capability.”.\nIt is true, but Fig. 2d also shows a degradation of VBR (VB) from 2240 V to about 1300 V from 250 °C to 300 °C. Is there a\nclear explanation ? Perhaps this strange behavior comes from some degradation of insulating layers… That demands some\nexplanations and that suggests the difficulty of reaching 250 °C.\nIn page 6, comes some comments on Fig. 3. In the caption it is written,\n“the insets show the optical images of the two prototyped submodules, where encapsulation is omitted to more clearly reveal\nthe package structure.”. That’s a good idea.\nMoreover in Supplementary Section S5 – Package Process, in the encapsulation section, it is written, “A 3D-printed polymer\nhousing was glued to the DBC surface using a slow-curing epoxy\nresin (Bob Smith Industries). A two-part silicone gel (Wacker 612 A/B) was mixed, vacuum-degassed to eliminate air\nbubbles”.\nUnfortunately, there is no presentation of the housing. The polymer structure, as well, silicone gel are some limitations for an\nindustrial product at 250 °C peak temperature. At least some comments or explanations must be given. For instance such\nhousing is needed to protect the module against moisture and other environmental duties.\nIn Supplementary Section S7 - Temperature-dependent Breakdown Characterization of SiC SBD, it is shown the\ntemperature limitation of the commercial SiC SBD (ROHM, S6304).\nThe comparison is not fair because some research papers show better performance even for high-voltage devices [1].\nIn Supplementary Section S9 - ANSYS Workbench simulation and calibration with experimental, Figure S9-2a is confusing\nbecause a similar but different circuit is presented in Fig. 4a and the associated optical pictures are the same.\nSome explanation must be given, at least for Fig. 4a, in the main text, where the SiC MOSFETs role must be given and the\nreferences of the devices are needed. Some explanations exist in Supplementary Section S11 –Experimental circuit testing\nsetup for short-pulse DPT but the MOSFETs references are not given. Moreover, this also contributes to the idea that SiC\nMOSFETs can replace Ga2O3 diodes in a pulsed power application. Further explanation is needed.\nIn figure S14, the color scale is not readable. Please correct that.\nFig. 3 | Thermal impedance characterization and time-resolved maximum power capacity\nderivation.\nIn Fig. 3e and Fig. 3f, it is clearly shown that the Ga2O3 module yields a better Zth or maximum transient power capacity\ndensity, respectively. However, this is not entirely fair because the SiC diode uses a TO220 package and has a low current\nrating, 19 A. It is even possible to deduce that, to better respect the maximum power density need in a pulse power\napplication, it is sufficient to choose a more recent diode with a higher current rating. So at least some additional\nexplanations must be given.\nFig. 4 | Demonstration of megawatt pulsed power switching in practical power converters.\nConcerning this figure, d) simulated time-resolved Tj evolution of the Ga2O3 sub-module with high-κ interface,\nbut the associate figure shows two curves. The read one (257 A) has a written label “breakdown” without any explanation.\nSome explanations or corrections must be given.\nFig. 5 | Surge current capability of Ga2O3 sub-module in conduction-dominant pulsed power\napplications.\nIn the caption, it is written, “… tested with an increased surge energy at a fixed pulse width of 3.6 µs. The critical peak surge\ncurrent is over 800 A.” For the top curve, it is written “device degradation”, but no explanation is given. Please correct this.\nConcerning the “Methods section”, it's rather confusing because the purpose of this section, after the conclusion, is unclear.\nProbably, a section before the conclusion with a small introduction to explain the purpose of the section will be clearer.\nThe conclusion is very positive for the performance of Ga2O3 modules for\n“pulsed power switching at 1000 A, 1000 V”.\nHowever, an analysis of the road map to industrial products should be very interesting for most readers. For instance in [2] it\nis written (by some of the same authors), “We envision the following immediate research gaps that need to be addressed for\nadvancing Ga2O3 into industrial power electronics applications”.\nProbably, a similar analysis of pulse power applications will be very useful.\nConclusion: the paper needs major revisions.", "reviewer_2": "The proposed methodology is novel and well-executed, integrating device-level dielectric engineering with packaging-level\nelectrothermal co-optimization. The incorporation of a high-k BaTiO3 interface for field flattening, combined with junction-\nside cooling and optimized die attach design, effectively address high electric field and thermal management challenges.\nThe authors also demonstrate a deep understanding of Ga2O3’s intrinsic properties, particularly its high volumetric heat\ncapacity and superior high temperature stability, and skillfully design both the device and packaging to exploit these\nadvantages for the high-pulse power applications. The module level results are encouraging and support the technical\nsoundness of the concept. Overall, this thoughtful UWBG co-design represents a promising step toward the practical\ndeployment of Ga2O3 based modules, particularly for high pulse energy use.\nPoints for clarification / potential concerns:\n1. It would be beneficial to add some comments on the dipole properties of BTO and why this material is the superior choice\nto others that may also possess such properties. I.e, why BTO?\n2. Will the high-k BaTiO₃ interface layer functionally replace the conventional SiO₂/SiN4 surface passivation on chips, or is it\nintended to be added on top of the conventional passivation to act as an additional field-modulation layer? If it is a\nreplacement, please comment on its insulating reliability and long-term stability? How will it stand up to humidity, a known\nissue with BaTiO3? I.e., will the field dampening properties be sacrificed? If so, by how much?\n3. Given the CTE mismatch between BaTiO₃ and Ga₂O₃, how robust is the interface during repeated thermal cycling and\nhigh-field pulsed operation? Please comment on potential interfacial defects, charge trapping/polarization drift, breakdown-\nvoltage stability, and any signs of delamination or micro-cracking.\n4. BaTiO₃ is deposited by RF magnetron sputtering in an Ar/O₂ ambient. How compatible is this process with large-area\nfabrication and downstream metallization/packaging?\n5. Can the high-k interface be extended to other WBG/UWBG devices (e.g., SiC, GaN, diamond)? If so, please outline\nmaterial-specific adaptations, interface reliability under cycling, CTE matching, and process compatibility.", "reviewer_3": "I co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the Nature\nCommunications initiative to facilitate training in peer review and to provide appropriate recognition for Early Career\nResearchers who co-review manuscripts.", "reviewer_4": "This is an excellent manuscript highlighting the performance of Ga2O3 UWBG power semiconductor devices,\nespecially for pulsed power applications. The autrhors provided a comprehensive literature review, indicating the uniques\nchallenges and how Ga2O3 can offer potential solutions. The emphasis on the electro-thermal co-design approach is a new\ntrend for all future power electronic systems. The experimintal demonstration of the Mega Watt pulse power is also impressive,\ncompleted with device simulation, packaging design, electrical and thermal considerations. I truly enjoy reading this paper.\nPerhpas one comment that may be help further improve this paper is to discuss how the repetition rate (or duty cycle) have\non the thermal capacity of the proposed power module. Will the proposed pulse power application require any thermal\nexchanger to further improve the performance?", "reviewer_5": "The paper demonstrates the first ultra-wide bandgap (UWBG) power module, which enhances the power capacity of UWBG\ndevices by over three orders of magnitude and identifies pulsed power electronics as a novel application for Ga2O3 power\ndevices. Considering the rapidly growing interest in UWBG power electronics and huge industrial investment in this domain,\nsuch a performance breakthrough is expected to have significant impact. This work also presents fundamental\nunderstanding by providing a high-κ device-package interface and highlighting the significance of heat capacity as a critical\nmaterial attribute for pulsed power electronics, suitable to various different semiconductors. This work could attract\nwidespread attention from this perspective.\nThe manuscript is clear, well written and well structured. The data are comprehensive, covering device, packaging, and\ncircuit-level verification, supported by theoretical analysis. To further improve the paper, the following technical points should\nbe clarified:\n1. For experimental circuit tests, is it possible to measure the power module under higher slew rate and switching\nfrequency? The authors are also suggested to comment on the limiting factors for slew rate and frequency in this circuit test.\n2. Ga2O3 devices are known to be promising for high-voltage applications, with devices up to 10,000 V having been\nexperimentally reported. Does the superior power capacity of Ga2O3 retain for higher-voltage devices? The authors may\nadd supplemental simulations.\n3. Following the above point, please also analyze if the power capacity advantage over SiC counterparts retains at higher\nvoltage, as SiC modules have been demonstrated up to 10 kV.\n4. In Fig. 1f, please clarify the physical mechanism by which the high-κ dielectric introduces dipole polarization charges at\nboth the high-κ/metal and high-κ/Ga2O3 interfaces.\n5. In Fig. 3b, the peak temperature appears at the anode edge for submodule B, but at the device center for submodule C.\nPlease explain the difference.\n6. Oscillations are observed in both the voltage and current waveforms in Fig. 4f and Fig. 4g\nfollowing the switching event. Please explain the origin of these oscillations. Additionally, are there any methods that can be applied to mitigate this\nphenomenon?\n7. For the pulse power application discussed, what is the rationale for selecting a pulse width of 3.6 µs? Furthermore, is it\nfeasible to reduce the pulse width?", "reviewer_6": "+ What are the noteworthy results?\n- This manuscript presents a novel power module based on Ga2O3 power devices for pulsed power applications. The\nmodule under investigation promises enhanced current/voltage capability as well as careful temperature management. The\nAuthors also assembled a multi-die module allowing switching at 1kA/1kV.\n+ Will the work be of significance to the field and related fields? How does it compare to the established literature? If the\nwork is not original, please provide relevant references\n- This work is significant to the field, as the proposed sample shows unprecedented features.\n+ Does the work support the conclusions and claims, or is additional evidence needed?\n- No additional evidence is needed.\n+ Are there any flaws in the data analysis, interpretation and conclusions? Do these prohibit publication or require revision?\n- Some minor remarks follow:\nIn fig. 1b there is a typo: \"shot\" is written but \"short\" was intended;\nInitially, the Authors claim that the value of the thermal conductivity of the assembly materials is not relevant in the case of\npulsed power electronics applications, whereas the heat capacity is the most important parameter; however, in the \"Device-\npackage electrothermal co-optimization\" paragraph, they underline the low-kt value of Ga2O3. Fig. 5h also shows that kt\nplays a relevant role in determining the thermal behavior of the modules. More details are needed to evaluate the individual\nimpact of the two above parameters on the FOMs of the proposed module.\n+ Is the methodology sound? Does the work meet the expected standards in your field?\n- The methodollgies are sound and meet the standart.\n+ Is there enough detail provided in the methods for the work to be reproduced?\n- The article as well as the supplementary material provide enough detail for the work to be reproduced."}, "author_response": "Response Letter (Manuscript ID: NCOMMS-25-66126)\nWe would like to thank Reviewers for their constructive and helpful suggestions. In the Response Letter, all\ncomments from reviewers have been addressed point-by-point, and the corresponding revisions have been\nhighlighted in BLUE in the revised manuscript. The replies are listed below.\n1. Response to 1st reviewer’s 2. Response to 2nd reviewer’s\ncomments comment\nPages numbers 1~23 24~30\n3. Response to 3rd reviewer’s 4. Response to 4th reviewer’s\ncomments comments\nPages numbers 31 32-34\n5. Response to 5th reviewer’s 6. Response to 6th reviewer’s\ncomments comments\nPages numbers 35-41 42-43\n1. Reply to the 1st reviewer’s comments\nReviewer #1 (Remarks to the Author):\nThe paper addresses the interesting topic of future pulsed power electronics. It mainly concerns the use of\nGa O , an UWBG material addressed in numerous recent publications.\n2 3\nThe presented diode Ga O module has very good performance.\n2 3\nThe originality of this paper comes from the pulsed power application and thus the major drawback of Ga O ,\n2 3\nits low thermal conduction, is less significant.\nHowever, some points must be better explained for the interest of most readers.\nResponse: We sincerely thank the reviewer for the positive and constructive comments. We appreciate the\nacknowledgment of the significance of pulsed power applications and the performance of our Ga O diode\n2 3\nmodule. Following the reviewer’s suggestions, we have revised the manuscript accordingly and improved\nthe explanations.\nComment (1): Page 4, concerning Fig. 1b “Pulsed power applications, material selection, as well as device\nand package designs.”, it is written, “Currently, pulsed power switches fall into two main categories: gas\ndischarge switches and solid-state switches”. However, Fig 1b shows controlled devices like thyratrons or\nSiC MOSFETs while the paper shows the performance of a Power Diode Module. So at least some\nexplanations about the role of diodes and controlled devices is expected. Particularly, what is the application\nof a good power diode module based on Ga O , as presented in the paper if no equivalent controlled switched\n2 3\nexists?\nResponse: We sincerely thank the reviewer for this insightful comment. We fully agree that the manuscript\nshould more clearly describe the roles of both power transistors (e.g., Si IGBT, SiC MOSFETs) and power\n1\ndiodes in pulsed-power systems.\nIn pulsed power systems, power transistors are usually used to control the pulse initiation, whereas\npower diodes are ubiquitously used for controlling the energy flow, as well as providing protection functions\nduring fast charge/discharge events. In nearly all pulsed-power architectures, including Marx generators,\nlinear transformer drivers, capacitor-bank discharges, XRAM current multipliers, and inductive-load pulsers,\ndiodes experience extremely large surge currents during capacitor discharge, very high di/dt from rapid\ncurrent interruption, high reverse blocking voltage during pulse formation, and often require avalanche and\ntransient energy absorption. These stresses are often more severe than those seen by power transistors (i.e.,\ncontrolled switches), making the performance of the diode equally critical.\nAs a general example, many pulsed-power systems drive inductive loads, such as pulsed magnetic-field\ngenerators, electromagnetic launchers, MRI gradient coils, pulsed solenoids, and magnetic-forming\nequipment. In inductive load switching circuit (Fig. R1)1-3, when the main switch turns off, the inductor\nforces V=L(di/dt), causing dangerous voltage overshoot. Here, the diode must conduct the full inductor\ncurrent through a freewheeling path, suppress large L·di/dt voltage spikes, undergo controlled avalanche\nunder extreme pulses to protect the switch.\nFigure R1. Inductive load switching circuit with freewheeling diode1-3.\nFor a more specific example, in electromagnetic launching systems (Fig. R2)4, the drive capacitor\ndischarges through the switch and coil. Once the capacitor is empty, the switch opens and the coil current\nmust fully flow through the diode until the launch completes. This requires a diode module with kA-level\nsurge capability and strong avalanche robustness.\nFigure R2. Single-stage reconnection electromagnetic launch model driving circuit4.\nAs another example, the XRAM current-multiplier circuit (Fig. R3) relies heavily on high-power diodes5.\nIn XRAM systems, multiple inductors are first charged in parallel by a low-voltage source and then\ndischarged in series to generate an exceptionally large load current. During this series-discharge process, the\n2\ndiodes must steer and combine the inductor currents, block high reverse voltages, and withstand extreme\nsurge stress. As a result, XRAM architectures impose exceptionally demanding requirements on the diodes,\nwith peak currents commonly reaching the kilo-ampere range and often exceeding 3 kA5.\nFigure R3. XRAM current multiplier circuit5.\nAs an example for the isolation function, some high-voltage pulse circuits often impose very high\ntransient reverse blocking demand on diodes. In voltage-multiplying and pulse-forming systems, such as\nMarx generators and stage-charging networks, diodes must block multi-kilovolt reverse voltage, high-\nfrequency charging transients, and echo/reflection voltages from pulse lines. For instance, Marx generator\ncharging stages shown in Fig. R4 require series-connected diodes to provide isolation and prevent reverse\nconduction during triggering6.\nFigure R4. Marx generator circuit6.\nMoreover, we would like to emphasize that many industrial pulsed-power circuits do not necessarily\nrely on controlled switches. In numerous practical systems, power diodes alone form the core functional\nelement, and no transistor is needed. For example, space and communication systems widely employ\nCapacitor-Diode-Based Voltage Multipliers (CDVMs), and microelectronic applications such as RF passive\ntransponders, passive wireless microsensors, and low-power portable devices commonly use Cockcroft-\nWalton (CW) multiplier stages (Fig. R5) for voltage boosting7,8. These circuits operate purely through the\ncoordinated action of diodes and capacitors, without any gate-driven switches, enabling exceptionally simple,\nlightweight, and high-reliability implementations.\nSimilarly, high-voltage generators used in X-ray sources, electrostatic precipitators, HV capacitor\nchargers, plasma generators, and many other pulsed-power systems rely heavily on CW-type multipliers. In\nsuch systems, the diode must sustain high reverse voltage, fast transient charging current, and low reverse-\nrecovery loss to maintain voltage regulation and pulse fidelity. These industrial applications therefore place\nstringent requirements on diode performance, independent of any controlled switching device.\nFigure R5. Cockcroft-Walton voltage multiplier7,8.\nOverall, a high-voltage, high-current, high-temperature-operational, and avalanche-and-surge capable\nGa O diode module can serve as a fundamental building block in a wide range of pulsed-power and high-\n2 3\nvoltage systems. This further underscores the practical value and immediate applicability of the Ga O diode\n2 3\nmodule demonstrated in our work.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 2nd paragraph of the “Pulsed power\napplications and material selection” section (Page 4) in the revised manuscript.\nRevised text:\n“Currently, pulsed power devices fall into two main categories: gas discharge devices and solid-state devices\n(Fig. 1b)30.”\nExpanded paragraph added:\n“Next-generation pulsed power devices, including both controlled switches (i.e., power transistors) and\npower diodes, are therefore in high demand. In pulsed-power systems, transistors are often used for initiating\nand shaping the pulse, whereas power diodes play indispensable roles in energy steering, stage isolation,\nrapid charge management, and transient overvoltage suppression. For instance, in inductive-load pulsed\ncircuits, the diode must withstand and conduct large surge currents while clamping voltage spikes induced\nby rapid current transients (L·di/dt), all within several micro-seconds. In high-voltage pulse generation\ncircuits, such as Marx and Cockcroft-Walton generators, the diode is further required to reliably block\nkilovolt reverse voltages.”\nReferences:\n[1] Williams, B.W. (1987). Load Considerations. In: Power Electronics. Palgrave, London.\nhttps://doi.org/10.1007/978-1-349-18525-2_6.\n[2]https://www.analog.com/en/resources/technical-articles/switching-inductive-loads-with-safe-\ndemagnetization.html.\n[3]https://www.powerelectronictips.com/what-is-the-purpose-of-a-freewheeling-diode-in-power-electronics.\n4\n[4] Dong, L., Jiang, W., Xie, X. et al. Design of maglev train driven by reconnection electromagnetic launcher.\nSci Rep 15, 22957 (2025). https://doi.org/10.1038/s41598-025-05992-0\n[5] H. Li et al., \"A Repetitive High-Current Pulse Generator Circuit Based on Multistage Pulse Transformers,\"\nin IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 9, no. 3, pp. 3189-3200, June\n2021, doi: 10.1109/JESTPE.2020.3010132.\n[6] Y. Wu, K. Liu, J. Qiu, X. Liu and H. Xiao, \"Repetitive and High Voltage Marx Generator Using Solid-\nstate Devices,\" in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 14, no. 4, pp. 937-940,\nAug. 2007, doi: 10.1109/TDEI.2007.4286529.\n[7] Khan, K. L., Verma, R., & Roy, A. (2024). Review of High Voltage Pulsed Power Supplies and Power\nElectronics in Pulse Power Generation. Power Research - A Journal of CPRI, 19(2), 157–162.\nhttps://doi.org/10.33686/pwj.v19i2.1140\n[8] F. Yuan and N. Soltani, \"Design techniques for power harvesting of passive wireless microsensors,\" 2008\n51st Midwest Symposium on Circuits and Systems, Knoxville, TN, USA, 2008, pp. 289-293, doi:\n10.1109/MWSCAS.2008.4616793.\nComment (2): Furthermore, Fig. 4a shows the schematic of the circuit used to test the surge power capability\nof the proposed Ga O diode module. This circuit uses some SiC MOSFETs. So a reader could understand\n2 3\nthat SiC MOSFETs are convenient for pulsed power applications, even to avoid the use of power diode\nmodules as in a synchronous converter. So why a power diode module is very important for pulsed power\napplications?\nResponse: We thank the reviewer for raising this important point. Building upon the clarification provided\nin our Response to Comment (1), power transistors and diodes are both required in pulsed power system.\nThe controlled switches trigger the pulse, while power diodes perform essential functions such as energy\nsteering, stage isolation, rapid charge management, and transient overvoltage suppression. In this test circuit\nof Fig. 4a, the SiC MOSFETs’ only purpose is to control short-pulse, high-voltage, and high-current\nwaveforms. These pulses are then delivered to the Ga O diode module, which is the only rectifying element\n2 3\nin the experiment – their functionalities and implementations are independent (e.g., can from two different\nsemiconductor technologies).\nAlthough SiC MOSFETs include a body diode and may be used in synchronous rectification, neither\nthe MOSFET body diode nor synchronous operation can replace a dedicated high-power diode in pulsed-\npower architectures, for the following reasons: 1) In any switching stage, a finite dead time is required to\navoid cross-conduction. During this interval: the energy must flow through a diode path, and the MOSFET’s\nbody diode becomes the unintended conduction path. Using only the MOSFET body diode leads to large\nreverse-recovery charge, high reverse current overshoot, elevated switching losses, and severe voltage\novershoot during L·di/dt events9. Thus, a separate external diode with fast recovery and strong robustness is\nessential, especially under high surge-current conditions used in our tests. 2) The SiC body diode typically\nsuffer from high forward voltage, large reverse-recovery charge, and strong bipolar degradation under high-\n5\ncurrent stress, poor avalanche and surge ruggedness compared with dedicated power diodes10. These\nlimitations become critical in pulsed-power systems. Thus, a discrete diode (module) is required to protect\nthe MOSFET and maintain pulse fidelity.\nFinally, regarding the material choice, we agree that SiC has excellent commercial diodes, as shown in\nFig. 3f in our manuscript, Ga O diodes offer unique and complementary advantages, higher blocking\n2 3\nstrength, higher transient power capability, and superior high-temperature performance compared with SiC\ndiodes, making them highly suitable for next-generation pulsed-power applications. Although commercial\nGa O transistors are still in their early stages, substantial progress is occurring toward Ga O power\n2 3 2 3\ntransistors that would eventually complement the diode demonstrated in this work. Recent reports present\nthe Ga O transistors with super high voltage of 10kV, which presents great potential in the power\n2 3\napplications. Once Ga O transistor technology is mature, a Ga O diode module will be the natural\n2 3 2 3\ncomplementary component, enabling fully Ga O -based pulsed-power platforms with unprecedented power\n2 3\ndensity and compactness.\nCorresponding change in manuscript: No\nReference:\n[9] X. Liu, X. Li, C. Herrmann and T. Basler, \"The Impact of the Dead-Time on the Reverse Recovery\nBehavior of SiC-MOSFET Body Diodes,\" 2023 35th International Symposium on Power Semiconductor\nDevices and ICs (ISPSD), Hong Kong, 2023, pp. 322-325, doi: 10.1109/ISPSD57135.2023.10147719.\n[10] X. Jiang et al., \"Investigation on Degradation of SiC MOSFET Under Surge Current Stress of Body\nDiode,\" in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 8, no. 1, pp. 77-89,\nMarch 2020, doi: 10.1109/JESTPE.2019.2952214.\nComment (3): Page 5, it is written: “As thermal diffusion is negligible, an approximate model dictates the\nlocal temperature rise ΔT to scale with Q/(C V), where Q is the heat generation energy, and V is the material\nV\nvolume. Hence, materials with higher C can absorb more energy with smaller temperature increases, offering\nv\nsuperior thermal buffering against fast surges”\nThis is true, and fig 2.c shows a better, about a ratio of 2, C for Ga O than for SiC, but the build-in potential\nv 2 3\nis higher in Ga O (~ 4.5 V) than in SiC (~2.8 V). So heat generation could be higher for Ga O . Furthermore,\n2 3 2 3\nin pulse power applications, heat generation is related to the high-pulsed current.\nThis issue is no more included in the Baliga’s FOM. So the conclusion of such data is not so easy and demands\nfurther discussion.\nResponse: We appreciate the reviewer’s insightful comments regarding the relationship between heat\ngeneration, built-in potential, and the thermal response during fast surge events. Our original intention was\nto provide a generic discussion on the transient temperature rise under the assumption of comparable heat\ngeneration (i.e., power loss). Our comparison of transient thermal buffering focuses on the material-\ndependent volumetric heat capacity C , assuming a similar heat generation level. Meanwhile, we agree that\nv\n6\nthe built-in potential and current amplitude affect the actual power dissipation, and we have clarified this\nsection accordingly.\nAlthough the intrinsic built-in potential of Ga O (~4.5 V) is higher than that of SiC (~2.8 V), the\n2 3\neffective forward voltage during conduction is also determined by device structure interface properties. For\nexample, in our NiO/Ga O heterojunction diode, the measured V is ~2 V, significantly lower than the\n2 3 ON\ntheoretical built-in potential of Ga O . In contrast, commercial SiC devices (e.g., the body diode of SiC\n2 3\nMOSFETs) often exhibit a similar or even higher V (which is usually close to SiC’s built-in potential).\nON\nThus, the practical forward conduction loss of Ga O diodes is not necessarily larger than that of SiC\n2 3\ncounterparts. Under high current surge conditions, the forward voltage is dominated by resistive drop rather\nthan the built-in voltage. Due to the diverse selection of device structure (e.g., homo-junction or hetero-\njunction) and the possibility of varying operation conditions (e.g., high surge current), it is very difficult to\nestablish a point-to-point relation between a material’s built-in potential and the conduction loss of power\ndiodes.\nWe appreciate the reviewer’s suggestion and have revised the wording to avoid implying that heat\ngeneration (i.e., power loss) is assumed to be identical across materials for the discussion under the specific\ncontext. This revision clarifies that the comparison is made under identical heat-load conditions and\nhighlights the physical meaning of C without conflating it with power loss mechanisms.\nv\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 3rd paragraph of the “Pulsed power\napplications and material selection” section (Page 5) in the revised manuscript.\nRevised text:\n“Hence, a higher C indicates a smaller temperature increase under the identical power loss32.”\nv\nComment (4): Fig. 2a, Breakdown voltage enhancement and sub-modules’ electrical characteristics.\nThe figure seems to be related to a heterojunction but it is not mentioned in the caption. It will be clearer for\nmost readers to explicitly mention it in the caption. Concerning the presented result, it is written, “all\nsimulated under a reverse bias of 2000 V”, while in Fig 2b), “Reverse I-V characteristics of three types of\nGa O sub-modules with different package structures” show V about of 930 V, 1560 V for structures A and\n2 3 BR\nB, so this is inconsistent. That needs some explanations or corrections.\nMoreover Fig. 2a shows a higher electric field (with orange region) in case of sub-modules A and C but not\nin case of sub-module B. This is also inconsistent with the I-V characteristic in Fig 2b. So please correct this\nor give an adequate explanation.\nResponse: We sincerely thank the reviewer for carefully examining Fig. 2. We provide detailed clarifications\nbelow and expand the discussion from the device-physics perspective to ensure full transparency. As\nsuggested, the caption of Fig. 2a has been revised to: “Simulated two-dimensional electric field contours in\nJSC-packaged NiO/Ga O heterojunction devices.” This clearly informs readers that the sub-modules\n2 3\ncorrespond to NiO/Ga O heterojunction diodes.\n2 3\nB\nmodule B) are lower than the 2000-V bias used in Fig. 2a (so simulation here presents a somewhat\n‘hypothetical’ case for these two sub-modules). Our purpose was to compare how different package structures\nredistribute electric fields under the same applied voltage, which is a standard and widely accepted method\nin power device research and presented in numerous publications11-13. Using the same bias condition allows\nthe differences in field modulation between sub-modules A, B, and C to be directly visualized and fairly\ncompared. A unified bias allows readers to see where the weakness of each structure lies, even if that voltage\nexceeds the measured breakdown of some structures.\nThe reviewer observed that peak electric fields in Fig. 2a appear higher in sub-modules A and C, yet\ntheir measured breakdown voltages differ in Fig. 2b. We emphasize that: V depends not only on peak field\nB\nmagnitude, but also on where the peak field occurs and the critical field of the material at that location. For\nsub-module A with the lowest V of 930V, at 2000 V bias, the peak E-field in submodule A is ~19 MV/cm\nB\ninside SiO , but the color bar saturates at 6 MV/cm to maintain visualization range. The deposited SiO has\n2 2\na critical breakdown field around 10 MV/cm (depending on thickness and quality). Any local\nconcentration >10 MV/cm triggers dielectric failure, forming leakage paths or micro-cracks. The SiO /metal\n2\ninterface is especially sensitive to field crowding, often dominating early failures. Thus, even though the\n2000-V simulation is above its measured breakdown voltage, the field distribution correctly reveals that SiO\n2\nis the limiting factor in sub-module A.\nFor sub-module B with V of 1560V, although submodule B shows a lower peak field (~4.4 MV/cm) at\nB\n2 3\nfield enhancement in the main junction leads to stronger local heating and faster thermal runaway. Meanwhile,\njunction is highly sensitive to defect-assisted impact ionization, sputtered NiO contains high density of grain\nboundaries and vacancies, which will trigger trap-assisted tunneling and localized thermal spots. Thus, sub-\nmodule B fails at 1560 V even though its simulated peak field (at 2000 V) is lower than that of sub-module\nC. For sub-module C with the highest V , the peak field of 5.7 MV/cm is located inside Ga O at the edge\nB 2 3\ntermination, not the main junction with the hetero-interface with NiO. This configuration is superior because\nhigh-quality single crystalline Ga O has an ultra-high theoretical critical field (>8 MV/cm), safe even at 5.7\n2 3\nMV/cm, and the field in the main junction is only 3.05 MV/cm. The edge termination can maintain uniform\nE-field and suppress hot spots in the main junction. Thus, sub-module C achieves the highest measured\nbreakdown voltage.\nTo further verify consistency between the simulated and measured breakdown voltages, we have added\nelectric-field contours simulated at the actual breakdown points. As shown in Fig. R6, at 930 V for sub-\nmodule A, the peak electric field within the SiO layer reaches approximately 11.7 MV/cm, which exceeds\n2\nthe dielectric strength of SiO and confirms that breakdown is governed by dielectric failure. For submodule\napproximately 4.2 MV/cm, which is significantly higher than the average junction field. Given the large\ndevice area (3 mm × 3 mm), localized leakage paths can readily initiate in this high-field region, ultimately\n8\nleading to breakdown.\nFig. R6. Simulated two-dimensional electric field contours in JSC-packaged NiO/Ga O heterojunction\n2 3\ndevices (a) with a SiO interface (control sub-module A) at 930 V, (b) with a post interface (control sub-\n2\nmodule B) at 1560 V.\nCorresponding change in manuscript: Yes\nLocation of Change:\n(1) The caption of Fig. 2a has been revised to: “Simulated two-dimensional electric field contours in JSC-\npackaged NiO/Ga O heterojunction devices.”\n2 3\n(2) Fig. R6. and related explanation have been incorporated into the “Supplementary Section S6” section\n(Page 8) in the revised Supplementary Information.\nReference:\n[11] J. Wen et al., \"Vertical β-Ga O Power Diodes: From Interface Engineering to Edge Termination,\" in\n2 3\nIEEE Transactions on Electron Devices, vol. 71, no. 3, pp. 1606-1617, March 2024, doi:\n10.1109/TED.2024.3360016.\n[12] Sushovan Dhara, Nidhin Kurian Kalarickal, Ashok Dheenan, Chandan Joishi, Siddharth Rajan. β-Ga O\n2 3\nSchottky barrier diodes with 4.1 MV/cm field strength by deep plasma etching field-termination. Appl.\nPhys. Lett. 14 November 2022; 121 (20): 203501.\n[13] X. Liu et al., \"1.7-kV Vertical GaN-on-GaN Schottky Barrier Diodes With Helium-Implanted Edge\nTermination,\" in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 1938-1944, April 2022, doi:\n10.1109/TED.2022.3153594.\nComment (5): Furthermore, on page 6 it is written, “the V increases from 2010 V to 2240V with T from RT\nB\nto 250 °C, exhibiting a positive temperature coefficient of ~1 V/°C, which suggests the avalanche capability.”.\n9\n)mm(\nnoitisoP\na\n2\n0\n-2\n-4\n-6\n-8\n-1 0\nN\no d\niO\ne\nO\nS u b\nv e rflo\nA g\nN i/A u\nN iO\n2 0\n- m o d u le A a t 9 3 0 V\nO v e rflo w e d A\nS iO\nG a O e p ila y e r\n2 3\nw e d\nS iO /T i 2\nG a O e p ila y e r 2 3\n4 0 6 0 8 0\nP o s itio n ( m ) m\ng\n2\n1 0\nM\n6\n5\n4\n3\n2\n1\n0\nm\nb\n)mm(\nnoitisoP\n2\n0\n-2\n-4\n-6\n-8\n-1 0\nS u b - m o d u le B a t 1 5 6\nA n o d e\nN iO\nin ju n c tio n\nG a O e p ila y e r\n2 3\nD B C\nP o s t\nS in te re d A g\nN i/A u /T i\nN iO\nG a O e p ila y e r 2 3\n2 0 4 0 6 0\nP o s itio n ( m ) m\n8 0 1 0\nM\n6\n5\n4\n3\n2\n1\n0\nm\nIt is true, but Fig. 2d also shows a degradation of V (V ) from 2240 V to about 1300 V from 250 °C to\nBR B\n300 °C. Is there a clear explanation? Perhaps this strange behavior comes from some degradation of insulating\nlayers… That demands some explanations and that suggests the difficulty of reaching 250 °C.\nResponse: We thank the reviewer for this insightful comment. The observation is correct that while the\nbreakdown voltage (V ) increases from room temperature to 250 oC with a positive temperature coefficient,\nB\nFig. 2d indeed shows a pronounced degradation of V when the temperature further increases from 250 oC to\nB\n300 oC. This behavior is not contradictory but instead reflects the appearance of a non-ideal preliminary\nbreakdown mechanism at extreme high temperatures, as explained below.\nWe believe the V degradation observed at 300 oC is primarily attributed to the trap-mediated\nB\npreliminary breakdown at a lower voltage before the intrinsic avalanche breakdown initiates, and such\npreliminary breakdown is likely due to the trap-assisted tunneling (TAT) current, which is highly dependent\non temperature and electric field and has been widely reported as the preliminary breakdown mechanism in\nwide-bandgap and ultra-wide bandgap power devices14-18. Moreover, this trap-mediated breakdown exhibits\na negative temperature coefficient ~11V/oC19, which is close to the V transition from 250 oC to 300 oC in\nB\nour device.\nThe location of trap-mediated preliminary breakdown is usually localized and consistent with the peak\nelectric field location18,20. As shown in Fig. R7a, under a reverse bias of ~2 kV, the peak electric field is at\nthe Ag/BTO/Ga O edge region. As the BTO layer is deposited by magnetron sputtering, which typically\n2 3\ncontains a non-negligible density of grain boundaries, a relatively high density of interface states can exist at\nboth the Ag/BTO interface and the BTO/Ga O interface. According to the band diagram (Fig. R7b), under\n2 3\nreverse bias, electrons can tunnel from Ag into the BTO layer via interfacial traps and subsequently tunnel\ninto Ga O through defect states at the BTO/Ga O interface. This path competes with the usual thermal\n2 3 2 3\nemission path (see dashed lines in Fig. R7b). At elevated temperatures, this trap-assisted tunneling process\nis thermally activated and significantly enhanced by high electric field, leading to rapidly increased leakage\ncurrent and premature breakdown at 300 oC.\nIn fact, similar trap-assisted preliminary breakdown mechanisms were also observed in other two\nsubmodules, whilst the preliminary breakdown locations can be very different. Fig. R8 shows the\ntemperature-dependent I-V characteristics of Ga O Sub-module A and Sub-module B, V both show\n2 3 B\nnegative temperature coefficient throughout temperatures from RT to 300 oC. Specifically, for sub-module\nA with a SiO interface, the peak electric field is concentrated at the Ag/SiO /Ga O edge, where tunneling\n2 2 2 3\ncan likewise be assisted by defect states in the SiO interface region. For sub-module B with the post interface,\n2\nthe peak electric field shifts to the main NiO/Ga O junction edge, where tunneling is facilitated by defect\n2 3\nstates in the NiO layer and the heterojunction. In all cases, increasing temperature leads to a sharp rise in\nleakage current and a substantial reduction in breakdown voltage. Therefore, we believe that the dominant\nfailure mechanism of sub-module C at 300 oC is the trap-assisted preliminary breakdown possibly originated\nfrom the interface states between Ag, BTO and Ga O .\n2 3\n2 3\ndevices with a BTO interface (Sub-module C) at 2 kV. (b) Band diagram of the Ag/BTO/Ga O structure\n2 3\nunder reverse high voltage. The dashed line shows the usual thermal electron emission path, and the solid\nline shows the TAT leakage path.\nFig. R8. Temperature-dependent reverse I-V characteristics of the Ga O sub-module A with SiO interface\n2 3 2\nand sub-module B with post interface.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 5th paragraph of the “Device-package\nelectrothermal co-optimization” section (Page 7) in the revised manuscript.\nExpanded text:\n“When the temperature is further increased to 300 oC, V decreases to 1330 V, which is likely due to the trap-\nB\nassisted preliminary breakdown possibly originating from the interface states between Ag, BTO and Ga O .\n2 3\nSuch a trap-assisted breakdown has been widely reported in other ultra-wide bandgap power devices and\nfeatures a negative temperature coefficient69,70.”\n11\n( a\n( a\n)A(\ntnerruC\n)\n)\n1\n-2\n)mm(\n-4 noitisoP\n-6\n-8\n-1 0\n0\n-4 1 0\n-6 1 0\n-8 1 0\n-1 0 0\n- 1 5 0\nn\n0\no d\nM\nS u b -m o d u le C\nO v e rflo e\na in ju n c tio n\nG a O e p ila y e r\n2 3\nO ve rflo w e d\nA g\nN i/A u /T i\nN iO\nG a O e p ila y e r\n2 3\n2 0 4 0 6 0\nP o s itio n ( m ) m\nS u b - m o d u l e A\nT\no R T 5 0 C\no o 1 0 0 C 1 5 0 C\no o 2 0 0 C 2 5 0 C\no 3 0 0 C\n- 1 0 0 0 - 5 0 0\nV o lt a g e ( V )\nw e d\nB\n8 0\nA g\nB T\nT O\nO\n1\n0\n6\n5\n4\n3\n2\n1\n0\nm\n(\n)A(\ntnerruC\nb\n1\n)\n1\n1\n1\n0\n( b\n-4 0\n-6 0\n-8 0\n-1 0\n- 2 0 0\n)\nR\n1\nT E\nB T\nS u b - m\nT\no 0 0 C\no 0 0 C\nT\n- 1\nV o lt a\n-fie ld\nT A T\nO G a O\n2\no d u l e B\no 5 0 Co\n1 5 0 Co\n2 5 0 C\n0 0 0\ng e ( V )\n3\n3 0 0 o C\n[14] X. Zou, X. Zhang, X. Lu, C. W. Tang and K. M. Lau, \"Fully Vertical GaN p-i-n Diodes Using GaN-on-\nSi Epilayers,\" in IEEE Electron Device Letters, vol. 37, no. 5, pp. 636-639, May 2016, doi:\n10.1109/LED.2016.2548488.\n[15] Ruizhe Zhang and Yuhao Zhang, “Power device breakdown mechanism and characterization: review\nand perspective,” Jpn. J. Appl. Phys. 62 SC0806, 2023.\n[16] A. O. Konstantinov, N. Nordell, Q. Wahab, U. Lindefelt; Temperature dependence of avalanche\nbreakdown for epitaxial diodes in 4H silicon carbide. Appl. Phys. Lett. 28 September 1998; 73 (13): 1850–\n1852.\n[17] Z. Zhang et al., \"Trap-Induced Leakage Current Increase in β-Ga O Schottky Barrier Diodes Under\n2 3\n473-MeV Kr Ion Irradiation,\" in IEEE Transactions on Nuclear Science, vol. 72, no. 11, pp. 3543-3550, Nov.\n2025, doi: 10.1109/TNS.2025.3620821.\n[18] Zhanbo Xia, Hareesh Chandrasekar, Wyatt Moore, Caiyu Wang, Aidan J. Lee, Joe McGlone, Nidhin\nKurian Kalarickal, Aaron Arehart, Steven Ringel, Fengyuan Yang, Siddharth Rajan; Metal/BaTiO /β-Ga O\n3 2 3\ndielectric heterojunction diode with 5.7 MV/cm breakdown field. Appl. Phys. Lett. 16 December 2019; 115\n(25): 252104.\n[19] Y. Qin et al., \"10-kV Ga O Charge-Balance Schottky Rectifier Operational at 200 oC,\" in IEEE Electron\n2 3\nDevice Letters, vol. 44, no. 8, pp. 1268-1271, Aug. 2023, doi: 10.1109/LED.2023.3287887.\n[20] J. Liu et al., \"Trap-Mediated Avalanche in Large-Area 1.2 kV Vertical GaN p-n Diodes,\" in IEEE\nElectron Device Letters, vol. 41, no. 9, pp. 1328-1331, Sept. 2020, doi: 10.1109/LED.2020.3010784.\nComment (6): In page 6, comes some comments on Fig. 3. In the caption it is written, “the insets show the\noptical images of the two prototyped submodules, where encapsulation is omitted to more clearly reveal the\npackage structure.”. That’s a good idea.\nMoreover in Supplementary Section S5 – Package Process, in the encapsulation section, it is written, “A 3D-\nprinted polymer housing was glued to the DBC surface using a slow-curing epoxy resin (Bob Smith\nIndustries). A two-part silicone gel (Wacker 612 A/B) was mixed, vacuum degassed to eliminate air\nbubbles”.\nUnfortunately, there is no presentation of the housing. The polymer structure, as well, silicone gel are some\nlimitations for an industrial product at 250 oC peak temperature. At least some comments or explanations\nmust be given. For instance such housing is needed to protect the module against moisture and other\nenvironmental duties.\nResponse: We thank the reviewer for raising these important questions regarding the housing and silicone-\ngel encapsulation materials. As correctly noted by the reviewer, to better show the internal package structures,\nthe optical images in the inset of Fig. 3a show sub-modules without encapsulation. In addition, all high-\ntemperature forward and reverse I-V characterization were performed on devices before the final housing or\nsilicone gel, to avoid the temperature limitations of these materials during the long characterizations at 250-\n300 oC.\nreviewer is correct that such polymer is not suitable for long-term operations at 250 oC. However, in this\nsubmodule, the housing is located far above the active device region. It mainly serves as a mechanical support\nand fixture to form a cavity for gel filling. It is not in direct thermal contact with the Ga O chip, the BTO\n2 3\nhigh-k interface, or the sintered-Ag layer. Thus, the housing does not experience the high junction-\ntemperature during transient power events, particularly in pulsed power applications.\nThe encapsulant used in the sub-module is Wacker SilGel 612 A/B, a two-component silicone gel with\nhigh dielectric strength, very low modulus, long-term reliable temperature up to ~200 oC and excellent\nmoisture barrier property. In the sub-module, silicone gel is used to provide isolation and anti-vibration\nprotection and prevent moisture or ionic contamination. Importantly, the silicone gel is not placed in the high\nheat-flux region.\nBecause pulse power is highly transient (microseconds-milliseconds), a strong temperature gradient is\npresent, and the encapsulant region remains far below 200 oC. The junction temperature during transient\npower may momentarily reach 250-300 oC. But the external package temperature remains much lower because\nof the extremely short pulse width and the low thermal diffusivity between junction and housing. Therefore,\nthe over 200 oC capability demonstrated in Fig. 2 represents an intrinsic property of the Ga O device itself\n2 3\nand the JSC stack, not of the external housing or silicone gel.\nWe agree with the reviewer that for industrial-grade 250 oC modules (particularly for applications with\nlonger pulses or even conventional switching applications), more robust encapsulation materials are needed.\nAs part of our continuing development plan, we will migrate to high-temperature housings (e.g., PEI/Ultem,\nPEEK and Metal frame structures) for maximum thermal stability. For high-temperature encapsulants,\nceramic-filled silicone gels and glass-based encapsulants are also in the further research, which can ensure\ntrue high-temperature reliability for industrial implementation.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the last paragraph of the “Supplementary\nSection S5 – Package Process” section (Page 7) in the revised Supplementary Information.\nExtended text:\n“A 3D-printed engineering-grade nylon housing was glued to the DBC surface using a slow-curing epoxy\nresin (Bob Smith Industries). The housing mainly serves as a mechanical support and fixture to form a cavity\nfor gel filling. A two-part silicone gel (Wacker 612 A/B) was mixed, vacuum-degassed to eliminate air\nbubbles, and poured into the housing to fully encapsulate the device and interconnects. The silicone gel is used\nto provide isolation and anti-vibration protection and prevent moisture or ionic contamination. The assembled\nmodules were then cured at 150 °C for 30 minutes on a hotplate to complete the packaging process. The\njunction temperature during transient power may momentarily reach 250-300 oC. But the external package\ntemperature remains much lower because of the extremely short pulse width and the low thermal diffusivity\n13\nbetween junction and housing. Therefore, the over 200 oC operation capability demonstrated in Fig. 2 reflects\nan intrinsic property of the Ga O device itself and the JSC stack, not of the external housing or silicone gel.”\n2 3\nComment (7): In Supplementary Section S7 - Temperature-dependent Breakdown Characterization of SiC\nSBD, it is shown the temperature limitation of the commercial SiC SBD (ROHM, S6304). The comparison\nis not fair because some research papers show better performance even for high voltage devices [1].\nReferences\n[1] KIMOTO, Tsunenobu, YAMADA, Kyosuke, NIWA, Hiroki, et al. Promise and challenges of high-\nvoltage SiC bipolar power devices. Energies, 2016, vol. 9, no 11, p. 908.\nResponse: We appreciate the reviewer’s comment regarding the temperature limitation of the commercial\nSiC SBD (ROHM, S6304) in Supplementary Section S7 and the suggestion to compare with SiC devices\nreported in above reference cited by the review. Our intention in Supplementary Section S7 was not to claim\nan absolute breakdown limit of SiC, but to provide a practical benchmark against a commercially available\n1.2-kV-class device with comparable drift-layer thickness and voltage rating to our Ga O diode.\n2 3\nThe paper cited by the reviewer (Kimoto et al., Energies, 2016, vol. 9, no 11, p. 908) is an excellent and\ncomprehensive review on high-voltage SiC bipolar power devices, focusing on PiN structures or merged\nPiN-Schottky (MPS) structures for ultra-high-voltage (>10 kV) applications. In these devices, the drift layer\nis typically very thick (50-100 µm) and engineered with strong conductivity modulation (i.e., strongly\nbipolar), target breakdown voltage is over 10 kV.\nIn contrast, our work targets Ga O diodes with very fast switching (i.e., ‘unipolar’) (note that although\n2 3\na bipolar NiO/Ga O heterojunction is used, due to the very short hole lifetime in Ga O , the diode is nearly\n2 3 2 3\nunipolar as proofed by the minimal reverse recovery), where the closest practical SiC counterpart in real\napplications is a 1.2-kV SiC SBD/JBS diode, rather than a >10 kV SiC PiN diode. Bipolar SiC PiN diodes\nare rarely used in standard 1.2-kV power conversion stages because of large forward voltage and significant\nreverse recovery loss due to minority carrier storage. Therefore, the cited reference by the review represents\nthe ultimate potential of ultra-high-voltage SiC bipolar devices, but not the typical unipolar device class\ndirectly comparable to our Ga O heterojunction diode in this work.\n2 3\nWe intentionally chose a commercial 1.2-kV SiC SBD (ROHM S6304) with a close voltage rating and\ncomparable drift-layer thickness. Although the ROHM S6304 is marketed as a “SiC SBD,” the bare die we\nobtained has a junction barrier Schottky (JBS) structure, which is in fact standard for most modern “SiC\nSBDs.” The device combines Schottky regions with buried p+ grids to suppress leakage. Under reverse bias,\nespecially at high temperature, leakage is still predominantly governed by the metal/SiC Schottky barrier,\nleading to a pronounced increase of leakage with temperature. This behavior, rapidly increasing reverse\nleakage current and practical breakdown limitation at elevated temperature, is well reported for SiC\nSchottky/JBS diodes in the literature Ref. 21 and Ref. 2221,22. While our Ga O heterojunction diode\n2 3\nmaintains lower leakage and more robust high-temperature blocking under the same bias and test setup.\nCorresponding change in manuscript: Yes\nSection S7” section (Page 10) in the revised Supplementary Information.\nExpanded text:\n“The SiC reference device used in Supplementary Section S7 is a commercial 1.2-kV SiC junction barrier\nSchottky (JBS) diode with a drift layer thickness comparable to our Ga O device. Note that it is used to\n2 3\nrepresent a typical industrial SiC SBD in the close voltage class, rather than the ultimate capability of high-\nvoltage SiC bipolar devices that has been reported to be able to operate at very high temperatures15. The\ndevice combines Schottky regions with buried p+ grids to suppress leakage. Under reverse bias, especially at\nhigh temperature, leakage is still predominantly governed by the metal/SiC Schottky barrier, leading to a\npronounced increase of leakage with temperature.”\nReference:\n[21] R. Radhakrishnan, T. Witt and R. Woodin, \"Temperature dependent design of Silicon Carbide Schottky\ndiodes,\" 2014 IEEE Workshop on Wide Bandgap Power Devices and Applications, Knoxville, TN, USA,\n2014, pp. 151-154, doi: 10.1109/WiPDA.2014.6964644.\n[22] P. Brosselard et al., \"Bipolar Conduction Impact on Electrical Characteristics and Reliability of 1.2- and\n3.5-kV 4H-SiC JBS Diodes,\" in IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 1847-1856, Aug.\n2008, doi: 10.1109/TED.2008.926636.\nComment (8): In Supplementary Section S9 - ANSYS Workbench simulation and calibration with\nexperimental,\nFigure S9-2a is confusing because a similar but different circuit is presented in Fig. 4a and the\nassociated optical pictures are the same.\nSome explanation must be given, at least for Fig. 4a, in the main text, where the SiC MOSFETs role must be\ngiven and the references of the devices are needed. Some explanations exist in Supplementary Section S11 –\nExperimental circuit testing setup for short-pulse DPT but the MOSFETs references are not given. Moreover,\nthis also contributes to the idea that SiC MOSFETs can replace Ga O diodes in a pulsed power application.\n2 3\nFurther explanation is needed.\nResponse: Thanks for the suggestion. The associated optical pictures in Figure S9-2a and Fig. 4a are different\nin all aspects, including PCB layout, device numbers, and connection configurations. It should be clarified\nthat the dynamic switching test and the surge current test share the same physical circuit board with different\nconnection configurations to achieve the target circuit functions (as seen in Fig. 5b and Supplementary Figure\nS9-2b), whereas the megawatt pulsed power test utilizes a completely separate, customized designed circuit\nboard to represent the unique operation profiles in pulsed power applications (as seen in Fig. 4b).\nConventional switching tests (e.g., double pulse test) primarily evaluate device behavior under moderate\nvoltage and current levels, whereas pulsed-power systems deliver much larger energy within ultra-short and\ntunable pulse widths, requiring a highly compact circuit topology with minimized loop inductance and\n15\nextremely low parasitic resistance to support megawatt-level instantaneous power.\nFig. R9 illustrates the circuit schematic and PCB layout for the multi-functional board used in both the\ndynamic switching (Supplementary Figure S9-2b) and surge current tests (Fig. 5b). This board integrates two\nswitches (S1 and S2), DC-link capacitors (C ), the DC power supply (V ), and the DUT. The circuit\nDC DC\ntopology is reconfigured via specific connection nodes: for the surge current test, Node 1 (N1) is connected\nto the surge inductor (L ) and Node 2 (N2) is left open, reproducing the circuit in Fig. 5a in the manuscript.\nsurge\nFor the dynamic switching test, N1 is shorted while the switching inductor (L ) is connected to N2,\nswitch\nreproducing the circuit in Supplementary Figure S9-2a. Fig. R9b highlights these connecting nodes to\ndemonstrate how this design strategy shares key components to significantly reduce design cost.\nFig. R9. (a) Circuit schematic and (b) PCB layout of the multi-functional board used for both dynamic\nswitching test and surge current test.\nIn contrast, the megawatt pulse power test board is different, and we have provided its specific PCB\nlayout in Fig. R10 for reference to clearly distinguish it from the multi-functional board. The detailed circuit\noperation has been presented in Supplementary Section S11.\n16\n(\n(\na\nb\n)\n)\nFig. R10. PCB layout of the dedicated pulse power circuit board.\nIn Fig. 4a, the part number of the SiC MOSFETs used in megawatt pulsed power switching circuit is\nC3M0016120D from Wolfspeed, the rated voltage is 1200 V and the typical on-resistance (R ) is 16 mΩ.\non\nThese devices were chosen solely because they offer very low R and fast switching at 1.2-kV rating,\non\nenabling the generation of high-current, fast-rise-time pulsers required to stress our Ga O diode module.\n2 3\nHere we use four switching branches, each consisting of five SiC MOSFETs in parallel. The MOSFETs’\nonly purpose is to control short-pulse, high-voltage, and high-current waveforms. These pulses are then\ndelivered to the Ga O diode module, which is the only rectifying element in the experiment. The reason for\n2 3\nusing many MOSFETs in parallel is to minimize the effective on-resistance of the switch array,\nachieve >1000 A pulsed current capability and reduce stress on individual MOSFETs during fast pulses.\nAs discussed in our Response (1) earlier, power diodes are mandatory components in pulsed-power\ncircuits. In practical pulsed systems, such as Marx generators, pulse-forming networks, inductive storage,\ncapacitive discharge systems, and high-current pulse chargers, diodes are essential for directing energy flow,\nisolating stages, clamping voltage transients, providing freewheeling paths during fast current interruptions\nand ensuring safe dead-time operation in converters. Although SiC MOSFET has intrinsic body diode, it\nsuffers from bipolar degradation and considerable reverse recovery, associated with basal-plane dislocation\nexpansion under forward conduction. The SiC MOSFET body diode is generally not used as a freewheeling\nor pulsed conduction diode in high-reliability power systems. Ga O diodes exhibit several properties that\n2 3\nmake them fundamentally more suitable than SiC MOSFET body diodes in pulsed-power operation. The\nGa O diode maintains stable high-temperature characteristics up to 250 °C, high-power capacity density,\n2 3\nsuperior surge current robustness, and fundamentally low-T rise due to Ga O ’s higher volumetric heat\nj 2 3\ncapacity. In summary, based on the different functionalities of SiC MOSFETs and Ga O diodes in pulsed\n2 3\npower circuits as well as the fundamental enabling capabilities of Ga O devices illustrated in this project,\n2 3\nGa O diodes cannot be replaced by SiC MOSFETs in a pulsed power application.\n2 3\nCorresponding change in manuscript: Yes\ndemonstration of megawatt pulsed-power switching” section (Page 8) in the revised manuscript, and the\n1st paragraph of the “Supplementary Section S11” section (Page 17) in the revised Supplementary\nInformation.\nRevised text:\n(1) “The DPT circuit consists of power SiC MOSFETs (C3M0016120D), an inductor, and the diode under\ntest (DUT). The inductor is first pre-charged to a target current value, acting as a current source. The SiC\nMOSFETs are used to control short-pulse, high-voltage, and high-current waveforms with an adjustable pulse\nwidth, these pulses are then delivered to the Ga O DUT for evaluating its turn-on and turn-off characteristics.”\n2 3\n(2) “The part number of the SiC MOSFETs is C3M0016120D from Wolfspeed, the rated voltage is 1200 V\nand the typical on-resistance (R ) is 16 mΩ.”\non\nComment (9): In figure S14, the color scale is not readable. Please correct that.\nResponse: We thank the reviewer for pointing this out. As shown in Fig. R11, the color scale in Fig. S14 has\nbeen enlarged and reformatted to improve readability. The updated figure has been included in the revised\nsupplementary document.\n3.6 us 8.5 us 73 us\nTemp. (oC) Temp. (oC) Temp. (oC)\n650.9 615.4 565.8\n571.9 540.7 497.3\n492.7 466.0 428.9\nGa 2 O 3 4 3 1 3 3 4 . . 6 5 Ga 2 O 3 3 31 9 6 1 . . 7 4 Ga 2 O 3 3 2 6 9 0 1 . . 4 9\n255.4 242.0 223.4\nDBC 176.2 DBC 167.3 DBC 155.0\n97.1 92.7 86.5\n18.0 18.0 18.0\nTemp. (oC) Temp. (oC) Temp. (oC)\n701.9 609.2 509.1\n616.4 535.3 447.7\n530.9 461.4 386.3\nSiC 445.4 SiC 387.5 SiC 324.9\n359.9 313.6 263.5\n274.5 239.7 202.1\nDBC 190.0 DBC 165.8 DBC 140.8\n103.5 91.9 79.4\n18.0 18.0 18.0\n610 us 4.6 ms 10 ms\nTemp. (oC) Temp. (oC) Temp. (oC)\n538.9 507.5 483.1\n473.7 446.3 425.0\n408.6 385.1 366.8\nGa 2 O 3 3 2 4 7 3 8 . . 5 4 Ga 2 O 3 3 2 2 6 3 2 . . 9 7 Ga 2 O 3 3 2 0 5 8 0 . . 7 5\n213.3 201.6 192.4\nDBC 148.2 DBC 140.3 DBC 134.3\n83.1 79.1 76.1\n18.0 18.0 18.0\nTemp. (oC) Temp. (oC) Temp. (oC)\n409.2 340.3 292.3\n360.3 299.9 258.0\n311.4 259.7 223.8\nSiC 262.5 SiC 219.4 SiC 189.5\n213.6 179.1 155.2\n164.7 138.9 120.9\nDBC 115.8 DBC 98.6 DBC 86.6\n66.9 58.2 52.3\n18.0 18.0 18.0\nFig.R11. Simulated temperature distribution in the Ga O sub-module and the hypothetical SiC submodule\n2 3\nin the surge current test under different pulse widths.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the Figure S14 of the “Supplementary\nSection S14” section (Page 22) in the revised Supplementary Information.\nderivation.\nIn Fig. 3e and Fig. 3f, it is clearly shown that the Ga O module yields a better Z or maximum transient\n2 3 th\npower capacity density, respectively. However, this is not entirely fair because the SiC diode uses a TO220\npackage and has a low current rating, 19 A. It is even possible to deduce that, to better respect the maximum\npower density need in a pulse power application, it is sufficient to choose a more recent diode with a higher\ncurrent rating. So at least some additional explanations must be given.\nResponse: We thank the reviewer for the thoughtful comments regarding Fig. 3e and Fig. 3f. Our intention\nwas to compare the intrinsic transient thermal behavior of various devices on a per-area basis, which is the\nphysically meaningful metric for pulse-power maximum transient power capacity density. Moreover, from\nthe discussion in this paper, in pulsed power applications, the shorter the pulse width, the less dependence of\ndevice maximum power capacity density on packages (as the heat diffusion is limited in the pulse transient\nand does not reach the package case); instead, it has a heavier dependence on material’s inherent heat capacity\nand device’s maximum operation temperatures.\nCommercial SiC diodes typically use TO-220 packages, and higher current ratings imply proportionally\nlarger die area. We agree with the reviewer that previous TO-220-packaged SiC diode (IDH02G120C5,\nInfineon) with small die area has a relatively small current rating. For transient maximum power capacity\ndensity analysis, we normalized the maximum allowable transient power by die area, because power capacity\ndensity (W/mm2) is the relevant figure of merit for pulse-power applications.\nFollowing the reviewer’s suggestion, we select a higher-current rated commercial SiC diode\n(IDWD20G120C5, Infineon) and performed a new comparison. The selected device exhibits a high\ncontinuous forward current of I = 61 A and a non-repetitive surge forward current of I = 190 A. This\nF FSM\ndiode’s thermal resistance is essentially identical to that of our Ga O module, enabling a fair comparison,\n2 3\nbut this diode presents larger die area. As shown in Figure R12(a) and (b), The Ga O module still\n2 3\ndemonstrates significantly higher maximum transient power capacity density across the entire time constant\nwindow. Even if SiC diodes are scaled to larger die areas, their transient maximum power capacity density\nremains fundamentally limited by SiC material and device properties. We have added Fig. R12a and Fig.\nR12b in the Supplementary Information to detail these analyses on high-current rated SiC diode.\n2 3\n(IDWD20G120C5) and (b) extracted maximum transient power capacity density across various time scales.\nCorresponding change in manuscript: Yes\nLocation of Change: The Fig. R12a-b and related explanation have been incorporated into the\n“Supplementary Section S10 –Power capacity modeling” section (Page 15) in the revised Supplementary\nInformation.\nExpanded text:\n“Finally, we discuss the impact of packages and device selections on the above comparative analysis. First,\nfrom the later discussion in Supplementary Section S14, in pulsed power applications, the shorter the pulse\nwidth, the device maximum power capacity density is expected to be less dependent on packages but\ndominantly determined by material’s inherent heat capacity and device’s maximum operation temperatures.\nThus, the TO package of SiC diode and the JSC package of our Ga O diode will present relatively minimal\n2 3\ndifference for the thermal transients at short pulse duration. Second, to investigate the analysis’ dependence\non device selection, we select a higher-current rated commercial SiC diode (IDWD20G120C5, Infineon) for\na new comparison, which exhibits a high continuous forward current of I = 61 A and a non-repetitive surge\nF\nforward current of I = 190 A. This thermal resistance is nearly identical to that of our Ga O module,\nFSM 2 3\nenabling a fair comparison. As shown in Figure S10-2(a) and (b), the Ga O module still demonstrates\n2 3\nsignificantly higher maximum transient power capacity density across the entire time window. This suggests,\neven if SiC diodes are scaled to larger die areas, their transient maximum power capacity density remains\nfundamentally limited by SiC material properties.”\nComment (11): Fig. 4 | Demonstration of megawatt pulsed power switching in practical power converters.\nConcerning this figure, d) simulated time-resolved T evolution of the Ga O sub-module with high-κ\nj 2 3\ninterface, but the associate figure shows two curves. The read one (257 A) has a written label “breakdown”\nwithout any explanation. Some explanations or corrections must be given.\n20\na\n)W/K(\nZ\n1\n1\n1\n1\n1\n0\n0\n0\n1 0\n0 0\n− 1\n− 2\n− 31\n0 − 6 1 0 −\nT\n3\nim\nS iC d\nG a O2\n1 0\ne ( s )\nio\n3\n0\nd\nd\ne\nio d e\n1 0 3\nb)2mm/W(\nytisned\nyticapac\nrewop\n.xaM\n1\n1\n1\n1\n5 0\n4 0\n3 0\n2 01\n0 − 6 1 0 −\nT\n3\nim\nS\nG\ne\niC d io\na O2 3\n1 0\n( s )\nd\nd\n0\ne\nio d e\n1 0 3\nResponse: We thank the reviewer for pointing out that Fig. 4d contains two simulated curves, and that the\nlabel “breakdown” associated with the 257-A condition was not adequately explained in the original\nsubmission. We fully agree and have added explicit discussion in the main text. Fig. 4d illustrates the\nsimulated time-resolved junction-temperature evolution of our Ga O sub-module during forward conduction\n2 3\nfollowed by a forced reverse blocking transition. When the switching current increases to 257 A, the device\nundergoes the following sequence: During forward conduction (10-15 µs window), power dissipation causes\nthe junction temperature to rise rapidly, and the simulated peak junction temperature reaches over 300 oC.\nImmediately after switching to high reverse bias, at ~15 µs, the conduction is cut off and the diode is forced\nto block over 1 kV. However, at this instant the device is already near the high-temperature limit observed in\nstatic measurements (see Fig. 2d in the main text). At this instant, the combination of high T and high reverse\nj\nelectric-field stress causes irreversible failure. Thus, when the device switches into the reverse-blocking state\nat over 300 oC, it can no longer sustain the reverse blocking requirement, leading to thermal-induced\nbreakdown. After reverse blocking capability collapses, the diode effectively behaves as a short circuit,\nresulting in sudden conduction of large reverse current, further power dissipation, and continued rise in\nsimulated temperature beyond 15 µs.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 1st paragraph of the “Circuit\ndemonstration of megawatt pulsed-power switching” section (Page 8) in the revised manuscript.\nExpanded text:\n“…. When the blocking voltage degrades below the bus voltage, breakdown occurs.”\nComment (12): Fig. 5 | Surge current capability of Ga O sub-module in conduction-dominant pulsed power\n2 3\napplications.\nIn the caption, it is written, “… tested with an increased surge energy at a fixed pulse width of 3.6 μs. The\ncritical peak surge current is over 800 A.” For the top curve, it is written “device degradation”, but no\nexplanation is given. Please correct this.\nResponse: We thank the reviewer for pointing out the lack of explanation regarding the “device degradation”\nlabel in Fig. 5. We clarify that this label refers to measurable degradation of reverse-blocking capability after\na surge-current event, rather than immediate device destruction during the pulse itself. After each surge\ncurrent test, forward and reverse I-V characteristics as well as breakdown voltage was measured to examine\nany possible degradation. When the post-surge reverse-blocking capability remained unchanged, the surge\nwas deemed safe. When we observed noticeable increase in leakage current, or a measurable drop of\nbreakdown voltage, we defined this condition as device degradation. Thus, degradation refers to a post-surge\ndeterioration of device blocking performance. As shown in Fig. 5c in the main test, the Ga O device sustains\n2 3\na peak surge current of 856 A, when we further increase the current, a noticeable degradation in breakdown\nwas observed. Therefore, 856 A is determined to be the maximum acceptable surge-current level before\nnoticeable degradation occurs. Beyond this level, the device does not catastrophically fail, but its reverse-\n21\nblocking margin begins to deteriorate. The degradation mechanism is consistent with that under the high-\ntemperature pulse circuit tests that involves both on-state current conduction and off-state high-voltage\nblocking, which has been discussed in detail in the last response.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 3rd paragraph of the “Short-pulse surge\ncurrent capability” section (Page 9) in the revised manuscript.\nExpanded text:\n“Post-test static characterization confirms the device integrity until the last 856 A surge current test, after\nwhich the device exhibits a measurable deterioration in its reverse-blocking capability.”\nComment (13): Concerning the “Methods section”, it's rather confusing because the purpose of this section,\nafter the conclusion, is unclear. Probably, a section before the conclusion with a small introduction to explain\nthe purpose of the section will be clearer.\nResponse: We thank the reviewer for the suggestion regarding the placement and clarity of the “Methods”\nsection. We fully understand that the structure may appear unconventional compared to other journal formats\n(e.g., IEEE). However, we would like to clarify that the current position and formatting of the Methods\nsection strictly follow Nature Communications manuscript preparation guidelines. This structure is required\nfor Nature Communications articles and adheres to the format recommended in their official author\ninstruction. The major purpose of placing Methods after the main sections in Nature-series papers is to present\nthe major results precisely in the main sections, which could be of interest to readers in a broad community,\nwhile leaving the technical details in the Methods and Supplementary Information to inform readers in a\nnarrower and more specific field.\nCorresponding change in manuscript: No\nComment (14): The conclusion is very positive for the performance of Ga O modules for “pulsed power\n2 3\nswitching at 1000 A, 1000 V”. However, an analysis of the road map to industrial products should be very\ninteresting for most readers. For instance in [2] it is written (by some of the same authors), “We envision the\nfollowing immediate research gaps that need to be addressed for advancing Ga O into industrial power\n2 3\nelectronics applications”.\nProbably, a similar analysis of pulse power applications will be very useful.\n[2] QIN, Yuan, WANG, Zhengpeng, SASAKI, Kohei, et al. Recent progress of Ga O power technology:\n2 3\nlarge-area devices, packaging and applications. Japanese Journal of Applied Physics, 2023, vol. 62, no SF,\np. SF0801.\nResponse: We thank the reviewer for encouraging a forward-looking discussion on the industrial roadmap\nof Ga O devices for pulsed-power applications. The demonstrated 1000 A / 1000 V pulsed-power switching\n2 3\nperformance highlights the intrinsic advantages of Ga O for ultra-high-power-density, short-duty-cycle\n2 3\noperations and reaches a power regime directly relevant to practical pulsed-power systems, indicating clear\n22\npotential for near-term industrial adoption. To further accelerate this transition, continued scaling of power\ncapacity is highly desirable. At present, power devices operating at multi-kiloamp and multi-kilovolt levels\nare predominantly based on Si bipolar technologies (e.g., IGBTs, IGCTs, and thyristors), which inherently\nsuffer from slow switching speeds and large reverse-recovery losses. The availability of a fast-switching,\ncompact UWBG module at comparable power levels would therefore offer a compelling performance\nadvantage.\nTo enable such power scaling in Ga O devices and modules, advances in current rating, voltage rating,\n2 3\nand operating temperature are required. From a material perspective, this necessitates improved wafer\nuniformity with reduced defect densities to support larger die areas and higher per-die current, as well as\nthicker, low-doped epitaxial layers to sustain higher blocking voltages. At the device and module levels,\nfurther optimization of heterogeneous interfaces in both devices and packaging will be essential to enable\nreliable high-voltage operation under the combined high temperature and electric-field conditions. Following\nthese considerations, we have added a corresponding forward-looking paragraph to the Conclusion of the\nrevised manuscript.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the “Conclusions” section (Page 11) in the\nrevised manuscript.\nExpanded text:\n“Looking forward, further upscaling of Ga O devices and modules toward higher power capacity will require\n2 3\nconcurrent advances in current and voltage ratings, as well as high-voltage reliability at temperatures beyond\nthe 250 oC demonstrated here. From a material perspective, this calls for the development of larger-diameter\nGa O wafers with improved uniformity and reduced defect density, together with thicker and low-doped\n2 3\nepitaxial layers to support higher voltages. At the device and module levels, continued optimization of edge\nterminations and heterogeneous interfaces in both devices and packaging will be essential to alleviate\ndegradation mechanisms that are accelerated by the combined effects of high electric field and elevated\ntemperature. Beyond diode demonstrations, the realization of Ga O transistors that leverage the device-\n2 3\npackage co-design principles identified in this work will be critical for enabling fully integrated, all-Ga O\n2 3\npulsed-power systems.”\nComment (15): Conclusion: the paper needs major revisions.\nResponse: We thank the reviewer for the overall evaluation. We have carefully revised the manuscript\naccording to all comments, we believe the revised version has been significantly improved.\n23\n2. Reply to the 2nd reviewer’s comments\nReviewer #2 (Remarks to the Author):\nThe proposed methodology is novel and well-executed, integrating device-level dielectric engineering with\npackaging-level electrothermal co-optimization. The incorporation of a high-k BaTiO interface for field\n3\nflattening, combined with junction-side cooling and optimized die attach design, effectively address high\nelectric field and thermal management challenges. The authors also demonstrate a deep understanding of\nGa O ’s intrinsic properties, particularly its high volumetric heat capacity and superior high temperature\n2 3\nstability, and skillfully design both the device and packaging to exploit these advantages for the high-pulse\npower applications. The module level results are encouraging and support the technical soundness of the\nconcept. Overall, this thoughtful UWBG co-design represents a promising step toward the practical\ndeployment of Ga O based modules, particularly for high pulse energy use.\n2 3\nResponse: We sincerely thank the reviewer for the positive and encouraging comments. We are glad that the\nmethodology and experimental results are well recognized, and we appreciate the reviewer’s\nacknowledgment of our approach and findings. Thank you for the supportive feedback.\nComment (1): It would be beneficial to add some comments on the dipole properties of BTO and why this\nmaterial is the superior choice to others that may also possess such properties. I.e, why BTO?\nResponse: We thank the reviewer for the suggestion and have revised the manuscript accordingly. Our\nmotivation for selecting BTO is primarily rooted in its high dielectric permittivity and the resulting electric‐\nfield modulation functionality under reverse bias. When the Ga O drift region becomes depleted, fixed\n2 3\npositive charge exists in the depletion region. Owing to the large permittivity contrast between BTO and\nGa O , the external electric field induces a polarization gradient inside the BTO layer, creating net negative\n2 3\nbound polarization charge at the BTO/Ga O interface and a corresponding positive charge beneath the\n2 3\nmetal/BTO interface. As shown in Fig. R13, the negative bound charge effectively compensates the positive\ncharge in the depletion region, reducing the local electric‐field peak and flattening the field distribution. This\npermittivity‐induced charge balancing is similar to conventional superjunction compensation, where equal\npositive and negative charges flatten the electric field and decouple breakdown voltage from sheet charge\ndensity.\nIn theory, this polarization superjunction functionality will hold for all high-permittivity dielectrics.\nHere, BTO is selected not only for its high permittivity (measured to be 155 from our C-V characterization,\nas shown in Supplementary Information S3), but also for its fabrication simplicity, low leakage current, and\nproven compatibility with Ga O to form high-quality heterojunctions23,24. In addition, BTO has been\n2 3\nsuccessfully applied in both Ga O and GaN based power devices, demonstrating superior capability in\n2 3\nimproving surface electric-field distribution and enhancing breakdown voltage25-27. Therefore, BTO\nrepresents an optimal dielectric choice for this work.\nmetal/BaTiO /Ga O structure\n3 2 3\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 3rd paragraph of the “Device-package\nelectrothermal co-optimization” section (Page 6) in the revised manuscript.\nExpanded text:\n“As illustrated in Fig. 1f, owing to the large permittivity contrast between BTO and Ga O , the external\n2 3\nelectric field induces a polarization gradient inside the BTO layer, creating net negative bound polarization\ncharge at the BTO/Ga O interface and a corresponding positive charge beneath the metal/BTO interface64,65.\n2 3\nThis polarization dipole can shield the electric field produced by charges in the metal and enable a nearly-\nzero net charge to flatten the crowded electric field – similar to the legacy superjunction design in\nmultidimensional power devices66.”\nReference:\n[23] S. Roy, A. Bhattacharyya, P. Ranga, H. Splawn, J. Leach and S. Krishnamoorthy, \"High-k Oxide Field-\nPlated Vertical (001) β-Ga O Schottky Barrier Diodes With Baliga’s Figure of Merit Over 1 GW/cm2,\" in\n2 3\nIEEE Electron Device Letters, vol. 42, no. 8, pp. 1140-1143, Aug. 2021, doi: 10.1109/LED.2021.3089945.\n[24] Xia, Z. et al. Metal/BaTiO /β-Ga O dielectric heterojunction diode with 5.7 MV/cm breakdown field.\n3 2 3\nApplied Physics Letters 115 (2019).\n[25] Roy, S., Bhattacharyya, A., Peterson, C. & Krishnamoorthy, S. β-Ga O lateral high-permittivity\n2 3\ndielectric superjunction Schottky barrier diode with 1.34 GW/cm2 power figure of merit. IEEE Electron\nDevice Lett. 43, 2037-2040 (2022).\n[26] Kyle J. Liddy, Weisong Wang, Stefan Nikodemski, Chris Chae, Kevin D. Leedy, Jean-Pierre Bega, Nolan\nS. Hendricks, Elizabeth A. Sowers, Ahmad E. Islam, Jinwoo Hwang, Siddharth Rajan, Andrew J. Green;\nUltra-high permittivity BaTiO (ε = 230) on Al O /AlGaN/GaN MISHEMTs for field-management in high-\n3 2 3\nvoltage RF applications. APL Electronic Devices 1 March 2025; 1 (1): 016112.\n[27] Mohammad Wahidur Rahman, Nidhin Kurian Kalarickal, Hyunsoo Lee, Towhidur Razzak, Siddharth\nRajan; Integration of high permittivity BaTiO with AlGaN/GaN for near-theoretical breakdown field kV-\n3\nclass transistors. Appl. Phys. Lett. 8 November 2021; 119 (19): 193501.\nG\ne d A\nB T\na O\n2\ng\nO\n3\n-+-+ -+-+\nP o\n-+-+\nla\n-+-+\nr iz a\n-+-+\ntio\n-+-+\nn e\n-+-+\nffe\n-+-+\nc\n-+-+\nt\n-+-+ -+-+\nE xE te r\n- fie\nn a\nld\nl\nComment (2): Will the high-k BaTiO interface layer functionally replace the conventional SiO /SiN surface\n3 2 4\npassivation on chips, or is it intended to be added on top of the conventional passivation to act as an additional\nfield-modulation layer? If it is a replacement, please comment on its insulating reliability and long-term\nstability? How will it stand up to humidity, a known issue with BaTiO ? I.e., will the field dampening\n3\nproperties be sacrificed? If so, by how much?\nGiven the CTE mismatch between BaTiO and Ga O , how robust is the interface during repeated thermal\n3 2 3\ncycling and high-field pulsed operation? Please comment on potential interfacial defects, charge\ntrapping/polarization drift, breakdown-voltage stability, and any signs of delamination or micro-cracking.\nResponse: We sincerely thank the reviewer for this insightful and constructive comment. In the present work,\nthe BaTiO layer is not intended to replace the conventional chip-level surface passivation (e.g., SiO /SiN ).\n3 2 x\nInstead, it acts as an additional high-k field-modulation/interface layer inside the junction-side cooling (JSC)\nstack that interfaces between the chip surface (i.e., passivation layer) and die attach metals (e.g., sintered Ag).\nThe reviewer is correct that humidity sensitivity is a known issue for exposed BTO material. In our package\nand module, the external package surface is further protected by the module encapsulation (housing and\nsilicone gel), so the BTO is not directly exposed to the ambient environment. Silicone gel is injected to form\na continuous dielectric barrier covering the device surface and sidewalls. The gel is then vacuum-degassed\nto eliminate air bubbles and voids, which are known to act as local moisture traps and accelerate dielectric\ndegradation. After degassing, the encapsulant is thermally baked to remove residual moisture content,\nensuring that the internal cavity remains dry. As a result, BTO is not subjected to open-environment humidity\nexposure, alleviating one of the main degradation concerns typically associated with perovskite-based\ndielectrics.\nIn addition, the BTO layer is deposited as a thin sputtered film in this work, rather than as a bulk ceramic.\nThin-film BTO exhibits significantly lower internal porosity, reduced grain-boundary conduction pathways,\nand reduced ionic migration compared to bulk sintered BaTiO used in MLCCs, which partially mitigates\n3\nhumidity- and defect-induced failure modes that are widely reported in ceramic capacitors.\nTable I. The list of key material CTE.\nWe also appreciate the reviewer brings up the possible concern about the coefficient of thermal\nexpansion (CTE) mismatch between BaTiO and Ga O . Table I summarizes the CTE of Ga O , SiO ,\n3 2 3 2 3 2\nBaTiO , and sintered Ag. Owing to the large CTE mismatch among Ga O , SiO , and sintered Ag, the\n3 2 3 2\n2 3 2\nIn contrast, replacing SiO with BaTiO improves the CTE match in the Ga O /BaTiO /Ag stack, thereby\n2 3 2 3 3\nmitigating edge-induced stress concentration. This trend is confirmed by thermo-mechanical simulations in\nANSYS. Fig. R14 shows the equivalent (von Mises) stress in the sintered-Ag layer for the two submodules\n(sub-module A with SiO interface, sub-module C with BaTiO interface) under identical boundary\n2 3\nconditions (convection coefficient of 1000 W·m-2·K-1 and 20 W power loss). The Ag edge stress in sub-\nmodule A reaches ~17 MPa, whereas it is reduced to ~12.5 MPa in sub-module C, evidencing the benefit of\nthe better CTE matching provided by BaTiO .\nSiO interface and (b) sub-module C with BaTiO interface.\n2 3\nTo evaluate long-term reliability under realistic thermal-electrical stress conditions, we performed a\nswitching-based power cycling test, which is one of the widest used methods for industrial module\nqualification28. Fig. R15a and Fig. R15b show the schematic and photo of switching-based power cycling\ncircuit. Initially, S1 and S3 are turned on, generating a high current within the rating range of the DUT. This\ncurrent flows through the loop formed by S1, S3, L, and the DUT. Next, S1 is turned off and S2 is turned on,\nforcing the current to freewheel through the loop consisting of S2, L, and the DUT. During this process, the\nfreewheeling time is relatively long, gradually heating the DUT. By repeating this cycle, the DUT can be\ngradually heated to the target temperature within 60 seconds. The diode is then switched off, allowing it to\ncool down to room temperature. This heating-cooling cycle is repeated to achieve power cycling. Fig. R15c\npresents the injected power profile applied to device and case temperature profile. In the subsequent 120-s\ncooling period, a forced-air convection is applied to rapidly dissipate accumulated heat. Case temperature\nevolution is continuously monitored using an infrared thermal-imaging camera, and the peak case\ntemperature reaches ~100 oC.\ndevice and case temperature profile. (d) Illustration of dynamic I-V reconstruction from the switching current\nand voltage waveforms recorded in each switching cycle. (e) Extracted V during power cycling test for sub-\nF\nmodule A with SiO interface and sub-module C with BTO interface.\nexcitation conditions and reconstruct a dynamic I-V curve by extracting a series of (I, V) points, each taken\nat the same time instant (Fig. R15d). From the re-constructed dynamic I-V characteristics, the forward-voltage\ndrop (V ) is extracted at a fixed current of 5 A. Fig. R15e shows that sub-module C exhibits minimal V shift\nF F\nover ~10,000 power-cycling cycles, indicating stable conduction characteristics. In addition, and we did not\n28\n(\n(\n(\na\nV\nD\nc\nrewoP\n)Co(\nT\nd\n)\nC\n)\nC\n)C\nV\nu\no\nS 1\nC\nD C\nS 2\nH e a tin g\nP o w e r o n\n…\nt = 6 0 s\no n\nr r e n t w a v e fo r\nlta g e w a v e fo\nm\nr m\nL D U T\nS h u n t\nS 3\nG N D\nC o o lin g\nP o w e r o\nM e a s u r e\np o in\nt = 1 2 0\no ff\nI- V R\n6\n)A\n4 (\ntnerr\n2 uC\n0\n0\nff\nm e\nt\ns\ne c o\n( b )\nT o V\nD C\nH e a\nP o w\n…\nn t\nt = 6\no n\nn s tr u c tio n\n2 3\nlt a g e ( V )\ntin g\ne r o\n0 s\nS h u\nn\n(\ne\n4\n3\n3 )V(\nF\nV 3\n3\n3\nn t\n).0\n.8\n.6\n.4\n.2\n.0\nS 1\nS 2 3\nC o o lin g\nP o w e r o ff\nM e a s u r e m e\np o in t\nt = 1 2 0 s\no ff\nS u b -m\nS u b -m\n2 5 0 0 5 0 0 0\nC y c le n u m\nn\no\no\n7\nb\nt\nd u\nd u\n5 0\ne r\nle\nle\nT im\nA\nC\n1 0 0 0\ne\ne\n0\nobserve measurable degradation in reverse blocking capability. In contrast, sub-module A exhibits serious\nV degradation after ~1,200 cycles, suggesting the possible formation of delamination, crack, and voids in\nF\nthe package interface. This contrast proves that submodule C with BTO interface demonstrates the high\nstructural and electrical robustness under dynamic switching stress.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the last paragraph of the “Short-pulse surge\ncurrent capability and Power cycling test” section (Page 10) in the revised manuscript; a new section\n“Supplementary Section S15-Material CTE and power cycling test” is added to the Supplementary\nInformation (Page 24).\nExpanded text in the manuscript:\n“Finally, we evaluate the reliability of the prototyped submodules. The BaTiO layer is fully encapsulated by\n3\nsilicone gel, forming a continuous dielectric barrier that suppresses humidity-induced degradation commonly\nobserved in bulk BaTiO ceramics76. In addition, the BaTiO interface is found to improve thermo-\n3 3\nmechanical reliability. Table S3 in Supplementary Section S16 summarizes the CTE of relevant materials.\nDue to the large CTE mismatch, conventional Ga O /SiO /Sintered Ag stacks experience elevated thermo-\n2 3 2\nmechanical stress near die edges. Replacing SiO with BaTiO significantly improves CTE matching. To\n2 3\nvalidate this, we perform a switching-based power-cycling test, the widely-used method for qualifying power\nmodule reliability77. As detailed in Supplementary Section S16, the sub-module C exhibits minimal\nparametric shift after 10,000 power-cycling cycles, whereas sub-module A exhibits pronounced forward\nvoltage degradation after ~1,200 cycles.”\nReference:\n[28] Y. Zhang et al., \"Power Cycling Testing for Power Semiconductor Switches: Methods, Standards,\nLimitations, and Outlooks,\" in IEEE Transactions on Power Electronics, vol. 41, no. 1, pp. 849-869, Jan.\n2026, doi: 10.1109/TPEL.2025.3595180.\nComment (3): BaTiO is deposited by RF magnetron sputtering in an Ar/O ambient. How compatible is\n3 2\nthis process with large-area fabrication and downstream metallization/packaging?\nResponse: We thank the reviewer for this question. The BaTiO layer used in this work is deposited by RF\n3\nmagnetron sputtering in Ar/O ambient, which is a well-established technique for large-area dielectric thin-\n2\nfilm fabrication. The scalability primarily depends on the sputtering chamber configuration, including target\ndiameter and substrate carrier size, rather than the material itself. Commercial sputtering systems already\nsupport 4-inch to 8-inch wafers using large-size targets. Therefore, extending BaTiO deposition to large-\n3\narea substrates is not a constraint. The process operates at relatively low substrate temperature, thus\nmaintaining full compatibility with downstream metallization and packaging flows. In our experiments, the\nsputtered BaTiO exhibited stable adhesion to subsequent metal deposition, as well as strong bonding to the\n3\n29\nsintered Ag layer in the module assembly, without additional surface treatment. Therefore, the deposition\nprocess is compatible with large-area fabrication and does not impose limitations on subsequent process\nintegration.\nCorresponding change in manuscript: No\nComment (4): Can the high-k interface be extended to other WBG/UWBG devices (e.g., SiC, GaN, diamond)?\nIf so, please outline material-specific adaptations, interface reliability under cycling, CTE matching, and\nprocess compatibility.\nResponse: We thank the reviewer for the insightful question. Yes, the high-k BaTiO interface concept can\n3\nbe extended to other WBG/UWBG platforms, including SiC, GaN, and diamond, although material-specific\nadaptations will be required. In terms of process compatibility, RF magnetron sputtering of BaTiO is a\n3\nwidely used and scalable thin-film approach. The deposition process can be directly adapted to SiC and GaN\nwafers, and thin-film perovskites have already been demonstrated on this semiconductor platforms 29-32. The\nscalability mainly depends on chamber configuration, rather than on material limitations. However, the film\nmorphology and interfacial trap density may vary depending on the underlying substrate surface quality,\nwhich requires careful investigations. For thermal-mechanical robustness, CTE matching becomes material-\ndependent. For GaN, the mismatch relative to BaTiO is moderate, so thin-film BaTiO can be directly\n3 3\nintegrated without introducing considerable strain. For SiC and diamond, however, the CTE difference is\nsignificantly larger. Thus, BaTiO would likely require thickness optimization, compliant transition layers,\n3\nor stress-relaxation interlayers to avoid interfacial cracking under repetitive thermal cycling. Therefore, the\nhigh-k field-modulation concept is broadly transferrable to other WBG/UWBG systems, but film thickness,\ninterface preparation, CTE matching strategy, and long-term reliability assessment will need to be tailored to\neach material system.\nCorresponding change in manuscript: No\nReferences:\n[29] Kyle J. Liddy, Weisong Wang, Stefan Nikodemski, Chris Chae, Kevin D. Leedy, Jean-Pierre Bega, Nolan\nS. Hendricks, Elizabeth A. Sowers, Ahmad E. Islam, Jinwoo Hwang, Siddharth Rajan, Andrew J. Green;\nUltra-high permittivity BaTiO (ε = 230) on Al O /AlGaN/GaN MISHEMTs for field-management in high-\n3 2 3\nvoltage RF applications. APL Electronic Devices 1 March 2025; 1 (1): 016112.\n[30] Mohammad Wahidur Rahman, Nidhin Kurian Kalarickal, Hyunsoo Lee, Towhidur Razzak, Siddharth\nRajan; Integration of high permittivity BaTiO with AlGaN/GaN for near-theoretical breakdown field kV-\n3\nclass transistors. Appl. Phys. Lett. 8 November 2021; 119 (19): 193501.\n[31] Choi, JS., Lee, HW., Lee, TH. et al. Effects of post-deposition annealing on BaTiO /4H-SiC MOS\n3\ncapacitors using aerosol deposition method. Appl. Phys. A 130, 188 (2024).\n[32] Thirumaleshwara N Bhat et al. Polarization-induced interfacial coupling modulations in BaTiO /GaN\n3\nheterojunction devices. 2017 J. Phys. D: Appl. Phys. 50 275101.\n30\n3. Reply to the 3rd reviewer’s comments\nReviewer #3 (Remarks to the Author):\nI co-reviewed this manuscript with one of the reviewers who provided the listed reports. This is part of the\nNature Communications initiative to facilitate training in peer review and to provide appropriate recognition\nfor Early Career Researchers who co-review manuscripts.\nResponse: We sincerely thank the reviewer and appreciate the effort contributed to this review. We also\nacknowledge and value the participation of Early Career Researchers in the evaluation process. Their\nconstructive comments and feedback have helped us significantly improve the manuscript. Thank you again\nfor your time and support.\n31\n4. Reply to the 4th reviewer’s comments\nReviewer #4 (Remarks to the Author):\nThis is an excellent manuscript highlighting the performance of Ga O UWBG power semiconductor devices,\n2 3\nespecially for pulsed power applications. The authors provided a comprehensive literature review, indicating\nthe uniques challenges and how Ga O can offer potential solutions. The emphasis on the electro-thermal co-\n2 3\ndesign approach is a new trend for all future power electronic systems. The experimental demonstration of\nthe Mega Watt pulse power is also impressive, completed with device simulation, packaging design, electrical\nand thermal considerations. I truly enjoy reading this paper.\nResponse: We sincerely thank the reviewer for the very positive and encouraging comments. We are glad\nthat the co-design approach, experimental demonstrations, and technical contributions were well recognized.\nYour supportive feedback is greatly appreciated and has motivated us to further refine and strengthen the\nwork. Thank you again for your thoughtful review.\nComment (1): Perhaps one comment that may be help further improve this paper is to discuss how the\nrepetition rate (or duty cycle) have on the thermal capacity of the proposed power module. Will the proposed\npulse power application require any thermal exchanger to further improve the performance?\nResponse: We appreciate the reviewer’s insightful comment. The repetition rate (or duty cycle) directly\ndetermines the average power dissipation of the module. For a given pulse energy, increasing the repetition\nrate increases the average heat load. To evaluate the impact of repetition rate (or duty cycle), we performed\ntransient electro-thermal simulations using ANSYS, in which the Ga O power sub-module is mounted on a\n2 3\nbackside heat sink and cooled by forced air (fan cooling), as shown in Fig. R16.\nFigure R16. Ansys simulation setup of Ga O power submodule with a backside heatsink and cooling fan.\n2 3\nTo explicitly study the repetition-rate effect, the applied power dissipation was modeled as a square-\nwave pulse, with a peak power of 10 kW and pulse width of 5 µs. Two repetition rates were considered:\n1\nkHz (duty cycle = 1/200) and 5 kHz (duty cycle = 1/40). The simulation setup schematic is shown in Fig.\nR17a. The corresponding transient junction-temperature (T) responses are compared in Fig. R17b. Owing to\nj\nthe large simulation data volume, only the first 5 ms of junction-temperature evolution is presented.\nincreases, and the peak transient temperature rise is governed by the thermal capacitance of the device and\npackage. When the repetition rate increases to 5 kHz, heat accumulation becomes pronounced because the\ngenerated heat cannot be fully dissipated between pulses. As a result, an elevated junction temperature\ndevelops in addition to the repetitive transient temperature peaks. While the transient peaks are still\ndetermined by the thermal capacitance of the device and package, the average junction temperature rise is\nstrongly influenced by long-timescale heat removal, including junction-side cooling and the thermal\nconductivity of the packaging materials in our sub-module structure.\nFigure R17. (a) Simulation setup schematic of applied power dissipation at different repetition rate. (b)\nTransient junction-temperature responses.\nThis average junction temperature rise can be effectively suppressed by more efficient external cooling.\nAs shown in Fig. R18, under conventional forced-air cooling, a steady-state junction temperature of 44.8 °C\nis obtained under an average power of 5 W; whereas increasing the repetition rate leads to an average power\nof 25 W, resulting in a much higher steady-state junction temperature of 140.6 °C. By enhancing the thermal\nexchanger (e.g., stronger forced-air cooling), the steady-state junction temperature can be reduced to 111.3 °C.\nFurther reduction is achievable by adopting more advanced cooling schemes, such as liquid cooling.\nOverall, the simulations indicate the important impact of duty cycle on the thermal performance of the\nGa O module. For low duty cycles, thermal exchangers and external cooling play a relatively minor role,\n2 3\n33\n( a\n( b\n)Co(\nT\n)\n)\nj\nrewoP\n2\n1\n1\n1\n1\n1\n1 0 k\nt = 5\no n\n0 0\n8 0\n6 0\n4 0\n2 0\n0 0\n8 0\n6 0\n4 0\n2 0\n00\n.0\nW\nμ\n0\ns\n0\nf=f= 15 t k H z , =\no ff\nt k H z , =\no ff\n1 k H z\n5 k H z\n0 .0 0 1\n91 99\n0\n5 μ s\n5 μ s\n.0 0\nT\n;;\n2\nim e (\n0\ns\n.0\n)\n0 3 0 .0 0 4 0 .0\n…\nT\n0\nim\n5\ne\nand the power capacity is mainly determined by the intrinsic properties of the device and module. For higher\nduty cycle pulsed applications (and even approaching the conventional power switching applications),\nthermal exchangers and external cooling become increasingly important and can become new limitations for\nthe power capacity; To fully exploit the intrinsically high power capability of the Ga O module,\n2 3\nadvanced thermal exchanger designs and enhanced cooling strategies are therefore required in this scenario.\nFigure R18. Transient time-resolved T simulation at various power and cooling conditions.\nj\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 5th paragraph of the “Circuit\ndemonstration of megawatt pulsed-power switching” section (Page 10) in the revised manuscript. In\naddition, a new section “Supplementary Section S15-Transient junction-temperature simulation under\nvarying duty cycles” has been added to the Supplementary Information (Page 23).\nExpanded text in the manuscript:\n“A similar consideration is also relevant for repetitive switching under varying duty cycles, or equivalently,\ndifferent repetition rates. As shown in the analysis in Supplementary Section S15, at relatively high duty\ncycles or repetition rates, an average junction temperature rise develops in addition to the transient pulsed\ntemperature peaks when the generated heat cannot be fully removed between pulses. This average junction\ntemperature rise can be suppressed through improved external cooling. In this scenario, advanced external\ncooling is required to fully exploit the module’s intrinsic power capacity.”\n34\n5. Reply to the 5th reviewer’s comments\nReviewer #5 (Remarks to the Author):\nThe paper demonstrates the first ultra-wide bandgap (UWBG) power module, which enhances the power\ncapacity of UWBG devices by over three orders of magnitude and identifies pulsed power electronics as a\nnovel application for Ga O power devices. Considering the rapidly growing interest in UWBG power\n2 3\nelectronics and huge industrial investment in this domain, such a performance breakthrough is expected to\nhave significant impact. This work also presents fundamental understanding by providing a high-κ device-\npackage interface and highlighting the significance of heat capacity as a critical material attribute for pulsed\npower electronics, suitable to various different semiconductors. This work could attract widespread attention\nfrom this perspective. The manuscript is clear, well written and well structured. The data are comprehensive,\ncovering device, packaging, and circuit-level verification, supported by theoretical analysis. To further\nimprove the paper, the following technical points should be clarified:\nResponse: We sincerely thank the reviewer for the positive and encouraging comments and for recognizing\nthe significance, impact, and clarity of this work.\nComment (1): For experimental circuit tests, is it possible to measure the power module under higher slew\nrate and switching frequency? The authors are also suggested to comment on the limiting factors for slew\nrate and frequency in this circuit test.\nResponse: We thank the reviewer for this insightful comment. The experimental circuit in this work is\ndesigned to emulate many typical pulsed-power switching applications that emphasize on delivering high\npeak current and high transient power within microsecond-scale pulses with a relatively small duty cycle.\nSuch operating conditions are representative of a wide range of pulse-power systems. For example, in the\nMarx pulse generator for high-power pulse applications, the pulse widths range from 50 to 1000 ns with\nsmall duty cycle less than 1/100 33.\nIn the present experiment measurements, the minimum achievable pulse width is 2.5 µs, and a peak\ncurrent slew rate (di/dt) of approximately 1.6 kA/µs is obtained. The achievable slew rate and pulse width in\nthe experimental setup are primarily limited by the parasitic capacitance and inductance of the test circuit, as\nwell as the switching speed of the SiC MOSFETs used to drive the module. The circuit was carefully\noptimized to minimize parasitics, and the achieved operating conditions already push the practical limits of\nthe current test platform.\nRegarding switching frequency, as discussed in the Response of Reviewer #4, in repetitive switching,\nswitching frequency can impact the module’s thermal performance. From the analysis in Supplementary\nSection S15, while the power capacity under short pulse widths and small duty cycles is mainly determined\nby the module’s intrinsic properties, at relatively high duty cycles or frequencies, an average junction\ntemperature rise develops in addition to the transient pulsed temperature peaks when the generated heat\ncannot be fully removed between pulses. This average junction temperature rise can be suppressed through\n35\nimproved external cooling. In this scenario, advanced external cooling is therefore required to fully exploit\nthe module’s intrinsic power capacity.\nWe also understand that high dv/dt slew rate is also required in many other pulsed-power applications,\nsuch as nuclear and fusion systems, high-power particle accelerators, pulsed X-ray sources, and\nelectromagnetic launchers. In these applications, pulse-forming networks, Marx generators, and fast solid-\nstate switches generate sub-microsecond voltage transitions, leading to high dv/dt over 10 V/ns34,35. At present,\nwe do not observe any fundamental limitation that would prevent our module from operating under such high\ndv/dt slew rates. From a thermal perspective, this regime closely resembles a short-pulse operation, in which\nthe temperature rise is dominated by thermal capacitance. Consequently, the Ga₂O₃ submodule is expected\nto sustain an even higher power capacity under these conditions. This expectation is further supported by the\nresults in Fig. 5 of the manuscript, where the surge-current capability—and the corresponding power capacity\nassuming a fixed switching voltage—increases with decreasing pulse width. Experimental validation at such\nhigh dv/dt requires specialized test platforms that are currently unavailable to our group and will be pursued\nin future work through collaborations with researchers in plasma and nuclear sciences.\nCorresponding change in manuscript: No\nReferences:\n[33] C. Yao et al., \"Parallel SiC MOSFETs Marx Pulse Generator Based on Magnetic Induction Current\nBalance,\" in IEEE Transactions on Plasma Science, vol. 52, no. 9, pp. 4250-4259, Sept. 2024, doi:\n10.1109/TPS.2024.3369047.\n[34] K. Wen, L. Liang, Z. Zhang and X. Yan, \"High Power and High Repetition Frequency Nanosecond\nMarx Generator Based on Avalanche Transistor With Triggering Acceleration Circuit,\" in IEEE Transactions\non Power Electronics, vol. 40, no. 6, pp. 8153-8167, June 2025, doi: 10.1109/TPEL.2025.3534802.\n[35] M. -K. Nguyen, F. Zare and N. Ghasemi, \"Switched-Capacitor-Based Nanosecond Pulse Generator\nUsing SiC MOSFET,\" 2018 Australasian Universities Power Engineering Conference (AUPEC), Auckland,\nNew Zealand, 2018, pp. 1-6, doi: 10.1109/AUPEC.2018.8757883.\nComment (2): Ga O devices are known to be promising for high-voltage applications, with devices up to\n2 3\n10,000 V having been experimentally reported. Does the superior power capacity of Ga O retain for higher-\n2 3\nvoltage devices? The authors may add supplemental simulations.\nResponse: We thank the reviewer for this insightful comment. Recently, Ga O devices have demonstrated\n2 3\nblocking voltages approaching 10 kV, particularly using lateral device architectures. At the current stage of\nepitaxial growth capability, Ga O cannot yet reliably realize thick (>50-80 µm) drift layers with sufficiently\n2 3\nlow doping (typically <5×1015 cm-3). Therefore, experimental validation of true vertical Ga O devices at 10\n2 3\nkV rating remains very limited. In response to the reviewer’s suggestion, we preformed electrical simulations\nof vertical Ga O device at 10 kV by scaling drift thickness (50 μm) and doping concentration (2×1015 cm-3),\n2 3\nthe device edge termination is the same as that in this manuscript. As shown in Fig. R19, at 10 kV, the Ga O\n2 3\n36\ndevice presents a peak E-field of 6 MV/cm below BTO field plate, and the main junction region still\ndemonstrated uniform E-field distribution.\nFig. R19. Simulated two-dimensional electric field contours in NiO/Ga O heterojunction diode with thick\n2 3\ndrift layer using the same edge termination.\nIn the short-pulse regime, increasing the drift-layer thickness does not significantly alter the thermal\nresponse, because the generated heat remains locally confined and thermal diffusion is negligible. As a result,\nthe transient temperature rise is primarily governed by the intrinsic volumetric heat capacity of the material.\nA thicker drift layer introduces a larger thermal capacitance, which can also lower the transient temperature\nrise. Even under longer pulse or higher frequency conditions, owing to the junction-side cooling\nconfiguration, the majority of the heat is extracted through the package rather than through the Ga O chip\n2 3\nitself. Moreover, the additional drift-layer thickness is relatively insignificant compared with the substrate\nthickness (650 µm). Therefore, under both short- and long-pulse operations, the module’s current handling\ncapability is not expected to be significantly affected, enabling good power scalability of pulsed power\ncapacity for the present module design. The fundamental advantage of Ga O module revealed in this work\n2 3\nremains effective to higher voltage, further supporting the Ga O ’s promise for ultra-high-power pulsed\n2 3\napplications.\nCorresponding change in manuscript: No\nComment (3): Following the above point, please also analyze if the power capacity advantage over SiC\ncounterparts retains at higher voltage, as SiC modules have been demonstrated up to 10 kV.\nResponse: We thank the reviewer for this important follow-up question. Following the discussion above, we\nexpect that the power capacity advantage of Ga O modules over their SiC counterparts is retained at higher\n2 3\nvoltage ratings, including the 10 kV class. First, as clarified in our previous response, the power capacity of\nthe proposed Ga O module is not fundamentally limited by the voltage rating. Under pulsed-power operation,\n2 3\nthe temperature rise is primarily governed by the effective thermal capacitance. Therefore, increasing the\nblocking voltage does not intrinsically degrade the transient power handling capability of the Ga O module.\n2 3\n8\n6\n4\n2\nSecond, the fundamental material advantages of Ga O over SiC (namely its large volumetric heat capacity\n2 3\nand high allowable operating temperature) are largely voltage-rating agnostic. These properties are intrinsic\nto the material and remain valid for higher-voltage devices, including those rated at 10 kV. Consequently,\nthe superior transient power capacity observed in Ga O devices at lower voltages is expected to persist at\n2 3\nelevated voltage levels.\nCorresponding change in manuscript: No\nComment (4): In Fig. 1f, please clarify the physical mechanism by which the high-κ dielectric introduces\ndipole polarization charges at both the high-κ/metal and high-κ/Ga O interfaces.\n2 3\nResponse: We thank the reviewer for the suggestion and have revised the manuscript accordingly. As\ndiscussed in Response (1) of Reviewer #2, our motivation for selecting BTO is primarily rooted in its high\ndielectric permittivity and the resulting electric‐field modulation functionality under reverse bias. When the\nGa O drift region becomes depleted, fixed positive charge exists in the depletion region. Owing to the large\n2 3\npermittivity contrast between BTO and Ga O , the external electric field induces a polarization gradient\n2 3\ninside the BTO layer, creating net negative bound polarization charge at the BTO/Ga O interface and a\n2 3\ncorresponding positive charge beneath the metal/BTO interface. As shown in Fig. R20, the negative bound\ncharge effectively compensates the positive charge in the depletion region, reducing the local electric‐field\npeak and flattening the field distribution. This permittivity‐induced charge balancing is similar to\nconventional superjunction compensation, where equal positive and negative charges flatten the electric field\nand decouple breakdown voltage from sheet charge density.\nIn theory, this polarization superjunction functionality will hold for all high-permittivity dielectrics.\nHere, BTO is selected not only for its high permittivity (measured to be 155 from our C-V characterization,\nas shown in Supplementary Information S3), but also for its fabrication simplicity, low leakage current, and\nproven compatibility with Ga O to form high-quality heterojunctions. In addition, BTO has been successfully\n2 3\napplied in both Ga O and GaN based power devices, demonstrating superior capability in improving surface\n2 3\nelectric-field distribution and enhancing breakdown voltage. Therefore, BTO represents an optimal dielectric\nchoice for this work.\nExternal\nPolarization effect\nE-field\nSintered Ag\n- - - - - - - - - - -\n+ + + + + + + + + + +\nBTO\n- - - - - - - - - - -\n+ + + + + + + + + + +\nGa O\n2 3\nFig. R20. Illustration of the polarization dipoles introduced by the high-κ dielectrics in the\nmetal/BaTiO /Ga O structure\n3 2 3\nCorresponding change in manuscript: Yes\nelectrothermal co-optimization” section (Page 6) in the revised manuscript.\nExpanded text:\n“As illustrated in Fig. 1f, owing to the large permittivity contrast between BTO and Ga O , the external\n2 3\nelectric field induces a polarization gradient inside the BTO layer, creating net negative bound polarization\ncharge at the BTO/Ga O interface and a corresponding positive charge beneath the metal/BTO interface64,65.\n2 3\nThis polarization dipole can shield the electric field produced by charges in the metal and enable a nearly-\nzero net charge to flatten the crowded electric field – similar to the legacy superjunction design in\nmultidimensional power devices66.”\nComment (5): In Fig. 3b, the peak temperature appears at the anode edge for submodule B, but at the device\ncenter for submodule C. Please explain the difference.\nResponse: We thank the reviewer for this important observation. The difference in peak-temperature\nlocations between sub-modules B and C arises from their distinct heat-spreading geometries and contact\nfootprints with the cooling structures. In sub-module B, a metal post is inserted on the top surface of the\nGa O chip. To prevent silver overflow during bonding, the post area is intentionally made smaller than the\n2 3\nactual anode metallization area. During pulse conduction, the majority of heat is generated beneath the full\nanode area, but only the region directly underneath the post provides efficient heat extraction. The peripheral\nportion of the anode, which is not covered by the post, must dissipate heat only through the Ga O layer,\n2 3\nresulting in slower cooling at the anode edge and the formation of a localized peak temperature.\nIn contrast, in sub-module C, the high-κ interface enables continuous silver bonding over the full anode\nfootprint. As a result, heat is extracted more uniformly from both the central and peripheral regions,\neliminating edge heating and yielding a much flatter junction temperature distribution. Quantitatively, sub-\nmodule B exhibits a local peak of ~89 oC near the edge, whereas submodule C maintains a nearly uniform\njunction temperature of ~57 oC. This confirms that the improved coverage and thermal spreading path in sub-\nmodule C effectively suppress the edge-localized hot spot observed in sub-module B.\nCorresponding change in manuscript: Yes\nLocation of Change: The revisions have been incorporated into the 2nd paragraph of the “Transient\nthermal impedance and maximum power capacity” section (Page 7) in the revised manuscript.\nRevised text:\n“These hot spots arise because the post contact area is smaller than the actual anode area, resulting in\nineffective heat extraction at the anode edge regions.”\nComment (6): Oscillations are observed in both the voltage and current waveforms in Fig. 4f and Fig. 4g\nfollowing the switching event. Please explain the origin of these oscillations. Additionally, are there any\nmethods that can be applied to mitigate this phenomenon?\nThese oscillations originate from the high-frequency resonance between parasitic inductances and\ncapacitances within the commutation loop during high-speed switching. As illustrated in the equivalent\ncircuit schematic in Fig. R21, the high-current path includes stray inductances from the PCB traces (L ,\nPCB\ntypically 1-5 nH) and the packaging inductances of the terminals (L , L , L , L , typically 1-10 nH). When\nD S A C\ncoupled with the parasitic output capacitance of the power switches (C ) and the junction capacitance of the\nDS\nGa O DUT (C ), these components form an RLC resonant tank. During the rapid switching transients\n2 3 DUT\nrequired for short-pulse generation, the high di/dt and dv/dt excite this resonant network, resulting in the\nobserved voltage and current ringing.\nTo mitigate this phenomenon, two primary strategies can be employed. The first is to minimize loop\ninductance through compact PCB layout and advanced packaging. In our design, we have implemented a\nminimum-loop PCB layout and utilized our low-inductance Ga O module packaging; however, the\n2 3\nnecessary inclusion of high-voltage, high-current commercial components (e.g., TO-247 packaged SiC\nMOSFETs) imposes a physical limit on the minimum achievable inductance. The second method is to\ndampen the oscillation by slowing down the switching speed (e.g., increasing gate resistance) to reduce di/dt.\nHowever, doing so would significantly widen the minimum pulse width beyond 5 µs. Since the primary\nobjective of this work is to characterize the transient thermal superiority of Ga O under ultra-short pulse\n2 3\nconditions, we prioritized fast switching speeds. Therefore, the waveforms presented in Fig. 4f and Fig. 4g\nin the main text represent an optimized trade-off between achieving minimal pulse widths and managing\nparasitic oscillations, with the observed ringing being characteristic of high-speed, megawatt-class dynamic\ntesting.\nFig. R21. Equivalent circuit schematic of switching legs in on-board pulsed power switching test.\nCorresponding change in manuscript: No\n3.6 µs? Furthermore, is it feasible to reduce the pulse width?\nResponse: We greatly appreciate the reviewer’s insightful comment regarding the selection of the pulse width.\nAs detailed in the circuit operation principle (Supplementary Figure S11), the duration of the current pulse\napplied to the DUT is determined by the off-time of switch S1 during Stage II. The commercial SiC\nMOSFETs used as control switches exhibit finite rise and fall times; to ensure a well-defined current pulse\nprofile rather than a transient spike, the pulse width must be sufficiently longer than these switching transition\nperiods. Furthermore, as discussed in the previous Response 6, high-speed switching induces high-frequency\nparasitic oscillations. Reducing the pulse width further risks merging the turn-on and turn-off transients,\nwhere the resulting ringing could induce false triggering or electromagnetic interference, compromising the\nsafety of the setup. Consequently, the selected pulse width represents an optimized operating point that\nbalances the requirements for short-pulse thermal characterization with the stability and safety of the high-\npower test platform developed in this work. It is important to note that further reduction of the pulse width is\ntechnically feasible by optimizing the test bed with lower-inductance PCB layouts or faster driving stages;\nhowever, the limit of the current experimental setup is imposed by the test circuit, not the Ga O module\n2 3\nitself, which has demonstrated a fast reverse recovery time of 23 ns.\nCorresponding change in manuscript: No\n41\n6. Reply to the 6th reviewer’s comments\nReviewer #6 (Remarks to the Author):\n+ What are the noteworthy results?\n- This manuscript presents a novel power module based on Ga O power devices for pulsed power\n2 3\napplications. The module under investigation promises enhanced current/voltage capability as well as careful\ntemperature management. The Authors also assembled a multi-die module allowing switching at 1kA/1kV.\n+ Will the work be of significance to the field and related fields? How does it compare to the established\nliterature? If the work is not original, please provide relevant references\n- This work is significant to the field, as the proposed sample shows unprecedented features.\n+ Does the work support the conclusions and claims, or is additional evidence needed?\n- No additional evidence is needed.\n+ Are there any flaws in the data analysis, interpretation and conclusions? Do these prohibit publication or\nrequire revision?\n+ Is the methodology sound? Does the work meet the expected standards in your field?\n- The methodologies are sound and meet the standard.\n+ Is there enough detail provided in the methods for the work to be reproduced?\n- The article as well as the supplementary material provide enough detail for the work to be reproduced.\nResponse: We sincerely thank the reviewer for the positive evaluation and encouraging remarks. We greatly\nappreciate the recognition of the novelty, experimental completeness, and methodological rigor of our work.\nWe are pleased that the reviewer finds the results significant, reproducible, and well supported by the\npresented evidence. Thank you for your constructive and supportive assessment.\n- Some minor remarks follow:\nComment (1): In fig. 1b there is a typo: \"shot\" is written but \"short\" was intended;\nResponse: Thank you for pointing out the typographical error. We have corrected “shot” to “short” in Fig.\n1b.\nComment (2): Initially, the Authors claim that the value of the thermal conductivity of the assembly materials\nis not relevant in the case of pulsed power electronics applications, whereas the heat capacity is the most\nimportant parameter; however, in the \"Device-package electrothermal co-optimization\" paragraph, they\nunderline the low-kt value of Ga O . Fig. 5h also shows that kt plays a relevant role in determining the thermal\n2 3\nbehavior of the modules. More details are needed to evaluate the individual impact of the two above\nparameters on the FOMs of the proposed module.\nResponse: We thank the reviewer for raising this important point. We clarify that thermal conductivity (k)\nt\nand volumetric heat capacity (C ) both play important roles, but their influence depends on the characteristic\nV\ntime scale of the pulsed power event and the repetition rate (or frequency). For very short pulses with small\nduty cycles (the usual application profile in pulsed power applications), the temperature rise can be\n42\napproximated by: ∆𝑇 =𝑄⁄(𝐶 𝑉) indicating that materials with larger heat capacity experience a smaller\nV\ninstantaneous temperature increase for the same injected energy36,37. As the pulse width increases or the\nfrequency increases, lateral and vertical heat spreading becomes dominant, and the time-dependent transient\nthermal resistance is strongly influenced by the thermal diffusion length: 𝐿 =2√(𝑘⁄𝐶 )𝑡, where t is the\nd t V\npulse on-state time38,39. When t becomes larger and diffusion length expands to package case, then heat\nextraction and k become more important. In conventional power switching applications, the pulse width is\nt\nusually relatively long with a duty cycle of 20~80%, making the material’s k important for module’s thermal\nT\nperformance. In pulsed power applications investigated in this work, the pulse width is usually short (down\nto a few micro-seconds or below) with a duty cycle usually below 1%, making the material’s C more\nV\nimportant for the module’s thermal performance.\nTo experimentally validate this, we designed the surge current tests with varying pulse widths across\nseveral orders of magnitude, and the results are presented in Fig. 5. As shown in Fig. 5h, for pulse widths\nbelow 10 µs, the Ga O module exhibits lower peak T compared to the SiC module benefiting its higher C\n2 3 j V\nand higher temperature endurance compared to SiC. For pulse widths above 100 µs, SiC module shows lower\nT than Ga O module due to SiC’s higher k . For these long pulse width and steady-state switching\nj 2 3 T\napplications, a widely-used package design to address the low k of Ga O (also adopted in this work) is the\nT 2 3\njunction-side-cooling package, which allows heat extraction directly from the device junction instead of\nthrough the low-k chip.\nT\nIn this work, despite the major focus being on short pulse width applications where C is more relevant,\nV\nwe still adopt the junction-side cooling package due to two reasons. First, it favors efficient heat extraction\nduring the cooling stage in each switching cycle. Second, the junction-side-cooling package can usually\nallows for a higher thermal capacitance (due to parallel connection of the chip and junction-side package in\nthe equivalent thermal network), which also favors for suppressing the temperature rise in the pulsed-on\ntransient.\nCorresponding change in manuscript: No\nReferences:\n[36] Incropera, F. P. & DeWitt, D. P. Fundamentals of heat and mass transfer. (6th Edition, J. Wiley & Sons,\nNew York, 2007).\n[37] Heat and Mass Transfer - Fundamentals and Applications, 6th Edition, McGraw-Hill Education,\nNew York, NY, 2020.\n[38] Marín, E. \"Characteristic dimensions for heat transfer.\" Latin-American Journal of Physics Education\n4.1 (2010): 56-60.\n[39] R. B. Bird, W. E. Stewart, E. N. Lightfoot. Transport Phenomena, John Wiley and Sons: New York,\n1976.\n43"}]

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