Generic logic block based on bias-gated 2D MoS_2 transistors

Domain: biology
Published: 2026-03-15
Editorial outcome: major_revision

Abstract
Integrating two-dimensional (2D) semiconductors and CMOS technology is a promising pathway for next-generation integrated circuits. However, the implementation of this strategy is hindered by the limited polarity modulation of 2D semiconductors and the inherent characteristics of CMOS architectures. Here, we report a generic logic block (GLB) that uses bias-gated molybdenum disulfide transistors (BG-FET). The BG-FETs exhibit threshold-adaptive field-effect characteristics through simple bias manipulation, enabling good rail-to-rail operation in the inverter circuits. The GLB composed of four BG-FETs can perform reconfigurable logic operations in a single circuit, including basic gate circuits, half-adder, multiplexer, encoder and static-random-access-memory. In contrast, conventional CMOS circuits require at least 100 transistors to perform the same set of operations. We further integrate flip-flop circuits and arithmetic logic units by cascading as-fabricated GLBs, featuring a transistor count saving of over 60% compared to CMOS design. Collectively, BG-FET-based GLB emerges as a post-CMOS integration technology with compelling potential.

Introduction
Two-dimensional (2D) semiconductors still maintain excellent electrical characteristics even at sub-nanometer scales and offer the potential for further extending the logic device scaling1-6. But its potential is severely hampered by the lack of proper logic architecture. The current silicon-based CMOS (complementary metal-oxide-semiconductor) architecture realized by high-energy doping technology is not suitable for atomically thin 2D semiconductors. So far, various doping methods have been developed to tune the polarity of 2D transistors7-9. But effective techniques towards practical circuit-level manufacture still lack because there is little physical space for impurity dopants in such atomically thin lattice10. Therefore, most large-scale logic circuits based on 2D semiconductors developed to date primarily follow the non-complementary NMOS architecture11-14, which inherently exhibit higher power consumption than CMOS technology. More importantly, an inherent problem is that logic functions implemented in CMOS or NMOS architecture require a large number of transistors, which hinders the processes of chip area scaling-down and function integration. Consequently, a necessity has been awakened to develop integrated device architectures based on the intrinsic advantages of 2D materials.

The emerging reconfigurable technology15, in which a transistor can be dynamically programmed to function as either an n- or p-FET during run-time by applying an external control voltage, presents a promising approach beyond CMOS. Reconfigurable circuits can achieve higher logic function density compared to CMOS architecture, thereby improving transistor utilization and reducing circuit redundancy. However, the reconfigurable field-effect transistor (RFET) relies on the modulation of device polarity, transitioning from ambipolar type to either n- or p- type, which necessitates additional hardware resources to implement16-19. This will result in additional power consumption and problems with circuit complexity. Moreover, the implementation of Boolean functions in the RFET-based circuits with full-swing output still follows a CMOS-like configuration20, utilizing p-FETs and n-FETs for pull-up and pull-down networks, respectively. This approach does not contribute to reducing the overall transistor count. Alternatively, reconfigurable circuit elements based on 2D homo- or heterostructure device21-23 and 2D single-transistor-based logic elements using a vertical- or split-dual-gate design24-27 are widely recognized as effective strategies to simplify circuits. However, these reconfigurable circuits are limited to small set of few fundamental logic operations and are further constrained by the intrinsic polarity or thickness of 2D semiconductors.

In this article, we report a bias-gated FET (BG-FET, Fig. 1a) designed to integrate generic logic blocks (GLBs). The asymmetric bias-gated device architecture enables BG-FETs to possess threshold-adaptive field-effect characteristics through different bias modes (source-gated or drain-gated, Fig. 1b). Leveraging these unique structural and electrical features, firstly, a cascaded logic inverter consisting of two BG-FETs with identical process parameters is fabricated to achieve good rail-to-rail operation. Subsequently, within a circuit composed of four BG-FETs, we design and fabricate a GLB with full-equivalent input/output (I/O) ports for performing dynamic reconfigurable logic computing by programming different combinations of input signals (Fig. 1c), including basic gate circuits, half-adder, multiplexer (MUX), encoder and static random-access memory (SRAM). As a benchmark comparison, implementing these functions in CMOS design typically requires more than 100 transistors (Fig. 1d). The as-fabricated GLBs are further used to integrate multiple arithmetic logic units and sequential circuit units with a transistor count reduction of over 60% compared to CMOS design, such as 2-bit multipliers and edge-triggered flip-flops.

Results
Characterization of the unipolar MoS BG-FET
2
A schematic of the BG-FET device concept is shown in Fig. 2a. The basic structure consists of a unipolar CVD-grown monolayer MoS channel sandwiched between hafnium oxide and antimony oxide (HfO /MoS /Sb O /HfO ), as well as a fully back-gated bottom electrode and a locally unilateral bias-gated top electrode. To confirm the signature device structure of our BG-FET, a representative sample and a traditional MOSFET for reference (Ref. FET) are simultaneously fabricated based on a same MoS film (Fig. 2b). The fabrication processes (see in Methods) of two devices are completely identical, except that an asymmetrically extended bias-gated electrode is added to the BG-FET. Notably, we choose a van der Waals crystal Sb O as a buffer layer to form a high-quality oxide-to-semiconductor interface28-30, enabling the integration of high-κ dielectrics via atomic layer deposition. Moreover, a van der Waals gate dielectric interface can better maintain the intrinsic properties of the underlying 2D materials, which also helpful for improving the uniformity and stability of 2D electronics.

The asymmetrical nature of this as-fabricated BG-FET is defined as two different bias schemes: extended bias-gated electrode as source (named source-gated, S-Gated) and as drain (named drain-gated, D-Gated). In principle, the energy band diagrams under two operating modes are shown in Fig. 2c. In S-Gated mode, the channel electrons around the source contact are depleted due to the bias-gated electrostatic (negative potential relative to the drain), resulting in the extension of the electron injection barrier compared to the Ref. FET. The widened barrier can block the injection of electrons from the source, thus requiring a larger V . In D-Gated mode, the accumulated electrons can improve the channel conductivity around the drain contact due to the bias-gated electrostatic (positive potential relative to the source), but not affecting the electron injection barrier at the source.

In detailed comparison, the electrical properties of two devices are investigated under the same testing conditions. As shown in Fig. 2d, the saturation voltage (V ) of BG-FET is smaller under the same gate voltage (V ) compared with the Ref. FET. By definition, the V corresponds to the drain-source voltage (V ) at which the drain-source current (I ) reaches saturation, equivalent to the V required for transistor pinch-off. Figure 2e illustrates the pinch-off mechanism of BG-FET and Ref. FET. As V increases, the depletion region of Ref. FET occurs at drain until the channel is pinched off and V is defined. In S-Gated mode, however, the depletion of BG-FET occurs both in drain and source due to the extended bias-gated electrode31,32. The source-side depletion region progressively expands towards the drain with the increasing V due to the bias-gated electrostatic (maintained at a negative potential relative to the drain), enabling the BG-FET to be pinched off prematurely and a smaller V is defined. Figure 2f exhibits the transfer characteristics of two devices both with a high on-off ratio of >109 and a low off-state current of less than 0.1 pA. Noticeably, the V (reference voltage, defined as the V required when the I is equal to 1 nA) in S-Gated mode is offset by around 0.7 V in the forward (right) direction compared to Ref. FET. A larger V for BG-FET is required to achieve the same current due to the bias-gated device structure. The maximum difference of I under the same V exceeds three orders of magnitude in the sub-threshold region. As the V increases, this difference gradually decreases and tends to be consistent, because the electron density in the channel is gradually dominated by V . The V -dependent V , R and more experimental data of two devices are demonstrated in Supplementary Fig. 1. These obvious differences between two devices indicate the effectiveness of the bias-gated structure design.

More valuable is that the asymmetric bias-gated device architecture enables BG-FETs to possess threshold-adaptive field-effect characteristics, which is crucial for subsequent GLB circuit design. To verify the inherent robustness of this characteristic and assess its scalability for large-scale integration, we fabricate an array of 256 BG-FETs distributed across 16 dies, with each die integrating 16 individual devices (Supplementary Fig. 2). All devices were fabricated on a continuous single-crystal MoS₂ thin film33 under identical process parameters. Subsequently, four BG-FETs were randomly selected from four units in each die for electrical characterization, yielding a total of 64 devices spread out to study uniformity over a large area. The transfer characteristics of BG-FETs under D-Gated and S-Gated modes are tested, as shown in Fig. 2g. The transistors exhibit a desired uniformity and threshold-adaptive field-effect characteristics. Besides, the statistical histogram of V difference in two modes is concentrated between 0.54-0.6 V (see the inset of Fig. 2g), indicating a low device-to-device variability.

To further explore the stability of BG-FETs, we electrically characterized the as-fabricated devices placed in the vacuum atmosphere for 1 week, 4 weeks, and 7 weeks. As shown in Fig. 2h, the BG-FET maintain excellent threshold-adaptive field-effect characteristics after seven weeks, and the ΔV of approximately 0.57 V between the two operating modes shows negligible variation throughout this period. And the BG-FET exhibit impressive threshold-adaptive field-effect characteristics even at high temperature of 400 K, as shown in Fig. 2i. Note that the threshold voltage of the BG-FET exhibits a negative shift with increasing temperature. This phenomenon can be attributed to the enhanced thermal activation of free carriers at elevated temperatures34,35. Furthermore, a larger shift amplitude is observed in S-Gated mode, leading to a progressive decrease in ΔV . This may be due to the release of more free carriers bound by the widened barrier induced by bias-gated electrostatic at high temperatures. The desired uniformity and stability of BG-FETs can be attributed to the bias-gated structure design with a built-in packaging function for maintaining the integrity of the channel materials, except for the high stability of the grown MoS .

Logic inverter based on unipolar MoS BG-FET
2
The inverter (NOT gate) that performs the Boolean function Y = A̅ is a basic logic element in digital circuits, in which A̅ is defined as an opposite voltage level to input A. Figure 3a shows the schematic of an adaptive-switching logic inverter composed of two as-fabricated unipolar MoS BG-FETs in series. In reported MoS -based inverter circuits11,12,36,37, specific designs are required for the driver and load devices to achieve rail-to-rail operation, such as different width/length (W/L) ratios, metal gates or channel materials between two transistors. In our demonstration, the as-fabricated SG-FET as driver (BG-FET in S-Gated mode) and DG-FET as load (BG-FET in D-Gated mode) can be dynamically switched through simple voltage manipulation.

To further clarify the role of a bias-gated device structure in digital circuits, two inverters made of BG-FETs and Ref. FETs are fabricated, respectively (Fig. 3b). The four devices used to fabricate two inverters have the same size and are based on a same single-layer MoS . Figure 3c shows the typical voltage transfer curves (VTCs) of two inverters with different switching threshold voltage (V ) at V = 2 V. The V of the BG-FET-based inverter (BG-inverter) shifts from approximately -0.15 V to 0.59 V compared with Ref. FET-based inverter (Ref.-inverter), which indicates that BG-inverter can realize good rail-to-rail operation due to the threshold-adaptive field-effect characteristics of BG-FET. Noticeably, an inverter that loses the cascaded function due to input and output not in the same range is strictly referred to as an invalid circuit. As mentioned above, the reported inverters require a specific design to achieve rail-to-rail operation, however, which cannot change the function of the constituent components (load or driver) once built.

More detailed static characteristics of the BG-inverter and Ref. inverter under different V are shown in Supplementary Fig. 3. Two inverters show similar performance for the parameters of gain and I across all V values. Where a peak gain of 157 for BG-inverter and of 159 for Ref. inverter, a peak I of less than 2 nA for BG-inverter and of less than 5 nA for Ref. inverter are achieved at V = 5 V. And the key parameters of BG-inverter, such as peak gain, V , noise margin (N /V ) and peak static power are intuitively shown in Fig. 3d-e. A total noise margin (NM + NM )/V over 85% and a low static power (P ) of less than 10 nW across all V values are calculated. And The V shift of 0.06 V for BG-inverter under different V is observed, which may be attributed to the ΔV variation of BG-FET under different V . In theory, the competition relationship between bias-gated and back-gated modulation can be controlled by optimizing the L /L ratios, in which L and L are defined as the length of the bias-gated electrode and the channel in Fig. 2a, respectively. As this ratio increases, the control region of the bias-gated electrode expands relatively. The controllable modulation of this competition relationship allows for the on-demand design of application-oriented devices.

Additionally, the BG-inverter can maintain a full-swing output response at a 2 V full-scale square input signal of 100 Hz, even after 1,000 switching cycles (Figure 3f). The dynamic switching speed mainly determined by the RC delay (𝜏) is also a very significant evaluation indicator in logic circuits. To further characterize this performance, the dynamic switching behavior of the BG-inverter by using an AC input signal is studied at higher frequencies (Supplementary Fig. 4). As demonstrated by the dynamic analysis, the inverter can immediately invert the input signal, and the output signal can maintain a high-quality waveform response that is opposite to the input signal at a relatively low frequency (<500 Hz). However, the output waveform gradually deformed with the frequency of the input signal increases, and full-swing output cannot be achieved at a higher frequency (>5 kHz) mainly due to a RC delay in dynamic switching. A rising time delay (𝜏 ) of 285 µs and falling time delay (𝜏 ) of 35 µs are extracted at 1 kHz, where the delay 𝜏 is defined as the time intervals between 10% and 90% of V , as shown in Fig. 3g. These performance metrics of the BG-inverters demonstrate competitive results at the current device scale compared with state-of-the-art 2D materials-based CMOS inverters (Supplementary Table 1). There remains significant potential for further optimization through continued device engineering and process refinement.

Generic logic block based on unipolar MoS BG -FET
2N
Figure 4a schematically depicts the circuit design diagram of a generic logic block (GLB) with a specific cascade mode based on four BG-FETs. This GLB can perform logic functions with six input terminals (V , V , V , V , V and V̅̅̅̅̅̅) and two output terminals (V and V ). The bias-gated source-drain is set as the pass-input terminal (V ), the non-bias-gated source-drain is set as the output terminal (V ), and the gate is set as the control-input terminal (V ). Note that the manufacturing process parameters of four BG-FETs used to fabricate the GLB are almost identical (as shown in Fig. 4b), and they can all dynamically switch between D-Gated mode and S-Gated mode through simple voltage manipulation (Fig. 4c). These features mean that four V ports of the as-fabricated GLB are fully equivalent, which is crucial for GLB to perform arbitrary logic operations in a same circuit. For example, the Boolean function for basic gate circuits (AND/NAND, OR/NOR, and XOR/XNOR), arithmetic unit (half-adder and 2:1 MUX) and memory cell (SRAM) can be achieved in a single GLB circuit by programming the combinations of input signals (as shown in Fig. 4d). The measured output waveforms driven by programming schemes and input combinations are shown in Fig. 4e, achieving a dynamic reconfigurable computing paradigm. Here, the high voltage level (2 V) is defined as logic ‘1’ and the low voltage level (0 V) is defined as logic ‘0’. The implementation of more details is shown in Supplementary Fig. 5-7.

In addition, the GLB can be reconstructed to a 4-2 encoder (a circuit that encodes 2n input signals using n-bit binary code) according the programming scheme shown in Fig. 4d. When V is set to A , V is set to A , V and V is set to A , V is set to A̅̅̅, V is set to Y , and V is set to Y , the GLB can perform the function of encoding 4-bit binary code (A , A , A , A ) with 2-bit binary code (Y , Y ). The measured result at a constraint condition (only one of the four signals A , A , A and A is set as logic ‘1’ at the same time) and a hidden condition (when A , A and A are all set as logic ‘0’, it means A is set as logic ‘1’) is shown in Fig. 4f. In this circuit, the 4-bit input signals: (0001), (0010), (0100), and (1000) are encoded as 2-bit binary codes: (00), (01), (10), and (11), respectively, which are consistent with the function truth table of the 4-2 encoder (Supplementary Fig. 8). Similarly, GLB can also be reconstructed as a 2-4 decoder (a circuit that decodes n-bit binary code into 2n-bit signals) that function exactly opposites to the encoder (Supplementary Fig. 9). Noteworthy, the GLB circuit can fully implement all logic functions with a full-swing output voltage due to the threshold-adaptive field-effect characteristics of BG-FET. The principle is analogous to the complementary structure in CMOS technology. More detailed explanation seen in Supplementary Fig. 10.

GLB-based digital circuits
To further verify the feasibility of GLB using BG-FET device architecture for digital circuit optimization, various arithmetic logic units (ALU) and sequential circuit units are integrated on the monolayer MoS film. Figure 5a shows the schematics and optical image of a 2-bit carry-save-adder (CSA) multiplier that consists of four GLBs and four BG-inverters with 24 BG-FETs in total. By analyzing the principle of multiplication (depicted in Supplementary Fig. 11a), it is found that the partial products can be achieved through logic AND gates (Y = AB). While the sum of partial products can be achieved through adder circuits. Based on this principle, two GLBs are reconstructed as four AND gates to implement four partial products, two GLBs are reconstructed as two half-adders for partial product summation and four embedded BG-inverters are used to provide necessary complementary signals. The measured output voltage signals (P , P , P , P ) are shown in Fig. 5b, indicating that GLB-based 2-bit CSA-multiplier can fully implement multiplication operations according to the truth table (shown in Supplementary Fig. 11b) for all the input combinations (A , A , B , B ). CSA multiplier circuits that can improve the speed of data processing and enable more complex data analysis with efficient computing play an important part in digital ICs. Furthermore, the circuit design, optical image and measured results for 1-bit digital comparator, controllable left/right shifter and 1-bit full-adder based on BG-FETs are also plotted as examples in Supplementary Fig. 12. The output voltage signals can correctly respond to all possible input combinations according to the truth table.

The sequential logic elements are critical components in memory and data manipulation circuits for digital ICs. Figure 5c shows the status table of D latch, D flip-flop (DFF) and T flip-flop (TFF), in which signal CLK as the global clock control input, signal D as the data input and signal Q as the output. The circuit design, optical image and measured waveforms of the D latch based on two BG-FETs and a SRAM reconstructed by GLB are plotted in Fig. 5d. In this sequential circuit, the output Qn+1 is seen to follow the input D when the input CLK is in logic ‘0’, which is consistent with the characteristic equation (Qn+1 = D). Conversely, the circuit operates as a memory mode when CLK is in logic ‘1’, meaning that the output Qn+1 remains in its current state Qn. Compared with D latch, an edge-triggered DFF with better anti-interference feature can be fabricated through two D latch elements in cascaded. Figure 5e shows the circuit schematic, optical image and measured waveforms of a falling edge-triggered DFF which consists of 12 BG-FETs in total. This circuit can immediately follow the data input D to output the correct logic signal (Qn+1 = D) at the falling edge of the control input CLK and hold the signal state (Qn+1 = Qn) until the next falling edge.

Additionally, combining flip-flop circuits and composite basic gate circuits can also implement other sequential logic functions for different applications. For example, a falling edge triggered TFF based on a characteristic equation (Qn+1 = T⊕Qn) can be fabricated by cascading an XOR gate at the D input terminal of DFF (that is, setting D = T⊕Qn), as shown in Fig. 5f. The output signal Qn+1 from the measured waveform flips once every time at the falling edge of control input CLK when data input T is logic ‘1’. Conversely, this TFF works in a memory mode when data input T is logic ‘0’. The TFF circuits can ensure the correct transmission of timing signals and also add a flipping function. Similarly, a flip-flop applied to the frequency-halving circuit is also shown as an example in Supplementary Fig. 13.

Methods
Device fabrication
The BG-FETs and BG-FET-based logic circuits are built using the fabrication process compatible with silicon-based technology. First, the pad electrode and bottom electrodes are mapped in advance on the SiO /Si substrate using laser direct writing (Micro-Writer ML3) technology and proximity UV lithography (MA/BA6 Gen4) technology. Then 10/50 nm Cr/Au is deposited using thermal evaporation (PRO-Line PVD 200), followed by atomic-layer deposition (TALD-200) of a 20-nm-thickness HfO the dielectric layer. The CVD-grown monolayer MoS films are accurately stacked on the HfO using wet-transfer technology with polymethyl methacrylate film as a sacrificial layer. It is necessary to pattern the MoS film using the plasma etching (RLE-100R) technique with a mixture of O and SF to define the channel region. Subsequently, the designed drain and source electrodes are deposited based on e-beam lithography (EBL, FEI Quanta 3D) and thermal evaporation technology, and the ALD-grown HfO with a buffer layer of Sb O is deposited as the top gate dielectric. Where Sb O powder was evaporated by heating in the PVD system with a high vacuum (10-7 torr). The deposition rate is controlled to be 0.05 Å/s for the flat film with a thickness of 2-3 nm. Finally, the top bias-gated electrodes are deposited onto the designated position.

Electrical measurement
The electrical characteristics of the single BG-RFET devices and simple circuits are measured using a semiconductor parameter analyzer (Agilent B1500 coupled with six SMUs and two PMUs) in a vacuum probe station (Lake Shore). The measurements of complex digital circuits are performed by a semi-automatic probe station (SUMMIT200) connecting to a modular PXle SMU testing system (M9019A) equipped with six 5-channel source/measure units with 30 SMUs in total. All measurements for BG-FET, GLB and GLB-based logic circuits are conducted at room temperature.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The authors propose an asymmetric bias-gated MoS2 transistor and demonstrate a range of reconfigurable logic gates and small digital circuits built from these devices. The manuscript is well motivated, pursuing logic built purely from MoS2 transistors is an interesting direction, and the experimental demonstrations are impressive in scope. However, in its present form the paper has two major issues that hold me back from supporting publication: (1) the device novelty is limited relative to existing dual-gate/bias-gated MOSFET structures, and (2) the circuit benchmarks are incomplete and, in several respects, fail to support the claimed advantages (transistor-count saving and reconfigurability) compared to conventional CMOS. Below I list major concerns and specific, actionable suggestions to improve the manuscript.\n1. Device novelty is limited. The proposed structure is equivalent to a conventional dual-gate MOSFET, where the top gate is connected to either the source or drain. Dual-gate MoS2 MOSFETs have already been reported (ACS Appl. Electron. Mater. 2020, 2, 111–119; Nat. Electron. 2, 563–571 (2019); 2021 IEDM, 10.1109/IEDM19574.2021.9720695). Moreover, such a configuration tends to degrade switching speed due to the increased capacitance between the top and bottom gate electrodes.\n2. Extended source/drain design. The introduction of an extended drain or source region typically enhances short-channel effects in a MOSFET, which is generally undesirable. I understand that the authors intentionally introduced this feature to generate performance variation for digital circuit design, which is a creative idea. However, this approach appears to be a compromise to address the lack of an ideal complementary p-type transistor to the MoS2 NMOS. As a downgraded CMOS strategy, the authors should provide a more comprehensive comparison with conventional CMOS, including aspects such as scalability, speed, noise tolerance, and power efficiency, to justify its acceptability.\n3. Reconfigurability concerns. (1) Although the circuits in Fig. 4 can be reconfigured to perform different functions, the reconfiguration appears to rely on manually rewiring the input/output, for example, VIN–P2 switching among B, A, and Ā. I assume this is achieved by altering probe connections. In a practical integrated circuit, such reconfiguration would require additional circuitry (e.g., multiplexers, inverters, or routing networks). Considering this overhead, the claimed advantage in transistor count saving may not hold. (2) For the digital circuits in Fig. 5, no on-chip reconfigurability is demonstrated, for example, dynamically switching the same circuit between D latch, D flip-flop, and T flip-flop functions.\n4. Performance concerns. I appreciate the authors’ efforts to demonstrate various digital circuits. However, I remain concerned about their actual performance. For instance, the inverter’s threshold voltage (0.59 V) deviates significantly from the ideal mid-point (1 V), leading to poor noise margins. Additionally, all demonstrations operate at very low clock frequencies (< 1 Hz). Since transistor count reduction may trade off with performance degradation, a more comprehensive benchmarking, including switching speed, energy efficiency, and noise tolerance, is necessary.\n5. Some minor issues.\n(1) In Fig. 3a, what is VINbar? I assume it is fixed at 0 V. If not, additional circuits are required to generate it.\n(2) In Fig. 4f, the waveform for A0 is missing.", "reviewer_2": "This manuscript presents a bias-gated MoS₂ transistor platform that enables reconfigurable logic behavior within a unified, unipolar device framework. By strategically tuning the bias configuration at the source and drain terminals, the same MoS₂ FET can exhibit both enhancement- and depletion-type characteristics. Building on this mechanism, the authors construct a Generic Logic Block (GLB) capable of implementing multiple Boolean and sequential functions through electrical reconfiguration. The concept is technically sound and conceptually elegant, representing a well-balanced device-to-circuit co-design approach that advances the field toward programmable, CMOS-compatible 2D electronics. The experimental results convincingly validate the proposed mechanism across multiple logic hierarchies—including inverters, logic gates, arithmetic circuits, and flip-flops—and the fabrication strategy appropriately preserves 2D material integrity through low-thermal-budget bonding and passivation. Overall, this study offers a coherent and comprehensive demonstration of a scalable, reconfigurable, and doping-independent logic framework in 2D materials. I consider this manuscript a strong contribution suitable for publication in Nature Communications, subject to minor clarifications and refinements as outlined below.\n1. Energy-band representation of bias-gated operation\nThe description of S-gated and D-gated operation modes is conceptually clear, but the accompanying energy-band diagrams are overly simplified. It is recommended to refine the schematic to more explicitly depict the spatial distribution of potential barriers and the corresponding modulation of threshold voltage in each configuration. A more detailed illustration—such as showing relative band alignment near the source and drain regions—would improve clarity and accessibility for a broad readership.\n2. Benchmarking of inverter performance\nThe reported inverter gain of 157 is impressive for a 2D logic circuit. However, the discussion would benefit from benchmarking against representative results from prior 2D logic demonstrations or conventional CMOS technologies. A brief comparative analysis emphasizing key metrics such as gain, noise margin, and switching sharpness would help position the proposed GLB within the broader context of state-of-the-art 2D logic performance.\n3. Dynamic reconfigurability demonstration\nThe reconfigurability of the GLB is effectively shown through static bias configurations, but its dynamic behavior remains unexplored. Including a brief experiment or supplementary figure demonstrating real-time switching between two logic modes (e.g., AND ↔ OR) would substantially strengthen the claim of electrical reconfigurability and distinguish this platform from previously reported static architectures.\n4. Scalability and energy considerations\nThe scalability and energy implications of the bias-gated architecture are not yet discussed. It would be valuable to include a short paragraph commenting on potential challenges—such as leakage current, bias overhead, and interconnect complexity—when scaling to higher integration levels. This discussion would provide a more comprehensive view of the feasibility of extending the GLB concept toward large-scale reconfigurable 2D logic systems.\n5. System-level circuit considerations\nThe demonstration of sequential circuits (D-latch, D-flip-flop, and T-flip-flop) serves as a meaningful validation of the GLB concept. Nevertheless, the discussion could be strengthened by addressing signal propagation, synchronization, and timing stability when cascading multiple GLBs in larger logic networks. A brief consideration of signal restoration, clock distribution, and potential strategies for maintaining bias uniformity would enhance the manuscript’s system-level perspective.\n6. Static power characterization\nTo more clearly elucidate the static power consumption characteristics of the proposed logic circuit, it is recommended that the authors provide the dependence of the inverter current (Idd) on the input voltage during operation. This would give a more complete picture of power behavior under different biasing conditions.\n7. Scaling and frequency limits\nTo further underscore the technological potential of this approach, a concise theoretical discussion on the ultimate scaling limits of the device dimensions and the upper frequency bound of circuit operation is encouraged. Such analysis would help clarify the long-term prospects of this bias-gated architecture.\n8. Full-swing output characteristics\nFinally, it is recommended that the authors elaborate on the mechanism responsible for achieving full-swing voltage output in the logic circuit. A more detailed explanation would help emphasize the advantage of the proposed approach over conventional NMOS-based designs, which typically exhibit threshold voltage–related signal degradation.", "reviewer_3": "Summary\nThis research presents an asymmetric MoS2 FET architecture as a foundation for high-density reconfigurable logic. MoS2 FET has been demonstrated into a generic logic block. MoS2-based GLB reduced the transistor count by over sixty percent versus equivalent CMOS circuits. Simple bias control toggles operation between source-gated and drain-gated modes. The block dynamically implements various logic functions, including inverter, half adder, multiplexer, encoder, and SRAM within one circuit. While the work is well-structured and the data are compelling, several points require clarification and revision before the manuscript can be deemed suitable for publication in this journal.\nMajor comments\n1. The manuscript provides insufficient information regarding Sb2O3. Unlike HfO2, Sb2O3 is not a commonly used dielectric material. Therefore, the authors should clarify why it was chosen, specify its thickness, and cite appropriate references [1, 2] that support its use. In addition, detailed information on the deposition process of the Sb2O3 buffer layer during device fabrication is required.\n2. The authors seem to emphasize the advantage of the van der Waals interface formed by Sb2O3 to enhance device performance. If that is the case, why was this material applied only in the top-gate configuration? In the BG inverter, part of the channel electrons accumulated on the upper side may indeed benefit from a clean interface, whereas in the Ref inverter, all channel electrons accumulate at the bottom interface, which is likely degraded by the ALD-grown HfO2. This raises concerns about the fairness of the comparison, as the two devices may not be under equivalent interfacial conditions.\n3. In Figure 3c, the authors compare the gain of the BG and Ref inverters only at VDD = 2 V, while Figures 3d and 3e present parameters solely for the BG inverter. Can the authors confirm that the BG inverter still shows similar or superior performance compared to the Ref inverter across all VDD values when considering parameters such as VM, gain, Pstatic, peak, and NM/VDD? A more comprehensive comparison, like Supplementary Figure 1, seems necessary. Moreover, including the V₍M₎ shift of 0.06 V (mentioned in Supplementary Figure 2b) directly in Figure 3d would make the data presentation more compelling.\n4. It would be beneficial to show the corresponding IOUT values for VIN = 0.9 V and 1.0 V in Supplementary Figure 2a. The current crop graph looks incomplete and visually unappealing.\n5. The Device Fabrication section lacks information on the e-beam lithography system used. Furthermore, for the CVD-grown MoS₂, details such as the precursor materials, film thickness, and lateral dimensions are missing.\n6. Supplementary Figures 1a–c appears to show the same output characteristics, but the reason for dividing VGS around 1 V is unclear. In Figures 1b and 1c, VDS is extended to 5 V, which makes VSAT variations difficult to observe and instead highlights the difference in IDS magnitude. Reducing the axis range and marking VSAT as done in Figure 1a could better emphasize the VSAT shift. Why was VSAT not explicitly indicated? In addition, in Figure 1f, the y-axis should be plotted linearly to enable a more accurate comparison of VSAT.\n7. While Figures 2 and Supplementary Figure 1 present a comparison between the BG-FET and Ref-FET, the main text only highlights the advantages of VSAT and VM in the BG-FET. Supplementary Figure 1, however, lacks any corresponding discussion. The authors should address the lower subthreshold swing and Ion observed in the BG-FET compared to the Ref-FET. How do these trade-offs impact the implementation of generic logic blocks?\n8. In Supplementary Fig. 10a, the truth table appears to be incorrect, and there is no clear correlation between the listed truth table and the voltage signal-time plot.\n9. In lines 95-99, the authors describe that the dependence of VSAT on VGS decreases as the LBG/Lch ratio increases. However, this is currently presented only as an experimental observation. It would be valuable if the authors could provide a more detailed physical explanation in conjunction with the operational principles of the S-Gated and D-Gated modes discussed in lines 120-127 from the perspectives of device structure, electrostatic potential distribution, and carrier transport path. In addition, the authors are encouraged to include relevant references supporting these interpretations.\n10. In lines 88 and 180, the authors state that the BG-FETs were fabricated under identical process parameters. While this indicates that the devices were processed under the same fabrication conditions, it does not necessarily guarantee uniform electrical performance. Therefore, statistical verification (e.g., device-to-device variation in Vth, Ion, and Ioff) is required to substantiate the claim of device uniformity. In fact, CVD-grown 2D materials are known to suffer from uniformity challenges (see 10.3390/ma14247590) [3]. Moreover, demonstrated noticeable device-to-device variability even under nominally identical fabrication conditions (see 10.1038/s41467-020-20732-w) [4]. Including such statistical data or discussion would considerably strengthen the manuscript’s credibility regarding process consistency.\n11. While conventional CMOS inverters experience electrical stress only when the transistors are in the ON-state, each BG-FET within the GLB is subjected to various static and dynamic bias conditions depending on the programmed logic function. Such complex stress profiles could lead to asymmetric aging among the devices, causing imbalanced degradation within the same GLB and potentially resulting in circuit malfunction over time. In other words, the reconfigurable nature of the GLB, though advantageous for functionality, may pose a reliability trade-off. Therefore, it would significantly strengthen the manuscript if the authors could provide experimental data on the long-term stability of the BG-FETs such as threshold voltage shifts, mobility/temperature stability, or bias-stress endurance tests (e.g., TDDB, PBS/NBS).\n12. It is generally known that SGTs exhibit lower on-current and larger SS compared to conventional transistors. However, your device shows no significant difference from the reference device except for the Vth shift. Could you address the possible reasons for its superior performance?\n13. Because the SG FET operates based on barrier-controlled conduction, its characteristics are highly sensitive to temperature. Therefore, information about the specific temperature at which all measurements were conducted must be provided.\nMinor comments\n1. The scale bar is missing in Figure 4b.\n2. The term “BG-RFET” is used only once in line 296. It would be better to maintain consistent terminology throughout the manuscript by using “BG-FET” instead.\n3. In Supplementary Fig. 5a, when both A and B are set to 1, the Sum output should be 0. However, it is incorrectly listed as 1 in the truth table.\n4. In Supplementary Fig. 5d, the (S, A, B) labeling is duplicated as (0, 0, 0) and (0, 0, 1). The labels should be revised to correctly reflect the intended sequence of (S, A, B).\n5. In Supplementary Fig. 9a, the partial product expression seems to contain a typographical error. The second partial product row should be corrected from A1B0, A0B0 to A1B1, A0B1 to accurately represent the 2-bit multiplication process."}, "author_response": "Reply: We sincerely thank the reviewer for reviewing our manuscript and raising constructive comments that are tremendously helpful for further improving our manuscript. Below are our detailed responses to each comment.\n1. Device novelty is limited. The proposed structure is equivalent to a conventional dual-gate MOSFET, where the top gate is connected to either the source or drain. Dual-gate MoS MOSFETs have already been reported (ACS Appl. Electron. Mater. 2020, 2, 111–119; Nat. Electron. 2, 563–571 (2019); 2021 IEDM, 10.1109/IEDM19574.2021.9720695). Moreover, such a configuration tends to degrade switching speed due to the increased capacitance between the top and bottom gate electrodes.\nReply: We thank the reviewer’s comments and we agree that conventional dual-gate MoS MOSFETs have already been reported from various research perspectives, as mentioned by the reviewer. However, our bias-gated device structure is fundamentally different from conventional dual-gate MOSFET.\nAnd we agree that the dual-gate configuration may degrade switching speed, mainly due to the RC delay in dynamic switching process. RC delay depends on the value of the parasitic resistance and capacitance where the capacitance is mainly determined by the device size. However, as the dimension of transistors continues to downscale to enable higher integration density, the capacitance and resistance of single transistor will sharply decrease1,2. At the circuit level, the switching speed or dynamic power mainly depends on the number of transistors. Notably, there is no capacitance between the top gate and the source or drain of our BG-FET due to the short-circuit.\nFinally, we thank the reviewer again for this important point, the dynamic characteristics of multi-field gated MOSFETs deserve further investigation in the future.\n2. Extended source/drain design. The introduction of an extended drain or source region typically enhances short-channel effects in a MOSFET, which is generally undesirable. I understand that the authors intentionally introduced this feature to generate performance variation for digital circuit design, which is a creative idea. However, this approach appears to be a compromise to address the lack of an ideal complementary p-type transistor to the MoS2 NMOS. As a downgraded CMOS strategy, the authors should provide a more comprehensive comparison with conventional CMOS, including aspects such as scalability, speed, noise tolerance, and power efficiency, to justify its acceptability.\nReply: We thank the reviewers for the careful reading and the valuable suggestions. In reality, the extended source/drain design or gate-all-around (GAA) design can enhance vertical gate control and improves the shielding effect of the source on the drain field3-5, thus exhibiting strong immunity to short-channel effects (SCEs). Moreover, the SCEs of the BG-FET has also been a concern for us, and we have also fabricated BG-FETs with a relatively short channel for testing and verification. As demonstrated in Fig. R1, the as-fabricated BG-FET with a channel length of 200 nm maintains excellent switching characteristics while preserving its threshold-adaptive field-effect properties. In our ongoing research, we are actively exploring the electrical characteristics of BG-FETs with even shorter channel lengths (< 50 nm) to comprehensively understand their scaling potential and performance limits. These findings will be incorporated in our future work, as they are crucial for practical applications of BG-FET technology.\nFig. R1. BG-FETs with a channel length of 200 nm. a, Optical image of the devices. Scale bar: 10 μm. b, SEM image of the device . Scale bar: 1 μm. c, Transfer characteristics of three BG-FETs in D-Gated mode and S-Gated mode at V = 1 V.\nDS\nAs for the design concept of BG-FET-based GLB, we appreciate the reviewer's understanding and we strongly agree that CMOS strategy, is currently the most mature technology. However, as mentioned by the reviewer, 2D materials-based CMOS has to address the lack of an ideal complementary p-type transistors to match n-type counterparts, and the increased process complexity when employing different 2D materials (e.g., WSe for p-type and MoS for n-type) in a single circuit. Therefore, the GLB architecture based on a single-polarity transistors may also offer a potentially promising solution for 2D integrated circuit manufacturing.\nAccepting the constructive suggestion, we have added a more comprehensive comparison with state-of-the-art 2D materials-based CMOS inverters in the revised version (see new Supplementary Table 1). Notably, we have to emphasize again that the key innovation of our work lies in the novel GLB architecture enabled by the unique threshold-adaptive field-effect characteristics of BG-FETs. The performance metrics of our BG-inverters demonstrate competitive results at the current device scale, and there remains significant potential for further optimization through continued device engineering and process refinement.\nNew Supplementary Table 1. Comparison of inverter performance with previous reports.\nStatic\nChannel Peak Noise RC\nV (V) power (peak Scalability Ref.\ndd\nmaterials gain margin delay\nvalue)\nGLB type\nThis\nMoS 1~5 30~157 1~9 nW >87% 160 μs Yes\nCMOS type\nMoS -BP 1~2 8~13 100~200 nW N/A 0.15 s No Ref.6\n2\n1~3 N/A < 100 pW N/A 40 μs Yes Ref.7\n1~4 2~19 3~74 nW N/A N/A No Ref.8\nMoS -WSe\n2 2\n0.1~2 1~110 0.2 nW~1 μW >87% >500 μs No Ref.9\n0.5~1 11~14 21nW~0.34 μW N/A N/A No Ref.10\nMoS -MoTe 1~5 3~33 0.4~4 nW <79% ~24 μs No Ref.11\n2 2\n1.5~5.5 40~340 8 nW~2 μW >90% N/A No Ref.12\nWSe\n2\n3~5 20-110 0.1~1 nW >60% 120 μs No Ref.2\nNMOS type\n2 43 12 nW\nMoS Ref.13\n2\n4 107 Yes\nN/A N/A\nMoS 5 20 N/A Ref.14\n2\n3. Reconfigurability concerns. (1) Although the circuits in Fig. 4 can be reconfigured to perform different functions, the reconfiguration appears to rely on manually rewiring the input/output, for example, VIN–P2 switching among B, A, and Ā. I assume this is achieved by altering probe connections. In a practical integrated circuit, such reconfiguration would require additional circuitry (e.g., multiplexers, inverters, or routing networks). Considering this overhead, the claimed advantage in transistor count saving may not hold. (2) For the digital circuits in Fig. 5, no on-chip reconfigurability is demonstrated, for example, dynamically switching the same circuit between D latch, D flip-flop, and T flip-flop functions.\nReply: We thank the reviewers for the careful reading and questioning. First, we apologize for the insufficient clarity in describing the operation mode of GLB in the previous version. In fact, the measured output waveforms of GLB in Fig. 4e is a real-time switching between various logic modes (e.g., basic logic gates, half adder and MUX). The probe connections remain unchanged throughout the entire testing process. Specifically, the output port responds to continuous timing signals upon applying pre-programmed waveforms to each input port. The output waveform is then compared with the truth table to validate whether each stage performs the intended logic operation. Notably, the proposed GLB can generate mutually inverted output signals (V and V ) to satisfy the complementary input requirements of the next-stage circuit.\nOUT-1\nOUT-2\nFor the digital circuits in Fig. 5, as mentioned by the reviewer, complex circuits such as multipliers or flip-flops demonstrate no on-chip reconfigurability. In this section, we just leverage the inherent versatility of GLBs by reconfiguring them into functional blocks required for complex circuits. These blocks are then cascaded to perform the targeted logic operations, thereby further validating the feasibility of GLB architectures for digital circuit optimization. Finally, we thank the reviewer for the valuable feedback and agree that achieving system-level on-chip reconfigurability represents a promising and interesting research direction for future work.\n4. Performance concerns. I appreciate the authors’ efforts to demonstrate various digital circuits. However, I remain concerned about their actual performance. For instance, the inverter’s threshold voltage (0.59 V) deviates significantly from the ideal mid-point (1 V), leading to poor noise margins. Additionally, all demonstrations operate at very low clock frequencies (< 1 Hz). Since transistor count reduction may trade off with performance degradation, a more comprehensive benchmarking, including switching speed, energy efficiency, and noise tolerance, is necessary.\nReply: We thank the reviewer for the constructive comments. Firstly, we have provided the experimental data and noise margin extraction of the BG-inverter under an operating voltage of 1.2 V, as shown in new Supplementary Fig. 3c. The inverter’s threshold voltage (approximately 0.6 V) can be located at the ideal mid-point of the operating voltage of 1.2 V. In reality, the voltage-switching point of the BG-inverter can be tuned to proper position by sizing the L /L ratios or process parameters16,17 (e.g., device dimensions, EOT of dielectric or metal gates), in which L and L are defined as the length of the bias-gated electrode and the channel in Fig. 2a, respectively. These are important means for reducing the operating voltage of logic circuits with proportional scaling in the future.\nNew Supplementary Fig. 3. c, Voltage transfer curve (VTC) and its mirror reflection of the BG-inverter with a switching threshold voltage V ≈ 0.6 V. The V , V , V , and V represent the minimum high output voltage, maximum low output voltage, maximum low input voltage, and minimum high input voltage for the inverter, respectively.\nM OH OL IL IH\nNew Fig. 3. f, Cyclic reliability of the BG-inverter at a 2 V full-scale square input signal of 100 Hz for more than 1000 switching cycles.\nMoreover, we have demonstrated the dynamic output voltage response of the BG-inverter at a 2 V full-scale square input signal of 100 Hz in the previous version (see Supplementary Fig. 3 or new Fig. 3f). To further characterize this performance, we added the dynamic switching behavior analysis of the BG-inverter by using an AC input signal at different frequencies (see new Supplementary Fig. 4). As demonstrated by the dynamic analysis, the inverter can immediately invert the input signal, and the output signal can maintain a high-quality waveform response that is opposite to the input signal at a relatively low frequency (<500 Hz). However, the output waveform gradually deformed with the frequency of the input signal increases, and full-swing output cannot be achieved at a higher frequency (>5 kHz) mainly due to a RC delay in dynamic switching.\nNew Supplementary Fig. 4. Frequency-dependent dynamic output voltage response of the BG-inverter at square wave input signal with a frequency of 100 Hz (a), 500 Hz (b), 1k Hz (c), 2k Hz (d), 5k Hz (e), 10 kHz (f).\nNew Fig. 3. g, Dynamic output voltage response at square wave input signal with a frequency of 1 kHz (upper), and the corresponding rise time and fall time of output voltage (lower).\nRC delay time of the inverter can be obtained by analyzing the dynamic output voltage curves. The rising time delay (߬ ) and falling time (߬ ) are defined as the time intervals between 10% of V and 90% of V . Under a square wave input signal with an AC frequency of 1kHz and a voltage swing of 2V, a ߬ of ~285 µs and a ߬ of ~35 µs are observed at V = 2 V, respectively (see new Fig. 3g). And the average τ of 160 µs is similar to the values noted in previous reports on 2D-based CMOS inverters1,2,11,18.\nFinally, we have to emphasize that the primary objective of this work is the functional validation of the proposed GLB architecture. Exploring the application potential of GLB design in system-level circuits with comprehensive consideration based on scaled devices may be an interesting research direction for future work.\n5. Some minor issues.\n(1) In Fig. 3a, what is VINbar? I assume it is fixed at 0 V. If not, additional circuits are required to generate it.\nReply: We sincerely thank the reviewer for pointing out this issue. In reality, Vതതതതത and V are electrically connected during BG-inverter testing, as evidenced by the optical image in Figure 3b. And we have marked it in the revised Fig. 3a.\n(2) In Fig. 4f, the waveform for A0 is missing.\nReply: We sincerely thank the reviewer for pointing out this issue. In principle, the 4-2 encoder circuit follows two conditions: “a constraint condition (only one of the four signals A , A , A and A is set as logic ‘1’ at the same time) and a hidden condition (when A , A and A are all set as logic ‘0’, it means A is set as logic ‘1’)”, as stated in the previous version. This means that the defined A input port does not receive any real signal input during the testing period.\nReference:\nReviewer #2 (Remarks to the Author):\nThis manuscript presents a bias-gated MoS₂ transistor platform that enables reconfigurable logic behavior within a unified, unipolar device framework. By strategically tuning the bias configuration at the source and drain terminals, the same MoS₂ FET can exhibit both enhancement- and depletion-type characteristics. Building on this mechanism, the authors construct a Generic Logic Block (GLB) capable of implementing multiple Boolean and sequential functions through electrical reconfiguration. The concept is technically sound and conceptually elegant, representing a well-balanced device-to-circuit co-design approach that advances the field toward programmable, CMOS-compatible 2D electronics. The experimental results convincingly validate the proposed mechanism across multiple logic hierarchies—including inverters, logic gates, arithmetic circuits, and flip-flops—and the fabrication strategy appropriately preserves 2D material integrity through low-thermal-budget bonding and passivation. Overall, this study offers a coherent and comprehensive demonstration of a scalable, reconfigurable, and doping-independent logic framework in 2D materials. I consider this manuscript a strong contribution suitable for publication in Nature Communications, subject to minor clarifications and refinements as outlined below.\nReply: We sincerely appreciate the reviewer for carefully reading of the manuscript and positive comments on our work. It is very encouraging to receive your constructive comments that are tremendously helpful for further improving our manuscript. We have modified the manuscript carefully and the detailed responses to your suggestions are listed below.\n1. Energy-band representation of bias-gated operation\nThe description of S-gated and D-gated operation modes is conceptually clear, but the accompanying energy-band diagrams are overly simplified. It is recommended to refine the schematic to more explicitly depict the spatial distribution of potential barriers and the corresponding modulation of threshold voltage in each configuration. A more detailed illustration—such as showing relative band alignment near the source and drain regions—would improve clarity and accessibility for a broad readership.\nReply: We thank the reviewer for the valuable suggestions. We have provided a more detailed illustration for the energy-band representation of bias-gated operation in the revised version (see new Fig. 2c). In S-Gated mode, the electron injection barrier is widened due to the bias-gated electrostatic (negative potential relative to the drain). Therefore, a higher V is required to open the carrier transport channel compared to the Ref. FET. In D-Gated mode, the bias-gated electrostatic (positive potential relative to the source) near the drain can facilitate carrier transport acceleration, while exerting negligible influence on electron injection at the source. Consequently, the asymmetry of the bias-induced-barrier-extending effect enables threshold-adaptive field-effect characteristics of BG-FET.\nNew Fig. 2. c, Schematic illustration of energy band diagrams for BG-FET in D-Gated mode and in S-Gated mode compare to Ref. FET.\n2. Benchmarking of inverter performance\nThe reported inverter gain of 157 is impressive for a 2D logic circuit. However, the discussion would benefit from benchmarking against representative results from prior 2D logic demonstrations or conventional CMOS technologies. A brief comparative analysis emphasizing key metrics such as gain, noise margin, and switching sharpness would help position the proposed GLB within the broader context of state-of-the-art 2D logic performance.\nReply: We thank the reviewer for the constructive suggestions. We have provided a brief comparative analysis with other representative 2D-based inverters in the revised version ((see new Supplementary Table 1). The performance metrics of our BG-inverters demonstrate competitive results at the current device scale, and there remains significant potential for further optimization through continued device engineering and process refinement.\nNew Supplementary Table 1. Comparison of inverter performance with previous reports.\nStatic\nChannel Peak Noise RC\nV (V) power (peak Scalability Ref.\ndd\nmaterials gain margin delay\nvalue)\nGLB type\nThis\nMoS 1~5 30~157 1~9 nW >87% 160 μs Yes\nCMOS type\nMoS -BP 1~2 8~13 100~200 nW N/A 0.15 s No Ref.6\n2\n1~3 N/A < 100 pW N/A 40 μs Yes Ref.7\n1~4 2~19 3~74 nW N/A N/A No Ref.8\nMoS -WSe\n2 2\n0.1~2 1~110 0.2 nW~1 μW >87% >500 μs No Ref.9\n0.5~1 11~14 21nW~0.34 μW N/A N/A No Ref.10\nMoS -MoTe 1~5 3~33 0.4~4 nW <79% ~24 μs No Ref.11\n2 2\n1.5~5.5 40~340 8 nW~2 μW >90% N/A No Ref.12\nWSe\n2\n3~5 20-110 0.1~1 nW >60% 120 μs No Ref.2\nNMOS type\n2 43 12 nW\nMoS Ref.13\n2\n4 107 Yes\nN/A N/A\nMoS 5 20 N/A Ref.14\n2\n3. Dynamic reconfigurability demonstration\nThe reconfigurability of the GLB is effectively shown through static bias configurations, but its dynamic behavior remains unexplored. Including a brief experiment or supplementary figure demonstrating real-time switching between two logic modes (e.g., AND ↔ OR) would substantially strengthen the claim of electrical reconfigurability and distinguish this platform from previously reported static architectures.\nReply: We thank the reviewer for the insightful suggestions and apologize for the unclear demonstration in the previous version. In fact, the measured output waveforms of GLB in Fig. 4e is a real-time switching between various logic modes (e.g., basic logic gates, half adder and MUX) at a 2 V full-scale square input signal of 20 Hz.\n4. Scalability and energy considerations\nThe scalability and energy implications of the bias-gated architecture are not yet discussed. It would be valuable to include a short paragraph commenting on potential challenges—such as leakage current, bias overhead, and interconnect complexity—when scaling to higher integration levels. This discussion would provide a more comprehensive view of the feasibility of extending the GLB concept toward large-scale reconfigurable 2D logic systems.\nReply: We thank the reviewer for the forward-looking suggestions. In fact, the scalability and energy of BG-FET has also been a concern for us. As the dimension of transistors continues to downscale to enable higher integration density, the extended source/drain design may enhance short-channel effects, leading to increased leakage current or loss of the threshold-adaptive field-effect characteristics. In response to the potential challenges, we have fabricated BG-FETs with a channel length of 200 nm to explore its scalability (see Fig. R1). We find that small-sized BG-FETs still exhibit excellent switching characteristics with a I < 1 pA and threshold-adaptive field-effect characteristics.\nOFF\nFig. R1. BG-FETs with a channel length of 200 nm. a, Optical image of the devices. Scale bar: 10 μm. b, SEM image of the device . Scale bar: 1 μm. c, Transfer characteristics of three BG-FETs in D-Gated mode and S-Gated mode at V = 1 V.\nDS\nAs for the energy consumption, in fact, the purpose of the GLB design is to reduce the circuit complexity at the hardware level. As shown in the “GLB-based digital circuits” section of the previous version, we regard GLB as a whole and cascade it to achieve different complex logic functions through different programming schemes. This may increase the algorithm difficulty at the software level, but we think that GLB design will simplify the circuit at the hardware level. In our ongoing research, we are actively exploring the electrical characteristics of BG-FETs with even shorter channel lengths (<50 nm) to comprehensively understand their scalability and energy consumption. These findings will be incorporated in our future work, as they are crucial for large-scale reconfigurable 2D integrated circuits manufacturing.\n5. System-level circuit considerations\nThe demonstration of sequential circuits (D-latch, D-flip-flop, and T-flip-flop) serves as a meaningful validation of the GLB concept. Nevertheless, the discussion could be strengthened by addressing signal propagation, synchronization, and timing stability when cascading multiple GLBs in larger logic networks. A brief consideration of signal restoration, clock distribution, and potential strategies for maintaining bias uniformity would enhance the manuscript’s system-level perspective.\nReply: We sincerely thank the reviewer for the forward-looking suggestions. System-level circuit manufacturing is indeed a future direction for us, and we have planned to explore the application potential of GLB design in larger logic networks through functional simulation and experimental verification of dual loops. Before that, we first need to spend time statistically verifying the uniformity of BG-FETs. We fabricate an array of 256 BG-FETs distributed across 16 dies, with each die comprising 16 individual devices (see new Supplementary Fig. 2).\nNew Supplementary Fig. 2. a, Optical image of an as-fabricated BG-FET array with 16 dies covering 256 devices. Scale bar: 500 μm. b, Partial enlarged view of a field with four BG-FETs in one die with four fields. Scale bar: 20 μm.\nAll devices were fabricated on a continuous MoS₂ thin film under identical process parameters. Subsequently, four BG-FETs were randomly selected from four fields in each die for electrical characterization, yielding a total of 64 devices spread out to study uniformity over a large area. The transfer characteristics of BG-FETs under D-Gated and S-Gated modes are tested, as shown in new Fig. 2g. The transistors exhibit excellent threshold-adaptive field-effect characteristics and a desired uniformity. Besides, the statistical histogram of V (reference voltage, defined as the V required when the I is equal to 1 nA) difference in two modes is concentrated between 0.54-0.6 V (see the inset of new Fig. 2g), which lays a solid device foundation for future system level circuit manufacturing.\nREF\nGS\nDS\nNew Fig. 3. g, Transfer curves of 64 BG-FETs in D-Gated mode and S-Gated mode at V = 2 V. Set V voltages equal to the V when I is 10-9 A. The inset is statistical histogram of ΔV for BG-FETs under two operation modes.\nDS\nREF\nGS\nDS\nREF\n6. Static power characterization\nTo more clearly elucidate the static power consumption characteristics of the proposed logic circuit, it is recommended that the authors provide the dependence of the inverter current (Idd) on the input voltage during operation. This would give a more complete picture of power behavior under different biasing conditions.\nReply: We thank the reviewer for this constructive suggestion and accept it. We have provided the dependence of the inverter current (I ) on the input voltage during operation in the revised version (see new Supplementary Fig. 3f). The peak static current of the inverter is less than 2 nA at V = 5 V.\ndd\nDD\nNew Supplementary Fig. 3. f, The static current (I ) curves of the BG-inverter as a function of V under different V .\ndd\nIN\nDD\n7. Scaling and frequency limits\nTo further underscore the technological potential of this approach, a concise theoretical discussion on the ultimate scaling limits of the device dimensions and the upper frequency bound of circuit operation is encouraged. Such analysis would help clarify the long-term prospects of this bias-gated architecture.\nReply: We thank the reviewer for the forward-looking suggestions. In theory, 2D material-based FETs can be scaled down to 10 nm in channel length due to the atomic thickness and excellent field effect characteristics of the 2D materials19-21. As for our BG-FET, introducing extended bias-gated electrode may lead to more severe technical challenges, just like the current advanced GAA device architecture. As demonstrated in Fig. R1, the as-fabricated BG-FET with a channel length of 200 nm maintains excellent switching characteristics while preserving its threshold-adaptive field-effect properties. In our ongoing research, we are actively exploring the electrical characteristics of BG-FETs with even shorter channel lengths (<50 nm) to comprehensively understand their scaling potential and performance limits. These findings will be incorporated in our future work, as they are crucial for practical applications of BG-FET technology.\nFor the upper frequency bound of circuit operation, mainly due to the RC delay in dynamic switching process. RC delay depends on the value of the parasitic resistance and capacitance where the capacitance is mainly determined by the device size. As the dimension of transistors continues to downscale to enable higher integration density, the capacitance and resistance of single transistor will sharply decrease1,2. And note that the switching speed or dynamic power is primarily determined by the transistor count at the circuit level. Given this, compared to conventional CMOS architectures, our GLB-based circuits that consume fewer transistors can exhibit a superior frequency upper bound under identical process conditions.\n8. Full-swing output characteristics\nFinally, it is recommended that the authors elaborate on the mechanism responsible for achieving full-swing voltage output in the logic circuit. A more detailed explanation would help emphasize the advantage of the proposed approach over conventional NMOS-based designs, which typically exhibit threshold voltage–related signal degradation.\nReply: We thank the reviewer for the constructive suggestions and have added a more detailed explanation on the mechanism responsible for achieving full-swing voltage output in the GLB circuit. As stated by the reviewer, typical n-type pass-transistor produces a strong logic ‘0’, but it produces a weak logic ‘1’ by lowering the output below V - V , where V is the threshold voltage of the n-FET. One possible solution to this problem is to adjust the V of the n-FETs such that it approaches 0 V or becomes negative. However, this method results in substantially increased static power in the circuit due to the n-FET being in a normally ‘ON’ state.\nDD\nTHn\nTHn\nTHn\nNew Supplementary Fig. 10. The operating principle of the GLB circuits with a full-swing output based the schematic diagram of circuit design.\nFor the GLB circuits, we take the circuit diagram of the GLB architecture as an example for analysis, noting that the upper and lower sections of GLB are fully symmetrical. As shown in new Supplementary Fig. 12, in the case where V inputs logic ‘1’ and V inputs logic ‘0’, BG-FET operates in D-Gated mode (functioning as a relative depletion-mode transistor) to ensure full-swing output, while BG-FET operates in S-Gated mode (functioning as a relative enhancement-mode transistor) to suppress the rise in path current. This design principle is analogous to the n-FET/p-FET complementary structure in CMOS technology. However, instead of relying on carrier-type complementarity, the GLB circuit employs DG-FET/SG-FET complementarity, where DG-FET refers to BG-FET operating in D-Gated mode (depletion-like behavior) and SG-FET refers to BG-FET operating in S-Gated mode (enhancement-like behavior).\nWe sincerely thank the reviewer again for these forward-looking suggestions, which provides important inspiration and guidance for our future work.\nReference:\nReviewer #3 (Remarks to the Author):\nSummary\nThis research presents an asymmetric MoS2 FET architecture as a foundation for high-density reconfigurable logic. MoS2 FET has been demonstrated into a generic logic block. MoS2-based GLB reduced the transistor count by over sixty percent versus equivalent CMOS circuits. Simple bias control toggles operation between source-gated and drain-gated modes. The block dynamically implements various logic functions, including inverter, half adder, multiplexer, encoder, and SRAM within one circuit. While the work is well-structured and the data are compelling, several points require clarification and revision before the manuscript can be deemed suitable for publication in this journal.\nReply: We sincerely thank the reviewers for the careful reading and suggestive feedback, and we have made the following revision to our manuscript according to your valuable suggestions and comments.\nMajor comments\n1. The manuscript provides insufficient information regarding Sb2O3. Unlike HfO2, Sb2O3 is not a commonly used dielectric material. Therefore, the authors should clarify why it was chosen, specify its thickness, and cite appropriate references [1, 2] that support its use. In addition, detailed information on the deposition process of the Sb2O3 buffer layer during device fabrication is required.\nReply: We thank the reviewers for these important points and apologize for neglecting the detailed analysis of Sb O in the previous version. The dangling-bond-free surface of 2D materials presents challenges for the direct growth of 3D high-κ dielectrics (e.g., HfO or Al O ) via conventional silicon-based atomic layer deposition (ALD) techniques. Here, we choose the van der Waals crystal Sb O as a buffer layer to form a high-quality oxide-to-semiconductor interface, enabling the integration of high-κ dielectrics via atomic layer deposition22,23. Moreover, a van der Waals gate dielectric interface can better maintain the intrinsic properties of the underlying 2D materials, which also helpful for improving the uniformity and stability of 2D electronics. Finally, we have added relevant information in the revised version, such as the thickness and deposition process of the Sb O , as well as key reference support.\n2 3\n2 3\n2 3\n2 3\n2. The authors seem to emphasize the advantage of the van der Waals interface formed by Sb2O3 to enhance device performance. If that is the case, why was this material applied only in the top-gate configuration? In the BG inverter, part of the channel electrons accumulated on the upper side may indeed benefit from a clean interface, whereas in the Ref inverter, all channel electrons accumulate at the bottom interface, which is likely degraded by the ALD-grown HfO2. This raises concerns about the fairness of the comparison, as the two devices may not be under equivalent interfacial conditions.\nReply: We thank the reviewers for the careful reading and questioning. As mentioned in the previous version, in order to compare the field-effect characteristics of BG-FET and Ref. FET more fairly, the fabrication processes of two devices are completely identical, except that an asymmetrically extended bias-gated electrode is added to the BG-FET. We deliberately choose the van der Waals crystal Sb O as a buffer layer to ensure that the intrinsic properties of the underlying 2D-channel materials are consistent for both devices (in fact, the Ref. FET itself does not require deposition of top gate dielectric). Moreover, our focus is on the V of the BG-FET-based inverter (BG-inverter) shifts from approximately -0.15 V to 0.59 V compared with Ref. FET-based inverter, not performance comparison. Noticeably, an inverter that loses the cascaded function due to input and output not in the same range is strictly referred to as an invalid circuit.\n2 3\nM\nAs for the partial electrons accumulated on the upper side, it is precisely the phenomenon we want to see after introducing the bias-gated structure. Finally, we also agree that using the Sb O as a buffer layer or other van der Waals dielectrics for gate-all-around is an important direction for realizing high-performance 2D electronics.\n2 3\n3. In Figure 3c, the authors compare the gain of the BG and Ref inverters only at VDD = 2 V, while Figures 3d and 3e present parameters solely for the BG inverter. Can the authors confirm that the BG inverter still shows similar or superior performance compared to the Ref inverter across all VDD values when considering parameters such as VM, gain, Pstatic, peak, and NM/VDD? A more comprehensive comparison, like Supplementary Figure 1, seems necessary. Moreover, including the V₍M₎ shift of 0.06 V (mentioned in Supplementary Figure 2b) directly in Figure 3d would make the data presentation more compelling.\nReply: We thank the reviewers for the careful reading. Accepting the constructive comments, we add a more comprehensive comparison of BG-inverter and Ref. inverter in the revised version. As demonstrated in new Supplementary Fig. 3, the BG-inverter and Ref. inverter both exhibit a full-swing output but with different switching threshold voltage (V ). The V of the BG-inverter shifts from approximately -0.15 V to 0.6 V compared with Ref. inverter. As for the parameters of gain and I show similar performance across all V values, where a peak gain of 157 for BG-inverter and of 159 for Ref. inverter are achieved at V = 5 V. A peak I of less than 2 nA for BG-inverter and of less than 5 nA for Ref. inverter are also achieved at V = 5 V. And a high noise margin (NM ) of∼0.56 V and a low noise margin (NM ) of∼0.53 V are extracted at V = 1.2 V, and the total NM is greater than 90% of V , indicating the high noise tolerance of the BG-inverter. Noticeably, the Ref. inverter that loses the cascaded function due to input and output not in the same range is strictly referred to as an invalid circuit. Moreover, the V shift of 0.06 V for BG-inverter under different V is more directly shown in the revised Fig. 3d.\nM\nM\nDD\nDD\nDD\nDD\nH\nL\nDD\nDD\nM\nDD\nNew Supplementary Fig. 3. Comparison of the static characteristics of the BG-inverter and Ref. inverter. a-b, Output characteristics of the load and driver under a given V from 0 to 0.9 V for BG-inverter (a) and under a given V from -0.5 to 0.2 V for Ref. inverter (b) at V = 5 V. c, The voltage transfer curve (VTC) and its mirror reflection of the BG- inverter with a switching threshold voltage V of 0.6 V at V = 1.2 V. V , V , V and V represent the minimum high-output voltage, maximum low-output voltage, maximum low-input voltage and minimum high-input voltage for the inverter, respectively. d-f, Typical voltage transfer curves (d), voltage gain curves (e), and static current curves (f) of BG-inverter as a function of V under different V . g-i, Typical voltage transfer curves (g), voltage gain curves (h), and static current curves (i) of Ref. inverter as a function of V under different V .\nIN\nIN\nDD\nM\nDD\nOH\nOL\nIL\nIH\nIN\nDD\nIN\nDD\n4. It would be beneficial to show the corresponding IOUT values for VIN = 0.9 V and 1.0 V in Supplementary Figure 2a. The current crop graph looks incomplete and visually unappealing.\nReply: We thank the reviewers for pointing out this point. In fact, the display in previous Fig. S2a is a common method used to highlight the input voltage when the output current of the load and driver are equal24. We have also provided the complete output current curves of BG-inverter at the different input voltages, as shown in new Supplementary Fig. 3a.\n5. The Device Fabrication section lacks information on the e-beam lithography system used. Furthermore, for the CVD-grown MoS₂, details such as the precursor materials, film thickness, and lateral dimensions are missing.\nReply: We thank the reviewers for pointing out the missing information. We have added relevant information of the e-beam lithography system in the revised version. Moreover, the channel material we selected is CVD-grown single-layer MoS films. More detailed growth parameters can refer to our previously published work25.\n2\n6. Supplementary Figures 1a–c appears to show the same output characteristics, but the reason for dividing VGS around 1 V is unclear. In Figures 1b and 1c, VDS is extended to 5 V, which makes VSAT variations difficult to observe and instead highlights the difference in IDS magnitude. Reducing the axis range and marking VSAT as done in Figure 1a could better emphasize the VSAT shift. Why was VSAT not explicitly indicated? In addition, in Figure 1f, the y-axis should be plotted linearly to enable a more accurate comparison of VSAT.\nReply: We thank the reviewers for the careful reading and questioning. As mentioned by the reviewer, reducing the axis range can better emphasize the V shift. However, as V further increases, the V rises correspondingly, necessitating an extended bias range to achieve a fully saturated output characteristic. Therefore, we divide the output curve at V of 1 V, emphasizing the V shift in small bias range and extracting more intuitive data comparison in the large bias range for presentation in Supplementary Fig. 1e-f. And the y-axis in Supplementary Fig. 1f has also been plotted linearly to enable a more accurate comparison of V in the revised version.\nSAT\nGS\nSAT\nGS\nSAT\nSAT\n7. While Figures 2 and Supplementary Figure 1 present a comparison between the BG-FET and Ref-FET, the main text only highlights the advantages of VSAT and VM in the BG-FET. Supplementary Figure 1, however, lacks any corresponding discussion. The authors should address the lower subthreshold swing and Ion observed in the BG-FET compared to the Ref-FET. How do these trade-offs impact the implementation of generic logic blocks?\nReply: We thank the reviewers for the careful reading and the constructive comments. Firstly, we apologize that our focus is not on comparing the performance of BG-FET and Ref. FET. As shown in Fig. 2, our focus is on the threshold-voltage adaptive characteristics achieved by the asymmetric nature of BG-FET. The comparison of the field-effect characteristics of BG-FET and Ref. FET in Supplementary Fig. 1 is to preliminarily confirm the effectiveness of the bias-gated structure design. And we have also added more detailed discussions for Supplementary Figure 1 in the revised version. Secondly, the implementation of generic logic blocks (GLBs) mainly relies on the threshold-voltage adaptive characteristics of BG-FET. As shown in Fig. 3c, the Ref. FET-based inverter can achieve logic inversion function, but it does not have a rail-to-rail output characteristics, which makes it impossible to further cascade, strictly defined as an invalid circuit. As for subthreshold swing (SS) and I of transistor, they are key on indicators for evaluating the power consumption and performance of logic devices. And the improved SS and I of BG-FET can be achieved with the optimization of fabrication process.\non\n8. In Supplementary Fig. 10a, the truth table appears to be incorrect, and there is no clear correlation between the listed truth table and the voltage signal-time plot.\nReply: We sincerely thank the reviewers for pointing out the error and we have corrected it, as shown in new Supplementary Fig. 11a. This comparison circuit can accurately determine the numerical size of two 1-bit binary codes according to the truth table. That is, value A is less than B when Y outputs logic ‘0’, value A is equal to B when Y outputs logic ‘0’ and value A is greater than B when Y outputs logic ‘0’. Note that the three output signals of this comparator have only one is logic ‘0’ at the same time, otherwise, the circuit is impossible.\nA<B\nA=B\nA>B\nNew Supplementary Fig. 11. a, Truth table of a 1-bit digital comparator.\n9. In lines 95-99, the authors describe that the dependence of VSAT on VGS decreases as the LBG/Lch ratio increases. However, this is currently presented only as an experimental observation. It would be valuable if the authors could provide a more detailed physical explanation in conjunction with the operational principles of the S-Gated and D-Gated modes discussed in lines 120-127 from the perspectives of device structure, electrostatic potential distribution, and carrier transport path. In addition, the authors are encouraged to include relevant references supporting these interpretations.\nReply: We thank the reviewers for the constructive comments and apologize for the neglecting of a detailed physical explanation of BG-FET in the previous version. In order to facilitate the understanding of the BG-FET by reviewers and readers, we have added the pinch-off mechanism of BG-FET and Ref. FET in the revised version (see new Fig. 2e). By definition, the V corresponds to the drain-source voltage (V ) at which the drain-source current (I ) reaches saturation, equivalent to the V required for transistor pinch-off. As V increases, the depletion region of Ref. FET occurs at drain until the channel is pinched off and V is defined. In S-Gated mode, however, the depletion of BG-FET occurs both in drain and source due to the extended bias-gated electrode26-28. The source-side depletion region progressively expands towards the drain with the increasing V due to the bias-gated electrostatic (maintained at a negative potential relative to the drain), enabling the BG-FET to be pinched off prematurely and a smaller V is defined.\nSAT\nDS\nDS\nDS\nSAT\nDS\nDS\nSAT\nNew Supplementary Fig. 2. e, Comparison of pinch-off mechanism of two devices. As bias increases, compared with the depletion region of Ref. FET only appearing at drain terminal, the depletion region of BG-FET occurs at both source and drain terminals. And as the L /L ratio increases, the control region dominated by the bias-gated electrode expands, while the region regulated solely by V contracts. This shift enhances the electrostatic influence of the bias-gated electrode on V while reducing the impact of V . This controllable modulation of this competition relationship allows for the on-demand design of subsequent logic circuits.\nBG\nch\nGS\nSAT\nGS\n10. In lines 88 and 180, the authors state that the BG-FETs were fabricated under identical process parameters. While this indicates that the devices were processed under the same fabrication conditions, it does not necessarily guarantee uniform electrical performance. Therefore, statistical verification (e.g., device-to-device variation in Vth, Ion, and Ioff) is required to substantiate the claim of device uniformity. In fact, CVD-grown 2D materials are known to suffer from uniformity challenges (see 10.3390/ma14247590) [3]. Moreover, demonstrated noticeable device-to-device variability even under nominally identical fabrication conditions (see 10.1038/s41467-020-20732-w) [4]. Including such statistical data or discussion would considerably strengthen the manuscript’s credibility regarding process consistency.\nReply: We thank the reviewer for the constructive comments and agree that demonstrated device-to-device variability even under nominally identical fabrication conditions. Accepting the forward-looking suggestions, we fabricate an array of 256 BG-FETs distributed across 16 dies, with each die comprising 16 individual devices (see new Supplementary Fig. X).\nNew Supplementary Fig. 2. a, Optical image of an as-fabricated BG-FET array with 16 dies covering 256 devices. Scale bar: 500 μm. b, Partial enlarged view of a field with four BG-FETs in one die with four fields. Scale bar: 20 μm.\nNew Fig. 2. g, Transfer curves of 64 BG-FETs in D-Gated mode and S-Gated mode at V = 2 V. Set V voltages equal to the V when I is 10-9 A. The inset is statistical histogram of ΔV for BG-FETs under two operation modes.\nDS\nREF\nGS\nDS\nREF\nAll devices were fabricated on a continuous single-crystal MoS₂ thin film (source: as in Q5 above) under identical process parameters. Subsequently, four BG-FETs were randomly selected from four fields in each die for electrical characterization, yielding a total of 64 devices spread out to study uniformity over a large area. The transfer characteristics of BG-FETs under D-Gated and S-Gated modes are tested, as shown in new Fig. 2g. The transistors exhibit a desired uniformity and threshold-adaptive field-effect characteristics. Besides, the statistical histogram of V (reference voltage, defined as the V required when the I is equal to 1 nA) difference in two modes is concentrated between 0.54-0.6 V (see the inset of new Fig. 2g), indicating a low device-to-device variability. This desired uniformity of BG-FETs can be attributed to the bias-gated structure design with a built-in packaging function for maintaining the integrity of the channel materials, except for the high stability of the grown MoS .\nREF\nGS\nDS\n2\n11. While conventional CMOS inverters experience electrical stress only when the transistors are in the ON-state, each BG-FET within the GLB is subjected to various static and dynamic bias conditions depending on the programmed logic function. Such complex stress profiles could lead to asymmetric aging among the devices, causing imbalanced degradation within the same GLB and potentially resulting in circuit malfunction over time. In other words, the reconfigurable nature of the GLB, though advantageous for functionality, may pose a reliability trade-off. Therefore, it would significantly strengthen the manuscript if the authors could provide experimental data on the long-term stability of the BG-FETs such as threshold voltage shifts, mobility/temperature stability, or bias-stress endurance tests (e.g., TDDB, PBS/NBS).\nReply: We thank the reviewer for the forward-looking suggestions. The stability of the BG-FET has also been a concern for us, in fact, and we have presented experimental data on the cycling reliability of the BG-FET-based inverter in the previous version (see Supplementary Fig. 3 or new Fig. 3f). It can be clearly seen that the inverter can maintain a full-swing output response at a 2 V full-scale square input signal of 100 Hz, even after 1,000 switching cycles.\nNew Fig. 3. f, Cyclic reliability of the BG-inverter at a 2 V full-scale square input signal of 100 Hz for more than 1000 switching cycles.\nMoreover, to further strengthen the manuscript, we have also added more experimental data on the long-term stability of the BG-FET. As shown in new Fig. 2h, the BG-FETs maintain excellent threshold-adaptive field-effect characteristics after seven weeks in vacuum atmosphere and the ΔV of approximately 0.57 V between the two operating modes (S-Gated and D-Gated) showed negligible variation throughout this period.\nREF\nNew Fig. 2. h, Transfer curves of the BG-FET placed in the vacuum atmosphere for 1 week, 4 weeks, 7 weeks. The inset corresponds to the variation of ΔV . i, Transfer curves of the BG-FET under different temperatures. The inset corresponds to the variation of ΔV at 293, 320, 360 and 400 K.\nREF\nREF\nTo further explore the temperature stability of BG-FET, we electrically characterized the devices at 293, 320, 360 and 400 K (see new Fig. 2i). The BG-FETs exhibit impressive threshold-adaptive field-effect characteristics even at high temperature of 400 K. Note that the threshold voltage of the BG-FET exhibits a negative shift with increasing temperature. This phenomenon can be attributed to the enhanced thermal activation of free carriers at elevated temperatures29,30. Furthermore, a larger shift amplitude is observed in S-Gated mode, leading to a progressive decrease in ΔV . This may be due to the release of more free carriers bound by the widened barrier induced by bias-gated electrostatic at high temperatures. This behavior may arise from the sudden release of more free carriers that are previously bound by the widened barrier due to bias-gated electrostatic. Finally, the excellent stability of BG-FET can be attributed to the bias-gated structure design with a built-in packaging function for maintaining the integrity of the channel materials, except for the high stability of the grown MoS .\nREF\n2\n12. It is generally known that SGTs exhibit lower on-current and larger SS compared to conventional transistors. However, your device shows no significant difference from the reference device except for the Vth shift. Could you address the possible reasons for its superior performance?\nReply: We thank the reviewers for the careful reading and questioning. The core feature of SGT (source-gated transistors) is the existence of a barrier near the source, which is jointly controlled by the gate and source to regulate carrier injection. In theory, if the gate can effectively modulate the barrier (such as high-κ dielectric materials), the SS of SGT can also approach the theoretical limit (60 mV/dec). As for BG-FET in S-Gated mode, the widened barrier caused by the extended bias-gated electrode has excellent gate-tunable characteristics, which means the BG-FET can also reduce SS through process optimization, such as high-κ gate dielectric technology22,31\nNew Fig. 2. f, Transfer curves of BG-FET and Ref. FET under the same testing conditions. Set V voltages equal to the V when I is 10-9 A.\nREF\nGS\nDS\nAs for on-current of BG-FET in S-Gated mode, a larger V for BG-FET is required to achieve the same current due to the widened electron injection barrier. The maximum difference of I under the same V exceeds three orders of magnitude in the sub-threshold region (see in Supplementary Fig. 1d or new Fig. 2f). As the V increases, this difference gradually decreases and tends to be consistent, because the electron density in the channel is gradually dominated by V .\nGS\nDS\nGS\nGS\nFinally, as mentioned above, our focus is on the threshold-voltage adaptive characteristics achieved by the asymmetric nature of BG-FET. And we apologize for neglecting a deeper discussion on the key performance indicators, such as SS and I of BG-FET. Which also points out an important direction for us to improve the performance of BG-FET-based logic circuits in the future.\non\n13. Because the SG FET operates based on barrier-controlled conduction, its characteristics are highly sensitive to temperature. Therefore, information about the specific temperature at which all measurements were conducted must be provided.\nReply: We sincerely thank the reviewers for the constructive suggestion. All measurements for BG-FET, GLB and GLB-based logic circuits are conducted at room temperature. And we have also updated this information to the methods section in the revised version.\nMinor comments\n1. The scale bar is missing in Figure 4b.\nReply: We sincerely thank the reviewer for pointing out this error and have added the scale bar in the revised Figure 4b.\n2. The term “BG-RFET” is used only once in line 296. It would be better to maintain consistent terminology throughout the manuscript by using “BG-FET” instead.\nReply: We sincerely thank the reviewer for pointing out this error and have corrected all ‘BG-RFET’ to ‘BG-FET’ in the revised version.\n3. In Supplementary Fig. 5a, when both A and B are set to 1, the Sum output should be 0. However, it is incorrectly listed as 1 in the truth table.\nReply: We sincerely thank the reviewer for pointing out the error and have corrected the truth table in the revised version.\n4. In Supplementary Fig. 5d, the (S, A, B) labeling is duplicated as (0, 0, 0) and (0, 0, 1). The labels should be revised to correctly reflect the intended sequence of (S, A, B).\nReply: We sincerely thank the reviewer for pointing out the error and have corrected the labels in the revised version.\n5. In Supplementary Fig. 9a, the partial product expression seems to contain a typographical error. The second partial product row should be corrected from A1B0, A0B0 to A1B1, A0B1 to accurately represent the 2-bit multiplication process.\nReply: We sincerely thank the reviewer for pointing out the error and have corrected the partial product row in the revised version.\nReferences\n1. Gao, Q. et al. Scalable high performance r Liu, K., Jin, B., Han, W. et al. A wafer-scale van der Waals dielectric made from an inorganic molecular crystal film. Nat Electron 4, 906–913 (2021).\n2. Liu, Y., Hone, J.C. Hybrid dielectrics for two-dimensional electronics. Nat. Mater. 22, 1059–1060 (2023). https://doi.org/10.1038/s41563-023-01642-w\n3. Seravalli, Luca, and Matteo Bosi. \"A review on chemical vapour deposition of two-dimensional MoS2 flakes.\" Materials 14.24 (2021): 7590.\n4. Sebastian, Amritanand, et al. \"Benchmarking monolayer MoS2 and WS2 field-effect transistors.\" Nature communications 12.1 (2021): 693.\nReference:\n2\n2"}, {"round": 2, "reviewer_comments": {"reviewer_1": "I appreciate the authors’ efforts in performing additional dynamic characterization, which makes the overall characterization more complete. However, I still have two concerns regarding the authors’ response.\nRegarding my Comment 2:\nThe authors appear to argue that the bias-gate design can potentially improve, rather than worsen, short-channel effects. However, they do not provide a clear explanation of how the bias-gate design modifies specific short-channel effects, such as drain-induced barrier lowering. Instead, they rely on comparisons to extended source/drain designs in silicon CMOS technology and the gate-all-around technique in 2D semiconductor channels (Ref. 5) to justify the role of their bias-gate design. These device architectures are fundamentally different from the bias-gate structure proposed in this paper, where the source/drain region is connected to a short gate. Therefore, it is not valid to use effects observed in these other architectures to explain the role of the bias-gate design in the short-channel regime of the proposed device.\nFurthermore, References 3-4 discuss thin-film source-gated transistors, whose architecture also differs significantly from that of a typical MOSFET. These devices utilize Schottky contacts and rely on the resulting depletion regions to suppress short-channel effects. This operating principle is not applicable to the bias-gate structure proposed here. Citing these irrelevant device designs and references to defend the proposed mechanism is misleading and inappropriate, which undermines the technical credibility of the work.\nRegarding my Comment 3:\nThanks for the clarification on the device characterization. It is now clear that the proposed GLB is effectively a 6-input, 2-output system. Nevertheless, this raises a more fundamental concern: how can the relationships among the different inputs be well-defined and enforced in a practical integrated-circuit implementation?\nThe gates demonstrated in Fig. 4 are mostly 2-input, 1-output blocks. Since only two inputs are logically required, defining and maintaining the relationships among the remaining four inputs will inevitably require additional circuitry. For example, in the AND/NAND case, Vin-p1 and Vin-p3 are inverted versions of each other, which would require an inverter. In contrast, in the 2-to-1 MUX case, Vin-p1 and Vin-p3 must be independent signals. Similarly, Vin-p2 and Vin-c are identical for AND/NAND but inverted for OR/NOR, etc. Reconfiguring these inputs would require switches to manage shorted connections, inversions, or disconnections, necessitating additional circuitry.\nThis highlights a significant overhead cost for the claimed “reconfigurable logic.” The current demonstration does not account for the peripheral circuits required to generate and manage these input relationships. These circuits are critical for achieving true reconfigurability, but they are neither explicitly presented nor discussed. Consequently, whether the proposed reconfigurability actually leads to a reduced transistor count in practical implementation remains an unanswered question.", "reviewer_2": "The authors have satisfactorily addressed all of my comments. I therefore recommend this manuscript for publication.", "reviewer_3": "Following the referees' comments, the authors had taken much effort to answer the questions arising from the previous manuscript. Therefore, I would like to recommend publishing the manuscript in the present form."}, "author_response": "Reply: We sincerely appreciate the reviewer for carefully reading the reply letter and revised manuscript, and affirmation of our work. Below are our detailed responses to remaining concerns.\nRegarding my Comment 2:\nThe authors appear to argue that the bias-gate design can potentially improve, rather than worsen, short-channel effects. However, they do not provide a clear explanation of how the bias-gate design modifies specific short-channel effects, such as drain-induced barrier lowering. Instead, they rely on comparisons to extended source/drain designs in silicon CMOS technology and the gate-all-around technique in 2D semiconductor channels (Ref. 5) to justify the role of their bias-gate design. These device architectures are fundamentally different from the bias-gate structure proposed in this paper, where the source/drain region is connected to a short gate. Therefore, it is not valid to use effects observed in these other architectures to explain the role of the bias-gate design in the short-channel regime of the proposed device.\nFurthermore, References 3-4 discuss thin-film source-gated transistors, whose architecture also differs significantly from that of a typical MOSFET. These devices utilize Schottky contacts and rely on the resulting depletion regions to suppress short-channel effects. This operating principle is not applicable to the bias-gate structure proposed here. Citing these irrelevant device designs and references to defend the proposed mechanism is misleading and inappropriate, which undermines the technical credibility of the work.\nReply: We thank the reviewer for carefully reading the reply letter and questioning. We agree that gate-all-around or source-gated transistors are different from the proposed BG-FET. In reality, we borrowed these device architectures to express that the extended source design can enhance vertical gate control and improves the shielding effect of the source on the drain field, thus exhibiting strong immunity to short-channel effects (SCEs).\nIn order to discuss the SCEs of BG-FET more intuitively, we have provided the energy band diagram of BG-FET and Ref. FET in long channel and short channel, respectively (see Fig. R1). At the same drain voltage, the drain electric field will increase with the shortening of the channel length. In S-Gated mode, the bias-gated electrostatic (negative potential relative to the drain) due to extended source design can shield the effect of the drain electric field. Therefore, the BG-FET possesses a better immunity to drain control compared to Ref. FET where the channel barrier decreases dramatically due to the increase in drain field.\nFig. R1. Schematic illustration of energy band diagrams for BG-FET in in long channel (left) and short channel (right) compare to Ref. FET. E and E represent the conduction-band minimum and Fermi-level, respectively. Φ represents source injection barrier height.\nC\nF\nAs for the drain-induced barrier lowering (DIBL) in D-Gated mode, the bias-gated electrostatic (positive potential relative to the source) will affect the electron injection barrier at the source with the shortening of the channel length. In this case, the BG-FET may exhibit a poorer immunity to drain control compared to Ref. FET. It is noteworthy, however, that the effect of bias-induced-barrier-extending can be restored to a state consistent with Ref. FET by regulating V . And it is precisely this asymmetry that enables BG-FETs to possess threshold-adaptive field-effect characteristics through different bias modes (S-Gated and D-Gated).\nGS\nRegarding my Comment 3:\nThanks for the clarification on the device characterization. It is now clear that the proposed GLB is effectively a 6-input, 2-output system. Nevertheless, this raises a more fundamental concern: how can the relationships among the different inputs be well-defined and enforced in a practical integrated-circuit implementation?\nReply: We thank the reviewer for carefully reading the reply letter and questioning. Firstly, we regard GLB as a whole and reconfigure it into functional block required for practical integrated-circuits.\nThe gates demonstrated in Fig. 4 are mostly 2-input, 1-output blocks. Since only two inputs are logically required, defining and maintaining the relationships among the remaining four inputs will inevitably require additional circuitry. For example, in the AND/NAND case, Vin-p1 and Vin-p3 are inverted versions of each other, which would require an inverter. In contrast, in the 2-to-1 MUX case, Vin-p1 and Vin-p3 must be independent signals. Similarly, Vin-p2 and Vin-c are identical for AND/NAND but inverted for OR/NOR, etc. Reconfiguring these inputs would require switches to manage shorted connections, inversions, or disconnections, necessitating additional circuitry.\nFig. R2. Optical image of a 2-bit CSA multiplier based on 24 MoS2 BG-FETs (six GLBs and four BG-inverters). Scale bar: 100 μm.\nAs mentioned by the reviewer, the gates demonstrated in Fig. 4 are mostly 2-input, 1-output blocks. The proposed GLB as a generic logic block also follows this principle. We take the 2-bit carry-save-adder (CSA) multiplier circuit in Fig. 5 as an example, two GLBs are reconstructed as four AND gates (2-input, 1-output) to implement four partial products, two GLBs are reconstructed as two half-adders (2-input, 1-output) for partial product summation. Notably, we agree that reconfiguring these inputs would require additional circuitry, and we have explained in the manuscript that four embedded BG-inverters are also used to provide necessary complementary signals in 2-bit CSA multiplier circuit (see Fig. R2).\nThis highlights a significant overhead cost for the claimed “reconfigurable logic.” The current demonstration does not account for the peripheral circuits required to generate and manage these input relationships. These circuits are critical for achieving true reconfigurability, but they are neither explicitly presented nor discussed. Consequently, whether the proposed reconfigurability actually leads to a reduced transistor count in practical implementation remains an unanswered question.\nMoreover, we strongly agree that system-level on-chip reconfigurability needs a significant overhead cost. Similar to FPGA (field programmable gate array) requires massive routing switches except the critical PLBs (programmable logic blocks). And we have also indicated that complex circuits such as multipliers or flip-flops in Fig. 5 demonstrate no reconfigurability. The implementation of reconfigurable GLB-based circuits in larger logic networks is a huge undertaking, but it is also a promising and interesting research direction for future work.\nFinally, the GLB-based multiplier with 24 BG-FETs (six GLBs and four BG-inverters) can indeed offer a transistor count reduction of nearly 60% compared to CMOS deign required more than 58 transistors. The GLB design may increase the algorithm difficulty at the software level, but we think that it will simplify the circuit at the hardware level. And the inherent versatility of GLB design is highly beneficial for the rapid establishment of a standard unit library compared to CMOS design where each function corresponds to a specific circuit."}, {"round": 3, "reviewer_comments": {"reviewer_1": "The authors have addressed my comments with reasonable explanations. I now recommend this manuscript for publication in Nature Communications."}, "author_response": ""}]

Decision letter