Multimodal ion-gated transistor based on 2D superionic conductor for in-memory computing in deep learning

Domain: biology
Published: 2026-03-18
Editorial outcome: major_revision

Abstract
For neuromorphic computing, integrating multiply-accumulate operations and nonlinear activation within a single device can reduce latency and power consumption while improving computational efficiency. However, these operations impose conflicting requirements: multiply-accumulate requires highly linear and non-volatile resistance states, while activation requires diverse nonlinear synaptic behaviors. These contrasting demands make integrating both functions in a single device challenging. Here, we construct a multimodal ion-gate transistor using 2D CdPS3-Li as dielectric layer and MoS2 as channel material. The layered structure of CdPS3-Li facilitates anisotropic ion transport for Li+ storage and produces strong ion-electron coupling, resulting in high-linearity and non-volatile resistance states under electrical pulses. Moreover, Cd vacancies in CdPS3-Li attract and trap photo-generated holes from MoS2, leading to rich nonlinear behavior under light pulses. Therefore, the CdPS3-Li transistor can simultaneously perform both operations. The CdPS3-Li transistor arrays achieved high accuracy in handwritten digit classification, offering a promising hardware solution for neuromorphic computing.

Introduction
Brain-inspired neuromorphic computing, renowned for its low power consumption and high parallelism, is widely considered as a promising solution to overcome the von Neumann bottleneck[1-4]. The multiply-accumulate (MAC) operation and nonlinear activation are two fundamental components of neuromorphic computing[5,6]. Implementing MAC and nonlinear activation as two separate units needs digital-to-analog converters (DACs) for interconnection, resulting in power consumption that significantly exceeds that of the MAC operations alone. In contrast, integrating both functions within a single device can reduce latency, power consumption, and integration complexity, thereby improving overall computational efficiency[7,8].

However, these two operations impose distinct device requirements: MAC operation requires devices capable of producing highly linear and non-volatile resistance states, whereas nonlinear activation demands devices that can generate diverse nonlinear synaptic behaviors to introduce nonlinearity into neural networks[9-13]. These conflicting demands make the integration of both functions into a single device highly challenging.

Using electrical pulses for MAC operation and light pulses for nonlinear activation offers an effective solution to this challenge. Electrical pulses can directly perform MAC operation through crossbar memory arrays, providing high efficiency and reduced energy consumption[12,13]. Meanwhile, postsynaptic currents (PSCs) generated by synaptic devices under light pulses can be modeled by a double-exponential function, which exhibits pronounced nonlinear characteristics, thus providing a feasible means to implement activation functions (Fig. 1a). Moreover, this approach allows multiple devices to output the same nonlinear activation simultaneously, ensuring uniform activation across all devices to enable parallel computing while minimizing interference with the MAC circuitry[14-16]. Multimodal artificial synapses, which can generate non-volatile resistance states under electrical pulses and produce PSC under optical pulses, provide the hardware foundation for this paradigm (Fig. 1b).

Various multimodal synapses have been developed, modulating device conductivity through defect migration, charge trapping, material phase change, or ferroelectricity[17-21]. However, these mechanisms often cause uncontrollable stochasticity, high operation voltages, and low linearity, significantly affecting computational accuracy[22]. In contrast, ion-gated transistors using ionic conductors as dielectric layers can modulate channel conductance via ion-electron coupling by intercalating or ejecting ions. They offer advantages such as low operating voltage, low power consumption, and easy regulation[22-24]. However, existing ion-gated transistors struggle to respond to both electrical and light signals, limiting their ability to achieve multimodal functionality. Additionally, the isotropic nature of current ionic conductor dielectric layers weakens ion-electron coupling effects. This results in low conductance ratios, poor long-term synaptic plasticity, and inferior memory performance[25-29]. To address these challenges, there is an urgent need for a new type of ionic dielectric material that can precisely control ion transport, achieve non-volatile ion storage, and effectively trap photo-generated charges.

Here, we construct a multimodal ion-gate transistor using 2D CdPS3-Li as the dielectric layer and 2D MoS2 as the channel layer. The unique layered structure of CdPS3-Li facilitates highly anisotropic ion transport, resulting in the non-volatile storage of Li+ and a strong ion-electron coupling effect to generate high-linearity and non-volatile resistance states (R² ≈ 0.99, retention>104 s) under electrical pulses. Additionally, Cd vacancies in CdPS3-Li can attract and trap photogenerated holes from MoS2 through Coulombic interactions to exhibit rich non-linear dynamic behaviors (conductance ratio of 105) under light pulses. Consequently, the CdPS3-Li transistor can simultaneously perform MAC operations and implement activation functions, enabling the physical realization of the complete forward propagation process in deep learning. We further developed CdPS3-Li transistor arrays to recognize handwritten digit images, achieving an accuracy exceeding 97.5%, which offers a promising hardware solution for neuromorphic computing.

Results
The construction of multimodal CdPS3-Li ion-gated transistors

We synthesized CdPS3-Li bulk crystals by chemical vapor transport (CVT) method (Fig. 1c). According to X-ray diffraction (XRD) patterns (Fig. 1d) and Fourier transform infrared (FTIR) absorption spectra (Supplementary Fig. 1), the crystals show similar structure with the CdPS3-Li membranes assembled by monolayer CdPS3 nanoflakes containing Cd vacancies[30], where the vacancies were found to significantly boost the ion transport in the nanochannels to achieve a superhigh in-plane ion conductivity. The X-ray photoelectron spectroscopy (XPS) peak at 56 eV confirms the presence of Li+ (Fig. 1e). However, due to the small atomic number, Li+ ions were hard to be observed by high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) imaging. Notably, such crystals contain abundant Cd vacancies, as evidenced by plan-view HAADF-STEM images (Fig. 1f) and the peak splitting in FTIR spectra (Supplementary Fig. 1).

The cross-sectional HAADF-STEM images clearly reveal that CdPS3-Li crystals have a van der Waals (vdW) layered structure, with an interlayer spacing of 6.55 Å (Fig. 1g). However, the Cd vacancies enable the crystals excellent hydration ability and exceptional hydrophilicity (Supplementary Fig. 2), resulting in a significantly expanded interlayer spacing (12.5 Å) under ambient conditions (~40% RH, 28 °C) (Fig. 1d), which corresponds to the intercalation of bilayer water molecules. Importantly, the crystals intercalated with water remain the well-ordered layered structure. Such highly anisotropic layered structure leads to a significant difference in the transport barriers between the in-plane and out-plane directions. Because of the well-ordered nanochannels and widened interlayer spacing, Li+ can rapidly transport along the in-plane direction through interlayer water molecules[30-32]. In contrast, the CdPS3-Li layers strongly restrict the out-plane transport of Li+.

We fabricated 2D CdPS3-Li nanoflakes by mechanical exfoliation of bulk crystals (Supplementary Fig. 3), which have atomically flat surface. The Li+ transport characteristics of 2D CdPS3-Li nanoflakes along the in-plane and out-plane directions were investigated by impedance spectroscopy under ambient conditions. Notably, the in-plane ionic conductivity is 0.134 S cm-1, while the out-plane ionic conductivity significantly decreases to 0.0258 S cm-1 (Fig. 1h). These results demonstrated the highly anisotropic Li+ transport behavior in 2D CdPS3-Li nanoflakes. Moreover, the 2D CdPS3-Li nanoflake exhibits a high dielectric constant (5.2) comparable to SiO2 (Supplementary Note 1) and a wide bandgap (Supplementary Fig. 5). Therefore, 2D CdPS3-Li nanoflake is expected to be an ideal dielectric layer to construct ion-gated transistors.

We further constructed CdPS3-Li ion-gated transistor (Fig. 2a) by using 70 nm-thick CdPS3-Li as the dielectric layer, monolayer MoS2 as the channel material, and 3-layer (3L) graphene as the top gate (Supplementary Fig. 6a and b). Monolayer MoS2 was selected for its direct bandgap (~1.8 eV) and exceptional optoelectronic properties (Supplementary Fig. 6c and d). The output curve of the CdPS3-Li ion-gated transistor exhibits excellent linearity (Supplementary Fig. 7a), suggesting an ohmic contact between the source/drain electrodes and the MoS2 channel. The transfer curve of the CdPS3-Li ion-gated transistor shows obvious n-type semiconductor behavior with a large on/off current ratio (~105, Fig. 2b) with ultralow gate leakage current (<5 pA, Supplementary Fig. 7b) and demonstrates a pronounced hysteresis (Fig. 2b). This hysteresis arises from the transport of Li+ to the MoS2/CdPS3-Li interface under gate voltage, resulting in ion-electron coupling effect and the formation of a double electric layer (Supplementary Fig. 8). Furthermore, the hysteresis windows become larger under slower sweep rates or wider gate voltage ranges (Supplementary Fig. 9b and c) because more Li+ can accumulate at the MoS2/CdPS3-Li interface, generating a stronger ion-electron coupling effect. This can be confirmed through Kelvin Probe Force Microscopy (KPFM) measurements (Supplementary Fig. 10). When a positive voltage is applied to the CdPS3-Li/MoS2 vertical heterostructure, Li+ in the CdPS3-Li transport vertically to the MoS2 surface. We measured the surface potential after the voltage was applied, which indicates a 0.55 eV decrease in the work function of MoS2 (Fig. 2c). Additionally, we scanned the MoS2 surface potential after removing voltage at 1- and 5-min intervals, observing a slight increase of the potential (Fig. 2c). This indicates that, due to the anisotropic ionic transport properties of CdPS3-Li, only a small amount of Li+ detaches from the interface, with the majority remaining stored, thereby resulting in a strong ion-electron coupling effect.

Additionally, CdPS3-Li crystals contain abundant Cd vacancies and such negatively charged vacancies can attract and trap the photo-generated holes of MoS2 through Coulombic interactions, facilitating the transfer of photo-generated holes from MoS2 into CdPS3-Li (Supplementary Fig. 11a). The calculation shows that the charge densities of S atoms on the CdPS3-Li side are significantly increased, demonstrating the occurrence of charge transfer[33-35] (Supplementary Fig. 11b). We further conducted femtosecond-transient absorption (fs-TA) spectroscopy on MoS2 and MoS2/CdPS3-Li heterostructures. Both ground-state bleaching and excited-state absorption peaks in the range of 600 to 750 nm can be observed, decaying over a timescale from 1 ps to 0.5 ns (Fig. 2d-g). Compared to MoS2, the intensities of both signals in the MoS2/CdPS3-Li heterostructure were significantly enhanced, indicating an increased number of particles transitioning from the ground state to the excited state (Fig.2d and e). By fitting the relaxation times of the MoS2 and MoS2/CdPS3-Li heterostructures, we obtained exciton lifetimes (Supplementary Fig. 11c): for MoS2, τ = 111 ps; for MoS2/CdPS3-Li, τ = 227 ps. The significant difference in dynamics confirms the photo-hole transfer from MoS2 into CdPS3-Li (Supplementary Note 2). This behavior demonstrates the capability of CdPS3-Li ion-gated transistors to exhibit dynamic behavior under light pulses.

The multimodal synaptic behavior of CdPS3-Li ion-gated transistors

We next investigated the synaptic behavior of the CdPS3-Li ion-gated transistor under electrical pulse. When applying a positive gate voltage pulse, Li+ would transport to the CdPS3-Li/MoS2 interface along the out-plane direction and generate ion-electron coupling effects, thereby enhancing channel conductivity to obtain a spike current. Upon removing the voltage, the majority Li+ could be remained at the interface, resulting in a non-volatile storage (Fig. 3a). Conversely, a negative gate voltage pulse induced the removal of Li+ from the interface, leading to a decrease in channel conductivity (Fig. 3b). Unlike ion-gated transistors using polymer electrolytes or solid electrolytes as dielectric layer, the highly anisotropic Li+ transport characteristic in CdPS3-Li significantly enhanced the storage capacity of Li+ at the interface, resulting in a long retention time over 104 s (Fig. 3c). The unchanged Raman spectra of MoS2 after multiple repeated tests confirm that Li+ is stored only at the CdPS3-Li/MoS2 interface without diffusion into MoS2 (Supplementary Fig. 12). By applying paired electrical pulses to the device, paired-pulse facilitation (PPF) and paired-pulse depression (PPD) effects can be induced (Supplementary Figs. 13 and 14). Applying a train of positive gate voltage pulses with increasing frequencies causes stronger potentiation effects (Supplementary Fig. 15), as shorter intervals enhance cumulative effects and boost non-volatile conduction changes.

2D CdPS3-Li ion-gated transistor shows excellent long-term-potentiation/depression (LTP/LTD) behavior with ultra-high linearity (Fig. 3d). As the number of positive gate voltage pulse gradually increased, more Li+ were stored at the CdPS3-Li/MoS2 interface, leading to a gradual increase in channel conductivity. On the contrary, each negative gate voltage pulse could erase partial Li+, thus gradually reducing the channel conductivity. In addition, the in-plane superionic transport of CdPS3-Li prevented Li+ aggregation, ensuring uniform distribution of Li+ at interface after the removal of the gate voltage pulse, which caused almost equal fluctuations in synaptic current. Thus, the 2D CdPS3-Li ion-gated transistor showed exceptional linearity in both writing and erasing processes (R2=0.9985 and 0.9993, respectively) (Fig. 3d). To evaluate the endurance of the CdPS3-Li ion-gated transistor, we applied successive positive and negative gate voltage pulses to switch the device between high- and low-resistance states. The device exhibited no performance degradation over 4,000 cycles (Supplementary Fig. 16). To assess its cycle-to-cycle variations, we applied 2,200 consecutive electrical pulses, conducting over 15 programming and erasing cycles (Fig. 3e). The results indicated minimal differences between cycles, demonstrating high stability and reliability. The transistor also had good ambient stability, thermal stability, and cycling stability (Supplementary Fig. 17). Statistical analysis of 32 separate transistors shows each device operates normally with consistent threshold voltages and Ion (Supplementary Fig. 18 and 19).

Meanwhile, we tested the synaptic behavior of CdPS3-Li ion-gated transistors from 273 K to 323 K and found significant variations in performance. As shown in Fig. 3f and g, the range of conductance modulation of the device increases as the temperature increases (from ~0.07 μA at 273 K to 0.43 μA at 323 K). This phenomenon occurs because higher temperatures lower the ion migration barrier, which enhances conductivity. Significantly, the synaptic weight of the 2D CdPS3-Li ion-gated transistor can be modulated by adjusting the gate voltage (Fig. 3h) or pulse width (Fig. 3i). At low gate voltages and short pulse width, a limited number of Li+ migrated to the interface, resulting in a rapid current decline following voltage removal. In contrast, higher gate voltages and wider pulse widths facilitated the storage of more Li+, further increasing the synaptic weight. Additionally, as the gate voltage and pulse width increase, the difference between the spike and memory currents decreases (Fig. 3j and k). It is worth noting that when the voltage increases to 500 mV and the pulse width extends to 1 ms, the current decline is completely eliminated after the electrical pulse is removed (Fig. 3l). We further fine-tuned the device algorithms at a drain voltage range of 1 V under electrical pulses to achieve 64 resistive states without overlap between each resistance state (Fig. 3m), laying the foundation for high-precision neuromorphic computing. Notably, when the gate voltage is further increased to 2 V, the electrical state modification time of device can be reduced to as low as 1 μs (Supplementary Fig. 20a). Although its response is slower than that of complementary metal oxide semiconductor (CMOS) circuits, the device can be integrated with CMOS circuits for neural network training. In such system, it performs forward propagation while CMOS circuits execute backward propagation for gradient calculation. This configuration allows one backward propagation module to coordinate multiple forward modules in parallel, thereby minimizing idle time and enhancing overall throughput[13, 36].

Besides the highly-linear non-volatile resistance state output observed under electrical pulse, Coulombic interactions between Cd vacancies in CdPS3-Li and photo-generated holes in MoS2 could induce non-linear dynamic behavior in response to light pulses. When applying a light pulse under the VGS = 0 V, CdPS3-Li ion-gated transistor generate PSCs, which subsequently decayed over time (Fig. 4a). Detailed fitting and analysis revealed that the decay curve can be accurately modeled using a double exponential decay function (y = A1e-(x-x0)/t1 + A2e-(x-x0)/t2), indicating the presence of both fast and slow decay mechanisms[22]. The initial fast decay was primarily due to the unabsorbed photo-generated holes gradually returning to MoS2 and being neutralized. Meanwhile, some of the photo-generated holes were trapped by the Cd vacancies in CdPS3-Li, resulting in a slower current decay that eventually stabilized at a constant value. Notably, our device can achieve a fast response within ~100 μs under light pulse (Supplementary Fig. 20b). The application of paired light pulses enabled the PPF effects (Supplementary Fig. 21). The PPF ratio increased with the reduction of the pulse interval (Fig. 4b). This result could be well fitted with a double-exponential decay function, PPF ratio = C0 + C1e-Δt/τ1 + C2e-Δt/τ2.

Figure 4c further demonstrated the excitatory PSC responses of the device under a train of light pulses with varying frequencies. As the pulse frequency increased from 1 Hz to 5 Hz, the cumulative effects became more pronounced, leading to higher excitatory PSC responses.

More importantly, the relaxation time, defined as the time for the inhibitory effect (ΔI) to decay to 1/e of its initial value, could be modulated by varying the light intensity, pulse width, and number of pulses, thereby influencing the fitting function of the decay curve. Wider pulse widths and higher light intensities increase the number of photo-generated holes in MoS2, leading to longer relaxation times (Fig. 4d and e). Quantitative analysis showed a roughly linear relaxation time increase with incremental pulse widths and light intensities (Fig. 4f and g). Additionally, under the same light intensity and pulse width, an increased number of light pulses also produced a stronger cumulative effect, leading to longer relaxation times (Supplementary Fig. 22). As shown in Fig. 4e, since the transistor can achieve synaptic dynamic behavior under dim light (1.02 mW cm-2) and short pulses (100 μs), it exhibited a low light energy consumption of only 2.05 fJ to generate one PSC in the device. Meanwhile, Li+ in 2D CdPS3-Li ion-gated transistor can be driven under short pulses width (1 μs) and ultra-low gate voltages (100 mV), as shown in Fig. 3h. This led to an ultra-low electrical energy consumption of 20 aJ to drive a single synaptic potentiation or depression operation (calculation details see Methods). It is noted that the CdPS3-Li ion-gated transistor exhibited a large conductance ratio of 105 (Fig. 3c) and simultaneously achieving a highly linear resistance state under electrical pulses with ultra-low energy consumption (Fig. 4h, i and Supplementary Table 1). Therefore, the CdPS3-Li ion-gated transistor has the potential to function as hardware for implementing activation functions and MAC, thereby improving system integration and computational efficiency.

Construction of CdPS3-Li ion-gated transistor arrays for in-memory computing in deep learning

We further explored the ability of the CdPS3-Li ion-gated transistor to simultaneously perform a MAC operation and an activation function during forward propagation in a convolutional neural network (CNN, Supplementary Fig. 25). For the MAC operation, we designed a 16 × 10 cross-bar dual-gate arrays (Fig. 5a). In this array, the bottom gates of devices in the same row were connected as ‘word lines’, utilizing BN as the bottom gate dielectric material, while the top gates of devices in the same column were connected as ‘bit lines’, with CdPS3-Li serving as the top gate dielectric material. The sources and drains of devices in the same row were connected as ‘source lines’ and ‘drain lines’, respectively. Only devices that were simultaneously selected by both ‘bit lines’ and ‘word lines’ will be activated (Supplementary Note 3). In the experiment, all 160 devices in the 16 × 10 array were tested, with 153 devices functioning effectively (95.63% yield). These devices demonstrated n-type transistor characteristics with on/off ratio exceeding 105 (Supplementary Fig. 26). The distributions of threshold voltage and on-state current were consistent (Supplementary Fig. 27). During the forward propagation process, the resistance states of devices in MAC array (weights) were effectively adjusted (Fig. 5b). Subsequently, the weights were stored non-volatilely and converted into channel conductance by applying VDS and reading the IDS current on each row according to Kirchhoff's law through the ‘drain line’ to complete the MAC operations.

Meanwhile, the activation function is implemented using a 2 × 8 array (Fig. 5c). In each epoch, light pulses with distinct parameters are applied to the array, generating PSC curves (Fig. 5d). The time vector (X = [X1, X2, X3, …, X16]) is derived from the results of the previous layer's MAC operations in the neural network and serve as the input for extracting the current from the PSC curves. Each value in this time vector corresponds to the specific time at which the current is measured from an individual device. These current values are then collected to form the output current vector, completing the activation function computation. Finally, the output current vector is converted to the voltage vector to serve as the voltage inputs for the subsequent layer of MAC (Fig. 5e). The device array requires 5.2 ms to complete a light-pulse-induced activation operation (Fig. 5d), a timescale compatible with the operating speeds of MAC circuits in neuromorphic computing systems[37].

Figure 5f illustrates the typical forward propagation process for handwritten digits classification using the CdPS3-Li ion-gate transistor array. The results indicated that as training epochs progressed, the model's attention gradually focused on the key areas of the target digits, while both accuracy and loss stabilized. Due to the large conductance ratio and high-linearity resistance states of the device, the CNN achieved a training accuracy of 97.5% and a validation accuracy of 96.28% after the 30th epoch (Fig. 5g), enabling accurate image recognition and classification (Supplementary Fig. 28). These results fully demonstrate that CdPS3-Li ionic-gated transistors can not only efficiently perform MAC but also provide nonlinear activation functions. Moreover, light activation and electrical MAC operations are assigned to separate arrays in our system, with a focused laser selectively illuminating only the activation array, leaving the MAC array unexposed and free from optical interference (Supplementary Fig. 29). This functional separation is compatible with integrated photonic-electronic platforms for neuromorphic computing.

Methods
Synthesis of CdPS3-Li crystals

CdPS3-Li crystals were synthesized by one-step CVT method. All chemicals including Cd (99.95%), P2S5 (99%), Li2S (99.9%), S (99.999%), and I2 (99.99%) were purchased from Alfa Aesar, Macklin, or Sinopharm Chemical Reagent Co. and used without further purification. Briefly, 2 g reagent powders with a specific stoichiometric ratio were mixed in a glovebox with nitrogen atmosphere and then vacuum sealed in a quartz ampoule. The sealed ampoule was placed in a dual-temperature zone furnace with the raw chemicals side set at 750 ℃ and the opposite side at 650 ℃ for 5 days. The as-synthesized powders were collected and stored under ambient conditions. The CdPS3-K and CdPS3-Mg crystals were fabricated using ion exchange method by immersing the CdPS3-Li crystals in 0.5 M KCl and MgCl2 aqueous solutions, respectively, for more than one week.

Characterizations of CdPS3-Li and CdPS3-Li/MoS2 heterojunction

HAADF-STEM characterizations were carried out on an aberration-corrected JEM ARM 200F scanning transmission electron microscopes equipped with a cold field emission gun operated at 200 kV. Cross-sectional samples of CdPS3-Li were made by focused ion beam cutting on Thermo Scientific Helios G4 CX DualBeam system, where the samples were cut at 30 kV and milled with the voltage gradually decreasing from 30 kV to 5 kV to minimize damage. A Bruker Dimension Icon AFM was used for thickness, morphology and surface potential tests, as well as KPFM characterizations. Optical images were collected by a Nikon LV-ND100 microscope. XPS (ESCALAB 250 instrument with Al Kα and He I radiation sources) was used to characterize the element composition of CdPS3-Li. The XPS spectra were fitted using the XPS peak 4.1 software in which a Shirley background was assumed. FTIR spectra were measured using a UV-vis absorption spectrometer (JACSO V-550). The absorption spectra were measured using a UV-vis-NIR spectrometer (Varian Cary 5000). The XRD (Rigaku, D/MAX 2400 and PANalytical, X’Pert PRO using Cu Kα radiation) was used to characterize the structure of CdPS3-Li crystal. The impedance and capacitance measurements were carried out on Autolab electrochemical workstation (PGSTAT204) with frequencies ranging from 20 Hz to 1 MHz and an alternating potential of 150 mV. The in-plane and out-plane ionic conductivities were calculated according to the formula: σ = L/(R*S), where L represents the length of the CdPS3-Li; R is the resistance, obtained from electrochemical impedance spectroscopy; and S is the cross-sectional area of the CdPS3-Li. Capacitance measurements were also conducted using the AC module of the B1500 semiconductor analyzer, applying a test bias of ±0.5 V. Transient absorption spectra were measured by the ultrafast HELIOS TA system. The pump beam of 340 nm (~200 μW) fs laser was obtained to excite MoS2/CdPS3-Li heterojunction. The probe beam was focused on the center of the pump beam (2 mm in diameter) on the sample. All measurements were performed at room temperature under aerated conditions. The laser spot completely covers the sample area, ensuring that the femtosecond transient absorption spectrum accurately represents the entire heterojunction.

Fabrication and measurements of 2D CdPS3-Li ion synaptic transistor

We first deposited Ti/Au (Ti/Au: 5 nm/50 nm) as source and drain electrodes on a 300 nm SiO2/Si substrate. The electrodes were then patterned by photolithography, electron beam evaporation, and lift-off processes. Then, the mechanically exfoliated 2D MoS2 nanoflakes were placed on the source and drain electrode. After that, a 2D CdPS3-Li nanoflake was transferred to fully cover MoS2 channel by dry method. Finally, multilayer graphene was transferred to connect CdPS3-Li and gate electrode. The mechanical exfoliation of highly oriented pyrolytic graphite (HOPG), MoS2 crystal and CdPS3-Li crystal was performed using 3M scotch tape to obtain multilayer graphene, and 2D MoS2 and CdPS3-Li nanoflakes. The tape was gently pressed onto the crystal surface to ensure good contact. It was then carefully peeled off to exfoliate thin nanoflakes. Multiple exfoliation attempts may be necessary to obtain nanoflakes of suitable thickness. After that, the tape was smoothed onto the Polydimethylsiloxane (PDMS) surface to eliminate air bubbles and ensure close contact between the nanoflakes and the PDMS. The tape was then removed, and suitable sizes and thicknesses of the nanoflakes were identified on the PDMS surface. Subsequently, the nanoflakes were transferred to the target device surface, followed by heating to facilitate their release. Finally, the PDMS stamp was slowly peeled off.

The current of the devices was measured using a Cascade M150 probe station at room temperature, with an Angilent B1500A Semiconductor Device Parameter Analyzer. All pulse measurements were carried out with pulse measurement units in a Keithley 4200A-SCS Parameter Analyzer using home-built LabVIEW programs. For photo response measurements of the ion synaptic transistor, we applied light pulses of 516 nm that were controlled by a laser controller (Thorlabs, ITC4001). The laser controller applied a current of 0.01 mA, yielding a light-source power conversion efficiency (η) of 4.9%. The optical power was measured with Thorlabs’ Optical Power Meter. The laser has a diameter of 320.06 μm. The intensity of the laser spot is uniform, approximately following a Gaussian distribution from the central region to the edge (Supplementary Fig. 32a). Electrical measurements are conducted using a B1500A semiconductor analyzer, which can detect pulses as short as 1 μs. This is adequate to record laser-induced current changes in the device at rising/falling edges. It accurately captures transitions even under 100 μs light pulses (Supplementary Fig. 20b). The laser employed can generate light pulses as short as 10 μs, meeting the device testing requirements.

Calculations of the electrical and light energy consumptions of 2D CdPS3-Li ion synaptic transistor

The electrical energy consumption of 2D CdPS3-Li ion synaptic transistor was calculated using the following formula:
E = VGS * IGS * Δt, where VGS, IGS, and Δt represent gate-source voltage, gate-source current and pulse width, respectively. In our experiments, the VGS and Δt were 100 mV and 1 μs (Fig. 3h), respectively. The IGS was 200 fA, as shown in Supplementary Fig. 7b. Accordingly, the energy required for a single synaptic potentiation or depression operation driven by an electrical pulse was 20 aJ. Under realistic operating conditions, a signal generator and an oscilloscope are required to supply the electrical pulses. In our experiment, the power of the signal generator and oscilloscope are 5 W and 8 W, respectively.

We calculated the light power consumption of the device using the formula:
Elight = P * Δt * S, where P, Δt and S refer to light intensity, pulse width, and device area, respectively.
In our experiments, the light intensity and pulse width were 1.02 mW/cm² and 100 μs (Fig. 4e), respectively. The effective area of the device we constructed was 20 μm2 (Supplementary Fig. 6a), resulting in an energy consumption of 2.05 fJ to generate one PSC.

Taking the light-source power conversion efficiency into account, the total electrical energy required to generate a single optical pulse that induces a PSC was determined as follows: Etotal = Elight / η = 41.83 fJ.
Under realistic operating conditions, a semiconductor parameter analyzer is required to read the current value at a specific time point. In our experiment, the power of the semiconductor parameter analyzer is 10 W.

Fabrication of 2D CdPS3-Li ion synaptic transistor cross-bar array

Materials for CdPS3-Li ion-gated transistor array: In CdPS3-Li ion-gated transistor array, MoS2, BN, multilayer graphene and CdPS3-Li serve as the channel layer, bottom dielectric layer, top and bottom gate electrodes, and top dielectric layer, respectively. Monolayer MoS2 film on sapphire substrate, 10-layer BN on Cu, and monolayer graphene film on Cu substrates were all prepared by the chemical vapor deposition (CVD) method. These films completely cover the surfaces of 1×1 cm2 Cu and sapphire substrates. Before use, these 2D material films were transferred onto the target substrate by a solution etching transfer method[40]. In detail, the transfer medium, polypropylene carbonate (PPC) was first spin-coated on the CVD-grown film. After etching away the sapphire or Cu substrates by H3PO4 or copper etchant (Alfa Chemistry), the 2D material films were lifted by the target substrate. Finally, the PPC was washed off in a benzyl ether solution. Note that, multi-layer graphene films were obtained by repeating the transfer process three times. This transfer process effectively maintains film integrity and prevents damage (Supplementary Fig. 32b), making it suitable for constructing large-area device arrays. CdPS3-Li nanoflake was obtained by mechanical exfoliation from CdPS3-Li crystal. The process begins with mechanically exfoliating CdPS3-Li single crystals using adhesive tape into CdPS3-Li nanoflakes on the surface of a blank silicon wafer. After selecting nanoflakes of the desired size, a pre-fabricated PPC/PDMS stamp is carefully attached to the silicon wafer with CdPS3-Li nanoflakes. By leveraging the adhesive properties of PPC and PDMS during the heating and cooling processes, the PPC and nanoflakes are lifted and transferred from the PDMS substrate to the target substrate. During this attachment process, it is crucial to ensure good contact between the nanoflakes and the substrate while avoiding the formation of bubbles or wrinkles. After transfer, the PPC is removed by immersing in anisole solution.

Fabrication of 16 × 10 CdPS3-Li ion-gated transistor arrays: We first transferred CVD-grown graphene film from Cu onto SiO2/Si substrate and patterned it using Electron Beam Lithography (EBL) (ABM/6/350/NUV/DCCD/M) with an exposure time of 4.5 s and oxygen plasma (PR500) technology (Supplementary Fig. 33a-c and Supplementary Fig. 34a). Then, we deposited electrodes of 5 nm Ti/20 nm Au by electron beam deposition with the ULVAC ei-501z system for bottom ‘word line’ (Supplementary Fig. 33d and Supplementary Fig. 34b). The deposition rates are 0.13 nm/s for Ti and 0.19 nm/s for Au. Next, we transferred the BN thin films and etched away the excess areas by the RIE-10NR reactive ion etching to serve as bottom dielectric material (a gas ratio of CF4 : O2 = 20 sccm: 4 sccm, a gas pressure of 2 Pa, a power setting of 50 W, and a reaction time of 2 mins) (Supplementary Fig. 33e and Supplementary Fig. 34c). Then, we transferred CVD-grown MoS2 film from sapphire onto surface of BN and patterned it using EBL and oxygen plasma technology (Supplementary Fig. 33f, g and Supplementary Fig. 34d). Then, we deposited electrodes of 5 nm Ti/20 nm Au by electron beam deposition with the ULVAC ei-501z system for source-drain electrodes of the MoS2 transistors on the same row (Supplementary Fig. 33h and Supplementary Fig. 34e). Then, we transferred CdPS3-Li nanoflake (50 μm×60 μm) onto the device surface using a dry method with PPC/PDMS as the transfer stamp (Supplementary Fig. 33i and Supplementary Fig. 34f). Subsequently, we transfer 3L graphene onto the surface of the device and patterned it using EBL and oxygen plasma technology (Supplementary Fig. 33j, k and Supplementary Fig. 34g, h). Finally, we deposited ‘bit line’ electrodes of Ti/Au to connect the gate electrodes of transistors by electron beam deposition to obtain the device array (Supplementary Fig. 33l).

The area of the device array is 50 μm × 50 μm. The multilayer graphene, MoS2, and BN used in this study are all cm-scale thin films. The CdPS3-Li nanoflake, obtained through mechanical exfoliation, measures 50 μm × 60 μm. All these materials can fully cover the device area (Supplementary Fig. 34g, h). The fabrication of a 2 × 8 CdPS3-Li ion-gated transistor array is nearly identical to that of a 16 × 10 CdPS3-Li ion-gated transistor array, except that it does not include a bottom gate.

Density functional theory calculations

All the calculations are performed in the framework of the density functional theory with the projector augmented plane-wave method, as implemented in the Vienna ab initio simulation package[41]. The exchange-correlation potential is modeled using the generalized gradient approximation by Perdew, Burke, and Ernzerhof[42] in conjunction with the DFT-D [43] method for van der Waals corrections. The cut-off energy for plane wave is set to 450 eV. The energy criterion is set to 10-5 eV in iterative solution of the Kohn-Sham equation. All the structures are relaxed until the residual forces on the atoms have declined to less than 0.02 eV/Å.

Measurement setup for MAC and activation using CdPS3-Li ion-gated transistor

The measurement setup comprises a dark box with a probe station used to measure the synaptic responses of the device under both light and electrical pulses (Supplementary Fig. 35). Specifically, a signal generator outputs electrical pulse signals, and an oscilloscope verifies the accuracy of these signals. A Python script directly converts MNIST images into electrical pulse parameters (amplitude, width, and number) and transmits them to the signal generator via USB. These electrical pulse as the input signals are applied to the device array to perform matrix multiplication (Supplementary Fig. 36) and output current signal. A laser controller generates light pulses to induce PSC in the device. The PSC is read through the source-drain electrode of the device as the output signal, thereby completing the activation function (Supplementary Fig. 36). All the output currents achieved under electrical pulse and optical pulse are read by a Keysight semiconductor parameter analyzer, which finally transmits all measured data back to the PC for further processing and analysis as the output of the neural network.

Peer review rounds
[{"round": 1, "reviewer_comments": {"reviewer_1": "The manuscript presents the fabrication and characterization of 2D CdPS₃-Li/MoS₂ heterostructure-based ion-gated field-effect transistors (FETs) for synaptic crossbar arrays, focusing on matrix multiplication and trainable activation functions. The study demonstrates multimodal synaptic behavior, a key feature for neuromorphic computing.\n1. While the work contributes to the growing interest in ion-gated transistors for neuromorphic applications, it lacks a distinct novelty presentation in the Introduction. Similar studies have already reported comparable work, including:\nA. Advances in Multi-Terminal Transistors as Reconfigurable Interconnections for Neuromorphic Sensing and Processing (Advanced Electronic Materials, 2024).\nB. Non-Linear Two-Dimensional Floating Gate Transistor as a Lateral Inhibitory Synapse for Retinal Early Visual Processing (Materials Horizons, 2022).\nC. Bio-Plausible Multimodal Learning with Emerging Neuromorphic Devices (Advanced Science, 2024).\nA benchmarking table comparing the proposed device with previous works would help highlight its novelty. Also, Introduction needs a major revision for showing importance of this work.\n2. The reported memory window in I–V characteristics is too small, resulting in a narrow conductance window in Fig. (d). This could limit its practical application in synaptic crossbar arrays. Despite this limitation, the authors claim 95% accuracy in neuromorphic computing, which seems questionable. A more rigorous analysis is needed to justify this claim.\n3. The low retention performance of the device raises concerns regarding its feasibility for long-term applications. The authors should provide a physical and application-oriented justification discussing its impact. Read noise in the retention measurements (Fig. (c)) is not addressed.\n4. The manuscript does not adequately report variability between devices, which is crucial for ion-gated FETs. Statistical data (bar plots, repeatability metrics) should be included to strengthen the reliability of the results. Since chemical and mechanical exfoliation methods often suffer from material reproducibility issues, variability analysis is essential.\n5. There is an inconsistency in the applied voltages used across figures: Fig. 1(d): 0V, 5V, and 10V and Figs. (a) & (b): VGS = 0.2V\nA clear correlation between different experimental conditions is missing.\n6. While cyclic variability is improved for simple devices (Fig. (c)), the same analysis should be extended to photogenerated or light-activated devices. The relationship between memory window size and cyclic variability should be clarified.\n7. The method used to determine the conductance ratio is unclear. More theoretical and critical assessment is required to confirm high linearity and non-linearity.\n8. The manuscript reports 64 conductance states in Fig. , but their stability and distinguishability under the same read voltage are not demonstrated.\n9. FESEM image (Fig. S2) lacks a scale bar. Also, FESEM image of final device is missing.\nThe manuscript could not provide a stronger contribution to the field of neuromorphic computing. It require a major rewrite for properly connecting lines and explain the relavant physics behind results.", "reviewer_2": "The authors report a novel ion-gated transistor that can perform artificial neural network (ANN) computations. Demonstrating non-linear activation functionality in semiconductor devices significantly impacts the AI semiconductor research society. However, I have several concerns about the general structure of this manuscript and its figure materials. I hope my comments improve the quality of the paper.\n- The introduction section needs to include relevant research summaries, limitations/problems of previous works, and this work's novel approach. However, the current version seems superficial. It does not properly describe previous literature related to this paper's topic.\n- Materials in the Supplementary Information should be supplementary, not necessary. However, many portions of the Supplementary Information materials should be moved to the main manuscript. I recommend the authors thoroughly re-arrange the figures. In the first paragraph of the main text, the authors refer to Supplementary Fig. –11, which is inappropriate. Also, the authors refer to Supplementary Fig. 1 in the introduction. I think it needs to be moved to the main figure, considering the importance of the introduction.\n- The structure and key parameters of the transistor are not provided in the main text (e.g., source/drain materials, thickness and capacitance of the gate dielectric, gate leakage current, etc.). As this work is based on the transistor, it would be good to explain the transistor and related synaptic characteristics sequentially. Why did the authors use MoS2 as the channel material?\n- Figure shows spiking shapes in current-time graphs with several conditions. Quantitative analyses are required as these transient properties are essential in neuromorphic applications.\n- The reliability of the device is essential for applications in ANN. Effects on bias/thermal stress and endurance data are crucial. Moreover, device-to-device and cycle-to-cycle variations are necessary.\n- The authors utilized light to control the non-linearity of the activation functionality. However, Fig 3 shows a general trend of light-induced modulation without any quantitative analysis, which is insufficient for utilization in the ANN system. Is it a good way to use light to control the non-linearity? Is it possible in practical applications?\n- The demonstrations in Fig 4 & 5 are outstanding as they show potential applications. However, the purpose of the demonstration is not clearly indicated. The system's overall performance shown in Fig 4a is assumed to be far below the state-of-the-art GPU system. The current version may give the reader a false sense that the system performs at a comparable level to the current GPU.", "reviewer_3": "This work studied the characteristics of MoS2/CdPS3-Li/Multiplayer graphene devices and their applications for synaptic applications.\nKey claims are 1) Linear control of Li ion movement, ) Light induced modulated of device characteristics (primarily hole trapping), 3) 16x10 cross-bar array fabrication, 4) applications to CNN training.\nSolid ionic conduction characteristics of CdPS3-Li has been published in Nature comm, 14, 3998 (2023).\nSince the synaptic operations of devices whose conductivity can be controlled linearly have been published so many times, in this review, claim #1 to #3 are examined more closely. However, many missing information and claims presented without detail justifications made the review difficult. Followings are the list of missing information and questions on the various claims.\n1) Why MLG is used as gate? If there is a specific reason to use MLG, please add. Also, correct all description using “graphene” to “multilayer graphene” or “MLG”.\n) What was the thickness and area of MLG? How it is transferred to single device and 16x10 array?\n3) Page 3: “The multilayer CdPS3-Li flake has a high dielectric constant of 5. and a wide bandgap of 3.55 eV (Supplementary Fig. 3).” This is a typical example of problems I had while I read through this work. Supp. Fig.3 does not provide proper information on how dielectric constant or bandgap is determined. Supp. Fig.3a shows large dispersion from 1Hz to 100KHz. How the author obtained the thickess and dielectric constant information from this data?\n4) Page 3: “This can be confirmed through Kelvin Probe Force Microscopy (KPFM) measurements (Fig. 1d and Supplementary Fig. 9 ).” I can’t see how the data shown in Fig.1d and Supp. Fig.9 confirm the “strong io-electron coupling effect”. The authors should explain more details. From now on, this kind of problem will be listed as “unjustified claim”.\n5) Page 3: “In contrast, the CdPS3-Li strongly restricts the out-plane transport of Li+ (Fig.1c, Supplementary Fig. 4: - unjustified claim. Also, I wonder whether the authors excluded the impact of contact resistance from the measurement. Otherwise, conduction behavior would be dominated by the contact resistance.\n6) Page 3: “indicating an increased number of particles transitioning from the ground state to the excited state (Fig.1g and h ).”. The authors should explain more how Fig.1g and h can lead to the claims on the increase in excitation. Which part of device is analyzed? How it is measured? Is there any uniformity problem? What was the spot size of fs-TA? Why the figure caption mentioned “mapping” while the data is decay time versus wavelengths?\n7) Fig.2a,b shows relaxation in the order of 5-10s. Explain the mechanism. Also, add device size information (channel length and width). I guess Fig.2a was obtained by applying 200mV Vg pulse for 1s and then -200mV was applied for 1s for the same device. If this is right, the author should provide detail sequences. Also, explain why there is a strong current level change even after 1s. Also, after 80s, how much (what %) is the change in the current level. These details are important to conform the stability of the synaptic device.\n8) Fig.2c should provide quantitative assessment in stead of “long retention time. #% after 10000s value should be provided.\n9) Fig.2a,b shows a strong time dependence after 1s pulse application. Fig.2d was obtained 1ms and 5s interval. Then, current was measure after 5s? Fig. a,b shows there might be some transient behavior after 5s. Supp. Fig.20 shows a more than +/-10% device current variation. Then, Fig.2d is obtained form single device? What happens if the same pulse measurement is performed to other devices?\n10) Fig.2e claims 64 state separation is possible by varying the current level from 25nA to 85nA. This might be from a single device. If there is a finite memory window change as shown in Fig.2c and if there is a device to device variation, this kind of state separation is not possible. The claim for the feasibility of state separation should consider these limitations. Thus, Fig.1e,f are too aggressive claim that can not be realized.\n11) When measure the current shown in Fig.2e, what was the gate bias? If it was not 0V, was there additional shift due to the Vg? If it was 0V, how 25-85nA is obtained? This kind of detail information should be added.\n12) Fig.2g,h needs more explanation. Why 100mV pulse shows decay? What 1ms pulse does not show decay while Fig.2a,b shows the decay?\n13) For the measurement shown in Fig.3, what was the device size, bias condition, beam uniformity, beam size, wavelength?\n14) Fig.3f, what was the laser pulse width? How they are controlled? Electro-optic or mechanical? Is the laser pulse rise and fall time fast enough compared to the electrical measurement? Due to a strong transient detrapping beahviors, it might be difficult to define a specific Id values. How and when Id was defined?\n15) In Fig, 4a. please provide more magnified picture shown the actual cell device. Also, In the method section, the authors mentioned that MLG is transferred first as a bottom gate. What is the reason for this change from the schematic shown in Fig.1a?\n16) Supp. Fig.27 shows the schematic of device fabrication flow. The authors showed figures indicating large area BN and MoS2 transfer. What was the area? Then, why the authors mentioned in the main text flake transfer?\n17) If the area of array is fully covered with MoS2 and BN, the area should be more than 50umz50um. Th authors need to provide more information about the MoS2 and BN formation and transfer process and their yield. Are the 16x10 array devices (160 cells) all working? What is the device distribution? There are many missing information related to array device fabrication and characeristics.\n18) Page 12: “It is worth noting that the device in MAC operations exhibited good uniformity (Supplementary Figs. 20).”. Supp. Fig.20 shows at least +/-10% Id variation and more than 0.5VVth variation. The authors should provide detail numbers instead of claiming “good uniformity”.\n19) Supp., Fig.2b and c. What is the size of scale bar?\n20) Supp. Fig.10c should be shown in log scale and two curves should be labeled."}, "author_response": "Response to reviewers’ comments\nReviewer #2 (Remarks to the Author):\nThe authors report a novel ion-gated transistor that can perform artificial neural network (ANN) computations. Demonstrating non-linear activation functionality in semiconductor devices significantly impacts the AI semiconductor research society.\nHowever, I have several concerns about the general structure of this manuscript and\nits figure materials. I hope my comments improve the quality of the paper.\nResponse: We would like to express our sincere gratitude to the reviewer for the\nconstructive comments and valuable suggestions. We have restructured the manuscript\nand rearranged the figures to improve clarity and the logical flow. Additionally, we\nhave incorporated new experimental data and conducted further quantitative analyses\nof the synaptic behavior of our devices. We have also corrected the inaccuracies in\ncomparison with GPU in the revised manuscript. The following are our point-by-point\nresponse to the reviewer's comments.\n- The introduction section needs to include relevant research summaries,\nlimitations/problems of previous works, and this work's novel approach. However, the\ncurrent version seems superficial. It does not properly describe previous literature\nrelated to this paper's topic.\nResponse: We thank the reviewer very much for the constructive suggestions, which\nhave helped us significantly improve the quality of our manuscript. According to the\nreviewer's suggestions, we have completely revised the introduction section as detailed\nbelow. It now offers a more comprehensive analysis of the previous literature on topics\nrelated to this paper, including summaries, limitations and problems of previous works,\nand the novel approach introduced in this study.\nAnalog-digital hybrid neuromorphic computing integrates digital and analog circuits,\naiming to overcome the limitations of traditional von Neumann architectures. In this\nparadigm, analog circuits are responsible for executing forward propagation, which\nincludes the multiply-accumulate (MAC) operation and non-linear activation. Non-\nlinear activation is crucial for introducing non-linearity into neural networks, and\ntrainable non-linear activations can adapt their form based on the complexity of the data.\nUtilizing electrical pulses to achieve MAC, while applying light pulses for non-linear\nactivation, presents significant advantages. In contrast to electrical pulses, light pulses\noffer a non-contact stimulation method. They do not introduce additional charges or\ncurrents, nor do they cause electromagnetic interference in MAC circuits. Postsynaptic\ncurrents (PSCs) are generated by synapses under light pulses, which can be modeled\nusing a double exponential function. This modeling facilitates establishing a\nmathematical equivalence between PSCs and activation functions like the Sigmoid\nfunction. Multimodal artificial synapses serve as the hardware for implementing this\nparadigm and must meet two critical requirements. First, they should exhibit high\nlinearity and non-volatile resistance states under electrical pulses to ensure high-\nprecision MAC operations. Second, they must be capable of generating diverse non-\nlinear PSCs (large conductance ratios) under light pulses to enable trainable activation.\nThis strategy has the potential to reduce energy consumption and enhance\ncomputational efficiency.\nVarious multimodal synapses have been developed, modulating device conductivity\nthrough defect migration, charge trapping, material phase change, or ferroelectricity.\nHowever, these mechanisms often cause uncontrollable stochasticity, high operation\nvoltages and low linearity, significantly affecting computational accuracy. In contrast,\nion-gated transistors using ionic conductors as dielectric layers can modulate channel\nconductance via ion-electron coupling by intercalating or ejecting ions. They offer\nadvantages such as low operating voltage, low power consumption, and easy regulation.\nHowever, existing ion-gated transistors struggle to respond to both electrical and light\nsignals, limiting their ability to achieve multimodal functionality. Additionally, the\nisotropic nature of current ionic conductor dielectric layers weakens ion-electron\ncoupling effects. This results in low conductance ratios, poor long-term synaptic\nplasticity, and inferior memory performance. To address these challenges, there is an\nurgent need for a new type of ionic dielectric material that can precisely control ion\ntransport, achieve non-volatile ion storage, and effectively trap photo-generated\ncharges.\nHere, we construct a multimodal ion-gate transistor using 2D CdPS -Li as the\n3\ndielectric layer and 2D MoS as the channel layer. The unique layered structure of\n3\nstorage of Li+ and a strong ion-electron coupling effect to generate high-linearity and\nnon-volatile resistance states (R² = 0.99, retention>104 s) under electrical pulses.\nAdditionally, Cd vacancies in CdPS -Li can attract and trap photo-generated holes from\n2\n(conductance ratio of 105) under light pulses. Consequently, the CdPS -Li transistor can\n3\nsimultaneously perform MAC operations and implement trainable activation functions,\nenabling the physical realization of the complete forward propagation process in deep\nlearning. We further developed a cross-bar structured CdPS -Li transistor array to\n3\nrecognize handwritten digit images, achieving a high accuracy exceeding 97.5%, which\noffers a promising hardware solution for neuromorphic computing.\n- Materials in the Supplementary Information should be supplementary, not necessary.\nHowever, many portions of the Supplementary Information materials should be moved\nto the main manuscript. I recommend the authors thoroughly re-arrange the figures. In\nthe first paragraph of the main text, the authors refer to Supplementary Fig. 2–11, which\nis inappropriate. Also, the authors refer to Supplementary Fig. 1 in the introduction.\nI think it needs to be moved to the main figure, considering the importance of the\nintroduction.\nResponse: We thank the reviewer very much for the constructive suggestions, which\nhave helped us significantly improve the quality of our manuscript.\nIn the revised manuscript, we have restructured and re-arranged the figures in the\nmain manuscript. Specifically, we moved part of Supplementary Fig. 1-11 to the main\ntext and designated it as Fig. 1, focusing on the properties of CdPS -Li single crystals\n3\nsynthesized via the chemical vapor transport method. Additionally, we renumbered the\noriginal Fig. 1-3 as Fig. 2-4, with Fig. 2 illustrating the device structure and working\nmechanism of the CdPS -Li transistor, Fig. 3 showing the device behavior under\n3\nelectrical pulses, and Fig. 4 highlighting its response to light pulses. Finally, we merged\nthe original Fig. 4 and 5 into a single figure to validate the effectiveness of the CdPS -\napplicability in handwritten digit recognition.\n- The structure and key parameters of the transistor are not provided in the main text\n(e.g., source/drain materials, thickness and capacitance of the gate dielectric, gate\nleakage current, etc.). As this work is based on the transistor, it would be good to explain\nthe transistor and related synaptic characteristics sequentially. Why did the authors use\nMoS2 as the channel material?\nResponse: We thank the reviewer very much for the constructive suggestions. In the\nrevised manuscript, we have provided detailed information on the transistor device\nstructure and key performance metrics, including the source/drain electrode materials,\ngate dielectric thickness, capacitance, gate leakage current, and other relevant\nparameters. Additionally, we have comprehensively explored the synaptic behavior of\nthe device and elucidated its underlying mechanisms. Furthermore, we have clarified\nwhy we selected MoS as the channel material. The addition and modifications we have\n2\nmade are as follows.\n The structure and key parameters of the transistor\nThe CdPS -Li ion-gated transistor features a vertically stacked architecture:\n3\nmonolayer MoS as the channel, 5-nm Ti/50-nm Au as the source/drain electrodes, 70\n2\nnm-thick CdPS -Li nanoflakes as the ionic gate dielectric, and 3-layer graphene as the\n3\ntop gate electrode (Fig. 2a and Fig. R1a, b). Monolayer MoS was selected for its direct\n2\nbandgap (~1.8 eV) [Phys. Rev. Lett. 105: 136805.] and exceptional optoelectronic\nproperties (Fig. R1c and d). Under light pulses, MoS generates large number of photo-\n2\ngenerated holes, which can be captured by Cd vacancies in CdPS -Li. This process\n3\nleads to nonlinear synaptic behaviors that are essential for the realization of activation\nfunctions (Fig. 4a).\nFigure R1. a, The AFM image of CdPS -Li ion-gated transistor. Scale bar is 5 μm. b,\n3\nin Figure R1a. c, d, The output (c) and the transfer curves (d) of monolayer MoS\n2\nnanoflake transistor in dark and light, indicating obvious photoconductivity property.\nC-V measurements on CdPS -Li nanoflakes revealed a high-frequency (1 MHz)\n3\ndielectric constant of 5.2 (Fig. R2a-d), calculated according to the formula:\n𝐶 ∙𝑑\n𝜀 = \n𝑟 𝜀 ∙𝐴\n0\nwhere C is the capacitance, d is the thickness of the dielectric layer, A is the electrode\narea, and ε is the vacuum permittivity (8.854×10-12 F/m). As can be seen from Fig. R2a\n0\nand b, the electrode area is 80 μm2, and the thickness of CdPS -Li nanoflake is 70 nm.\n3\nspectrum and calculated the bandgap using the equation:\nE=hν/λ\nwhere E represents photon energy, h is the Planck constant, ν is the speed of light,\nand λ denotes wavelength. By converting the x-axis from wavelength to photon energy\n(Fig. R2e), we plot the absorption spectrum against photon energy. The bandgap (E )\ng\ncorresponds to the photon energy at which the absorbance begins to rise sharply. Thus,\nwe determined the bandgap E to be 3.55 eV.\ng\nCombined with its wide bandgap and high dielectric constant (Fig. R2d and e),\nCdPS -Li is an ideal dielectric layer for ion-gated transistor. As shown in Fig. R2f,\nmeasuring the dielectric constant of CdPS -Li nanoflakes. Scale bar is 10 μm. The inset\n3\nis height profile of CdPS -Li nanoflake along the white line. c, The capacitance as a\n3\nfunction of electrode potential V with frequency of 1 MHz measured by a\nsemiconductor analyzer. d, Dielectric constant of CdPS -Li vs frequency at room\n3\ntemperature measured by an electrochemical workstation. e, The experimental\nabsorption spectrum of the CdPS -Li crystal. f, The I -V curve of the CdPS -Li ion-\ngated transistor plotted on a log scale.\n The characteristics of CdPS -Li ion-gated transistor\n3\n(Supplementary Fig. 7a), suggesting an ohmic contact between the source/drain\nelectrodes and the MoS channel. The transfer curve of the CdPS -Li ion-gated\n2 3\ntransistor shows obvious n-type semiconductor behavior with a large on/off current\nratio ~ 105 and demonstrates a pronounced counterclockwise hysteresis (Fig. 2b). This\nhysteresis arises from the transport of Li+ to the MoS /CdPS -Li interface under gate\n2 3\nvoltage, resulting in ion-electron coupling effect and the formation of a double electric\nlayer (Supplementary Fig. 8). Furthermore, the hysteresis windows become larger\nunder slower sweep rates or wider gate voltage ranges (Supplementary Fig. 9b and c)\nbecause more Li+ can accumulate at the MoS /CdPS -Li interface, generating a stronger\n2 3\nion-electron coupling effect. For comparison, MoS transistors using BN or SiO as the\n2 2\ndielectric layer were also fabricated, which exhibits a relatively small hysteresis\nwindows (<20 at V = 0 V, Supplementary Fig. 9a).\nGS\n The synaptic behavior of CdPS -Li ion-gated transistor under electrical pulse\n3\nunder electrical pulse through ion-electron coupling effect. A positive gate pulse drives\nLi+ to move toward the CdPS -Li/MoS interface, where an electric double layer is\n3 2\nformed to induce negative charge for doping MoS , thereby enhancing channel\n2\nconductivity (Supplementary Fig. 8a, and Fig. 3a). Owing to the anisotropic Li+\ntransport properties in CdPS -Li, most of Li+ could be stored at the interface after the\n3\nremoval of gate voltage, resulting in non-volatile storage. Conversely, a negative gate\nvoltage pulse induced the erasure of Li+ from the interface, leading to a decrease in\nchannel conductivity (Supplementary Fig. 8b and Fig. 3b).\nMoreover, 2D CdPS -Li ion-gated transistor shows excellent long-term-\n3\npotentiation/depression (LTP/LTD) behavior with ultra-high linearity (Fig. R3). As the\nnumber of positive gate voltage pulse gradually increased, more Li+ were stored at the\nCdPS -Li/MoS interface, leading to a gradual increase in channel conductivity. On the\n3 2\ncontrary, each negative gate voltage pulse could erase partial Li+, thus gradually\nreducing the channel conductivity. We further fine-tuned the device algorithms at a\ndrain voltage range from 0 to -1 V under electrical pulse to achieve 64 resistive states\n(Fig. 3e). Each state demonstrates non-volatile storage, and there was no significant\noverlap between the nearest-neighbor states, which lays the foundation for high-\nprecision calculations (Fig. 3e and Fig. R3). In addition, the in-plane superionic\ntransport of CdPS -Li prevented the aggregation of Li+, ensuring a uniform distribution\n3\nof Li+ at interface. Thus, the 2D CdPS -Li ion-gated transistor showed exceptional\n3\nlinearity in both writing and erasing processes (R2= 0.9985 and R2=0.9993, respectively)\n(Fig. R3). The device also shows a long retention time exceeding 104 s both at high\nresistance state and low resistance state (Fig. 3c).\nFigure R3 a, b, Cumulative writing (a) and erasing (b) with progressive multilevel\nstates for CdPS -Li ion-gated transistor. The electrical pulse widths and intervals were\n3\n1 ms and 5 s, respectively.\n- Figure 2 shows spiking shapes in current-time graphs with several conditions.\nQuantitative analyses are required as these transient properties are essential in\nneuromorphic applications.\nResponse: We thank the reviewer very much for the constructive suggestion. In the\nrevised manuscript, we carried out a quantitative analysis on how various parameters,\nincluding gate voltage, pulse width, and duration, affect the synaptic behavior of the\nCdPS -Li ion-gated transistor. Meanwhile, we have conducted additional experiments\n3\nto investigate both the pairing pulse facilitation (PPF) and depression (PPD) effects as\nwell as the impact of varying pulse intervals and frequencies on the synaptic behavior\nof the device. The addition and modifications we have made are as follows.\nUnder gate voltage pulse, the CdPS -Li ion-gated transistor first generates a spike\n3\ncurrent and then decays to a steady state (memory current) (Fig. 3a and b). We\nsystematically investigated the synaptic behavior of the device under different gate\nvoltage amplitudes and widths. Accordingly, we extracted the spike and memory\ncurrents and plotted them against the gate voltage and pulse width for quantitative\nanalysis. The results indicate that both the spike and memory currents increase linearly\nwith the increase of gate voltages and pulse width (Fig. R4). This is because a large\nvoltage and pulse width enable more ions to overcome the out-plane transport barrier,\nreach the interface, and create stronger ion-electron coupling effect.\nAdditionally, as the gate voltage and pulse width increase, the difference between the\nspike and memory currents decreases (Fig. R4). That is because, in addition to the out-\nplane transport barrier, in CdPS -Li, Li+ occupies negatively charged vacancies to\n3\nmaintain the material's electrical neutrality. When a positive gate voltage is applied, the\nLi+ must also overcome the Coulombic interaction with these vacancies. Higher\nvoltages and wider pulse widths provide Li+ with increased energy, enabling them to\nmore effectively surmount these energy barriers. Upon the removal of voltage, the Li+\nthat have transported to the interface retain sufficient energy to overcome the Coulomb\ninteraction force between vacancies and Li+. Therefore, Li+ can be stably stored at the\ninterface without detaching. Conversely, at lower voltages or shorter pulse widths, the\nLi+ that reaches the interface lack adequate energy to fully overcome the Coulomb\ninteraction force between vacancies and Li+, resulting in some Li+ detaching from the\ninterface and causing a more pronounced current decay.\nFigure R4. a, Absolute change (∆I) in synaptic current with varying gate voltage (pulse\nwidth, 1 ms). b, ∆I with varying pulse width (gate voltage is constant, 500 mV).\nBy applying paired electrical pulses to the device, PPD and PPF effects can be\ninduced. When the second pulse arrives before the postsynaptic current (PSC) from the\nfirst pulse fully relaxes, cumulative effects lead to higher or lower PSC spikes (Fig. R5\nand R6). Applying a train of positive gate voltage pulses with increasing frequencies\ncauses stronger potentiation effects (Fig. R7) as shorter intervals enhance cumulative\neffects and boost non-volatile conduction changes.\nFigure R5. a-e, PPD effect, where a pair of gate voltage pulses was applied (-0.1 V,\n1 ms) and 0.1 V source-drain voltage (V ) was used to read the device state, with an\nDS\ninterval of 1 s (a), 1.5 s (b), 2.5 s (c), 3.5 s (d), 4 s (e). h, PPD ratio as a function of the\npulse interval, defined as |A - A |/A × 100%, where A represents the amplitude of the\n2 1 1 1\nfirst pulse, and A represents the amplitude of the second pulse. The black line\n2\nrepresents fitting results using the double exponential decay function.\nFigure R6. a-e, PPF effect, where a pair of pulses were applied (0.1 V, 1 ms) and 0.1 V\nV was used to read the device state, with an interval of 1 s (a), 1.5 s (b), 2 s (c), 2.5 s\nDS\n(d), 3 s (e). f, PPF ratio as a function of the pulse interval, defined as\n(A − A )/A × 100%, where A represents the amplitude of the first pulse, and A\n2 1 1 1 2\nrepresents the amplitude of the second pulse. The black line represents fitting results\nusing the double exponential decay function.\nFigure R7. Excitatory PSC induced by a train of electrical pulses (V =100 mV, with\nGS\nfrequencies of 1, 2, 2.5 and 5 Hz) using 0.1 V V to read the device state, showing that\nDS\nhigher pulse frequency leads to a more prominent accumulation effect.\n- The reliability of the device is essential for applications in ANN. Effects on\nbias/thermal stress and endurance data are crucial. Moreover, device-to-device and\ncycle-to-cycle variations are necessary.\nResponse: We sincerely appreciate the reviewer’s constructive suggestions. In the\nrevised manuscript, we have conducted a systematical analysis of the device's reliability.\nSpecifically, we evaluated the performance variations of the CdPS -Li ion-gated\n3\ntransistor over 4,000 cycles, quantifying cycle-to-cycle variations. Additionally, we\nassessed device-to-device variations by testing 32 individual devices and investigated\nthe effects of bias and temperature on device performance.\n The endurance and cycle-to-cycle variations of CdPS -Li ion-gated transistor.\n3\npositive and negative gate voltage pulses to switch the device between high- and low-\nresistance states. The device exhibited no performance degradation over 4,000 cycles\n(Fig. R8a). To assess its cycle-to-cycle variations, we applied 2,200 consecutive\nelectrical pulses, conducting over 15 programming and erasing cycles (Fig. R8b). The\nresults indicated minimal differences between cycles, demonstrating high stability and\nreliability.\nFigure R8 a, Cycling stability of CdPS -Li ion-gated transistor. The high- and low-\n3\nresistance states are induced by applying gate voltage of -2 V and +2 V, respectively. b,\nCumulative electrical writing and erasing processes. 2,200 successive electrical pulses\n(±0.2 V) with pulse width of 1 ms and interval time of 5 s were applied. V = 0.1 V.\nDS\n The impact of bias/thermal stress on device performance.\nIt is noted that the Li+ conductivity of CdPS -Li increases with rising temperature\n3\n[Science 370, 596-600(2020). Nat. Commun. 14, 3998 (2023).]. We tested the synaptic\nbehavior of CdPS -Li transistors from 273 K to 323 K and found significant variations\n3\nin performance. As shown in Fig. R9, the range of conductance modulation of the\ndevice increases as the temperature increases (from ~0.07 μA at 273 K to 0.43 μA at\nbarrier, which enhances conductivity. More Li+ accumulates at the interface under the\nsame voltage, thereby strengthening ion-electron coupling effect and improving the\nrange of conductance modulation.\nThe magnitude of the gate voltage and pulse width significantly affects the synaptic\nbehavior of the device (Fig. 3h and i, Fig. R4). At the same temperature, a higher voltage\nand wider pulse allow more ions to overcome the barrier and migrate to the interface\nfor storage. This process leads to a stronger ion-electron coupling effect. As the voltage\nand pulse width gradually increases, the synaptic current exhibits an approximately\nlinear increase.\nFigure R9 a, The synaptic behavior of CdPS -Li ion-gated transistor at various\n3\ntemperatures. b, The change in current as a function of temperature in Kelvins under\n16 electrical pulses.\n The device-to-device variations of CdPS -Li ion-gated transistors.\nThe results demonstrate that each device operates normally, exhibiting consistent\nthreshold voltages and I (Fig. R10a-d). Furthermore, under continuous positive and\non\nnegative pulse, the devices exhibit uniform electrical writing and erasing behavior (Fig.\nR10e and f). Each device demonstrates similar synaptic weight changes under identical\nelectrical pulses and retains non-volatile memory functionality after pulse removal,\nconfirming the uniformity of device performance.\nFigure R10 a, b, The I -V curves (a) and I -V curves (b) of 32 separate devices.\nDS GS GS GS\nc, d, The threshold voltage distribution (c) and I distribution (d) of 32 separate devices.\non\ne, f, The continuous electric writing (e) and erasing (f) process involves 32 individual\ndevices with each achieving at least 64 resistance states, demonstrating good uniformity.\n- The authors utilized light to control the non-linearity of the activation functionality.\nHowever, Fig 3 shows a general trend of light-induced modulation without any\nquantitative analysis, which is insufficient for utilization in the ANN system. Is it a\ngood way to use light to control the non-linearity? Is it possible in practical applications?\nResponse: We thank the reviewer very much for the constructive comment. In the\nrevised manuscript, we conducted a quantitative analysis of the nonlinear behavior of\nthe device, specifically focusing on the relaxation time in relation to the number of\npulses, light intensity, and pulse width. Additionally, we provided a thorough example\nof how to utilize the nonlinear postsynaptic current generated by light pulses as the\nactivation function, highlighting its effectiveness and advantages in practical\napplications.\n The quantitative analysis of nonlinear synaptic behavior under light pulses.\nWhen a light pulse was applied to the CdPS -Li transistor, and a source-drain voltage\n3\nof 100 mV was used to measure its conductance, the device exhibited a nonlinear PSC\n(Fig. 4a). This was primarily attributed to the photo-induced current in MoS , which\n2\ncaused an increase in PSC, followed by a decay process that gradually reaches a\nconstant state (higher than the initial state). Detailed fitting and analysis revealed that\nthe decay curve could be fitted with a double-exponential decay function, y=A 1 e-(x-x 0 )/t 1\n+A 2 e-(x-x 0 )/t 2, implying the presence of both fast and slow decay mechanisms. The initial\nfast decay was primarily due to the unabsorbed photo-generated holes gradually\nreturning to MoS and being neutralized. Meanwhile, some of the photo-generated\n2\nholes were trapped by the Cd vacancies in CdPS -Li, resulting in a slower current decay\n3\nthat eventually stabilized at a constant value.\nThe application of paired light pulses enabled the PPF effects (Fig. R11a-e). The PPF\nratio increased with the reduction of the pulse interval (Fig. R11f). This result could be\nwell fitted with a double-exponential decay function, PPF ratio = C\n0\n+C\n1\ne−Δt/τ 1+C\n2\ne−Δt/τ 2.\nFigure R12 further demonstrated the excitatory PSC responses of the device under a\ntrain of light pulses with varying frequencies. As the pulse frequency increased from 1\nHz to 5 Hz, the cumulative effects became more pronounced, leading to higher\nexcitatory PSC responses.\nFigure R11. a-e, PPF effect, where a pair of light pulses was applied (1.02 mW cm-2,\n1 ms) using 1 V source-drain voltage (V ) to read the device state, with an interval of\nDS\n1.5 ms (a), 2 ms (b), 3 ms (c), 4 ms (d), 4.5 ms (e). f, PPF ratio as a function of the\npulse interval, where the black line represents fitting results using the double\nexponential decay function.\nFigure R12. Excitatory PSC induced by a train of light pulses (1.02 mW cm-2, 10 ms,\nwith frequencies of 1, 2 and 5 Hz) using 1 V V to read the device state.\nDS\nMore importantly, the relaxation time, defined as the time for the inhibitory effect\n(ΔI) to decay to 1/e of its initial value, could be modulated by varying the light intensity,\npulse width, and number of pulses, thereby influencing the fitting function of the PSC\ncurve [Nat. Electron. 5, 761-773 (2022).]. Wider pulse widths and higher light\nintensities increase photo-generated holes in MoS , leading to longer relaxation times\n2\n(Fig. 4d and e). Quantitative analysis showed a roughly linear relaxation time increase\nwith incremental pulse widths and light intensities (Fig. R13). Additionally, under the\nsame light intensity and pulse width, an increased number of light pulses also produced\na stronger cumulative effect, leading to longer relaxation times (Fig. R14).\nFigure R13. a, b, The dependence of relaxation time on pulse widths (a) and light\nintensities (b).\nFigure R14. a-e, PSC obtained with increased light pulse number of 2-6. The light\ndensity is 1.02 mW cm-2 and pulse width are 1 ms. f, The dependence of relaxation time\non pulse number.\n Trainable nonlinear activation functions using nonlinear synaptic behavior\nunder light pulses.\nTrainable activation functions offer significant advantages over fixed ones as they\ncan automatically adjust their shape based on data complexity, thereby enhancing the\nadaptability and performance of neural networks [Neurocomputing, 503, 92-108,\n(2022).]. Our device can generate rich PSCs with varying relaxation times, and each\nnonlinear PSC exhibits a high similarity to activation functions in neural networks, such\nas the sigmoid function (Fig. 1a). Therefore, the rich PSCs of CdPS -Li transistors have\n3\nthe potential to act as trainable nonlinear activation functions.\nWe further investigate the specific process of CdPS -Li ion-gated transistors in\n3\nimplementing trainable activation functions (Fig. R15 and 16). We designed a multi-\nlayer neural network architecture that comprises three convolutional layers, one\nactivation function layer, and channel-wise fully connected layer to accomplish the\nMNIST handwritten digit recognition task (Supplementary Fig. 24). The input image\nsequentially passes through the two convolutional layers, an activation function layer,\na convolutional layer and finally enters the parallel fully connected module to complete\nthe output. The convolutional and fully connected layers in the neural network are\nphysically implemented using a matrix multiplication module (a 16×10 array, Fig. 5a),\nwhile the activation function layers are realized using activation function modules (a\n2×8 array, Fig. R15a).\nIn each epoch, the optimal activation function is determined using a grid search\nalgorithm. This optimal activation function is physically implemented by applying light\npulses with distinct parameters to activation function modules (Fig. R15b), which\ngenerates PSC curves. Notably, all devices in activation function module exhibit similar\nPSC curves under the light pulse, ensuring a high-precision calculation (Fig. R17). Next,\nthe time vector (X = [X , X , X , …, X ]) is derived from the results of the previous\n1 2 3 16\nlayer of the neural network. This vector is used as input to read the current from the\nPSC curve under the light pulse. Each value in this time vector corresponds to the\nspecific time at which the current is measured from an individual device. For example,\nX corresponds to reading the current from the first device at time X , X derives from\n1 1 2\nthe second device at time X , and so forth. These current values are collected to form\n2\nthe output current vector, which completes the computation of the activation function.\nFinally, the output current vector is then converted to the voltage vector for the voltage\ninputs for the subsequent layer of matrix multiplication (Fig. R16).\nFor instance, during the second epoch, grid search algorithm identifies the light pulse\nparameters to be applied as an optical power of 1.02 mW cm-2 and a pulse width of 2\nms. It is noteworthy that all CdPS -Li transistors within the activation function module\n3\nproduce highly consistent PSC curves under light pulses, meeting the requirements for\nhigh-precision computation (Fig. R17). The results from the previous layer of neural\nnetwork computation are represented as X = [4.9, 4.8, 4.9, 5, 4.7, 4.5, 5, 4, 5, 4.7, 4.8,\n2.5, 1.15, 2.25, 3, 4.3], which correspond to the current values read from each device at\ndifferent time intervals. This results in the output current vector I = [0.044, 0.056, 0.044,\n0.032, 0.067, 0.092, 0.032, 0.166, 0.032, 0.067, 0.056, 0.543, 0.705, 0.555, 0.250,\n0.059], thus completing the activation function computation process (Fig. R17).\nFigure R15. a, The optical image of 2×8 array using for activation function. Scale bar\nis 2 μm. b, The output PSC curves of the CdPS -Li ion-gated transistor under light pulse\n3\nduring training epochs in the activation function module.\nFigure R16. The schematic diagram illustrates the forward propagation process\nexecuted by the CdPS -Li ion-gate transistor array, which not only performs MAC but\n3\nalso incorporates a trainable activation function module. The backpropagation process\nis facilitated by external circuits.\nFigure R17. The output PSC curves of the CdPS -Li ion-gated transistor in 2×8 array\n3\nunder light pulse during the second training epochs.\nFigure 5f and R18 show the results of employing a CdPS -Li ionic-gated transistor\n3\narray as a MAC and activation function module for handwritten digit classification. The\nresults reveal that as training progresses, the model's attention increasingly focuses on\nthe key areas of the target digits, while both accuracy and loss stabilized. To verify the\neffectiveness of using the PSC curve from CdPS -Li ion-gated transistors as the\n3\nactivation function, we compared the recognition performance with that of the GPU-\ncomputed trainable Sigmoid activation function. It is noted that both can accurately\nrecognize images. The GPU achieved 98.5% accuracy, while 97.5% accuracy from our\ndevice with training finished at the 30th epoch.\nFigure R18. a, The accuracy as a function of the training epoch, with training finished\nat the 30th epoch, achieved an accuracy of 97.5% and 98.5% by using CdPS -Li ion-\n3\ngate transistor array and GPU, respectively. b, c, The images recognized by the CdPS -\nIn contrast to electrical pulses, light pulses offer a non-contact stimulation method.\nThey do not introduce additional charges or currents, nor do they cause electromagnetic\ninterference in MAC circuits. Additionally, their parameters including intensity,\nfrequency, pulse width, and count can be finely tuned. Thus, we can precisely control\nthe amplitude and shape of postsynaptic currents. This flexible control over activation\nfunction parameters enables the neural network to better adapt to various architectures\nand learning tasks, thereby improving its training accuracy and overall performance.\nMeanwhile, light pulses facilitate rapid responses and low power consumption,\nenabling the lightweight deployment of complex neural networks.\n- The demonstrations in Fig 4 & 5 are outstanding as they show potential applications.\nHowever, the purpose of the demonstration is not clearly indicated. The system's overall\nperformance shown in Fig 4a is assumed to be far below the state-of-the-art GPU\nsystem. The current version may give the reader a false sense that the system performs\nat a comparable level to the current GPU.\nResponse: We sincerely appreciate the reviewer's insightful comments regarding the\nclarification of our demonstrations. To better clarify the purpose of Figs. 4-5, we have\nrevised the manuscript as follows:\nIn this study, we constructed a 16×10 crossbar array (Fig. 5a) as the matrix\nmultiplication module and a 2×8 device array as activation function module (Fig. R15)\nto verify two core capabilities for deep learning implementation. On one hand, the ion-\ngated transistors can output highly linear multilevel resistance states under electrical\npulse, enabling high-precision matrix multiplication. On the other hand, by leveraging\nCd vacancies to trap photo-generated holes, the devices exhibit rich nonlinear behavior,\nwhich can serve as a trainable activation function module for artificial neural networks\n(ANNs), thereby enabling the forward propagation process in ANNs.\nTo avoid the reader misunderstanding, in the revised manuscript, we have changed\nthe statement that \"This performance is higher than that of GPUs along with\nsignificantly reducing energy consumption.\" as follows:\n“Due to the large conductance ratio and high-linearity resistance states of the device,\nthe CNN achieved a training accuracy of 97.5% and a validation accuracy of 96.28%\nafter the 30th epoch (Fig. 5g). These results fully demonstrate that CdPS -Li ionic-gated\n3\ntransistors can not only efficiently perform MAC but also provide nonlinear activation\nfunctions, offering a promising hardware solution for neuromorphic computing (Fig.\n5g and Supplementary Figs. 26).”\nReviewer #3 (Remarks to the Author):\nThis work studied the characteristics of MoS2/CdPS3-Li/Multiplayer graphene\ndevices and their applications for synaptic applications.\nKey claims are 1) Linear control of Li ion movement, 2) Light induced modulated of\ndevice characteristics (primarily hole trapping), 3) 16x10 cross-bar array fabrication, 4)\napplications to CNN training.\nSolid ionic conduction characteristics of CdPS3-Li has been published in Nature\ncomm, 14, 3998 (2023).\nSince the synaptic operations of devices whose conductivity can be controlled\nlinearly have been published so many times, in this review, claim #1 to #3 are examined\nmore closely. However, many missing information and claims presented without detail\njustifications made the review difficult. Followings are the list of missing information\nand questions on the various claims.\nResponse: Thank the reviewer very much for the constructive comments and valuable\nsuggestions. In the revised manuscript, we have supplemented the missing information\nand claims, and provided detailed justifications. Additionally, we have incorporated\nnew experimental data to demonstrate the synaptic behavior of our devices and\nhighlight their advantages. The following is our point-by-point response to the\nreviewer's comments, which we hope to address all the reviewer's concerns.\n1) Why MLG is used as gate? If there is a specific reason to use MLG, please add.\nAlso, correct all description using “graphene” to “multilayer graphene” or “MLG”.\nResponse: We thank the reviewer very much for the constructive comment.\nWe selected multilayer graphene as the gate electrode due to its excellent\nconductivity and high transparency. The excellent conductivity ensures efficient\napplication of the top gate voltage to the device. Additionally, unlike metal electrodes,\nthe high transparency of graphene allows laser penetration to excite MoS and generates\n2\nexcitons. This enables the device a nonlinear synaptic behavior under light pulse\nmodulation, thereby achieving multimodal synaptic behavior under both electrical and\nlight pulse modulation.\nWe have corrected \"graphene\" to \"multilayer graphene\" in the revised manuscript.\n2) What was the thickness and area of MLG? How it is transferred to single device\nand 16x10 array?\nResponse: We thank the reviewer very much for the constructive comment.\nFor individual devices, mechanically exfoliated graphene nanoflakes (thickness ~2.5\nnm, Fig. R19a) from highly oriented pyrolytic graphite (HOPG) were employed. While\nfor device arrays, multi-transferred chemical vapor deposition (CVD)-grown graphene\nfilms were utilized (thickness ~2.5 nm, Fig. R19b and c). The area of graphene\nnanoflakes is over 300 μm2 and that of CVD-grown graphene films is full coverage of\na 1×1 cm2 SiO /Si substrate.\n47, 53-68]. First, 3M scotch tape was gently pressed onto the HOPG surface to ensure\ngood contact. It was then carefully peeled off to exfoliate thin graphene nanoflakes.\nMultiple exfoliation attempts were made to obtain flakes of suitable thickness. After\nthat, the tape was smoothed onto the PDMS surface to ensure close contact between the\ngraphene flakes and the PDMS. The tape was then removed, and suitable sizes and\nthicknesses of the graphene nanoflakes were identified on the PDMS surface.\nSubsequently, the graphene nanoflakes were transferred onto the target device surface,\nfollowed by heating to facilitate their release. Finally, the PDMS was slowly peeled off.\nFor device arrays, monolayer graphene films on Cu substrates were prepared using\nthe CVD method. These films were then transferred onto the target substrate using a\nsolution etching transfer method [Nat. Nanotechnol. 19, 34-43 (2024), Nat. Commun.\n8, 14560 (2017)]. Specifically, the transfer medium, polypropylene carbonate (PPC),\nwas first spin-coated onto the CVD-grown monolayer graphene film. After etching\naway the Cu substrates with a copper etchant (Alfa Chemistry, Ammonia H O (3%)\n2 2\nDI Water), the graphene films were lifted onto the target substrate. Finally, the PPC was\ndissolved in a benzyl ether solution. This process was repeated three times to obtain 3\nL graphene. As the Raman spectra of 19,000 points shown, the transferred graphene\nfilm has good quality with weak D peaks and narrow full width at half maximum\n(FWHM) (Fig. R19d), making it suitable for use as a top gate electrode in large-area\ndevice arrays.\nWe have added thickness and area of MLG, and explained how it is transferred to\nsingle device and 16x10 array in the revised manuscript.\nFigure R19. a, AFM image of graphene nanoflake on SiO /Si substrate. Inset is the\n2\nheight profile along white line. Scale bar, 10 μm. b, The optical microscope image of\nCVD-grown graphene on SiO /Si substrate via layer-by-layer transfer three times. c,\n2\nwhite line. Scale bar, 10 μm. d, The Raman spectra of 19,000 points in b.\n3) Page 3: “The multilayer CdPS3-Li flake has a high dielectric constant of 5.2 and\na wide bandgap of 3.55 eV (Supplementary Fig. 3).” This is a typical example of\nproblems I had while I read through this work. Supp. Fig.3 does not provide proper\ninformation on how dielectric constant or bandgap is determined. Supp. Fig.3a shows\nlarge dispersion from 1Hz to 100KHz. How the author obtained the thickess and\ndielectric constant information from this data?\nResponse: We thank the reviewer very much for the constructive comment.\nWe utilized a parallel-plate capacitor structure to measure the dielectric constant of\nCdPS -Li nanoflakes. As shown in Fig. R2a, multilayer graphene was used as the top\n3\nand bottom electrodes with the CdPS -Li flake sandwiched in between. We measured\n3\nthe capacitance-voltage (C-V) curves at different frequencies using an electrochemical\nworkstation. Based on the obtained curves, we calculated the dielectric constant using\nthe parallel-plate capacitor model, with the formula:\n𝐶 ∙𝑑\n𝜀 = \n𝑟 𝜀 ∙𝐴\n0\nwhere C is the capacitance, d is the thickness of the dielectric layer, A is the electrode\narea, and ε is the vacuum permittivity (8.854×10-12 F/m). From the optical microscope\n0\nimage, we determined the electrode area to be 80 μm². The thickness of the CdPS -Li\n3\nnanoflake was characterized as 70 nm using AFM (Fig. R2b). The capacitance values\nwere extracted from the C-V curves at 0 V.\nThe material's dielectric constant varies with frequency [Nat. Electron. 5, 859-869\n(2022). J. Appl. Phys., 128, 234104 (2020).], and can be categorized the dielectric\nconstant into low-frequency and high-frequency values, with the latter decreasing as\nfrequency increases (Fig. R2d). Generally, high-frequency dielectric constant was used\nfor comparison, typically measured at 1 MHz. We additionally measured the C-V curves\nof the same device using a semiconductor analyzer at 1 MHz (Fig. R2c). The dielectric\nconstant of 5.2 were consistent with those obtained from the electrochemical\nworkstation, confirming the reliability of our results.\nWe measured the absorption spectrum of CdPS -Li using UV-Vis-NIR absorption\n3\nspectroscopy and calculated the bandgap using the equation:\nE=hν/λ\nwhere E represents photon energy, h is the Planck constant, ν is the speed of light,\nand λ denotes wavelength. By converting the x-axis from wavelength to photon energy\n(Fig. R2f), we plot the absorption spectrum against photon energy. The bandgap (E )\ng\ncorresponds to the photon energy at which the absorbance begins to rise sharply. Thus,\nwe determined the bandgap E to be 3.55 eV.\ng\nGiven high dielectric constant and wide bandgap, CdPS -Li is a promising candidate\n3\nas a dielectric layer for MoS transistors. We measured the transfer characteristics of\n2\nmodulation of the channel conductance (Fig. 2b). Additionally, the gate leakage current-\nvoltage curves were measured to be in the fA range, further validating the potential of\nCdPS -Li as an effective dielectric layer (Fig. R2f).\n4) Page 3: “This can be confirmed through Kelvin Probe Force Microscopy (s)\nmeasurements (Fig. 1d and Supplementary Fig. 9 ).” I can’t see how the data shown in\nFig.1d and Supp. Fig.9 confirm the “strong io-electron coupling effect”. The authors\nshould explain more details. From now on, this kind of problem will be listed as\n“unjustified claim”.\nResponse: We thank the reviewer very much for the constructive comment.\nWe employed Kelvin Probe Force Microscopy (KPFM) to probe the interfacial ion-\nelectron coupling effect between CdPS -Li and MoS . The sample is prepared by\n3 2\ntransferring MoS on a gold coated silicon substrate, with CdPS -Li vertically stacked\n2 3\non the top of MoS (Supplementary Fig. 10a in revised manuscript). The gold coated\n2\nsilicon surface acts as the reference potential, while a voltage is applied to the CdPS -\n2 2\nsurface, forming an electric double layer and creating a pronounced ion-electron\ncoupling effect [Nat. Mater. 18, 141-148 (2019). Adv. Funct. Mater. 31, 2100069\n(2021)]. This process reduces the Fermi level (work function) of MoS , thereby such\n2\nchanges can be verified through KPFM.\nWe have added the related explanation in the revised manuscript as follows.\nThe \"strong ion-electron coupling effect\" refers to the phenomenon where, after the\nvoltage is removed, the change in surface potential caused by ion-electron coupling\neffect does not decay significantly. When a positive voltage is applied to the CdPS -\n2 3 2\nsurface (Fig. R20). We measured the potential after the voltage was applied, which\nindicates a 0.55 eV decrease in the work function of MoS (Fig. R21a, b and Fig. R21e).\n2\n5-min intervals, observing a slight increase of the potential (Fig. R21c, d and e).\nThis indicates that, due to the anisotropic ionic transport properties of CdPS -Li,\n3\nonly a small amount of Li+ detaches from the interface, with the majority remaining\nstored, thereby resulting in a strong ion-electron coupling effect.\nWe have added the above discussion in the revised manuscript.\nFigure R20. Schematic diagram of CdPS -Li transistors under positive gate voltage,\n3\nillustrating the transport of Li+ at the interface to enhance the ion-electron coupling\neffect.\nFigure R21. a-d, The surface potential images of the 2D CdPS -Li/MoS\n3 2\nheterojunction on an Au/SiO /Si substrate were measured before (a) and after applying\n2\nthe gate pulse (b), after removing voltage at 1 min (c) and 5 min intervals (d). e, the\ncorresponding potential profiles along the white lines in a-d. Scale bars, 5 μm.\n5) Page 3: “In contrast, the CdPS3-Li strongly restricts the out-plane transport of Li+\n(Fig.1c, Supplementary Fig. 4: - unjustified claim. Also, I wonder whether the authors\nexcluded the impact of contact resistance from the measurement. Otherwise,\nconduction behavior would be dominated by the contact resistance.\nResponse: We thank the reviewer very much for the constructive comment.\nThe Cd vacancies in CdPS -Li enable the crystals excellent hydration ability and\n3\nexceptional hydrophilicity (Fig. R22a), resulting in a significantly expanded interlayer\nspacing (12.5 Å) under ambient conditions (~40% RH, 28 °C) (Fig. 1d), which\ncorresponds to the intercalation of bilayer water molecules. Importantly, the crystals\nintercalated with water remain the well-ordered layered structure. Such highly\nanisotropic layered structure leads to a significant difference in the transport barriers\nbetween the in-plane and out-plane directions. Because of the well-ordered\nnanochannels and widened interlayer spacing, Li+ can rapidly transport along the in-\nplane direction through interlayer water molecules. In contrast, the CdPS -Li layers\n3\nstrongly restrict the out-plane transport of Li+ [Science 370,596-600(2020); Nat.\nCommun. 14, 3998 (2023).].\nThe in-plane and out-plane ionic conductivities were measured using\nelectrochemical impedance spectroscopy (Fig. 1h). The device used for in-plane ion\nconductivity measurement consists of parallel graphene electrodes with the following\ntransfer of the CdPS -Li nanoflake on the surfaces (Fig. R22b). For the measurement\n3\nof out-plane ionic conductivity, the CdPS -Li nanoflake is sandwiched between the top\n3\nand bottom graphene electrodes (Fig. R2a). We calculated the ionic conductivities\naccording to the formula:\n𝐿\n𝜎 = ,\n𝑅 𝑆\nwhere L represents the length of the CdPS -Li nanoflake; R is the resistance, obtained\n3\nfrom impedance spectroscopy; and S is the cross-sectional area of the CdPS -Li\n3\nnanoflake. Notably, the in-plane ionic conductivity is 0.134 S cm-1, while the out-plane\nionic conductivity significantly decreases to 0.0258 S cm-1 (Fig. 1h). Such substantial\nionic conductivity difference confirms the anisotropic nature of ionic transport in the\nmaterial.\nTheoretically, graphene, being a semi-metallic material, is more prone to forming\nOhmic contacts compared to traditional metal electrodes [Nano Lett. 2013, 13, 4001-\n4005]. We experimentally measured the I-V curves of both in-plane and out-plane ionic\nconductivity devices, which exhibited highly linear characteristics, confirming the\nOhmic contact of the interface (Fig. R22c).\nFigure R22. a, Water contact angle on a CdPS -Li crystal. b, The optical microscope\n3\nimage of the device used for in-plane ion conductivity measurement. c, The I-V curves\nof the device used for in-plane and out-plane ion conductivity measurement.\nWe have added related explanations in the revised manuscript.\n6) Page 3: “indicating an increased number of particles transitioning from the ground\nstate to the excited state (Fig.1g and h ).”. The authors should explain more how Fig.1g\nand h can lead to the claims on the increase in excitation. Which part of device is\nanalyzed? How it is measured? Is there any uniformity problem? What was the spot\nsize of fs-TA? Why the figure caption mentioned “mapping” while the data is decay\ntime versus wavelengths?\nResponse: We thank the reviewer very much for the constructive comment.\nfs-TA was employed to investigate the carrier dynamics in the CdPS -Li/MoS\n3 2\nheterojunction. As shown in Fig. 2d and 2e in revised manuscript, MoS exhibited a\n2\ndistinct negative absorption band in the range of 640-670 nm, accompanied by a\npositive photoinduced absorption band from 675-725 nm. The negative absorption band\noriginated from photoexcited electrons transitioning from the conduction band to\nvacancy centers, while the positive absorption band was attributed to signals from\nphoto-generated holes. In comparison to MoS , the intensities of both the negative and\n2\npositive absorption bands were significantly enhanced in the CdPS -Li/MoS\n3 2\nheterojunction. This enhancement suggests that photoexcited electrons transfer from\nthe conduction band to vacancy centers in CdPS -Li, thereby intensifying the dynamics\n3\nof photo-generated carriers and demonstrating that this behavior can be effectively\nmodulated by Cd vacancy defects.\nAdditionally, the decay curves of MoS and the CdPS -Li/MoS heterojunction at\n2 3 2\n428 nm were recorded and fitted using a bi-exponential function to investigate the\ndynamics of photo-generated holes (Supplementary Figure 11c). The shorter time\nconstant (τ₁) and the longer time constant (τ₂) correspond to the processes of photo-\ngenerated holes being captured by shallow and deep trap states, respectively. Compared\nto standalone MoS (τ₁ = 18 ps, τ₂ = 111 ps), the CdPS -Li/MoS heterojunction exhibits\n2 3 2\nextended hole lifetime (τ₁ = 29 ps, τ₂ = 227 ps), suggesting the presence of additional\ninterfacial hole transfer channels. This confirms that Cd vacancies in CdPS -Li can\n3\ncapture photo-generated holes from MoS .\npump beam of 340 nm (~200 μW) fs laser was obtained to excite the MoS /CdPS -Li\n2 3\nheterojunction. The probe beam was focused on the center of the pump beam (2 mm in\ndiameter) on the sample. All measurements were performed at room temperature under\naerated conditions. The laser spot completely covers the sample area, ensuring that the\nfemtosecond transient absorption spectrum accurately represents the entire\nheterojunction. Therefore, there are no issues with uniformity.\nIn fs-TA experiments, \"mapping\" is common terminology, which denotes to the\nvisualization of transient absorption data across the wavelength versus time delay\n[Angew. Chem. Int. Ed. 63, e202405756 (2024)]. This mapping allows researchers to\nobserve how transient absorption changes with both wavelength and time after\nphotoexcitation, providing insights into the dynamics of excited states.\nWe have added the above discussion in the revised manuscript.\n7) Fig.2a,b shows relaxation in the order of 5-10s. Explain the mechanism. Also, add\ndevice size information (channel length and width). I guess Fig.2a was obtained by\napplying 200mV Vg pulse for 1s and then -200mV was applied for 1s for the same\ndevice. If this is right, the author should provide detail sequences. Also, explain why\nthere is a strong current level change even after 1s. Also, after 80s, how much (what %)\nis the change in the current level. These details are important to conform the stability\nof the synaptic device.\nResponse: We thank the reviewer very much for the constructive comment. We have\nadded the following details in the revised manuscript.\nThe channel length and width of the device are 5 μm and 4 μm (Fig. R1a),\nrespectively. In original Fig. 2a and b (Fig. 3a and b in the revised manuscript), the\ncurrent changes were obtained by applying a positive voltage of 200 mV and a negative\nvoltage pulse of -200 mV, each with a width of 1 ms.\nIn CdPS -Li, Li+ occupies negatively charged vacancies to maintain the material's\n3\nelectrical neutrality. When a positive gate voltage is applied, Li⁺ can overcome the both\nCoulombic interactions with these vacancies and the interlayer barrier, facilitating its\ntransport to the CdPS -Li/MoS interface. After the removal of voltage, a small portion\n3 2\nof the ions detaches from the interface due to Coulombic interactions with the vacancies,\nwhile the majority of Li+ ions remain stored at the interface due to the anisotropic ionic\ntransport properties of CdPS -Li. This allows a strong current level change even after\n3\n1s and then the current to a stable level for non-volatile storage (Fig. 3a). Conversely,\na negative gate voltage pulse induces the removal of Li+ from the interface, leading to\na decrease in channel conductivity (Fig. 3b).\nAs shown in Fig. 3a, under positive voltage, the spike current is 41 nA stabilizing at\na constant current of 32 nA after 80 s with a decay ratio of 21.9 %. While under a\nnegative voltage (Fig. 3b), the spike current is 20 nA, stabilizing at a constant current\nof 23 nA (15 % decay).\n8) Fig.2c should provide quantitative assessment in stead of “long retention time. #%\nafter 10000s value should be provided.\nResponse: We thank the reviewer very much for the constructive comment.\nAt the initial state (t = 0 s), the current in the high-resistance state (HRS) was\nmeasured at 2.35 pA, while the current in the low-resistance state was 400 nA. After\n10,000 seconds, the current in the LRS decreased to 258 nA, corresponding to a decay\nof 37.5%, whereas the current in the HRS increased to 2.55 pA, indicating an increase\nof 8.5%. These results demonstrate excellent long-term retention characteristics.\nMoreover, to enhance the clarity of the data analysis, we performed an exponential\nfit of I as a function of time using the asymptotic function (y = a + b x) for both the\nDS\nLRS and HRS (Fig. R23). The parameters for the exponential fit were shown as follows:\na = -7.267 × 106 and b = -0.07296 for LRS, a = -12.733×106 and b = 0.07281 for HRS.\nWe defined the criterion for conductance state failure as the point at which the\nconductance value of the HRS intersects with that of the LRS. This intersection was\nreferred to as the conductance retention time [ACS Nano, 15, 17214-17231(2021). Nat.\nElectron. 3, 371-382 (2020). Adv. Sci. 2502286, (2025).]. From the results of the\nexponential fit, the HRS and LRS of the device can be maintained for up to 5 years.\nWe have provided quantitative assessment instead of “long retention time” in the\nrevised manuscript.\nFigure R23. Retention tests of 2D CdPS -Li ion-gated transistor at V =-100 mV. The\nlow and high resistance states (LRS and HRS) were induced by applying gate voltage\nof +3 V and -3 V, respectively. The pulse width was 1 s.\n9) Fig.2a,b shows a strong time dependence after 1s pulse application. Fig.2d was\nobtained 1ms and 5s interval. Then, current was measure after 5s? Fig.2 a,b shows there\nmight be some transient behavior after 5s. Supp. Fig.20 shows a more than +/-10%\ndevice current variation. Then, Fig.2d is obtained form single device? What happens if\nthe same pulse measurement is performed to other devices?\nResponse: We thank the reviewer very much for the constructive comment.\nFor original Fig. 2d (Fig. 3d in the revised manuscript), we applied gate voltage\npulses of 200 mV and -200 mV for the writing and erasing processes, respectively, each\nwith a pulse width of 1 ms and an interval of 5 s. Following a 5 s decay, the current\nstabilized without transient behavior, indicating non-volatile storage (Fig. 3a and b).\nTherefore, we measured the non-volatile current of the device after 5 s. In the original\nmanuscript, data were obtained from a single device. In the revised version, we\nconducted a statistical analysis involving 32 individual devices. Each device was\napplied over 128 continuous electrical writing and erasing pulses, achieving high\nlinearity in both the writing and erasing processes (Fig.R24 and 25).\nFigure R24. a, The continuous electrical writing process involves 32 individual devices\nwith each achieving at least 64 resistance states demonstrating good uniformity. b-g,\nEnlarged views of different regions in a.\nFigure R25. a, The continuous electrical erasing process involves 32 individual devices\nwith each achieving at least 64 resistance states. b-g, Enlarged views of different\nregions in a.\n10) Fig.2e claims 64 state separation is possible by varying the current level from 25nA\nto 85nA. This might be from a single device. If there is a finite memory window change\nas shown in Fig.2c and if there is a device to device variation, this kind of state\nseparation is not possible. The claim for the feasibility of state separation should\nconsider these limitations. Thus, Fig.1e,f are too aggressive claim that can not be\nrealized.\nResponse: We thank the reviewer very much for the constructive comment.\nThe original Fig. 2c (Fig. 3c in the revised manuscript) shows a large conductance\nratio exceeding 105. This large conductance ratio provides a broad dynamic\nconductance range from 2 pA to 0.4 μA, enabling the device to support at least 64\ndistinct resistance states. In the revised manuscript, we evaluated 32 independent\ndevices using consecutive electrical pulses for both writing and erasing. The results\nindicated that each device can achieve at least 64 distinct resistance states with high\nlinearity in both the writing and erasing processes (Fig. R24 and 25). Importantly,\ndevice to device is nearly identical with little variation and each state of each device is\ndistinct, with no overlap observed during either the writing or erasing processes.\nTherefore Fig.1e, f (Fig. 3 d and e in the revised manuscript) can be realized.\n11) When measure the current shown in Fig.2e, what was the gate bias? If it was not\n0V, was there additional shift due to the Vg? If it was 0V, how 25-85nA is obtained?\nThis kind of detail information should be added.\nResponse: We thank the reviewer very much for the constructive comment.\nFigure 2e (Fig. 3e in the revised manuscript) illustrates the resistance states of the\nCdPS -Li transistor, with the read voltage ranging from 0 to -1 V. The testing process\n3\nincludes resistance state adjustment and resistance state reading [Nature 615, 823-829\n(2023). Nat. Commun. 16, 4925 (2025).]. For state adjustment process, a gate voltage\npulse of +200 mV with a pulse width of 1 ms, generated by a signal generator, was\napplied to the top gate electrode while the source-drain voltage was maintained at 0 V.\nFor the resistance state reading, the channel conductance was characterized after a 5 s\ndelay to allow currents to stabilize. A source-drain voltage sweeping from 0 to -1 V was\napplied without gate bias, across the MoS channel, and the I -V characteristic\ncurves were measured. For each applied gate voltage pulse that adjusted the resistance\nstate, the resistance state was subsequently read, and this process was repeated 64 gate\nvoltage pulses, yielding the adjustment of 64 resistance states.\nWe have added the experimental details in the revised manuscript.\n12) Fig.2g,h needs more explanation. Why 100mV pulse shows decay? What 1ms pulse\ndoes not show decay while Fig.2a,b shows the decay?\nResponse: We thank the reviewer very much for the constructive comment.\nWhen applying a positive gate voltage pulse to CdPS -Li ion gated transistors, Li+\n3\nwould transport to the CdPS -Li/MoS interface and generate ion-electron coupling\n3 2\neffects, thereby enhancing channel conductivity to obtain a spike current. Upon\nremoving the voltage, the majority Li+ could be remained at the interface, resulting in\na non-volatile storage and generating a memory current as shown in Fig. 2a (Fig. 3a in\nthe revised manuscript). Conversely, a negative gate voltage pulse induced the removal\nof Li+ from the interface, leading to a decrease in channel conductivity as shown in Fig.\n2b (Fig. 3b in the revised manuscript).\nThe magnitude and pulse width of the gate voltage can significantly influence Li+\ntransport and storage behavior, thereby impacting the current decay. The parameters of\ngate voltage pulse applied to the device in Fig. 2a, b and g, h (Fig. 3a, b and h, i in the\nrevised manuscript) are different. In Fig. 2a and b (Fig. 3a and b in the revised\nmanuscript), the applied gate voltage pulses were 200 mV and 1 ms width. In Fig. 2g\n(Fig. 3h in the revised manuscript), the voltage ranged from 100 mV to 1.5 V with a\nfixed pulse width of 1 ms. In Fig. 2h (Fig. 3i in the revised manuscript), the pulse width\nvaried from 10 μs to 1 ms at a constant voltage of 500 mV. As shown in Fig. 3h and Fig.\n3i, under the same pulse as Fig. 3a and b (200 mV, 1 ms), the current exhibits a similar\ndecay behavior. However, as the gate voltage or pulse width gradually increases, the\ndegree of current decay progressively decreases.\nIn CdPS -Li, Li+ occupies negatively charged vacancies to maintain the material's\n3\nelectrical neutrality. When a positive gate voltage is applied, Li⁺ must overcome not\nonly the out-plane transport barrier but also the Coulombic interaction with these\nvacancies. Under higher voltages and wider pulse widths, Li+ gain increased energy,\nenabling them to more effectively overcome energy barriers. Even after the voltage is\nremoved, the Li+ at the interface retain sufficient energy to counteract the Coulomb\ninteraction force between vacancies and Li+, thereby reducing Li+ detachment and\nmitigating current decay. Conversely, lower voltages or shorter pulse widths do not\nprovide sufficient energy for Li+. As a result, they are unable to fully overcome the\nCoulomb interaction force, which leads to an increased detachment of Li+ from the\ninterface and a more pronounced decay in current.\nThe extent of current decay is correlated with the magnitude of the applied voltage\nand the pulse width, exhibiting synaptic behaviors similar to those reported in previous\nstudies [Nat. Nanotechnol. 20, 93-103 (2025). Sci. Adv. 6, eabc 6389(2020)]. To\nquantitatively analyze current decay under varying voltage and pulse width conditions,\nwe applied voltage pulses with different parameters to the device (Fig. R4). The results\nconfirm that higher voltages and wider pulses significantly reduce the current decay\nratio. Therefore, the 100 mV 1 ms and 200 mV 1 ms electrical pulses exhibit decay,\nwhile the 500 mV 1 ms electrical pulse does not show decay.\nWe have added the related explanations in the revised manuscript.\n13) For the measurement shown in Fig.3, what was the device size, bias condition, beam\nuniformity, beam size, wavelength?\nResponse: We thank the reviewer very much for the constructive comment.\nThe optical image of the device is depicted in Fig. R26a. The width and length of the\nchannel of the device are 5 μm and 4 μm, respectively.\nIn Fig. 3a (Fig. 4a in the revised manuscript), the measurement was performed at V\nDS\n= 100 mV with light pulse intensity of 1.05 mW cm-2, and a pulse width of 1 ms. In Fig.\n3b (Fig. 4d in the revised manuscript), the measurement was performed at V = 100\nDS\nmV, V = 0 V, with light pulse intensity of 1.05 mW cm-2, and a pulse width of\nGS\n0.1, 0.2, 0.5, 0.8, 1, 1.2, 1.5, 2, 2.5 and 3 ms. In Fig. 3c (Fig. 4e in the revised\nmanuscript), the measurement was performed at V = 100 mV, V = 0 V with varying\nDS GS\nlight pulse intensity of 1.02, 1.72, 2.42, 3.15, 3.85, 4.56, 5.22, 5.90, 6.62 and\n7.22 mW cm-2, and a pulse width of 2 ms.\nThe laser has a diameter of 320.06 μm and a wavelength of 516 nm. The intensity of\nthe laser spot is uniform, approximately following a Gaussian distribution from the\ncentral region to the edge (Fig. R26b).\nWe have added the device size and measurement conditions including bias, beam\nuniformity, beam size, wavelength in the revised manuscript.\nFigure R26. a, The optical microscope image of CdPS -Li ion-gated transistor. Scale\n3\nbar, 5 μm. b, An optical microscope image of a SiO /Si substrate illuminated by the\n2\nlaser, displaying a laser spot diameter of 320.06 µm. The wavelength of the laser is 516\nnm.\n14) Fig.3f, what was the laser pulse width? How they are controlled? Electro-optic or\nmechanical? Is the laser pulse rise and fall time fast enough compared to the electrical\nmeasurement? Due to a strong transient detrapping beahviors, it might be difficult to\ndefine a specific Id values. How and when Id was defined?\nResponse: We thank the reviewer very much for the constructive comment.\nIn Fig. 3f (Fig. 4g in the revised manuscript), the pulse width is 2 ms, which is\nelectro-optically regulated by a laser controller (Fig. R27a). Electrical measurements\nare conducted using a B1500A semiconductor analyzer, which can detect pulses as short\nas 1 μs. This is adequate to record laser-induced current changes in the device at\nrising/falling edges. It accurately captures transitions even under 1 ms light pulses (Fig.\nR27b and c). The laser employed can generate light pulses as short as 10 μs, meeting\nthe device testing requirements.\nFigure R27. a, A photo of the laser controller, which electro-optically regulates laser\npulses. The adjustable parameters include pulse width, pulse interval, light intensity,\nand frequency. b, PSC generated by the CdPS -Li ion-gated transistor under 1 ms light\n3\npulses. c, An enlarged view of the area within the box in b, illustrating the rise and fall\ntimes of the current, which facilitates precise reading and collection of laser-induced\ncurrent changes.\nUnder a light pulse, the PSC curve generated by the device is utilized to implement\nthe activation function. The specific definition of I values is determined by the output\nDS\ntime vector of the previous layer of the neural network, which serves as the input for\nthe current layer when applying activation functions. Below, we illustrate how to define\nspecific I values for CdPS -Li ion-gated transistors in the context of the MNIST\nDS 3\nhandwritten digit recognition task, demonstrating their role in realizing trainable\nactivation functions.\nWe designed a multi-layer neural network architecture that comprises three\nconvolutional layers, one activation function layer, and channel-wise fully connected\nlayer to accomplish the MNIST handwritten digit recognition task (Supplementary Fig.\n24). The input image sequentially passes through two convolutional layers, activation\nfunction layer, convolutional layer, and finally enters the parallel fully connected\nmodule to complete the output. The convolutional and fully connected layers in the\nneural network are physically implemented using a matrix multiplication module (a\n16×10 array, Fig. 5a), while the activation function layer is realized using activation\nfunction module (a 2×8 array, Fig. R15a).\nIn each epoch, the optimal activation function is identified using a grid search\nalgorithm. This adjustment is physically implemented by first applying light pulses with\nd\ni\ns\nt\ni\nn\nc\nt\np\na\nr\nFor instance, during the second epoch, grid search algorithm identifies the light pulse\na\nm\ne\nt\nparameters to be applied as an optical power of 1.02 mW cm-2 and a pulse width of 2\nms. It is noteworthy that all CdPS -Li transistors within the activation function module\n3\nproduce highly consistent PSC curves under light pulses, meeting the requirements for\nhigh-precision computation (Fig. R17). The results from the previous layer of neural\nnetwork computation are represented as X = [4.9, 4.8, 4.9, 5, 4.7, 4.5, 5, 4, 5, 4.7, 4.8,\n2.5, 1.15, 2.25, 3, 4.3], which correspond to the current values read from each device at\ndifferent time intervals. This results in the output current vector I = [0.044, 0.056, 0.044,\n0.032, 0.067, 0.092, 0.032, 0.166, 0.032, 0.067, 0.056, 0.543, 0.705, 0.555, 0.250,\n0.059], thus completing the activation function computation process (Fig. R17).\n15) In Fig, 4a. please provide more magnified picture shown the actual cell device. Also,\nIn the method section, the authors mentioned that MLG is transferred first as a bottom\ngate. What is the reason for this change from the schematic shown in Fig.1a?\nResponse: We thank the reviewer very much for the constructive comment.\nAccording to the reviewer’s suggestion, we have provided more magnified pictures\n(Fig. R28) to show the actual cell device. The reason for transferring the MLG as a\nbottom gate is that it establishes a stable electric field foundation and aids in the control\nof Li+ transport and storage. In conjunction with the top gate, which primarily facilitates\nLi+ migration to modulate channel conductance, this configuration enhances\nindependent device control and prevents crosstalk between devices during write and\nerase operations.\nOriginal Fig. 1a showed the schematic structure of single transistor, while in the\nmethod section, we used MLG as a bottom gate for device array. Compared to single\ndevices, integrating devices into arrays for matrix multiplication (MAC) necessitates\nthe prevention of crosstalk between different components. Therefore, during the\nfabrication of array devices, a crossbar configuration was employed to effectively\nminimize crosstalk and enable independent control of each device. In this case, only\nthe device located at the intersection of the selected top gate and bottom gate is activated.\nThe crossbar configuration is analogous to the configurations used in memristor and\nferroelectric memory arrays for MAC operations [Nature 624, 551-556 (2023).\nNature 577, 641-646 (2020).].\nWe further verified the effectiveness of this crossbar device configuration in\nfacilitating independent device control and preventing crosstalk between devices. For\nexample, to enhance the conductivity of the device located at row 1, column 1, a\nnegative gate voltage of -1 V is applied to the bottom gate of the first row, while the\nother rows receive positive gate voltages of 1 V. Simultaneously, a positive gate voltage\npulse of 200 mV is applied to the top gate of the first column. The source-drain electrode\nof row 1 is utilized to measure the change in device conductance for electrical writing\nprocess (Fig. R29a, 30a and b). It is observed that the conductance of the device\ngradually increases with the number of pulses, while the resistance states of the other\ndevices remain unchanged. Conversely, to reduce the conductance (for electrical\nerasing) of the device at row 1, column 1, a positive gate voltage is applied to the bottom\ngate of the first row, while the other rows are subjected to negative gate voltages.\nSubsequently, a negative gate voltage pulse of -200 mV is applied to the top gate of the\nfirst column. In this configuration, only the conductance of the selected device is\nmodulated, leaving the other devices unaffected (Fig. R29b, 30c and d). This selective\nactivation ensures precise control over individual devices within the array, facilitating\nefficient operation and minimizing interference between adjacent devices.\nFigure R28. a, b, The optical microscope image of the CdPS -Li ion-gated transistor\n3\narray at 50× (a) and 100× (b) magnification. Scale bar, 10 μm in a and 2 μm in b.\nFigure R29. a, b, A schematic diagram illustrating the modulation of electrical writing\n(a) and erasing processes (b) for the device located at the intersection of the first row\nand the first column within a CdPS -Li ion-gated transistor array.\nDS\nthe first row (a) and the second row (b), when the device located at the intersection of\nthe first row and the first column is activated and a positive top-gate voltage pulse is\napplied through the first line. c, d, The electrical erasing process reads the changes in\nI over time in the first row (c) and performs the same analysis for the second row (d),\nDS\nwhen the device located at the intersection of the first row and the first column is\nactivated and a negative top-gate voltage pulse is applied through the first line.\n16) Supp. Fig.27 shows the schematic of device fabrication flow. The authors showed\nfigures indicating large area BN and MoS2 transfer. What was the area? Then, why the\nauthors mentioned in the main text flake transfer?\nResponse: We thank the reviewer very much for the constructive comment.\nIn this study, individual devices used mechanically exfoliated graphene, BN, and\nMoS nanoflakes, while array devices used the chemical vapor deposition (CVD)-\n2\ngrown graphene, BN, and MoS films to achieve larger dimensions. These films\n2\ncompletely cover the surfaces of 1×1 cm2 Cu and sapphire substrates.\nWe have added the related explanations in the revised manuscript.\n17) If the area of array is fully covered with MoS2 and BN, the area should be more\nthan 50umz50um. Th authors need to provide more information about the MoS2 and\nBN formation and transfer process and their yield. Are the 16x10 array devices (160\ncells) all working? What is the device distribution? There are many missing information\nrelated to array device fabrication and characeristics.\nResponse: We thank the reviewer very much for the constructive suggestion. We used\nconventional photolithography, O-plasma and reactive ion etching to realize the\nintegration of array devices. In the revised manuscript, we have provided detailed\ninformation of materials and fabrication process of CdPS -Li ion-gated transistor\n3\ndevice array, as shown below.\nMaterials for CdPS -Li ion-gated transistor array: In CdPS -Li ion-gated transistor\n3 3\narray, MoS , BN, graphene and CdPS -Li serve as the channel layer, bottom dielectric\n2 3\nlayer, top and bottom gate electrode, and top dielectric layer, respectively. Monolayer\nMoS film on sapphire substrate, 10-layer BN on Cu, and monolayer graphene film on\nBefore use, these 2D material films were transferred onto the target substrate by a\nsolution etching transfer method [Nat. Nanotechnol. 19, 34-43 (2024), Nat. Commun.\n8, 14560 (2017)]. In detail, the transfer medium, polypropylene carbonate (PPC) was\nfirst spin-coated on the CVD-grown film. After etching away the sapphire or Cu\nsubstrates by H PO or copper etchant (Alfa Chemistry), the 2D material films were\n3 4\nlifted by the target substrate. Finally, the PPC was washed off in a benzyl ether solution.\nNote that, MLG were obtained by repeating the transfer process three times. This\ntransfer process effectively maintains the film integrity and prevents damage (Fig.\nR19b), making it suitable for constructing large-area device arrays. CdPS -Li nanoflake\n3\nwas obtained by the mechanical exfoliation from CdPS -Li crystal. The process begins\n3\nwith mechanically exfoliating CdPS -Li single crystals using 3M scotch tape into\n3\nof the desired size, a pre-fabricated PPC/PDMS stamp is carefully attached to the\nsilicon wafer with CdPS -Li nanoflakes. By leveraging the adhesive properties of PPC\n3\nand PDMS during the heating and cooling processes, the PPC and nanoflakes are lifted\nand transferred from the PDMS substrate to the target substrate. During this attachment\nprocess, it is crucial to ensure good contact between the nanoflakes and the substrate\nwhile avoiding the formation of bubbles or wrinkles. After transfer, the PPC is removed\nby immersing in anisole solution.\nFabrication of 16×10 CdPS -Li ion-gated transistor array for MAC: We first\n3\ntransferred CVD-grown graphene film from Cu onto SiO /Si substrate and patterned it\n2\nusing EBL (ABM/6/350/NUV/DCCD/M) with an exposure time of 4.5 s and oxygen\nplasma (PR500) technology for bottom gate (Fig. R31a-c and Fig. R32a). Then, we\ndeposited electrodes of 5 nm Ti/20 nm Au by electron beam deposition with the ULVAC\nei-501z system for ‘word line’ (Fig. R31d and Fig. R32b). The deposition rates are 0.13\nnm/s for Ti and 0.19 nm/s for Au. Next, we transferred the BN thin films and etched\naway the excess areas by the RIE-10NR reactive ion etching to serve as bottom\ndielectric material (a gas ratio of CF : O = 20 sccm: 4 sccm, a gas pressure of 2 Pa, a\n3 2\npower setting of 50 W, and a reaction time of 2 mins) (Fig. R31e and Fig. R32c). Then,\nwe transferred CVD-grown MoS film from sapphire onto surface of BN and patterned\n2\nit using EBL and oxygen plasma technology (Fig. R31 f, g and Fig. R32d). Then, we\ndeposited electrodes of 5 nm Ti/20 nm Au by electron beam deposition with the ULVAC\nei-501z system for source-drain electrodes of the MoS transistors on the same row (Fig.\n3\nthe device surface using a dry method with PPC/PDMS as the transfer stamp (Fig. R31i\nand Fig. R32f). Subsequently, we transfer 3L graphene onto the surface of the device\nand patterned it using EBL and oxygen plasma technology (Fig. R31j, k and Fig. R32g,\nh). Finally, we deposited ‘bit line’ electrodes of Ti/Au to connect the gate electrodes of\ntransistors by electron beam deposition to obtain the device array (Fig. R31l).\nThe area of the device array is 50 μm × 50 μm. The multilayer graphene, MoS , and\n3\nthrough mechanical exfoliation, measures 50 μm × 60 μm. All of these materials can\nfully cover the device area (Fig. R32g, h).\nFigure R31. The fabrication process of the 16×10 device array. a, The substrate of\na silicon wafer with a 300 nm SiO layer. b, transfer multilayer graphene films as\n2\nbottom gate electrode. c, pattern the multilayer graphene using electron beam\nlithography (EBL) and oxygen plasma technology. d, deposition of Ti (5 nm)/Au (20\nnm) electrodes as ‘word lines’. e, transfer multilayer BN films and etch away the excess\nareas to serve as bottom dielectric material. f, transfer monolayer MoS film as channel\n2\nmaterial. g, pattern MoS using EBL and oxygen plasma technology. h, deposition of\n3\nnanoflake as top dielectric material. j, transfer multilayer graphene as top gate electrode.\nk, patterning multilayer graphene using EBL and oxygen plasma technology. l,\ndeposition of Ti (5 nm)/Au (20 nm) electrodes as ‘bit lines’.\nFigure R32. Photograph of the fabrication process for the 16×10 device array.\na,\nTransfer graphene and pattern it using EBL and O plasma as the bottom gate. b,\nbeam deposition. c, Transfer multilayer BN and etch away the excess areas as the\nbottom dielectric layer. d, Transfer monolayer MoS as the channel material and pattern\n2\nit using EBL and O plasma. e, Deposit Ti (5 nm)/Au (20 nm) source/drain electrodes\n2\nusing electron beam deposition. f, Transfer CdPS -Li nanoflakes as the top dielectric\n3\nlayer. g, Transfer 3L graphene as the top-gate electrodes. h, Pattern graphene using EBL\nand O plasma, and deposit Ti (5 nm)/Au (20 nm) as “bit lines”. Scale bars, 5 μm.\nn\nWe have added the related results in the revised manuscript.\nt\nh\ne\ne\nx\np\ne\nr\ni\nm\ne\nn\ntF\n,i\ng\nau\nlr\nle\n1R\non\ndevices in a 16×10 device array.\n18) Page 12: “It is worth noting that the device in MAC operations exhibited good\nuniformity (Supplementary Figs. 20).”. Supp. Fig.20 shows at least +/-10% Id variation\nand more than 0.5V Vth variation. The authors should provide detail numbers instead\nof claiming “good uniformity”.\nResponse: We thank the reviewer very much for the constructive suggestion.\nWe tested the transfer characteristics of each device in the 16×10 array of CdPS -Li\n3\ntransistor array and statistically analyzed the threshold voltage and on-state current of\n153 effective devices (Fig. R33 and R34). The results show that the errors in threshold\nvoltage and on-state current are 10% and 5%, respectively, which demonstrates good\nuniformity.\nWe have added the above discussion in the revised manuscript.\n19) Supp., Fig.2b and c. What is the size of scale bar?\nResponse: We thank the reviewer very much for pointing out our oversight. The size\nof scale bar is 2 μm. We have added it in the revised manuscript.\n20) Supp. Fig.10c should be shown in log scale and two curves should be labeled.\nResponse: We thank the reviewer very much for the constructive suggestion.\nAccording to the reviewer’s suggestion, we have added the log scale for the curves\nand labeled them accordingly (Fig. R2f) in the revised manuscript."}, {"round": 2, "reviewer_comments": {"reviewer_1": "The authors have adequately addressed certain aspects of my comments. Nonetheless, I remain unconvinced regarding the necessity of multimodal devices (electrical and optical) for in-memory computing and possess several questions and concerns about the current version.\nThe primary objective of this study is to develop multimodal ion-gated transistors for in-memory computing. Given that the device is responsible for handling electrical and optical signals, both types of inputs are employed for multiply-accumulate (MAC) and activation operations, respectively. Although the device demonstrates optoelectrical properties, practical operations involving light manipulation necessitate additional components and increased power consumption. In this research, a bulk light source can be conveniently utilized to generate the desired light pulses for device characterization; however, employing such a setup in practical neuromorphic systems is neither straightforward nor efficient. It is imperative to elucidate the necessity for the study and development of the multimodal (electrical and optical) ion-gated transistor within the introductory section. Failure to adequately address this aspect may undermine the perceived novelty of the research, potentially affecting its suitability for publication in this journal.\nStill, the manuscript includes an excessive number of references for supplementary information. The manuscript must be self-contained, and any supplementary files should not contain information essential for a correct understanding of the paper. Kindly differentiate the figures in the main text and supplementary materials. For instance, in the two sentences below, please clarify which information is intended for the main text and which for the supplementary information. There are more sentences required for revision in this aspect.\nPage 3:\nThe crystals show similar structure with the CdPS3-Li membranes assembled by monolayer CdPS3 nanoflakes containing Cd vacancies[27,28] (Fig. 1d and Supplementary Fig. 1).\nPage 6:\nThe transfer curve of the CdPS3-Li ion-gated transistor shows obvious n-type semiconductor behavior with a large on/off current ratio ~105 with ultralow gate leakage current (<5 pA, Fig. 2b and Supplementary Fig. 7b).\nCould you please specify the experimental setup used to process the data presented in Figure 5f? This should include external equipment, additional boards (if used), computer signal processing, and related components. A detailed description of the experimental configuration, as well as the input/output signals, should be incorporated into the manuscript.\nIn Figure 5, the ordering of the a~e figures is not intuitive.\nOn page 13, the energy consumption of the device is compared with that of the human brain. More detailed information is needed on how to obtain those numbers.\nIt is demonstrated that the device can employ K+ and Mg2+ as substitutes for Li+. The authors also reference multi-ion artificial synapses that purportedly replicate the functions of the human brain. However, in the absence of further explanation, it is challenging to concur with this assertion, given that the functionality of the human brain is considerably more intricate than the system described in the manuscript.\nI identified several grammatical errors, including the incorrect use of articles. Kindly refine the English writing.", "reviewer_3": "Many of concerns on the lack of description on technical details have been addressed quite well.\nFollowing comments are regarding the points that are not clearly explained yet.\n1) Fig.R22 does not show a significant difference between in-plane and out-of-plane conductance as claimed by the authors.\n) Ion-electron couling can decay over minute time scale. Can this be a problem for the device opration?\n3) For comment #8, the authors provided a linear fitting data. Linear fit is not a right method to extrapolate this kind of decay behaior because it usually accelerate over time.\n4) The state separation shown in Fig.3 is indeed impressive. However, the authors had to wait 5 seconds to obtain stabilized current. How this kind of writing method can be used for neuromorphic computing purpose? It will take a really long time to write an array.\n5) When the operation mechanism of this device is explained, the authors didn't consider Li+ diffusion into MoS2. If there is a right justification, it should be included in this discussion.\n6) When writing an array using a laser, how long did it take? For fair judgement, I suggest include this number in the manuscript."}, "author_response": "Response to reviewers’ comments\nReviewer #2 (Remarks to the Author):\nThe authors have adequately addressed certain aspects of my comments. Nonetheless, I\nremain unconvinced regarding the necessity of multimodal devices (electrical and optical) for\nin-memory computing and possess several questions and concerns about the current version.\nResponse: We sincerely appreciate the reviewer’s insightful comments and constructive\nsuggestions, which have helped us greatly improve the quality of the work. The following are\nour point-by-point response to the reviewer's comments, including the necessity of multimodal\ndevices for in-memory computing and other questions and concerns.\n1) The primary objective of this study is to develop multimodal ion-gated transistors for in-\nmemory computing. Given that the device is responsible for handling electrical and optical\nsignals, both types of inputs are employed for multiply-accumulate (MAC) and activation\noperations, respectively. Although the device demonstrates optoelectrical properties, practical\noperations involving light manipulation necessitate additional components and increased power\nconsumption. In this research, a bulk light source can be conveniently utilized to generate the\ndesired light pulses for device characterization; however, employing such a setup in practical\nneuromorphic systems is neither straightforward nor efficient. It is imperative to elucidate the\nnecessity for the study and development of the multimodal (electrical and optical) ion-gated\ntransistor within the introductory section. Failure to adequately address this aspect may\nundermine the perceived novelty of the research, potentially affecting its suitability for\npublication in this journal.\nResponse: We appreciate the reviewer’s comments and constructive suggestions.\nThe multiply-accumulate (MAC) operation and nonlinear activation are fundamental\ncomponents of neuromorphic computing. MAC operation requires high-density weight storage\nwith independent control, so that each weight can be individually modulated and preserved.\nImplementing MAC operation with light typically relies on large-scale optical interference\narrays, which make independent control of individual units difficult and increase integration\ncomplexity. In contrast, crossbar-configured device arrays utilize electrical pulses to perform\nMAC operations with high efficiency and low latency, while enabling in-memory computation\nand maintaining compatibility with mature CMOS processes [Nature 577, 641-646 (2020); Nat.\nElectron. 3, 371-382 (2020)].\nThe requirements of nonlinear activation differ from those of MAC operations. It must\nprovide uniform activation across all devices while maintaining low power consumption and\nminimizing interference with the MAC circuitry [Neurocomputing 503, 92-108 (2022)]. Using\nlight signals to implement activation functions enables simultaneous nonlinear activation across\nmultiple devices, as the light spot can fully cover all devices in the array. This approach allows\nfor parallel computing without crosstalk in the MAC circuitry. In addition, by tuning the light\nintensity or wavelength, controllable nonlinear synaptic behaviors can be achieved, extending\nthe modulating range. Compared with electrical pulses, light also consumes less power\nconsumption [Nat. Commun. 15, 6147 (2024)].\nIndeed, as the reviewer pointed out, conventional operations involving light manipulation\nnecessitate additional components and increased power consumption. If the MAC operation\nand nonlinear activation are implemented as two separate units, digital-to-analog converters\n(DACs) are required to interconnect them. Previous studies have shown that signal conversions\ninvolving such DACs result in power consumption that far exceeds that of the MAC operations\nthemselves [Nat. Nanotechnol. 16, 680-687 (2021); Nat. Nanotechnol. 18, 486-492 (2023)]. In\ncontrast, in this work, we developed a multimodal ion-gated transistor that exhibits a high linear\nresistance state under electrical pulses and produces a nonlinear postsynaptic current (PSC)\nresponse under light pulses. This device integrates MAC operations and nonlinear activation\nwithin a single unit, physically combining both functions. The nonlinear PSC output directly\nprovides nonlinear activation, which can be used immediately for matrix multiplication,\neliminating the need for secondary conversions via DACs and thereby reducing latency and\npower consumption.\nMoreover, a bulk light source can not only be conveniently used to generate desired light\npulses for device characterization but is also practical and efficient for system implementation.\nThe process of integrating the light source with optoelectronic synapses is CMOS-compatible\nand well established, encompassing coupling, packaging, and thermal management. This\nenables direct incorporation into existing silicon photonics/electronics co-packaging production\nlines [Nat. Commun. 15, 751 (2024); Adv. Mater. 36, 2307393 (2024)]. By implementing\nactivation functions, our device eliminates the need for individual laser irradiation of each array\ncomponent. Instead, it enables simultaneous illumination of the entire array with a single bulk\nlight source, thereby generating uniform PSCs under light pulses. The activation function is\nrealized by independently reading through the source-drain voltage. This feature not only\nsimplifies the operation process but also significantly enhances energy efficiency, providing a\ncrucial advantage for the integration and parallel operation of large-scale arrays.\nIn the revised manuscript, we have summarized the above content and incorporated it\ninto the ‘Introduction’ section as follows:\nBrain-inspired neuromorphic computing, renowned for its low power consumption and high\nparallelism, is widely considered as a promising solution to overcome the von Neumann\nbottleneck. The multiply-accumulate (MAC) operation and nonlinear activation are two\nfundamental components of neuromorphic computing. Implementing MAC and nonlinear\nactivation as two separate units needs digital-to-analog converters (DACs) for interconnection,\nresulting in power consumption that significantly exceeds that of the MAC operations alone. In\ncontrast, integrating both functions within a single device can reduce latency, power\nconsumption, and integration complexity, thereby improving overall computational efficiency.\nHowever, these two operations impose distinct device requirements: MAC operation requires\ndevices capable of producing highly linear and non-volatile resistance states, whereas nonlinear\nactivation demands devices that can generate diverse nonlinear synaptic behaviors to introduce\nnonlinearity into neural networks. These conflicting demands make the integration of both\nfunctions into a single device highly challenging.\nUsing electrical pulses for MAC operation and light pulses for nonlinear activation offers an\neffective solution to this challenge. Electrical pulses can perform MAC operation directly\nthrough crossbar memory arrays, providing high efficiency, low latency, and reduced energy\nconsumption. Meanwhile, postsynaptic currents (PSCs) generated by synaptic devices under\nlight pulses can be modeled by a double-exponential function, which is equivalent to a sigmoid\nfunction, thus providing a feasible means to implement activation functions (Fig. 1a). Moreover,\nthis approach allows multiple devices to output the same nonlinear activation simultaneously,\nensuring uniform activation across all devices to enable parallel computing while minimizing\ninterference with the MAC circuitry. Multimodal artificial synapses, which can generate non-\nvolatile resistance states under electrical pulses and produce PSC under optical pulses, provide\nthe hardware foundation for this paradigm (Fig. 1b).\n2) Still, the manuscript includes an excessive number of references for supplementary\ninformation. The manuscript must be self-contained, and any supplementary files should not\ncontain information essential for a correct understanding of the paper. Kindly differentiate the\nfigures in the main text and supplementary materials. For instance, in the two sentences below,\nplease clarify which information is intended for the main text and which for the supplementary\ninformation. There are more sentences required for revision in this aspect.\nPage 3:\nThe crystals show similar structure with the CdPS3-Li membranes assembled by monolayer\nCdPS3 nanoflakes containing Cd vacancies[27,28] (Fig. 1d and Supplementary Fig. 1).\nPage 6:\nThe transfer curve of the CdPS3-Li ion-gated transistor shows obvious n-type semiconductor\nbehavior with a large on/off current ratio ~105 with ultralow gate leakage current (<5 pA, Fig.\n2b and Supplementary Fig. 7b).\nResponse: We appreciate the reviewer’s constructive suggestions.\nIn the revised manuscript, we have reduced the number of references in the supplementary\ninformation and moved important references to the main text. We also carefully reviewed the\nfigures citation in the manuscript to clarify which information belongs to the main text and\nwhich belongs to the supplementary material. Detailed revisions are shown below:\nPage 3: “The crystals show similar structure with the CdPS -Li membranes assembled by\n3\nmonolayer CdPS nanoflakes containing Cd vacancies[27,28] (Fig. 1d and Supplementary Fig. 1)”\n3\nwas change to “According to XRD patterns (Fig. 1d) and Fourier transform infrared (FTIR)\nabsorption spectra (Supplementary Fig. 1), the crystals show similar structure with the CdPS -\n3\nsemiconductor behavior with a large on/off current ratio ~105 with ultralow gate leakage current\n(<5 pA, Fig. 2b and Supplementary Fig. 7b)” was changed to “The transfer curve of the CdPS -\ncurrent ratio (~105, Fig. 2b) and ultralow gate leakage current (<5 pA, Supplementary Fig. 7b)”.\nPage 9: “Statistical analysis of 32 separate transistors shows each device operates normally\nwith consistent threshold voltages, I , and uniform electrical writing and erasing\non\n(Supplementary Fig. 16 and 17).” was changed to “Statistical analysis of 32 separate transistors\nshows each device operates normally with consistent threshold voltages and I (Supplementary\non\nFig. 18), as well as uniform electrical writing and erasing (Supplementary Fig. 19).”\nPage 15: “Due to the large conductance ratio and high-linearity resistance states of the device,\nthe CNN achieved a training accuracy of 97.5% and a validation accuracy of 96.28% after the\n30th epoch, enabling accurate image recognition and classification (Fig. 5g and Supplementary\nFig. 26).” was changed to “Due to the large conductance ratio and high-linearity resistance\nstates of the device, the CNN achieved a training accuracy of 97.5% and a validation accuracy\nof 96.28% after the 30th epoch (Fig. 5g), enabling accurate image recognition and classification\n(Supplementary Fig. 28).\n3) Could you please specify the experimental setup used to process the data presented in Figure\n5f? This should include external equipment, additional boards (if used), computer signal\nprocessing, and related components. A detailed description of the experimental configuration,\nas well as the input/output signals, should be incorporated into the manuscript. In Figure 5,\nthe ordering of the a~e figures is not intuitive.\nResponse: We appreciate the reviewer’s constructive suggestions.\nThe measurement setup comprises a dark box with a probe station used to measure the\nsynaptic responses of the device under both light and electrical pulses (Fig. R1). Specifically, a\nsignal generator outputs electrical pulse signals, and an oscilloscope verifies the accuracy of\nthese signals. A Python script directly converts MNIST images into electrical pulse parameters\n(amplitude, width, and number) and transmits them to the signal generator via USB. These\nelectrical pulse as the input signals are applied to the device array to perform matrix\nmultiplication (Fig. R2) and output current signal. A laser controller generates light pulses as\nthe input signal to induce postsynaptic current (PSC) in the device. The PSC is read through\nthe source-drain electrode of the device as the output current signal, thereby completing the\nactivation function (Fig. R2). All the output currents achieved under electrical pulse and optical\npulse are read by a Keysight semiconductor parameter analyzer, which finally transmits all\nmeasured data back to the PC for further processing and analysis as the output of the neural\nnetwork.\nIn the revised manuscript, we have added a description of the experimental setup used to\nprocess the data in the ‘Methods’ section. We also adjusted the order of panels from a to e in\nFigure 5 to make it more intuitive.\nFigure R1. The instruments for synaptic behavior measurement of CdPS -Li ion-gated\n3\ntransistor array.\nFigure R2. Experimental setup flow diagram for performing matrix multiplication and\nactivation functions using CdPS -Li ion-gated transistor array.\n3\n4) On page 13, the energy consumption of the device is compared with that of the human brain.\nMore detailed information is needed on how to obtain those numbers.\nResponse: We appreciate the reviewer’s constructure suggestion.\nWe calculated the light power consumption of the device using the formula:\n𝐸 = 𝑃×∆𝑡×𝑆,\n𝑙𝑖𝑔ℎ𝑡\nwhere P, ∆𝑡 and S refer to light intensity, pulse width, and device area, respectively.\nIn our experiments, the light intensity and pulse width were 1.02 μW/cm² and 100 μs (Fig.\n4e), respectively, and the effective area of the device was 20 μm2 (Supplementary Fig. 6a). Thus,\nthe light power consumption was about 2.05 fJ.\nThe electrical power consumption was calculated using the formula:\n𝐸 = 𝑉 ×𝐼 ×∆𝑡,\n𝐺𝑆 𝐺𝑆\nwhere 𝑉 , 𝐼 , and ∆𝑡 represent gate-source voltage, gate-source current, and pulse width,\n𝐺𝑆 𝐺𝑆\nrespectively.\nIn our experiments, the 𝑉 , and ∆𝑡 were 100 mV and 1 ms (Fig. 3h), respectively, and 𝐼\n𝐺𝑆 𝐺𝑆\nwas 200 fA (Supplementary Fig. 7b). Accordingly, the electrical power consumption was 20 aJ.\nIn the revised manuscript, we have added detailed information for calculating power\nconsumptions of the devices in the ‘Methods’ section.\n5) It is demonstrated that the device can employ K+ and Mg2+ as substitutes for Li+. The authors\nalso reference multi-ion artificial synapses that purportedly replicate the functions of the human\nbrain. However, in the absence of further explanation, it is challenging to concur with this\nassertion, given that the functionality of the human brain is considerably more intricate than the\nsystem described in the manuscript.\nResponse: We appreciate the reviewer’s insightful comment.\nIn the original manuscript, the phrase ‘we can construct multi-ion artificial synapses that\naccurately simulate the functions of the human brain’ may cause misunderstanding. Indeed, the\nhuman brain is far more complex than that of multi-ion synapses, and thus it is hard for multi-\nion synapses to replicate the functions of the human brain. However, multi-ion synapses can\nmodulate synaptic weights and simulate the parallel information processing observed in the\nhuman brain, which cannot be achieved by single-ion synapse.\nIn the human brain, synapses involve connections between multiple neurons, and each\nsynapse can release various types of neurotransmitters. These neurotransmitters can activate\nvarious types of receptors, which influence the excitatory or inhibitory nature of neurons,\nthereby establishing distinct synaptic weights-a fundamental principle of parallel processing\n[Nat. Commun. 12, 1068 (2021)]. An important feature of 2D CdPS -Li is that the Li+ ions can\n3\nbe exchanged into other ions such as K+ and Mg2+ through solution replacement\n(Supplementary Fig. 29), yielding a variety of highly anisotropic layered superionic conductors.\nThis allows us to construct multi-ion synapses (Supplementary Fig. 30a) to simulate parallel\nprocessing in the human brain. The cooperative effect among multi-ion synapses significantly\nenhances the overall synaptic weight (Supplementary Fig. 30b). In this configuration, each ion\nspecies contributes differently to conductance modulation, and their combined action generates\na broader and more flexible range of synaptic weights than a single-ion synapse can achieve.\nAs a result, multi-ion synapses provide an analogy to the cooperative signaling of\nneurotransmitters in biological neural networks, thereby offering a foundation for simulating\nbrain-inspired parallel information processing (Fig. R3).\nIn the revised manuscript, we have re-organized the above information into a new\n‘Discussion’ section, replacing the original ‘Discussion’.\nFigure R3. Illustration of three connections in biological neurons. Pre-spikes of pre-neurons\n(Li+, K+, and Mg2+) are integrated at the membrane potential of post-neuron, generating\npostsynaptic currents (I ).\nout\n6) I identified several grammatical errors, including the incorrect use of articles. Kindly refine\nthe English writing.\nResponse: We appreciate the reviewer’s kind correction. We have carefully reviewed the entire\ntext and corrected grammatical errors, including the incorrect use of articles.\nReviewer #3 (Remarks to the Author):\nMany of concerns on the lack of description on technical details have been addressed quite well.\nFollowing comments are regarding the points that are not clearly explained yet.\nResponse: We sincerely appreciate the reviewer’s insightful comments and constructive\nsuggestions, which have helped us greatly improve the quality of the work. The following are\nour point-by-point response to the reviewer's comments.\n1) Fig. R22 does not show a significant difference between in-plane and out-of-plane\nconductance as claimed by the authors.\nResponse: We appreciate the reviewer’s insightful comment. We would like to clarify the\nmisunderstanding caused by the caption of Fig. R22 (Supplementary Fig. 4d in Supplementary\ninformation).\nFig. R22 shows direct current (DC) I-V curves to verify the ohmic contact of the device used\nfor ionic conductivity measurements, not to test the ionic conductivity of the material. Since\nCdPS -Li is an insulator with wide bandgap, it exhibits very low current in both the in-plane\n3\nand out-plane directions, showing no visible anisotropy in electrical conductivity. In this work,\nimpedance spectroscopy was used to reveal the significant difference between in-plane and out-\nplane ion conductance, and the results are shown Fig. 1h.\nIn the revised manuscript, we have changed the figure caption to ‘The I-V curves of the\ndevices in a and c. The good linearity indicates the excellent contact between the CdPS\n3\n-Li\nflakes and the electrodes.’\n2) Ion-electron coupling can decay over minute time scale. Can this be a problem for the device\noperation?\nResponse: We appreciate the reviewer’s insightful comment.\nIn conventional ion-gated transistors, an isotropic ionic conductor serves as the dielectric\nlayer, while a semiconductor acts as the channel. Ion-electron coupling in such devices typically\ndecays over a time scale of minutes because of the isotropic nature of ion transport [Nat.\nElectron. 5, 859-869 (2022); Adv. Funct. Mater. 31, 2100069 (2021)]. This isotropy prevents\neffective control over the direction of ion transport. When ions accumulate at the ionic\nconductor/channel interface, the removal of the gate voltage results in their slow detachment\nfrom the interface. This leads to a continuous decay in ion-electron coupling and, consequently,\na noticeable current decay.\nIn contrast, our devices utilize a CdPS -Li ionic dielectric with a layered structure that\n3\npromotes anisotropic ion transport. This layered structure restricts ion migration away from the\ninterface after the gate voltage is removed, enabling effective storage of ions. Consequently, the\nion-electron coupling effect is significantly stabilized, contributing to the excellent non-volatile\nstorage characteristics as demonstrated in our devices (Fig. 3c).\n3) For comment #8, the authors provided a linear fitting data. Linear fit is not a right method to\nextrapolate this kind of decay behavior because it usually accelerates over time.\nResponse: We appreciate the reviewer very much for pointing out the limitation of linear fitting.\nIn the revised manuscript, we removed the linear fitting data from the retention test of device\nand revised the caption of Fig. 3c as follows: The retention test shows an initial high-resistance\nstate (HRS) current of 23.5 fA and a low-resistance state (LRS) current of 100 nA at t = 0 s.\nAfter 10,000 seconds, the HRS current increased to 25 fA (6% increase), while the LRS\ndecreased to 90 nA (10% decay). These results demonstrate excellent long-term retention\ncharacteristics.\n4) The state separation shown in Fig.3 is indeed impressive. However, the authors had to wait\n5 seconds to obtain stabilized current. How this kind of writing method can be used for\nneuromorphic computing purpose? It will take a really long time to write an array.\nResponse: We appreciate the reviewer’s insightful comment.\nBy optimizing the testing conditions, we have effectively suppressed current decay and\neliminated the waiting time required to achieve a stabilized current. Both the width and\namplitude of the top-gate voltage pulse are found to significantly influence the current decay\nbehavior. As the gate voltage or pulse width gradually increases, the degree of current decay\nprogressively decreases (Fig. 3h and i in manuscript). In our original experiments, the applied\nvoltage pulse was 200 mV with a pulse width of 1 ms. By simply increasing the pulse amplitude\nto 500 mV, the current decay was effectively suppressed (Fig. R4a). Under these optimized\nconditions, the devices achieved distinct, stable, and non-overlapping non-volatile states, with\na high linearity between resistance states (Fig. R4b and c). These states can be directly utilized\nas weights in convolutional neural networks (CNNs) or artificial neural networks (ANNs).\nIn the revised manuscript, we have included the new data and related discussions.\nFigure R4. a, Current change of CdPS -Li ion-gated transistor after applying a positive gate\n3\nvoltage pulse of 500 mV. The pulse width was 1 ms. b, Cumulative writing with progressive\nmultilevel states. c, Retention of 64 conductance states for read noise extraction at V = 1 V.\nDS\n5) When the operation mechanism of this device is explained, the authors didn't consider Li+\ndiffusion into MoS . If there is a right justification, it should be included in this discussion.\nexperiments to clarify the Li⁺ diffusion into MoS .\n2\ncompared to multilayer MoS . This characteristic also inherently avoids Li⁺ intercalation. It has\n2\nbeen reported that the diffusion of Li⁺ ions into MoS could trigger a phase transition of MoS\n2 2\nfrom the semiconducting 2H phase to the metallic 1T phase [Chem. Eng. J., 428, 131014 (2022);\nAdv. Mater. 31, 1900568 (2019)]. However, Raman spectroscopy characterization after 1,000\noperation cycles revealed no changes in the characteristic 2H phase peaks of MoS in the\n3\nconsequently no significant Li⁺ diffusion, has occurred.\nFigure R5. Raman spectra of MoS\n2\nin the CdPS\n3\n-Li ion-gated transistor before and after 1000\ncycling tests.\n6) When writing an array using a laser, how long did it take? For fair judgement, I suggest\ninclude this number in the manuscript.\nResponse: We appreciate the reviewer’s constructive suggestion.\nWhen programming the array with a laser, the light spot fully covers all devices\n(Supplementary Fig. 32a), allowing them to generate postsynaptic currents simultaneously\nunder a light pulse and thereby enabling rapid write speed. As an example, during the second\nepoch, a 0.2 ms pulse was applied and the current of each device was recorded at various\nintervals (Supplementary Fig. 27). With a maximum readout interval of 5 ms, the total time to\nwrite the entire array was 5.2 ms."}, {"round": 3, "reviewer_comments": {"reviewer_1": "I appreciate the authors’ efforts in revising the manuscript. The revisions have been made thoughtfully, and the overall quality of the work has improved. Nevertheless, I have a remaining concern regarding the power calculation. In the current analysis of light power consumption, the authors have used only the light intensity. Since power should represent the total energy required to operate the AI computing system, the calculation should be adjusted to incorporate the power conversion efficiency of the light source. Accordingly, the total input power necessary to drive the light source, rather than the emitted light intensity alone, should be used in the analysis.", "reviewer_3": "The authors provided reasonable responses except for the comment # and #6 (Reviewer #3). I think my comment was not straightforward enough. let me rephrase the comment again.\n#) Ion-electron coupling can decay over minute time scale. Can this be a problem for the device operation? -> My question was if the electrical state modification takes a few seconds (Fig.3a), how this device can be used in combination with other semiconductor devices operating in ps time scale?\nThe author's response referred Fig.3c, but Fig,3c is about the stability of state (retention), which only shows how long a given state can be maintained. It does not explain how the device can operate for realistic computing.\n#6) When writing an array using a laser, how long did it take? For fair judgement, I suggest include this number in the manuscript. -> In essence, this question is same as #. If the optical state modification takes 5.2ms, how this device can be used in combination with other circuits? For example, in case of old Ultraviolet Erasable Programmable Read-Only Memory (USEPROM), it took a few minutes to erase the information. Thus, it was used only for limited purpose and is no longer used. In case of multimodal operation, some part of circuit should be illuminated for 5ms while other circuit part are working. Can this be a reasonable way to operate a computing system? Authors need to provide answers for this kind of question before claiming the usefulness of multimodal ion gate device."}, "author_response": "Response to reviewers’ comments\nReviewer #2 (Remarks to the Author):\nI appreciate the authors’ efforts in revising the manuscript. However, I still have concerns\nregarding the power consumption analyses. Power consumption is a critical issue for\nneuromorphic and synaptic devices and is also emphasized as a key contribution of the present\nwork. For this reason, power and energy values must be calculated and compared with particular\ncare and clarity.\nWhen the term power is used, it should always be defined together with the corresponding\noperational conditions. In the manuscript, the authors report an energy consumption of 20 aJ\nbased on the device characteristics shown in Figure S7b. However, it is unclear which specific\noperation the device is performing while consuming this energy. Although the reported value\nof 20 aJ appears promising, the device does not seem to execute any meaningful function under\nthese conditions, to the best of my understanding. For example, energy consumption should be\nassociated with well-defined operations such as potentiation/depression, programming or\nerasing a memory state, or processing a certain amount of data. The revised manuscript should\nexplicitly specify the operation corresponding to each reported power value.\nFurthermore, while some previous studies have employed simplified expressions such as\nE = P×Δt×S to estimate energy consumption, this approach involves substantial assumptions.\nlight\nIn the present work, optical excitation is an essential requirement for device operation rather\nthan optional. Consequently, any realistic power analysis should include the total power\nrequired to generate and maintain the specified light intensity, rather than considering only the\neffective component.\nAs noted above, power analyses must clearly state the exact operating conditions and\nfunctional tasks being performed. In this context, the authors’ claim that the total energy\nconsumption required to operate the AI computing system is 41.83 fJ may be misleading. As\nwritten, this statement may be interpreted as a specific AI computation can be executed with\nonly 41.83 fJ of energy.\nI strongly encourage the authors to revise the manuscript to address these issues by explicitly\nlinking reported power values to concrete device operations and by accounting for all necessary\ncomponents under realistic operating conditions.\nResponse: We sincerely appreciate the reviewer’s valuable comments and suggestions.\nThe reported electrical energy consumption of 20 aJ corresponds to the energy required for\na single synaptic potentiation or depression operation driven by an electrical pulse in the device.\nThis value represents the energy consumption of the synaptic operation itself and does not\ninclude the energy overhead from external pulse-generation instruments. Under realistic\noperating conditions, a signal generator and an oscilloscope are required to supply the electrical\npulses. In our experiment, the power of the signal generator and oscilloscope are 5 W and 8 W,\nrespectively.\nFor optical stimulation, the reported 2.05 fJ corresponds to the energy required to generate\none postsynaptic current (PSC) in response to an optical pulse in the device. In contrast, the\nreported 41.83 fJ represents the total electrical energy required to generate a single optical pulse\ncapable of inducing a PSC, after considering the electrical-to-optical conversion efficiency of\nthe laser controller. Under realistic operating conditions, a semiconductor parameter analyzer\nis required to read the current value at a specific time point. In our experiment, the\nsemiconductor parameter analyzer is 10 W.\nIn the revised manuscript, we have clarified the correspondence between the reported power\nconsumption values and specific device operations, and given all necessary components under\nrealistic operating conditions.\nReviewer #3 (Remarks to the Author):\nThe authors provided a systematic response to the questions raised about the efficiency of\nneuromorphic device operation using a slowly responding devices.\nThe authors claimed that MAC operation can be performed by limiting the applications of this\ndevice for the slow propagation part. While it may not be the best method for neuromorphic\ncomputing, the concept of dual functionality is worth to be published. I recommend the\npublication of this manuscript.\nResponse: We thank the reviewer for the positive comments and efforts dedicated to improving\nthe quality of our work."}, {"round": 4, "reviewer_comments": {"reviewer_1": "I appreciate the authors’ efforts in revising the manuscript. However, I still have concerns regarding the power consumption analyses.\nPower consumption is a critical issue for neuromorphic and synaptic devices and is also emphasized as a key contribution of the present work. For this reason, power and energy values must be calculated and compared with particular care and clarity.\nWhen the term power is used, it should always be defined together with the corresponding operational conditions. In the manuscript, the authors report an energy consumption of 20 aJ based on the device characteristics shown in Figure S7b. However, it is unclear which specific operation the device is performing while consuming this energy. Although the reported value of 20 aJ appears promising, the device does not seem to execute any meaningful function under these conditions, to the best of my understanding. For example, energy consumption should be associated with well-defined operations such as potentiation/depression, programming or erasing a memory state, or processing a certain amount of data. The revised manuscript should explicitly specify the operation corresponding to each reported power value.\nFurthermore, while some previous studies have employed simplified expressions such as E_light = P × Δt × S to estimate energy consumption, this approach involves substantial assumptions. In the present work, optical excitation is an essential requirement for device operation rather than optional. Consequently, any realistic power analysis should include the total power required to generate and maintain the specified light intensity, rather than considering only the effective component.\nAs noted above, power analyses must clearly state the exact operating conditions and functional tasks being performed. In this context, the authors’ claim that the total energy consumption required to operate the AI computing system is 41.83 fJ may be misleading. As written, this statement may be interpreted as a specific AI computation can be executed with only 41.83 fJ of energy.\nI strongly encourage the authors to revise the manuscript to address these issues by explicitly linking reported power values to concrete device operations and by accounting for all necessary components under realistic operating conditions.", "reviewer_3": "The authors provided a systematic response to the questions raised about the efficiency of neuromorphic device operation using a slowly responding devices.\nThe authors claimed that MAC operation can be performed by limiting the applications of this device for the slow propagation part. While it may not be the best method for neuromorphic computing, the concept of dual functionality is worth to be published. I recommend the publication of this manuscript."}, "author_response": ""}]

Decision letter