1 . 1 . . . . . . . . . 1 C LSI VHDL 2 Synthesis Very High Speed Integrated Circuit Hardware VHDL VHDL Description Language
LSI VHDL LSI VHDL LSI 3.1 LSI LSI
LSI LSI IC CPU   ROM/RAM LSI LSI ASSP LSI Application Specific Standard Product LSI ASIC   Application Specific Integrated Circuit 1960
1970 4 CPU i4004 1970
1990 1980 1986 64Mbit    DRAM 1 LSI
10 CPU 3 LSI IC
ASIC
3 FPGA   Field Programmable Gate Array CPLD   Complex Programmable Logic Device LSI LSI 3 3 3.2 LSI LSI 6 10 LSI 3.3 VHDL HDL VHDL Verilog-HDL 2 VHDL 3.3.1. VHDL VHSIC Very High Speed Integrated VHDL 1970 Circuit 1981 ASIC 3 4 ASIC 2 IC HDL AISC LSI VHDL 1983 1 1985
1986
7.2 1986 Electronic  Engineers Language Reference Manual Institute of Electrical and IEEE LRM 1987 5 IEEE-1076 12 IEEE-1164 1992 5 3 2 3.3.2. VHDL VHDL
3-1
{ ASSP ASIC FPGA... 3-1 VHDL
VHDL
RTL   Register Transfer Level HDL VHDL 1 2 3 3.4
FPGA/CPLD
CPLD Complex FPGA   Field  Programmable  Gate  Array Programmable Logic Device CLB(Configurable Logic Block) CLB CLB FG FF CLB SRAM CPLD FPGA CLB ASIC FPGA/CPLD FPGA/CPLD 3 4 LSI HDL 4.1 5 4-1 4-1 4.2 4.2.1. waterfall model 5 7 4-2 ( ) 5
7
4-3 5 4.3 4-5 5 1 BS JK 5 ( ) 4-7 4-7 READ WRITE 1 1 5 7 4.5 7 ( ) 5 GUI 7
4.6
4-9 7 4.7 5 7 5 1960 X 1970 CT  computed tomography 1980 3 1980 1990 VR IT 10 5.1 RGB 2 2 R G B 3 i={1,2,...,M} j={ 1,2,...,N} k={ 1,2,...,K} 5-1 5-1 CIL(channel interleaved by line) interleaved by pixel CSQ(channel sequential) CIP channel M × N × K K M × N 5-2 10 5.2
OS
5.2.1. BMP Microsoft device independent bitmap BMP C BMP Microsoft OS Windows 8 1 24 1 8 3 256 54Byte 6-2 4byte 4byte BMP OS 10
5-3
016 3516 54Byte 3616 5.3
5.3.1. 1 1

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G 8ij (i.j) (2K+1)    (2L+1) f pq , {i − K      p     i + K , j − L     q      j + L} 8ij (5.2) 10 8 ij .fij 5.4 1 1 5.4.1. x f y = f (x) 5-5 Xmin X max Y min Y max y y =
(5.3) 5-5 Y1,Y2,A Yn [ x i , x i+1 ]
(5.4) 10
5.4.2.

f ij (2K+1)
±  M
8ij
3× 3 9 8ij g(i,j) = { f (i − 1,j-1) + f (i,j − 1) + f (i + 1,j − 1) + f (i − 1,j) + f (i,j) + f (i + 1,j) + f (i − 1,j + 1) + f (i,j + 1) + f (i + 1,j + 1)}/9 (5.6)
1/9 M = 1, N = 1 5-6 h
(2K+1)×  (2L+1) 5.4.3. h 10 y b x b x
(5.11) a>1 0<b<1 10 6 HDL VHDL 6.1 b>1 y .y (5.12) 6-1
6.2
3 VHDL 4 6-2 FPGA
6-3
4 2.3 6-3 6.3 VHDL C Borland C++ Compiler 5.5 Xilinx WebPACK Ver4.1 Project Navigator Altera MAX+PLUS II Xilinx WebPACK 4.1 ModelSim XE Starter A205
6.4
LSI LSI
LSI
JK 4 6-4 1
6.5
6-4
2
1
C VHDL 1 6-6 ROM RAM RAM ROM ALU   Arithmetic and Logical Unit DATA1  2 OP DATAOUT 6-7 TV 6-7 6-8 6-4 6-9
6.6 C
VHDL VHDL LSI C 5 BMP 1 1 6-10 BMP 24bit 160× 160 Red Green Blue RGB 8bit 3 CIP 5 5.1 5.1 XSIZE r ]  3× 160  480 (6.1) */ */ #define XSIZE 480 #define YSIZE 160 /* /* #include <stdio.h> #include <string.h> #include <stdlib.h> /* */ void NAME(char *FILENAME); void IMAGE_READ (unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME); void IMAGE_WRITE(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME); 6-10 void NAME void IMAGE_READ void IMAGE_WRITE IMAGE_READ
BMP

2 BMP BMP buffer[ya][xa] 2 buffer[ya][xa] y buffer buffer[ya]  IMAGE y y IMAGE[ya][xa] IMAGE[ya] IMAGE[ ya ] = YSIZE – 1 – buffer [ ya ] (6.2) IMAGE[ya][xa] IMAGE[ya][xa] buffer[ya][xa] 6-13 buffer[ ya ] = YSIZE − 1 − IMAGE[ ya ] (6.3) BMP 5 5.4.3 BMP CIP 1 buffer   IMAGE 3 6.1 6-11 6-14 x y 6-12 RGB 5 1 6-15 0 B (Y-1)/3 6-15 2 B G R for(y=0;y<YSIZE;y++) { for(x=0;x<XSIZE/3;x++) { B[y][x] = IMAGE[y][x*3]; G[y][x] = IMAGE[y][x*3+1]; R[y][x] = IMAGE[y][x*3+2]; } } 2 B G R for(yb=0;yb<YSIZE;yb++) { for(xb=0;xb<XSIZE/3;xb++) { IMAGE[yb][3*xb] = b[yb][xb]; IMAGE[yb][3*xb+1] = g[yb][xb]; IMAGE[yb][3*xb+2] = r[yb][xb]; } } B 2
b[yb][xb]  g[yb][xb]  r[yb][xb]
90 90 90 for(y=0;y<YSIZE;y++) { for(x=0;x<XSIZE/3;x++) { b[y][x] = B[YSIZE-1-x][y]; g[y][x] = G[YSIZE-1-x][y]; r[y][x] = R[YSIZE-1-x][y]; } } 90 for(y=0;y<YSIZE;y++) { for(x=0;x<XSIZE/3;x++) { b[y][x] = B[x][YSIZE-1-y]; g[y][x] = G[x][YSIZE-1-y]; r[y][x] = R[x][YSIZE-1-y]; } } 16 16 2 6.7 VHDL C RTL 6.7.1. 6 RAM 6-6 6-14 RAM VHDL 2 RAM 2 1 2 library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SRAM is Port ( RD,WR,CS : in std_logic; ADR : in std_logic_vector(7 downto 0); DIN : in std_logic_vector(7 downto 0); DOUT : out std_logic_vector(7 downto 0)); end SRAM; architecture Behavior of SRAM is subtype SRAMWR is std_logic_vector(7 downto 0); type SRAMARRAY is array (0 to 255)ofSRAMWR; signal SRAMDATA : SRAMARRAY; signal INT : integer range 0 to 255; ROMARRAY SRAMWR SRAMARRAY SRAMARRAY SRAMDATA VHDL 7 VHDL LSI C 8 9 1 .. 2 3 4 5 6 7
8 9 10 "
" 1999 ” CQ
"
"
"
"
" "
2001 " 11 14 /* *** 2002.1.19 BMP 90 90 *** */ #define XSIZE 480 #define YSIZE 160 #include <stdio.h> #include <string.h> #include <stdlib.h> void NAME(char *FILENAME); void Filter1(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME); void Filter2(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME); void Filter3(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME); void IMAGE_WRITE(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME); /* B,G,R3 */ unsigned char HEADER[54],image[YSIZE][XSIZE]; char buff[80]: unsigned char b[YSIZE][XSIZE/3],g[YSIZE][XSIZE/3],r[YSIZE][XSIZE/3]; void main() { char *filename=buff; /*Filter1 */ printf("Please Reading Image File Name.... ¥n"); NAME(filename);Filter1(image,filename); printf("Image File Read end.[%s] ¥n¥n",filename); printf("Please Writing Filter1 Imgae Fle Name.... ¥n"); NAME(filename); IMAGE_WRITE(image,filename); printf("Image File Write end.[%s] ¥n¥n",filename); /*Filter2 */ Filter2(image,filename); printf("Please Writing Filter2 Imgae File Name.... ¥n"); NAME(filename); IMAGE_WRITE(image,filename); printf("Image File Write end.[%s] ¥n¥n",filename); /*Filter3 */ Filter3(image,filename); printf("Please Writing Filter3 Imgae File Name.... ¥n"); NAME(filename); IMĂGE_WRITĂ(image,filename); printf("Image File Write end.[%s] ¥n¥n",filename); } */ /* { void NAME(char *FILENAME) scanf("%s",FILENAME); if(strstr(FILENAME,".bmp") == NULL){ strcat(FILENAME,".bmp"); } } */ /*BMP void Filter1(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME) { int xa,ya; FILE *fp; unsigned char buffer[YSIZE][XSIZE]; unsigned char B[YSIZE][XSIZE/3],G[YSIZE][XSIZE/3],R[YSIZE][XSIZE/3]; if((fp=fopen(FILENAME,"rb")) == NULL) { printf("Image Read Error. [%s] ¥n",FILENAME); exit(1); } else { fread(HEADER,1,54,fp); fread(buffer,YSIZE,XSIZE,fp); fclose(fp); } for(ya=0; ya<YSIZE; ya++) { for(xa=0; xa<XSIZE; xa++) { IMAGE[ya][xa] = buffer[YSIZE-1-ya][xa]; } } } 90 */ /*BMP void Filter2 (unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME) { int xa,ya; int x,y,xb,yb; FILE * unsigned char buffer[YSIZE][XSIZE]; unsigned char B[YSIZE][XSIZE/3],G[YSIZE][XSIZE/3],R[YSIZE][XSIZE/3]; unsigned char b[YSIZE][XSIZE/3],g[YSIZE][XSIZE/3],r[YSIZE][XSIZE/3]; if((fp=fopen(FILENAME,"rb")) == NULL) { printf("Image Read Error. [%s] ¥n",FILENAME); exit(1); } else { fread(HEADER,1,54,fp); fread(buffer,YSIZE,XSIZE,fp); fclose(fp); } for(ya=0; ya<YSIZE; ya++) { for(xa=0; xa<XSIZE; xa++) { IMAGE[ya][xa] = buffer[YSIZE-1-ya][xa]; } } for(y=0;y<YSIZE;y++) { for(x=0;x<XSIZE/3;x++) { B[y][x] = IMAGE[y][x*3]; G[y][x] = IMAGE[y][x*3+1]; R[y][x] = IMAGE[y][x*3+2]; } } for(y=0;y<YSIZE;y++) { for(x=0;x<XSIZE/3;x++) { b[y][x] = B[x][YSIZE-1-y]; g[y][x] = G[x][YSIZE-1-y]; r[y][x] = R[x][YSIZE-1-y]; } } /* */ for(yb=0;yb< YSIZE;yb++) {
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for(x=0;x<XSIZE/3;x++) { b[y][x] = B[YSIZE-1-x][y]; g[y][x] = G[YSIZE-1-x][y]; r[y][x] = R[YSIZE-1-x][y]; } } /* */ for(yb=0;yb< YSIZE;yb++) i for(xb=0;xb<XSIZE/3;xb++) { IMAGE[yb][3*xb] = b[yb][xb]; IMAGE[yb][3*xb+1] = g[yb][xb]; IMAGE[yb][3*xb+2] = r[yb][xb]; } } } /*BMP */ void IMAGE_WRITE(unsigned char IMAGE[YSIZE][XSIZE],char *FILENAME) int xa,ya,xb; unsigned char buffer[YSIZE][XSIZE]; unsigned char B[YSIZE][XSIZE/3],G[YSIZE][XSIZE/3],R[YSIZE][XSIZE/3]; FILE *fp; for(ya=0; ya<YSIZE; ya++)はfor(xa=0; xa<XSIZE; xa++) { buffer[ya][xa] = IMAGE[ya][xa]; } } if((fp=fopen(FILENAME,"wb")) == NULL) { printf("Write Image Error. [%s] ¥n",FILENAME); exit(1); } else { fwrite(HEADER,1,54,fp); fwrite(buffer,YSIZE,XSIZE,fp); fclose(fp); } } 16 16 0000000 16 54 100
16 ( FF) (FF) (FF) 16 16