Introduction
Event Receivers decode timing events and signals from an optical event stream transmitted by an Event Generator. Events and signals are received at predefined rate the event clock that is usually divided down from an accelerators main RF reference. The event receivers lock to the phase event clock of the Event Generator and are thus phase locked to the RF reference. Event Receivers convert event codes transmitted by an Event Generator to hardware outputs. They can also generate software interrupts and store the event codes with globally distributed timestamps into FIFO memory to be read by a CPU.
Functional Description
After recovering the event clock the Event Receiver demultiplexes the event stream to 8-bit distributed bus data and 8-bit event codes. The distributed bus may be configured to share its bandwidth with time deterministic data transmission.
Event Decoding
The Event Receiver provides two mapping RAMs of 256 × 128 bits. Only one of the RAMs can be active at a time, however both RAMs may be modified at any time. The event code is applied to the address lines of the active mapping RAM. The 128-bit data programmed into a specific memory location pointed to by the event code determines what actions will be taken.
There are 32 bits reserved for internal functions which are by default mapped to the event codes shown in table . The remaining 96 bits control internal pulse generators. For each pulse generator there is one bit to trigger the pulse generator, one bit to set the pulse generator output and one bit to clear the pulse generator output.
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Heartbeat Monitor
A heartbeat monitor is provided to receive heartbeat events. Event code $7A is by default set up to reset the heartbeat counter. If no heartbeat event is received the counter times out (approx. 1.6 s) and a heartbeat flag is set. The Event Receiver may be programmed to generate a heartbeat interrupt.
Event FIFO and Timestamp Events
The Event System provides a global timebase to attach timestamps to collected data and performed actions. The time stamping system consists of a 32-bit timestamp event counter and a 32-bit seconds counter. The timestamp event counter either counts received timestamp counter clock events or runs freely with a clock derived from the event clock. The event counter is also able to run on a clock provided on a distributed bus bit. The event counter clock source is determined by the prescaler control register. The timestamp event counter is cleared at the next event counter rising clock edge after receiving a timestamp event counter reset event. The seconds counter is updated serially by loading zeros and ones (see mapping register bits) into a shift register MSB first. The seconds register is updated from the shift register at the same time the timestamp event counter is reset. The timestamp event counter and seconds counter contents may be latched into a timestamp latch. Latching is determined by the active event map RAM and may be enabled for any event code. An event FIFO memory is implemented to store selected event codes with attached timing information. The 80-bit wide FIFO can hold up to 511 events. The recorded event is stored along with 32-bit seconds counter contents and 32-bit timestamp event counter contents at the time of reception. The event FIFO as well as the timestamp counter and latch are accessible by software. Page: 7 of 64
Event Log
Up to 512 events with timestamping information can be stored in the event log. The log is implemented as a ring buffer and is accessible as a memory region. Logging events can be stopped by an event or software.
Distributed Bus and Data Transmission
The distributed bus is able to carry eight simultaneous signals sampled with the event clock rate. over the fibre optic transmission media. The distributed bus signals may be output on programmable front panel outputs. The distributed bus bandwidth may be shared by transmission of a configurable size data buffer to up to 2 kbytes. When data transmission is enabled the distributed bus bandwidth is halved. The remaining bandwidth is reserved for transmitting data with a speed up to 50 Mbytes/s (event clock rate divide by two).
Pulse Generators
The structure of the pulse generation logic is shown in Figure 2. Three signals from the mapping RAM control the output of the pulse: trigger, 'set' pulse and 'reset' pulse. A trigger causes the delay counter to start counting, when the end-of-count is reached the output pulse changes to the 'set' state and the width counter starts counting. At the end of the width count the output pulse is cleared. The mapping RAM signal 'set' and 'reset' cause the output to change state immediately without any delay. Document: EVR-MRM-003.doc Page: 8 of 64 32 bit registers are reserved for both counters and the prescaler, however, the prescaler is not necessarily implemented for all channels and may be hard coded to 1 in case the prescaler is omitted. Software may write 0xFFFFFFF to these registers and read out the actual width or hard-coded value of the register. For example if the width counter is limited to 16 bits a read will return 0x000FFFF after a write of 0xFFFFFFF.
Prescalers
The Event Receiver provides a number of programmable prescalers. The frequencies are programmable and are derived from the event clock. A special event code reset prescalers $7B causes the prescalers to be synchronously reset, so the frequency outputs will be in same phase across all event receivers.
Programmable Front Panel Connections
The front panel outputs are programmable: each pulse generator output, prescaler and distributed bus bit can be mapped to any output. The mapping is shown in table below. Table 1: Signal mapping IDs

Front Panel TTL Outputs (VME-EVR-230 and VME-EVR-230RF)
The VME-EVR-230 provides eight programmable TTL outputs in the front panel TTL0 to TTL7 whereas the number of TTL level outputs in the VME-EVR-230RF is limited to four (TTL0 to TTL3). These outputs are capable of driving a TTL level signal into a 50 ohm ground terminated coaxial cable. The source for these signals are determined by mapping registers which allow selecting different types of pulse outputs, prescalers and distributed bus signals.
Front Panel Universal I/O Slots
Universal I/O slots provide different types of output with exchangeable Universal I/O modules. Each module provides two outputs e.g. two TTL output, two NIM output or two optical outputs. The source for these outputs is selected with mapping registers. Two front panel Universal I/O slots have extra I/O pins to allow controlling the delay of UNIV- LVPECL-DLY modules. For the cPCI-EVR-300 the two slots that allow UNIV-LVPECL-DLY modules are UNIV8/9 and UNIV10/11. An optional side-by-side front panel module for the cPCI-EVR-220 and cPCI-EVR-230 offers three additional Universal I/O slots with a maximum of six outputs. The cPCI-EVR-300 has six Universal I/O slots.
Front Panel CML Outputs (VME-EVR-230RF only)
Front Panel CML Outputs provide low jitter differential signals with special outputs. The outputs can work in different configurations: pulse mode, pattern mode and frequency mode.
CML Pulse Mode
The source for these outputs is selected in a similar way than the TTL outputs using mapping registers, however, the output logic monitors the state of this signal and distinguishes between state low (00), rising edge (01), high state (11) and falling edge (10). Based on the state a 20 bit pattern is sent out with a bit rate of 20 times the event clock rate. . . . . When the source for a CML output is low and was low one event clock cycle earlier (state low), the CML output repeats the 20 bit pattern stored in pattern_00 register. When the source for a CML output is high and was low one event clock cycle earlier (state rising), the CML output sends out the 20 bit pattern stored in pattern_01 register. When the source for a CML output is high and was high one event clock cycle earlier (state high), the CML output repeats the 20 bit pattern stored in pattern_11 register. When the source for a CML output is low and was high one event clock cycle earlier (state falling), the CML output sends out the 20 bit pattern stored in pattern_10 register. For an event clock of 125 MHz the duration of one single CML output bit is 400 ps. These outputs allow for producing fine grained adjustable output pulses and clock frequencies.
CML Frequency Mode
In frequency mode one can generate clocks where the clock period can be defined in steps of 1/20 th part of the event clock cycle i.e. 400 ps step with an event clock of 125 MHz. There are some limitations, however: . Clock high time and clock low time must be ≥ 20/20 th event clock period steps . Clock high time and clock low time must be < 65536/20 th event clock period steps The clock output can be synchronized by one of the pulse generators, distributed bus signal etc. When a rising edge of the mapped output signal is detected the frequency generator takes its output value from the trigger level bit and the counter value from the trigger position register. Thus one can adjust the phase of the synchronized clock in 1/20 th steps of the event clock period. Usage example: Australian synchrotron booster clock. We have following: . . . . Event clock of 499.654 MHz/4 Storage ring 360 RF buckets Booster 217 RF buckets Booster and storage ring coincidence clock on DBUS7 The CML outputs are running at a rate of 20 times the event clock or 499.654 MHz * 5, thus the booster revolution period is 217 * 5 CML bit periods. In CML frequency mode we can now set the output period (pulse high time + pulse low time) to 217 * 5 = 1085 bits. For approximately 50% duty cycle we set the pulse high time to 542 (0x21e) and the pulse low time to 543 (0x21f). The actual register settings required are: Write 0x0000011 to CML Control register (CMLxENA) Write 0x021e to CML High Period Count register (CMLxHP) Write 0x021f to CML Low Period Count register (CMLxLP) We also need to set the trigger from DBUS7 by setting up register FPOutMapx. To change the generated clock phase in respect to the trigger we can select the trigger polarity by bit CMLTL in the CML Control register and the trigger position also in the CML Control register.
CML Pattern Mode
In pattern mode one can generate arbitrary bit patterns taking into account following: The pattern length is a multiple of 20 bits, where each bit is 1/20 th of the event clock . period Maximum length of the arbitrary pattern is 20 × 2048 bits . A pattern can be triggered from any pulse generator, distributed bus bit etc. When . triggered the pattern generator starts sending 20 bit words from the pattern memory sequentially starting from position 0. This goes on until the pattern length set by the samples register has been reached. . If the pattern generator is in recycle mode the pattern continues immediately from position 0 of the pattern memory. . If the pattern generator is in single pattern mode, the pattern stops and the 20 bit word from the last position of the pattern memory (2047) is sent out until the pattern generator is triggered again.
cPCI-EVRTG-300 GTX Front Panel Outputs
All eight cPCI-EVRTG-300 front panel output are similar to the CML outputs on the VME-EVR- 230RF. The GTX Outputs provide low jitter differential signals with special outputs. The outputs can work in different configurations: pulse mode, pattern mode and frequency mode. The difference compared to the CML output of the VME-EVR-230RF is that instead of 20 bits per
event clock cycle the GTX outputs have 40 bits per event clock cycle doubling the resolution to 200 ps/bit at an event clock of 125 MHz. In addition to the higher bit rate each of the GTX outputs has a programmable delay line between the FPGA and the actual output which allows a delay range of 1024 steps of ~9 ps. The delay value is set with registers GTX0Dly to GTX7Dly.
GTX Pulse Mode
The source for these outputs is selected in a similar way than the TTL outputs using mapping registers, however, the output logic monitors the state of this signal and distinguishes between state low (00), rising edge (01), high state (11) and falling edge (10). Based on the state a 40 bit pattern is sent out with a bit rate of 40 times the event clock rate. . . . . When the source for a GTX output is low and was low one event clock cycle earlier (state low), the GTX output repeats the 40 bit pattern stored in pattern_00 register. When the source for a GTX output is high and was low one event clock cycle earlier (state rising), the GTX output sends out the 40 bit pattern stored in pattern_01 register. When the source for a GTX output is high and was high one event clock cycle earlier (state high), the GTX output repeats the 40 bit pattern stored in pattern_11 register. When the source for a GTX output is low and was high one event clock cycle earlier (state falling), the GTX output sends out the 40 bit pattern stored in pattern_10 register. For an event clock of 125 MHz the duration of one single GTX output bit is 200 ps. These outputs allow for producing fine grained adjustable output pulses and clock frequencies.
GTX Frequency Mode
In frequency mode one can generate clocks where the clock period can be defined in steps of 1/40 th part of the event clock cycle i.e. 200 ps step with an event clock of 125 MHz. There are some limitations, however: . . Clock high time and clock low time must be ≥ 40/40 th event clock period steps Clock high time and clock low time must be < 65536/40 h event clock period steps The clock output can be synchronized by one of the pulse generators, distributed bus signal etc. When a rising edge of the mapped output signal is detected the frequency generator takes its output value from the trigger level bit and the counter value from the trigger position register. Thus one can adjust the phase of the synchronized clock in 1/40 th steps of the event clock period. To change the generated clock phase in respect to the trigger we can select the trigger polarity by bit CMLTL in the CML Control register and the trigger position also in the CML Control register.
GTX Pattern Mode
. . . In pattern mode one can generate arbitrary bit patterns taking into account following: The pattern length is a multiple of 40 bits, where each bit is 1/40 th of the event clock period . . Maximum length of the arbitrary pattern is 40 × 2048 bits A pattern can be triggered from any pulse generator, distributed bus bit etc. When triggered the pattern generator starts sending 40 bit words from the pattern memory sequentially starting from position 0. This goes on until the pattern length set by the samples register has been reached. If the pattern generator is in recycle mode the pattern continues immediately from position 0 of the pattern memory. If the pattern generator is in single pattern mode, the pattern stops and the 40 bit word from the last position of the pattern memory (2047) is sent out until the pattern generator is triggered again.
GTX GUN-TX-203 Mode
The cPCI-EVRTG-300 has two SFP outputs CH1 (GTX6) and CH2 (GTX7) that can generate a modulated signal that can be received by the Electron Gun trigger receiver GUN-RC-203. The GUN-TX-203 Mode has been designed to operate with a RF bucket clock of 499.654 MHz and event clock of ¼ of the RF clock. To enable the GUN-TX-203 Mode one has to set bits GTX2MD and CMLENA in the CML/GTX Control register for the given GTX output. The pulse output delay can be changed in quarters of the event clock period by the GTXPH1:0 bits. For finer delay tuning the GTX delay lines may be adjusted (registers GTX6Dly for CH1 and GTX7Dly for CH2). The two SFP outputs share an external inhibit signal that only allows triggers when the external inhibit signal is in a given state. To use the external inhibit function a UNIV-TTLIN-IL module has to be mounted in Universal I/O slot UNIV0/1. To allow output pulses the inhibit signal at
Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finl Document: EVR-MRM-003.doc Page: 14 of 64 UNIVO has to be pulled low. In case of an open circuit output pulses are inhibited. It is possible to override the inhibit input with a control register bit.
Configurable Size Data Buffer
Some applications require deterministic data transmission. The configurable size data buffer provides a configurable size buffer that may be transmitted over the event system link. The buffer size is configured in the Event Generator to up to 2 kbytes. The Event Receiver is able to receive buffers of any size from 4 bytes to 2 kbytes in four byte (long word) increments. Data reception is enabled by changing the distributed bus mode for data transmission ( mode = 1 in Data Buffer Control Register). This halves the distributed bus update rate. Before a data buffer can be received the data buffer receiver has to be enabled (write enable = 1 in control register). This clears the checksum error flag and sets the rx_enable flag. When a data buffer has been received the rx_enable flag is cleared and rx_complete flag is set. If  the received and computed checksums do not match the checksum error flag is set. The size of the data buffer transfer can be read from the control register. An interrupt may be generated after reception of a data buffer.
Interrupt Generation
The Event Receiver has multiple interrupt sources which all have their own enable and flag bits. The following events may be programmed to generate an interrupt: Receiver link state change . Receiver violation: bit error or the loss of signal. . Lost heartbeat: heartbeat monitor timeout. . . Write operation of an event to the event FIFO. . Event FIFO is full. . Data Buffer reception complete. In addition to the events listed above an interrupt can be generated from one of the pulse generator outputs, distributed bus bits or prescalers. The pulse interrupt can be mapped in a similar way as the front panel outputs.
External Event Input
An external hardware input is provided to be able to take an external pulse to generate an internal event. This event will be handled as any other received event.
Programmable Reference Clock
The event receiver requires a reference clock to be able to synchronise on the incoming event stream sent by the event generator. For flexibility a programmable reference clock is provided to allow the use of the equipment in various applications with varying frequency requirements.
Fractional Synthesiser
The clock reference for the event receiver is generated on-board the event receiver using a fractional synthesiser. A Micrel ( http://www.micrel.com ) SY87739L Protocol Transparent Fractional-N Synthesiser with a reference clock of 24 MHz is used. The following table lists programming bit patterns for a few frequencies.
The event receiver reference clock is required to be in ±100 ppm range of the event generator event clock.
Connections
cPCI-EVR-2x0 Front Panel Connections
The front panel of the Event Receiver and its optional side-by-side module is shown in Figure 6 and Figure 7. Document: EVR-MRM-003.doc Page: 16 of 64 Figure 7: Optional Side-by-side Module Front Panel The front panel of the Event Receiver includes the following connections and status leds:

VME-EVR-230 and VME-EVR-230RF Front Panel Connections
The front panel of the VME-EVR-230 Event Receiver is shown in Figure 6 and VME-EVR- 230RF in Figure 9: VME-EVR-230RF Event Receiver Front PanelFigure 9 respectively. Figure 8: VME-EVR-230 Event Receiver Front Panel The front panel of the Event Receiver includes the following connections and status leds: Connector / Led FAIL
Description Module Failure/Interlock active Micro-Research Finland Oy Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 17 of 64

VME P2 User I/O Pin Configuration
The following table lists the connections to the VME P2 User I/O Pins.
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PMC-EVR-230 Front Panel Connections The front panel of the PMC Event Receiver is shown in Figure 10. The front panel of the Event Receiver includes the following connections and status leds:

PMC-EVR-230 Pn4 User I/O Pin Configuration
The following table lists the connections to the PMC Pn4 User I/O Pins and to VME P2 pins when the module is mounted on a host with "P4V2-64ac" mapping complying VITA-35 PMC-P4 to VME-P2-Rows-A,C.
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cRIO-EVR-300 Front Panel Connections
Front Panel Connections
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Figure 12: cPCI-EVRTG-300 Event Receiver Front Panel
cPCI-EVR-300 Front Panel Connections
Figure 13: cPCI-EVR-300 Event Receiver Front Panel
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A 10baseT network interface is provided to upgrade the FPGA firmware and set up boot options. It is also possible to control the module over the network interface.
Assigning an IP Address to the Module
By default the modules uses DHCP (dynamic host configuration protocol) to acquire an IP address. In case a lease cannot be acquired the IP address set randomly in the 169.254.x.x subnet. The board can be programmed to use a static address instead if DHCP is not available. The module can be located looking at the lease log of the DHCP server or using a Windows tool called Locator.exe.
Using Telnet to Configure Module
To connect to the configuration utility of the module issue the following command: telnet 192.168.1.32 23 The latter parameter is the telnet port number and is required in Linux to prevent negotiation of telnet parameters which the telnet server of the module is not capable of. The telnet server responds to the following commands:
help command)
Boot Configuration (command b)
Command b displays the current boot configuration parameters of the module. The parameter may be changed by giving a new parameter value. The following parameters are displayed:
0 = use static IP address, 1 = use DHCP to acquire address, net mask Micro-Research Finland Oy Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 23 of 64
Note that after changing parameters the parameters have to be saved to internal flash by issuing the Save boot configuration (s) command. The changes are applied only after resetting the module using the reset command or hardware reset/power sequencing.
Memory dump (command d)
This command dumps 16 bytes of memory starting at the given address, if the address is omitted the previous address value is increased by 16 bytes. The most significant byte of the address determines the function of the access:
To dump the start of the EVR register map issue the 'd' command from the telnet prompt: VME-EVR-230RF -> d 7a00000 ↓ Addr 7a00000:  1005 0001 0000 0000 0000 0000 0000 VME-EVR-230RF -> d J Addr 7a000010:  0000 VME-EVR-230RF ->
Memory modify (commands d and m)
The access size is always a short word i.e. two bytes. To check the status register from the telnet prompt: VME-EVR-230RF -> m 7a00000 ↓ Addr 7a00000 data 1005 VME-EVR-230RF -> To clear the violation flag issue: J VME-EVR-230RF -> m 7a00000 1005 J Micro-Research Finland Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finl Document: EVR-MRM-003.doc Addr 7a00000 data 0000 VME-EVR-230RF ->
Tuning Delay Line (command t)
The VME Event Receiver VME-EVR-230RF has to be configured for proper event clock rate and the on-board delay line has to be tuned for the operating conditions. Before setting up the board make sure you have an Event Generator with the correct event clock connected to the Event Receiver. Also, let the EVR reach operating temperature (power on for 10 minutes in crate). See previous section for setting up the event clock rate. To start tuning issue command 't' from the telnet prompt: VME-EVR-230RF -> t 』 Starting tuning... Adjusted sampling phase to 75 Initial DCM phase -85 Fine tuned sampling phase to 78 Final DCM phase -73. VME-EVR-230RF -> After tuning the tuned values have to be stored in non-volatile memory: VME-EVR-230RF -> s J Confirm save (yes/no) ? yes J Configuration saved. VME-EVR-230RF -> Upgrading IP2022 Microprocessor Software (command u) To upgrade the Ubicom IP2022 microprocessor software download the upgrade image containing the upgrade to the module using TFTP: Linux In Linux use e.g. interactive tftp: $ tftp 192.168.1.32 tftp> bin tftp> put upgrade.bin /fw tftp> quit Windows In Windows command prompt issue the following command: C:\> tftp -i 192.168.1.32 PUT upgrade.bin /fw When the upgrade image has been downloaded and verified, enter at the telnet prompt following: VME-EVR-230 -> u J Really update firmware (yes/no) ? yes J
Document: EVR-MRM-003.doc Page: 25 of 64 Self programming triggered. The Event Receiver starts programming the new software and restarts. Upgrading FPGA Configuration File When the FPGA configuration file resides in internal flash memory a new file system image has to be downloaded to the module. This is done using TFTP protocol: Linux In Linux use e.g. interactive tftp: $ tftp 192.168.1.32 tftp> bin tftp> put filesystem.bin / tftp> quit Windows In Windows command prompt issue the following command: C:\> tftp -i 192.168.1.32 PUT filesystem.bin / Now the FPGA configuration file has been upgraded and the new configuration is loaded after next reset/power sequencing. Note! Due to the UDP protocol it is recommended to verify (read back and compare) the filesystem image before restarting the module. This is done following: Linux In Linux use e.g. interactive tftp: $ tftp 192.168.1.32 tftp> bin tftp> get / verify.bin tftp> quit $ diff filesystem.bin verify.bin $ If files differ you should get following message: Binary files filesystem.bin and verify.bin differ Windows In Windows command prompt issue the following command: C:\> tftp -i 192.168.1.32 GET / verify.bin C:\> fc /b filesystem.bin verify.bin Comparing files filesystem.bin and verify.bin FC: no differences encountered Micro-Research Finland C Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finlan Document: EVR-MRM-003.doc Page: 26 of 64
UDP Remote Programming Protocol
The VME-EVR can be remotely programmed using the 10baseT Ethernet interface with a protocol over UDP (User Datagram Protocol) which runs on top of IP (Internet Protocol). The default port for remote programming is UDP port 2000. The UDP commands are built upon the following structure: access_type (1 byte) status (1 byte) address (4 bytes) ref (4 bytes) data (2 bytes) The first field defines the access type:
0x02 Write and Read back Register from module The second field tells the status of the access:
The access size is always a short word i.e. two bytes. The most significant byte of the address determines the function of the access: Address 0x7800000 0x7a00000 Function CR/CSR space access EVR registers access Read Access (Type 0x01) The host sends a UDP packet to port 2000 of the VME-EVR with the following contents: data (2 bytes) access_type (1 byte) 0x01 status (1 byte) 0x00
address (4 bytes) 0x7a00000 (Control and Status register Function 0 address) ref (4 bytes) 0x000000 If the read access is successful the VME-EVR replies to the same host and port the message came from with the following packet: access_type (1 byte) data (2 bytes) 0x01
address (4 bytes) 0x7a00000 (Control and Status register Function 0 address) Micro-Research Finland C Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 27 of 64 ref (4 bytes) 0x000000 Write Access (Type 0x02) The host sends a UDP packet to port 2000 of the VME-EVR with the following contents: access_type (1 byte) status (1 byte) 0x02 0x00 data (2 bytes) 0x0001 address (4 bytes) 0x7a00002 (Mapping RAM Address register Function 0 address) ref (4 bytes) 0x000000 If the write access is successful the VME-EVR replies to the same host and port the message came from with the following packet: access_type (1 byte) status (1 byte) 0x00 0x02 data (2 bytes) 0x0001 address (4 bytes) 0x8000000 (Mapping RAM Address register Function 0 address) ref (4 bytes) Notice that in the reply message the data returned really is the data read from the address specified in the address field so one can verify that the data really was written ok. 0x000000
cRIO-EVR-300
Connections
The cRIO-EVR connects to the CompactRIO backplane through a DSUB connector. The pin usage is as follows:
The serial interface runs with a baud rate of 115200 baud, 8 bit data, one stop bit, no parity and no handshaking.
Boot Monitor
The boot monitor is started in case the cRIO-EVR receives a '@' character immediately after it has been powered up. The boot monitor can be used to flash the cRIO-EVR firmware. It supports the following commands:

Firmware Upgrade (on Linux)
The configuration flash memory of the cRIO-EVR holds two firmware images: a primary image and a golden image. The primary image is normally loaded and upgraded. If the primary image for gets corrupted because of a programming error or power failure during upgrade the golden image gets loaded which will allow retrying the firmware upgrade of the primary image. This upgrade procedure will require the cRIO-EVR-UNIVIO –board connected to the cRIO- EVR. The firmware can be upgraded on a CompactRIO system using a tool written in LabView. Connect a USB cable to the cRIO-EVR-UNIVIO USB connector and start your favourite terminal program with 115200 baud, 8 bit data, one stop bit, no parity and no handshaking. Keep the '@' key pressed, power up the cRIO-EVR and wait until the cRIO-EVR 1. responds with periods ‘.’ Enter the command 'EPI' (the characters are not echoed back). The cRIO-EVR will 2. respond with a number of '+' one for each erased sector and a final '.' when complete. Enter the command ‘L’ 3. From a command window send the new firmware image to the serial port e.g. 4. dd if=firmware_file.exo of=/dev/ttyusb0 5. When the previous operation is complete enter '@' on the terminal to stop loading S- records. The cRIO-EVR will responds with the number of S-records received and the number of checksum errors, two concatenated 32-bit hexadecimal numbers Enter command 'PPI' to program the firmware image from RAM to flash. The cRIO- 6. EVR will output lots of '+', one for each successful page program and a final '.' The following steps are optional: Enter command 'RP' to refresh the RAM image from 7. flash. Enter command ‘V’ 8. From a command window send the new firmware image to the serial port e.g. 9. dd if=firmware_file.exo of=/dev/ttyusb0 10. When the previous operation is complete enter '@' on the terminal to stop loading S- records. The cRIO-EVR will responds with the number of S-records received and the number of checksum errors, two concatenated 32-bit hexadecimal numbers
Programming Details
VME CR/CSR Support
The VME Event Receiver modules provides CR/CSR Support as specified in the VME64x specification. The CR/CSR Base Address Register is determined after reset by the inverted state of VME64x P1 connector signal pins GA4*-GA0*. In case the parity signal GAP* does not match the GAx* pins the CR/CSR Base Address Register is loaded with the value 0xf8 which corresponds to slot number 31. Note: the boards can be used in standard VME crates where geographical pins do not exist, in this case the user may either insert jumpers to set the geographical address or use the default setting when the board's CR/CSR base address will be set to 0xf8.
After power up or reset the board responds only to CR/CSR accesses with its geographical address. Prior to accessing Event Receiver functions the board has to be configured by accessing the boards CSR space. The Configuration ROM (CR) contains information about manufacturer, board ID etc. to identify boards plugged in different VME slots. The following table lists the required field to locate an Event Receiver module.
For convenience functions are provided to locate VME64x capable boards in the VME crate. STATUS vmeCRFindBoard(int slot, UINT32 ieee_oui, UINT32 board_id, int *p_slot); To locate the first Event Receiver in the crate starting from slot 1, the function has to be called following: #include "vme64x_cr.h" int slot = 1; int slot_evr; vmeCRFindBoard(slot, MRF_IEEE_OUI, MRF_EVR200RF_BID, &slot_evr); If this function returns OK, an Event Receiver board was found in slot slot_evr .
Event Receiver Function 0,1 and 2 Registers
The Event Receiver specific register are accessed via Function 0 and Function 1 as specified in the VME64x specification. The access size for Function 0 has been limited to 2 kbytes (0x0800) so not all EVR registers are accessible through this Function. The access size for Functions 1 and 2 is 256 kbytes, so this function should not be used for A16 access. Contrary to the VME64x specification the address/address modifier compare logic does not distinguish between privileged and non-privileged accesses and accepts both. To enable a Function, the address decoder compare register for the Function in CSR space has to be programmed. For convenience a function to perform this is provided, too: STATUS vmeCSRWriteADER(int slot, int func, UINT32 ader); To configure Function 0 of a Event Receiver board in slot 3 to respond to A16 accesses at the address range 0x1800-0x1FFF the function has to be called with following values: vmeCSRWriteADER(3, 0, 0x18A4); ADER contents are composed of the address mask and address modifier, the above is the same as:
Document: EVR-MRM-003.doc Page: 31 of 64 vmeCSRWriteADER(3, 0, (slot << 11) | (VME_AM_SUP_SHORT_IO << 2)); To get the memory mapped pointer to the configured Function 0 registers on the Event Receiver board the following VxWorks function has to be called: MrfEvrStruct *pEvr; sysBusToLocalAdrs(VME_AM_SUP_SHORT_IO, (char *) (slot << 11), (void *) pEvr); Note: using the data transmission capability requires more than 4 kbytes, so using function 1 with addressing mode A24 is suggested, following: vmeCSRWriteADER(3, 1, (slot << 19) | (VME_AM_STD_USR_DATA << 2)); MrfEvrStruct *pEvr; sysBusToLocalAdrs(VME_AM_STD_USR_DATA, (char *) (slot << 19), (void *) pEvr);
Register Map

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Bit EVREN TXLP RXLP OUTEN SRST LEMDE
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Interrupt Flag Register

Interrupt Enable Register
Bit IRQEN Function Master interrupt enable: 0 – disable all interrupts 1 – allow interrupts
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This bit is used by the low level driver to disable further interrupts before
Hardware Interrupt Mapping Register
address Bit 7 bit 5 Bit 4 bit 3 bit 2 bit 6 0x013 Mapping ID (see Table 1 for mapping IDs) bit 1 bit 0

Transmit Data Buffer Control Register

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FPGA Firmware Version Register

address 0x02F
Bits Form Factor Function 0 – CompactPCI 3U 1 – PMC 2 – VME64x 3 – CompactRIO 4 – CompactPCI 6U
Event Counter Clock Prescaler Register
address 0x042 bit 15 Timestamp Event Counter Clock Prescaler Register bit 0 Microsecond Divider Register address 0x04e
bit 0 For 100 MHz event clock this register should read 100, for 50 MHz event clock this register should read 50. This value is used e.g. for the heartbeat timeout. Micro-Research Finland Oy Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 40 of 64
Clock Control Register

Bit Function CGLOCK Micrel SY87739L locked (read-only) Other bits n/a on cPCI-EVR
Seconds Shift Register
bit 31 address 0x05c Seconds Shift Register (read-only) bit 0 Seconds Counter Register address 0x060 bit 31 Seconds Counter Register (read-only) bit 0
Timestamp Event Counter Register
address 0x064 bit 31 Timestamp Event Counter Register (read-only) bit 0 Seconds Latch Register address 0x068 bit 31
Timestamp Event Latch Register address bit 31 0x06c Timestamp Event Latch Register (read-only) bit 0 FIFO Seconds Register address 0x070 bit 31 FIFO Seconds Register (read-only) bit 0 FIFO Timestamp Register bit 31 address 0x074 FIFO Timestamp Register (read-only) bit 0
FIFO Event Register
address 0x07b FIFO Event Code Register (read-only) bit 0 bit 7
Document: EVR-MRM-003.doc Page: 41 of 64 Note that reading the FIFO event code registers pulls the event code and timestamp/seconds value from the FIFO for access. The correct order to read an event from FIFO is to first read the event code register and after this the timestamp/seconds registers in any order. Every read access to the FIFO event register pulls a new event from the FIFO if it is not empty.

SY87739L Fractional Divider Configuration Word
address 0x080 bit 31

Prescaler 0 Register
Bit 15 address 0x102 Prescaler 0 Register
bit 0 bit 0 Micro-Research Finland Oy Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 42 of 64 Prescaler 2 Register address Bit 15 0x10a Prescaler 2 Register bit 0
bit 0
Micro-Research Finland Oy Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 43 of 64 0x40D Front panel OUT6 Mapping ID Front panel OUT7 Mapping ID 0x40F Notes: cPCI-EVR does not have any Front panel outputs. PMC-EVR has three front panel outputs OUT0 to OUT2. VME-EVR-230 has eight Front panel outputs OUT0 to OUT7. VME-EVR-230RF has seven Front panel outputs OUT0 to OUT3 (TTL level), OUT4 to OUT6 CML level (see section about CML outputs for details). bit 0
cPCI-EVR-220/230 has two Universal I/O slots (four outputs UNIV0 to UNIV3). An optional side-by-side module provides three more slots (six additional outputs UNIV4 to UNIV9). PMC-EVR does not have any Universal I/O slots. VME-EVR has two Universal I/O slots (four outputs UNIVO to UNIV3). cPCI-EVR-300 has six Universal I/O slots (twelve outputs UNIVO to UNIV11).
Transition Board Output Mapping Registers
bit 0
Bit 7 bit 6 Bit 4 bit 5 bit 3 bit 2 bit 1 Transition Board Output TBOUT0 Mapping ID (see Table 1 for mapping IDs) Transition Board Output TBOUT1 Mapping ID Transition Board Output TBOUT2 Mapping ID ... Notes: cPCI-EVRs and cRIO-EVR do not have any Transition board outputs.
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CML Output Pattern Registers (CMLxPatxx)
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Bit 19 MSB is sent out first, LSB last Note that GTX pattern registers are accessed through the first four address locations of the GTX pattern memory.
CML/GTX Output Control Register

SFP Module EEPROM and Diagnostics
Small Form Factor Pluggable (SFP) transceiver modules provide a means to identify the module by accessing an EEPROM. As an advanced feature some modules also support reading dynamic information including module temperature, receive and transmit power levels etc. from the module. The EVR gives access to all of this information through a memory window of 2 × 256 bytes. The first 256 bytes consist of the EEPROM values and the rest of the advanced values.
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Application Programming Interface (API)
A Linux device driver and application interface is provided to setup up the Event Receiver. Function Reference int EvrOpen(struct MrfErRegs **pEr, char *device_name); Opens the EVR device for access. Simultaneous Description
Micro-Research Finland Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finla Document: EVR-MRM-003.doc Page: 50 of 64 Returns -1 on error. int EvrClose(int fd); Description
Closes the EVR device after opening by EvrOpen. File descriptor returned by EvrOpen Returns zero on success. Returns -1 on error. int EvrEnable(volatile struct MrfErRegs *pEr, int state); Description Parameters volatile struct MrfErRegs *pEr int state Return value Enables the EVR and allows reception of events. Pointer to memory mapped EVR register base. 0: disable 1: enable Returns zero when EVR disabled Returns non-zero when EVR enabled int EvrGetEnable(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value Retrieves state of  the EVR. Pointer to memory mapped EVR register base. Returns zero when EVR disabled Returns non-zero when EVR enabled void EvrDumpStatus(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value Dump EVR status. Pointer to memory mapped EVR register base. None int EvrGetViolation(volatile struct MrfErRegs *pEr, int clear); Description Parameters volatile struct MrfErRegs *pEr
Return value Get/clear EVR link violation status. Pointer to memory mapped EVR register base. 0: don’t clear 1: clear status Returns 0 when no violation detected. Return non-zero when violation detected. Micro-Research Finland ( Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 51 of 64 void EvrDumpMapRam(volatile struct MrfErRegs *pEr, int ram); Dump EVR mapping RAM. Description volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register Parameters base. int ram Number of RAM: 0 or 1 None Return value int EvrMapRamEnable(volatile struct MrfErRegs *pEr, int ram, int enable); Description Parameters volatile struct MrfErRegs *pEr
Return value Enable/disable EVR mapping RAM. Pointer to memory mapped EVR register base. Number of RAM: 0 or 1 0: disable RAM 1: enable RAM None int EvrSetForwardEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable); Description Parameters volatile struct MrfErRegs *pEr int ram int code int enable Return value int EvrEnableEventForwarding(volatile struct MrfErRegs *pEr, int state): Description Parameters volatile struct MrfErRegs *pEr int state Return value Enables forwarding of enabled event codes. Pointer to memory mapped EVR register base. 0: disable forwarding 1: enable forwarding Returns zero when forwarding disabled Returns non-zero when forwarding enabled int EvrGetEventForwarding(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value Enable/disable EVR event forwarding. Pointer to memory mapped EVR register base. Number of mapping RAM: 0 or 1 Event code to enable/disable event forwarding 0: disable event forwarding for code 1: enable event forwarding for code None Retrieves state of  event forwarding. Pointer to memory mapped EVR register base. Returns zero when forwarding disabled Micro-Research Finland Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finl Document: EVR-MRM-003.doc Page: 52 of 64 Returns non-zero when forwarding enabled int EvrSetLedEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable); Description Parameters volatile struct MrfErRegs *pEr
Enable/disable EVR led event (Front panel led will flash up for enabled event codes). Pointer to memory mapped EVR register base. Number of mapping RAM: 0 or 1 Event code to enable/disable led event for 0: disable led event for code 1: enable led event for code None Return value int EvrSetFIFOEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable); Description Parameters volatile struct MrfErRegs *pEr int ram int code int enable Return value Enable/disable storing specified event code into FIFO. Pointer to memory mapped EVR register base. Number of mapping RAM: 0 or 1 Event code to enable/disable 0: disable storing event code in FIFO 1: enable storing event code in FIFO None int enable); int EvrSetLatchEvent(volatile struct MrfErRegs *pEr, int ram, int code, Enable/disable latching timestamp on specified event code. Pointer to memory mapped EVR register base. Number of mapping RAM: 0 or 1 Event code to enable/disable 0: disable latching of timestamp on event code 1: enable latching of timestamp upon reception of event code None Description volatile struct MrfErRegs *pEr Parameters Return value int EvrSetLogStopEvent(volatile struct MrfErRegs *pEr, int ram, int code, int enable); Description Enable/disable stopping of writes to event log on reception of event code. Pointer to memory mapped EVR register base. volatile struct MrfErRegs *pEr Parameters int ram int code int enable Micro-Research Finland C Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finlan
Document: EVR-MRM-003.doc Page: 53 of 64 Number of mapping RAM: 0 or 1 Event code to enable/disable 0: disable stop log event 1: stop log writes upon reception of event code None Return value int EvrClearFIFO(volatile struct MrfErRegs *pEr); Clear EVR Event FIFO. Pointer to memory mapped EVR register base. None. Description Parameters volatile struct MrfErRegs *pEr Return value int EvrGetFIFOEvent(volatile struct MrfErRegs *pEr, struct FIFOEvent *fe); Get one Event from EVR Event FIFO. Pointer to memory mapped EVR register base. Pointer to structure to place event in. Description Parameters volatile struct MrfErRegs *pEr struct FIFOEvent *fe struct FIFOEvent { u32 TimestampHigh; u32 TimestampLow; u32 EventCode; }; Return value 0 – Event retrieved successfully -1 – Event FIFO was empty int EvrEnableLogStopEvent(volatile struct MrfErRegs *pEr, int enable); Description Enable/disable stopping of writing to event log on reception of event codes with STOP Log mapping bit set. Pointer to memory mapped EVR register base. 0: disable stop log event 1: stop log writes upon reception of event codes with STOP log mapping bit set. Returns zero when stop events disabled Returns non-zero when stop events enabled volatile struct MrfErRegs *pEr Parameters int enable Return value int EvrGetLogStopEvent(volatile struct MrfErRegs *pEr); Check if log stop events are enabled. Pointer to memory mapped EVR register base. Returns zero when stop events disabled Returns non-zero when stop events enabled Description Parameters volatile struct MrfErRegs *pEr Return value Micro-Research Finland Oy Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 54 of 64 int EvrEnableLog(volatile struct MrfErRegs *pEr, int enable); Enable/disable writing to log. Description volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register Parameters base. int enable 0: disable writes to log 1: enable writes to log Returns zero when log enabled Return value Returns non-zero when log stopped. int EvrGetLogState(volatile struct MrfErRegs *pEr, int enable); Description Get log state. Pointer to memory mapped EVR register volatile struct MrfErRegs *pEr Parameters base. Returns zero when logging enabled Return value Returns non-zero when logging stopped. int EvrGetLogStart(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value int EvrGetLogEntries(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value void EvrDumpFIFO(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value int EvrClearLog(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value void EvrDumpLog(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value Get log start position. Pointer to memory mapped EVR register base. Returns relative address to first log entry in log ring buffer. Get number of entries in log. Pointer to memory mapped EVR register base. Returns number of entries in log (0 to 512). Dump EVR FIFO on stdout. Pointer to memory mapped EVR register base. None Empty EVR Event Log. Pointer to memory mapped EVR register base. None. Print out full EVR event log on stdout. Pointer to memory mapped EVR register base. None Micro-Research Finland ( Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 55 of 64 int EvrSetPulseMap(volatile struct MrfErRegs *pEr, int ram, int code, int trig, int set, int clear); Description Set up pulse generators for event codes. volatile struct MrfErRegs *pEr Parameters Pointer to memory mapped EVR register
int set int clear Return value int EvrClearPulseMap(volatile struct MrfErRegs *pEr, int ram, int code, int trig, int set, int clear); Description Parameters volatile struct MrfErRegs *pEr int ram int code int trig Set up pulse generators for event codes. Pointer to memory mapped EVR register base. Number of mapping RAM: 0 or 1 Event code affected 0: no change 1: Don’t trigger pulse generator from this event code 0: no change 1: Don’t set pulse high with this event code 0: no change 1: Don’t pull pulse low with this event code None
Return value int EvrSetPulseParams(volatile struct MrfErRegs *pEr, int pulse, int presc, int delay, int width); Description Parameters volatile struct MrfErRegs *pEr int pulse
Return value Set pulse generator parameters. Pointer to memory mapped EVR register base. Number of pulse generator 0-9 Prescaler value Delay Value Width Value Returns 0 on success, -1 on error void EvrDumpPulses(volatile struct MrfErRegs *pEr, int pulses); Description Dump EVR pulse generator settings. volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register Parameters base. Number of mapping RAM: 0 or 1 Event code affected 0: no change 1: Trigger pulse generator from event code 0: no change 1: Set pulse high with this event code 0: no change 1: Pull pulse low with this event code None Micro-Research Finland C Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finla Document: EVR-MRM-003.doc Page: 56 of 64 base. Number of pulse generators to dump None int EvrSetPulseProperties(volatile struct MrfErRegs *pEr, int pulse, int polarity, int map_reset_ena, int map_set_ena, int map_trigger_ena, int enable); Description Parameters volatile struct MrfErRegs *pEr
Set pulse generator properties. Pointer to memory mapped EVR register base. Number of pulse generator 0-9 0: normal polarity 1: inverted polarity 0: disable reset input 1: enable reset input 0: disable set input 1: enable set input 0: disable trigger input 1: enable trigger input 0: pulse output disabled 1: pulse output enabled Returns 0 on success, -1 on error Return value int EvrSetUnivOutMap(volatile struct MrfErRegs *pEr, int output, int map); Description Parameters volatile struct MrfErRegs *pEr
Return value Set up universal output mappings. Pointer to memory mapped EVR register base. Universal Output number Signal mapping (see erapi.h for details) Returns 0 on success, -1 on error void EvrDumpUnivOutMap(volatile struct MrfErRegs *pEr, int outputs); Description Parameters volatile struct MrfErRegs *pEr
Dump EVR Universal output mappings. Pointer to memory mapped EVR register base. Number of outputs to dump
int pulses Return value Micro-Research Finland ( Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finlan Document: EVR-MRM-003.doc Page: 57 of 64 int EvrSetFPOutMap(volatile struct MrfErRegs *pEr, int output, int map); Description Parameters volatile struct MrfErRegs *pEr
Return value Set up front panel output mappings. Pointer to memory mapped EVR register base. Front Panel Output number Signal mapping (see erapi.h for details) Returns 0 on success, -1 on error void EvrDumpFPOutMap(volatile struct MrfErRegs *pEr, int outputs); Dump EVR Front panel output mappings. Description Parameters volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register base. int outputs Number of outputs to dump None Return value int EvrSetTBOutMap(volatile struct MrfErRegs *pEr, int output, int map); Description Parameters volatile struct MrfErRegs *pEr
Set up Transition board output mappings. Pointer to memory mapped EVR register base. Transition Board Output number Signal mapping (see erapi.h for details) Returns 0 on success, -1 on error Return value void EvrDumpTBOutMap(volatile struct MrfErRegs *pEr, int outputs); Dump EVR Transition board output Description mappings. Parameters volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register base. int outputs Number of outputs to dump None Return value void EvrIrqAssignHandler(volatile struct MrfErRegs *pEr, int fd, void (*handler)(int)); Description Parameters volatile struct MrfErRegs *pEr
Return value Assign EVR interrupt handler. Pointer to memory mapped EVR register base. File descriptor returned by EvrOpen Pointer to interrupt handler function None Micro-Research Finland ( Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland Document: EVR-MRM-003.doc Page: 58 of 64 int EvrIrqEnable(volatile struct MrfErRegs *pEr, int mask); Enable EVR interrupts. Description volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register Parameters base. int mask Interrupt mask (see erapi.h) for mask bits. Return value Returns mask read back from EVR. int EvrGetIrqFlags(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value Get EVR interrupt flags. Pointer to memory mapped EVR register base. Returns EVR interrupt flags. int EvrClearIrqFlags(volatile struct MrfErRegs *pEr, int mask); Clears EVR interrupt flags. Description volatile struct MrfErRegs *pEr Parameters Pointer to memory mapped EVR register base. int mask Interrupt clear mask (see erapi.h) for flag bits. Return value Returns flags read back from EVR. void EvrIrqHandled(int fd); Description Parameters volatile struct MrfErRegs *pEr
Return value Function to call at the end of interrupt handler function. Pointer to memory mapped EVR register base. File descriptor returned by EvrOpen None int EvrSetPulseIrqMap(volatile struct MrfErRegs *pEr, int map); Set up interrupt mappings. Description Parameters Pointer to memory mapped EVR register volatile struct MrfErRegs *pEr base. int map Signal mapping (see erapi.h for details) Returns 0 on success, -1 on error Return value int EvrUnivDlyEnable(volatile struct MrfErRegs *pEr, int dlymod, int enable); Description Parameters volatile struct MrfErRegs *pEr Enable/disable UNIV-LVPECL-DLY output. Pointer to memory mapped EVR register base. Micro-Research Finland C Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finlan
int enable Return value Document: EVR-MRM-003.doc Page: 59 of 64 Number of UNIV-LVPECL-DLY module: 0 – module in slot #1 (UNIV0/1) 1 – module in slot #2 (UNIV2/3) 0 – disable module output 1 – enable module output Returns 0 on success, -1 on error int EvrUnivDlySetDelay(volatile struct MrfErRegs *pEr, int dlymod, int dly0, int dly1); Description Parameters volatile struct MrfErRegs *pEr int dlymod
int dly01 Return value Enable/disable UNIV-LVPECL-DLY output. Pointer to memory mapped EVR register base. Number of UNIV-LVPECL-DLY module: 0 – module in slot #1 (UNIV0/1) 1 – module in slot #2 (UNIV2/3) Delay value for output 0/2: 0 – shortest delay 1023 – longest delay (approx. 9-10 ps/step) Delay value for output 1/3: 0 – shortest delay 1023 – longest delay (approx. 9-10 ps/step) Returns 0 on success, -1 on error int EvrSetFracDiv(volatile struct MrfErRegs *pEr, int fracdiv); Description Set fractional divider control word which Parameters volatile struct MrfErRegs *pEr
Return value provides reference frequency for receiver. Pointer to memory mapped EVR register base. Fractional divider control word Returns control word written int EvrGetFracDiv(volatile struct MrfErRegs *pEr); Description Parameters volatile struct MrfErRegs *pEr Return value Get fractional divider control word which provides reference frequency for receiver. Pointer to memory mapped EVR register base. Returns control word int EvrSetDBufMode(volatile struct MrfErRegs *pEr, int enable); Description Enable/disable data buffer mode. When data buffer mode is enabled every other distributed bus byte is reserved for data transmission thus the distributed bus Micro-Research Finland Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finla Document: EVR-MRM-003.doc Page: 60 of 64 Parameters volatile struct MrfErRegs *pEr
Return value bandwidth is halved. Pointer to memory mapped EVR register base. 0 – disable data buffer mode 1 – enable data buffer mode Data buffer status (see Receive Data Buffer Control and Status Register on page 38 for bit definitions). int EvrGetDBufStatus(volatile struct MrfErRegs *pEr); Description Get data buffer mode. When data buffer Parameters volatile struct MrfErRegs *pEr
mode is enabled every other distributed bus byte is reserved for data transmission thus the distributed bus bandwidth is halved. Pointer to memory mapped EVR register base. Data buffer status (see Receive Data Buffer Control and Status Register on page 38 for bit definitions). int EvrReceiveDBuf(volatile struct MrfErRegs *pEr, int enable); Enable reception of data buffer. After Description Parameters volatile struct MrfErRegs *pEr int enable Return value reception of a data buffer further reception is disabled until re-enabled by software. Pointer to memory mapped EVR register base. 0 – disable data buffer reception. 1 – enable data buffer reception Data buffer status (see Receive Data Buffer Control and Status Register on page 38 for definitions). int EvrGetDBuf(volatile struct MrfErRegs *pEr, char *dbuf, int size); Description Parameters volatile struct MrfErRegs *pEr
Return value Receive data buffer data. Pointer to memory mapped EVR register base. Pointer to local data buffer Size of dbuf buffer. Size of received buffer. -1 on error (no buffer received, local buffer too small or checksum error) Document: EVR-MRM-003.doc Page: 61 of 64 Micro-Research Finland ( Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finland int EvrSetTimestampDivider(volatile struct MrfErRegs *pEr, int div); Set timestamp counter divider Description volatile struct MrfErRegs *pEr Pointer to memory mapped EVR register Parameters base. int div Timestamp divider value: 0 – count timestamp events (or use DBUS4 as clock) 1 to 65535 – count at event clock/value rate Return value Return divider value. int EvrSetTimestampDBus(volatile struct MrfErRegs *pEr, int enable); Description Control timestamp counter count from distributed bus bit 4 (DBUS4). Pointer to memory mapped EVR register base. 0 – disable counting from DBUS4 1 – enable timestamp counting from DBUS4. Note: Timestamp counter has to be 0. volatile struct MrfErRegs *pEr Parameters Return value int EvrGetTimestampCounter(volatile struct MrfErRegs *pEr); Description Get Timestamp Counter value volatile struct MrfErRegs *pEr Parameters Pointer to memory mapped EVR register base. Return value Timestamp Counter value Get Timestamp Seconds Counter value Pointer to memory mapped EVR register base. Timestamp Seconds Counter value Description Parameters volatile struct MrfErRegs *pEr Return value int EvrGetTimestampLatch(volatile struct MrfErRegs *pEr); Get Timestamp Latch value Pointer to memory mapped EVR register base. Timestamp Latch value Description Parameters volatile struct MrfErRegs *pEr Return value int EvrGetSecondsLatch(volatile struct MrfErRegs *pEr); Get Timestamp Seconds Latch value Description volatile struct MrfErRegs *pEr Parameters Pointer to memory mapped EVR register int enable int EvrGetSecondsCounter(volatile struct MrfErRegs *pEr); Document: EVR-MRM-003.doc Page: 62 of 64 Micro-Research Finland ( Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finl base. Timestamp Seconds Latch value Return value int EvrSetPrescaler(volatile struct MrfErRegs *pEr, int presc, int div); Set prescaler divider Pointer to memory mapped EVR register base. Number of prescaler Prescaler divider value: 1 to 65535 – count at event clock/value rate Return divider value. Description Parameters volatile struct MrfErRegs *pEr int presc int div Return value int edge_enable, int level_enable); int EvrSetExtEvent(volatile struct MrfErRegs *pEr, int ttlin, int code, Description Parameters Set external event code Pointer to memory mapped EVR register base. Number of front panel input: 0, 1 Event code to generate on detected edge/level 0 – disable 1 – enable events on active edge 0 – disable 1 – enable sending out event every 1 us on active level 0 – successful -1 – error volatile struct MrfErRegs *pEr int ttlin int code int edge_enable int level_enable Return value int EvrSetBackEvent(volatile struct MrfErRegs *pEr, int ttlin, int code, int edge_enable, int level_enable); Description Parameters Set backwards event code Pointer to memory mapped EVR register base. Number of front panel input: 0, 1 Event code to send out on detected edge/level 0 – disable 1 – enable events on active edge 0 – disable 1 – enable sending out event every 1 us on active level 0 – successful -1 – error volatile struct MrfErRegs *pEr int ttlin int code int edge_enable int level_enable Return value Micro-Research Finland Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Finla Document: EVR-MRM-003.doc Page: 63 of 64 int EvrSetExtEdgeSensitivity(volatile struct MrfErRegs *pEr, int ttlin, int edge); Description Parameters volatile struct MrfErRegs *pEr
Return value -1 – error int EvrSetExtLevelSensitivity(volatile struct MrfErRegs *pEr, int ttlin, int level); Description
volatile struct MrfErRegs *pEr
Return value Set external input edge sensitivity Pointer to memory mapped EVR register base. Number of front panel input: 0, 1 0 – detect rising edges 1 – detect falling edges 0 – successful Set external input edge sensitivity Pointer to memory mapped EVR register base. Number of front panel input: 0, 1 0 – detect high level (active high) 1 – detect low level (active low) 0 – successful -1 – error int EvrSetTxDBufMode(volatile struct MrfErRegs *pEr, int enable); Enable/disable transmitter data buffer mode. Description
volatile struct MrfErRegs *pEr
When data buffer mode is enabled every other distributed bus byte is reserved for data transmission thus the distributed bus bandwidth is halved. Pointer to memory mapped EVR register base. 0 – disable transmitter data buffer mode 1 – enable transmitter data buffer mode Transmit data buffer status (see Transmit Data Buffer Control Register on page 38 for bit definitions). int EvrGetTxDBufStatus(volatile struct MrfErRegs *pEr); Description Get transmit data buffer status. When data buffer mode is enabled every other distributed bus byte is reserved for data transmission thus the distributed bus bandwidth is halved. Pointer to memory mapped EVR register base. Transmit data buffer status (see Transmit Data Buffer Control Register on page 38 for
Micro-Research Finland Jorvas Hitech Center, Hirsalantie 11, 02420 Jorvas, Fir Document: EVR-MRM-003.doc Page: 64 of 64 bit definitions). int EvrSendTxDBuf(volatile struct MrfErRegs *pEr, char *dbuf, int size); Description Get transmit data buffer status. When data buffer mode is enabled every other
Return value int EvrGetFormFactor(volatile struct MrfErRegs *pEr);
volatile struct MrfErRegs *pEr Get form factor code from EVR. Pointer to memory mapped EVR register base. Form factor. See FPGA Firmware Version Register on page 39 for details.