ILC vertex detector

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A B S T R A C T

1. Introduction
Silicon-on-Insulator (SOI) technology integrates both silicon sensor and readout electronics in the same wafer [ 1 ]. Pixel detectors based on the SOI technology have several advantages compared with conven- tional hybrid detectors which are used for high energy physics experi- ments. The SOI detector realizes a low material budget, small pixel size, and low detector capacitance owing to the monolithic structure without bump-bonding. In addition, the detector employs a double SOI structure to improve radiation tolerance and to reduce cross talk between circuits and sensors ( Fig. 1 ). The double SOI wafer has an additional silicon layer for compensating the effect caused by the accumulation of holes in the oxide layer [ 2 ]. We are developing a new SOI pixel sensor for the vertex detector of the International Linear Collider (ILC) experiment. The ILC requires a new vertex detector system with high spatial resolution in order to identify the decay vertex of short-life-time particles for the precise measurement of Higgs boson and the search for physics beyond the Standard Model. We are currently designing an SOI pixel sensor, SOi sensor for FIne measurement of Space and Time (SOFIST), which has a pixel circuit with high position resolution and fine time resolution. In this paper, we report the development and evaluation results of the SOFIST prototype sensors.
2.  SOI sensor for ILC
The overview of the SOFIST sensor is shown in Fig. 2 . The following are requirements for the SOFIST development [ 3 ]. •  Single point resolution : 3 μm • Identification of 1300 bunches in ILC beam collisions every 554 ns The pixel circuit of the SOFIST has an area of 20 × 20 μm². For each pixel, the signal amplitude and timing information are stored in corresponding memories when the signal amplitude is higher than the threshold of the comparator. The timing information is used for the hit bunch identification. The timestamp memory holds the voltage level of the ramping signal. The ramp voltage is proportional to the integration time and provided globally to all pixels in a chip. This timestamp circuit records the hit timing as the ramp voltage. In order to handle possible multiple hits during the signal accumulation, the pixel has multiple sets of analog signal memories and timestamps. It is necessary to optimize the implementation of these functions in a small pixel area. We are prototyping step sensors for realizing this pixel circuit .
3.  SOFIST Ver.1
The prototype chips were fabricated with the 0.2 μm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process of Lapis semiconductor [ 4 ]. The first chip is called SOFIST Ver.1. It has 50 × 50 pixels with a pitch of 20 μm ( Fig. 3 ). The sensor thickness is 500 μm. Each pixel circuit has a pre-amplifier and memory capacitors. The pre-amplifier is a charge sensitive amplifier with a common-source stage and feedback https://doi.org/10.1016/j.nima.2018.06.075 Received 17 February 2018; Received in revised form 25 May 2018; Accepted 20 June 2018 Available online 30 June 2018 0168-9002/© 2018 Elsevier B.V. All rights reserved. capacitance. The sensor chip also has 8-bit Wilkinson-type ADC circuits of 50 channels. The Ver.1 sensor was evaluated with a 120 GeV proton beam at the FermiLab Test Beam Facility [ 5 ]. The detector setup consists of two SOFIST Ver.1 and four FPIX, SOI Fine PIXel detector ( Fig. 5 ). The FPIX also acts as the SOI detector and has small pixels with a pitch of 8 μm [ 6 ]. The FPIX sensors were used as the tracking detector for evaluating the SOFIST position resolution. Since the collected charge signal is proportional to the depletion thickness, we measured the backplane bias dependence of the SOFIST signal ( Fig. 4 ). The SOFIST signal was saturated about –80 V, so the sensor layer of 500 μm was fully depleted at this voltage. The SOFIST sensor data were taken with backplane biases of −130 and −15 V, which correspond to the sensor depletion thicknesses of 500 and 200 μm, respectively. The charge signal was digitized by 12-bit ADC on the readout board. The hit signal was reconstructed by clustering 5 × 5 pixels around the hit pixel. The hit position on the SOFIST chip was calculated from the weighted center of the cluster signal. We analyzed the position resolution by using the particle tracks. We extracted the track candidates from the hits of f four FPIX sensors. There were some spurious hit combinations due to the long integration time of FPIX. The track with minimum chi-square to the straight line was chosen for the analysis. We analyzed the residual of the hit position of the SOFIST to the reconstructed track. Figs. 6 and 7 show the residual distributions of X (horizontal) and Y (vertical) directions at 500 μm and 200 μm depletion thickness, respectively. The standard deviation of the residual distribution was evaluated as the position resolution. We obtained position resolutions of 1.37 in X direction and 1.35 μm in Y direction at a depletion thickness of 500 μm. The residuals were still narrow at a depletion thickness of 200 μm, and the position resolution is 1.33 μm in X direction and 1.32 μm in Y direction. The measured residual is the sum of the squares of the intrinsic resolution of SOFIST Ver.1 and the track uncertainty. The track uncertainty is expressed in terms of the FPIX resolution and the geometrical position of the SOFIST. The FPIX is shown to have an intrinsic resolution of about 0.65 μm [ 6 ] and the track uncertainty on the SOFIST sensor becomes about 0.65 μm. The SOFIST intrinsic resolution was extracted about 1.2 μm.
4.  SOFIST Ver.2
Fig. 8 shows the SOFIST Ver.2 sensor chip. The sensor has 80 × 64 pixels with a pitch of 25 μm. Since ILC detector requires the sensor thickness less than 100 μm for reducing multiple scattering effect, the Ver.2 sensor layer is thinned to 75 μm by grinding the back side of the chip. The Ver.2 pixel has a comparator circuit for discriminating the signal exceeding the threshold voltage. We have designed two types of pixel circuits, namely Analog signal pixel and Timestamp pixel ( Fig. 9 ). We will verify in-pixel timestamp function and the degradation of the position resolution. The pixel circuit and size will be optimized for satisfying both the timestamp and the resolution based on the evaluation of the Ver.2 sensor. The sensor production has been completed. We are currently evaluating the Ver.2 pixel circuits. Fig. 10  shows the responses of Analog signal and Timestamp pixel when a test pulse is inputted. The charge signal is input to the sensor node of the pixel. The pixel memory holds the signal voltage when the input signal exceeds the threshold level. Fig. 11 shows the pixel timestamp signal with inputting test pulse at specific timings. The ramp signal was generated with 1 mV per microsecond and delivered to each pixel. The slope of measured timestamp became about 0.96 mV per microsecond. We have confirmed the functionality of Ver.2 pixel circuits.
5.  Conclusion and future prospect
We have developed two prototype chips for realizing a new SOI pixel sensor SOFIST optimized for the ILC vertex detector. SOFIST Ver.1 chip has a pixel area of 20 × 20 μm² and column parallel ADC circuits. We evaluated the position resolution with a 120 GeV proton beam at the Fermilab Test Beam Facility. We obtained a position distribution of about 1.3 μm at a depletion thickness of 200 μm. The SOFIST Ver.1 resolution meets the requirement for the ILC experiment. SOFIST Ver.2 chip has a pixel area of 25 × 25 μm². We designed an in-pixel comparator for storing the amplitude and timestamp of the hit signal. These pixel functions have been verified by inputting the test pulse. We are planning a beam test for Ver.2 sensor in February 2018. We are also developing next sensors, Ver.3 and Ver.4, with full SOFIST functionality. The pixel of Ver.3 sensor has both analog signal and timestamp memories within 30 × 30 μm². The Ver.4 sensor is to be processed with 3D stacking technology in order to shrink the pixel size [ 7 ]. These sensor chips will be delivered by spring 2018.
Acknowledgments
This work was supported by MEXT KAKENHI Grant-in-Aid for Scientific Research on Innovative Areas 25109006, the Japan/US Co- operation Program in the Field of High Energy Physics. We wish to thank the staff of Fermilab Test Beam Facility for the support they provided for our beam test. This work was also supported by the VLSI Design and Education Center (VDEC), The University of Tokyo, with the collaboration of Cadence Design Systems, Inc., Mentor Graphics Co., Ltd., and Synopsys, Inc.