Merge of Functions in High-Level Synthesis Using Assembly Codes as Intermediate Representation Fumiaki TAKASHIMA † , Nagisa ISHIURA † , Makoto ORINO † , Hiroyuki TOMIYAMA †† , and Hiroyuki KANBARA††† † Kwansei Gakuin University, Gakuen 2-1, Sanda, Hyogo, 669–1337 Japan †† Ritsumeikan University, Noji-higashi 1-1-1, Kusatsu, Shiga, 525–8577 Japan ††† ASTEM RI, 134 Minamimachi Chudoji, Simogyo-ku Kyoto, 600–8813 Japan Abstract  This article presents a method of merging functions during high-level synthesis whose inputs are as- sembly codes generated by a compiler front-end. While synthesizing functions in programs into separate hardware modules is one of the major approaches in hardware/software codesign, the overheads for passing arguments, return values, and control will not be negligible when inter-function calls are made frequently. Our method attempts to reduce the overhead by merging multiple functions into a single hardware module. The functions are merged by "goto conversion" so that hardware function modules are callable both from the other hardware function modules and the software program. We take advantage of the fact that all the necessary tasks associated with function calls are incorporated as well as optimized in assembly codes generated by a front-end compiler, so that the major part of the merger tasks is done in source code level transformation.  By the merger, hardware cost, as well as the overhead for inter-function calls, is reduced due to resource sharing among the functions. The preliminary experiments based on ACAP high-level synthesizer showed that the number of the execution cycles is reduced by 15% while the FPGA LUT count is reduced by about 60%. Key words   high-level synthesis, function call, merge of function, goto conversion, ACAP — 1 — 1. [1] , C , [2]   [4] [5]. 1 , [3], [2], [4] CPU goto / . , . [2]   [4]. [2]   [4] 。 . , C , 1    , . (a) , (b) . (c)(d) (b) . (c) , (a) ,           , 1) (_ARG_ (b)
60%
2.1 /
）  (_RUN_ ) , 3) (_RET_ , (c) / [2]   [4]. (CDFG) , , 1 2.2 goto , (d)    , , 。 . , 4) ) (a) SW (b) HW 3.1 Goto goto 2 2(a)    , 1 _HW_func2, _HW_func3 Wait . _HW_func1 , Load ARG Store ARG, , Set RUN, Wait, Load RET    _HW_func3 Store RET    Reset RUN (DFG)           .  dfg1 dfg2     HW_func1 _HW_func2, _HW_func3 DFG . 2(b)  ,   2(a) ,        _HW_func2     _HW_func3 . Store ARG , Set ARG      HW_func3 DFG , HW_func3 . _HW_func2     _HW_func3 (dfg5) DFG . HW_func3 dfg6 DFG .  , Get RET , dfg2 , HW_func3 , _HW_func3     Wait, Load ARG, Store RET, Reset Run , _HW_func3 Wait , dfg5 , hw_sub.c ,  RUN_sub , _RUN_sub
= 1, 2, 3   , _HW_func1, _HW_func2, _HW_func3__ .  3. . hw_sub.c Wait, Load ARG, Store . RET, Reset RUN DFG 3.2 2(c) C DFG , 2) goto ( ) , ra 1(b) 3 3(a)   sw_stub.c  ,   1(a)   main.c . (  DFG .  (STATE)  ra ·       1(c) _RUN_sub . , .  12       , 20       , 28 , _RUN_sub    1, 2, 3 . 3(b)   hw_sub.c   , .  _HW_stub (9   28      )   , 2(c) , _RUN_sub . 30 48 f1, f2, f3    ,    1(b)                         , hw_sub.c sub.c 3(b)   hw_sub.c MIPS 4 (jump and link)             f3 . f1       8       jal , . / Goto CDFG 8 jal , jr (jump register) . jal      , DFG (10   15 ,  .      , jr        , ra . ra , DFG) ID      DFG , , / .  .          , goto 3.3 CDFG 5(a)   , goto DFG   , dfg5    dfg1 . dfg5 dfg2, dfg3 dfg4 . ra ID , dfg5    ID DFG , . DFG , . (a) 1      1 HW (b) Goto 2 Goto 14 , . 8wstub.c
10 { 11 12 13 14 15 }
_ARG_f2_0 = a2; _RUN_sub = 2; while(_RUN_sub){ ; } return RET_f2; 25 int f3(int a3) 26 {
27 28 29 30 31 } (a) SW _ARG_f1_0 = a1; _RUN_sub = 1; while(_RUN_sub){ ; } return _RET_f1; 12 13 14 15 16 17 18 19 20 21 22
23 24 25 26 27 28 } 29 30 int f1(int a1) 31 { 32 33 34 35 } 37 int f2(int a2) 39 40 return r2; 43 45 { 47 int r3 = a3 * 10; return r3; (b) HW 
 
 4. ACAP [2] 14 C . 1 50%, 15% Store [6] 2 Goto Goto ( ) LUT hw_sub.c
while(_RUN_sub==0){;} if(_RUN_sub==1) { int a1 = _ARG_f1_0; _RET_f1 = f1(a1); } else if(_RUN_sub==2) { int a2 = _ARG_f2_0;
_RET_f2 = f2(a2); } else if(_RUN_sub==3) { int a3 = _ARG_f3_0; _RET_f3 = f3(a3); _RUN_sub=0; 5 Perl (5.10.1) . ACAP Mac OSX Windows Cygwin MIPS CPU GCC (mips-elf-gcc 4.5.1) C MIPS CDFG Verilog-HDL , Linux, Xilinx ISE 12.2, ModelSim-Altera 6.5b Starter Edition _ARG_f3_0 = a3; _RUN_sub = 3; while(_RUN_sub){;} return RET_f3; 41 int r2 = f3(x2); 42 } 46 48 } 1 Verilog-HDL FF , Load 9 int x1 = a1 + 1; return r1; int r1 = f3(x1); 39  int x2 = a2 + 10;
39 44 int f3(int a3)

5.
ACAP 15%, FPGA LUT 60% [1] Daniel D. Gajski, Nikil D. Dutt, Allen C-H Wu, and Steve Y-L Lin:  High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers (1992). [2] : "MIPS , , "," , 2010-SLDM-144-58 (2010 3 ). Greg Stitt and Frank Vahid:  "Binary Synthesis,"  ACM [3] Trans. Design Automation of Electronic Systems, vol. 12, no. 3, article 34 (Aug 2007). Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, [4] Ahmed Kammoona, Jason Anderson, Stephen Brown, and Tomasz Czajkowsk: "LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems," in Proc 19th ACM/SIGDA International Symposium on Field Pro- grammable Gate Arrays, pp. 33–36 (2011). Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki [5] Takada, and Katsuya Ishii:  "Behavioral Synthesis of Double-Precision Floating-Point Adders with Function- Level Transformations:  A Case Study," in Proc Inter- national Conference on Embedded Software and Systems (ICESS), pp. 261–270 (May 2007). [6] : " 9 ). — 6 —