13.2
A 1.8V 30nJ Adaptive Program-Voltage (20V)
Generator for 3D-Integrated NAND Flash SSD
Koichi Ishida', Tadashi Yasufuku', Shinji Miyamoto², Hiroto Nakai², Makoto Takamiya', Takayasu Sakurai', Ken Takeuchi' ¹University of Tokyo, Tokyo, Japan ²Toshiba, Yokohama, Japan Decreasing power consumption is the key design issue of SSDs. A typical SSD consists of more than 16 NAND Flash memories, DRAMs and a NAND con¬ troller. Since the NAND write performance is 10MB/s [1,2], to raise the write speed of SSD to the level of HDD, 100MB/s, 8 or more NAND chips in SSD are simultaneously programmed. As the feature size decreases, the total bitline capacitance in a chip increases beyond 200nF. If 8 or more NAND chips oper¬ ate in parallel, a large current of 800mA flows to charge the bitline capacitance in a sub-30nm SSD [3]. A good strategy to decrease the power is lowering the supply voltage, V co , from 3.3 to 1.8V. Yet, at 1.8V, the power consumption of conventional charge pumps, used to generate the 20V program voltage, V FGM , drastically increases and the total power consumption of the NAND does not decrease, as shown in Fig. 13.2.1(a). The charge-pump area more than dou- bles, which increases the NAND chip area by 5 to 10%. To overcome this problem, we implement a low-power program-voltage generator (PVG) using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller. Figure 13.2.1(b) shows our 3D-integrated SSD. NAND chips, DRAM, a NAND controller and the PVG are integrated with SiP. The PVG consists of an induc- tor in an interposer, the high-voltage MOS (HVMOS) and the AFD controller. An inductor is available with no area penalty by using wiring in the interposer connecting dice. The die size of the NAND decreases by 5 to 10% because no charge pump is needed. The HVMOS is fabricated with a mature NAND process and its area is just 15% of the conventional charge pump. Since the die size of the AFD controller is 0.188mm² with a 0.18μm CMOS process, it can be integrated in a NAND controller with a negligible area increase. A PVG using a boost converter was reported for a NOR flash memory [4]. A comparison between the PVG for a NOR flash memory and for a NAND flash memory is summarized in Fig. 13.2.2(a). In a NOR flash memory, the load of the PVG is resistive. The PVG continuously supplies a load current of 20mA at an output voltage of 5V. With a resistive load and a low output voltage, a con- ventional PWM is employed [4]. In a NAND flash memory, the load is capaci- tive and the output voltage, V rgm, is 20V. During program, V rgm is applied to the wordline and a DC load current of 20μA flows. Also, a PVG for a NAND Flash memory should support on and off modes to save power. In this condi- tion both switching frequency and duty cycle must be dynamically optimized and the conventional PWM of changing only the duty cycle cannot be used. To identify the most power-efficient frequency and duty cycle, an input supply current, I co , is measured with our PVG. As shown in Fig. 13.2.2(b), each V egM has a different optimal frequency and duty cycle that minimizes l oo . In other words, the power efficiency is a function of V PGM , the switching frequency and a duty cycle, since the PVG operates in a discontinuous mode with a capacitive load. With a bit-by-bit program-verify scheme, in each program cycle, V PGM is incremented by 0.5V from 15 to 25V [5]. For each V PGM , the our AFD controller adaptively manages the switching frequency and the duty cycle simultaneous- ly so that the energy loss is minimized. Figure 13.2.3 shows the PVG with the AFD controller. V FGM is monitored with three comparators and the control logic selects the proper switching frequen¬ cy and duty cycle from the registers, Reg. L , Reg. M , and Reg. H . These registers store a table of the frequency and duty cycle that minimize both the power and the output-voltage fluctuation. A digitally controlled oscillator (DCO) is depict- ed in Fig. 13.2.4. The DCO consists of current-reference circuits and a couple of capacitor arrays. The DCO enables the clock shape to be determined only by the resistor and the capacitor, since the reference current I ref is copied to the node V capa and V cape with a current mirror [6]. The frequency and the duty cycle are robust against V co fluctuation, global transistor V r variation and tem- perature variation. The switching times of the DCO, T on = R-C A1-An, and Toff = R·C B1 . Bn . Since Ca1- sn and C B1- sn are independently selected according to the data in the registers, Ton and Ton are independently controlled. To suppress the V rgm fluctuation, the AFD controller dynamically changes the frequency and the duty cycle in three steps, as shown in Fig. 13.2.5. In the first step, a power-efficient lower frequency is chosen. The AFD controller outputs pulses with the switching frequency and duty cycle, f L and D L , determined by Reg.L. V FGM rises coarsely and rapidly until V FGM reaches V FEFL . With fL and DL, the voltage increment for each pulse is 5V. The frequency becomes higher in the second and the third steps. In the second step, the AFD controller changes the switching pulse from frequency and duty cycle f t and D L to f M and D M as determined by Reg. M . Finally, the AFD controller finely raises V FGM With f H and DH toward the target voltage. When VPGM reaches the target voltage, the AFD controller stops switching pulses to save power. As a result, the PVG raises V FGM more than 3× faster than the conventional charge pump with minimum power. V PGM is precisely controlled with less than 0.3V fluctuation, which enables a tight memory-cell V – distribution. Key features of this work and experimental results are summarized in Fig. 13.2.6. Figure 13.2.7 shows the micrograph of the breadboard model of the SSD consisting of the HVMOS chip (0.35 × 0.50mm²), the AFD controller chip (0.67 × 0.28mm²), a 270nH 0.5Ω inductor in an interposer (5 × 5mm²), and a 56nm 16Gb NAND Flash memory chip. The measured waveforms during the program of a 56nm 16Gb NAND flash memory with the PVG are shown in Fig.13.2.6. When a write command inputs to the NAND, the ready/busy signal turns to low and the NAND goes into the busy state. The program voltage is supplied from the PVG and the program pulse is applied to the memory cells. Then, the verify-read detects that all memory cells are successfully programmed and the ready/busy-signal returns to high. The measured power consumption of the PVG is 30nJ, which is 12% of the conventional charge pump. Measured rising time of the PVG is 0.92μs (at V op of 1.8V and V FGM of 15V), while that of the charge pump is 3.45μs. As the rising time of the V PGM decreases by 2.53μs, the program pulse width is shortened by 2.53μs. As a result, the total program time of a NAND flash memory, a sum of the program pulse width and the verify-read time, is 7.8% shorter than the conventional 1.8V NAND Flash memory. The area of the HVMOS chip is 15% of the charge pump without a control circuit or an oscil- lator. By decreasing V co from 3.3V to 1.8V, the total power consumption of a NAND flash memory decreases by 68%, as shown in Fig. 13.2.1(a). Acknowledgements: The authors appreciate S. Ohshima, T. Hara, Y. Watanabe, T. Futatsuyama, G. Iwasaki and Toshiba NAND team for their support and chip fabrication. References: [1] K. Takeuchi, Y. Kameda, S. Fujimura, et al., "A 56nm CMOS 99mm² 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput," ISSCC Dig. Tech. Papers, pp. 144-145, Feb. 2006. [2] K. Kanda, M. Koyanagi, T. Yamamura, et. al., "A 120mm² 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 430-431, Feb. 2008. [3] K. Takeuchi, "Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30nm Low-Power High-Speed Solid-State Drives (SSD)," Symp VLSI Circuits , pp. 124-125, Jun. 2008. [4] R. Sundaram, J. Javanifard, P. Walimbe, et al., "A 128Mb NOR Flash Memory with 3MB/s Program Time and Low-Power Write Using an In-Package Inductor Charge- Pump," ISSCC Dig. Tech. Papers, pp. 50-51, Feb. 2005. [5] K-D. Suh, B-H. Suh, Y-H. Lim, et. al, "A 3.3 V 32 Mb NAND flash memory with incre- mental step pulse programming scheme," ISSCC Dig. Tech. Papers, pp. 128-129, Feb. 1995. [6] T. Tanzawa, T. Tanaka, "A Stable Programming Pulse Generator for Single Power Supply Flash Memories," IEEE J. Solid-State Circuits , vol. 32, no. 6, pp. 845-851, Jun. 1997. (b) structure of the proposed 3D-integrated SSD. Figure 13.2.3: Circuit diagram of the adaptive high-voltage generator. Figure 13.2.5: Simulation result.
Figure 13.2.6: Experimental results and key features. Figure 13.2.2: (a) Comparison of the conventional boost converter [4] and this work 13 Figure 13.2.7: Die micrograph.