I. Introduction
NINCE THE first 1-Kbit dRAM [1] was introduced in the )semiconductor market, four times greater integration has been achieved every three years in the past decade. This inte¬ gration has maintained its advantage in higher density and lower cost over other types of memories. As a result, the pres¬ ent 64K dRAM has now reached maturity in production, and is being followed by the 256K dRAM development. This rapid evolution has been achieved mainly by the progresses in finer photolithography resulting in doubled packing density and cir¬ cuit cleverness such as one-device cell [2] and address multi- plexing. Although these progresses facilitate small cheap pack- aging, the chip size of the present 256K's approaches the maximum cavity size of the standard 16-pin dual-in-line pack- age, as shown in Fig. 1. Therefore, forthcoming 1 Mbit dRAM will require an accelerated reduction of feature size leading to four times denser packing in order to maintain its great advan¬ tage over other memories. Along with this greater integration, memory cells have also been reduced in size resulting in the decreases in capacitance area S and maximum storable charge, as shown in Fig. 2. However, storage capacitor value C 5 has to be large enough to have sufficient S/N ratio [3] from the manufacturability and Fig. 1. Chip size increase in MOS dRAM's over commercially available chips provided by various manufacturers. About 1.4 times chip-size increase has been observed for four times greater integration of dRAM. Consequently, the chip size will soon meet a maximum cav¬ ity size of a 16-pin dual-in-line package. the reliability standpoints. Regarding this S/N problem, a maximum storable charge Qms is preferred to be greater than 200 fC. In addition to the S/N problem, it is also better to be greater than 200 fC since an alpha particle [4] can produce hazardous electrons of greater than 200 fC at a typical maxi¬ mum particle energy of 5 MeV. To supply large Cs value, the storage capacitor insulator has been decreasing in thickness with C c area reduction. However, this approach towards thinner insulator will soon meet its limit in the forthcoming 1-MBit dRAM in which chip size is kept below 50 mm² unless extremely tough and thin and/or high-permeability insulator is realized. An ordinary memory cell layout offers a Cs area of 5 to 10 pm 2 . To pro- vide 60 fF Cs, which facilitates highly stable dRAM operation [3], the SiO2 must be thinner than 6 nm. Applying 5 V across the 6 nm SiO2 causes almost 10 MV/cm electric field. This immediately leads to catastrophic breakdown. Thus from the reliability and manufacturability standpoints, it is desirable that the field across the SiO2 is kept to be less than about 2 MV/cm.
II.  CCC CONCEPT
To overcome this dilemma between greater integration and large Cs value implementation, there is one approach which provides enlargement of the capacitor region without increas¬ ing cell area. In other words, a vertically formed capacitor [5] , [6] will solve the problem. As one of the vertical capaci- tor application, a breakthrough cell, called "CCC" (Corrugated Capacitor Cell), has been newly proposed [7]. A bird's eye view of the CCC is shown in Fig. 3. This cell is characterized by a capacitor region consisting of an etched moat which ex- tends into the substrate. In this CCC, Cs value can increase independently of cell size since moat depth can increase also independently. Storage capacitance values obtained by a static capacitance measurement are plotted in Fig. 4 for 4 X 8 and 3 X 7 pm 2 cell sizes. Almost linear increase in Cs value is obtained with increasing moat depth. If the moat stretches straightly into substrate, Cs is defined as Cp + CiLpmd, where Cp, Ci, Lpm, and d are capacitance of horizontal portion, insulator capaci¬ tance per unit area, perimeter length of horizontal shape of moat, and moat depth, respectively. Therefore, a gradient of the curve shown in Fig. 4 is CiLpm • A difference between two curves is caused by a difference in horizontal shape of moat, not in cell size. The 3 X 7 pm² cell has a rectangular-type hor- izontal moat pattern which measures 1.0 pm by 2.6 pm. As is shown in Fig. 4, C5 values for 3 X 7 pm 2 cells with and with- out a 4-pm deep moat are 60 and 8 fF, respectively, a 7.5 times Cs increase has been obtained. In other words, CCC can offer a very high storage capacitance with both small cell size and moderate insulator thickness.
III. PROCESS AND CAPACITOR PERFORMANCE
A.  Process Sequence
A fundamental process sequence to realize CCC structure is shown in Fig. 5. This is as follows: Step-I. A triple layered insulator of CVD PSG/CVD Si3 N 4 / thermal SiO2 as an etching mask is provided to make deep moats into the Si substrate. Photoresist patterning of around 1 μm size is required for lithography. Step-II. The Si substrate is etched with CCl 4 gas subsequent to an etching of the triple layer with CF4 + H2 gas.P A moderate selectivity of around 8 is realized for Si to SiO2 with CCl4 gas. Slight wet etching of dry etched Si surface is subsequently added to remove slightly damaged and/or contaminated moat surface. Step-III. A CVD Si 3 N 4 film is deposited using LPCVD sub¬ sequent to thin bottom-oxide formation. A top layer of SiO2 is also formed by thermal oxidation of Si3N4 result¬ ing in extinction of possible pin holes and a protection film formation against dry etching of polysilicon plate which will be overlayed later on this capacitor insulator. Resultant triple layer of capacitor insulator is equivalent to 15 nm SiO 2 in thickness. Step-IV. A first polysilicon deposition is performed to form polysilicon plate and is subsequently doped with phos¬ phorus using POCl 3 gas. Then the second polysilicon is deposited on slightly oxidized first polysilicon surface. The second polysilicon deposition is used only to fill up remained umoat. Then subsequent thermal oxidation makes intermediate insulator on the polysilicon plate. As a result, the wedge-shaped filled second-polysilicon is elec¬ trically floating, however, no harmful effect has not been found. Thus these processes are easily applied to the conven- tional double polysilicon gate technology [8], [9] with high compatibility.
B.  Capacitor Performance
Capacitance-voltage (C-V) curves of capacitors with and without 3600 individual moats are shown in Fig. 6. There has been no significant difference with respect to interface state density and flat-band voltage VFB. Furthermore, transient pulsed capacitance (C-t) and microwave minority-carrier- lifetime measurements have given no notable difference either. They have shown saturation time tr of around 10 min and 80- 150 ps, respectively, at room temperature. These values are on almost the same level with those in the conventional processes. In this study, the triple layered capacitor insulator of SiO2/ Si3N4/SiO2 is found far better than single oxide layer as far as infant mortality and short-term breakdown field strength are concerned. Breakdown voltage distributions are shown in Fig. 7 for the capacitors with and without 3600 moats. Slightly scattered distribution for cells with moats may originate not from moats themselves but from increased capacitor area since the breakdown voltage is defined as an applied gate voltage which induces 10 nA across the capacitor insulator for both capacitors in spite of the different area. An influence of keen edges of the moat on breakdown characteristics has not been found for the triple-layered insulator. On the other hand, 20-nm-thick single-oxide insulator results in breakdown volt- ages of 12 and 20 V for capacitors with and without 3600 moats, respectively. Keen edges obviously degrade the break- down field strength of the single SiO2 capacitor insulator. Further investigation will be made on long-term reliability for CCC capacitors. A TEM cross section of realized two CCC's is shown in Fig. 8 Grains of polysilicon layer are clearly shown in the micro- graph. The delineated moat shape is found to be sensitive to the dry etching environment. An optimum etching condition has realized the moat shape shown in Fig. 8.
500 IV. MEMORY OPERATION
A memory operation has been clarified with a unit array of 32Kbit. The array is composed of 256 folded-bit lines [10] having 128 bit of 4 X 8 pm 2 CCC with 2.5-pm deep moat, as shown in Fig. 9. The cell structure has already been shown in Fig. 3. To compare a difference in electrical performance of the cells accurately, two types of the cell with and without moat have been put into together in the same array. As Cs values for the cells with and without moat are 45 and 18 fF, respectively, a 2.5 times Cs increase has been obtained for the cell with moat in this sample. The same amount of Cs in¬ crease has been found also in dRAM's operation with identical CCC's. A storage capacitance Cg and a bit line capacitance CD are 45 and 400 fF, respectively, resulting in Cs/CD value of 0.11. Output signal waveforms are shown in Fig. 10 for the cells with and without moat. A signal voltage of 200 mV has been realized with the CCC arrangement at 5-V power supply. An obtained S/N ratio is large enough to get very stable dRAM operation and high immunity to alpha particles for megabit dRAM's.
V. Limiting Factor Consideration
One of the biggest obstacle hindering closer packing of CCC's has been found to be a punchthrough current from one moat to the adjacent one, causing a loss of stored charge. An interference effect of adjacent cells are discussed in detail in terms of the leakage current between them.
A. Experimental Results
In an actual memory array, as shown in Fig. 11, some leak- age currents have been observed. One is designated by I LMM which flows through one moat to the adjacent one. The other is designated by I LMB which flows through one moat to n + - diffused layer connected to Al bit line. As for dRAM operation, a leakage current of 10-13 A causes notable information loss of stored charges during one refresh cycle. A drain and/or plate voltage inducing 10~ 1 3 A is de¬ fined as VLTH . (Leakage current itself will be shown later in Figs. 15 and 16.) A setup for the leakage current measure- ment is illustrated in Fig. 12. This VLTH has been affected by moat to moat spacing WM - M and moat to bit line (n*-region) spacing WM - B as shown in Fig. 13. In this paper, WM - M and WM - B are actual dimensions after devices are fabricated, but, a field oxide width WF is a nominal one on photomask. Actual WF is about 0.4 pm greater than the nominal one due to bird's beak. In Fig. 13, it is clearly shown that the moat to moat leakage current ILMM is dominant compared to ILMB. The reason is speculated to be due to a punchthrough phenomenon in deeper portion of the substrate, as will be discussed later. Based on the experimental results, two leakage current paths are considered. One is a path for current, denoted by I L F , which flows just underneath the field oxide, and the other, de- noted by I L B , is a punchthrough current flowing through deeper portion of the substrate. As is shown in Fig. 14, a VLTH becomes greater than 10 V at -3 V BBB and this 10 V V LTH is sufficiently high compared to 5-V operation. In addi- tion, ILB becomes dominant compared to ILF in WF region of greater than around 1 pm. No field oxide region has been formed in WF region of less than 0.6 pm due to a practical resolution limit of 10 to 1 Reduction Projection Aligner. The reason why a VLTH of around 2 V has been obtained for WF below 0.6 μm is speculated to be due to boron field implant leakage. All of WF values are 1.2 pm for CCC's discussed be¬ low, unless otherwise noted. The leakage current has become appreciable for WM-M of 1.6 pm, as shown in the next two figures, Figs. 15 and 16, for 3 X 7 pm 2 CCC of which layout has already been illustrated in Fig. 11. A moat width WM is 2.6 pm unless otherwise noted. In these figures, there are two distinguishable leakage current One is steep line and the other is plateau region. regimes. These characteristics are very similar to a common-gate(plate) MOS transistor of which sources and drains are connected in Both side transistors have thin gate insulator(20-nm- series. thick triple-layered insulator) and relatively long channels along the moat wall. A center transistor has a thick gate insu- lator(around 500-nm-thick field oxide) and a high channel¬ dose(field channel stopper) and very deep source and drain simulated to two adjacent moats. Consequently, extremely strong dependence of the leakage current on moat-to-moat spacing is observed, as shown in Fig. 17. In case of 10 Ω - cm substrate, a WM - M has to be greater than 1.8 pm at VBB of -3 V. As is expected in these considerations, leakage current for WM - M of 1.8 pm has been found negligible at adequate condi- tions such as at 6 V VDD, 6 V VP, -3 V VBB, and room tem- perature, as shown in Fig. 18. Some kink phenomenon is ob¬ served and is reproducible over various samples, however, this is not clarified yet. Therefore, the leakage current is of no im- portance to be taken into consideration when the moat to moat spacing WM - M exceeds around 2 pm in case of 10 Ω • cm. Regarding these leakage current characteristics cited above, slight disagreement has been found in different patterns as shown in Figs. 13 and 15. The reason is as follows: WM-M is defined as the shortest distance between two adjacent moats. The leakage current, however, flows through a deeper portion of the moats, as will be discussed later. Therefore, the current strongly depends on a wall shape of the moat. As a result, such disagreement is caused for the leakage current characteris- tics of different patterns. In addition to the moat-to-moat spacing WM - M , a moat width WM also strongly affects the leakage current between adjacent moats. Increasing WM leads to a hyper-linear in- crease in the leakage current. This effect will be discussed in Section VI.
B.  Two-Dimensional Device Simulation
To outline the leakage current qualitatively, two-dimensional device simulation using CADDET [11] has been carried out. To simplify the analyses, a MOSFET has simulated actual CCC structure. A difference between the actual and the simulated characteristics has been found to be of considerable impor- tance, as discussed later. However, the MOSFET which has deep source and drain and thick gate oxide (field oxide) has been used to simulate the actual structure, as shown in Fig. 19, because complicated device structures such as CCC, previously shown in Fig. 13, cannot be analyzed yet at present. The deep source represents a "low" level signal which means maximum electron charges are stored in the inversion layer. While, the deep drain denotes a "high" level signal which forms the deep depletion layer containing no electron charge. Calculated drain current (leakage current) ID versus drain voltage VD curves are shown in Fig. 20. A broken line drawn also in the same figure is an experimental result for 1.6 pm Wm - m . There surely exists a significant difference. Accord¬ ing to the simulation, a relation between WM - M and impurity concentration of the substrate NA with respect to various VLTH is obtained as shown in Fig. 21. With increasing NA, VLTH also increases to some extent. Therefore, the use of lower resistivity substrate leads to reduced WM - M , namely, denser packing of CCC's. In fact, the leakage current has been found negligible for a 4-2 • cm substrate even with a WM-M of 1.6 μm for which it has been appreciable for 10 Ω · cm, as shown in Figs. 15 and 16. But it also causes some detrimental effects on circuit performances, such as increased back bias ef¬ fect and increased parasitic junction capacitance.
VI. DISCUSSION
Through the experimental investigation, the leakage current between adjacent moats has been found of considerable im- portance. Even if the simulation clarifies qualitative behavior of the leakage current, there still exists a poor coincidence be- tween the simulation and the experimental results. For in¬ stance, it has been found that a VLTH is less than 2 V at WM - M of 1.8 pm for 10-2 · cm substrate. This value of 1.8 pm is significantly different from the experimental results shown in Figs. 17 and 18. To explain the difference, it is thus speculated as follows. The simulation is, of course, two-dimensional numerical calcu- lation which neglects an influence of bulk perpendicular to the cross section shown in Figs. 12 and 19. However, the poten¬ tial distribution in the bulk along a direction perpendicular to the cross section has notable effect on the potential minimum where the leakage current flows. Schematic view of the potential is shown in Fig. 22. If the potential minimum point is called "saddle" point X sai, a po- tential Psat at Xsat has great influence on the leakage carrier (electron) which flows riding across the saddle point Xsqi, be- cause the carrier density at X sat reveals Boltzmann's distribu- tion and shows exponential like behavior. Therefore, when source and drain (moat) width WM decreases, saddle potential Psai is raised by an influence of the substrate potential (VBB of -3 V) resulting in exponential current decrease. These are present speculation to explain the poor coincidence between the simulation and the experimental results. In this sense, three-dimensional device simulation is needed to analyze the experimental quantitatively. These behaviors of the leakage current discussed here imply constant current flow from one moat to the adjacent one. However, the leakage current in an actual dRAM operation is not constant since an amount of stored charges are limited. Then, a potential of one moat increases and that of the other decreases following to the charge transfer. This behavior is very similar to that of the charge-coupled device (CCD). Therefore, the leakage current analyses discussed in this paper can explain very early stage of the leakage current flow. Dy¬ namic charge transfer behavior will be taken into future consideration.
VI. CONCLUSIONS
Based on the one-device cell concept a vertically structured dRAM cell named Corrugated Capacitor Cell (CCC) has been successfully developed. Since a storage capacitor is formed in an etched moat, almost linear increase in Cs value has been achieved with increasing moat depth. A typical Cs value of 60 fF has been obtained with 3.X 7 pm² cell having a 4-pm deep moat and a capacitor insulator equivalent to 15-nm SiO2 in thickness. A C5 increase has also been clarified in 32 Kbit dRAM operation with a folded-bit line arrangement having 128 bit cells. One of the biggest obstacles hindering closer packing of CCC's has been found to be a punchthrough current from one moat to the adjacent one, causing a loss of stored charge. As the results of experiments, it is found that moat-to-moat spac¬ ings of greater than 2 pm are large enough to suppress hazard¬ ous punchthrough current in case of 10-2 · cm substrate and 3 X 7 μm² memory cell. Based on the experimental and analytical investigation of CCC, further integration of CCC is under development. A typical sample is shown in Fig. 23. This SEM micrograph shows a cross section of a memory array consisting of 3 X 7 µm 2 CCC's with 4-µm deep moats. An area layout of the ar- ray has already been shown in Fig. 11. A Cs value of 60 fF and a maximum storable charges of around 250 fC can be ex- pected for this CCC array. This array has been successfully operated resulting in a signal of 250 mV. This CCC will be very promising for forthcoming 1-Mbit dRAM and beyond because of its very large storage capaci- tance in small cell size with moderate insulator thickness from manufacturability and reliability standpoints. The future ap¬ plication of the CCC seems to be limited by the optical lithog- raphy, not by the device concept itself. On the basis of the CCC concept, further integration of denser packing has been under development.
Acknowledgment
The authors wish to express their thanks to Dr. K. Sato and Dr. M. Kubo for their constant encouragement which made this work possible. They are also grateful to Dr. K. Yagi and Dr. Y. Wada and R. Hori and Y. Kawamoto for their technical assistance in a new memory cell implementation and S. Aoki for TEM observation.