A Study on Multimedia Processing Library for DDMP 1030320 14 DDMP DDMP(Data-Driven Multimedia Processor) DDMP DADT(DDMP Application Designer's Toolkit)
Masaaki Yamaoka With growth of micro-fabrication technology, data network system for ubiquitous computing is within reach. In such a system, multimedia-oriented processing program becomes important and very huge, the productivity of software would be unmanageable. In order to improve the production efficiency, high-level description of software is key.With DFG (Data-Flow Graph), the specification can be converted into object code directly, and the comprehension for module interface can be clearly cognized by its diagramatic representation, thus high-parallel execution subtended in multimedia processing is naturally described. Moreover DFG can be executed by DDMP (Data- Driven Multimedia Processor) with dynamic data-driven scheme.  DDMP, which is realizes high-parallel processing by its self-timed pipelines, is hopeful architecture for multimedia processing.However DADT (DDMP Application Designer's Toolkit), current software development tool, is designed to target assembler-level description, thus the development of application systems in a high level is extremely difficult. As one sphere of the study on high-level development environment, higher-level description of software using library is studied. In this paper, a multimedia processing library for DDMP is developed based on the existing multimedia instruction sets of Intel's IA-32. key words dataflow graph,library,multimedia processing,high-level development environment
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1 . . ISDN(Integrated Services Digital Network) ADSL(Asymmetric  Digital  Subscriber  Line) CPU CPU MMX (MultiMedia eXtension) x86 CPU VIS (Visual SSE(Streaming SIMD Extensions)/SSE2 SPARC CPU Instruction Set)  PA-RISC CPU MAX (Multimedia Acceleration eXtensions) MIPS CPU MDMX (Digital Media eXtension) DDMP:DataDriven Multimedia Pro- [1] cessor DDMP DADT DDMP Application Designer's Toolkit DDMP DDMP 2 DDMP 3 DDMP 4 5 2 2.1 DDMP
DDMP
2.2
2.2.1 (DDMP) ( 2.1 ● M MM ● MM     M FP ● FP Branch CPS MM   :Matching Memory(待ち合わせメモリ)
FP   :Functional Processing Unit(演算部) CPS  :Cache Program Storage(プログラム記憶部:Flow Merging Module(合流部) M :Flow Diverting Module(分岐部) D 2.1 ● CPS ● D D PE (
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[[6]次ステージが占められている2.2.2 2.3
2.3
DADT
DADT(DDMP Application Designer's Toolkit) GUI 1. FED(Flowgraph EDitor) DFG(Data Flow Graph) DFG FED 2. Validator FED DFG 2.3 DADT 3.  Allocator FED DFG PE PE 4. Estimator DFG( ) nPE DDMP 5. Assembler DFG 6. Simulator Assembler DDMP 1. FED DFG Validator DFG 2. Allocator,Estimator,Assembler DDMP Simulator 3. DDMP 4. Simulator GUI DDMP 2.4 5. Simu- lator GUI 2.4 1. DDMP 2. 2.5 DDMP DDMP 3 3.1 DDMP 3.2 MMX 3.2.1 SIMD 1 MMX SIMD(Single Instruction Multiple Data) [5] DSP . SIMD 3.1 16 4 8 8 MMX
3.1 SIMD 3.2.2 MMX IA 32 MMX . . . . . . . ● EMMS
1
0
EMMS MMX 3.2
3.2 MMX 3.2.3 MMX 3 . . . 16 7FFFH 8000H 16 FFFFH 000H
SSE
3.3
SSE2
SSE D D SSE 128 ( ?? ) 128ビットパックド単精度浮動小数点数3.3 128 SSE 4 . ● 64 SIMD . . . . . . . . 4 32
SIMD
3.4 ( ) 3.4 3 3.5 ( ) 3.5 SSE SSE SSE SSE2 3.3 SSE AND NOT   OR XOR SSE 0     1 SSE SSE SIMD 64 64 MXCSR MXCSR SSE2 3D 2 D 3.6 . SSE2 4 . 3.6 SSE2 ● 64 128 SIMD ● 128 . . . . . . . 128ビットパックド倍精度浮動小数点数128ビットパックドバイト整数128ビットパックドワード整数128ビットパックド・ダブルワード整数128ビットパックド・クワッドワード整数32 4 SIMD (
3 (
) SSE2 SSE2 3.7 SSE2 AND   AND NOT   OR XOR 0 SSE2 1 2 SSE2 SSE2 . 3.4 . .
SIMD
64 64 PADDB MMX SSE2 128 SIMD MFENSE LFENSE LFENSE MFENSE LFENSE SFENSE PAUSE 3.4 IA 32 MMX SSE SSE2 4 4.1 FIS   DADT 4.2 FIS DDMP FIS(Fundamental Instruction Set) FIS FIS 4.3 MMX FIS DADT MMX FIS 32 4.4 . . . . ( 4.5 DDMP
DDMP 4.1     3 DDMP A 174 MMX FIS 37 4.6 MMX FIS   DADT
1
5 5.1 MMX 5.2 FFT (Fast Fourier Transform:FFT[3]) Fourier Transform:DFT) FFT (Discrete 56 64 [4] DADT MMX FIS DADT 8 5.1 3 . 5.1 (N 8) . . FFT 64 FFT MMX FFT
5.3
5.1 5.1 FFT 70 55
5.4 FFT
FFT FIS DADT FFT DDMP 5.5 DADT MMX FIS DADT 6 DDMP DDMP FIS FIS FFT
DADT FIS DADT . . . 5 MMX MMX
FFT MMX　SSE SSE2 FFT 4 SIMD(Single Instruction Multiple Data) MIMD(Multiple Instruction Multiple Data) . . FFT MMX
CPU SPARC VIS (Visual Instruction Set)   PA-RISC CPU MAX (Multimedia Acceleration CPU MDMX (Digital Media eXtension) eXtensions)   MIPS [1] H. Terada, et al.," DDMP's: self-timed super-pipelined data-driven multimedia processors,"  Proc. of IEEE, 87(2), 282-296, 1999. [2] , " FIS ," 13 [3] .. , April 1996. [4] , " ," , September 1994. [5] ,“ IA-32 ." A
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