GD25WD10C/05C GD25WD10C/05C DATASHEET Standard and Dual Serial Flash GD25WD10C/05C

1. FEATURES
◆ 1M/512K-bit Serial Flash -128K/64K-byte -256 bytes per programmable page ◆  Standard, Dual Output -Standard SPI: SCLK, CS#, SI, SO, WP# -Dual Output: SCLK, CS#, IO0, O1, WP# ◆ Clock Frequency -100MHz for fast read on 3.0~3.6V power supply ◆ Dual Output Data Transfer up to 160Mbits/s -70MHz for fast read on 2.1~3.0V power supply Dual Output Data Transfer up to 120Mbits/s ◆ -50MHz for fast read on 1.65~2.1V power supply ◆ Dual Output Data Transfer up to 80Mbits/s ◆ Software/Hardware Write Protection -Write protect all/portion of memory via software -Enable/Disable protection with WP# Pin ◆ Minimum 100,000 Program/Erase Cycles ◆ Data Retention -20-year data retention typical ◆ Fast Program/Erase Speed -Page Program time: 1.6ms typical -Sector Erase time: 150ms typical -Block Erase time: 0.5/0.8s typical -Chip Erase time: 1.5/0.8s typical ♦ Flexible Architecture -Uniform Sector of 4K-byte -Uniform Block of 32/64K-byte ◆ Low Power Consumption -0.1uA typical standby current -0.1uA typical power down current ◆ Advanced Security Features -128-bit Unique ID for each device ◆  Single Power Supply Voltage -Full voltage range: 1.65~3.6V ◆ Package option -SOP8 150mil -SOP8 208mil -TSSOP8 173mil -USON8 3x2mm -USON8 1.5x1.5mm -USON6 1.2x1.2mm

2. GENERAL DESCRIPTION
The GD25WD10C/05C (1M/512K-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual Output: Serial Clock, Chip Select, Serial Data I/OO (SI), O1 (SO). The Dual Output data is transferred with maximum speed of 160Mbits/s. CONNECTION DIAGRAM AND PIN DESCRIPTION
Note: CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.
GD25WD10C/05C 6 - LEAD USON
Standard and Dual Serial Flash BLOCK DIAGRAM GD25WD10C/05C
UNIFORM BLOCK SECTOR ARCHITECTURE
GD25WD05C 64K Bytes Block Sector Architecture

4.  DEVICE OPERATION
SPI Mode Standard SPI The GD25WD10C/05C features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25WD10C/05C supports Dual Output operation when using the “Dual Output Fast Read” (3BH) commands. These commands allow data to be transferred to o r from the device at twice the rate of the standard SPI. When using the Dual Output command the SI and SO pins become bidirectional I/O pins: IO0 and O1.

5.  DATA PROTECTION
◆ The GD25WD10C/05C provides the following data protection methods: Write Enable (WREN) command: The WREN command is s set the Write Enable Latch bit (WEL). The WEL bit will reset to 0 in the following situations: -Power-Up -Write Disable (WRDI) -Write Status Register (WRSR) -Page Program (PP) ◆ -Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) Software Protection Mode: The Block Protect (BP2, BP1, BP0) bits define the section of the protected memory area which is read-only and unalterable. ◆ ◆ Hardware Protection Mode: WP# goes low to protect the BP0~BP2 bits and SRP bits. Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down Mode command. Write Inhibit Voltage (VWI): Device would reset automatically when VCC is below a certain threshold VWI. ◆
Table1(b) GD25WD05C Protected area size
The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress. when WIP bit is cleared to 0, it means the device is not in program/erase/write status register progress. The default value of WIP is 0. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase command is accepted. The default value of WEL is 0. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table1).becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the Block Protect (BP2, BP1, BP0) bits are all 0. The default value of BP2:0 are 0s. SRP bit The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device to the Hardware Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status Register(SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not execution. The default value of SRP is 0.
All commands, addresses and data are shifted in and out of the device by the host system, with the most significant bit first. On the first rising edge of SCLK after CS# is driven low, the one-byte command code must be shifted into the device, with the most significant bit first on SI, and each bit being latched on the rising edges of SCLK. See Table2, every command sequence starts with a one-byte command code. Depending on the command, this might be followed by address bytes, or data bytes, or dummy bytes. CS# must be driven high after the last bit of the command sequence has been completed. For the command of Read, Fast Read, Read Status Register or Release from Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can be driven high after any bit of the data- out sequence is being shifted out. For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, which means the clock pulse number should be an exact multiple of eight. Otherwise the command is rejected to executed. Especially for Page Program command, if at any time the input end is not a completed byte, nothing will be written into the memory array, neither would WEL bit be reset.
NOTE: 1. Dual Output data IO0 = (D6, D4, D2, D0) O1 = (D7, D5, D3, D1) Standard and Dual Serial Flash GD25WD10C/05C 7.1.  TABLE OF ID DEFINATION:
GD25WD05C

7.2.  Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS# goes high. Figure1. Write Enable Sequence Diagram
7.3.  Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase commands. The Write Disable command sequence: CS# goes low→Sending the Write Disable command →CS# goes high. Figure2. Write Disable Sequence Diagram
7.4.  Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is also possible to read the Status Register continuously. For command code "05H", the SO will output Status Register bits S7~S0. Figure3. Read Status Register Sequence Diagram
7.5.  Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. A Write Enable (WREN) instruction must be executed previously to set the Write Enable Latch (WEL) bit, before it can be accepted. The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (DI). The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. Otherwise, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (the duration is tW) is initiated. While the Write Status Register cycle is in progress, reading Status Register to check the Write In Progress (WIP) bit is achievable. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and turn to 0 on the completion of the Write Status Register. When the cycle is completed, the Write Enable Latch (WEL) is reset to 0. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, which are utilized to define the size of the read-only area. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once enter into the Hardware Protected Mode (HPM). 7.6.  Read Data Bytes (READ) (03H) The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency f R , on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
7.7.  Read Data Bytes at Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, and each bit being latched-in on the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, and each bit being shifted out, at a Max frequency fc, on the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure6. Read Data Bytes at Higher Speed Sequence Diagram 7.8.  Dual Output Fast Read (3BH) The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed Figure7. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure7. Dual Output Fast Read Sequence Diagram
7.9.  Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program command. The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three address bytes and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7- A0) are all zero). CS# must be driven low for the entire duration of the sequence. The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address on SI → at least 1 byte data on SI → CS# goes high. The command sequence is shown in Figure8. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program (PP) command is not executed. As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is t Þ ) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) command is not executed when it is applied to a page protected by the Block Protect (BP2, BP1, BP0). http://www.elm-tech.com - Rev.1.5 17 Figure8. Page Program Sequence Diagram
7.10.  Sector Erase (SE) (20H)
The Sector Erase (SE) command is for erasing the all data of the specific sector. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The Sector Erase (SE) command is entered by driving CS# low, followed by the command code, and 3-address byte on SI. Any address inside the sector is a valid address for the Sector Erase (SE) command. CS# must be driven low for the entire duration of the sequence. The Sector Erase command sequence: CS# goes low → sending Sector Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure9. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tse) is initiated. While the Sector Erase cycle is in progress, the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) command applied to a sector which is protected by the Block Protect (BP2, BP1, BP0) bit (see Table1) is not executed. Figure9. Sector Erase Sequence Diagram 7.11. 32KB Block Erase (BE) (52H) The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 32KB Block Erase command sequence: CS# goes low → sending 32KB Block Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure10. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tםם) is initiated. While the Block Erase cycle is in progress, the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table1) is not executed. Figure10. 32KB Block Erase Sequence Diagram
7.12. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low → sending 64KB Block Erase command → 3-byte address on SI → CS# goes high. The command sequence is shown in Figure11. CS# must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tםם) is initiated. While the Block Erase cycle is in progress, the Status Register is accessed to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and becomes 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table1) is not executed. Standard and Dual Serial Flash Figure11. 64KB Block Erase Sequence Diagram
7.13.  Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit .The Chip Erase (CE) command is entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low for the entire duration of the sequence. The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The command sequence is shown in Figure12. CS# must be driven high after the eighth bit of the command code has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-timed Chip Erase cycle (whose duration is t ε ) is initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed if the Block Protect (BP2, BP1, BP0) bits are all 0. The Chip Erase (CE) command is not executed if any sector is under protection. Figure12. Chip Erase Sequence Diagram
7.14. Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to enter the lowest consumption mode (the Deep Power-Down Mode). Unlike deselecting the device by driving CS# high, or entering into the Standby Mode (if there is no internal cycle currently in progress), the Deep Power-Down Mode provides an extra software protection mechanism while the device is not in active use. The only access to this mode is by executing the Deep Power-Down (DP) command. Since in the Deep Power-Down mode, the device ignores all Write, Program and Erase commands. Once the device is in the Deep Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device ID (RDI) command. The Release from Deep Power-Down and Read Device ID (RDI) command releases the device from Deep Power-Down mode, also allows the Device ID of the device to be output on SO. The Deep Power-Down Mode automatically stops at Power-Down, and the device is in the Standby Mode after Power- Up. 20 Standard and Dual Serial Flash The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS# goes high. The command sequence is shown in Figure13. CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon as CS# is driven high, it requires a delay of t P before the supply current is reduced to Iccz and the Deep Power-Down Mode is entered. Any Deep Power- Down (DP) command, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
7.15. Release from Deep Power-Down / Read Device ID (ABH)
The Release from Power-Down  and  Read  Device ID command is a multi-purpose  command,  which  can  be  used  to release the device from the Power-Down state or obtain the devices electronic identification (ID) number. When used to release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting the instruction code "ABH" and driving CS# high as shown in Figure14. Release from Power-Down will take the time duration of tres1 (See AC Characteristics) before the device will resume normal operation and other command are accepted. The CS# pin must keep high during the tres1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure15. The Device ID value for the GD25WD10C/05C is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure15, except that after CS# is driven high it must remain high for a time duration of tres2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down and Read Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure14. Release Power-Down Sequence Diagram GD25WD10C/05C Figure15. Release Power-Down and Read Device ID Sequence Diagram
7.16. Read Manufacture ID/ Device ID (REMS) (90H)
The Read Manufacturer/Device ID command is an alternative to the Release from Power-Down / Device ID command that provides both the JEDEC assigned Manufacturer ID and the specific Device ID. The command is initiated by driving the CS# pin low and shifting the command code "90H" followed by a 24-bit address (A23-A0) of 00000H. After that, the Manufacturer ID and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure16. If the 24-bit address is initially set to 00001H, the Device ID will be read first.
7.17.  Read Identification (RDID) (9FH)
The Read Identification (RDID) command allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. Any Read Identification (RDID) command while an Erase or Program cycle is in progress is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) command should not be issued while the device is in Deep Power-Down Mode. The device is first selected by driving CS# low. Then, the 8-bit command code for the command is shifted in. This is 22 GD25WD10C/05C followed by the 24-bit device identification, stored in the memory. Each bit is shifted out on the falling edge of Serial Clock. The command sequence is shown in Figure17. The Read Identification (RDID) command is terminated by driving CS# high at any time during data output. When CS# is driven high, the device is in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute commands. Figure17. Read Identification ID Sequence Diagram
Read Unique ID (4BH)
7.18.
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each device. The Unique ID can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command → 3-Byte Address (00000H) →Dummy Byte→128bit Unique ID Out →CS# goes high. Standard and Dual Serial Flash

8.1.  POWER-ON TIMING

8.2.  INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1(each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0).
8.3.  ABSOLUTE MAXIMUM RATINGS

Figure20. Maximum Negative/positive Overshoot Diagram
8.4.  CAPACITANCE MEASUREMENT CONDITIONS

Maximum Positive Overshoot Waveform
Figure21. Input Test Waveform and Measurement Level Note: Input pulse rise and fall time are <5ns
1. Typical value tested at T = 25 ℃. lcc3 (>50MHz) tested at VCC = 3.3V. lcc3 (≤50MHz) tested at VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production. GD25WD10C/05C
1. Typical value tested at T = 25 ℃. Icc3 (>50MHz) tested at VCC = 3.3V. Icc3 (≤50MHz) tested at VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production. GD25WD10C/05C
1. Typical value tested at T = 25 ℃. lcc3 (>50MHz) tested at VCC = 3.3V. lcc3 (≤50MHz) tested at VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production. Standard and Dual Serial Flash GD25WD10C/05C
Note: 1. Typical values given for TA=25°C VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production.
Standard and Dual Serial Flash
Note: 1. Typical values given for TA=25°C VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production.
Standard and Dual Serial Flash Chip Erase Time (GD25WD10C/05C)
Note: 1. Typical values given for TA=25°C VCC = 1.8V. 2. Value guaranteed by design and/or characterization, not 100% tested in production. Figure22. Output Timing Standard and Dual Serial Flash GD25WD10C/05C 9. ORDERING INFORMATION Series WD: 1.65~3.6V, 4KB Uniform Sector Product Family 25: SPI NOR Flash *Please contact GigaDevice sales for automotive products. **F grade has implemented additional test flows to ensure higher product quality than I grade. GD25WD10C/05C 9.1.   Valid Part Numbers Please contact GigaDevice regional sales for the latest product selection and available form factors. Temperature Range I: Industrial (-40°C  to +85°C)
Temperature Range J: Industrial+ (-40℃  to +105℃)
GD25WD10C/05C Temperature Range E: Industrial+ (-40℃  to +125℃)
Temperature Range F: Industrial+ (-40℃  to +85℃)
Standard and Dual Serial Flash 10. PACKAGE INFORMATION 10.1. Package SOP8 150MIL
1. Both the package length and width do not include the mold flash. 2. Seating plane: Max. 0.1mm. 10.2. Package SOP8 208MIL
1. Both the package length and width do not include the mold flash. 2. Seating plane: Max. 0.1mm. 10.3. Package TSSOP8 173MIL
1. Both package length and width do not include mold flash. 2. Seating plane: Max. 0.1mm. 10.4. Package USON8 (1.5 x 1.5mm) Side View
1. The exposed metal pad area on the bottom of the package is floating. 2. Coplanarity ≪0.08mm. Package edge tolerance≪0.10mm. 3. The lead shape may be of little difference according to different package factories. These lead shapes are compatible with each other. 10.5. Package USON8 (3 x 2mm, 0.45mm thickness) Side View
Note: 1. The exposed metal pad area on the bottom of the package is floating. 2. Coplanarity ≪0.08mm. Package edge tolerance≪0.10mm. 3. The lead shape may be of little difference according to different package factories. These lead shapes are compatible with each other. 10.6. Package USON6 (1.2x1.2mm) Side View
1. Coplanarity ≪0.08mm. Package edge tolerance≪0.10mm. 2. The lead shape may be of little difference according to different package factories. These lead shapes are compatible with each other. 43 Standard and Dual Serial Flash GD25WD10C/05C

Important Notice
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