Makoto Takamiya, Member, IEEE, Tsuyoshi Sekitani,  Yusaku Kato, Student Member, IEEE, Hiroshi Kawaguchi, Member, IEEE,  Takao Someya, Member, IEEE, and  Takayasu Sakurai, Fellow, IEEE Abstract —An integrated system of organic FETs (OFETs) and plastic actuators is proposed, and it is applied to a Braille sheet dis- play. Some circuit technologies are presented to enhance the speed and the lifetime for the Braille sheet display. An OFET SRAM is developed to hide the slow transition of the actuators. Developed five-transistor SRAM cell reduces the number of the bit lines by one-half and reduces the SRAM cell area by 20%. Pipelining the write-operation reduced the SRAM write-time by 69%. Threshold voltage control technology using a back gate increased the static noise margin of SRAM and compensated for the chemical degra- dation of the OFETs after 15 days. The oscillation frequency tuning range from −82% to +13% in a five-stage ring oscillator is also demonstrated with the threshold voltage control technology. The overdrive techniques for the driver OFETs reduced the transition time of the actuator from 34 s to 2 s. These developed circuit technologies achieved the practical 1.75-s operation to change all 144 Braille dots on Braille sheet display and will be essential for the future large area electronics made with OFETs. Index Terms— —Actuator, Braille, large-area electronics, organic FET, SRAM.
I. I NTRODUCTION
ARGE-AREA electronics is a new frontier in electronics where intelligent electronic devices are distributed on a flexible square, 10 cm to 10 m on a side, for human interface and comfortable daily life. Flexible and low-cost organic FETs (OFETs) are suitable for large-area electronics and have a potential as a supplement of solid and expensive silicon MOSFETs. OFETs have been applied to active-matrix displays [1]–[3], RF-ID transponders [4], [5], and sensors [6]–[10]. They are examples of the large-area electronics except for RF-ID. Compared with the silicon MOSFETs, however, the opera- tion speed of OFETs is extremely slow and the device lifetime of OFETs is very short, because fabrication technologies for OFETs are not yet mature. Table I shows a comparison between
our OFETs and the state-of-the-art 90-nm silicon MOSFETs. The gate delay of the OFETs is 3 × 10 7  times larger than that of the silicon MOSFETs, because the design rule of the OFETs is 556 times larger than that of the silicon MOSFETs and the drive current of the OFETs is 1/4000  of that of the silicon MOS- FETs. The device lifetime of OFETs is several days, while that of the silicon MOSFETs is more than 10 years, because OFETs are chemically degraded by the oxygen and moisture in the at- mosphere. In addition, threshold voltage ( V TH ) control process technology such as an ion implantation is not yet established for OFETs. The cost per area of OFETs is lower than that of the sil- icon MOSFETs, while the cost per transistor of OFETs is higher than that of the silicon MOSFETs. In order to put the large-area electronics using OFETs into practical use, circuit technologies to assist the slow and unreliable OFETs are important. In this paper, an integrated system of OFETs and actuators is proposed, and a Braille sheet display is demonstrated [11], [12], which shows a new application of the large-area electronics using OFETs. Device and process technology of the OFETs and the plastic actuators are shown in [11] and this paper focuses on circuit technology [12]. A commercially available Braille dis- play uses piezo actuators and displays 16 Braille characters. The usability of the conventional Braille display, however, is limited due to its weight (～1.0 kg) and thickness (～4 cm). The devel- oped lightweight (〜5 g [11]) and flexible Braille sheet display expands the application of the Braille. The developed Braille sheet display has an actuator array. When the actuators are se- quentially driven, it t takes more than 1 hour to change the actu- ator array, which is impractical. To increase the speed of the ac- tuator, OFET SRAM and overdrive techniques for a driver tran- sistor is proposed. To achieve a reliable and stable SRAM oper- ation, a V TH control technology using a back gate is developed. A five-transistor SRAM cell is also developed to reduce the number of bit lines and cell area. Section II provides a detailed overview of the Braille sheet display and discusses the meaning of SRAM for the display. Section III describes the developed key circuit technologies for the display. Section IV presents an- other application of the V T H control technology. Section V sum- marizes the speed improvement and the power consumption. Fi- nally, some concluding remarks are given in Section VI.
II.  BRAILLE SHEET DISPLAY
Fig. 1 shows the developed Braille sheet display. Braille char- acters in a 6×4 array are shown on the 4 cm ×4 cm display. Each Braille character consists of 2 × 3 dots, and the display has a total of 144 dots. As shown in Fig. 2(a), four films (frame, actuator, OFETs driver, and OFETs SRAM) are stacked in the Braille sheet display. Each Braille dot has an OFET SRAM to compensate for the slow transition of the actuator. The frame is a surface-protecting layer. Pentacene is used as an organic semi- conductor and the pentacene achieves pMOS operations. Nafion is used as the actuators, PEN is used as substrates, polyimide is used as the gate dielectric, parylene is used as passivation layers, and gold is used as all electrodes. Nafion is sandwiched between the upper grounded electrode and the lower electrode. OFETs for SRAM have back gates to control VTH. As shown in Fig. 2(b), the Braille character is changed by moving the dots up and down by means of the actuator, depending on the input voltage. Fig. 3 shows the reason why SRAM is embedded in the Braille sheet display. The display has 12 bit-lines and 12 word-lines for a 12 × 12 Braille dots array. The time to change all Braille dots (T1) is discussed here. Without SRAM, T1 is 408 s, because the 144 actuators are sequentially driven by 12 word lines and it t akes 34 s for an actuator to move. T1 more than 1 minute is not practical. In order to reduce T1, SRAM is embedded. When the SRAM is added, T1 is the sum of SRAM write-time and the above 34 s and equals to 34.5 s, because all actuators are a simultaneously driven after the data are written to SRAM. By using SRAM, T1 is reduced from 408 s to 34.5 s, which corresponds to 1/12 of initial T1. In Section V, the 34.5-s operation time will be reduced to 1.75 s by additional techniques.
III.  KEY CIRCUIT TECHNOLOGIES
A.  Five-Transistor SRAM Cells and Pipelining for Write-Operation Fig. 4 shows the circuit of the SRAM and the driver for one actuator. Only pMOS OFETs are used, because the performance of nMOS OFETs is commonly worse than pMOS. The OFETs for SRAM have back gates [13] to control VTH. A write-only SRAM is enough for our Braille application, because the ac- tuator moves depending on the hold data (DATA, DATAb) and a SRAM read-operation is not required. Therefore, to save the film area, a five-transistor SRAM cell is developed. Compared with a conventional six-transistor SRAM cell, a five-transistor SRAM cell reduces the number of the bit lines by one-half and reduces the SRAM cell area by 20%. Fig. 5 shows a micrograph of the five-transistor SRAM cell. The cell area is 3.7 mm by 2.0 mm, which fits into the 4.0-mm-by-2.0-mm cell size for the stacked one actuator and the two driver transistors [11]. The whole cell is covered with the common back gate and each SRAM cell has the separate back gate. In the five-transistor SRAM cell, a foremost concern is the slow write-time of DATAb, because DATAb has no access transistors. Our design target for the write-time of the whole SRAM (= 144 cells) is within 0.2 s. Fig. 6(a) shows the mea- sured SRAM circuits and Fig. 6(b) and (c) show the measured waveforms of DATA and DATAb during a write-operation. In Fig. 6(b), BL of low is written to SRAM and the transition time of DATAb is 2 ms. In contrast, in Fig. 6(c), BL of high is written and the transition time of DATAb is 40 ms, because the drive current of M1 in Fig. 6(a) is small. This slow transition time can be hidden in the SRAM system-level by pipelining the write-operation. Fig. 7 shows the timing chart for the pipeline. With the pipelining in Fig. 7(b), the write-operation moves to the next SRAM cell after every 10 ms, because the 10%–50% transition time of DATAb is 10 ms in Fig. 6(c) and DATAb flips from high to low. By pipelining, the total write-time for the 12 × 12 SRAM cells is reduced from 480 ms (= 40 ms × 12) to 150 ms (= 10 ms × 11 + 40 ms), which achieves 69% delay reduction and satisfies our design target.
B.  Control of SRAM Static Noise Margin With a Back Gate
The VTH control technology using a back gate is shown to compensate for the immature V t h control process technology and to achieve a reliable SRAM operation. Fig. 8 shows the drain current dependence of the gate voltage of a pMOS OFET. Back gate voltage ( VBGATE ) is varied. By changing VBGATE , V TH can be controlled. Fig. 9(a) shows measured inverters in the SRAM and Fig. 9(b) shows the measured butterfly curves of the SRAM. Back gate voltage (V BGATE ) is varied. The static noise margin (SNM) increases as VBGATE increases. The in- verter gain is 2.7. It is difficult to obtain a larger inverter gain, because the SRAM uses only pMOS OFETs. Therefore, it is im- portant to control V TH in the OFET SRAM in order to obtain a sufficient SNM by using the low-gain inverters. Fig. 9(c) shows the measured VBGATE dependence of SNM. The power supply voltage (VDD) is varied. When VDD is 40 V, SNM increases as V BGATE increases. In contrast, when V D  is 20 V, an optimum V BGATE ー V DD of 25 V achieves the maximum SNM, because there is an optimum |VTH| of OFETs. Compared with SNM at V BGATE ー V DD = 0 V , by adjusting V BGATE , SNM increases 2.4 and 2.6 times when VDD is 40 V and 30 V, respectively. The chemical degradation is the most serious problem for OFETs. Fig. 10 shows a measured dependence of VTH of pMOS OFETs on the time after fabrication. It should be noted that the OFETs in Fig. 10 is different from the OFETs used in the Braille sheet display and have no correlation with all the other figures. Amplitude of V tH shift during 14 days is 5.3 V and 0.68 V in the air and in nitrogen, respectively. VTH shift in the air is larger than that in nitrogen, because the oxygen and moisture in the air enhances the chemical degradation. Both V TH shifts, however, are too large and are not acceptable for SRAM design. There- fore, the VTH control technology is also applied to compensate for the chemical degradation of OFETs and to achieve a reliable SRAM operation. Fig. 11(a) shows a measured inverter in the SRAM and Fig. 11(b) shows the measured aging characteris- tics of the inverter without the VTH control technology. The in- verter was kept in a nitrogen atmosphere without bias stressing except for the measuring time. As time passes, the inverter char- acteristics show a rightward shift due to the reduced | VTH of OFETs. Similar rightward shift of the inverter characteristics after 7800-s bias stressing is reported in [14], which is because of the electrical degradation. Fig. 11(c) compares the measured virgin characteristics of the inverter without the compensation and aging characteristics of the inverter compensated by the back gate. By manually adjusting VBGATE , the chemical degra- dation after 15 days is successfully compensated and the similar inverter characteristics are obtained. Fig. 11(d) shows the aging characteristics of SNM calculated based to Fig. 11(b) and (c). By compensating the reduced |VTH | of OFETs due to the chem- ical degradation with the back gate, the reduced SNM after 15 days recovers to the initial level. When VBGATE is adaptively controlled, a constant SNM can be achieved. Because the chem- ical degradation is inherent in OFETs, the proposed compensa- tion technology is essential to OFET applications. Of course, the process technology improvement is also important to extend the device lifetime. Our recent results show little V TH shift after 60 days exposure in air by newly developed passivation layer [15]. However, further process technology improvement is required to put OFETs to practical use. Systematic manufacturing vari- ation within a plastic film for the OFETs can also be compen- sated by dividing the back gate and adaptively applying different VBGATE-
C.  Overdrive Techniques for Driver Transistors
Our design target for the transition time of the actuator is within 2 s. Fig. 12(a) shows the driver circuits for the actuator to investigate overdrive techniques. An equivalent circuit of actu- ator is also shown. In order to achieve the fast movement of the actuator, large drive current of the driver transistor is required to quickly charge and discharge the large capacitance (100 μ F) of the actuator. As s shown in Fig. 4, the gate width of the driver tran- sistor is 49000 μ m to o obtain large drive current. The breakdown voltage of the actuator is ±3 V. Fig. 12(b) shows the measured waveforms of the actuator voltage ( VACT ) and the actuator dis- placement. The step voltage height (V x ) of V p L is varied. The required displacement by Braille users is 0.2 mm. When V PL is equal to the breakdown voltage of −3 V, the transition time is 34 s, which exceeds our design target. In order to reduce the tran- sition time, VPH and VPL overdrive techniques are proposed. By increasing Vχ from −3 V to −10 V, the transition time is re- duced from 34 s to 2.0 s, which satisfies our design target. In order to avoid the breakdown of the actuator, the overdrive pe- riod is determined by the time when V ACT is within ±3 V. Finally, an operation of the Braille sheet display is demon- strated. Fig. 13(a) shows a measured circuits and Fig. 13(b) shows the measured waveforms of the driver and the actu- ator for a Braille dot. Movement of the Braille dot, both up and down, has been successfully demonstrated. By using ±10-V-overdrive techniques during 2.5 s in VpH and VpL, a 1.6-s up-transition time and a 0.74-s down-transition time of the actuator are achieved. 98
IV.  DISCUSSIONS
In the Section III-B, the control of the SRAM static noise margin with the VTH control technology using the back gate was presented. In this section, another application of the VTH control technology is shown. The VTH control technology is ap- plied to an OFET ring oscillator and an oscillation frequency tuning is demonstrated. Fig. 14(a) shows a circuit schematic of a measured five-stage ring oscillator with the back gate. The transistor sizes and the bias conditions for an inverter in the os- cillator are identical with those in SRAM. The output waveform was directly measured with an oscilloscope probe with 100-MΩ input impedance and no output buffer for the oscillator is used, because the OFET gate capacitance is larger than the capaci- tance of a pad and the probe. Fig. 14(b) shows a micrograph of the oscillator. The area for the oscillator is 4.5 mm by 5.0 mm. All OFETs are covered with the common back gate. Fig. 14(c) shows the measured VBGATE dependence of the oscillation fre- quency. At V BGATE — V DD = 0 V , the center oscillation fre- quency is 339 Hz which corresponds to the gate delay of 0.3 ms in Table I. The oscillation frequency tuning range from 62 Hz (−82%) to 383 Hz (+13%) is achieved by changing VBGATE- The frequency tuning asymmetry derives from the VTH tuning asymmetry shown in Fig. 8 and discussed in [13]. The developed delay tuning method using the back gate enables a post-fabrica- tion tuning of OFET circuits.
V.  Performance Summary
Fig. 15 summarizes the time to change 144 Braille dots and the speeding up by the developed circuit technologies. At an ini- tial design without the SRAM, it takes 408 s, because the 144 actuators are sequentially driven by 12 word lines. When the SRAM is added, it takes 34.5 s, because all actuators are a si- multaneously driven after the data are written to SRAM. At a final design, the developed pipelining for SRAM write-opera- tion and overdrive technology for the driver increased the speed of the Braille sheet display 233 times, and achieved the practical 1.75-s operation. Fig. 16 shows the power consumption for the whole Braille sheet display at 0.1-Hz operation. The total power consumption is 51.9 mW. The dominant component is the leakage power of the actuators (21.6 mW = 50 μ A × 3 V × 144). In contrast, the leakage power of piezo actuators used in a commercially avail- able Braille display [16] is 230.4 mW (= 8 μA × 200 V × 144) which is 10.7 times larger than that of our actuators. Therefore, our plastic actuators contribute to the low power operation for the Braille display.
VI.  CONCLUSION
OFETs were integrated with actuators, and a Braille sheet dis- play was demonstrated. An SRAM made with OFETs is demon- strated for the first time. Pipelining the write-operation reduced the SRAM write-time by 69%. Threshold voltage control tech- nology using a back gate increased the SNM and compensated for the chemical degradation of the OFETs after 15 days. The overdrive techniques for the driver OFETs reduced the transi- tion time of the actuator from 34 s to 2 s. These developed circuit technologies will be essential for the future large area electronics made with OFETs.
A CKNOWLEDGMENT
The authors would like to acknowledge Prof. M. Doi, Univer- sity of Tokyo, and Dr. K. Asaka, AIST, for the sheet-type plastic actuator.
R eferences
[1] E. Huitema, G. Gelinck, B. van der Putten, E. Cantatore, E. van Vee- nendaal, L. Schrijnemakers, B.-H. Huisman, and D. de Leeuw, "Plastic transistors in active-matrix displays," in IEEE ISSCC Dig. Tech. Pa- pers , 2003, pp. 380–381. [2] T. Shimoda and T. Kawase, "All-polymer thin film transistor fabricated by high-resolution ink-jet printing," in IEEE ISSCC Dig. Tech. Papers , 2004, pp. 286-287. [3] P. van Lieshout, E. van Veenendaal, L. Schrijnemakers, G. Gelinck, F. Touwslager, and E. Huitema, "A flexible 240 × 320-pixel display with integrated row drivers manufactured in organic electronics," in IEEE ISSCC Dig. Tech. Papers , 2005, pp. 578–579. [4] M. Böhm, A. Ullmann, D. Zipperer, A. Knobloch, W. H. Glauert, and W. Fix, "Printable electronics for polymer RFID applications," in IEEE ISSCC Dig. Tech. Papers , 2006, pp. 270–271. [5] E. Cantatore, T. C. T. Geuns, A. F. A. Gruijthuijsen, G. H. Gelinck, S. Drews, and D. M. de Leeuw, "A 13.56 MHz RFID system based on organic transponders," in IEEE ISSCC Dig. Tech. Papers , 2006, pp. 272–273. [6] T. Someya and T. Sakurai, "Integration of organic field-effect transis- tors and rubbery pressure sensors for artificial skin applications," in IEEE IEDM Tech. Dig., 2003, pp. 203–206. [7] H. Kawaguchi, T. Someya, T. Sekitani, and T. Sakurai, "Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin," IEEE J. Solid-State Circuits , vol. 40, no. 1, pp. 177–185, Jan. 2005. [8] T. Someya, Y. Kato, S. Iba, Y. Noguchi, T. Sekitani, H. Kawaguchi, and T. Sakurai, "Integration of organic FETs with organic photodiodes for a large area, flexible, and lightweight sheet image scanners," IEEE Trans. Electron Devices , vol. 52, no. 11, pp. 2502–2511, Nov. 2005. [9] H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and T. Sakurai, "A sheet-type scanner based on a 3-D stacked organic-transistor circuit with double word-line and double bit-line structure," in IEEE ISSCC Dig. Tech. Papers , 2005, pp. 580–581. [10] V. Subramanian, J. B. Lee, V. H. Liu, and S. Molesa, "Printed elec- tronic nose vapor sensors for consumer product monitoring," in IEEE ISSCC Dig. Tech. Papers , 2006, pp. 274–275. [11] Y. Kato, S. Iba, T. Sekitani, Y. Noguchi, K. Hizu, X. Wang, K. Takenoshita, Y. Takamatsu, S. Nakano, K. Fukuda, K. Nakamura, T. Yamaue, M. Doi, K. Asaka, H. Kawaguchi, M. Takamiya, T. Sakurai, and T. Someya, "A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix," in IEEE IEDM Tech. Dig., 2005, pp. 105–108. [12] M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An organic FET SRAM for Braille sheet display with back gate to increase static noise margin," in IEEE ISSCC Dig. Tech. Papers , 2006, pp. 276–277. [13] S. Iba, T. Sekitani, Y. Kato, T. Someya, H. Kawaguchi, M. Takamiya, T. Sakurai, and S. Takagi, "Control of threshold voltage of organic field-effect transistors with double gate structure," Appl. Phys. Lett., vol. 87, p. 023509, Jul. 2005. [14] S. J. Zilker, C. Detcheverry, E. Cantatore, and D. M. de Leeuw, "Bias stress in organic thin-film transistors and logic gates," Appl. Phys. Lett. , vol. 79, p. 1124, Aug. 2001. [15] T. Sekitani, M. Takamiya, T. Sakurai, and T. Someya, "Air-stable op- eration of pentacene field-effect transistors on plastic films using or- ganic/metal hybrid passivation layers," Appl. Phys. Lett. , submitted for publication. [16] Input/output and read Braille characters. [Online]. Available: http:// www.kgs-jpn.co.jp/epiezo.html Makoto Takamiya (S'98–M'00) received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 1995, 1997, and 2000, respectively. In 2000, he joined NEC Corporation, Japan, where he was engaged in the circuit design of high speed digital LSIs and developed the field of on-chip mea- surement macros to solve the power integrity issues. In 2005, he joined University of Tokyo, Japan, where he is an Associate Professor of the VLSI Design and Education Center. His research interests include power and signal integrity issues in LSIs, low-power RF integrated circuits, low-power digital circuits, and large area electronics with organic transistors. Tsuyoshi Sekitani received the B.S. degree from Osaka University, Japan, in 1999, and the Ph.D. degree in applied physics from the University of Tokyo, Japan, in 2003. From 1999 to 2003, he was with the Institute for Solid State Physics, University of Tokyo. Since 2003, he has been a Research Associate of the Quantum- Phase Electronics Center, University of Tokyo. His current object of physics research is organic semicon- ductors and organic-FET devices. Dr. Sekitani is a member of the American Physical Society (APS), the Materials Research Society (MRS), the Physical Society of Japan, and the Japanese Society of Applied Physics. Takao Someya (M'03) received the Ph.D. degree in electrical engineering from the University of Tokyo, Japan, in 1997. In 1997, he joined Institute of Industrial Sci- large-area sensors, and plastic actuators. Prof. Someya is a member of the IEEE Electron Devices Society (EDS), the Materials Research Society (MRS), and the Japanese Society of Applied Physics. He serves as a subcommittee member for the IEEE International Elec- tron Device Meeting (IEDM) and a member of the IEEE/EDS Organic Elec- Yusaku Kato (S'05) was born in Tokyo, Japan, in 1981. He received the B.S. degree in applied physics from the University of Tokyo in 2004, and he is now a graduate student of master's course in applied physics at the University of Tokyo. He is currently involved in development of the new large-area integrated devices that are composed of or- ganic transistors and other function elements. Mr. Kato is a student member of the IEEE, the Ma- terials Research Society (MRS), and the Japanese So- ciety of Applied Physics. (S'77-M'78-SM'01-F'03) Hiroshi Kawaguchi (M'98) received the B.E. and M.E. degrees in electronic engineering from Chiba University, Chiba, Japan, in 1991 and 1993, respec- tively. He received the Ph.D. degree in engineering from the University of Tokyo, Tokyo, Japan, in 2006. He joined Konami Corporation, Kobe, Japan, in 1993, where he developed arcade entertainment sys- on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC's and large-area electronics. Dr. Sakurai has published more than 350 technical publications including 70 invited publications and several books and filed more than 100 patents. He served as a conference chair for the Symposium on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the first A-SSCC, and VLSI symp. and a program committee member for ISSCC, CICC, DAC, ESSCIRC, ICCAD, FPGA workshop, ISLPED, TAU, and other international conferences. He is a plenary speaker for the 2003 ISSCC. He is a recipient of 2005 IEEE ICICDT Award, 2005 IEEE ISSCC Takuo Sugano Award and 2005 P&I Patent of the Year Award. He is an IEEE Fellow, a STARC Fellow, an elected AdCom member for the IEEE Solid-State Circuits Society, and an IEEE CAS distinguished lec- turer. dustrial Science, the University of Tokyo. Dr. Kawaguchi is a recipient of the IEEE ISSCC 2004 Takuo Sugano Award for Outstanding Far-East Paper. He has served as a program committee member for IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips). He is a guest associate editor of IEICE Transactions on Fundamentals of Elec- tronics, Communications and Computer Sciences . His current research interests include low-power VLSI design, hardware design for wireless sensor network, and recognition processor. Dr. Kawaguchi is a member of the IEEE and the Association for Computing Machinery (ACM). ence (IIS), the University of Tokyo, as a Research Associate and was appointed to be a Lecturer of the Research Center for Advanced Science and Technology (RCAST), the University of Tokyo, in 1998, and an Associate Professor of RCAST in 2002. From 2001 to 2003, he worked for the Nanocenter (NSEC) of Columbia University and Bell Labs, Lucent Technologies, as a Visiting Scholar. Since 2003, he has been an Associate Professor of the Department of Applied Physics and Quantum-Phase Electronics Center, the University of Tokyo. His current research interests include organic transistors, flexible electronics, plastic integrated circuits, tronics Committee. Takayasu Sakurai received the Ph.D. degree in electrical engineering from the University of Tokyo, Japan, in 1981. In 1981, he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has worked extensively on interconnect delay and capacitance modeling known as Sakurai model and alpha power-law MOS model. From 1988 through 1990, he was a visiting researcher at the University of California, Berkeley, where he conducted research in the field of VLSI CAD. Since 1996, he has been a Professor at the University of Tokyo, working tems. He moved to the Institute of Industrial Science, the University of Tokyo, as a Technical Associate in 1996, and was appointed to be a Research Associate in 2003. Since 2005, he has been a Research Asso- ciate in the Department of Computer and Systems Engineering, Kobe Univer- sity, Kobe, Japan. He is also a Collaborative Researcher in the Institute of In-