1. Introduction
Energy harvesting has attracted considerable attention since it can realize energy-autonomous applications, and many battery-free applications using energy harvesting have been proposed [1] – [5] . RF energy harvesting [6] is one of the en- ergy harvesting approaches that produces energy from ambi- ent RF signals.  Although it can only obtain a small amount of energy, it is more stable than energy harvesting from solar and wind energy [7] . Figure 1 (a) shows a block diagram of a typical IoT node with RF energy harvesting. The antenna receives an RF signal (e.g., 920 MHz).  Then, the charge pump converts the RF signal into a DC voltage (VDD) and charges the output capacitor C 1 . Before the energy harvest- ing operation starts, V DD is 0 V. Once it starts, V DD increases gradually with the charging current from the charge pump. Since the charging current is very small (e.g., 1 μ A [8] or 1 nA [6] , during the charging period, the output switch M 1 must be turned off completely to prevent the charging cur- rent from flowing into the output load. The voltage detector (VD) monitors V DD and turns the output switch M 1 on or off depending on the value of V DD .  Figure 1 (b) shows an Example of IoT node with RF energy harvesting. (a) Block dia- gram. (b) Waveform illustrating operation sequence. operation sequence of the IoT node shown in Fig. 1 (a).  At the start of the charging, V D  gradually increases from 0 V since the output power of the antenna is very small. While the charge pump charges C 1 , the VD keeps M 1 off. When V DD reaches a predefined detection voltage (V DETECT), the VD turns M 1 on and the load circuits start their operation. Since the VD is directly connected to the output node of the charge pump, it must have very low power consumption of less than 1 nA [6] . The VD must operate from 0 V with- out any glitch in V OUT , otherwise it will mistakenly turn M 1 on and spoil the energy harvesting.  Furthermore,  V DETECT must be robust against variation in the process, voltage, and temperature (PVT). In this paper, a novel circuit scheme for a VD [9] is introduced to achieve ultra-low power operation, robustness against PVT variations, and glitch-free operation at the same time.  The theoretical analysis and design consideration of the proposed VD is added to [9] . This paper is organized as follows. In Sect. 2, the con- ventional VDs are introduced with emphasis on their prob- lems. In Sect. 3, the concept of the proposed glitch-free and programmable VD is described. Section 4 introduces the de- sign consideration of the proposed multiple voltage copier. Section 5 gives measurement results and a comparison with other VDs. Finally, conclusions are described in Sect. 6.
Issues with Conventional Voltage Detectors
2.
Glitch-Free and Programmable Operation
2.1
Figures 2 (a) and (b) show a circuit schematic and an input- output characteristic of commercially available VDs [10] – [12] , respectively.  The VD is composed of a voltage di- vider for V IN , a voltage reference generator, and a compara- tor.  When the input voltage (V IN ) is lower or higher than V DETECT, V OUT is low or high, respectively. V DETECT is ex- pressed as follows:
where k is the division ratio of the voltage divider for V IN . V REF is the supply voltage from the voltage reference circuit. In most cases, V DETECT is factory-trimmed by changing the value of k. The voltage reference circuit is an important part in that it dominates the power consumption of the VD and determines the temperature dependence of V DETECT . Typi- cal voltage reference circuit is bandgap reference (BGR), on the other hand, the power consumption of BGR is usually over 10 nW. It also limits the operation voltage of the VD since the typical minimum operation voltage of BGR is over 1 V. An ultra-low power 2-transistor voltage reference was proposed in [13] . Though it operates at 0.5 V supply volt- age with sub-10pW power consumption, Vref is sensitive to the process variation because V REF is determined by the threshold voltages of the transistors in the voltage reference circuit. With the voltage reference [13] , the power consump- tion of the VD is reduced, on the other hand, V DETECT Varies by the process variation.  Some post-fabrication program- ming methods are required to compensate for the variation in V DETECT . In this work, a post-fabrication programming method is proposed. Another problem of the commercially available VD is the glitch in Vout.  Compared with VDs for hardware re- set detection such as Brown-out Reset (BOR), VDs for en- ergy harvesters with small output power must operate even though V IN is near 0 V as mentioned in Sect. 1. The mini- mum operating voltage (V MIN ), however, is defined in com- mercially available VDs. As shown in Fig. 2 (b), when V N is between 0 V and V MIN , V OUT is undefined and sometimes a glitch is generated, which spoils the power charging in the energy harvesting. Figure 3 shows the 1.6 nW glitch-free VD proposed in [14] .  As shown in Fig.3(b), the VD has no glitch in V OUT , whereas V DETECT is fixed. In addition, V DETECT has a large temperature coefficient (TC) which is calculated to be 2.0 mV/°C using typical transistor parameters.  In [15] , a VD for miniature sensor nodes was proposed.  Although the VD realized sub-1 nW operation, the programmability of V DETECT was not discussed and V DETECT had a large TC of 1.5 mV/°C. 2.2  Low Power and Temperature-Variation-Tolerant Oper- ation of Programmable Voltage Detector A simple idea for realizing a post-fabrication programmable VD is to use a voltage reference with a resistance ladder as shown in Fig. 4.  A multiplexer (MUX) which is imple- mented with transistor switches, selects the output voltage of the programmable voltage reference to achieve a suitable V DETECT . The problem of the scheme, however, is that there is a tradeoff between the temperature dependence of the out- put voltage of the programmable voltage reference (V ref1 ) and the power consumption required to generate V REF1 . Ide- ally, the MUX has no leakage current, that is, I B1, I B2, and I BN = 0 and I 1 = I 2 . Then, the TC of V REF1 is equal to that of V REF . In reality, the switches in the MUX have leakage currents [16] .  Without a sufficient I ,  the  temperature  de- pendence of V REF1 is inferior to that in the ideal case.  The voltage reference must drive a large I 1 , which causes an in- crease in the power consumption of the voltage reference. The TC of V REF1 and the power consumption of the voltage reference have a tradeoff relationship.  The tradeoff is later quantitatively shown in Fig. 14.
Proposed Glitch-Free Programmable Voltage Detec-
3.
tor
3.1
Glitch-Free and Programmable Operation
Figures 5 (a) and (b) show a block diagram and the concept of the proposed glitch-free programmable VD, respectively. As shown in Fig.5, by combining the programmable VD with the glitch, and the glitch-free VD with a fixed V DETECT , both glitch-free and programmable operation are achieved when V MIN < V DETECT2 < V DETECT1 , where V DETECT1 and V DETECT2 are the detection voltages of the programmable VD and the glitch-free VD respectively. Table 1 summarizes the four VDs regarding their programmability and glitch- free operation.  Figure 6 shows a schematic of the entire circuit of the proposed VD. All MOSFETs operate in the subthreshold region, which enables the ultra-low power con- sumption of the proposed VD. The body node and the source node are shorted in pMOSFETs in the proposed VD to avoid the body effect.  Assuming that the proposed VD is ap- plied to the RF energy harvesting shown in Fig. 1, the output node of the VD (V outb) is designed to be high/low when V IN  is  lower/higher than V DETECT .  In  the  proposed  pro- grammable VD, the voltage reference is implemented with two stacked pMOSFETs with different threshold voltages (VTH), which is a similar concept to that in [13] , in which two stacked nMOSFETs with different values of V tH are implemented. The V tH difference is approximately 0.4 V. In our design, the target V DETECT is s set to 0.7 V. On the other hand, from the corner analysis in the SPICE simulation, the target V DETECT Varies ±60 mV with the process variation of the pMOSFETs.  Then, the programmability in V DETECT is set to cover the effect of the process variation.  To reduce the step of the programmable V DETECT , voltage dividers are added to both V IN and V REF .  The MUX in the proposed VD adopts low-V tH MOSFETs as the switches to enable the low voltage operation of the VD and achieve the low voltage V DETECT . When V IN is lower voltage than the V H of the low-V th MOSFET, the programmable VD does not operate properly, which causes the glitch in V OUT1. On the other hand, the glitch in V outb is removed thanks to the glitch-free VD. In this work, a glitch-free temperature-variation- tolerant VD is newly proposed. As shown in Fig. 6, the VD is composed of two stacked pMOSFETs M 8 and M 9 with different V th .  When V in is lower than V detect2, the cur- rent on M 9 (I 9 ) is much larger than the current on M 8 (I 8 ), then V OUT2 is kept to 0 V. As V IN increases, I 8 increases exponentially, and once I 8 exceeds I 9 , the voltage level of V OUT2 changes from 0 V to V IN .  At the point, the drain to source voltages of M 8 and M 9 are over 3V T . The currents of M 8 and M 9 are expressed as follows [17] :
where m 8 (m 9 ), V tH 8 (V tH 9 ), and μ 8 (μ 9 ) are the body-effect coefficient, the threshold voltage of transistor M 8 (M 9 ), and the mobility of the transistor, respectively. V T is the thermal voltage (= k B T/q), k B is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge.  W 8
(W 9 ) and L 8 (L 9 ) are the gate width and length of each tran- sistor and Coxs (Cox9) is the gate capacitance per unit area of each transistor. From (2) and (3), V DETECT2 is calculated as follows.
In (4), by sizing M 8 and M 9 properly, the temperature de- pendence of the V DETECT2 can be mitigated since the TC of the first and the second terms are opposite character- In our design, the sizing ratio of the glitch- istics [18]. free VD (W 9L 8/W 8L ) is decided by the SPICE simulation to minimize the temperature dependence of the V DETECT2 . V DETECT2 is expressed as about the difference of thresh- old voltages between high-Vth pMOSFET and low-Vth pMOSFET. Figure 7 shows the input-output characteris- tics of the glitch-free temperature-tolerant VD obtained by SPICE simulation.  The simulated TC of V DETECT2 is less than 0.1 mV/°C. The conventional AND or NAND gate for the VD shown in Fig.5(a) has a minimum operating voltage (V MIN2 ) [19] which may cause a glitch in V OUTB . To elimi- nate this possibility, a new NAND gate is proposed as shown in Fig.6. Using the proposed NAND gate, V OUTB is fixed to V IN when V IN < V MIN2 . The NAND gate is composed of M 4 , M 5 , and M 6 , which are high-V TH transistors, and M 7 , which is a low-V tH transistor. When V IN is 0 V, the gate-to- source voltage of all the transistors is 0 V, then the leakage current of M 7 is much larger than the currents in the other transistors because V th of M 7 is lower than that for other transistors.  While V IN is increasing, the leakage current on M 7 increases V OUTB to V IN . Figure 8 shows the input- output characteristics of the proposed VD with a conven- tional NAND gate and with the proposed NAND gate, ob- tained by SPICE simulation. With the conventional NAND gate, a glitch is generated in Voutb when V in is less than 0.5 V. In contrast, the glitch in V OUTB is removed with the proposed NAND gate. 3.2 Multiple Voltage Copier for Low Power and Tem- perature-Variation-Tolerant Programmable Operation To solve the tradeoff between the power consumption and the temperature dependence of the programmable voltage detector as described in Sect. 2, a multiple voltage copier (MVC) is newly proposed and inserted between the volt- age divider used for the voltage reference and the MUX. The MVC is a multiple-input and multiple-output voltage buffer.  In the MVC in Fig. 6, M 0 is the current source with a subthreshold leakage current (V GS  =  0) of I C 0 , and the other transistors (M 1 , M 2 , and M N ) are serially stacked. The source currents (I C 0 , I C 1 , I C 2 , and I C N ) are sufficiently larger than the leakage currents (I B0 , I B1 , and I BN ) of the switches to avoid the voltage drop and the temperature dependence of selectable output nodes (V'REF, V', and V',). Then, an inter- esting characteristic of the MVC is that each input voltage is equal to each output voltage (V REF = V r EF , V r = V r , and for all transistors in the MVC. Thus, in the MVC, multiple input voltages are simultaneously copied to multiple output voltages. The power overhead of the MVC is 56 pW at 0.8 V. In Fig. 4 (a) and Fig. 6, the supply currents for the volt- age references must be sufficiently larger than I 1 to elim- inate the voltage drop and the temperature dependence of each V REF . By inserting the MVC between the voltage di- vider and the MUX in Fig. 6, I A0 = I A1 = I AN = 0 and I 1 can be greatly reduced compared with I 1 in Fig. 4 (a), which en- ables the power reduction in the voltage reference in Fig. 6. Thus, the tradeoff between the power consumed to generate V REF1 and the temperature dependence of V REF1 in the con- ventional programmable VD is solved by using the MVC. In the SPICE simulation, the current on MVC is set to 10 times larger than the amount of the leakage currents of the MUX in the target temperature range.
Design Consideration and Theoretical Analysis of
4.
MVC
In the Sect. 3, the MVC was newly proposed as a multiple- input and multiple-output voltage buffer.  Ideally, the MVC copies multiple input voltages to the multiple output nodes simultaneously without any duplication errors. In fact, ow- ing to the load current in each output node, a slight error, which is the difference between the input voltage and out- put voltage, is generated in the duplication. The duplication error is dependent on the current in the MVC and the load current in each output node. In this section, the design con- sideration and a theoretical analysis of the MVC are intro- duced to clarify the relationship between the current in the MVC and the accuracy of the duplication. The model used for the analysis is shown in Fig.9. ΔV i = V i – V i (i = 1,2,...,N) is the duplication error in each output node. Assuming that each transistor is suffi- ciently large, the effect of random variation is neglected. To simplify the analysis, each load current is assumed to be the same (I 01 = I 02 = . . . I ON = I 0 ). Assuming for V DS of each transistor is sufficiently large (> 3VT), the drain currents of Mo and Mi are expressed as follows:
where where μ and C OX are the mobility and gate capacitance of the transistor respectively. From (5) and (6), the ratio of I D0 to ID: is
where
From (8) and (9), ΔVi is given as follows.
When I LEAK ,i/I D0 is sufficiently small (< 0.1), ΔV i is approx- imated as
From (11), the conditions for the worst ∆ V i are introduced. 1) The absolute value of the duplication error (|ΔVi|) is the largest when i = N. That is, designers have to con- sider ΔV N to evaluate the worst duplication error in the MVC. 2) The TC of ΔV is positive as shown in Fig. 10 since the temperature dependence of −1/I D0 is dominant in (11). It implies that the |ΔV i | is the largest at the lowest temperature in the designer's target temperature range. To verify the consistency of the analysis, SPICE simula- tions were conducted. Figure 10 shows a comparison of the SPICE simulation results for the temperature dependence of △V N in the target range of −20°C to 80°C with that given by (11). The body-effect coefficient m is determined from the characteristics of the pMOSFET at −20°C in the SPICE simulation. I LEAK N /I D0 is set to 0.1 at −20°C. The SPICE simulation results are in agreement with (11) within an error of 11%. The simulation results and (11) show that the TC of AV N is positive and that the largest | ΔV N | occurs at the low- est temperature in the target range. From (11), ΔV N and I D0
have a tradeoff relationship. Figure 11 shows the relation- ship between I LEAK , N /I D 0 and ΔV N . ΔV N is proportional to I LEAK,N/I D0 .  This means that to reduce the duplication error in the MVC to within a certain voltage, the MVC requires a sufficient value of I D 0 . To maintain the duplication error in the MVC (= ΔV N ) below ΔV URS , the following equation must be satisfied:
where T MIN is the lowest target temperature and AV URS is the acceptable error defined by designers.  Equation (12) means that once T MIN , I LEAK , N , and ΔV URS are defined by designers, the optimum I D0 (= I D0,min ) is automatically given by (12).
Measurement Results
5.
A test chip is fabricated in a 2.5 V 250 nm CMOS process. Figure 12 shows a chip photograph of the proposed VD. The core area is 76 µm by 120 µm. Figure 13 shows the simulated and measured input- output characteristics of Vout², Vout², and Voutb for the proposed glitch-free programmable VD in Fig. 6.  When V IN is near 0 V, there is a glitch in V OUT1 .  Owing to the combination of the glitch-free VD and the programmable VD, the glitch is removed from Voutb.  The voltage level OF V OUTB is maintained at V IN when V IN is lower than V DETECT .  To clarify the tradeoff between the power con- sumed to generate V REF1 and the temperature dependence of V REF1 , Fig. 14 shows the power supply current depen- dence of the TC for V REF1 with and without the MVC. For V REF1 without the MVC, the results are obtained by SPICE simulation of the circuits in Fig. 4 (a), where the voltage ref- erence shown in Fig. 6 is used and the transistor gate width of the voltage reference is varied to change I 1 in the sim- ulation.  As the power supply current is reduced, the TC increases, which indicates a tradeoff between the power consumption and the TC. A measured result is shown for V REF1 with the MVC. By introducing the MVC, the trade- off is solved, and both a low supply current (92pA) and a low TC (0.10 mV/°C) are simultaneously achieved. Fig- ure 15 shows the measured programmable V DETECT in the proposed glitch-free programmable VD. The programmable range of V DETECT is from 0.52 V to 0.85 V in steps of less than 49 mV. The programming step ensures the safe operat- ing tolerance V DD of ±5% in the load circuit. Figure 16 (a) shows the measured temperature dependence of V DETECT for five dies. Figure 16(b) shows the change of V DETECT nor- malized by the values at 25°C. The measured TC of V DETECT is 0.11 mV/°C from −20°C to 80°C. The cause of the nega- tive TC is assumed to be the temperature characteristics of the 2-transistors voltage reference.  The measured V TH of the pMOSFETs in the VD is slightly higher than it was ex- pected, which causes the negative temperature dependence
of V REF and V DETECT in our design.  Other assumed rea- son for the negative TC is the mismatch in the compara- tor. It is improved by enlarging the size of transistors. Fig- ure 17 shows the power consumption of the proposed VD for five dies and the breakdown of the power consumption. The power consumption is 248 pW at V IN = 1.0 V. The cur- rent increases almost linearly in 0 V to 1 V range. The V IN dependence is caused by the current in the input voltage di- vider.  The subthreshold current in the voltage divider in- creases exponentially with the increase of the gate to source voltage of each transistor. On the other hand, by stacking a lot of transistor diodes for the voltage divider, the change of the gate to source voltage of each transistor is slight against the change of V IN . It causes the linear increase of the power consumption of the VD in the range.  In Table 2, the results of this work are compared with those for previously pub- lished VDs.  In this work, the operating supply voltage is defined as the voltage region where the VD does not gen- erate a glitch in the output node.  We achieve a minimum operating voltage of 0 V owing to the glitch-free operation, which is essential for energy harvesting.  We have demon- strated a programmable VD with steps of less than 49 mV to compensate for a die-to-die variations. The proposed MVC enables a programmable VD with the lowest reported power
of 248 pW and a competitive TC of 0.11 mV/°C.
Conclusion
6.
In this paper, an ultra-low power, glitch free, and PVT- variation-tolerant voltage detector (VD) is proposed and im- plemented in a 250nm CMOS process. This is the first re- port of an ultra-low power glitch-free programmable VD. The proposed VD is composed of a programmable VD and a glitch-free VD. All MOSFETs operate in the subthreshold region to reduce the power consumption of the VD. Owing to the proposed glitch-free VD and a novel NAND gate, the glitch of the proposed VD is removed.  To realize a pro- grammability in the VD with little power loss, a multiple voltage copier (MVC) for the programmable VD is pro- posed. It operates as a multiple-input and multiple-output voltage buffer, which copies the input voltage level to the output node.  It solves the tradeoff between the power con- sumption of the programmable VD and the temperature de- pendence of V DETECT . The power consumption of the MVC is 56pW. From the measurement results, the power con- sumption decreases without the deterioration of the temper- ature dependence in the programmable VD when the MVC is used.  In this work, the design consideration and a theo- retical analysis of the MVC are introduced to clarify the re- lationship between the current in the MVC and the accuracy of the duplication.  From the analysis, a tradeoff between the duplication error and the current of the MVC is demon- strated. Measurement results show that the power consump- tion of the proposed VD is 248 pW. This is the lowest power consumption ever reported for a VD. The temperature co- efficient (TC) has a competitive value of 0.11 mV/°C. The steps of the programmable detection voltage are less than 49mV while its range is from 0.52 V to 0.85 V. The pre- sented VD is expected to be particularly advantageous for applications that require power consumption of less than 1 nW such as energy-harvesting systems.