FPGA FPGA-Specific Circuit Implementation of Data-Driven Processor 1020267 2002 2 8 13 FPGA FPGA FPGA DDP FPGA FPGA
OGURA, Michihiro By evolution of sen micon ductor integration technology, the processors that carry hundreds of millions of transistors had been developed. Almost of those current processors implement the von Neumann principle and those are realized by synchronous circuits. However, it becomes difficult to attain the further improvement in the speed, integration, and power-saving. These problems arise from the nature of the sequential processing. The self-timed pipeline was intro- duced to settle these problems. The self-timed pipeline has a strong affinity to the data-driven principle. Transmission of the data is asynchronously conducted by local transfer control units in the self-timed data-driven architecture (DDP). Therefore, flexible data transmission can be realized and wiring can be localized by these control units. Since the data-driven processor becomes free from the problems mentioned above, it has more high capability than the von Neumann type  processor. This paper aims at building the developping environment of the application-specific data- dnven processors made of the self-timed pipeline. To implement a data-driven processor on an FPGA chip, the self-timed pipeline, the packet copy control circuit, and packet elimination The data-driven processor which implemented the proposed control circuit were proposed. circuit was compared with the existing software simulator. Consequently, they have high precision and high speed for functional verification. Furthermore, the amount of resource consumption of FPGA was investigated and functional verification of a multiprocessor was considered and showed a good result for large scale DDP system. key words self-timed pipelene, data-driven processor, FPGA
48 49
the content of the cont . - . - DDP Data Driven Processor  [1] DDP FPGA Field Programmable Gate Array DDP DDP FPGA DDP DDP RTL(Register Transfer Level) (Processing Element) FPGA DDP F PG A DDP LSI DDMP FPG A DDP LSI LSI FPGA DDP FPGA DDP FPGA 2 2.1 FPGA LSI 2.2 2.1 D Li Li D L i i 2 1 2.2 DL i D L i +1 D L i _ 1 D L i 2 2.2 2.2 2.1 C Send ( Ack) P, 2.1 C 2.3 2.3 C 2 2 DDMP C “ 1 ” “0” C MR “ 1 ” C DDP C RS-FF1 RS-FF2 (Send in) (Ack_in) 2.3 5 “1” RS FF Rは、 DL Send out Ack in DL 2.4 C Q 1 Q2 Q 3 Q4 Q2 2.4 DDP 2.4
DDP
LSI FPGA DDP 2.4.1 LSI LSI [2] 1. 2. HDL 3. 4. 5. Description Language)[3] LSI HDL( Hardware HDL ● LSI Around Time . . Turn TAT DDP DDP FPGA FPGA 2.4 DDP PLD(programmable logic device) 2.5 1 LSI LSI LSI FPGA DDP PCI  LV DS(Low Volt age  Differential  Signaling) I/O FPGA LSI LSI 2.2 FPGA RT L LSI DDP 2.4 DDP

FPGA
2.4.2
F PG A DDP HD L (Renoir) (Model Sim) (Leonardo Spectrum) (Quartus) 2.6 FPGA . – . l DDP 2.5 2.5 C DDP FPGA LSI 3
3.1 C FPGA DDP FPGA 3.2 DL C F PG A 3.2 C C DL C 2 C C C C 3.1 AND “ 1 ” “0” Sendin 5 NAND “ 1 ” “0” DL “ 1 ” DL C C 1 2 C 3.2 DL 3.3 1/2 FPGA Send Ack LSI Send Ack 4 3.3 1 1      1 3.3 4 DDP CPS DDP [4]  FPGA 3.4) 3.4 3.4 2 C 1 C C 2 C C's C's C 3.3 C 3 2 C . . C 1 C 2 C C C C C C C 2 3.5 Pulse Generator Pulse Generator Copy Control DL Copy Control Copy DL 2 Send flg C Copy Control C D L C Pulse Generator Copy Control Pulse Generator C Send DL Copy Control 3.6 Copy Control 3.6 Copy Control Pulse Generator "," Pulse Generator “ 1 ” “ 1 ” u " → " 1 " 3.4 3.4 DDP MM CPS LSI 3.8 [4] 3.8 Send Ack C C C Send C FPGA Ack 1. 2. DL Ack C Ack Ack DL Ack Ack 3.9 3.4 3.9 Send Ack Ack Send 2 DL DL Circuit 3.1 0 DL AND “ 1 ” C Ack DL DL Ack 2 R RS-FF “ 1 ” 2 C Clear 3.5 C 2 RS-FFは、 RS-FF S  “1” 2 C Ack Ack 3 DL 2 DL 3.11 3.11 3.5 DDP FPGA F PG A
4.1 3 DDP DDP DDP 4.2 FPGA DDP DDMP4G 4.2.1 ●  OCP(operation  Code  Processor) . . . . . DDP ●  M(Flow  Mergeging  Module)[5] – 1 ● MM(Matching Memory) – CST(matching with constant) FC(matching with variables) ●  FP(Functional Processing Unit) - ● CPS(Cache Program Storage) - ●  D(Flow  Diverting  Module)[5] - D : Flow Diverting Module 4.1 DDP 4.2 DDP 4.2.2 DDP 4.2 DDP 4.3 MM FP RD
1259 4.2.3 DDP 4.1 4.4  FP CPS
4.3 4.3 4.3.1 M( Flow  Mergeging  Module) D Branch Input Path A Branch Input Path B MM
4.5
C NOR C DL C Out Put PathX FF NOR Input Path B :To Data Latch Arbitration Signal 4.5 Me rge Input Path A
Input Path A C
Send
Path
A⇒B Input Pat h A ⇒ Input Path C C Send Input Path A Input Path B Send Input Path A C ⇒ Input Path C Ack Send
4.3.2
MM(Matching Memory)
2 (Hash Memory)
2 Hash Memory 4.7 MM
4.3 ● Hash Address Generator – Operetion Code 2bit Destination Code Generation  ID 3bit ● CST – Destination Code CST Memory 2 ●  Flag Generator – Destination Code Generation  ID * * * 1 ●  Mode Selector –  Flag Generator * * * Low Wirte Enable ● Clear Control Control – MM 3 L/R
4.8 Hash Address Generator, CST input Packet Format
HC 4.9 CST output Packet Form at
HC 4.10 Flag  Generator in put  Packet  Format
Flag Generator output Packet Format L/R
4.12 Mode Selector output Packet Form at
Hash Memory input output Data Packet Format L/R

4.3.3
FP(Functional Processing Unit) 4.14
4.3.4
CPS( Cache  Program  Storage) Cache Program Memory CPS True node False node Cache Program Memory Format CPS F P True node False no de TG, FG Destination Code Cache Program Memory Destination Code DDP 4.3 ● Cache Program Memory – ●  Load Cache Program - Memory ● Verdict Code Generator - ● Clear Control – VCG Clear Circuit ● Clear Control Circuit - 3 ● Selector – ClearControl ● Copy Control Circuit - 3 CPS DL Cache  Program
4.17   CPS input Packet 4.6
4.7
VCG Code
4.19
Selector output Packt Format
4.3.5
D(Flow  Diverting  Module) M Merge DDP Merge OutputPathX Output Pat h Y Input Put Path A 4.21 Input P ath A C DL D- FF Control F LG Output PathX, Output PathY send NAND NAND
“ 1 ” Control FLG aカDL Control FLG X,Y Control FLG C Send

DDP
4.4
DDP . . . 4.4 DDP Memory HDL 4.22
HDL 4.9
4.5 4.5 DDP DDP DDP DDP HDL MM 1 5.1 4 DDP DD MP G DDP FPGA F PG A 5.2 DDMP4G DDP RGB Y Cr Cb DDP DDP FPGA =  )
+ . II DDMP4G 5.1
DDP
1
4 1 20 I/O [6] FPG A 5.2 Logic Cell Memory LC 16.85% DDP 1
LC DDP
20 FPGA 5 DDP DDP 5 5.3 5.3 FPGA DDP FPGA 20 F PG A
DDP FPGA DDP 6 6.1 1 LSI ASIC) DDP DDP FPGA DDP F PG A DDP C LSI 6.1 DDP FPGA FPGA DDP DDP FPG A 1. a DDP 1 DDP b CST Destination code 2. a Cache Program Memory b 1 DDP PE 3. 6.1 PE FPGA DDP DDP Ruck Thawonmas [1] H. Terada, S. Miyata and M. Iwata, "DDMP's: Self-timed Super-Pipelined Data- Driven Multimedia Processors ", Proc. of IEEE, Vol. 87, No. 2, pp. 282-296, Febru- ary 1999. [2] -
[3] Donald E. Thomas, Philip R. Moorby, "The Verilog Hardware Description Lan- guage", Kluwer Academic Publishers, 1995. [4]せ

, 1995.
[5] H. Kanekura, “Data junction and branching apparatus for an asynronous data transmission path" , U.S. Patent 5 396 638, March. 1995. [6] http://www.altera.com/products/devices/apex/apx-overview.html#1.8, APEX20KE Device Data Sheet