Abstract

Experimental
Introduction
The top priority in low power device design is a high current drive at very low supply voltage (Var < 0.5 V). The dynamic threshold SOI MOSFET (DTMOS) has an ideal subthreshold slope and a high current drive [ 1 ]. To enhance the current drive of DTMOS, a large body effect is essential, because DTMOS operating at V dd effectively operates at V dd +AV th, where AV th is the V th shift due to the body effect ob- tained by connecting gate to body [2]. However, it is very hard to attain a large body effect factor (Y=AVq, /AVq,) at low V th, because y is primarily determined by the ratio of gate oxide thickness to channel depletion layer width (Wd) which is reduced by high channel doping concentration. The pre- viously reported DTMOS's [1,3-5] have small ydue to low V h and do not take full advantage of high current drive inher- ent to DTMOS. In this study, we propose a novel Electri- cally Induced Body DTMOS (EIB-DTMOS) which achieves large yand low V b at the same time. Thin SOI layer thick- ness provides very large χ while V th is determined by impu- rity concentration in the SOI layer. Experimental and simu- lation results demonstrate the superiority of EIB-DTMOS to conventional DTMOS and normal SOI MOSFETs. Y is as high as 0.8 - 1 and V n can be set to around 0.1 V.
Device Structure
Fig. 1 shows schematic cross-sections of the proposed EIB-DTMOS in an inversion mode and an accumulation The body region is electrically induced (accumulated mode. in the inversion mode and inverted in the accumulation mode) by a static substrate bias at the back-interface in the The gate is tied to this electrically induced body SOI layer. via a body contact terminal. The back gates below buried oxide are fabricated by ion implantation through buried oxide [6,7]. In EIB-DTMOS, the channel depletion layer width Therefore, by thinning the (Wd) equals to the SOI thickness. SOI thickness, EIB-DTMOS can reduce W 4 and realize larger yand thus, higher current drive than the conventional DTMOS. The inversion mode EIB-MOSFET is compared with conventional fully depleted (FD) and partially depleted (PD) SOI MOSFETs by experiment. The devices measured are fully depleted SOI nMOSFETs fabricated on a SIMOX wafer [8]. Thicknesses of the gate oxide, SOI, and buried oxide are 10 nm, 40 nm, and 100 nm, respectively. The SOI layer is p-type with concentration in the order of 1016 cm 3 . A MOSFET is measured in three different modes (FD, PD, and EIB-DTMOS) by changing the bias conditions shown in Fig. 2 shows subthreshold characteristics in the Table I. three modes. EIB-DTMOS has the ideal subthreshold slope, and y is as high as 0.8 resulting from thin SOI thickness which corresponds to Wd. Fig. 3 shows V n rolloff and sub- threshold slope degradation by the short channel effect (SCE). EIB-DTMOS suppresses SCE very well, because drain de- pletion layer width is reduced by the forward body bias in DTMOS. In Fig. 4, on/off characteristics are compared. EIB-DTMOS shows high current drive and low off-current due to high y and steep subthreshold slope. These experi- mental results show EIB-DTMOS is superior to conventional FD and PD SOI MOSFETs.
Comparison with other DTMOS
In order to demonstrate advantages of EIB-DTMOS, four types of DTMOS shown in Fig. 5 are compared by de- vice simulation [9]. Type-A is a conventional DTMOS [1, 3-5] and type-C is a counter doped DTMOS [2,10]. Type-B and D are the inversion mode and accumulation mode EIB- DTMOS, respectively. Channel profiles of type-C and D can be realized by Sb ion implantation [11].
A. Inversion mode EIB-DTMOS
Fig. 6 shows the dependence of V th on yfor type-A and y of type-B has two times as large as that of type-A at B. fixed V n [12], because W d of type-B is half of that of type-A, The experimental result (Vo which is shown analytically. =0.45 V, y= 0.8) in the previous section is also plotted, which fits the simulation very well. However, V n of the experi- mental result is too high for supply voltage below 0.5 V. The decrease in V h leads to the decrease in yas shown in the Fig. 6. In the inversion mode EIB-DTMOS, therefore, the large yand low V th are not attained at the same time.
B. Accumulation mode EIB-DTMOS
To realize both large y and low V th , the accumulation mode device (type-D) is required. In type-D, the body re- gion is formed by electrically inverted carriers and W d is limited by thin SOI thickness. The carrier concentration of the body (holes for nMOS) could be very high and a very steep carrier profile is achieved. On the other hand, the conventional counterpart of type-D is a counter doped DTMOS (type-C), where not only the counter doped region but the body region is formed by the doping. Therefore, the body concentration is limited and it is very difficult to obtain a steep carrier profile. yof type-C and D are also plotted in Type-D has much higher ydue to the thin SOI layer Fig.6. and steeper carrier profile.
C. Body resistance
Body RC delay is a serious problem in DTMOS with wide gate width (We), because body potential doesn't follow the gate voltage and differs in the gate width direction in AC operation [3,5,13]. EIB-DTMOS also has the serious body RC delay. Body capacitance of EIB-DTMOS (type-B, D) is much lower than that of the conventional DTMOS (type-A, However, EIB- C), because p-n junction area is very small. DTMOS has higher body resistance (10~100 kΩ/□) than the conventional DTMOS (5~50 kQ/D) and bulk DTMOS (1~10 kΩ/□) [5], because the body is electrically induced only at SOI/buried oxide interface. Fig. 7 shows the channel donor concentration (ND4) dependence of front Vu, back Vu, 7, and body sheet resistance in the accumulation mode EIB-DTMOS By increasing ND4, front V th is lowered and 7 is (type-D). increased due to thinning of the effective SOI thickness, which results in higher current drive. However, high ND4 also leads to increased body resistance, because back V an is also lowered and the back-interface is not sufficiently invert- ed at a given negative substrate bias. To decrease the body resistance, higher substrate bias is needed but causes a reli- ability problem in buried oxide (E tox > 5 MV/cm) as shown in Fig. 7 (b). A low/high/low channel profile alleviates the problem. A DTMOS divided into n narrow MOSFETs with respective body contacts is also effective, because body re- sistance is proportional to n . . The effect of body resistance on the AC performance will be discussed later.
D. Performance
Fig. 8 shows V th rolloff and S degradation of type-A, B, C, and D with V ch of 0.12 V at L = 0.5 μm. SCE of type-D is the smallest. Fig. 9 shows on/off characteristics of the four types. Although the on-current for the four type is almost the same at fixed Lg, type-D shows three decades less off-current than type-A at L x = 0.07 µm due to suppressed SCE. Fig. 10 shows on/off characteristics of type-A, C, and D with the same off-current at L c =0.07 μm. Type-D shows one and a half times as high on-current as type-A due to large y in spite of much less DIBL in type-D as shown in the inset These results indicate that type-D has better of Fig. 10. performance than any other DTMOS at any conditions. Fig. 11 shows forward bias p-n junction current of
15.6.2
type-A, B, C, and D. Type-D shows the smallest leakage current due to very small junction area and high hole con- When the SOI thickness is thinned below 10 nm centration. in EIB-DTMOS to scale down Lg, leakage current will in- crease due to direct tunneling between electrons at the front interface and holes at the back interface [14]. Finally, we compare AC characteristics of type-C, and D by mixed-mode simulations. Fig. 12 shows the depen- Type-D is dence of the inverter delay on wire capacitance. faster than type-C, because type-D has higher current drive and lower junction capacitance. In Fig. 12, the effect of the When body resistance is negligible because Wg is narrow. W e is wider, the body RC delay becomes comparable to the gate delay and the body potential does not follow the gate When W, is voltage, resulting in slower propagation delay. much wider and body RC delay is much longer, the body po- tential will strongly depend on history of the input and output voltages and vary between 0 V and V as. In such a case, histo- ry dependent propagation delay and large power consumption due to low V th would be expected.
Conclusions
We have proposed the high performance EIB-DTMOS Electrically induced with large body effect and low V α . body with high carrier concentration at back interface and thin SOI layer reduces the channel depletion layer width and maximizes the body effect. Among several DTMOS's, the accumulation mode EIB-DTMOS shows the highest current drive at fixed off-current due to the large V a shift and the suppressed short channel effect.
Acknowledgements
T. Saraya and T. N. Duyet contributed greatly to the fabrication of the devices used in this work. This work was partly supported by JSPS Research for the Future Program.