| 1030174 ___ 15 2 24
57 60 61 64 66 67 68 1 Integrated Circuit 2 IC VHDL Very high speed integrated circuit Hardware Description Language 5 2 1 3 2 IC IC VHDL 4 5 FPGA IC FPGA 1 2 IC 2 IC Electronics Workbench Multisim 2001 PowerPro 2.1 1 2 3 4 1 “ 99  46 " ”“ 1/100 ”“ 1/10 a " " ” " ”“ 1/100 9 0 0 00 00.00 .. ,9 ”
” 0 00 00 00 2 00 00.00 59 59.99 1/100 1 SW1 ON   OFF Reset SW2 00 00.00 2 3 “ ” 99  46 BCD bit SW5 a " BCD SW4 SW6 00 00 00 SW7 4 SW3 SW SWITCH 1 7 2 1 LED 2 2
2.2 00 99 1/100 1 59 100 60 “ 1/100
99  66 " 60 99 " 00
00 00.00
,, "
2 1 7 LED 7
LED
2 1 “ 1/100 ”
3

± 25ppm CLOCK 4000 11 1 1 2.2.2 1MHz 1/1000 100Hz 2 2
4 4
2    3 2 4 6 AND 2 2 10 74HC160 CLK RCO Enable Enable RCO 74HC160 ENP RCO “ 1” RCO AND AND 2 5 RCO  AND RCO Enable AND RCO AND ENT 74HC160 AND 2 5 2 6
AND IC 74HC08 2 AND 74HC08 2 A B 2 7 74HC08
10
2.2.3 100 “ 1/100  ” 100Hz 74HC160 100 CLOCK 2 100 2.2.4 60 “ 1/100 RCO RCO AND Enable 60 8 74HC160 5 101 RCO 10 2 QC AND QA LOAD 2 IC Enable Enable CLK RCO AND ENP ENT Hi RCO 10 .. ," " ." 60 ,” 100 8 “ 2   99  46 2 60 60 2 5 “ " 5 11 CLK CLK 74HC160 9 08 RCO CLK 19 11 10 08 09 10 11 CLK RCO NAND LOAD IC NAND NAND 74HC00 74HC00 2 9
2 9 [5] 00 59 00 59 1 1 ON OFF a 99 66 60 60 ” " “ a “ " 60 a ,” SW5 SW4 SW5 60 SW4 CLOCK 2 10
12
60
2.2.5
4bit comparator 74HC85 4 74HC85 2 11 2 12 ao — (10) 0 ） COMP (12) A1 P 3 , < P<Q = P = Q
> P>Q
0 · Q B3 — (1)
2　12　74HC85
[5]
14
2 13 74HC85
[7] ” BCD BCD 7bit 7bit 74HC85 A=B IN    A=B OUT B 7bit 7bit A A=B 4 4 A=B OUT 2 14
2.2.6
“ 4bit Selector    multiplexor    74HC157 6 ,, " ”“ 1/100  ” BCD 7bit    7bit    8bit A BCD Select 7bit    7bit         B 74HC157 SW3 2 15 2 16
2 15 74HC157 [5]
16
2.2.7
LED BCD Selector 7 BCD to 7 Segment Decoder LED (Hi 74LS47 low 2 17 2 18 74LS47 6 Low 74LS47 ) 7 active 11 10 12 14 15 13 NUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS SEGMENT IDENTIFICATION
2 74LS47
[5]
2.2.8 7 SW1 SW2 SW3 SW4 SW5 SW6 SW7 2 SWITCH 1 3 ON OFF 4 SW1 SW3 SW6 3 SW2 SW4 SW5 SW7 19 2 10ms 2 19 a b SW1 SW3 SW6 SW4 SW5 1 1CLOCK CLOCK 2 20 2 3 RS FF b a 2 20(a) RS   FF S 1 S R 1 RS FF Q 1 Q 0 2 4 2 4 RS FF
CR 2 21 2 b Hi d 2 21 RS FF IC 10ms SW4 SW5 22 2 a SW2 SW7 b IC 6 74HC14 2 23 74HC14
Y
[5]
2.3
2 25

9ms
  a 100 b 60 2    26    100        60 2 26 100 60

a
2.4
1

2
2 27 2
155mm× 230mm

3
Hardware  Discription  Language HDL HDL ASIC ASIC FPGA PLD HDL VHDL
3.1 VHDL
Very high speed integrated circuit Hardware Description VHDL Language VHSIC    Very High Speed Integrated Circuit IEEE 1986 1981 LPM 1987       5 IEEE Std 1076 Language Reference Manual 12 1993 IEE Std 1164 VHDL VHDL
30
VHDL 3.2 3 1 VHDL 2 2 IC 1MHz IC VHDL FPGA SWITCH SW1 7 2 3 1
3.3
VHDL
Electronics Workbench VHDL Multisim VHDL Power Professional component 3.3.1 VHDL 3 1
VHDL 3 2 3 2 3 1 1ns 1/3 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
end BUNSYU; architecture RTL of BUNSYU is signal BCD1 : std_logic_vector(3 downto 0); signal BCD2 : std_logic_vector(3 downto 0); signal BCD3 : std_logic_vector(3 downto 0); signal BCD4 : std_logic_vector(3 downto 0); begin P1:process(CLK0,RESET) begin if(RESET='1') then BCD1 <= "000"; elsif(CLK0' event and CLK0='1') then if(BCD1 = "1001") then BCD1 <= "000"; else BCD1 <= BCD1 + 1; end if; end if; end process P1; P2:process(CLK0,RESET) begin if(RESET='1') then BCD2 <= "000"; elsif(CLK0' event and CLK0='1') then if(BCD1="1001") then if(BCD2 = "1001") then BCD2 <= "000"; else BCD2 <= BCD2 + 1; end if; end if; end if; end process P2; P3:process(CLK0,RESET) begin if(RESET='1') then BCD3 <= "000"; elsif(CLK0' event and CLK0='1') then if (BCD1="1001" and BCD2="1001") then if(BCD3 = "1001") then BCD3 <= "000"; else BCD3 <= BCD3 + 1; end if; end if; end if; end process P3; P4:process(CLK0,RESET) begin if(RESET='1') then BCD4 <= "000"; elsif(CLK0' event and CLK0='1') then if(BCD1="1001" and BCD2="1001" and BCD3="1001") then if(BCD4 = "1001") then BCD4 <= "000"; else BCD4 <= BCD4 + 1; end if; end if; end if; end process P4; P5:process(BCD1,BCD2,BCD3,BCD4) begin if(BCD1="1001" and BCD2="1001" and BCD3="1001" and BCD4="1001") then CLK1 <= '1'; else CLK1 <= '0'; end if; end process P5; end RTL; 3    2
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
SIM2:process begin RESET <= '1';
end SIM; 3    2 3 2(a) CLK=' 1' 3  2(b) CLK0 10000 1ns 10us CLK1 3.3.2 Decoder 4bit 0 9 BCD 3　2　 BCDto7SegmentDecoder 7bit 3
2
BCD to 7 Segment Decoder

BCD
Decoder 0 9 case “ 1/100 1946 "
(4bit) (4bit) BCD to 7 2 Segment Decoder 2
VHDL 3 
 
 BCD to 7 Segment Decoder 3 4 
 
 3 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity BCDto7segDecoder is port( BCD     : in std_logic_vector(7 downto 0); SEG1   : out std_logic_vector(6 downto 0); SEG10 : out std_logic_vector(6 downto 0) ); end BCDto7segDecoder; architecture RTL of BCDto7segDecoder is signal INDATA1    : std_logic_vector(3 downto 0); signal INDATA10 : std_logic_vector(3 downto 0); begin INDATA1  <=  BCD(3 downto 0); INDATA10<=  BCD(7 downto 4); Decoder1:process(INDATA1) begin case INDATA1 is when "000" => SEG1 <= "111110";  --0 when "0001" => SEG1 <= "0110000";  --1 when "0010" => SEG1 <= "1101101";  --2 when "0011" => SEG1 <= "111001";  --3 when "0100" => SEG1 <= "0110011";  --4 when "0101" => SEG1 <= "1011011";  --5 when "0110" => SEG1 <= "101111";  --6 when "0111" => SEG1 <= "1110010";  --7 when "1000" => SEG1 <= "111111";  --8 when "1001" => SEG1 <= "111011";  --9 when others => SEG1 <= "000000";  --X end case; end process Decoder1; 2/2
end RTL; 3   4   BCD to 7 Segment Decoder library ieee;
entity TEST_BCDto7segDecoder is end TEST_BCDto7segDecoder; architecture SIM of TEST_BCDto7segDecoder is component BCDto7segDecoder port( BCD     : in std_logic_vector(7 downto 0); SEG1   : out std_logic_vector(6 downto 0); SEG10 : out std_logic_vector(6 downto 0) ); end component; signal BCD      : std_logic_vector(7 downto 0); 1/3
3/3
BCD <= "1111000";    wait for 10ns;   --F0 wait; end process S1; end SIM; 3　3　BCD to 7 Segment Decoder BCD 8bit INDATA10　4bit INDATA1  4bit     , SEG1 SEG10 3.3.3
3 4

Selector  Comparator component 3 5 3 6 3 5 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Total is CLK,SW1,RESET_SW       : in std_logic; port( A_CLK1,A_CLK2,RESET_ALARM     : in std_logic; SEL                 : in std_logic; ALARMOUT : out std_logic; SEG_OUT1 : out std_logic_vector(6 downto 0); SEG_OUT2 : out std_logic_vector(6 downto 0); SEG_OUT3 : out std_logic_vector(6 downto 0); SEG_OUT4 : out std_logic_vector(6 downto 0); SEG_OUT5 : out std_logic_vector(6 downto 0); SEG_OUT6 : out std_logic_vector(6 downto 0) ); end Total; architecture RTL of Total is component BUNSYU port(    CLK0   : in std_logic; RESET: in std_logic; CLK1   : out std_logic ); end component; component BCDto7segDecoder port(    BCD    : in std_logic_vector(7 downto 0); SEG1   : out std_logic_vector(6 downto 0); SEG10 : out std_logic_vector(6 downto 0) ); end component; signal CLK_SW     : std_logic; signal BCD_a1       : std_logic_vector(3 downto 0);
3 5 3/9 BCD(7 downto 0) => BCD_IN(15 downto 8), SEG1(6 downto 0) => SEG_OUT3(6 downto 0), SEG10(6 downto 0) => SEG_OUT4(6 downto 0) ); --- ---minit 7SegDecoder --- P3: BCDto7segDecoder port map( BCD(7 downto 0) => BCD_IN(23 downto 16), SEG1(6 downto 0) => SEG_OUT5(6 downto 0), SEG10(6 downto 0) => SEG_OUT6(6 downto 0) ); --- --Stopwatch_0.01second --- a1:process(CLK_SW,RESET_SW) begin if(RESET_SW='1') then BCD_a1 <= "000"; elsif(CLK_SW' event and CLK_SW='1') then if(SW1='1')then if(BCD_a1 = "1001") then BCD_a1 <= "000"; else BCD_a1 <= BCD_a1 + 1; end if; end if; end if; end process a1; a2:process(CLK_SW,RESET_SW) begin if(RESET_SW='1') then BCD_a10 <= "000"; elsif(CLK_SW' event and CLK_SW='1') then if(SW1='1' and BCD_a1="1001") then 3 5 4/9 if(BCD_a10="1001") then BCD_a10 <= "000"; else BCD_a10 <= BCD_a10 + 1; end if; end if; end if; end process a2; a3:process(SW1,BCD_a1,BCD_a10) begin if(SW1='1' and BCD_a1="1001" and BCD_a10="1001") then CIN_b <= '1'; else CIN_b <= '0'; end if; end process a3; --- --Stopwatch_second --- b1:process(CLK_SW,RESET_SW) begin if(RESET_SW='1') then BCD_b1 <= "000"; elsif(CLK_SW' event and CLK_SW='1') then if (CIN_b = '1') then if(BCD_b1 = "1001") then BCD_b1 <= "000"; else BCD_b1 <= BCD_b1 + 1; end if; end if; end if; end process b1; b2:process(CLK_SW,RESET_SW) begin if(RESET_SW='1') then 3 5 5/9 BCD_b10 <= "000"; elsif(CLK_SW' event and CLK_SW='1') then if (CIN_b='1' and BCD_b1="1001") then if(BCD_b10 = "101") then BCD_b10 <= "000"; else BCD_b10 <= BCD_b10 + 1; end if; end if; end if; end process b2; b3:process(CIN_b,BCD_b1,BCD_b10) begin if(CIN_b='1' and BCD_b1="1001" and BCD_b10="101") then CIN_c <= '1'; else CIN_c <= '0'; end if; end process b3; --- --Stopwatch_minutes --- c1:process(CLK_SW,RESET_SW) begin if(RESET_SW='1') then BCD_c1 <= "000"; elsif(CLK_SW' event and CLK_SW='1') then if (CIN_c = '1') then if(BCD_c1 = "1001") then BCD_c1 <= "000"; else BCD_c1 <= BCD_c1 + 1; end if; end if; end if; end process c1; c2:process(CLK_SW,RESET_SW) begin if(RESET_SW='1') then BCD_c10 <= "000"; elsif(CLK_SW' event and CLK_SW='1') then if (CIN_c='1' and BCD_c1="1001") then if(BCD_c10 = "101") then BCD_c10 <= "000"; else BCD_c10 <= BCD_c10 + 1; end if; end if; end if; end process c2; --- --ALARM_Second --- d1:process(RESET_ALARM,A_CLK1) begin if(RESET_ALARM='1') then BCD_d1 <= "000"; elsif(A_CLK1' event and A_CLK1='1') then if(BCD_d1 = "1001") then BCD_d1 <= "000"; else BCD_d1 <= BCD_d1 + 1; end if; end if; end process d1; d2:process(RESET_ALARM,A_CLK1) begin if(RESET_ALARM='1') then BCD_d10 <= "000"; elsif(A_CLK1'event and A_CLK1='1') then if (BCD_d1="1001") then if(BCD_d10 = "101") then 3 5 7/9 BCD_d10 <= "000"; else BCD_d10 <= BCD_d10 + 1; end if; end if; end if; end process d2; --- --ALARM_minutes --- e1:process(RESET_ALARM,A_CLK2) begin if(RESET_ALARM='1') then BCD_e1 <= "000" ; elsif(A_CLK2'event and A_CLK2='1') then if(BCD_e1 = "1001") then BCD_e1 <= "000"; else BCD_e1 <= BCD_e1 + 1; end if; end if; end process e1; e2:process(RESET_ALARM,A_CLK2) begin if(RESET_ALARM='1') then BCD_e10 <= "000"; elsif(A_CLK2'event and A_CLK2='1') then if (BCD_e1="1001") then if(BCD_e10 = "101") then BCD_e10 <= "000"; else BCD_e10 <= BCD_e10 + 1; end if; end if; end if; end process e2; ---
3 5 9/9 BCD_IN(23) <= '0'; end if; end process SELECTOR; end RTL;
3/3
end SIM; CLK CLK_SW 5 9 5 5 VHDL CLK CLK_SW  <= CLK 3 4 029 60.5us 60.4us 60.3us 60.2us
b 3 4 a Comparator RESET_ALARM Comparator “  ." SEL ' 1' Selector Selector Reset RESET_SW Reset “  ALARMOUT SEL=' 0' BCD_IN 3 4 b “ 1/100    ”     “      ” CIN_ “  CIN_ 00 59 59 01     00     00 3.4
FPGA
3.4.1  FPGA VHDL ICP ALTERA aritec FPGA FPGA EPM9320LC84-15 ALTERA ISP-01-9320-84 3 5 EPM9320LC84-15 3 6

3　6　EPM9320LC84-15

EPM9320LC84-15 84 FPGA GND I/O 3 7
8
3

58

3.4.2  FPGA FPGA FPGA I/O VHDL DIN1 GCLK1 DIN2   GCLK2 DIN3   GCLR 3 9
MAX plus
3.5
1
2 3 5 2 9.5× 14.5mm
3 6 4 2 IC 3 FPGA FPGA 4　1 IC FPGA 4　1 5.00V IC
5.00V 258.3mA FPGA IC 160.9mA 7
FPGA IC IC CMOS  IC FPGA 74HC14 IC 34
IC IC33 FPGA PIN IC IC IC FPGA FPGA IC IC IC VHDL IC FPGA FPGA 2.54mm FPGA 5 IC VHDL VHDL FPGA VHDL IC FPGA VHDL IC [1] [2] [3] [4] 2000
CQ
[5]  TEXAS INSTRUMENTS http://www.ti.com/   http://www.tij.co.jp/ [6]  HITACHI Semiconductor Products http://www.hitachisemiconductor.com/sic/servlet/request [7] http://www.semicon.toshiba.co.jp/prd/logic/ft  logic.html [8] VHDL CQ