1. Introduction
A tunneling field effect transistor (TFET) is drawing attention with the expectation that a TFET circuit provides better energy efficiency than a normal MOSFET counter- part by reducing leakage in ultra-low supply voltage (V DD ) domain [1]. Fig. 1 shows calculated power-delay (PD) product, that is, the energy of TFET and MOSFET logic circuits. ξ is an effective time ratio and normally around 10 3 for logic [2]. V OPT is the voltage at which the energy is minimized, and V OPT of TFET logic circuits is 0.1V as in- dicated in Fig. 1. Thus, the circuit must be operated at V DD =V OPT to achieve the maximum energy efficiency. However, such ultra-low V D  operation could cause func- tional errors. A minimum operatable voltage (V DDmin ) is the lowest voltage at which these functional errors do not occur [3]. When V D min is higher than V OPT , minimum energy operation is not achieved. Therefore, investigations on V DD min are essential for ultra-low V DD TFET logic circuits. Although variations in TFET devices have been analyzed in [4], it is not clear how such variations affect V DDmin . In this paper, V DDmin of TFET logic circuits due to the within-die threshold voltage (V tH ) variation (σ v ) is investigated for the first time, and based on the investigation, the design guideline for TFET circuits is presented. 2. TFET model used for simulation with V TH variability To perform TFET circuit investigation under V TH vari- ability, a device model is needed. A measured Si TFET device as an example is shown in Figs. 2 and 3. A compact model is elaborated and is implemented as a SPICE Veri- log-A model, whose calculation result is shown in Fig.4 and shows good agreement with the measurement [5,6]. Discrepancy in very low current region is due to the gate ² Green Nanoelectronics Center, AIST Tsukuba, Japan leakage but the region is not used in the simulations in this paper. With this manufactured device, however, it is im- possible to achieve steep-S feature at ultra-low V DD region. Thus, in the simulation below, a work function parameter is modified and Si is changed to Ge to enable low V DD opera- tions. The resultant I DS-V DS characteristics which are used in this paper are shown in Fig. 5. I DS-V GS characteristics in Figs. 5 (c) and (d) show the cases when V TH is shifted by ±30mV through changing the work function parameter. The exact physical origin of the V TH variation is not in focus here but rather the existence of the V TH variation is important since V TH changes the cur- rent exponentially, which in turn affects the circuit behavior strongly. The compact model, being different from a table model, enables the V TH variability simulation. 3. Minimum operatable voltage (V DDmin) of logic circuits The closed-form expression for estimating V DDmin for MOSFET logic circuits has been proposed in [3]. Since I-V characteristics of TFET’s in low V D S region differ from those of conventional MOSFET’s, an approximate expres- sion of I DS characteristics of TFET's is introduced and shown in Fig. 6 to derive V DDmin expression for TFET logic circuits. Strictly speaking, S has voltage dependence in TFET as shown in Fig. 6. However, the voltage dependence is small at ultra-low V D . Hence, S is approximated as an average over OV and 0.1V. The derived V DDmin expression for TFET logic circuits is shown in Fig. 7. Fig. 7 shows V DDmin 's of TFET inverter chains obtained by Monte Carlo simulations with the compact model and by the V DDmin expression. Monte Carlo simulations to obtain V DD min in this paper comply with the procedure described in [3]. The coincidence of theory and simulation show the validity of the approximation illustrated in Fig. 6. The V DD min dependence of TFET logic circuits on the number of gates and σντ is same as that of MOSFET logic circuits. The derivation is based on inverters but it was shown that the expression works well with NAND’s and NOR’s [3]. In order to achieve minimum energy operation, circuits must be functional at V OPT , that is, V DDmin is less than V OPT . The expression of V OPT for conventional MOSFET circuits has been derived in [7]. In this paper, V oPt for TFET logic circuits is derived by using the approximate I DS characteris- tics of TFET’s shown in Fig. 6. From the expressions of V DD min and V OPT , OVT max , which is the maximum σ T for V DDmin<V OPT , is derived. Fig. 8 shows σντ,παx for 1M and 10B-gate logic circuits, which indicates that V TH variation must be reduced as S becomes steeper. With TFET tech- nology described in this paper (S=30mV/dec), σντ,max is l 5mV for 1M-gate logic circuits, that is, σVT has to be con- trolled within 15mV to achieve operation at V OPT of 0.1 V.
Acknowledgements
This research is partly granted by JSPS through FIRST Pro-