Abstract

l. Introduction
It is generally expected to achieve smaller wiring pitch, higher operating speed (>3.1 GHz), larger chip area (>310 mm²), larger number of flip-chip pads (>4000), and smaller area array flip-chip pad pitch (<0.15 mm) in future advanced ULSIs [1]. In contrast, the wiring pitch dimensions in ULSI packages are not scaled down so much, mostly because of the cost and registration accuracy issues. Therefore, as this trend proceeds, the following subjects should be taken into account: 1) the design rule mismatch between ULSIs and packaging substrates [2], and 2) the power supply voltage drop (IR-drop) in ULSI chips at high speed operation. The design rule mismatch between ULSIs and packages makes it very difficult to produce high-density and fine-pitch advanced packaging substrates. The stable fabrication of the packaging substrate wirings smaller than 20 μm in width is especially difficult, Because of this mismatch, the flip-chip pad pitch on the surface of ULSIs should be expanded to fit the design rule of packaging substrates. Consequently, the number of wiring layers inside ULSIs increases unnecessarily, resulting in high chip fabrication cost. The IR-drop in ULSI chips becomes larger for smaller pitch wiring, higher operating speed, and larger chip area. Power supply wiring and global interconnect resistance especially influence the IR-drop and signal delay [ 1 ]. Lower resistance wirings with larger width and thickness are needed for these wirings. Although present ULSIs have several layers of power supply wiring for the reduction of circuit resistance [3], the improvement in IR-drop is not sufficient. To solve these problems, we have developed a package-process-oriented multilevel thick Cu winng technology with electroplated Cu of the thickness of 5 μm and photosensitive resin without using CMP process, to replace conventional power supply wiring in high-speed ULSIs. Figure 1 shows the concept of our multilevel thick Cu Since this technology has 20-μm-pitch Cu wiring technology. with 5-μm thickness, it is expected to reduce the number of power or ground pads of ULSIs by connecting common circuits, in order to solve the design rule mismatch. Also, the IR-drop in ULSI chips is expected to be improved. In this paper, we describe our thick Cu wiring process technology and discuss the IR-drop evaluation results.
II. Multilevel thick Cu wiring technology
A. Multilevel wiring process
The thick Cu wiring technology is based on our packaging substrate technology, reported as deposited substrate on laminate (DSOL) previously [4]. The main features are pulse periodic reverse (PPR) Cu electroplating process and high-resolution photosensitive epoxy resin for interlayer dielectric. The former makes it possible to eliminate barrier metal layer used in conventional Cu interconnect, and to control Cu thickness on the wafer without CMP process. The latter contributes to develop low-cost process without using dry etching step. Figure 2 shows our thick Cu wiring process for one layer. The photosensitive resin is coated on the wafer with CMOS transistors and several Cu or Al wiring layers. After photolithography for via-hole fabrication and curing, a seed layer is sputtered. Then, thick photoresist are patterned and Cu is plated by PPR Cu electroplating. Since the Cu thickness is fairly large, the photoresist thickness should be 10 μm. After stripping photoresist, the seed layer is removed by wet etching, and no CMP process is needed. An aligner-type exposure system is used to expose an entire 8-inch wafer simultaneously, so that the throughput and process cost are much better, compared to using an ordinary stepper system. Three layers of wiring are fabricated by repeating this flow
B. PPR Cu electroplating
When the thick Cu wiring is electroplated only at the designated area, opening pattern regulated by photoresist and its density affect the uniformity of Cu thickness. Moreover, an electric charge concentration generally occurs at the top edge of the via-holes, and this uneven electric field is not suitable for stable via-hole electroplating smaller than 20 μm in diameter. In the PPR Cu electroplating process, the input current waveform is controlled during plating, as shown in Fig. 3. Cu ions and additives move to the anode side during minus current step, and the electric charge concentration during plus current The thickness uniformity is better than the step is suppressed. conventional direct current (DC) Cu electroplating used in the When the target thickness is 5 μm on an packaging process. 8-inch wafer, the thickness variation by PPR Cu electroplating is less than 2 μm, compared to that of 5 μm or more by conventional DC Cu electroplating.
C. Interlayer dielectric material
Via-hole resolution, in other words, the aspect ratio is an important characteristic regarding the connectivity of the thick Cu wiring to the ULSI inner wiring. Several kinds of resin have been evaluated, in terms of internal stress, endurance for plasma treatment, and organic solution resistance.  Finally, a negative-type epoxy resin is selected. Table 1 shows the epoxy resin characteristics.
This epoxy resin has the advantages of low dielectric constant of 3.2, low dissipation factor of 0.002, and high Glass transition temperature of 230 °C. In particular, a remarkable property is excellent via-hole resolution, so that 10-μm diameter via-holes are fabricated for the connection to the ULSI inner wiring. Since the curing temperature of epoxy resin is as low as 160 °C, ULSIs are not thermally influenced. High temperature and humidity bias tests (HHBTs) are performed to estimate the insulation reliability of the resin, using line-and-space patterns. The test patterns are 20-um-pitch Cu wiring with 5-um thickness covered with The applied voltage, temperature, and 8-μm-thick resin. reiative humidity are 10 V, 85 °C, and 85 %, respectively. Figure 4 shows the insulation resistance for ten samples as a function of time. The resistance of the insulation remains excellent value, approximately 1x1013 Q, over a period of 1000 hours. There is little variation in resistance among the samples. From this result, this resin prevents Cu migration under an ULSI operating condition.
Ill. Thick Cu wiring ULSI and electrical properties
A. Test structures
Four types of test structure were prepared for the IR-drop The basic structure, named as M3 shown in Fig. evaluation. 5(a), consists of 0.13-um CMOS transistors and conventional three layers of 0.5-μm-thick Al wiring. ・On this M3 structure, additional wiring of two layers of 0.5-pm-thick Al, one layer of 5-um-thick Cu, and three layers of 5-um-thick Cu were fabricated for M5, TEG-1, and TEG-2, respectively. Table 2 shows the design rule for thick Cu wiring. Chip and IR-drop evaluation circuit photographs for TEG-2 are shown in Fig. 6(a). Cross-sectional SEM images of Cu and Al wirings are shown in Fig. 6(b). The thick Cu wiring dimensions are larger than that of Al wiring. The epoxy resin surface is approximately flat without polishing, because it has excellent surface planarization characteristics.
B. IR-drop evaluation
The resistance of power supply wirings, R, is evaluated by measuring the circuit current, I ah for each test structure, in order to investigate the IR-drop, as shown in Fig. 7. The resistance reduction, AR, is defined as follows:
AR = R x - R x g   (X = M5, TEG-1, TEG-2)
, where R xo, R xo, R teg i, and R teg .2 denote the resistances of power supply wiring for M3, M5, TEG-1, and TEG-2, respectively. The clock frequency, fclock, and power supply voltage, Vas are 1 GHz and 1.5 V, respectively, and a switching capacitance, Comich, is estimated to be 1 nF. The AR values are relatively plotted in Fig. 8, with regarding M5 as standard. The proposed Cu wirings of TEG-2 successfully demonstrate the reduction of power supply resistance five times as large as that of the conventional two layers of Al wirings of M5. Even the TEG-1 with one thick Cu wiring layer shows the resistance
IV. Conclusion
A multilevel 5-μm-thick Cu wiring technology was successfully developed and the improvement in the resistance of ULSIs power supply wirings was demonstrated. The PPR Cu electroplating and photosensitive resin made a simple process flow and low cost fabrication possible. This technology is believed to provide not only advanced ULSIs with stable power supply wirings and higher speed operation, but also connectivity between ULSIs and packaging substrates and possible wiring in System-in-Package.
Acknowledgements
We thank Mr. Hirofumi Sasaki for his encouragement and also thank Mr. Keiichiro Kata, and Mr. Kazuhiro Baba for their useful suggestion and fruitful discussion. [1] [2] [3]