I.  INTRODUCTION
Digital gate drivers (DGD) ICs, which digitally change the gate current ( I G ) multiple times in fine time slots during the switching period of power devices, are attracting attention as a technology that can solve the trade-off problem between loss and noise during power device switching [1-10]. In all conventional DGD ICs [1-9], the IG range and resolution are fixed for each IC. Different power devices require different I G ranges and resolutions, which means that DGD ICs must be redesigned for each power device, which has been one of the challenges for the practical application of DGD ICs. For example, in a 6-bit DGD IC, when more than half of the maximum Ig is not needed, the most significant bit is not used, and the IC operates as a 5-bit DGD, thereby preventing DGD from fully utilizing the original 6-bit IG controllability. Generalizing this, when the maximum I G required by the user is x times (0 < x < 1) the maximum I G of the DGD ICs, then log 2 (1/x) bits are unused and wasted. To solve the problem, the variable I G range DGD (VIR-DGD) IC was proposed in [10]. In [10], the trade-off problems between loss and noise during the turn-on switching in two types of IGBT modules with twice the rated current have been successfully solved by an active gate driving using the same VIR-DGD IC. In this paper, this VIR-DGD IC is applied to SiC MOSFETs for the first time. Specifically, by using the same VIR-DGD IC, the trade-off problems between loss and noise during the turn-on switching in two types of SiC modules with 2.6 times different rated current have been successfully solved. Parallel-in serial-out shift register (PISO) Прмоѕ：Integer from 0 to 63 /1BIT：Any number between 7.0 mA and 70 mA ton, toff generator (TGEN) Fig. 1. Circuit schematic of variable I G range DGD (VIR-DGD) IC [10].
II.  V ARIABLE G ATE C URRENT R ANGE D IGITAL G ATE
Driver IC
Figs. 1 and 2 show a circuit schematic and a timing chart of VIR-DGD IC [10], respectively. In the following, turn- on is discussed for simplicity, whereas the exact same is true for turn-off. In [10], the gate driver output was – 15 V to 15 V to drive IGBTs, while in this paper the gate driver output is 0 V to 18 V to drive SiC MOSFETs. In VIR-DGD IC, V GS (PMOS) amplitude of the 6-bit pMOSFETs in the output stage is changed with the analog voltage (CONT PMOS ) via a variable resistor ( R 2 ) on PCB to realize a variable IG function. VIR-DGD IC has a ton , toff generator (TGEN), which generates the timing signal that define the time slots ( ton ) of the DGD using on-chip voltage controlled oscillators. Though not shown in Fig. 1, toN can be changed by varying the analog voltage (CONT ON ) via a variable resistor on PCB. The equation for IG is shown in Fig. 1. The innovation of the VIR-DGD IC was that it can always achieve 6-bit controllability for a wide variety of power devices, because the 1-bit IG ( I IBIT ) is variable by changing VGS (PMOS) amplitude [10]. As shown in Fig. 2, I G can be changed 9 times with 6 bits (= 64 levels) in a ton time slot. Fig. 3 shows a die photo of VIR-DGD IC [10] fabricated with 180-nm BCD process. The die size is 2.0 mm by 2.5 mm.
III.  MEASURED RESULTS
Fig. 4 shows the measured npmos dependence of I G at four different I 1 BIT values from 7.0 mA (minimum value) to 70 mA (maximum value), where npmos is a 6-bit control bit of I G and is an integer from 0 to 63. Fig. 4 shows the full 6-bit resolution of I G over all ranges from 0.44 A to 4.4 A. Figs. 5 and 6 show a circuit schematic and a measurement setup of the double pulse test using the developed VIR-DGD IC and an SiC module at 600 V, respectively. To demonstrate the broad applicability of the VIR-DGD IC, the same VIR-DGD IC with varied I 1BIT is applied to two types of SiC modules (SiC1 and SiC2) with 2.6 times different rated current, as shown in the table in Fig. 5. Figs. 7 (a) and (b) show timing charts of conventional single-step gate driving (SGD) and proposed active gate driving (AGD) at turn-on for comparison, respectively. In SGD, n is varied, which emulates a conventional gate driver with varied gate resistance. In AGD with 50 ns × 4 slots and a last long slot, four parameters ( n 1 to n 4 ) are varied. Note that [10] used AGD with 140 ns × 4 slots to drive IGBTs, while this paper uses AGD with 50 ns × 4 slots to drive SiC MOSFETs, which switch faster than IGBTs. ton can be changed from 140 ns to 50 ns by varying the analog voltage (CONT ON ) via the variable resistor on PCB. Figs. 8 (a) and (b) show the measured switching loss (E LOSS ) vs. drain current overshoot ( I OVERSHOOT ) of the conventional SGD and the proposed AGD in SiCl (load current ( I L ) = 70 A, I IBIT = 35 mA) and SiC2 ( I L = 28 A, I 1BIT = 14 mA) at turn-on, respectively. The black curves show the trade-off curves for SGD with varying n . In this paper, an evaluation function ( fobj ) shown in Eq. (1) [1-2, 9] is defined as a performance index of gate driving, and it is discussed that a gate driving with small fob」 is an excellent gate driving with small E LOSS and I OVERSHOOT.
l overshoot I OVERSHOOT, MAX (1) where the subscript MAX signifies the maximum of the corresponding quantity. The dotted concentric curves in Fig. 8 show the contour of fobj. In the proposed AGD, the
double pulse tests are repeated more than 2500 times, and each time E LOSS and I OVERSHOOT are measured to calculate fobj defined in Eq. (1), and the combination of the four parameters ( n 1 to n 4 ) that minimizes fobj is searched using the simulated annealing algorithm [1]. In Fig. 8 (a), Point C is the best point with the smallest fobj. Points A and B are the conventional SGD points with I OVERSHOOT and E LOSS approximately the same as the proposed Point C, respectively. Similarly, in Fig. 8 (b), Point F is the best point with the smallest fob」. Points D and E are the conventional SGD points with Iovershoot and Eloss approximately the same as the proposed Point F, respectively. In SiCl and SiC2, compared with the conventional SGD, the proposed AGD using the same VIR-DGD IC reduces E LOSS by 60 % and 47 % under Iovershoot-aligned condition and reduces Iovershoot by 57 % and 42 % under ELOSS-aligned condition, respectively. Fig. 9 shows measured waveforms of Points A to C in Fig. 8 (a). In Fig. 9 (c), the proposed AGD (Point C) achieves low Eloss and Iovershoot by setting npmos to 1 just before the timing of Iovershoot. Fig. 10 shows measured waveforms of Points D to F in Fig. 8 (b). In Fig. 10 (c), the proposed AGD (Point F) achieves low ELOSS and Iovershoot by setting npmos to 13 just before the timing of I OVERSHOOT . Table I shows a comparison table of DGD ICs. In this paper, VIR-DGD IC [10] demonstrated in IGBTs is applied to SiC MOSFETs for the first time. In conclusion, [10] and this paper demonstrate that the same VIR-DGD IC can properly perform the digital active gate driving for two types of IGBTs (1200 V, 100 A rating and 1200 V, 50 A rating) and two types of SiC MOSFETs (1200 V, 204 A rating and 1200 V, 80 A rating) with full 6-bit resolution, which proves the broad applicability of the proposed VIR- DGD IC.
IV.  CONCLUSIONS
VIR-DGD IC, which can always achieve 6-bit IG controllability for a wide variety of power devices, is applied to SiC MOSFETs for the first time. To demonstrate the broad applicability of the VIR-DGD IC, the same VIR-DGD IC with varied I 1 BIT is applied to two types of SiC modules including SiCl (204 A rating, I L = 70 A, I IBIT = 35 mA) and SiC2 (80 A rating, I L = 28 A, I IBIT = 14 mA). In the turn-on measurements of SiCl and SiC2 at 600 V, compared with the conventional SGD, the proposed AGD using the same VIR-DGD IC reduces E LOSS by 60 % and 47 % under I OVERSHOOT-aligned condition and reduces Iovershoot by 57 % and 42 % under E LOSS-aligned condition, respectively.
A CKNOWLEDGMENT
This work was partly supported by NEDO (JPNP21009).