I. Introduction
N UB-THRESHOLD circuits, which operate at a lower sup- ply voltage (VDD) than threshold voltage (VTH), are one of promising solutions to achieve ultra-low power oper- ation [1]. When V D  is reduced from the above-threshold region  to  the  sub-threshold  region,  the  gate delay variations (= sigma/average(= σ / μ )) due to the within-die random V H variation sharply increase [2], because the sub-threshold current has an exponential dependence on V T H . In the sub-threshold logic circuits, the average ( μ ) and the variation ( σ / μ ) of the gate delay increase with decreasing temperature [3]. Therefore, the worst-case μ as well as the largest σ/μ is observed at low temperatures (e.g., −40 °C), a variability analysis at the worst-case temperature is required. Therefore, in this paper, the temperature dependence of 256 within-die random gate delay variations (σ/μ) in sub-threshold logic circuits is measured in 40-nm CMOS test chips and is explained with a newly developed model. It is found that σ / μ in sub-threshold logic circuits is proportional to 1 / T for the first time, where T is the absolute temperature. This paper is organized as follows. Section II describes silicon measurements of the within-die distribution of the os- cillation periods of ring oscillators (ROs) and the calculation of random component of the gate delay variations. In order Fig. 1.  Chip micrograph and layout of the device matrix array (DMA) test chip in 40-nm CMOS. to investigate the dependence of the gate delay variation on temperature at low VDD, a new model of the temperature de- pendence of the gate delay variations is proposed in Section III. Finally, Section IV concludes this paper.
II.  MEASUREMENT OF WITHIN-DIE RANDOM
G ATE D ELAY V R IATIONS
A.  Test Chip Design
In order to measure the within-die random variation of the gate delay dependence on the supply voltage and the tem- perature efficiently, a device matrix array (DMA) test chip is designed and fabricated in 40-nm low-Vth (LVT) CMOS technology. Fig. 1 shows the chip micrograph and layout. The device under testing is a 16 × 16 array with a 2.1-mm square. Each unit with a 130- μ m square includes eight-type ROs. Fig. 2 shows a schematic of the DMA. The oscillation periods of ROs are measured and the variability among 256 ROs is analyzed. The ROs are in the variable supply voltage region and the output of ROs are level-shifted to the nominal voltage (= 1.1 V). The measured eight-type ROs and measurement conditions are shown in Table I and Table II. The 11-stage ROs at 0.7 V and 1.1 V, and 31-stage ROs at 1.1 V, are not measured, since the oscillation frequencies are too fast to be measured in our measurement setup. Two-input NAND gate with ×2 drivability and two-input NOR gate with ×2 drivability are used. These ROs are designed so that the every gate has the same fan-out.
TABLE II M EASUREMENT C ONDITIONS Supply voltage [V] 0.3 / 0.5 / 0.7 / 1.1 -40 / -20 / 0 / 25 / 50 / 85 Temperature [°C]
B.  Measurement Results
Fig. 3 shows the measured dependence of the normal- ized σ / μ of the oscillation period on the number of stages ( N ) at V DD = 0.5 V and 25 °C. σ /μ is normalized to the 11-stage RO. In order to separate the random variability com- ponent and the systematic variability component from the mea- sured raw data, the fourth-order polynominal fitting proposed in [4] is used in this paper. The extracted random component is inversely proportional to the square root of N , which confirms the validity of the separation. Figs. 4 and 5 show the measured temperature dependence of normalized mean (μ) and variation (σ/μ) of nand and NOR gate delay with different V D , respectively. In Figs. 4 and 5, μ and σ/μ are normalized to the NAND gate at 1.1 V and 25 °C. In Fig. 4, the worst-case (= largest) μ is observed at 0.3 V and −40 °C, where the normalized μ is more than 10 4 . In Fig. 5, the worst-case (= largest) σ / μ is also observed at 0.3 V and −40 °C, where the normalized σ /μ is more than 10. In the NAND gate at 0.3 V, σ / μ at −40 °C is 1.4 times of that at 25 °C, and 1.8 times of that at 85 °C. The temperature de- pendence of σ/μ in the sub-threshold logic circuits is not negligible. Therefore, the temperature dependence of σ/μ is modeled in the next section.
III.  Modeling of Temperature Dependence
OF GATE DELAY VARIATIONS
A.  Temperature Dependence of Gate Delay Variations in the Above-Threshold Region In this section, σ / μ of the gate delay in the above-threshold region is modeled. In the above-threshold region, on current ( I ON ) is modeled by the alpha-power law MOSFET model [5] as
where α is the velocity saturation index and I O is a technology- dependent parameter. Let t pd be a gate delay and it is given by
where b is a proportional constant and C is the load capacitance. The gate delay variation ( ∆ t pd ) induced by the V t h variation ( △V T H ) can be expressed by the first-order approximation as
When ∆VτH is σντH , which is defined as the standard devi- ation of the within-die V H  variation, ∆ t pd corresponds to the standard deviation of the gate delay variation ( σ ). Therefore, σ/μ of the gate delay due to the within-die random V H variation is derived from (3) as
In this paper, we assume that α and σντн do not depend on temperature for simplicity, since the dependence of σγτH on temperature is small, as reported in [6]. The dependence of σ / μ of the gate delay on temperature is derived as
where κ is the temperature coefficient for V τ H and given by
(6) where V H (T) is V T H at t the temperature of T and T 0 is the nominal temperature. At the nominal supply voltage of 1.1 V, (V DD − V TH )² is much larger than ακσ ν TH and, hence, the dependence of σ / μ of the gate delay on temperature is s signifi- cantly small, as shown in Fig. 5. B.  Temperature Dependence of Gate Delay Variations in the Sub-Threshold Region In this section, σ / μ of the gate delay in the sub-threshold region is modeled. In the sub-threshold region, I ON is expressed as
where n is the sub-threshold swing parameter, k is the Boltzmann constant, q is the elementary charge, T is the abso- lute temperature, and I 0 is a technology-dependent parameter [7]. When V D  is more than 0.1 V, I ON is approximated to
Here, XVTH is introduced to express the within-die random V T  variation as
where σΥＴＨ is the standard deviation of the within-die random V TH variation and V TH 0 is the mean of the V TH variation. A gate delay ( t pd ) in the sub-threshold region is derived as
where d is a proportional constant and
Equation (11) indicates that the variation of the gate delay in the sub-threshold region follows log-normal distribution. Therefore, the mean and the variance of the gate delay variation are given by
Consequently, σ / μ of the gate delay is derived as
When (qσντн/nkT)² ≪ 1, (15) can be approximated to
Since the dependence of σντH on temperature is s mall [6], (16) shows that σ/μ in the sub-threshold region is proportional to 1/T , which is clarified for the first time. Equation (16) is compared with the measured results in Fig. 6. It should be noted that σντH in (16) is estimated by the least squares method. Fig. 6 shows the measured and calculated temperature dependence of normalized σ / μ of NAND and NOR gate delay at 0.3 V. σ / μ is normalized to the NAND gate at 25 °C. Equation (16) is a good approximation to the measured temperature dependence of the gate delay variations, since the relative errors between the measured and calculated results are less than 11%. In Fig. 6, only NAND and NOR gates are shown. In order to investigate the temperature dependence in various gates, five- type gates are simulated with SPICE and compared with the calculated results by (16). Fig. 7 shows the SPICE simulated and calculated temperature dependence of normalized σ / μ of the five-type gates at 0.3 V. Three-type inverters with ×1 drivability, ×2 drivability, and ×4 drivability are added. σ / μ is normalized to the inverter with ×1 drivability at 25 °C. The simulated results are obtained by 3000 times Monte-Carlo SPICE. Fig. 7 indicates that (16) is a good approximation to the simulated temperature dependence of the gate delay variations, since the relative errors between the simulated and calculated results are less than 12%. As the inverter drivability is reduced, σ/μ increases, because the random V H variations increase with reducing transistor size.
IV.  CONCLUSION
In this paper, the temperature dependence of the within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 °C to −40 °C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that variation (σ/μ) of the gate delay is proportional to 1 / T  for the first time, where T  is the absolute temperature. Therefore, the large delay variations at low tem- peratures should be considered in the worst-case design of the sub-threshold logic circuits.
A CKNOWLEDGMENT
This work was carried out as a part of the Extremely Low Power project supported by the Ministry of Economy, Trade, and Industry and the New Energy and Industrial Technology Development Organization.
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