Gil-Su Kim, Makoto Takamiya, and Takayasu Sakurai The Institute of Industrial Science The University of Tokyo Tokyo, Japan gskim＠iis.u-tokyo.ac.jp; mtaka＠iis.u-tokyo.ac.jp; tsakurai＠iis.u-tokyo.ac.jp Abstract —A  high-sensitivity  capacitive-coupling  interface  is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver converts the data with various logic thresholds to that with optimum logic threshold. The receiver with the optimum logic threshold achieves the highest sensitivity of 25 mV at t he data rate of 2 Gb/s in 0. 18 μm CMOS. The proposed receiver increases the communication distance over 4 times while providing tolerance against the distance-voltage-area variations.
I.
Introduction
The wireless wafer level testing, as a counterpart to a mechanical one, provides promising solutions to pick out known good die, such as improved reliability, increased production yield, and even reduced cost [1]. Reliability can be increased as a result of elimination of physical damage on I/O pads. In contrast, the mechanical wafer testing requires the careful control of probing needles to minimize the deformation of I/O pads. The wireless wafer level testing also increases the number of probes, which allows for highly parallel testing for multidie and reduces the cost of testing. Besides, the wireless approach can provide internal testing points as well as peripheral points, by adding wireless interfaces within the device under test (DUT); thus it allows for the flexible layout of tested pads. For a wafer level testing, a wireless interface that is combined into the DUT must be implemented with small area so as not to degrade the established integration level of the DUT [1]. It also requires a high I/O bandwidth and should be tolerant to the variations in communication distance and transmitting voltage (or current) as well as misalignment between two interfaces, where the maximum communication distance is a measure of the tolerance for a given receiver sensitivity. Moreover, the interferences coming from adjacent channels must be kept low to maintain the signal integrity, which is essential for multichannel applications [1]. Inductive and capacitive couplings [1]−[8] can be adopted to implement a wireless wafer testing system. Since inductive coupling [1]–[4] is current driven, the transmission gain can be increased easily, which allows for long distance communications that can guarantee a good tolerance [2]. In contrast, capacitive coupling [5]–[8] is voltage driven, and its maximum transmission gain can be limited by the voltage swing of a transmitter driver and the coupling capacitance between two electrodes; thus its applications are usually restricted to short-distance communications [7]. The superior transmission capability of inductive coupling, however, leads to large area as well as high power consumption because the capability is obtained by increasing the current or the number of turns of an inductor. In addition, inductive coupling requires large pitch to minimize the crosstalk that is hardly shielded because it propagates in all directions in a transmitter and is superimposed in a receiver. Although modulation can be used to avoid the crosstalk, it limits the maximum data rate and requires huge inductors. Moreover, the inductive interconnection basically requires separate interfaces (i.e., inductors) which also give rise to area overhead [ 1 ]. In contrast, the capacitive crosstalk is not only less than the inductive one, but also can be blocked easily by shielding elements [9]. Consequently, one can realize a wireless interface with fine pitch. Moreover, since capacitive coupling can use the existing I/O pads instead of additional interfaces, the interface can be implemented with high area efficiency. The bandwidth of inductive coupling is limited by the input capacitance of a receiver and the input resistance, whereas that of capacitive coupling is determined by the coupling capacitance between two electrodes, the input capacitance of a receiver, and the input resistance. Since the input capacitance of the receiver is normally larger than the coupling capacitance owing to large input capacitances of ESD circuits, particularly for wireless wafer level testing, both interfaces represent similar bandwidth limitations. In this paper, a capacitive-coupling interface with the high sensitivity is presented to increase the communication distance tolerance  against distance-voltage-area while    providing variations for wireless wafer testing.
II.
W IRELESS W AFER TESING SYSTEM
Fig. 1 illustrates the wireless wafer testing system based on capacitive-coupling interface. The upper pads are a implemented on the bottom side of a printed circuit board (PCB) that can reduce cost and can easily be customized, whereas the lower pads are realized on the tested wafer. The power is supplied through a physical connection such as microbumps [6]. Fig. 2 illustrates simplified channel models for the wireless wafer testing system. In contrast to chip-to- chip interfaces (e.g., 3-D ICs [2]–[4], [6]–[8]), the wireless wafer testing system has large input capacitances, C RX (= C ESD + C PAD + C WIRE ) caused by ESD protection circuits, which results in both significant signal attenuation and bandwidth limitation in a receiver, where C ESD is the capacitance of ESD, C PAD is the capacitance of the pad, and C WIRE is the capacitance of the bonding wire. The simulation results (Fig. 3(a)) indicate that the signal attenuation is greater than 35 dB for the DUT- to-TEST LSI. This value corresponds to the received voltage (V RX ) of about 30 mV with a transmitted voltage of 1.8 V. The estimated minimum V R  against different input capacitances of a receiver is shown in Fig. 3(b). A coupling capacitor with the distance of 4 µm and the area of 80 µm × 80 µm is used for the estimation. Consequently, the signal attenuation due to the large input capacitance of a receiver limits the minimum area of pads, the misalignment between two pads, the maximum allowable distance, and the minimum voltage swing of the transmitter driver. The high sensitivity of the receiver can mitigate all these limitations, and, in turn, increases the tolerance against the distance-voltage-area variations. In this paper, a capacitive-coupling interface with the highest sensitivity of 25 mV at t the data rate of 2 Gb/s in 0.18 µm CMOS process is presented.
III.
H IGH-S ENSITIVITY OPTIMUM LOGIC THRESHOLD
RECEIVER
Interface Characteristic
A.
In contrast to previous works [1]–[7], the proposed interface has a large RC time constant (τ) for high-sensitivity, high- speed operation, where τ has its usual meaning and is determined by the resistance and the capacitance of a receiver. The receiver with small τ restores asymmetric and triangular pulses with filtered low-frequency components [5], as shown in Fig. 4(a). The signals with attenuated pulse swing, which is caused by the channel characteristic, represent narrow pulse width, which reduces the timing margin for data recovery and limits the maximum data rate [6]. Thus, the small-τ receiver with a limited timing margin requires complex timing control circuits to recover transmitted signals for a given data rate [1], [2], [5], [6]. In contrast, a large-t receiver maintains the original forms of transmitted signals (Fig. 4(b)); thus one can achieve the maximum timing margin, even when the pulse swing becomes smaller owing to the channel characteristic [10]. As a result, the large-τ receiver exhibits higher sensitivity and a higher data rate than the small-τ receiver. The large- τ receiver, however, suffers from the DC-offset (i.e., various logic thresholds) as a result of distance-area- supply voltage variations and the zero wander effect wherein the received signals go down below '0' V [10]. The direct application of a fixed reference results in both low sensitivity and pulse width distortion, which in turn increase BER. In order to remove the DC-offset, one can insert a coupling capacitor in front of the receiver. However, the required capacitance is normally large [10]. Feedback topology can remove the DC-offset and the zero wander effect, but it limits the maximum data rate and is not suitable for high-speed applications [10]. The proposed receiver employs feedforward topology without the coupling capacitor and converts the received signals into other signals with the optimum logic threshold (OLT) in order to eliminate the DC-offset and the zero wander effect. B. Optimum Logic Threshold Receiver Fig. 5(a) shows the schematic diagram of the proposed OLT receiver. The receiver is composed of a level shifter, a subtrac- tor, a replica bias circuit, a comparator, and a reset circuitry. The subtractor and replica bias circuit provide output signals, V 2 and V 4 , to the following comparator (sense amplifier-type flip-flop), respectively. The RC network consisting of resistor R and input capacitor of M1 produces an averaged signal, D ex, in , with the same logic threshold voltage, V TH , as those of the received signal, D RX,IN , under a balanced data pattern (e.g., 8B/10B encoding). After an appropriate level shift by ΔV, the circuit consisting of M3 and M4 subtracts the shifted signal (V 1 ) from D RX,IN and generates the output signal, V 2 , with a constant V TH , as shown in Fig. 5(b), where the output voltage of the subtractor can be defined as V 2 = (V DD - AV)+ (D RX,DN - D RX,DN ). small and large D RX_IN with different V TH , with high sensitivity, because the subtractor removes D R , n from D R , IN and produces signals with the optimum logic threshold. A replica bias circuit, M5-M8, provides a fixed reference voltage, V 4 , which is equal to V TH of V 2 , which can be easily achieved by applying the same potentials to the gates of M5 and M7. A reset circuitry provides reset signal, V c , to M9, in order to maintain the bottom level of D RX IN . The zero wander effect can be easily eliminated by the reset signal because the continuous fall of the bottom level of D RX,IN is prevented by the reset to 'O' V after the transitions of output signals, D RX OUT-
E XPERIMENTAL RESULTS
IV.
The micrograph of the test chip fabricated by the 1.8 V, 0.18 µm CMOS process is shown in Fig. 6. Fig. 7 shows the test environment for the proposed OLT receiver. For chip-to-board communication, a TX pad of 80 µm × 80 µm is patterned on the thin transparent flexible board, and one of the peripheral I/O pads is used as the RX pad of the same size. The BER was measured as a function of the supply voltage of TX and the simulated received voltage of RX (Fig. 8) using the internal PRBS and BER checker with pattern lengths of 2 33 -1. For a received voltage of 25 mV and a communication distance of 4 µm, the BER is <10 10 with the maximum data of 2 Gb/s. The measured performance is summarized in Table I. The performance of the proposed interface is at least 4 times superior to those of previous works. The OLT receiver with the sensitivity of 25 mV can increase the communication distance and reduce the pad size over 4 times, respectively. Note that the increased maximum communication distance
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