SAMSUNG SSD 845DC EVO
Data Sheet, Ver. 1.1

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DATA SHEET
Ver. 1.1, June, 2014

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1

Revision History
Revision No.

History

Date

Ver.1.0

Initial Release

May 2014

Ver.1.1

Content reorganized

June 2014

DATA SHEET
Ver. 1.1, June, 20142

Table of Contents
Product Overview
Revision history
1. General Description .......................................................................................................................................................................... 5
2. Mechanical Specification ................................................................................................................................................................ 6
2.1 Physical dimensions and Weight........................................................................................................................................... 6
3. Product Specifications ..................................................................................................................................................................... 7
3.1 Interface and Configuration .................................................................................................................................. 7
3.2 Capacity ................................................................................................................................................................ 7
3.3 Performance .............................................................................................................................................................................. 7
3.3.1 Sequential Read/Write Bandwidth ................................................................................................................................ 7
3.3.2 Random Read/Write Input/Output Operations Per Second (IOPS)................................................................ 7
3.3.3 IOPS Consistency ................................................................................................................................................................ 7
3.3.4 Latency ........................................................................................................................................... ..................... 8
3.3.5 Quality of Service (QoS)...................................................................................................................................................... 8
3.4 Electrical Characteristics.......................................................................................................................................................... 9
3.4.1 Supply Voltage .................................................................................................................................................................
9
3.4.2 Power Consumption ................................. ..................................... ............... ................................................................
9
3.4.3 Power Loss Protection ............................................................................ ................................................... 9
3.5 Reliability .............................................................................................................. .............................. 10
3.6 Environmental Specifications ............................................................................................................................................. 10
4. Electrical Interface Specification ……………………………………………………………………………………………………………………………………… 11
4.1 Serial ATA Interface connector............................................................................................................................................... 11
4.2 Pin Assignments............................................................................................................................................................................ 11
5. Shadow Register Block registers Description ...........................................................................................................................12
5.1 Command Register........................................................................................................................................................................12
5.2 Device Control Register.............................................................................................................................................................. 125.2.1 Field / bit description .........................................................................................................................................................12
5.3 Device / Head Register............................................................................................................................................................... 125.3.1 Field / bit description .................................................................................................................................................………12
5.4 Error Register ..........................…………………………………………………………………………………………………………………………………………..125.4.1 Field / bit description …………………………………………………………..……………………………………….............................................12
5.5 Features Register ......................................................................................................................................................................... 12
5.6 Cylinder High (LBA High) Register ......................................................................................................................................... 13
5.7 Cylinder Low (LBA Mid) Register ............................................................................................................................................ 13
5.8 Sector Number (LBA low) Register ....................................................................................................................................... 13
5.9 Sector Count Register ................................................................................................................................................................ 13
5.10 Status Register ........................................................................................................................................................................... 13
5.10.1 Field / bit description .......................................................................................................................................................13
6. Command Descriptions......................................................................................................................................................................14
6.1 Supported ATA Commands……………………………………………………………………………………………………………………………………….….14
6.2 SECURITY FEATURE Set ............................................................................................................................................................ 15
6.2.1 SECURITY mode default setting.................................................................................................................................... 15
6.2.2 Initial setting of the user password............................................................................................................................... 15
6.2.3 SECURITY mode operation from power-on.............................................................................................................. 15
6.2.4 Password lost......................................................................................................................................................................... 15
6.3 SMART FEATURE Set (B0h) …………………………………………………………………………………………………………………………………………. 15
6.3.1 Sub Command ..................................................................................................................................................................... 15
6.3.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h)............................................................................... 15
6.3.1.2 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h) ..................................................................... 15
6.3.1.3 S.M.A.R.T. Enable/Disable Attribute Autosave (subcommand D2h) ................................................... 15
6.3.1.4 S.M.A.R.T. Save Attribute Values (subcommand D3h) .............................................................................. 16
6.3.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h) ...........................................................……..16
6.3.1.6 S.M.A.R.T. Selective self-test routine ................................................................................................................ 16
6.3.1.7 S.M.A.R.T. Read Log Sector (subcommand D5h)...........................................................................................18

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Ver. 1.1, June, 20143

6.3.1.8 S.M.A.R.T. Write Log Sector (subcommand D6h)..........................................................................................18
6.3.1.9 S.M.A.R.T. Enable Operations (subcommand D8h) ……………………………………………………………………………..18
6.3.1.10 S.M.A.R.T. Disable Operations (subcommand D9h) .................................................................………………18
6.3.1.11 S.M.A.R.T. Return Status (subcommand DAh) ........................................................................................….18
6.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (subcommand DBh) ................................................. 19
6.3.2 Device Attribute Data Structure.......................................................................................................................................... 19
6.3.2.1 Data Structure Revision Number ...................................................................................................................... 19
6.3.2.2 Individual Attribute Data Structure .................................................................................................................. 19
6.3.2.3 Off-Line Data Collection Status .......................................................................................................................... 21
6.3.2.4 Self-test execution status...................................................................................................................................... 21
6.3.2.5 Total time in seconds to complete off-line data collection activity .................................................... 21
6.3.2.6 Current segment pointer ...................................................................................................................................... 21
6.3.2.7 Off-line data collection capability ………………………………………………………………………………………………………….. 21
6.3.2.8 S.M.A.R.T. Capability ................................................................................................................................................ 22
6.3.2.9 Error logging capability ......................................................................................................................................... 22
6.3.2.10 Self-test failure check point.............................................................................................................................. 22
6.3.2.11 Self-test completion time ................................................................................................................................. 22
6.3.2.12 Data Structure Checksum.................................................................................................................................. 22
6.3.3 Device Attribute Thresholds data structure .................................................................................................................. 22
6.3.3.1 Data Structure Revision Number ……………………………………………………………………………………………………………. 22
6.3.3.2 Individual Thresholds Data Structure............................................................................................................... 22
6.3.3.3 Attribute ID Numbers ............................................................................................................................................. 22
6.3.3.4 Attribute Threshold ................................................................................................................................................. 23
6.3.3.5 Data Structure Checksum..................................................................................................................................... 23
6.3.4 S.M.A.R.T. Log Directory …………………………………………………………………………………………………………………………………………… 23
6.3.5 S.M.A.R.T. error log sector ……………………………………………………………………………………………………………………………………….. 23
6.3.5.1 S.M.A.R.T. error log version ………………………………………………………………………………………………………………………. 23
6.3.5.2 Error log pointer ....................................................................................................................................................... 23
6.3.5.3 Device error count .................................................................................................................................................. 23
6.3.5.4 Error log data structure ......................................................................................................................................... 23
6.3.5.5 Command data structure ..................................................................................................................................... 23
6.3.5.6 Error data structure.................................................................................................................................................. 25
6.3.6 Self-test log structure ................................................................................................................................................ 25
6.3.7 Selective self-test log data structure ………………………………………………………………………………………………………… 25
6.3.8 Error reporting .............................................................................................................................................................. 26
7. OOB signaling and Phy Power State ............................................................................................................................................ 27
7.1 OOB signaling ................................................................................................................................................................................ 27
7.1.1 OOB signal spacing ............................................................................................................................................................. 27
7.2 Phy Power State............................................................................................................................................................................ 27
7.2.1 COMRESET sequence state diagram .......................................................................................................................... 27
8. SPOR Specification(Sudden Power Off and Recovery) ........................................................................................................ 28
8.1. Data Recovery in Sudden Power Off..................................................................................................................................... 28
8.2 Time to Ready Sequence........................................................................................................................................................... 28
9. SATA II Optional Feature.................................................................................................................................................................... 29
9.1 Asynchronous Signal Recovery............................................................................................................................................... 29
9.2 Power Segment Pin P11 ........................................................................................................................................................... 29
9.3 Activity LED indication ............................................................................................................................................................... 29
10. Product Compliance......................................................................................................................................................................... 30
10.1 Product Regulatory compliance and Certifications .................................................................................................... 30
11. Identify Device Data ........................................................................................................................................................................ 31
12. Product Line up ................................................................................................................................................................................. 33

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Ver. 1.1, June, 20144

1. General Description
Samsung SSD 845DC EVO is designed for server and data centers delivering an exceptionally highperformance, consistent low latency and outstanding reliability. With the addition of Tantalum capacitors,
crucial data is protected from corruption due to power loss more than ever before. The 845DC EVO provides
a state-of-the-art yet cost-effective solution for today’s increasing data traffic.
845DC EVO
Capacity
Application
Dimensions (LxWxH)
WeightInterface
Form Factor
Controller
NAND Flash Memory
DRAM Cache memory

240GB, 480GB, 960GB
Mixed and Read-centric applications are recommended(100.20±0.25) x (69.85±0.25) x (6.80±0.20) mm
Max. 63g (960GB)
Serial ATA 6Gb/s (compatible with SATA 3Gb/s and SATA 1.5Gb/s)
Fully complies with ATA/ATAPI-7 Standard(Partially Complies with ATA/ATAPI-8)
Support NCQ : Up to 32 depth
2.5” typeSamsung 3-core MEX controller
Samsung 19nm Toggle 3bit MLC NAND
256MB (240GB), 512MB (480GB), 1GB (960GB)
Sequential Read:
Sequential Write:

Performance*

Random Read (4KB, QD32):
Random Write (4KB, QD32):

Quality of Service(4KB, QD32)

99.99%

Read: 0.6ms

Write: 7ms

Max.

Read: 3ms

Write: 8ms

Latency(4KB, QD1)

Sequential

Read :55 us

Write : 45us

RandomRead :115us

Write : 55usReliability

TBW
Power Consumption
Temperature*

Up to. 530 MB/s
Up to. 410 MB/s (480GB, 960GB)
Up to. 270 MB/s (240GB)
Max. 87,000 IOPS
Max. 14,000 IOPS(480GB, 960GB)
Max. 12,000 IOPS(240GB)- Mean Time Between Failures (MTBF) : 2,000,000 hours- Uncorrectable Bit Error Rate (UBER) : 1 sector per 1017 bits read
- End-to-end data protection
240GB : 150TBW
480GB : 300TBW
960GB : 600TBW

Active Read/Write : 3.1 Watt/4.2Watt
Idle : 1.5 Watt
Operating:
Non-Operating:

0°C to 70°C
-40°C to 85°C

Humidity

5% to 95%, non-condensing

Vibration

Non-Operating:

20~2000Hz, 20G

Shock
Certification
RoHS compliance
Warranty

Non-Operating:

1500G , duration 0.5m sec, 3 axis

CE, BSMI, KCC, VCCI, C-tick, FCC, IC, UL, TUV, CB
ROHS2
5 years limited

Actual performance may vary depending on use conditions and environment
1. Performance measured using FIO with queue depth 32
2. Measurements are performed on whole LBA range
3. Write cache enabled
4. 1MB/sec = 1,048,576 bytes/sec was used in sequential performance
5. Uncorrectable Bit Error Rate (UBER) and Endurance (TBW) is based on JEDEC standard.

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Ver. 1.1, June, 20145

2. Mechanical Specification
2.1 Physical dimensions and Weight※

Model Name

HeightWidth

LengthWeightMZ-7GE240
MZ-7GE480
MZ-7GE960

6.80±0.20

69.85±0.25

100.20±0.25

Max. 63g

For the thickness size(height), drive label thickness was included[Figure 2-1] Physical dimension

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Ver. 1.1, June, 20146

3. Product Specifications
3.1 Interface and Configuration
Burst read/write rate is 600 MB/sec (6Gb/s).
Fully compatible with ATA-7 Standard(Partially Complies with ATA/ATAPI-8)

3.2 Capacity
MZ-7GE240

MZ-7GE480

MZ-7GE960

Unformatted Capacity

240 GB480 GB

960 GB

User-addressable Capacity(Number of sectors)

468,862,128

937,703,088

1,875,385,008

Byte per Sector※

512 Bytes

1 Megabyte (MB) = 1 Million bytes; 1 Gigabyte (GB) = 1 Billion bytes
Actual usable capacity may be less due to formatting, partitioning, operating system, application and otherwise.

3.3 Performance
3.3.1 Sequential Read/Write Bandwidth

Read

MZ-7GE240
530

Model Name
MZ-7GE480
530

MZ-7GE960
530

Write

270

410

410

Sequential (128KB, MB/s)

3.3.2 Random Read/Write Input/Output Operations Per Second (IOPS)
4KB Random (IOPS)
QD 32
QD 1

MZ-7GE240

MZ-7GE480

MZ-7GE960

Read IOPS

87,00087,00087,000

Write IOPS

12,00014,00014,000

Read IOPS

8,000

8,000

8,000

Write IOPS

12,00014,00014,000

MZ-7GE240

MZ-7GE480

MZ-7GE960

Read IOPS

55,00055,00055,000

Write IOPS

6,000

7,000

7,000

Read IOPS

7,000

7,000

7,000

Write IOPS

3,000

5,000

5,000

8KB Random (IOPS)
QD 32
QD 1
※

Actual performance may vary depending on usage conditions and system environment.
1. Performance measured FIO with queue depth 32
2. Measurements are performed on whole LBA range
3. Write cache enabled
4. 1MB/sec = 1,048,576 bytes/sec was used in sequential performance

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Ver. 1.1, June, 20147

3.3.3 IOPS Consistency
4KB

MZ-7GE240

MZ-7GE480

MZ-7GE960

Random Read (%)

QD1
QD32

95
99

95
99

95
99

Random Write (%)

QD1
QD32

85
90

85
90

85
90

QD1

MZ-7GE240
95

MZ-7GE480
95

MZ-7GE960
95

QD32

99

99

99

QD1

90

90

90

QD32

90

90

90

MZ-7GE480
115
55
55
45

MZ-7GE960
115
55
55
45

8KB
Random Read (%)
Random Write (%)※

IOPS Consistency [%] = (99.9% IOPS)/(Average IOPS) x 100

3.3.4 Latency
Read (us)Write (us)※Typical 4KB Random
Typical Sequential
Typical 4KB Random
Typical Sequential

MZ-7GE240
110
55
50
45

Latency is measured using 4KB transfer size with Queue Depth 1.

3.3.5 Quality of Service (QoS)
Quality of Service (QoS) is the level of quality that provides steady and consistent performance given as a
maximum response time under the certain confidence level of 99.9% or 99.9999%.

99.9%
(ms)

4KB

MZ-7GE240
Read
Write
0.2
0.4

8KB

0.2

0.6

0.2

0.6

0.2

0.6

Max (99.9999%)
(ms)

4KB

1

1

1

1

1

1

8KB

1

1.5

1

1.5

1

1.5

QD1

QD32

※

MZ-7GE240
Read
Write
0.6
7

MZ-7GE480
Read
Write
0.2
0.4

MZ-7GE960
Read
Write
0.2
0.4

MZ-7GE480
Read
Write
0.6
7

MZ-7GE960
Read
Write
0.6
7

99.9%
(ms)

4KB
8KB

1

10

1

10

1

10

Max (99.9999%)
(ms)

4KB

3

8

3

8

3

8

8KB

5

15

5

15

5

15

Actual performance may vary depending on usage conditions and system environment.
Test condition: Intel® i3-3240 3.40GHz, 4GB DDR3-1600, Intel C216 Family Chipset
RedHat Enterprise Linux 6.4 with AHCI (ver.9.3.0.1011)
Test program: FIO 2.1.3

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3.4 Electrical Characteristics
3.4.1 Supply Voltage※

Characteristics

Requirements

Allowable voltage

5V ± 5%

Allowable noise/ripple

100mV p-p or less

Rise time (Max./Min.)

1s / 1ms

Fall time

500ms

Inrush current (Typical Peak)

1.5A, <1s

The 845DC EVO needs only 5V power rail, and the 12V power pin of a SATA connector is not connected to any
net and components in the 845DC EVO.
If both 12V and 5V power rails are provided to the SSD, the SSD would work well.
If only 5V power rail is provided to the SSD, the SSD would work well.
If only 12V power rail is provided to the SSD, the SSD would not work, but this won’t bring any problems to hostsystem.

3.4.2 Power Consumption
MZ-7GE240

MZ-7GE480

MZ-7GE960

Active Read
(Watt)

Average

3.1

3.1

3.1

Burst

3.1

3.1

3.1

Active Write(Watt)

Average

3.1

4.1

4.2

Burst

3.4

4.4

4.8

1.0

1.5

1.5

Idle (Watt)

3.4.3 Power Loss Protection (PLP)
Samsung 845DC EVO SSD is built with tantalum capacitors to protect all data in the write cache in caseof a power failure. On detection of the external power loss, the SSD uses the electricity from a tantalum
capacitor to transfer the cached data in DRAM to the flash memory.
This enterprise-grade PLP provides an added level of security to ensure that valuable write information iswell protected against data corruption caused by sudden power loss.
MZ-7GE240

MZ-7GE480

MZ-7GE960

Number of Capacitors

14

21

23

Capacitance

1.4mF

2.1mF

2.3mF

Discharging time

DATA SHEET
Ver. 1.1, June, 2014

Min 35ms

9

3.5 Reliability
MZ-7GE240

MZ-7GE480

MZ-7GE960

Mean Time Between Failures (MTBF)

2,000,0000 Hours

Uncorrectable Bit Error Rate (UBER)

1 sector per 10^17 bits read

Endurance(TBW)※

150TBW

300TBW

600TBW

Data Retention

3 months (@40℃)

Power on/off cycle

24 per Day

Insertion cycle

500 cycles

Refer to JESD218 standard table 1 for requirements of enterprise SSD reliability.

3.6 Environmental Specifications※

Features

Operating

Non-Operating

Temperature

0℃ to 70℃

-40℃ to 85℃

Humidity

5% to 95%, non-condensing

Vibration

1~2KHz, 20Grms, 20min/3-axis

Shock

1500G with 0.5ms duration

Notes :
1. Temperature specification is following JEDEC standard; Expressed temperature must be measured right on
the case.
2. Humidity is measured in non-condensing.
3. Shock test condition: 0.5ms duration with half sine wave.
4. Vibration test condition: 10Hz to 2,000Hz, 15mins/axis on 3axis(X,Y,Z)

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Ver. 1.1, June, 201410

4. Electrical Interface Specification
4.1 Serial ATA Interface connector
Drive Connector : AMPHENOL, SATA-001-0009-1-TR

4.2 Pin Assignments
No.

Signal

S1
S2
S3
S4
S5
S6
S7

Power

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

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Ver. 1.1, June, 2014

Plug Connector pin definitionnd

GND
2 mateA+
Differential signal A from Phy
AGND
2nd mate
BDifferential signal A from Phy
B+
GND
2nd mate
Key and spacing separate signal and power segments
V33
3.3V power (Unused)V33
3.3V power (Unused)V33
3.3V power, pre-charge, 2nd mate (Unused)
GND
1st mate
GND
2nd mate
GND
2nd mate
V5
5V power, pre-charge, 2nd mate
V5
5V power
V5
5V powerGND
2nd mate
DAS/DSS
Device Activity Signal/Disable Staggered Spinup
GND
1st mate
V12
12V power, pre-charge, 2nd mate (Unused)
V12
12V power (Unused)
V12
12V power (Unused)11

5. Shadow Register Block registers Description
5.1 Command Register
This register contains the command code being sent to the device. Command execution begins
immediately after this register is written. All other registers required for the command must be set up
before writing the Command Register.

5.2 Device Control Register
This register contains the command code being sent to the device. Command execution begins
immediately after this register is written. All other registers required for the command must be set up
before writing the Command Register

5.2.1 Field/bit description
7
HOB

6
-

5
-

4
-

3
-

2
SRST

1
nlEN

0
0

※

HOB is defined by the 48bit Address feature set. A write to any Command register shall clear the HOB bit to zero.

※

SRST is the host software reset bit. SRST=1 indicates that the drive is held reset and sets BSY bit in Status register.
Setting SRST=0 re-enables the device.

※nIEN is the enable bit for the device Assertion of INTRQ to the host. When nIEN=0, and the device is selected by
Drive select bit in DEVICE/HEAD register, device interrupt to the host is enabled. When this bit is set, the "I’ bit in
the Register Host to Device, PIO setup, Set Device Bits and DMA Set Up will be set, whether pending interrupt isfound or not.

5.3 Device / Head Register
5.3.1 Field / bit description
The content of this register shall take effect when written.
7
-

6
L

5
-

4
DEV

3
HS3

2
HS2

1
HS1

0
HS0

※

L : Binary encoded address mode select. When L=0, addressing is by CHS mode. When L=1, addressing is by LBA
mode.

※

DEV: Device select. Cleared to zero selects Device 0. Set to one selects Device1.

※

HS3, HS2, HS1, HS0 : Head select bits. The HS3 through HS0 contain bits 24-27 of the LBA. At commandcompletion, these bits are updated to reflect the current LBA bits 24-27.

5.4 Error Register
This register contains the command code being sent to the device. Command execution begins
immediately after this register is written. All other registers required for the command must be set up
before writing the Command Register.

5.4.1 Field / bit description
7
ICRC

6
UNC

5
0

4
IDNF

3
0

2
ABRT

1
TKONF

0
AMNF

※

ICRC: Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus during a Ultra-DMA transfer.

※

UNC: Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been encountered.

※

IDNF: ID Not Found. IDN=1 indicates the requested sector’s ID field coul※

ABRT: Aborted Command. ABT=1 indicates the requested command has been aborted due to a device statuserror or an invalid parameter in an output register.

※

TKONF: Track 0 Not Found. T0N=1 indicates track 0 was not found during a Recalibrate command.

※

AMNF: Address Mark Not Found. When AMN=1, it indicates that the data address mark has not been found after
finding the correct ID field for the requested sector.

5.5 Features Register
This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function Set
command.

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Ver. 1.1, June, 201412

5.6 Cylinder High (LBA High)This register contains Bits 16-23. At the end of the command, this register is updated to reflect thecurrent LBA Bits 16-23.

5.7 Cylinder Low (LBA Mid) Register
This register contains Bits 8-15. At the end of the command, this register is updated to reflect the current
LBA Bits 8-15. When 48-bit addressing commands are used, the "most recently written" content contains
LBA Bits 8-15, and the "previous content" contains Bits 32-39

5.8 Sector Number (LBA low) Register
This register contains Bits 0-7. At the end of the command, this register is updated to reflect the current
LBA Bits 0-7. When 48-bit commands are used, the "most recently written" content contains LBA Bits 0-7,
and the "previous content" contains Bits 24-31.

5.9 Sector Count Register
This register contains the number of sectors of data requested to be transferred on a read or write
operation between the host and the device. If the value in the register is set to 0, a count of 256 sectors(in 28-bit addressing) or 65,536 sectors (in 48-bit addressing) is specified. If the register is zero atcommand completion, the command was successful. If not successfully completed, the register contains
the number of sectors which need to be transferred in order to complete the request. The contents of theregister are defined otherwise on some commands. These definitions are given in the commanddescriptions.

5.10 Status Register
This register contains the device status. The contents of this register are updated whenever an error
occurs and at the completion of each command. If the host reads this register when an interrupt is
pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever thisregister is read. If BSY=1, no other bits in the register are valid. And read/write operations of any otherregister are negated in order to avoid the returning of the contents of this register instead of the otherregisters’ contents.

5.10.1 Field / bit description.
7
BSY

6
DRDY

5
DF

4
DSC

3
DRQ

2
CORR

1
IDX

0
ERR

※

BSY : Busy. BSY=1 whenever the device is accessing the registers. The host should not read or write any registers※

DRDY : Device Ready. RDY=1 indicates that the device is capable of responding to a command. RDY will be set to
0 durin※

DF : Device Fault. DF=1 indicates that the device has detected a write fault condition. DF is set to 0 after the
Status Register is read by the host.

※

DSC : Device Seek Complete. DSC=1 indicates that a seek has completed and the device head is settled over a
track. DSC is set to 0 by the device just before a seek begins. When an error occurs, this bit is not changed until
the Status Register is read by the host, at which time the bit again indicates the current seek complete status.
When the device enters into or is in Standby mode or Sleep mode, this bit is set by device in spite of not spinningup.

※

DRQ : Data Request. DRQ=1 indicates that the device is ready to transfer a word or byte of data between the hostand the device. The host should not write the Command register when DRQ=1.

※

CORR : Corrected Data. Always 0.

※

IDX : Index. IDX=1 once per revolution. Since IDX=1 only for a very short time during each revolution, the host
may not see it set to 1 even if the host is reading the Status Register continuously. Therefore the host should not
attempt to use IDX for timing purposes.

※

ERR : ERR=1 indicates that an error occurred during execution of the previous command. The Error Registershould be read to determine the error type. The device sets

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6. Command Descriptions
6.1 Supported ATA Commands
Command Name

CommandCode(Hex)CHECK POWER MODEDATA SET MANAGEMENTDEVICE CONFIGURATION FREEZE LOCKDEVICE CONFIGURATION IDENTIFY
DEVICE CONFIGURATION RESTORE
DEVICE CONFIGURATION SETDOWNLOAD MICROCODEDOWNLOAD MICROCODE DMAEXECUTE DEVICE DIAGNOSTIC
FLUSH CACHE
FLUSH CACHE EXTIDENTIFY DEVICE
IDLE
IDLE IMMEDIATEINITIALIZE DEVICE PARAMETERSNOPREAD BUFFER
READ BUFFER DMAREAD DMAREAD DMA EXTREAD DMA WITHOUT RETRIESREAD FPDMA QUEUEDREAD LOG DMA EXTREAD LOG EXTREAD MULTIPLE
READ MULTIPLE EXTREAD NATIVE MAX ADDRESSREAD NATIVE MAX ADDRESS EXTREAD SECTORSREAD SECTORS EXTREAD SECTORS WITHOUT RETRY
READ VERIFY SECTORSREAD VERIFY SECTORS EXTREAD VERIFY SECTORS WITHOUT RETRY
RECALIBRATERECEIVE FPDMA QUEUEDSECURITY DISABLE PASSWORDSECURITY ERASE PREPARESECURITY ERASE UNIT
SECURITY FREEZE LOCKSECURITY SET PASSWORDSECURITY UNLOCKSEEKSEND FPDMA QUEUEDSET MAX ADDRESSSET MAX ADDRESS EXT
SET MULTIPLE MODE
SLEEP
SMART

E5h
06h
B1/C1
B1/C2
B1/C0
B1/C3
92h
93h
90h
E7h
EAh
ECh
E3h
E1h
91h
00h
E4h
E9h
C8h
25h
C9h
60h
47h
2Fh
C4h
29h
F8h
27h
20h
24h
21h
40h
42h
41h
10h
65h
F6h
F3h
F4h
F5h
F1h
F2h
70h
64h
F9h
37h
C6h
E6h
B0h

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Ver. 1.1, June, 201414

Command Name

CommandCode(Hex)

STANDBY
STANDBY IMMEDIATEWRITE BUFFER
WRITE BUFFER DMA
WRITE DMAWRITE DMA EXT
WRITE DMA FUA EXT
WRITE DMA WITHOUT RETRY
WRITE FPDMA QUEUEDWRITE LOG DMA EXT
WRITE LOG EXTWRITE MULTIPLE
WRITE MULTIPLE EXTWRITE MULTIPLE FUA EXT
WRITE SECTORSWRITE SECTORS EXT
WRITE SECTORS WITHOUT RETRY
WRITE UNCORRECTABLE EXT

E2h
E0h
E8h
EBh
CAh
35h
3Dh
CBh
61h
57h
3Fh
C5h
39h
CEh
30h
34h
31h
45h

6.2 SECURITY FEATURE Set
The Security mode features allow the host to implement a security password system to prevent
unauthorized access to the disk drive.

6.2.1 SECURITY mode default setting
The SSD is shipped with master password set to 00h value(ASCII blanks) and the lock function disabled.
The system manufacturer/dealer may set a new master password by using the SECURITY SET PASSWORD
command, without enabling the lock function.

6.2.2 Initial setting of the user password
When a user password is set, the drive automatically enters lock mode by the next powered-on.

6.2.3 SECURITY mode operation from power-on
In locked mode, the SSD rejects media access commands until a SECURITY UNLOCK command is
successfully completed.

6.2.4 Password lostIf the user password is lost and High level security is set, the drive does not allow the user to access any
data. However, the drive can be unlocked using the master password. If the user password is lost andMaximum security level is set, it is impossible to access data. However, the drive can be unlocked using
the ERASE UNIT command with the master password. The drive will erase all user data and unlock thedrive.

6.3 SMART FEATURE Set (B0h)
The SMART Feature Set command provides access to the Attribute Values, the Attribute Thresholds, andother low level subcommands that can be used for logging and reporting purposes and to accommodate
special user needs. The SMART Feature Set command has several separate subcommands which are
selectable via the device's Features Register when the SMART Feature Set command is issued by the host.
In order to select a subcommand the host must write the subcommand code to the device's Features
Register before issuing the SMART Feature Set command.

6.3.1 Sub Command
In order to select a subcommand the host must write the subcommand code to the device's Features
Register before issuing the S.M.A.R.T. Function Set command. The subcommands and their respective
codes are listed below.
Command Name

Code

SMART READ DATASMART READ ATTRIBUTE THRESHOLDSSMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE
SMART SAVE ATTRIBUTE VALUESSMART EXECUTE OFF-LINE IMMIDIATE
SMART READ LOG

D0h
D1h
D2h
D3h
D4h
D5h

Command Name
SMART WRITE LOG
SMART ENABLE OPERATIONSSMART DISABLE OPERATIONSSMART RETURN STATUS
SMART ENABLE/DISABLE
AUTOMATIC OFF-LINE

Code
D6h
D8h
D9h
DAh
DBh

6.3.1.1 S.M.A.R.T. Read Attribute Values (subcommand D0h)
This subcommand returns the device's Attribute Values to the host. Upon receipt of the S.M.A.R.T.
Read Attribute Values subcommand from the host, the device asserts BSY, saves any updated
attribute Values to the Attribute Data sectors, asserts DRQ, clears BSY, asserts INTRQ, and thenwaits for the host to transfer the 512 bytes of Attribute Value information from the device via the
Data Register.
6.3.1.2 S.M.A.R.T. Read Attribute Thresholds (subcommand D1h)
This subcommand returns the device's Attribute Thresholds to the host. Upon receipt of the
S.M.A.R.T. Read Attribute Thresholds subcommand from the host, the device reads the Attribute
Thresholds from the Attribute Threshold sectors and then waits for the host to transfer the 512
bytes of Attribute Thresholds information from the device
6.3.1.3 S.M.A.R.T. Enable/Disable Attribute Auto-save (subcommand D2h)
This subcommand enables and disables the attribute auto save feature of the device. The S.M.A.R.T.
Enable/Disable Attribute Auto-save subcommand allows the device to automatically save its

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updated Attribute Values to the Attribute Data Sector at the timing of the first transition to Active
idle mode and after 15 minutes after the last saving of Attribute Values. This subcommand causes
the auto save feature to be disabled. The state of the Attribute Auto-save feature—either enabledor disabled—will be preserved by the device across the power cycle. A value of 00h—written by thehost into the device's Sector Count Register before issuing the S.M.A.R.T. Enable/Disable AttributeAuto-save subcommand— will cause this feature to be disabled. Disabling this feature does notpreclude the device from saving Attribute Values to the Attribute Data sectors during some othernormal operation such as during a power-up or a power-down. A value of F1h—written by the host
into the device's Sector Count Register before issuing the S.M.A.R.T. Enable/Disable AttributeAuto-save subcommand— will cause this feature to be enabled. Any other nonzero value writtenby the host into this register before issuing the S.M.A.R.T. Enable/Disable Attribute Auto-savesubcommand will not change the current Auto-save status. The device will respond with the error
code specified in Table: “S.M.A.R.T. Error Codes” on page 26. The S.M.A.R.T. Disable Operations
subcommand disables the auto save feature along with the device's S.M.A.R.T. operations. Uponthe receipt of the subcommand from the host, the device asserts BSY, enables or disables the
Auto-save feature, clears BSY, and asserts INTRQ.
6.3.1.4 S.M.A.R.T. Save Attribute Values (subcommand D3h)
This subcommand causes the device to immediately save any updated Attribute Values to thedevice's Attribute Data sector regardless of the state of the Attribute Auto-save feature. Upon
receipt of the S.M.A.R.T. Save Attribute Values subcommand from the host, the device asserts BSY,
writes any updated Attribute Values to the Attribute Data sector, clears BSY, and asserts INTRQ.
6.3.1.5 S.M.A.R.T. Execute Off-line Immediate (subcommand D4h)
This subcommand causes the device to immediately initiate the set of activities that collect
Attribute data in an offline mode (off-line routine) or execute a self-test routine in either captive or
off-line mode. The LBA Low register shall be set to specify the operation to be executed
LBA Low
00h
01h
02h
03h
04h
40h
7Fh
81h
82h
84h
C0h

Subcommand
Execute S.M.A.R.T. off-line data collection routine immediately
Execute S.M.A.R.T. Short self-test routine immediately in off-line mode
Execute S.M.A.R.T. Extended self-test routine immediately in off-line mode
Reserved
Execute S.M.A.R.T. Selective self-test routine immediately in off-line mode
Reserved
Abort off-line mode self-test routine
Execute S.M.A.R.T. short self-test routine immediately in captive mode
Execute S.M.A.R.T. Extended self-test routine immediately in captive mode
Execute S.M.A.R.T. selective self-test routine immediately in captive mode
Reserved

Off-line mode : The device executes command completion before executing the specified routine. During execution of theroutine the device will not set BSY nor clear DRDY. If the device is in the process of performing its routine and is interrupted
by a new command from the host, the device will abort or suspend its routine and service the host within two seconds after
receipt of the new command. After servicing the interrupting command, the device will resume its routine automatically or
not start its routine depending on the interrupting command.
Captive mode : When executing self-test in captive mode, the device sets BSY to one and executes the specified self-test
routine after receipt of the command. At the end of the routine, the device sets the execution result in the Self-test
execution status byte (see Table “Device Attribute Data Structure” on page 6.3.2) and ATA registers and then executes thecommand completion. See definitions below.
Status Set ERR to one when the self-test
Error Set ABRT to one when the self-test
LBA Low Set to F4h when the self-test has failed
LBA High Set to 2Ch when self-test has failed

6.3.1.6 S.M.A.R.T. Selective self-test routine
When the value in the LBA Low register is 4 or 132, the Selective self-test routine shall be
performed. This self test routine shall include the initial tests per-formed by the Extended self-test
routine plus a selectable read scan. The host shall not write the Selective self-test log while theexecution of a Selective self-test command is in progress. The user may choose to do read scan

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only on specific areas of the media. To do this, user shall set the test spans desired in the Selective
self-test log and set the flags in the Feature flags field of the Selective self-test log to indicate do
not perform off-line scan. In this case, the test spans defined shall be read scanned in their entirety.
The Selective self-test log is updated as the self-test proceeds indicating test progress. When all
specified test spans have been completed, the test is terminated and the appropriate self-test
execution status is reported in the SMART READ DATA response depending on the occurrence oferrors. Below figure shows an example of a Selective self test definition with three test spansdefined. In this example, the test terminates when all three test spans have been scanned.

After the scan of the selected spans described above, a user may wish to have the rest of media
read scanned as an off-line scan. In this case, the user shall set the flag to enable off-line scan in
addition to the other settings. If an error occurs during the scanning of the test spans, the error isreported in the self-test execution status in the SMART READ DATA response and the off-line scan
is not executed. When the test spans defined have been scanned, the device shall then set theoffline scan pending and active flags in the Selective self-test log to one, the span under test to avalue greater than five, the self-test execution status in the SMART READ DATA response to 00h,
set a value of 03h in the off-line data collection status in the SMART READ DATA response and shallproceed to do an off-line read scan through all areas not included in the test spans. This off-line
read scan shall completed as rapidly as possible, no pauses between block reads, and any errors
encountered shall not be reported to the host. Instead error locations may be logged for future
reallocation. If the device is powered-down before the off-line scan is completed, the off-line scan
shall resume when the device is again powered up. From power-up, the resumption of the scan
shall be delayed the time indicated in the Selective self-test pending time field in the Selective selftest log. During this delay time the pending flag shall be set to one and the active flag shall be set
to zero in the Selective self-test log. Once the time expires, the active flag shall be set to one, andthe off-line scan shall resume. When the entire media has been scanned, the off-line scan shallterminate, both the pending and active flags shall be cleared to zero, and the off-line datacollection status in the SMART READ DATA response shall be set to 02h indicating completion.
During execution of the Selective self-test, the self-test executions time byte in the Device SMART
Data Structure may be updated but the accuracy may not be exact because of the nature of thetest span segments. For this reason, the time to complete off-line testing and the self-test polling
times are not valid. Progress through the test spans is indicated in the selective self-test log. A
hardware or software reset shall abort the Selective self-test except when the pending bit is set to
one in the Selective self-test log). The receipt of a SMART EXECUTE OFF-LINE IMMEDIATE
command with 0Fh, Abort off-line test routine, in the LBA Low register shall abort Selective selftest regardless of where the device is in the execution of the command. If a second self-test isissued while a selective self-test is in progress, the selective self-test is aborted and the newly
requested self-test is executed.

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6.3.1.7 S.M.A.R.T. Read Log Sector (subcommand D5h)
This command returns the indicated log sector contents to the host. Sector count specifies thenumber of sectors to be read from the specified log. The log transferred by the drive shall start at
the first sector in the specified log, regardless of the sector count requested. Sector number
indicates the log sector to be returned as described in the following Table.
LBA Low00h01h02h04h-05h06h
08h
09h
0Ah-7Fh80h-9Fh
A0h-FFh

Subcommand
Log directory
SMART error log
Comprehensive SMART error log
Reserved
SMART self-test log
Reserved
Selective self-test log
Reserved
Host vendor specificReserved

RO
RO
RO
RO
RO
RO
R/W
RO
R/W
VS

RO – Log is read only by the host.
R/W – Log is read or written by host.
VS - Log is vendor specific thus read/write ability is vendor specific.

6.3.1.8 S.M.A.R.T. Write Log Sector (subcommand D6h)
This command writes 512 bytes of data to the specified log sector. The 512 bytes of data aretransferred at a command and the LBA Low value shall be set to one. The LBA Low shall be set tospecify the log sector address. If a Rea Only log sector is specified, the device returns ABRT error.
6.3.1.9 S.M.A.R.T. Enable Operations (subcommand D8h)
This subcommand enables access to all S.M.A.R.T. capabilities within the device. Prior to receipt ofa S.M.A.R.T. Enable Operations subcommand, Attribute Values are neither monitored nor saved by
the device. The state of S.M.A.R.T.—either enabled or disabled—will be preserved by the device
across power cycles. Once enabled, the receipt of subsequent S.M.A.R.T. Enable Operations
subcommands will not affect any of the Attribute Values. Upon receipt of the S.M.A.R.T. Enable
Operations subcommand from the host, the device asserts BSY, enables S.M.A.R.T. capabilities andfunctions, clears BSY, and asserts INTRQ.
6.3.1.10 S.M.A.R.T. Disable Operations (subcommand D9h)
This subcommand disables all S.M.A.R.T. capabilities within the device including the device's
attribute auto save feature. After receipt of this subcommand the device disables all S.M.A.R.T.
operations. Non self-preserved Attribute Values will no longer be monitored. The state of
S.M.A.R.T.—either enabled or disabled—is preserved by the device across power cycles. Note that
this subcommand does not preclude the device's power mode attribute auto saving. Upon receiptof the S.M.A.R.T. Disable Operations subcommand from the host, the device asserts BSY, disables
S.M.A.R.T. capabilities and functions, clears BSY, and asserts INTRQ. After receipt of the device of
the S.M.A.R.T. Disable Operations subcommand from the host, all other S.M.A.R.T. subcommands—
with the exception of S.M.A.R.T. Enable Operations—are disabled, and invalid and will be aborted by
the device—including the S.M.A.R.T. Disable Operations subcommand— returning the error code as
specified in Table: “S.M.A.R.T. Error Codes” on page 6.3.8. Error reporting. Any Attribute Values
accumulated and saved to volatile memory prior to receipt of the S.M.A.R.T. Disable Operationscommand will be preserved in the device's Attribute Data Sectors. If the device is re-enabled, these
Attribute Values will be updated, as needed, upon receipt of a S.M.A.R.T. Read Attribute Values or a
S.M.A.R.T. Save Attribute Values command
6.3.1.11 S.M.A.R.T. Return Status (subcommand DAh)This subcommand is used to communicate the reliability status of the device to the host's request.
Upon receipt of the S.M.A.R.T. Return Status subcommand the device asserts BSY, saves any
updated Attribute Values to the reserved sector, and compares the updated Attribute Values to
the Attribute Thresholds. If the device does not detect a Threshold Exceeded Condition, or detects
a Threshold Exceeded Condition but involving attributes are advisory, the device loads 4Fh into the
LBA Mid register, C2h into the LBA High register, clears BSY, and asserts INTRQ. If the device
detects a Threshold Exceeded Condition for pre-failure attributes, the device loads F4h into the

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LBA Mid register, 2Ch into the LBA High register, clears BSY, and asserts INTRQ. Advisory attributes
never result in a negative reliability condition.
6.3.1.12 S.M.A.R.T. Enable/Disable Automatic Off-line (subcommand DBh)
This subcommand enables and disables the optional feature that cause the device to perform theset of off-line data collection activities that automatically collect attribute data in an off-line modeand then save this data to the device's nonvolatile memory. This subcommand may either cause
the device to automatically initiate or resume performance of its off-line data collection activities
or cause the automatic off-line data collection feature to be disabled. This subcommand alsoenables and disables the off-line read scanning feature that cause the device to perform the entire
read scanning with defect reallocation as the part of the off-line data collection activities. The
Sector Count register shall be set to specify the feature to be enabled or disabled:
Sector Count00h
F8h

Feature Description
Disable Automatic Off-line
Enable Automatic Off-line

A value of zero written by the host into the device's Sector Count register before issuing thissubcommand shall cause the automatic off-line data collection feature to be disabled. Disabling
this feature does not preclude the device from saving attribute values to nonvolatile memory
during some other normal operation such as during a power-on, during a power-off sequence, or
during an error recovery sequence. A value of F8h written by the host into the device's Sector
Count register before issuing this subcommand shall cause the automatic Off-line data collection
feature to be enabled. Any other non-zero value written by the host into this register before
issuing this subcommand is vendor specific and will not change the current Automatic Off-Line
Data Collection and Off-line Read Scanning status. However, the device may respond with the error
code specified in Table: “S.M.A.R.T. Error Codes” on 6.3.8 Error reporting.
6.3.2 Device Attribute Data Structure
The following defines the 512 bytes that make up the Attribute Value information. This data structure isaccessed by the host in its entirety using the S.M.A.R.T. Read Attribute Values subcommand.
Device Attribute Data StructureByte
0~1
2 ~ 361362
363
364 ~ 365366
367
368 ~ 369
370
371
372
373
374 ~ 510
511

Description
Data structure revision number
1st - 30th Individual attribute data
Off-line data collection status
Self-test execution status
Total time in seconds to complete off-line data collection activity
Vendor SpecificOff-line data collection capability
SMART capability
Error logging capability
7-1
Reserved
01=Device error logging supported
Self-test failure check point
Short self-test routine recommended polling time (in minutes)
Extended self-test routine recommended polling time (in minutes)
Reserved
Data structure checksum

6.3.2.1 Data Structure Revision Number
The Data Structure Revision Number identifies which version of this data structure is implemented
by the device. This revision number will be set to 0005h. This revision number identifies both the
Attribute Value and Attribute Threshold Data structures.
6.3.2.2 Individual Attribute Data Structure

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19

The following defines the 12 bytes that make up the information for each Attribute entry in the
Device Attribute Data Structure.
Byte

Description

0

Attribute ID number 01-FFh
Status flag
bit 0 (pre-failure/advisory bit)
bit 0 = 0: If attribute value is less than the threshold, the drive is in advisory condition.
Product life period may be expired.
bit 0 = 1: If attribute value is less than the threshold, the drive is in pre-failure
condition. The drive may have failure. bit 1 (on-line data collection bit)1~2
bit 1 = 0: Attribute value will be changed during off-line data collection operation.
bit 1 = 1: Attribute value will be changed during normal operation.
bit 2 (Performance Attribute bit)bit 3 (Error rate Attribute bit)
bit 4 (Event Count Attribute bit)bit 5 (Self-Preserving Attribute bit) bit 6-15 Reserved
Attribute value 01h-FDh *100h, FEh, FFh = Not in use
3
01h = Minimum value
64h = Initial value
Fdh = Maximum value
4
Worst Ever normalized Attribute Value (valid values from 01h-FEh)
Raw Attribute
5 ~ 10
Value Attribute specific raw data
(FFFFFFh - reserved as saturated value)
11
Reserved(00h)*1 For ID = 199 CRC Error Count
Attribute ID Numbers: Any nonzero value in the Attribute ID Number indicates an active attribute. The device supports
following Attribute ID Numbers.

Attribute name

ID

5
9
12
177
179
180
181
182
183
184
187
190
195
199
202
235
241
242
250

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Reallocated Sector CountPower-on Hours
Power-on Count
Wear Leveling Count
Used Reserved Block Count (total)
Unused Reserved Block Count (total)
Program Fail Count (total)
Erase Fail Count (total)
Runtime Bad Count (total)
End to End Error data path Error Count
Uncorrectable Error CountAir Flow Temperature
ECC Error Rate
CRC Error CountSSD Mode Status
Power Recovery Count
Total LBA Written
Total LBA Read
SATA Interface Downshifts (total)

20

6.3.2.3 Off-Line Data Collection Status
The value of this byte defines the current status of the off-line activities of the device. Bit 7
indicates an Automatic Off-line Data Collection Status.
Bit 7
0
1

Automatic Off-line Data Collection Status
Automatic Off-line Data Collection is disabled.
Automatic Off-line Data Collection is enabled.

Bits 0–6 represent a hexadecimal status value reported by the device
Value Definition
0
Off-line data collection never started.
2
All segments completed without errors. In this case the current segment pointer is equal to the total segments
required.
3
Off-line activity in progress.
4
Off-line data collection is suspended by the interrupting command.
5
Off-line data collecting is aborted by the interrupting command.
6
Off-line data collection is aborted with a fatal error.

6.3.2.4 Self-test execution status
Bit
0-3
4-7

Definition
Percent Self-test remaining. An approximation of the percent of the self-test routine remaining until completion
given in ten percent increments. Valid values are 0 through 9.
Current Self-test execution status.
0
The self-test routine completed without error or has never been run.
1
The self-test routine was aborted by the host.
2
The self-test routine was interrupted by the host with a hard or soft reset.
3
The device was unable to complete the self-test routine due to a fatal error or unknown test error.
4
The self-test routine was completed with an unknown element failure.
5
The self-test routine was completed with an electrical element failure.
6
The self-test routine was completed with a servo element failure.
7
The self-test routine was completed with a read element failure.
15
The self-test routine is in progress.

6.3.2.5 Total time in seconds to complete off-line data collection activity
This field tells the host how many seconds the device requires to complete the off-line data collection activity.

6.3.2.6 Current segment pointerThis byte is a counter indicating the next segment to execute as an off-line data collection activity. Because the number ofsegments is 1, 01h is always returned in this field

6.3.2.7 Off-line data collection capability
Bit
0
1
2

3
4
5
6
7

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Ver. 1.1, June, 2014

Definition
Execute Off-line Immediate implemented bit
0
S.M.A.R.T. Execute Off-line Immediate subcommand is not implemented
1
S.M.A.R.T. Execute Off-line Immediate subcommand is implemented
Enable/disable Automatic Off-line implemented bit
0
S.M.A.R.T. Enable/disable Automatic Off-line subcommand is not implemented
1
S.M.A.R.T. Enable/disable Automatic Off-line subcommand is implemented
Abort/restart off-line by host bit
0
The device will suspend off-line data collection activity after an interrupting command and resume itafter a vendor specific event
1
The device will abort off-line data collection activity upon receipt of a new command Bit Definition
Off-line Read Scanning implemented bit
0
The device does not support Off-line Read Scanning1
The device supports Off-line Read Scanning
Self-test implemented bit0
Self-test routing is not implemented
1
Self-test routine is implemented
Reserved (0)Selective self-test routine is not implemented0
Selective self-test routine is not implemented
1
Selective self-test routine is implemented
Reserved (0)216.3.2.8 S.M.A.R.T. Capability
This word of bit flags describes the S.M.A.R.T. capabilities of the device. The device will return 03h indicating that the device
will save its Attribute Values prior to going into a power saving mode and supports the S.M.A.R.T. ENABLE/DISABLE
ATTRIBUTE AUTOSAVE command.
Bit
0
1
2-15

Definition
Pre-power mode attribute saving capability. If bit = 1, the device will save its Attribute Values prior to going into a
power saving mode (Standby or Sleep mode).
Attribute auto save capability. If bit = 1, the device supports the S.M.A.R.T. ENABLE/ DISABLE ATTRIBUTE
AUTOSAVE command.
Reserved (0)6.3.2.9 Error logging capability
Bit
7-1
0

Definition
Reserved (0)The Error Logging support bit. If bit = 1, the device supports the Error Logging

6.3.2.10 Self-test failure check point
This byte indicates the section of self-test where the device detected a failure.

6.3.2.11 Self-test completion time
These bytes are the minimum time in minutes to complete the self-test.

6.3.2.12 Data Structure Checksum
The Data Structure Checksum is the 2's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data
structure.

6.3.3 Device Attribute Thresholds data structure
The following defines the 512 bytes that make up the Attribute Threshold information. This data structure is accessed by
the host in its entirety using the S.M.A.R.T. Read Attribute Thresholds. All multibyte fields shown in these data structures
follow the ATA/ATAPI-6 specification for byte ordering, that is, that the least significant byte occupies the lowest numberedbyte address location in the field. The sequence of active Attribute Thresholds will appear in the same order as theircorresponding Attribute Values
Device Attribute Thresholds Data Structure

Byte
0~1
2 ~ 361362 ~ 379
380 ~ 510
511

Description
Data structure revision number
1st - 30th Individual attribute data
Reserved
Vendor SpecificData structure checksum

6.3.3.1 Data Structure Revision NumberThis value is the same as the value used in the Device Attributes Values Data Structure.

6.3.3.2 Individual Thresholds Data Structure
The following defines the 12 bytes that make up the information for each Threshold entry in the Device Attribute
Thresholds Data Structure. Attribute entries in the Individual Threshold Data Structure are in the same order andcorrespond to the entries in the Individual Attribute Data Structure.

Byte
0

1

2~11

Description
Attribute ID Number (01h to FFh)
Attribute Threshold (for comparison with Attribute Values from 00h to FFh)00h - "always passing" threshold value to be used for code test purposes
01h - minimum value for normal operation
FDh - maximum value for normal operation
FEh - invalid for threshold value
FFh - "always failing" threshold value to be used for code test purposes
Reserved (00h)6.3.3.3 Attribute ID Numbers
Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures.

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6.3.3.4 Attribute Threshold
These values are preset at the factory and are not meant to be changeable. However, the host might use the "S.M.A.R.T.
Write Attribute Threshold" subcommand to override these preset values in the Threshold sectors.

6.3.3.5 Data Structure Checksum
The Data Structure Checksum is the 2's compliment of the result of a simple 8-bit addition of the first 511 bytes in the data
structure.

6.3.4 S.M.A.R.T. Log Directory
The following defines the 512 bytes that make up the S.M.A.R.T. Log Directory. The S.M.A.R.T. Log
Directory is on S.M.A.R.T. Log Address zero and is defined as one sector long.
S.M.A.R.T Log Directory
Byte
0~1
2
3
4
5
……
510
511

Description
S.M.A.R.T. Logging Version
Number of sectors in the log at log address 1
Reserved
Number of sectors in the log at log address 2
Reserved
Number of sectors in the log at log address 255
Reserved

The value of the S.M.A.R.T. Logging Version word shall be 01h. The logs at log addresses 80-9Fh aredefined as 16 sectors long.
6.3.5 S.M.A.R.T. error log sector
The following defines the 512 bytes that make up the S.M.A.R.T. error log sector. All multi-byte fields
shown in these data structures follow the ATA/ATAPI- 6 specifications for byte ordering.
S.M.A.R.T error log sectorByte
01
2 ~ 9192 ~ 181
182 ~ 271
272 ~ 361
362 ~ 451
452 ~ 453
454 ~ 510
511

Description
S.M.A.R.T. error log version
Error log pointer
1st error log data structure
2nd error log data structure
3rd error log data structure
4th error log data structure
5th error log data structure
Device error countReserved
Data structure checksum

6.3.5.1 S.M.A.R.T. error log version
This value is set to 01h.

6.3.5.2 Error log pointerThis value points to the most recent error log data structure. Only values 1 through 5 are valid.

6.3.5.3 Device error countThis field contains the total number of errors. The value will not roll over.

6.3.5.4 Error log data structure
The data format of each error log structure is shown below.

Error log data structureByten ~ n + 11
n + 12 ~ n + 23
n + 24 ~ n +35
n+36 ~ n + 47
n+48 ~ n + 59
n+60 ~ n+89

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Description
1st command data structure
2nd command data structure
3rd command data structure
4th command data structure
5th command data structure
Error data structure23

6.3.5.5 Command data structure
Data format of each command data structure is shown below.
Command data structure
Byte
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11

Description
Content of the Device Control register when the Command register was written
Content of the Features Control register when the Command register was written
Content of the Sector Count Control register when the Command register was written
Content of the LBA Low register when the Command register was written
Content of the LBA Mid register when the Command register was written
Content of the LBA High register when the Command register was written
Content of the Device/Head register when the Command register was written
Content written to the Command register
Timestamp
Timestamp
Timestamp
Timestamp

Timestamp shall be the time since power-on in milliseconds when command acceptance occurred. This timestamp
may wrap around.

6.3.5.6 Error data structure
Data format of error data structure is shown below.
Error data structure
Byte
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8 ~ n + 26
n+27
n+28
n+29

Description
Reserved
Content written to the Error register after command completion occurred.
Content written to the Sector Count register after command completion occurred.
Content written to the LBA Low register after command completion occurred.
Content written to the LBA Mid register after command completion occurred.
Content written to the LBA High register after command completion occurred.
Content written to the Device/Head register after command completion occurred.
Content written to the Status register after command completion occurred.
Extended error information
State
Life Timestamp (least significant byte)
Life Timestamp (most significant byte)

Extended error information is vendor specific which is not available for 845DC EVOState field contains a value indicating the device state when command is issued to the device.
Byte
x0h
x1h
x2h
x3h
x4h
x5h ~ xAh
xBh ~ xFh

Description
Unknown
Sleep
Standby
Active/Idle with BSY cleared to zero
Executing SMART off-line or self-test
Reserved
Vendor unique

Vendor unique is not available for 845DC EVO.

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6.3.6 Self-test log structure
The following defines the 512 bytes that make up a Self-test log sector.
Self-test log data structure
Byte

Description

0~1
n*24 + 2
n*24 + 3
n*24 + 4 ~ n*24 + 5
n*24 + 6
n*24 + 7 ~ n*24 + 10
n*24 +11 ~ n*24 + 25……
506 ~ 507
508
509 ~ 510
511

Data structure revision
Self-test number
Self-test execution status
Life timestamp
Self-test failure check point
LBA of first failure
Vendor specificVendor specificSelf-test log pointerReserved
Data structure checksum

NOTE : N is 0 through 20
The data structure contains the descriptor of the Self-test that the device has performed. Each descriptor is 24 bytes long andthe self-test data structure is capable to contain up to 21 descriptors. After 21 descriptors has been recorded, the oldest
descriptor will be overwritten with the new descriptor. The self-test log pointer points to the most recent descriptor. When
there is no descriptor, the value is 0. When there are descriptor(s), the value is 1 through 21.

6.3.7 Selective self-test log data structure
The Selective self-test log is a log that may be both written and read by the host. This log allows the host to selectthe parameters for the self-test and to monitor the progress of the self-test. The following table defines the contentsof the Selective self-test log which is 512 bytes long. All multi-byte fields shown in these data structures follow thespecifications for byte ordering.

Byte
0–1
2–9
10 – 1118 – 25
26 – 33
34 – 41
42 – 49
50 – 57
58 – 65
66 – 73
74 – 81
82 – 337
338 – 491
492 – 499
500 – 501
502 – 503
504 – 507
508 – 509
510
511

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Description
Data structure revision
Starting LBA for test span 1
Ending LBA for test span 1
Starting LBA for test span 2
Ending LBA for test span 2
Starting LBA for test span 3
Ending LBA for test span 3
Starting LBA for test span 4
Ending LBA for test span 4
Starting LBA for test span 5
Ending LBA for test span 5
Reserved
Vendor specific
Current LBA under test
Current span under test
Feature flags
Vendor SpecificSelective self-test pending time
Reserved
Data structure checksum

25

Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Vendor Specific
Read
Read
R/W
Vendor Specific
R/W
Reserved
R/W

6.3.8 Error reporting
The following table shows the values returned from the Status and Error Registers when specific error
conditions are encountered by a device.
S.M.A.R.T Error Codes
Error condition
A S.M.A.R.T. FUNCTION SET command was received by the device
without the required key being loaded into the LBA High and LBA
Mid registers.
A S.M.A.R.T. FUNCTION SET command was received by the device
with a subcommand value in the Features Register that is either
invalid or not supported by this device.
A S.M.A.R.T. FUNCTION SET command subcommand other than
S.M.A.R.T. ENABLE OPERATIONS was received by the device while
the device was in a "S.M.A.R.T Disabled" state.
The device is unable to read its Attribute Values or Attribute
Thresholds data structure
The device is unable to write to its Attribute Values data structure.

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26

StatusRegister

Error
Register

51h

04h

51h

04h

51h

04h

51h

10h or 04h

51h

10h or 04h

7. OOB signaling and Phy Power State
7.1 OOB signaling
7.1.1 OOB signal spacing
There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE. Each burst isfollowed by idle periods (at common-mode levels), having durations as depicted in following Figure and Table. The COMWAKE OOB
signaling is used to bring the Phy out of a power-down state (Partial or Slumber)

Time

Value

T1

106.7 ns

T2

320ns

7.2 Phy Power State
7.2.1 COMRESET sequence state diagram

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8. SPOR Specification (Sudden Power Off and Recovery)
8.1 Data Recovery in Sudden Power Off
If power interruption is detected, SSD dumps all cached user data and meta data to NAND Flash. SSD
could protect even the user data in DRAM from sudden power off while SSD is used with cache on.
Commonly, data is protected all of the operation period.

8.2 Time to Ready Sequence
In normal power-off recovery status, SSD needs less than 11 seconds to reach operating mode where SSD
works perfectly with cache-on state. SSD is ready to respond Identify Device command during FTL OPEN.
When the sudden power-off occurs, the user data in DRAM will be dumped into to NAND Flash using thestored power in the capacitor. In sudden power-off recovery condition, mapping data will be loaded or the
FTL meta data be rebuilt perfectly for initial max. 40 seconds. During this period, Identify Device commandis still supported. It is called SPOR.(Sudden Power Off and Recovery)

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9. SATA II Optional Feature
9.1 Asynchronous Signal Recovery
Phys may support asynchronous signal recovery for those applications where the usage model of device
insertion into a receptacle does not apply. When signal is lost, both the host and the device may attempt
to recover the signal. A host or device shall determine loss of signal as represented by a transition fromPHYRDY to PHYRDYn, which is associated with entry into states LSI: NoCommErr or LS2:NoComm within
the Link layer. Note that negation of PHYRDY does not always constitute a loss of signal. Recovery of thesignal is associated with exit from state LS2:NoComm. If the device attempts to recover the signal before
the host by issuing a COMINIT, the device shall return its signature following completion of the OOB
sequence which included COMINIT. If a host supports asynchronous signal recovery, when the host
receives an unsolicited COMINIT, the host shall issue a COMRESET to the device. When a COMRESET issent to the device in response to an unsolicited COMINIT, the host shall set the Status register to 7Fh andshall set all other Shadow Command Block Registers to FFh. When the COMINIT is received in response to
the COMRESET which is associated with entry into state HP2B:HR_AwaitNoCOMINIT, the Shadow Status
register value shall be updated to either FFh or 80h to reflect that a device is attached.

9.2 Power Segment Pin P11
Pin P11 of the power segment of the device connector may be used by the device to provide the hostwith an activity indication and it may be used by the host to indicate whether staggered spinup should be
used. To accomplish both of these goals, pin P11 acts as an input from the host to the device prior to
PHYRDY for staggered spin-up control and then acts as an output from the device to the host after
PHYRDY for activity indication. The activity indication provided by pin P11 is primarily for use in backplane
applications. A host may only support one pin P11 feature, either receiving activity indication or staggered
spin-up disable control. If a host supports receiving activity indication via pin P11, then the host shall notuse pin P11 to disable staggered spin-up. If a host does not support receiving activity indication via pin
P11, then the host may use pin P11 to disable staggered spin-up.

9.3 Activity LED indications
The signal provides for activity indication. This is a low-voltage and low-current driver intended for
efficient integration into present and future IC manufacturing processes. The signal is NOT suitable fordirectly driving an LED and must first be buffered using a circuit external to the drive before driving andLED. The LED indication signal is working on 200msec periods on FORMAT and Write same command.
(100ms at high state and then 100msec at low state) On the other case of commands, the signal is
working on 100msec periods.

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10. Product Compliance10.1 Product regulatory compliance and Certifications
Category

Certification

CE

Comunaute Europeenne

BSMI

Bureau of Standards, Metrology and Inspection

KCC

Korea Communications commission

VCCI

Voluntary Control Council for Interference

C-TickRadio Telecommunication Labeling

FCC

Federal Communications Commission

IC

Industry Canada

UL

Underwriters Laboratories, Inc.

TUVTechnischer Uberwachungs Vereine e.V
Scheme of the IECEE for Mutual Recognition of Test Certificates for Electrical
Equipment

CB

Caution: Any changes or modifications in construction of this device which are not expressly approved by
the party responsible for compliance could void the user's authority to operate the equipment.
NOTE :
This equipment has been tested and found to comply with the limits for a Class B digital device,pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection
against harmful interference in a residential installation This equipment generates, uses and canradiate radio frequency energy and, if not installed and used in accordance with the instructions, maycause harmful interference to radio communications, However, there is no guarantee thatinterference will not occur in a particular installation. If this equipment does cause harmfulinterference to radio or television reception, which can be determined by turning the equipment off
and on, the user is encouraged to try to correct the interference by one or more of the following
measures:- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and receiver.
- Connect the equipment into an outlet on a circuit different from that to which the receiver isconnected.
- Consult the dealer or an experienced radio/TV technician for help.
Modifications not expressly approved by the manufacturer could void the user's authority to operate theequipment under FCC rules.

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11. Identify Device Data
Word
0
1
2
3
4–5
6
7–8
9
10 – 19
20 – 2122
23 – 26
27 – 46
47
48
49
50
51-52
53
54-58
59
60
61
62
63
64
65
66
67
68
69
70 – 74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93

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400GB

800GB

Description

0040h
3FFFh
C837h
0010h
0000h
003Fh
0000h
0000h
XXXXh
0000h
0000h
XXXXh
XXXXh
8010h
4000h
2F00h
4000h
0200h
0007h
3FFFh
D110h
FFFFh
0FFFh
0000h
0007h
0003h
0078h
0078h
0078h
0078h
4F20h
0000h

0040h
3FFFh
C837h
0010h
0000h
003Fh
0000h
0000h
XXXXh
0000h
0000h
XXXXh
XXXXh
8010h
4000h
2F00h
4000h
0200h
0007h
3FFFh
D110h
FFFFh
0FFFh
0000h
0007h
0003h
0078h
0078h
0078h
0078h
4F20h
0000h

General information
Obsolete
Specific configuration
Obsolete
RetiredObsolete
Reserved for the Compact Flash Association
RetiredSerial Number (ATA string)
RetiredObsolete
Firmware revision (ATA string)
Model number
Read/Write Multiple Support
Trusted Computing feature set options
Capabilities
Capabilities
Obsolete
Field Validity
Obsolete
Multiple Logical Setting
Total number of user addressable logical sectors for 28-bit commands
Total number of user addressable logical sectors for 28-bit commands
Obsolete
Multi-word DMA transfer
PIO transfer modes supported
Minimum Multiword DMA transfer cycle time per word (ns)Manufacturer's recommended Multiword DMA cycle time (ns)Minimum PIO transfer cycle time without IORDY flow control (ns)Minimum PIO transfer cycle time with IORDY flow control (ns)
Additional supported
Reserved

001Fh

001Fh

Queue depth

850Eh

850Eh

Serial ATA capabilities

0046h

0046h

Reserved for Serial ATA

0064h

0064h

Serial ATA features supported

0064h

0064h

Serial ATA features enabled

03FCh

03FCh

Major version number

0039h

0039h

Minor version number

746Bh

746Bh

Commands and feature sets supported

7D01h

7D01h

Commands and feature sets supported

4163h

4163h

Commands and feature sets supported

7469h

7469h

Commands and feature sets supported or enabled

BC01h

BC01h

Commands and feature sets supported or enabled

4163h

4163h

Commands and feature sets supported or enabled

207Fh

207Fh

Ultra DMA Modes

0010h

0010h

Normal Security Erase Unit Time

0010h

0010h

Enhanced Security Erase Unit Time

0000h

0000h

Advanced Power Management Level

FFFEh

FFFEh

Master Password Revision Code

0000h

0000h

Hardware reset result

31

Word
94
95
96
97
98 – 99
100 – 103
104
105
106
107
108
109
110 – 111
112 – 115
116
117 – 118
119
120
121 – 126
127
128
129 – 159160
161 – 167
168
169
170 – 173
174 – 175
176 – 205
206
207 – 208
209
210 – 211
212 – 213214
215 – 216
217
218
219
220
221
222
223
224 – 229
230 – 233
234

400GB

800GB

0000h

0000h

Obsolete

0000h

0000h

Stream Minimum Request Size

0000h

0000h

Streaming Transfer Time - DMA

0000h

0000h

Streaming Access Latency - DMA and PIO

0000h

0000h

Streaming Performance Granularity (DWord)

XXXXh

XXXXh

Total Number of User 48-Bit LBA

0000h

0000h

Streaming Transfer Time - PIO

0008h

0008h

Maximum number of 512-byte data blocks of LBA Range Entries per DATA SETMANAGEMENT command

4000h

4000h

Physical sector size / logical sector size

0000h

0000h

Inter-seek delay for ISO 7779 standard acoustic testing 108 5002h

5002h

5002h

World wide name

5388h

5388h

World wide name

XXXXh

XXXXh

World wide name

0000h

0000h

Reserved

0000h

0000h

Reserved

0000h

0000h

Logical sector size (Dword)

235
236 - 242243
244-254255

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Description

401Eh

401Eh

Commands and feature sets supported

401Ch

401Ch

Commands and feature sets supported or enabled

0000h

0000h

Reserved for expanded supported and enabled settings

0000h

0000h

Obsolete

0029h

0029h

Security status

0000h

0000h

Vendor specific

0000h

0000h

CFA power mode

0000h

0000h

Reserved for the CFA(Compact Flash Association)

0000h

0000h

Device Nominal Form Factor

0001h

0001h

DATA SET MANAGEMENT is supported

2020h

2020h

Additional Product Identifier (ATA string)

0000h

0000h

Reserved

0000h

0000h

Current Media Serial Number

003Dh

003Dh

SCT Command Transport

0000h

0000h

Reserved

4000h

4000h

Alignment of logical blocks within a physical block

0000h

0000h

Write-Read-Verify Sector Count Mode 3

0000h

0000h

Write-Read-Verify Sector Count Mode 2

0000h

0000h

Obsolete

0000h

0000h

Obsolete

0001h

0001h

Nominal media rotation rate

0000h

0000h

Reserved

0000h

0000h

Obsolete

0000h

0000h

Write Read Verify Mode

0000h

0000h

Reserved

107Fh

107Fh

Transport major version number

0000h

0000h

Transport major version number

0000h

0000h

Reserved

0000h

0000h

Extended Number of User Addressable Sectors

0000h

0000h

0800h

0800h

0000h

0000h

Reserved

0000h

0000h

FDE_function

0000h

0000h

Reserved

0AA5h

0AA5h

Integrity Word

Minimum number of 512-byte data blocks per DOWNLOAD MICROCODE commandfor mode 03h
Minimum number of 512-byte data blocks per DOWNLOAD MICROCODE commandfor mode 03h32

12. Product line up
Density

Model Name

Model CodeBox Contents

240 GB

MZ-7GE240

MZ-7GE240EW

Basic (SSD, warranty, Label)

480 GB

MZ-7GE480

MZ-7GE480EW

Basic (SSD, warranty, Label)

960 GB

MZ-7GE960

MZ-7GE960EW

Basic (SSD, warranty, Label)

240 GB

MZ-7GE240

MZ-7GE240Z

Bulk (SSD)

480 GB

MZ-7GE480

MZ-7GE480Z

Bulk (SSD)

960 GB

MZ-7GE960

MZ-7GE960Z

Bulk (SSD)

For more information, please visit www.samsung.com/ssd.
To download the latest software & manuals, please visit www.samsung.com/samsungssd.

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