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CYW20721

Enhanced Low Power, Bluetooth LE
Bluetooth 5.1 SOC for Audio
CYW20721, Single-Chip Bluetooth Transceiver for Wearables and Internet of Things (IoT) Devices

The CYW20721 is a Bluetooth 5.1-compliant, stand-alone baseband processor with an integrated 2.4 GHz transceiver with
Bluetooth LE, EDR and BR. The device is intended for use in audio, IoT, sensors (medical, home, security, and so forth) and humaninterface device (HID) applications. Manufactured using an advanced 40nm CMOS low-power fabrication process, the CYW20721
employs high level of integration to reduce external components, thereby minimizing application footprint and costs.
This datasheet provides details of the functional, operational, and electrical characteristics of the CYW20721 device. It is intended for
hardware, design, application, and OEM engineers.

Functional Block Diagram

RF

MODEM

PKA

LCU

SHA

96 MHzARM CM4
w/FPU

Flash 1 MBRAM
448 KB

Patch RAM
64 KB

RX/TX

AES
ROM 2 MB

Bluetooth 5.0
MAC

Security Engine
Patch Control

AHB Bus Matrix

PWM x6

RandomNumber
Generator

Key Scan

ADC

Peripheral
UART

1x I2C M/S
1x I2CmasterHCI UART

Watchdog

SPIFFY X2(MIPI
DBI-C, SPI,
Quad SPI)

GPIO
x40

XTALOSC
32 KHz

LP- LPO
32 KHzXTALOSC
24 MHz

HID OFF
Timer

Clock Management

Hardware Peripheral Block

Cypress Semiconductor Corporation
Document Number: 002-26642 Rev. *F

HP- LPO128 KHz•198 Champion Court•

Core Buck

DigitalLDO

RF LDOPower Management
Unit

San Jose, CA 95134-1709•
408-943-2600
Revised February 14, 2022

CYW20721
Features
Bluetooth Subsystem

Peripherals and Communication■ Complies with Bluetooth Core Specification v5.1 with LE 2

■ 6x 16-bit PWMs

Mbps
■ Supports Basic Rate (BR), Enhanced Data Rate (EDR) 2&3
Mbps, Bluetooth Low Energy■ Supports Adaptive Frequency Hopping (AFH)■ TX power 5 dBm■ RX sensitivity -95.5 dBm (Bluetooth LE)■ Ultra-low-power radio❐ RX current 5.9 mA (Bluetooth LE)❐ TX current 5.6 mA @ 0 dBm (Bluetooth LE)■ Programmable key-scan matrix interface, up to 8x20 key1, 2scanning matrix■ Watchdog timer (WDT)■ 1x peripheral UART, 1x UART for programming and HCI■ 2x SPI (master or slave mode) Blocks (SPI, Quad SPI, and
MIPI DBI-C)
2■ 1x I C master■ 1x 28-channel ADC (10-ENoB for DC measurement and 12-

ENOB for Audio measurement)■ Hardware security engine

Coexistence Support■ Support for Global Coexistence Interface for easy coexis-

tence implementation with select Cypress Wi-Fi devices

General Purpose Input Output (GPIO)■ 16 GPIOs on QFN package■ 40 GPIOs on WLCSP package

MCU Subsystem®
■ 96-MHz Arm Cortex-M4 microcontroller unit MCU with float-

ing point unit (FPU)■ Supports serial wire debug (SWD)■ Runs Bluetooth stack and application■ Option to execute from on-chip flash or RAM■ Support up to 3.63 V operation■ Four GPIOs support 16 mA and 8 mA sink at 3.3 V and 1.8 V

respectively

Operating Voltage and Low-power Support■ Wide operating voltage range: 1.76V to 3.63V■ 5 power modes to implement ultra-low power application –Memory Subsystemmanaged by real time operating system■ 1 MB flash2■ 0.4 μA current in HID-OFF mode (wake from GPIO).

■ 512 KB RAM■ 2 MB ROM that stores Bluetooth stack and driver and off-

Packages

Audio Features and Interfaces■ 3.2 mm  3.1 mm 134-ball Wafer Level Chip Scale Package

loads flash for user applications(WLCSP)2■ 1x I S with master and slave modes

Software Support■ 1x PCM■ PDM■ Modus Toolbox. Features are subject to support in the Blue-2■ Analog front end for analog microphone■ 5 mm  5 mm 40-pin quad flat no-lead (QFN)

1

Clockstooth SDK.
■ Check the latest version of the Bluetooth SDK Technical brief
for supported features.

■ On-chip 32 kHz oscillator (LP-LPO)

Applications■ On-chip 128 kHz oscillator (HP-LPO)■ Wearables and Fitness bands■ 32 kHz crystal oscillator (Optional if low power modes not■ Headsets, earbuds, and other audio solutions

required)■ 24 MHz crystal oscillator■ 48-bit real time clock (RTC)■ Home automation■ Blood pressure monitors and other medical applications■ Proximity sensors■ Key Fobs
■ Thermostats and thermometers■ Toys

1. Available only in WLCSP Package.
2. Subjected to driver support in Bluetooth SDK.

Document Number: 002-26642 Rev. *F

Page 2 of 47

CYW20721
Contents
1. Bluetooth Baseband Core ........................................... 4
1.1 BQB and Regulatory Testing Support ................... 4
2. MCU ............................................................................... 5
3. External Reset ............................................................... 5
4. Power Management Unit (PMU) .................................. 5
5. Integrated Radio Transceiver ...................................... 6
5.1 Transmitter Path .................................................... 6
5.2 Receiver Path ........................................................ 6
5.3 Local Oscillator (LO) .............................................. 6
6. Peripheral and Communication Interfaces ................ 7
6.1 I2C Compatible Master .......................................... 7
6.2 HCI UART Interface .............................................. 7
6.3 Peripheral UART Interface .................................... 7
6.4 Crystal Oscillators ................................................. 7
6.5 Low-Frequency Clock Sources ............................. 9
6.6 GPIO Ports .......................................................... 10
6.7 Keyboard Scanner (Available only on
WLCSP Package) ............................................... 10
6.8 ADC ..................................................................... 10
6.9 PWM .................................................................... 11
6.10 Serial Peripheral Interface Block ....................... 12
6.11 Pulse Density Modulation (PDM) Microphone ... 12
6.12 I2S Interface ..................................................................... 12
6.13 PCM Interface ................................................................. 13
6.14 Security Engine ................................................. 14
6.15 Power Modes ................................................................... 14
7. Firmware ...................................................................... 15

Document Number: 002-26642 Rev. *F

8. Pin Assignments and GPIOs ..................................... 16
8.1 40-Pin QFN and WLCSP Pin Assignments ......... 16
8.2 40-Pin QFN and WLCSP GPIOs ......................... 18
9. Pin/Ball Maps .............................................................. 23
9.1 40-Pin QFN Pin Map ........................................... 23
9.2 WLCSP Ball Map ...............................................................24
10. Specifications ........................................................... 28
10.1 Electrical Characteristics ................................... 28
10.2 RF Specifications .............................................. 32
10.3 Timing and AC Characteristics .......................... 35
11. Mechanical Information ........................................... 40
11.1 40-Pin QFN Package ........................................ 40
11.2 WLCSP Package ............................................... 41
11.3 WLCSP Package Keep-out ............................... 42
11.4 Tape Reel and Packaging Specifications .......... 42
12. Ordering Information ................................................ 43
13. Acronyms .................................................................. 44
14. Document Conventions ........................................... 45
14.1 Units of Measure ............................................... 45
15. Document History Page ........................................... 46
15. Sales, Solutions, and Legal Information ................ 47
Worldwide Sales and Design Support ....................... 47
Products .................................................................... 47
PSoC® Solutions ...................................................... 47
Cypress Developer Community ................................. 47
Technical Support ..................................................... 47

Page 3 of 47

CYW20721
1. Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth operation. The
BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities
including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the hostcontroller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward
error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, anddata whitening/dewhitening.
Table 1. Bluetooth Features
Bluetooth 1.0

Bluetooth 1.2

Bluetooth 2.0

Basic Rate

Interlaced Scans

EDR 2 Mbps and 3 Mbps

SCO

Adaptive Frequency Hopping–

Paging and Inquiry

eSCO

–

Page and Inquiry Scan

–

–

Sniff

–

–

Bluetooth 2.1

Bluetooth 3.0

Bluetooth 4.0

Secure Simple Pairing

Unicast Connectionless Data

Bluetooth Low Energy

Enhanced Inquiry Response

Enhanced Power Control–

Sniff Subrating

eSCO

–

Bluetooth 4.1

Bluetooth 4.2

Bluetooth 5.0

Low Duty Cycle Advertising

Data Packet Length Extension

LE 2 Mbps

Dual Mode

LE Secure Connection

Slot Availability Mask

LE Link Layer Topology

Link Layer Privacy

High Duty Cycle Advertising

1.1 BQB and Regulatory Testing Support
The CYW20721 fully supports Bluetooth Test mode as described in Part 1:1 of the Specification of the Bluetooth System v3.0. This
includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence.
In addition to the standard Bluetooth Test Mode, the CYW20721 also supports enhanced testing features to simplify RF debugging
and qualification and type-approval testing. These features include:■

Fixed frequency carrier wave (unmodulated) transmission❐ Simplifies some type-approval measurements (Japan)❐ Aids in transmitter performance analysis■

Fixed frequency constant receiver mode
❐ Receiver output directed to I/O pin❐ Allows for direct BER measurements using standard RF test equipment❐ Facilitates spurious emissions testing for receive mode■

Fixed frequency constant transmission❐ 8-bit fixed pattern or PRBS-9❐ Enables modulated signal measurements with standard RF test equipment

Document Number: 002-26642 Rev. *F

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CYW20721
2. MCUThe CYW20721 includes a Cortex M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip
flash. The CM4 has a maximum speed of 96 MHz. CYW20721 supports execution from on-chip flash (OCF).
The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU).
The CM4 runs all the Bluetooth layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stacklayers freeing up the flash for application usage. A standard SWD Interface provides debugging support.

3. External Reset
An external active-low reset signal, RESET_N, can be used to put the CYW20721 in the reset state. The RESET_N should be released
only after the VDDO supply voltage level has been stabilized for at least 35 ms.

4. Power Management Unit (PMU)
Figure 1 shows the CYW20721 PMU block diagram. The CYW20721 includes an integrated buck regulator, a bypass LDO, a capless
LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once Vbat supply falls
below 2.1 V.
The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.
Figure 1. Default Usage ModePMU
VBAT: 1.76V to 3.63V

SR_VDDBAT3V
SR_VLX
VBATCore Buck
Regulator
CBUCK
Maximum 50 mA

DIGLDO_VDDOUT

DIGLDO_VDDIN

Digital LDO
Bluetooth Digital
SR_
PVSS

Internal LDO (capless)Bluetooth Retention
MemoryRFLDO_VDDOUT

BYPLDO
50 mA

RF LDO

Bluetooth RF

RFLDO_VDDIN

Denotes board pin
Denotes chip pin
Denotes power switch

Document Number: 002-26642 Rev. *F

Page 5 of 47

CYW20721
5. Integrated Radio Transceiver
The CYW20721 has an integrated radio transceiver that has been designed to provide low power operation in the globally available
2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and exceeds the requirements to provide
the highest communication link quality of service.

5.1 Transmitter Path
The CYW20721 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.
Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes
any frequency drift or anomalies in the modulation characteristics of the transmitted signal.
Power Amplifier
The CYW20721 has an integrated power amplifier (PA) that can transmit up to +5 dBm.

5.2 Receiver Path
The receiver path uses a low IF scheme to down-convert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in
the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYW20721 to be usedin most applications without off-chip filtering.
Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit
synchronization algorithm.
Receiver Signal Strength Indicator
The radio portion of the CYW20721 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller
to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether thetransmitter should increase or decrease its output power.

5.3 Local Oscillator (LO)LO provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels for BR/EDR functionality. The
CYW20721 uses an internal loop filter.

Document Number: 002-26642 Rev. *F

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CYW20721
6. Peripheral and Communication Interfaces
6.1 I2C Compatible Master
The CYW20721 provides a 2-pin I2C compatible Master interface to communicate with I2C compatible peripherals. The I2C compatible
master supports the following clock speeds:■

100 kHz■400 kHz■800 kHz (Not a standard I2C-compatible speed.)■

1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)

SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA
the GPIOs go into open drain mode and require an external pull-up for proper operation. I2C block does not support multi mastercapability by either master/slave devices.

6.2 HCI UART Interface
The CYW20721 includes a UART interface for factory programming as well as when operating as a Bluetooth HCI device in a systemwith an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates
from 115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available.
Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The
CYW20721 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.
The UART interface has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface
supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
During HCI mode the DEV_WAKE signal can be programmed to wake up the CYW20721 or allow the CYW20721 to sleep when radio
activities permit. The CYW20721 can also wake up the host as needed or allow the host to sleep via the HOST_WAKE signal. The
combined two signals allow the host and the CYW20721 to optimize system power consumption by allowing independent control of
low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor specific command.

6.3 Peripheral UART Interface
The CYW20721 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through theoptional I/O ports, which can be configured individually and separately for each functional pin. The CYW20721 can map the peripheral
UART to any GPIO (P0-P39). The Peripheral UART is functionally the same as HCI UART but with a 256 byte transmit and receive
FIFO.

6.4 Crystal Oscillators
6.4.1 24-MHz Crystal Oscillator
The CYW20721 uses a 24 MHz crystal oscillator (XTAL). The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth
specification. Two external load capacitors are required to work with the crystal oscillator. The selection of the load capacitors is XTALdependent (see Figure 2).
Figure 2. Recommended 24 MHz Oscillator Configuration

CL1
XIN
CrystalXOUT
CL2Document Number: 002-26642 Rev. *F

Page 7 of 47

CYW20721

Table 2. Reference Crystal Electrical Specifications
Parameter

Conditions

Min.
–

Typ.

Max.

Unit

24.000–MHz

Nominal frequency–

Oscillation mode–

Frequency accuracy

Includes operating temperature
range and aging

–

–

± 20

ppm

Equivalent series resistance

–

–

–

60

Ω

Fundamental–

Load capacitance

–

–

8

–

pF

Drive level

–

–

–

200

μW

Shunt capacitance

–

–

–

2

pF

6.4.2 32 kHz Crystal Oscillator
The CYW20721includes a 32 kHz oscillator to provide accurate timing during low power operations. Figure 3 shows the 32 kHz XTAL
oscillator with external components and Table 3 lists the oscillator’s characteristics. This oscillator can be operated with 32.768 kHz
crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 MΩ and C1 = C2 =~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.
Figure 3. Recommended 32 kHz Oscillator Electrical Specification
C2
3 2 .7 6 8 k H z
XTAL

R1

C1

Table 3. Reference 32 kHz Oscillator Electrical Specification
Parameter
Output frequency

SymbolFoscoutFrequency tolerance

Conditions

Typ.

Max.

Unit

–

32.768–kHz

Crystal-dependent

–

100

–

ppm

Tstartup

–

–

500

–

ms

XTAL drive level

Pdrv

For crystal selection

–

–

0.5

μW

XTAL series resistance

Rseries

For crystal selection

–

–

70

kΩ

XTAL shunt capacitance

CshuntFor crystal selection

–

–

2.2

pF

VIN (AC)

Ccouple = 100 pF;
Rbias= 10 MΩ

400

–

–

mVpp

Start-up time

External AC input amplitude

–

Min.

–

Document Number: 002-26642 Rev. *F

Page 8 of 47

CYW20721
6.5 Low-Frequency Clock Sources
The 32-kHz low-frequency clock (lhl_lpo_32-kHz on the following figure) can be obtained from multiple sources. There are two internal
low-power oscillators (LPOs) called the LP-LPO and HP-LPO and external crystal (OSC32K). The firmware determines the clock
source to use among the available LPOs depending on the accuracy and power requirements. The preferred source is the external
LPO (OSC32K) because it has good accuracy with the lowest current consumption. Internal LP-LPO has low current consumption
and low accuracy whereas HP-LPO has higher accuracy and higher current consumption. The firmware assumes the external LPO
has less than 250 PPM error with little or no jitter.
Figure 4. Simplified Clock Source
Variable
Frequency
DIV

Fixed
Frequency
Block

48/96
M

HCLK

CPU

DIV
XTAL 24M

ADPLL

1M

Timers

96 M
SPI2

SPI1

DIV

48 M
24 M

PUART

PTU

HCI UART

ADC(12 M)

24 M

DIV

24 M

I2C

1M
ACLK0

24 M

ACLK1

PWM(0‐5)

LPO

LPO

LPO

OSC32K
HP‐LPOlhl_lpo
32 K

LHL

LP‐LPO
RTC

Document Number: 002-26642 Rev. *F

Page 9 of 47

CYW20721
6.6 GPIO Ports
The CYW20721 has 40 GPIOs labeled P0-P39 on WLCSP package and 16 GPIOs on QFN package.
All GPIOs support the following:■

programmable pull-up/down of approx 45 k.

■

input disable, allowing pins to be left floating or analog signals connected without risk of leakage.

■source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.

■

P15 is Bonded to the same pin as XTALI_32K on the QFN package (Pin 32). If External 32.768kHz crystal is not used, then thispin can be used as GPIO P15.

■

P26/P27/P28/P29 (some of these pins are not available on QFN package) sink/source 16 mA at 3.3 V and 8 mA at 1.8 V.

Most peripheral functions can be assigned to any GPIO. For details, refer to Table 4 and Table 5.

6.7 Keyboard Scanner (Available only on WLCSP Package)
The CYW20721 includes a HW keyscanner that supports a maximum matrix size of 20x8. The scanner has 8 inputs (also referred toas rows) and 20 outputs (also referred to as columns). Keys are detected by driving the columns down sequentially and sampling therows. The HW scanner includes support for ghost key detection and debouncing. The scanner can also operate in sleep and PDS
mode allowing low power operation while continuing to detect/store all key strokes, up or down. In other low power modes, the scanner
can continue to monitor the matrix and initiate exit to active mode upon detecting a change of state.
Note Subject to the driver support in Bluetooth SDK.

6.8 ADCCYW20721includes is a Σ-Δ ADC designed for audio (13 bits) and DC (10 bits) measurements. The ADC can measure the voltage
on 28 GPIO. When used for analog inputs, the GPIOs must be placed in digital input disable mode to disconnect the digital circuitfrom the pin and avoid leakage. The internal band gap reference has ±5% accuracy without calibration. Calibration and digitalcorrection schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode.
■ P0, P1, P8-P18, P21-23, P28-P38 can be used as ADC inputs.

Document Number: 002-26642 Rev. *F

Page 10 of 47

CYW20721
6.9 PWM
The CYW20721 has six internal PWMs, labeled PWM0-5■

Each of the six PWM channels contains the following registers:❐ 16-bit initial value register (read/write)❐ 16-bit toggle register (read/write)❐ 16-bit PWM counter value register (read)

PWM configuration register is shared among PWM0–5 (read/write). This 6-bit register is used:❐ To enable/disable each PWM channel❐ To select the clock of each PWM channel❐ To invert the output phase of each PWM channel
The application can access the PWM module through the FW driver.
■

Figure 5 shows the structure of one PWM channel.
Figure 5. PWM Block Diagram
pwm#_init_val_adr register
enableclk_selo_flippwm_cfg_adr register

pwm#_togg_val_adr register

16

16

pwm#_cntr_adr

16
cntr value is ARM readable

pwm_out

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)
PWM cntr w/ pwm#_init_val = x (solid line)
16'HFFFF
pwm_togg_val_adr
16'Hx
16'H000

pwm#_init_value is x

Document Number: 002-26642 Rev. *F

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CYW20721
6.10 Serial Peripheral Interface Block
The CYW20721 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well
as MIPI DBI-C Interface. Either of the interface can be a master/slave. SPI2 can support only one slave. SPI1 has a 1024 byte transmit
and receive buffers which is shared with the host UART interface. SPI2 has a dedicated 256 byte transmit and receive buffers. To
support more flexibility for user applications, the CYW20721 has optional I/O ports that can be configured individually and separately
for each functional pin. SPI I/O voltage depends on VDDO.
6.10.1 MIPI interface
There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYW20721 plays the role of host, and only
the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins
are used. In the 8-bit mode, an additional pin DCX, indicating whether the current outgoing bit stream is a command or data byte isrequired.

6.11 Pulse Density Modulation (PDM) Microphone
The CYW20721 accepts a ΣΔ-based one-bit PDM input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates.
The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input
shares the filter path with the aux ADC. Two types of data rates can be supported:
■

8 kHz

■

16 kHzThe external digital microphone takes in a 2.4 MHz clock generated by the CYW20721 and outputs a PDM signal which is registeredby the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The
design can accommodate two simultaneous PDM input channels, so stereo voice is possible.
Note Subject to the driver support in Bluetooth SDK.

6.12 I2S Interface
The CYW20721 supports a single I2S digital audio port in both master and slave modes. The I2S signals are:■

I2S Clock: I2S SCK■I2S Word Select: I2S WS■

I2S Data Out: I2S DO■
2I2S Data In: I2S DI

I S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output and I2S DI
stays as input. The channel word length is fixed to 16 bits (frame length of 32 bits) and the data is justified so that the MSB of the leftchannel data is aligned with the MSB of the I2S bus, as per I2S Specifications. The MSB of each data word is transmitted one bit clock
cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted when I2S WS is low,
and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW20721 are synchronized with the falling edgeof I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK.
The I2S port is primarily used to transfer audio samples while using the A2DP profile[1]. The A2DP controller is half duplex and the
direction of the audio samples depend on the A2DP role (sink/source). The I2S clock in the master mode can either be■

44.1 kHz x 32 bits per frame = 1411.2 kHz■

48 kHz x 32 bits per frame = 1536 kHz

In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz.
Note PCM interface shares HW with the I2S interface which means that both voice and audio cannot be routed at the same time.

Note
1. The I2S port cannot be used at the application level for purposes other than routing A2DP audio samples.

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CYW20721
6.13 PCM Interface
The CYW20721 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode,
the CYW20721 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another device on
the PCM interface and are inputs to the CYW20721. Some of the parameters of the PCM interface may be configured by the host.
The PCM interface is used for full-duplex bi-directional transfer of 8K or 16K voice samples from and to a SCO or eSCO connection[2].
By default, the PCM interface runs in an I2S compatible mode, which allows the CYW20721 to transfer voice samples to I2S devices.
Note PCM interface shares HW with the I2S interface which means that both voice and audio cannot be routed simultaneously.
6.13.1 Slot Mapping
The CYW20721 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface, when operatingin HCI mode. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8
kHz or 16 kHz voice sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface
rate (128 kHz, 256kHz, 512 kHz, 1024 kHz or 2048 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output
driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver
tristates its output after the falling edge of the PCM clock during the last bit of the slot.
6.13.2 Frame Synchronization
The CYW20721 supports both short and long-frame synchronization in both master and slave modes and can be configured from thehost. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is asingle-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge ofthe bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode,the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods andthe pulse starts coincident with the first bit of the first slot.
6.13.3 Data Formatting
The CYW20721 may be configured to generate or accept several different data formats. For conventional narrow band speech mode,
the CYW20721 always uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support
various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit,or a programmed value on the output. The default format is 13-bit 2's complement data, left justified, filled with 0's and clocked MSB
first.
6.13.4 Burst PCM ModeIn this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation andsave current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated withan HCI command from the host.

Note
2. The PCM interface cannot be used as a generic serial interface at the application level. It can only be used for routing SCO or eSCO voice samples.

Document Number: 002-26642 Rev. *F

Page 13 of 47

CYW20721
6.14 Security Engine
The CYW20721 includes a hardware security accelerator which greatly decreases the time required to perform typical security
operations.This security engine includes:■

Public key acceleration (PKA) cryptography■

AES-CTR/CBC-MAC/CCM acceleration■

SHA2 message hash and HMAC acceleration■

RSA encryption and decryption of modulus sizes up to 2048 bits■

Elliptic curve Diffie-Hellman in prime field GF(p)Note Security engine is used only by Bluetooth stack to reduce CPU overhead. It is not available for application use
6.14.1 Random Number Generator
This hardware block is used for key generation for Bluetooth.
Note Availability for use by the application is subject to the support in Bluetooth SDK.

6.15 Power Modes
The CYW20721 supports the following HW power modes:■

Active mode - Normal operating mode in which all peripherals are available and the CPU is active.

■

Idle mode- In this mode, the CPU is in “Wait for Interrupt” (WFI) and the HCLK, which is the high frequency clock derived from themain crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained.

■

Sleep mode - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off
and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU),
and SRAM is retained.

■

Power Down Sleep (PDS) mode -This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and
SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused.

■

Shut Down Sleep (SDS) mode -Everything is turned off except I/O Power Domain, RTC, and LPO. The device can come out of
this mode either due to Bluetooth activity or by an external interrupt. Before going into this mode, the application can store somebytes of data into “Always On RAM” (AON). When the device comes out of this mode, the data from AON is restored. After waking
from SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON.
In the SDS mode, a single Bluetooth task with no data activity, such as an ACL connection, Bluetooth LE connection, or Bluetooth
LE advertisement can be performed.

■■

HID-OFF[3] (Timed-Wake) mode -The device can enter this mode asynchronously, that is, the application can force the device into
this mode at any time. I/O Power Domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wakethe device up after a predetermined fixed time.
HID-OFF[3] (External Interrupt-Waked) mode - This mode is similar to Timed-Wake, but in HID-OFF mode even the LPO and RTC
are turned off. Therefore, the only wakeup source is an external interrupt.

Transition between power modes is handled by the on-chip firmware with host/application involvement. Please see Firmware Section
for details.

Note
3. Subject to driver support in Bluetooth SDK.

Document Number: 002-26642 Rev. *F

Page 14 of 47

CYW20721
7. Firmware
The CYW20721 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip
hardware functions as well as the Bluetooth/LE baseband, Link Manager (LM), HCI, Generic Attribute Profile (GATT), AttributeProtocol (ATT), Logical Link Control and Adaptation Protocol (L2CAP) and Service Discovery Protocol (SDP) layers. The ROM also
includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between
different power modes.
The CYW20721 is fully supported by the Cypress Modus Toolbox platform. Bluetooth SDK releases provide latest ROM patches,
drivers, and sample applications allowing customized applications using the CYW20721 to be built quickly and efficiently.
Refer to CYW20721 Product Guide for details on the firmware architecture, driver documentation, power modes and how to write
applications/profiles using the CYW20721.

Document Number: 002-26642 Rev. *F

Page 15 of 47

CYW20721
8. Pin Assignments and GPIOs
This section addresses both QFN and WLCSP pin assignments and GPIOs for the CYW20721 device.

8.1 40-Pin QFN and WLCSP Pin Assignments
Table 4. 40-Pin QFN and WLCSP Pin Assignments
Pin Name

Pin Number
QFN-40

WLCSP

–

5

I/O

Power Domain

I

VDDIO

Description

Microphone
ADC_avddBAT

VDDIO

ADC_AVDDC

–

3

I

–

Mic_avdd–

19

I

MIC_AVDDNo Connect

Micbias–32

I

MIC_AVDD

Microphone Bias Supply

Micn

–

4

I

MIC_AVDD

Microphone negative input

Micp

–

18

I

MIC_AVDD

Microphone positive input

ADC_AVSS

–

34

I

AVSS

Microphone supply

Analog ground

ADC_AVSSC

–

17

I

AVSS

Analog ground

ADC_REFGND

–

33

I

AVSS

Analog reference groundMic_avss

–

47

I

AVSS

Microphone analog ground

BT_VDDO25

1,8,9,11,14,26,29,4
2,56,66,91

I

VDDO

I/O Pad Power supply

BT_VDDC–

2,43,58,74,
99

I/O

VDDC

Baseband core power supply

VDDO

39

-

I

VDDO

LHL PAD power supply. Can be tied to
BT_VDDO.
PA supply

Baseband Supply

RF Power Supply
BT_PAVDD

17

116

I

PAVDD

BT_PLLVDD1p2

21

106

I

PLLVDD1P2

RFPLL and crystal oscillator supply

BT_VCOVDD1p2

20

125

I

VCOVDD1P2

VCO supply

BT_IFVDD1P2

19

110

I

IFVDD1P2

IFPLL Power Supply

16

127

I

DIGLDO_VDDOUT

–

126

O

RFLDO_VDDIN

15

111

I

–

RF LDO Input

RFLDO_VDDOUT

14

128

O

–

RF LDO Output

SR_VDDBAT3V

13

129

I

–

Core Buck Input

VDDBAT3V

–

120

I

–

Core Buck Input

SR_VLX

12

121

O

–

Core Buck Output

–

123

I

VSS

BT_PLLVSS

–

107

I

VSS

GroundBT_VCOVSS

–

119

I

VSS

GroundBT_IFVSS

–

115

I

VSS

Ground–30, 57, 75, 87, 117,
118, 124, 133, 134I

VSSGroundOnboard LDO’s
DIGLDO_VDDINInternal Digital LDO inputInternal Digital LDO output

Ground Pins
BT_PAVSS

BT_VSSC

Document Number: 002-26642 Rev. *F

GroundPage 16 of 47

CYW20721
Table 4. 40-Pin QFN and WLCSP Pin Assignments (Cont.)
Pin Name

Pin Number

I/O

Power Domain

112

I

VSS

Ground–10,13, 25, 28,72,
96,101I

VSS

GroundSR_PVSS

–

130

I

VSS

Groundxtal_avss

–

35

I

XTAL_AVSS

Crystal ground

PMU_AVSS–

113,114I

PMU_AVSSPMU ground

VSS

H

–

I

VSS

Exposed center pad, connect to ground.

BT_UART_CTS_N

30

15

I, PU

VDDO

Clear to send (CTS) for HCI UART
interface. Leave unconnected if not
used.

BT_UART_RTS_N

29

31

O, PU

VDDO

Request to send (RTS) for HCI UART
interface. Leave unconnected if not
used.

BT_UART_RXD

27

45

I

VDDO

UART serial input. Serial data input for
the HCI UART interface.

BT_UART_TXD

28

46

O, PU

VDDO

UART serial output. Serial data output
for the HCI UART interface.

QFN-40

WLCSP

VSSC

–

VSSO_0Description

UART

Crystal

BT_XTALI

22

105

I

PLLVDD1P2

Crystal oscillator input. See “The XTAL
must have an accuracy of ±20 ppm as
defined by the Bluetooth specification.
Two external load capacitors are
required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see Figure 2)”
for options.

BT_XTALO

23

104

O

PLLVDD1P2

Crystal oscillator output.

XTALI_32K

32

6

I

VDDO

Low-power oscillator input.

XTALO_32K

31

20

O

VDDO

Low-power oscillator output.

BT_RF

18

132

–

–

RF Antenna Port

BT_CLK_REQ

–

68

O

N/A

Used for shared-clock application.

JTAG_SEL

11

102

–

–

Reserved Arm® JTAG debug mode
control. Connect to GND for all applications.

RST_N

10

103

I

VDDO

Active-low system reset with internal
pull-up resistor.

Reserved

26

21, 36, 49, 61, 77,
84, 85, 108

N/A

N/A

Reserved. Leave unconnected.

Reserved, Connect to
GND–

16, 92

N/A

N/A

Reserved, connect to GND

Reserved Pins

Document Number: 002-26642 Rev. *F

Page 17 of 47

CYW20721
8.2 40-Pin QFN and WLCSP GPIOs
Table 5. 40-Pin QFN and WLCSP GPIOs
Pin Number

I/O

Power
DomainDescription

86

I

VDDO

A signal from the host to the CYW20721 indicating thatthe host requires attention.

24

76

O

VDDO

A signal from the CYW20721 device to the hostindicating that the Bluetooth device requires attention.

BT_GPIO_2

–

44

I/O

VDDO

GPIO: Can also be configured as a GCI Pin

BT_GPIO_3

–

59

I/O

VDDO

GPIO: Can also be configured as a GCI Pin

BT_GPIO_4

–

79

I/O

VDDO

GPIO: Can also be configured as a GCI Pin

BT_GPIO_5

–

78

I/O

VDDO

GPIO: Can also be configured as a GCI Pin
GPIO: P0
Keyboard scan input (row): KSI0
A/D converter input 29
Supermux I/O functions as defined in Table 6.

Pin Name

QFN-40WLCSP

BT_DEV_WAKE–

BT_HOST_WAKE

P0

3

93

I/O

VDDO

■
■
■
■

P1

4

54

I/O

VDDO

■
■
■
■

GPIO: P1
Keyboard scan input (row): KSI1
A/D converter input 28
Supermux I/O functions as defined in Table 6

P2

34

60

I/O

VDDO

■
■
■

GPIO: P2
Keyboard scan input (row): KSI2
Supermux I/O functions as defined in Table 6

P3

–

22

I/O

VDDO

■
■
■

GPIO: P3
Keyboard scan input (row): KSI3
Supermux I/O functions as defined in Table 6

P4

35

23

I/O

VDDO

■
■
■

GPIO: P4
Keyboard scan input (row): KSI4
Supermux I/O functions as defined in Table 6

P5

–

37

I/O

VDDO

■
■
■

GPIO: P5
Keyboard scan input (row): KSI5
Supermux I/O functions as defined in Table 6

P6

36

50

I/O

VDDO

■
■
■

GPIO: P6
Keyboard scan input (row): KSI6
Supermux I/O functions as defined in Table 6

P7

37

62

I/O

VDDO

■
■
■

GPIO: P7
Keyboard scan input (row): KSI7
Supermux I/O functions as defined in Table 6

P8

–

69

I/O

VDDO

■
■
■

GPIO: P8
A/D converter input 27
Supermux I/O functions as defined in Table 6

P9

–

52

I/O

VDDO

■
■
■
■

GPIO: P9
A/D converter input 26
External T/R switch control: tx_pd
Supermux I/O functions as defined in Table 6

VDDO

■
■
■
■

GPIO: P10
Keyboard scan output (column): KSO2
A/D converter input 25
Supermux I/O functions as defined in Table 6

P10

40

63

I/O

Notes
4. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.
5. During power-on reset, all inputs are disabled.
6. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow
through these pins until the part comes out of reset.

Document Number: 002-26642 Rev. *F

Page 18 of 47

CYW20721
Table 5. 40-Pin QFN and WLCSP GPIOs (Cont.)
Pin Number

I/O

Power
Domain

70

I/O

VDDO

■
■
■

GPIO: P11
A/D converter input 24
Supermux I/O functions as defined in Table 6

–

40

I/O

VDDO

■
■
■

GPIO: P12
A/D converter input 23
Supermux I/O functions as defined in Table 6

P13

–

71

I/O

VDDO

■
■
■

GPIO: P13
A/D converter input 22
Supermux I/O functions as defined in Table 6

P14

–

24

I/O

VDDO

■
■
■

GPIO: P14
A/D converter input 21
Supermux I/O functions as defined in Table 6

P15c

32

7

I/O

VDDO

■
■
■

GPIO: P15
A/D converter input 20
Supermux I/O functions as defined in Table 6

P16

33

48

I/O

VDDO

■
■
■

GPIO: P16
A/D converter input 19
Supermux I/O functions as defined in Table 6

P17

38

38

I/O

VDDO

■
■
■

GPIO: P17
A/D converter input 18
Supermux I/O functions as defined in Table 6

P18

–

51

I/O

VDDO

■
■
■

GPIO: P18
A/D converter input 17
Supermux I/O functions as defined in Table 6

P19

–

39

I/O

VDDO

■

Reserved for system use. Leave unconnected.

P20

–

12

I/O

VDDO

■

Reserved for system use. Leave unconnected.

P21

–

53

I/O

VDDO

■
■
■

GPIO: P21
A/D converter input 14
Supermux I/O functions as defined in Table 6

P22

–

27

I/O

VDDO

■
■
■

GPIO: P22
A/D converter input 13
Supermux I/O functions as defined in Table 6

P23

–

64

I/O

VDDO

■
■
■

GPIO: P23
A/D converter input 12
Supermux I/O functions as defined in Table 6

P24

–

90

I/O

VDDO

■
■

GPIO: P24
Supermux I/O functions as defined in Table 6

P25

8

97

I/O

VDDO

■
■

GPIO: P25
Supermux I/O functions as defined in Table 6

P26

7

83

I/O

VDDO

■
■
■

GPIO: P26
Current: 16 mA sink
Supermux I/O functions as defined in Table 6

P27

–

94

I/O

VDDO

■
■
■

GPIO: P27
Current: 16 mA sink
Supermux I/O functions as defined in Table 6

P28

1

41

I/O

VDDO

■
■
■
■

GPIO: P28
A/D converter input 11
Current: 16 mA sink
Supermux I/O functions as defined in Table 6

Pin Name

QFN-40

WLCSP

P11

–

P12

Description

Notes
4. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.
5. During power-on reset, all inputs are disabled.
6. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow
through these pins until the part comes out of reset.

Document Number: 002-26642 Rev. *F

Page 19 of 47

CYW20721
Table 5. 40-Pin QFN and WLCSP GPIOs (Cont.)
Pin Number

I/O

Power
Domain

80

I/O

VDDO

■
■
■
■

GPIO: P29
A/D converter input 10
Current: 16 mA sink
Supermux I/O functions as defined in Table 6

–

95

I/O

VDDO

■
■
■

GPIO: P30
A/D converter input 9
Supermux I/O functions as defined in Table 6

P31

–

73

I/O

VDDO

■
■
■

GPIO: P31
A/D converter input 8
Supermux I/O functions as defined in Table 6

P32

–

98

I/O

VDDO

■
■
■

GPIO: P32
A/D converter input 7
Supermux I/O functions as defined in Table 6

P33

9

100

I/O

VDDO

■
■
■

GPIO: P33
A/D converter input 6
Supermux I/O functions as defined in Table 6

P34

5

81

I/O

VDDO

■
■
■

GPIO: P34
A/D converter input 5
Supermux I/O functions as defined in Table 6

P35

–

65

I/O

VDDO

■
■
■

GPIO: P35
A/D converter input 4
Supermux I/O functions as defined in Table 6

P36

–

55

I/O

VDDO

■
■
■

GPIO: P36
A/D converter input 3
Supermux I/O functions as defined in Table 6

P37[6]

–

88

I/O

VDDO

■
■
■

GPIO: P37
A/D converter input 2
Supermux I/O functions as defined in Table 6

P38

6

89

I/O

VDDO

■
■
■

GPIO: P38
A/D converter input 1
Supermux I/O functions as defined in Table 6

P39

–

82

I/O

VDDO

■

Reserved for system use. Leave unconnected.

BT_TM1

–

67

I

–

PMU_DISABLE

–

109

I

VDDO

Pin Name

QFN-40

WLCSP

P29

2

P30

Description

Strapping Pins
Device test mode control. Connect to GND for all applications.
PMU Enable/Disable. Connected to ground.

Notes
4. All GPIOs are super mux. All GPIOs can be programmed for any alternative functions as listed in Table 6 and Table 7.
5. During power-on reset, all inputs are disabled.
6. P15 and P37 should not be driven high externally while the part is held in reset (they can be floating or driven low). Failure to do so may cause some current to flow
through these pins until the part comes out of reset.

Document Number: 002-26642 Rev. *F

Page 20 of 47

CYW20721

Table 6. GPIO Supermux Input Functions
Input

Table 7. GPIO Supermux Output Functions

Description

OutputDescription

SWDCK

Serial Wire Debugger Clock

do_P# (data out of GPIO. For example: 0)

SWDIO

Serial Wire Debugger I/O

kso0

Key Scan output 0

spiffy1_clk[s]SPIFFY 1 Clock (Slave)kso1

Key Scan output 1

spiffy1_cs[s]SPIFFY 1 Chip Select (Slave)kso2

Key Scan output 2

spiffy1_mosi[s]SPIFFY 1 MOSI (Slave)kso3

Key Scan output 3

spiffy1_miso[m]SPIFFY 1 MISO (Master)

kso4

Key Scan output 4

spiffy1_io2

SPIFFY 1 I/O 2 (Quad SPI)

kso5

Key Scan output 5

spiffy1_io3

SPIFFY 1 I/O 3 (Quad SPI)

kso6

Key Scan output 6

spiffy1_int[s]SPIFFY 1 Interrupt (Slave)

kso7

Key Scan output 7

spiffy2_clk[s]SPIFFY 2 Clock (Slave)

kso8

Key Scan output 8

spiffy2_cs[s]SPIFFY 2 Chip Select (Slave)

kso9

Key Scan output 9

spiffy2_mosi[s]SPIFFY 2 MOSI (Slave)

kso10

Key Scan output 10

spiffy2_miso[m]SPIFFY 2 MISO (Master)

kso11

Key Scan output 11

spiffy2_io2

SPIFFY 2 I/O 2

kso12

Key Scan output 12

spiffy2_io3

SPIFFY 2 I/O 3

kso13

Key Scan output 13

spiffy2_int[s]SPIFFY 2 Interrupt (Slave)

kso14

Key Scan output 14

puart_rx

Peripheral UART RX

kso15

Key Scan output 15

puart_cts_n

Peripheral UART CTS

kso16

Key Scan output 16

SCL

I2C Clockkso17

Key Scan output 17

SDA

I2C Data

kso18

Key Scan output 18

PCM_INPCM Input

kso19

Key Scan output 19

PCM_CLKPCM Clock

do_P# ^ pwm0

PWM Channel 0

PCM_SYNCPCM Sync

do_P# ^ pwm1

PWM Channel 1

I2S_DII2S Data Input

do_P# ^ pwm2

PWM Channel 2

I2S_WSI2S Word Select

do_P# ^ pwm3

PWM Channel 3

I2S_CLKI2S Clock

do_P# ^ pwm4

PWM Channel 4

PDM_IN_Ch_1

PDM Input Channel 1

do_P# ^ pwm5

PWM Channel 5

PDM_IN_Ch 2

PDM Input Channel 2

aclk0

Auxiliary clock Output 0

aclk1

Auxiliary clock Output 1

HID_OFF

HID-OFF Indicatorpa_ramp

External PA ramp

tx_pu

External PA Control Signal

rx_pu

External PA Control Signal

SWDIO

Serial Wire Debugger Input/
Outputpuart_tx (uart2_tx)

Peripheral UART TX

puart_rts_n (uart2_rts_n)

Peripheral UART RTS

spiffy1_CLK

SPIFFY 1 Clock

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CYW20721
Table 7. GPIO Supermux Output Functions (Cont.)
OutputDescription

spiffy1_CS

SPIFFY 1 Chip Selectspiffy1_MOSISPIFFY 1 MOSI

spiffy1_MISOSPIFFY 1 MISO

spiffy1_IO2SPIFFY I/O 2

spiffy1_IO3SPIFFY I/O 3

spiffy1_INTSPIFFY Interrupt

spiffy1_DCX

MIPI-DBI Data/Command
Indicator

spiffy2_CLK

SPIFFY 2 Clockspiffy2_CS

SPIFFY 2 Chip Selectspiffy2_MOSISPIFFY 2 MOSI

spiffy2_MISOSPIFFY 2 MISO

spiffy2_IO2SPIFFY 2 I/O 2

spiffy2_IO3SPIFFY 2 I/O 3

spiffy2_INTSPIFFY 2 Interrupt

spiffy2_DCX

MIPI-DBI Data/Command
Indicator

pcm_in_o

PCM IN

pcm_out_o

PCM Out

pcm_bclk_o

PCM Bit Clockpcm_sync_o

PCM Sync Output

i2s_ssd

I2S Slave Serial Data

i2s_sws

I2S Slave Word Selecti2s_sckI2S Slave Clocki2s_msd

I2S Master Serial Data

i2s_mws

I2S Master Word Selecti2s_mck

I2S Master Clock

Document Number: 002-26642 Rev. *F

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CYW20721
9. Pin/Ball Maps
9.1 40-Pin QFN Pin Map
The CYW20721 40-pin QFN package is shown in Figure 6.
Figure 6. 40-Pin QFN Pin Map
40

39

38

37

36

35

34

33

32

31

P10

LHL_VDDO

P17

P7

P6

P4

P2

P16

xtali_32k/
P15xtalo_32K

1

P28

UART_
CTS_N

30

2

P29

UART_
RTS_N

29

3

P0

UART_TXD

28

4

P1

UART_RXD

27

5

P34

RSVD

26

6

P38

BT_VDDO

25

7

P26

HOST_
WAKE

24

8

P25

XTALO

23

9

P33

XTAL1

22

10

RST_N

PLLVDD1p2

21

CYW20721 5x5 QFN-40

JTAG_SEL

SR_VLXSR_VDDBAT3V

RFLDO_VDDOOUTRFLDO_VDDIN

DIGLDO_
VDDIN

PAVDD

BT_RF

IFVDD1p2

VCOVDD1p2

11

12

13

14

15

16

17

18

19

20

Document Number: 002-26642 Rev. *F

Page 23 of 47

CYW20721
9.2 WLCSP Ball Map
The CYW20721 WLCSP package is shown in Figure 7.
Figure 7. WLCSP Ball Map

14

13

12

11

10

9

8

7

6

5

4

3

2

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

42

41

40

39

38

37

36

35

34

33

32

31

30

29

55

54

53

52

51

50

49

48

47

46

45

44

43

66

65

64

63

62

61

60

59

58

57

56

73

72

71

70

69

68

67

83

82

81

80

78

77

76

75

91

90

89

88

87

86

85

84

98

97

96

95

103

102

101

100

109

114

74

79

94

93

92

99

108

113

110

112

111

121

120

131

130

129

104

106

107

115
118

122

105

116

117

123
119
124

128

127

125

126
134

133

132

Notes
7. Figure 7 shows the bottom view of the WLCSP package (Bumps facing up).
8. See Table 4 and Table 8 and for additional WLCSP information.
9. Table 8 shows the package view from the bottom (bumps facing up).
10. Coordinate origin (0, 0) is at the center of the WLCSP package with the bumps facing up.

Document Number: 002-26642 Rev. *F

Page 24 of 47

CYW20721
Table 8. CYW20721 WLCSP Bump Coordinates
Bump#

NET_NAME

X-COORD (μm)

Y-COORD (μm)

1

BT_VDDO1232.28

1356.88

2

BT_VDDC1032.28

1356.88

3

Reserved - Do not connect

832.281356.884

Micn

632.281356.885

ADC_avddBAT

432.281356.886

xtali_32K

232.291356.88

7

P15

32.29

1356.888

VDDO_0-167.71356.889

VDDO_0-367.71356.8810

VSSO_0-567.71356.8811

VDDO_0-767.71356.8812P20-967.69

1356.8813

VSSO_0-1167.69

1356.88

14

VDDO_0-1367.69

1356.88

15

BT_UART_CTS_N

1232.28

1156.88

16

Reserved, Connect to GND

1032.28

1156.8817

ADC_AVSSC

832.281156.8818

Micp632.281156.8819

Mic_avdd

432.281156.8820

xtalo_32K

232.291156.88

21

Reserved

32.29

1156.8822P3-167.71156.8823P4-367.71156.8824

P14-567.71156.881156.8825

VSSO_0-767.726

VDDO_0-967.69

1156.8827

P22-1167.69

1156.8828

VSSO_0-1367.69

1156.88

29

BT_VDDO1232.28956.8830

BT_VSSC1032.28956.8831

BT_UART_RTS_N

832.28956.8832

Micbias632.28956.8833

ADC_REFGND

432.28956.8834

ADC_AVSS

232.29956.8835

xtal_avss

32.29

956.8836

Reserved-167.7956.88956.8837P5-367.738P17-567.7956.8839P19-767.7956.8840P12-967.69956.8841P28-1167.69

956.8842

VDDO_0-1367.69

956.8843

BT_VDDC

1232.28756.8944

BT_GPIO_2

1032.28756.8945

BT_UART_RXD

832.28756.8946

BT_UART_TXD

632.28756.89Document Number: 002-26642 Rev. *F

Page 25 of 47

CYW20721
Table 8. CYW20721 WLCSP Bump Coordinates (Cont.)
Bump#

X-COORD (μm)

Y-COORD (μm)

47Mic_avss

NET_NAME

432.28756.89

48

P16

32.29

756.8949

Reserved-167.7756.8950

P6-367.7756.8951P18-567.7756.8952

P9-767.7756.8953

P21-967.69756.8954

P1-1167.69

756.8955

P36-1367.69

756.8956

BT_VDDO1232.28556.8957

BT_VSSC1032.28556.8958

BT_VDDC

832.28556.8959

BT_GPIO_3

632.28556.89

60

P2

32.29

556.8961

Reserved-167.7556.8962P7-367.7556.8963P10-767.7556.8964P23-967.69556.8965

P35-1167.69

556.8966

VDDO_0-1367.69

556.8967

BT_TM11232.28356.8968

BT_CLK_REQ

1032.28356.8969P8-367.7356.8970P11-767.7356.8971P13-967.69356.8972

VSSO_0-1167.69

356.8973

P31-1367.69

356.8974

BT_VDDC

401.88322.9475

BT_VSSC

1432.27

156.8976

BT_HOST_WAKE

1232.28

156.8977

Reserved

1032.28

156.8978

BT_GPIO_5

832.28156.8979

BT_GPIO_4

632.28156.8980P29-767.7156.8981P34-967.69

156.8982

P39-1167.69

156.8983

P26-1367.69

156.8984

Reserved

1432.27-43.1

85

Reserved

1232.28-43.1

86BT_DEV_WAKE

1032.28-43.1

87

BT_VSSC

832.28

-43.1

88

P37

-767.7

-43.1

89

P38

-967.69

-43.1

90

P24

-1167.69

-43.1

91

VDDO_0-1367.69

-43.1

92

Reserved, Connect to GND

1432.27-243.09

Document Number: 002-26642 Rev. *F

Page 26 of 47

CYW20721
Table 8. CYW20721 WLCSP Bump Coordinates (Cont.)
Bump#

X-COORD (μm)

Y-COORD (μm)

93P0

NET_NAME-367.7-243.0994P27-567.7-243.0995

P30-767.7-243.0996

VSSO_0-967.69-243.0997

P25-1167.69-243.0998

P32-1367.69-243.09-435.87

99

BT_VDDC

56.23

100

P33

-767.7-443.09

101

VSSO_0-967.69-443.09102

JTAG_SEL-1167.69-443.09

103

RST_N

-1367.69-443.09

104

BT_XTALO

1462.79-597.97

105

BT_XTALI

1262.79-597.97

106

BT_PLLVDD1p2

1262.79-797.97

107

BT_PLLVSS

1462.79-814.63

108

Reserved-1059.5-819

109

PMU_DISABLE-1259.5-819

110

BT_IFVDD1p2

1062.79-849.66

111

RFLDO_VDDIN1P5-659.5-1018.99

112

VSSC

-859.5-1018.99

113

PMU_AVSS-1059.5-1018.99

114

PMU_AVSS-1459.49-1018.99

115

BT_IFVSS

1159.51-1035.5

116

BT_PAVDD

756.99-1087.29

117

BT_VSSC

-234-1128.6

118

BT_VSSC-433.99-1128.6

119

BT_VCOVSS

1472.59-1212.28

120

VDDBAT3V-1059.5-1218.99

121

SR_VLX-1259.5-1218.99

122

Reserved-1459.49-1218.99

123

BT_PAVSS

994.94-1153.5

124

BT_VSSC-34-1328.59

125

BT_VCOVDD1p2

1472.59-1412.28

126

DIGLDO_VDDOUT-459.5-1418.99

127

DIGLDO_VDDIN1P5-659.5-1418.99

128

RFLDO_VDDOUT-859.5-1418.99

129

SR_VDDBAT3V-1059.5-1418.99130

SR_PVSS-1259.5-1418.99

131

Reserved-1459.49-1418.99

132

BT_RF

988.31-1475

133

BT_VSSC

365.99-1479.96

134

BT_VSSC

165.99-1479.96

Document Number: 002-26642 Rev. *F

Page 27 of 47

CYW20721
10. Specifications
10.1 Electrical Characteristics
Caution! The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even
if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at
absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 9. Absolute Maximum RatingsSpecifications

Requirement Parameter

Unit

Min.

Nom.

Max.

Maximum Junction Temperature

–

–

125

°C

VDD IO (BT_VDDO, VDDO_0)

–0.5

–

3.795

V

VDD RF (BT_IFVDD1p2, BT_PLLVDD1p2,
BT_VCOVDD1p2, BT_PAVDD)

–0.5

–

1.38

V

VDDBAT3V/SR_VDDBAT3V

–0.5

–

3.795

V

DIGLDO_VDDIN1P5

–0.5

–

1.65

V

RFLDO_VDDIN1P5

–0.5

–

1.50

V

MIC_AVDD

–0.5

–

3.795

V

BT_RF

–

–

0

dBm

Table 10. ESD/Latch up
Specifications

Requirement Parameter

Unit

Min.

Nom.

Max.

ESD Tolerance HBM

–2000

–

2000

V

ESD Tolerance CDM

–500

–

500

V

–

200

–

mA

Value

Unit

Operating Temperature–30 to +85°C

Storage Temperature–40 to +150

°C

Latch up

Table 11. Environmental Ratings
Characteristics

Note
11. Lowest operating temperature for the 32 kHz xtal is -10°C.

Table 12. Recommended Operating Conditions
Parameter

Specifications

Unit

Min.

Typ.

Max.

VDDIO (BT_VDDO, VDDO_0)

1.76

3.0

3.63

V

VDDBAT3V/SR_VDDBAT3V

1.76

3.0

3.63

V

MIC_AVDD

1.76

3.0

3.63

V

Document Number: 002-26642 Rev. *F

Page 28 of 47

CYW20721
10.1.1 Core Buck Regulator
Table 13. Core Buck Regulator
Conditions

Min.

Typ.

Max.

Unit

Input supply voltage DC, VBAT

Parameter

DC voltage range inclusive of disturbances

1.76

3.0

3.63

V

CBUCK output current

Low Power Operation Mode (LPOM) only

–

–

65

mA

Output voltage range

Programmable, 30mV/stepdefault = 1.2 V (bits = 0000)

1.2

1.26

1.5

V

Output voltage DC accuracy

Includes load and line regulation

–4

–

+4

%

LPOM efficiency (high load)

–

–

85

–

%

LPOM efficiency (low load)

–

–

80

–

%

Input supply voltage ramp-up time

0 to 3.3 V

40

–

–

μs

■

Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature,
and aging.

■Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any
decoupling capacitors connected at the load side, if any.

10.1.2 Recommended External Component for Core Buck Regulator
Table 14. Recommended External Component for Core Buck Regulator
Parameter

Conditions

Min.

Typ.

Max.

Unit

External output inductor L

2.2 μH ±25%, DCR=114 mΩ ±20%, ACR<1Ω(for frequency<1 MHz)

–

2.2

–

μH

External output capacitor, Cout

4.7 μF ±10%, 6.3V, 0402, X5R, MLCC capacitor+board total-ESR < 20 mΩ

–

4.7

–

μF

External input capacitor, Cin

For SR_VDDBAT pin
Ceramic, X5R, 0402, ESR<30 mΩ at
4 MHz, +/-20%, 6.3V, 10 μF

–

10

–

μF

Min.

Typ.

Max.

Unit

0.5

2.2

4.7

μF

10.1.3 Recommended External Components for RFLDO
Table 15. Recommended External Components for RFLDO
Parameter
External output capacitor, Co

Document Number: 002-26642 Rev. *F

Conditions
Total ESR (trace/cap): 5 m–240 mΩ

Page 29 of 47

CYW20721
10.1.4 Digital I/O Characteristics
Table 16. Digital I/O Characteristics
Symbol

Min.

Typ.

Max.

Unit

Input low voltage (VDDO = 3 V)

Characteristics

VIL

–

–

0.8

V

Input high voltage (VDDO = 3 V)

VIH

2.4

–

–

V

Input low voltage (VDDO = 1.8 V)

VIL

–

–

0.4

V

Input high voltage (VDDO = 1.8 V)

VIH

1.4

–

–

V

Output low voltage

VOL

–

–

0.45

V

Output high voltage

VOH

VDDO – 0.45 V

–

–

V

Input low current

IIL

–

–

1.0

μA

Input high current

IIH

–

–

1.0

μA

Input capacitance

CIN

–

–

0.4

pF

Output low current (VDDO = 3 V, VOL = 0.5 V)

IOL

–

–

8.0

mA

Output low current (VDDO = 1.8 V, VOL = 0.5 V)

IOL

–

–

4.0

mA

Output high current (VDDO = 3 V, VOH = 2.55 V)

IOH

–

–

8.0

mA

Output high current (VDDO = 1.8 V, VOH = 1.35 V)

IOH

–

–

4.0

mA

Typ.

Max.

Unit

10.1.5 ADC Electrical Characteristics
Table 17. Electrical Characteristics
Parameter

SymbolConditions/Comments

Min.

Current consumption

ITOT

–

–

2

3

mA

Power down current–

At room temperature

–

1

–

μA

From BG with ±3% accuracy

–

0.85

–

V

ADC Core Specification
ADC reference voltage

VREF

ADC sampling clock

–

–

–

12

–

MHz

Absolute error–

Includes gain error, offset anddistortion. Without factory calibration.

–

–

5

%

Includes gain error, offset anddistortion. After factory calibration.

–

–

2

%

For audio application

12

13

–

Bit

For static measurement

10

–

–

For audio application

–

1.6

–

For static measurement

1.8

–

3.6

ENOB
ADC input full scale–
FS

Conversion rate–

For audio application

8

16

–

kHz

Signal bandwidth–

For audio application

20

–

8K

Hz

For static measurement

–

DC

–

Input impedance

RIN

For audio application

10

–

–

For static measurement

500

–

–

Startup time–

For audio application

–

10

–

ms

For static measurement

–

20

–

μs

KΩ

MIC PGA Specifications
MIC PGA gain range

–

–

0

–

42

dB

MIC PGA gain step

–

–

–

1

–

dB

Note
12. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.

Document Number: 002-26642 Rev. *F

Page 30 of 47

CYW20721
Table 17. Electrical Characteristics (Cont.)
Parameter

SymbolConditions/Comments

Min.

Typ.

Max.

Unit

PGA input referred noise–

At 42 dB PGA gain A-weighted

–

–

4

μV

MIC PGA gain error–

Includes part-to-part gain variation

–1

–

1

dB

PGA input referred noise–

At 42 dB PGA gain A-weighted

–

–

4

μV

Passband gain flatness–

PGA and ADC, 100 Hz–4 kHz

–0.5

–

0.5

dB

MIC bias output voltage–

At 3 V supply, 25°C, default settings

–

2.4

–

V

MIC bias loading current

–

–

–

–

3

mA

MIC bias noise–

Refers to PGA input 20 Hz to
8 kHz, A-weighted

–

–

3

μV

MIC bias PSRR–

at 1 kHz

40

–

–

dB

ADC SNR–A-weighted 0 dB PGA gain,
Temperature= 25°C

–

78

–

dB

ADC THD + N––3 dBFS input 0 dB PGA gain,
Temperature= 25°C

–

70

–

dB

Always lower than avddBAT

–

–

3.6

V

Resistance

–

–

1

kΩ

Capacitance

–

–

10

pF

MIC Bias Specifications

GPIO input voltage
GPIO source impedance[12]–Note
12. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO input channel.

10.1.6 Current Consumption
In Table 18, current consumption measurements are taken at input of VBAT and VDDIO combined (LDOIN = VDDIO = 3.0V).
Table 18. Current Consumption Bluetooth/LE
Operational Mode
HCI

Typ.

Unit

48 MHz with Pause

Conditions

1.1

mA

48 MHz Without Pause

2.2

mA

RX

Continuous RX

5.9

mA

TX

Continuous TX - 0 dBm

5.6

mA

61

μA

PDS
HID-Off

32 kHz XTAL and 16 KB Retention RAM on

1.6

μA

Advertising

Unconnectable - 1 sec

14

μA

Connectable undirected - 1 sec

17

μA

LE Connection - SDS

Master - 1 sec

16

μA

Slave - 1 sec

17

μA

Page Scan - PDS

Interlaced - R1

122

μA

Sniff - PDS

500 ms Sniff, 1 attempt, 0 timeout - Master

132

μA

500 ms Sniff, 1 attempt, 0 timeout - Slave

138

μA

6.9

mA

Bi-Directional Data Exchange Continuous DM5 or DH5 packets - Master/Slave

Document Number: 002-26642 Rev. *F

Page 31 of 47

CYW20721
10.2 RF Specifications
Note Table 19 and Table 20 apply to single-ended industrial temperatures. Unused inputs are left open.
Table 19. Receiver RF Specifications
Parameter
Frequency range

Mode and Conditions
–

Min.

Typ.

Max.

Unit

2402

–

2480

MHz

[13]

GFSK, 0.1% BER, 1 Mbps

–

–92.0

–

dBm

π/4-DQPSK, 0.01% BER, 2 Mbps–

–94.0[14]–dBm

8-DPSK, 0.01% BER, 3 Mbps–

–88.0[14]–dBm

GFSK, 0.1% BER, 1 Mbps–

–91.5[14]–dBm

π/4-DQPSK, 0.01% BER, 2 Mbps–

–93.5[14]–dBm

8-DPSK, 0.01% BER, 3 Mbps–

–87.5[14]–dBm

All data rates

–

–

–20

dBm

C/I cochannel

GFSK, 0.1% BER[13]

–

–

11.0

dB

C/I 1 MHz adjacent channel

GFSK, 0.1% BER[14]

–

–

0

dB

C/I 2 MHz adjacent channel

GFSK, 0.1% BER[15]

–

–

–30.0

dB

C/I 3 MHz adjacent channel

GFSK, 0.1% BER[13]

–

–

–40.0

dB

C/I image channel

GFSK, 0.1% BER[15]

–

–

–9.0

dB

C/I 1 MHz adjacent to image channel GFSK, 0.1% BER[15]

–

–

–20.0

dB

13.0

dB

RX sensitivity (QFN)[13]

RX sensitivity (WLCSP)[13]
Maximum input
GFSK Modulation

QPSK Modulation
C/I cochannel

p/4-DQPSK, 0.1% BER[15]––C/I 1 MHz adjacent channel

p/4-DQPSK, 0.1% BER[16]

–

–

0

dB

C/I 2 MHz adjacent channel

p/4-DQPSK, 0.1% BER[15]

–

–

–30.0

dB

C/I 3 MHz adjacent channel

p/4-DQPSK, 0.1% BER[17]

–

–

–40.0

dB

C/I image channel

p/4-DQPSK, 0.1% BER[15]

–

–

–9.0

dB

C/I 1 MHz adjacent to image channel

p/4-DQPSK, 0.1% BER[15]

–

–

–20.0

dB

C/I cochannel

8-DPSK, 0.1% BER[15]

–

–

21.0

dB

C/I 1 MHz adjacent channel

8-DPSK, 0.1% BER[15]

–

–

5.0

dB

C/I 2 MHz adjacent channel

8-DPSK, 0.1% BER

[15]

–

–

–25.0

dB

C/I 3 MHz adjacent channel

8-DPSK, 0.1% BER[17]

–

–

–33.0

dB

C/I image channel

8-DPSK, 0.1% BER[15]

–

–

0

dB

C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER[15]

–

–

13

dB

8PSK Modulation

Out-of-Band Blocking Performance (CW)[16]30 MHz to 2000 MHz

BDR GFSK 0.1% BER

–

–10.0

–

dBm

2000 MHz to 2399 MHz

BDR GFSK 0.1% BER

–

–27.0

–

dBm

2498 MHz to 3000 MHz

BDR GFSK 0.1% BER

–

–27.0

–

dBm

3000 MHz to 12.75 GHz

BDR GFSK 0.1% BER

–

–10.0

–

dBm

Inter-modulation Performance[13]Notes
13. Dirty TX is off.
14. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
15. The receiver sensitivity is measured at BER of 0.1% on the device interface.
16. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
17. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
18. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal atfrequency f2, f0 = 2*f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.

Document Number: 002-26642 Rev. *F

Page 32 of 47

CYW20721
Table 19. Receiver RF Specifications (Cont.)
Parameter

Mode and Conditions

Min.

Typ.

Max.

Unit

BDR GFSK 0.1% BER

–

–

–39.0

dBm

30 MHz to 1 GHz

–

–

–

–57.0

dBm

1 GHz to 12.75 GHz

–

–

–

–55.0

dBm

Bluetooth, interferer signal level
Spurious Emissions

Notes
13. Dirty TX is off.
14. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
15. The receiver sensitivity is measured at BER of 0.1% on the device interface.
16. Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
17. Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
18. Desired signal is -64 dBm Bluetooth-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1, interferer 2 is –39 dBm Bluetooth modulated signal atfrequency f2, f0 = 2*f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.

Table 20. Transmitter RF Specifications
Parameter

Min.

Typ.

Max.

Unit

Frequency range

2402

–

2480

MHz

GFSK TX power

–

5

–

dBm

Transmitter Section

EDR TX power

–

0

–

dBm

20 dB bandwidth

–

930

1000

kHz

|M – N| = 2

–

–

–20

dBm

|M – N| 3

–

–

–40

dBm

30 MHz to 1 GHz

–

–

–36.0

dBm

1 GHz to 12.75 GHz

–

–

–30.0

dBm

1.8 GHz to 1.9 GHz

–

–

–47.0

dBm

5.15 GHz to 5.3 GHz

–

–

–47.0

dBm

–75

–

+75

kHz

DH1 packet

–25

–

+25

kHz

DH3 packet

–40

–

+40

kHz

DH5 packet

–40

–

+40

kHz

Drift rate

–20

20

kHz/50 µs

Adjacent Channel Power

Out-of-Band Spurious Emission

LO Performance
Initial carrier frequency tolerance
Frequency Drift

Frequency Deviation
Average deviation in payload (sequence used is 00001111)

140

–

175

kHz

Maximum deviation in payload (sequence used is 10101010)

115

–

–

kHz

Channel spacing

–

1

–

MHz

p/4-DQPSK frequency stability

–10

–

10

kHz

p/4-DQPSK RMS DEVM

–

–

20

%

Modulation Accuracy

p/4-QPSK Peak DEVM

–

–

35

%

p/4-DQPSK 99% DEVM

–

–

30

%

Document Number: 002-26642 Rev. *F

Page 33 of 47

CYW20721
Table 20. Transmitter RF Specifications (Cont.)
Parameter

Min.

Typ.

Max.

Unit

8-DPSK frequency stability

–10

–

10

kHz

8-DPSK RMS DEVM

–

–

13

%

8-DPSK Peak DEVM

–

–

25

%

8-DPSK 99% DEVM

–

–

20

%

1.0 MHz < |M – N| < 1.5 MHz

–

–

–26

dBc

1.5 MHz < |M – N| < 2.5 MHz

–

–

–20

dBm

|M – N| > 2.5 MHz

–

–

–40

dBm

In-Band Spurious Emissions

Table 21. Bluetooth LE RF Specifications
Parameter
Frequency range

Conditions
N/A

Min.

Typ.

Max.

Unit

2402

–

2480

MHz

–

dBm

–

dBm

RX sensitivity (QFN)[19]

LE GFSK, 0.1% BER, 1 Mbps–

–95.5[20]RX sensitivity (WLCSP)[19]

LE GFSK, 0.1% BER, 1 Mbps–

–94.5[20]TX power

N/A

–

5.5

–

dBm

Mod Char: Delta F1 average N/A

225

255

275

kHz

Mod Char: Delta F2 max[20]

N/A

99.9

–

–

%

Mod Char: Ratio

N/A

0.8

0.95

–

%

Notes
19. Dirty Tx is Off.
20. Up to 1dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations.
21. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.

Table 22. BLE2M RF Specifications
Parameter

Conditions

Min.

Typ.

Max.

Unit

2402

–

2480

MHz

255 Packets

–

–90.5

–

dBm

N/A

–

5.5

–

dBm

Mod char: Delta F1 average

N/A

450

500

550

kHz

Mod char: Delta F2 max

N/A

370

–

–

kHz

Mod char: Ratio

N/A

0.8

–

–

%

Frequency range

N/A

RX sensitivity[22]TX power

Frequency drift

N/A

–50

–

50

kHz

Drift rate

N/A

–20

–

20

kHz/50μs

Min.

Typ.

Max.

Unit

Note
22. Dirty Tx is Off.

Table 23. CYW20721 GPS and GLONASS Band Spurious Emission
Parameter

Conditions

1570-1580 MHz

GPS

–

–160

–

dBm/Hz1592-1610 MHz

GLONASS

–

–159

–

dBm/HzDocument Number: 002-26642 Rev. *F

Page 34 of 47

CYW20721
10.3 Timing and AC Characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.
10.3.1 UART Timing
Table 24. UART Timing Specifications
Reference

Characteristics

Min.

Typ.

Max.

Unit

1

Delay time, UART_CTS_N low to UART_TXD valid

–

–

1.50

Bit periods

2

Setup time, UART_CTS_N high before midpoint of stop bit

–

–

0.67

Bit periods

3

Delay time, midpoint of stop bit to UART_RTS_N HIGH

–

–

1.33

Bit periods

Figure 8. UART Timing

UART_CTS_N

2

1

UART_TXD
M id p o in t o f S T O P b it

M id p o in t o f S T O P b it

UART_RXD3

UART_RTS_N

Document Number: 002-26642 Rev. *F

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CYW20721
10.3.2 SPI Timing
The SPI interface can be clocked from 1 to 12 MHz and 24 MHz.
Table 25 and Figure 9 show the timing requirements when operating in SPI Mode 0 and 2.
Table 25. SPI Mode 0 and 2
Reference

Characteristics

Min.

Max.

Unit

1

Time from master assert SPI_CSN to first clock edge

45

–

ns

2

Hold time for MOSI data lines

12

½ SCK

ns

3

Time from last sample on MOSI/MISO to slave deassert SPI_INT

0

100

ns

4

Time from slave deassert SPI_INT to master deassert SPI_CSN

0

–

ns

5

Idle time between subsequent SPI transactions

1 SCK

–

ns

Figure 9. SPI Timing, Mode 0 and 2
5

SPI_CSN
SPI_INT(DirectWrite)
3

4

SPI_INT(DirectRead)

1

SPI_CLK(Mode 0)SPI_CLK(Mode 2)

2First Bit

SPI_MOSISPI_MISO

Not Driven

First Bit

Second Bit

Last bit

Second Bit

Last bitNot Driven

Table 26 and Figure 10 show the timing requirements when operating in SPI Mode 0 and 2.
Table 26. SPI Mode 1 and 3
Reference

Min.

Max.

Unit

1

Time from master assert SPI_CSN to first clock edge

Characteristics

45

–

ns

2

Hold time for MOSI data lines

12

½ SCK

ns

3

Time from last sample on MOSI/MISO to slave deassert SPI_INT

0

100

ns

4

Time from slave deassert SPI_INT to master deassert SPI_CSN

5

Idle time between subsequent SPI transactions

Document Number: 002-26642 Rev. *F

0

–

ns

1 SCK

–

ns

Page 36 of 47

CYW20721
Figure 10. SPI Timing, Mode 1 and 3
SPI_CSN5

SPI_INT(DirectWrite)
3

4

SPI_INT(DirectRead)

SPI_CLK(Mode 1)

1

SPI_CLK(Mode 3)
2
SPI_MOSISPI_MISO

Not Driven

Invalid bit

First bit

Last bit

Invalid bit

First bit

Last bitNot Driven

10.3.3 I2C Compatible Interface Timing
The specifications in Table 27 references Figure 11.
Table 27. I2C Compatible Interface Timing Specifications (up to 1 MHz)
Reference
1

Characteristics
Clock frequency

Min.

Max.

Unit

–

100

kHz

400
800
1000
2

START condition setup time

650

–

3

START condition hold time

280

–

4

Clock low time

650

–

5

Clock high time

280

–

6

Data input hold time[23]

0

–

7

Data input setup time

100

–

8

STOP condition setup time

280

–

9

Output valid from clock

–

400

10

Bus free time[24]

650

–

ns

Notes
23. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
24. Time that the CBUS must be free before a new transaction can start.

Document Number: 002-26642 Rev. *F

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CYW20721
Figure 11. I2C Interface Timing Diagram
1
5

SCL
2
8

6

4
3

7

SDA
IN

10
9

SDA
OUT

Table 28. Timing for I2S Transmitters and Receivers
Transmitter

Clock Period T

ReceiverLower Limit

Upper Limit

Lower Limit

Upper Limit

Notes

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Ttr

–

–

–

Tr

–

–

–

[25]

Master Mode: Clock generated by transmitter or receiver
HIGH tHC

0.35Ttr–––

0.35Ttr

–

–

–

[26]

LOWtLC

0.35Ttr–––

0.35Ttr

–

–

–

[26]

Slave Mode: Clock accepted by transmitter or receiver
HIGH tHC–

0.35Ttr–––

0.35Ttr

–

–

[27]

LOW tLC–

0.35Ttr–––

0.35Ttr

–

–

[27]

Rise time tRC––

0.15Ttr

–

–

–

–

[28]

Delay tdtr

–

–

–

0.8T

–

–

–

–

[29]

Hold time thtr

0

–

–

–

–

–

–

–

[28]

Setup time tsr

–

–

–

–

0.2Ttr

–

–

–

[30]

Hold time thr

–

–

–

–

0.2Ttr

–

–

–

[30]

Transmitter

ReceiverNotes
25. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate.
26. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified withrespect to T.
27. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum
periods are greater than 0.35Tr, any clock that meets the requirements can be used.
28. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceedingtRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr zero, so long as the clock rise-time tRC is not more than tRCmax,
where tRCmax is not less than 0.15Ttr
29. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient
setup time.
30. The data setup and hold time must not be less than the specified receiver setup and hold time.

Document Number: 002-26642 Rev. *F

Page 38 of 47

CYW20721
Figure 12. I2S Transmitter Timing

TtRC*

tLC > 0.35T

tHC > 0.35T
VH = 2.0V

SCK
VL = 0.8V

thtr > 0
totr < 0.8T

SD and WS

T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr* tRC is only relevant for transmitters in slave mode.

Figure 13. I2S Receiver Timing
TtLC > 0.35T

tHC > 0.35
VH = 2.0V

SCK
VL = 0.8V

tsr > 0.2T

thr > 0SD and WS

T = Clock period
Tr = Minimum allowed clock period for transmitter
T > TrDocument Number: 002-26642 Rev. *F

Page 39 of 47

CYW20721
11. Mechanical Information
11.1 40-Pin QFN Package
Figure 14. CYW20721 5.0 mm x 5.0 mm 40-Pin QFN Package

002-13583 *A

Document Number: 002-26642 Rev. *F

Page 40 of 47

CYW20721
11.2 WLCSP Package
Figure 15. CYW20721 WLCSP Package

6

5

NOTES:DIMENSIONSSYMBOL

MIN.

A

NOM.

MAX.

-

0.33

-

A1

0.075

-

-

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

D

3.22 BSC

4. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS.

E

3.31 BSC

5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

D1

2.84 BSC

E1

2.84 BSC

N

134
b

0.100

0.115

PLANE PARALLEL TO DATUM C.
6. BUMP #1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
0.130

METALIZED MARK, INDENTATION OR OTHER MEANS.
7. JEDEC SPECIFICATION NO. REF. : N/A.

Document Number: 002-26642 Rev. *F

002-16658 *A

Page 41 of 47

CYW20721
11.3 WLCSP Package Keep-out
Figure 16 shows the top view of the WLCSP package (Bumps facing down).
Figure 16. CYW20721YB2 WLCSP Keep-out Model
3310.0000

1

2

3

4

5

6

7

8

9 10 11 12 13 14

15 16 17 18 19 20 21 22 23 24 25 26 27 28
29 30 31 32 33 34 35 36 37 38 39 40 41 42
43 44 45 46 47

48 49 50 51 52 53 54 55

56 57 58 59

60 61 62

63 64 65 66

69

70 71 72 73

67 68

74

75 76 77 78 79

80 81 82 83

84 85 86 87

88 89 90 91

923220.0000

93 94 95 96 97 98
99

100 101 102 103

104 105
107 106 110

Bump Origin
119

108 109
111 112 113

115
116
123

125

117 118124

132

133 134

114

120 121 122

126 127 128 129 130 131

Routing Keep-Out

11.4 Tape Reel and Packaging Specifications
Table 29. CYW20721 Tape Reel Specifications
Parameter

Value

Quantity per reel

5000

Reel diameter

13 inches

Hub diameter

4 inches

Tape width

12 mm

Tape pitch

8 mm

The top-left corner of the CYW20721 package is situated near the sprocket holes, as shown in Figure 17.
Figure 17. Pin 1 Orientation

Pin 1: Top left corner of package toward sprocket holes

Document Number: 002-26642 Rev. *F

Page 42 of 47

CYW20721
12. Ordering Information
Table 30. Ordering Information
Part Number

PackageAmbient Operating Temperature

CYW20721B2KWB9G

3.2  3.1 134-Ball WLCSP–30°C to 85°C

CYW20721B2KUMLG

5  5 40-pin QFN–30°C to 85°C

13. Acronyms
Table 31. Acronyms Used in this Document
Term

Description

Table 31. Acronyms Used in this Document (Cont.)
Term

Description

PLL

phase locked loop

PMU

power management unit

POR

power-on reset

PRBS

Pseudo Random Binary Sequence

AFH

adaptive frequency hopping

ATT

Attribute Protocol

BBC

Bluetooth Baseband Core

BDR

basic data rate

BRbasic data rate

BQS

Bluetooth Qualification Body

CRC

cyclic redundancy checkEDerroneous data

EIR

extended inquiry response

EPR

encryption pause resume

A resistor-capacitor oscillator is a circuitof an amplifier, which provides theRC oscillator composed
output signal, and a resistor-capacitor network,
which controls the frequency of the signal.

FEC

forward error correction

RFradio frequency

FPU

floating point unitROM

read-only memory

GATT

Generic Attribute Profile

RX/TX

receive/transmit

GAP

generic access profile

SCO

synchronous connection-oriented

GFSK

Gaussian Frequency Shift Keying

SDP

Service Discovery Protocol

GPIO

general-purpose I/O

SDS

Shut Down Sleep

HCI

host control interface

SPI

serial peripheral interfaceIFintermediate frequency

SPIFFY

serial peripheral interface fully functional

JTAG

Joint Test Action Group

SSP

secure simple pairing

L2CAP

Logical Link Control and Adaptation Protocol

SSR

sniff subrating

LCU

link control unit

SWD

serial wire debug

LDO

low drop-out

TSSI

transmit signal strength indicatorLE

low energy

UART

universal asynchronous receiver/transmitter

LM

Link Manager

WLCSP

wafer level chip scale package

LO

local oscillator

LPO

low power oscillator

LSTO

link supervision time out

PApower amplifier

PBFpacket boundary flag

PDM

pulse density modulation

PDS

Power down sleep

Document Number: 002-26642 Rev. *F

PWM

pulse width modulation

QFN

quad flat no-lead

QoS

quality of serviceRAM

random access memory

Page 43 of 47

CYW20721
14. Document Conventions
14.1 Units of Measure
Table 32. Units of Measure
SymbolUnit of Measure°C

degrees CelsiusdB

decibeldBidecibels relative to isotropicdBm

decibel-milliwatts

GHzgigahertz

Hz

hertz

KB

1024 bytes

kHzkilohertzkkilo ohmkVkilovoltmAmilliamperes

Mbps

megabits per secondMHzmegahertzM

mega-ohm

mm

millimeters

Msps

megasamples per secondmVmillivoltµA

microampereµF

microfaradµm

micrometersµs

microsecondµV

microvoltµW

microwattmA

milliamperemmilliohmmsmillisecondmVmillivoltnA

nanoampere

ns

nanosecond



ohm

pF

picofaradppm

parts per millionpspicosecondssecondsps

samples per second

V

volt

Document Number: 002-26642 Rev. *F

Page 44 of 47

CYW20721

15. Document History Page
Document Title: CYW20721, Enhanced Low Power, Bluetooth LE Bluetooth 5.1 SOC for Audio
Document Number: 002-26642
Revision

ECN

Submission
Date

*F

765581002/14/2022

Document Number: 002-26642 Rev. *F

Description of Change

Removed “Preliminary” status.
Updated Table 4.

Page 46 of 47

CYW20721
Sales, Solutions, and Legal Information
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cypress.com/wireless47m© Cypress Semiconductor Corporation, 2019-2022. This document is the property of Cypress Semiconductor Corporation, an Infineon Technologies company, and its affiliates (“Cypress”). This
document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States andother countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the
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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
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and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arisingfrom any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except tothe limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance
written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary ofCypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-26642 Rev. *F

Revised February 14, 2022

Page 47 of 47