S-1011 Series
www.ablic.com
www.ablicinc.com

HIGH-WITHSTAND VOLTAGE
BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02© ABLIC Inc., 2014-2015

The S-1011 Series is a high-accuracy voltage detector developed using CMOS technology. The detection voltage is fixedinternally, and the accuracy of the S-1011 Series A / C / E / G type is 1.5%. It operates with current consumption of
600 nA typ.
Apart from the power supply pin, the detection voltage input pin (SENSE pin) is also prepared in the SENSE detection
product, so the output is stable even if the SENSE pin falls to 0 V.
The detection signal and release signal can be delayed by setting a capacitor externally, and the detection delay time
accuracy is 20% (CN = 3.3 nF, Ta = 25°C), the release delay time accuracy is 20% (CP = 3.3 nF, Ta = 25°C).
Output form is Nch open-drain output.

 Features Detection voltage: Detection voltage accuracy: Detection delay time accuracy:
 Release delay time accuracy:
 Current consumption:
 Operation voltage range:
 Hysteresis width: Output form: Operation temperature range: Lead-free (Sn 100%), halogen-free

3.0 V to 10.0 V (0.05 V step) (SENSE detection product)
3.6 V to 10.0 V (0.05 V step) (VDD detection product)
1.5% (A / C / E / G type)20% (CN = 3.3 nF)
20% (CP = 3.3 nF)
600 nA typ.
1.8 V to 36.0 V"Available" (5.0% typ.) / "unavailable" is selectable.
Nch open-drain output
Ta = 40°C to 85°C

 Applications
 Power supply monitor for microcomputer and reset for CPU
 Constant voltage power supply monitor for TV and home appliance etc.
 Power supply monitor for Blu-ray recorder, notebook PC and digital still camera Industrial equipment, housing equipment

 Package SOT-23-6

1

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Block Diagrams
1. S-1011 Series A / J type (VDD detection product)
CP

Function
StatusVoltage detection VDD detection
Available
Hysteresis width(5.0% typ.)

VDD



*1

Delay
circuit

OUT
*1

VREF
*1

*1

VSS
CN

*1.

Parasitic diodeFigure 1

2. S-1011 Series C / L type (VDD detection product)
CP

Function
StatusVoltage detection VDD detection
Hysteresis width Unavailable

VDD



*1

Delay
circuit

OUT
*1

VREF
*1

*1

VSS
CN

*1.

Parasitic diodeFigure 22

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

3. S-1011 Series E / N type (SENSE detection product)
CP

SENSE

Function
StatusVoltage detection SENSE detection
Available
Hysteresis width(5.0% typ.)

VDD

*1

*1



Delay
circuit

OUT

*1

VREF
*1

*1

VSS
CN

*1.

Parasitic diodeFigure 3

4. S-1011 Series G / Q type (SENSE detection product)
CP

SENSE

Function

StatusVoltage detection SENSE detection
Hysteresis width Unavailable

VDD

*1

*1



Delay
circuit

OUT

*1

VREF
*1

*1

VSS
CN

*1.

Parasitic diodeFigure 43

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Product Name Structure
Users can select the product type and detection voltage value for the S-1011 Series.
Refer to "1. Product name" regarding the contents of product name, "2. Function list of product types" regarding
the product types, "3. Package" regarding the package drawings and "4. Product name lists" regarding details of
the product name.

1.

Product name
S-1011

x

xx

-

M6T1

U

4
Environmental codeU:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
M6T1: SOT-23-6, Tape
Detection voltage value
30 to A0(e.g., when the output voltage is 3.0 V, it is expressed as 30.
when the output voltage is 10.0 V, it is expressed as A0.)
Product type*2
A, C, E, G, J, L, N, Q

*1.
*2.

Refer to the tape drawing.
Refer to "2. Function list of product types".

Remark2.

Although the detection voltage in the S-1011 Series is 10.0 V max., the detection voltage exceeding
10.0 V with an external resistor can be set.
Refer to "2. SENSE pin" in " Operation" for details.

Function list of product types
Table 1
Product Type
A
C
E
G
J
L
N
Q

3.

Voltage Detection
VDD detection
VDD detection
SENSE detection
SENSE detection
VDD detection
VDD detection
SENSE detection
SENSE detection

Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"

Detection Voltage
5.0 V to 10.0 V
5.0 V to 10.0 V
5.0 V to 10.0 V
5.0 V to 10.0 V
3.6 V to 4.95 V
3.6 V to 4.95 V
3.0 V to 4.95 V
3.0 V to 4.95 V

Package
Table 2
Package Name
SOT-23-6

4

Hysteresis Width
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable
Available (5.0% typ.)
Unavailable

Package Drawing Codes

Dimension

Tape

Reel

MP006-A-P-SD

MP006-A-C-SD

MP006-A-R-SD

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
4.

Product name lists
4. 1

S-1011 Series A type
Voltage detection: VDD detection
Hysteresis width: Available (5.0% typ.)Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 3Detection Voltage
5.0 V  1.5%
6.0 V  1.5%
7.0 V  1.5%
8.0 V  1.5%
9.0 V  1.5%
10.0 V  1.5%
Remark
4. 2

SOT-23-6
S-1011A50-M6T1U4
S-1011A60-M6T1U4
S-1011A70-M6T1U4
S-1011A80-M6T1U4
S-1011A90-M6T1U4
S-1011AA0-M6T1U4

Please contact our sales office for products with specifications other than the above.

S-1011 Series C type
Voltage detection: VDD detection
Hysteresis width: Unavailable

Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 4

Detection Voltage
5.0 V  1.5%
6.0 V  1.5%
7.0 V  1.5%
8.0 V  1.5%
9.0 V  1.5%
10.0 V  1.5%
Remark
4. 3

SOT-23-6
S-1011C50-M6T1U4
S-1011C60-M6T1U4
S-1011C70-M6T1U4
S-1011C80-M6T1U4
S-1011C90-M6T1U4
S-1011CA0-M6T1U4

Please contact our sales office for products with specifications other than the above.

S-1011 Series E type
Voltage detection: SENSE detection
Hysteresis width: Available (5.0% typ.)Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 5Detection Voltage
5.0 V  1.5%
6.0 V  1.5%
7.0 V  1.5%
8.0 V  1.5%
9.0 V  1.5%
10.0 V  1.5%
Remark
4. 4

SOT-23-6
S-1011E50-M6T1U4
S-1011E60-M6T1U4
S-1011E70-M6T1U4
S-1011E80-M6T1U4
S-1011E90-M6T1U4
S-1011EA0-M6T1U4

Please contact our sales office for products with specifications other than the above.

S-1011 Series G type
Voltage detection: SENSE detection
Hysteresis width: Unavailable

Output logic: Active "L"
Detection voltage: 5.0 V to 10.0 V
Table 6Detection Voltage
5.0 V  1.5%
6.0 V  1.5%
7.0 V  1.5%
8.0 V  1.5%
9.0 V  1.5%
10.0 V  1.5%
Remark

SOT-23-6
S-1011G50-M6T1U4
S-1011G60-M6T1U4
S-1011G70-M6T1U4
S-1011G80-M6T1U4
S-1011G90-M6T1U4
S-1011GA0-M6T1U4

Please contact our sales office for products with specifications other than the above.

5

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

4. 5

S-1011 Series J type
Voltage detection: VDD detection
Hysteresis width: Available (5.0% typ.)Output logic: Active "L"
Detection voltage: 3.6 V to 4.95 V
Table 7Detection Voltage
3.6 V  3.0%
4.2 V  2.5%
Remark4. 6

SOT-23-6
S-1011J36-M6T1U4
S-1011J42-M6T1U4

Please contact our sales office for products with specifications other than the above.

S-1011 Series L type
Voltage detection: VDD detection
Hysteresis width: Unavailable

Output logic: Active "L"
Detection voltage: 3.6 V to 4.95 V
Table 8Detection Voltage
3.6 V  3.0%
4.2 V  2.5%
Remark4. 7

SOT-23-6
S-1011L36-M6T1U4
S-1011L42-M6T1U4

Please contact our sales office for products with specifications other than the above.

S-1011 Series N type
Voltage detection: SENSE detection
Hysteresis width: Available (5.0% typ.)Output logic: Active "L"
Detection voltage: 3.0 V to 4.95 V
Table 9Detection Voltage
3.0 V  3.0%
3.3 V  3.0%
3.6 V  3.0%
4.2 V  2.5%
Remark
4. 8

SOT-23-6
S-1011N30-M6T1U4
S-1011N33-M6T1U4
S-1011N36-M6T1U4
S-1011N42-M6T1U4

Please contact our sales office for products with specifications other than the above.

S-1011 Series Q type
Voltage detection: SENSE detection
Hysteresis width: Unavailable

Output logic: Active "L"
Detection voltage: 3.0 V to 4.95 V
Table 10Detection Voltage
3.0 V  3.0%
3.3 V  3.0%
3.6 V  3.0%
4.2 V  2.5%
Remark6

SOT-23-6
S-1011Q30-M6T1U4
S-1011Q33-M6T1U4
S-1011Q36-M6T1U4
S-1011Q42-M6T1U4

Please contact our sales office for products with specifications other than the above.

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Pin Configurations
1. S-1011 Series A / C / J / L type (VDD detection product)
1. 1

SOT-23-6
Table 11Top view
6 5 4

1 2 3

Figure 5

Pin No.

SymbolDescription

1
VDD
Voltage input pin
NC*1
2
No connection
3
OUT
Voltage detection output pin*2CP
4Connection pin for release delay capacitor
5
VSS
GND pin
CN*3
6
Connection pin for detection delay capacitor*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
*2. Connect a capacitor between the CP pin and the VSS pin.
The release delay time can be adjusted according to the capacitance.
Moreover, the CP pin is available even when it is open.
*3. Connect a capacitor between the CN pin and the VSS pin.
The detection delay time can be adjusted according to the capacitance.
Moreover, the CN pin is available even when it is open.

2. S-1011 Series E / G / N / Q type (SENSE detection product)
2. 1

SOT-23-6
Table 12Top view
6 5 4

1 2 3

Figure 6

Pin No.

SymbolDescription

1
VDD
Voltage input pin
2
SENSE
Detection voltage input pin
3
OUT
Voltage detection output pin
CP*1
4Connection pin for release delay capacitor
5
VSS
GND pinCN*2
6
Connection pin for detection delay capacitor*1. Connect a capacitor between the CP pin and the VSS pin.
The release delay time can be adjusted according to the capacitance.
Moreover, the CP pin is available even when it is open.
*2. Connect a capacitor between the CN pin and the VSS pin.
The detection delay time can be adjusted according to the capacitance.
Moreover, the CN pin is available even when it is open.

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HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Absolute Maximum Ratings
Table 13
(Ta = 25°C unless otherwise specified)
Item
SymbolAbsolute Maximum Rating
Unit
Power supply voltage
VDD  VSS
VSS  0.3 to VSS  45
V
SENSE pin input voltage
VSENSEVSS  0.3 to VSS  45
V
CP pin input voltage
VCP
VSS  0.3 to VDD  0.3  VSS  7.0
V
CN pin input voltage
VCN
VSS  0.3 to VDD  0.3  VSS  7.0
V
Output voltage
VOUT
VSS  0.3 to VSS  45
V
Output current
IOUT
25
mA
Operation ambient temperatureTopr40 to 85°CStorage temperatureTstg
40 to 125
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.

 Thermal Resistance Value
Table 14
Item

Condition
Board 1SOT-23-6jaJunction-to-ambient thermal resistance*1
Board 2
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark8

Symbol

Min.



Typ.
159
124

Refer to " Thermal Characteristics" for details of power dissipation and test board.

Max.



Unit
°C/W
°C/W

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series Electrical Characteristics
1. VDD detection product1. 1

S-1011 Series J / L type
Table 15

Item

SymbolCondition
3.6 V  VDET(S)  4.15 V

Detection voltage*1

VDET
4.2 V  VDET(S)  4.95 V
3.6 V  VDET(S)  4.15 V

Hysteresis width

VHYS

J type4.2 V  VDET(S)  4.95 V*2Current consumption
Operation voltage

ISS
VDD

Output current

IOUT

Leakage current

ILEAK

L type3.6 V  VDET(S)  4.95 V
VDD = VDET  0.1 V, 3.6 V  VDET  4.95 VOutput transistor
VDD = 2.9 V
Nch*3
VDS = 0.05 V
Output transistor
VDD = 30.0 V, VOUT = 30.0 V
Nch
CN = 3.3 nF
CP = 3.3 nF(Ta = 25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
CircuitVDET(S)VDET(S) 0.970
VDET(S)VDET(S) 0.975
VDET
VDET 0.010  0.050
VDET
VDET
 0.020  0.050

0

0.60
1.8


VDET(S) 1.030
VDET(S) 1.025
VDET
 0.100
VDET
 0.090

1.60
36.0

V

1

V

1

V

1

V

1

V
A
V

1
2
1

0.33





mA

3





2.0

A

3

Detection delay time*4 tRESET
8.0
10.0
12.0
ms
4
Release delay time*5 tDELAY
8.0
10.0
12.0
ms
4
CP pin discharge
RCP
VDD = 6.9 V, VCP = 0.5 V
0.52

2.2
k

ON resistance
CN pin discharge
RCN
VDD = 2.9 V, VCN = 0.5 V
1.0

5.0
k

ON resistance*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. VDS: Drain-to-source voltage of the output transistor*4. The time period from when the pulse voltage of VDET(S)  0.5 V  VDET(S)  0.5 V is applied to the VDD pin to when
VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.
*5. The time period from when the pulse voltage of VDET(S)  0.5 V  VDET(S)  0.5 V is applied to the VDD pin to when
VOUT reaches VDD / 2.

9

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

1. 2

S-1011 Series A / C type
Table 16

Item

SymbolDetection voltage*1

VDET

Hysteresis width

VHYS

Current consumption
Operation voltage

ISS
VDD

Output current

IOUT

Leakage current

ILEAK

Condition
5.0 V  VDET(S)  10.0 V
A typeC type*2
VDD = VDET  0.1 V, 5.0 V  VDET  10.0 V
Output transistor
VDD = 4.5 V
Nch*3
VDS = 0.05 V
Output transistor
VDD = 30.0 V, VOUT = 30.0 V
Nch
CN = 3.3 nF
CP = 3.3 nF(Ta = 25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
CircuitVDET(S)VDET(S)VDET(S)V1
 0.985
 1.015
VDET
VDET
VDET
V
1
 0.030  0.050  0.080

0

V
1

0.60
1.60
A
2
1.8

36.0
V
1
0.5





mA

3





2.0

A

3

Detection delay time*4 tRESET
8.0
10.0
12.0
ms
4
Release delay time*5 tDELAY
8.0
10.0
12.0
ms
4
CP pin discharge
RCP
VDD = 14.0 V, VCP = 0.5 V
0.30

2.60
k

ON resistance
CN pin discharge
RCN
VDD = 4.5 V, VCN = 0.5 V
0.63

2.60
k

ON resistance*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. VDS: Drain-to-source voltage of the output transistor*4. The time period from when the pulse voltage of VDET(S)  1.0 V  VDET(S)  1.0 V is applied to the VDD pin to when
VOUT reaches VDD / 2, after the power supply voltage (VDD) reaches the release voltage once.
*5. The time period from when the pulse voltage of VDET(S)  1.0 V  VDET(S)  1.0 V is applied to the VDD pin to when
VOUT reaches VDD / 2.

10

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

2. SENSE detection product2. 1

S-1011 Series N / Q type
Table 17

Item

SymbolCondition
3.0 V  VDET(S)  4.15 V

Detection voltage

*1

VDET

VDD = 16.0 V
4.2 V  VDET(S)  4.95 V
3.0 V  VDET(S)  4.15 V

Hysteresis width

VHYS

VDD = 16.0 V

N type4.2 V  VDET(S)  4.95 V
Q type*2 3.0 V  VDET(S)  4.95 V

Current*3
consumption
Operation voltage

VDD

Output current

IOUT

ISS

Leakage current

ILEAK
*5

VDD = 16.0 V, VSENSE = VDET  0.1 V,
3.0 V  VDET  4.95 VOutput transistor
VDD = 5.0 V, VSENSE = 2.9 V
Nch*4
VDS = 0.05 V
Output transistor VDD = 30.0 V, VOUT = 30.0 V,
Nch
VSENSE = 30.0 V
CN = 3.3 nF
CP = 3.3 nF
(Ta = 25°C unless otherwise specified)
Test
Min.
Typ.
Max. Unit
CircuitVDET(S)VDET(S) 0.970
VDET(S)VDET(S) 0.975
VDET
VDET 0.010  0.050
VDET
VDET
 0.020  0.050

VDET(S) 1.030
VDET(S) 1.025
VDET
 0.100
VDET
 0.090

V

1

V

1

V

1

V

1



0



V

1



0.55

1.55

A

2

3.0



36.0

V

1

0.5





mA

3





2.0

A

3

Detection delay time tRESET
8.0
10.0
12.0
ms
4
Release delay time*6 tDELAY
8.0
10.0
12.0
ms
4
SENSE pin resistance RSENSE
6.8
275 M2
CP pin discharge
RCP
VDD = 3.0 V, VSENSE = 6.9 V, VCP = 0.5 V
0.72

4.29 kON resistance
CN pin discharge
RCN
VDD = 3.0 V, VSENSE = 2.9 V, VCN = 0.5 V
0.72

4.29 kON resistance*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4. VDS: Drain-to-source voltage of the output transistor*5. The time period from when the pulse voltage of VDET(S)  0.5 V  VDET(S)  0.5 V is applied to the SENSE pin towhen VOUT reaches VDD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (VSENSE)
reaches the release voltage once.
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of VDET(S)  0.5 V 
VDET(S)  0.5 V is applied to the SENSE pin to when VOUT reaches VDD / 2.

11

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

2. 2

S-1011 Series E / G type
Table 18

Item

SymbolCondition

Detection voltage*1

VDET

VDD = 16.0 V, 5.0 V  VDET(S)  10.0 V

Hysteresis width

VHYS

VDD = 16.0 V

E typeG type*2

Current*3
consumption
Operation voltage

VDD

Output current

IOUT

Leakage current

ILEAK

ISS

VDD = 16.0 V, VSENSE = VDET  0.1 V,
5.0 V  VDET  10.0 V
Output transistor
VDD = 5.0 V, VSENSE = 4.5 V
Nch*4
VDS = 0.05 V
Output transistor VDD = 30.0 V, VOUT = 30.0 V,
Nch
VSENSE = 30.0 V
CN = 3.3 nF
CP = 3.3 nF
(Ta = 25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
CircuitVDET(S)VDET(S)VDET(S)V1
 0.985
 1.015
VDET
VDET
VDET
V
1
 0.030  0.050  0.080


0



V

1



0.55

1.55

A

2

3.0



36.0

V

1

0.5





mA

3





2.0

A

3

Detection delay time*5 tRESET
8.0
10.0
12.0
ms
4
Release delay time*6 tDELAY
8.0
10.0
12.0
ms
4
SENSE pin resistance RSENSE
26.0

400
M
2
CP pin discharge
RCP
VDD = 4.5 V, VSENSE = 14.0 V, VCP = 0.5 V
0.30

2.60
k

ON resistance
CN pin discharge
RCN
VDD = 4.5 V, VSENSE = 4.5 V, VCN = 0.5 V
0.63

2.60
k

ON resistance*1. VDET: Actual detection voltage value, VDET(S): Set detection voltage value*2. Hysteresis width is "unavailable", so release voltage = detection voltage.
*3. The current flowing through the SENSE pin resistance is not included.
*4. VDS: Drain-to-source voltage of the output transistor*5. The time period from when the pulse voltage of VDET(S)  1.0 V  VDET(S)  1.0 V is applied to the SENSE pin towhen VOUT reaches VDD / 2, after voltage of 16.0 V is applied to the VDD pin and the SENSE pin input voltage (VSENSE)
reaches the release voltage once.
*6. The time period from when voltage of 16.0 V is applied to the VDD pin and the pulse voltage of VDET(S)  1.0 V 
VDET(S)  1.0 V is applied to the SENSE pin to when VOUT reaches VDD / 2.

12

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Test Circuits

R
100 k

VDD
OUT

VDD



VSS

V

Figure 7



A

CP

V



Figure 9

VDD

Test Circuit 2(VDD detection product)


V

VSS

CP

CN

VSS

CP

Figure 13

V

Test Circuit 1(SENSE detection product)

A

OUT

SENSE
VSS

CP

CN

Test Circuit 2(SENSE detection product)

VDS

VDD



V

 VSENSE

Test Circuit 4(VDD detection product)

VSS

CP

Figure 12

P.G.

CN

VDS



Test Circuit 3(SENSE detection product)

R
100 k

VDD

VDD

A
V

Oscilloscope

CN


OUT

SENSE

R
100 k
OUT

CP

VDD

Test Circuit 3(VDD detection product)

VDD

CN

Figure 10

V

Figure 11



A

VSS

VDD


OUT

OUT

VSENSE

CN

VDD
VDD

A


OUT
CP

V

SENSE

Figure 8

VDD

VSS



VSENSE

Test Circuit 1(VDD detection product)

VDD

P.G.

VDD



CN

R
100 k

VDD

SENSE


VSS

OUT
CP

Figure 14

OscilloscopeCN

Test Circuit 4(SENSE detection product)

13

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Standard Circuits
1.

VDD detection productR
100 k

VDD
OUT
VSS

CP

CN
CP*1

*1.
*2.

CN*2

The delay capacitor (CP) should be connected directly to the CP pin and the VSS pin.
The delay capacitor (CN) should be connected directly to the CN pin and the VSS pin.
Figure 15

2.

SENSE detection productR
100 k

VDD
SENSE
VSS

OUT
CP

CN
CP*1

*1.
*2.

CN*2

The delay capacitor (CP) should be connected directly to the CP pin and the VSS pin.
The delay capacitor (CN) should be connected directly to the CN pin and the VSS pin.
Figure 16

Caution14

The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series Explanation of Terms
1.

Detection voltage (VDET)The detection voltage is a voltage at which the output in Figure 21 or Figure 22 turns to "L" (VDD detection
product: VDD, SENSE detection product: VSENSE). The detection voltage varies slightly among products of the same
specification. The variation of detection voltage between the specified minimum (VDET min.) and the maximum(VDET max.) is called the detection voltage range (Refer to Figure 17, Figure 19).
Example: In VDET = 5.0 V product, the detection voltage is either one in the range of 4.925 V  VDET  5.075 V.
This means that some VDET = 5.0 V product have VDET = 4.925 V and some have VDET = 5.075 V.

2.

Release voltage (VDET)The release voltage is a voltage at which the output in Figure 21 or Figure 22 turns to "H" (VDD detection product:
VDD, SENSE detection product: VSENSE).
The difference of detection voltage and release voltage is 5.0% typ.
The release voltage varies slightly among products of the same specification. The variation of release voltage
between the specified minimum (VDET min.) and the maximum (VDET max.) is called the release voltage range(Refer to Figure 18, Figure 20). The range is calculated from the actual detection voltage (VDET) of a product.
In the S-1011 Series C / G / L / Q type, the release voltage (VDET) is the same value as the actual detection
voltage (VDET) of a product.
Example:In VDET = 6.0 V product, the release voltage is either one in the range of 6.0873 V  VDET  6.5772 V.
This means that some VDET = 6.0 V product have VDET = 6.0873 V and some have VDET = 6.5772 V.

15

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

VDD
Detection voltage Release voltage
VDET max.

Detection voltage
range

VDET min.

VDET max.

Release voltage
range

VDET min.
VDD

VOUT

VOUT
tRESET

Figure 17

tDELAY

Detection Voltage (VDD detection product)

Figure 18

Release Voltage (VDD detection product)

VSENSE
Detection voltage Release voltage
VDET max.

Detection voltage
range

VDET min.

VDET max.

Release voltage
range

VDET min.
VSENSE

VOUT

VOUT
tRESET

Figure 19

tDELAY

Detection Voltage(SENSE detection product)

R
100 k

VDD
OUT

VDD


V

Figure 21

3.

VSS

Figure 20

CP

CN


V

Test Circuit of Detection Voltage
and Release Voltage(VDD detection product)

Release Voltage(SENSE detection product)

R
100 kVDD
VDD
VSENSE

Figure 22


V

SENSE

OUT

VSS

CN

CP


V

Test Circuit of Detection Voltage
and Release Voltage(SENSE detection product)

Hysteresis width (VHYS)
The hysteresis width is the voltage difference between the detection voltage and the release voltage (the voltage atpoint B  the voltage at point A = VHYS in Figure 24 and Figure 28). Setting the hysteresis width between thedetection voltage and the release voltage, prevents malfunction caused by noise on the input voltage.

4.

Feed-through current
The feed-through current is a current that flows instantaneously to the VDD pin at the time of detection and releaseof a voltage detector.

16

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Operation
1.

Basic operation
1. 1

S-1011 Series A / J type(1) When the power supply voltage (VDD) is the release voltage (VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
(RB  RC )  VDD.
Since the Nch transistor (N1) is turned off, the input voltage to the comparator isRA  RB  RC
(2) Even if VDD decreases to VDET or lower, VDD is output when VDD is higher than the detection voltage (VDET).
When VDD decreases to VDET or lower (point A in Figure 24), the Nch transistor is turned on. And then VSS ("L")
is output from the OUT pin after the elapse of the detection delay time (tRESET).
RB  VDD.
At this time, N1 is turned on, and the input voltage to the comparator isRA  RB(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher. Even if VDD exceeds VDET, VSS is
output when VDD is lower than VDET.
(5) When VDD increases to VDET or higher (point B in Figure 24), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.

VDDR
100 k

RA
VDD




*1

OUT

Delay
circuit

RB

*1

VREF

N1

Nch

RC

VSS

*1

CP
CP

*1.


V

*1

CN
CN

Parasitic diodeFigure 23

Operation of S-1011 Series A / J Type

(1)

(2)

Hysteresis width
VDD

(4)
B

A

(VHYS)(3)(5)
Release voltage (VDET)
Detection voltage (VDET)
Minimum operation voltage
VSS
VDD

Output from OUT pin
VSSRemarktRESETtDELAY
When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstable inthe shaded area.
Figure 24 Timing Chart of S-1011 Series A / J Type17

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

1. 2

S-1011 Series C / L type(1) When the power supply voltage (VDD) is the release voltage (VDET) or higher, the Nch transistor is turned off to
output VDD ("H") when the output is pulled up.
(RB  RC )  VDD.
At this time, the input voltage to the comparator isRA  RB  RC
(2) When VDD decreases to the detection voltage (VDET) or lower (point A in Figure 26), the Nch transistor isturned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
(3) The output is unstable when VDD decreases to the IC's minimum operation voltage or lower. VDD is output when
the output is pulled up.
(4) VSS is output by increasing VDD to the minimum operation voltage or higher.
(5) When VDD increases to VDET or higher (point B in Figure 26), the Nch transistor is turned off. And then VDD is
output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.

VDDR
100 k

RA
VDD




*1

OUT

Delay
circuit

RB

*1

VREF
Nch
RC

VSS

*1

CP
CP

*1.


V

*1

CN
CN

Parasitic diodeFigure 25

Operation of S-1011 Series C / L Type(1)

Detection voltage (VDET)

(2)
A

(3)

(4)
B

(5)

Release voltage (VDET)VDD
Minimum operation voltage
VSS
VDD
Output from OUT pin
VSStRESETtDELAY
Remark 1. When VDD is the minimum operation voltage or lower, the output voltage from the OUT pin is unstablein the shaded area.
2. The release voltage is set to the same value as the detection voltage, since there is no hysteresis
width.

Figure 26

18

Timing Chart of S-1011 Series C / L Type

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

1. 3

S-1011 Series E / N type(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage(VSENSE) is the release voltage (VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up.
(RB  RC )  VSENSE
Since the Nch transistor (N1) is turned off, the input voltage to the comparator is.
RA  RB  RC
(2) Even if VSENSE decreases to VDET or lower, VDD is output when VSENSE is higher than the detection voltage(VDET).
When VSENSE decreases to VDET or lower (point A in Figure 28), the Nch transistor is turned on. And then VSS("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
RB  VSENSE.
At this time, N1 is turned on, and the input voltage to the comparator isRA  RB(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin isstable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE exceeds VDET, VSS is output when VSENSE is lower than VDET.
(5) When VSENSE increases to VDET or higher (point B in Figure 28), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
SENSE
VDD
R
100 k

RA
VDD




*1

*1

VSENSE

RB
VREF

*1

N1

Nch

RC

VSS

*1

CP
CP

*1.

OUT

Delay
circuit


V

*1

CN
CN

Parasitic diodeFigure 27

Operation of S-1011 Series E / N Type
(1)

(2)

(3)

(4)

(5)

B

Hysteresis width
A(VHYS)

Release voltage (VDET)
Detection voltage (VDET)VSENSE

Minimum operation voltage
VSS
VDD
Output from OUT pin

VSStRESET

Figure 28

tDELAY

Timing Chart of S-1011 Series E / N Type19

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

1. 4

S-1011 Series G / Q type(1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage(VSENSE) is the release voltage (VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the
output is pulled up.
(RB  RC )  VSENSEAt this time, the input voltage to the comparator is.
RA  RB  RC
(2) When VSENSE decreases to the detection voltage (VDET) or lower (point A in Figure 30), the Nch transistor isturned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tRESET).
(3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin isstable when VDD is minimum operation voltage or higher.
(4) Even if VSENSE increases, VSS is output when VSENSE is lower than VDET.
(5) When VSENSE increases to VDET or higher (point B in Figure 30), the Nch transistor is turned off. And then VDD
is output from the OUT pin after the elapse of the release delay time (tDELAY) when the output is pulled up.
SENSE
VDD
R
100 k

RA
VDD




*1

*1

VSENSE

OUT

Delay
circuit

RB

*1

VREF
Nch
RC

VSS

*1

CP
CP

*1.


V

*1

CN
CN

Parasitic diodeFigure 29

Operation of S-1011 Series G / Q Type(1)

Detection voltage (VDET)(2)
A(3) (4)B(5)

Release voltage (VDET)VSENSE
Minimum operation voltage
VSS
VDD
Output from OUT pin

RemarktRESETtDELAYThe release voltage is set to the same value as the detection voltage, since there is no hysteresis width.

Figure 30

20

VSS

Timing Chart of S-1011 Series G / Q Type

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

2.

SENSE pin
2. 1

Error when detection voltage is set externally

The detection voltage for the S-1011 Series is 10.0 V max., however, in the SENSE detection product with VDET =10.0 V, the detection voltage can be set externally by connecting a node that was resistance-divided by the resistor(RA) and the resistor (RB) to the SENSE pin as shown in Figure 31.
For conventional products without the SENSE pin, external resistor cannot be too large since the resistance-divided
node must be connected to the VDD pin. This is because a feed-through current will flow through the VDD pin
when it goes from detection to release, and if external resistor is large, problems such as oscillation or larger error
in the hysteresis width may occur.
In the S-1011 Series, RA and RB in Figure 31 are easily made larger since the resistance-divided node can beconnected to the SENSE pin through which no feed-through current flows. However, be careful of error in thecurrent flowing through the internal resistance (RSENSE) that will occur.
Although RSENSE in the S-1011 Series is large (the S-1011 Series E / G type: 26 M min., the S-1011 Series N / Q
type: 6.8 M min.) to make the error small, RA and RB should be selected such that the error is within the allowable
limits.
2. 2

Selection of RA and RB

In Figure 31, the relation between the external setting detection voltage (VDX) and the actual detection voltage(VDET) is ideally calculated by the equation below.
RA
VDX = VDET  (1  R )B··· (1)

However, in reality there is an error in the current flowing through RSENSE.
When considering this error, the relation between VDX and VDET is calculated as follows.
RA
VDX = VDET  (1  R || R
)
B
SENSE
RA

= VDET  1 
RB  RSENSE RB  RSENSE RARA VDET= VDET  (1  R )  R
B
SENSE··· (2)RA.
By using equations (1) and (2), the error is calculated as VDET  R
SENSE
The error rate is calculated as follows by dividing the error by the right-hand side of equation (1).
RA || RB
RA  RB
 100 [%] = R
 100 [%]RSENSE  (RA  RB)
SENSE··· (3)As seen in equation (3), the smaller the resistance values of RA and RB compared to RSENSE, the smaller the error
rate becomes.

21

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 SeriesAlso, the relation between the external setting hysteresis width (VHX) and the hysteresis width (VHYS) is calculated
by equation below. Error due to RSENSE also occurs to the relation in a similar way to the detection voltage.
RA
VHX = VHYS  (1  R )B··· (4)
A
RA
VDX

VDET

VDD
SENSE

OUT

RSENSERB

Figure 31

VSS

Detection Voltage External Setting Circuit

Caution 1. When externally setting the detection voltage, perform the operation with VDET = 10.0 V product.
Contact our sales office for details.
2. If the current flowing through RB is set to 1 A or less, the error may become larger.
3. If the parasitic resistance and parasitic inductance between VDX  point A and point A  VDD pin
are larger, oscillation may occur. Perform thorough evaluation using the actual application.
4. If RA and RB are large, the SENSE pin input impedance becomes higher and may cause a
malfunction due to noise. In this case, connect a capacitor between the SENSE pin and the VSS
pin.

22

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

3.

Delay circuit
The delay circuit has a function that adjusts the detection delay time (tRESET) from when the power supply voltage(VDD) or SENSE pin voltage (VSENSE) reaches the detection voltage (VDET) or lower to when the output from OUT
pin inverts.
It also has a function that adjusts the release delay time (tDELAY) from when the power supply voltage (VDD) or
SENSE pin voltage (VSENSE) reaches the release voltage (VDET) to when the output from OUT pin inverts.
tRESET is determined by the delay coefficient, the delay capacitor (CN) and the detection delay time when the CN pin
is open (tRESET0), and the tDELAY is determined by the delay coefficient, the delay capacitor (CP) and the release
delay time when the CP pin is open (tDELAY0). They are calculated by the equation below.
tRESET [ms] = Delay coefficient  CN [nF]  tRESET0 [ms]tDELAY [ms] = Delay coefficient  CP [nF]  tDELAY0 [ms]Table 19
Operation
Temperature
Ta = 85°C
Ta = 25°C
Ta = 40°C

Min.

Delay Coefficient
Typ.

Max.

2.41
2.41
2.40

2.85
2.86
2.83

3.32
3.30
3.25

Table 20
Operation
Temperature
Ta = 40°C to 85°C
Caution 1.

2.

3.

Detection Delay Time
when CN Pin is Open (tRESET0)
Typ.
0.35 ms

Release Delay Time
when CP Pin is Open (tDELAY0)
Typ.
0.35 ms

Mounted board layout should be made in such a way that no current flows into or flows fromthe CN pin or CP pin since the impedance of the CN pin and CP pin are high, otherwise correct
delay time cannot be provided.
There is no limit for the capacitance of CN and CP as long as the leakage current of thecapacitor can be ignored against the built-in constant current value (approximately 300 nA).
The leakage current may cause error in delay time. When the leakage current is larger than thebuilt-in constant current, no detect or release takes place.
The above equation will not guarantee successful operation. Determine the capacitance of CN
and CP through thorough evaluation including temperature characteristics in the actual usage
conditions.
When using an X8R equivalent capacitor, refer to the "2. Detection delay time (tRESET) vs.
Temperature (Ta)", "3. Detection delay time (tRESET) vs. Power supply voltage (VDD)", "5.
Release delay time (tDELAY) vs. Temperature (Ta)" and "6. Release delay time (tDELAY) vs.
Power supply voltage (VDD)" in " Reference Data" for details.

23

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Usage Precautions
1.

Feed-through current during detection and release
In the S-1011 Series, the feed-through current flows at the time of detection and release. For this reason, if the
input impedance is high, oscillation may occur due to voltage drop caused by the feed-through current.
When using the S-1011 Series in configurations like those shown in Figure 32 and Figure 33, it is recommended
that input impedance be set to 1 k or less.
Determine the impedance through thorough evaluation including temperature characteristics.
RA

VDD

RA

VDD

VDD

VDD
OUT

VBAT

VBAT
VSS

Figure 32

24

OUT

SENSE

CP

VSS

CN

VDD Detection ProductFigure 33

CP

CN

SENSE Detection ProductHIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

2.

Power on and shut down sequence
SENSE detection products monitor SENSE pin voltage (VSENSE) while power is being supplied to the VDD pin.
Apply power in the order, the VDD pin then the SENSE pin.
In addition, when shutting down VDD pin, shut down the SENSE pin first, and shut down the VDD pin after thedetection delay time (tRESET) has elapsed.
VDD

VDET

VSENSEVDET(S)tDELAYtRESET

VOUT

Figure 34

Falling power (reference)
Figure 35 shows the relation between VDD amplitude (VP-P) and input voltage falling time (tF) where the releasestatus can be maintained when the VDD pin (VDD detection product) sharply drops to a voltage equal to or higher
than the detection voltage (VDET) during release status.
S-1011A50
Ta = 40C to 85C
40.0
30.0

VP-P [V]

3.

20.0
10.0
0.0
0.1

1
tF [s]10

Figure 35
tF
VIH*1
VDET

VP-P

VIL*2

VDD

VDET
VSS

*1.
*2.

VIH = 36.0 V
VIL = VDET(S)  1.0 V

Figure 36
CautionVDD Pin Input Voltage Waveform

Figure 35 shows the input voltage conditions which can maintain the release status. If thevoltage whose VP-P and tF are larger than these conditions is input to the VDD pin (VDD detection
product), the OUT pin may change to a detection status.

25

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

4.

Detection delay time accuracy (reference)
Figure 37 and Figure 38 show the relation between VDD amplitude (VP-P) and input voltage falling time (tF) where
the arbitrarily set detection delay time accuracy can be maintained when the VDD pin (VDD detection product)
sharply drops.
S-1011A50

S-1011A50
Ta = 40C to 85C

40.0

40.0

30.0

30.0

VP-P [V]VP-P [V]Ta = 40C to 85C

20.0
10.0

20.0
10.0

0.0

0.0
0.1

1
tF [s]Figure 37

0.1

10

CN = 3.3 nF

1
tF [s]Figure 38

10

CN = 100 nF

tF
VIH*1
VDET
VP-P
VDD VDET
VIL*2
3.0 V
VSS

*1.
*2.

VIH = 36.0 V
VIL = VDET(S)  1.0 V (3.0 V min.)Figure 39
Caution26

VDD Pin Input Voltage Waveform

Figure 37 and Figure 38 show the input voltage conditions which can maintain the detection
delay time accuracy. If the voltage whose VP-P and tF are larger than these conditions is input tothe VDD pin (VDD detection product), the desired detection delay time may not be achieved.

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

VDD drop during release delay time (reference)
Figure 40 and Figure 41 show the relation between pulse width (tPW ) and VDD lower limit (VDROP) where a releasesignal can be output after the normal release delay time has elapsed when the VDD pin (VDD detection product)
instantaneously drops to the detection voltage (VDET) or lower and then increases to the release voltage (VDET) or
higher during release delay time.
S-1011AA0
Ta = 40C to 85C, CP = CN = 3.3 nF,
10000

1000

1000
tPW [s]

S-1011A50
Ta = 40C to 85C, CP = CN = 3.3 nF,
10000

tPW [s]

5.

Inhibited Area

100
10

Inhibited Area

100
10

1

1
0.0

0.5

1.0

1.5

0.0

2.0

0.5

VDROP [V]Figure 40

1.0
VDROP [V]

1.5

2.0

Figure 41
tF*1

tPW

tR*1

16 V

VDD

VDET

VDROP
tDELAY  0.8

tDELAYVOUT*1.

tR = tF = 10 s
Figure 42

Caution 1.

2.

VDD Pin Input Voltage Waveform

Figure 40 and Figure 41 show the input voltage conditions when a release signal is output
after the normal release delay time has elapsed. When this is within the inhibited area, release
may erroneously be executed before the delay time completes.
When the VDD pin voltage is within the inhibited areas shown in Figure 40 and Figure 41
during release delay time, input 0 V to the VDD pin then restart the S-1011 Series.

27

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Precautions
 Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
 Because the SENSE pin has a high impedance, malfunctions may occur due to noise.
Be careful of wiring adjoining SENSE pin wiring in actual applications.
 When designing for mass production using an application circuit described herein, the product deviation andtemperature characteristics of the external parts should be taken into consideration. ABLIC Inc. shall not bear any
responsibility for patent infringements related to products using the circuits described herein.
 ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement byproducts including this IC of patents owned by a third party.

28

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Characteristics (Typical Data)1.

Detection voltage (VDET), Release voltage (VDET) vs. Temperature (Ta)

VDET

5.30
5.20
5.10

VDET

5.00
4.90

2.

1. 2 SENSE detection productS-1011E50
5.40

VDET, VDET [V]VDET, VDET [V]

1. 1 VDD detection productS-1011A50
5.40

0

25
Ta [C]

50

VDET

5.30
5.20
5.10

VDET

5.00
4.90

40 25

VDD = 16.0 V

75 85

40 25025Ta [C]50

75 85

Detection voltage (VDET), Release voltage (VDET) vs. Power supply voltage (VDD)
2. 1

SENSE detection product

VDET, VDET [V]S-1011E50
5.40
VDET

5.30
5.20

Ta = 25C
Ta = 85C
Ta = 40C

5.10
5.00

VDET

4.90

0.0

3.

6.0

12.0

18.0 24.0
VDD [V]

30.0

36.0

Current consumption (ISS) vs. Power supply voltage (VDD)
3. 1

VDD detection product
VDD = 0 V  36.0 V

ISS [µA]

S-1011A50
1.50

Ta = +85°C

1.00
0.50
0.00

3. 2

Ta = +25°C
Ta = −40°C
0.0

6.0

12.0

18.0 24.0
VDD [V]SENSE detection product

30.0

36.0

Ta = −40°C

1.00

S-1011E50
1.50

Ta = +25°C

ISS [µA]

ISS [µA]

S-1011E50
VDD = 0 V  36.0 V,
VSENSE = VDET  0.1 V (during detection)
1.50

0.50

VDD = 0 V  36.0 V,
VSENSE = VDET  0.1 V (during release)

1.00

Ta = −40°C

0.50

Ta = +85°C
0.00

0.0

6.0

12.0

18.0 24.0
VDD [V]

30.0

36.0

Ta = +25°C

0.00

Ta = +85°C
0.0

6.0

12.0

18.0 24.0
VDD [V]

30.0

36.0

29

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

4.

Current consumption (ISS) vs. Temperature (Ta)
4. 1

VDD detection product4. 2

S-1011A50

S-1011E50
VDD = VDET  0.1 V

1.00
0.50

5.

40 250.50

25Ta [C]5075 85

40 25025Ta [C]50

75 85

Current consumption during detection delay (ISS) vs. Temperature (Ta)5. 1

VDD detection product
VCN = 0.2 V

2.00
1.00
0.00

6.

5. 2

40 25

25
Ta [C]50

VDD = 16.0 V, VCN = 0.2 V

2.00
1.00
0.00

0

SENSE detection productS-1011E50
3.00

ISS [A]

ISS [A]

S-1011A50
3.00

75 85

40 25025Ta [C]50

75 85

Current consumption during release delay (ISS) vs. Temperature (Ta)6. 1

VDD detection product

6. 2
VCP = 0.2 V

2.00
1.00
0.00

40 25

25
Ta [C]

50

75 85

VDD = 16.0 V, VCP = 0.2 V

2.00
1.00
0.00

0

SENSE detection productS-1011E50
3.00

ISS [A]

ISS [A]

S-1011A50
3.00

30

1.00

0.00
0

VDD = 16.0 V, VSENSE = VDET  0.1 V

1.50

ISS [A]

ISS [A]

1.50

0.00

SENSE detection product40 25025Ta [C]

50

75 85

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

7.

Nch transistor output current (IOUT) vs. VDS
7. 1

SENSE detection productS-1011E50

S-1011E50
VDD = VSENSE = 4.5 V, Ta = 40°C

30.0

VDD = VSENSE = 4.5 V, Ta = 25°C

30.0

20.0

VDD = 36.0 V

VDD = 16.0 V

IOUT [mA]

IOUT [mA]

VDD = 36.0 V

VDD = 3.0 V
10.0
0.0

20.0

VDD = 16.0 V
VDD = 3.0 V

10.0
0.0

0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

0.0

0.1

0.2

0.3
0.4
VDS [V]

0.5

0.6

S-1011E50
VDD = VSENSE = 4.5 V, Ta = 85°C

IOUT [mA]

30.0

VDD = 36.0 V

20.0

VDD = 16.0 V
VDD = 3.0 V

10.0
0.0
0.0

0.2

0.3
0.4
VDS [V]0.5

0.6

Nch transistor output current (IOUT) vs. Power supply voltage (VDD)
8. 1

VDD detection product

IOUT [mA]

S-1011A50
2.0

8. 2
VDS = 0.05 V

1.5
1.0

Ta = −40°C
Ta = +25°C
Ta = +85°C

0.5
0.0

0.0

5.0

10.0

1.5
1.0

Ta = +25°C

0.5
15.0

VDD [V]

RemarkSENSE detection productS-1011E50
VSENSE = 4.5 V, VDS = 0.05 V
2.5
Ta = −40°C
2.0
IOUT [mA]

8.

0.1

0.0

Ta = +85°C
0.0

6.0

12.0

18.0 24.0
VDD [V]

30.0

36.0

VDS: Drain-to-source voltage of the output transistor

31

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

9.

Minimum operation voltage (VOUT) vs. Power supply voltage (VDD)
9. 1

VDD detection productS-1011A50
Pull-up to VDD, Pull-up resistance: 100 k
6.0

S-1011A50
Pull-up to 16.0 V, Pull-up resistance: 100 k
20.0

4.0
3.0
2.0
1.0
0.0

9. 2

Ta = −40°C
Ta = +25°C
Ta = +85°C

VOUT [V]

VOUT [V]5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]

S-1011E50
VDD = 3.0 V,
Pull-up to 16.0 V, Pull-up resistance: 100 k
20.0

2.0

Ta = +85°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VSENSE [V]

VOUT [V]

VOUT [V]3.0

Ta = −40°C
Ta = +25°C

1.0

32

Ta = −40°C
Ta = +25°C
Ta = +85°C

SENSE detection product

5.0

0.0

10.0
5.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD [V]

S-1011E50
VDD = 3.0 V,
Pull-up to VDD, Pull-up resistance: 100 k
6.0
4.0

15.0

15.0
10.0
5.0
0.0

Ta = −40°C
Ta = +25°C
Ta = +85°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VSENSE [V]HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

10.

Dynamic response vs. Output pin capacitance(COUT) (CP pin, CN pin; open)
10. 1

VDD detection product
Ta = 40°C
tPHL

1
0.1

tPLH

0.01
0.001
0.00001

0.001
0.01
0.0001
Output pin capacitance [F]

0.1

tPHL

1
0.1

tPLH

0.01
0.001
0.00001

0.001
0.01
0.0001
Output pin capacitance [F]

0.1

Ta = 85°C

S-1011A50
10

Response time [ms]Ta = 25°C

S-1011A50
10

Response time [ms]Response time [ms]S-1011A50
10

tPHL

1
0.1

tPLH

0.01
0.001
0.00001

0.001
0.01
0.0001
Output pin capacitance [F]

1 s

0.1

1 s

VIH*1
Input voltage
VIL*2

tPHL

OUT

tPLH

VDD

VDD1
Output voltage

*1.
*2.

R
100 k

VDD

VDD1  50%

VDD1  50%



VSS

V

CP



CN

VDD1

V

VIH = 36.0 V
VIL = 3.0 V
Figure 43
CautionTest Condition of Response Time

Figure 44

Test Circuit of Response TimeThe above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

33

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series Reference Data1.

Detection delay time (tRESET) vs. CN pin capacitance (CN) (Without output pin capacitance)
1. 1

VDD detection producttRESET [ms]S-1011A50
1000
100
10

Ta = 40C

1
0.1
0.01

2.

Ta = 85C
Ta = 25C

0.1

1
10
CN [nF]

100

1000

Detection delay time (tRESET) vs. Temperature (Ta)2. 1

VDD detection productS-1011A50
CN = 3.3 nF

12.0

tRESET [ms]

10.0
8.0
6.0
4.0
2.0
0.0

40 25025Ta [C]

50

75 85

1 s
VIH*1
Input voltage
VIL*2

OUT

tRESET

VDD

VDD
VDD  50%

Output voltage

R
100 k

VDD



VSS

CP



CN

V

V
CN

VSS

*1.
*2.

VIH = VDET(S)  1.0 V
VIL = VDET(S)  1.0 V

Figure 45
Caution34

Test Condition of Detection Delay Time

Figure 46

Test Circuit of Detection Delay TimeThe above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

Detection delay time (tRESET) vs. Power supply voltage (VDD)
3. 1

SENSE detection product
CN = 3.3 nF

S-1011E50
12.0
tRESET [ms]3.

Ta = +25°C

11.0

Ta = +85°C

10.0
9.0
Ta = −40°C

8.0
0.0

6.0

12.0

18.0 24.0
VDD [V]

30.0

36.0

1 s
VIH*1
Input voltage
VIL*2

tRESET

VDD

VDD


V

OUT

SENSE
VSS

CP



CN
V

VDD  50%

Output voltage

R
100 kVDD

VSENSE

CN

VSS

*1.
*2.

VIH = VDET(S)  1.0 V
VIL = VDET(S)  1.0 V

Figure 47
CautionTest Condition of Detection Delay Time

Figure 48

Test Circuit of Detection Delay TimeThe above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

35

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

4.

Release delay time (tDELAY) vs. CP pin capacitance (CP) (Without output pin capacitance)
4. 1

VDD detection producttDELAY [ms]S-1011A50
1000
100
10

Ta = 40C

1
0.1
0.01

5.

Ta = 85C
Ta = 25C

0.1

1
10
CP [nF]

100

1000

Release delay time (tDELAY) vs. Temperature (Ta)5. 1

VDD detection productS-1011A50
CP = 3.3 nF

12.0

tDELAY [ms]

10.0
8.0
6.0
4.0
2.0
0.0

40 25025Ta [C]

50

75 85

1 s
VIH*1
Input voltage
VIL*2

OUT

tDELAY

VDD

VDD
VDD  50%

Output voltage

R
100 k

VDD



VSS

CP



CN

V

V
CP

VSS

*1.
*2.

36

VIH = VDET  1.0 V
VIL = VDET  1.0 V

Figure 49

Test Condition of Release Delay Time

Figure 50

Test Circuit of Release Delay Time

Caution

The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series

Release delay time (tDELAY) vs. Power supply voltage (VDD)
6. 1

SENSE detection product
CP = 3.3 nF

S-1011E50
12.0
tDELAY [ms]6.

Ta = 25C

Ta = 85C

11.0
10.0
9.0

Ta = 40C

8.0
0.0

6.0

12.0

18.0 24.0
VDD [V]

30.0

36.0

1 s
VIH*1
Input voltage
VIL*2

tDELAY

VDD

VDD


V

OUT

SENSE
VSS

CP



CN
V

VDD  50%

Output voltage

R
100 kVDD

VSENSE

CP

VSS

*1.
*2.

VIH = VDET  1.0 V
VIL = VDET  1.0 V

Figure 51

Test Condition of Release Delay Time

Figure 52

Test Circuit of Release Delay Time

Caution

The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

37

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series
 Application Circuit Examples
1.

Microcomputer reset circuits
In microcomputers, when the power supply voltage is lower than the minimum operation voltage, an unspecified
operation may be performed or the contents of the memory register may be lost. When power supply voltage
returns to the normal level, the microcomputer needs to be initialized. Otherwise, the microcomputer may
malfunction after that. Reset circuits to protect microcomputer in the event of current being momentarily switched
off or lowered.
Using the S-1011 Series which has the low minimum operation voltage, the high-accuracy detection voltage andthe hysteresis width, reset circuits can be easily constructed as seen in Figure 53 and Figure 54.

VDD

VDD1
VDD
OUT
VSS CP CN

VDD1

VSENSE

Microcomputer

VDD
SENSE
OUT
VSS CP CN

Microcomputer

GND

Figure 53

Caution38

Example of Reset Circuit(VDD detection product)

GND

Figure 54

Example of Reset Circuit(SENSE detection product)

The above connection diagram and constant will not guarantee successful operation.
Perform thorough evaluation using the actual application to set the constant.

HIGH-WITHSTAND VOLTAGE BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR
Rev.1.2_02
S-1011 Series Thermal Characteristics
1. SOT-23-6
Tj = 125C max.

Power dissipation (PD) [W]

1.0

0.8

0.6

0.2

Figure 55
Board 1

Board 10.63 W

0.4

0

1. 1

Board 20.81 W

0

50
100
150
Ambient temperature (Ta) [C]Power Dissipation of Package (When Mounted on Board)*1

76.2 mmTable 21114.3 mm

Item
Thermal resistance value
(ja)
Size
Material
Number of copper foil layer
12
Copper foil layer
34Thermal via

Figure 56

Specification
159C/W
114.3 mm  76.2 mm  t1.6 mm
FR-4
2Land pattern and wiring for testing: t0.070 mm

74.2 mm  74.2 mm  t0.070 mm


1. 2 Board 2*1
76.2 mmTable 22114.3 mm

Item
Thermal resistance value(ja)Figure 57*1.

Size
Material
Number of copper foil layer
12
Copper foil layer
34Thermal via

Specification
124C/W
114.3 mm  76.2 mm  t1.6 mm
FR-4
4Land pattern and wiring for testing: t0.070 mm
74.2 mm  74.2 mm  t0.035 mm
74.2 mm  74.2 mm  t0.035 mm
74.2 mm  74.2 mm  t0.070 mm


The board is same in SOT-23-3, SOT-23-5 and SOT-23-6.

39

2.9±0.2
1.9±0.2
6

0.95

4

5

1

2

3

+0.1

0.15 -0.05

0.95

0.35±0.15

No. MP006-A-P-SD-2.1

TITLE

SOT236-A-PKG Dimensions

No.

MP006-A-P-SD-2.1

ANGLE
UNIT

mm

ABLIC Inc.

4.0±0.1(10 pitches:40.0±0.2)+0.1

ø1.5 -0+0.2

ø1.0 -0

2.0±0.05

0.25±0.1

4.0±0.1

1.4±0.2

3.2±0.2

3 2 1

4 5 6

Feed direction

No. MP006-A-C-SD-3.1

TITLE

SOT236-A-Carrier Tape

No.

MP006-A-C-SD-3.1

ANGLE
UNIT

mm

ABLIC Inc.

12.5max.

9.0±0.3

Enlarged drawing in the central part

ø13±0.2

(60°)

(60°)

No. MP006-A-R-SD-2.1

TITLE

SOT236-A-Reel

No.

MP006-A-R-SD-2.1

ANGLE

QTY

UNIT

mm

ABLIC Inc.

3,000

Disclaimers (Handling Precautions)1.

All the information described herein (product data, specifications, figures, tables, programs, algorithms andapplication circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.

2.

The circuit examples and the usages described herein are for reference only, and do not guarantee the success ofany specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any otherright due to the use of the information described herein.

3.

ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information describedherein.

4.

Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due tothe use of the products outside their specified ranges.

5.

Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.

6.

When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-relatedlaws, and follow the required procedures.

7.

The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,biological or chemical weapons or missiles, or use any other military purposes.

8.

The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.

9.

In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products areallowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of thisdocument described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07

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