Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is thecompany that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon productportfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon productportfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use theordering part numbers listed in the datasheet for ordering.

www.infineon.com

PRELIMINARYCYW43907

WICED™ IEEE 802.11 a/b/g/n SoC with an
Embedded Applications Processor
The Cypress CYW43907 embedded wireless system-on-a-chip (SoC) is uniquely suited for Internet-of-Things (IoT) applications. It
supports all rates specified in the IEEE 802.11 a/b/g/n specifications.The device includes an Arm® Cortex®-based applications
processor, a single stream IEEE 802.11n MAC/baseband/radio, a dual-band 5 GHz and 2.4 GHz transmit power amplifier (PA), anda receive low-noise amplifier (LNA). It also supports optional antenna diversity for improved RF performance in difficult environments.
The CYW43907 is an optimized SoC targeting embedded IoT applications in the industrial and medical sensor, home appliance, andembedded audio markets. Using advanced design techniques and process technology to reduce active and idle power, the device isdesigned for embedded applications that require minimal power consumption and a compact size.
The device includes a PMU for simplifying system power topology and allows for direct operation from a battery while maximizing
battery life.

Features
Application Processor Features■■Arm® Cortex®-R4 32-bit RISC processor.

■

2 MB of on-chip SRAM for code and data.

■

An on-chip Cryptography core■

Software architecture supported by standard WICED® SDK
allows easy migration from existing discrete MCU designs
and to future devices.
Security support:❐®
■ 640 KB of ROM containing WICED SDK components such

as RTOS and TCP/IP stack.

❐

WPA and WPA2 (Personal) support for powerfulencryption and authentication.
AES and TKIP in hardware for faster data encryption andIEEE 802.11i compatibility.
Reference WLAN subsystem provides Cisco compatible
extensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, and CCX
5.0).
Wi-Fi Protected Setup and Wi-Fi Easy Setup■

17 GPIOs supported.

■

Q-SPI serial flash interface to support up to 40 Mbps of peaktransfer.

■

Support for UART (3), SPI/ Cypress Serial Control (CSC)
Master (2), CSC-only (2), and I2S (2) Interfaces. (CSC is an
I2C-compatible Interface.)■■

Dedicated fractional PLL for audio clock (MCLK) generation.

General Features■

USB 2.0 host and device modes.

■■

SDIO 3.0 host mode.

Supports battery voltage range from 3.0 V to 4.8 V with aninternal switching regulator.

■

Programmable dynamic power management.

■

6 Kb OTP memory for storing board parameters■316-bump wafer-level chip-scale package (WLCSP)(4.583 mm × 5.533mm, 0.2mm pitch)

Key IEEE 801.11x Features■

IEEE 802.11n compliant.

■Single-stream spatial multiplexing up to 150 Mbps.

■

Supports 20/40 MHz channels with optional SGI.

■

Full IEEE 802.11 a/b/g legacy compatibility with enhanced
performance.

■

On-chip power and low-noise amplifiers.

■

An internal fractional nPLL allows support for a wide range ofreference clock frequencies.

■

❐

❐

Worldwide regulatory support: Global products supportedwith worldwide design approval.

Integrated Arm® Cortex®-R4 processor with tightly coupledmemory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for
standard WLAN functions (to further minimize power consumption while maintaining the ability to upgrade to futurefeatures in the field).

Cypress Semiconductor Corporation
Document Number: 002-14829 Rev. *L•

198 Champion Court•

San Jose, CA 95134-1709•
408-943-2600
Revised Tuesday, March 23, 2021

PRELIMINARYCYW43907n.

Figure 1. Functional Block DiagramCYW43907
2 MB RAM,640 KB ROM

USB 2.0

UART

SDIO 3.0

CSC

PWM (6)PWM
SPI

CSC (2)

USB

SPI (2)GPIO

Crytography
Engine

AXI

DMA

I2S

Audio PLLRMII/MII

AXI

Audio

32 kHzExternal LPO®

WLAN Arm
Cortex ® -R4

AXI-to-AXI
Bridge

AXI to AXI
BridgeJTAG

GPIO (17)I2S (2)APPS ARM
Cortex-R4
32 KB (I),32 KB (D)ICACHESDIO

UART (3)TCM
512 KB RAM
320 KB ROM

WLANIEEE 802.11 MAC

APPS Domain

RF Switch Controls
1 x 1, IEEE 802.11n PHY

Always-On Domain
REG_ONHIB_REG_ON_IN

AXI
PS RAMPS
SR_Eng

CSC = Cypress Serial Control. An I2C‐compatible interface.

PMU

TX
Switch

VIO

LNA
PMU
Control

VBAT

37.4 MHz Crystal

2.4 GHz and 5 GHz Radio

AXI-to-AXI
Bridge2.4 GHz

PA

LNA

5 GHz

PA

TX
Switch

WRF_PAOUT_5G
WRF_RFIN_5G
WRF_PAOUT_2G
WRF_RFIN_2G

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

Contents
1. Overview ................................................................ 5
1.1

Introduction ..............................................................5
1.1.1

1.2

7.2

Features ...................................................... 5

7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8

Standards Compliance .............................................6

2. Power Supplies and Management....................... 7
2.1

Power Supply Topology ...........................................7

2.2

CYW43907 Power Management Unit Features .......7

2.3Power Management ..............................................10

2.4

PMU Sequencing ...................................................10

2.5

Power OFF Shutdown ............................................11

2.6

Power Up/Power Down/Reset Circuits ...................11

3. Frequency References ....................................... 12
3.1

Crystal Interface and Clock Generation .................12

3.2

External Frequency Reference ..............................13

3.3

External 32.768 kHz Low-Power Oscillator (LPO) .14

4. Applications Subsystem .................................... 15
4.1

Overview ................................................................15

4.2

Applications CPU and Memory Subsystem ...........15

4.3

Memory-to-Memory DMA Core ..............................15

4.4

Cryptography Core .................................................15

5. Applications Subsystem External Interfaces ... 16

IEEE 802.11n MAC ................................................ 25
7.2.1 Programmable State Machine (PSM) ......... 26
7.2.2 Wired Equivalent Privacy (WEP) ................ 26

7.3

Transmit Engine (TXE) ............................... 27
Receive engine (RXE) ................................ 27
Interframe-spacing (IFS) ............................. 27
Timing Synchronization Function (TSF) ..... 27
Network Allocation Vector (NAV) ................ 27
MAC-PHY Interface .................................... 28

IEEE 802.11™ a/b/g/n PHY .................................... 28

8. WLAN Radio Subsystem ................................... 29
8.1

Receiver Path ......................................................... 29

8.2

Transmit Path ......................................................... 29

8.3

Calibration .............................................................. 29

9. Pinout and Signal Descriptions........................ 30
9.1

Bump List ............................................................... 31

9.2

Signal Descriptions ................................................ 35

10. GPIO Signals and Strapping Options ............... 41
10.1 Overview ................................................................ 41
10.2 Weak Pull-Down and Pull-Up Resistances ............ 41
10.3 Strapping Options .................................................. 41
10.4 Alternate GPIO Signal Functions ...........................42

11. Pin Multiplexing .................................................. 43

5.1

Ethernet MAC Controller (MII/RMII) .......................16

5.2

GPIO ......................................................................16

12. I/O States ............................................................. 46

5.3

Cypress Serial Control (CSC) ................................16

13. Electrical Characteristics................................... 48

5.4

I2S ..........................................................................16

13.1 Absolute Maximum Ratings ................................... 48

5.5

JTAG and Arm® Serial Wire Debug .......................18

13.2 Environmental Ratings ........................................... 48

5.6

Pulse Width Modulation (PWM) .............................18

13.3 Electrostatic Discharge Specifications ................... 49

5.7

SDIO 3.0 - Host Mode ............................................18

5.8

S/PDIF ....................................................................19

13.4 Recommended Operating Conditions and DC ...........
Characteristics 49

5.9

SPI Flash ................................................................19

13.5 Power Supply Segments ........................................ 51

5.10 UART .....................................................................20

13.6 Ethernet MAC Controller (MII/RMII) DC
Characteristics ....................................................... 51

5.11 USB 2.0 ..................................................................20
5.11.1 Overview .....................................................20
5.11.2 USB 2.0 Features ....................................... 225.12 SPI .........................................................................22

6. Global Functions................................................. 23

13.7 GPIO, UART, and JTAG Interfaces DC
Characteristics ....................................................... 51

14. WLAN RF Specifications.................................... 52
14.1 Introduction ............................................................ 52
14.2 2.4 GHz Band General RF Specifications .............. 52

6.1

External Coexistence Interface ..............................23

6.2

OTP ........................................................................23

6.3

Hibernation Block ...................................................23

6.4

System Boot Sequence ..........................................24

14.4 WLAN 2.4 GHz Transmitter Performance ..................
Specifications 55

7. Wireless LAN Subsystem................................... 25

14.5 WLAN 5 GHz Receiver Performance
Specifications ......................................................... 56

7.1

WLAN CPU and Memory Subsystem ....................25

Document Number: 002-14829 Rev. *L

14.3 WLAN 2.4 GHz Receiver Performance
Specifications ......................................................... 53

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PRELIMINARYCYW43907

14.6 WLAN 5 GHz Transmitter Performance
Specifications .........................................................58

17.5.3 Memory Fast-Read Timing ......................... 80

14.7 General Spurious Emissions Specifications ...........58
14.7.1 Transmitter Spurious Emissions
Specifications .............................................59
14.7.2 Receiver Spurious Emissions
Specifications .............................................60

17.5.5 SPI Flash Parameters ................................ 82

15. Internal Regulator Electrical Specifications..... 61
15.1 Core Buck Switching Regulator .............................61

17.5.4 Memory-Write Timing ................................. 81
17.6 USB PHY Electrical Characteristics and Timing .... 83
17.6.1 USB 2.0 and USB 1.1 Electrical andTiming Parameters ..................................... 83
17.6.2 USB 2.0 Timing Diagrams .......................... 85

18. Power-Up Sequence and Timing ....................... 87

15.4 LNLDO ...................................................................6418.1 Sequencing of Reset and Regulator Control
Signals ................................................................... 87
18.1.1 Description of Control Signals .................... 87
18.1.2 Control Signal Timing Diagrams ................. 87

15.5 BBPLL LDO ............................................................65

19. Thermal Information ........................................... 88

16. System Power Consumption ............................. 66

19.1 Package Thermal Characteristics .......................... 88

16.1 WLAN Current Consumption ..................................66
16.1.1 2.4 GHz Mode ............................................66
16.1.2 5 GHz Mode ...............................................67

19.2 Junction Temperature Estimation and PSIJT Versus .
THETAJC 88

17. Interface Timing and AC Characteristics.......... 68

20. Mechanical Information...................................... 89

17.1 Ethernet MAC (MII/RMII) Interface Timing .............68
17.1.1 MII Receive Packet Timing .........................68

21. Ordering Information.......................................... 90

17.1.2 MII Transmit Packet Timing ........................ 68

22. Additional Information ....................................... 90

15.2 3.3V LDO (LDO3P3) ..............................................6215.3 CLDO .....................................................................63

19.3 Environmental Characteristics ............................... 88

17.1.3 RMII Receive Packet Timing ...................... 69

22.1 Acronyms and Abbreviations ................................. 90

17.1.4 RMII Transmit Packet Timing ..................... 70

22.2 References ............................................................. 91

17.2 I2S Master and Slave Mode TX Timing ..................71

22.3 IoT Resources ........................................................ 91

17.3 SDIO Interface Timing ............................................73
17.3.1 SDIO Default-Speed Mode Timing .............73

22.4 Errata ..................................................................... 91

17.3.2 SDIO High-Speed Mode Timing ................. 74
17.3.3 SDIO Bus Timing Specifications in SDR
Modes .........................................................75
17.4 S/PDIF Interface Timing .........................................76
17.5 SPI Flash Timing ....................................................78
17.5.1 Read-Register Timing .................................78

Document History Page ..................................................... 92
Sales, Solutions, and Legal Information .......................... 94
Worldwide Sales and Design Support ............................94
Products ......................................................................... 94
Cypress Developer Community ...................................... 94
Technical Support ........................................................... 94

17.5.2 Write-Register Timing ................................. 79

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

1. Overview
1.1 Introduction
The Cypress CYW43907 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip withintegrated IEEE 802.11 a/b/g/n MAC/baseband/radio and a separate Arm® Cortex®-R4 applications processor. It provides a small
form-factor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system withflexibility in size, form, and function. Comprehensive power management circuitry and software ensure that the system can meet theneeds of highly embedded systems that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43907 and their associated external interfaces, which aredescribed in greater detail in Section 5. “Applications Subsystem External Interfaces”.
Figure 2. Block Diagram and I/O

CYW43907
SPI Flash
GPIO[16:0]

RF TX
APPS Subsystem

WLAN Subsystem

Arm® Cortex®‐R4

Arm® Cortex®‐R4

320 MHz
32 KB I‐cache
32 KB D‐cache

160 MHz448 KB ROM TCM
576 KB SRAM TCM

2 MB SRAM
640 KB ROM

802.11n
1x1
2.4 GHz and 5 GHz

RF RX

2x 2-Wire UART
4-Wire UART
2x I2S
2x SPI/CSC
2x CSC
JTAG/SWD
10/100 Ethernet

Switch Control
Antenna Diversity

SDIO 3.0/gSPI

VDDIOsUSB 2.0

GND

WAKE

1.1.1 Features
The CYW43907 supports the following features:■

The applications domain (APPS) Arm® Cortex®-R4 core can be clocked at 60 MHz, 80 MHz, 120 MHz, 160 MHz or 320 MHz.

■

2 MB of SRAM and 640 KB ROM available for the applications processor.

■

One high-speed 4-wire UART Interface with operation up to 3 Mbps.

■

Two low-speed 2-wire UART interfaces multiplexed on general purpose I/O (GPIO) pins.

■

Two dedicated CSC1 interfaces.

■ Two SPI master interfaces with operation up to 24 MHz.
Note: Either or both of the SPI interfaces can be used as CSC master interfaces. This is in addition to the two dedicated CSC
interfaces.
■

One SPI Master Interface for Serial Flash.

■Six dedicated PWM outputs.

1. Cypress Serial Control (CSC) is an I2C-compatible Interface.

Document Number: 002-14829 Rev. *L

Page 5 of 94

PRELIMINARY■

Two I2S interfaces.

■

Seventeen GPIOs.

■

IEEE 802.11 a/b/g/n 1×1 2.4 GHz and 5 GHz radio.

■

Single and dual-antenna support.

CYW43907

1.2 Standards Compliance
The CYW43907 supports the following standards:■

IEEE 802.11n■

IEEE 802.11b■

IEEE 802.11g■

IEEE 802.11d■IEEE 802.11h■

IEEE 802.11i■

Security:
❐

WEP

❐

WPA Personal❐

WPA2 Personal

❐

WMM

❐

WMM-PS (U-APSD)❐

WMM-SA❐AES (hardware accelerator)❐

TKIP (hardware accelerator)❐

CKIP (software support)

The CYW43907 supports the following additional standards:■

IEEE 802.11r—Fast Roaming (between APs)■

IEEE 802.11w—Secure Management Frames■IEEE 802.11 Extensions:❐

IEEE 802.11e QoS enhancements (already supported as per the WMM specification)❐

IEEE 802.11i MAC enhancements❐

IEEE 802.11k radio resource measurement

Document Number: 002-14829 Rev. *L

Page 6 of 94

PRELIMINARYCYW43907

2. Power Supplies and Management
2.1 Power Supply Topology
One core buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43907. All
regulators are programmable via the PMU. These blocks simplify power supply design for application and WLAN functions inembedded designs.
A single VBAT (3.0V to 4.8V DC maximum) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by
the regulators in the CYW43907.
The REG_ON control signal is used to power up the regulators and take the appropriate sections out of reset. The CBUCK, CLDO,LNLDO, and other regulators power up when any of the reset signals are deasserted. All regulators are powered down only when
REG_ON is deasserted. The regulators may be turned off/on based on the dynamic demands of the digital baseband.
The CYW43907 provides a low power-consumption mode whereby the CBUCK, CLDO, and LNLDO regulators are shutdown. In thisstate, the low-power linear regulator (LPLDO1) supplied by the system VIO supply provides the CYW43907 with all required voltages.

2.2 CYW43907 PMU Features
The CYW43907 supports the following PMU features:■

VBAT to 1.35Vout (550 mA maximum) core buck (CBUCK) switching regulator■

VBAT to 3.3Vout (450 mA maximum) LDO3P3■

1.35V to 1.2Vout (150 mA maximum) LNLDO■

1.35V to 1.2Vout (350 mA maximum) CLDO with bypass mode for Deep Sleep■

1.35V to 1.2Vout (55 mA maximum) LDO for BBPLL■

Additional internal LDOs (not externally accessible)■

PMU internal timer auto-calibration by the crystal clock for precise wakeup timing from the low power-consumption mode.

Figure 3 and Figure 4 show the regulators and a typical power topology.

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PRELIMINARYCYW43907

Figure 3. Typical Power Topology (Page 1 of 2)
WLRF TX Mixer and PA (not always)

CYW43907 1.2V
VBAT
Operational:
2.3V to 4.8V
Performance:
3.0V to 4.8V
Absolute Maximum: 5.5V
VDDIO
Operational:

3.3V

Cap-less
LNLDO

1.2V

Cap-less
LNLDO

1.2V

Cap-less
VCOLDO
Cap-less
LNLDO

1.2V

Cap-less
LNLDO

1.2V

15 mA
XTAL LDO

1.2V

1.2V

Mini‐PMU(Inside WL Radio)
VBAT

1.35V

LPLDO1WLRF LNA
WLRF AFE and TIAWLRF TXWLRF ADC REF
WLRF XTALWLRF RFPLL, PFD, and MMD
1.2V

LNLDO

Core Buck
Regulator(CBUCK)VDDIO

WLRF LOGEN

1.35V

BBPLL
LNLDO

Audio PLL

1.2V
WL BBPLL/DFLL

REG_ON

CLDO

1.3V, 1.2V,.095V (AVS)WLAN/CLB/Top, Always On
WL PHYWL Subcore

Supply ballSupply bump/pad

PowerswitchGround ball

Ground bump/pad

No power switch

WLAN resetball

External to chipNo dedicated power switch, but internal power‐
down modes and block‐specific power switches

Document Number: 002-14829 Rev. *L

WL VDDM (SRAMS in AOS)APPS VDDMAPPS SOCSRAMAPPS Subcore

Page 8 of 94

PRELIMINARYCYW43907

Figure 4. Typical Power Topology (Page 2 of 2)

CYW43907 2.5V and 3.3V
450 to800 mAWLRF PA(2.4 GHz and 5 GHz)

3.3V

VBAT

LDO3P3WLRF Pad (2.4 GHz and 5 GHz)VDDIO_RFWL OTP 3.3V

2.5V Cap-less
LNLDO

WL RF RX, TX, NMOS, Mini-PMU LDOs

2.5V Cap-less
LNLDO

2.5V

2.5V Cap-less
LNLDO

2.5V

WL RF VCOWL RF CPVCOLDO2P5
Inside WL Radio

Supply ballSupply bump/pad

PowerswitchGround ball

Ground bump/pad

No power switch

External to chipNo dedicated power switch, but internal power‐
down modes and block‐specific power switches

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

2.3 Power Management
The CYW43907 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of thechip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current
and supply voltages. Additionally, the CYW43907 includes an advanced PMU sequencer. The PMU sequencer provides significant
power savings by putting the CYW43907 into various power management states appropriate to the environment and activities thatare being performed. The PMU enables and disables internal regulators, switches, and other blocks based on a computation of therequired resources and a table that describes the relationship between resources and the time needed to enable and disable them.
Power up sequences are fully programmable. Configurable, free-running counters (running at a 32.768 kHz LPO clock) in the PMU
sequencer are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically changed (or gatedaltogether) as a function of the mode. Slower clock speeds are used whenever possible.
Table 2 provides descriptions for the CYW43907 power modes.
Table 2. CYW43907 Power Modes
Mode

Description

ActiveAll WLAN blocks in the CYW43907 are powered up and fully functional with active carrier sensing and frametransmission and receiving.
All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds
are dynamically adjusted by the PMU sequencer.

Doze

The radio, analog domains, and most of the linear regulators are powered down.
The rest of the CYW43907 remains powered up in an idle state. All main clocks (PLL, crystal oscillator, or TCXO)
are shut down to minimize active power consumption. The 32.768 kHz LPO clock is available only for the PMU
sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active
Mode. In Doze Mode, the primary power consumed is due to leakage current.

Deep Sleep

Most of the chip, including both analog and digital domains and most of the regulators, is powered OFF.
Logic states in the digital core are saved and preserved in a retention memory in the Always-On domain before
the digital core is powered off. Upon a wakeup event triggered by the PMU timers, an external interrupt, or a hostresume through the USB bus, logic states in the digital core are restored to their pre-Deep Sleep settings to avoid
lengthy Hardware reinitialization.

Power Down

The CYW43907 is effectively powered OFF by shutting down all internal regulators.
The chip is brought out of this mode by external logic re-enabling the internal regulators.

2.4 PMU Sequencing
The PMU sequencer minimizes system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable
them.
Resource requests can come from several sources: clock requests from cores, the minimum resources defined in the ResourceMin
register, and the resources requested by any active resource-request timers. The PMU sequencer maps clock requests into a set ofresources required to produce the requested clocks.
Each resource is in one of the following four states:■

Enabled■Disabled■

Transition_on■

Transition_off

The timer contains 0 when the resource is enabled or disabled and a nonzero value when in a transition state. The timer is loadedwith the time_on or time_off value of the resource after the PMU determines that the resource must be enabled or disabled anddecrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to
enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0
indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequencerefer to either the immediate transition or the timer load-decrement sequence.
Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

During each clock cycle, the PMU sequencer performs the following actions:■

Computes the required resource set based on requests and the resource dependency table.

■

Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit of the resource
and inverts the ResourceState bit.

■Compares the request with the current resource status and determines which resources must be enabled or disabled.

■

Initiates a disable sequence for each resource that is enabled, is no longer being requested, and has no powered-up dependents.

■

Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

2.5 Power off Shutdown
The CYW43907 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other system
devices remain operational. When the CYW43907 is not needed in the system, VDDIO_RF and VDDC are shutdown while VDDIO
remains powered. This allows the CYW43907 to be effectively off while keeping the I/O pins powered so that they do not draw extra
current from devices connected to the I/O.
During a low-power shutdown state, provided VDDIO remains applied to the CYW43907, all outputs are tristate and most inputs
signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths
or create loading on any digital signals in the system, and enables the CYW43907 to be fully integrated in an embedded device while
taking full advantage of the lowest power-saving modes.
When the CYW43907 is powered on from this state, it is the same as a normal power-up and does not retain any information about
its state from before it was powered down.

2.6 Power Up/Power Down/Reset Circuits
The CYW43907 has two signals (see Table 3) that enable or disable circuits and the internal regulator blocks, allowing the host tocontrol power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 18. “Power-Up
Sequence and Timing”.
Table 3. Power-Up/Power-Down/Reset Control Signals
SignalDescription

REG_ON

This signal is used by the PMU to power up the CYW43907. It controls the internal CYW43907 regulators.
When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low, the device
is in reset and the regulators are disabled. This pin has an internal 200 k pull-down (PD) resistor that is
enabled by default. It can be disabled through programming.

HIB_REG_ON_IN

This signal is used by the hibernation block to decide whether or not to power down the internal CYW43907
regulators. If HIB_REG_ON_IN is LOW, the regulators will be disabled. For a signal at HIB_REG_ON_IN tofunction as intended, HIB_REG_ON_OUT must be connected to REG_ON.

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

3. Frequency References
An external crystal is used for generating all radio frequencies and normal-operation clocking. As an alternative, an external frequency
reference can be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.

3.1 Crystal Interface and Clock Generation
The CYW43907 can use an external crystal to provide a frequency reference. The recommended crystal oscillator configuration,
including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.
Figure 5. Recommended Oscillator Configuration

Device boundaryC
WRF_XTAL_XON
1.3 pF
27 pF
37.4 MHzC
x ohmsProgrammable internal shunt caps arefrom 0 pF to 7.5 pF in steps of 0.5 pF.

WRF_XTAL_XOP

27 pF External resistor and programmableinternal resistor value is determinedby crystal drive level.

0.4 pF
Programmable internal series resistor is from 50 ohms to 500 ohms
in steps of 50 ohms. Boot‐up ROM value is 50 ohms.

Note: A reference schematic is available for further details. Contact your Broadcom FAE.
A fractional-N synthesizer in the CYW43907 generates the radio frequencies, clocks, and data/packet timing, enabling it to operateusing a wide selection of frequency references.
The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed inTable 4.
Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.

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3.2 External Frequency Reference
An alternate crystal to the external precision frequency reference can be used, provided that it meets the phase noise requirements
listed in Table 4.
If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shownin Figure 6. The internal clock buffer connected to this pin will be turned off when the CYW43907 goes into Sleep Mode. When theclock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin.
Figure 6. Recommended Circuit to Use With an External Reference Clock1000 pF
ReferenceClock

WRF_XTAL_XON
NC

WRF_XTAL_XOP

Table 4. Crystal Oscillator and External Clock—Requirements and Performance
Parameter

Frequency

2.4 GHz and 5 GHz bands:
IEEE 802.11a/b/g/n operation

Frequency tolerance over the
lifetime of the equipment,
Without trimming
including temperaturec

External Frequency
Referenceb cCrystala

Conditions/Notes

Units

Min.

Typ.

Max.

Min.

Typ.

Max.

–

37.4

–

–

–37.4

–

MHz

–20

–

20

–20

–

20

ppm

Crystal load capacitance

–

–

16

–

–

–

–

pF

ESR

–

–

–

60

–

–

–

Ω

Drive level

External crystal must be able to tolerate
this drive level.

200

–

–

–

–

–

µW

Input impedance(WRF_XTAL_XON)

Resistive

–

–

–

30k

100k

–

Ω

Capacitive

–

–

7.5

–

–

7.5

pF

WRF_XTAL_XON
Input low level

DC-coupled digital signal

–

–

–

0

–

0.2

V

WRF_XTAL_XON
Input high level

DC-coupled digital signal

–

–

–

1.0

–

1.26

V

WRF_XTAL_XON
input voltage (see Figure 6)

IEEE 802.11a/b/g operation only

–

–

–

400

–

1200

mVp-p

WRF_XTAL_XON
input voltage(see Figure 6)

IEEE 802.11n AC-coupled analog input

–

–

–

1

–

–

Vp-p

Duty cycle

37.4 MHz clock

–

–

–

40

50

60

%

Phase noised(IEEE 802.11b/g)

37.4 MHz clock at 10 kHz offset

–

–

–

–

–

–129

dBc/Hz37.4 MHz clock at 100 kHz offset

–

–

–

–

–

–136

dBc/HzPhase noised(IEEE 802.11a)

37.4 MHz clock at 10 kHz offset

–

–

–

–

–

–137

dBc/Hz37.4 MHz clock at 100 kHz offset

–

–

–

–

–

–144

dBc/HzPhase noised(IEEE 802.11n, 2.4 GHz)

37.4 MHz clock at 10 kHz offset

–

–

–

–

–

–134

dBc/Hz37.4 MHz clock at 100 kHz offset

–

–

–

–

–

–141

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Table 4. Crystal Oscillator and External Clock—Requirements and Performance (Cont.)
Parameter
Phase noised(IEEE 802.11n, 5 GHz)

External Frequency
Referenceb cCrystala

Conditions/Notes

Units

Min.

Typ.

Max.

Min.

Typ.

Max.

37.4 MHz clock at 10 kHz offset

–

–

–

–

–

–142

dBc/Hz37.4 MHz clock at 100 kHz offset

–

–

–

–

–

–149

dBc/Hza. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP.
b. See “External Frequency Reference” for alternative connection methods.
c. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications.
d. Assumes that external clock has a flat phase noise response above 100 kHz.

3.3 External 32.768 kHz Low-Power Oscillator (LPO)The CYW43907 uses a secondary low frequency clock for low-power-mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,voltage, and temperature, which is adequate for some applications. However, one tradeoff caused by this wide LPO tolerance is asmall current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed inTable 5.
Table 5. External 32.768 kHz Sleep Clock Specifications
Parameter

LPO ClockUnits

32.768kHz

Frequency accuracy

±200

ppm

Duty cycle

30–70

%

Nominal input frequency

Input signal amplitude

200–3300

mV, p-p

Square-wave or sine-wave–

Input impedancea>100 k<5Ω
pF

Clock jitter (during initial start-up)<10,000

ppm

Signal typea. When power is applied or switched OFF.

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4. Applications Subsystem
4.1 Overview
The Applications subsystem contains the general use CPU, memory, the standalone DMA core, the Cryptography core, and the
majority of the external interfaces.

4.2 Applications CPU and Memory Subsystem
This subsystem has an integrated 32-bit Arm® Cortex®-R4 processor with an internal 32 KB D-cache and an internal 32 KB I-cache.
The Arm® Cortex®-R4 is a low-power processor that features a low gate count, low interrupt latency, and low-cost debugging capabilities. It is intended for deeply embedded applications that require fast interrupt response features. The Arm® Cortex®-R4 implements
the Arm® v7-R architecture and supports the Thumb-2 instruction set.
At 0.19 µW/MHz, the Cortex®-R4 is the most power efficient general-purpose microprocessor available, outperforming 8 and 16-bit
devices on a MIPS/µW basis. It also supports integrated Sleep Modes.
Using multiple technologies to reduce cost, the Arm® Cortex®-R enables improved memory utilization, reduced pin overhead, andreduced silicon area. It also has extensive debugging features, including real-time tracing of program execution.
On-chip memory for the CPU includes 2 MB SRAM, 640 KB ROM, and an 8 KB RAM powered independently of the application
subsystem.

4.3 Memory-to-Memory DMA (M2MDMA)CoreThe CYW43907 M2MDMA engine contains eight DMA channel pairs, each containing one transmit/pull engine and one receive/pushengine.
The DMA engine provides general purpose data movement between memories that can be on the device, attached directly to thedevice, or accessed through a Host Interface. The transmit/pull engine reads data from the source memory and immediately passes
it to the paired receive/push engine, which proceeds to write it to the destination memory. Multiple masters can program the individual
channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters.

4.4 Cryptography Core
This core provides general purpose data movement between memories, which may be either on the device, attached directly to thedevice, or accessed through a Host Interface. The transmit/pull engine reads data from the source memory and passes it immediately
to the paired receive/push engine that proceeds to write it to the destination memory. Multiple masters may program the individual
channels, and multiple interrupts are provided so that interrupts for different channels can be routed separately to different masters.
The cryptography block provides a hardware accelerator for enciphering and deciphering data that has undergone processing using
standards-based encryption algorithms. The cryptography block includes the following primary features:■

Encryption and hash engines that support single pass AUTH-ENC or ENC-AUTH processing.

■A scalable AES module that supports CBC, ECB, CTR, CFB, OFB, and XTS encryption with 128, 192, and 256-bit key sizes.

■

A scalable DES module that supports DES and 3DES in ECB and CBC modes.

■

An RC4 stream cipher module that supports state initialization, state update, and key-stream generation.

■

MD5, SHA1, SHA224, and SHA256 engines that support pure hash or HMAC operations.

■

A built-in 512-byte key cache for locally protected key storage.

OTP memory is used to store authentication keys.

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5. Applications Subsystem External Interfaces
5.1 Ethernet MAC Controller (MII/RMII)The CYW43907 integrates a high performance Ethernet MAC controller. The controller interfaces to an external PHY either over aMedia Independent Interface (MII) or a Reduced Media Independent Interface (RMII). The controller can transmit and receive data at
10 Mbps and 100 Mbps.

5.2 GPIO
There are 17 GPIO pins available on the CYW43907. The GPIOs can be used to connect to various external devices.
Upon power-up and reset, the pins are in tristate. Subsequently, they can be programmed to be either input/output pins via the GPIO
control register. In addition, the GPIO pins can be assigned to various other functions.
Apart from other functions, GPIOs are used to set bootstrap options and use the JTAG Interface for debugging during softwaredevelopment.

5.3 CSCThe CYW43907 has two CSC2 master interfaces for external communication with codecs, DACs, NVRAM, etc. The I/O pads can be
configured as pull-ups or it can be installed on the reference design to support a multimaster on an open drain bus.
The I2C0 CSC Master Interface can support repeated start, however it does not support clock stretching. The I2C1 CSC Master
Interface does not support repeated start or clock stretching. The CSC Master can support a maximum clock frequency of 400kHz.
If clock stretching is required a bit banging driver is recommended. Cypress's WICED® SDK provides and example of such a bit
banging I2C driver. Note that only I2C0 mentioned in Table 10 is multiplexed with GPIOs and supports bit banging. I2C1 is not
multiplexed with GPIOs and therefore cannot support bit banging.

5.4 I2SThe CYW43907 has two I2S interfaces for audio signal data. The two interfaces are identical. Each interface supports both masterand slave modes.
The following signals apply to the first I2S Interface:■

I2S bit clock: I2S_SCLK0 (sometimes referred to as I2S_BITCLK)■I2S word select: I2S_LRCK0 (sometimes referred to as I2S_WS)■

I2S serial data out: I2S_SDATAO0■

I2S serial data in: I2S_SDATAI0■

I2S Master clock: I2S_MCLK0

The following signals apply to the second I2S Interface:■

I2S bit clock: I2S_SCLK1 (sometimes referred to as I2S_BITCLK)■I2S word select: I2S_LRCK1 (sometimes referred to as I2S_WS)■

I2S serial data out: I2S_SDATAO1■

I2S serial data in: I2S_SDATAI1■
2

I2S Master clock: I2S_MCLK1I S_SDATAO0 and I2S_SDATAO1 are outputs.
I2S_MCLK, I2S_SCLK and I2S_LRCLK can be configured as either inputs or outputs depending on whether the master clock sourceis on-chip/off-chip and whether the I2S is operating in Master/Slave Mode.
Channel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are supported, and the data is justified so that the MSB of the left-channel
data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one-bit clock cycle
after the I2S_LRCK transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S_LRCK is

2. Cypress Serial Control is an I2C compatible Interface.

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PRELIMINARYCYW43907

low, and right-channel data is transmitted when I2S_LRCK is high. An embedded 128 × 32-bit single-port SRAM for data processing
enhances the performance of the Interface.
An audio PLL generates an internal Master clock (for I2S_MCLK0 and I2S_MCLK1) that provides support for various sampling rates.
Note: In I2S Slave Mode if LRCLK changes on the rising edge of the bit clock, the MSB data bit is set half of a bit cycle after LRCLK.
Table 6 shows the MCLK rates (in MHz) associated with each of the various sample rates. In the table, FS refers to the sample rate
in kHz and typical MCLK rates are shaded.
Table 6. Variable Sample Rate and MCLK Rate Supporta
MCLK Rate (MHz)b

SampleRate (kHz)128 × FS

192 × FS

256 × FS

384 × FS

512 × FS

640 × FS

768 × FS

1152 × FS

8

1.024

1.536

2.048

3.072

4.096

5.12

6.144

9.216

11.0251.41122.11682.82244.23365.64487.056

8.467212.7008

12

1.536

2.304

3.072

4.608

6.144

7.68

9.216

13.824

16

2.048

3.072

4.096

6.144

8.192

10.24

12.28818.43222.05

2.82244.23365.64488.4672

11.2896

14.112

16.934425.4016

24

3.072

4.608

6.144

9.216

12.28815.36

18.43227.648

32

4.096

6.144

8.192

12.28816.38420.48

24.57636.86444.1

5.64488.4672

11.2896

16.9344

22.5792

28.22433.8688

–

48

6.144

9.216

12.28818.43224.57630.72

36.864

–

64

8.192

12.28816.38424.57632.768

–

–

–

88.2

11.2896

16.9344

22.5792

33.8688

–

–

–

–

96

12.28818.43224.57636.864

–

–

–

–

192

24.57636.864

–

–

–

–

–

–

a. All data in the table assumes a crystal frequency of 37.4 MHz.
b. MCLK frequency errors are less than 1 ppb.

For an MCLK specification, see Table 44.

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5.5 JTAG and Arm® Serial Wire Debug
The CYW43907 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG Interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
The CYW43907 also supports Arm® SWD for connecting a JTAG debugger directly to both Arm® Cortex®-R4s. For SWD, thecombination of a clock and a bidirectional signal (on a single pin) provides normal JTAG debug and test functionality. The reduced
pin-count SWD Interface is a high-performance alternative to the JTAG Interface.
Table 7 shows the JTAG_SEL and TAP_SEL states for test and debug function selection. Test and debug function selection is
independent of the debugging Interface (JTAG or SWD) being used.
Table 7. JTAG_SEL and TAP_SEL States for Test and Debug Function Selection
JTAG_SEL StateTAP_SEL State

Test and Debug Function

00JTAG not used.

01

JTAG not used.

1

0

Access the LV tap directly for ATE and bring-up.

1

1

Access either of the Arm® Cortex®-R4’s directly via either the 5-pin JTAG port or
2-pin SWD configuration.

Note: JTAG_SEL is exposed on a dedicated physical pin. TAP_SEL uses the GPIO_8 physical pin.

5.6 Pulse Width Modulation (PWM)
The CYW43907 provides up to six independent PWM channels. The following features apply to the PWM channels:■

Each channel is a square wave generator with a programmable duty cycle.

■

Each channel generates its duty cycle by dividing down the input clock.

■

Both the high and low duration of the duty cycle can be divided down independently by a 16-bit divider register.

■

Each channel can work independently or update simultaneously.

■

Pairs of PWM outputs can be inverted for devices that need a differential output.

■

Continuous or single pulses can be generated.

■

The input clock can either be a high-speed clock from a PLL channel or a lower speed clock at the crystal frequency.

5.7 SDIO 3.0 - Host Mode
The CYW43907 WLAN section supports SDIO v3.0, including the new UHS-I modes:■

DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling).

■

HS: High-speed up to 50 MHz (3.3 V signaling).

■

SDR12: SDR up to 25 MHz (1.8 V signaling).

■

SDR25: SDR up to 50 MHz (1.8 V signaling).

Note: The CYW43907 is backward compatible with SDIO v2.0 devices.
In this mode, the device supports the following features:■

ADMA2.

■

Out-of-band signaling for card detection, write protection, and I/O voltage levels (which are available on GPIOs).

■

Dynamic, specification-compliant shifting from 3.3 V to 1.8 V I/Os.

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5.8 S/PDIF
S/PDIF is a serial audio data transport format used to connect consumer audio devices such as CD players, DVD players, andsurround-sound receivers. Although S/PDIF can be used to transport uncompressed audio formats, the primary use case for the
CYW43907 S/PDIF Interface is to transport multichannel compressed audio for surround-sound applications, especially Dolby Digitaland DTS, to an auxiliary external audio processor.
The CYW43907 can support two S/PDIF interfaces via the I2S_SDATA00 and I2S_SDATA01 pins. Because each S/PDIF Interface
uses an I2S data line, only I2S or S/PDIF functionality can be enabled on each I2S Interface.
Each S/PDIF Interface has the following key requirements:■

S/PDIF transmissions that conform with IEC 60958-1 (receiver not required).

■

Support for linear PCM audio data that conforms with IEC 60948-3.

■

Support for nonlinear PCM audio data that conforms with IEC 60948-3.

■

Support for priority payload formats that include IEC 61937-3 (AC-3) and IEC 61937-5 (DTS).

■

Support for sample rates from 32 kHz to 192 kHz.

■Support for 16, 20, and 24-bit audio samples.

■

Support for only one concurrent compressed audio stream.

5.9 SPI FlashThe SPI Flash Interface supports the following features:■

A SPI-compatible serial bus.

■

An 80 MHz (maximum) clock frequency.

■

Increased throughput to 40 MBps in Quad-mode or upto 10 MBps in single Mode3.

■

Support for either ×1 or ×4 addresses with ×4 data.

■

3-bytes and 4-byte addressing modes.

■

A configurable dummy-cycle count that is programmable from 1 to 15.

■

Programmable instructions output to serial flash.

■

An option to change the sampling edge from rising-edge to falling-edge for read-back data when in high-speed mode.

5.10 UART
A high-speed 4-wire CTS/RTS UART Interface can be enabled by software and has dedicated pins. Provided primarily for debugging
during development, this UART enables the CYW43907 to operate as RS-232 data termination equipment (DTE) for exchanging andmanaging data with other serial devices. It is compatible with the industry standard 16550 UART and provides a FIFO size of 64 × 8
in each direction.
There are two low-speed UART interfaces on the CYW43907. Each functions as a standard 2-wire UART. They are also enabled asalternate functions on GPIOs and can be enabled independently of the 4-wire fast UART.
Note: The high-speed, 4-wire UART Interface is identified as UART0 in this document and in reference schematics. The two lowspeed,2-wire UART interfaces are identified as UART1 and UART2 in this document and in the reference schematics.

3.

Note that the clock needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures. The throughput of the SPI Flash block is therefore
restricted to ~13 MBps for Quad mode and ~3 MBps for single mode.

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5.11 USB 2.0
5.11.1 Overview
The USB 2.0 host controller (HC) and device controller (DC) Interface to a backplane via Advanced eXtensible Interface (AXI) and
Advanced Peripheral Bus (APB). They Interface externally through a USB 2.0 and HSIC interfaces.
Figure 7 shows the topology of the USB 2.0 core.
Figure 7. Topology of the USB 2.0 Core
AXI/APB

USB Device
Controller

APB

USB Host
Controller

UTMI/ULPI
Host/
DeviceSelectUTMI/ULPIMultiplexer

UTMI/ULPI

USB 2.0 PHY
Chip
Boundary
USB I/F

The CYW43907 contains both a USB 2.0 HC and DC. Therefore, it can operate in the host-only, device-only, and dual-role device(DRD) modes. In DRD mode, the CYW43907 can be configured as either the host or a device on the fly but must remain in the samemode until the next boot cycle. The restriction that the host or device mode remains fixed during a boot cycle is what differentiates
DRD from On-The-Go (OTG).
The state of the USB2_DSEL pin sets the mode as either host or device for USB Type A and Type B connectors. For a USB MicroAB connector, the USB2_DSEL pin sets the mode as either host or device while the overall mode is Dual Role Device (DRD).

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Table 8 shows the supported application cases. The table also shows the USB mode and PHY type, the connector type, and theUSB2_DSEL state associated with each case.
Table 8. USB Application Cases
Application Case Shorthand

Mode

PHY

USB2_DSEL

DRD-Host

USB 2.0

0

DRD-Device

USB 2.01

Type: Micro-AB
Connect USB2_DSEL to the ID pin of the Micro-AB
receptacle.

Host + USB 2.0 PHY

Host

USB 2.00Type A

Device + USB2.0 PHY

DeviceUSB 2.01Type B

DRD + USB 2.0 PHY

Connector Information

Note: In host mode, the USB core can process an overcurrent event and take the appropriate action. The overcurrent event is input
into the CYW43907 via the alternative mode pin USB20H_CTL.
Figure 8 shows the CYW43907 configured to operate in DRD mode with a USB 2.0 PHY.
Figure 8. CYW43907 Configured as a DRD + USB 2.0 PHY
AXI/APB

PPC
EHC/OHC

DWDC/DMA

OVC
UTMI

UTMI

Multiplexer
UTMI
Demulitplexer
VBUS

UTMI
USB 2.0 PHY
D+/D–

5V

VBUS
SwitchUSB 2.0
Micro-AB ID
Connector

USB2_DSEL

Chip Boundary
EHC:
OHC:
OVC:
PPC:
UTMI:

Enhanced Host Controller
Open Host Controller
Overcurrent indication
Port power control
USB

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USB 2.0
Hostor Device

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The following information pertains to Figure 8:■

The Micro-AB receptacle connects the CYW43907 to an external host/device.

■

The Micro-AB connector ID pin is connected to the CYW43907 USB2_DSEL pin.

■

The CYW43907 GPIO_9 pin is high in order to select the USB 2.0 PHY.

■

The PPC line indicates whether the USB 2.0 host controller supports port power control.

■

The OVC line is used to indicate an overcurrent condition.

■

Standard differential signal lines D+ (DP) and D– (DM) are used for the USB 2.0 Interface

5.11.2 USB 2.0 Features
The following capabilities and features apply to the CYW43907 USB 2.0 PHY:■

Compliant with the UTMI+ level 2 specification.

■

Functions as a host/device.

■

Supports high speed (HS) at 480 Mbps, full speed (FS) at 12 Mbps, and low speed (LS) at 1.5 Mbps.

■

Integrates pull-up (PU) and pull-down (PD) terminations with resistor support (per an engineering change notice to the USB 2.0
specification).

■Contains a calibrated 45Ω termination for HS TX/RX.

■

Uses half-duplex differential data signaling with Non-return-to-zero (NRZI) encoding.

■

Recovers the data and clock from the data stream.

■

Integrates a 960 MHz PLL with a single-ended reference clock.

■Supports host resume and remote wake-up.

■

Supports L1 and L2 suspend, shallow sleep, and Link-Power Management (LPM).

■

Supports legacy USB 1.1 devices through a SPI.

■

Supports dribble bits.

■

Supports LS keep-alive packets (LS EOP).

■

Support HS keep-alive packets (HS SYNC).

■

Contains an onboard BERT for self-testing (PRBS and fixed patterns).

■

Dissipates a maximum power of 150 mW for 1-port in loop-back mode.

■

Contains an integrated 3.3V to 1.2V LDO.

■

Uses 3.3V.

5.12 SPICYW43907 contains two SPI blocks. These blocks support a fixed SPI Mode (CPOL = 0, CPHA = 0) and 8-bit data read/write.
CPOL = 0: Clock idles at 0, and each cycle consists of a pulse of 1. The leading edge is a rising edge, and the trailing edge is a fallingedge. CPHA = 0: The "OUT" side changes the data on the trailing edge of the preceding clock cycle, while the "IN" side captures thedata on (or shortly after) the leading edge of the clock cycle.
The SPI hardware blocks support a hold time of 25ns and a maximum clock frequency of 40MHz.
If a SPI Slave does not support the above mode or requires a hold time greater than 25ns, a bit banging software SPI driver should
be used. Cypress's WICED® SDK provides and example of such a driver. Note that the maximum SPI frequency support by a software
SPI driver is much lower than 40 MHz.
SPI0 mentioned in Table 10 is multiplexed with GPIOs and can therefore support a bit banging based software SPI driver. SPI1 is not
multiplexed with GPIOs and cannot support a bit banging based software SPI driver

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6. Global Functions
6.1 External Coexistence Interface
An external handshake Interface is available to enable signaling between the device and an external colocated wireless device, suchas Bluetooth, to manage wireless medium sharing for optimum performance.
Figure 9 shows the coexistence interface.
Figure 9. Cypress 2-Wire External Coexistence Interface

CYW54907
WLAN

GCI

BT\IC
SECI_OUTUART_IN

SECI_IN

UART_OUTNOTES:
 SECI_OUT/BT_TXD and SECI_IN/BT_RXD are multiplexed on the GPIOs.
 The 2‐wire coexistence interface is intended for future compatibility with the BT SIG 2‐wire interface that is being standardized for Core 4.1.

Note: SECI UART is the same as UART2, one of the low-speed UART Interfaces mentioned in section 5.10 and in the reference
schematics.

6.2 OTP Memory
Various hardware configuration parameters can be stored in an internal 6144-bit (768 bytes) OTP memory that is read by system
software after a device reset. In addition, customer-specific parameters, including the system vendor ID and MAC address can be
stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP memory device is 0. After any bit is programmed to 1, it cannot be reprogrammed
to 0. The entire OTP memory array can be programmed in a single write-cycle using a utility provided with the Cypress WLAN
manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits that are
still in the 0 state can be altered during each programming cycle.
Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file. The nvram.txt file isprovided with the reference board design package.

6.3 Hibernation Block
The Hibernation (HIB) block is a self-contained power domain that can be used to completely shutdown the rest of the CYW43907.
This optional block uses the HIB_REG_ON_OUT pin to drive the REG_ON pin. Therefore, for the HIB block to work as designed, the
HIB_REG_ON_OUT pin must be connected to the REG_ON pin. To use the HIB block, software programs the HIB block with a wakecount and then asserts a signal indicating that the chip should be put into hibernation. After assertion, the HIB block drives
HIB_REG_ON_OUT low for the number of 32 kHz clock cycles programmed as the wake count. After the wake-count timer expires,
HIB_REG_ON_OUT is driven high. Other than the logic state of the HIB block, no state is saved in the CYW43907 during hibernation.

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PRELIMINARYCYW43907

6.4 System Boot Sequence
The following general sequence occurs after a CYW43907 is powered on:
1. Either REG_ON or HIB_REG_ON_IN is asserted.
Note: For HIB_REG_ON_IN to function as intended, HIB_REG_ON_OUT must be connected to REG_ON.
2. The core LDO (CLDO) and LDO3P3 outputs stabilize.
3. The OTP memory bits are used to initialize various functions, such as PMU trimming, package selection, memory size selection,and so on.
4. The APP and WLAN cores are powered up.
5. The XTAL is powered up.
6. The APP and WLAN CPU bootup sequences start.

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PRELIMINARYCYW43907

7. Wireless LAN Subsystem
7.1 WLAN CPU and Memory Subsystem
The CYW43907 WLAN section includes an integrated 32-bit Arm® Cortex®-R4 processor with internal RAM and ROM. The Arm®
Cortex®-R4 is a low-power processor that features a low gate count, a small interrupt latency, and low-cost debug capabilities. It is
intended for deeply embedded applications that require fast interrupt response features. Delivering more than a 30% performancegain over ARM7TDMI, the Arm® Cortex®-R4 implements the Arm® v7-R architecture with support for the Thumb-2 instruction set.
At 0.19 µW/MHz, the Cortex®-R4 is the most power efficient general-purpose microprocessor available, outperforming 8 and 16-bit
devices on MIPS/µW. It also supports integrated sleep modes.
On-chip memory for this CPU includes 576 KB of SRAM and 448 KB of ROM.

7.2 IEEE 802.11n MAC
The CYW43907 WLAN MAC is designed to support high-throughput operation with low power consumption. It does so withoutcompromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several
power-saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing
synchronization. The architecture diagram of the MAC is shown in Figure 10.
The following sections provide an overview of the important MAC modules.
Figure 10. WLAN MAC Architecture

Embedded CPU Interface
Host Registers, DMA Engines

TX‐FIFO
32 KB

PMQ

RX‐FIFO
10 KB

PSM

PSM
UCODE
MemoryIFS
Backoff, BTCXWEP
TKIP, AES, WAPI

TSF

SHM
BUS

IHR
NAV

EXT‐ IHR

BUS
TXE
TX A‐MPDU

RXE
RX A‐MPDU

Shared Memory
6 KB

MAC‐PHY Interface

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PRELIMINARYCYW43907

The CYW43907 WLAN MAC supports features specified in the IEEE 802.11 base standard and amended by IEEE 802.11n. The key
MAC features include:■

Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT).

■Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP), and multiphase PSMP
operation.

■

Support for immediate ACK and block-ACK policies.

■

Interframe space timing support, including RIFS.

■

Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.

■

Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.

■

Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)
generation in hardware.

■

Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.

■

Support for coexistence with Bluetooth and other external radios.

■

Programmable independent basic service set (IBSS) or infrastructure basic service set functionality.

■

Statistics counters for MIB support.

7.2.1 Programmable State Machine (PSM)
PSM is a microcoded engine that provides most of the low-level control to the hardware in order to implement the IEEE 802.11
specification. It is a microcontroller that is highly optimized for flow-control operations, which are predominant in implementations ofcommunication protocols. The instruction set and fundamental operations are simple and general, allowing algorithms to be optimized
very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications.
The PSM fetches instructions from microcode memory. It uses the shared memory to obtain operands for instructions, as a data store,
and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad memory(similar to a register bank) to store frequently accessed and temporary variables.
The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs
are colocated with the hardware functions they control and are accessed by the PSM via the IHR bus.
The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal,or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction
literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.
There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points
in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition
signals are available to the PSM without polling the IHRs) or on the results of ALU operations.
7.2.2 Wired Equivalent Privacy (WEP)The WEP engine encapsulates all the hardware accelerators to perform encryption and decryption as well as MIC computation andverification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP.
The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to use. It supplies thekeys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and computethe MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames.

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PRELIMINARYCYW43907

7.2.3 TXEThe TXE constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO.
It interfaces with the WEP Module to encrypt frames and transfers the frames across the MAC-PHY Interface at the appropriate time
determined by the channel-access mechanisms.
The data received from the DMA engines are stored in transmit FIFOs. The MAC has multiple logical queues to support traffic streams
that have different QoS priority requirements. The PSM uses the channel access information from the IFS Module to schedule a queue
from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise
timing trigger received from the IFS Module.
The TXE Module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware
module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.
7.2.4 Receive engine (RXE)The RXE constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RXFIFO.
It transfers bytes across the MAC-PHY Interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored
in the RXFIFO.
The RXE Module contains filters that are programmed by the PSM to accept/filter frames based on several criteria such as receiveraddress, BSSID, and certain frame types.
The RXE Module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate
them into component MPDUS.
7.2.5 Interframe Spacing (IFS)The IFS Module contains the timers required to determine interframe-space timing including RIFS timing. It also contains multiple
backoff engines required to support prioritized access to the medium as specified by WMM.
The interframe-spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers
provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform
transmit frame-bursting (RIFS/SIFS separated, as within a TXOP).
The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or
pause the backoff counters. When the backoff counters reach 0, the TXE gets notified so that it may commence frame transmission.
In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies
provided by the PSM.
The IFS Module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE powersave mode. In this mode, the MAC is in a suspended state with its clock turned OFF. A sleep timer, whose count value is initialized
by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. When the timer
expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the
TSF is synchronized to the network.
The IFS Module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.
7.2.6 Timing Synchronization Function (TSF)
The TSF Module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer
hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in orderto maintain synchronization with the network.
The TSF Module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink
transmission times used in PSMP.
7.2.7 Network Allocation Vector (NAV)The NAV Timer Module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This
ensures that the MAC complies with the protection mechanisms specified in the standard.
The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.
This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.

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PRELIMINARYCYW43907

7.2.8 MAC-PHY Interface
The MAC-PHY Interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is anprogramming interface that can be controlled either by the host or the PSM to configure and control the PHY.

7.3 IEEE 802.11™ a/b/g/n PHY
The CYW43907 WLAN digital PHY complies with IEEE 802.11a/b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 150 Mbps for low-power, high-performance, handheld applications.
The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates
optimized implementations of filters, fast Fourier transform (FFT), and Viterbi-decoder algorithms. Efficient algorithms have been
designed to achieve maximum throughput and reliability, including algorithms for carrier sensing and rejection, frequency/phase/timing
acquisition and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator.
The PHY carrier-sensing algorithm provides high throughput for IEEE 802.11b/g hybrid networks with Bluetooth coexistence.
The key PHY features include:■

Programmable data rates from MCS0–7 in 20 MHz and 40 MHz channels.

■

Support for optional short GI and Green Field modes in TX and RX.

■

All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive
direction.

■

Support for IEEE 802.11h/k for worldwide operation.

■

Advanced algorithms for low power consumption and enhanced sensitivity, range, and reliability.

■

Algorithms to improve performance in the presence of externally received Bluetooth signals.

■

An automatic gain control scheme for blocking and nonblocking cellular applications.

■

Closed loop transmit power control.

■

Digital RF chip calibration algorithms to handle CMOS RF chip Process, Voltage, and Temperature (PVT) variations.

■On-the-fly channel frequency and transmit power selection.

■

Per-packet RX antenna diversity.

■

Available per-packet channel quality and signal-strength measurements.

■

Compliance with FCC and other worldwide regulatory requirements.
Figure 11. WLAN PHY Block Diagram
Filte rs
an d
R ad io
Com p

A FE
an d
R ad io

R ad ioC o n tro l
B lo ck

Com m onLo gicB lo ck
Filte rs
an d
R ad ioCom p

C C K/D SSS
D e m o d u late

Freq u e n cy
an d Tim in g
Syn chC arrier Sen se,
A G C , an d R x
FSM

Tx FSM

O FD MD e m o d u lateB u ffe rs

V iterb i D e co d e r

D e scram b lean d D e fram e

FFT/IFFTM AC
In te rface

M o d u latio n
an d C o d in g
Fram e an dScram b le

PA Com p

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PRELIMINARYCYW43907

8. WLAN Radio Subsystem
The CYW43907 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz
Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operatingin the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering,mixing, and gain control functions.
Ten RF control signals are available to drive external RF switches. In addition, these control signals can be used to support optional
external 5 GHz band power and low-noise amplifiers. See the reference board schematics for more information.
A block diagram of the radio subsystem is shown in Figure 12. Note that integrated on-chip baluns (not shown) convert the fully
differential transmit and receive paths to single-ended signal pins.

8.1 Receiver Path
The CYW43907 has a wide dynamic range, direct conversion receiver that employs high-order on-chip channel filtering to ensure
reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. The 2.4 GHz and 5 GHz paths each have a dedicatedon-chip low-noise amplifier (LNA).

8.2 Transmit Path
Baseband data is modulated and up converted to the 2.4 GHz ISM or 5 GHz U-NII bands, respectively. Linear on-chip power amplifiersdeliver high output powers while meeting IEEE 802.11a/b/g/n specifications without the need for external PAs. When using the internalPA, which is required in the 2.4 GHz band and optional in the 5 GHz band, closed-loop output power control is completely integrated.

8.3 Calibration
The CYW43907 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations
across components. These calibration routines are performed periodically during the course of normal radio operation. Examples ofsome of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance and local
oscillator feed-through (LOFT) calibration for carrier leakage reduction. In addition, I/Q calibration and VCO calibration are performed
on-chip. No per-board calibration is required during manufacturing testing. This helps to minimize the test time and cost in largevolume production environments.
Figure 12. Radio Functional Block Diagram
W L T X 2 .4 G H z M ix e r

TX M odeS w it c h

W L DACW L PAW L TXLPFW L DACW L A ‐P A

W L A ‐P A D

W L TXLPFW L T X 5 G H z M ix e r
W L R X 5 G H z M ix e r

W LA N B B

V o lt a g e
R e g u la t o r s

W L ADCW L A ‐L N A 1 1

W L A ‐L N A 1 2

W L R XLPF

W L ADCTX M odeS w it c h

W L ‐G ‐L N A 1 1

W L G ‐L N A 1 2

W L R XLPFW L R X 2 .4 G H z M ix e r

W L 5 GHz TX
W L 5 GHz RX
W L 2 .4 G H z T X
W L 2 .4 G H z R X

W L LO G ENW L PLL
XON
Sh a re d X O

LP O /E xt LP O /R C A L

Document Number: 002-14829 Rev. *L

XOPPage 29 of 94

PRELIMINARYCYW43907

9. Pinout and Signal Descriptions
Figure 13 shows the bump map of the WLCSP package.
Figure 13. 316-Bump WLCSP Map

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PRELIMINARYCYW43907

9.1 Bump List
Table 9 contains the WLCSP bump names.
Table 9. WLCSP Bump Names
Bump

Name

Bump

Name

1

NO_CONNECT

40

VSSC

2

NO_CONNECT

41

NO_CONNECT

3

NO_CONNECT

42

VSSC

4

NO_CONNECT

43

NO_CONNECT

5

NO_CONNECT

44

NO_CONNECT

6

VSSC

45

NO_CONNECT

7

NO_CONNECT

46

NO_CONNECT

8

NO_CONNECT

47

NO_CONNECT

9

NO_CONNECT

48

NO_CONNECT

10

NO_CONNECT

49

NO_CONNECT

11

NO_CONNECT

50

VSSC

12

NO_CONNECT

51

NO_CONNECT

13

NO_CONNECT

52

VSSC

14

VSSC

53

VSSC

15

VSSC

54

NO_CONNECT

16

NO_CONNECT

55

NO_CONNECT

17

NO_CONNECT

56

VSSC

18

NO_CONNECT

57

VSSC

19

NO_CONNECT

58

VSSC

20

NO_CONNECT

59

VSSC

21

VSSC

60

VSSC

22

VSSC

61

NO_CONNECT

23

NO_CONNECT

62

NO_CONNECT

24

NO_CONNECT

63

NO_CONNECT

25

VSSC

64

NO_CONNECT

26

NO_CONNECT

65

NO_CONNECT

27

NO_CONNECT

66

NO_CONNECT

28

NO_CONNECT

67

NO_CONNECT

29

NO_CONNECT

68

NO_CONNECT

30

NO_CONNECT

69

NO_CONNECT

31

NO_CONNECT

70

NO_CONNECT

32

NO_CONNECT71

SFL_IO133

NO_CONNECT72

SFL_IO334

NO_CONNECT73

SFL_IO0

35

VSSC

74

SFL_CS

36

NO_CONNECT75

SFL_IO2

37

NO_CONNECT

76

SPI0_CLK38

NO_CONNECT77

SFL_CLK

39

VSSC

78

SPI0_MISO

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PRELIMINARY

Bump
79

Name

CYW43907

Bump

Name

VSSC

121

VOUT_CLDO

80

SPI1_CS

122

SR_VDDBAT5V

81

SPI0_SISO

123

SR_PVSS82

SPI0_CS124

SR_PVSS83

SPI1_CLK125

SR_VDDBAT5V

84

SPI1_MISO126

VOUT_CLDO85

UART0_CTS

127

LDO_VDD1P5

86

SPI1_SISO128

LDO_VDDBAT5V

87

UART0_TXD

129

LDO_VDDBAT5V

88

UART0_RXD

130

GPIO_1489

I2C1_CLK131

GPIO_1390

I2C1_SDATA

132

GPIO_591

UART0_RTS

133

GPIO_692

I2C0_CLK134

GPIO_893

I2C0_SDATA

135

VSSC

94

GPIO_9136

GPIO_495

GPIO_7137

GPIO_16

96

VSSC

138

VDDC

97

PMU_AVSS139

GPIO_298

SR_VLX

140

GPIO_1199

SR_VLX

141

GPIO_0100

REG_ON142

GPIO_1

101

SR_VLX

143

GPIO_12102

SR_VLX

144

GPIO_3

103

VOUT_CLDO_SENSE

145

GPIO_15

104

VSSC

146

GPIO_10

105

VDDIO

147

SDIO_DATA_3

106

VOUT_LNLDO

148

SDIO_DATA_2

107

VOUT_BBPLLOUT

149

SDIO_DATA_1

108

SR_VDDBAT5V

150

SDIO_DATA_0

109

SR_VLX151

SDIO_CMD

110

SR_PVSS152

SDIO_CLK111

SR_PVSS

153

I2S_MCLK0112

SR_VLX154

I2S_SCLK0113

SR_VDDBAT5V

155

I2S_SDATAO1

114

VOUT_CLDO

156

I2S_SDATAI1

115

LDO_VDD1P5

157

VDDIO_I2S

116

LDO_VDD1P5

158

I2S_MCLK1

117

VOUT_3P3_SENSE

159

VDDIO_I2S

118

VOUT_3P3

160

I2S_SCLK1

119

VOUT_3P3161

I2S_SDATAO0120

LDO_VDD1P5

162

I2S_LRCLK1

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PRELIMINARY

Bump
163

Name

CYW43907

Bump

Name

I2S_LRCLK0205

RF_SW_CTRL_3

164

I2S_SDATAI0206

RF_SW_CTRL_4

165

USB2_DSEL

207

RF_SW_CTRL_5

166

USB2_AVDD33

208

VDDIO_RF

167

USB2_DP

209

VSSC

168

USB2_AVSS

210

VSSC

169

USB2_RREF

211

RF_SW_CTRL_2

170

USB2_DM

212

AVSS

171

USB2_DVSS213

LPO_XTAL_IN

172

USB2_AVSSBG

214

RF_SW_CTRL_1

173

USB2_AVDD33LDO

215

RF_SW_CTRL_0

174

VDDIO

216

VDDC

175

USB2_MONCDR

217

VDDC

176

USB2_AVDD33IO

218

WRF_AFE_GND

177

VSSC

219

WRF_AFE_GND

178

VSSC

220

WRF_XTAL_VDD1P2

179

NO_CONNECT221

WRF_XTAL_VDD1P35

180

NO_CONNECT222

WRF_XTAL_XOP

181

NO_CONNECT223

WRF_SYNTH_VDD3P3

182

VSSC

224

WRF_AFE_GND

183

VSSC

225

WRF_AFE_GND

184

USB2_MONPLL

226

WRF_XTAL_XON

185

PWM0

227

WRF_PMU_VDD1P35

186

PWM1

228

WRF_PMU_VDD1P35

187

PWM4

229

WRF_SYNTH_VDD1P2

188

PWM5

230

WRF_AFE_GND

189

PWM3

231

WRF_AFE_VDD1P35

190

PWM2

232

WRF_AFE_GND

191

AVSS_AUDIO233

WRF_RFIN_5G

192

AVDD1P2_AUDIO234

WRF_AFE_GND

193

JTAG_SEL235

WRF_EXT_TSSIA194

CLK_REQ236

WRF_AFE_GND

195

VDDIO

237

WRF_GPAIO_OUT

196

RF_SW_CTRL_9

238

WRF_AFE_GND

197

VSSC

239

WRF_PAOUT_5G

198

SRSTN

240

WRF_PA_VDD3P3

199

VDDIO_RF241

WRF_PA_VDD3P3

200

RF_SW_CTRL_8

242

WRF_AFE_GND

201

RF_SW_CTRL_7

243

WRF_AFE_GND

202

RF_SW_CTRL_6

244

WRF_TXMIX_VDD

203

OTP_VDD3P3

245

WRF_PAOUT_2G

204

AVDD1P2

246

WRF_RFIN_2G

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Page 33 of 94

PRELIMINARY

Bump

Name

CYW43907

Bump

Name

247

WRF_AFE_GND

289

VDDC

248

VSSC

290

VSSC

249

HIB_XTALIN

291

VSSC

250

HIB_XTALOUT

292

VSSC

251

VSSC

293

RMII_G_COL

252

VDDC

294

RMII_G_TXC

253

VSSC

295

RMII_G_RXD2

254

VDDC

296

RMII_G_RXD3255

VDDIO_SD

297

RMII_G_RXC

256

VSSC

298

RMII_G_CRS

257

VDDIO

299

RMII_G_RXD1

258

VDDIO

300

RMII_G_TXD2

259

VSSC

301

VSSC

260

VSSC

302

VSSC

261

VDDIO

303

RMII_G_RXD0

262

VSSC

304

RMII_G_TXD0

263

VDDIO

305

VDDIO_RMII

264

VSSC

306

RMII_G_TXEN

265

VSSC

307

VDDIO_RMII

266

VSSC

308

VSSC

267

VDDC

309

VDDC

268

VDDC

310

RMII_MDC

269

VDDIO

311

RMII_G_TXD1

270

HIB_VDDO

312

RMII_G_RXDV

271

VDDC

313

VSSC

272

VSSC

314

VDDC

273

VSSC

315

VSSC

274

VSSC

316

VDDC

275

VDDC

276

VDDC

277

VDDC

278

HIB_REG_ON_OUT

279

HIB_WAKE_B

280

VDDC

281

VDDC

282

HIB_REG_ON_IN

283

HIB_LPO_SELMODE

284

RMII_G_TXD3

285

VDDC

286

VDDC

287

VSSC

288

RMII_MDIO

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PRELIMINARYCYW43907

9.2 Signal Descriptions
Table 10 provides the signal name, type, and description for each CYW43907 bump. The symbols shown under Type indicate pin
directions (I/O = bidirectional, I = input, and O = output) and the internal PU/PD characteristics (PU = weak internal pull-up resistor
and PD = weak internal pull-down resistor), if any.
Table 10. Signal Descriptions
Bump Number

Signal NameType

Description

CSC Interface
92

I2C0_CLKO

CSC master clock.

93

I2C0_SDATA

I/O

CSC serial data

89

I2C1_CLKO

CSC master clock90

I2C1_SDATA

I/O

CSC serial data

222

WRF_XTAL_XOPI

XTAL oscillator input.

226

WRF_XTAL_XONO

XTAL oscillator output.

213

LPO_XTAL_IN

I

External sleep clock input (32.768 kHz).

Clocks249

HIB_XTALIN

I

3.3V 32 kHz crystal input

250

HIB_XTALOUT

O

3.3V 32 kHz crystal output

194

CLK_REQO

Reference clock request

297

RMII_G_RXC

I

MII receive clock

293

RMII_G_COL

I

MII collision detection

298

RMII_G_CRS

I

MII carrier sense

294

RMII_G_TXC

I

MII/RMII transmit clock

MII/RMII304

RMII_G_TXD0O

MII/RMII transmit signal

311

RMII_G_TXD1O

MII/RMII transmit signal

300

RMII_G_TXD2O

MII transmit signal

284

RMII_G_TXD3O

MII transmit signal

303

RMII_G_RXD0I

MII/RMII receive signal

299

RMII_G_RXD1

I

MII/RMII receive signal

295

RMII_G_RXD2

I

MII receive signal

296

RMII_G_RXD3

I

MII receive signal

288

RMII_MDIOI/O

MII/RMII management data

310

RMII_MDCOMII/RMII management clock306

RMII_G_TXENO

MII/RMII transmit enable

312

RMII_G_RXDVI

MII/RMII receive data valid

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

Table 10. Signal Descriptions (Cont.)
Bump Number

Signal NameType

Description

GPIO Interface (WLAN)141

GPIO_0

I/O

142

GPIO_1

I/O

139

GPIO_2

I/O

144

GPIO_3

I/O

136

GPIO_4

I/O

132

GPIO_5

I/O

133

GPIO_6

I/O

95

GPIO_7

I/O

134

GPIO_8I/O

94

GPIO_9I/O

146

GPIO_10I/O

140

GPIO_11

I/O

143

GPIO_12

I/O

131

GPIO_13I/O

130GPIO_14

I/O

145

GPIO_15

I/O

137

GPIO_16

I/O

Programmable GPIO pins.

Ground218, 219, 224, 225, 230, 232, 234, 236, 238, 242,
WRF_AFE_GND
243, 247

GND

AFE ground

6, 14, 15, 21, 22, 25, 35, 39, 40, 42, 50, 52, 53, 56–
60, 79, 96, 104, 135, 177, 178, 182, 183, 197, 209,
VSSC
210, 248, 251, 253, 256, 259, 260, 262, 264–266,
272–274, 287, 290–292, 301, 302, 308, 313, 315

GND

Core ground for WLAN and APP sections

110, 111, 123, 124

SR_PVSS

GND

Power ground97

PMU_AVSS

GND

Quiet ground

212

AVSS

GND

Baseband PLL ground

191

AVSS_AUDIO

GND

AUDIO PLL ground168

USB2_AVSS

GND

USB 2.0 analog ground172

USB2_AVSSBG

GND

USB 2.0 analog ground171

USB2_DVSS

GND

USB 2.0 digital ground

Hibernation Block, Power Down/Power Up, and Reset

100

282

Document Number: 002-14829 Rev. *L

REG_ONHIB_REG_ON_IN

I

Used by PMU to power up or power down
the internal CYW43907 regulators used by
the WLAN and APP sections. Also, whendeasserted, this pin holds the WLAN and
APP sections in reset. This pin has aninternal 200 kΩ PD resistor that is enabled
by default. It can be disabled throughprogramming.

I

Used by the hibernation block to power up
or power down the internal CYW43907
regulators. For applications that use thehibernation block, HIB_REG_ON_OUT
must connect to REG_ON. Also, whendeasserted, this pin holds the WLAN and
APP sections in reset.

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Table 10. Signal Descriptions (Cont.)
Bump Number

Signal NameType

Description

278

HIB_REG_ON_OUTO

REG_ON output signal generated by thehibernation block.

279

HIB_WAKE_B

I

Wake up chip from hibernation mode.

283

HIB_LPO_SELMODE

I

Select precise or coarse 32 kHz clock.

198

SRSTN

I

System reset. This active-low signal resets
the backplanes.

153

I2S_MCLK0

I/O

Master clock

154

I2S_SCLK0

I/O

Serial clock

163

I2S_LRCLK0

I/O

Left- Right (LR) clock

164

I2S_SDATAI0I

I2S data input

161

I2S_SDATAO0O

I2S data output

158

I2S_MCLK1

I/O

Master clock

160

I2S_SCLK1

I/O

Serial clock

162

I2S_LRCLK1

I/O

LR clock

156

I2S_SDATAI1I

I2S data input

155

I2S_SDATAO1O

I2S data output

193

JTAG_SELI

JTAG select. This pin must be connected to
ground if the JTAG Interface is not used.

–

No connect

I2S Interface

JTAG Interface

No Connects
1–5, 7–13, 16–20, 23, 24, 26–34, 36–38, 41, 43–
NO_CONNECT
49, 51, 54, 55, 61–70, 179–181
Power supplies (Miscellaneous)203

OTP_VDD3P3

138, 216, 217, 252, 254, 267, 268, 271, 275–277,
VDDC
280, 281, 285, 286, 289, 309, 314, 316
105, 174, 195, 257, 258, 261, 263, 269

VDDIO

PWR

OTP 3.3V supply

PWR

1.2V core supply for WLAN

PWR

I/O supply

199, 208

VDDIO_RFPWR

I/O supply for RF switch control pads (3.3V).

157, 159

VDDIO_I2S

PWR

I/O supply for I2S

305, 307

VDDIO_RMII

PWR

I/O supply for RMII255

VDDIO_SD

PWR

I/O supply for SDIO270

HIB_VDDO

PWR

I/O supply for hibernation block204

AVDD1P2

PWR

1.2V supply for baseband PLL

192

AVDD1P2_AUDIO

PWR

1.2V supply for audio PLL

166

USB2_AVDD33

PWR

3.3V supply for USB 2.0

173

USB2_AVDD33LDO

PWR

3.3V supply for USB 2.0

176

USB2_AVDD33IO

PWR

3.3V supply for USB 2.0

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

Table 10. Signal Descriptions (Cont.)
Bump Number

Signal NameType

Description

Power supplies (WLAN)WRF_SYNTH_VDD3P3

PWR

Synthesizer VDD 3.3V supply

240, 241

WRF_PA_VDD3P3

PWR

2.4 GHz and 5 GHz PA 3.3V VBAT supply

227, 228

WRF_PMU_VDD1P35

PWR

PMU 1.35V supply

244

WRF_TXMIX_VDD

PWR

3.3V supply for TX mixer

229

WRF_SYNTH_VDD1P2

PWR

1.2V supply for synthesizer

231

WRF_AFE_VDD1P35

PWR

1.35V supply for the analog front end
(AFE)

185

PWM0

O

Pulse width modulation bit 0.

186

PWM1

O

Pulse width modulation bit 1

190

PWM2

O

Pulse width modulation bit 2

189

PWM3

O

Pulse width modulation bit 3

187

PWM4

O

Pulse width modulation bit 4

188

PWM5

O

Pulse width modulation bit 5

246

WRF_RFIN_2G

I

2.4 GHz WLAN receiver input

233

WRF_RFIN_5G

I

5 GHz WLAN receiver input

223

PWM Interface

RF Signal Interface (WLAN)

245

WRF_PAOUT_2G

O

2.4 GHz WLAN PA output

239

WRF_PAOUT_5G

O

5 GHz WLAN PA output

235

WRF_EXT_TSSIAI

5 GHz TSSI input from an optional external
power amplifier/power detector

237

WRF_GPAIO_OUT

I/O

Analog GPIO

215

RF_SW_CTRL_0

O

214

RF_SW_CTRL_1

O

RF Switch Control Lines

211

RF_SW_CTRL_2

O

205

RF_SW_CTRL_3

O

206

RF_SW_CTRL_4

O

207

RF_SW_CTRL_5

I/O

202

RF_SW_CTRL_6

I/O

201

RF_SW_CTRL_7

I/O

200

RF_SW_CTRL_8

I/O

196

RF_SW_CTRL_9

I/O

152

SDIO_CLK

I/O

SDIO cock151

SDIO_CMD

I/O

SDIO command line

150

SDIO_DATA_0

I/O

SDIO data line 0

149

SDIO_DATA_1

I/O

SDIO data line 1

148

SDIO_DATA_2

I/O

SDIO data line 2

147

SDIO_DATA_3

I/O

Programmable RF switch control lines. The
control lines are programmable via the driverand nvram.txt file.

SDIO Interface

Document Number: 002-14829 Rev. *L

SDIO data line 3

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PRELIMINARYCYW43907

Table 10. Signal Descriptions (Cont.)
Bump Number

Signal NameType

Description

S/PDIF Interface
Note: Supported via 161 (I2S_SDATAO0) and 155 (I2S_SDATAO1).
SPI Flash Interface
77

SFL_CLKO

Flash clock73

SFL_IO0

I/O

Flash data

71

SFL_IO1

I/O

Flash data

75

SFL_IO2

I/O

Flash data

72

SFL_IO3

I/O

Flash data

74

SFL_CSO

Flash Slave selectSPI Interface
Note: Each SPI Interface can alternatively be configured and used as a CSC Interfacea.
76

SPI0_CLKO

SPI clock78

SPI0_MISOI

SPI data master in81

SPI0_SISOO

SPI data master out

82

SPI0_CSO

SPI slave select83

SPI1_CLKO

SPI clock84

SPI1_MISOI

SPI data master in86

SPI1_SISOO

SPI data master out

80

SPI1_CSO

SPI slave select85

UART0_CTSI

UART clear-to-send

91

UART0_RTSO

UART request-to-send

88

UART0_RXDI

UART serial input

87

UART0_TXDO

UART serial output

170

USB2_DM

I/O

USB 2.0 data

167

USB2_DPI/O

USB 2.0 data

169

USB2_RREF

I

USB 2.0 reference resistor connection

175

USB2_MONCDRO

USB 2.0 CDR monitor

184

USB2_MONPLL

O

USB 2.0 PLL monitor

165

USB2_DSELI

USB 2.0 host and device mode selection

UART Interface

USB 2.0

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PRELIMINARYCYW43907

Table 10. Signal Descriptions (Cont.)
Bump Number

Signal NameType

Description

Voltage Regulators (Integrated)
108, 113, 122, 125
98, 99, 101, 102, 109, 112

SR_VDDBAT5V

I

VBAT.

SR_VLXOCBUCK switching regulator output

115, 116, 120, 127

LDO_VDD1P5I

LNLDO Input

128, 129

LDO_VDDBAT5V

I

LDO VBATWRF_XTAL_VDD1P35

I

XTAL LDO input (1.35 V)

220

WRF_XTAL_VDD1P2OXTAL LDO output (1.2 V)

106

VOUT_LNLDO

O

Output of LNLDO

221

114, 121, 126

VOUT_CLDOO

Output of core LDO

118, 119

VOUT_3P3

O

LDO 3.3 V output

117

VOUT_3P3_SENSE

OVoltage sense pin for LDO 3.3 V output

103

VOUT_CLDO_SENSE

OVoltage sense pin for core LDO

107

VOUT_BBPLLOUT

O

Output of baseband PLL

a. The SPI blocks can be re-purposed as I2C, however the WICED SDK does not support this. Certain I2C features are not available when using the SPI blocks
as I2C. Therefore Cypress does not recommend using the SPI blocks as I2C Interfaces.

Document Number: 002-14829 Rev. *L

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10. GPIO Signals and Strapping Options
10.1 Overview
This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine various
operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, eachpin assumes the GPIO or alternative function specified in Table 12. Each strapping option pin has an internal PU/PD resistor that
determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground, using a 10kΩ resistor or less.
Note: Refer to the reference board schematics for more information.

10.2 Weak PD and PU Resistances
At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak PD resistances (for a pin voltage of VDDO) are 37.99 kΩ, 44.57 kΩ,
and 51.56 kΩ, respectively. At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak PU resistances (for a pin voltage of0V) are 34.73 kΩ, 39.58 kΩ, and 44.51 kΩ, respectively.

10.3 Strapping Options
Table 11 provides the strapping options.
Table 11. Strapping Options
Pin Name

Strap

Bump #

Default Internal
pull During
Strap

Description

GPIO_1

GSPI_MODE

142

PD

Enable gSPI Interface

GPIO_7

WCPU_BOOT_MODE

95

PD

Boot from tightly coupled memory (TCM) ROM or TCM
RAM

GPIO_11

ACPU_BOOT_MODE

140

PD

Boot from SoC SROM or SoC SRAM

GPIO_13

SDIO_MODE

131

PD

Select SDIO host mode

GPIO_15VTRIM_EN

145

PD

Enable PMU voltage trimming

RF_SW_CTRL_5

DAP_CLK_SEL

207

PD

Select XTAL clock or the test clock (tck) for the debug
access port (DAP)

RF_SW_CTRL_7

RSRC_INIT_MODE

201

PD

PMU resource initialization mode selection

Document Number: 002-14829 Rev. *L

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10.4 Alternate GPIO Signal Functions
Table 12 provides the alternate signal functions of the GPIO signals.
Table 12. Alternate GPIO Signal Functions
GPIO

Default

JTAG_SEL

Default Pull

GPIO_0
GPIO_1

HOLD/PDLOW/PDHIGH

Strap

Comments

USB20H_CTL–

No pull

–

–

Down

HOLD

–

8 mA

HOLD

GSPI_MODE

GPIO_2

GCI_GPIO(0)JTAG_TCK

No pull

8 mA

HOLD

–

8 mA

GPIO_3

GCI_GPIO(1)JTAG_TMSGPIO_4

GCI_GPIO(2)JTAG_TDI

No pull

HOLD

–

8 mA

No pull

HOLD

–

8 mA

GPIO_5

GCI_GPIO(3)JTAG_TDO

No pull

HOLD

–

8 mA

GPIO_6

GCI_GPIO(4)JTAG_TRST

No pull

GPIO_7

–

–

Down

HOLD

–

8 mA

HOLD

WCPU_BOOT_MODE

GPIO_8GPIO_8–

No pull

HOLD

8 mA

–

8 mA

GPIO_9GPIO_9

–

Down

HOLD

–

8 mA

GPIO_10

GPIO_10–

No pull

HOLD

–

8 mA

GPIO_11

–

–

Down

HOLD

ACPU_BOOT_MODE

8 mA

GPIO_12

GPIO_12–

No pull

HOLD

–

8 mA

GPIO_13

–

–

Down

HOLD

SDIO_MODE

8 mA

GPIO_14

GPIO_14–

No pull

HOLD

–

8 mA

GPIO_15

–

–

Down

HOLD

VTRIM_EN

8 mA

GPIO_16––

No pull

HOLD

–

8 mA

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

11. Pin Multiplexing
Table 13 shows the pin multiplexing functions.
Table 13. Pin Multiplexing
Pin

Function
2

3

8

9

GPIO_0

GPIO_01

UART0_RXD

I2C1_SDATA

PWM0

4

SPI1_MISO

5PWM2GPIO_12

GPIO_8–PWM4USB20H_CTL

GPIO_1

GPIO_1

UART0_TXD

I2C1_CLK

PWM1

SPI1_CLKPWM3

GPIO_13

GPIO_9–PWM5–GPIO_2

GPIO_2––

GCI_GPIO_0

–

–

–

–

TCK

–

GPIO_3

GPIO_3––

GCI_GPIO_1

–

–

–

–

TMS

–

–

GPIO_4

GPIO_4––

GCI_GPIO_2

–

–

–

–

TDI

–

–

GPIO_5

GPIO_5––

GCI_GPIO_3

–

–

–

–

TDO

–

–

GPIO_6

GPIO_6––

GCI_GPIO_4–

TRST_L–GPIO_7

GPIO_7

UART0_
RTS_OUT

–

PWM1

PWM3

SPI1_CS

6–
I2C1_CLK7–
GPIO_15

GPIO_11

PMU_TEST_O

10

–

11

–

–
PWM5

GPIO_8GPIO_8

SPI1_MISO

PWM2

PWM4

UART0_RXD–

GPIO_16

GPIO_12

TAP_SEL_P

I2C1_SDATAPWM0

GPIO_9GPIO_9

SPI1_CLK

PWM3

PWM5

UART0_TXD–

GPIO_0

GPIO_13–

I2C1_CLK

PWM1

GPIO_10

GPIO_10

SPI1_MOSI

PWM4

I2C1_SDATA

UART0_
CTS_INPWM0

GPIO_1

GPIO_14PWM2GPIO_11

GPIO_11

SPI1_CS

PWM5

I2C1_CLKUART0_
RTS_OUTPWM1GPIO_7

GPIO_15PWM3GPIO_12

GPIO_12

I2C1_SDATA

UART0_RXD

SPI1_MISO

PWM2

PWM4

GPIO_8GPIO_16

PWM0

GPIO_13

GPIO_13

I2C1_CLKUART0_TXD

SPI1_CLK

PWM3

PWM5

GPIO_9GPIO_0PWM1

GPIO_14

GPIO_14PWM0

UART0_
CTS_IN

SPI1_MOSII2C1_SDATA

GPIO_10–PWM4GPIO_15

GPIO_15PWM1

UART0_
RTS_OUTSPI1_CS

I2C1_CLK–GPIO_11

GPIO_7PWM5GPIO_16

GPIO_16

UART0_
CTS_INPWM0

PWM2

SPI1_MOSII2C1_SDATA

GPIO_14

GPIO_10RF_DISABLE_L–

SDIO_CLKSDIO_CLK

–

–

–

–

–

–

–

SDIO_AOS_
CLK–

SDIO_CMDSDIO_CMD

–

–

–

–

–

–

–

SDIO_AOS_
CMD

–

SDIO_
DATA_0

SDIO_D0

–

–

–

–

–

–

–

SDIO_AOS_
D0

–

SDIO_
DATA_1

SDIO_D1

–

–

–

–

–

–

–

SDIO_AOS_
D1

–

SDIO_
DATA_2

SDIO_D2

–

–

–

–

–

–

–

SDIO_AOS_
D2–

Document Number: 002-14829 Rev. *L–

SDIO_SEP_INT SDIO_SEP_IN
T_0D
–

–

SDIO_SEP_INT SDIO_SEP_IN
_0D
T
–
–
–

–
PWM2
PWM3
PWM4
–
–
–
–
–

Page 43 of 94

PRELIMINARYCYW43907

Table 13. Pin Multiplexing
Pin

Function
1

2

3

4

5

6

8

9

10

11

–

–

SDIO_AOS_
D3

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

UART_
DBG_RX a

–

–

–

–

–

–

SECI_OUT a

UART_
DBG_TX a

–

–

–

–

–

–

PWM0

GPIO_2

GPIO_18

–

–

–

–

–

–

–

–

PWM1

GPIO_3

GPIO_19

–

–

–

–

–

–

–

–

PWM2

PWM2

GPIO_4

GPIO_20

–

–

–

–

–

–

–

–

PWM3

PWM3

GPIO_5

GPIO_21

–

–

–

–

–

–

–

–

PWM4

PWM4

GPIO_6

GPIO_22

–

–

–

–

–

–

–

–

PWM5

PWM5

GPIO_8GPIO_23

–

–

–

–

–

–

–

–

SPI0_MISO

SPI0_MISOGPIO_17

GPIO_24

–

–

–

–

–

–

–

–

SPI0_CLK

SPI0_CLKGPIO_18

GPIO_25

–

–

–

–

–

–

–

–

SPI0_MOSISPI0_MOSIGPIO_19

GPIO_26

–

–

–

–

–

–

–

–

SPI0_CS

SPI0_CS

GPIO_20

GPIO_27

–

–

–

–

–

–

–

–

I2C0_SDATA

I2C0_SDATA

GPIO_21

GPIO_28

–

–

–

–

–

–

–

–

I2C0_CLK

I2C0_CLKGPIO_22

GPIO_29

–

–

–

–

–

–

–

–

I2S_MCLK0

I2S_MCLK0

GPIO_23

GPIO_0

–

–

–

–

–

–

–

–

I2S_SCLK0

I2S_SCLK0

GPIO_24

GPIO_2

–

–

–

–

–

–

–

–

I2S_LRCLK0

I2S_LRCLK0GPIO_25

GPIO_3

–

–

–

–

–

–

–

–

SDIO_
DATA_3

SDIO_D3

–

–

–

–

–

RF_SW_
CTRL_5

RF_SW_
CTRL_5

GCI_GPIO_5

–

–

–

RF_SW_
CTRL_6

RF_SW_
CTRL_6UART_
DBG_RXa

SECI_IN a–

RF_SW_
CTRL_7

RF_SW_
CTRL_7UART_
DBG_TX a

SECI_OUT a

RF_SW_
CTRL_8RF_SW_
CTRL_8

SECI_IN a

RF_SW_
CTRL_9RF_SW_
CTRL_9PWM0
PWM1Document Number: 002-14829 Rev. *L

7

–
–
–
–

–
–
–
–

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PRELIMINARYCYW43907

Table 13. Pin Multiplexing
Function

Pin

3

4

5

6

7

8

9

GPIO_26

GPIO_4

–

–

–

–

–

–

DATAI0I2S_

SDATAI0

I2S_
SDATAO0

I2S_
SDATAO0GPIO_27

GPIO_5

–

–

–

–

–

–

I2S_
SDATAO1

I2S_
SDATAO1

GPIO_28

GPIO_6

–

–

–

–

–

–

I2S_SDATAI1 I2S_SDATAI1 GPIO_29

GPIO_8

–

–

–

–

–

–

–

–

I2S_S

1

2

10
–
–
–

11
–
–
–

I2S_MCLK1

I2S_MCLK1

GPIO_30

GPIO_17

–

–

–

–

–

–

–

–

I2S_SCLK1

I2S_SCLK1

GPIO_31

GPIO_30

–

–

–

–

–

–

–

–

I2S_LRCLK1I2S_LRCLK1GPIO_0

GPIO_31

–

–

–

–

–

–

–

–

a. UART_DBG_TX and UART_DBG_RX are for UART1 mentioned in section 5.10 and in the reference schematics. SECI_IN and SECI_OUT are for UART2 mentioned in section 5.10 and in the reference schematics.

Document Number: 002-14829 Rev. *L

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12. I/O States
Table 14 provides I/O state information for the signals listed.
The following notations are used in Table 14:■

I: Input signal■

O: Output signal■

I/O: Input/Output signal■

NoPull = Neither pulled up nor pulled down

Table 14. I/O States
Low Power State/Sleep (All Power
Present)

Powerdownb(REG_ON
Held Low)

Out-of-Reset; Before Power
Software Download
Rail(REG_ON High)Ball Name

I/O

KeeperaHIB_REG_ON_IN

I

N

Input; PD (Pull-down can be disabled.) Input; PD (Pull-down can be disabled.) Input

REG_ONI

N

Input; PD (Pull-down can be disabled.) Input; PD (Pull-down can be disabled.) Input; PD (of 200 kΩ) Input; PD (of 200 kΩ)

CLK_REQ

I/O

YOpen drain or push-pull (programmable). Active high.

Open drain or push-pull (programmable). Active high.

High-Z, NoPull

Open drain; active
high

VDDO

GPIO_0I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

High-Z, NoPull

Input; PD

VDDIOGPIO_1

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_2

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_3

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

High-Z, NoPull

Input; PD

VDDIOGPIO_4I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_5I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

High-Z, NoPull

Input; PD

VDDIOGPIO_6

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

Active Mode

Document Number: 002-14829 Rev. *L

Input

–
–

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PRELIMINARYCYW43907

Table 14. I/O States
Low Power State/Sleep (All Power
Present)

Powerdownb(REG_ON
Held Low)

Out-of-Reset; Before Power
Software Download
Rail(REG_ON High)

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

Y

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

High-Z, NoPull

Input; PD

VDDIO

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

High-Z, NoPull

Input; PD

VDDIOGPIO_10I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_11

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

Input/Output; PU, PD, or NoPull(programmable [Default: PD])

High-Z, NoPull

Input; PD

VDDIOGPIO_12I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_13

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_14

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_15

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

GPIO_16

I/O

Y

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])

Input/Output; PU, PD, or NoPull(programmable [Default: NoPull])High-Z, NoPull

Input; NoPull

VDDIO

RF_SW_CTRL(0 to 9)I/O

Y

Output; NoPull

Output; NoPull

High-Z

Output; NoPull

VDDIO
_RF

I/O

KeeperaGPIO_7I/O

Y

GPIO_8I/O

GPIO_9Ball Name

Active Modea. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in power down state. If there is no keeper, and it is an input and there is NoPull, then the pad should be driven to prevent
leakage due to floating pad (WL_REG_ON, for example).
b. In the power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied.

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13. Electrical Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

13.1 Absolute Maximum Ratings
Caution! The absolute maximum ratings in Table 15 indicate levels where permanent damage to the device can occur, even if theselimits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute
maximum conditions for extended periods can adversely affect long-term reliability of the device.
Table 15. Absolute Maximum Ratings
Parameter

SymbolDC supply for VBAT and PA driver supply a

VBAT

Value

Unit

–0.5 to +5.5

V

DC supply voltage for digital I/O

VDDIO–0.5 to 3.9V

DC supply voltage for I2S I/O

VDDIO_I2S–0.5 to 3.9V

DC supply voltage for RF switch I/O

VDDIO_RF–0.5 to 3.9V

DC supply voltage for Ethernet I/O

VDDIO_RMII–0.5 to 3.9V

DC supply voltage for SDIO I/O

VDDIO_SD

DC input supply voltage for CLDO, LNLDO, and BBPLL LDOb–

–0.5 to 3.9

V–0.5 to 1.575

V

3.3 V DC supply for USB

USB2_AVDD33
USB2_AVDD33LDO
USB2_AVDD33IO–0.5 to 3.9V

3.3 V DC supply voltage for RF analogc

VDD3P3RF–0.5 to 3.6

V

1.35 V DC supply voltage for RF analogd

VDD1P35RF–0.5 to 1.5V

1.2 V DC supply voltage for RF analoge

VDD1P2RF–0.5 to 1.26

V

1.2 V DC supply voltage for analog circuitsf

VDD1P2A–0.5 to 1.26

V

DC supply voltage for the coreg

VDDC–0.5 to 1.32

V

DC supply voltage for OTP memory

OTP_VDD3P3–0.5 to 3.9

V

Maximum undershoot voltage for I/O

Vundershoot

–0.5

V

Maximum junction temperature

Tj

125

°C

a. For the SR_VDDBAT5V and LDO_VDDBAT5V supplies.
b. For the LDO_VDD1P5 and WRF_XTAL_VDD1P35 supplies.
c. For the WRF_SYNTH_VDD3P3, WRF_PA_VDD3P3, and WRF_TXMIX_VDD supplies.
d. For WRF_PMU_VDD1P35 and WRF_AFE_VDD1P35 supplies.
e. For the WRF_SYNTH_VDD1P2 supply.
f. For the AVDD1P2_AUDIO, AVDD1P2, and HSIC_AVDD12 supplies.
g. For the VDD, HSIC_DVDD12, and HSIC2_DVDD2 supplies.

13.2 Environmental Ratings
The environmental ratings are shown in Table 16.
Table 16. Environmental Ratings
Characteristic

Value

Units

Conditions/Comments

Ambient temperature (TA)–30 to +85°C

Storage temperature–40 to +125

°C

Less than 60%

Storage

Less than 85%

Operation

Relative humidity

Document Number: 002-14829 Rev. *L

Functional operation–

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PRELIMINARYCYW43907

13.3 Electrostatic Discharge Specifications
Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps
to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
Table 17. ESD Specifications
Pin Type

SymbolCondition

ESD
RatingUnit

ESD

ESD_HAND_HBM

Human body model contact discharge per JEDEC EID/JESD22-A114

1.5 k

V

CDM

ESD_HAND_CDM

Charged device model contact discharge per JEDEC EIA/
JESD22-C101

250

V

13.4 Recommended Operating Conditions and DC Characteristics
Caution! Functional operation is not guaranteed outside of the limits shown in Table 18. Operation outside these limits for extended
periods can adversely affect long-term reliability of the device.
Table 18. Recommended Operating Conditions and DC Characteristics
Parameter

SymbolValue
Minimum

TypicalMaximum

Unit

DC supply voltage for VBAT

VBAT

2.3a

3.6

4.8

V

DC supply voltage for digital I/O

VDDIO

1.71

–

3.63

V

DC supply voltage for I2S I/O

VDDIO_I2S

1.71

–

3.63

V

DC supply voltage for RF switch I/Os

VDDIO_RFb

3.13

3.3

3.6

V

DC supply voltage for Ethernet I/O

VDDIO_RMII

1.71

–

3.63

V

DC supply voltage for SDIO I/O

VDDIO_SD

1.71

–

3.63

V

–

1.3

1.35

1.5

V

USB2_AVDD33
USB2_AVDD33LDO
USB2_AVDD33IO

2.97

3.3

3.63

V

3.3V DC supply voltage for RF analog

VDD3P3RFc

3

3.3

3.45

V

1.35V DC supply voltage for RF analog

VDD1P35RFc

1.3

1.35

1.5

V

1.2V DC supply voltage for RF analog

VDD1P2RFc

1.1

1.2

1.26

V

1.2V DC supply voltage for analog

VDD1P2Ac

1.1

1.2

1.26

V

VDDC

1.14

1.2

1.26

V

OTP_VDD3P3b

2.97

3.3

3.63

V

WRF_TCXO_VDDc

1.62

1.8

1.98

V

Vth_POR

0.4

–

0.7

V

VIH

1.27

–

–

V

DC input supply voltage for CLDO, LNLDO, and BBPLL
LDO
3.3V DC supply for USB

DC supply voltage for core
DC supply voltage for OTP memory
DC supply voltage for TCXO input bufferInternal POR threshold
SDIO Interface I/O Pins
For VDDIO_SD = 1.8V:
Input high voltage
Input low voltage

VIL

–

–

0.58

V

Output high voltage @ 2 mA

VOH

1.40

–

–

V

Output low voltage @ 2 mA

VOL

–

–

0.45

V

VIH

0.625 ×
VDDIO

–

–

V

For VDDIO_SD = 3.3V:
Input high voltage

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Table 18. Recommended Operating Conditions and DC Characteristics (Cont.)
Parameter

SymbolValue
Minimum

TypicalMaximum

Unit

Input low voltage

VIL

–

–

0.25 ×
VDDIO

V

Output high voltage @ 2 mA

VOH

0.75 × VDDIO

–

–

V

Output low voltage @ 2 mA

VOL

–

–

0.125 ×
VDDIO

V

VIH

0.65 × VDDIO

–

–

V
V

Other Digital I/O Pins
For VDDIO = 1.8V:
Input high voltage
Input low voltage

VIL

–

–

0.35 ×
VDDIO

Output high voltage @ 2 mA

VOH

VDDIO – 0.45

–

–

V

Output low voltage @ 2 mA

VOL

–

–

0.45

V

For VDDIO = 3.3V:
Input high voltage

VIH

2.00

–

–

V

Input low voltage

VIL

–

–

0.80

V

Output high voltage @ 2 mA

VOH

VDDIO – 0.4

–

–

V

Output low voltage @ 2 mA

VOL

–

–

0.40

V

RF Switch Control Output Pinsd
For VDDIO_RF = 3.3V:
Output high voltage @ 2 mA

VOH

VDDIO – 0.4

–

–

V

Output low voltage @ 2 mA

VOL

–

–

0.40

V

Input capacitance

CIN

–

–

5

pF

a. The CYW43907 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3V < VBAT < 4.8V.
b. VDD3P3RF, which is an internally generated supply, can drive this node. There is sufficient current and the appropriate state is maintained during hibernation andsleep cycles.
c. Internally generated supply.
d. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

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13.5 Power Supply Segments
The digital I/Os are placed in physical segments. The supply voltage for each segment can be independently selected.
Table 19 shows the power supply segments and the I/O pins associated with each segment.
Table 19. Power Supply Segments
Power Supply
Segment

Pins

VDDIO

CLK_REQ, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, GPIO_8, GPIO_9,
GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14, GPIO_15, GPIO_16, I2C0_CLK, I2C0_SDATA, I2C1_CLK,
I2C1_SDATA, JTAG_SEL, PWM0, PWM1, PWM2, PWM3, PWM4, PWM5, SFL_CLK, SFL_CS, SFL_IO0,
SFL_IO1, SFL_IO2, SFL_IO3, SPI0_CLK, SPI0_CS, SPI0_MISO, SPI0_SISO, SPI1_CLK, SPI1_CS,
SPI1_MISO, SPI1_SISO, SRSTN, UART0_CTS, UART0_RTS, UART0_RXD, UART0_TXD, USB2_DSELVDDIO_I2S

I2S_LRCLK0, I2S_LRCLK1, I2S_MCLK0, I2S_MCLK1, I2S_SCLK0, I2S_SCLK1, I2S_SDATAI0, I2S_SDATAI1,
I2S_SDATAO0, I2S_SDATAO1VDDIO_RF

RF_SW_CTRL_0, RF_SW_CTRL_1, RF_SW_CTRL_2, RF_SW_CTRL_3, RF_SW_CTRL_4, RF_SW_CTRL_5,
RF_SW_CTRL_6, RF_SW_CTRL_7, RF_SW_CTRL_8, RF_SW_CTRL_9

VDDIO_RMIIRMII_G_COL, RMII_G_CRS, RMII_G_RXC, RMII_G_RXD0, RMII_G_RXD1, RMII_G_RXD2, RMII_G_RXD3,
RMII_G_RXDV, RMII_G_TXC, RMII_G_TXD0, RMII_G_TXD1, RMII_G_TXD2, RMII_G_TXD3, RMII_G_TXEN,RMII_MDC, RMII_MDIO

13.6 Ethernet MAC Controller (MII/RMII) DC Characteristics
Table 20. MII Recommended Operating Condition
Parameter
Supply voltage

Symbol
GMAC_VDDIO (MII/RMII)

Minimum

Maximum

Units

3.14

3.47

V

13.7 GPIO, UART, and JTAG Interfaces DC Characteristics
Table 21. GPIO, UART, and JTAG Interfaces
Parameter

SymbolMinimum

Maximum

Units

Conditions

Logic Input high voltage

VIH

2.0

VDDIO + 0.5

V–

Logic Input low voltage

VIL

–0.5

0.8

V

–

Logic Output high voltage

VOH

2.4

–

V

–

Logic Output low voltage

VOL

–

0.4

V

–

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

14. WLAN RF Specifications
14.1 Introduction
The CYW43907 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section
describes the RF characteristics of the 2.4 GHz and 5 GHz radio.
Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results.
Unless otherwise stated, limit values apply for the conditions specified in Table 16: “Environmental Ratings” andTable 18: “Recommended Operating Conditions and DC Characteristics”. Typical values apply for the following conditions:■

VBAT = 3.6V■

Ambient temperature = +25°C
Figure 14. Port Locations for WLAN Testing
Chip Output PortCYW43907
2.4 GHz WLAN TX(WRF_PAOUT_2G)
2.4 GHz WLAN RX(WRF_RFIN_2G)

Chip Input Port

Diplexer
Chip Output Port
5 GHz WLAN TX(WRF_PAOUT_5G)

RF PortTR Switch

5 GHz WLAN RX(WRF_RFIN_5G)
Chip Input Port

14.2 2.4 GHz Band General RF Specifications
Table 22. 2.4 GHz Band General RF Specifications
Minimum

TypicalMaximum

Unit

TX/RX switch time

Item

Including TX ramp down

–

–

5

µs

RX/TX switch time

Including TX ramp up

–

–

2

µs

Power up and powerdown ramp time

DSSS/CCK
modulations

–

–

<2

µs

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14.3 WLAN 2.4 GHz Receiver Performance Specifications
Note: The specifications shown in Table 23 apply at the chip ports, unless otherwise defined.
Table 23. WLAN 2.4 GHz Receiver Performance Specifications
Parameter

Condition/Notes

Minimum–

Frequency range
1 Mbps DSSS

TypicalMaximum

Unit

2400

–

2500

MHz

–

–98.9

–

dBm

2 Mbps DSSS
RX sensitivity IEEE 802.11b(8% PER for 1024 octet PSDU) 5.5 Mbps DSSS

–

–96.0

–

dBm

–

–93.9

–

dBm

11 Mbps DSSS

–

–90.4

–

dBm

6 Mbps OFDM

–

–95.0

–

dBm

9 Mbps OFDM

–

–93.8

–

dBm

12 Mbps OFDM

–

–92.7

–

dBm

18 Mbps OFDM

–

–90.3

–

dBm

24 Mbps OFDM

–

–87.1

–

dBm

36 Mbps OFDM

–

–83.6

–

dBm

48 Mbps OFDM

–

–79.3

–

dBm

54 Mbps OFDM

–

–78.0

–

dBm

MCS0

–

–94.6

–

dBm

MCS1

–

–92.1

–

dBm

MCS2

–

–89.8

–

dBm

MCS3

–

–86.6

–

dBm

MCS4

–

–83.0

–

dBm

MCS5

–

–78.3

–

dBm

MCS6

–

–76.6

–

dBm

MCS7

–

–75.0

–

dBm

RX sensitivity IEEE 802.11g(10% PER for 1024 octet
PSDU)

20 MHz channel spacing for all MCS rates

RX sensitivity IEEE 802.11n(10% PER for 4096 octet
PSDU) a Defined for default
parameters: 800 ns GI and
non-STBC.

Input in-band IP3

Maximum receive level@ 2.4 GHz

Maximum LNA gain

–

–8

–

dBm

Minimum LNA gain

–

+9

–

dBm

@ 1, 2 Mbps (8% PER, 1024 octets)

–3.5

–

–

dBm

@ 5.5, 11 Mbps (8% PER, 1024 octets)

–9.5

–

–

dBm

@ 6, 9, 12 Mbps (10% PER, 1024 octets)

–9.5

–

–

dBm

@ MCS0–2 rates (10% PER, 4095 octets)

–9.5

–

–

dBm

@ 18, 24, 36, 48, 54 Mbps (10% PER, 1024 octets)

–14.5

–

–

dBm

@ MCS3–7 rates (10% PER, 4095 octets)

–14.5

–

–

dBm

35

–

–

dB

35

–

–

dB

35

–

–

dB

35

–

–

dB

Desired and interfering signal 30 MHz apart
Adjacent channel rejection1 Mbps DSSS
–74 dBm
DSSS(Difference between interfering 2 Mbps DSSS
–74 dBmand desired signal at 8% PER
Desiredandinterfering
signal25 MHz apartfor 1024 octet PSDU withdesired signal level as
5.5 Mbps DSSS
–70 dBm
specified in Condition/Notes.)
11 Mbps DSSS
–70 dBm

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PRELIMINARYCYW43907

Table 23. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)
Parameter
Adjacent channel rejectionOFDM(Difference between interferingand desired signal (25 MHzapart) at 10% PER for 1024
octet PSDU with desired signal
level as specified in Condition/
Notes.)

Adjacent channel rejection
MCS0–7(Difference between interferingand desired signal (25 MHzapart) at 10% PER for 4096
octet PSDU with desired signal
level as specified in Condition/
Notes.)

Condition/Notes

Minimum

TypicalMaximum

Unit

6 Mbps OFDM

–79 dBm

16

–

–

dB

9 Mbps OFDM

–78 dBm

15

–

–

dB

12 Mbps OFDM

–76 dBm

13

–

–

dB

18 Mbps OFDM

–74 dBm

11

–

–

dB

24 Mbps OFDM

–71 dBm

8

–

–

dB

36 Mbps OFDM

–67 dBm

4

–

–

dB

48 Mbps OFDM

–63 dBm

0

–

–

dB

54 Mbps OFDM

–62 dBm

–1

–

–

dB

MCS0

–79 dBm

16

–

–

dB

MCS1

–76 dBm

13

–

–

dB

MCS2

–74 dBm

11

–

–

dB

MCS3

–71 dBm

8

–

–

dB

MCS4

–67 dBm

4

–

–

dB

MCS5

–63 dBm

0

–

–

dB

MCS6

–62 dBm

–1

–

–

dB

MCS7

–61 dBm

–2

–

–

dB

Maximum receiver gain

–

–

–

66

–

dB

Gain control step

–

–

–

3

–

dB

Range –95c dBm to –30 dBm

–5

–

5

dB

Range above –30 dBm

–8

–

8

dB

Return loss

Zo = 50Ω, across the dynamic range

10

11.5

13

dB

Receiver cascaded noise
figureAt maximum gain

–

4

–

dB

RSSI accuracyba. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.
b. The minimum and maximum values shown have a 95% confidence level.
c. –95 dBm with calibration at time of manufacture, –92 dBm without calibration.

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14.4 WLAN 2.4 GHz Transmitter Performance Specifications
Note: Unless otherwise noted, the values shown in Table 24 apply at the chip ports.
Table 24. WLAN 2.4 GHz Transmitter Performance Specifications
Parameter

Condition/Notes

Minimum–

Frequency range

TX power EVMa
(highest power setting, 25°C, and
VBAT = 3.6)

TypicalMaximum

Unit

2400

–

2500

MHz

–

20.5

–

dBm

DSS/CCK–9 dB

OFDM, BPSK

–8 dB

–

20

–

dBm

OFDM, QPSK

–13 dB

–

20

–

dBm

OFDM, 16-QAM–19 dB

–

19

–

dBm

OFDM, 64-QAM (R = 3/4) –25 dB

–

19

–

dBm

OFDM, 64-QAM (MCS7,
HT20)–27 dB

–

18.5

–

dBm

OFDM, BPSK

5 dBm

–29

–31

–

dB

OFDM, 64-QAM

5 dBm

–31

–33

–

dB

MCS7

5 dBm

–33

–35

–

dB

37.4 MHz crystal, integrated from 10 kHz to
10 MHz–0.45–

Degrees

TX power control dynamic range

–

10

–

–

dB

Closed-loop TX power variation at
highest power level setting

Across full temperature and voltage range.
Applies to 10 dBm to 20 dBm output power
range.

–

–

±1.5

dB

–

15

–

–

dBc

–

–

0.25

–

dB

–

6

–

dB

OFDM EVMb(25°C, VBAT = 3.6V)
Phase noise

Carrier suppression
Gain control step
Return loss at Chip port TX

Zo = 50Ω

a. This specification row indicates the linear power specification as measured from the chip output port. The requirement is in dBm (TX power). The ratio (dB) in theConditions/Notes column is the EVM.
b. This specification row indicates the EVM floor. The requirement is in dB (EVM). The power in the Conditions/Notes column is the TX power specification in dBm.

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14.5 WLAN 5 GHz Receiver Performance Specifications
Note: Unless otherwise noted, the values shown in Table 25 apply at the chip ports.
Table 25. WLAN 5 GHz Receiver Performance Specifications
Parameter

Condition/Notes

Minimum–

Frequency range

RX sensitivity IEEE 802.11a (10%PER for 1000 octet PSDU)

TypicalMaximum

Unit

4900

–

5845

MHz

6 Mbps OFDM

–

–93.6

–

dBm

9 Mbps OFDM

–

–92.4

–

dBm

12 Mbps OFDM

–

–91.3

–

dBm

18 Mbps OFDM

–

–88.9

–

dBm

24 Mbps OFDM

–

–85.7

–

dBm

36 Mbps OFDM

–

–82.3

–

dBm

48 Mbps OFDM

–

–77.9

–

dBm

54 Mbps OFDM

–

–76.6

–

dBm

MCS0

–

–93.2

–

dBm

MCS1

–

–90.7

–

dBm

MCS2

–

–88.4

–

dBm

MCS3

–

–85.2

–

dBm

MCS4

–

–81.6

–

dBm

MCS5

–

–76.9

–

dBm

MCS6

–

–75.2

–

dBm

MCS7

–

–73.6

–

dBm

MCS0

–

–90.3

–

dBm

MCS1

–

–87.5

–

dBm

MCS2

–

–84.9

–

dBm

MCS3

–

–81.8

–

dBm

MCS4

–

–78.3

–

dBm

MCS5

–

–73.9

–

dBm

MCS6

–

–72.7

–

dBm

MCS7

–

–71.2

–

dBm

Maximum LNA gain

–

–12

–

dBm

Minimum LNA gain

–

+4

–

dBm

@ 6, 9, 12 Mbps (10% PER, 1024 octets)

–9.5

–

–

dBm

@ MCS0–2 rates (10% PER, 4095 octets)

–9.5

–

–

dBm

@ 18, 24, 36, 48, 54 Mbps (10% PER, 1024
octets)

–14.5

–

–

dBm

@ MCS3–7 rates (10% PER, 4095 octets)

–14.5

–

–

dBm

20 MHz channel spacing for all MCS rates

RX sensitivity IEEE 802.11n (10%PER for 4096 octet PSDU)
Defined for default parameters:
800 ns GI and non-STBC.

40 MHz channel spacing for all MCS rates

RX sensitivity IEEE 802.11n (10%PER for 4096 octet PSDU)
Defined for default parameters:
800 ns GI and non-STBC.

Input in-band IP3

Maximum receive level @ 5 GHz

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Table 25. WLAN 5 GHz Receiver Performance Specifications (Cont.)
Parameter

Adjacent channel rejection(Difference between interfering anddesired signal (20 MHz apart) at 10%
PER for 1000 octet PSDU with desired
signal level as specified in Condition/
Notes)

Alternate adjacent channel rejection(Difference between interfering anddesired signal (40 MHz apart) at 10%
PER for 1000a octet PSDU withdesired signal level as specified in
Condition/Notes)

Condition/Notes

Minimum

TypicalMaximum

Unit

6 Mbps OFDM

–79 dBm

16

–

–

dB

9 Mbps OFDM

–78 dBm

15

–

–

dB

12 Mbps OFDM

–76 dBm

13

–

–

dB

18 Mbps OFDM

–74 dBm

11

–

–

dB

24 Mbps OFDM

–71 dBm

8

–

–

dB

36 Mbps OFDM

–67 dBm

4

–

–

dB

48 Mbps OFDM

–63 dBm

0

–

–

dB

54 Mbps OFDM

–62 dBm

–1

–

–

dB

65 Mbps OFDM

–61 dBm

–2

–

–

dB

6 Mbps OFDM

–78.5 dBm

32

–

–

dB

9 Mbps OFDM

–77.5 dBm

31

–

–

dB

12 Mbps OFDM

–75.5 dBm

29

–

–

dB

18 Mbps OFDM

–73.5 dBm

27

–

–

dB

24 Mbps OFDM

–70.5 dBm

24

–

–

dB

36 Mbps OFDM

–66.5 dBm

20

–

–

dB

48 Mbps OFDM

–62.5 dBm

16

–

–

dB

54 Mbps OFDM

–61.5 dBm

15

–

–

dB

65 Mbps OFDM

–60.5 dBm

14

–

–

dB

Maximum receiver gain

–

–

66

–

dB

Gain control step

–

–

3

–

dB

Range –92 dBm to –30 dBm

–5

–

5

dB

Range above –30 dBm

–8

–

8

dB

Return loss

Zo = 50Ω, across the dynamic range

10

–

13

dB

Receiver cascaded noise figure

At maximum gain

–

5

–

dB

RSSI accuracyba. For 65 Mbps, the size is 4096.
b. The minimum and maximum values shown have a 95% confidence level.

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14.6 WLAN 5 GHz Transmitter Performance Specifications
Note: Unless otherwise noted, the values shown in Table 26 apply at the chip ports.
Table 26. WLAN 5 GHz Transmitter Performance Specifications
Parameter

Condition/Notes

Minimum–

Frequency range

TypicalMaximum

Unit

4900

–

5845

MHz

OFDM, QPSK

–13 dB

–

20

–

dBm

OFDM, 16-QAM–19 dB

–

18.5

–

dBm

OFDM, 64-QAM (R –25 dB= 3/4)

–

17

–

dBm

OFDM, 64-QAM(MCS7, HT20)–27 dB

–

16.5

–

dBm

OFDM, 64-QAM(MCS7, HT40)–27 dB

–

15.5

–

dBm

OFDM, BPSK

0 dBm

–

–30

–

dB

OFDM, 64-QAM (R 0 dBm= 3/4)

–

–33

–

dB

MCS7 HT20

0 dBm

–

–34

–

dB

MCS7 HT40

0 dBm

–

–33

–

dB

37.4 MHz Crystal, Integrated from 10 kHz
to 10 MHz

–

0.5

–

Degrees

TX power control dynamic range

–

10

–

–

dB

Closed loop TX power variation at
highest power level setting

Across full-temperature and voltage range.
Applies across 10 to 20 dBm output power
range.

–

–

±2.0

dB

Carrier suppression

–

15

–

–

dBc

Gain control step

–

–

0.25

–

dB

–

6

–

dB

a

TX power EVM(highest power setting, 25°C, and
VBAT = 3.6V)

OFDM EVMb(25°C, VBAT = 3.6V)

Phase noise

Return loss

Zo = 50Ω

a. This specification row indicates the linear power specification as measured from the chip output port. The requirement is in dBm (TX power). The ratio (dB) in theConditions/Notes column is the EVM.
b. This specification row indicates the EVM floor. The requirement is in dB (EVM). The power in the Conditions/Notes column is the TX power specification in dBm.

14.7 General Spurious Emissions Specifications
This section provides the TX and RX spurious emissions specifications for the WLAN 2.4 GHz and 5 GHz bands. The recommended
spectrum analyzer settings for the spurious emissions specifications are provided in Table 27.
Table 27. Recommended Spectrum Analyzer Settings
Parameter

Setting

Resolution bandwidth (RBW)

1 MHz

Video bandwidth (VBW)

1 MHz

Sweep

Auto

Span

100 MHz

Detector

Maximum peakTrace

Maximum hold

Modulation

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14.7.1 Transmitter Spurious Emissions Specifications
2.4 GHz Band Spurious Emissions
20 MHz Channel Spacing
Table 28. 2.4 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications
2G - 20 MHz BW

Spurious Emissions Level (dBm)

Emissions Frequency Range (MHz)Channel Power (dBm)

CH2442

1000-2000

21–50

2000-2400

21–40

2500-3000

21–40

3000-4000

21–39

4000-5000

21–24

5000-6000

21–48

6000-7000

21–49

7000-8000

21–13

8000-10000

21

–43

10000-12000

21

–52

12000-15000

21

–50

15000-20000

21

–49

5 GHz Band Spurious Emissions
20 MHz Channel Spacing
Table 29. 5 GHz Band, 20-MHz Channel Spacing TX Spurious Emissions Specifications
5G - 20 MHz BW

Spurious Emissions Level (dBm)

Emissions Frequency Range (MHz) Channel Power (dBm)

CH5180CH5500CH58251000-2000

19

–50

–51

–50

2000-3000

19

–48

–48

–49

3000-4000

19

–42

–43

–40

4000-5000

19

–42

–46

–48

5000-6000

19

–41

–40

–40

6000-7000

19

–48

–49

–47

7000-8000

19

–50

–49

–49

8000-10000

19

–53

–52

–53

10000-12000

19

–10

–13

–17

12000-15000

19

–51

–51

–51

15000-20000

19

–19

–19

–20

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40 MHz Channel Spacing
Table 30. 5 GHz Band, 40-MHz Channel Spacing TX Spurious Emissions Specifications
5G - 40 MHz BW
Emissions Frequency
Range (MHz)Spurious Emissions Level (dBm)

Channel Power (dBm)

CH5190m

CH5510m

CH5795m

1000-2000

19

–50

–52

–52

2000-3000

19

–49

–50

–49

3000-4000

19

–43

–42

–39

4000-5000

19

–42

–44

–48

5000-6000

19

–40

–40

–38

6000-7000

19

–48

–48

–48

7000-8000

19

–49

–48

–48

8000-10000

19

–52

–53

–53

10000-12000

19

–12

–15

–19

12000-15000

19

–51

–51

–51

15000-20000

19

–24

–22

–24

TypicalMaximum

Unit

2.4 GHz < f < 2.5 GHz

–75.5

–74.1

dBm

3.6 GHz < f < 3.8 GHz

–52.8

–50.9

dBm

5150 MHz < f < 5850 MHz

–57.7

–56.1

dBm

3.45 GHz < f < 3.9 GHz

–48.6

–47.6

dBm

14.7.2 Receiver Spurious Emissions Specifications
Table 31. 2G and 5G General Receiver Spurious Emissions
Band
2G
5G

Frequency Range

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15. Internal Regulator Electrical Specifications
15.1 Core Buck Switching Regulator
Note: Values in this data sheet are design goals and are subject to change based on device characterization results.
Note: Functional operation is not guaranteed outside of the specification limits provided in this section.
Table 32. Core Buck Switching Regulator (CBUCK) Specifications
Specification

Notes

Input supply voltage (DC)DC voltage range inclusive of disturbances.

PWM Mode switching frequency

CCM, load > 100 mA VBAT = 3.6 V.

PWM Output current–

Output current limit

Typ.

Max.

Unit

3.0

3.6

4.8a

V

–

4

–

MHz

–

–

550

mA

–

1400

–

mA

Programmable, 30 mV steps. Default = 1.35 V.

1.2

1.35

1.5

V

PWM Output voltage DC accuracy

Includes load and line regulation. Forced PWM Mode.

–4

–

4

%

PWM ripple voltage, static

Measure with 20 MHz bandwidth limit.
Static load. Max. ripple based on VBAT = 3.6 V, Vout = 1.35 V,
Fsw = 4 MHz,
2.2 μH inductor with min. effective L > 1.05 μH,
cap. + board total – ESR < 20 mΩ,
Cout > 1.9 μF, ESL<200 pH

–

7

20

mVpp

PWM Mode peak efficiency

Peak efficiency at 200 mA load.

78

86

–

%

PFM Mode efficiency

10 mA load current.

70

81

–

%

Start-up time from power down

VIO already ON and steady. Time from REG_ON rising edge
to CLDO reaching 1.2 V.

–

400

500

µs

External Inductor

0806 size, 2.2 µH, DCR = 0.11Ω,
ACR = 1.18Ω @ 4 MHz.

–

2.2

–

µH

External output capacitor

Ceramic, X5R, 0402, ESR <30 mΩ at 4 MHz, 4.7 µF ±20%,
6.3 V.

2.0b

4.7

10c

µF

External input capacitor

For SR_VDDBAT5V pin, ceramic, X5R, 0603, ESR < 30 mΩ
at 4 MHz, ±4.7 µF ±20%, 6.3 V.

0.67b

4.7

–

µF

Input supply voltage ramp-up time

0 to 4.3 V.

40

–

–

µs

Output voltage range

–

Min.

a. The maximum continuous voltage is 4.8 V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages ashigh as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.
c. Total capacitance includes those connected at the far end of the active load.

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15.2 3.3V LDO (LDO3P3)
Table 33. LDO3P3 Specifications
Specification
Input supply voltage, Vin

Notes

Min.

Typ.

Max.

Units

Min. = Vo + 0.2 V = 3.5 V dropout voltage requirement
must be met under maximum load for performance
specifications.

3.0

3.6

4.8a

V

–

0.001

–

450

mA

Output current
Nominal output voltage, Vo

Default = 3.3 V.

–

3.3

–

V

Dropout voltage

At max. load.

–

–

200

mV

Output voltage DC accuracy

Includes line/load regulation.

–5

–

+5

%

Quiescent current

No load.

–

–

85

µA

Line regulation

Vin from (Vo + 0.2 V) to 4.8 V, max. load.

–

–

3.5

mV/V

Load regulation

Load from 1 mA to 450 mA.

–

–

0.3

mV/mA

Power Supply Rejection Ratio(PSRR)

Vin ≥ Vo + 0.2 V, Vo = 3.3 V, Co = 4.7 µF,
Max load, 100 Hz to 100 kHz.

20

–

–

dB

LDO turn-on time

Chip already powered up.

–

160

250

µs

External output capacitor, Co

Ceramic, X5R, 0402, (ESR: 5 mΩ–240 mΩ),
± 10%, 10V.

1.0b

4.7

10

µF

External input capacitor

For LDO_VDDBAT5V pin (shared with band gap)
ceramic, X5R, 0402, (ESR: 30mΩ–200 mΩ), ± 10%,
10V. Not needed if sharing 4.7 µF VBAT capacitor with
SR_VDDBAT5V.

–

4.7

–

µF

a. The maximum continuous voltage is 4.8V. Voltages up to 6.0 V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages ashigh as 5.0 V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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15.3 CLDO
Table 34. CLDO Specifications
Specification
Input supply voltage, Vin

Notes

Min.

Typ.

Max.

Units

Min. = 1.2 + 0.15 V = 1.35 V dropout voltage requirement
must be met under maximum load.

1.3

1.35

1.5

V

–

0.2

–

350

mA

Output current
Output voltage, Vo

Programmable in 10 mV steps. Default = 1.2 V.

0.95

1.2

1.26

V

Dropout voltage

At max. load.

–

–

150

mV

Output voltage DC accuracy

Includes line/load regulation.

–4

–

+4

%

No load.

–

26

–

μA

200 mA load.

–

2.48

–

mA

Vin from (Vo + 0.15 V) to 1.5 V, maximum load.

–

–

5

mV/V

Load from 1 mA to 300 mA.

–

0.02

0.05

mV/mA

Power down.

–

10

40

μA

6

µA

Quiescent current
Line regulation
Load regulation
Leakage current

Bypass mode.

–

2

PSRR

@1 kHz, Vin ≥ 1.35 V, Co = 4.7 µF.

20–Start-up time of PMU

VIO up and steady. Time from the REG_ON rising edge to
the CLDO reaching 1.2V.

–

–

700

μs

LDO turn-on time

LDO turn-on time when the rest of the chip is up.

–

140

180

μs

3.76a

4.7

–

μF

–

1

2.2

μF

External output capacitor, Co

Total ESR: 5 mΩ–240 mΩ.

External input capacitor

Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.

dB

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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15.4 LNLDO
Table 35. LNLDO Specifications
Specification
Input supply voltage, Vin

Notes

Min.

Typ.

Max.

Units

Min. Vin = Vo + 0.15 V = 1.35 V (where Vo = 1.2 V) dropout
voltage requirement must be met under maximum load.

1.3

1.35

1.5

V

–

0.1

–

150

mA

Output current
Output voltage, Vo

Programmable in 25 mV steps. Default = 1.2 V.

1.1

1.2

1.275

V

Dropout voltage

At maximum load.

–

–

150

mV

Includes line/load regulation.

–4

–

+4

%

No load.

–

44

–

µA

Output voltage DC accuracy
Quiescent current

Max. load.

–

970

990

µA

Line regulation

Vin from (Vo + 0.1V) to 1.5 V, 150 mA load.

–

–

5

mV/V

Load regulation

Load from 1 mA to 150 mA.

–

0.02

0.05

mV/mA

Leakage current

Power-down.

–

–

10

µA

Output noise@30 kHz, 60–150 mA load Co = 2.2 µF.
@100 kHz, 60–150 mA load Co = 2.2 µF.

–

–

60
35

nV/Root Hz

PSRR@ 1kHz, Input > 1.35V, Co= 2.2 µF, Vo = 1.2 V.

20

–

–

dB

LDO turn-on time

LDO turn-on time when the rest of the chip is up.

–

140

180

µs

External output capacitor, Co

Total ESR (trace/capacitor): 5 mΩ–240 mΩ.

0.5a

2.2

4.7

µF

External input capacitor

Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ.

–

1

2.2

µF

a. Minimum capacitor value refe rs to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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15.5 BBPLL LDO
Table 36. BBPLL LDO Specifications
Parameter

Min.

Typ.

Max.

Units

Input supply voltage, Vin

Min. Vin= Vo + 0.15 V = 1.35 V (for Vo = 1.2 V).
The dropout voltage requirement must be met undermaximum load.

1.3

1.35

1.5

V

Output voltage, Vo

Programmable in 25 mV steps. Default = 1.2 V.

1.1

1.2

1.275

V

Dropout voltage

At max. load

–

–

150

mV

Output voltage DC accuracy

Includes line/load regulation.

–4

–

+4

%

Output current

Peak load = 80 mA, average = 35 mA

0.1

–

55

mA

No load

–

10

12

µA

55 mA load

–

550

570

µA

Quiescent current

Conditions and Comments

Line regulation

Vin from (Vo + 0.15 V) to 1.5 V; 200 mA load

–

–

5

mV/V

Load regulationload from 1mA to 200 mA; Vin ≥ (Vo + 0.15 V)

–

0.025

0.045

mV/mA

Powered down. Junction temperature is 85°C.

–

5

20

µA

Bypass Mode

–

0.2

1.5

µA

PSRR

@1 kHz, Vin ≥ Vo + 0.15 V, Co = 4.7 µF

20

–

–

dB

Start-up time of PMU

VIO up and steady. Time from REG_ON rising edge to CLDO
reaching 99% of Vo.

–

530

700

us

LDO turn-on time

The LDO turn-on time when the rest of the chip is up.

–

140

180

us

Inrush current

Vin = Vo + 0.15 V to 1.5 V, Co = 0.47uF, no load

–

60

70

mA

External Output capacitor, Co

Ceramic, X5R, size 0201, max. 6.3V, 20% tolerance

0.27

0.47

–

µF

External Input capacitor

Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.

–

1

–

µF

Leakage current

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16. System Power Consumption
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
Note: Unless otherwise stated, these values apply for the conditions specified in Table 18: “Recommended Operating Conditions and
DC Characteristics”.

16.1 WLAN Current Consumption
The tables in this subsection show the typical, total current used by the CYW43907. Current values may be measured with the APPS
core powered off. The first column of the table, the mode description, will state the power condition of the APPS core.
16.1.1 2.4 GHz Mode
Table 37. 2.4 GHz Mode WLAN Current Consumption
Mode

VBAT = 3.6V a(µA)

VDDIO =VDDIO_HIB = 3.3V a, b, c(µA)

Sleep Modes
Radio OFFd3

3

Sleep e, f

6160IEEE Power Save, DTIM=1, single RX, APPS powered down g

2180

160

IEEE Power Save, DTIM=3, single RX, APPS powered down h

680

160

IEEE Power Save, DTIM=9, single RX, APPS powered down

233

160

Continuous RX mode MCS7, HT20, 1SS, APPS powered up i, j

57,20060

CRS-HT20, APPS powered up k

55,20060

Continuous TX Mode 1 Mbps, APPS powered up l

325,000

60

Continuous TX Mode MCS7, HT20, 1SS, 1 TX, APPS powered up m

302,900

60

336,000

60

6

160

Active Modes

Ping Modes
Ping to associated access point l
Sleep
a. Typical silicon.
b. VIO is specified with all pins idle (not switching) and not driving any loads.
c. Excludes VDDIO_USB, VDDIO_RMII, VDDIO_I2S, and VDDIO_SD.
d. REG_ON is low or the device is in hibernation, and all supplies are present.
e. REG_ON is high. APPS domain is powered down. WLAN domain is in low-power state retention mode. Top level is powered up.
f. Inter-beacon current.
g. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
h. Beacon interval = 307.2 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
i. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.
j. Measured using packet engine test mode.
k. Carrier sense (CCA) when no carrier present.
l.

Duty cycle is 100%. TX power at chip output ~17.7 dBm.

m. Duty cycle is 100%. TX power at chip output ~15.2 dBm.

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16.1.2 5 GHz Mode
Table 38. 5 GHz Mode WLAN Current Consumption
Mode

VBAT = 3.6V a(µA)

VDDIO = VDDIO_HIB =3.3V a, b, c
(µA)

3

3

Sleep Modes
Radio OFFd
Sleep e, f

6

160

1390

160

IEEE Power Save, DTIM=3, single RX, APPS powered down h

470

160

IEEE Power Save, DTIM=9, single RX, APPS powered down

160

160

Continuous RX Mode MCS7, HT20, 1SS, APPS powered up i, j

72,40060

Continuous RX Mode MCS7, HT40, 1SS, APPS powered up i, j

84,70060

CRS-HT20, APPS powered up k

70,20060IEEE Power Save, DTIM=1, single RX, APPS powered down g

Active Modes

CRS-HT40, APPS powered up k

79,50060

Continuous TX mode MCS7, HT20, 1SS, 1 TX, APPS powered up l

312,000

60

Continuous TX mode MCS7, HT40, 1SS, 1 TX, APPS powered up m

309,000

60

Ping Modes
Ping to associated access point l
Sleep

327,000

60

6

160

a. Typical silicon.
b. VIO is specified with all pins idle (not switching) and not driving any loads.
c. Excludes VDDIO_USB, VDDIO_RMII, VDDIO_I2S, and VDDIO_SD.
d. REG_ON is low or the device is in hibernation, and all supplies are present.
e. REG_ON is high. APPS domain is powered down. WLAN domain is in low-power state retention mode. Top level is powered up.
f. Inter-beacon current.
g. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
h. Beacon interval = 307.2 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals.
i. Duty cycle is 100%. Carrier sense (CS) detect/packet receive.
j. Measured using packet engine test mode.
k. Carrier sense (CCA) when no carrier present.
l. Duty cycle is 100%. TX power at chip output ~13.9 dBm.
m. Duty cycle is 100%. TX power at chip output ~12.9 dBm.

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17. Interface Timing and AC Characteristics
17.1 Ethernet MAC (MII/RMII) Interface Timing
17.1.1 MII Receive Packet Timing
Figure 15 and Table 39 provide the MII receive packet timing.
Figure 15. MII Receive Packet Timing
t4 0 4t4 0 2
t4 0 1

t4 0 3RXC

RXDV

R X D [3 :0 ]Table 39. MII Receive Packet Timing Parameters
Parameter
t401
t402
t403

Description

Minimum

TypicalMaximum

Units

RXDV and RXD[3:0] to RXC rising setup time

10

–

–

ns

RXC clock period (10BASE-T Mode)

–

400

–

ns

RXC clock period (100BASE-TX Mode)

–

40

–

ns

RXC low/high time (10BASE-T Mode)

160

–

240

ns

RXC low/high time (100BASE-TX Mode)

16

–

24

ns

t404

RXDV and RXD[3:0] to RXC rising hold time

10

–

–

ns

–

Duty cycle

40

50

60

%

TypicalMaximumUnits

17.1.2 MII Transmit Packet Timing
Figure 16 and Table 40 provide the MII transmit packet timing.
Figure 16. MII Transmit Packet Timing

TXC
TXEN
T X D [3 :0 ]Table 40. MII Transmit Packet Timing Parameters
Parameter

Description

Minimumt405

TXC high to TXEN and TXD[3:0] valid

0

–

25

ns

t406

TXC high to TXEN and TXD[3:0] invalid (hold)

0

–

–

ns

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17.1.3 RMII Receive Packet Timing
Figure 17 and Table 41 provide the RMII receive packet timing.
Figure 17. RMII Receive Packet Timing

REF_CLKCRS_DVRXD[1]

0

0

0

0

0

0

0

0

0

0

0

0

0

1

X

X

X

X

X

X

0

RXD[0]

0

0

0

0

0

0

0

1

1

1

1

1

1

1

X

X

X

X

X

X

0

/J /

/K/

Preamble

SFD

Data

Table 41. RMII Receive Packet Timing
SymbolMinimum

TypicalMaximum

Unit

REF_CLK[1, 2] Cycle TimeParameter

–

–

20

–

ns

RXD[1:0], RXER, CRS_DV Output delay from REF_CLK rising

–

2

–

10

ns

Notes:
1. In 10 Mbps mode, there are ten REF_CLK periods per data period.
2. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering.

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17.1.4 RMII Transmit Packet Timing
Figure 18 and Table 42 provide the RMII transmit packet timing.
Figure 18. RMII Transmit Packet Timing

REF_CLKT X _E N

T XD[1]

0

0

0

0

0

0

0

0

0

0

0

0

0

1

X

X

X

X

X

X

0

T XD[0]

0

1

1

1

1

1

1

1

1

1

1

1

1

1

X

X

X

X

X

X

0

Preamble

S FD

Data

Table 42. RMII Transmit Packet Timing Parameters
Parameter
REF_CLK[4] Cycle Time

SymbolMinimum

TypicalMaximum

Unit

–

–

20

–

ns

TXEN, TXER, TXD[1:0][3] setup time to REF_CLK rising

TXEN_SETUP

4

–

–

ns

TXEN, TXER, TXD[1:0] hold time from REF_CLK rising

TXEN_HOLD

2

–

–

ns

Notes
3. TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted.
4. In 10 Mbps mode, there are ten REF_CLK periods per data period.

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17.2 I2S Master and Slave Mode TX Timing
Figure 19 and Table 43 provide the I2S Master mode transmitter timing.
Figure 19. I2S Master Mode Transmitter Timing
Tt RC

I2S_SCLKt HC = 0.35T
V

t LC = 0.35T

t htr = 0

V

H = 2.0V
L = 0.8V

t dtr = 0.8T

I2S_SDATO
and I2S_LRCK
T = Clock period.
Ttr = Minimum allowed clock period for transmitter.
T > Ttr.
tRC is only relevant for transmitters in Slave mode.

Figure 20 and Table 43 provide the I2S Slave mode receiver timing.
Figure 20. I2S Slave Mode Receiver Timing

T

I2S_SCLK

tHC = 0.35T
V

tLC = 0.35T
tsr = 0.2TV

H = 2.0V
L = 0.8V

thr = 0I2S_SDATAIand I2S_LRCK
T = Clock period.
Tr = Minimum allowed clock period for the transmitter.
T > Tr.

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Table 43. Timing for I2S Transmitters and Receivers
Transmitter
Parameter

ReceiverLower Limit

Upper Limit

Lower Limit

Minimum

Maximum

Minimum

Maximum

Minimum

Maximum

Ttr

–

–

–

Ttr

–

Clock period T
Slave Mode:
Clock high, tHC–

0.35Tr

–––

0.35TrClock low tLC–

0.35Tr

–––

0.35TrClock rise time, tRC––

0.15Ttr–––

Transmitter delay, tdtr

–

–

–

0.8T

–

–

Transmitter hold time, thtr

0

–

–

–

–

–

Receiver setup time, tsr

–

–

–

–

–

0.2Tr

Receiver hold time, thr

–

–

–

–

–

0

Table 44 provides the I2S_MCLK specification.
Table 44. I2S_MCLK Specification
Minimum

TypicalMaximum

Unit

Frequency range

Parameter

1

–

40

MHz

Frequency accuracy (with respect to the XTAL frequency)

–

1

–

ppb

Tuning resolution

–

50

–

ppb

Tuning range

–

1000

–

ppm

Tuning step size

–

–

10

ppm

Tuning rate

–

1

–

ppm/msBaseband jitter (100 Hz to 40 kHz)

–

–

100

ps rmsWideband jitter (100 Hz to 1 MHz)

–

–

200

ps rmsFigure 21 shows the I2S frame-level timing.
Figure 21. I2S Frame-Level Timing

1/fs
I2S_LRCLK

Left Channel

Right Channel

I2S_SCLK
1 clock
1

I/O Data

2

1 clock
3

MSB

Document Number: 002-14829 Rev. *L

n– 2 n–1

n

1
LSB

MSB

2

3

n–2 n–1n
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17.3 SDIO Interface Timing
17.3.1 SDIO Default-Speed Mode Timing
SDIO default-speed (DS) Mode timing is shown by the combination of Figure 22 and Table 45.
Figure 22. SDIO Bus Timing (DS Mode)
fPP
tWL

tWH

SDIO_CLK

tTHL

tTLH
tISU

tIH

Input

Output
tODLY

tODLY

(max)

(min)

Table 45. SDIO Bus Timinga Parameters (DS Mode)
Parameter

SymbolMinimum

TypicalMaximum

Unit

SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer mode

fPP

0

–

25

MHz

Frequency – Identification mode

fOD

0

–

400

kHz

Clock low time

tWL

10

–

–

ns

Clock high time

tWH

10

–

–

ns

Clock rise time

tTLH

–

–

10

ns

Clock low time

tTHL

–

–

10

ns

Input setup time

tISU

5

–

–

ns

Input hold time

tIH

5

–

–

ns

Output delay time – Data Transfer Mode

tODLY

0

–

14

ns

Output delay time – Identification Mode

tODLY

0

–

50

ns

Inputs: CMD, DAT (referenced to CLK)

Outputs: CMD, DAT (referenced to CLK)a. Timing is based on CL  40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.

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17.3.2 SDIO High-Speed Mode Timing
SDIO high-speed (HS) mode timing is shown by the combination of Figure 23 and Table 46.
Figure 23. SDIO Bus Timing (HS Mode)
fPP
tWL

tWH

50% VDD

SDIO_CLK
tTHL
tISU

tTLH
tIH

Input

OutputtODLY

tOH

Table 46. SDIO Bus Timinga Parameters (HS Mode)
Parameter

SymbolMinimum

TypicalMaximum

Unit

SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer Mode

fPP

0

–

50

MHz

Frequency – Identification Mode

fOD

0

–

400

kHz

Clock low time

tWL

7

–

–

ns

Clock high time

tWH

7

–

–

ns

Clock rise time

tTLH

–

–

3

ns

Clock low time

tTHL

–

–

3

ns

Input setup time

tISU

6

–

–

ns

Input hold time

tIH

2

–

–

ns

Inputs: CMD, DAT (referenced to CLK)

Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode

tODLY

–

–

14

ns

Output hold time

tOH

2.5

–

–

ns

Total system capacitance (each line)

CL

–

–

40

pF

a. Timing is based on CL  40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.

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17.3.3 SDIO Bus Timing Specifications in SDR Modes
Clock Timing
SDIO clock timing in the SDR modes is shown by the combination of Figure 24 and Table 47.
Figure 24. SDIO Clock Timing (SDR Modes)

tCLK

SDIO_CLK
tCR

tCF

tCR

Table 47. SDIO Bus Clock Timing Parameters (SDR Modes)
Parameter

Symbol–tCLK–
Clock duty cycle

Minimum

Maximum

Unit

Comments

40

–

ns

SDR12 mode

20

–

ns

SDR25 modetCR, tCF–

0.2 × tCLK

ns

CCARD = 10 pF

–

30

70

%

–

Device Input Timing
SDIO device input timing in the SDR modes is shown by the combination of Figure 25 and Table 48.
Figure 25. SDIO Bus Input Timing (SDR Modes)

SDIO_CLKtIS

tIH

CMD input
DAT[3:0] input

Table 48. SDIO Bus Input Timing Parameters (SDR Modes)
SymbolMinimum

Maximum

Unit

tIS

3.00

–

ns

CCARD = 10 pF, VCT = 0.975V

tIH

0.80

–

ns

CCARD = 5 pF, VCT = 0.975V

Document Number: 002-14829 Rev. *L

Comments

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Device Output Timing
SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of Figure 26 and Table 49.
Figure 26. SDIO Bus Output Timing (SDR Modes up to 50 MHz)t C LKS D IO _ C L K

t O D LYtOH

C M D in p u t
D A T [3 :0 ] in p u tTable 49. SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)
SymbolMinimum

Maximum

Unit

Comments

tODLY

–

14.0

ns

tCLK ≥ 20 ns CL= 40 pF

tOH

1.5

–

ns

Hold time at the tODLY (min.) CL= 15 pF

17.4 S/PDIF Interface Timing
The S/PDIF protocol embeds the clock and data within a stream of data using a Biphase Mark Code (BMC).
Figure 27 shows the S/PDIF Interface timing.
Figure 27. S/PDIF Interface Timing

C lo c k

D a ta
1

0

0

1

1

0

1

0

0

1

0

E n c o d e d (B M C )Figure 28 shows the S/PDIF data output timing.
Figure 28. S/PDIF Data Output TimingtC LK

S P D IF _ O U T
tC RDocument Number: 002-14829 Rev. *L

tC F

tC R

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Table 50 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 28).
Table 50. SPDIF Biphase Mark Code Timing Parameters
Parameter

SymbolMinimum

Maximum

Unit

Comments

–

tCLK

40

–

ns

192 kHz sample rate–tCR, tCF–

0.3 × tCLK

ns

–

–

30

70

%

–

Duty cycle

Table 51 provides the S/PDIF biphase mark code (BMC) sample rate and receiver clock frequency.
Table 51. SPDIF BMC Sample Rate and Receiver Clock Frequency
Parameter

SymbolMinimum

Maximum

Unit

Sampling frequency

fS

–

192

kHz

192 kHz sample rate maximum.

Component clock
frequency

fCLOCK–

25

MHz

Typical is 128 × fS, max is 192 × fS.
Clock is 2× the desired data rate or
2 × 192 kHz × 64 = 24.576 MHz.

Document Number: 002-14829 Rev. *L

Comments

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17.5 SPI Flash Timing
17.5.1 Read-Register Timing
Figure 29 shows the SPI flash extended and quad read-register timing.
Note: Figure 29: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile Configuration Register operation will output data starting fromthe least significant byte.
Figure 29. SPI Flash Read-Register Timing

Extended

0

7

8

9

10

11

12

13

14

15

C
LSB
DQ0

Command
MSB

DQ1

LSB
High-Z

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

MSB

Quad

0

1

2

3

C
LSB
DQ[3:0]CommandMSB

Document Number: 002-14829 Rev. *L

LSB
DOUT

DOUT

DOUT

Don’t care

MSB

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17.5.2 Write-Register Timing
Figure 30 shows the SPI flash extended and quad write-register timing.
Note: Figure 30:
1. All write-register commands except Write Lock Register are supported.
2. The waveform must be extended to 23 for extended write and to five for quad write register timing.
3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte.
Figure 30. SPI Flash Write-Register Timing

Extended

0

7

8

9

10

11

12

13

14

15

C
LSB

LSB
DQ0

Command

DIN

MSB

Quad

DIN

DIN

DIN

DIN

DIN

DIN

DIN

DIN

MSB

0

1

2

3

C
LSB
DQ[3:0]LSB
DINCommandMSB

Document Number: 002-14829 Rev. *L

DIN

DIN

MSB

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17.5.3 Memory Fast-Read Timing
Figure 31 shows the SPI flash extended and quad memory fast-read timing.
Note: Figure 31:
1. 24-bit addressing is used, so A[MAX] = A[23] and A[MIN] = A[0].
2. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1).
3. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Figure 31. Memory Fast-Read Timing
Extended

0

7

8

Cx

C
A[MIN]

LSB
Command

DQ0
MSB
DQ1

A[MAX]

LSB
DOUT

High-Z

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

DOUT

MSB
Dummy Cycles

Quad

0

1

2

Cx

C
LSB

A[MIN]LSB
DQ[3:0]CommandMSB

DOUTA[MAX]DOUT

MSB
Dummy Cycles

Document Number: 002-14829 Rev. *L

DOUT

Don’t care

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17.5.4 Memory-Write Timing
Figure 32 shows the SPI flash extended and quad memory-write (Page Program) timing.
Note: Figure 32:
1. For an extended SPI protocol, Cx = 7 + (A[MAX] + 1).
2. For a quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
Figure 32. Memory-Write Timing

Extended

0

7

8

Cx

C
LSB

A[MIN]LSB

DIN

Command

DQ0
MSB

Quad

A[MAX]

0

1

DIN

DIN

DIN

DIN

DIN

DIN

DIN

DIN

MSB

2

Cx

C
LSB

A[MIN]LSB
DQ[3:0]CommandMSB

Document Number: 002-14829 Rev. *L

DIN
A[MAX]

DIN

DIN

MSB

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17.5.5 SPI Flash Parameters
The combination of Figure 33 and Table 52 provide the SPI flash timing parameters.
Figure 33. SPI Flash Timing Parameters Diagram
T_DVCHClock (C)T_CHDX

Data in (DIN)(DQ1 in Serial [Extended] mode)(DQ[3:0] in Quad mode)
T_CLQX

Data out (DOUT)(DQ0 in Serial [Extended] mode)(DQ[3:0] in Quad mode)
T_CLQV

Table 52. SPI Flash Timing Parameters
Parameter

Description

Minimum

Maximum

Units

T_DVCH

Data setup time

2

–

ns

T_CHDX

Data hold time

3

–

ns

T_CLQX

Output hold time

1

–

ns

T_CLQV

Output valid time (with a 10 pF load)

–

5

ns

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17.6 USB PHY Electrical Characteristics and Timing
17.6.1 USB 2.0 and USB 1.1 Electrical and Timing Parameters
Table 53 provides electrical and timing parameters for USB 2.0.
Table 53. USB 2.0 Electrical and Timing Parameters
Parameter

SymbolMinimum

TypicalMaximum

Units

Conditions

Baud rate

BPS

–

480

–

Mbps

–

Unit interval

UI

–

2083

–

ps

–

VHSDI

300

–

–

mV

Receiver – HS Mode
Differential input voltage sensitivity
Input common mode voltage range

VHSCM

Static | VIDP – VIDN |

–50

–

500

mV

–

THSRX

–0.15

–

0.15

UI

–

RIN

40.5

45

49.5

Ω

Output high voltage

VHSOH

360

400

440

mV

Static condition

Output low voltage

VHSOL

–10

0

10

mV

Static condition

Output rise time

THSR

500

–

–

ps

10% to 90%

Output fall time

THSF

500

–

–

ps

90% to 10%

Receiver jitter tolerance
Input impedance

Single ended

Transmitter – HS Mode

Transmitter jitter THSTX

–0.05

–

0.05

UI

Transmit output jitter

Output impedance

RO

40.5

45

49.5

Ω

Single ended

Chirp-J output voltage (differential)

VCHIRPJ

700

–

1100

mV

HS termination disabled. 1.5kΩ ± 5% PU resistor
connected.

Chirp-K output voltage (differential)

VCHIRPK

–900

–

–500

mV

HS termination disabled. 1.5kΩ ± 5% PU resistor
connected.

Note: Refer to Section 7 of the USB 2.0 specification for more information on the receiver eye diagram template.

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Table 54 provides electrical and timing parameters for USB 1.1.
Table 54. USB 1.1 FS/LS Electrical and Timing Parameters a
Parameter

SymbolValue
Minimum

TypicalMaximum

Unit

Condition

Baud Rate
FS

BPS

–

12

–

Mbps

–

LS

BPS

–

1.5

–

Mbps

–

Unit Interval
FS

UI

–

83.33

–

ns

–

LS

UI

–

666.67–ns–

Differential input sensitivity

VFSDI

200

–

–

mV

Input common mode range

ReceiverStatic |VIDP – VIDN |

VFSCM

0.8

–

2.5

V

–

Input impedance

ZIN

300

–

–

kΩ

–

Input high voltage

VFSIH

2.0

–

–

V

StaticInput low voltage

VFSIL

–

–

0.8

V

StaticOutput high voltage

VFSOH

2.8

–

–

V

StaticOutput low voltage

VFSOL

–

–

0.3

V

StaticOutput rise/fall time for fast speed

TR,TF

4

–

20

ns

10 to 90%

TR,TF

75

–

300

ns

10 to 90%

–2

–

2

ns

Transmitter

Output rise/fall time for low speed
Low-speed jitter

FSTXLSTX

–25

–

25

ns

–

Output impedance

RO

28

–

44

Ω

Single ended

Fast-speed jitter–a. For more details, refer to the USB 1.1 Specification.

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17.6.2 USB 2.0 Timing Diagrams
Figure 34 shows the important timing parameters associated with a post-reset transition to HS operation.
Figure 34. USB 2.0 Bus Reset to HS Mode Operation

40 to 60 μs< 100 μs
DP

100 to 500 μs

Idle

HS Data
HighSpeed
Chirp

DM

DeviceK-ChirpIdle
3 to 3.125 ms

HS Data> 1.0 ms
100 to875 μs< 7 ms> 10 ms

Start of
Reset

Start of Host
(Hub) Chirp

Device Goes
into FullSpeed Mode

End of Host
(Hub) Chirp

End ofReset

Device Tests forSingle-Ended Zero
(SE0) State

Figure 35 shows the USB 2.0 HS Mode transmit timing.
Figure 35. USB 2.0 HS Mode Transmit Timing
96 bits

DP/DM

Latency = 42 bits

CLK60

TXDATA

PID

B0

B1

TXVALIDTXREADYXVERSEL00

OPMODE

00

TERMSEL0

TX driver is enabled here.

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Figure 36 shows the USB 2.0 HS Mode receive timing.
Figure 36. USB 2.0 HS Mode Receive Timing
Latency = 72 bits
64 bits
DP/DM

CLK60

RXACTIVE

RXVALID

B0

RXDATAXVERSEL00

OPMODE

00

TERMSEL

0Document Number: 002-14829 Rev. *L

B1

B2

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18. Power-Up Sequence and Timing
18.1 Sequencing of Reset and Regulator Control Signals
The CYW43907 has two signals that allow the host to control power consumption by enabling or disabling the internal regulator blocks.
These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various
operational states (see Figure 37 and Figure 38). The timing values indicated are minimum required values; longer delays are also
acceptable.
18.1.1 Description of Control Signals■

REG_ON: Used by the PMU to power-up the CYW43907. It controls the internal CYW43907 regulators. When this pin is high, theregulators are enabled and the device is out of reset. When this pin is low the regulators are disabled.

HIB_REG_ON_IN: Used by the Hibernation (HIB) block to power up the internal CYW43907 regulators. If the HIB_REG_ON_IN
pin is low, the regulators are disabled. For the HIB_REG_ON_IN pin to work as designed, HIB_REG_ON_OUT must be connected
to REG_ON.
Notes:
1. The CYW43907 has an internal POR circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO
have both passed the POR threshold.
2. The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up before or at the same time as
VDDIO. VDDIO should not be present first or be held high before VBAT is high.
■

18.1.2 Control Signal Timing Diagrams
Figure 37. REG_ON = HIGH, No HIB_REG_ON_OUT Connection to REG_ON
3 2 .6 7 8 k H z
S le e p C lo c k
VBAT

V D D IO
> 2 S le e p C y c le s
R EG _O N

H IB _ R E G _ O N _ IN

Figure 38. HIB_REG_ON_IN = HIGH, HIB_REG_ON_OUT Connected to REG_ON

32.678 kHz
Sleep Clock
VBAT

VDDIO
> 2 Sleep Cycles
HIB_REG_ON_IN

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19. Thermal Information
19.1 Package Thermal Characteristics
Table 55. Package Thermal Characteristicsa
Characteristic

WLCSPJA (°C/W) (value in still air)JB (°C/W)
JC (°C/W)

33.74

JT (°C/W)
JB (°C/W)

5.86
11.52

Maximum Junction Temperature Tj (°C)

116.7

Maximum power dissipation (W)

1.38

5.5
1.74

a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7. Air velocity is 0 m/s.

19.2 Junction Temperature Estimation and PSIJT Versus THETAJC
Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using

the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power isdissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom
and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation
for calculating the device junction temperature is:
TJ = TT + P x JT
Where:■

TJ = Junction temperature at steady-state condition (°C)■

TT = Package case top center temperature at steady-state condition (°C)■

P = Device power dissipation (Watts)■

JT = Package thermal characteristics; no airflow (°C/W)

19.3 Environmental Characteristics
For environmental characteristics data, see Table 16: “Environmental Ratings”.

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20. Mechanical Information
Figure 39. WLCSP Package

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

21. Ordering Information
Package

Description

Operating Ambient
Temperature

4.583 mm x 5.533 mm, 316-pin WLCSP––30°C to +85°C

Part Number
CYW43907KWBG

Note: Add a "T" suffix to the part number to order in Tape and Reel"

22. Additional Information
22.1 Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in
Cypress documents, go to: http://www.cypress.com/glossary.
.

Term

Term

Description

Description

AES

Advanced Encryption Standard

LCU

AES-CTR

Advanced Encryption Standard-Counter ModeLDO

low drop-out

AHB

advanced high-performance bus

MIB

Management Information Base

ALU

Arithmetic logic unit

OFDM

Orthogonal Frequency Division Multiplexing

APB

advanced peripheral bus

PDM

pulse density modulation

APU

audio processing unit

PLL

phase locked loop

CBC-MAC

Cipher Block Chaining Message Authentication
Code

POR

power-on reset

CCK

Complementary Code Keying

CCM

Counter with Cipher block chaining Message
authentication code

CSC

Cypress Serial Control

CTS

Clear to Send

DMA

direct memory access

DSSS

Direct Sequence Spread Spectrum

EBI

external bus interface

HCI

Host Control Interface

HVhigh voltage

IDC

initial digital calibration

IRQ

interrupt request

JTAG

Joint Test Action Group

Document Number: 002-14829 Rev. *Llink control unit

RC oscillator A resistor-capacitor oscillator is a circuitcomposed of an amplifier, which provides theoutput signal, and a resistor-capacitor network,
which controls the frequency of the signal.
RMII

Reduced Media Independent Interface

RTS

Request to Send

RX/TX

receive, transmit

SDIO

Secure Digital Input Output

SPI

serial peripheral interface

SWD

serial wire debug

TXOP

Transmit Opportunity

UART

universal asynchronous receiver/transmitterWD

watchdog

WEP

wired equivalent privacy

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PRELIMINARYCYW43907

22.2 References
The references in this section may be used in conjunction with this document.
Note: Cypress provides customer access to technical documentation and software through its Customer Support Portal (CSP) andDownloads and Support site (see IoT Resources).
Document (or Item) Name
1. USB 2.0 specification

Sourcewww.usb.org

22.3 IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for yourdesign, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website(https://community.cypress.com/)

22.4 Errata
1. The RTC block has been deprecated from this datasheet in revision *A and later. This block is used by Cypress for internal
testing/validation/verification and is not intended for customers to use.
2. The details of the SPI hardware blocks were missing from this datasheet till revision *H. Revision *I adds this in section 5.12.SPI
Note that the SPI hardware blocks can only support a hold time of 25 ns and a fixed SPI mode (CPHA=0, CPOL = 0). For slavesthat require higher hold times or a different mode a bit banging based SPI driver is recommended.
3. The clock for the SPI Flash block needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures.
The throughput of the SPI Flash block is therefore restricted to ~13 MBps for Quad mode and ~3 MBps for single mode. (Added
in Rev *J).
4. USB Host and USB Device functionality require the WLAN domain to be powered on to ensure that USB transactions are completed successfully. Note that though WLAN domain is powered on the radios can be clock gated.
5. The SDIO device mode has been deprecated from this datasheet in Rev *F and beyond. Cypress's WICED® SDK does not provide the drivers for the SDIO device mode functionality. SDIO device mode block is used by Cypress for internal testing/validation/verification and is not intended for customers to use.

Document Number: 002-14829 Rev. *L

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PRELIMINARYCYW43907

Document History Page
Document Title: CYW43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14829
Revision

ECN

Submission
Date

**

-

11/03/2014

43907-DS100-R
Initial release*A-

03/10/2015

43907-DS101-R
See the revision history of the applicable release.

*B-

10/15/2015

43907-DS102-R

Description of Change

Updated:Figure 3: “Typical Power Topology (Page 1 of 2)”.
Table 3: “Crystal Oscillator and External Clock — Requirements and Performance”“Transmit Path”.
Figure 14: “Radio Functional Block Diagram”.
“Calibration”.
Table 17: “Strapping Options”.
Table 23: “ESD Specifications”.
Table 24: “Recommended Operating Conditions and DC Characteristics”.
“Introduction”.
Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 32: “WLAN 5 GHz Receiver Performance Specifications”.
Table 33: “WLAN 5 GHz Transmitter Performance Specifications”.
Section 18: “System Power Consumption”
Table 56: “SDIO Bus Input Timing Parameters (SDR Modes)”.
Table 64: “Package Thermal Characteristics”.
*C-

11/03/2015

43907-DS103-R

Updated:Table 21: “Absolute Maximum Ratings”.
Table 24: “Recommended Operating Conditions and DC Characteristics”
Table 30: “WLAN 2.4 GHz Receiver Performance Specifications”
Table 31: “WLAN 2.4 GHz Transmitter Performance Specifications”.
Table 32: “WLAN 5 GHz Receiver Performance Specifications”.
Table 33: “WLAN 5 GHz Transmitter Performance Specifications”.
*D-

03/12/2016

43907-DS104-R

Updated:General edits*E

5525655

11/17/2016

Added Cypress Part Numbering Scheme and Mapping Table
Updated to Cypress template.

*F

555359001/17/2017

Updated: Two SPI master interfaces with operation up to 24 MHz. in page 5.

*G5730057

05/10/2017

Updated Cypress Logo and Copyright.

07/14/2017

Replaced BSC to CSC throughout the datasheet.
Updated Figure 1, Figure 2, Table 4, Table 13.
Removed 3.3 Frequency Selection.
Updated 5.9 SPI Flash:- Replaced Quad I/O, which Provides increased throughput to 40 MB/s to Increased
Throughput to 40 MBps in Quad-mode or upto 10 MBps in single Mode.
Added Footnote for Table 13.
Updated Contents in the Table 28, Table 29, Table 30.
Updated Table 17 on page 49.

*H5812137

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PRELIMINARYCYW43907

Document Title: CYW43907 WICED™ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor
Document Number: 002-14829
Revision

*I

*J

ECN

5954959

5999198

Submission
Date

Description of Change

11/02/2017

Added SPI section.
Added a Note: “The SPI blocks can be re-purposed as I2C, however the WICED SDK
does not support this. Certain I2C features may be unavailable when using the SPI blocks
as I2C. Therefore Cypress recommends using the the CSC blocks or a bit banging I2C
driver over GPIOs instead.” below Table 10 on page 35.
Added a 22.4.Errata section.
Replaced BCS to CSC throughout the document.

12/22/2017

Updated Revisions details in the section 22.4.Errata.
Updated Note “Note that the clock needs to be constrained to ~26.67MHz for reliable
operation at high operating temperatures. The throughput of the SPI Flash block istherefore restricted to ~13 MBps for Quad mode and ~3 MBps for single mode” for
5.9.SPI Flash.
Replaced “ARM Cortex-R4 clocked at 160 MHz (in 1× mode) or up to 320 MHz (in 2×mode)” with “The APPS ARM Cortex-R4 core can be clocked at 60 MHz, 80 MHz, 120
MHz, 160 MHz or 320 MHz” in the Features section.
Updated the URL “www.usb.org” to “http://www.usb.org/developers/docs/usb20_docs/
usb_20_020718.zip”.
Updated Figure 37 on page 87 and Figure 38 on page 87.
Removed RTC from Figure 1 on page 2.
Removed Proprietary Protocols from Standards Compliance section.
Added "Note: Add a "T" suffix to the part number to order in Tape and Reel" below
Ordering Information table.
Updated section SDIO 3.0 - Host Mode.
Interchanged the description of GPIO_7 and GPIO_11 in Table 11.
Updated Table 26.
Updated the link for USB 2.0 and USB 1.1 as “http://www.usb.org/developers/docs/
usb20_docs/usb_20_020718.zip”.
Added Acronym table in Acronyms and Abbreviations section.
Added in the 22.4.Errata section: 4. USB Host and USB Device functionality require the
WLAN domain to be powered on to ensure that USB transactions are completed
successfully. Note that though WLAN domain is powered on the radios can be clockgated.
5. The SDIO device mode has been deprecated from this datasheet in Rev *K andbeyond. Cypress's WICED SDK does not provide the drivers for the SDIO device mode
functionality. SDIO device mode block is used by Cypress for internal testing/validation/verification and is not intended for customers to use”.

*K

6279518

08/16/2018*L7109428

03/23/2021

Document Number: 002-14829 Rev. *L

Removed Cypress Part Numbering Scheme.
Updated Features and IEEE 802.11™ a/b/g/n PHY.

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PRELIMINARYCYW43907
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cypress.com/wireless© Cypress Semiconductor Corporation, 2014-2021. This document is the property of Cypress Semiconductor Corporation, and Infineon Technologies company, and its affiliates (“Cypress”). This
document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States andother countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the
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externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWAREOR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, andother medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the HighRisk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any
use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates, and its directors, officers, employees, agents, distributors, andassigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising fromany use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to thelimited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance
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Cypress, the Cypress logo, and combinations thereof, WICED, ModusToolBox, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress or a subsidiaryof Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14829 Rev. *L

Revised March 23, 2021

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