QN908x
Ultra low power Bluetooth 5 system-on-chip solution
Rev. 1.3 — 6 January 2021

Product data sheet

1. Introduction
QN908x is an ultra low power Bluetooth Low Energy wireless MCU with on-chip memory,
USB 2.0 full-speed compliant device interface, and 16-bit ADC for Bluetooth Smartapplications.
QN9080 integrates a 32-bit ARM Cortex-M4F core with Bluetooth Low Energy (v5.0)
compliant radio, link controller, host stack and GATT profiles. The 32-bit ARM Cortex-M4F
MCU and on-chip memory provides additional signal processing and scope to run
applications for a true single-chip Bluetooth Low Energy (v5.0) solution.
The QN908x uses a multi-layer AHB matrix to connect the ARM Cortex-M4 buses andother bus masters to peripherals in a flexible manner. It optimizes performance byallowing peripherals that are on different slave ports of the matrix to be accessed
simultaneously by different bus masters.

2. General description
The QN908x is a single chip, 1.6 mW peak power, high performance Bluetooth Low
Energy SoC platform. It facilitates the development of end products such as wearables,
health, and sport and fitness trackers. The end products also include retail beacons,connected smart home appliances, smart remote controls, HID devices, asset trackers,
and home automation.
QN9080 provides single-chip solution for Bluetooth Smart applications by integrating aBluetooth Low Energy (v5.0) compliant radio, link controller, host stack and GATT profiles.
The integrated 32-bit ARM Cortex-M4F MCU with on-chip flash memory and a mix ofanalogue and digital peripherals provides the most efficient data fusion engine. The
feature makes it a superior solution for applications requiring significant sensor fusion
computation.
Additional system features include a fully integrated DC-to-DC converter, LDO, low-power
sleep timer, battery monitor, high resolution ADC, and GPIO. These features reduceoverall system cost and size.
The QN908x operates with a power supply range of 1.62 V to 3.6 V. The best in-classactive current, with ultra-low power sleep modes, give excellent battery life allowing
operation from a coin cell battery.

NXP reserves the right to change the production detail specifications as may be required topermit improvements in the design of its products.

QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

3. Features and benefits True single-chip Bluetooth Low Energy (v5.0) SoC solution
 Integrated Bluetooth LE radio, protocol stack and application profiles
 Supports central and peripherals roles
 Supports master/slave concurrency
 Supports 16 simultaneous links
 Supports secure connections
 Supports data packet length extension
 Wifi/Bluetooth LE coexistence interface
 48-bit unique bluetooth device address
 RF 95dBm RX sensitivity in 1Mbps mode, -92dBm RX sensitivity in 2Mbps mode
(LDO mode) 94dBm RX sensitivity in 1Mbps mode, -91.5dBm RX sensitivity in 2Mbps mode
(DC-to-DC converter mode) Fast and reliable RSSI in 1dB step
 TX output power from 20 dBm to 2 dBm
 Single-ended RF port with integrated balun
 Generic FSK modulation with programmed data rate from 250Kbps to 2Mbps
 Compatible with worldwide radio frequency regulations
 Very low power consumption
 Single 1.62 V to 3.6 V power supply
 Integrated DC-to-DC buck converter and LDO
 1.0 A power-down 1 mode, to wake up by GPIO
 2.5 A power-down 0 mode, to wake up by 32 kHz sleep timer, RTC and GPIO
 3.5 mA RX current with DC-to-DC convertor enabled at 3 V supply in 1Mbps mode
 5.0 mA RX current with DC-to-DC convertor enabled at 3 V supply in 2Mbps mode 3.5 mA TX current @0 dBm TX power with DC-to-DC converter enabled at 3 V
supply in both 1Mbps and 2Mbps mode
 ARM Cortex-M4 core (version r0p1)
 ARM Cortex-M4 processor, running at a frequency of up to 32 MHz
 Floating Point Unit (FPU) and Memory Protection Unit (MPU) ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC)
 Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,
and four watch points, including serial wire output for enhanced debug capabilities
 System tick timer
 On-chip memory
 512 kB on-chip flash program memory and 2 kB page erase and write 128 kB SRAM
 256 kB ROM
 ROM API support
 Flash In-System Programming (ISP) Serial interfaces Four Flexcomm serial peripherals
QN908x

Product data sheet

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Rev. 1.3 — 6 January 2021

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

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





QN908x

Product data sheet

 USART protocol supported by Flexcomm0, USART and I2C by Flexcomm1, SPI
and I2C by Flexcomm2, and SPI by Flexcomm3
 Each Flexcomm includes a FIFO I2C-bus interfaces support fast mode and with multiple address recognition andmonitor mode USB 2.0 (full speed) device interface
 Two quadrature decoders
 SPI Flash Interface (SPIFI) uses a SPI bus superset with four data lines to accessoff-chip quad SPI flash memory at a much higher rate than is possible using
standard SPI or SSP interfaces
 Supports SPI memories with 1 or 4 data lines
Digital peripherals
 DMA controller with 20 channels, able to access memories and DMA capable
peripherals
 Up to 35 General Purpose Input Output (GPIO) pins, with configurable pull-up or
pull-down resistors
 GPIO registers are located on the AHB for fast access 32 GPIOs can be selected as Pin INTerrupts (PINT), triggered by rising, or falling
input edges
 AES-128 security coprocessor Random Number Generator (RNG)
 CRC engine
 Fusion Signal Processor (FSP) for data fusion and machine learning algorithms
resulting in low power consumption compared to software processing
Analog peripherals
 16-bit ADC with 8 external input channels, with sample rates of up to 32k sample
per second, and with multiple internal and external trigger inputs
 Integrated temperature sensor, connected to one internal dedicated ADC channel
 Integrated battery monitor connected to one internal dedicated ADC channel
 General-purpose 8-bit 1M sample per second DAC
 Integrated capacitive sense up to 8 channels, able to wake up the MCU from low
power states.
 Two ultra low-power analog comparators, able to wake up the MCU from low powerstates.
Timers Four 32-bit general-purpose timers or counters, support capture inputs andcompare outputs, PWM mode, and external count input
 Sleep timer, which can work in power-down mode and wake up MCU
 32-bit Real Time Clock (RTC) with 1 second resolution running in the always-on
power domain; can be used for wake-up from all low power modes including
power-down Watchdog Timer.
 SC Timer or PWM.
Clock generation
 32 MHz internal RC oscillator, which can be used as a system clock

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Rev. 1.3 — 6 January 2021

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

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

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QN908x

Product data sheet 16 MHz or 32 MHz crystal oscillator, which can be used as a system and RF
reference 32 kHz on-chip RC oscillator 32.768 kHz crystal oscillator
Power control
 Programmable Power Management Unit (PMU) to minimize power consumption
 Reduced power modes: sleep, and power-down
 Power-On Reset (POR)
 Brown-Out Detection (BOD) with separate thresholds for interrupt and forced reset
Single power supply 1.62 V to 3.6 V
Operating temperature range 40 °C to +85 °C
Available as 6 6 HVQFN48 and 3.28 3.20 mm WLCSP packages

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

4. Ordering information
Table 1.

Ordering information

Type number

Package
Name

Description

Version

QN9080

HVQFN48plastic thermal enhanced very thin quad flat package; no leads; 48 terminals;
body 6 6 0.85 mm

SOT778-7

QN9083WLCSP47

wafer level chip-scale package; 47 bumps; 3.28 3.20 0.365 mm, 0.40 mm
pitch

SOT1882-1

4.1 Ordering options
Table 2.

Ordering options

Type number

Device orderpart number

Siliconrevision[1]Flash (kB) Total SRAM(kB)

Cortex-M4
with FPUFSP

USB FS GPIO

QN9080

QN9080CHN

C

512

128

1

1

1

35

QN9080DHN

D

512

128

1

1

1

35

QN9083CUK

C

512

128

1

1

1

28

QN9083DUK

D

512

128

1

1

1

28

QN9083[1]

For details of Silicon revision, please refer to Errata sheet.

5. Marking

Fig 1.

HVQFN48 package marking

Fig 2.

WLCSP47 package marking

The HVQFN package has the following top-side marking:• Line A: “9080” for QN9080• Line B1: xxxxxx• Line B2: xxxx
• Line C: xxYYWW[R]– YY: year code, 17 for 2017
– WW: week code
– R = Chip revision
QN908x

Product data sheet

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Rev. 1.3 — 6 January 2021

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

The WLCSP package has the following top-side marking:• Line A: “9083”• Line B1: xxxxxx• Line B2: xxWW
– WW: week code

• Line C: YY[R]x– YY: year code, 17 for 2017
– R = Chip revision
Table 3.

QN908x

Product data sheet

Device revision table

Revision identifier (R)Revision description‘D’

Current revision‘C’

Second metal fix revision

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

6. Block diagram

Fig 3.

QN908x block diagram

QN908x

Product data sheet

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

7. Pinning information
7.1 Pinning

Fig 4.

QN908x

Product data sheet

HVQFN48 pin configuration

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Fig 5.

QN908x

Product data sheet

WLCSP pin configuration

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

7.2 Pin description
In QN908x, each pin can support up to eight different digital or analog functions, including
General Purpose Input Output (GPIO).
Table 4.

Pin description

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA00

GPIOA0I/O

general-purpose digital input output pin

ADC0

AI

ADC external input 0

PA01

PA02

PA03

PA04

11

10

9

8

7

QN908x

Product data sheet

6B

6A

-

-

5B

PU

PU

PU

PU

PU

SCT0_OUT0O

SCTimer output 0

CTIMER0_CAP0

I32-bit CTimer 0 capture input 0

FC0_RTS

I/O

flexcomm 0: USART RTS

FC2_SSEL3

I/O

flexcomm 2: SPI SSEL3

WLAN_TXI

WLAN active high TX active indicator forcoexistence

GPIOA1

I/O

general-purpose digital input output pin

ADC1

AI

ADC external input 1

SCT0_OUT1OSCTimer output 1

CTIMER0_CAP1

I32-bit CTimer 0 capture input 1

FC0_CTS

I/O

flexcomm 0: USART CTS

FC2_SSEL2

I/O

flexcomm 2: SPI SSEL2

WLAN_RXI

WLAN active high RX active indicator forcoexistence

GPIOA2

I/O

general-purpose digital input output pin

QDEC0_AI

quadrature decoder 0 input channel A

SCT0_OUT2O

SCTimer output 2

CTIMER0_MAT0O32-bit CTimer 0 match output 0R

I/O

reserved

FC2_SCL_SSEL1

I/O

flexcomm 2: I2C SCL, SPI SSEL1

RFE_RX_ENO

RX enable for external RF front-end

GPIOA3

I/O

general-purpose digital input output pin

QDEC0_BI

quadrature decoder 0 input channel B

SCT0_OUT3O

SCTimer output 3

CTIMER0_MAT1

O32-bit CTimer 0 match output 1

RO

reserved

FC2_SDA_SSEL0

I/O

flexcomm 2: I2C SDA, SPI SSEL0

RFE_TX_ENO

TX enable for external RF front-end

GPIOA4

I/O

general-purpose digital input output pin

ADC2

AI

ADC external input 2

SCT0_OUT4O

SCTimer output 4

CTIMER0_MAT0O32-bit CTimer 0 match output 0

FC0_TXD

I/O

flexcomm 0: USART TXD

FC2_SDA_MOSI

I/O

flexcomm 2: I2C SDA, SPI MOSISPIF_IO0

I/O

data bit 0 for the SPI flash interface

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA05

GPIOA5

I/O

general-purpose digital input output pin

ADC3

AI

ADC external input 3

SCT0_OUT5O

SCTimer output 5

CTIMER0_MAT1

O32-bit CTimer 0 match output 1

FC0_RXD

I/O

flexcomm 0: USART RXD

PA06

PA07

PA08

PA09

6

5

4

46

45

QN908x

Product data sheet

5A

4B

3B

2B

1B

PU

PU

PU

PU

PU

FC2_SCL_MISO

I/O

flexcomm 2: SCL, SPI MISOSPIF_IO1

I/O

data bit 1 for the SPI flash interface

GPIOA6

I/O

general-purpose digital input output pin

ADC_EX_CAP

Aconnected with ADC external capacitor

SCT0_OUT3O

SCTimer output 3

CTIMER0_MAT2

O32-bit CTimer 0 match output 2

FC1_RTS_SCL

I/O

flexcomm 1: USART RTS, I2C SCL

BLE_PTI0

O

BLE packet traffic information bit 0

SPIFI_CLKO

clock output for the SPI flash interface

GPIOA7

I/O

general-purpose digital input output pin

ADC_VREFIAI

ADC external reference voltage input

SCT0_OUT2O

SCTimer output 2

CTIMER1_CAP0

I

timer 1 input capture 0

FC1_CTS_SDA

I/O

flexcomm 1: USART CTS, I2C SDA

BLE_PTI1

O

BLE packet traffic information 1

SPIFI_CSN

O

active low chip select output for the SPI flash
interface

GPIOA8

I/O

general-purpose digital input output pin

ADC4

AI

ADC external input 4

SCT0_IN0I

SCTimer input 0

CTIMER1_CAP1

I

timer 1 input capture 1

FC1_TXD_SCL

I/O

flexcomm 1: USART TXD, I2C SCL

BLE_PTI2

O

BLE packet traffic information 2

SPIFI_IO2

I/O

data bit 2 for the SPI flash interface

GPIOA9I/O

general-purpose digital input output pin

ADC5

AI

ADC external input 5

SCT0_IN1I

SCTimer input 1

CTIMER1_MAT0O32-bit CTimer 1 match output 0

FC1_RXD_SDA

I/O

flexcomm 1: USART RXD, I2C SDA

BLE_PTI3

O

BLE packet traffic information bit 3

SPIFI_IO3

I/O

data bit 3 for the SPI flash interface

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QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA10

GPIOA10

general-purpose digital input output pin

PA11

PA12

PA13

PA14

44

43

42

32

31

QN908x

Product data sheet

2C

2D

-

-

5G

PU

PU

PU

PU

PU

I/O

ADC6

AI

ADC external input 6

SCT0_IN2I

SCTimer input 2

CTIMER1_MAT1

O32-bit CTimer 1 match output 1

FC1_SCK

I/O

flexcomm 1: USART clock

ACMP0_OUT

O

analog comparator 0 output

BLE_TXO

BLE transmit indicator for coexistence

GPIOA11

I/O

general-purpose digital input output pin

ADC7

AI

ADC external input 7

SCT0_IN3I

SCTimer input 3

CTIMER1_MAT2

O32-bit CTimer 1 match output 2

FC2_SSEL2

I/O

flexcomm 2: SPI SSEL2

ACMP1_OUT

O

analog comparator 1 output

BLE_RXO

BLE reception indicator for coexistence

GPIOA12

I/O

general-purpose digital input output pin

RO

reserved

SCT0_OUT5O

SCTimer output 5

ACMP0_OUT

O

analog comparator 0 output

FC1_TXD_SCL

I/O

flexcomm 1: USART TXD, I2C SCL

SD_DACO

sigma-delta modulator DAC output

ANT_SWO

external antenna switch for diversity

GPIOA13

I/O

general-purpose digital input output pin

R

I/O

reserved

SCT0_OUT4O

SCTimer output 4

ACMP1_OUT

O

analog comparator 1 output

FC1_RXD_SDA

I/O

flexcomm 1: USART RXD, I2C SDA

FC3_SSEL1

I/O

flexcomm 3: SPI SSEL1

RFE_EN

O

enable for external RF front-end

GPIOA14

I/O

general-purpose digital input output pin

CS0

AI

capacitive touch sense button input 0

ANT_SWO

external antenna switch for diversity

CTIMER2_CAP0

I

timer 2 input capture 0

FC0_RTS

I/O

flexcomm 0: USART RTS

FC3_SSEL0

I/O

flexcomm 3: SPI SSEL0

QDEC1_AI

quadrature decoder 1 input channel A

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA15

GPIOA15

I/O

general-purpose digital input output pin

CS1

AI

capacitive touch sense button input 1

SCT0_OUT0O

SCTimer output 0, PWM output 0

CTIMER2_CAP1

I

timer 2 input capture 1

FC0_CTS

I/O

flexcomm 0: USART CTS

PA16

PA17

PA18

PA19

30

29

28

27

26

QN908x

Product data sheet

4G

4F

6G

5F

7G

PU

PU

PU

PU

PU

FC3_SCK

I/O

flexcomm 3: SPI clock

QDEC1_BI

quadrature decoder 1 input channel B

GPIOA16

I/O

general-purpose digital input output pin

CS2

AI

capacitive touch sense button input 2

SCT0_OUT1OSCTimer output 1, PWM output 1

CTIMER2_MAT0O32-bit CTimer 2 match output 0

FC0_TXD

I/O

flexcomm 0: USART TXD

FC3_MOSI

I/O

flexcomm 3: SPI MOSIQDEC0_AI

quadrature decoder 0 input channel A

GPIOA17

I/O

general-purpose digital input output pin

CS3

AI

capacitive touch sense button input 3

SD_DACO

sigma-delta modulator DAC output

CTIMER2_MAT1

O32-bit CTimer 2 match output 1

FC0_RXD

I/O

flexcomm 0: USART RXD

FC3_MISO

I/O

flexcomm 3: SPI MISOQDEC0_BI

quadrature decoder 0 input channel B

GPIOA18

I/O

general-purpose digital input output pin

CS4

AI

capacitive touch sense button input 4

SCT0_OUT3O

SCTimer output 3, PWM output 3

CTIMER2_MAT2

O32-bit CTimer 2 match output 2

FC0_SCK

I/O

flexcomm 0: USART clock

FC3_SSEL2

I/O

flexcomm 3: SPI SSEL2

BLE_SYNCO

BLE sync pulse

GPIOA19

I/O

general-purpose digital input output pin

CS5

AI

capacitive touch sense button input 5

SCT0_OUT2O

SCTimer output 2, PWM output 2

RFE_EN

O

enable for external RF front-end

FC0_SCK

I/O

flexcomm 0: USART clock

FC3_SSEL3

I/O

flexcomm 3: SPI SSEL3

BLE_IN_PROCO

BLE event in process indicator for coexistence

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA20

GPIOA20

general-purpose digital input output pin

PA21

SWCLK
/PA22

SWDIO/
PA23

PA24

25

24

23

22

21

QN908x

Product data sheet

-

-

7F

6F

6E

PU

PU

PU

PU

PU

I/O

QDEC1_AI

quadrature decoder 1 input channel A

SCT0_OUT1OSCTimer output 1, PWM output 1

CTIMER2_MAT0O32-bit CTimer 2 match output 0

SWO

I/O

serial wire trace output

FC1_RTS_SCL

I/O

flexcomm 1: USART RTS, I2C SCLSPIFI_CLKO

clock output for the SPI flash interface

GPIOA21

I/O

general-purpose digital input output pin

QDEC1_BI

quadrature decoder 1 input channel B

SCT0_OUT0O

SCTimer output 0, PWM output 0

CTIMER2_MAT1

O32-bit CTimer 2 match output 1

FC2_SSEL3

I/O

flexcomm 2: SPI SSEL3

FC1_CTS_SDA

I/O

flexcomm 1: USART CTS, I2C SDASPIFI_CSN

O

active low chip select output for the SPI flash
interface

SWCLK

I/O

serial wire clock; it is the default function after reset

GPIOA22

I/O

general-purpose digital input output pin

SCT0_IN2I

SCTimer input 2

CTIMER3_MAT0O32-bit CTimer 3 match output 0

FC2_SDA_SSEL0

I/O

flexcomm 2: I2C SDA, SPI SSEL0

FC3_SSEL3

I/O

flexcomm 3: SPI SSEL3

QDEC1_AI

quadrature decoder 1 input channel A

SWDIO

I/O

serial wire debug I/O; it is the default function after
booting

GPIOA23

I/O

general-purpose digital input output pin

SCT0_IN3I

SCTimer input 3

CTIMER3_MAT1

O32-bit CTimer 3 match output 1

FC2_SCL_SSEL1

I/O

flexcomm 2: I2C SCL, SPI SSEL1

FC3_SSEL2

I/O

flexcomm 3: SPI SSEL2

QDEC1_BI

quadrature decoder 1 input channel B

GPIOA24

I/O

general-purpose digital input output pin

ACMP0N/CS6

AI

analog comparator 0 negative input, or capacitive
touch sense button input 6

ETM_TRACEDAT0 O

ETM trace data output bit 0

CTIMER3_CAP0

I

timer 3 input capture 0

RFE_RX_ENO

RX enable for external RF front-end

FC3_SSEL1

I/O

flexcomm 3: SPI SSEL1SPIFI_IO0

I/O

data bit 0 for the SPI flash interface

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA25

GPIOA25

I/O

general-purpose digital input output pin

ACMP0P/CS7

AI

analog comparator 0 positive input, or capacitive
touch sense button input 7

PA26

PA27

PA28

PA29

20

19

18

17

16

7E

6D

7D

-

6C

PU

PU

PU

PU

PU

ETM_TRACEDAT1 O

ETM trace data output bit 1

CTIMER3_CAP1

I

timer 3 input capture 1

RFE_TX_ENO

TX enable for external RF front-end

FC3_SSEL0

I/O

flexcomm 3: SPI SSEL0SPIFI_IO1

I/O

data bit 1 for the SPI flash interface

GPIOA26

I/O

general-purpose digital input output pin

USB_DP

I/O

USB0 bidirectional D+ line

SCT0_IN0I

SCTimer input 0

CTIMER1_MAT0O32-bit CTimer 1 match output 0

FC2_SDA_MOSI

I/O

flexcomm 2: I2C SDA, SPI MOSIQDEC0_AI

quadrature decoder 0 input channel A

BLE_SYNCO

BLE sync pulse

GPIOA27

I/O

general-purpose digital input output pin

USB_DM

I/O

USB0 bidirectional D- line

SCT0_IN1I

SCTimer input 1

CTIMER1_MAT2

O32-bit CTimer 1 match output 2

FC2_SCL_MISO

I/O

flexcomm 2: I2C SCL, SPI MISOQDEC0_BI

quadrature decoder 0 input channel B

BLE_IN_PROCO

BLE event in process indicator for coexistence

GPIOA28

I/O

general-purpose digital input output pin

CLK_AHBOAHB clock output

ETM_TRACECLKOETM trace clock output

RTC_CAPI

RTC capture input

FC1_SCK

I/O

flexcomm 1: USART clock

SD_DACO

sigma-delta modulator DAC output

SPIFI_CSN

O

active low chip select output for the SPI flash
interface

GPIOA29

I/O

general-purpose digital input output pin

ACMP1NAI

analog comparator 1 negative input

ETM_TRACEDAT2 O

QN908x

Product data sheet

ETM trace data output bit 2

CTIMER3_MAT0

O

timer 3 match output 0

FC2_SCK

I/O

flexcomm 2: SPI clock

FC3_MISO

I/O

flexcomm 3: SPI MISOSPIFI_IO2

I/O

data bit 2 for the SPI flash interface

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Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

PA30

GPIOA30

I/O

general-purpose digital input output pin

ACMP1PAI

analog comparator 1 positive input

PA31

XTAL32_OUT/P
B00

XTAL32_IN/PB0
1

15

12

3

7C

7B

4A

PU

PU

-

ETM_TRACEDAT3 O

ETM trace data output bit 3

CTIMER3_MAT1

O

timer 3 match output 1

FC2_SCK

I/O

flexcomm 2: SPI clock

FC3_MOSI

I/O

flexcomm 3: SPI MOSISPIFI_IO3

I/O

data bit 3 for the SPI flash interface

GPIOA31

I/O

general-purpose digital input output pin

DAC

AO

DAC analog output

RTC_CAPI

RTC capture input

CTIMER3_MAT2

O

Timer 3 match output 2

SWO

I/O

serial wire trace output

FC3_SCK

I/O

flexcomm 3: SPI clock

SPIFI_CLKO

clock output for the SPI flash interface

XTAL32_OUT

AO

32.768 kHz crystal oscillator output
Remark: leave it unconnected or used as GPIO
when the LFXO is not used.

2

3A

-

GPIOB00

I/O

general-purpose digital input output pin

XTAL32_IN

AI

32.768 kHz crystal oscillator input
Remark: external input clock can be injected whenthe LFXO is not used.

CHIP_M 33
ODE/PB
02

3C

PU

GPIOB01

I/O

general-purpose digital input output pin

CHIP_MODEI

boot selection with pull-up by default; it should be
pulled low to go through the normal ISP process forfirmware programming, otherwise the ISP process
is escaped to jump to flash

GPIOB02

I/O

general-purpose digital input output pin

ANT_SWO

external antenna switch for diversity

RSTN

34

4E

PU

-

I

active low reset input

XTAL_O
UT

39

1D

-

-

AO

16/32 MHz crystal oscillator output

XTAL_I
N

40

RF

35

2G

-

-

RF

RF input output port with Tx or Rx switch integrated
on chip

VCC

1

2A

-

-

-

power supply (1.62 V to 3.6 V)

VDD1

13

7A

-

-

-

digital power supply

VDD2

37

1E

-

-

-

RF power supply

VDD3

41

2E

-

-

-

analog power supply

Remark: leave it unconnected if not used forcrystal oscillator
1C

-

-

AI

16/32 MHz crystal oscillator input
Remark: this can be used as external clock input,
without using internal crystal oscillator

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Table 4.

Pin description …continued

Symbol HVQFN48 WLCSP Resetstate[1]Alternate function Type

Description

VSS

14,47

1F,3D,3E ,3F,3G,4
C,4D,5C,
5D,5E

-

-

ground

IDC

48

1A

-

-

AO

DC-to-DC converter output; refer to reference
design circuit when DC-to-DC is used; leave it open
when DC-to-DC is not used

NC

36,38

-

-

-

-

not connected[1]

PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VCC). Z = high impedance; pull-up or pull-down disabled, AI = analog
input, AO = analog output, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For
pin states in the different power modes, see Section 7.2.2. For termination on unused pins, see Section 7.2.1.

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7.2.1 Termination of unused pins
Table 5 shows how to terminate pins that are not used in the application. In many cases,
unused pins should be connected externally or configured correctly by software tominimize the overall power consumption of the part.
Unused pins with GPIO function can be left unconnected and are configured as input with
their internal pull-up or pull-down enabled. Enabling pull-down is preferred.
In addition, it is recommended to configure all GPIO pins that are not bonded out on
smaller packages as inputs, with their internal pull-up or pull-down enabled.
Table 5.

Termination of unused pins

Pin

Default state[1] Recommended termination of unused pins

PAnm

I; PU

unconnected if driven LOW and configured as GPIO output with pull-up disabled bysoftware

XTAL32_IN-

unconnected

XTAL32_OUT-

unconnected[1]

I = Input, PU = Pull-up enabled

7.2.2 Pin states in different power modes
Table 6.

Pin states in different power modes

Pin

ActivePAnm pins

As configured in the SYSCON[1]. Default: input with internal pull-up enabled

RSTN

Reset function enabled. Default: input, internal pull-up enabled

[1]

Sleep

Power-down

Default and programmed pin states are retained in sleep and power down mode

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8. Functional description
8.1 Architectural overview
The ARM Cortex-M4 includes one AHB-Lite bus, one system bus, and I-code and D-codebuses. Separate buses are dedicated for instruction fetch (I-code) and data access(D-code).
The QN908x uses a multi-layer AHB matrix to connect the ARM Cortex-M4 buses andother bus masters to peripherals in a flexible manner. It optimizes performance byallowing peripherals that are on different slave ports of the matrix to be accessed
simultaneously by different bus masters.

8.2 ARM Cortex-M4 processor
The ARM Cortex-M4 is a general-purpose, 32-bit microprocessor, which offers highperformance and very low power consumption. The ARM Cortex-M4 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply anddivide, and interruptable or continuable multiple load and store instructions. It also
provides automatic state save and restore for interrupts, tightly integrated interrupt
controller with wake-up interrupt controller, and multiple core buses capable ofsimultaneous accesses.
A 3-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is executed, its successor is
decoded, and a third instruction is fetched from memory.

8.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)
The FPU supports single-precision add, subtract, multiply, divide, multiply andaccumulate, and square root operations. It also provides conversions between fixed-pointand floating-point data formats, and floating-point constant instructions.
The FPU provides floating-point computation functionality that is compliant with the
ANSI/IEEE standard 754-2008. The IEEE standard for binary floating-point arithmetic isreferred as the IEEE 754 standard.

8.4 Memory Protection Unit (MPU)
The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve
the reliability of an embedded system by protecting critical data within the user
application.
The MPU allows separating processing tasks by disallowing access to each other's data.
Access to memory regions can be disabled and also be defined as read-only. It detects
unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions, each of which is
divided into eight sub-regions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will trigger memory management fault
exception.

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8.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The NVIC supports 52 external interrupt input sources, each with eight levels of priority.
The processor supports both level and edge interrupts. External interrupt signals areconnected to the NVIC, and the NVIC prioritizes the interrupts. Software is used to set thepriority of each interrupt. The NVIC and the Cortex-M4F processor core are closely
coupled, providing low-latency interrupt processing and efficient processing of late arriving
interrupts.
The Wake-up Interrupt Controller (WIC) supports ultra-low power sleep mode. It enables
the processor and NVIC to be put into a very low-power sleep mode leaving the WIC to
identify and prioritize the interrupts. The processor implements the Wait-For-Interrupt(WFI), Wait-For-Event (WFE) and the Send EVent (SEV) instructions. In addition, theprocessor also supports use of SLEEPONEXIT, which causes the processor core to enter
sleep mode when it returns from an exception handler to thread mode.

8.5.1 Features• Controls system exceptions and peripheral interrupts• 52 external interrupt input sources• Eight programmable interrupt priority levels, with hardware priority level masking• Relocatable vector table using Vector Table Offset Register (VTOR)• Software interrupt generation
8.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. There are 52 interrupt sources in total.

8.6 System Tick timer (SysTick)
The ARM Cortex-M4 core includes a System Tick timer (SysTick) that generates a
dedicated SYSTICK exception. The clock source for the SysTick can be the system clockor the SYSTICK clock.

8.7 On-chip static RAM
QN908x supports 128 kB SRAM with separate bus master access for higher throughput
and individual power control for low-power operation.
The 128 kB SRAM is divided into ten memory blocks, each with separate power control, torefine the power consumption according to application requirements.
Table 7.

QN908x

Product data sheet

SRAM memory blocks

SRAM block

SIze

Start address offset

9

4k 32 bit

0x0001 C000

84k 32 bit

0x0001 8000

74k 32 bit

0x0001 4000

6

4k 32 bit

0x0001 0000

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Table 7.

SRAM memory blocks

SRAM block

SIze

Start address offset

5

4k 32 bit

0x0000 C000

44k 32 bit

0x0000 8000

34k 32 bit

0x0000 400022k 32 bit

0x0000 2000

1

1k 32 bit

0x0000 10000

1k 32 bit

0x0000 0000

8.8 On-chip flash
The QN908x supports 512 kB of on-chip flash memory, to store code and data. The MCU
accesses the flash via flash controller.

• 256 equal pages with 2 kB each; any page can be erased individually• Greater than 10 years of data retention at 85°C
• Endurance: minimum 10,000 cycles
8.9 On-chip ROM
The 256 kB on-chip ROM contains boot loader and the following Application Programming
Interfaces (API):• In-System Programming (ISP) support for flash programming
8.10 Memory mapping
QN908x incorporates several distinct memory regions. The APB peripheral area is 64 kB
in size and is divided to allow for multiple peripherals. The registers incorporated into theCPU, such as NVIC, SysTick, and sleep mode control, are located on the private
peripheral bus.
QN908x integrates four types of memories: embedded flash, ROM, SRAM, and external
SPIFI memory interface. To provide enough flexibility, the flash, ROM and RAM can bemapped to different regions of the memory map, depending on the register bits remap.
The remap is 0 after reset and ROM is remapped to the address 0x0000 0000.
Table 8.

QN908x

Product data sheet

Memory map options

MemoryPrimary space

Alias

Memory remap
optionROM (256 kB)

0x0300 0000 to
0x0304 0000

N/A

0x0000 0000 to
0x0004 0000
(remap=0)

flash (512 kB)

0x0100 0000 to
0x0108 0000

0x2100 0000 to
0x2108 0000; 0x3100
0000 to 0x3108 0000

0x0000 0000 to
0x0008 0000
(remap=1)

SRAM (128 kB)

0x0400 0000 to
0x0402 0000

0x2000 0000 to
0x2002 0000

0x0000 0000 to
0x0002 0000
(remap=2)

SPIFI flash memory

0x1000 0000 to
0x1800 0000

0x8000 0000 to
0x8800 0000

N/A

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Figure 6 shows the overall map of the entire address space from the user program
viewpoint.

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The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

Fig 6.

QN908x memory mapping

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Fig 7.

QN908x APB memory map

8.11 Power management
To minimize system power consumption, the QN908x supports a variety of power modes
and power management features.

8.11.1 Power supply
QN908x integrates both LDO and DC-to-DC converter. When the device is powered at ahigher supply voltage like 3 V, DC-to-DC converter can be used to reduce current
consumption.
When in the LDO mode without using DC-to-DC converter, users should make sure the
VDD1, VDD2 and VDD3 never ramp-up before VCC. A simple way is to connect them
together. Refer to the reference schematic for more information.

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Fig 8.

QN908x power supply

8.11.2 Power modes
A variety of power modes are supported for the optimization of power consumption,
including active, sleep, power-down 0 and power-down 1 mode. Upon power-up or reset,
the device enters active mode. After processing is complete, the software puts the chip
into sleep mode or power-down mode, to save power consumption. The device is woken
up either by a reset or an interrupt trigger like a GPIO interrupt, timer timeout, or otherwake-up sources.
8.11.2.1 Sleep mode
In sleep mode, the system clock to the CPU is stopped and execution of instructions issuspended until either a reset or an interrupt occurs. Peripheral functions, if selected to beclocked, can continue operation during sleep mode and may generate interrupts to cause
the processor to resume execution. Sleep mode eliminates dynamic power used by theprocessor itself, memory systems and related controllers, internal buses, and unused
peripherals. The processor state and registers, peripheral registers, and internal SRAM
values are maintained, and the logic levels of the pins remain static.
8.11.2.2 Power-down 0 mode
In power-down 0 mode, power is shut off to the entire chip except for the always-on PMU
domain, 32.768 kHz crystal oscillator, 32k RC oscillator, sleep timer, RTC, and the RSTN
pin. All peripheral clocks and all clock sources are off with the option of keeping the
32 kHz clock running. In addition, all analog blocks and flash are shut down. In power
down mode, the application can keep the analog comparator circuit running to monitor
external voltage input, which wakes up the device if external voltage is higher than thereference voltage.
The QN908x wakes up from power-down 0 mode via a reset, digital pins selected as
inputs to the pin interrupt block, sleep timer timeout interrupt, RTC interrupt, BOD forced
reset, analog comparator interrupt, or cap sense interrupt.

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In power-down 0 mode, the processor state, registers, and SRAM values can be
maintained, and the logic levels of the pins remain static. Power-down mode reduces
power consumption compared to sleep mode, at the expense of longer wake-up times.
8.11.2.3 Power-down 1 mode
In power-down 1 mode, 32k clock source is powered off too. The capacitive sensor, RTC
or BLE’s low power domain does not work either. Only external IO, analog comparator canwake up system from this mode.
Table 9 shows the peripheral configuration in reduced power modes.
Table 9.

Peripheral configuration in reduced power modes
Peripheral

Sleep mode

Power-down 0 mode

Power-down 1 mode

Flash

Software configured

Off

Off

SRAM blocks

Software configured

Software configured

Software configured

Sleep timer

Software configured

Software configured

Off

RTC

Software configured

Software configured

Off

Other digital peripherals

Software configured

Off

Off

Analog comparator

Software configured

Software configured

Software configured

32 kHz RCO

Software configured

Software configuredOff32.768 kHz crystal oscillator

Software configured

Software configured

Off

BOD

Software configured

Software configured

Software configured

Capacitive sense

Software configured

Software configured

Software configured

Other analog peripherals

Software configured

Off

Off

8.11.3 Brown-Out Detection (BOD)
The QN908x includes a monitor for the voltage level on pin VCC. If this voltage falls below
a fixed level, the BOD sets a flag that can cause an interrupt. In addition, separate
threshold levels can be selected to cause chip reset and interrupt. By default, the BOD isdisabled.

8.12 General-Purpose Input Output (GPIO)The QN908x has two GPIO ports with a total of 35 GPIO pins. Device pins that are notconnected to a specific peripheral function are controlled by the GPIO registers. Pins may
be dynamically configured as inputs or outputs. The current level of a port pin can be readback, no matter what peripheral is selected for that pin. See Table 4 for the default state
on reset.

8.12.1 Features• Accelerated GPIO functions– GPIO registers are located on the AHB so that the fastest possible I/O timing canbe achieved– All GPIO registers are word, half-word, and byte addressable– Entire port value can be written in one instruction• Direction control of individual bits
• All I/O default to inputs after reset
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request8.13 Pin interrupt
The pin interrupt block configures up to four pins from all digital pins to provide four
external interrupts connected to the NVIC. Any digital pin, independent of the function
selected through the switch matrix can be configured through the SYSCON block as an
input to the pin interrupt. The registers that control the pin interrupt are located on the I/O+
bus for fast single-cycle access.

8.13.1 Features• Pin interrupts:– All pins of GPIO A can be selected as edge sensitive or level sensitive interrupt
requests, each request creates a separate interrupt in the NVIC
– Edge sensitive interrupt pins can interrupt on rising or falling edges or both
– Level sensitive interrupt pins can be active HIGH or active LOW– Pin interrupts can wake up the device from sleep mode, but not in power-down
mode

8.14 AHB peripherals
8.14.1 DMA controller
The DMA controller allows peripheral to memory, memory to peripheral, and memory tomemory transactions. Each DMA stream provides unidirectional DMA transfers for asingle source and destination.
8.14.1.1

Features• 20 channels, 15 of which are connected to peripheral DMA requests, these DMA
requests come from the Flexcomm (USART, SPI, I2C), and SPIFI interfaces• DMA operations can be triggered by on-chip or off-chip events• Priority is user-selectable for each channel (up to eight priority levels)• Continuous priority arbitration• Address cache with four entries• Efficient use of data bus• Supports single transfers of up to 1024 words• Address increment options allow packing and/or unpacking data
8.15 Digital serial peripherals
8.15.1 USB 2.0 (full-speed) device controller
8.15.1.1

Features• USB 2.0 (full-speed) device controller operating at 12Mbit/s• Supports ten physical (five logical) endpoints including one control endpoint
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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4• Single- and double buffering supported• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types• Supports wake-up from deep sleep mode on USB activity and remote wake-up• Link Power Management (LPM) supported
8.15.2 SPI Flash Interface (SPIFI)The SPI Flash Interface (SPIFI) allows low-cost serial flash memories to be connected toCPU, with little performance penalty compared to parallel flash devices with higher pin
count. A driver API handles setup, programming, and erasure. After an initialization call to
the SPIFI driver, the flash content is accessible as normal memory using byte, half word,
and word accesses by the processor and/or DMA.
8.15.2.1

Features• SPI flash interface to external flash• Transfer rates of up to SPIFI_CLK/2 bytes per second• Code in the serial flash memory can be executed as if it was in the internal memory
space of the CPU. It is accomplished by mapping the external flash memory directly
into the CPU memory space
Remark: the SPIFI implemented on QN908x devices is intended for data access. The
cache size is reduced and therefore direct execution from off-chip SPI flash is notrecommended.

• Supports 1-bit, 2-bit, and 4-bit bidirectional serial protocols• Half-duplex protocol compatible with various vendors and devices• A driver library available from NXP Semiconductors to assist in using the SPIFI
8.15.3 Flexcomm serial communication (0,1,2,3)
Each Flexcomm provides a choice of peripheral functions, one of which the user mustchoose before the function can be configured and used.
8.15.3.1

Features• USART with asynchronous operation or synchronous master or slave operation• SPI-bus master or slave, with up to four slave selects• I2C-bus, including separate master, slave, and monitor functions• Data for USART, and SPI traffic uses the Flexcomm FIFO. The I2C function does not
use the FIFO

• Flexcomm 0: USART• Flexcomm 1: USART and I2C-bus• Flexcomm 2: SPI-bus and I2C-bus• Flexcomm 3: SPI-bus
8.15.4 I2C-bus interface
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address andcan operate as either a receiver-only device (for example, an LCD driver) or a transmitter
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with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether thechip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus
and can be controlled by more than one bus master connected to it.
8.15.4.1

Features• Independent master and slave functions• Bus speeds supported:– Standard mode, up to 100 kbits/s– Fast mode, up to 400 kbits/s• Supports both multi-master and multi-master with slave functions• Programmable I2C-bus slave addresses• No chip clocks are required to receive and compare an address as a slave; so thisevent can wake up the device from sleep mode

8.15.5 USART
8.15.5.1

Features• Synchronous mode with master or slave operation. Includes data phase selection andcontinuous clock option• Maximum bit rates of 1 Mbit/s in asynchronous mode
• Maximum data rates of 1 Mbit/s in synchronous master and slave modes for USART
functions• Multiprocessor/multidrop (9-bit) mode with software address compare• RS-485 transceiver output enable• Auto-baud mode for automatic baud rate detection• Parity generation and checking: odd, even, or none
• Software selectable oversampling from 5 to 16 clocks in asynchronous mode
• One transmit and one receive data buffer• RTS/CTS for hardware signaling for automatic flow control; software flow control canbe performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output• Received data and status can optionally be read from a single register• Break generation and detection• Receive data is 2 of 3 sample "voting"; status flag set when one sample differs• Built-in baud rate generator with auto-baud function• Fractional rate divider shared among all USARTs• Interrupts available for FIFO receive level reached, FIFO transmit level reached,transmit idle, change in receiver break detect, framing error, parity error, overrun,
underrun, delta CTS detect, and receiver sample noise detected• Loopback mode for testing of data and flow control• USART transmit and receive functions work with the system DMA controller
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8.15.6 SPI serial I/O controller
8.15.6.1

Features• Master and slave operation• Maximum data rates of 16 Mbit/s in master mode for SPI functions• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or
DMA set-up• Master and slave operation• Data can be transmitted to a slave without the need to read incoming data; useful
while setting up an SPI memory• Control information can optionally be written along with data; allows very versatile
operation, including “any length” frames• Three slave select input/outputs with selectable polarity and flexible usage
8.16 Timers
8.16.1 Standard timer/counter (CTIMER0 to 3)
The QN908x includes four general-purpose 32-bit timer/counters.
The timer/counter is designed to count cycles of the system-derived clock or an externallysupplied clock. It optionally generates interrupts, timed DMA requests, or perform otheractions at specified timer values, based on four match registers. Each timer/counter also
includes two capture inputs, to trap the timer value when an input signal transitions,
optionally generating an interrupt.
8.16.1.1

Features• A 32-bit timer/counter with a programmable 32-bit prescaler• Counter or timer operation• Up to three 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions; a capture event may also generate an interrupt• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge

• Four 32-bit match registers that allow:– Continuous operation with optional interrupt generation on match– Stop timer on match with optional interrupt generation– Reset timer on match with optional interrupt generation• Up to four external outputs per timer corresponding to match registers with thefollowing capabilities:– Set LOW on match– Set HIGH on match– Toggle on match– Do nothing on match
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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4• Up to two match registers can be used to generate timed DMA requests• PWM mode using up to three match channels for PWM output
8.16.2 SCTimer/PWM
The SCTimer/PWM is a flexible timer module capable of creating complex PWM
waveforms. It can also perform other advanced timing and control operations with minimal
or no CPU intervention.
The SCTimer/PWM can operate as a single 32-bit counter or as two independent, 16-bit
counters in uni-directional or bi-directional mode. It supports a selection of match registers
against which the count value can be compared. It also has capture registers where thecurrent count value can be recorded when some pre-defined condition is detected.
The SCTimer/PWM module supports multiple separate events. The events can be definedby the user based on some combination of parameters including a match on one of thematch registers, and/or a transition on one of the SCTimer/PWM inputs or outputs, thedirection of count, and other factors.
Every action that the SCTimer/PWM block can perform occurs in direct response to one ofthese user-defined events without any software overhead. Any event can be enabled to:• Start, stop, or halt the counter• Limit the counter which means to clear the counter in unidirectional mode or change
its direction in bi-directional mode

• Set, clear, or toggle any SCTimer/PWM output• Force a capture of the count value into any capture registers• Generate an interrupt of DMA request
8.16.2.1

Features• The SCTimer/PWM supports:– Five inputs– Six outputs– Ten match/capture registers– Ten events– Ten states• Counter/timer features– Each SCTimer/PWM is configurable as two 16-bit counters or one 32-bit counter– Counters clocked by system clock or selected input– Configurable number of match and capture registers. Up to five match and capture
registers total– Ten events– Ten states– Upon match and/or an input or output transition create the following events:
interrupt; stop, limit, halt the timer or change counting direction; toggle outputs;change the state– Counter value can be loaded into capture register triggered by a match or
input/output toggle
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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4– Each SCTimer/PWM is configurable as two 16-bit counters or one 32-bit counter– Counters clocked by system clock or selected input– Configurable number of match and capture registers. Up to five match and capture
registers total– Ten events– Ten states– Upon match and/or an input or output transition create the following events:
interrupt; stop, limit, halt the timer or change counting direction; toggle outputs;change the state– Counter value can be loaded into capture register triggered by a match or
input/output toggle• PWM features:– Counters can be used in conjunction with match registers to toggle outputs andcreate time-proportioned PWM signals– Up to eight single-edge or four dual-edge PWM outputs with independent duty
cycle and common PWM cycle length• Event creation features:– The following conditions define an event: a counter match condition, an input (oroutput) condition such as an rising or falling edge or level, a combination of match
and/or input/output condition– Selected events can limit, halt, start, or stop a counter or change its direction– Events trigger state changes, output toggles, interrupts, and DMA transactions– Match register 0 can be used as an automatic limit– In bi-directional mode, events can be enabled based on the count direction– Match events can be held until another qualifying event occurs• State control features:– A state is defined by events that can happen in the state while the counter isrunning– A state changes into another state as a result of an event– Each event can be assigned to one or more states– State variable allows sequencing across multiple counter cycles

8.16.3 WatchDog Timer (WDT)The Watchdog timer (WDT) is a 32-bit timer clocked by 32 kHz clock. It is intended as arecovery method in situations where the CPU is subjected to software upset. The WDT
resets the system when software fails to clear the WDT within the selected time interval.
The WDT is configured as either a watchdog timer or as a timer for general-purpose use.
If the watchdog function is not required in an application, it is possible to configure thewatchdog timer as an interval timer that can be used to generate interrupts at selected
time intervals. The maximum timeout interval is 1.5 days.
8.16.3.1

Features• Programmable 32-bit timer
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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4• Internally resets chip if not reloaded during the programmable time-out period• Flag to indicate Watchdog reset
8.16.4 RTC timer
The RTC block has three counters:• 15-bit counter running of 32 kHz clock, to generate second• 32-bit second counter to count seconds• 32-bit free running counter with associated match registers to generate interrupt andforced reset
8.16.4.1

Features• 15-bit counter, to generate second:– Operate on 32 kHz clock– Programmable 1second interrupt– Calibration function to compensate clock inaccuracy• 32-bit second counter to count seconds generated by the 15-bit counter– Support configuration of second register on the fly• 32-bit free running counter and associated match register:– Operate on 32 kHz clock– Match register for interrupt generation– Match register to generate reset, to be used as watchdog function• Can wake up MCU from sleep mode and power down mode
• Can capture edge of input pins, to generate interrupts on either rising edge or fallingedge

8.17 Analog peripherals
8.17.1 16-bit Analog-to-Digital Converter (ADC)The ADC is a 16-bit general-purpose Sigma-Delta (SD) type ADC that can sample up to
32 kilo sample per second, using up to eight different external input channels, withmultiple trigger sources.
8.17.1.1

Features• 16-bit sigma-delta analog to digital converter• 14-bit ENOB at 32 kHz sampling rate
• Integrated filter with 256 decimation rate. Additional software filtering by user canachieve higher resolution• Up to eight external single-ended inputs, which can be configured as differential mode
• Supports both single or burst mode
• Supports scan mode
• Multiple trigger resources• A temperature sensor is connected as an alternative input of ADC
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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4• A battery monitor is connected as an alternative input of ADC• ADC output buffer• ADC done interrupt with DMA capability
8.17.2 Temperature sensor
The temperature sensor transducer uses an intrinsic pn-junction diode reference andoutputs a Complement To Absolute Temperature (VCTAT) voltage. The output voltage
varies inversely with device temperature with an absolute accuracy of better than ±2°C
over the full temperature range (-40°C to 85°C). The temperature sensor is only
approximately linear with a slight curvature. The output voltage is measured over different
ranges of temperatures and fit with linear-least-square lines.
After power-up, the temperature sensor output must be allowed to settle to its stable value
before it can be used as an accurate ADC input.

8.17.3 Battery monitor
The battery monitor is used to monitor the VCC supply. A voltage divider (VCC/4) is
integrated and connected to an ADC internal channel.

8.17.4 Analog comparators (ACMP0, ACMP1)The QN908x integrates two analog voltage comparators. The analog comparator is used
to compare the voltage of two analog inputs. It generates a digital output to indicate thehigher input voltage. The positive input is always from the external pin. The negative input
can either be one of the selectable internal references or from an external pin. The
ultra-low power analog comparator triggers an interrupt and wakes up the devices frompower-down mode.
8.17.4.1

Features• External negative input or configurable internal reference• Comparator output can be read via register, or output to GPIO pins
• Configurable output polarity• Can trigger an interrupt• Can wake up the device from power-down mode
8.17.5 Digital-to-Analog Converter (DAC)The DAC supports two modes:• 1 MHz 8-bit digital-to-analog conversion• Sigma-delta modulated digital output with 20-bit digital input
8.17.5.1

Features• 1 MHz 8-bit Digital-to-analog conversion mode
• Sigma-delta modulation of 20-bit digital input data
– 8-bit or 20-bit digital input from MCU or DMA, with gain control– Internal generated 20-bit sin-wave with configurable frequency and amplitude• Eight entry input data FIFO
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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4• Input FIFO status indication with DMA capability• Multiple trigger sources to start conversion:– Timer timeout– GPIO– Software trigger

8.17.6 Capacitive sense
The QN908x integrates a capacitive sense module, by monitoring the frequency changeof the RC ring oscillator induced changing capacitance on external input pins. The
monitored output is stored in FIFO for further software processing, to realize flexible userinterface design. Smaller capacitance leads to higher frequency with bigger output data,
and vice versa.
8.17.6.1

Features• Up to eight input channels• Support hardware continuous detection to reduce power consumption• Scan mode among selected channels• Eight entry output data FIFO, with interrupt to MCU• Output data with channel index for easy software processing• Programmable frequency range with trade off for current consumption• Low power mode, operating on 32 kHz clock allows one selected channel to wake up
the device from power down mode, with pre-defined threshold

8.18 CRC engine
The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

8.19 Random Number Generator (RNG)
QN908x integrates a random number generator for security purpose. The Random
Number Generator (RNG) generates true non-deterministic random numbers forgenerating keys, initialization vectors and other random number requirements.

8.20 Advanced Encryption Standard (AES) coprocessor
The Advanced Encryption Standard (AES) coprocessor allows encryption/decryption to be
performed with minimal CPU usage. The coprocessor supports 128-bit key.

8.21 Quadrature DECoder (QDEC)The QN908x integrates two quadrature decoders.The decoder supports decoding of
quadrature encoded sensor signals. It provides a pulse train with 90 degrees phasedifference depending on whether the reference signal is leading or lagging, to determine
the direction of rotation. It is suitable for mechanical or optical sensors with optional input
debounce filter. The sample period and accumulation are configurable to provide flexibility
for application.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

8.22 Fusion Signal Processor (FSP)The QN908x integrates a co-processor (FSP) as hardware accelerator to offload the MCU
from routine computations in data fusion and machine learning algorithms. The FSP is on
the AHB bus. Once it is programmed and the input data is ready, it starts working andgenerates interrupt once the operation is complete. The interrupt triggers the MCU or
DMA engine to fetch output data. To reduce current consumption for data transfers, the
FSP has direct access to system memory to read input data and write the resultant output.

8.22.1 Features• Matrix operations: inverse, add, multiplication, dot multiplication, transpose– Maximum size of matrix is 9 9– Floating point operation• Transform engine supports FFT, IFFT, DCT, IDT operations– Configurable 64, 128, or 256 points operation– Supports real/complex, and fixed point/floating point input data
– Supports real/complex, and fixed point/floating point output result• Linear operation: FIR filter and correlation– Up to 9 parallel FIR filters– Each FIR filter has up to 15 taps with programmable coefficients. Supports both
fixed point and floating point operation– Correlation between two sequences with length up to 256. Supports both fixed
point and floating point operation• Non-linear operations include Sine, Cosine, Log, Sqrt, Cordic– Supports both fixed point and floating point operation• Statistics include Min, Max, Sum, Power Sum– Supports both fixed-point and floating-point operation– Supports up to 256 samples

8.23 Clock management
8.23.1 Clock sources
The QN908x supports two external and two internal clock sources:• Internal 32 MHz oscillator• Internal 32 kHz RC oscillator• External high frequency crystal oscillator (32 MHz or 16 MHz)• External 32.768 kHz crystal oscillator
8.23.1.1

Internal 32 MHz oscillator
The internal 32 MHz oscillator can be used as a clock that drives the CPU. Upon
power-up, or any chip reset, the QN908x uses the internal oscillator as the clock source.
Software switches to one of the available clock sources later.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

8.23.1.2

Internal 32 kHz oscillator
The 32 kHz oscillator is a low-power internal oscillator. It can be used to provide a clock tothe sleep timer, RTC and to the entire chip. After proper calibration, the peripherals
including RTC and sleep timer can achieve the accuracy of 500 ppm.

8.23.1.3

External high frequency crystal oscillator
QN908x has 16/32 MHz external crystal with 50 ppm accuracy. The high frequency
crystal oscillator provides reference frequency for the radio transceiver. The load
capacitance is integrated to reduce BOM cost, configurable by software.

8.23.1.4

External 32.768 kHz crystal oscillator
A 32.768 kHz crystal oscillator is used to replace the internal 32 kHz oscillator whereaccurate timing is needed. The 32 kHz clock with higher accuracy reduces power
consumption of Bluetooth Low Energy operation.

8.23.2 Clock generation
The system control block facilitates the clock generation. Many clocking variations are
possible. Figure 9 gives an overview of the potential clock options.

Fig 9.

QN908x clock generation

8.24 Code security
This feature of the QN908x allows the user to enable different levels of security in thesystem so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) is restricted.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

8.25 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug andtrace functions are supported. The ARM Cortex-M4 is configured to support up to eight
breakpoints and four watch points.
The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,
execute the boot code, restart from address 0x0000 0000, and break at the user entry
point.
The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the
SWD functions by default.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

9. Limiting values
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]SymbolParameter

Conditions

Min

Max

Unit

VCC

supply voltage

on pin VCC

[2]

-0.3

3.6

V

VDD1

digital supply voltage

on pin VDD1

[2]

-0.3

3.6

V

VDD2

RF supply voltage

on pin VDD2

[2]

-0.3

3.6

V

on pin VDD3

[2]

-0.3

3.6

V

VDD3

analog supply voltage

[6]

VI

input voltage

-0.3

3.6

V

VI

input voltage

RF pin

-0.3

1.3

V

VI

input voltage

USB_DM,

-0.3

3.6

V

VIA

analog input voltage

on digital pins configured for ananalog function

[7]

-0.3

3.6

V

ICC

total supply current

per supply pin

[3]

-

50

mA

[3]

USB_DP pins

ISS

total ground current

per ground pin

IlatchI/O latch-up current

(0.5VCC) < VI < (1.5VCC);

-

50

mA

-

100

mA

Tj < 125 C
Vi(HFXO)

32/16 MHz oscillator
input voltage

[2]

-0.3

3.6

V

Vi(LFXO)

32.768 kHz oscillator
input voltage

[2]

-0.3

3.6

V

Tstg

storage temperature[8]

Tj(max)maximum junction
temperature

VESD

electrostatic discharge
voltage[1]

Human Body Model; all pins

[4]

-65

150

C

-

+150

C

-

2

kV

500

V

400

V

Charged Device Model; all pins
HVQFN48

[5]

WLCSP

[5]

-

The following applies to the limiting values:a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unlessotherwise noted.
c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is notguaranteed. The conditions for functional operation are specified in Table 18.

[2]

Maximum/minimum voltage above the maximum operating voltage (see Table 18) and below ground that can be applied for a short time(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3]

The peak current is limited to 25 times the corresponding maximum current.

[4]

Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kOhm series resistor.

[5]

Charged device model.

[6]

Including the voltage on outputs in 3-state mode.

[7]

It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[8]

Dependent on package type.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

10. Thermal characteristics
The average chip junction temperature, Tj (°C), can be calculated using the following
equation:T j = T amb +  P D  R th  j – a  (1)• Tamb = ambient temperature (°C),• Rth(j-a) = the package junction-to-ambient thermal resistance (°C/W)• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 11.

Thermal resistance

Symbol Parameter

Conditions

Max/Min

Unit

JEDEC (4.5 in  4 in); still air

28±15%

C/W

4±15%

C/W

53±15%

C/W

1±15%

C/W

HVQFN64 packageRth(j-a)thermal resistance fromjunction to ambient

Rth(j-c)thermal resistance fromjunction to caseWLCSP47 package

QN908x

Product data sheet

Rth(j-a)thermal resistance fromjunction to ambient

Rth(j-c)thermal resistance fromjunction to case

JEDEC (4.5 in  4 in); still air

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11. Static characteristics
11.1 General operating conditions
Table 12. General operating conditions
Tamb = 40 C to +85 C, unless otherwise specified.
SymbolParameter

Conditions

Min

Typ[1]

Max

Unit

fclk

clock frequency

internal CPU/system clock

-

-

32

MHz

VCC

supply voltage

1.62

-

3.6

V

VDD1

digital supply voltage

1.3

-

3.6

V

VDD2

RF supply voltage

1.3

-

3.6

V

VDD3

analog supply voltage

1.3

-

3.6

V

Vref

ADC reference voltage

1.2

-

VCC

V

External reference

External 32.768 kHz crystal oscillator pins
Vi32.768 kHz oscillator
input voltage

on pin XTAL32_IN

0

-

3.6

V

Vo

32.768 kHz oscillator
output voltage

on pin XTAL32_OUT

0

-

3.6

V

External high frequency crystal oscillator pins
Vi16 / 32 MHz oscillator
input voltage

on pin XTAL_IN

0

-

3.6

V

Vo

16 / 32 MHz oscillator
output voltage

on pin XTAL_OUT

0

-

3.6

V

[1]

Typical ratings are not guaranteed. The values listed are for room temperature (25 °C), nominal supply voltages.

11.2 CoreMark data
Table 13. CoreMark score
Tamb = 25C, VCC = 3.0V
Parameter

Conditions

Typ

Unit

ARM Cortex-M4 in active mode
CoreMark score
CoreMark score

CoreMark code executed from SRAM

[1][2]

2.3(Iterations/s) / MHz

CoreMark code executed from flash[1][2]

2.3(Iterations/s) / MHz[1]

Characterized through bench measurements using typical samples.

[2]

Compiler settings: Keil µVision v.5.14., optimization level 3, optimized for time on.

11.3 Power consumption
Power measurements in active, sleep, power down modes were performed under thefollowing conditions:• All peripherals disabled• Analog peripherals (ADC/DAC/ACMP/Capacitive Sense) powered down
• RF off• Internal 32 MHz HFRCO powered down

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 14. Static characteristics: Power consumption in active modes
Tamb = 40 C to +85 C, unless otherwise specified.
SymbolParameter

Conditions

Min

Typ[1]Max

Unit

16 MHz crystal oscillator; DC-to-DC converter enabled, Vcc = 3.0 V
ICC

supply current

CoreMark code executed from RAM; flash powered down
CLK_AHB = 16 MHz

[2]

-

670

-

A

CLK_AHB = 8 MHz

[2]

-

480

-

A

CLK_AHB = 16 MHz

[2]

-

870

-

A

CLK_AHB = 8 MHz

[2]

-

590

-

A

CoreMark code executed from flash

32 MHz crystal oscillator; DC-to-DC converter enabled, Vcc = 3.0 V
ICC

supply current

CoreMark code executed from RAM; flash powered down
CLK_AHB = 32 MHz

[2]

-

1080

-

A

CLK_AHB = 16 MHz

[2]

-

750

-

A

CLK_AHB = 8 MHz

[2]

-

560

-

A

CLK_AHB = 32 MHz

[2]

-

1410

-

A

CLK_AHB = 16 MHz

[2]

-

900

-

A

CLK_AHB = 8 MHz

[2]

-

640

-

A

CoreMark code executed from flash

16 MHz crystal oscillator; DC-to-DC converter disabled, Vcc = VDD1 to VDD3 = 3.0 V
ICC

supply current

CoreMark code executed from RAM; flash powered down
CLK_AHB = 16 MHz

[2]

-

1140

-

A

CLK_AHB = 8 MHz

[2]

-

760

-

A

CLK_AHB = 16 MHz

[2]

-

1450

-

A

CLK_AHB = 8 MHz

[2]

-

920

-

A

CoreMark code executed from flash;

32 MHz crystal oscillator; DC-to-DC converter disabled, Vcc = VDD1 to VDD3 = 3.0 V
ICC

supply current

CoreMark code executed from RAM; flash powered down
CLK_AHB = 32 MHz

[2]

-

2070

-

A

CLK_AHB = 16 MHz

[2]

-

1370

-

A

CLK_AHB = 8 MHz

[2]

-

980

-

A

CLK_AHB = 32 MHz

[2]

-

2660

-

A

CLK_AHB = 16 MHz

[2]

-

1650

-

A

CLK_AHB = 8 MHz

[2]

-

1120

-

A

CoreMark code executed from flash[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).

[2]

Characterized through bench measurements using typical samples.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 15. Static characteristics: Bluetooth LE power consumption in active modes
Tamb = 40 C to +85 C, unless otherwise specified.
SymbolParameter

Conditions

Min

Typ[1][2]Max[3]

Unit

32 MHz crystal oscillator, CLK_AHB = 16 MHz. Transmitter mode: fc = 2440 MHz, 1Mbps mode
ICC

supply current

DC-to-DC converter enabled, Vcc = 3 V
Tx power = 0 dBm

-

3.5

-

mA

Tx power = 4 dBm

-

2.5

-

mA

Tx power = 0 dBm

-

7.1

-

mA

Tx power = 4 dBm

-

5.0

-

mA

DC-to-DC converter disabled, Vcc = 3 V

32 MHz crystal oscillator, CLK_AHB = 32 MHz. Transmitter mode: fc
ICC

supply current= 2440 MHz, 2Mbps mode[4]DC-to-DC converter enabled, Vcc = 3 V
Tx power = 0 dBm

-

3.5

-

mA

-

7.1

-

mA

DC-to-DC converter disabled, Vcc = 3 V
Tx power = 0 dBm

32 MHz crystal oscillator, CLK_AHB = 16 MHz. Receiver mode: fc = 2440 MHz, 1Mbps mode
ICC

supply current

DC-to-DC converter enabled, Vcc = 3 V
94 dBm RX sensitivity

-

3.5

-

mA

-

7.2

-

mA

DC-to-DC converter disabled, Vcc = 3 V
95 dBm RX sensitivity

32 MHz crystal oscillator, CLK_AHB = 32 MHz. Receiver mode: fc = 2440 MHz, 2Mbps mode[4]ICC

supply current

DC-to-DC converter enabled, Vcc = 3 V
91.5 dBm RX sensitivity

-

5.0

-

mA

-

10.3

-

mA

DC-to-DC converter disabled, Vcc = 3 V
92dBm RX sensitivity[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).

[2]

Characterized through bench measurements using typical samples, with 50 ohm loading on RF port.

[3]

Guaranteed by characterization, not tested in production.

[4]2Mbps mode is only supported when AHB clock is 32MHz.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

Table 16. Static characteristics: Power consumption in sleep, and power-down modes
Tamb = 40 C to +85 C; unless otherwise specified.
Min

Typ[1][2]Max[3]

SymbolParameter

Conditions

ICC

supply current

Sleep mode:
all SRAM on. Flash in standby mode. DC-to-DC converter enabled, Vcc = 3 V.

Unit

32 MHz crystal oscillator
CLK_AHB = 8 MHz

-

350

-

A

CLK_AHB = 16 MHz

-

420

-

A

Sleep mode:
all SRAM on. Flash in standby mode. DC-to-DC converter disabled, Vcc = 3 V.
32 MHz crystal oscillator
CLK_AHB = 8 MHz

-

600

-

A

CLK_AHB = 16 MHz

-

750

-

A

Power down 1 mode; all clocks off.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.
32 KB SRAM powered

-

1.0

-

A

64 KB SRAM powered

-

1.2

-

A

128 KB SRAM powered

-

1.8

-

A

Power down 0 mode; 32.768 kHz crystal oscillator on.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.
32 KB SRAM powered

-

2.5

-

A

64 KB SRAM powered

-

2.8

-

A

128 KB SRAM powered

-

3.4

-

A

Power down 0 mode; 32kHz on-chip RC oscillator on.
Flash is powered down. DC-DC disabled, Vcc = 3 V. Tamb = 25 C.
32 KB SRAM powered

-

2.2

-

A

64 KB SRAM powered

-

2.3

-

A

128 KB SRAM powered

-

2.9

-

A

[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C).

[2]

Characterized through bench measurements using typical samples.

[3]

Guaranteed by characterization, not tested in production.

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Table 17. Static characteristics: ADC power consumption
Tamb = 40 C to +85 C, unless otherwise specified.1.62 V  VCC  3.6 V.
Min

Typ[1]

Max

Unit

Internal reference

-

200

-

A

PGA, gain = 1

-

330

-

A

PGA, gain = 16

-

660

-

A

Modulator

-

270

-

A

Internal reference

-

140

-

A

PGA, gain = 1

-

220

-

A

PGA, gain = 8

-

880

-

A

Modulator

-

100

-

A

SymbolParameter

Conditions

ICC

analog supply current

2 MHz sampling clock

500 kHz sampling clock[1]

Typical ratings are not guaranteed. Typical values listed are at room temperature (25 °C), nominal supply voltages.

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11.4 Pin characteristics
Table 18. Static characteristics: pin characteristics
Tamb = 40 C to +85 C, unless otherwise specified. 1.62 V  VCC  3.6 V unless otherwise specified. Values tested in
production unless otherwise specified.
SymbolParameter

Conditions

Min

Typ[1]

Max

Unit
V

RSTN pin
VIH

HIGH-level input voltage

0.8  VCC

-

3.6

VIL

LOW-level input voltage

0.5

-

0.3  VCC V

Vhys

hysteresis voltage

0.05  VCC -

-

V

-

25

300

nA

V

Standard I/O pins
IIN

[2]

Input leakage current (perGPIO pin)

Input characteristics
VIH

HIGH-level input voltage

1.62 V  VCC < 3.6 V

0.7 VCC

-

-

VIL

LOW-level input voltage

1.62 V  VCC < 3.6 V--

0.3VCC V

Vhys

hysteresis voltage

0.1  VCC

-

-

V

[3]

Output characteristicsVO

output voltage

0

-

VCC

V

VOH

HIGH-level output voltage IOH = 4 mA[4]; 1.62 V  VCC < 3.6 V

output active

VCC-0.3

-

-

V

VOL

LOW-level output voltage IOL = 4 mA[4]; 1.62 V  VCC < 3.6 V

-

-

0.45

V

IOH

HIGH-level output current 1.62 V  VCC < 3.6 V

4

-

-

mA

IOL

LOW-level output current 1.62 V  VCC < 3.6 V

4

-

-

mA

RPD

Pull-down register

1.62 V  VCC < 3.6 V

-

170

-

kΩ

RPU

Pull-up resistor

1.62 V  VCC < 3.6 V

-

90

-

kΩ

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltage.

[2]

The typical value is at 25 °C and 3 V.

[3]Guaranteed by design, not tested in production.

[4]

Pin’s settings DRV_CTRL must be set to high to drive 4mA output.

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12. Dynamic characteristics
12.1 Start-up behavior
Table 19. Start-up characteristics
Tamb = 40 C to +85 C; 1.62 V  VCC  3.6 V
Max

Unit

ta

Symbol Parameter
32MHz RCO
start-up

Conditions[1][2]

10stb

POR ready[1][2]

10stc

VDD1~3 rampup

[1][2]10s

td

PMU supply
ramp up[1][2]

1

ms

te

RSTN delay[1][2]

1

ms

tf

boot time[1][2]

218

s

[1]

See Figure 10.

[2]

Based on characterization, not tested in production.

Min

Typ

Fig 10. Start-up timing

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

12.2 Flash memory
Table 20. Flash characteristics
Tamb = 40 C to +85 C, unless otherwise specified. 1.62 V  VCC  3.6 V
SymbolParameter

Conditions

endurance

Nendu

page erase/program

retention time

tret

[1]

Min

Typ

Max

Unit

10000

-

-

cyclesmass erase/program

10000

-

-

cyclespowered

10

-

-

years

unpowered

10

-

-

years

ter

erase time

page/mass

-

-

100

ms

tprog

programming
time

word

-

-

20

ms

[1]

Number of erase/program cycles.

12.3 I/O pins
Table 21. Dynamic characteristic: I/O pins[1]Tamb = 40 C to +85 C; 1.62 V  VCC  3.6 V
Symbol Parameter Conditions

Min

Typ

Max

Unit

Standard I/O pinstrtf

QN908x

Product data sheet

rise time

fall time

pin configured as output; standard mode

[2][3]

-

-

2.4

ns

pin configured as output; high drivemode[2][3]

-

-

1.6

ns

pin configured as output; standard mode

[2][3]

-

-

4.2

ns

pin configured as output; high drivemode[2][3]

-

-

1.6

ns

tr

rise time

pin configured as input

[4]

-

-

2

ns

tf

fall time

pin configured as input

[4]

-

-

2

ns

[1]

Simulated data.

[2]

Simulated using 10 cm of 50  PCB trace with 5 pF receiver input. Rise and fall times measured between
80 % and 20 % of the full output signal level.

[3]

The slew rate is configured by register. See the QN9080 user manual.

[4]

CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.

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12.4 Wake-up process
Table 22. Dynamic characteristic: Typical wake-up times from low power modes
VCC = 3.0 V;Tamb = 25 C; using 32MHz Oscillator as the system clock.
Symbol Parameter
twake

wake-uptime

Conditions
from Sleep mode, waked up by
GPIO interrupt, to code executing
in flash[2][5]

from power down mode, waked up
by GPIO interrupt, to code
executing in flash[2][5]

from power down mode, waked up
by GPIO interrupt, to Bluetooth
advertising[3][6]

from RSTN pin deasserted, tocode executing in flash[4][5]

from power-up, to code executing
in flash[5][5]Min

Typ[1]

-

3

s

-

10

s

-

7

ms

-

218

s

1.2

ms

Max Unit[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages. Based on characterization. Not tested in production.

[2]

The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler.

[3]

The time measured is the time between when a GPIO input pin is triggered to when a peripheral starts
advertising.

[4]

The wake-up time measured is the time between when the RSTN pin is de-asserted to wake the[5]

The wake-up time measured is the time between power on and when a GPIO output pin is set in the reset
handler.

[6]

16 MHz HFXO enabled, all peripherals off; CLK_AHB=16 MHz.

device up and when a GPIO output pin is set in the reset handler.

12.5 Internal 32MHz oscillator
Table 23. Dynamic characteristic: internal 32MHz oscillator
Tamb = 25 C; 1.62 V  VCC  3.6 V.
Min

Typ[1]

Max

Unit

oscillator frequency

-

32

-

MHz

temperature coefficient

-

0.04

-

%/C

foscVCC

oscillator frequency
variation with supply
voltage

-

3

-

%/V

tstartstart-up time

-

-

2

s

Icc

current consumption

-

60

-

A

SymbolParameter

fosc(HFRCO)
TC[1]

QN908x

Product data sheet

Conditions

Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.

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12.6 External high frequency crystal oscillator
Table 24. Dynamic characteristic: external high frequency crystal oscillator
Tamb = 25 C; 1.62 V  VCC  3.6 V.
SymbolParameter

fxtal

crystal frequency

fxtalcrystal frequency
accuracy

ESR

equivalent serial
resistanceCLload capacitancetstartstart-up time

Icc

[1]

current consumption

Conditions

Min

Typ[1]

Max

Unit

-

16

-

MHz

-

32

-

MHz

50

-

+50

ppm

16 MHz, 9 pF
load

-

-

100



32 MHz, 9 pF
load

-

-

100



12

pF

16 MHz, 9 pF
load

5
-

-

700

s

32 MHz, 9 pF
load

-

-

400

s

16 MHz, 9 pF
load

-

100

-

A

32 MHz, 9 pF
load

-

200

-

A

Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.

12.7 External 32.768 kHz crystal oscillator
See Section 13.5 for connecting the 32.768 kHz oscillator to an external clock source.
Table 25. Dynamic characteristic: LFXO
Tamb = 40 C to +85 C; 1.62  VCC  3.6[1]SymbolParameter

Conditions

Min

Typ[1]--

32.768

-50

-

+50

ppm

-

-

100

k

fxtal

input frequency

fxtalFrequency tolerance

ESR

Equivalent serial
resistance

Product data sheet

5

Unit
kHz

CL

Load capacitance

12

pF

tstart(LFXO)

Start-up time

9 pF load

-

-

1

S

Icc(LFXO)

Current consumption

9 pF load

-

1

-

A

[1]

QN908x9 pF load

Max

Parameters are valid over operating temperature range unless otherwise specified.

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Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

12.8 Internal 32 kHz oscillator
Table 26. Dynamic characteristics: internal 32 kHz oscillator
Tamb = 40 C to +85 C; 1.62  VCC  3.6[1]SymbolParameter[2]Min

Typ[1]

-

32

fosc

oscillator frequency

fosc(acc)

clock accuracy after
calibration

-500

TC

temperature coefficient-foscVCC

oscillator frequency
variation with supply
voltagetstart
Icc

Max

Unit

-

kHz

+500

ppm

0.04

-

%/C

-

3

-

%/V

start-up time

-

-

1

mS

current consumption

-

1

-

A

[1]

Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2]

The typical frequency spread over processing and temperature (Tamb = -40 °C to +85 °C) is ±40 %.

12.9 SPI interfaces
In master mode, the maximum supported bit rate is 16 Mbit/s. In slave mode, assuming a
set-up time of 4 ns for the external device and neglecting any PCB trace delays, themaximum supported bit rate is 16 Mbit/s. The actual bit rate depends on the delays
introduced by the external trace and the external device.
Table 27. SPI dynamic characteristics[1]Tamb = 40 C to 85 C; VCC = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew =1 ns; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
SymbolParameter

Conditions

Min

Max

Unit

SPI mastertDS

data set-up time

5

-

ns

tDH

data hold time

5

-

ns

tv(Q)

data output valid time

4

7

ns

tDS

data set-up time

7

-

ns

tDH

data hold time

5

-

ns

tv(Q)

data output valid time

2

16

ns

SPI slave[1]

QN908x

Product data sheet

Based on simulated values.

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Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)

SSEL

MOSI (CPHA = 0)

tv(Q)

tv(Q)

DATA VALID (MSB)

DATA VALIDDATA VALID (MSB)

MOSI (CPHA = 1)

IDLE

DATA VALID (MSB)

DATA VALID (LSB)

IDLE

DATA VALID (MSB)

tDH

tDS

MISO (CPHA = 0)

DATA VALID (LSB)

DATA VALID

tv(Q)

tv(Q)

DATA VALID (LSB)

DATA VALIDtDS

MISO (CPHA = 1)
DATA VALID (LSB)

DATA VALID (MSB)IDLE

DATA VALID (MSB)

DATA VALID (MSB)IDLE

DATA VALID (MSB)tDH
DATA VALID

aaa-014969

Tcy(clk) = CLK_AHB/DIVVAL with CLK_AHB = AHB bus clock frequency. DIVVAL is the SPI clock divider. See the QN908x Usermanual.

Fig 11. SPI master timing

QN908x

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Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)

SSEL

MISO (CPHA = 0)

tv(Q)

tv(Q)

DATA VALID (MSB)

DATA VALIDDATA VALID (MSB)MISO (CPHA = 1)

IDLE

DATA VALID (MSB)

DATA VALID (LSB)

IDLE

DATA VALID (MSB)

tDH

tDS

MOSI (CPHA = 0)

DATA VALID (LSB)

DATA VALID

tv(Q)

tv(Q)

DATA VALID (LSB)

DATA VALIDtDS

MOSI (CPHA = 1)
DATA VALID (LSB)

DATA VALID (MSB)IDLE

DATA VALID (MSB)

DATA VALID (MSB)IDLE

DATA VALID (MSB)tDH
DATA VALID

aaa-014970

Fig 12. SPI slave timing

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12.10 USART interface
In master and slave synchronous modes, the maximum supported bit rate is 1
Mbit/sec.The actual bit rate depends on the delays introduced by the external trace, theexternal device, and capacitive loading.
Table 28. USART dynamic characteristics[1]Tamb = 40 C to 85 C; VCC = 1.62V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew =1 ns; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol Parameter

Conditions

Min

Max

Unit

USART master (in synchronous mode)tsu(D)

data input set-up time

21

-

ns

th(D)

data input hold time

2

-

ns

tv(Q)

data output valid time

5

12

ns

USART slave (in synchronous mode)tsu(D)

data input set-up time

6

-

ns

th(D)

data input hold time

6

-

ns

tv(Q)

data output valid time

2

21

ns

[1]

Based on simulated values.

Tcy(clk)

Un_SCLK (CLKPOL = 0)

Un_SCLK (CLKPOL = 1)
tv(Q)
TXD

tvQ)

START

BIT0

BIT1

tsu(D) th(D)

RXD

START

BIT1

BIT0

aaa-015074

In master mode, Tcy(clk) = CLK_AHB/BRGVAL. See the QN908x user manual.

Fig 13. USART timing

12.11 SPIFI
Table 29. Dynamic characteristics: SPIFI[1]Tamb = 40 C to 85 C; VCC = 1.62 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew
= 1 ns; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
SymbolParameter

Tcy(clk)

Conditions

Min

Typ

Max

Unit

clock cycle time

-

62.5

-

ns

tDS

data set-up time

11

-

-

ns

tDH

data hold time

4

-

-

ns

tv(Q)

data output valid time

-5

-

7

ns

SPIFI

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Based on simulated values.

Tcy(clk)

SPIFI_SCK

tv(Q)

th(Q)

DATA VALIDSPIFI data out

DATA VALIDtDSDATA VALIDSPIFI data in

tDH
DATA VALID

002aah409

Fig 14. SPI flash interface timing (mode 0)

12.12 SCTimer output timing
Table 30. SCTimer output dynamic characteristics
Tamb = 40 C to 85 C; 1.62 V  VCC  3.6 V CL = 30 pF. Simulated skew (over process, voltage,
and temperature) of any two SCT fixed-pin output signals; sampled at 10 % and 90 % of the signal
level; values guaranteed by design.
SymbolParameter

Conditions

Min

Typ

Max

Unit

tsk(o)

output skew time

-

-

-

1.1

ns

12.13 USB interface characteristics
Table 31. Dynamic characteristics: USB pins (full speed)
CL = 50 pF; Rpu = 1.5 k on D+ to VCC, unless otherwise specified; 3.0 V  VCC  3.6 V.
SymbolParameter

Conditions

Min

Typ

Max

Unit

tr

rise time

CL=50pF, 10 %to 90 %

4

-

20

ns

tf

fall time

CL=50pF, 10 %to 90 %

4

-

20

ns

tFRFM

differential rise and fall time matching

tr / tf

90

-

111

%

VCRS

output signal crossover voltage

1.3

-

2.0

V

tFEOPTsource SE0 interval of EOP

see Figure 15

160

-

175

ns

tFDEOP

source jitter for differential transition
to SE0 transition

see Figure 15

-2

-

+5

ns

tJR1

receiver jitter to next transition

-18.5

-

+18.5

ns

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Table 31. Dynamic characteristics: USB pins (full speed) …continued
CL = 50 pF; Rpu = 1.5 k on D+ to VCC, unless otherwise specified; 3.0 V  VCC  3.6 V.

[1]

SymbolParameter

Conditions

tJR2

receiver jitter for paired transitions

10 % to 90 %tEOPR1

EOP width at receivermust reject as
EOP; seeFigure 15[1]

tEOPR2

EOP width at receivermust accept as
EOP; seeFigure 15

[1]

Min

Typ

Max

Unit

-9

-

+9

ns

40

-

-

ns

82

-

-

ns

Characterized but not implemented as production test. Guaranteed by design.

TPERIOD

crossover point
extendedcrossover point

differential
data lines

source EOP width: tFEOPT
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOP

receiver EOP width: tEOPR1, tEOPR2
002aab561

Fig 15. Differential data-to-EOP transition skew and EOP width

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Product data sheet

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13. RF characteristics
13.1 Receiver
Table 32. Receiver characteristics
Tamb = 25 C; based on characterization; not tested in production. VCC = 3 V; fc = 2440 MHz; BER <0.1 %SymbolSRX

SRX2M

Parameter

Conditions

Min

Typ

Max

Unit

-

95

-

dBm

RX sensitivity

high performancemode with DC-to-DC
converter disabled

low power mode with DC-to-DC converter

94

-

dBm

DC-to-DC converter
disabled

-

-92

-

dBm

DC-to-DC converter
enabled

-

-91.5

-

dBm

250kbps,
GFSK-BT=0.5,
h=0.5

-

95

-

dBm

-

0

-

dBm

RX sensitivity(2Mbps)SGFSK

GFSK RXsensitivity

Pi(max)maximum input
power
co-channel

C/Iimagesup(oob)

-

6

-

dB

adjacent channel @ carrier-to-interfere
1 MHznce ratio
alternate channel @ 2 MHz

4

-

dB

41

-

dB

image rejection

41

-

dB

30 MHz to 2000 MHz 1

-

-

dBm

2003 MHz to 2399
MHz

10

-

-

dBm

2484 MHz to 2997
MHz

10

-

-

dBm

3 GHz to 12.75 GHz

10

-

-

dBm

out-of-band
suppression-

Table 33.Receiver specification with GFSK modulations (Data Rate <= 1Mbps)
Tamb = 25 C; based on characterization; not tested in production. VCC = 3 V; fc = 2440 MHz; BER < 0.1 %GFSK BT=0.5,h=0.5

Adjacent/Alternate Channel Selectivity (dB)

Data Rate(kbps)

TypicalSensitivity(dBm)

DesiredInterferer
Interferer
signal level at -/+1*
at -/+2*(dBm)
channelchannelBW offset[1] BW offset

Interfererat -/+3*
channelBW offset

Interfererat -/+4*
channelBW offset

Cochannel

1000

-95

-67

-6

-43

-46

-49

5

500

-95

-67

-5

-31

-33

-35

4

250

-95

-67

-9

-32

-36

-42

0

[1]Channel BW offset equals to 1MHz.

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Table 34.Receiver specification with GFSK modulations (Data Rate = 2Mbps)
Tamb = 25 C; based on characterization; not tested in production. VCC = 3 V; fc = 2440 MHz; BER < 0.1 %GFSK BT=0.5, h=0.5

Adjacent/Alternate Channel Selectivity (dB)

Data Rate(kbps)

TypicalSensitivity(dBm)

DesiredInterferer
Interferer
signal level at -/+2*
at -/+4*(dBm)
channelchannelBW offset[1] BW offset

Interfererat -/+6*
channelBW offset

Interfererat -/+8*
channelBW offset

Cochannel

2000

-92

-67

-46

-51

5

-8

-44

[1]Channel BW offset equals to 1MHz.

13.2 Transmitter
Table 35. Transmitter characteristics
Tamb = 25 C; based on characterization; not tested in production.VCC = 3 V; fc = 2440 MHz

QN908x

Product data sheet

SymbolParameterfo(RF)

Conditions

Min

Typ

Max

RF output
frequency

2400-

2483.5 MHz

CSchannelseparation

-

2

-

MHz

Po

output power

20

-

+2

dBm

TX power

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14. Analog characteristics
14.1 BOD
Table 36. BOD static characteristics
Tamb = 25 C; based on characterization; not tested in production.
SymbolParameter

Conditions

Vththreshold voltage

interrupt level 0

Min

Typ

Max

Unit

assertion

-

2.05

-

V

de-assertion

-

2.35

-

V

-

1.50

-

V

assertion

-

2.45

-

V

de-assertion

-

2.80

-

V

-

1.85

-

V

reset level 0
assertionVththreshold voltage

interrupt level 1

reset level 1
assertionVththreshold voltage

interrupt level 2
assertion

-

2.70

-

V

de-assertion

-

3.10

-

V

-

2.0

-

V

assertion

-

3.05

-

V

de-assertion

-

3.45

-

V

-

2.35

-

V

reset level 2
assertionVththreshold voltage

interrupt level 3

reset level 3
assertion

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14.2 ADC
Table 37.16-bit ADC static characteristics
Tamb = 40 C to +85 C; 1.62 V  VCC  3.6 V; VREFP = VDDA; VSSA = VREFN = GND. ADC calibrated at Tamb =25C.
SymbolParameter

VI

Conditions

Min

Typ

Max

input voltage range VREF = 1.2 V(VINP-VINN)-

0.8 
VREF/(
PGA_G
AIN
ADC_G
AIN)

-

VREF = VCC-

0.5 
VREF/(PGA_G
AIN 
ADC_G
AIN)

-

-

10

DC signal, PGA enabled>10

DC signal, PGA bypassed,
2MHz sampling clock-Ci

input capacitanceZi

input impedance

Unit

-

pF

-

M

50

-

k

fclk(ADC)

ADC samplingclock frequency

-

-

2

MHz

fc

output date rate?

-

-

31.25

ksps

ENOB

Effective number

500 kHz sampling clock,over-sampling rate = 256,
data rate = 1.9 kHz, all gains,
all temperature, all Vcc

14.2

15.2

-

bit

2 MHz sampling clock,over-sampling rate = 256,
data rate = 7.8 kHz, all gains,
all temperature, all Vcc

12.9

14.4

-

bit

PGA enabled-+/-30[1]+/-200ppm-+/-60[1]+/-250

ppm

-

2

4

%

20

50

-

dB

-40

-50

-

dB

INL

integralnon-linearity

PGA bypassed

EO

gain error

CMRR

common mode
rejection

at DC

PSRR

power-supply
rejection

at DC

[2]

VBG ( 25 C) 1.2V Bandgap
voltage reference

Tamb = 25 C[3][4]

1.216

1.222

1.227

V

1.2V Bandgap
VBG( -40~85 C) voltage reference

Tamb = -40~85 C[3][4]

1.211

-

1.232

V

[4]

-

3

-

mV

BG_SEL steps[1]

QN908x

Product data sheet

Characterized but not implemented as production test. Guaranteed by design.

[2]

CMRR degrades severely if Vcc < 3V

[3]

BG_SEL = 0x08
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All values are obtained at Vcc = 3V

14.3 Temperature sensor
Table 38. Temperature sensor static and dynamic characteristics
VDD = VDDA = 1.62 V to 3.6 V
SymbolParameter

Conditions

Min

Typ[1]Max

Unit

Tm (C)

range

Tamb = 40 C to +85 C

-40

-

+85

C

dTm (C)

error

with 1-point calibration

-

[1]

1

3

C

3

5

C

Min

Typ

Max

Unit

-

8

-

bits

without calibration

Typical value is obtained at Tamb =25C, VCC / VDD =3V

14.4 DAC
Table 39. DAC static and dynamic characteristics
VCC = 1.62 V to 3.6 V
SymbolParameter

Conditions

resolution
DNL

differential
nonlinearity

[1]

-

0.2

-

LSB

INL

integralnonlinearity

[1]

-

0.2

-

LSB

bandwidth of theinternal low passfilter

-

150

-

kHz

output voltage
range

0.7

-

VCC
0.7

Vfull scale output
voltage swing
step size

40

-

197

mV

-

10

-

pF

-

-

1

MHz

Vout

capacitive loadstability

RL=1 kfrequency ofsample[1]

Characterized but not implemented as production test. Guaranteed by design.

14.5 Analog comparator
Table 40.Analog comparator static and dynamic characteristics
VCC = 1.62 V to 3.6 V

QN908x

Product data sheet

SymbolParameter

Min

Typ

Max

Unit

Vi

input voltage

Conditions

0

-

VCC

V

ICC(int)A

analog internal
supply current

-

0.3

-

A

Vhys

hysteresis

40

55

mV

use VBG as reference voltage
35(register bit
ACMP_VREF_SEL=1,ACM_REF=8)

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14.5.1 Capacitive sense
Table 41. Capacitive sense static and dynamic characteristics
VDD = 1.62 V to 3.6 V

QN908x

Product data sheet

SymbolParameter

Min

Typ

Max

Unit

ICC

supply current

Conditions

-

2.6

-

A

noise level

-

0.2%

-

/base
cap

temperature
coefficient

-

0.02

-

%/C

input cap range

-

-

100

pF

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15. Application information
15.1 Schematic for QN9080 with DC-to-DC converter

Fig 16. QN9080 typical application schematic with DC-to-DC converter

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15.2 Schematic for QN9080 without DC-to-DC converter

Fig 17. QN9080 typical application schematic without DC-to-DC converter

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15.3 Schematic for QN9083 with DC-to-DC converter

Fig 18. QN9083 typical application schematic with DC-to-DC converter

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15.4 Schematic for QN9083 without DC-to-DC converter

Fig 19. QN9083 typical application schematic without DC-to-DC converter

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15.5 QN908x external component list
Table 42.

External component list

Component

Description

Value

C4

capacitor for RF harmonic filter

1.8 pF

C5

capacitor for RF harmonic filter

1.8 pF

C1, C3, C7, C10

supply decoupling capacitors

100 nF, X5R, 10 %, 6.3 V, 0402

C6

supply decoupling capacitor

4.7 F, X5R, 10 %, 6.3 V, 0402

C2

supply decoupling capacitor

1 F, X7R, 5 %, 6.3 V, 0402

C8

capacitor used for reset

0.1 F, 5 %, 6.3 V, 0402

C9

capacitor used for RF front-end

8.2 pF, C0G,0.5pF, 50V, 0402

L2

inductor for RF harmonic filter

3.3 nH

L1

chip inductor for DC-to-DC converter

10 H

L3

chip inductor for DC-to-DC converter

10 nH

Y1

crystal

16 MHz or 32 MHz

Y2crystal32.768 kHz

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16. Package outline

Fig 20. HVQFN48 package outline
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Fig 21. WLCSP Package outline

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17. SolderingFig 22. HVQFN48 Soldering footprint

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Fig 23. WLCSP Soldering footprint

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18. Abbreviations
Table 43.

Abbreviations

AcronymDescription

AHB

Advanced High-performance Bus

APB

Advanced Peripheral Bus

API

Application Programming Interface

DMA

Direct Memory Access

GPIO

General-Purpose Input Output

LSB

Least Significant Bit

MCU

MicroController Unit

SPI

Serial Peripheral Interface

USART

Universal Asynchronous Receiver/Transmitter

TTL

Transistor-Transistor Logic

ENOB

Equivalent Number of Bits

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19. Revision history
Table 44.

Revision history

Document ID

Release date Substantial changes

QN908x Rev.1.3

01/2021• Updated the peak power to 1.6 mW in Section 2 “General

Supersedes
QN908x v.1.2

description”• Added IIN in Table 18.
• Updated HVQFN48-pin package outline in Figure 20
QN908x Rev.1.2

04/2018

Add Silicon revision in Table 2.

QN908x v.1.1

QN908x Rev.1.1

02/2018

Append characteristics data

QN908x v.1.0

QN908x Rev.1.0

07/2017

Initial Release-

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20. Legal information
20.1 Data sheet status
Document status[1][2]Product status[3]Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

Preliminary [short] data sheet

Qualification

This document contains data from the preliminary specification.

Product [short] data sheet

Production

This document contains the product specification.

[1]

Please consult the most recently issued document before initiating or completing a design.

[2]

The term ‘short data sheet’ is explained in section “Definitions”.

[3]

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

20.2 Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences ofuse of such information.
Short data sheet — A short data sheet is an extract from a full data sheetwith the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed andfull information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, thefull data sheet shall prevail.
Product specification — The information and data provided in a Productdata sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors andcustomer have explicitly agreed otherwise in writing. In no event however,shall an agreement be valid in which the NXP Semiconductors product isdeemed to offer functions and qualities beyond those described in the
Product data sheet.

20.3 Disclaimers
Limited warranty and liability — Information in this document is believed tobe accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for theconsequences of use of such information. NXP Semiconductors takes noresponsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordancewith the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to makechanges to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

QN908x

Product data sheet

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications andproducts planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with theirapplications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in thecustomer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications andthe products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or theCharacteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects toapplying the customer’s general terms and conditions with regard to thepurchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted orconstrued as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents orother industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use inautomotive applications to automotive specifications and standards, customer(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design anduse of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.

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21. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.

Ordering information . . . . . . . . . . . . . . . . . . . . .5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .5
Device revision table . . . . . . . . . . . . . . . . . . . . .6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . .10
Termination of unused pins. . . . . . . . . . . . . . . .18
Pin states in different power modes . . . . . . . . .18
SRAM memory blocks . . . . . . . . . . . . . . . . . . .20
Memory map options . . . . . . . . . . . . . . . . . . . .21
Peripheral configuration in reduced power modes
26
Table 10. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 11. Thermal resistance . . . . . . . . . . . . . . . . . . . . . .40
Table 12. General operating conditions . . . . . . . . . . . . . .41
Table 13. CoreMark score . . . . . . . . . . . . . . . . . . . . . . . .41
Table 14. Static characteristics: Power consumption in
active modes . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 15. Static characteristics: Bluetooth LE power
consumption in active modes . . . . . . . . . . . . . .43
Table 16. Static characteristics: Power consumption insleep, and power-down modes. . . . . . . . . . . . .44
Table 17. Static characteristics: ADC power consumption45
Table 18. Static characteristics: pin characteristics . . . . .46
Table 19. Start-up characteristics . . . . . . . . . . . . . . . . . . .47
Table 20. Flash characteristics . . . . . . . . . . . . . . . . . . . . .48
Table 21. Dynamic characteristic: I/O pins[1] . . . . . . . . . .48
Table 22. Dynamic characteristic: Typical wake-up times
from low power modes . . . . . . . . . . . . . . . . . . .49
Table 23. Dynamic characteristic: internal 32MHz oscillator
49
Table 24. Dynamic characteristic: external high frequency
crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . .50
Table 25. Dynamic characteristic: LFXO . . . . . . . . . . . . .50
Table 26. Dynamic characteristics: internal 32 kHz oscillator
51
Table 27. SPI dynamic characteristics[1] . . . . . . . . . . . . .51
Table 28. USART dynamic characteristics[1] . . . . . . . . . .54
Table 29. Dynamic characteristics: SPIFI[1] . . . . . . . . . . .54
Table 30. SCTimer output dynamic characteristics . . . . .55
Table 31. Dynamic characteristics: USB pins (full speed) .
55
Table 32. Receiver characteristics . . . . . . . . . . . . . . . . . .57
Table 33. Receiver specification with GFSK modulations(Data Rate <= 1Mbps) . . . . . . . . . . . . . . . . . . .57
Table 34. Receiver specification with GFSK modulations(Data Rate = 2Mbps) . . . . . . . . . . . . . . . . . . . .58
Table 35. Transmitter characteristics . . . . . . . . . . . . . . . .58
Table 36. BOD static characteristics. . . . . . . . . . . . . . . . .59
Table 37. 16-bit ADC static characteristics . . . . . . . . . . .60
Table 38. Temperature sensor static and dynamic
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 39. DAC static and dynamic characteristics . . . . . .61
Table 40. Analog comparator static and dynamic
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 41. Capacitive sense static and dynamic
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 42. External component list . . . . . . . . . . . . . . . . . .67
QN908x

Product data sheet

Table 43. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 44. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73

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Rev. 1.3 — 6 January 2021

© NXP B.V. 2021. All rights reserved.

76 of 80

QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

22. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.

HVQFN48 package marking . . . . . . . . . . . . . . . . .5
WLCSP47 package marking . . . . . . . . . . . . . . . . .5
QN908x block diagram . . . . . . . . . . . . . . . . . . . . .7
HVQFN48 pin configuration . . . . . . . . . . . . . . . . . .8
WLCSP pin configuration. . . . . . . . . . . . . . . . . . . .9
QN908x memory mapping . . . . . . . . . . . . . . . . .23
QN908x APB memory map . . . . . . . . . . . . . . . . .24
QN908x power supply . . . . . . . . . . . . . . . . . . . . .25
QN908x clock generation . . . . . . . . . . . . . . . . . .37
Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SPI master timing . . . . . . . . . . . . . . . . . . . . . . . .52
SPI slave timing . . . . . . . . . . . . . . . . . . . . . . . . .53
USART timing . . . . . . . . . . . . . . . . . . . . . . . . . . .54
SPI flash interface timing (mode 0) . . . . . . . . . . .55
Differential data-to-EOP transition skew and EOP
width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
QN9080 typical application schematic with
DC-to-DC converter . . . . . . . . . . . . . . . . . . . . . . .63
QN9080 typical application schematic without
DC-to-DC converter . . . . . . . . . . . . . . . . . . . . . . .64
QN9083 typical application schematic with
DC-to-DC converter . . . . . . . . . . . . . . . . . . . . . . .65
QN9083 typical application schematic without
DC-to-DC converter . . . . . . . . . . . . . . . . . . . . . . .66
HVQFN48 package outline . . . . . . . . . . . . . . . . .68
WLCSP Package outline . . . . . . . . . . . . . . . . . . .69
HVQFN48 Soldering footprint . . . . . . . . . . . . . . .70
WLCSP Soldering footprint . . . . . . . . . . . . . . . . .71

QN908x

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.3 — 6 January 2021

© NXP B.V. 2021. All rights reserved.

77 of 80

QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

23. Contents
1
2
3
4
4.1
5
6
7
7.1
7.2
7.2.1
7.2.2
8
8.1
8.2
8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 5
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinning information . . . . . . . . . . . . . . . . . . . . . . 8
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
Termination of unused pins. . . . . . . . . . . . . . . 18
Pin states in different power modes . . . . . . . . 18
Functional description . . . . . . . . . . . . . . . . . . 19
Architectural overview . . . . . . . . . . . . . . . . . . 19
ARM Cortex-M4 processor . . . . . . . . . . . . . . . 19
ARM Cortex-M4 integrated Floating Point Unit
(FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.4
Memory Protection Unit (MPU). . . . . . . . . . . . 19
8.5
Nested Vectored Interrupt Controller (NVIC) for
Cortex-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.5.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 20
8.6
System Tick timer (SysTick) . . . . . . . . . . . . . . 20
8.7
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 20
8.8
On-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.9
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 21
8.10
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 21
8.11
Power management . . . . . . . . . . . . . . . . . . . . 24
8.11.1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.11.2
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.11.2.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.11.2.2 Power-down 0 mode. . . . . . . . . . . . . . . . . . . . 25
8.11.2.3 Power-down 1 mode. . . . . . . . . . . . . . . . . . . . 26
8.11.3
Brown-Out Detection (BOD) . . . . . . . . . . . . . . 26
8.12
General-Purpose Input Output (GPIO) . . . . . . 26
8.12.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.13
Pin interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.13.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.14
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 27
8.14.1
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 27
8.14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.15
Digital serial peripherals . . . . . . . . . . . . . . . . . 27
8.15.1
USB 2.0 (full-speed) device controller . . . . . . 27
8.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.15.2SPI Flash Interface (SPIFI) . . . . . . . . . . . . . . 28
8.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.15.3
Flexcomm serial communication (0,1,2,3) . . . 28
8.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.15.4
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 28
8.15.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.15.5
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.15.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.15.6
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 30
8.15.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
QN908x

Product data sheet

8.16
8.16.18.16.1.1
8.16.28.16.2.1
8.17
8.17.1
8.17.1.1
8.17.28.17.38.17.48.17.4.1
8.17.58.17.5.1
8.17.6
8.17.6.1
8.18
8.19
8.20

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard timer/counter (CTIMER0 to 3) . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCTimer/PWM . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog peripherals . . . . . . . . . . . . . . . . . . . . .
16-bit Analog-to-Digital Converter (ADC). . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature sensor . . . . . . . . . . . . . . . . . . . .
Battery monitor. . . . . . . . . . . . . . . . . . . . . . . .
Analog comparators (ACMP0, ACMP1). . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital-to-Analog Converter (DAC). . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive sense . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Number Generator (RNG) . . . . . . . .
Advanced Encryption Standard (AES)
coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . .
8.21
Quadrature DECoder (QDEC) . . . . . . . . . . . .
8.22
Fusion Signal Processor (FSP) . . . . . . . . . . .
8.22.1Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.23
Clock management . . . . . . . . . . . . . . . . . . . .
8.23.1Clock sources . . . . . . . . . . . . . . . . . . . . . . . .
8.23.1.1 Internal 32 MHz oscillator . . . . . . . . . . . . . . .
8.23.1.2 Internal 32 kHz oscillator . . . . . . . . . . . . . . . .
8.23.1.3 External high frequency crystal oscillator. . . .
8.23.1.4 External 32.768 kHz crystal oscillator . . . . . .
8.23.2Clock generation . . . . . . . . . . . . . . . . . . . . . .
8.24
Code security . . . . . . . . . . . . . . . . . . . . . . . .
8.25
Emulation and debugging . . . . . . . . . . . . . . .
9Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
10Thermal characteristics . . . . . . . . . . . . . . . . .
11
Static characteristics . . . . . . . . . . . . . . . . . . .
11.1
General operating conditions . . . . . . . . . . . . .
11.2
CoreMark data . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Power consumption . . . . . . . . . . . . . . . . . . . .
11.4
Pin characteristics . . . . . . . . . . . . . . . . . . . . .
12Dynamic characteristics. . . . . . . . . . . . . . . . .
12.1
Start-up behavior . . . . . . . . . . . . . . . . . . . . . .
12.2
Flash memory . . . . . . . . . . . . . . . . . . . . . . . .
12.3
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4
Wake-up process . . . . . . . . . . . . . . . . . . . . . .
12.5Internal 32MHz oscillator . . . . . . . . . . . . . . . .
12.6
External high frequency crystal oscillator. . . .
12.7
External 32.768 kHz crystal oscillator . . . . . .
12.8Internal 32 kHz oscillator . . . . . . . . . . . . . . . .
12.9
SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . .
12.10
USART interface . . . . . . . . . . . . . . . . . . . . . .
12.11
SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.12
SCTimer output timing . . . . . . . . . . . . . . . . . .
12.13
USB interface characteristics. . . . . . . . . . . . .
13
RF characteristics . . . . . . . . . . . . . . . . . . . . . .
13.1
Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

All information provided in this document is subject to legal disclaimers.

Rev. 1.3 — 6 January 2021

30
30
30
31
31
33
33
33
34
34
34
34
34
34
35
35
35
35
35
35
36
36
36
36
36
37
37
37
37
37
38
39
40
41
41
41
41
46
47
47
48
48
49
49
50
50
51
51
54
54
55
55
57
57

© NXP B.V. 2021. All rights reserved.

78 of 80

QN908xNXP Semiconductors

Bluetooth Low Energy microcontroller with 32-bit ARM Cortex-M4

13.2
14
14.1
14.2
14.3
14.4
14.5
14.5.1
15
15.1
15.2
15.3
15.4
15.5
16
17
18
19
20
20.1
20.2
20.3
21
22
23

Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Analog characteristics . . . . . . . . . . . . . . . . . . 59
BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Temperature sensor . . . . . . . . . . . . . . . . . . . . 61
DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Analog comparator . . . . . . . . . . . . . . . . . . . . . 61
Capacitive sense . . . . . . . . . . . . . . . . . . . . . . 62
Application information. . . . . . . . . . . . . . . . . . 63
Schematic for QN9080 with DC-to-DC converter .
63
Schematic for QN9080 without DC-to-DC
converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Schematic for QN9083 with DC-to-DC converter .
65
Schematic for QN9083 without DC-to-DC
converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
QN908x external component list . . . . . . . . . . 67
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 68
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73
Legal information. . . . . . . . . . . . . . . . . . . . . . . 74
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

QN908x

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1.3 — 6 January 2021

© NXP B.V. 2021. All rights reserved.

79 of 80

How To Reach Us
Home Page:
nxp.com
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Limited warranty and liability — Information in this document is believed to be accurate and reliable. However,NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy orcompleteness of such information and shall have no liability for the consequences of use of such information. NXP
Semiconductors takes no responsibility for the content in this document if provided by an information source outsideof NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special
or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related
to the removal or replacement of any products or rework charges) whether or not such damages are based on tort(including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate
and cumulative liability towards customer for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of NXP Semiconductors.
Right to make changes - NXP Semiconductors reserves the right to make changes to information published in thisdocument, including without limitation specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the publication hereof.
Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities.
Customer is responsible for the design and operation of its applications and products throughout their lifecycles toreduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also
extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications.
NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow
up appropriately.
Customer shall select products with security features that best meet rules, regulations, and standards of the intended
application and make the ultimate design decisions regarding its products and is solely responsible for compliancewith all legal, regulatory, and security related requirements concerning its products, regardless of any information or
support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of
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Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use
in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of
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Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested inaccordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion
and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive
specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b) whenever customer uses the product for
automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk,and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting
from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard
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Applications — Applications that are described herein for any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors
products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product

Table continues on the next page...

design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit
for the customer’s applications and products planned, as well as for the planned application and use of customer’s
third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on
any weakness or default in the customer’s applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using
NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of
IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operationof the device at these or any other conditions above those given in the Recommended operating conditions section (ifpresent) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting
values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commerical sale — NXP Semiconductors products are sold subject to the general terms
and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in avalid written individual agreement. In case an individual agreement is concluded only the terms and conditions of therespective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s generalterms and conditions with regard to the purchase of NXP Semiconductors products by customer.
Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V
may appear when operating this product, depending on settings and application. Customers incorporating or otherwise
using these products in applications where such high voltages may appear during operation, assembly, test etc. of suchapplication, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting
from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60
950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages.
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NXP B.V. All other product or service names are the property of their respective owners. AMBA, Arm, Arm7,
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subsidiaries) in the US and/or elsewhere. The related technology may be protected by any or all of patents, copyrights,
designs and trade secrets. All rights reserved.

© NXP B.V. 2017-2021.

All rights reserved.

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Date of release: 01/2021
Document identifier: QN908x