PSoC™ 6 MCU: CY8C63x6, CY8C63x7 Datasheet

PSoC™ 63 MCU with Bluetoot h® LE
General description
PSoC™ 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT
applications. The PSoC™ 63 with Bluetooth® LE product line, based on the PSoC™ 6 MCU platform, is acombination of a high-performance microcontroller with low-power flash technology, digital programmable
logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.
The PSoC™ 63 product line provides wireless connectivity with Bluetooth® LE 5.0 compliance.

Features• 32-bit Dual CPU subsystem- 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit
(MPU)
- 100-MHz Cortex®-M0+ (CM0+) CPU with single-cycle multiply and MPU- User-selectable core logic operation at either 1.1 V or 0.9 V- Active CPU current slope with 1.1-V core operation• Cortex®-M4: 40 µA/MHz• Cortex®-M0+: 20 µA/MHz- Active CPU current slope with 0.9-V core operation• Cortex®-M4: 22 µA/MHz• Cortex®-M0+: 15 µA/MHz- Two DMA controllers with 16 channels each
• Memory subsystem• 1-MB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write(RWW) support. Two 8-KB flash caches, one for each CPU.
• 288-KB SRAM with power and data retention control• One-time-programmable (OTP) 1-Kb eFuse array• Bluetooth® Low Energy subsystem- 2.4-GHz RF transceiver with 50- antenna drive- Digital PHY- Link Layer engine supporting master and slave modes- Programmable TX power: up to 4 dBm- RX sensitivity: –95 dBm- RSSI: 4-dB resolution- 5.7-mA Tx (0 dBm) and 6.7 mA RX (2 Mbps) current with 3.3-V supply and internal SIMO Buck converter- Link Layer engine supports four connections simultaneously- Supports 2 Mbps data rate
• Low-power 1.7-V to 3.6-V operation- Six power modes for fine-grained power management- Deep Sleep mode current of 7 µA with 64-KB SRAM retention- On-chip Single-In Multiple Out (SIMO) DC-DC buck converter, <1 µA quiescent current- Backup domain with 64 bytes of memory and real-time clock• Flexible clocking options- 8-MHz Internal Main Oscillator (IMO) with ±2% accuracy- Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO)- On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
Datasheetwww.infineon.com

Please read the Important Notice and Warnings at the end of this document
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Features- Phase-locked loop (PLL) for multiplying clock frequencies- Frequency-locked loop (FLL) for multiplying IMO frequency- Integer and fractional peripheral clock dividers• Quad SPI (QSPI)/Serial Memory Interface (SMIF)- Execute-In-Place (XIP) from external quad SPI Flash- On-the-fly encryption and decryption- 4-KB cache for greater XIP performance with lower power- Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps
• Segment LCD Drive- Supports up to 83 segments and up to 8 commons• Serial communication- Nine run-time configurable serial communication blocks (SCBs)• Eight SCBs: configurable as SPI, I2C, or UART
• One Deep Sleep SCB: configurable as SPI or I2C- USB full-speed device interface• Audio subsystem- Two pulse density modulation (PDM) channels and one I2S channel with time division multiplexed (TDM) mode
• Timing and pulse-width modulation- Thirty-two timer/counter/pulse-width modulators (TCPWM)- Center-aligned, edge, and pseudo-random modes- Comparator-based triggering of Kill signals• Programmable analog- 12-bit 1-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging- Two low-power comparators available in Deep Sleep and Hibernate modes- Built-in temperature sensor connected to ADC- One 12-bit voltage-mode digital-to-analog converter (DAC) with < 2-µs settling time
- Two opamps with low-power operation modes• Up to 84 programmable GPIOs- Two Smart I/O™ ports (16 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep- Programmable drive modes, strengths, and slew rates- Six overvoltage-tolerant (OVT) pins
• Capacitive sensing- CAPSENSE™ provides best-in-class signal-to-noise ratio (SNR), liquid tolerance, and proximity sensing- Enables dynamic usage of both self and mutual sensing- Automatic hardware tuning (SmartSense)• security Built into Platform Architecture- ROM-based root of trust via uninterruptible “Secure Boot”- Step-wise authentication of execution images- Secured execution of code in execute-only mode for protected routines- All Debug and Test ingress paths can be disabled- Up to eight Protection Contexts• Cryptography accelerator- Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions- True random number generation (TRNG) function

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Features• Programmable digital- Twelve programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital
blocks or UDBs)- Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog-programmable blocks- Infineon-provided peripheral component library using UDBs to implement functions such as communication
peripherals (for example, LIN, UART, SPI, I2C, S/PDIF and other protocols), Waveform Generators, Pseudo-Random Sequence (PRS) generation, and many other functions.
• Profiler- Eight counters provide event or duration monitoring of on-chip resources• Packages- 124-BGA and 104-M-CSP; with USB- 116-BGA, 104-M-CSP, and 68-QFN; no USB• Device Identification and Revisions- Product line ID (12-bit): 0x100- Major/Minor Die Revision ID: 2/4- Firmware Revisions: Rom Boot: 4.1, Flash Boot: 1.20.1.45 (see Boot Code section)- This product line has a JTAG ID which is available through the SWJ interface. It is a 32-bit ID, where:- The most significant digit is the device revision, based on the Major Die Revision- The next four digits correspond to the part number, for example "E4B0" as a hexadecimal number- The three least significant digits are the manufacturer ID, in this case "069" as a hexadecimal number- The Silicon ID system call can be used by firmware to get Silicon ID and ROM Boot data. For more information,
see the technical reference manual (TRM).
- The Flash Boot version can be read directly from a designated address 0x1600 2004. For more information,
see the technical reference manual (TRM).

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Table of contents

Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents ...............................................................................................................................4
1 Development ecosystem .................................................................................................................6
1.1 PSoC™ 6 MCU resources .........................................................................................................................................6
1.2 ModusToolbox™ Software ......................................................................................................................................7
1.3 PSoC™ Creator ........................................................................................................................................................8
2 Blocks and functionality ..................................................................................................................9
3 Functional description ..................................................................................................................11
3.1 CPU and Memory Subsystem ...............................................................................................................................123.1.1 CPUs....................................................................................................................................................................123.1.2 Interrupts............................................................................................................................................................123.1.3 InterProcessor Communication (IPC) ...............................................................................................................13
3.1.4 DMA controllers..................................................................................................................................................13
3.1.5 Cryptography accelerator (Crypto)...................................................................................................................13
3.1.6 Protection units .................................................................................................................................................14
3.1.7 Memory...............................................................................................................................................................14
3.1.8 Boot Code...........................................................................................................................................................14
3.1.9 Memory Map.......................................................................................................................................................16
3.2 System resources..................................................................................................................................................173.2.1 Power system .....................................................................................................................................................173.2.2 Power modes .....................................................................................................................................................173.2.3 Clock system ......................................................................................................................................................17
3.2.4 Internal Main Oscillator (IMO) ...........................................................................................................................18
3.2.5 Internal Low-speed Oscillator (ILO) ..................................................................................................................18
3.2.6 External Crystal Oscillators ...............................................................................................................................19
3.2.7 Watchdog timers (WDT, MCWDT) ......................................................................................................................19
3.2.8 Clock dividers.....................................................................................................................................................19
3.2.9 Trigger routing ...................................................................................................................................................20
3.2.10 Reset .................................................................................................................................................................20
3.3 Bluetooth® LE Radio and Subsystem ...................................................................................................................20
3.4 Programmable analog subsystem .......................................................................................................................22
3.4.1 12-bit SAR ADC ...................................................................................................................................................22
3.4.2 Temperature sensor ..........................................................................................................................................22
3.4.3 12-bit digital-analog converter .........................................................................................................................22
3.4.4 Continuous Time Block mini (CTBm) with two opamps..................................................................................22
3.4.5 Low-power comparators ...................................................................................................................................22
3.5 Programmable digital...........................................................................................................................................24
3.5.1 Smart I/O ............................................................................................................................................................24
3.5.2 Universal digital blocks (UDBs) .........................................................................................................................24
3.6 Fixed-function digital............................................................................................................................................25
3.6.1 Timer/counter/pulse-width modulator (TCPWM) block..................................................................................25
3.6.2 Serial communication blocks (SCB)..................................................................................................................25
3.6.3 USB Full-Speed device interface .......................................................................................................................26
3.6.4 QSPI Interface Serial Memory Interface (SMIF) ................................................................................................26
3.6.5 LCD......................................................................................................................................................................26
3.7 GPIO .......................................................................................................................................................................27
3.8 Special-function peripherals................................................................................................................................28
3.8.1 Audio subsystem................................................................................................................................................28
3.8.2 CAPSENSE™ Subsystem.....................................................................................................................................28
4 Pinouts ........................................................................................................................................32
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Table of contents
5 Power Supply Considerations ........................................................................................................47
6 Electrical specifications.................................................................................................................53
6.1 Absolute maximum ratings ..................................................................................................................................53
6.2 Device-level specifications ...................................................................................................................................53
6.2.1 Power supplies...................................................................................................................................................54
6.2.2 CPU current and transition times .....................................................................................................................55
6.2.3 XRES....................................................................................................................................................................61
6.2.4 GPIO....................................................................................................................................................................61
6.3 Analog peripherals................................................................................................................................................63
6.3.1 Opamp................................................................................................................................................................63
6.3.2 Low-Power (LP) Comparator.............................................................................................................................67
6.3.3 SAR ADC ..............................................................................................................................................................68
6.3.4 DAC .....................................................................................................................................................................70
6.3.5 CSD .....................................................................................................................................................................70
6.4 Digital peripherals.................................................................................................................................................75
6.4.1 LCD Specifications ............................................................................................................................................77
6.5 Memory..................................................................................................................................................................78
6.5.1 Flash ...................................................................................................................................................................78
6.6 System resources..................................................................................................................................................79
6.6.1 Power-on-reset ..................................................................................................................................................79
6.6.2 Voltage monitors................................................................................................................................................79
6.6.3 SWD and Trace interface ...................................................................................................................................80
6.6.4 Internal Main Oscillator .....................................................................................................................................80
6.6.5 Internal Low-Speed Oscillator .........................................................................................................................80
6.6.6 Crystal oscillator ...............................................................................................................................................81
6.6.7 External clock ....................................................................................................................................................81
6.6.8 PLL ......................................................................................................................................................................81
6.6.9 Clock source switching time..............................................................................................................................82
6.6.10 FLL ....................................................................................................................................................................82
6.6.11 UDB ...................................................................................................................................................................82
6.6.12 USB ...................................................................................................................................................................84
6.6.13 QSPI ..................................................................................................................................................................84
6.6.14 Audio Subsystem .............................................................................................................................................85
6.6.15 Smart I/O ..........................................................................................................................................................87
6.6.16 Precision ILO (PILO) .........................................................................................................................................87
6.6.17 JTAG Boundary Scan .......................................................................................................................................87
6.7 Bluetooth® LE ........................................................................................................................................................88
7 Ordering information ....................................................................................................................94
7.1 PSoC™ 6 MPN decoder..........................................................................................................................................95
8 Packaging ....................................................................................................................................96
9 Acronyms ................................................................................................................................... 101
10 Document conventions.............................................................................................................. 105
10.1 Unit of measure.................................................................................................................................................105
Revision history ............................................................................................................................ 106

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Development ecosystem

1

Development ecosystem

1.1

PSoC™ 6 MCU resources

Infineon provides a wealth of data at www.infineon.com to help you select the right PSoC™ device and quickly
and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 6 MCU:
• Overview: PSoC™ Portfolio, PSoC™ Roadmap• Product Selectors: PSoC™ 6 MCU• Application notes cover a broad range of topics, from basic to advanced level, and include the following:- AN221774: Getting Started with PSoC™ 6 MCU- AN210781: Getting Started with PSoC™ 6 MCU with Bluetooth® Low Energy Connectivity- AN218241: PSoC™ 6 MCU Hardware Design Guide- AN213924: PSoC™ 6 MCU Device Firmware Update Guide- AN215656: PSoC™ 6 MCU Dual-CPU System Design- AN219528: PSoC™ 6 MCU Power Reduction Techniques- AN221111: PSoC™ 6 MCU Creating a Secured System- AN85951: PSoC™ 4, PSoC™ 6 MCU CAPSENSE™ Design Guide• Code examples demonstrate product features and usage, and are also available on Infineon GitHub
repositories.
• Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC™ 6 MCU architecture and registers.
• PSoC™ 6 MCU Programming Specification provides the information necessary to program PSoC™ 6 MCU
nonvolatile memory.
• Development Tools- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries.
- CY8CKIT-062-BLE - PSoC™ 6-Bluetooth® LE Pioneer Kit: a hardware platform that enables design and debugof the PSoC 63-BLE product line.
- CY8CPROTO-063-BLE - PSoC™ 6-Bluetooth® LE Prototyping Kit: a low-cost PSoC™ 63-Bluetooth® LE kit witha snap-away form factor.
- PSoC™ 6 CAD libraries provide footprint and schematic support for common tools. BSDL files and IBIS
models are also available.
• Training Videos are available on a wide range of topics including the PSoC™ 6 MCU 101 series.
• Infineon Developer Community enables connection with fellow PSoC developers around the world, 24 hours
a day, 7 days a week, and hosts a dedicated PSoC™ 6 MCU Community.

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Development ecosystem

1.2

ModusToolbox™ Software

ModusToolbox™ Software is Infineon’s comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub. This includes:• Board Support Packages (BSPs) aligned with Infineon kits
• Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL)• Middleware enabling industry-leading features such as CAPSENSE™, Bluetooth® Low Energy, and meshnetworks• An extensive set of thoroughly tested code example applications
Note: The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Infineon
MCUs. It is a generic interface that can be used across multiple product families. For example, it wraps the
PSoC™ 6 PDL with a simplified API, but the PDL exposes all low-level peripheral functionality. You can leverage
the HAL's simpler and more generic interface for most of an application, even if one portion requires finer-grained
control.
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as theoptional Eclipse IDE for ModusToolbox, as Figure 1 shows. For information on using Infineon tools, refer to the
documentation delivered with ModusToolbox software, and AN228571: Getting Started with PSoC™ 6 MCU on
ModusToolbox.

Figure 1

Datasheet

ModusToolbox™ Software Tools

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Development ecosystem

1.3

PSoC™ Creator

Note: PSoC™ Creator is not recommended for new designs.
PSoC™ Creator is a free Windows-based Integrated Design Environment (IDE). It enables you to design hardwareand firmware systems concurrently, based on the PSoC™ 6 MCU. Figure 2 shows that with PSoC™ Creator, youcan:
1. Explore the library of 200+ Components in PSoC™ Creator
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component Configuration Tools and the Component datasheets
4. Co-design your application firmware and hardware in the PSoC™ Creator IDE or build project for third-party IDE
5. Prototype your solution with the PSoC™ 6 Pioneer Kits. If a design change is needed, PSoC™ Creator andComponents enable you to make changes on-the-fly without the need for hardware revisions.

Figure 2

Datasheet

PSoC™ Creator Schematic Entry and Components

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Blocks and functionality

2

Blocks and functionality

BOD

Buck Regulator

SystemHibernate Mode

ECO

FLL

2 x PLL

2 x MCWDTPILOXRES Reset
Backup Regs

Backup
Domain

IMO

ILO

WDT

RTC

WCO

Cortex M4 F CPU
150/ 50 MHz ,1.1/ 0. 9V
SWJ , ETM ,ITM ,CTI

System Int erconnect (Multi Layer AHB, IPC, MPU/SMPU)

Crypto
DES/ TDES, AES, SHA ,CRC, TRNG, RSA/ ECC
Accelerator

Flash1024 KB + 32KB + 32KB
8 KB cache for each CPU

32 x TCPWM
SCB
8 x I2 C , SPI,UART, or LIN
I2 C or SPI
Bluetooth® LE
PSoC 6-BLE
Programmable
Link Layer

2 MbpsRadio

Audio Subsystem
I2 S
PDM- PCM
ProfilereFuse: 1024 bits

USB- FSROM
128KB

Datasheet

Programmable Digital:12 x UDB

QSPI ( SMIF)
with OTF Encryption/ Decryption

SRAM
288KB

Figure 3

CAPSENSE™

LP Comparator

CPU Subsystem

2 x DMA
Controller

Temperature Sensor

LCD

PMIC Control

Cortex M 0 + CPU
100/ 25 MHz,1.1/0. 9 V
SWJ , MTB ,CTI

2 x Opamp

I/O Subsystem : Up to 84 GPIOs (including 6 OVT), 124-BGA P ackage
B oundary Scan

LVD

POR

DAC 12-bit

DSI

OVP

ClocksSARMUX

System Resources
Power

SystemDeepSleep Mode

Programmable Analog
SAR ADC12- bitP eri pheral cl ock (clk_ peri)

System LP/ULP Mode
CPUs Active/Sleep

PSoC™63 MCU with Bluetooth® LE
CY8C63x6 , CY8C63 x7

P eri pheral Int erconnect (MMIO, PPU)

Color Key:Power Modes andDomains

2x Smart I/O Ports

Figure 3 shows the major subsystems and a simplified view of their interconnections. The color coding shows
the lowest power mode where a block is still functional. For example, the SRAM is functional down to Deep Sleep
mode.

USB
PHY

Block diagram

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Blocks and functionality
There are three debug access ports, one each for CM4 and CM0+, and a system port. PSoC™ 6 MCU devices include
extensive support for programming, testing, debugging, and tracing both hardware and firmware. All device
interfaces can be permanently disabled for applications concerned about a reprogrammed device or starting andinterrupting flash programming sequences. All programming, debug, and test interfaces can be disabled.
Complete debug-on-chip functionality enables full device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only thestandard programming connections are required to fully support debug.
The Eclipse IDE for ModusToolbox™ software and PSoC™ Creator[1] Integrated Development Environment (IDE)
provide fully integrated programming and debug support for these devices. The SWJ (SWD and JTAG) interface
is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very
robust flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip
programmable blocks, PSoC™ 6 provides multiple levels of device security.

Note
1. PSoC™ Creator is not recommended for new designs.
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Functional description

3

Functional description

The following sections provide an overview of the features, capabilities and operation of each functional block
identified in the block diagram in Figure 3. For more detailed information, refer to the following documentation:• Board Support Package (BSP) Documentation
BSPs are available on GitHub. They are aligned with Infineon kits and provide files for basic device functionality such as hardware configuration files, startup code, and linker files. The BSP also includes other libraries
that are required to support a kit. Each BSP has its own documentation, but typically includes an API referencesuch as the example here. This search link finds all currently available BSPs on the Infineon GitHub site.
• Hardware Abstraction Layer API Reference Manual
The Hardware Abstraction Layer (HAL) provides a high-level interface to configure and use hardware blocks
on Infineon MCUs. It is a generic interface that can be used across multiple product families. You can leverage
the HAL's simpler and more generic interface for most of an application, even if one portion requires finer-grained control. The HAL API Reference provides complete details. Example applications that use the HAL
download it automatically from the GitHub repository.
• Peripheral Driver Library (PDL) Application Programming Interface (API) Reference Manual
The Peripheral Driver Library (PDL) integrates device header files and peripheral drivers into a single package
and supports all PSoC™ 6 MCU product lines. The drivers abstract the hardware functions into a set ofeasy-to-use APIs. These are fully documented in the PDL API Reference. Example applications that use the
PSoC™ 6 PDL download it automatically from the GitHub repository.
• Architecture Technical Reference Manual (TRM)
The architecture TRM provides a detailed description of each resource in the device. This is the next reference
to use if it is necessary to understand the operation of the hardware below the software provided by PDL. It
describes the architecture and functionality of each resource and explains the operation of each resource inall modes. It provides specific guidance regarding the use of associated registers.
• Register Technical Reference Manual
The register TRM provides a complete list of all registers in the device. It includes the breakdown of all register
fields, their possible settings, read/write accessibility, and default states. All registers that have a reasonable
use in typical applications have functions to access them from within PDL. Note that ModusToolbox and PDL
may provide software default conditions for some registers that are different from and override the hardware
defaults.

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Functional description

3.1

CPU and Memory Subsystem

PSoC™ 6 has multiple bus masters, as Figure 3 shows. They are: CPUs, DMA controllers, QSPI, USB, and a Crypto
block. Generally, all memory and peripherals can be accessed and shared by all bus masters through multi-layer
Arm AMBA high-performance bus (AHB) arbitration. Accesses between CPUs can be synchronized using aninter-processor communication (IPC) block.

3.1.1

CPUs

There are two Arm® Cortex® CPUs:
The Cortex®-M4 (CM4) has single-cycle multiply, a floating-point unit (FPU), and a memory protection unit (MPU).
It can run at up to 150 MHz. This is the main CPU, designed for a short interrupt response time, high code density,and high throughput.
CM4 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the Armv7-M
Architecture Reference Manual).
The Cortex®-M0+ (CM0+) has single-cycle multiply, and an MPU. It can run at up to 100 MHz; however, for CM4
speeds above 100 MHz, CM0+ and bus peripherals are limited to half the speed of CM4. Thus, for CM4 running at
150 MHz, CM0+ and peripherals are limited to 75 MHz in system low power (LP) mode. In system ultra-low power(ULP) mode, CPU speeds are limited to 50 MHz and 25 MHz respectively.
CM0+ is the secondary CPU; it is used to implement system calls and device-level safety and protection features.
CM0+ provides a secured, uninterruptible boot function. This helps ensure that post boot, system integrity ischecked and memory and peripheral access privileges are enforced.
CM0+ implements the Armv6-M Thumb instruction set (defined in the Armv6-M Architecture Reference Manual).
The CPUs have the following power draw, at VDDD = 3.3 V and using the internal buck regulator:
Table 1

Active Current Slope at VDDD = 3.3 V Using the Internal Buck Regulator
System Power Mode

CPU

ULP

LP

Cortex-M0+

15 A/MHz

20 A/MHz

Cortex-M4

22 A/MHz

40 A/MHzThe CPUs can be selectively placed in their Sleep and Deep Sleep power modes as defined by Arm.
Both CPUs have nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response, andwakeup interrupt controllers (WIC) for CPU wakeup from Deep Sleep power mode.
The CPUs have extensive debug support. PSoC™ 6 has a debug access port (DAP) that acts as the interface fordevice programming and debug. An external programmer or debugger (the “host”) communicates with the DAP
through the device serial wire debug (SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP(and subject to restrictions), the host can access the device memory and peripherals as well as the registers inboth CPUs.
Each CPU offers debug and trace features as follows:• CM4 supports six hardware breakpoints and four watchpoints, 4-bit embedded trace macrocell (ETM), serial
wire viewer (SWV), and printf()-style debugging through the single wire output (SWO) pin.
• CM0+ supports four hardware breakpoints and two watchpoints, and a micro trace buffer (MTB) with 4-KB
dedicated RAM.
PSoC™ 6 also has an Embedded Cross Trigger for synchronized debugging and tracing of both CPUs.

3.1.2

Interrupts

This product line has 147 system and peripheral interrupt sources and supports interrupts and system exceptions
on both CPUs. CM4 has 147 interrupt request lines (IRQ), with the interrupt source ‘n’ directly connected to IRQn.
CM0+ has 32 interrupts IRQ[31:0] with configurable mapping of one system interrupt source to any of theIRQ[31:0].
Each interrupt supports configurable priority levels (eight levels for CM4 and four levels for CM0+). One systeminterrupt can be mapped to each of the CPUs' non-maskable interrupts (NMI). Up to 41 interrupt sources arecapable of waking the device from Deep Sleep power mode using the WIC. Refer to the technical reference
manual for details.
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Functional description

3.1.3

InterProcessor Communication (IPC)

In addition to the Arm SEV and WFE instructions, a hardware InterProcessor Communication (IPC) block is
included. It includes 16 IPC channels and 16 IPC interrupt structures. The IPC channels can be used to implement
data communication between the processors. Each IPC channel also implements a locking scheme which can beused to manage shared resources. The IPC interrupts let one processor interrupt the other, signaling an event.
This is used to trigger events such as notify and release of the corresponding IPC channels. Some IPC channels
and other resources are reserved, as Table 2 shows:
Table 2Distribution of IPC channels and other resources
Resources Available
IPC channels,
16 available
IPC interrupts,
16 available
Other interrupts
CM0+ NMI
Other resources:
clock dividers, DMA channels, etc.

3.1.4

Resources Consumed
8 reserved
8 reserved
1 reserved
Reserved
1 CM0+ interrupt mux

DMA controllers

There are two DMA controllers with 16 channels each, which support CPU-independent accesses to memory andperipherals. The descriptors for DMA channels can be in SRAM or flash. Therefore, the number of descriptors arelimited only by the size of the memory. Each descriptor can transfer data in two nested loops with configurable
address increments to the source and destination. The size of data transfer per descriptor varies based on thetype of DMA channel. Refer to the technical reference manual for detail.

3.1.5

Cryptography accelerator (Crypto)This subsystem consists of hardware implementation and acceleration of cryptographic functions and random
number generators.
The Crypto subsystem supports the following:• Encryption/Decryption Functions- Data Encryption Standard (DES)- Triple DES (3DES)- Advanced Encryption Standard (AES) (128-, 192-, 256-bit)- Elliptic Curve Cryptography (ECC)- RSA cryptography functions• Hashing functions- Secure Hash Algorithm (SHA)- SHA-1- SHA-224/-256/-384/-512• Message authentication functions (MAC)- Hashed message authentication code (HMAC)- Cipher-based message authentication code (CMAC)• 32-bit cyclic redundancy; code (CRC) generator• Random number generators- Pseudo random number generator (PRNG)- True random number generator (TRNG)

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Functional description

3.1.6

Protection units

This product line has multiple types of protection units to control erroneous or unauthorized access to memory
and peripheral registers. CM4 and CM0+ have Arm MPUs for protection at the bus master level. Other bus masters
use additional MPUs. Shared memory protection units (SMPUs) help implement memory protection for memory
resources that are shared among multiple bus masters. Peripheral protection units (PPU) are similar to SMPUs
but are designed for protecting the peripheral register space.
Protection units support memory and peripheral access attributes including address range, read/write,code/data, privilege level, secured/non-secured, and protection context. Some protection unit resources arereserved for system usage; see the technical reference manual (TRM) for details.

3.1.7

MemoryPSoC™ 6 contains flash, SRAM, ROM, and eFuse memory blocks.
• FlashThere is up to 1 MB of application flash, organized in 256-KB sectors. There are also two 32-KB flash sectors:- Auxiliary flash (AUXflash), typically used for EEPROM emulation- Supervisory flash (SFlash). Data stored in SFlash includes device trim values, Flash Boot code, and encryption
keys. After the device transitions into the “Secure” lifecycle stage, SFlash can no longer be changed.
The flash has 128-bit-wide accesses to reduce power. Write operations can be performed at the row level. A
row is 512 bytes. Read operations are supported in both Low Power and Ultra-Low Power modes, however
write operations may not be performed in Ultra-Low Power mode.
The flash controller has two caches, one for each CPU. Each cache is 8 KB, with 4-way set associativity.
• SRAM
Up to 288 KB of SRAM is provided. Power control and retention granularity is implemented in 32-KB blocks
allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode.
• ROM
The 128-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system
functions. The ROM contains device initialization, flash write, security, eFuse programming, and other system-level routines. ROM code is executed only by the CM0+ CPU, in protection context 0. A system function canbe initiated by either CPU, or through the DAP. This causes an NMI in CM0+, which causes CM0+ to execute thesystem function.
• eFuseA one-time-programmable (OTP) eFuse array consists of 1024 bits, of which 512 are reserved for system use
such as die ID, device ID, initial trim settings, device life cycle, and security settings. The remaining bits areavailable for storing key information, hash values, unique IDs or similar custom content.
Each fuse is individually programmed; once programmed (or “blown”), its state cannot be changed. Blowing
a fuse transitions it from the default state of 0 to 1. To program an eFuse, VDDIO0 must be at 2.5 V ±5%, at 14 mA.
Because blowing an eFuse is an irreversible process, programming is recommended only in mass production
under controlled factory conditions. For more information, see
PSoC™ 6 MCU Programming Specifications.

3.1.8

Boot CodeTwo blocks of code, ROM Boot and Flash Boot, are pre-programmed into the device and work together toprovide device startup and configuration, basic security features, life-cycle stage management and other system
functions.
• ROM Boot
On a device reset, the boot code in ROM is the first code to execute. This code performs the following:- Integrity checks of flash boot code
- Device trim setting (calibration)
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PSoC™ 63 MCU with Bluetooth® LE
Functional description- Setting the device protection units- Setting device access restrictions for life-cycle states
ROM cannot be changed and acts as the Root of Trust in a secured system.
• Flash Boot
Flash boot is a firmware module stored in SFlash and application flash. It ensures that only a validated application may run on the device. It also ensures that the firmware image has not been modified, such as by amalicious third party.
Flash boot:- Is validated by ROM Boot
- Runs after ROM Boot and before the user application- Enables system calls- Configures the Debug Access Port
- Launches the user application
If the user application cannot be validated, then flash boot ensures that the device is transitioned into a safe
state.

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Functional description

3.1.9

Memory Map

Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address
space is divided into the regions shown in Table 3. Note that code can be executed from the Code and External
RAM.
Table 3

Address Map for CM4 and CM0+
Address Range

Name

Use

0x0000 0000 – 0x1FFF FFFF

Code

Program code region. Data can also be placed here. It
includes the exception vector table, which starts ataddress 0.

0x2000 0000 – 0x3FFF FFFF

SRAM

Data region. This region is not supported in PSoC™ 6.

0x4000 0000 – 0x5FFF FFFF

Peripheral

All peripheral registers. Code cannot be executed fromthis region. CM4 bit-band in this region is not supported
in PSoC™ 6.

0x6000 0000 – 0x9FFF FFFF

External
RAM

0xA000 0000 – 0xDFFF FFFF

External
DeviceNot used.

0xE000 0000 – 0xE00F FFFF

PrivatePeripheral
Bus

Provides access to peripheral registers within the CPU
core.

0xE010 0A000 – 0xFFFF FFFF

DeviceSMIF or Quad SPI, (see the QSPI Interface
Serial Memory Interface (SMIF) section).

Code can be executed from this region.

Device-specific system registers.

The device memory map shown in Table 4 applies to both CPUs. That is, the CPUs share access to all PSoC™ 6
MCU memory and peripheral registers.
Table 4

Internal Memory Address Map for CM4 and CM0+
Address Range
0x0000 0000 – 0x0001 FFFF
0x0800 0000 – 0x0804 7FFF
0x1000 0000 – 0x100F FFFF
0x1400 0000 – 0x1400 7FFF
0x1600 0000 – 0x1600 7FFF

Memory TypeROM
SRAM
Application flash
Auxiliary flash, can be used for
EEPROM emulation
Supervisory flash

Size
128 KBUp to 288 KB
Up to 1 MB
32 KB
32 KB

Note that the SRAM is located in the Arm® Code region for both CPUs (see Table 3). There is no physical memory
located in the CPUs’ Arm SRAM regions.

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3.2

System resources

3.2.1

Power system

The power system provides assurance that voltage levels are as required for each respective mode and will either
delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function
or generate resets (brown-out detect (BOD)) when the power supply drops below specified levels. The design
guarantees safe chip operation between power supply voltage dropping below specified levels (for example,
below 1.7 V) and the reset occurring. There are no voltage sequencing requirements.
The VDDD supply (1.7 to 3.6 V) powers an on-chip buck regulator or a low-dropout regulator (LDO), selectable by
the user. In addition, both the buck and the LDO offer a selectable (0.9 or 1.1 V) core operating voltage (VCCD). The
selection lets users choose between two system power modes:• System Low Power (LP) operates VCCD at 1.1 V and offers high performance, with no restrictions on device
configuration.
• System Ultra Low Power (ULP) operates VCCD at 0.9 V for exceptional low power, but imposes limitations onclock speeds.
In addition, a backup domain adds an “always on” functionality using a separate power domain supplied by a
backup supply (VBACKUP) such as a battery or supercapacitor. It includes a real-time clock (RTC) with alarmfeature, supported by a 32.768-kHz watch crystal oscillator (WCO), and power-management IC (PMIC) control.
Refer to Power Supply Considerations for more details.

3.2.2

Power modes

PSoC™ 6 MCU can operate in four system and three CPU power modes. These modes are intended to minimize
the average power consumption in an application. For more details on power modes and other power-saving
configuration options, see the application note, AN219528: PSoC™ 6 MCU low-power modes and power
reduction techniques and the Architecture TRM, Power Modes chapter.
Power modes supported by PSoC™ 6 MCUs, in the order of decreasing power consumption, are:• System Low Power (LP) – All peripherals and CPU power modes are available at maximum speed• System Ultra Low Power (ULP) – All peripherals and CPU power modes are available, but with limited speed• CPU Active – CPU is executing code in system LP or ULP mode
• CPU Sleep – CPU code execution is halted in system LP or ULP mode
• CPU Deep Sleep – CPU code execution is halted and system Deep Sleep is requested in system LP or ULP mode
• System Deep Sleep – Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode
• System Hibernate – Device and I/O states are frozen and the device resets on wakeup
CPU Active, Sleep, and Deep Sleep are standard Arm-defined power modes supported by the Arm® CPU
instruction set architecture (ISA). System LP, ULP, Deep Sleep and Hibernate modes are additional low-power
modes supported by PSoC™ 6 MCU.

3.2.3

Clock system

Figure 4 shows that the clock system consists of the following:• Internal main oscillator (IMO)• Internal low-speed oscillator (ILO)• Precision ILO (PILO)• Watch crystal oscillator (WCO)• External MHz crystal oscillators (ECOs) for the system and the Bluetooth® LE subsystem• External clock input
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PSoC™ 63 MCU with Bluetooth® LE
Functional description• Phase-locked loop (PLL)• Frequency-locked loop (FLL)
Clocks may be buffered and brought out to a pin on a smart I/O port.
The default clocking when the application starts is CLK_HF[0] being driven by the IMO and the FLL. CLK_HF[0],clk_fast, clk_peri, and clk_slow are all either 50 MHz (LP mode) or 25 MHz (ULP mode). All other clocks, including
all peripheral clocks, are off.

3.2.4

Internal Main Oscillator (IMO)The IMO is the primary source of internal clocking. It is trimmed during testing to achieve the specified accuracy.
The IMO default frequency is 8 MHz and tolerance is ±2%.

3.2.5Internal Low-speed Oscillator (ILO)The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can becalibrated against a higher accuracy clock for better accuracy.
Precision ILO (PILO)PILO is a 32.768-kHz clock that can provide a more accurate clock than ILO when periodically calibrated using ahigh-accuracy clock such as the ECO.
Yellow multiplexers
are glitch safe

Path Mux(FLL/PLL)

Root mux
Divider

FLL

IMO

Predivider(1/2/4/8)

CM4

CLK_HF[0]dsi_in0

Divider

clk_peri

Peripheral
Clock Dividers

Divider

CM0+

EXTCLK
PLL

Predivider(1/2/4/8)

ECO

CLK_HF[1]Audio

dsi_in1
AHB

CLK_PATH2
ALTHF

Predivider(1/2/4/8)

CLK_HF[2]Predivider(1/2/4/8)

CLK_HF[3]CLK_PATH3

dsi_out <1:0>

CLK_PATH4

Predivider(1/2/4/8)

System LP/ULP Domain
System Deep Sleep /Hibernate Domain

eFuse
USB

dsi_in3

CLK_HF[4]

DMA

MMIO

clk_ext

PPU

TCPWM

SCB
CapSense
UDB
LCD
AnalogSubsystem
Smart I/O

dsi_in4
CryptoILO*WCO*

QSPI/SMIF

dsi_in2

Peripheral
clocks

CLK_LF*Works in Hibernate

PILO

Figure 4

Datasheet

Clocking diagram

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3.2.6

External Crystal Oscillators

Figure 5 shows all of the external crystal oscillator circuits for this product line. The component values shown
are typical; check the ECO Specifications for the crystal values, and the crystal datasheet for the load capacitor
values. The ECO and WCO require balanced external load capacitors. The Bluetooth® LE oscillator does not
require external load capacitors. For more information, see the TRM and AN218241, PSoC™ 6 MCU Hardware
Design Considerations.

MHz XTAL

CL / 2

Figure 5

MHz XTAL for
Bluetooth® LE

32.768 kHz XTALC L/ 2CL / 2XO

XI

WCO_OUT, P0.1

WCO_IN, P0.0

ECO_IN, P12.6

ECO_OUT, P12.7

PSoC™ 6

CL / 2

Oscillator circuits

If the ECO is used, note that its performance is affected by GPIO switching noise. GPIO ports should be used as
Table 5 shows. See also Table 6 for additional restrictions for general analog subsystem use.
Table 5ECO Usage Guidelines

Ports

Max Frequency

Port 11
Ports 12 and 13

60 MHz for SMIF (QSPI)Slow slew rate setting

3.2.7

Drive Strength for VDDD ≤ 2.7
V
DRIVE_SEL 2
No restrictions

Drive Strength for VDDD >2.7 V
DRIVE_SEL 3
No restrictions

Watchdog timers (WDT, MCWDT)PSoC™ 6 MCU has one WDT and two multi-counter WDTs (MCWDTs). The WDT has a 16-bit free-running counter.
Each MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit
counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event.
The WDT is clocked by the ILO. It can do interrupt/wakeup generation in system LP/ULP, Deep Sleep, andHibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can do periodic interrupt/wakeup
generation in system LP/ULP and Deep Sleep power modes.

3.2.8

Clock dividers

Integer and fractional clock dividers are provided for peripheral use and timing purposes. There are:• Eight 8-bit clock dividers• Sixteen 16-bit integer clock dividers• Four 16.5-bit fractional clock dividers• One 24.5-bit fractional clock divider

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3.2.9

Trigger routing

PSoC™ 6 MCU contains a trigger multiplexer block. This is a collection of digital multiplexers and switches thatare used for routing trigger signals between peripheral blocks and between GPIOs and peripheral blocks.
There are two types of trigger routing. Trigger multiplexers have reconfigurability in the source and destination.
There are also hardwired switches called “one-to-one triggers”, which connect a specific source to a destination.
The user can enable or disable the route.

3.2.10Reset

PSoC™ 6 MCU can be reset from a variety of sources:• Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for thedevice to function properly. POR activates automatically at power-up.
• Brown-out detect (BOD) reset to monitor the digital voltage supply VDDD and generate a reset if VDDD falls below
the minimum required logic operating voltage.
• External reset dedicated pin (XRES) to reset the device using an external source. The XRES pin is active low. It
can be connected either to a pull-up resistor to VDDD, or to an active drive circuit, as Figure 6 shows. If a pull-up
resistor is used, select its value to minimize current draw when the pin is pulled low; 4.7 kΩ to 100 kΩ is typical.
1.7 to 3.6 V

PSoC™ 6VDDD

4.7 kΩ typ.
XRES
drive

Figure 6

XRES

XRES connection diagram• Watchdog timer (WDT or MCWDT) to reset the device if firmware fails to service it within a specified timeout
period.
• Software-initiated reset to reset the device on demand using firmware.
• Logic-protection fault can trigger an interrupt or reset the device if unauthorized operating conditions occur;for example, reaching a debug breakpoint while executing privileged code.
• Hibernate wakeup reset to bring the device out of the system Hibernate low-power mode.
Reset events are asynchronous and guarantee reversion to a known state. Some of the reset sources are recorded
in a register, which is retained through reset and allows software to determine the cause of the reset.

3.3

Bluetooth® LE Radio and Subsystem

This product line incorporates a Bluetooth® LE subsystem that contains the Physical Layer (PHY) and Link Layer(LL) engines with an embedded security engine. Infineon also provides extensive driver library and middleware
support for Bluetooth® LE; see ModusToolbox™ Software.
The physical layer consists of the digital PHY and the RF transceiver that transmits and receives Gaussian
frequency shift keying (GFSK) packets at 2 Mbps over a 2.4-GHz ISM band, which is compliant with Bluetooth® LE
Specification 5.0.
The baseband controller is a composite hardware and firmware implementation that supports both master andslave modes. Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical
functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in
hardware (in the LL engine).
The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω
antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from theantenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block

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PSoC™ 63 MCU with Bluetooth® LE
Functional description
performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting
it through the antenna.
Key features, implemented in hardware and firmware, are as follows:• Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute(ATT), and security manager (SM) protocols• API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP• L2CAP connection-oriented channel (Bluetooth® 4.1 feature)• GAP features- Broadcaster, Observer, Peripheral, and Central roles- Security Mode 1: Level 1, 2, 3, and 4; Security Mode 2: Level 1 and 2- User-defined advertising data
- Multiple bond support• GATT features- GATT Client and Server- Supports GATT sub-procedures- 32-bit universally unique identifier (UUID) (Bluetooth® 4.1 feature)• Security Manager (SM)- Pairing methods: Just works, Passkey Entry, and Out of Band
- LE Secure Connection Pairing model- Authenticated man-in-the-middle (MITM) protection and data signing• Link Layer (LL)
- Master and Slave roles- 128-bit AES engine- Low-duty cycle advertising- LE Ping- LL privacy 1.2 (Bluetooth® 4.2 feature)- Data length extension (Bluetooth® 4.2 feature)• Supports all SIG-adopted Bluetooth® LE profiles
Power consumption for Advertisement (1.28s, 31-byte packets, 0 dBm TX output power) and Connection (300 ms,
0-byte packets, 0 dBm TX output power) are 42 µW and 70 µW respectively

Datasheet

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Functional description

3.4

Programmable analog subsystem

3.4.1

12-bit SAR ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion. One of three internal references may be used for the ADC reference
voltage: VDDA, VDDA/2, and an analog reference (AREF). AREF is nominally 1.2 V, trimmed to ±1%; see Table 23. An
external reference may also be used, by driving the VREF pin. When using VDDA/2 or AREF as a reference, an external
bypass capacitor may be connected to the VREF pin to improve performance in noisy conditions. These reference
options allow ratio-metric readings or absolute readings at the accuracy of the reference used. The input rangeof the ADC is the full supply voltage between VSS and VDDA/VDDIOA. The SAR ADC may be configured with a mix ofsingle-ended and differential signals in the same configuration.
The SAR ADC’s sample-and-hold (S/H) aperture is programmable to allow sufficient time for signals with a highimpedance to settle sufficiently, if required. System performance will be 65 dB for true 12-bit precision provided
appropriate references are used and system noise levels permit it.
The SAR is connected to a fixed set of pins through an input multiplexer. The multiplexer cycles through theselected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, theaggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several
channels). The result of each channel is buffered, so that an interrupt may be triggered only when a full scan of
all channels is complete. Also, a pair of range registers can be set to detect and cause an interrupt if an input
exceeds a minimum and/or maximum value. This allows fast detection of out-of-range values without having to
wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values insoftware. The SAR can also be connected, under firmware control, to most other GPIO pins via the Analog
Multiplexer Bus (AMUXBUS). The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 3.6 V.
ADC accuracy is affected by GPIO switching noise. To improve accuracy, implement the GPIO port restrictions
listed in Table 6. In addition, there should be no switching outputs on ports 9 and 10.

3.4.2

Temperature sensor

An on-chip temperature sensor is part of the SAR and may be scanned by the SAR ADC. It consists of a diode, which
is biased by a current source that can be disabled to save power. The temperature sensor may be connected
directly to the SAR ADC as one of the measurement channels. The ADC digitizes the temperature sensor’s output
and a Infineon-supplied software function may be used to convert the reading to temperature which includes
calibration and linearization.

3.4.3

12-bit digital-analog converter

There is a 12-bit voltage mode DAC on the chip, which can settle in less than 2 µs. The DAC may be driven by the
DMA controllers to generate user-defined waveforms. The DAC output from the chip can either be the resistive
ladder output (highly linear near ground) or a buffered output using an opamp in the CTBm block.

3.4.4

Continuous Time Block mini (CTBm) with two opamps

This block consists of two opamps, which have their inputs and outputs connected to pins and other analog
blocks, as Figure 7 shows. They have three power modes (high, medium, and low) and a comparator mode. The
opamps can be used to buffer SAR inputs and DAC outputs. The non-inverting inputs of these opamps can beconnected to either of two pins, thus allowing independent sensors to be used at different times. The pin
selection can be made via firmware. The opamps also support operation in system Deep Sleep mode, with lower
performance and reduced power consumption.

3.4.5

Low-power comparators

Two low-power comparators are provided, which can operate in all power modes. This allows other analog
system resources to be disabled while retaining the ability to monitor external voltage levels during system Deep
Sleep and Hibernate modes. The comparator outputs are normally synchronized to avoid metastability unlessoperating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by acomparator-switch event.
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P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7

P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7

Figure 7 shows an overview of the analog subsystem. This diagram is a high-level abstraction. See theArchitecture TRM for detailed connectivity information.
AMUXBUSAAMUXBUSB
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7

CSD
shield_pad
vref_ext
csh
cmod
amuxbusa
amuxbusb

LPCOMP0
inp
inn
LPCOMP1
inp
inn

P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7

Red dots indicate
AMUXBUS splitter
switches
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P14.0
P14.1

CTDAC

VDDA

vref

The DAC output is alsorouted directly to P9.6;
not shown in thisdiagram.
See the Alternate PortPin Functionality table.

vout
S/H

OA1
P9.3
P9.7
P9.5

10x

+
-

comp out
1x

P9.4
P9.0
P9.6

Bold lines indicate
direct connections
from the opamp 10x
ouputs directly to port
pins.

OA0
10x

+
-

P9.1

comp out
1x

P9.2

SARMUX (2)

P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7

TEMP
temp
VSS

Datasheet

P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7

P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7

AREF, 1.2 V

Figure 7

P0.0
P0.1
P0.2
P0.3
P0.4
P0.5

SAR ADC
vplus
vminusvref
V DDA
V DDA / 2

SARREF

P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7

To VREF pin, for bypass capacitor

Analog subsystem

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3.5

Programmable digital

3.5.1

Smart I/O

Smart I/O is a programmable logic fabric that enables Boolean operations on signals traveling from device
internal resources to the GPIO pins or on signals traveling into the device from external sources. A Smart I/O blocksits between the GPIO pins and the high-speed I/O matrix (HSIOM) and is dedicated to a single port.
There are two Smart I/O blocks: one on Port 8 and one on Port 9. When Smart I/O is not enabled, all signals on
Port 8 and Port 9 bypass the Smart I/O hardware.
Smart I/O supports:• System Deep Sleep operation• Boolean operations without CPU intervention• Asynchronous or synchronous (clocked) operation
Each Smart I/O block contains a data unit (DU) and eight lookup tables (LUTs).
The DU:• Performs unique functions based on a selectable opcode.
• Can source input signals from internal resources, the GPIO port, or a value in the DU register.
Each LUT:• Has three selectable input sources. The input signals may be sourced from another LUT, an internal resource,
an external signal from a GPIO pin, or from the DU.
• Acts as a programmable Boolean logic table.
• Can be synchronous or asynchronous.

3.5.2

Universal digital blocks (UDBs)

This product line has 12 UDBs. Each UDB is a collection of uncommitted logic (PLD) and nano-CPU (datapath)
optimized to create common embedded peripherals and custom functionality, as Figure 8 shows. UDB
datapaths are 8 bits wide, and can be chained to form 16, 24, and 32-bit functions. Included with the UDBs is thedigital system interconnect (DSI), which routes signals among UDBs, fixed function peripherals, I/O pins andother system blocks to implement full featured device connectivity. The DSI enables routing between any digital
function and any pin. Port adapter blocks extend the UDBs to provide an interface to the GPIOs through the
HSIOM.
PLD
Chaining
Clockand Reset
Control

PLD
12C4(8 PTs)

PLD
12C4(8 PTs)Status andControl

Datapath

Datapath
Chaining

Routing Channel

Figure 8

Datasheet

UDB Block Diagram

24

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3.6
3.6.1

Fixed-function digital
Timer/counter/pulse-width modulator (TCPWM) block• The TCPWM supports the following operational modes:- Timer-counter with compare- Timer-counter with capture- Quadrature decoding- Pulse width modulation (PWM)- Pseudo-random PWM- PWM with dead time
• Up, down, and up/down counting modes.
• Clock prescaling (division by 1, 2, 4, ... 64, 128)
• Double buffering of compare/capture and period values• Underflow, overflow, and capture/compare output signals• Supports interrupt on:- Terminal count – Depends on the mode; typically occurs on overflow or underflow- Capture/compare – The count is captured to the capture register or the counter value equals the value in thecompare register• Complementary output for PWMs
• Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge,
both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state.
In this device there are:• Eight 32-bit TCPWMs• Twenty-four 16-bit TCPWMs

3.6.2

Serial communication blocks (SCB)

This product line has nine SCBs:• Eight can implement either I2C, UART, or SPI.
• One SCB (SCB #8) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI
slave or I2C slave.
I2C Mode: The SCB can implement a full multi-master and slave interface (it is capable of multimaster
arbitration). This block can operate at speeds of up to 1 Mbps (Fast Mode Plus). It also supports EZI2C, which
creates a mailbox address range and effectively reduces I2C communication to reading from and writing to anarray in the memory.The SCB supports a 256-byte FIFO for receive and transmit.
The I2C peripheral is compatible with I2C standard-mode, Fast Mode, and Fast Mode Plus devices as defined in
the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in
open-drain modes.
UART Mode: This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals
connected over common Rx and Tx lines. Common UART functions such as parity error, break detect, and frame
error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulsethat is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block supports
an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI
interface operates with a 25-MHz clock.

Datasheet25002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Functional description

3.6.3

USB Full-Speed device interface

PSoC™ 6 incorporates a full-speed USB device interface. The device can have up to eight endpoints. A 512-byte
SRAM buffer is provided and DMA is supported.
Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins
unconnected.

3.6.4

QSPI Interface Serial Memory Interface (SMIF)

A serial memory interface is provided, running at up to 80 MHz. It supports single, dual, quad, dual-quad and octal
SPI configurations, and supports up to four external memory devices. It supports two modes of operation:• Memory-mapped I/O (MMIO), a command mode interface that provides data access via the SMIF registers and
FIFOs• Execute in Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers.
In XIP mode, the external memory is mapped into the PSoC™ 6 MCU internal address space, enabling code
execution directly from the external memory. To improve performance, a 4-KB cache is included. XIP mode also
supports AES-128 on-the-fly encryption and decryption, enabling secured storage and access of code and datain the external memory.

3.6.5

LCD

This block drives LCD commons and segments; routing is available to most of the GPIOs. One to eight of the GPIOs
must be used for commons, the rest can be used for segments.
The LCD block has two modes of operation: high speed (8 MHz) and low speed (32 kHz). Both modes operate insystem LP and ULP modes. Low-speed mode operates with reduced contrast in system Deep Sleep mode - review
the number of common and segment lines, viewing angle requirements, and prototype performance before
using this mode.

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PSoC™ 63 MCU with Bluetooth® LE
Functional description

3.7

GPIO

This product line has up to 84 GPIOs, which implement:• Eight drive strength modes:- Analog input mode (input and output buffers disabled)- Input only
- Weak pull-up with strong pull-down- Strong pull-up with weak pull-down- Open drain with strong pull-down- Open drain with strong pull-up- Strong pull-up with strong pull-down- Weak pull-up with weak pull-down• Input threshold select (CMOS or LVTTL)• Hold mode for latching previous state (used for retaining the I/O state in system Hibernate mode)• Selectable slew rates for dV/dt-related noise control to improve EMI
The pins are organized in logical entities called ports, which are up to 8 pins in width. Data output and pin stateregisters store, respectively, the values to be driven on the pins and the input states of the pins.
Every pin can generate an interrupt if enabled; each port has an interrupt request (IRQ) associated with it.
The port 1 pins are capable of overvoltage-tolerant (OVT) operation, where the input voltage may be higher than
VDDD. OVT pins are commonly used with I2C, to allow powering the chip OFF while maintaining a physicalconnection to an operating I2C bus without affecting its functionality.
GPIO pins can be ganged to source or sink higher values of current. GPIO pins, including OVT pins, may not bepulled up higher than the absolute maximum; see Electrical specifications.
During power-on and reset, the pins are forced to the analog input drive mode, with input and output buffers
disabled, so as not to crowbar any inputs and/or cause excess turn-on current.
A multiplexing network known as the high-speed I/O matrix (HSIOM) is used to multiplex between various
peripheral and analog signals that may connect to an I/O pin.
Analog performance is affected by GPIO switching noise. In order to get the best analog performance, thefollowing frequency and drive mode constraints must be applied. The DRIVE_SEL values (refer to Table 6)
represent drive strengths (see the Architecture and Register TRMs for further detail).
See also Table 5 for additional restrictions for ECO use.
Table 6

DRIVE_SEL Values
Ports

Max Frequency

Port 0Port 18 MHz
1 MHz; slow slew rate, 2 outputs
max
16 MHz; 25 MHz for SPI
80 MHz for SMIF (QSPI).
8 MHz; slow slew rate setting for
TQFP Packages for ADC performance

Ports 5 to 10
Ports 11 to 13
Ports 9 and 10

Datasheet

27

Drive Strength for VDDD ≤ Drive Strength for VDDD >
2.7 V
2.7 V
DRIVE_SEL 2
DRIVE_SEL 3

DRIVE_SEL 1
No restrictions

DRIVE_SEL 2
No restrictions

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PSoC™ 63 MCU with Bluetooth® LE
Functional description

3.8
3.8.1

Special-function peripherals
Audio subsystem

This subsystem consists of the following hardware blocks:• One Inter-IC Sound (I2S) interface• Two pulse-density modulation (PDM) to pulse-code modulation (PCM) decoder channels
The I2S interface implements two independent hardware FIFO buffers – TX and RX, which can operate in masteror slave mode. The following features are supported:• Multiple data formats – I2S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B• Programmable channel/word lengths – 8/16/18/20/24/32 bits
• Internal/external clock operation. Up to 192 ksps
• Interrupt mask events – trigger, not empty, full, overflow, underflow, watchdog• Configurable FIFO trigger level with DMA support
The I2S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones.
The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input
stream to PCM data output. The following features are supported:• Programmable data output word length – 16/18/20/24 bits
• Programmable gain amplifier (PGA) for volume control – from –12 dB to +10.5 dB in 1.5 dB steps• Configurable PDM clock generation. Range from 384 kHz to 3.072 MHz• Droop correction and configurable decimation rate for sampling; up to 48 ksps
• Programmable high-pass filter gain
• Interrupt mask events – not empty, overflow, trigger, underflow• Configurable FIFO trigger level with DMA support
The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones canbe connected to the same PDM Data line.

3.8.2

CAPSENSE™ Subsystem

CAPSENSE™ is supported in PSoC™ 6 MCU through a CAPSENSE™ sigma-delta (CSD) hardware block. It is
designed for high-sensitivity self-capacitance and mutual-capacitance measurements, and is specifically built
for user interface solutions.
In addition to CAPSENSE™, the CSD hardware block supports three general-purpose functions. These areavailable when CAPSENSE™ is not being used. Alternatively, two or more functions can be time-multiplexed in
an application under firmware control. The four functions supported by the CSD hardware block are:
• CAPSENSE™
• 10-bit ADC• Programmable current sources (IDAC)• Comparator
CAPSENSE™
Capacitive touch sensors are designed for user interfaces that rely on human body capacitance to detect thepresence of a finger on or near a sensor. CAPSENSE™ solutions bring elegant, reliable, and simple capacitive
touch sensing functions to applications including IoT, industrial, automotive, and home appliances.
The CAPSENSE™ technology offers the following features:• Best-in-class signal-to-noise ratio (SNR) and robust sensing under harsh and noisy conditions• Self-capacitance (CSD) and mutual-capacitance (CSX) sensing methods

Datasheet28002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Functional description• Support for various widgets, including buttons, matrix buttons, sliders, touchpads, and proximity sensors• High-performance sensing across a variety of materials• Best-in-class liquid tolerance• SmartSense auto-tuning technology that helps avoid complex manual tuning processes• Superior immunity against external noise• Spread-spectrum clocks for low radiated emissions• Gesture and built-in self-test libraries• Ultra-low power consumption• An integrated graphical CAPSENSE™ tuner for real-time tuning, testing, and debugging
CAPSENSE™ sensitivity and accuracy are affected by GPIO switching noise. To improve sensitivity and accuracy,
implement the GPIO port restrictions listed in Table 6, and do the following:• Restrict CAPSENSE™ pins to ports 6 and 7• There should be no other GPIO output activity on ports 6 and 7• There should be no more than two GPIO outputs on ports 5 and 8• Restrict GPIO output switching in ports 5 and 8 to 1 MHz, with slow slew rate setting
ADC
The CAPSENSE™ subsystem slope ADC offers the following features:• Selectable 8- or 10-bit resolution• Selectable input range: GND to VREF and GND to VDDA on any GPIO input• Measurement of VDDA against an internal reference without the use of GPIO or external components
IDAC
The CSD block has two programmable current sources, which offer the following features:• 7-bit resolution• Sink and source current modes• A current source programmable from 37.5 nA to 609 A• Two IDACs that can be used in parallel to form one 8-bit IDAC
Comparator
The CAPSENSE™ subsystem comparator operates in the system Low Power and Ultra-Low Power modes. The
inverting input is connected to an internal programmable reference voltage and the non-inverting input can beconnected to any GPIO via the AMUXBUS.
CapSense Hardware Subsystem
Figure 9 shows the high-level hardware overview of the CAPSENSE™ subsystem, which includes a delta sigma
converter, internal clock dividers, a shield driver, and two programmable current sources.
The inputs are managed through analog multiplexed buses (AMUXBUS A/B). The input and output of all functions
offered by the CSD block can be provided on any GPIO or on a group of GPIOs under software control, with the
exception of the comparator output and external capacitors that use dedicated GPIOs.
Self-capacitance is supported by the CSD block using AMUXBUS A, an external modulator capacitor, and a GPIO
for each sensor. There is a shield electrode (optional) for self-capacitance sensing. This is supported using
AMUXBUS B and an optional external shield tank capacitor (to increase the drive capability of the shield driver)should this be required. Mutual-capacitance is supported by the CSD block using AMUXBUS A, two external
integrated capacitors, and a GPIO for transmit and receive electrodes.
The ADC does not require an external component. Any GPIO that can be connected to AMUXBUS A can be an input
to the ADC under software control. The ADC can accept VDDA as an input without needing GPIOs (for applications
such as battery voltage measurement).

Datasheet29002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Functional description
The two programmable current sources (IDACs) in general-purpose mode can be connected to AMUXBUS A or B.
They can therefore connect to any GPIO pin. The comparator resides in the delta-sigma converter. The
comparator inverting input can be connected to the reference. Both comparator inputs can be connected to any
GPIO using AMUXBUS B; see Figure 9. The reference has a direct connection to a dedicated GPIO; see Table 9.
The CSD block can operate in active and sleep CPU power modes, and seamlessly transition between system LP
and ULP modes. It can be powered down in system Deep Sleep and Hibernate modes. Upon wakeup from
Hibernate mode, the CSD block requires re-initialization. However, operation can be resumed without
re-initialization upon exit from Deep Sleep mode, under firmware control.
AMUXBUSA
B
GPIO Pin
CSD Sensor 1

GPIO
Cell

Clock Input

CS1

I / O Configured for CSD Mode

GPIO Pin

GPIO
Cell

CSD Sensor 2
CS2

CSD Hardware Block

CMOD PinC MOD
C

SH_TANK

Sense clock

Clock
Generator

GPIO Pin( optional )Modulator
Clock

Shield Drive
Circuit
GPIO Pin

GPIO
Cell
CompensationIDAC

C SHIELD

Shield Electrode
Modulator
IDAC

GPIO PinTx
CSX Sensor 3

IDAC control

GPIO
Cell

I / O Configured for CSX Mode

CS3

Rx

C INTA Pin
CINTAI / O for General Purpose
Mode

CINT
B

Figure 9

GPIO Pin

CINTB Pin

Sigma Delta
Converter

GPIO
Cell

Raw
Count

V REF

GPIO
Cell

GPIO
Cell

ADC Input
IDAC Outputs

Comp Input

CAPSENSE™ Hardware Subsystem

Figure 10 shows the high-level software overview. Infineon provides middleware libraries for CAPSENSE™, ADC,
and IDAC on GitHub to enable quick integration. The Board Support Package for any kit with CAPSENSE™
capabilities automatically includes the CAPSENSE™ library in any application that uses the BSP.
User applications interact only with middleware to implement functions of the CSD block. The middlewareinteracts with underlying drivers to access hardware as necessary. The CSD driver facilitates time-multiplexingof the CSD hardware if more than one piece of CSD-related middleware is present in a project. It prevents accessconflicts in this case.
ModusToolbox Software provides a CAPSENSE™ configurator to enable fast library configuration. It also provides
a tuner for performance evaluation and real-time tuning of the system. The tuner requires an EZI2C
communication interface in the application to enable real-time tuning capability. The tuner can update
configuration parameters directly in the device as well as in the configurator.
CAPSENSE™ and ADC middleware use the CSD interrupt to implement non-blocking sensing and A-to-D
conversion. Therefore, interrupt service routines are a defined part of the middleware, which must be initialized
by the application. Middleware and drivers can operate on either CPU. Infineon recommends using the
middleware only in one CPU. If both CPUs must access the CSD driver, memory access should be managed in theapplication.
Datasheet30

002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Functional description
Refer to AN85951: PSoC™ 4 and PSoC™ 6 MCU CAPSENSE™ Design Guide for more details on CSX sensing, CSD
sensing, shield electrode usage and its benefits, and capacitive system design guidelines.
Refer to the API reference guides for CAPSENSE™, ADC, and IDAC available on GitHub.
Application Program
SoftwareMiddleware

Comp

IDAC

ADC

CapSense

Configurator

Tuner

SCB Driver(EZI2C)CSD Driver

GPIO / Clock
DriversSCB

CSD Block

GPIOs / Clock

Hardware and Drivers

Figure 10

Datasheet

CAPSENSE™ software/firmware subsystem

31002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Pinouts

4

Pinouts

Note: The CY8C63x6/CY8C63x7 datasheet web page contains a spreadsheet with a consolidated list of pinouts
and pin alternate functions with HSIOM mapping.
GPIO ports are powered by VDDx pins as follows:• P0: VBACKUP• P1: VDDD. Port 1 pins are overvoltage tolerant (OVT).
• P5, P6, P7, P8: VDDIO1• P9, P10: VDDIOA, VDDA (VDDIOA, when present, and VDDA must be connected together on the PCB)
• P11, P12, P13: VDDIO0• P14: VDDUSB

Datasheet

32002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Pinouts

Table 7
Pin
VDDD
VCCD
VDDA
VDDIOA
VDDIO0VDDIO1VBACKUPVDDUSBVSS
VSSR
VDD_NS
VIND1
VIND2
VBUCK1
VRF
VDCDC
VDDR1
VDDR2
VDDR3
DVDD
VDDR_HVL
XRES
VREF
ANT
GANT
XI
XO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
Datasheet

Packages and Pin Information
124-BGA

116-BGA

Packages
104-M-CSP(no USB)

A13
B1
B13
A2
M13
A9
N13
D11
B3
M4
G10
A10
C1
A2
C11, D4, D10, K4,
B2, B9, D1, H2, H9
K10, M12
A1, B1, B2, C3, D1, E3, J1, K2, K3, K4, K5, L1,
G2
L3, L4, L5, M3, M8
A5
H3
B5
F1
B4
G1
C4
G2
A4
H1
F3
M7
C2
L2
E2
M1
D2
M2
F2
M6
G3
L7
A8
E2
N12
B10
C1
K1
F1
M4
E1
M5
C9
C2
B9
D3
A9
E4
C8
E3
B8
F3
C7
D2
B7
G3
A7
F2
C6
J5
B6
J4
A6
J3
C5
J2
33

104-M-CSP(with USB)
C6
C7
A1
B6
D1
C9

68-QFNH7
D4, D7, F4, G7, P1

68
67
47
53
64
43
1
GND PAD

M3, N9, P3, P6, P7

GND PAD

G9
G8
H8

9
10
11
12
13
24
15
19
20
23
25
8
52
17
16, 18
21
22
2
3
4
5
6
7
-

J8

F9
H9
P4
L9
P9
P8
M4
L2
E5
M9
M5
P5
D8
E6
D9
E7
E8
E9
F5
F6
-

F9

F8
F7

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PSoC™ 63 MCU with Bluetooth® LE
Pinouts
Table 7
Pin
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
P10.0
P10.1
Datasheet

Packages and Pin Information (continued)
124-BGA

116-BGA

G1
H3
H2
H1
J3
J2
J1
K1
K2
K3
L3
L2
L1
M2
M1
N2
N3
M3
N4
N1
L4
N5
M5
L5
N6
M6
L6
N7
M7
L7
N8
M8
L9
M9
N9
L8
N10
M10
L10
N11
M11
L13

L6
K6
J6
K7
J7
L8
M9
K8
J8
L9
K9
J9
M10
L10
K10
J10
H10
H8
H7
H6
G9
G8
G7
F10
F9
F8
F7
G6
E9
E8
E7
D10
D9
D8
D7
C10
C9
C8
C7
B8
A8

Packages
104-M-CSP(no USB)

104-M-CSP(with USB)
J7
J5
J6

H7
H6

H6
H5
J4
K3
K4
J3
K2
M2
L1
J2
K1
N2
M1
N1
G6
H4
G5
H3
H2
G3
G2
G4
G1
F3
F2
F1
E3
E1
E2
D2
C1
D3
B1
C2
B2

34

68-QFN
26
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
48
49
50
51
54
55
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PSoC™ 63 MCU with Bluetooth® LE
Pinouts
Table 7

Packages and Pin Information (continued)

Pin
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P14.0 / USBDP
P14.1 / USBDM
NC

124-BGA

116-BGA

L12
L11
K13
K12
K11
J13
J12
J11
H13
H12
H11
G13
G12
G11
F13
F12
F11
E13
E12
E11
D13
D12
A12
C13
C12
B12
B11
A11
C10
B10
B3
A3
D3

F6
E6
D6
B7
A7
–
F5
E5
D5
C6
B6
A6
B5
A5
A4
B4
C4
A3
C5
D4
G5
H5
H4
G4
–
–
–
–
F4
C3
–
–
–

Packages
104-M-CSP(no USB)

104-M-CSP(with USB)
C3
E4
A2
A3
D5
B3
C4
C5
D6
B4
A4
B5
A5
A6
B7
A7
B8
A8
C8
–
–
–
A9
B9
–
–
–
–
–
–

–
–
H5, J9, P2

J8
J9
P2

68-QFN
–
–
56
57
58
59
60
61
62
63
–
–
–
–
–
–
65
66
–
–
–
–
–
–
–
–
–
–
14, 27

Note: Balls H5 and J9 are No-Connects (NC) in the 104-M-CSP package.

Datasheet35002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Pinouts

P10.0
VDDIOA
VREF

55
54
53
52

58
57
56

VDDIO0
P11.7
P11.6

VCCD
P12.7
P12.6

P11.5
P11.4
P11.3
P11.2
P11.1
P11.0
P10.1

49
48
47
46
45
44
43
42
41
40
39
38
37
36
35

QFN

P9.3
P9.2
P9.1
P9.0
VDDA
P8.2
P8.1
P8.0
VDDIO 1
P7.7
P7.6
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0

P6.5
P6.6
P6.7

28
29
30
31
32
33
34
P6.1
P6.2
P6.3
P6.4

(TOP VIEW)

VDDR_HVL
P6.0
NC

VDDR 1
GANT
ANT

51
50

18
19
20
21
22
23
24
25
26
27

NC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

GANT
VDDR2
VDDR3
XI
XO
DVDD
VDCDC

VBACKUP
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
XRES
VDD_NS
VIND1
VIND2
VBUCK1
VRF

66
65
64
63
62
61
60
59

68
67

VDDD

Figure 11Device Pinout for 68-QFN Package[2]Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins
unconnected.

Note
2. The center pad on the QFN package should be connected to PCB ground relative to device VDDx for best mechanical, thermal, andelectrical performance. For more information, see AN72845, Design Guidelines for QFN Devices.

Datasheet36002-18787 Rev. *R
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ACT #0

ACT #1

P0.0

tcpwm[0].l tcpwm[1].line
ine[0]:0
[0]:0

P0.1

DS #2

ACT #4

ACT #5

ACT #6

srss.ext_clk:0

ACT #7

ACT #8

ACT #9

ACT #10

ACT #12

ACT #1337

scb[0].spi_
select1:0

peri.tr_io_i
nput[0]:0

tcpwm[0].ltcpwm[1].line
ine_compl_compl[0]:0[0]:0

scb[0].spi_
select2:0

peri.tr_io_i
nput[1]:0

P0.2

tcpwm[0].l tcpwm[1].line
ine[1]:0[1]:0

scb[0].ua scb[0].i2c scb[0].spi_
rt_rx:0_scl:0mosi:0P0.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[1]:0[1]:0

scb[0].ua scb[0].i2c scb[0].spi_
rt_tx:0_sda:0miso:0P0.4

tcpwm[0].l tcpwm[1].line
ine[2]:0[2]:0scb[0].ua
rt_rts:0

scb[0].spi_
clk:0

peri.tr_io_o
utput[0]:2

P0.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[2]:0[2]:0

scb[0].ua
rt_cts:0

scb[0].spi_
select0:0

peri.tr_io_o
utput[1]:2

P1.0

tcpwm[0].l tcpwm[1].line
ine[3]:0[3]:0scb[7].ua scb[7].i2c scb[7].spi_
rt_rx:0_scl:0mosi:0peri.tr_io_i
nput[2]:0

P1.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[3]:0[3]:0scb[7].ua scb[7].i2c scb[7].spi_
rt_tx:0_sda:0miso:0peri.tr_io_i
nput[3]:0

P1.2

tcpwm[0].l tcpwm[1].line
ine[4]:4[12]:1

scb[7].ua
rt_rts:0

scb[7].spi_
clk:0

P1.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[12]:1[4]:4

scb[7].ua
rt_cts:0

scb[7].spi_
select0:0

P1.4

tcpwm[0].l tcpwm[1].line
ine[5]:4[13]:1

scb[7].spi_
select1:0

P1.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[14]:1[5]:4

scb[7].spi_
select2:0

P5.0

tcpwm[0].l tcpwm[1].line
ine[4]:0[4]:0scb[5].ua scb[5].i2c scb[5].spi_
rt_rx:0_scl:0mosi:0audioss.clk peri.tr_io_i_i2s_if
nput[10]:0

P5.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[4]:0[4]:0scb[5].ua scb[5].i2c scb[5].spi_
rt_tx:0_sda:0miso:0audioss.tx_ peri.tr_io_isck
nput[11]:0

P5.2

tcpwm[0].l tcpwm[1].line
ine[5]:0[5]:0scb[5].ua
rt_rts:0

audioss.tx_
ws

srss.ext_clk:1

scb[5].spi_
clk:0

ACT #14

ACT #15

DS #4

DS #5

DS #6

cpuss.swj_t
rstn

002-18787 Rev. *R
2023-05-10

Note
3. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are
more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of theline output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisationof on-chip resources.

PSoC™ 63 MCU with Bluetooth® LE

Multiple Alternate Functions[3]Table 8
Port/
Pin

Pinouts

Datasheet

Each Port Pin has multiple alternate functions. These are defined in Table 8.

ACT #0

ACT #1

P5.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[5]:0
[5]:0

P5.4

DS #2

ACT #4

ACT #5

ACT #6
scb[5].ua
rt_cts:0

ACT #7

ACT #8

ACT #9

ACT #10

ACT #12

ACT #13

ACT #14

ACT #15

DS #4

DS #5

DS #6

38

scb[5].spi_
select0:0

audioss.tx_
sdo

tcpwm[0].l tcpwm[1].lineine[6]:0[6]:0scb[5].spi_
select1:0

audioss.rx_
sck

P5.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[6]:0[6]:0

scb[5].spi_
select2:0

audioss.rx_
ws

P5.6

tcpwm[0].l tcpwm[1].lineine[7]:0[7]:0scb[5].spi_
select3:0

audioss.rx_
sdi

P5.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[7]:0[7]:0

scb[3].spi_
select3:0

P6.0

tcpwm[0].l tcpwm[1].line scb[8].i2c
ine[0]:1[8]:0_scl:0scb[3].ua scb[3].i2c scb[3].spi_
rt_rx:0_scl:0mosi:0

cpuss.fault_out[0]scb[8].spi_
mosi:0

P6.1

tcpwm[0].ltcpwm[1].line scb[8].i2c
ine_compl_compl[8]:0_sda:0[0]:1

scb[3].ua scb[3].i2c scb[3].spi_
rt_tx:0_sda:0miso:0

cpuss.fault_out[1]

scb[8].spi_
miso:0

P6.2

tcpwm[0].l tcpwm[1].line
ine[1]:1[9]:0

scb[3].ua
rt_rts:0

scb[3].spi_
clk:0

scb[8].spi_
clk:0

P6.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[9]:0[1]:1

scb[3].ua
rt_cts:0

scb[3].spi_
select0:0

scb[8].spi_
select0:0

P6.4

tcpwm[0].l tcpwm[1].line scb[8].i2c
ine[2]:1[10]:0_scl:1

scb[6].ua scb[6].i2c scb[6].spi_
rt_rx:2_scl:2
mosi:2

peri.tr_io_i peri.tr_io_o
nput[12]:0 utput[0]:1

cpuss.swj_s scb[8].spi_
wo_tdomosi:1

P6.5

tcpwm[0].ltcpwm[1].line scb[8].i2c
ine_compl_compl[10]:0_sda:1[2]:1

scb[6].ua scb[6].i2c scb[6].spi_
rt_tx:2_sda:2
miso:2

peri.tr_io_i peri.tr_io_o
nput[13]:0 utput[1]:1

cpuss.swj_s scb[8].spi_
wdoe_tdi
miso:1

P6.6

tcpwm[0].l tcpwm[1].line
ine[3]:1[11]:0scb[6].ua
rt_rts:2

scb[6].spi_
clk:2

cpuss.swj_s scb[8].spi_
wdio_tms
clk:1

P6.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[11]:0[3]:1

scb[6].ua
rt_cts:2

scb[6].spi_
select0:2

cpuss.swj_s scb[8].spi_
wclk_tclk
select0:1

P7.0

tcpwm[0].l tcpwm[1].line
ine[4]:1[12]:0scb[4].ua scb[4].i2c scb[4].spi_
rt_rx:1_scl:1
mosi:1

peri.tr_io_i
nput[14]:0

P7.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[12]:0[4]:1

scb[4].ua scb[4].i2c scb[4].spi_
rt_tx:1_sda:1
miso:1

peri.tr_io_i
nput[15]:0

cpuss.trace_clock002-18787 Rev. *R
2023-05-10

Note
3. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are
more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of theline output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisationof on-chip resources.

PSoC™ 63 MCU with Bluetooth® LE

Port/
Pin

Pinouts

Datasheet

Multiple Alternate Functions[3] (continued)

Table 8

ACT #0

ACT #1DS #2

ACT #4

ACT #5

ACT #6

ACT #7

ACT #8

ACT #9

ACT #10

ACT #12

ACT #13

ACT #14

ACT #15

cpuss.trace_data[3]:2

39

P7.2

tcpwm[0].l tcpwm[1].line
ine[5]:1[13]:0scb[4].ua
rt_rts:1

scb[4].spi_
clk:1

P7.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[13]:0[5]:1

scb[4].ua
rt_cts:1

scb[4].spi_
select0:1

P7.4

tcpwm[0].l tcpwm[1].lineine[6]:1[14]:0scb[4].spi_
select1:1

bless.ext_lna_rx_ctl_out

P7.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[14]:0[6]:1

scb[4].spi_
select2:1

bless.ext_pa_tx- cpuss.trace_ctl_out_data[2]:2

P7.6

tcpwm[0].l tcpwm[1].lineine[7]:1[15]:0scb[4].spi_
select3:1

bless.ext_pa_l- cpuss.trace
na_chip_en_out _data[1]:2

P7.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[15]:0[7]:1

scb[3].spi_ cpuss.clk_f
select1:0
m_pumpP8.0

tcpwm[0].l tcpwm[1].line
ine[0]:2[16]:0scb[4].ua scb[4].i2c scb[4].spi_
rt_rx:0_scl:0mosi:0peri.tr_io_i
nput[16]:0

P8.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[16]:0[0]:2

scb[4].ua scb[4].i2c scb[4].spi_
rt_tx:0_sda:0miso:0peri.tr_io_i
nput[17]:0

P8.2

tcpwm[0].l tcpwm[1].line
ine[1]:2[17]:0scb[4].ua
rt_rts:0

scb[4].spi_
clk:0

P8.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[17]:0[1]:2

scb[4].ua
rt_cts:0

scb[4].spi_
select0:0

P8.4

tcpwm[0].l tcpwm[1].line
ine[2]:2[18]:0scb[4].spi_
select1:0

P8.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[18]:0[2]:2

scb[4].spi_
select2:0

P8.6

tcpwm[0].l tcpwm[1].line
ine[3]:2[19]:0scb[4].spi_
select3:0

P8.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[19]:0[3]:2

scb[3].spi_
select2:0

P9.0

tcpwm[0].l tcpwm[1].line
ine[4]:2[20]:0scb[2].ua scb[2].i2c scb[2].spi_
rt_rx:0_scl:0mosi:0

DS #4

DS #5

DS #6

cpuss.trace_data[0]:2

peri.tr_io_i
nput[18]:0

cpuss.trace_data[3]:0002-18787 Rev. *R
2023-05-10

Note
3. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are
more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of theline output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisationof on-chip resources.

PSoC™ 63 MCU with Bluetooth® LE

Port/
Pin

Pinouts

Datasheet

Multiple Alternate Functions[3] (continued)

Table 8

ACT #0

ACT #1DS #2

ACT #4

ACT #5

ACT #6

ACT #7

ACT #8

ACT #9

ACT #10

ACT #12

ACT #13

ACT #14

ACT #1540

P9.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[20]:0[4]:2

scb[2].ua scb[2].i2c scb[2].spi_
rt_tx:0_sda:0miso:0

P9.2

tcpwm[0].l tcpwm[1].line
ine[5]:2[21]:0scb[2].ua
rt_rts:0

scb[2].spi_
clk:0

pass.dsi_ctb_cmp0:1

cpuss.trace_data[1]:0

P9.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[21]:0[5]:2

scb[2].ua
rt_cts:0

scb[2].spi_
select0:0

pass.dsi_ctb_cmp1:1

cpuss.trace_data[0]:0

P9.4

tcpwm[0].l tcpwm[1].lineine[7]:5[0]:2

scb[2].spi_
select1:0

P9.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[0]:2[7]:5

scb[2].spi_
select2:0

P9.6

tcpwm[0].l tcpwm[1].line
ine[0]:6[1]:2

scb[2].spi_
select3:0

P9.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[1]:2
[0]:6

P10.0

tcpwm[0].l tcpwm[1].lineine[6]:2[22]:0scb[1].ua scb[1].i2c scb[1].spi_
rt_rx:1_scl:1
mosi:1

peri.tr_io_i
nput[20]:0

cpuss.trace_data[3]:1

P10.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[22]:0[6]:2

scb[1].ua scb[1].i2c scb[1].spi_
rt_tx:1_sda:1
miso:1

peri.tr_io_i
nput[21]:0

cpuss.trace_data[2]:1

P10.2

tcpwm[0].l tcpwm[1].lineine[7]:2[23]:0scb[1].ua
rt_rts:1

scb[1].spi_
clk:1

cpuss.trace_data[1]:1

P10.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[23]:0[7]:2

scb[1].ua
rt_cts:1

scb[1].spi_
select0:1

cpuss.trace_data[0]:1

P10.4

tcpwm[0].l tcpwm[1].line
ine[0]:3[0]:1

scb[1].spi_ audioss.pd
select1:1
m_clk

P10.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[0]:1[0]:3

scb[1].spi_ audioss.pd
select2:1
m_dataP10.6

tcpwm[0].l tcpwm[1].line
ine[1]:6[2]:2

scb[1].spi_
select3:1

P10.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[2]:2[1]:6

peri.tr_io_i
nput[19]:0

DS #4

DS #5

DS #6

cpuss.trace_data[2]:0002-18787 Rev. *R
2023-05-10

Note
3. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are
more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of theline output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisationof on-chip resources.

PSoC™ 63 MCU with Bluetooth® LE

Port/
Pin

Pinouts

Datasheet

Multiple Alternate Functions[3] (continued)

Table 8

ACT #0

ACT #1DS #2

ACT #4

ACT #5

ACT #6

ACT #7

ACT #8

ACT #9

ACT #10

ACT #12

ACT #13

P11.0

tcpwm[0].l tcpwm[1].line
ine[1]:3[1]:1

smif.spi_ scb[5].ua scb[5].i2c scb[5].spi_
select2
rt_rx:1_scl:1
mosi:1

peri.tr_io_i
nput[22]:0

P11.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[1]:1[1]:3

smif.spi_ scb[5].ua scb[5].i2c scb[5].spi_
select1
rt_tx:1_sda:1
miso:1

peri.tr_io_i
nput[23]:0

P11.2

tcpwm[0].l tcpwm[1].line
ine[2]:3[2]:1

smif.spi_ scb[5].ua
select0
rt_rts:1

scb[5].spi_
clk:1

P11.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[2]:1[2]:3

smif.spi_ scb[5].ua
data3
rt_cts:1

scb[5].spi_
select0:1

peri.tr_io_o
utput[0]:0

P11.4

tcpwm[0].l tcpwm[1].line
ine[3]:3[3]:1

smif.spi_
data2

scb[5].spi_
select1:1

peri.tr_io_o
utput[1]:0

P11.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[3]:1[3]:3

smif.spi_
data1

scb[5].spi_
select2:1

P11.6

smif.spi_
data0

scb[5].spi_
select3:1

P11.7

smif.spi_
clk

41

P12.0

tcpwm[0].l tcpwm[1].line
ine[4]:3[4]:1

smif.spi_ scb[6].ua scb[6].i2c scb[6].spi_
data4
rt_rx:0_scl:0mosi:0peri.tr_io_i
nput[24]:0

P12.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[4]:1[4]:3

smif.spi_ scb[6].ua scb[6].i2c scb[6].spi_
data5
rt_tx:0_sda:0miso:0peri.tr_io_i
nput[25]:0

P12.2

tcpwm[0].l tcpwm[1].line
ine[5]:3[5]:1

smif.spi_ scb[6].ua
data6
rt_rts:0

scb[6].spi_
clk:0

P12.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[5]:1[5]:3

smif.spi_ scb[6].ua
data7
rt_cts:0

scb[6].spi_
select0:0

P12.4

tcpwm[0].l tcpwm[1].lineine[6]:3[6]:1

smif.spi_select3scb[6].spi_ audioss.pd
select1:0
m_clk

P12.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[6]:1[6]:3

scb[6].spi_ audioss.pd
select2:0
m_dataP12.6

tcpwm[0].l tcpwm[1].lineine[7]:3[7]:1

scb[6].spi_
select3:0

ACT #14

ACT #15

DS #4

DS #5

DS #6

002-18787 Rev. *R
2023-05-10

Note
3. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are
more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of theline output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisationof on-chip resources.

PSoC™ 63 MCU with Bluetooth® LE

Port/
Pin

Pinouts

Datasheet

Multiple Alternate Functions[3] (continued)

Table 8

ACT #0

ACT #1DS #2

ACT #4

ACT #5

ACT #6

ACT #7

ACT #8

ACT #9

ACT #10

ACT #1242

P12.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[7]:1
[7]:3

P13.0

tcpwm[0].l tcpwm[1].line
ine[0]:4[8]:1

scb[6].ua scb[6].i2c scb[6].spi_
rt_rx:1_scl:1
mosi:1

peri.tr_io_i
nput[26]:0

P13.1

tcpwm[0].ltcpwm[1].line
ine_compl_compl[8]:1[0]:4

scb[6].ua scb[6].i2c scb[6].spi_
rt_tx:1_sda:1
miso:1

peri.tr_io_i
nput[27]:0

P13.2

tcpwm[0].l tcpwm[1].line
ine[1]:4[9]:1

scb[6].ua
rt_rts:1

scb[6].spi_
clk:1

P13.3

tcpwm[0].ltcpwm[1].line
ine_compl_compl[9]:1[1]:4

scb[6].ua
rt_cts:1

scb[6].spi_
select0:1

P13.4

tcpwm[0].l tcpwm[1].line
ine[2]:4[10]:1

scb[6].spi_
select1:1

P13.5

tcpwm[0].ltcpwm[1].line
ine_compl_compl[10]:1[2]:4

scb[6].spi_
select2:1

P13.6

tcpwm[0].l tcpwm[1].line
ine[3]:4[11]:1

scb[6].spi_
select3:1

P13.7

tcpwm[0].ltcpwm[1].line
ine_compl_compl[11]:1[3]:4

ACT #13

ACT #14

ACT #15

DS #4

DS #5

DS #6

Note
3. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are
more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of theline output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximise utilisationof on-chip resources.

PSoC™ 63 MCU with Bluetooth® LE

Port/
Pin

Pinouts

Datasheet

Multiple Alternate Functions[3] (continued)

Table 8002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Pinouts
Analog, Smart I/O, and DSI alternate Port Pin functionality is provided in Table 9.
Table 9Port Pin Analog, Smart I/O, and DSI Functions

Port/Pin

Name

AnalogP0.0

P0.0

wco_indsi[0].port_if[0]

P0.1

P0.1

wco_out

dsi[0].port_if[1]

P0.2

P0.2

dsi[0].port_if[2]

P0.3

P0.3

dsi[0].port_if[3]

P0.4

P0.4

pmic_wakeup_in
hibernate_wakeup[1]dsi[0].port_if[4]

P0.5

P0.5

pmic_wakeup_out

dsi[0].port_if[5]

P1.0

P1.0

dsi[1].port_if[0]

P1.1

P1.1

dsi[1].port_if[1]

P1.2

P1.2

dsi[1].port_if[2]

P1.3

P1.3

dsi[1].port_if[3]

P1.4

P1.4

P1.5

P1.5

dsi[1].port_if[5]

P2.0

P2.0

dsi[2].port_if[0]

P2.1

P2.1

dsi[2].port_if[1]

P2.2

P2.2

dsi[2].port_if[2]

P2.3

P2.3

dsi[2].port_if[3]

P2.4

P2.4

dsi[2].port_if[4]

P2.5

P2.5

dsi[2].port_if[5]

P2.6

P2.6

dsi[2].port_if[6]

P2.7

P2.7

dsi[2].port_if[7]

P3.0

P3.0

P3.1

P3.1

P3.2

P3.2

P3.3

P3.3

P3.4

P3.4

P3.5

P3.5

P4.0

P4.0

dsi[0].port_if[6]

P4.1

P4.1

dsi[0].port_if[7]

P4.2

P4.2

dsi[1].port_if[6]

P4.3

P4.3

dsi[1].port_if[7]

P5.0

P5.0

dsi[3].port_if[0]

P5.1

P5.1

dsi[3].port_if[1]

P5.2

P5.2

dsi[3].port_if[2]

P5.3

P5.3

dsi[3].port_if[3]Datasheet

Digital HVhibernate_wakeup[0]

43

DSI

SMARTIO

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PSoC™ 63 MCU with Bluetooth® LE
Pinouts
Table 9Port Pin Analog, Smart I/O, and DSI Functions (continued)

Port/Pin

Name

P5.4

P5.4

dsi[3].port_if[4]

P5.5

P5.5

dsi[3].port_if[5]

P5.6

P5.6

lpcomp.inp_com
p0

dsi[3].port_if[6]

P5.7

P5.7

lpcomp.inn_com
p0

dsi[3].port_if[7]

P6.0

P6.0

dsi[4].port_if[0]

P6.1

P6.1

dsi[4].port_if[1]

P6.2

P6.2

lpcomp.inp_com
p1

dsi[4].port_if[2]

P6.3

P6.3

lpcomp.inn_com
p1

dsi[4].port_if[3]

P6.4

P6.4

dsi[4].port_if[4]

P6.5

P6.5

dsi[4].port_if[5]

P6.6

P6.6

swd_data

dsi[4].port_if[6]

P6.7

P6.7

swd_clkdsi[4].port_if[7]

P7.0

P7.0

P7.1

P7.1

csd.cmodpadd
csd.cmodpads

dsi[5].port_if[1]

P7.2

P7.2

csd.csh_tankpad
dcsd.csh_tankpads

dsi[5].port_if[2]

P7.3

P7.3

csd.vref_ext

dsi[5].port_if[3]

P7.4

P7.4

dsi[5].port_if[4]

P7.5

P7.5

dsi[5].port_if[5]

P7.6

P7.6

dsi[5].port_if[6]

P7.7

P7.7

P8.0

P8.0

dsi[11].port_if[0] smartio[8].io[0
]

P8.1

P8.1

dsi[11].port_if[1] smartio[8].io[1
]

P8.2

P8.2

dsi[11].port_if[2] smartio[8].io[2
]

P8.3

P8.3

dsi[11].port_if[3] smartio[8].io[3
]

P8.4

P8.4

dsi[11].port_if[4] smartio[8].io[4
]

P8.5

P8.5

dsi[11].port_if[5] smartio[8].io[5
]

P8.6

P8.6

dsi[11].port_if[6] smartio[8].io[6]Datasheet

AnalogDigital HV

DSISMARTIO

dsi[5].port_if[0]csd.cshieldpads

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PSoC™ 63 MCU with Bluetooth® LE
Pinouts
Table 9Port Pin Analog, Smart I/O, and DSI Functions (continued)

Port/Pin

Name

P8.7

P8.7

P9.0

P9.0

ctb_oa0+dsi[10].port_if[0] smartio[9].io[0
]

P9.1

P9.1

ctb_oa0-dsi[10].port_if[1] smartio[9].io[1
]

P9.2

P9.2

ctb_oa0_out

dsi[10].port_if[2] smartio[9].io[2
]

P9.3

P9.3

ctb_oa1_out

dsi[10].port_if[3] smartio[9].io[3
]

P9.4

P9.4

ctb_oa1-dsi[10].port_if[4] smartio[9].io[4
]

P9.5

P9.5

ctb_oa1+dsi[10].port_if[5] smartio[9].io[5
]

P9.6

P9.6

ctb_oa0+or ctdac_out

dsi[10].port_if[6] smartio[9].io[6
]

P9.7

P9.7

ctb_oa1+or ext_vref

dsi[10].port_if[7] smartio[9].io[7
]

P10.0

P10.0

sarmux[0]dsi[9].port_if[0]

P10.1

P10.1

sarmux[1]dsi[9].port_if[1]

P10.2

P10.2

sarmux[2]dsi[9].port_if[2]

P10.3

P10.3

sarmux[3]dsi[9].port_if[3]

P10.4

P10.4

sarmux[4]dsi[9].port_if[4]

P10.5

P10.5

sarmux[5]dsi[9].port_if[5]

P10.6

P10.6

sarmux[6]dsi[9].port_if[6]

P10.7

P10.7

sarmux[7]dsi[9].port_if[7]

P11.0

P11.0

dsi[8].port_if[0]

P11.1

P11.1

dsi[8].port_if[1]

P11.2

P11.2

dsi[8].port_if[2]

P11.3

P11.3

dsi[8].port_if[3]

P11.4

P11.4

dsi[8].port_if[4]

P11.5

P11.5

dsi[8].port_if[5]

P11.6

P11.6

dsi[8].port_if[6]

P11.7

P11.7

dsi[8].port_if[7]

P12.0

P12.0

dsi[7].port_if[0]

P12.1

P12.1

dsi[7].port_if[1]

P12.2

P12.2

dsi[7].port_if[2]

P12.3

P12.3

dsi[7].port_if[3]

P12.4

P12.4

dsi[7].port_if[4]

P12.5

P12.5

dsi[7].port_if[5]

P12.6

P12.6

Datasheet

AnalogDigital HV

DSISMARTIO

dsi[11].port_if[7] smartio[8].io[7]srss.eco_in45dsi[7].port_if[6]002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Pinouts
Table 9Port Pin Analog, Smart I/O, and DSI Functions (continued)

Port/Pin

Name

Analog

P12.7

P12.7

srss.eco_out

P13.0

P13.0

dsi[6].port_if[0]

P13.1

P13.1

dsi[6].port_if[1]

P13.2

P13.2

dsi[6].port_if[2]

P13.3

P13.3

dsi[6].port_if[3]

P13.4

P13.4

dsi[6].port_if[4]

P13.5

P13.5

dsi[6].port_if[5]

P13.6

P13.6

dsi[6].port_if[6]

P13.7

P13.7

dsi[6].port_if[7]Datasheet

Digital HV

46

DSI

SMARTIO

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PSoC™ 63 MCU with Bluetooth® LE
Power Supply Considerations

5

Power Supply Considerations

The following power system diagrams show typical connections for power pins for all supported packages.
In these diagrams, the package pin is shown with the pin name, for example “VDDA, M13”. For VDDx pins, the I/O
port that is powered by that pin is also shown, for example “VDDD, A13; I/O port P1”.
1.7 to 3.6 V

CY8C63x6/7, 124-BGA package

1 KΩ at
100 MHz10 µF

0.1 µF1 µF

0.1 µF

1 µF

1 KΩ at
100 MHz

1 KΩ at
100 MHz0.1 µF1 µF

0.1 µF1 µF

0.1 µF10 µF

0.1 µFVDDD , A13; I/O port P1

V DD_NS, A5

VBACKUP, A10; I/O port P0

VBUCK 1, C4

0.1 µF10 µF

4.7 µF

VDDIO0 , D11; I/O ports P11, P12, P13
VCCD , B13
VDDIO1 , M4; I/O ports P5, P6, P7, P8
VDDUSB, A2; I/O port P14

VIND1 , B5
2.2 µH

VDDA, M13

VIND2 , B4

0.1 µF

VDDIOA, N13; I/O ports P9, P10
VRF , A4
1 KΩ at
100 MHz
1 µF

1 µF

DV DD , F2

VDCDC , F3

V DDR_HVL, G3

VDDR1, C2
VDDR2, E2
VDDR3 , D2

Figure 12

Datasheet

C11, D4, D10, K4, K10, M12

A1, B1, B2, C3, D1, E3, G2

VSS

V SSR

10 µF

0.1 µF1 µF

0.1 µF1 µF

0.1 µF

1 µF

124-BGA Power Connection Diagram

47

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PSoC™ 63 MCU with Bluetooth® LE
Power Supply Considerations

1.7 to 3.6 V

CY8C63x6/7, 116-BGA package

1 KΩ at
100 MHz10 µF

0.1 µF1 µF

0.1 µF

1 µF

1 KΩ at
100 MHz

1 KΩ at
100 MHz0.1 µF1 µF

0.1 µF10 µF

0.1 µFVDDD , B1; I/O port P1

VDD_NS, H3

VBACKUP, C1; I/O port P0

V BUCK1, G2

0.1 µF10 µF

4.7 µF

VDDIO0, B3; I/O ports P11, P12, P13
V CCD, A2
VDDIO1, G10; I/O ports P5, P6, P7, P8
VDDA , A9; I/O ports P9, P10

V IND1, F1
2.2 µH

VIND2, G1

0.1 µF

V RF, H1
1 KΩ at
100 MHz
1 µF

1 µF

DV DD, M6

VDCDC , M7

VDDR_HVL, L7

V DDR1, L2
VDDR2, M1
V DDR3, M2

Figure 13

Datasheet

B2, B9, D1, H2, H9

J1, K2, K3, K4, K5, L1, L3, L4, L5, M3, M8

V SS

VSSR

10 µF

0.1 µF1 µF

0.1 µF1 µF

0.1 µF

1 µF

116-BGA Power Connection Diagram

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PSoC™ 63 MCU with Bluetooth® LE
Power Supply Considerations

1.7 to 3.6 V

CY8C63x6/7, 104-M-CSP package (no USB)

1 KΩ at
100 MHz

10 µF

1 µF

1 KΩ at
100 MHz

1 KΩ at
100 MHz0.1 µF0.1 µF1 µF

0.1 µF1 µF

0.1 µF10 µF

0.1 µFVDDD, C6; I/O port P1

VDD_NS , G9

VBACKUP, C9; I/O port P0

0.1 µFVBUCK1, J8

10 µF

4.7 µF

VDDIO0, B6; I/O ports P11, P12, P13
VCCD, C7VDDIO1, D1; I/O ports P5, P6, P7, P8
VDDA, A1; I/O ports P9, P10

VIND1, G8
2.2 µH

VIND2, H8

0.1 µF

VRF, H9
1 KΩ at
100 MHz
1 µF

1 µF

DVDD, M4VDCDC, P4

VDDR_HVL, L2

VDDR1, L9

10 µF

VDDR2, P9
VDDR3, P8

Figure 14

D4, D7, F4, G7, P1

M3, N9, P3, P6, P7

VSS

VSSR

0.1 µF1 µF

0.1 µF1 µF

0.1 µF

1 µF

104-M-CSP Power Connection Diagram

1.7 to 3.6 V

CY8C63x6/7, 104-M-CSP package (with USB)

1 KΩ at
100 MHz

10 µF

1 µF

1 KΩ at
100 MHz

1 KΩ at
100 MHz0.1 µF0.1 µF1 µF

0.1 µF1 µF

0.1 µF1 µF

0.1 µF10 µF

0.1 µFVDDD, C6; I/O port P1

VDD_NS , G9

VBACKUP, C9; I/O port P0

VBUCK1, F9

0.1 µF10 µF

4.7 µF

VDDIO0, B6; I/O ports P11, P12, P13
VCCD, C7VDDIO1, D1; I/O ports P5, P6, P7, P8
VDDUSB , H7; I/O port P14

VIND1, G8

VDDA, A1; I/O ports P9, P10

VIND2, H8

2.2 µH0.1 µF

VRF, H9
1 KΩ at
100 MHz
1 µF

1 µF

DVDD, M4VDCDC, P4

VDDR_HVL, L2

VDDR1, L9
VDDR2, P9
VDDR3, P8

Figure 15

Datasheet

D4, D7, F4, G7, P1

M3, N9, P3, P6, P7

VSS

VSSR

10 µF

0.1 µF1 µF

0.1 µF1 µF

0.1 µF

1 µF

104-M-CSP-USB Power Connection Diagram

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PSoC™ 63 MCU with Bluetooth® LE
Power Supply Considerations
In the QFN package, all internal grounds are routed to the metal pad (epad) in the package. This pad must be
grounded on the PCB. In addition, the two antenna ground pins (GANT1 and GANT2) on the 68-QFN package
should also be connected to the epad ground on the PCB with as short a connection as possible.
1.7 to 3.6 V

CY8C63x6/7, 68-QFN package

1 KΩ at
100 MHz10 µF

0.1 µF1 µF

0.1 µF

1 µF

1 KΩ at
100 MHz

1 KΩ at
100 MHz0.1 µF1 µF

0.1 µF10 µF

0.1 µFVDDD , 68

VDD_NS, 9

VBACKUP, 1; I/O port P0

VBUCK1 , 12

0.1 µF10 µF

4.7 µF

VDDIO0, 64; I/O ports P11, P12
VCCD, 67
VDDIO1, 43; I/O ports P6, P7, P8
V IND1, 10

VDDA , 47
VDDIOA , 53; I/O ports P9, P10

2.2 µHV IND2, 11

0.1 µF

VRF, 13
1 KΩ at
100 MHz
1 µF

1 µF

DVDD, 23

V DCDC , 24

VDDR_HVL, 25

V DDR1, 15
V DDR2, 19
VDDR3 , 20

10 µF

0.1 µF1 µF

0.1 µF1 µF

0.1 µF

1 µF

GND PAD

Figure 16

68-QFN Power Connection Diagram

There are as many as eight VDDx supply pins, depending on the package, and multiple VSS ground pins. The power
pins are:• VDDD: the main digital supply. It powers the low dropout (LDO) regulators and I/O port 1. [4]..
• VCCD: the main LDO output. It requires a 4.7-µF capacitor for regulation. The LDO can be turned off when VCCD
is driven from the switching regulator (see VBUCK1 below). For more information, see the power system block
diagram in the device technical reference manual (TRM).
• VDDA: the supply for the analog peripherals. Voltage must be applied to this pin for correct device initialization
and boot up.
• VDDIOA: the supply for I/O ports 9 and 10. If it is present in the device package, it must be connected to VDDA.
• VDDIO0: the supply for I/O ports 11, 12, and 13.
Note
4. Port 1 is not available in the 68-QFN package.
Datasheet

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PSoC™ 63 MCU with Bluetooth® LE
Power Supply Considerations• VDDIO1: the supply for I/O ports 5, 6, 7, and 8.
• VBACKUP: the supply for the backup domain, which includes the 32-kHz WCO and the RTC. It can be a separate
supply as low as 1.4 V, for battery or supercapacitor backup, as Figure 17 shows. Otherwise it is connected to
VDDD. It powers I/O port 0.
Figure 17

Separate Battery Connection to VBACKUP

1.7 to 3.6 V

1.4 to 3.6 V

10 µF

0.1 µF1 µF

0.1 µFVDDD
VBACKUP• VDDUSB: the supply for the USB peripheral and the USBDP and USBDM pins. It must be 2.85 V to 3.6 V for USB
operation. If USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can be used as limited-capability GPIOs
on I/O port 14.
Table 10 shows a summary of the I/O port supplies:
Table 10I/O Port Supplies
Port0
1
5, 6, 7, 8
9, 10
11, 12, 13
14

SupplyVBACKUP
VDDD
VDDIO1VDDIOA
VDDIO0VDDUSB

Alternate Supply
VDDD
VDDA
-

Note: If the USB pins are not used, connect VDDUSB to ground and leave the P14.0/USBDP and P14.1/USBDM pins
unconnected.
Voltage must be applied to the VDDD pin, and the VDDA pin as noted above, for correct device initialization andoperation. If an I/O port is not being used, applying voltage to the corresponding VDDx pin is optional.
• VSS and VSSR: ground pins for the above supplies. All ground pins should be connected together to a common
ground.
In addition to the LDO regulator, a single input multiple output (SIMO) switching regulator is included. It provides
two regulated outputs using a single inductor. The regulator pins are:
• VDD_NS: the regulator supply.
• VIND1 and VIND2: the inductor and capacitor connections.
• VBUCK1: the first regulator output. It is typically used to drive VCCD, see above• VRF: the second regulator output. It is typically used to drive the Bluetooth® LE radio power pins: VDCDC and VDDRx.
A set of power pins for the Bluetooth® LE radio are included. They are:
• VDCDC: the radio digital supply.
• VDDR1, VDDR2, and VDDR3: the radio analog supplies.
• DVDD: the radio digital LDO output. It requires a 1-µF capacitor for regulation.

Datasheet51002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Power Supply Considerations• VDDR_HVL: the radio analog LDO output. It requires a 1-µF capacitor for regulation.
The various VDD power pins are not connected together on chip. They can be connected off chip, in one or more
separate nets. If separate power nets are used, they can be isolated from noise from the other nets using optional
ferrite beads, as indicated in the diagrams.
No external load should be placed on VCCD, VRF, or any of the switching regulator power pins; whether or not theswitching regulator is used.
There are no power pin sequencing requirements; power supplies may be brought up in any order. The power
management system holds the device in reset until all power pins are at the voltage levels required for proper
operation.
Note: If a battery is installed on the PCB first, VDDD must be cycled for at least 50 µs. This prevents prematuredrain of the battery during product manufacture and storage.
Bypass capacitors must be connected to a common ground from the VDDx and other pins, as indicated in the
diagrams. Typical practice for systems in this frequency range is to use a 10-µF or 1-µF capacitor in parallel witha smaller capacitor (0.1 µF, for example). Note that these are simply rules of thumb and that, for criticalapplications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated for optimal
bypassing.
All capacitors and inductors should be ±20% or better. The capacitor connected to VIND2 should be 100 nF. The
recommended inductor value is 2.2 µH ±20% (for example, TDK MLP2012H2R2MT0S1).
It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and theDC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the applied
voltage is a significant percentage of the rated working voltage.
For more information on pad layout, refer to PSoC™ 6 CAD libraries.

Datasheet52002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6

Electrical specifications

All specifications are valid for –40°C ≤ TA ≤ 85°C and for 1.71 V to 3.6 V except where noted.

6.1

Absolute maximum ratings

Table 11

Absolute maximum ratings[5]Spec ID#

Parameter

SID1

Min

Typ

Max

Unit Details / Conditions

VDD_ABS

Analog or digital supply relative –0.5
to VSS (VSSD = VSSA)

–

4

V

SID2

VCCD_ABS

Direct digital core voltage input –0.5
relative to VSSD

–

1.2

V

SID3

VGPIO_ABS

GPIO voltage; VDDD or VDDA

–0.5

–

VDD + 0.5

V

SID4

IGPIO_ABS

Current per GPIO

–25

–

25

mA

SID5

IGPIO_injection

GPIO injection current per pin

–0.5

–

0.5

mA

SID3A

ESD_HBM

Electrostatic discharge Human
Body Model

2200

–

–

V

SID3B

ESD_HBM_ANTElectrostatic discharge Human
Body Model; Antenna Pin

500

–

–

V

SID4A

ESD_CDM

Electrostatic discharge Charged
Device Model

500

–

–

V

SID4B

ESD_
CDM_ANTElectrostatic discharge Charged
Device Model; Antenna Pin

200

–

–

V

RF pinSID4C

ESD_CDM_X

Electrostatic discharge Charged
Device Model; XI, XO pins

200

–

–

V

XI, XO Pins

SID5A

LU

Pin current for latchup-free
operation

–100

–

100

mA

6.2

Description

RF pinDevice-level specifications

Table 14 provides detailed specifications of CPU current. Table 12 summarizes these specifications, for rapid
review of CPU currents under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+
is 100 MHz. IMO and FLL are used to generate the CPU clocks; FLL is not used when the CPU clock frequency is
8 MHz.
Table 12CPU current specifications summary

Condition
Range
LP Mode, VDDD = 3.3 V, VCCD = 1.1 V, with buck regulator
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
Across CPUs clock ranges: 8–150/100 MHz;
Dhrystone with flash cache enabled
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
Minimum regulator current mode Across CM4/CM0+ CPU active/sleep modes
ULP Mode, VDDD = 3.3 V, VCCD = 0.9 V, with buck regulator

Typ Range

Max Range

0.9–6.9 mA
0.8–3.8 mA
0.7–1.5 mA
0.7–1.3 mA
0.6–0.7 mA

1.5–8.6 mA
1.3–4.5 mA
1.3–2.2 mA
1.3–2 mA
1.1–1.1 mA

Note
5. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above
normal operating conditions, the device may not operate to specification.
Datasheet

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PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 12CPU current specifications summary

Condition
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
CM0+ sleep, CM4 off
Minimum regulator current mode
Deep Sleep
Hibernate

Range

Typ Range
0.65–1.6 mA
0.51–0.91 mA
0.42–0.76 mA
0.41–0.62 mA
0.39–0.54 mA
7–9 µA
300–800 nA

Across CPUs clock ranges: 8 – 50/25 MHz;
Dhrystone with flash cache enabled
Across CM4/CM0+ CPU active/sleep modes
Across SRAM retention
Across VDDD

Max Range
0.8–2.2mA
0.72–1.25 mA
0.65–1.1 mA
0.6–0.9 mA
0.6–0.76 mA-

8
CM4 Active, CM0+ Sleep 1/2 CM47

CM4 Active, CM0+ Sleep same as CM4

IDDD, mA

6

CM0+ Active, CM4 Sleep

5
4
3

2
1
0
0

25

50

75

100

125

150

CPU Clock, MHz

Figure 18

Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode[6]6.2.1Power supplies

Table 13Power supply DC specifications

Spec ID# Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

SID6

VDDD

Internal regulator and Port 1
GPIO supply

1.7

–

3.6

V

–

SID7

VDDA

Analog power supply voltage.
Shorted to VDDIOA on PCB.

1.7

–

3.6

V

Internally unregulated
supplySID7A

VDDIO1

GPIO supply for ports 5 to 8 whenpresent

1.7

–

3.6

V

Must be ≥ VDDA if the
CAPSENSE™ (CSD) block isused in the application

SID7B

VDDIO0GPIO supply for ports 11 to 13
when present

1.7

–

3.6

V

–

SID7E

VDDIO0

Supply for eFuse programming

2.38

2.5

2.62

V

Note
6. CM4 Active, CM0+ Sleep 1/2 CM4 trace values are higher because above 100 MHz, the PLL must be used instead of the FLL.

Datasheet54002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 13Power supply DC specifications (continued)

Spec ID# Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

SID7D

VDDIOA

GPIO supply for ports 9 and 10
when present. Must beconnected to VDDA on PCB.

1.7

–

3.6

V

–

SID7F

VDDUSB

Supply for port 14 (USB or GPIO)
when present

1.7

–

3.6

V

Min. supply is 2.85 V for USB

SID6B

VBACKUP

Backup power and GPIO Port 0
supply when present

1.7

–

3.6

V

Min. is 1.4 V when VDDD isremoved.

SID8

VCCD1

Output voltage (for core logic
bypass)

–

1.1

–

V

System LP mode

SID9

VCCD2

Output voltage (for core logic
bypass)

–

0.9

–

V

ULP mode. Valid for –20 to85 °C.

SID10

CEFC

External regulator voltage (VCCD)
bypass

3.8

4.7

5.6

µF X5R ceramic or better;
Value for 0.8 to 1.2 V.

SID11

CEXC

Power supply decoupling
capacitor

–

10

–

µF X5R ceramic or better

6.2.2

CPU current and transition times

Table 14CPU current and transition times

Spec ID# Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

VDDD = 3.3 V, Buck ON, Max
at 60 °CLP RANGE POWER SPECIFICATIONS (for VCCD = 1.1 V with Buck and LDO)
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)

SIDF1

SIDF2

IDD1

IDD2

Execute from Flash; CM4
Active 50 MHz,
CM0+ Sleep 25 MHz.
With IMO & FLL. While(1).

Execute from Flash; CM4
Active 8 MHz, CM0+ Sleep 8MHz. With IMO. While(1).

–

2.3

3.2

mA

–

3.1

3.6

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

5.7

6.5

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

0.9

1.5

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.2

1.6

mA

–

2.8

3.5

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

6.9

8.6

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

10.9

13.7

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

13.7

15.5

mA

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Execute with Cache Enabled

SIDC1

Datasheet

IDD3

Execute from Cache; CM4
Active 150 MHz, CM0+ Sleep 75
MHz.
IMO & PLL. Dhrystone.

55

VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

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PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 14CPU current and transition times (continued)

Spec ID# Parameter

SIDC2

SIDC3

SIDC4

IDD4

IDD5

IDD6

Description
Execute from Cache;
CM4 Active 100 MHz, CM0+
Sleep 100 MHz. IMO & FLL.
Dhrystone.

Execute from Cache; CM4
Active 50 MHz, CM0+ Sleep 25
MHz. IMO & FLL. Dhrystone

Execute from Cache; CM4
Active 8 MHz, CM0+ Sleep 8MHz. IMO. Dhrystone.

Min

Typ

Max

Unit

Details / Conditions

–

4.8

5.8

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

7.4

8.4

mA

–

11.3

12

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

2.4

3.4

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

3.7

4.1

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

6.3

7.2

mA

–

0.9

1.5

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.3

1.8

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

3

3.8

mA

VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

2.4

3.3

mA

VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

3.2

3.7

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

5.6

6.3

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

0.8

1.5

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.1

1.6

mA

–

2.60

3.4

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

3.8

4.5

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

5.9

6.5

mA

–

9

9.7

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

0.8

1.3

mA

–

1.20

1.7

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

2.60

3.4

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

VDDD = 1.8 V, Buck ON, Max
at 60 °C

VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)

SIDF3

SIDF4

IDD7

IDD8

Execute from Flash;
CM4 Off, CM0+ Active 50 MHz.
With IMO & FLL. While (1).

Execute from Flash;
CM4 Off, CM0+ Active 8 MHz.
With IMO. While (1).

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Execute with Cache Enabled

SIDC5

SIDC6

Datasheet

IDD9

IDD10

Execute from Cache;
CM4 Off, CM0+ Active 100 MHz.
With IMO & FLL. Dhrystone.

Execute from Cache;
CM4 Off, CM0+ Active 8 MHz.
With IMO. Dhrystone.

56

VDDD = 1.8 V, Buck ON, Max
at 60 °C

VDDD = 3.3 V, Buck ON, Max
at 60 °C

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PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 14CPU current and transition times (continued)

Spec ID# Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

–

1.5

2.2

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

2.2

2.7

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

4

4.6

mA

VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

1.2

1.9

mA

VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

1.7

2.2

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

3.4

4.3

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

0.7

1.3

mA

–

1

1.5

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

2.4

3.3

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

1.3

2

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

1.9

2.4

mA

–

3.80

4.6

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

0.7

1.3

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

1

1.5

mA

–

2.4

3.3

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

0.9

1.5

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.2

1.7

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

2.8

3.5

mA

–

0.9

1.5

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.3

1.8

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

2.9

3.7

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

Cortex M4. Sleep Mode

SIDS1

SIDS2

SIDS3

IDD11

IDD12

IDD13

CM4 Sleep 100 MHz;
CM0+ Sleep 25 MHz. With IMO& FLL.

CM4 Sleep 50 MHz;
CM0+ Sleep 25 MHz. With IMO& FLL.

CM4 Sleep 8 MHz, CM0+ Sleep
8 MHz.
With IMO.

VDDD = 3.3 V, Buck ON, Max
at 60 °C

Cortex M0+. Sleep Mode

SIDS4

SIDS5

IDD14

IDD15

CM4 Off, CM0+ Sleep 50 MHz.
With IMO & FLL.

CM4 Off, CM0+ Sleep 8 MHz.
With IMO.

VDDD = 1.8 V, Buck ON, Max
at 60 °C

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Cortex M4. Minimum Regulator Current ModeSIDLPA1

SIDLPA2

IDD16

IDD17

Execute from Flash; CM4 LPA 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While (1).

Execute from Cache; CM4 LPA
8 MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.

VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

Cortex M0+. Minimum Regulator Current Mode
Datasheet57

002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 14CPU current and transition times (continued)

Spec ID# Parameter

SIDLPA3

SIDLPA4

IDD18

IDD19

Description
Execute from Flash;
CM4 Off, CM0+ Active 8 MHz.
With IMO. While (1).

Execute from Cache; CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.

Min

Typ

Max

Unit

Details / Conditions

–

0.8

1.4

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

1.1

1.6

mA

–

2.7

3.6

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

–

0.8

1.4

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.2

1.7

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

2.7

3.6

mA

VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

0.7

1.1

mA

VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

1

1.5

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

2.4

3.3

mA VDDD = 1.8 to 3.3 V, LDO, Max
at 85 °C

–

0.6

1.1

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

0.9

1.5

mA

–

2.4

3.3

V
= 1.8 to 3.3 V, LDO, Max
mA atDDD
85 °C

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Cortex M4. Minimum Regulator Current ModeSIDLPS1

IDD20

CM4 Sleep 8 MHz, CM0+ Sleep
8 MHz.
With IMO.

Cortex M0+. Minimum Regulator Current ModeSIDLPS3

IDD22

CM4 Off, CM0+ Sleep 8 MHz.
With IMO.

VDDD = 1.8 V, Buck ON, Max
at 60 °CULP RANGE POWER SPECIFICATIONS (for VCCD = 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C.
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
SIDF5

SIDF6

VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

1.7

2.2

mA

IDD3

Execute from Flash; CM4
Active 50 MHz, CM0+ Sleep 25
MHz.
With IMO & FLL. While(1).

–

2.1

2.4

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

0.56

0.8

IDD4

Execute from Flash; CM4
Active 8 MHz, CM0+ Sleep 8MHz. With IMO. While (1)mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

0.75

1

mA

–

1.6

2.2

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

2.4

2.7

mA

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Execute with Cache Enabled
SIDC8

Datasheet

IDD10

Execute from Cache; CM4
Active 50 MHz, CM0+ Sleep 25
MHz.
With IMO & FLL. Dhrystone.

58

VDDD = 1.8 V, Buck ON, Max
at 60 °C

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 14CPU current and transition times (continued)

Spec ID# Parameter
SIDC9

Description

Min

Typ

Max

Unit

Execute from Cache; CM4
Active 8 MHz, CM0+ Sleep 8
MHz.
With IMO. Dhrystone.

–

0.65

0.8

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

0.8

1.1

mA

–

1

1.4

IDD16

Execute from Flash; CM4 Off,
CM0+ Active 25 MHz. With IMO& FLL. Write(1).

V= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.34

1.6

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

0.54

0.75

mA

IDD17

Execute from Flash; CM4 Off,
CM0+ Active 8 MHz. With IMO.
While(1).

–

0.73

1

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

0.91

1.25

IDD18

Execute from Cache; CM4 Off,
CM0+ Active 25 MHz. With IMO& FLL. Dhrystone.

V= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.34

1.6

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

0.51

0.72

mA

IDD19

Execute from Cache; CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.

–

0.73

0.95

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

0.76

1.1

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

1.1

1.4

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

0.42

0.65

mA

–

0.59

0.8

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

0.62

0.9

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

0.88

1.1

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

0.41

0.6

mA

–

0.58

0.8

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

IDD11

Details / Conditions

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
SIDF7

SIDF8

VDDD = 3.3 V, Buck ON, Max
at 60 °C

Execute with Cache Enabled
SIDC10

SIDC11

VDDD = 3.3 V, Buck ON, Max
at 60 °C

Cortex M4. Sleep Mode
SIDS7

SIDS8

IDD21

CM4 Sleep 50 MHz, CM0+ Sleep
25 MHz. With IMO & FLL.

IDD22

CM4 Sleep 8 MHz, CM0+ Sleep
8 MHz.
With IMO.

VDDD = 3.3 V, Buck ON, Max
at 60 °C

Cortex M0+. Sleep Mode
SIDS9

SIDS10IDD23

CM4 Off, CM0+ Sleep 25 MHz.
With IMO & FLL.

IDD24

CM4 Off, CM0+ Sleep 8 MHz.
With IMO.

VDDD = 3.3 V, Buck ON, Max
at 60 °C

Cortex M4. Minimum Regulator Current Mode

Datasheet

59002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 14CPU current and transition times (continued)

Spec ID# Parameter

Description

Min

Typ

Max

Unit

–

0.52

0.75

IDD25

Execute from Flash. CM4
Active 8 MHz, CM0+ Sleep 8MHz. With IMO. While(1).

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

0.76

1

mA

–

0.54

0.76

IDD26

Execute from Cache. CM4
Active 8 MHz, CM0+ Sleep 8MHz. With IMO. Dhrystone.

V= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

0.78

1

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

0.51

0.75

IDD27

Execute from Flash. CM4 Off,
CM0+ Active 8 MHz. With IMO.
While (1).

V= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

0.75

1

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

0.48

0.7

mA

IDD28

Execute from Cache. CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.

–

0.7

0.95

V
= 1.8 V, Buck ON, Max
mA atDDD
60 °C

–

0.4

0.6

V
= 3.3 V, Buck ON, Max
mA atDDD
60 °C

–

0.57

0.8

mA VDDD = 1.8 V, Buck ON, Max
at 60 °C

–

0.39

0.6

mA VDDD = 3.3 V, Buck ON, Max
at 60 °C

–

0.56

0.8

mA

With internal buck enabled
and 64K SRAM retention

–

7

–

µA Max value is at 85 °C

SIDDS1_B IDD33A_B

With internal buck enabled
and 64K SRAM retention

–

7

–

µA Max value is at 60 °C

SIDDS2

With internal buck enabled
and 256K SRAM retention

–

9

–

µA Max value is at 85 °C

With internal buck enabled
and 256K SRAM retention

–

9

–

µA Max value is at 60 °C

SIDLPA5

SIDLPA6

Details / Conditions

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Cortex M0+. Minimum Regulator Current ModeSIDLPA7SIDLPA8VDDD = 3.3 V, Buck ON, Max
at 60 °C

Cortex M4. Minimum Regulator Current ModeSIDLPS5

IDD29

CM4 Sleep 8 MHz, CM0 Sleep 8
MHz.
With IMO.

Cortex M0+. Minimum Regulator Current ModeSIDLPS7

IDD31

CM4 Off, CM0+ Sleep 8 MHz.
With IMO.

VDDD = 1.8 V, Buck ON, Max
at 60 °C

Deep Sleep Mode
SIDDS1

IDD33AIDD33B

SIDDS2_B IDD33B_B
Hibernate Mode
SIDHIB1

IDD34

VDDD = 1.8 V

–

300

–

nA No clocks running

SIDHIB2

IDD34AVDDD = 3.3 V

–

800

–

nA No clocks runningPower Mode Transition Times
SID12

TLPACT_ACT

Minimum regulator current toLP transition time

–

–

35

µs

Including PLL lock time

SID13

TDS_LPACT

Deep Sleep to LP transition
time

–

–

25

µs

Guaranteed by design

Datasheet

60

002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 14CPU current and transition times (continued)

Spec ID# Parameter
SID14

THIB_ACT

Description

Min

Typ

Max

Unit

Details / Conditions

–

500

–

µs

Including PLL lock time

Min

Typ

Max

Unit

Hibernate to LP transition
time

6.2.3

XRES

Table 15

XRES DC Specifications

Spec
ID#

Parameter

SID17

TXRES_IDD

IDD when XRES asserted

–

300

–

nA

VDDD = 1.8 V

SID17ATXRES_IDD_1 IDD when XRES asserted

–

800

–

nA

VDDD = 3.3 V

SID77

VIH

Input voltage high threshold

0.7 ×
VDD

–

–

V

CMOS Input

SID78

VIL

Input voltage low threshold

–

–

0.3 ×
VDD

V

CMOS Input

SID80

CIN

Input capacitance

–

3

–

pF

–

SID81

VHYSXRES

Input voltage hysteresis

–

100

–

mV –

SID82

IDIODE

Current through protection
diode to VDD/VSS

–

–

100

µA

Min

Typ

Max

Unit

Details / Conditions

Table 16

Description

Details / Conditions–

XRES AC Specifications

Spec ID# Parameter

Description

SID15

TXRES_ACTTime from XRES release toCortex-M0+ executing application code

–

750

–

µs

Not minimum regulator
current mode; Cortex-M0+
executing at 50 MHz

SID16

TXRES_PWXRES Pulse width

5

–

–

µs

–

Min

Typ

Max

Unit Details / Conditions

6.2.4

GPIO

Table 17

GPIO DC Specifications

Spec ID#

Parameter

Description

SID57

VIH

Input voltage high threshold 0.7 × VDD

–

–

V

CMOS Input

SID57A

IIHS

Input current when Pad >VDDIO for OVT inputs

–

–

10

µA

Per I2C Spec

SID58

VIL

Input voltage low threshold

–

–

0.3 ×
VDD

V

CMOS Input

SID241VIH

LVTTL input, VDD < 2.7 V

0.7 × VDD

–

–

V

–

SID242VIL

LVTTL input, VDD < 2.7 V

–

–

0.3 ×
VDD

V

–

SID243VIH

LVTTL input, VDD ≥ 2.7 V

2.0

–

–

V

–

SID244VIL

LVTTL input, VDD ≥ 2.7 V

–

–

0.8

V

–

SID59

VOH

Output voltage high level

VDD – 0.5––

V

IOH = 8 mA

SID62AVOL

Output voltage low level

–

–

0.4

V

IOL = 8 mA

SID63

RPULLUP

Pull-up resistor

3.5

5.6

8.5

kΩ

–

Datasheet61002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 17
Spec ID#

GPIO DC Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit Details / Conditions

SID64

RPULLDOWN

Pull-down resistor

3.5

5.6

8.5

kΩ

–

SID65

IIL

Input leakage current(absolute value)

–

–

2

nA

25 °C, VDD = 3.0 V

SID65A

IIL_CTBM

Input leakage on CTBm
input pins

–

–

4

nA

–

SID66

CIN

Input Capacitance

–

–

5

pF

–

SID67

VHYSTTL

Input hysteresis LVTTL VDD >
2.7 V

100

0

–

mV

–

SID68

VHYSCMOS

Input hysteresis CMOS

0.05 × VDD

–

–

mV

–

SID69

IDIODE

Current through protection
diode to VDD/VSS

–

–

100

µA

–

SID69AITOT_GPIO

Maximum total source orsink Chip Current

–

–

200

mA

–

Min

Typ

Max

Unit Details / Conditions

Table 18

GPIO AC Specifications

Spec ID#

Parameter

SID70

TRISEF

Rise time in Fast Strong
Mode. 10% to 90% of VDD

–

–

2.5

ns

Cload = 15 pF, 8 mA
drive strength

SID71

TFALLF

Fall time in Fast Strong Mode.
10% to 90% of VDD

–

–

2.5

ns

Cload = 15 pF, 8 mA
drive strength

SID72

TRISES_1

Rise time in Slow Strong
Mode. 10% to 90% of VDD

52

–

142

ns

Cload = 15 pF, 8 mA
drive strength,
VDD  2.7 V

SID72A

TRISES_2

Rise time in Slow Strong
Mode. 10% to 90% of VDD

48

–

102

ns

Cload = 15 pF, 8 mA
drive strength, 2.7 V< VDD  3.6 V

SID73

TFALLS_1

Fall time in Slow Strong
Mode. 10% to 90% of VDD

44

–

211

ns

Cload = 15 pF, 8 mA
drive strength,
VDD 2.7 V

SID73ATFALLS_2

Fall time in Slow Strong
Mode. 10% to 90% of VDD

42

–

93

ns

Cload = 15 pF, 8 mA
drive strength,
2.7 V < VDD  3.6 V

SID73GTFALL_I2C

Fall time (30% to 70% of VDD) 20 × VDDIO/ 5.5
in Slow Strong mode

–

250

ns

Cload = 10 pF to400 pF, 8-mA drive
strength

SID74

FGPIOUT1

GPIO Fout. Fast Strong mode.

–

–

100

MHz 90/10%, 15-pF load,
60/40 duty cycle

SID75

FGPIOUT2GPIO Fout; Slow Strong
mode.

–

–

16.7

MHz 90/10%, 15-pF load,
60/40 duty cycle

SID76

FGPIOUT3

GPIO Fout; Fast Strong mode.

–

–

7

MHz 90/10%, 25-pF load,
60/40 duty cycle

SID245FGPIOUT4GPIO Fout; Slow Strong
mode.

–

–

3.5

MHz 90/10%, 25-pF load,
60/40 duty cycle

SID246FGPIOIN

GPIO input operating
frequency;1.71 V  VDD 3.6 V

–

–

100

MHz 90/10% VIO

Datasheet

Description

62002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.3
6.3.1

Analog peripherals
Opamp

Table 19

Opamp specifications

Spec ID#

Parameter

SID278SID279SID280

IOUT_MAX_HI
IOUT_MAX_MID
IOUT_MAX_LO

Description
Opamp block current. No
load.
Power = HiPower = MedPower = Lo
Load = 50 pF, 0.1 mA.
VDDA  2.7 V
Power = HiPower = MedPower = Lo
VDDA  2.7 V, 500 mV fromrail
Power = HiPower = MedPower = Lo
VDDA = 1.71 V, 500 mV fromrail
Power = HiPower = MedPower = Lo

SID281

VIN

Input voltage range

SID282VCM

IDD
SID269SID270
SID271

IDD_HI
IDD_MED
IDD_LOW
GBW

SID272
SID273
SID274

GBW_HI
GBW_MED
GBW_LOIOUT_MAX

SID275
SID276
SID277

IOUT_MAX_HI
IOUT_MAX_MID
IOUT_MAX_LO
IOUT

Min

Typ

Max

–

–

–

–
–
–

1300
450
250

1500
600
350

–

–

–

6
3
1

–
–
–

–
–
–

–

–

–

10
10
–

–
–
5

–
–
–

–

–

–

4
4
–

–
–
2

–
–
–

0

–

0

–

–

–

VDDA –
0.2
VDDA –
1.5–
VDDA –
0.5
VDDA –
0.2
VDDA –
0.2
VDDA –
0.2

VOUT

Input common mode
voltage
VDDA ≥ 2.7 V

SID283

VOUT_1

Power = Hi, Iload = 10 mA

0.5–

SID284

VOUT_2

Power = Hi, Iload = 1 mA

0.2–

SID285

VOUT_3

Power = Med, Iload = 1 mA

0.2–

SID286

VOUT_4

Power = Lo, Iload = 0.1 mA

0.2–

SID288

VOS_TR

Offset voltage

–1

±0.5

1

SID288A
SID288B

VOS_TR
VOS_TR

Offset voltage
Offset voltage

–
–

±1
±2

–
–

SID290

VOS_DR_TR

Offset voltage drift

–10

±3

10

SID290A
SID290B

VOS_DR_TR
VOS_DR_TR

Offset voltage drift
Offset voltage drift

–
–

±10
±10

–
–

Datasheet

63

Unit

Details / Conditions
–

µA
µA
µA

–
–
–
–

MHz –
MHz –
MHz –
–
mA
mA
mA

–
–
–
–

mA
mA
mA

–
–
–
Charge pump ON

V
V

V
V
V
V

Charge pump OFF,VDDA  2.7 V
–
–
–
–
–

Power = Hi, 0.2 V <VOUT < (VDDA - 0.2 V)
mV Power = MedmV Power = LoPower = Hi, 0.2 V <µV/°C
VOUT < (VDDA - 0.2 V)µV/°C Power = MedµV/°C Power = LomV

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 19

Opamp specifications (continued)

Spec ID#

Parameter

SID291CMRR

SID292

PSRR

SID65A

IIL_CTBM

Description
DC common mode
rejection ratio
Power supply rejection
ratio at 1 kHz, 10-mV ripple
Input leakage on CTBm
input pins

Min

Typ

Max

Unit

Details / Conditions

67

80

–

dB

VDDA ≥ 2.7 V

70

85

–

dB

VDDA ≥ 2.7 V

–

–

4

nA

–

–

100

–

µVrms

–

180

–

–

70

–

–

38

–

–

–

125

Noise
SID293VN1

SID294VN2

SID295VN3SID296VN4SID297CLOAD

SID298SID299SID300
SID301
SID302
SID303

SLEW_RATE

Input-referred, 1 Hz –1 GHz, power = Hi
Input-referred, 1 kHz,power = Hi
Input-referred, 10 kHz,power = Hi
Input-referred, 100 kHz,power = Hi
Stable up to max. load.
Performance specs at 50
pF.

Output slew rate

4

From disable to enable, no
external RC dominating
Comparator mode; 50-mV
COMP_MODE overdrive, Trise = Tfall(approx.)
TPD1
Response time; power = Hi
Response time; power =
TPD2
Med
TPD3
Response time; power = Lo
VHYST_OP
Hysteresis
T_OP_WAKE

Deep Sleep Mode

Mode 2 is lowest current
range. Mode 1 has higher
GBW.

SID_DS_1
SID_DS_2
SID_DS_3
SID_DS_4
SID_DS_5
SID_DS_6
SID_DS_7

Mode 1, High current
Mode 1, Medium current
Mode 1, Low current
Mode 2, High current
Mode 2, Medium current
Mode 2, Low current
Mode 1, High current

Datasheet

IDD_HI_M1
IDD_MED_M1
IDD_LOW_M1
IDD_HI_M2
IDD_MED_M2
IDD_LOW_M2
GBW_HI_M1

64

–

–

25

–

–

–

nV/rtH –znV/rtH –znV/rtH –
z
–
pF

V/µs

µs

Cload = 50 pF,
Power = Hi, VDDA  2.7
V
Refer to Figure 19
and Figure 20.
–
–

–

–

150

–

ns

–

400

–

ns

–
–

2000
10

–
–

ns
mV

–
–
–
–
–
–
–

1300

1500
600
350
–
–
–
–

460
230
120
60
15
4

–

–
–

–
–
Deep Sleep mode
operation:
VDDA ≥ 2.7 V.
VIN is 0.2 to VDDA –1.5 VµA Typ at 25 °CµA Typ at 25 °CµA Typ at 25 °CµA 25 °C
µA 25 °C
µA 25 °C
MHz 25 °C

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 19
Spec ID#
SID_DS_8
SID_DS_9

Opamp specifications (continued)
Parameter
Description
GBW_MED_M
Mode 1, Medium current
1
GBW_LOW_M
Mode 1, Low current
1

SID_DS_10 GBW_HI_M2

Mode 2, High current

Min

Typ

Max

Unit

–

2

–

MHz 25 °C

–

0.5

–

MHz 25 °C

–

0.5

–

SID_DS_11

GBW_MED_M
Mode 2, Medium current
2

–

0.2

–

SID_DS_12

GBW_LOW_M
Mode 2, Low current
2

–

0.1

–

SID_DS_13 VOS_HI_M1

Mode 1, High current

–

5

–

SID_DS_14 VOS_MED_M1

Mode 1, Medium current

–

5

–

SID_DS_15 VOS_LOW_M1

Mode 1, Low current

–

5

–

SID_DS_16 VOS_HI_M2

Mode 2, High current

–

5

–

SID_DS_17 VOS_MED_M2

Mode 2, Medium current

–

5

–

SID_DS_18 VOS_LOW_M2

Mode 2, Low current

–

5

–

SID_DS_19 IOUT_HI_M1

Mode 1, High current

–

10

–

SID_DS_20 IOUT_MED_M1

Mode 1, Medium current

–

10

–

SID_DS_21 IOUT_LOW_M1

Mode 1, Low current

–

4

–

SID_DS_22 IOUT_HI_M2

Mode 2, High current

–

1

–

SID_DS_23 IOUT_MED_M2

Mode 2, Medium current

–

1

–

SID_DS_24 IOUT_LOW_M2

Mode 2, Low current

–

0.5

–

Datasheet

65

Details / Conditions

20-pF load, no DC
MHz load 0.2 V to VDDA –1.5 V
20-pF load, no DC
MHz load 0.2 V to VDDA –1.5 V
20-pF load, no DC
MHz load 0.2 V to VDDA –1.5 V
25 °C, 0.2 V to VDDA –mV
1.5 V
25 °C, 0.2 V to VDDA –mV
1.5 V
25 °C, 0.2 V to VDDA –mV
1.5 V
25 °C, 0.2 V to VDDA –mV
1.5 V
25 °C, 0.2 V to VDDA –mV
1.5 V
25 °C, 0.2 V to VDDA –mV
1.5 V
Output is 0.5 V tomA
VDDA – 0.5 V
Output is 0.5 V tomA
VDDA – 0.5 V
Output is 0.5 V tomA
VDDA – 0.5 V
Output is 0.5 V tomA
VDDA – 0.5 V
Output is 0.5 V tomA
VDDA – 0.5 V
Output is 0.5 V tomA
VDDA – 0.5 V

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

1.4

Input and Output Signals, V

1.2
1
0.8
0.6

Output, Power = Hi
0.2
0
-0.25

Figure 19

Input

0.4

Output, Power = Med
0

0.25
0.5
Time, µs

0.75

1Opamp Step Response, Rising

Input and Output Signals, V

1.4

Datasheet

Output, Power = Hi

1

Output, Power = Med

0.8
0.6
0.4
0.2
0
-0.25

Figure 20

Input

1.2

0

0.25
0.5
Time. µs

0.75

1Opamp Step Response, Falling66002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.3.2

Low-Power (LP) Comparator

Table 20

LP Comparator DC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit Details / Conditions

SID84

VOFFSET1

Input offset voltage for
COMP1. Normal power
mode.

–10

–

10

mV

SID85AVOFFSET2

Input offset voltage.
Low-power mode.

–25

±12

25

mV

SID85BVOFFSET3

Input offset voltage. Ultra
low-power mode.

–25

±12

25

mV

SID86

VHYST1

Hysteresis when enabled inNormal mode

–

–

60

mV

SID86A

VHYST2Hysteresis when enabled in
Low-power mode

–

–

80

mV

SID87

VICM1

Input common mode
voltage in Normal mode

0–

VDDIO1 – 0.1

V

SID247VICM2

Input common mode
voltage in Low power mode

0–

VDDIO1 – 0.1

V

SID247A

VICM3Input common mode
voltage in Ultra low power
mode

0

–

VDDIO1 – 0.1

V

SID88

CMRR

Common mode rejection
ratio in Normal power
mode

50

–

–

dB

SID89

ICMP1

Block Current, Normal
mode

–

–

150

µA

SID248ICMP2Block Current, Low power
mode

–

–

10

µA

SID259ICMP3Block Current in Ultra
low-power mode

–

0.3

0.85

µA

SID90

ZCMP

DC Input impedance ofcomparator

35

–

–

MΩ

Min

Typ

Max

–

–

100

Unit Details / Conditions
–
ns

–

–

1000

ns

–

–

20

µs

–

–

10

µs

–

–

50

µs

Table 21
Spec ID#

–
–
–
–
–
–
–
–
–
–
–
–

LP Comparator AC Specifications
Parameter

SID91

TRESP1

SID258TRESP2

SID92

TRESP3

SID92E

T_CMP_EN1

SID92F

T_CMP_EN2

Datasheet

COMP0 offset is±25 mV

Description
Response time, Normalmode, 100 mV overdrive
Response time, Low powermode, 100 mV overdrive
Response time, Ultra-low
power mode, 100 mV
overdrive
Time from Enabling tooperation
Time from Enabling tooperation

67––
Normal and
Low-power modes
Ultra low-powermode

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

Table 22

Temperature sensor specifications

Spec ID#
SID93
Table 23
Spec
ID#
SID93R

Parameter
TSENSACC

Description
Temperature sensor
accuracy

Min

Typ

Max

Unit

–5

±1

5

°C

Description

Min

Typ

Max

Unit

–

1.188

1.2

1.212

V

–40 to +85 °C

Internal reference specification
Parameter
VREFBG

6.3.3

SAR ADC

Table 24

12-bit SAR ADC DC Specifications

Spec
ID#

Details / Conditions

Parameter

Details / Conditions–

Description

Min

Typ

Max

Unit

Details / Conditions

SID94

A_RES

SAR ADC Resolution

–

–

12

bits

–

SID95

A_CHNLS_S

Number of channels single-ended

–

–

16

–

8 full speed.

SID96

A-CHNKS_D

Number of channels - differential

–

–

8

–

Diff inputs use neighboring I/O

SID97

A-MONO

Monotonicity

–

–

–

–

Yes

SID98

A_GAINERR

Gain error

–

–

±0.2

%

With external reference.

SID99

A_OFFSET

Input offset voltage

–

–

2

mV

Measured with 1-V
reference

SID100 A_ISAR_1

Current consumption at 1
Msps

–

–

1

mA

At 1 Msps. External
Bypass Cap.

SID100
A_ISAR_2
A

Current consumption at 1
Msps. Reference = VDD

–

–

1.25

mA

At 1 Msps. External
Bypass Cap.

SID101 A_VINS

Input voltage range single-ended

VSS

–

VDDA

V

SID102 A_VIND

Input voltage range - differential

VSS

–

VDDA

V

SID103 A_INRES

Input resistance

–

–

2.2

kΩ

–

SID104 A_INCAP

Input capacitance

–

–

10

pF

–

Min

Typ

Max

Unit

Table 25––

12-bit SAR ADC AC Specifications

Spec ID# Parameter

Description

Details / Conditions

12-bit SAR ADC AC Specifications
SID106

A_PSRR

Power supply rejection ratio

70

–

–

dB

–

SID107

A_CMRR

Common mode rejection ratio

66

–

–

dB

Measured at 1 V.

One Megasample per second mode:
SID108

A_SAMP_1

Sample rate with externalreference bypass cap.

–

–

1

Msps –

SID108A

A_SAMP_2

Sample rate with no bypass
cap; Reference = VDD

–

–

250

ksps –

Datasheet

68002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 25

12-bit SAR ADC AC Specifications (continued)

Spec ID# Parameter

Description

Min

Typ

Max

Unit

SID108B A_SAMP_3

Sample rate with no bypass
cap. Internal reference.

–

–

100

ksps –

SID109

A_SINAD

Signal-to-noise and Distortion
ratio (SINAD). VDDA = 2.7 to
3.6 V, 1 Msps.

64

–

–

dB

Fin = 10 kHz

SID111A

A_INL

Integral Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps

–2

–

2

LSB

Measured with internal
VREF = 1.2 V and bypass
cap.

SID111B A_INL

Integral Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps

–4

–

4

LSB

Measured with external
VREF ≥ 1 V and VIN
common mode < 2 * Vref.

SID112A

A_DNL

Differential Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps

–1

–

1.4

LSB

Measured with internal
VREF = 1.2 V and bypass
cap.

SID112B A_DNL

Differential Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps

–1

–

1.7

LSB

Measured with external
VREF ≥ 1 V and VIN
common mode < 2 * Vref.

SID113

Total harmonic distortion.
VDDA = 2.7 to 3.6 V, 1 Msps.

–

–

–65

dB

Fin = 10 kHz

Datasheet

A_THD

69

Details / Conditions

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.3.4

DAC

Table 26

12-bit DAC DC Specifications

Spec
ID#

Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

SID108D DAC_RES

DAC resolution

–

–

12

bits

–

SID111D DAC_INL

Integral non-linearity

–4

–

4

LSB

–

SID112D DAC_DNL

Differential non-linearity

–2

–

2

LSB

Monotonic to 11 bits.

SID99D

Output Voltage zero offset
error

–2

–

1

mV

For 000 (hex)

SID103D DAC_OUT_RE DAC Output Resistance
S

–

15

–

kΩ

–

SID100D DAC_IDD

DAC Current

–

–

125

µA

–

SID101D DAC_QIDDDAC Current when DAC
stopped

–

–

1

µA

–

Min

Typ

Max

Unit

Details / Conditions

DAC_OFFSET

Table 27SpecID#

12-bit DAC AC Specifications
Parameter

Description

SID109D DAC_CONVDAC Settling time

–

–

2

µs

Driving through CTBm
buffer; 25-pF load

SID110D DAC_Wakeup

Time from Enabling to readyfor conversion

–

–

10

µs

–

6.3.5

CSD

Table 28

Capacitive Sigma-Delta (CSD) Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit Details / Conditions

Max allowed ripple on
power supply, DC to 10 MHz

–

–

±50

mV VDDA > 2 V (with ripple),
25 °C TA,
Sensitivity = 0.1 pF

SYS.PER#16 VDD_RIPPLE_1.8

Max allowed ripple on
power supply, DC to 10 MHz

–

–

±25

mV VDDA > 1.75 V (withripple), 25 ° C TA,
Parasitic Capacitance(CP) < 20 pF, Sensitivity≥ 0.4 pF

SID.CSD.BLK ICSD

Maximum block current

4500

µA –

SID.CSD#15

Voltage reference for CSD
and Comparator

0.6

VDDA –
0.6

V

VDDA – VREF ≥ 0.6 V

SID.CSD#15A VREF_EXT

External Voltage reference
for CSD and Comparator

0.6

VDDA –
0.6

V

VDDA – VREF ≥ 0.6 V

SID.CSD#16

IDAC1IDD

IDAC1 (7-bits) block current

–

–

1900

µA –

SID.CSD#17

IDAC2IDDIDAC2 (7-bits) block current

–

–

1900

µA –

SID308

VCSD

Voltage range of operation

1.7

–

3.6

V

1.71 to 3.6 V

SID308A

VCOMPIDAC

Voltage compliance rangeof IDAC

0.6–

VDDA –
0.6

V

VDDA – VREF ≥ 0.6 V

CSD V2 Specifications
SYS.PER#3

Datasheet

VDD_RIPPLE

VREF

70

1.2

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 28
Spec ID#

Capacitive Sigma-Delta (CSD) Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit Details / Conditions

SID309IDAC1DNL

DNL

–1

–

1

LSB –

SID310

IDAC1INL

INL

–3

–

3

LSB If VDDA < 2 V then for
LSB of 2.4 µA or less

SID311

IDAC2DNL

DNL

–1

–

1

LSB –

SID312

IDAC2INL

INL

–3

–

3

LSB If VDDA < 2 V then for
LSB of 2.4 µA or less

SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization
SID313_1A

SNRC_1SRSS Reference. IMO + FLL
Clock Source. 0.1-pF sensitivity

5

–

–

Ratio 9.5-pF max. capacitance

SID313_1B

SNRC_2SRSS Reference. IMO + FLL
Clock Source. 0.3-pF sensitivity

5

–

–

Ratio 31-pF max. capacitance

SID313_1C

SNRC_3SRSS Reference. IMO + FLL
Clock Source. 0.6-pF sensitivity

5

–

–

Ratio 61-pF max. capacitance

SID313_2A

SNRC_4

PASS Reference. IMO + FLL
Clock Source. 0.1-pF sensitivity

5

–

–

Ratio 12-pF max. capacitance

SID313_2B

SNRC_5PASS Reference. IMO + FLL
Clock Source. 0.3-pF sensitivity

5

–

–

Ratio 47-pF max. capacitance

SID313_2C

SNRC_6PASS Reference. IMO + FLL
Clock Source. 0.6-pF sensitivity

5

–

–

Ratio 86-pF max. capacitance

SID313_3A

SNRC_7PASS Reference. IMO + PLL
Clock Source. 0.1-pF sensitivity

5

–

–

Ratio 27-pF max. capacitance

SID313_3B

SNRC_8PASS Reference. IMO + PLL
Clock Source. 0.3-pF sensitivity

5

–

–

Ratio 86-pF max. capacitance

SID313_3C

SNRC_9PASS Reference. IMO + PLL
Clock Source. 0.6-pF sensitivity

5

–

–

Ratio 168-pF max. capacitance

SID314

IDAC1CRT1

Output current of IDAC1 (7bits) in low range

4.2

5.7

µA LSB = 37.5-nA typ

SID314A

IDAC1CRT2

Output current of IDAC1(7bits) in medium range

33.7

45.6

µA LSB = 300-nA typ.

SID314B

IDAC1CRT3

Output current of IDAC1(7bits) in high range

270

365

µA LSB = 2.4-µA typ.

SID314C

IDAC1CRT12

Output current of IDAC1 (7bits) in low range, 2X mode

8

11.4

µA LSB = 37.5-nA typ.
2X output stage

SID314D

IDAC1CRT22

Output current of IDAC1(7bits) in medium range, 2X
mode

67

91

µA LSB = 300-nA typ.
2X output stage

Datasheet71002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 28
Spec ID#

Capacitive Sigma-Delta (CSD) Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit Details / Conditions

SID314E

IDAC1CRT32

Output current of IDAC1(7540bits) in high range, 2X mode.
VDDA > 2 V

730µA LSB = 2.4-µA typ.
2X output stage

SID315

IDAC2CRT1

Output current of IDAC2 (7bits) in low range

4.2

5.7

µA LSB = 37.5-nA typ.

SID315A

IDAC2CRT2

Output current of IDAC2 (7bits) in medium range

33.7

45.6

µA LSB = 300-nA typ.

SID315B

IDAC2CRT3

Output current of IDAC2 (7bits) in high range

270

365

µA LSB = 2.4-µA typ.

SID315C

IDAC2CRT12

Output current of IDAC2 (7bits) in low range, 2X mode

8

11.4

µA LSB = 37.5-nA typ.
2X output stage

SID315D

IDAC2CRT22

Output current of IDAC2(7bits) in medium range, 2X
mode

67

91

µA LSB = 300-nA typ.
2X output stage

SID315E

IDAC2CRT32

Output current of IDAC2(7540bits) in high range, 2X mode.
VDDA > 2 V

730µA LSB = 2.4-µA typ.
2X output stage

SID315F

IDAC3CRT13

Output current of IDAC in
8-bit mode in low range

8

11.4

µA LSB = 37.5-nA typ.

SID315G

IDAC3CRT23

Output current of IDAC in
8-bit mode in medium
range

67

91

µA LSB = 300-nA typ.

SID315H

IDAC3CRT33

Output current of IDAC in
8-bit mode in high range.
VDDA > 2V

540

730

µA LSB = 2.4-µA typ.

SID320IDACOFFSETAll zeroes input

–

–

1

LSB Polarity set by Sourceor Sink

SID321IDACGAIN

Full-scale error less offset

–

–

±15

%

SID322

IDACMISMATCH1

Mismatch between IDAC1
and IDAC2 in Low mode

–

–

9.2

LSB LSB = 37.5-nA typ.

SID322A

IDACMISMATCH2

Mismatch between IDAC1
and IDAC2 in Medium mode

–

–

6

LSB LSB = 300-nA typ.

SID322B

IDACMISMATCH3

Mismatch between IDAC1
and IDAC2 in High mode

–

–

5.8

LSB LSB = 2.4-µA typ.

SID323IDACSET8

Settling time to 0.5 LSB for
8-bit IDAC

–

–

10

µs

Full-scale transition.
No external load.

SID324IDACSET7

Settling time to 0.5 LSB for
7-bit IDAC

–

–

10

µs

Full-scale transition.
No external load.

SID325CMOD

External modulator
capacitor.

–

2.2

–

nF 5-V rating, X7R or NP0
cap.

Datasheet72

LSB = 2.4-µA typ.

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

Table 29

CSD ADC Specifications

Spec ID#

Parameter

Description

Min

Typ Max

Unit

Details / Conditions

CSDv2 ADC Specifications
SIDA94

A_RES

Resolution

–

–

10

bits Auto-zeroing isrequired every millisecond

SID95

A_CHNLS_S

Number of channels - single
ended

–

–

–

16

–

SIDA97

A-MONO

Monotonicity

–

–

Yes

–

VREF mode

SIDA98

A_GAINERR_VREF Gain error

–

0.6

–

%

Reference Source:
SRSS(VREF = 1.20 V, VDDA <2.2 V),(VREF = 1.6 V, 2.2 V <VDDA< 2.7 V), (VREF =2.13 V, VDDA > 2.7 V)

SIDA98A

A_GAINERR_VDDA

Gain error

–

0.2

–

%

Reference Source:
SRSS(VREF = 1.20 V, VDDA
< 2.2V),(VREF = 1.6 V,
2.2 V < VDDA < 2.7 V),(VREF = 2.13 V,
VDDA > 2.7 V)

SIDA99A_OFFSET_VREF

Input offset voltage

–

0.5

–

LSB After ADC calibration,
Ref. Src = SRSS, (VREF =1.20 V,
VDDA < 2.2 V), (VREF =1.6 V, 2.2 V < VDDA <2.7 V),(VREF = 2.13 V, VDDA >2.7 V)

SIDA99A

A_OFFSET_VDDA Input offset voltage

–

0.5

–

LSB After ADC calibration,
Ref.
Src = SRSS, (VREF =1.20 V, VDDA < 2.2 V),(VREF = 1.6 V, 2.2 V <VDDA < 2.7 V),(VREF = 2.13 V, VDDA >2.7 V)

SIDA100

A_ISAR_VREF

Current consumption

–

0.3

–

mA

CSD ADC Block current

SIDA100A A_ISAR_VDDA

Current consumption

–

0.3

–

mA

CSD ADC Block current

SIDA101

Input voltage range - single
ended

VSSA

–

VREF

V

(VREF = 1.20 V, VDDA <2.2 V),(VREF = 1.6 V,
2.2 V < VDDA < 2.7 V),(VREF = 2.13 V, VDDA > 2.7
V)

Datasheet

A_VINS_VREF

73002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 29

CSD ADC Specifications (continued)

Spec ID#

Parameter

Description

Min

Typ Max

Unit

Details / Conditions

SIDA101A A_VINS_VDDA

Input voltage range - single
ended

VSSA

–

VDDA

V

(VREF = 1.20 V, VDDA <2.2 V),(VREF = 1.6 V,
2.2 V < VDDA < 2.7 V),(VREF = 2.13 V, VDDA > 2.7
V)

SIDA103

A_INRES

Input charging resistance

–

15

–

kΩ

–

SIDA104

A_INCAP

Input capacitance

–

41

–

pF

–

SIDA106

A_PSRR

Power supply rejection
ratio (DC)

–

60

–

dB

–

SIDA107

A_TACQ

Sample acquisition time

–

10

–

µs

Measured with 50-Ωsource impedance. 10µs is default software
driver acquisition time
setting. Settling towithin 0.05%.

SIDA108

A_CONV8

Conversion time for 8-bit
resolution at conversion
rate = Fhclk/(2"(N+2)).
Clock frequency = 50 MHz.

–

25

–

µs

Does not include acquisition time.

SIDA108A A_CONV10

Conversion time for 10-bit
resolution at conversion
rate = Fhclk/(2"(N+2)).
Clock frequency = 50 MHz.

–

60

–

µs

Does not include acquisition time.

SIDA109

A_SND_VRE

Signal-to-noise andDistortion ratio (SINAD)

–

57

–

dB

Measured with 50-Ωsource impedance

SIDA109A A_SND_VDDA

Signal-to-noise andDistortion ratio (SINAD)

–

52

–

dB

Measured with 50-Ωsource impedance

SIDA111

A_INL_VREF

Integral non-linearity.
11.6 ksps––

2

LSB Measured with 50-Ωsource impedance

SIDA111A A_INL_VDDA

Integral non-linearity.
11.6 ksps––

2

LSB Measured with 50-Ωsource impedance

SIDA112

A_DNL_VREF

Differential non-linearity.
11.6 ksps––

1

LSB Measured with 50-Ωsource impedance

SIDA112A A_DNL_VDDA

Differential non- linearity.
11.6 ksps––

1

LSB Measured with 50-Ωsource impedanceDatasheet

74002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.4

Digital peripherals

Table 30

Timer/Counter/PWM (TCPWM) Specifications

Spec ID#

Parameter

Description

Min Typ Max Unit

Details / Conditions

SID.TCPWM.1 ITCPWM1Block current
consumption at 8 MHz

–

–

70

µA All modes (TCPWM)

SID.TCPWM.2 ITCPWM2Block current
consumption at 24 MHz

–

–

180

µA All modes (TCPWM)

SID.TCPWM.2
ITCPWM3A

Block current
consumption at 50 MHz

–

–

270

µA All modes (TCPWM)

SID.TCPWM.2
ITCPWM4B

Block current
consumption at 100 MHz

–

–

540

µA All modes (TCPWM)

Operating frequency

–

–

100

MHz

Fc max = Fcpu
Maximum = 100 MHz

ns

Trigger Events can be Stop,
Start, Reload, Count,
Capture, or Kill dependingon which mode of operationis selected. Fc is counter
operating frequency.

SID.TCPWM.3

TCPWMFREQ

Input Trigger Pulse Width
2 / Fcfor all Trigger Events

SID.TCPWM.4 TPWMENEXT––

SID.TCPWM.5 TPWMEXT

Output Trigger Pulse
widths

1.5 /
Fc

–

–

ns

Minimum possible width ofOverflow, Underflow, andCC (Counter equals
Compare value) trigger
outputs

SID.TCPWM.5
TCRESAResolution of Counter

1 / Fc––ns

Minimum time between
successive counts

SID.TCPWM.5
PWMRESB

PWM Resolution

1 / Fc––ns

Minimum pulse width of
PWM Output

SID.TCPWM.5
QRESC

Quadrature inputs
resolution–

ns

Minimum pulse width
between Quadrature phase
inputs. Delays from pins
should be similar.

Min TypMax

Unit

Details / Conditions

Table 31
Spec ID#

2 / Fc–Serial Communication Block (SCB) Specifications
Parameter

Description

Fixed I2C DC Specifications
SID149II2C1Block current
consumption at 100 kHz

–

–

30

µA –

SID150II2C2

Block current
consumption at 400 kHz

–

–

80

µA –

SID151II2C3Block current
consumption at 1 Mbps

–

–

180

µA –

SID152

II2C4

I2C enabled in Deep Sleep
mode

–

–

1.7

µA At 60 °C

Bit Rate

–

–

1

Mbp –
s

Fixed I2C AC Specifications
SID153

Datasheet

FI2C1

75

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 31
Spec ID#

Serial Communication Block (SCB) Specifications (continued)
Parameter

Description

Min TypMax

Unit

Details / Conditions

Fixed UART DC Specifications
SID160IUART1

Block current
consumption at 100 kbps

–

–

30

µA –

SID161IUART2Block current
consumption at
1000 kbps

–

–

180

µA –

–

–

3

Mbp ULP Mode
s

–

–

8

LP ModeFixed UART AC Specifications
SID162A

FUART1

SID162B

FUART2

Bit Rate

Fixed SPI DC Specifications
SID163ISPI1Block current
consumption at 1 Mbps

–

–

220

µA –

SID164ISPI2Block current
consumption at 4 Mbps

–

–

340

µA –

SID165ISPI3Block current
consumption at 8 Mbps

–

–

360

µA –

SID165A

ISP14Block current
consumption at 25 Mbps

–

–

800

µA –

Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID166FSPISPI Operating Frequency
Master and Externally
Clocked Slave

–

–

25

MHz 14-MHz max for ULP (0.9 V)
mode

SID166A

FSPI_ICSPI Slave Internally
Clocked––15

MHz 5-MHz max for ULP (0.9 V)
mode

SID166B

FSPI_EXTSPI Operating Frequency
Master (FSCB is SPI Clock)––

FSCB/4 MHz FSCB max is 100 MHz in LP
mode, 25 MHz max in ULP
mode

Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID167TDMO

MOSI Valid after SClockdriving edge

–

–

12

ns 20-ns max for ULP (0.9 V)
mode

SID168TDSIMISO Valid before SClockcapturing edge

5

–

–

ns Full clock, late MISO
sampling

SID169THMO

MOSI data hold time

0

–

–

ns Referred to Slave capturingedge

SID169A

TSSELMSCK1SSEL Valid to first SCK
Valid edge

18

–

–

ns Referred to Master clockedge

SID169B

TSSELMSCK2SSEL Hold after last SCK
Valid edge

18

–

–

ns Referred to Master clockedge

Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID170TDMI

MOSI Valid before Sclock
Capturing edge

5

–

–

ns –

SID171A

TDSO_EXTMISO Valid after Sclock
driving edge in Ext. Clk.
mode

–

–

20

ns 35-ns max. for ULP (0.9 V)
mode

Datasheet

76002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 31

Serial Communication Block (SCB) Specifications (continued)

Spec ID#

Parameter

Description

Min TypMax

Unit

Details / Conditions

SID171TDSO

MISO Valid after Sclock
driving edge in Internally
Clk. Mode––

TDSO_EXT+
3 × Tscb

ns Tscb is Serial Comm. Block
clock period.

SID171B

TDSO

MISO Valid after Sclock
driving edge in Internally
Clk. Mode with Medianfilter enabled.

––

TDSO_EXT+
4 × Tscb

ns Tscb is Serial Comm. Block
clock period.

SID172THSO

Previous MISO data hold
time

5

–

–

ns –

SID172ATSSELSCK1SSEL Valid to first SCK
Valid edge

65

–

–

ns –

SID172B

TSSELSCK2SSEL Hold after Last SCK
Valid edge

65

–

–

ns

6.4.1

LCD Specifications

Table 32

LCD Direct Drive DC Specifications

Spec
ID#

Parameter

Description
Operating current in low-powermode
LCD capacitance persegment/common driver

SID154ILCDLOW

SID155

CLCDCAP

SID156LCDOFFSET Long-term segment offset

SID157ILCDOP1

SID158ILCDOP2

Table 33
SpecID#
SID159

Datasheet

Min Typ Max Unit

PWM Mode current.
3.3-V bias. 8-MHz IMO. 25 °C.
PWM Mode current.
3.3-V bias. 8-MHz IMO. 25 °C.

–

5

–

µA

–

500 5000

pF

–

20

–

mV

–

0.6

–

mA

–

0.5

–

Details / Conditions
16 × 4 small segment display
at 50 Hz––32 × 4 segments
50 Hz
32 × 4 segments
mA
50 Hz

LCD Direct Drive AC Specifications
Parameter
FLCD

Description
LCD frame rate

77

Min

Typ

Max

Unit

Details / Conditions

10

50

150

Hz

–

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.5

Memory

6.5.1

Flash

Table 34

Flash DC Specifications[7]

Spec
ID#

Parameter

SID173A IPE
Table 35

Description
Erase and program current

Min

Typ

Max

Unit

Details / Conditions

–

–

6

mA

–

Typ

Max

Unit

Details / Conditions

–
–
–
–
–
–

16
11
5
11
11
11

ms
ms
ms
ms
ms
ms

Row = 512 bytes–––
512 rows per sector
8 rows per subsector

–

51

ms

–

–

2.6

–

15

–

–

secon
–
ds
secon
–
ds
cycles –––years –––

years –––

years –

–
–

–
–

–
–

Flash AC Specifications

Spec
Parameter
Description
Min
ID#
SID174 TROWWRITE
Row write time (erase & program)–
SID175 TROWERASE
Row erase time–
SID176 TROWPROGRAM Row program time after erase–
SID178 TBULKERASE
Bulk erase time (1024 KB)–
SID179 TSECTORERASE Sector erase time (256 KB)–
SID178S TSSERIAE
Subsector erase time–
Subsector write time; 1 erase plus
SID179S TSSWRITE–
8 program times
Sector write time; 1 erase plus
SID180S TSWRITE–
512 program times
SID180TDEVPROG

Total device write time

SID181FEND

SID182

FRET1

Flash Endurance
100 kFlash Retention. TA  25 °C, 100 k
10
P/E cycles
Flash Retention. TA  85 °C, 10 k
10P/E cycles
Flash Retention. TA 55 °C, 20 k
20P/E cycles
Number of Wait states at 100 MHz
3
Number of Wait states at 50 MHz
2

SID182A FRET2
SID182B FRET3
SID256
SID257

TWS100
TWS50

–

Note
7. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will beinterrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states andprivilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
Datasheet78002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6

System resources

6.6.1

Power-on-reset

Table 36

Power-on-reset (POR) with brown-out detect (BOD) DC specifications

Spec
ID#

Parameter

SID190 VFALLPPOR
SID192 VFALLDPSLP
Table 37

Description

Min

BOD trip voltage in system LP
1.54
and ULP modes.
BOD trip voltage in system Deep
1.54
Sleep mode.

Typ

Max

Unit

–

–

V

–

–

V

Details / Conditions
Reset guaranteed for VDDD
levels below 1.54 V

POR with BOD AC Specifications

Spec ID# Parameter

Description

Min

Typ

Max

Unit

SID192A VDDRAMP

Maximum power supply ramp
rate (any supply)

–

–

100

mV/µ
System LP modes

SID194A VDDRAMP_DS

Maximum power supply ramp
rate (any supply) in system Deep
Sleep mode

–

–

10

mV/µ BOD operations guaranteed

Min

Typ

Max

Unit

1.18
1.38
1.57
1.76
1.95
2.05
2.15
2.24
2.34
2.44
2.53
2.63
2.73
2.82
2.92
3.02
–

1.23
1.43
1.63
1.83
2.03
2.13
2.23
2.33
2.43
2.53
2.63
2.73
2.83
2.93
3.03
3.13
5

1.27
1.47
1.68
1.89
2.1
2.2
2.3
2.41
2.51
2.61
2.72
2.82
2.92
3.03
3.13
3.23
15

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA

Min

Typ

Max

Unit

–

–

170

ns

6.6.2

Voltage monitors

Table 38

Voltage monitors DC Specifications

Spec
Parameter
Description
ID#
SID195R VHVD0
SID195 VHVDI1
SID196 VHVDI2
SID197 VHVDI3
SID198 VHVDI4
SID199 VHVDI5
SID200 VHVDI6
SID201 VHVDI7
SID202 VHVDI8
SID203 VHVDI9
SID204 VHVDI10
SID205 VHVDI11
SID206 VHVDI12
SID207 VHVDI13
SID208 VHVDI14
SID209 VHVDI15
SID211 LVI_IDD
Block current
Table 39
SpecID#

Details / Conditions
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–

Voltage Monitors AC Specification
Parameter

SID212 TMONTRIP
Datasheet

Details / Conditions

Description
Voltage monitor trip time
79

Details / Conditions–
002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6.3

SWD and Trace interface

Table 40

SWD and Trace specifications

Spec ID#

Parameter

SID214

F_SWDCLK2

SID214L

F_SWDCLK2L

SID215

Description

Min

Typ

Max

Unit

Details / Conditions

1.7 V  VDDD  3.6 V

–

–

25

MHz

LP mode.
VCCD = 1.1 V

1.7 V  VDDD 3.6 V

–

–

12

MHz

ULP mode.
VCCD = 0.9 V

T_SWDI_SETUP T = 1/f SWDCLK

0.25 * T

–

–

ns

–

SID216

T_SWDI_HOLD T = 1/f SWDCLK

0.25 * T

–

–

ns

–

SID217

T_SWDO_VALID T = 1/f SWDCLK––

0.5 * T

ns–

SID217A T_SWDO_HOLD T = 1/f SWDCLK

1

–

–

ns

–

SID214T

Trace Data setup/hold
F_TRCLK_LP1 With
times of 2/1 ns respectively

–

–

75

MHz

LP Mode.
VDD = 1.1 V

SID215T

F_TRCLK_LP2 With Trace Data setup/holdtimes of 3/2 ns respectively

–

–

70

MHz

LP Mode.
VDD = 1.1 V

SID216T

With Trace Data setup/hold
F_TRCLK_ULP times of 3/2 ns respectively

–

–

25

MHz

ULP Mode.
VDD = 0.9 V

6.6.4

Internal Main Oscillator

Table 41

IMO DC Specifications
Min

Typ

Max

Unit

–

9

15

µA

Description

Min

Typ

Max

Unit

SID223 FIMOTOL1Frequency variation centeredon 8 MHz

–

–

±2

%

SID227 TJITR

Cycle-to-Cycle and Period
jitter

–

±250

–

ps

Description

Min

Typ

Max

Unit

ILO operating current at 32
kHz

–

0.3

0.7

µA

Min

Typ

Max

Unit

Details / Conditions

Spec
ID#

Parameter

SID218 IIMO1
Table 42
Spec
ID#

Description
IMO operating current at 8
MHz

Parameter

Internal Low-Speed Oscillator

Table 43

ILO DC Specification
Parameter

SID231 IILO2Table 44
Spec
ID#

–

IMO AC Specifications

6.6.5
Spec
ID#

Details /Conditions

Details /Conditions––

Details /Conditions–

ILO AC Specifications
Parameter

Description

SID234 TSTARTILO1

ILO startup time

–

–

7

µs

Startup time to 95%
of final frequency

SID236 TLIODUTYILO Duty cycle

45

50

55

%

–

SID237 FILOTRIM1

ILO frequency

28.8

32

36.1

kHz

Factory trimmedDatasheet

80002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6.6

Crystal oscillator

Table 45

ECO Specifications

Spec
ID#

Parameter

Description

Min

Typ

Max

Unit

Details /Conditions

–

800

1600

µA

Max = 35 MHz,
Typ = 16 MHz

16

–

35

MHz –

MHz ECO DC Specifications
SID316 IDD_MHz

Block operating current with
Cload up to 18 pF

MHz ECO AC Specifications
SID317 F_MHz

Crystal frequency range

kHz ECO DC Specification
SID318 IDD_kHz

Block operating current with
32-kHz crystal

–

0.38

1

µA

SID321
ESR32KE

Equivalent Series Resistance

–

80

–

kΩ

SID322
PD32K
E

Drive level

–

–

1

µW

–
–
–

kHz ECO AC Specification
SID319 F_kHz

32-kHz frequency

–

32.76
8

–

kHz

SID320 Ton_kHz

Startup time

–

–

500

ms

SID320FTOL32K
E

Frequency tolerance

–

50

250

ppm

Description

Min

Typ

Max

Unit

SID305 EXTCLKFREQ

External Clock input Frequency

0

–

100

MHz –

SID306 EXTCLKDUTY

Duty cycle; Measured at VDD/2

45

–

55

%

Min

Typ

Max

Unit

6.6.7

External clock

Table 46

External Clock Specifications

Spec
ID#

Parameter

6.6.8

PLL

Table 47

PLL Specifications

Spec
ID#

Parameter

Description–––

Details /Conditions–

Details /Conditions

SID304P PLL_IN

Input frequency to PLL block

4

–

64

MHz

SID305P PLL_LOCKTime to achieve PLL Lock

–

16

35

µs

SID306P PLL_OUT

Output frequency from PLL Block 10.62
5

–

150

MHz –

SID307P PLL_IDD

PLL Current

–

0.55

1.1

mA

Typ at 100 MHz out.

SID308P PLL_JTR

Period Jitter

–

–

150

ps

100-MHz output
frequency

Datasheet81–002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6.9

Clock source switching time

Table 48

Clock source switching time specifications

Spec
ID#

Parameter

SID262 TCLKSWITCH

Min

Typ

Max

Clock switching from clk1 to clk2 inclock periods[8]––4 clk1–
period
+3
s
clk2

Min

Typ

Max

Unit

Details / Conditions

0.001

–

100

MHz

Lower limit allows lockto USB SOF signal(1 kHz). Upper limit isfor External input.

6.6.10FLL

Table 49

Frequency Locked Loop (FLL) Specifications
Description

Unit

Details /Conditions

Description

Spec ID#

Parameter

SID450

FLL_RANGESID451

FLL_OUT_DIV Output frequency range.
2
VCCD = 1.1 V

24.00

–

100.00MHz

Output range of FLL
divided-by-2 output

SID451A

FLL_OUT_DIV Output frequency range.
2
VCCD = 0.9 V

24.00

–

50.00

MHz

Output range of FLL
divided-by-2 output

SID452

FLL_DUTY_DIV2

Divided-by-2 output; High or 47.00
Low

–

53.00

%

–

SID454

FLL_WAKEUP Time from stable input clock
to 1% of final value on deep
sleep wakeup

–

–

7.50

µs

With IMO input, lessthan 10 °C change intemperature while in
Deep Sleep, and Fout ≥50 MHz.

SID455FLL_JITTER

–

–

35.00

ps

50 ps at 48 MHz, 35 ps
at 100 MHz

SID456

FLL_CURRENT CCO + Logic current––

5.50 µA/MHz –Description

Min

Typ

Max

Unit Details / Conditions

Input frequency range.

Period jitter (1 sigma at 100
MHz)

6.6.11

UDB

Table 50

UDB AC Specifications

Spec ID#

Parameter

Data Path Performance
SID249FMAX-TIMER

Max frequency of 16-bit timer
in a UDB pair

–

–

100

MHz

SID250

FMAX-ADDER

Max frequency of 16-bit adderin a UDB pair

–

–

100

MHz

SID251

FMAX_CRC

Max frequency of 16-bit
CRC/PRS in a UDB pair

–

–

100

MHz

Max frequency of 2-pass PLD
function in a UDB pair

–

–

100

MHz

–
–
–

PLD Performance in UDB
SID252

FMAX_PLD–

Note
8. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 4) then clk1 is the IMO and clk2 is the FLL.
Datasheet82002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 50Spec ID#

UDB AC Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit Details / Conditions

Prop. delay for clock in to data
out

–

5

–

ns

Clock to Output Performance
SID253

TCLK_OUT_UDB1–

UDB Port Adapter Specifications
Conditions: 10-pF load, 3-V VDDIO and VDDD
SID263

TLCLKDOLCLK to Output delay

–

–

11

ns

LCLK is a selected
clock; for more information see the TRM

SID264

TDINLCLK

Input setup time to LCLK rising
edge

–

–

7

ns

–

SID265

TDINLCLKHLD

Input hold time from LCLK
rising edge

5

–

–

ns

–

SID266TLCLKHIZLCLK to Output tristated

–

–

28

ns

–

SID267

TFLCLKLCLK frequency

–

–

33

MHz –

SID268TLCLKDUTYLCLK duty cycle (percentage
high)

40%

–

60%

%

Datasheet83–002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6.12

USB

Table 51

USB Specifications (USB requires LP Mode 1.1-V Internal Supply)
Description

Min

Typ

Max

Unit

Details /Conditions

SID322U Vusb_3.3

Device supply for USB
operation

3.15

–

3.6

V

USB Configured

SID323U Vusb_3

Device supply for USB
operation (functional
operation only)

2.85

–

3.6

V

USB Configured

SID325U Iusb_config

Block supply current in Active
mode

–

8

–

mA

VDDD = 3.3 V

SID328Iusb_suspend

Block supply current insuspend mode

–

0.5

–

mA

VDDD = 3.3 V, Device
connected

SID329Iusb_suspend

Block supply current insuspend mode

–

0.3

–

mA

VDDD = 3.3 V, Device
disconnected

SID330U USB_Drive_Res USB driver impedance

28

–

44

Ω

Series resistors areon chip

USB pull-down resistors in
Host mode

14.25

–

24.8

kΩ

–

Idle mode range

900

–

1575

Ω

Bus idle

Active mode

1425

–

3090

Ω

Upstream device
transmittingSpec ID#

Parameter

USB Block Specifications

SID331U USB_Pulldown
SID332U

USB_Pullup_Idle

SID333U USB_Pullup

6.6.13QSPI

Table 52QSPI Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details /Conditions

SMIF QSPI Specifications. All specs with 15-pF load.
SID390Q

Fsmifclock

SMIF QSPI output clock frequency

–

–

80

MHz

LP mode (1.1 V)

SID390QU

Fsmifclocku

SMIF QSPI output clock frequency

–

–

50

MHz

ULP mode (0.9 V).
Guaranteed by
Char.

SID397Q

Idd_qspi

Block current in LP mode (1.1 V)

–

–

1900

µA

LP mode (1.1 V)

SID398Q

Idd_qspi_u

Block current in ULP mode (0.9 V)

–

–

590

µA

ULP mode (0.9 V)

SID391Q

Tsetup

Input data set-up time with respect
to clock capturing edge

4.5

–

–

ns

–

SID392Q

TdataholdInput data hold time with respect toclock capturing edge

0

–

–

ns

–

SID393Q

Output data valid time with respect
Tdataoutvalid to clock falling edge

–

–

3.7

ns

7.5-ns max for ULP
mode (0.9 V)

SID394Q

Tholdtime

Output data hold time with respect
to clock rising edge

3

–

–

ns

–

SID395Q

Tseloutvalid

Output Select valid time withrespect to clock rising edge

–

–

7.5

ns

15-ns max for ULP
mode (0.9 V)

SID396Q

Tselouthold

Output Select hold time withrespect to clock rising edge

0.5*
Tsclk

–

–

ns

Tsclk = Fsmifclk
cycle time

Datasheet

84002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6.14

Audio Subsystem

Table 53

Audio Subsystem Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

PDM Specifications
SID400P

PDM_IDD1PDM Active current, Stereo
operation, 1-MHz clock

–

175

–

µA

16-bit audio at 16 ksps

SID401

PDM_IDD2PDM Active current, Stereo
operation, 3-MHz clock

–

600

–

µA

24-bit audio at 48 ksps

SID402[9]PDM_JITTERRMS Jitter in PDM clock

–200

–

200

ps

–

[9]

PDM_CLKPDM Clock speed

0.384

–

3.072

MHz

–

[9]

PDM_BLK_CLKPDM Block input clock

1.024

–

49.152MHz–PDM_SETUP

Data input set-up time to
PDM_CLK edge

10

–

–

ns

–

SID403C[9] PDM_HOLD

Data input hold time to PDM_CLK
edge

10

–

–

ns

–

SID404[9]PDM_OUT

Audio sample rate

8

–

48

ksps

–

SID405[9]PDM_WL

Word Length

16

–

24

bits

–

SID406[9]PDM_SNR

Signal-to-Noise Ratio(A-weighted)

–

100

–

dB

PDM input, 20 Hz to
20 kHz BW

SID407[9]PDM_DR

Dynamic Range (A-weighted)

–

100

–

dB

20 Hz to 20 kHz BW,–60 dB FS

SID408[9]PDM_FR

Frequency Response

–0.2

–

0.2

dB

DC to 0.45f. DC
Blocking filter off.

SID409[9]PDM_SB

Stop Band

–

0.566

–

f

–

SID410[9]PDM_SBA

Stop Band Attenuation

–

60

–

dB

–
PDM to PCM,
1.5 dB/step

SID403

SID403A

SID403B[9]SID411[9]PDM_GAIN

Adjustable Gain

–12

–

10.5

dB

SID412[9]PDM_ST

Startup time

–

48

–

WS (Word Select) cycles

I2S Specifications. The same for LP and ULP modes unless stated otherwise.
SID415

I2S_IDD

Block current

–

400

–

µA

SID413

I2S_WORD

Length of I2S Word

8

–

32

bits

–

SID414

I2S_WS

Word Clock frequency in LP mode

–

–

192

kHz

12.288-MHz bit clockwith 32-bit word

SID414M

I2S_WS_U

Word Clock frequency in ULP
mode

–

–

48

kHz

3.072-MHz bit clockwith 32-bit word

SID414A

I2S_WS_TDM

Word Clock frequency in TDM
mode for LP

–

–

48

kHz

Eight 32-bit channels

SID414X

I2S_WS_TDM_U

Word Clock frequency in TDM
mode for ULP

–

–

12

kHz

Eight 32-bit channels

I2S Slave Mode
SID430

TS_WS

WS Setup Time to the Following
Rising Edge of SCK for LP Mode

5

–

–

ns

–

SID430U

TS_WS

WS Setup Time to the Following
Rising Edge of SCK for ULP Mode

11

–

–

ns

–

SID430A

TH_WS

WS Hold Time to the Following
Edge of SCKTMCLK_SOC[10] +
5

–

–

ns

–

SID432

TD_SDO–
Delay Time of TX_SDO Transition(TMCLK_SOC + 25
from Edge of TX_SCK for LP mode)–

TMCLK_SOC + 2
5ns

Associated clock edge
depends on selected
polarityNotes
9. Guaranteed by design, not production tested.
10.TMCLK_SOC is the internal I2S master clock period.
Datasheet

85002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 53
Spec ID#

Audio Subsystem Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

SID432U

TD_SDO

Delay Time of TX_SDO Transition
from Edge of TX_SCK for ULP
mode–(TMCLK_SOC +70)–

TMCLK_SOC + 70ns

Associated clock edge
depends on selected
polarity

SID433

TS_SDI

RX_SDI Setup Time to the
Following Edge of RX_SCK in Lp
Mode

5

–

–

ns

–

SID433U

TS_SDI

RX_SDI Setup Time to the
Following Edge of RX_SCK in ULP
mode

11

–

–

ns

–

SID434

TH_SDI

RX_SDI Hold Time to the Rising
Edge of RX_SCKTMCLK_SOC + 5

–

–

ns

–

SID435

TSCKCY

TX/RX_SCK Bit Clock Duty Cycle

45

–

55

%

–

I2S Master Mode
SID437

TD_WS

WS Transition Delay from Falling
Edge of SCK in LP mode

–10

–

20

ns

–

SID437U

TD_WS_U

WS Transition Delay from Falling
Edge of SCK in ULP mode

–10

–

40

ns

–

SID438

TD_SDOSDO Transition Delay from Falling
Edge of SCK in LP mode

–10

–

20

ns

–

SID438U

TD_SDOSDO Transition Delay from Falling
Edge of SCK in ULP mode

–10

–

40

ns

–

SID439TS_SDISDI Setup Time to the Associated
Edge of SCK

5

–

–

ns

Associated clock edge
depends on selected
polarity

SID440

TH_SDISDI Hold Time to the Associated
Edge of SCK

SID443

TSCKCY

SID445TMCLK_SOC + 5

–

–

ns

T is TX/RX_SCK Bit
Clock period.
Associated clock edge
depends on selected
polarity.

SCK Bit Clock Duty Cycle

45

–

55

%

–

FMCLK_SOC

MCLK_SOC Frequency in LP mode

1.024

–

98.304

MHz FMCLK_SOC =8 * Bit-clock

SID445UFMCLK_SOC_U

MCLK_SOC Frequency in ULP
mode

1.024

–

24.576MHzFMCLK_SOC_U =8 * Bit-clock

SID446TMCLKCYMCLK_SOC Duty Cycle

45

–

55

%

–

SID447

TJITTERMCLK_SOC Input Jitter

–100

–

100

ps

–

Datasheet86002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.6.15

Smart I/O

Table 54

Smart I/O specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details / Conditions

SID420

SMIO_BYP

Smart I/O Bypass delay

–

–

2

ns

–

SID421

SMIO_LUT

Smart I/O LUT prop delay

–

8

–

ns

–

Min

Typ

Max

Unit

Details / Conditions

6.6.16

Precision ILO (PILO)

Table 55

PILO specifications

Spec ID#

Parameter

Description

SID 430R IPILO

Operating current

–

1.2

4

µA

–

SID431PILO nominal frequency

–

32768

–

Hz

T = 25 °C

–500

–

500

ppm –

F_PILO

SID432R ACC_PILO

PILO accuracy with periodic
calibration

6.6.17JTAG Boundary Scan

Table 56

JTAG Boundary Scan

Spec ID#

DescripMin Typ Max
tion

Parameter

Units

JTAG Boundary Scan Parameters
JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:

SID468TCKLOW

TCK LOW

52

–

–

ns

–

SID469TCKHIGHTCK HIGH

10

–

–

ns

–

SID470

TCK_TDOTCK falling edge to output valid

–

40

ns

–

SID471

TSU_TCK

Input valid to TCK rising edge

12

–

–

ns

–

SID472

TCk_THD

Input hold time to TCK rising edge

10

–

–

ns

–

SID473

TCK_TDOVTCK falling edge to output valid(High-Z to Active).

40

–

–

ns

–

SID474

TCK_TDOZ

TCK falling edge to output valid(Active to High-Z).

40

–

–

ns

–

JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:
SID468ATCKLOW

TCK low

102

–

–

ns

–

SID469A

TCKHIGH

TCK high

20

–

–

ns

–

SID470A

TCK_TDOTCK falling edge to output valid

–

80

ns

–

SID471A

TSU_TCK

Input valid to TCK rising edge

22

–

–

ns

–

SID472A

TCk_THD

Input hold time to TCK rising edge

20

–

–

ns

–

SID473A

TCK_TDOVTCK falling edge to output valid(high-Z to active).

80

–

–

ns

–

SID474A

TCK_TDOZ

TCK falling edge to output valid(active to high-Z).

80

–

–

ns

–

Datasheet

87002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

6.7

Bluetooth® LE

Table 57

Bluetooth® LE Subsystem Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit Details / Conditions

RF Receiver Specifications (1 Mbps)
SID317R RXS,IDLE

RX Sensitivity with Ideal
Transmitter

–

–95

–

dBm

Across RF Operating
Frequency Range

SID317RR RXS,IDLE

RX Sensitivity with Ideal
Transmitter

–

–93

–

255-byte packet
dBm length, acrossFrequency Range

SID318R RXS,DIRTY

RX Sensitivity with Dirty
Transmitter

–

–92

–

RF-PHY SpecifidBm cation(RCV-LE/CA/01/C)

SID319R PRXMAX

Maximum received signal
strength at < 0.1% PER

–

0

–

RF-PHY SpecifidBm cation(RCV-LE/CA/06/C)

SID320R CI1

Co-channel interference,
Wanted Signal at –67 dBm
and Interferer at FRX

–

9

21

dB

RF-PHY Specification(RCV-LE/CA/03/C)

SID321R CI2

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at FRX ± 1 MHz

–

3

15

dB

RF-PHY Specification(RCV-LE/CA/03/C)

SID322R CI3

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at FRX ± 2 MHz

–

–26

–17

dB

RF-PHY Specification(RCV-LE/CA/03/C)

SID323R CI4

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at ≥ FRX ± 3
MHz

–

–33

–27

dB

RF-PHY Specification(RCV-LE/CA/03/C)

SID324R CI5

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at Image
frequency (FIMAGE)

–

–20

–9

dB

RF-PHY Specification(RCV-LE/CA/03/C)

SID325R CI6

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at Image
frequency (FIMAGE ± 1 MHz)

–

–28

–15

dB

RF-PHY Specification(RCV-LE/CA/03/C)

Across RF Operating
Frequency Range

RF Receiver Specifications (2 Mbps)
RXS,IDLE

RX Sensitivity with Ideal
Transmitter

–

–92

–

dBm

SID326R RXS,IDLE

RX Sensitivity with Ideal
Transmitter

–

–90

–

255-byte packet
dBm length, acrossFrequency Range

SID326

Datasheet

88002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 57
Spec ID#

Bluetooth® LE Subsystem Specifications (continued)
Min

Typ

Max

Unit Details / Conditions

RX Sensitivity with Dirty
Transmitter

–

–89

–

RF-PHY SpecifidBm cation(RCV-LE/CA/01/C)

SID328R PRXMAX

Maximum received signal
strength at < 0.1% PER

–

0

–

RF-PHY SpecifidBm cation(RCV-LE/CA/06/C)

SID329R CI1

Co-channel interference,
Wanted Signal at –67 dBm
and Interferer at FRX

–

9

21

dB

RF-PHY Specification(RCV-LE/CA/03/C)

SID330CI2

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at FRX ± 2 MHz

–

3

15

dB

RF-PHY Specification(RCV-LE/CA/03/C)

CI3

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at FRX ± 4 MHz

–

–26

–17

dB

RF-PHY Specification(RCV-LE/CA/03/C)

CI4

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at ≥ FRX ± 6
MHz

–

–33

–27

dB

RF-PHY Specification(RCV-LE/CA/03/C)

CI5

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at Image
frequency (FIMAGE)

–

–20

–9

dB

RF-PHY Specification(RCV-LE/CA/03/C)

CI6

Adjacent channel interference
Wanted Signal at –67 dBm
and Interferer at Image
frequency (FIMAGE ± 2MHz)

–

–28

–15

dB

RF-PHY Specification(RCV-LE/CA/03/C)

OBB1

Out of Band Blocking
Wanted Signal at –67 dBm
and Interferer at F = 30–2000
MHz

–30

–27

–

RF-PHY SpecifidBm cation(RCV-LE/CA/04/C)

OBB2

Out of Band Blocking
Wanted Signal at –67 dBm
and Interferer at F = 2003–
2399 MHz

–35

–27

–

RF-PHY SpecifidBm cation(RCV-LE/CA/04/C)

OBB3

Out of Band Blocking,Wanted Signal at –67 dBm
and Interferer at F= 2484–
2997MHz

–35

–27

–

RF-PHY SpecifidBm cation(RCV-LE/CA/04/C)

OBB4

Out of Band Blocking
Wanted Signal at –67 dBm
and Interferer at F= 3000–
12750 MHz

–30

–27

–

RF-PHY SpecifidBm cation(RCV-LE/CA/04/C)

SID327

SID331

SID332

SID333

SID334

Parameter
RXS,DIRTY

Description

RF Receiver Specification (1 & 2 Mbps)
SID338SID339SID340

SID341

Datasheet

89002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 57
Spec ID#

SID342

SID343

SID344

Bluetooth® LE Subsystem Specifications (continued)
Parameter

IMD

RXSE1

Min

Typ

Max

Unit Details / Conditions

Intermodulation Performance
Wanted Signal at –64 dBm
and 1 Mbps Bluetooth® LE,
3rd, 4th, and 5th offset
channel–50––

RF-PHY SpecifidBm cation(RCV-LE/CA/05/C)–57

100-kHzmeasurementdBm bandwidth
ETSI EN300 328
V2.1.11-MHz
measurementdBm bandwidth
ETSI EN300 328
V2.1.1

Receiver Spurious emission
30 MHz to 1.0 GHz

Receiver Spurious emission
1.0 GHz to 12.75 GHz

–

–

–

–

–53

RF Transmitter Specifications

–

–

–

–

SID345

TXP,ACCRF Power Accuracy

–1

–

1

dB

–

SID346

TXP,RANGE

Frequency Accuracy

–

24

–

dB

–20 dBm to +4 dBm

SID347

TXP,0dBm

Output Power, 0 dB Gain
setting

–

0

–

dBm –

SID348

TXP,MAX

Output Power, Maximum
Power Setting

–

4

–

dBm –

SID349

TXP,MIN

Output Power, Minimum
Power Setting

–

–20

–

dBm –

SID350F2AVG

Average Frequency
deviation for 10101010
pattern

185––

RF-PHY SpecifikHz cation(TRM-LE/CA/05/C)

SID350R F2AVG_2M

Average Frequency
deviation for 10101010
pattern for 2 Mbps

370

–

–

RF-PHY SpecifikHz cation(TRM-LE/CA/05/C)

SID351

Average Frequency
deviation for 11110000
pattern

225

250

275

RF-PHY SpecifikHz cation(TRM-LE/CA/05/C)

SID351R F1AVG_2M

Average Frequency
deviation for 11110000
pattern for 2 Mbps

450

500

550

RF-PHY SpecifikHz cation(TRM-LE/CA/05/C)

SID352EO

Eye opening =∆F2AVG/∆F1AVG

0.8

–

–

–

SID353

FTX,ACC

Frequency Accuracy

–150

–

150

RF-PHY SpecifikHz cation(TRM-LE/CA/06/C)

SID354

FTX,MAXDR

Maximum Frequency Drift

–50

–

50

RF-PHY SpecifikHz cation(TRM-LE/CA/06/C)

Datasheet

RXSE2

Description

F1AVG

90

RF-PHY Specification(TRM-LE/CA/05/C)

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 57
Spec ID#

Bluetooth® LE Subsystem Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit Details / Conditions

SID355FTX,INITDR

Initial Frequency drift

–20

–

20

RF-PHY SpecifikHz cation(TRM-LE/CA/06/C)

SID356

FTX,DR

Maximum Drift Rate

–20

–

20

RF-PHY SpecifikHz/
cation
50 µs(TRM-LE/CA/06/C)

IBSE1

In Band Spurious Emission
at 2 MHz offset (1 Mbps)
In Band Spurious Emission
at 4 MHz offset (2 Mbps)

–

–

–20

RF-PHY SpecifidBm cation(TRM-LE/CA/03/C)

SID358IBSE2In Band Spurious Emission
at ≥ 3 MHz offset (1 Mbps)
In Band Spurious Emission
at ≥ 6 MHz offset (2 Mbps)

–

–

–30

RF-PHY SpecifidBm cation(TRM-LE/CA/03/C)

SID359TXSE1Transmitter Spurious
Emissions (Averaging), < 1.0
GHz

–

–

–55.5

dBm FCC-15.247

SID360TXSE2Transmitter Spurious
Emissions (Averaging), > 1.0
GHz

–41.5

dBm FCC-15.247

SID357

RF Current Specification
SID361

IRX1_wb

Receive Current (1 Mbps)

–

6.7

–

VDD_NS = VDDD =mA 3.3 V current withbuck

SID362

ITX1_wb_0dBm

TX Current at 0 dBm setting(1 Mbps)

–

5.7

–

VDD_NS = VDDD =mA 3.3 V current withbuck

SID363

IRX1_nb

Receive Current (1 Mbps)

–

11

–

mA

VDDD current
without buck

SID364

ITX1_nb_0dBm

TX Current at 0-dBm setting(1 Mbps)

–

10

–

mA

VDDD current
without buck

SID365

ITX1_nb_4dBm

TX Current at 4-dBm setting(1 Mbps)

–

13

–

mA

VDDD current
without buck

SID365R

ITX1_wb_4dBm

TX Current at 4-dBm setting(1 Mbps)

–

8.5

–

VDD_NS = VDDD =mA 3.3 V current withbuck

SID366

ITX1_nb_20dBm

TX Current at –20-dBm
setting (1 Mbps)

–

7

–

mA

SID367

IRX2_wb

Receive Current (2 Mbps)

–

7

–

VDD_NS = VDDD =mA 3.3 V current withbuck

SID368

ITX2_wb_0dBm

TX Current at 0-dBm setting(2 Mbps)

–

5.7

–

VDD_NS = VDDD =mA 3.3 V current withbuck

SID369IRX2_nb

Receive Current (2 Mbps)

–

11.3

–

mA

Datasheet

91

VDDD current
without buck

VDDD current
without buck002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications
Table 57
Spec ID#

Bluetooth® LE Subsystem Specifications (continued)
Parameter

Description

Min

Typ

Max

Unit Details / Conditions

SID370

ITX2_nb_0dBm

TX Current at 0-dBm setting(2 Mbps)

–

10

–

mA

VDDD current
without buck

SID371

ITX2_nb_4dBm

TX Current at 4-dBm setting(2 Mbps)

–

13

–

mA

VDDD current
without buck

SID371R

ITX2_wb_4dBm

TX Current at 4-dBm setting(2 Mbps)

–

8.5

–

VDD_NS = VDDD =mA 3.3 V current withbuck

SID372

ITX2_nb_20dBm

TX Current at –20-dBm
setting (2 Mbps)

–

7

–

mA

2400

–

2482

MHz –

VDDD current
without buck

General RF Specification
SID373FREQ

RF operating frequency

SID374CHBW

Channel spacing

–

2

–

MHz –

SID375DR1

On-air Data Rate (1 Mbps)

–

1000

–

kbps –

SID376DR2

On-air Data Rate (2 Mbps)

–

2000

–

kbps –

SID377

TXSUP

Transmitter Startup time

–

80

82

µs

–

SID378

RXSUP

Receiver Startup time

–

80

82

µs

–

RSSI Specification
SID379

RSSI,ACCRSSI Accuracy

–4

–

4

dB

–95 dBm to –20 dBm
measurement range

SID380

RSSI,RESRSSI Resolution

–

1

–

dB

–

SID381

RSSI,PERRSSI Sample Period

–

6

–

µs

–

System-Level Bluetooth® LE Specifications
SID433R Adv_Pwr

1.28s, 32 bytes, 0 dBm

–

42

–

µW

3.3 V, Buck, w/o
Deep Sleep current

Conn_Pwr_300

300 ms, 0 byte, 0 dBm

–

70

–

µW

3.3 V, Buck, w/o
Deep Sleep current

SID435R Conn_Pwr_1S 1000 ms, 0 byte, 0 dBm

–

30

–

µW

3.3 V, Buck, w/o
Deep Sleep current

SID436R Conn_Pwr_4S 4000 ms, 0 byte, 0 dBm

–

4

–

µW

3.3 V, Buck, w/o
Deep Sleep current

SID434R

Datasheet92002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Electrical specifications

Table 58
Spec
ID#

Bluetooth® LE ECO Specifications
Parameter

Description

Min Typ

Max

Unit Details / Conditions

16-MHz Crystal Oscillator
SID382FXO1Crystal frequency

–

16

–

MHz –

SID383

ESR1

Equivalent series resistance

–

100

250

Ω

–

SID384Txostart1

Startup time

–

400

–

µs

Frequency Stable(16 MHz ±50 ppm)

SID385IXO1

Operating current

–

300

–

µA

Includes crystal
current, LDO and BG

32-MHz Crystal Oscillator
SID386FXO2Crystal frequency

–

32

–

MHz –

SID387

ESR2

Equivalent series resistance

–

50

100

Ω

–

SID388Txostart2

Startup time

–

400

–

µs

Frequency Stable(32 MHz ±50 ppm)

SID389IXO2Operating current

–

350

–

µA

Includes crystal
current, LDO and BG

16-MHz and 32-MHz Crystal Oscillator
SID390FTOLFrequency tolerance

–20

–

20

After trimming,
ppm including aging andtemp drift

SID391PD

Drive level

–

–

100

µW

Datasheet

93–002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Ordering information

7

Ordering information

Table 59 lists the CY8C63x6 and CY8C63x7 part numbers and features. All devices include a Bluetooth® LE radio,
DC-DC converter, QSPI SMIF, ADC, DAC, 9 SCBs, 32 TCPWMs, and 2 PDMs. See also the product selector guide.

CY8C6336BZI-BLF03

150–

SingleCY8C6316BZI-BLF0350–

CY8C6316BZI-BLF5350–

CY8C6337BZI-BLF13150

CY8C6336BZI-BLD13150

CY8C6347BZI-BLD43
CY8C6347BZI-BLD33
CY8C6347BZI-BLD53

No

No

No

36

No

68-QFN

Yes

No

No

36

No

68-QFN

Yes

Yes

No

36

No

68-QFN

No

No

No

78

Yes

116-BGA

No

No

No

No

78

Yes

116-BGA

Yes

Yes

No

No

78

Yes

116-BGA

No

No

No

78

Yes

116-BGA

No

No

No

78

Yes

116-BGA

Yes

Yes

No

78

Yes

116-BGA

No

No

No

78

Yes

116-BGA

Yes

Yes

No

78

Yes

116-BGA

No

No

Yes

84

Yes

124-BGA

No

No

No

Yes

84

Yes

124-BGA

Yes

Yes

No

Yes

84

Yes

124-BGA

No

No

Yes

84

Yes

124-BGA

No

No

Yes

84

Yes

124-BGA

Yes

Yes

Yes

84

Yes

124-BGA

No

No

Yes

84

Yes

124-BGA

Yes

Yes

Yes

84

Yes

124-BGA

No

No

No

70

Yes

104-M-CSP

Yes

Yes

Yes

No

70

Yes

104-M-CSP

Yes

No

No

No

70

Yes

104-M-CSP

12

Yes

Yes

Yes

No

70

Yes

104-M-CSP

0

0

Yes

No

No

Yes

69

Yes

104-M-CSP-USB

0

0

Yes

Yes

Yes

Yes

69

Yes

104-M-CSP-USB

288

1

12

Yes

No

No

Yes

69

Yes

104-M-CSP-USB

288

1

12

Yes

Yes

Yes

Yes

69

Yes

104-M-CSP-USB

0

0

Yes

1

12

Yes

128

0

0

No

512

128

0

0

512

128

1

12

1024

288

0

0

Yes

LP

512

128

0

0

Yes

FLEX

1024

288

0

0

Yes

FLEX

1024

288

1

12

Yes

FLEX

1024

288

1

12

Yes

Single

LP

512

128

0

0

No

–

Single

ULP

512

128

0

0

–

Single

ULP

512

128

1

12

150

–

Single

LP

1024

288

0

0

Yes

CY8C6336BZI-BLD14

150

100

Dual

LP

512

128

0

0

Yes

CY8C6347BZI-BLD44

150/50 100/25

Dual

FLEX

1024

288

0

0

Yes

CY8C6347BZI-BLD34

150/50 100/25

Dual

FLEX

1024

288

1

12

Yes

CY8C6347BZI-BLD54

150/50 100/25

Dual

FLEX

1024

288

1

12

Yes

CY8C6347FMI-BLD13

150/50 100/25

Dual

FLEX

1024

288

0

0

Yes

CY8C6347FMI-BLD43

150/50 100/25

Dual

FLEX

1024

288

0

0

CY8C6347FMI-BLD33

150/50 100/25

Dual

FLEX

1024

288

1

12

CY8C6347FMI-BLD53

150/50 100/25

Dual

FLEX

1024

288

1

CY8C6347FMI-BUD13

150/50 100/25

Dual

FLEX

1024

288

CY8C6347FMI-BUD43

150/50 100/25

Dual

FLEX

1024

288

CY8C6347FMI-BUD33

150/50 100/25

Dual

FLEX

1024

CY8C6347FMI-BUD53

150/50 100/25

Dual

FLEX

1024

512

128

LP

512

128

FLEX

1024

288

LP

512

SingleULPSingleULP–Single

LP

100

Dual

150/50 100/25

Dual

150/50 100/25

Dual

150/50 100/25

Dual

CY8C6336BZI-BLF04

150–

CY8C6316BZI-BLF0450

CY8C6316BZI-BLF5450

CY8C6337BZI-BLF14

MPN

FamilySRAM (KB)

No

Flash (KB)0

ULP/LP

0LP

CY8C6336LQI-BLF02

63

Package

Dual

I2S

SingleGPIOs–

150/50 100/25

USB

150

CY8C6347LQI-BLD52‘Secure Boot’CY8C6336LQI-BLF42

CRYPTO

SingleCAPSENSE™

–

No. of UDBs

Single CPU/Dual CPU

150

No. of CTBMs

CPU Speed (CM0+)CY8C63 Series part numbers
CPU Speed (CM4)

Table 59

Datasheet

94002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Ordering information

7.1

PSoC™ 6 MPN decoder

CY XX 6 A B C DD E - FF G H I JJ K L
Field Description Values
CY

XX

Cypress

Firmware

8C

Meaning
Cypress - An Infineon
Technologies
company
Standard

B0“Secure Boot” v1

CY

6“Standard Secure” AWS
PSoC™ 6

0

Value

1
2
3
4
2
3
4

Programmable
Performance
Connectivity
Secured100 MHz
150 MHz
150/50 MHz

0-3

S0
6

A

B

C

DD

Architecture

Line

Speed

Memory Size
(Flash/SRAM)

Package

Datasheet

Field

E

Description

Temperature
Range

ValuesMeaning

C

ConsumerI

Industrial
Extended Industrial

Q

Cypress internalFF

Feature Code

S2-S6
BL

G

CPU Core

H

Attributes CodeI

GPIO countReserved

JJ

Engineering
sample(optional)

45

256K/128K
512K/256K

K

Die Revision(optional)

6

512K/128K

L

Tape/Reel
Shipment(optional)

F
D
0–9
1
2
3
4
ES

Integrated
Bluetooth® LE
Single Core
Dual Core
Feature set
31–50
51–70
71–90
91–110Engineering
samples or not

Base
A1–A9 Die revision
T

Tape and Reel
shipment

71024K/288K
8
1024K/512K
9
Reserved
A
2048K/1024K
AZ, AX TQFP
LQ QFNBZ BGAFM M-CSP
FN, FD,
WLCSP
FT

95

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Packaging

8

PackagingThis product line is offered in four packages: 68-QFN, 116-BGA, 124-BGA, and 104-M-CSP.
Table 60

Package Dimensions

Spec ID# Package

Package Drawing
NumberDescription

124-BGA 124-BGA, 9  9  1 mm height with 0.65-mm pitch

001-97718

PKG_2 104-M-CSP 104-M-CSP, 3.8  5  0.65 mm height with 0.35-mm pitch

002-16508

PKG_4

116-BGA 116-BGA, 5.2  6.4  0.70 mm height with 0.5-mm pitch

002-16574

PKG_5

68-QFN

68-QFN, 8  8  1 mm height with 0.4-mm pitch

001-96836

PKG_1

Table 61

Package Characteristics

Parameter

Description

Conditions

Min

Typ

Max

Unit

TA

Operating ambient temperature

–

–40

25.00

85

°C

TJ

Operating junction temperature

–

–40

–

100

°C

TJA

Package JA (124-BGA)

–

–

64.3

–

°C/watt

TJC

Package JC (124-BGA)

–

–

37

–

°C/watt

TJA

Package JA (116-BGA)

–

–

36.5

–

°C/watt

TJC

Package JC (116-BGA)

–

–

12

–

°C/watt

TJA

Package JA (104-CSP)

–

–

33.7

–

°C/watt

TJC

Package JC (104-CSP)

–

–

0.2

–

°C/watt

TJA

Package JA (68-QFN)

–

–

21.6

–

°C/watt

TJC

Package JC (68-QFN)

–

–

7.2

–

°C/watt

Table 62

Solder Reflow Peak Temperature
Package

Maximum Peak Temperature

Maximum Time at Peak
Temperature

124-BGA, 116-BGA, and 68-QFN

260 °C

30 seconds

104-M-CSP

260 °C

30 seconds

Table 63

Datasheet

Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package

MSL

124-BGA, 116-BGA, and 68-QFN

MSL 3

104-M-CSP

MSL 1

96

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Packaging

5.

7.

6.

6.

TOP VIEW

BOTTOM VIEW

SIDE VIEWNOTES:DIMENSIONSSYMBOL

MIN.

NOM.

MAX.

A

-

-

0.650

A1

0.167

0.185

0.203

D

3.791

3.841

3.891

E

4.95

5.00

5.05

D1

2.80 BSC

E1

4.55 BSC

MD

9

ME

14

N

1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIXSIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

104

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

b

0.215

0.245

0.275

eD

0.335

0.350

0.365

eE

0.335

0.350

0.365

SD

0.35 BSC

SE

0.175 BSC

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARKMETALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDERBALLS.

002-16508 *E

9. JEDEC SPECIFICATION NO. REF. : N/A.

Figure 21

Datasheet

104-M-CSP 3.8 × 5.0 × 0.65 mm

97002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Packaging002-16574 *B

Figure 22

Datasheet

116-BGA 5.2 × 6.4 × 0.70 mm

98002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Packaging001-97718 *B

Figure 23

Datasheet

124-BGA 9.0 × 9.0 ×1.0 mm

99002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Packaging001-96836 *A

Figure 24

Datasheet

68 QFN 8 × 8 × 1 mm

100

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Acronyms

9

Acronyms
AcronymDescription

3DES

triple DES (data encryption standard)

ADC

analog-to-digital converter

AES

advanced encryption standard

AHB

AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data transfer bus

AMUX

analog multiplexer

AMUXBUSanalog multiplexer bus

APIapplication programming interfaceArm®

advanced RISC machine, a CPU architecture

BGA

ball grid array

BOD

brown-out detect

CAD

computer aided design

CCO

current controlled oscillator

CM0+

Cortex-M0+, an Arm CPU

CM4

Cortex-M4, an Arm CPU

CMAC

cipher-based message authentication code

CMOS

complementary metal-oxide-semiconductor, a process technology for IC fabrication

CMRR

common-mode rejection ratioCPUcentral processing unit

CRC

cyclic redundancy check, an error-checking protocol

CSD

Capacitive Sigma-Delta

CSX

Mutual capacitance sensing method. See also CSD

DAC

digital-to-analog converter, see also IDAC, VDAC

DAP

debug ccess port

DES

data encryption standard

DMA

direct memory access, see also TD

DNL

differential nonlinearity, see also INL

DSI

digital system interconnect

DU

data unit

ECC

elliptic curve cryptography

ECO

external crystal oscillator

EEPROM

electrically erasable programmable read-only memoryEMIelectromagnetic interference

ESDelectrostatic discharge

ETM

embedded trace macrocell

FIFO

first-in, first-out

FLL

frequency locked loop

FPU

floating-point unitFSfull-speed

GND

GroundGPIOgeneral-purpose input/output, applies to a PSoC™ pin

HMAC

Hash-based message authentication code

HSIOM

high-speed I/O matrix

I/O

input/output, see also GPIO, DIO, SIO, USBIO

Datasheet101

002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Acronyms
AcronymDescription

2

I C, or IIC

Inter-Integrated Circuit, a communications protocol

I2S

inter-IC soundIC

integrated circuit

IDAC

current DAC, see also DAC, VDAC

IDE

integrated development environment

ILO

internal low-speed oscillator, see also IMO

IMO

internal main oscillator, see also ILO

INL

integral nonlinearity, see also DNL

IoTinternet of things

IPC

inter-processor communication

IRQ

interrupt request

ISR

interrupt service routine

JTAG

Joint Test Action Group

LCD

liquid crystal display

LIN

Local Interconnect Network, a communications protocolLP

low powerLS

low-speed

LUT

lookup table

LVD

low-voltage detect, see also LVI

LVTTL

low-voltage transistor-transistor logic

MAC

multiply-accumulate

M-CSP

molded chip scale package

MCU

microcontroller unit

MCWDT

multi-counter watchdog timer

MISO

master-in slave-out

MMIO

memory-mapped input output

MOSI

master-out slave-in

MPU

memory protection unit

MSL

moisture sensitivity level

Msps

million samples per second

MTB

micro trace buffer

MULmultiplierNC

no connect

NMI

nonmaskable interrupt

NVIC

nested vectored interrupt controller

OTP

one-time programmable

OVT

overvoltage tolerant

PASS

programmable analog subsystem

PCB

printed circuit board

PCM

pulse code modulation

PDM

pulse density modulation

PHY

physical layer

PICU

port interrupt control unit

PLL

phase-locked loop

Datasheet

102002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Acronyms
AcronymDescription

PMIC

power management integrated circuit

POR

power-on reset

PPU

peripheral protection unit

PRNG

pseudo random number generator

PSoC™

Programmable System-on-Chip

PSRR

power supply rejection ratio

PWM

pulse-width modulator

QD

quadrature decoder

QSPI

quad serial peripheral interfaceRAM

random-access memory

RISC

reduced-instruction-set computing

RMS

root-mean-squareROM

read-only memory

RSA

Rivest–Shamir–Adleman, a public-key cryptography algorithm

RTC

real-time clockRX

receive

S/H

sample and hold

SAR

successive approximation register

SARMUXSAR ADC multiplexer bus

SCB

serial communication block

SFlashsupervisory flash

SHA

secure hash algorithm

SINAD

signal to noise and distortion ratio

SNR

signal-to-noise ration

SOF

start of frame

SPI

Serial Peripheral Interface, a communications protocol

SRAM

static random access memory

SROM

supervisory read-only memory

SRSS

system resources subsystem

SWD

serial wire debug, a test protocol

SWJ

serial wire JTAG

SWO

single wire output

SWV

serial-wire viewer

TCPWM

timer, counter, pulse-width modulator

TDM

time division multiplexed

TQFP

thin quad flat package

TRM

technical reference manual

TRNG

true random number generator

TX

transmit

UART

Universal Asynchronous Transmitter Receiver, a communications protocol

UDB

universal digital block

ULP

ultra-low power

USB

Universal Serial Bus

WCO

watch crystal oscillator

Datasheet103002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Acronyms
AcronymDescription

WDT

watchdog timer

WIC

wakeup interrupt controller

WLCSP

wafer level chip scale package

XIP

execute-in-place

XRES

external reset input pin

Datasheet104002-18787 Rev. *R
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PSoC™ 63 MCU with Bluetooth® LE
Document conventions

10

Document conventions

10.1

Unit of measure

Table 64

Unit of measure

SymbolUnit of Measure°C

degrees CelsiusdB

decibelfF

femto farad

Hz

hertz

KB

1024 bytes

kbps

kilobits per secondkhrkilohourkHzkilohertzkkilo ohm

ksps

kilosamples per second

LSB

least significant bit

Mbps

megabits per secondMHzmegahertzM

mega-ohm

Msps

megasamples per secondµA

microampereµF

microfaradµH

microhenryµs

microsecondµV

microvoltµW

microwattmA

milliampere

msmillisecondmVmillivoltnA

nanoampere

ns

nanosecondnV

nanovolt



ohm

pF

picofaradppm

parts per millionpspicosecondssecondsps

samples per second

sqrtHzsquare root of hertz

V

volt

Datasheet

105002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Revision history

Revision histor yDocument
revision
*F
*G

Date

Description of changes

2018-05-03
2018-07-17

Release of production datasheet.
Corrected document number in the revision history table.
Updated Functional description.
Added “Pinouts for 104-MCSP with USB” table in Pinouts.
Added package diagram (spec 001-97718 *B).
Added a note in Table 4.
Updated Table 13, Table 31, and Table 45 in Electrical specifications.
Updated Features, Blocks and functionality, Internal Low-speed
Oscillator (ILO), Packaging, and Ordering information.
Updated Figure 21 (spec 002-16508 *D to *E) in Packaging.
Corrected Unit usage throughout the document.
Added Errata.
Updated Copyright information in Sales page.
Updated the title.
Added UDB in Acronyms.
Updated Features.
Updated Blocks and functionality and Functional description.
Updated Pinouts and Power Supply Considerations.
Updated Features.
Updated Functional description.
Updated Pinouts.
Updated PSoC™ 6 MPN decoder.
Updated Development ecosystem, GPIO, and LCD sections.
Added External Crystal Oscillators.
Updated Errata.
Updated Flexible clocking options, Figure 3, CPUs, Clock system, andSID431.
Updated Universal digital blocks (UDBs), UDB Port Adapter Specifications
Conditions.
Added InterProcessor Communication (IPC).
Updated Audio subsystem diagram.
Updated the XRES bullet in Reset, updated SID15 Description andConditions, and Power-on-reset specifications table.
Updated ModusToolbox™ Software.
Updated Reset.
Updated Figure 4.
Updated Protection units and Boot Code.
Integrated ECO erratum into External Crystal Oscillators. Added Table 5.
Updated Power Supply Considerations.
Updated Opamp.
Added spec SID468 - SID474, and SID468A - SID474A.
Updated Audio Spec SID408.
Updated SID7A conditions, SID7D description, and SID8 conditions.
Added footnote to TMCLK_SOC specs.
Added Table 12 and Figure 18.
Updated conditions for SID316 and updated description of SID319.
Changed BLE references to Bluetooth LE.
Updated Security terminology to Infineon standards.
Removed the Errata section; incorporated errata into the GPIO, ADC, andCapSense sections.
Added opamp graphs (Figure 19 and Figure 20).

*H

2019-04-01*I

2019-09-20*J

2019-12-20*K

2020-03-31*L

2020-06-22*M

2020-11-10*N

2021-02-26*O

2021-06-30

Datasheet106002-18787 Rev. *R
2023-05-10

PSoC™ 63 MCU with Bluetooth® LE
Revision history
Document
revision

Date*P

2021-12-14*Q

2022-10-31*R

2023-05-10

Datasheet

Description of changes
Added note regarding unused USB pins in USB Full-Speed device
interface, Power Supply Considerations, and Pinouts.
Updated SIDC1 description.
Updated Figure 18 and added related footnote.
Updated details/conditions for SID7A.
Updated SID325U, SID328, and SID329 description.
Added I2S column to Table 59.
Added device identification and revision information in Features.
Added spec SID415 and SID304P.
Added footnote “Guaranteed by design, not production tested” for specs
SID402 - SID412.
Updated Clock system.
Updated PLL specifications.
Updated Protection units.
Updated Development ecosystem:
Updated PSoC™ Creator:
Added a note “PSoC™ Creator is not recommended for new designs” in thestarting.

107002-18787 Rev. *R
2023-05-10

Please read the Important Notice and Warnings at the end of this document

Trademarks
All referenced product or service names and trademarks are the property of their respective owners.

Edition 2023-05-10
Published byInfineon Technologies AG
81726 Munich, Germany© 2023 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about thisdocument?
Email:
erratum@infineon.com
Document reference002-18787 Rev. *R

IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typicalvalues stated herein and/or any information
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Technologies hereby disclaims any and all
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The data contained in this document is exclusively
intended for technically trained staff. It is the
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to evaluate the suitability of the product for theintended application and the completeness of the
product information given in this document withrespect to such application.

WARNINGS
Due to technical requirements products may containdangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
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representativesofInfineonTechnologies, Infineon Technologies’ products may
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