Time Domain
Simulation ofElectrostatic
Discharge Testing
RemcomState College, Pa.

An electrostatic discharge (ESD) isthe sudden flow of current between two electrically charged
objects, caused by the break- Fig. 1 Electric fields during a simulated ESD test of a DDR3 RAM stick.

down of the dielectrics separating them, i.e.,
dielectric breakdown. In the case of electronic devices, the resulting current flow andpossible spark can permanently damage thedevice (see Figure 1). An often recited yet
unsubstantiated quote is “…losses associated with ESD in the electronics industry are
estimated at between half a billion and $5billion annually.” In reality, estimating theexact cost of ESD loss is extremely difficult;nonetheless, ESD forces the development
and testing of many hardware prototypes
during design and manufacturing and contributes to a high number of warranty claims
with loss of consumer confidence if a failure
occurs in the hands of the consumer. Therefore, electronics manufacturers go to great
lengths to properly shield sensitive components and design systems to reduce, dissipate and neutralize static charge.
To test ESD susceptibility, hardware engineers typically use test models defined byvarious standards, from organizations such

Reprinted with permission of MICROWAVE JOURNAL® from the July 2019 issue.
©2019 Horizon House Publications, Inc.

ProductFeature Fig. 2 8 kV HBM waveform in XFdtd.
as ANSI, JEDEC and the IEC. The
most common and widely used
ESD models are the human bodymodel (HBM), which approximatesa discharge from a charged humanfingertip to a grounded device (seeFigure 2), and the charged device
model (CDM), which approximatesa discharge from a charged device
to another conducting object at alower electrostatic potential. Thesetests are generally performed using ESD simulators or ESD guns toapply high speed and high voltage
pulses to various points of the device under test (DUT).
Even for an experienced engineer, pinpointing the location of
an ESD failure during testing—ordetermining whether a failure occured at all—can be extremely challenging. ESD failures are typically
categorized in three groups: catastrophic, latent or upset. In the caseof a catastrophic failure, the DUT nolonger functions and there is usually
physical damage such as melted
and/or charred components. Intuitively, a catastrophic failure maysound like the worst-case scenario;
however, it is actually the most ideal
to encounter during quality assurance testing, because it is easily
recognized, located and accounted
for in the final ESD mitigation design. On the other hand, latent andupset failures are much more difficult to diagnose because the DUT
still functions, with little or no signof physical damage. Latent failures
are often not visible to the naked
eye and result in a weakened device
which functions at the time of testing and deteriorates over time with

continued usage,often malfunctioning or failing intheconsumer’spossession. Upset
failures result fromover-currents which
do not physicallydamage the DUT
butcompromise
the components’semiconductive
properties, leading
to unpredictablebehavior and data
loss in use. Latent
failures can some-  Fig. 3 Definition of dielectric breakdown sensor.
times be identified
with magnification,
but upset failures
are nearly impossible to detect during testing.
Given the highcost of time andmaterials for ESD
hardware testing
and the difficulty
locating latent andupset failures, simulating ESD testing is extremely Fig. 4 Risk areas for dielectric breakdown identified during
valuable, as it can simulated ESD testing.
pinpoint locations
susceptible to ESD damage andexperiencing dielectric breakdown
then help optimize ESD mitigation(i.e., losing its insulating properties).
during product design. RespondUpon adding the dielectric strength
ing to this growing need, newparameter to XFdtd, it is possible
ESD simulation features have been
to monitor FDTD cell edges for poadded to Remcom’s full wave electential breakdown during transient
tromagnetic simulation software
simulations using a dielectric breakpackage, XFdtd®. Using XFdtd’s
down near-field sensor (see Figure
improved user-defined waveform3). The sensor instructs the XFdtd
feature, engineers can import ESD
calculation engine to monitor cellwaveforms defined by various testedges for electric fields exceeding standards, using them to create
ing the dielectric strength of their
ESD current sources in an XFdtd
constituent materials, recording inproject. At this point, ESD simulastances when dielectric breakdown
tor/gun models can be created andis likely to occur. The sensor requires
used to excite the DUT geometry
the user to define the free space diat locations of interest, with the reelectric strength, used for all edges
sulting electromagnetic (EM) fields
that do not contain a defined mateand current flows simulated andrial. The default free space dielectric
analyzed (see Figure 1).
strength is set to 3 MV/m, the dielecTo solve the challenge of detertric strength of air at sea level. The
mining if and where an actual ESD
sensor also allows the user to define
failure occured, a new material paa bounding box to limit the volume
rameter, dielectric strength, wasmonitored for dielectric breakdown.
added to XFdtd’s electric material
Using this feature saves on compudefinitions. The dielectric strength
tation by defining the specific areasof a material defines the maximumof interest, rather than examining
electric field it can withstand without
the entire computational domain.

ProductFeature Fig. 5 Summary of components exceeding rated design
parameters during simulated ESD testing.

At the conclusion of an FDTD simulation, the cell edges
which exceed their respective dielectric strengths canbe viewed, as shown in Figure 4.
Functionality was also added to XFdtd to monitor
specific electronic components that are taxed beyond
their rated voltage and current input parameters, which
can be obtained from the components’ data sheets.

Post-simulation results identify those components thatare subject to permanent damage due to unsafe limits(see Figure 5).
While simulation cannot and should not replace
hardware testing entirely, these new computationalfeatures provide ESD engineers with more insight into
the probable locations of ESD failure, enabling ESD
mitigation designs to be optimized prior to prototyping
hardware. Remcom believes this capability will reduce
product development cost and time to market, while
improving product reliability and consumer confidence.
These new features lay the foundation for additional
multiphysics capabilities, including plasma discharge
and thermal simulation to model the current and heatgenerated from spark discharges. Merging these computational techniques will enable the analysis of downstream current flows after an initial dielectric breakdown, more accurately predicting dielectric and circuitcomponent failures.
RemcomState College, Pa.
www.remcom.com