DATA SHEET
www.onsemi.com

Self-Test Ground Fault
Circuit Interrupter (GFCI)
NCS37021
The NCS37021 is a UL943 compliant signal processor for GFCI
applications with self−test. The device integrates a flexible power
supply (including a 12 V shunt, two 3.3 V internal series
regulators and a 1.8 V internal regulator), differential fault,
and grounded−neutral detection circuits. Self−test is monitored at startup and then every minute.

QFN16
CASE 485FQMARKING DIAGRAM

37021
ALYW

Features(Coil is not Energized Near the AC Mains Zero Crossings)• Power Supply Monitor that Verifies Full Diode Bridge Operation• Tiered GF Trip Times that Increase Immunity to Noise• Under−voltage Detection that Allows for Increased Operation at
Lower AC Input Voltages• Intelligent Sensing Differentiating Ground Fault versus Ground
Neutral Fault (Prevent Nuisance Tripping)• 16 Pin QFN Package• This is a Pb−Free Device
Typical Applications• GFCI Receptacles• Load Panel GFCI Breakers• In−line GFCI Circuits (Power Cords)= Specific Device Code= Assembly Location= Wafer Lot= Year= Work Week

PIN CONNECTIONS
SCR
GFT
LED
DRF

(120−480 V AC Mains with the Appropriate Series Impedance)• Wide Operating Temperature Range from 40°C to 95°C
• Low Quiescent Current• Optimized Solenoid Deployment

37021
A
L
Y
W

CTG
SCM
CTB
CTS

SUP
AUX
MLD
PTT
CTO
IDF
REF
GND

• Meets UL943 Self−test GFCI Requirements• 4.0 – 12 V Operation(Top View)

ORDERING INFORMATION
See detailed ordering and shipping information on page 9 ofthis data sheet.

© Semiconductor Components Industries, LLC, 2024

September, 2024 − Rev. 0

1

Publication Order Number:
NCS37021/D

NCS37021
BLOCK DIAGRAM

CTB

1.65V

12V Shunt
Regulator

−
+

REF/2

IDF

HV Bandgap
Reference

REF

SUP
AUX

3.3V Analog
Regulator

Bias
Block

NCS37021

EE Vref

3.3V Digital
Regulator
1.8V
DigitalRegulator

1.8V
Ref

DRF

Oscillator

POR

−
+/−
+
CTO

+0.2V
data[9:0]

SAR
ADC

Saturation
Clamp/
Detection

+
−

−

CTG

EEPROM Memory

−0.2V

chop

done
adc_start
adc_clk+

LED

CONTROL LOGICGF Detection

CTS
MLD

saturated
3.3V Voltage Clamp

SCR

chop
gnCompSCM

Digital Filter

GN Fault Detection
Open Solenoid Detection
Self TestUVD

ADC Offset Correction

3.3V Voltage Clamp

PTT
3.3V Voltage Clamp

Figure 1. Simplified Block Diagram
Table 1. QFN PIN DESCRIPTION
Pin #

Name

1

CTG

Ground Neutral current transformer stimulus

2

SCM

Test input for SCR functionality

3

CTB

Differential current transformer bias voltage

4

CTS

Differential current input

5

CTO

Differential current to voltage output

6

IDF

Differential low pass filter/ADC input

7REF

3.3 V Internal reference voltage

8

GND

Electronics ground

9

PTT

Reference current bias input Push to Test

10

MLD

Mains level/under voltage detector

11

AUX

Auxiliary power supply input

12

SUP

Power supply input

13

DRF

1.8 V Internal reference voltage

14

LED

End of life LED drive

15

GFT

Differential self−test output signal

16

SCR

SCR gate drive signal

Pin Description

www.onsemi.com
2

GFT

GND

NCS37021
Table 2. ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
RatingSymbol

Value

Unit

Supply Voltage Range

Vs

13.5

V

Supply Current

Is

10

mA

Input Voltage Range (Note 3)

Vin−0.3 to 3.6

V

Output Voltage Range

Vout−0.3 to 3.6 V or (Vin + 0.3),
whichever is lower

V

Maximum Junction Temperature

TJ(max)140°C

Storage Temperature Range

TSTG−65 to 150°C

ESD Capability, Human Body Model (Note 4)

ESDHBM

2kV

ESD Capability, Charge Device Model (Note 4)

ESDCDM

500

V

TSLD

260

°C

Lead Temperature Soldering Reflow (SMD Styles Only),
Pb−Free Versions (Note 5)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Functional operation above the Recommended Operating Conditions is not implied.
2. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
3. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (JEDEC JS−001−2010)
ESD Charge Device Model tested per AEC−Q100−003 (JESD22−C101−A)
Latchup Current Maximum Rating: ≤100 mA per JEDEC standard: JESD78
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

Table 3. THERMAL CHARACTERISTICS
Rating
Thermal Characteristics, QFN16, 3 × 3.3 mm (Note 6)
Thermal Resistance, Junction−to−Air (Note 7)

Symbol

Value

Unit

RqJA

64

°C/W

6. Refer to ELECTRICAL CHARACTERISTICS for Safe Operating Area.
7. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.

www.onsemi.com
3

NCS37021
Table 4. OPERATING RANGES (Unless otherwise noted, ISUP = 3 mA, MLD input = 60 Hz, Refer to Figure 2)
Parameter

Max

Unit

Operating Temperature

Ambient

Conditions

Min
−40

Typ

95

°C

Shunt Regulator Voltage

SUP to GND, ISUP = 1 mA

11

13

V

Shunt Regulator Current

ISUP

10

mA

Quiescent Current

ISUP_Quiescent

1.3

mA

RMS Trip Threshold Voltage (5 mA)

IDF to CTB, R4A = 36 kW
R4B = 50 W

160

mV

SCR Trigger Current

ISCR

SCR Trigger Output Voltage

SCR to GND, SUP > 4 V

LED Output Voltage
CTB Bias Voltage

4

mA

3.3

V

LED to GND, SUP > 4 V

3.3

V

CTB to GND, VDA = 3.3 V

1.65

V

CTS−CTB Absolute Offset Voltage

CTS−CTB±125

mV

Fault Response Time

5 mA ≤ IDIFF < 15 mA

135

ms

Fault Response Time

15 mA ≤ IDIFF < 30 mA

70

ms

Fault Response Time

30 mA ≤ IDIFF

20

ms

CTG Comparator Threshold

CTG to GND, VDA = 3.3 V

CTG GN Trip Frequency

CTG to GND

7kHz

GN Response Time

Continuous GN Fault

50

ms

Internal Oscillator Frequency

FAC = 60 Hz ±0.1

25

MHz

Under Voltage Detect

VAC to GND, R7 = 1 MW, ±1%

MLD/SCM Max Clamp Current

IMLD Max Sink Current

MLD/SCM Pull Down Current

MLD = 1 V

1mA

PTT Internal Pull Up Resistance

PTT = 0 V

50kW

PTT Debounce TimePTT Assert Low

First ST Timer

VDA > 3 V

1s

Periodic ST Timer, Pass

Steady State, ST Pass1

min

Periodic ST Timer, Fail

ST Fail12

AC cycle

Consecutive ST Failure Timer

ST Fail Counter, Enable SCR

7

times

LED Blink Frequency

First ST Failure

4

Hz

ST Cycle GF Pass Window

IDIFF Ground Fault

7mA

MLD Pin Check Wait Time to Enable LED

No MLD signal

64

ms

MLD Pin Continuity Pass

Input Frequency

60

Hz

LED Blink Frequency

No MLD signal

4

Hz

MLD/SCM Pin Check Wait Time to Enable
SCR

No MLD signal

4

s

1.95
2

80

4.75

87

16

V

95

Vrms

400

mA

ms

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

www.onsemi.com
4

NCS37021
APPLICATIONS INFORMATION

MOV

Sense Coil 1:1000

RESET

GN Coil 1:250

Line Hot

FUSE

C7

C9

C6
L1

D2

D4

R5

R4A

R6

R12 R13

DB

Q2

D5

1

C5

R7

CTG

SCM

CTB

CTS

R4B

R11

R10

GFT

NCS37021

Q3

R9

REF

LED

GND

DRF

R2

C2A

SUP

AUX

MLD

PTT

C2B
LED

TEST
R1C

R1D
C1
R1A

C10

R1B

Figure 2. GFCI Receptacle Application Diagram

www.onsemi.com
5

R8

C3

U1

IDF

Q1

16

SCR

CTO

R3

D1

C8

L2

D3
C4

Load Neutral

SolenoidLine Neutral

Load Hot

D6

NCS37021
Table 5. RECOMMENDED EXTERNAL COMPONENTS
Component Type

Instance

Value

SCR

Q1, Q2

−

Note

NPN

Q3

−

Diode Bridge

DB

−

Diode

D1, D2, D3, D4, D5

−

LED

D6

−

LED for self−test failure

Capacitor

C1

1 mF

SUP pin holding capacitor

Capacitor

C2A, C2B

1 mF

Internal 3.3 V and 1.8 V reference filter cap

Capacitor

C3

10 nF

SCR gate filter capacitor

Capacitor

C4

56 nF

Anti−aliasing filter (1 kHz corner frequency)

Capacitor

C5

1 nF

High frequency filter

Capacitor

C6

33 nF

Differential current filter capacitor

Capacitor

C7

1 nF

CTB bias filter

Capacitor

C8

10 nF

Ground Neutral CT resonance capacitor

Capacitor

C9

120 pF

Ground Neutral CT AC coupler

Capacitor

C10

100 pF

Ground noise filter

Resistor

R1A, R1B, R1C,
R1D

25 kW

Current limit resistors

Resistor

R2

1 MW

MLD current limit/under voltage attenuator

Resistor

R3

20 kW

Differential filter resistor

Resistor

R4A

36 kW

Precision resistor (1%), Differential burden/CT low pass filter

Resistor

R4B

50 W

CT low pass filter

Resistor

R5

370 W

Differential burden resistor, 1% tolerance

Resistor

R60−200 W

Sets the GN sensitivity

Resistor

R7, R13

4.7 kW

Sets the SCR gate current

Resistor

R8

15 kW

Controls the self−test current in the Q3

Resistor

R9

3.3 kW

LED current limiter resistor

Resistor

R10

10 kW

Sets the current in the base of Q3

Resistor

R11

10 kW

SCR gate discharge current

Resistor

R12−

Current limit resistor for SCM

Inductor

L1, L21k@
100 MHz

Current Transformer

CT1

1000

Differential current transformer

Current Transformer

CT2

250

GN current transformer

MMBT6517LT1−D

CIM05U102, CT RF filter

www.onsemi.com
6

NCS37021
MOV

SwitchSense Coil 1:1000

GN Coil 1:250

Line Hot

Load HotLine Neutral

Load Neutral
D2

Solenoid

C7

C9

C6
L1

C8

L2

D3

R5

C4

R6

R12

1

C5

R13
Q1
R7

CTG

SCM

CTB

CTS

R11
16

U1

IDF

R10

GFT

NCS37021

Q3
LED

R9

REF

LED

GND

DRF

R8

C3

SCR

CTO

R3

Q2

D5

R4A

R4B

D1

D4

D8

C2A

SUP

AUX

MLD

PTT

C2B

TEST
R2

DB

R1B

R1D

R1A

R1C

C1

C10

Figure 3. Circuit Breaker Application Diagram (Half Bridge Supply)

FUNCTIONAL DESCRIPTION (Refer to Application Circuit)• 1.65 V reference for the CT,• 25 MHz oscillator dynamically trimmed to the AC line

The NCS37021 provides ground fault, grounded neutral
and self−test protection solution for a single IC controller
per the UL943 standard.
The key internal blocks include:• 12 V shunt regulator,• Precision bandgap reference,• Two 3.3 V linear regulators (one for the digital IO andone for the analog core circuit),• 1.8 V linear regulator for digital core circuit,• Sense amplifiers with VOS cancellation,

frequency,• 10−bit SAR ADC,
• Comparators, digital filters, and digital control logic.
The SUP pin provides the bias voltage for the analog anddigital IO via two 3.3 V linear regulators, as well as for the
1.8 V linear regulator for the internal digital circuitry. For
safety operation this pin is clamped at ~12 volts by the shunt
regulator.

www.onsemi.com
7

NCS37021
If a very high GF occurs and a greater than 230 mV signal
occurs across the CT for greater than 1.4 ms, the SCR will
be immediately enabled.Note that the above equation is for
an ideal CT. In practice, the GF threshold can be +/−20%
different and should be empirically set.
When the PTT pin is enabled for greater than 16 ms a ST
cycle will be enabled. If the ST cycle passes, the SCR will
be enabled and the LED will blink once (for breakers, theLED can blink until power down). If the ST cycle fails, theLED will keep blinking and SCR will not be fired. The PTT
pin has an internal 50 kΩ pull up resistor. This pin is a CMOS
input with hysteresis. To enable the PTT function, the input
voltage should go below 1.2 volts.
The MLD pin monitors the phase and zero cross for the
AC supply. The MLD circuit clamps the pin voltage to GND
and REF. When the pin is clamped at REF, the current on the
MLD Pin is compared to an internal current thresholdrefence such that if the VAC mains voltage is below
87 VRMS, the ST GF threshold will be reduced by 50%.
This function provides for an AC under voltage detection
which allows for the ST cycle to pass with a lower GF
threshold. The AC UVD threshold can be user
programmable by changing R2.
Grounded Neutral detection is accomplished by theaddition of a GN coil to generate a “dormant oscillator”
circuit. When a GN condition occurs, both the sense coil andGN coils are mutually coupled and the GN amplifier will
oscillate. This oscillation can be observed at the CTG pin.
The maximum time required during power up is 150 ms. The
sensitivity of the GN detection can be changed by capacitor
C8 and resistor R6. The frequency of this CTG oscillationneeds to be in the 2 kHz to 7 kHz.
The internal oscillator is trimmed to 25 MHz. If the ACmains frequency changes it can impact the accuracy of the
GF and GN sensitivity, for lower ADC mains frequency, theGF trip threshold response time will be slower and the GN
sensitivity will be lower.
When the IC logic enables the SCR gate driver circuit, theSCR pin will go high 2 ms after zero cross (for AC Mains at
60 Hz) for ~6ms covering the duration of the MLD halfcycle.
Contact onsemi for self−test requirement details andnoise filtering recommendations.

At POR detection (REF > 2.475) the logic is reset and thebias circuitry is enabled. The MLD pin is continuallychecked for an input signal of 60 Hz. If the MLD has not
toggled in approximately 64 ms, the fault condition is sent
to the SCR block. If, after 4 seconds, the fault condition isstill present, the SCR will fire for approximately 20 ms. Thistiming will continue if the fault condition remains.
The first self−test (ST) cycle will occur at 1 second andthereafter every 1 minute. During the ST cycle the GFT pin
will be enabled at the positive MLD phase for ~16 ms andthe CT current (set at 8 mA RMS, R8) will be verified for
positive or negative MLD phase. During the next negative
half cycle, at the beginning of the cycle the SCR’s anodevoltage will be pre−biased by the SCM pin to ~3.3 volts
which will be verified by internal logic. The SCR will thenbe enabled and the SCR’s anode voltage will be monitoredby the SCM pin. If the anode voltage goes below ~2.1 volts,
the SCR will be disabled after at least 250 us verification
check and the ST logic will register a passing ST cycle. If a
ST cycle fails due to a low GF detection, the LED blinking
logic will be enabled. After a self−test failure, the testing
frequency is accelerated to a faster interval 12 MLD. If
seven consecutive ST cycles fail the SCR will be enabled. If
a ST cycle passes before any of the 7 consecutive ST cycle
counter, the ST logic will be reset and a ST cycle will occurin 1 minute.
The CT is biased approximately at 1.65 volts. The sense
amplifier monitors the ground fault current. This current isconverted to a voltage level at the CTO pin which is the input
to the ADC (IDF pin). The resistor R4 sets the GF threshold
per the following equation, and it needs to be above thisthreshold for > 8.35 ms within an AC Mains period:
I diff +

RCT1
fAC
LCT1

0.160

CT 1
R 4A

ǒR CT1 ) R5 ) 2pfACLCT1Ǔ
ǒRCT1 ) 2pfACLCT1Ǔ

(eq. 1)is DC winding resistance of differential CT
is AC mains frequency
is Inductance of differential CT

The ground fault detection circuit has different levels oftime delay before the SCR is enabled:
6 mA to 15 mA≤ 135 ms
15 mA to 30 mA≤ 70 ms> 30 mA≤ 20 ms

www.onsemi.com
8

NCS37021
WAVEFORMS
Ch1: SCM, Ch2: SCR, Ch3: MLD, Ch4: GFT

Ch1: CTG Ch2: SCR, Ch3: MLD, Ch4: REF

Figure 4. Self Test

Figure 5. Grounded Neutral Fault Detection

Ch1: IDF Ch2: SCR, Ch3: MLD, Ch4: REF

Ch1: SCM Ch2: SCR, Ch3: MLD, Ch4: PTT

Figure 6. Ground Fault Detection

Figure 7. PTT Self Test

ORDERING INFORMATION
Device
NCS37021MNTWG

Package

Shipping†

QFN16(Pb−Free)3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

www.onsemi.com
9

NCS37021
PACKAGE DIMENSIONSQFN16 3x3, 0.5P
CASE 485FQISSUE B

onsemi,, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of theinformation, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or useof any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance mayvary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any licenseunder any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATIONONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales

TECHNICAL PUBLICATIONS:Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com◊

www.onsemi.com
10