AN90006

Circuit design and PCB layout recommendations
for GaN FET half bridges
Rev. 1.1 — 13 February 2019

Application note

Document information
Information

Content

Keywords

GaN FET, Half bridges, Circuit design, PCB layout

Abstract

This appplication note explains the Recommendations for circuit design and PCB layout when
applying GaN FET half bridges.

AN90006

Nexperia

Circuit design and PCB layout recommendations for GaN FET half bridges

1. Diode-free bridges
Power GaN FETs are nearly ideal switches for many applications. A particular advantage in bridge
circuits is that they can carry the freewheeling current without the need of an additional anti-parallel
diode. The diagrams in Fig. 1 compare a traditional high-voltage half bridge to a half bridge madewith GaN FET devices. In the traditional half bridge each switch (shown here as an IGBT) is pairedwith a freewheeling diode. Because the HEMT channel exists in pure, undoped GaN, there is noparasitic p-n junction to provide an unwanted current path, and bidirectional flow of majority carriers
can be realized in the channel.
Vdd

Hi/Lo
DRIVER

Vdd

Hi/Lo
DRIVER

aaa-029628

Fig. 1.

AN90006

Application note

Comparison of a traditional high-voltage half bridge to a GaN FET half bridge.

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges
In Nexperia’s two-die GaN FET the freewheeling current does indeed flow in the body diode ofa silicon MOSFET, but because the silicon MOSFET is a low voltage part, the injected charge
is very small. Indicated in Fig. 2 are the current paths for three modes of operation. In thereverse conducting mode the conduction loss may be reduced by enhancing the silicon MOSFET(driving VGS > VGS(th)). As indicated in Fig. 2, the voltage drop from source to drain decreases by
about 0.8 V with a 5 A reverse current when the gate is enhanced.

aaa-029630

aaa-029629

aaa-029631

b. Reverse conduction
VGS < VGS(th)a. Forward conduction

c. Reverse conduction
VGS > VGS(th)aaa-029632

15
(A)

(1)

10

(2)

5

(3)

I

0

III

(4)

-5
(5)

-10
-15

-3

-2

-1

0

1

2

(VDS)

3

(1) VGS = 8 V(2) VGS = 4 V(3) VGS = 3 V(4) VGS = 0 V, 1 V, 2V(5) VDS
Fig. 2.

AN90006

Application note

Current paths in the GaN FET switch for three operating modes, and thecorresponding I-V characteristic.

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AN90006

Nexperia

Circuit design and PCB layout recommendations for GaN FET half bridges
Some transistor technologies include junctions which could, if permitted, serve the function of
the freewheeling diode, the body diode of a MOSFET being one example. The reverse recovery
charge for these devices will be much larger than for a GaN FET with similar ratings. The graphs
shown in Fig. 3 compare the total reverse-recovery charge for a Nexperia GaN FET to a low-QRR(CFD series) superjunction silicon MOSFET. The QRR ratio, Si/GaN, varies with exact partnumbers.

(V)

aaa-029633

600
Vd (V)Id (A)

500

60
50

(A)

(V)

aaa-029634

600
Vd (V)Id (A)

500

60
50

400

40

400

40

300

30

300

30

200

20

200

20

100

10

100

10

0

0

0

0

179 nC

-100

-10

-100

-200

-20

-200

-300

-30

-300

-400

-40

-400

-50
300

-500

-500

0

50

a. GaN FET
Fig. 3.

100

150

200

250

(ns)

(A)

-10
-20

2790 nC

-30
-40

0

50

100

150

200

250

(ns)

-50
300

b. CFD series superjunction Si MOSFET

Reverse recovery charge test result for a GaN FET (left) and a CFD series superjunction Si MOSFET(right).

AN90006

Application note

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

2. Circuit-design recommendations
The high switching speed of GaN FET devices necessitates observation of a few specificcircuit-design guidelines. Before explaining these requirements, however, one simplification may bementioned: negative gate drive is neither necessary nor recommended. Due to the high thresholdvoltage (Vth = 4 V typical) and extremely low Miller capacitance (QGD = 6 nC typical), there isadequate turn-off margin with a simple 0 V to 10-12 V drive.
While high-speed switching brings the benefit of reduced power loss, the inherent transientscan create stability problems. Specifically, the hightransient during switching, combined withparasitic inductances, leads to transient voltages in the circuit. These voltage transients caninterfere with the gate and the driver of the device, and, in the worst case, creates sustained
oscillation that must be prevented for safe operation of the circuit. The following section provides
guidance on how to eliminate oscillation and how to achieve high switching current with acontrolled.
VBUS

DC busdriverRG

RCDCL(place as close as
possible to drain pin)

Q2

VSdriver

RG

Vo

Q1
RSN

RCSN

C SN

aaa-029331

Fig. 4.

Half-bridge switching circuit

2.1. Solutions to suppress oscillation
To avoid sustained oscillation, it is important to minimize noise generation, to minimize noise
feedback, and to damp the ringing energy resulting from the high current and voltage transients.
This can be achieved with the recommendations outlined below using a half-bridge switching circuitin Fig. 4 as an example.
1. Optimize the PCB layout to minimize external parasitic inductances and associated feedback.
Details follow in Section 3 of this application note.
2. Use a DC-link RC snubber [RCDCL in Fig. 4]. The DC rail or DC-link, when decoupled with a
low-ESR fast capacitor, can be considered a high-Q C-L network at high frequencies (with "L"being the feed inductance of the DC bus). This can interact with the devices during transientsand lead to ringing. Adding an RC snubber across the DC-link close to the drain pin of the highside device can effectively absorb the ringing energy, suppressing potential oscillation. Thiseffect can be seen where the high-frequency ringing at 25 A turn-off is substantially dampedwith the RCDCL. Since this snubber is not inserted at the switching node, it does not add
switching loss to the circuit.
Note: This is recommended even for single-ended non-half-bridge designs. The
practical values of the RCDCL can be two sets of 6 - 10 Ω / 0.5 W SMD resistors
in series with a 10 nF / 600 - 1000 V ceramic SMD capacitor, or one 3 - 4 Ω / 1 W
resistors in series with a 10 - 20 nF / 600 - 1000 V capacitor if space is limited.
3. Adding a switching-node RC snubber [RCSN in Fig. 4] can further reduce high-frequency
ringing and help control
transients at high operating currents. The effect of the RCSN on theswitching waveform can be seen at a switching current > ISWL, see Table 1. Unlike the RCDCL,
the capacitance of the RCSN does increase switching loss. The degradation in efficiency is
minimal however, when using the recommended snubber parameters given in the data sheet,and summarized in Table 1.

AN90006

Application note

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

2.2. Gate drive and bootstrap supply
Since high slew rates of the order of 50 - 100 V/ns are normal, the high-side gate-driver musthave good common-mode transient immunity. Apart from that consideration, there are no special
requirements for the Hi/Lo gate driver used with Nexperia’s GaN FET switches. As with any
insulated-gate power transistor, the gate-drive current should be consistent with the desired turn-ontime and total gate charge. As mentioned in the opening paragraph of Section 2, use of a negativegate voltage in the off state is not recommended. Selecting a gate driver with a lower drive current
can be appropriate for reducing . Drivers with 0.5 A output current have been used with goodresults, for example. Nexperia GaN FETs in the TO-247 package include an integrated ferrite beadin series with the gate.
The bootstrap, or floating, supply for the high-side gate drive comprises components R4, D1,
C12, and C13 in Fig. 8. The junction capacitance of D1 contributes directly to switching loss,
and so a fast, low capacitance diode should be used. Resistor R4 is critical for limiting the inrush
charging current; a value of 10 - 15 Ω works well. If an isolated DC-DC converter is used for thehigh-side supply, the isolation capacitance plays the same role as the junction capacitance of
D1 in the bootstrap supply. Inductance in series with this capacitance will create an additional
resonance which will be excited with each switching transient, so careful layout applies here. Useof a common-mode choke in the floating supply can be helpful.

2.3. Summary of circuit-design recommendations
•
•
•
•
•

•
•

AN90006

Application note

SMD mounting is recommended for all snubber components.
A gate resistor (RG) is required for all devices.
The RCDCL snubber reduces voltage ringing due to interaction of the GaN FET with the bypass
network.
The RCSN snubber enables increased output power while slightly reducing light and medium
load efficiency.
The RCSN implementation in a half-bridge has the advantage of allowing a higher peak turn-off
switching current due to the reduction of theseen by the freewheeling device as the main
active switch turns off.
Gate ferrite beads (FB1) may be required for future devices in other package types;
TO-247 devices have built-in ferrite beads hence no external FB1 is needed.
Refer to Nexperia Application Note AN90005 for an explanation of data-sheet limitations andrelevant recommendations for when to use a switching-node snubber.

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

2.4. Required and recommended external components
The recommended components of the half-bridge circuit in Fig. 4 are summarized in Table 1.
They have been tested and verified to prevent oscillation for safe, reliable operation with therecommended gate drive voltage ranges shown. Using a higher “on” voltage is not recommended
and may increase the propensity for oscillation and will require a larger gate resistor. Using a lower“on” voltage may increase switching and conduction losses due to increased RDS(on).
Table 1. Recommended components for half-bridge circuit
Parameters \ Part Number
GaN041-650WSA

GaN063-650WSA

Package

TO-247

TO-247

Recommended Gate-Drive Voltage

0 V, 10 - 12 V

0 V, 10 - 12 V

Recommended Gate Resistor (Rg)30 Ω30 - 45 Ω

Gate Ferrite Bead (FB1)

Not required

Not required

Recommended RCSN

200 pF + 5 Ω

100 pF + 10 Ω

Recommended RCDCL(10 nF + 8 Ω) x 2(10 nF + 8 Ω) x 2

ISWL

17 A

14 A

2.5. To verify GaN FET stable operation
To verify adequate operational margin without oscillation, as a minimum observe the VDS
waveforms at the turn-on and turn-off switching edges at the application’s maximum drain current.
This may occur during start-up or at the application’s maximum load step. A double-pulse or
multi-pulse test is highly recommended utilizing the actual layout, with current levels at or greaterthan 120 % of the application’s anticipated peak current. Verify that the ringing on the VDS
waveform at the transition edges is adequately damped.

AN90006

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

3. PCB layout
The parasitic inductances of the input (gate) and output (power) loops contribute significantly toovershoot, ringing, and stability in general.

3.1. Pin assignment
Nexperia GaN FETs in the TO-247 package use a Gate-Source-Drain pin assignment, which differsfrom that used for older transistors in the same package. The reason for centering the source
rather than the drain is that the source is the common node to both gate and power loops. This
minimizes coupling of the two loops, as illustrated in Fig. 5.

G

gate
loop

D

S

power
loop
aaa-029293

a. Conventional pins assginment
Fig. 5.

AN90006

Application note

G

ZL

gate
loop

S

D

ZL

power
loop
aaa-029294

b. Nexperia pin assigment

Illustration of the de-coupling achieved with a centered-source pin assignment.

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

3.2. Power loop
Although the various charges are low with GaN FET switches, they are not zero, and there will be avery fast transient current during switching as these charges are redistributed. This current will flowfrom the positive supply node, through both transistors to the negative supply node. To minimize
ringing due to this transient, inductances in this path should be minimized. Referring to Fig. 6,
these inductances are indicated as LS1, LD1, LS2, and LD2. To minimize these, low impedance
power and ground traces, or planes, should be used and bypass capacitance and DC-link snubber
should be placed as close as possible to the transistors. It is not critical to minimize inductanceLout since it is in series with the load inductance, and to a first approximation simply adds to it. The
connection between the high-side (Q1) source pin and the low-side (Q2) drain pin should also bevery short. Placing the two transistors back-to-back on a common heat sink helps accomplish this.
Shown in Fig. 7 to Fig. 10, is a portion of the layout of a Nexperia half-bridge evaluation board,
indicating the placement of the power transistors.
Vdd
LD1

LD_int1

LG1

LG_int1

LS_int1

+HVdc

LS1

outloop-looptransient current

LD1

LD2

Q1

Hi/Lo
GATE
DRIVERCout

L_loadL

LD_int2

LS1
Lout

Lload

LG2
LD2

LG_int2

Cout

LS_int2

Q2
LS2

LS2
aaa-029640

aaa-029639

a. Only elements external to GaN FET packages
Fig. 6.

Lout

b. Both internal and external parasitic elements

Parasitic elements in the power loop.

AN90006

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges
Details of the power loop layout are highlighted in Fig. 9. To minimize inductance, the drain of Q1 isconnected directly to the power plane; the source of Q2 is connected directly to the ground plane.
The power and ground planes are on internal layers of the PCB, not visible in the figure. The
switching node is formed by the wide trace connecting the source of Q1 to the drain of Q2.

Fig. 7.

PCB layout - Power-stage

AN90006

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges
HV

+5 V

R17
10 Ω

R18
10 Ω

R19
10 Ω

C33
10 nF

C34
10 nF

C35
10 nF

C4
10 nF

C5
10 nF

HV

C6
10 nF

C7
0.1 µF

PGND

VG

R3
10 MΩ

PGND

R4
C10
0.1 µF
TP1

VIA
VIB

TP3

VDDI
PWM_U_LO

GND1
DISABLE
DT
n.c.

AGND

HV

D1

AGND

PWM_U_HI

TP4

10 Ω

C11
0.1 µF

VDDI1

R7
12 kΩ

AGND

U2
1

16

2

15

3

14

4
5

VDDA
VOA

C12
0.1 µF

C13
10 µF

GNDA

Q1
GaN063-650WSA
R11
G
30 Ω

D
S

R13
15 Ω
C24
47 pF

R14
15 Ω

TP2
PFC103100-1

SI8230

6

11

7

10

8

9

VDDB
VOB

C14
0.1 µF

C15
10 µF

GNDB

Q2
GaN063-650WSA
R12
G
30 Ω

D
S

R15
15 Ω

R16
15 Ω
TP5

C25
47 pF

AGND

PGND

PGND
aaa-029641

Fig. 8.

PCB layout - Corresponding schematic section

Fig. 9.

PCB layout - Detail of power connections

AN90006

Application noteFig. 10. PCB layout - Detail of bypassing: SMD
capacitors on PCB backside

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges
Illustrated in Fig. 11 is an alternative placement where the GaN FETs are side-by-side, rather
than back-to-back, as in Fig. 7 to Fig. 10. Inductances are higher with this arrangement, but it issometimes preferable for manufacturing reasons.
+5 V
C32
1 µF
TP1

VCC
C33
1 µF

GND1

C78
10 pF

PWM_H

VIA

PWM_L

VIB
VDDI

C79
10 pF

TP2

GND1

GND1

GND1
DISABLE

GND1

+5 V
R69

R71

100 kΩ

0Ω

R24

DT

12 kΩ
(65 kΩ
for
8274)

n.c.
VDDI1

1

16

2

15

3

14

5

R22

10 µF

4.7 Ω
D3

AGND

U7

4

C34

VDDA
VOA

R70

GNDA

30 Ω

C39
1 µF

GH

PB1

G

40
R45
10 kΩ

6

11

7

10

8

9

VCC

VDDB
VOB

R42

GNDB

30 Ω

C44
1 µF

C43
4.7 µF

GL

AGND

AGND

TP4
D

R28
15 Ω

DC OUT

S
C75
47 pF
R43
10 Ω

R44
10 Ω

R55
10 Ω
C48
10 µH

L6
HF-TOROID
C14
10 nF
Q3
GaN041-650WSA

GL

GH

VS

SI8230GND1

Q2
GaN041-650WSA

C38
10 µF

FB2

G

40

TP8

R47
10 kΩ

D

R51
15 Ω

C22
10 nF

C23
10 nF

C62
680 µFC49
680 µFC72
680 µFC67
680 µF

TP5

S
C74
47 pF

5 4 3 2AGND

aaa-029642(a) Schematic diagram

AN90006

Application note

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AN90006

Nexperia

Circuit design and PCB layout recommendations for GaN FET half bridges(b) PCB layout
Fig. 11. Totem pole PFC PCB.
Capacitance on the switching node, indicated as Cout in Fig. 6, adds directly to switching loss, andso the total area of copper which forms the switching node should be kept low, but not so low thatinductance becomes significant. A typical 4-layer board with 12 mils (0.3 mm) between outer trace2
2
and internal ground plane adds about 15 pF / cm . At 100 kHz switching, each 1 cm would add2
P = 1/2 CV fs = 120 mW switching loss, for example.

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

4. Heat Sink connection
The heat sink should be connected to an AC ground. In the evaluation board of Fig. 7 to Fig. 10
the heat sink is electrically connected to the negative supply, or ground plane. Both low-side andhigh-side transistors are insulated from the heat sink. For the low-side transistor the capacitance
between tab and heat sink is not critical, since the tab of the TO-247 is connected to the source.
This transistor could be mounted directly to the heat sink, but the possibility that load current could
flow in the heat sink must be allowed for. If a reliable connection between tab and heat sink iseither not possible or not desirable, use of an insulator is necessary. For the high-side transistor,
capacitance between the TO-247 mounting base and the heat sink will add to switching loss, andso a thick and/or low permittivity insulator should be used.

4.1. Gate-drive loop
As with the output loop, minimizing inductance in the input, or gate-drive loop is critical. Particularly
important is the source inductance (LS2 in Fig. 6, for example), which is common to both loops.
Any voltage developed across this inductance due to a change in the output current,,
will appear in the input loop. The gate–source loop should be made as compact as possible
to minimise the gate loop inductance. The gate-source loop inductance and GaN FET input
capacitance form a resonant tank and will have a corresponding resonant frequency. The resonant
circuit will be excited into oscillation by the back EMF produced by thein the source inductance.
Fig. 12 Usually the resonant frequency of the gate-source loop will be less than 200 MHz. A ferrite
bead fitted in series with the gate can have a beneficial effect by “de-Qing” the gate-source
resonant circuit. For this reason, a small ferrite bead is integrated inside the TO-247 package.
For future Nexperia GaN FETs where it is not integrated, the ferrite bead should be located as
close as possible to the gate pin of the GaN FET so that the damping is applied to the device gate
where it is needed. A gate ferrite bead is needed for both single-ended non half-bridges as well as
half-bridge designs.
Vdd

Ld

Ld_int

Cgd_GaN
Rg_int1

GaN
HEMT

Cds_GaN

M1
LV_MOS

Cds_MOSCgs_GaN

Mid-Node
Cgd_MOS

Vg

Rg

Lg

Lg_intRg_intCgs_MOSResonant circuit

Ls_intLs

aaa-029643

Fig. 12. Input Loop for a cascode GaN FET

AN90006

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AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

4.2. Summary of PCB layout recommendations
•
•
•
•
•

Place the RCDCL as close as possible to the drain pin of the high-side GaN FET and ground it to
the large ground plane.
Use a large area ground plane for an overall low-noise base potential.
Arrange the gate drive circuit on one side and the output circuit on the other side of the PCB tominimize noise feedback from the output loop to the input loop.
Place the driver circuit close to the gate of the device.
Shorten the power loop by arranging the high-side and low-side devices close-by.

5. Revision history
Table 2. Revision history
Revision number

Date

Description

1.1

20190213

AN90006

1.0

20181112

Preliminary AN90006

AN90006

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Circuit design and PCB layout recommendations for GaN FET half bridges

6. Legal information
Definitions
Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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Circuit design and PCB layout recommendations for GaN FET half bridges

List of Tables
Table 1. Recommended components for half-bridge circuit. 7
Table 2. Revision history....................................................15

AN90006

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Rev. 1.1 — 13 February 2019

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AN90006

Nexperia

Circuit design and PCB layout recommendations for GaN FET half bridges

List of Figures
Fig. 1. Comparison of a traditional high-voltage half
bridge to a GaN FET half bridge......................................... 2
Fig. 2. Current paths in the GaN FET switch for threeoperating modes, and the corresponding I-V characteristic. 3
Fig. 3. Reverse recovery charge test result for a GaN
FET (left) and a CFD series superjunction Si MOSFET(right).................................................................................... 4
Fig. 4. Half-bridge switching circuit...................................... 5
Fig. 5. Illustration of the de-coupling achieved with acentered-source pin assignment.......................................... 8
Fig. 6. Parasitic elements in the power loop........................ 9
Fig. 7. PCB layout - Power-stage...................................... 10
Fig. 8. PCB layout - Corresponding schematic section...... 11
Fig. 9. PCB layout - Detail of power connections...............11
Fig. 10. PCB layout - Detail of bypassing: SMD
capacitors on PCB backside..............................................11
Fig. 11. Totem pole PFC PCB............................................13
Fig. 12. Input Loop for a cascode GaN FET...................... 14

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AN90006

Nexperia

Circuit design and PCB layout recommendations for GaN FET half bridges

Contents
1. Diode-free bridges........................................................ 2
2. Circuit-design recommendations................................ 5
2.1. Solutions to suppress oscillation................................. 5
2.2. Gate drive and bootstrap supply................................. 6
2.3. Summary of circuit-design recommendations.............. 6
2.4. Required and recommended external components..... 7
2.5. To verify GaN FET stable operation............................ 7
3. PCB layout.................................................................... 8
3.1. Pin assignment............................................................ 8
3.2. Power loop...................................................................9
4. Heat Sink connection................................................. 14
4.1. Gate-drive loop.......................................................... 14
4.2. Summary of PCB layout recommendations............... 15
5. Revision history..........................................................15
6. Legal information........................................................16© Nexperia B.V. 2019. All rights reserved

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Date of release: 13 February 2019

AN90006

Application note

All information provided in this document is subject to legal disclaimers.

Rev. 1.1 — 13 February 2019

© Nexperia B.V. 2019. All rights reserved

19 / 19