RS9112C, RS9113C, RS9114C

RS911xC 3.3-V and 2.5-V LVCMOS High-Performance
Clock Buffer Family
1 FEATURES••3 DESCRIPTIONSHigh-Performance 1:2, 1:3, 1:4 LVCMOS

Three different fan-out variations, 1:2 to 1:4, are

Clock Buffer Family

available. All of the devices are pin-compatible toSupply Voltage: 3.3 V or 2.5 V
fmax = 250 MHz for 3.3 V

each other for easy handling.

fmax = 180 MHz for 2.5 V

All family members share the same high performing•Operating Temperature Range: –40°C to 85°C

characteristics such as low skew, and wide operating•Available in 8-Pin TSSOP Package

temperature range.
The RS911xC supports an asynchronous output

2 APPLICATIONS•General-Purpose Communication, Industrial,

enable control (1G) which switches the outputs into aand Consumer Applications

low state when 1G is low.
The RS911xC family operates in a 2.5-V and 3.3-V
environment and are characterized for operation from–40°C to 85°C.

Device Information (1)PART NUMBER

PACKAGEBODY SIZE (NOM)

TSSOP83.00 mm × 4.40 mm

RS9112C
RS9113C
RS9114C(1)

For all available packages, see the orderable addendum at theend of the data sheet.

4 Functional Block Diagram

REV A.1

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RS9112C,RS9113C,RS9114C
Table of Contents
1 FEATURES ............................................................................................................................................................................... 1
2 APPLICATIONS ...................................................................................................................................................................... 1
3 DESCRIPTIONS ...................................................................................................................................................................... 1
4 Functional Block Diagram .................................................................................................................................................... 1
5 Revision History ..................................................................................................................................................................... 3
6 Pin Configuration and Functions ........................................................................................................................................ 4
7 SPECIFICATIONS ................................................................................................................................................................... 5
7.1 Absolute Maximum Ratings .......................................................................................................................................... 5
7.2 ESD Ratings ...................................................................................................................................................................... 5
7.3 Recommended Operating Conditions ......................................................................................................................... 5
7.4 Electrical Characteristics ................................................................................................................................................ 6
7.5 Switching Characteristics............................................................................................................................................... 7
7.6 Parameter Measurement Information ........................................................................................................................ 88 Detailed Description ...........................................................................................................................................................108.1 Overview .........................................................................................................................................................................108.2 Functional Block Diagram............................................................................................................................................108.3 Feature Description ......................................................................................................................................................108.4 Device Functional Modes ............................................................................................................................................109 Application and Implementation ......................................................................................................................................119.1 Application Information ...............................................................................................................................................119.2 Typical Application ........................................................................................................................................................11
9.3 Design Requirements ...................................................................................................................................................11
9.4 Detailed Design Procedure .........................................................................................................................................1110 Power Supply Recommendations ..................................................................................................................................1210.1 Power Considerations ................................................................................................................................................1211 PACKAGE OUTLINE DIMENSIONS .............................................................................................................................132 / 13

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RS9112C,RS9113C,RS9114C
5 Revision History
Note: Page numbers for previous revisions may different from page numbers in the current version.
VERSION

Change Date

Change Item

A.1

2024/02/27

Initial version completed

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RS9112C,RS9113C,RS9114C
6 Pin Configuration and Functions
PW Package 8-Pin TSSOP Top View

Pin Functions
PIN
NAME

RS9112CTYPE

DESCRIPTION

1InputInput Pin

22Input

Output Enable

Output

LVCMOS output. Unused outputs
can be left floating.

RS9113C

RS9114C

1

LVCMOS CLOCK INPUT
CLKIN

1

CLOCK OUTPUT ENABLE
1G2

LVCMOS CLOCK OUTPUT
Y0333

Y1—88Y2—

55Y3——

7666

Power

2.5-V or 3.3-Vdevice supply444GND

Device ground

SUPPLY VOLTAGE
VDD
GROUND
GND

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RS9112C,RS9113C,RS9114C
7 SPECIFICATIONS
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN

MAX

UNIT

VDD

Supply voltage

-0.5

3.9

V

VIN

Input voltage (2)-0.5

VDD+0.5

VVO

Output voltage (2)-0.5

VDD+0.5

V

IIN

input current-2020mA

IO

Continuous output current-5050mA

TJ

Maximum junction temperature

125°C

150°C

Tstg
(1)
(2)

Storage temperature-65

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 3.9 V maximum.

7.2 ESD Ratings
VALUE
V(ESD)(1)(2)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)Charged-device model (CDM), per JEDEC specification
JESD22-C101(2)UNIT±3000±1500

V

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

ESD SENSITIVITY CAUTION
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MINNOMMAX

3.3V supply

33.3

3.6

2.5V supply

2.3

2.5

2.7

VDDSupply voltage

VIL

Low-level input voltage

VIH

High-level input voltage

VTH

Input threshold voltage

tr/ tfInput slew rate

twMinimum pulse width at
CLKIN

VDD = 3.0 V to 3.6 V

1.8

VDD = 2.3 V to 2.7 V

2.75

fCLK

LVCMOS clock Input
Frequency

VDD = 3.0 V to 3.6 V

DC250

VDD = 2.3 V to 2.7 VDC180TA

Operating free-air temperature-4085

VDD = 3.0 V to 3.6 V

VDD/2 – 600

VDD = 2.3 V to 2.7 V

VDD/2 – 400

VDD = 3.0 V to 3.6 V

VDD/2 + 600

VDD = 2.3 V to 2.7 V

VDD/2 + 400

VDD = 2.3 V to 3.6 V

5 / 13V
mV
mV

VDD/21UNIT

mV
4

V/nsnsMHz°C

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RS9112C,RS9113C,RS9114C
7.4 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINOVERALL PARAMETERS FOR ALL VERSIONS
1G = VDD; CLKIN = 0 V or VDD; IO = 0mA; VDD = 3.6 V
IDD
Static device current
1G = VDD; CLKIN = 0 V or VDD; IO = 0mA; VDD = 2.7 V
1G = 0 V; CLKIN = 0 V or VDD; IO = 0IPD
Power-down current
mA; VDD = 3.6 V or 2.7 V
VDD = 3.3 V; f = 10 MHz
Power dissipation capacitance per
CPD
output (2)VDD = 2.5 V; f = 10 MHz
IITYP (1)MAX3.510

1.563460mA10.7

VI = 0 or VDD, VDD = 3.6 Vor2.7 V

10Input leakage current at CLKIN

VI = 0 or VDD, VDD = 3.6 V or 2.7 V

28

VDD = 3.3 V

42

VDD = 2.5 V

49

Output impedance

fOUT

Output frequency

µA
pF

7.4

Input leakage current at 1G

ROUT

UNIT

µA
Ω

VDD = 3 V to 3.6 V

DC

250

VDD = 2.3 V to 2.7 V

DC

180

MHz

OUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
VOHVOL

High-level output voltage

Low-level output voltage

VDD = 3 V, IOH = –0.1 mA

2.9

VDD = 3 V, IOH = –8 mA

2.5

VDD = 3 V, IOH = –12 mA

2.2

V

VDD = 3 V, IOL = 0.1 mA

0.1

VDD = 3 V, IOL = 8 mA

0.5

VDD = 3 V, IOL = 12 mA

0.8V

OUTPUT PARAMETERS FOR VDD =2.5 V ± 0.2 V
VOH

High-level output voltage

VOL

Low-level output voltage

(1)
(2)

VDD = 2.3 V, IOH = –0.1 mA

2.2

VDD = 2.3 V, IOH = –8 mA

1.7V

VDD = 2.3 V, IOL = 0.1 mA

0.1

VDD = 2.3 V, IOL = 8 mA

0.5

V

All typical values are at respective nominal VDD. For switching characteristics, outputs are terminated to 50 Ω to VDD/2 (see Figure 1).
This is the formula for the power dissipation calculation (see and the Power Considerations section).
Ptot = Pstat + Pdyn + PCload [W]Pstat = VDD × IDD [W]Pdyn = CPD × VDD2 × ƒ [W]
PCload = Cload × VDD2 × ƒ × n [W]n = Number of switching output pins

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RS9112C,RS9113C,RS9114C
7.5 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP (1)MAXUNITOUTPUT PARAMETERS FOR VDD = 3.3 V ± 0.3 V
tPLH/ tPHL

Propagation delay

CLKIN toYn

0.82.0nstr/ tf

Rise and fall time

20%–80% (VOH - VOL)

0.30.8nstDIS

Output disable time

1G to Yn

6nstEN

Output enable time
Pulse skew ; tPLH(Yn) –tPHL(Yn) (1)Additive jitter rms(2)1G to Yn

6ns180

ps100

fstsk(p)tjitter

12 kHz to 20 MHz, fOUT = 250 MHz

OUTPUT PARAMETERS FOR VDD =2.5 V ± 0.2 V
tPLH/ tPHLPropagation delay

CLKIN to Yn

1

2.6

ns

tr/ tfRise and fall time

20%–80% (VOH - VOL)

0.3

1.2

nstDIS

Output disable time

1G to Yn

10nstEN

Output enable time
Pulse skew ; tPLH(Yn) –tPHL(Yn) (1)Additive jitter rms (2)1G to Yn

10

ns220

ps

350

fstsk(p)tjitter(1)(2)

12 kHz to 20 MHz, fOUT = 180 MHztsk(p) depends on output rise- and fall-time (tr/tf).The output duty-cycle can be calculated: odc = (tw(OUT) ± tsk(p))/tperiod; tw(OUT) is pulse-widthof output waveform and tperiod is 1/fOUT.
Parameter is specified by characterization. Not tested in production

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RS9112C,RS9113C,RS9114C
7.6 Parameter Measurement Information

Figure 1. Test Load Circuit

Figure 2. Application Load With 50-Ω Line Termination

Figure 3. Application Load With Series Line Termination

Figure 4. tDIS and tEN for Disable Low

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RS9112C,RS9113C,RS9114C

Figure 5. Pulse Skew tsk(p) and Propagation Delay tPLH/tPHL

Figure 6. Rise/Fall Times tr /tf

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RS9112C,RS9113C,RS9114C
8 Detailed Description
8.1 Overview
The RS911xC family of devices is a low-jitter and low-skew LVCMOS fan-out buffer solution. For best signal
integrity, it is important to match the characteristic impedance of the RS911xC 's output driver with that of thetransmission line. Figure 2 and Figure 3 show the proper configuration per configuration for both V DD = 3.3 V
and VDD = 2.5 V. RUNIC recommends placing the series resistor close to the driver to minimize signal reflection.

8.2 Functional Block DiagramFigure 7. RS911xC functional block diagram
Table 1. Output Logic Table
INPUTSOUTPUTS

CLKIN

1GYnXLLLHL

HHH

8.3 Feature Description
The outputs of the RS911xC can be disabled by driving the asynchronous output enable pin (1G) low. Unused
output can be left floating to reduce overall system component cost. All supply and ground pins must beconnected to VDD and GND, respectively.

8.4 Device Functional Modes
The RS911xC operates from supplies between 2.5 V and 3.3 V.

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RS9112C,RS9113C,RS9114C
9 Application and Implementation
9.1 Application Information
The RS911xC family is a low additive jitter LVCMOS buffer solution that can operate up to 250 MHz at and 180
MHz at VDD = 2.5 V. Low output skew as well as the ability for asynchronous output enable is featured tosimultaneously enable or disable buffered clock outputs as necessary in the application.

9.2 Typical Application

Figure 8. Example System Configuration

9.3 Design Requirements
The RS911xC shown in Figure 8 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator. TheCPU is configured to control the output state through 1G. The configuration example is driving three LVCMOS
receivers in a backplane application with the following properties:• The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near theRS911xC to closely match the characteristic impedance of the trace to minimize reflections.
• The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the RS911xC.
• The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage ismismatched.

9.4 Detailed Design Procedure
Refer to Figure 3 and the Electrical Characteristics table to determine the appropriate series resistance needed
for matching the output impedance of the RS911xC to that of the characteristic impedance of the transmission
line.
Unused outputs can be left floating. See the Power Supply Recommendations section for recommended filtering
techniques.

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RS9112C,RS9113C,RS9114C
10 Power Supply Recommendations
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase theadditive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
the jitter and phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guards the power supply systemagainst induced fluctuations. These bypass capacitors also provide instantaneous current surges as required bythe device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, theymust be placed very close to the power-supply terminals and laid out with short loops to minimize inductance.
RUNIC recommends adding as many high-frequency (for example, 0.1 µ F) bypass capacitors, as there are supply
terminals in the package. RUNIC recommends, but does not require, inserting a ferrite bead between the board
power supply and the chip power supply that isolates the high-frequency switching noises generated by theclock buffer; these beads prevent the switching noise from leaking into the board supply. It is imperative tochoose an appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board
supply and the chip supply, as well as to maintain a voltage at the supply terminals that is greater than theminimum voltage required for proper operation.
Figure 9 shows this recommended power supply decoupling method.

Figure 9. Power Supply Decoupling

10.1 Power Considerations
The following power consideration refers to the device-consumed power consumption only. The device power
consumption is the sum of static power and dynamic power. The dynamic power usage consists of twocomponents:• Power used by the device as it switches states.
• Power required to charge any output load.
The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs
in and Figure 1 can be used to obtain the power consumption of the device:
Pdev = Pstat + n (Pdyn + PCload)
Pstat = VDD × IDD Pdyn + PCload
where:VDD = Supply voltage ( 3.3Vor 2.5 V )IDD = Static device current (typical 3.5 mA for VDD = 3.3 V; typical 1.5 mA for VDD = 2.5 V)
n = Number of switching output pins
Example for device power consumption for RS9114C: four outputs are switching, f = 120 MHz, VDD = 3.3 V, andCload = 2 pF per output:
Pdev = Pstat + n (Pdyn + PCload) = 11.55 mW + 50 mW = 61.55 mW
Pstat = VDD × IDD = 3.5 mA × 3.3 V = 11.55 mWn (Pdyn + PCload) = 4 × 12.5 mW = 50 mW12 / 13

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RS9112C,RS9113C,RS9114C
11 PACKAGE OUTLINE DIMENSIONSTSSOP8 (3)
eb

5.6

E1 E

1.78
D

0.65

0.42

RECOMMENDED LAND PATTERN (Unit: mm)

A2
A1

HCA

θ

L

SymbolDimensions In Millimeters

Dimensions In Inches

MinMin

Max

A (1)

Max

1.200

0.047

A1

0.050

0.150

0.002

0.006

A2

0.800

1.050

0.031

0.041

b0.190

0.300

0.007

0.012

c0.090

0.200

0.004

0.008

D (1)

2.900

3.100

0.114

0.122

E (1)

4.300

4.500

0.169

0.177

E1

6.250

6.550

0.246

0.258

0.650(BSC) (2)

eL

0.500

Hθ

0.026(BSC) (2)
0.700

0.020

0.25(TYP)
1°

0.028
0.01(TYP)

7°

1°

7°

NOTE:
1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
2. BSC (Basic Spacing between Centers), "Basic" spacing is nominal.
3. This drawing is subject to change without notice.

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