AN90030

Paralleling of Nexperia cascode GaN FETs in half-bridge
topology
Rev. 3.0 — 22 March 2023

application note

Document information
Information

Content

Keywords

NX-HB7000EV, GaN FET, TO-247, half-bridge, converter, paralleling, circuit design, PCB layout

Abstract

This appplication note explains the recommendations for circuit design and PCB layout whenparalleling Nexperia TO-247 GaN FETs in a half-bridge configuration.

AN90030

Nexperia

Paralleling of Nexperia cascode GaN FETs in half-bridge topology

1. Introduction
GaN FETs are becoming increasingly important for modern power conversion systems, examples
being inverters, power supplies and on-board chargers. The fundamental building block for many
applications is the half-bridge as shown in Fig. 1 below.
Driver PCB

Power PCB

+HVDC

+HVDC

high voltage
buck input/
boost output

PULSE-GEN
CIRCUIT
HI/LO
GATE
DRIVER

logic-level inputs

high voltage
buck output/
boost input

4 x GAN041-650WSB
aaa-033976

Fig. 1.

Half-bridge with paralleled GaN FETs functional block diagram

To realise the power levels demanded by the growing number of high-power applications, designs
using multiple GaN FETs in parallel are becoming more widespread.
With both the high currents in conjunction with the fast-switching speeds that are possible whenutilising GaN FETs in these systems, these combinations of factors do present some challenges forthe designer that will be discussed here.
One of the main challenges is current sharing between GaN FETs and associated switchingstability. We will show how to parallel leaded TO-247 GaN FETs used for the high-side and low-sideof a half-bridge driving an inductive load effectively.
It is obviously very important for paralleled GaN FETs to share current equally to prevent any
individual device suffering from excessive power dissipation that could compromise reliability andlifetime. It is also very important that switching is stable without excessive oscillation which would inturn result in higher switching losses than are acceptable.

2. Half-bridge current sharing topology[1]

For the purposes of this application note two paralleled GAN041-650WSB GaN FETs in a sideby-side configuration for both the high-side and low-side have been selected for the half-bridge test
circuit, which provides the following design benefits:••Compact switching node
Optimised current flow path

In addition to this, a separate PCB is utilised for the Gate drivers, which provides the following
design benefits:•

Short and balanced gate drives

Symmetry is the key factor so that the effective impedance paths are matched as much as
possible.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

3. Gate drive design considerations
In this study we use a common gate driver for the paralleled GaN FETs. This means that thenormal requirement for short gate-drive loops is complicated by the need for matched switching
behaviour. Gate drive loops give the best performance when the Gate-Source loops are equalisedin terms of path length (effective impedance) for each device being paralleled.
The drivers should be physically as close to the gates as possible to limit the track lengths, which
provides the following benefits:••

Current shared equally by linear design
Gate track lengths equal (as highlighted by the red rectangles in Fig. 2).

aaa-034005

Fig. 2.

Gate driver PCB track lengths

Best design practice is for the driver to be placed on the same PCB as the GaN FETs so that theinductance between the Source pin and driver are reduced as much as practically possible.
However, where this is not feasible due to design, placement or packaging constraints, and aseparate driver board must be used, then the use of short wide tracks or ideally multiple signal
planes on both boards, in association with large gauge terminals soldered between the boards,
is advised. This will reduce the inductance between the GaN FET Source pin and driver as muchas practically possible. Use of non-soldered connectors, such as plugs and sockets, are notrecommended in the Gate-Source loop as these typically increase the inductance, leading to anincreased risk of oscillation.
Also, for best Gate signal integrity, it is recommended that the connection between the Source pin
and driver are to a “quiet” ground connection, where none of the main current is able to flow.

3.1. Gate driver IC considerations
Isolated driver ICs offer packaging benefits as transformer isolation is a standard requirement formost designers to use between the controller and the power electronics and driver.
The gate driver IC utilized for the half-bridge test circuit is from the Silicon Labs Si827x series,[2]

specifically the Si8271 .
Features which make these gate drivers an appropriate choice include:•••high dv/dt immunity of 200 kV/μs CMTI
fully isolated
high output source/sink current capability

Similar features are available in gate driver ICs from other manufacturers also.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

3.2. Gate Ferrite beads and resistors
Due to the extremely fast dv/dt that occurs during switching, this increases the possibilityof oscillation in the half-bridge test circuit, which can very quickly lead to device damage ordestruction. However, with very careful selection of the Gate ferrite bead and resistors for eachconnection to the GaN FETs, the possibility of oscillation can be minimised.
The GAN041-650WSB GaN FETs do not have an internal ferrite bead and as such allows
the designer much more flexibility in selecting the optimal component required. As specified[1]

in the Nexperia GAN041-650WSB data sheet , the recommended ferrite bead is the
BLM18AG221SN1D, supplied by Murata. This ferrite has a typical impedance of 220 Ω at 100 MHz
and has been found to be extremely effective in suppressing any gate circuit instability in the halfbridge test circuit.
Along with the ferrite bead, the value of the resistor(s) in the gate circuit also contributes
significantly to the switching stability. Nexperia recommends that initial stability tests are conductedwith a gate resistance of 15 Ω. However, the final value(s) chosen will depend on the driver used
and its respective current source/sink capabilities.
For the half-bridge test circuit, resistances of 15 Ω and 7.5 Ω are connected to the active high andlow outputs of the drivers respectively.
While individual ferrite beads should be used in series with each gate, a single gate resistor can beused at the driver output. Refer to the schematics Fig. 21 and Fig. 26 for further details.

4. DC bus snubbers and decoupling
DC bus snubbers must be connected between the high voltage and ground planes (very large
voltage overshoots are seen without appropriate suppression) and should be located as close as
possible to each GaN FET. Typically, these DC Bus snubbers would consist of a 10 Ω resistor inseries with 10 nF capacitor.
Also, decoupling capacitances of 10 nF and 100 nF value should be located as close as possible
to each GaN FET and be connected between the high voltage and ground planes. See Fig. 3 andFig. 4.
DC Bus snubbers

decoupling capacitors

aaa-033977

Fig. 3.

AN90030

application noteBus snubber RC networks and decoupling capacitors schematic

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033978

Fig. 4.

Bus snubber RC networks and decoupling capacitors PCB layout

4.1. Switching node snubber
Switching node snubbers are only recommended to achieve maximum stability at high switchingcurrents. These will increase the switching loss and are only recommended at high power levels
where the losses are a very small percentage of the total power.
Although provision has been made in the half-bridge test circuit for multiple snubbers between the
DC bus and switch node and between the Switch Node and Ground, none were required to be
populated to achieve switching stability and excellent switch node voltage overshoot control anddamping.

4.2. Thermal considerations
The RDSon of the cascode GaN HEMT has a positive temperature coefficient. The VGS(th) of
the GaN FET has a negative temperature coefficient which means that the device with thehigher junction temperature will turn on first and therefore be subjected to a higher share of thecurrent. However, the GaN FETs have been mounted so that even heat distribution is achieved,
which results in even current sharing between devices. So, when paralleling GaN FETs, it isvery important for them to be effectively heatsinked and implicitly very well connected thermally
together.

5. Layout optimisation for current Sharing
Testing has shown that current sharing can be improved by positioning the devices in line with thecurrent and load path to keep the distances between the inputs and outputs symmetrical.
The current path is much better with balanced copper flood planes. For balanced operation, alayout should aim to have the parallel devices in line with the load and power as shown in Fig. 5,
keeping the current loop as small as possible.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033979

Fig. 5.

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application note

PCB current paths

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

6. Captured waveforms from single-shot staircase test
In this section are shown the test results from performing a seven pulse, single-shot staircase
test at 100 kHz. The inductor is connected to the BUS voltage set at 400 V and the current flows
through the low-side GaN FETs and recirculates through the high-side GaN FETs. Each pulse hasa width of 1.9 µs, leading to a peak inductor current of 114 A.
See Fig. 6, the oscilloscope channel identifications are as follows:••••

C1 – low-side GaN FET Q2 gate signal
C2 – low-side GaN FET Q4 gate signal
C3 – inductor current
C4 – switch node voltage

aaa-033980

Fig. 6.

Single-Shot staircase test waveforms
Note : An air-cored non-overlapped inductor is used, avoiding saturation and keeping winding
parasitic capacitance low.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033981

Fig. 7.

Zoom of final pulse
Notice how closely matched the gate signals are, and that they are nicely damped at switch off - assuch there is no risk of sustained oscillation.
The impedance of the ferrite bead permits the ringing on the internal Source inductance to bevisible at the Gate pin. This is a natural consequence of the decoupling effect of the ferrite. If theGate potential were held rigidly, then instead of observable voltage oscillations, there would beunobservable current oscillations which would be coupled and amplified.
Fig. 8 shows the individual GaN FET currents measured in the same seven pulse, 100 kHz,
staircase test.
The oscilloscope channel identification are as follows:••••

AN90030

application note

C1 – low-side GaN FET Q2 gate signal
C2 – switch node voltage
C3 – low-side GaN FET Q2 device current
C4 – low-side GaN FET Q4 device current

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033982

Fig. 8.

Individual GaN FET currents
Note - the magenta and green traces are measured GaN FET currents, showing excellent current
sharing between devices.

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7. System performance running in BUCK mode
In this section are shown the captured oscilloscope traces and test results when the system isrunning in BUCK mode. The operating conditions are as follows:
•
•
•
•
•

Input voltage = 400 V
Output voltage = 225 V
Output power = 6.6 kW
Switching frequency = 100 kHz
Ambient temperature = 34 °C

In Fig. 9 the oscilloscope channel identification are as follows:••••

C1 – low-side GaN FET Q2 Gate signal
C2 – low-side GaN FET Q4 Gate signal
C3 – Inductor current
C4 – Switch Node voltage

aaa-033983

Fig. 9.

System running in BUCK mode

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology
Fig. 10 and Fig. 11 show zooms of the low-side GaN FETs during switch ON and switch OFF.

aaa-033984

Fig. 10. Zoom of Q2 and Q4 low-side GaN FETs - switch ON

aaa-033985

Fig. 11. Zoom of Q2 and Q4 low-side GaN FETs - switch OFF

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology
Note that during switching events any voltage oscillations on both the Gate and Switch Nodesignals have been very effectively damped.
Fig. 12 shows the high-side currents, the oscilloscope channel identification are as follows:••••

C1 – low-side GaN FET Q2 Gate signal
C2 – Switch Node voltage
C3 – high-side GaN FET Q1 device current
C4 – high-side GaN FET Q3 device current

aaa-033986

Fig. 12. System running in BUCK mode - GaN FET high-side currents

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology
Fig. 13 shows the low-side device currents, the oscilloscope channel identification are as follows:•••

C1 – low-side GaN FET Q2 Gate signal
C2 – Switch Node voltage
C3 – low-side GaN FET Q2 device current•

C4 – low-side GaN FET Q4 device current

aaa-033987

Fig. 13. System running in BUCK mode - GaN FET low-side currents

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

7.1. Efficiency sweep and device temperatures
Fig. 14 shows the measured efficiency of the circuit using 2 parallel GAN041-650WSB GaN FETs
while operating in BUCK mode.
aaa-033988

100
Efficiency
(%)
99

98

97

96

0

2000

4000

6000
8000
output power (W)Parallel GAN041-650WSB GaN FETs
Fig. 14. Efficiency as a function of output power, BUCK mode
Device temperatures were measured using thermocouples bonded to the front face of the mounting
bases and are all very close to each other:••••high-side GaN FET Q1 = 69.6 °C
high-side GaN FET Q3 = 74.9 °C
low-side GaN FET Q2 = 72.3 °C
low-side GaN FET Q4 = 69.1 °C

These results confirm excellent current sharing and thermal connection of all devices.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

8. System performance running in BOOST mode
In this section are shown the captured oscilloscope traces and test results when the system isrunning in BOOST mode. The operating conditions are as follows:
•
•
•
•
•

Input voltage = 225 V
Output voltage = 400 V
Output power = 6.6 kW
Switching frequency = 100 kHz
Ambient temperature = 32 °C

In Fig. 15 the oscilloscope channel identification are as follows:••••

C1 – low-side GaN FET Q2 Gate signal
C2 – low-side GaN FET Q4 Gate signal
C3 – Inductor current
C4 – Switch Node voltage

aaa-033989

Fig. 15. System running in BOOST mode

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology
Fig. 16 and Fig. 17 show zooms of the low-side GaN FETs during switch ON and switch OFF.

aaa-033990

Fig. 16. Zoom of Q2 and Q4 low-side GaN FETs - switch ON

aaa-0339915

Fig. 17. Zoom of Q2 and Q4 low-side GaN FETs - switch OFF

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology
Note that during switching events any voltage oscillations on both the Gate and Switch Nodesignals have been very effectively damped.
Fig. 18 shows the high-side currents, the oscilloscope channel identification are as follows:••••

C1 – low-side GaN FET Q2 Gate signal
C2 – Switch Node voltage
C3 – high-side GaN FET Q1 device current
C4 – high-side GaN FET Q3 device current

aaa-033992

Fig. 18. System running in BOOST mode - GaN FET high-side currents
Fig. 19 show the low-side device currents, the oscilloscope channel identification are as follows:••••

AN90030

application note

C1 – low-side GaN FET Q2 Gate signal
C2 – Switch Node voltage
C3 – low-side GaN FET Q2 device current
C4 – low-side GaN FET Q4 device current

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aaa-033993

Fig. 19. System running in BOOST mode - GaN FET low-side currents

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

8.1. Efficiency sweep and device temperatures
Fig. 20 shows the measured efficiency of the circuit using 2 parallel GAN041-650WSB GaN FETs
while operating in BOOST mode.
aaa-033994

100
Efficiency
(%)
99

98

97

96

0

2000

4000

6000
8000
output power (W)Parallel GAN041-650WSB GaN FETs
Fig. 20. Efficiency as a function of output power, BOOST mode
Device temperatures were measured using thermocouples bonded to the front face of the mounting
bases and are all very close to each other:••••high-side GaN FET Q1 = 60.3 °C
high-side GaN FET Q3 = 67.2 °C
low-side GaN FET Q2 = 78.0 °C
low-side GaN FET Q4 = 71.0 °C

These results confirm excellent current sharing and thermal connection of all devices.

9. Probing considerations[3]

Nexperia application note AN90004 , “Probing considerations for fast switching applications”
should be followed to ensure accurate measurement of any switching circuits.
Additionally, the low-side ground spring should either be soldered directly to the Source pin on the
package or alternatively to a “quiet” ground connection, where none of the main current is able toflow.

10. Design Details
The half-bridge converter circuit detailed in this application note has been implemented on two 4layer PCBs with 2 oz copper for the outer layers and 1.5 oz copper for the inner layers.
The circuit schematic, PCB layout and Bill of Material for the two PCBs are shown in the next
sections.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

10.1. Power board schematic

aaa-033995

Fig. 21. Power board schematic
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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

10.2. Power board PCB layout, planes and tracking

aaa-033996

Fig. 22. Power board - top layer
Note how the Drain connections identified by the blue rectangles have been made symmetrically to
Switch Node and HV, the snubbers identified by the red rectangles are placed directly on the Drain
pins and the use of stitch vias between planes.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033997

Fig. 23. Power board - inner layer 1 - Switch node and Ground plane
Note the extremely compact Switch Node.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033998

Fig. 24. Power board - inner layer 2 - Switch node, HV and Ground planes

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-033999

Fig. 25. Power board - bottom layer

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

10.3. Power board Bill of Materials
Table 1. Power board Bill of Material
Part
Value
Voltage

Package

Description

Supplier

Supplier P/N

C1

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C2

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C3

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C4

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C5

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C6

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C7

100n

1kV

C1812

Capacitor, Ceramic

Farnell

2085218

C8

100n

1kV

C2225

Capacitor, Ceramic

Farnell

1838767
or 2896821

C9

2.2uF

630V

PHE450_2U

Capacitor, PP Film

RS

105-1057

C10

100n

1kV

C1812

Capacitor, Ceramic

Farnell

2085218

C11

-

-

C1210

Capacitor, Ceramic

-

-

C12

-

-

C1210

Capacitor, Ceramic

-

-

C13

-

-

C1210

Capacitor, Ceramic

-

-

C14

-

-

C1210

Capacitor, Ceramic

-

-

C15

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C16

100n

1kV

C2225

Capacitor, Ceramic

Farnell

1838767
or 2896821

C17

100n

1kV

C2225

Capacitor, Ceramic

Farnell

1838767
or 2896821

C18

2.2uF

630V

PHE450_2U

Capacitor, PP Film

RS

105-1057

C19

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C24

-

-

C1210

Capacitor, Ceramic

-

-

C25

-

-

C1210

Capacitor, Ceramic

-

-

C26

2.2uF

630V

PHE450_2U

Capacitor, PP Film

RS

105-1057

C27

2.2uF

630V

PHE450_2U

Capacitor, PP Film

RS

105-1057

C28

2.2uF

630V

PHE450_2U

Capacitor, PP Film

RS

105-1057

C29

2.2uF

630V

PHE450_2U

Capacitor, PP Film

RS

105-1057

C30

100n

1kV

C2225

Capacitor, Ceramic

Farnell

1838767
or 2896821

C31

100n

1kV

C2225

Capacitor, Ceramic

Farnell

1838767
or 2896821

C32

100n

1kV

C2225

Capacitor, Ceramic

Farnell

1838767
or 2896821

C33

10n

630V

C1206

Capacitor, Ceramic

Farnell

1759518

C34

-

-

C1210

Capacitor, Ceramic

-

-

C35

-

-

-

C1210

Capacitor, Ceramic-

HS1

COOL_INNO_1

Heatsink

Cool
Innovations

J2

KEYSTONE_7691

Screw Terminal

Mouser534-7691-SEMS

J3

KEYSTONE_7691

Screw Terminal

Mouser534-7691-SEMS

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J5

KEYSTONE_7691

Screw Terminal

Mouser534-7691-SEMS

J7

KEYSTONE_7691

Screw Terminal

Mouser534-7691-SEMS

L1

220uH

Q1

GAN041-650WSB

650V

TO-247

GaN FET

Nexperia

GAN041-650WSB

Q2

GAN041-650WSB

650V

TO-247

GaN FET

Nexperia

GAN041-650WSB

Q3

GAN041-650WSB

650V

TO-247

GaN FET

Nexperia

GAN041-650WSB

Q4

GAN041-650WSB

650V

TO-247

GaN FET

Nexperia

GAN041-650WSB

R1

-

-

R1206

Resistor

-

-

R2

-

-

R1206

Resistor

-

-

R3

10MEG

R1206

Resistor

Farnell

1469973

R4

-

-

R1206

Resistor

-

-

R5

-

-

R1206

Resistor

-

-

R6

10

-

R1206

Resistor

Farnell

1738986

R7

10

-

R1206

Resistor

Farnell

1738986

R11

220

0603

FerriteFarnell

1515674

R12

220

0603

FerriteFarnell

1515674

R13

-

-

R1206

Resistor

-

-

R14

-

-

R1206

Resistor

-

-

R15

-

-

R1206

Resistor

-

-

R16

-

-

R1206

Resistor

-

-

R17

10

-

R1206

Resistor

Farnell

1738986

R18

-

-

R1206

Resistor

-

-

R19

-

-

R1206

Resistor

-

-

R33

220

0603

FerriteFarnell

1515674

R34

220

0603

FerriteFarnell

1515674

Alumina insulator

Mouser532-4169G

Alumina insulator

Mouser532-4169G

Alumina insulator

Mouser532-4169G

Alumina insulator

Mouser532-4169G

Cooling Fan

RS922-6248

Standoff

Farnell

1733422

Standoff

Farnell

1733422

Standoff

Farnell

1733422

Standoff

Farnell

1733422

Screw M3 x 6mm

RS560-754

Screw M3 x 6mm

RS560-754

Screw M3 x 6mm

RS560-754

Screw M3 x 6mm

RS560-754PCB

PCBWayNX-HB7000EV
Parallel TO-247
Current
Board Rev1.1

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

10.4. Driver board schematics

aaa-034000

Fig. 26. Driver board schematic

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10.5. Driver board PCB layout, planes and tracking
aaa-034001

Fig. 27. Driver board - top layer
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Paralleling of Nexperia cascode GaN FETs in half-bridge topology
Note the top layer, (Fig. 27), uses symmetrical GaN FET Gate connections for one high-side andone low-side identified by the blue rectangles – the Gate connections for the associated paralleled
GaN FET are routed on the Bottom Layer.

aaa-034002

Fig. 28. Driver board - inner layer 1 – Switch Node, 12 V, Analogue Ground and Power Ground Planes

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

aaa-034003

Fig. 29. Driver board - inner layer 2 – Switch Node, Analogue Ground and Power Ground Planes

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aaa-034004

Fig. 30. Driver board - bottom layer

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10.6. Driver board Bill of Materials
Table 2. Driver board Bill of Material
Part
Value
Voltage

Package

Description

Supplier

Supplier P/N

C1

22uF

35V

C1206

Capacitor, Ceramic

Farnell

2525173

C2

1uF

50V

C0805

Capacitor, Ceramic

Farnell

2094043

C3

2.2uF

50V

C0805

Capacitor, Ceramic

Farnell

2346931

C4

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C10

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C11

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C12

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C13

10uF

35V

C0805

Capacitor, Ceramic

Farnell

2547034

C14

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C15

10uF

35V

C0805

Capacitor, Ceramic

Farnell

2547034

C19

100pF

100V

C0603

Capacitor,
Ceramic C0G

Farnell

1740605

C20

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C21

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C22

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C23

220pF

50V

C0603

Capacitor,
Ceramic C0G

Farnell

498579

C37

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

C38

100nF

100V

C0603

Capacitor, Ceramic

Farnell

2749806

D1

ES1J

600V

DO-214AC

Diode

Farnell

3519291

D2

BAT54

30V

SOT23

Diode, Schottky

Nexperia

BAT54,215

D3

BAT54

30V

SOT23

Diode, Schottky

Nexperia

BAT54,215

D4

LED

-

D0805

LED, Green

Farnell

2610419J1

22-23-2021

2.54mm2-pin header

Farnell

1462926

J4

BU-SMA-G-

BU-SMA-G

Female SMA
Connector

Farnell

2112448

J6

BU-SMA-G-

BU-SMA-G

Female SMA
Connector

Farnell

2112448JP1--

2.54mm3-pin header

Farnell

1248150JP2--2.54mm3-pin header

Farnell

1248150

R1

4.99k

-

R1206

Resistor

Farnell

1470015

R2

499k

-

R1206

Resistor

Farnell

1470019

R3

-

-

R0805

Resistor

-

-

R4

10R

-

R0805

Resistor

Farnell

2303326

R5

51R

-

R1206

Resistor

Farnell

1470021

R6

51R

-

R1206

Resistor

Farnell

1470021

R7

7R5

-

R0805

Resistor

Farnell

3235185

R8

2k

-

R0603

Resistor

Farnell

2059343

R9

0R

-

R1206

Resistor

Farnell

1469963

R10

3k3

-

R0603

Resistor

Farnell

2303173

R11

-

-

R0805

Resistor

-

-

R12

15R

-

R0805

Resistor

Farnell

1750730

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R13

-

-

R0805

Resistor

-

-

R14

7R5

-

R0805

Resistor

Farnell

3235185

R15

0R

-

R0805

Resistor

Farnell

9233750

R16

0R

-

R0805

Resistor

Farnell

9233750

R21

15R

-

R0805

Resistor

Farnell

1750730

R22

-

-

R0805

Resistor

-

-

R23

1k

-

R0805

Resistor

Farnell

1469847

U1

LT3082-

SOT223-3

Linear Regulator

Mouser

584-LT3
082EST#PBF

U2

Si8271BB-IS

-

SOIC8

HI/LO ISO Gate Driver

Farnell

2524443

U3A1

74LVC1G17GW-TSSOP-5

Schmitt Trigger Buffer

Nexperia

74LVC1G17GW

U4B1

74HCT1G86GW-TSSOP-5

2-input X-OR gate

Nexperia

74HCT1G86GW

U5B1

74HCT1G86GW-TSSOP-5

2-input X-OR gate

Nexperia

74HCT1G86GW

U8Si8271BB-IS

-

SOIC8

HI/LO ISO Gate Driver

Farnell

2524443

Shorting Link

RS

251-8503

Shorting Link

RS

251-8503

PCB

PCBWayNX-HB7000EV
Parallel TO-247
Driver Board
Rev1.1

11. Summary
By using careful layout, short and impedance balanced gate drives, correctly placed DC Bus
snubbers and decoupling, it is possible to achieve excellent current sharing in paralleled GaN FETs
driving an inductive load. This has been effectively shown using leaded parts on a 4-layer FR4
PCB.

12. References
1. GAN041-650WSB data sheet.
2. Si8271 data sheet.
3. Nexperia application note AN90004.

13. Revision history
Table 3. Revision history
Revision
Date
numberDescription

3.0

2023-03-22

Title changed from “Paralleling of Nexperia GaN FETs in half-bridge topology” to “Parallelingof Nexperia cascode GaN FETs in half-bridge topology".
Typo repaired in Section 10.

2.0

2021-10-19

Minor changes to Section 2 and Section 4.

1.0

2021-09-21

Initial version.

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14. Legal information
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Draft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included hereinand shall have no liability for the consequences of use of such information.

Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for theconsequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outsideof Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not suchdamages are based on tort (including negligence), warranty, breach ofcontract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with theTerms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-criticalsystems or equipment, nor in applications where failure or malfunctionof an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products insuch equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability forany assistance with applications or customer product design. It is customer’ssole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards tominimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for thecustomer’s applications and products using Nexperia products in order toavoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a priorauthorization from competent authorities.
Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.

Trademarks
Notice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

List of Tables
Table 1. Power board Bill of Material................................. 25
Table 2. Driver board Bill of Material................................. 32
Table 3. Revision history....................................................33

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

List of Figures
Fig. 1. Half-bridge with paralleled GaN FETs functional
block diagram.......................................................................2
Fig. 2. Gate driver PCB track lengths.................................. 3
Fig. 3. Bus snubber RC networks and decoupling
capacitors schematic............................................................4
Fig. 4. Bus snubber RC networks and decoupling
capacitors PCB layout..........................................................5
Fig. 5. PCB current paths.................................................... 6
Fig. 6. Single-Shot staircase test waveforms....................... 7
Fig. 7. Zoom of final pulse................................................... 8
Fig. 8. Individual GaN FET currents.................................... 9
Fig. 9. System running in BUCK mode.............................. 10
Fig. 10. Zoom of Q2 and Q4 low-side GaN FETs switch ON...........................................................................11
Fig. 11. Zoom of Q2 and Q4 low-side GaN FETs switch OFF......................................................................... 11
Fig. 12. System running in BUCK mode - GaN FET
high-side currents...............................................................12
Fig. 13. System running in BUCK mode - GaN FET
low-side currents................................................................ 13
Fig. 14. Efficiency as a function of output power,
BUCK mode....................................................................... 14
Fig. 15. System running in BOOST mode......................... 15
Fig. 16. Zoom of Q2 and Q4 low-side GaN FETs switch ON...........................................................................16
Fig. 17. Zoom of Q2 and Q4 low-side GaN FETs switch OFF......................................................................... 16
Fig. 18. System running in BOOST mode - GaN FET
high-side currents...............................................................17
Fig. 19. System running in BOOST mode - GaN FET
low-side currents................................................................ 18
Fig. 20. Efficiency as a function of output power,
BOOST mode.....................................................................19
Fig. 21. Power board schematic........................................ 20
Fig. 22. Power board - top layer........................................ 21
Fig. 23. Power board - inner layer 1 - Switch node and
Ground plane..................................................................... 22
Fig. 24. Power board - inner layer 2 - Switch node, HV
and Ground planes............................................................ 23
Fig. 25. Power board - bottom layer.................................. 24
Fig. 26. Driver board schematic......................................... 27
Fig. 27. Driver board - top layer.........................................28
Fig. 28. Driver board - inner layer 1 – Switch Node, 12
V, Analogue Ground and Power Ground Planes................29
Fig. 29. Driver board - inner layer 2 – Switch Node,Analogue Ground and Power Ground Planes....................30
Fig. 30. Driver board - bottom layer...................................31

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Paralleling of Nexperia cascode GaN FETs in half-bridge topology

Contents
1. Introduction................................................................... 2
2. Half-bridge current sharing topology......................... 2
3. Gate drive design considerations............................... 3
3.1. Gate driver IC considerations...................................... 3
3.2. Gate Ferrite beads and resistors................................. 4
4. DC bus snubbers and decoupling.............................. 4
4.1. Switching node snubber.............................................. 5
4.2. Thermal considerations............................................... 5
5. Layout optimisation for current Sharing.................... 5
6. Captured waveforms from single-shot staircase test7
7. System performance running in BUCK mode.......... 10
7.1. Efficiency sweep and device temperatures................14
8. System performance running in BOOST mode........15
8.1. Efficiency sweep and device temperatures................19
9. Probing considerations..............................................19
10. Design Details...........................................................19
10.1. Power board schematic........................................... 20
10.2. Power board PCB layout, planes and tracking.........21
10.3. Power board Bill of Materials...................................25
10.4. Driver board schematics..........................................27
10.5. Driver board PCB layout, planes and tracking......... 28
10.6. Driver board Bill of Materials................................... 32
11. Summary....................................................................33
12. References................................................................ 33
13. Revision history........................................................33
14. Legal information......................................................34© Nexperia B.V. 2023. All rights reserved

For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 22 March 2023

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